.gitlab-ci.yml

image: registry.gitlab.com/canfd/server-tools/ghdl
before_script:
    - "export PATH=/opt/ghdl/bin:$PATH"
    - export LC_ALL=C.UTF-8
    - export LANG=C.UTF-8
    - export PYTHONUNBUFFERED=1
    - export CTU_TB_TOP_TARGET="tb_ctu_can_fd_rtl_vunit"


stages:
    - precheck
    #- test_driver
    - build
    - test_rtl
    - test_gates
    - coverage
    - deploy

check_component:
    stage: precheck
    script:
        - scripts/gen_vivado_component.py
        - cd scripts && ./update_reg_map
        - git diff --exit-code || (echo "Vivado component file or register map products are not up-to-date. Either run scripts/gen_vivado_component.py and scripts/update_reg_map or download the files from this job's artifacts."; exit 1)
    artifacts:
        expire_in: 1 week
        paths:
            - src/component.xml
            - doc/core/registerMap.lyx
            - driver/ctucanfd_regs.h
            - driver/ctucanfd_frame.h
            - src/lib/can_fd_register_map.vhd

###############################################################################
# Build stage
###############################################################################

build_ip_and_tests:
    stage: build
    tags:
        - simulation
    script:
        - cd test
        - make elaborate
    only: &only
        - master     # Run on all changes to master branch
        - tags       # Run on all tags
        - triggers   # Run by trigger (on merge request)
        - web        # Run by manual request from web UI


build_compliance_lib:
    stage: build
    tags:
        - simulation
    script:
        - cd test/main_tb/iso-16845-compliance-tests/
        - source ./build.sh
    artifacts:
        paths:
            - test/main_tb/iso-16845-compliance-tests/build/Debug/src/cosimulation/libGHDL_VPI_COSIM_LIB.so
            - test/main_tb/iso-16845-compliance-tests/build/Debug/src/cosimulation/libVCS_VHPI_COSIM_LIB.so
            - test/main_tb/iso-16845-compliance-tests/build/Release/src/cosimulation/libGHDL_VPI_COSIM_LIB.so
            - test/main_tb/iso-16845-compliance-tests/build/Release/src/cosimulation/libVCS_VHPI_COSIM_LIB.so
    only: *only


build_driver:
    stage: build
    tags:
        - simulation
    only: *only
    script:
        - cd driver
        - "make -j`nproc`"

build_doc:
    stage: build
    tags:
        - simulation
    only: *only
    image: registry.gitlab.com/canfd/server-tools/lyx
    script:
        - export LC_ALL=en_US.UTF-8
        - export LANG=en_US.UTF-8
        - make -C doc/core
        - make -C doc/driver
    artifacts:
        paths:
            - doc/core/Progdokum.pdf
            - doc/core/ctu_can_fd_architecture.pdf
            - doc/core/tb_architecture.pdf
            - doc/driver/build

build_linux_driver:
    stage: build
    tags:
        - simulation
    only: *only
    image: registry.gitlab.com/canfd/server-tools/ctucanfd_drvtest
    script:
        - cd driver/linux
        - "make -j`nproc` KDIR=/linux/build CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm"
        - "make checkpatch KDIR=/linux/build CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm"
    artifacts:
        paths:
            - driver/linux/ctucanfd.ko

run_synthesis:
    stage: build
    tags:
        - synthesis
    only: *only
    tags:
        - vps
    script:
        - source /opt/xilinx/vivado-2018.2/settings.sh
        - cd synthesis/Vivado/ci_benchmark
        - echo "Running minimal configuration..."
        - vivado -mode tcl -source vivado_benchmark_minimal.tcl
        - echo "Running typical configuration..."
        - vivado -mode tcl -source vivado_benchmark_typical.tcl
        - echo "Running maximal configuration..."
        - vivado -mode tcl -source vivado_benchmark_maximal.tcl

        # Remove reference to UNISIM library, all cell models are included in netlist!
        - sed -i 's\library UNISIM;\\g' maximal_design_config/can_top_level.vhd
        - sed -i 's\library UNISIM;\\g' typical_design_config/can_top_level.vhd
        - sed -i 's\library UNISIM;\\g' minimal_design_config/can_top_level.vhd
    artifacts:
        paths:
            - synthesis/Vivado/ci_benchmark/*_design_config
        expire_in: 12 hrs


###############################################################################
# Run emulator tests (on ZynQ MZ_APO board)
###############################################################################

# Disable for now. Multi-project pipelines are available only in Premium Gitlab
# Edition!

#run_emulator_tests:
#    stage: test_driver
#    only:
#        - master
#
    # Trigger pipeline in MZ_APO Zynq top repo. This will:
    #   1. Update sub-modules (CTU CAN FDs latest master is taken in Zynq build).
    #   2. Build Vivado design with CTU CAN FD, SJA1000, Zlogan etc...
    #   3. Build CTU CAN FD driver (from latest CTU CAN FD master)
    #   3. Run test on MZ_APO board which:
    #       1. Loads driver
    #       2. Sends frames over SocketCAN between CTU CAN FD and SJA100 in various
    #          combinations. This is sort-of driver sanity check, not its full
    #          verification!
    #trigger:
    #    project: canbus/zynq/zynq-can-sja1000-top
    #    strategy: depend


###############################################################################
# Test RTL stage (fast + nightly)
###############################################################################
test_fast_asic:
    stage: test_rtl
    tags:
        - simulation
    only: *only
    script:
        - cd test
        - make tb_rtl_test_fast_asic
        - make tb_rtl_test_fast_asic_logs
    artifacts:
        when: always
        paths:
            - test/tb_rtl_test_fast_asic.xml
            - test/tb_rtl_test_fast_asic_summary
            - test/tb_rtl_test_fast_asic.sim_time
        reports:
            junit: test/tb_rtl_test_fast_asic.xml

test_fast_fpga:
    stage: test_rtl
    tags:
        - simulation
    only: *only
    script:
        - cd test
        - make tb_rtl_test_fast_fpga
        - make tb_rtl_test_fast_fpga_logs
    artifacts:
        when: always
        paths:
            - test/tb_rtl_test_fast_fpga.xml
            - test/tb_rtl_test_fast_fpga_summary
            - test/tb_rtl_test_fast_fpga.sim_time
        reports:
            junit: test/tb_rtl_test_fast_fpga.xml

test_nightly:
    stage: test_rtl
    tags:
        - simulation
    only:
        - master
    script:
        - cd test
        - make tb_rtl_test_nightly
        - make tb_rtl_test_nightly_logs
    artifacts:
        when: always
        paths:
            - test/tb_rtl_test_nightly.xml
            - test/tb_rtl_test_nightly_summary
            - test/tb_rtl_test_nightly.sim_time
            - test/vunit_out/functional_coverage
        reports:
            junit: test/tb_rtl_test_nightly.xml

    # Nightly tests might fail due to randomization. It is not preffered to
    # kill whole follow-up coverage processing due to this failure!
    # OTOH, fast pipeline can't fail because it must pass before merge!
    allow_failure: true


###############################################################################
# Test RTL stage (Compliance test runs)
###############################################################################
test_compliance_short:
    stage: test_rtl
    tags:
        - simulation
    dependencies: [build_compliance_lib]
    only: *only
    script:
        - cd test
        - make tb_rtl_test_compliance_short
        - make tb_rtl_test_compliance_short_logs
    artifacts:
        when: always
        paths:
            - test/tb_rtl_test_compliance_short.xml
            - test/tb_rtl_test_compliance_short_summary
            - test/tb_rtl_test_compliance_short.sim_time
        reports:
            junit: test/tb_rtl_test_compliance_short.xml

    # For now not all compliance tests are debugged, allow failure...
    allow_failure: true

test_compliance_full_typ:
    stage: test_rtl
    tags:
        - simulation
    dependencies: [build_compliance_lib]
    only:
        - master
    script:
        - cd test
        - make tb_rtl_test_compliance_full_typ
        - make tb_rtl_test_compliance_full_typ_logs
    artifacts:
        when: always
        paths:
            - test/tb_rtl_test_compliance_full_typ.xml
            - test/tb_rtl_test_compliance_full_typ_summary
            - test/tb_rtl_test_compliance_full_typ.sim_time
            - test/vunit_out/functional_coverage
        reports:
            junit: test/tb_rtl_test_compliance_full_typ.xml

    # For now not all compliance tests are debugged, allow failure...
    allow_failure: true

test_compliance_full_max:
    stage: test_rtl
    tags:
        - simulation
    dependencies: [build_compliance_lib]
    only:
        - master
    script:
        - cd test
        - make tb_rtl_test_compliance_full_max
        - make tb_rtl_test_compliance_full_max_logs
    artifacts:
        when: always
        paths:
            - test/tb_rtl_test_compliance_full_max.xml
            - test/tb_rtl_test_compliance_full_max_summary
            - test/tb_rtl_test_compliance_full_max.sim_time
            - test/vunit_out/functional_coverage
        reports:
            junit: test/tb_rtl_test_compliance_full_max.xml

    # For now not all compliance tests are debugged, allow failure...
    allow_failure: true


# MIN run is not feasible with GHDL. Min run with VCS on fast machine takes 6-8
# hours -> TODO: Add min run once we flip to NVC.

###############################################################################
# Test gates (Gate level simulation on post synthesis netlist)
###############################################################################
#test_gates_simple:
#    stage: test_gates
#    tags:
#        - simulation
#    dependencies: [run_synthesis]
#    timeout: 6h
#    only:
#        - master
#    script:
#        - cd test
#        - make tb_gate_xilinx_test_simple
#        - make tb_gate_xilinx_test_simple_logs
#    artifacts:
#        when: always
#        paths:
#            - test/tb_gate_xilinx_test_simple.xml
#            - test/tb_gate_xilinx_test_simple_summary
#            - test/tb_gate_xilinx_test_simple.sim_time
#        reports:
#            junit: test/tb_gate_xilinx_test_simple.xml
#
#    # Some gates might fail, TODO: Debug
#    allow_failure: true

test_gates_compliance:
    stage: test_gates
    tags:
        - simulation
    dependencies: [run_synthesis, build_compliance_lib]
    timeout: 6h
    only:
        - master
    script:
        - cd test
        - make tb_gate_xilinx_test_compliance
        - make tb_gate_xilinx_test_compliance_logs
    artifacts:
        when: always
        paths:
            - test/tb_gate_xilinx_test_compliance.xml
            - test/tb_gate_xilinx_test_compliance_summary
            - test/tb_gate_xilinx_test_compliance.sim_time
        reports:
            junit: test/tb_gate_xilinx_test_compliance.xml

    # TODO: Still some compliance tests are not yet fully debugged!
    allow_failure: true



###############################################################################
# Results processing
###############################################################################

process_coverage:
    stage: coverage
    tags:
        - simulation
    dependencies: [test_compliance_full_typ, test_nightly]
    only:
        - master
    script:
        # Process functional coverage
        - cd test
        - make functional_coverage

        # Generate VRM
        - cd ../scripts
        - chmod +x gen_vrm
        - ./gen_vrm

    coverage: "/lines......: ([^%]+%)/"
    artifacts:
        when: always
        paths:
            - test/vunit_out/functional_coverage/functional_coverage_report.html
            - test/vunit_out/functional_coverage/html
            - scripts/VRM.html

pages:
    stage: deploy
    when: always
    script:
        - echo "Creating delivery package..."

        # Create directory structure for release
        - mkdir -p public
        - mkdir -p public/rtl
        - mkdir -p public/tb
        - mkdir -p public/doc
        - mkdir -p public/doc/linux_driver
        - mkdir -p public/regression_results
        - mkdir -p public/synthesis
        - mkdir -p public/vivado_component

        # Copy RTL
        - cp src/*.vhd public/rtl/
        - cp src/**/*.vhd public/rtl/
        - cp src/**/**/*.vhd public/rtl/
        - cp src/slf_*.yml public/

        # Copy TB
        - cp test/main_tb/*.vhd public/tb/
        - cp test/main_tb/**/*.vhd public/tb/
        - cp test/main_tb/**/**/*.vhd public/tb/
        - cp test/slf_*.yml public/

        # Copy test list files
        - cp test/tlf_* public/

        # Compliance test library
        - cp test/main_tb/iso-16845-compliance-tests/build/Release/src/cosimulation/libGHDL_VPI_COSIM_LIB.so public/
        - cp test/main_tb/iso-16845-compliance-tests/build/Release/src/cosimulation/libVCS_VHPI_COSIM_LIB.so public/

        # Copy regression results and code coverage

        # DO NOT pack the complete regression results they include all log files and that overflows pages artifacts!
        #- cp test/*.xml public/regression_results/ || true
        - cp test/*_summary public/regression_results/ || true

        # Measure total simulation time
        - cat test/*.sim_time | paste -sd+ | bc > total.sim_time
        - echo "Total simulation time is `cat total.sim_time` fs."

        # Copy documentation
        - mv doc/core/Progdokum.pdf public/doc/Datasheet.pdf || true
        - cp doc/core/ctu_can_fd_architecture.pdf public/doc/System_Architecture.pdf || true
        - cp doc/core/tb_architecture.pdf public/doc/Testbench.pdf || true
        - cp -R doc/driver/build public/doc/linux_driver || true

        # Copy functional coverage HTML reports
        - mkdir public/regression_results/functional_coverage
        - cp test/vunit_out/functional_coverage/*.html public/regression_results/functional_coverage || true
        - cp -R test/vunit_out/functional_coverage/html public/regression_results/functional_coverage || true

        # Copy synthesis results + constraints
        - cp -R synthesis/Vivado/ci_benchmark/*_design_config public/synthesis
        - cp synthesis/Constraints/ctu_can_fd.sdc public/synthesis

        # Copy Vivado component
        - cp src/component.xml public/vivado_component

        # VRM result
        - cp scripts/VRM.html public/regression_results/ || true

        # Check size, compress, check again
        - echo "Size of artifacts:"
        - du -skh public/*

    only:
        - master
    artifacts:
        paths:
            - public

variables:
    GIT_SUBMODULE_STRATEGY: recursive