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papilio_pro.ucf
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# UCF file for the Papilio Pro board
# Generated by pin_converter, written by Kevin Lindsey
# https://github.com/thelonious/papilio_pins/tree/development/pin_converter
# Main board wing pin [] to FPGA pin Pxx map
# -------C------- -------B------- -------A-------
# [GND] [C00] P114 [GND] [B00] P99 P100 [A15]
# [2V5] [C01] P115 [2V5] [B01] P97 P98 [A14]
# [3V3] [C02] P116 [3V3] [B02] P92 P93 [A13]
# [5V0] [C03] P117 [5V0] [B03] P87 P88 [A12]
# [C04] P118 [B04] P84 P85 [A11] [5V0]
# [C05] P119 [B05] P82 P83 [A10] [3V3]
# [C06] P120 [B06] P80 P81 [A09] [2V5]
# [C07] P121 [B07] P78 P79 [A08] [GND]
# [GND] [C08] P123 [GND] [B08] P74 P75 [A07]
# [2V5] [C09] P124 [2V5] [B09] P95 P67 [A06]
# [3V3] [C10] P126 [3V3] [B10] P62 P66 [A05]
# [5V0] [C11] P127 [5V0] [B11] P59 P61 [A04]
# [C12] P131 [B12] P57 P58 [A03] [5V0]
# [C13] P132 [B13] P55 P56 [A02] [3V3]
# [C14] P133 [B14] P50 P51 [A01] [2V5]
# [C15] P134 [B15] P47 P48 [A00] [GND]
## Prohibit the automatic placement of pins that are connected to VCC or GND for configuration.
CONFIG PROHIBIT=P144;
CONFIG PROHIBIT=P69;
CONFIG PROHIBIT=P60;
NET CLK LOC="P94" | IOSTANDARD=LVTTL | PERIOD=31.25ns; # CLK
NET TXD LOC="P105" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # TX
NET RXD LOC="P101" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # RX
NET WING_A(0) LOC="P48" | IOSTANDARD=LVTTL; # A0
NET WING_A(1) LOC="P51" | IOSTANDARD=LVTTL; # A1
NET WING_A(2) LOC="P56" | IOSTANDARD=LVTTL; # A2
NET WING_A(3) LOC="P58" | IOSTANDARD=LVTTL; # A3
NET WING_A(4) LOC="P61" | IOSTANDARD=LVTTL; # A4
NET WING_A(5) LOC="P66" | IOSTANDARD=LVTTL; # A5
NET WING_A(6) LOC="P67" | IOSTANDARD=LVTTL; # A6
NET WING_A(7) LOC="P75" | IOSTANDARD=LVTTL; # A7
NET WING_A(8) LOC="P79" | IOSTANDARD=LVTTL; # A8
NET WING_A(9) LOC="P81" | IOSTANDARD=LVTTL; # A9
NET WING_A(10) LOC="P83" | IOSTANDARD=LVTTL; # A10
NET WING_A(11) LOC="P85" | IOSTANDARD=LVTTL; # A11
NET WING_A(12) LOC="P88" | IOSTANDARD=LVTTL; # A12
NET WING_A(13) LOC="P93" | IOSTANDARD=LVTTL; # A13
NET WING_A(14) LOC="P98" | IOSTANDARD=LVTTL; # A14
NET WING_A(15) LOC="P100" | IOSTANDARD=LVTTL; # A15
NET WING_B(0) LOC="P99" | IOSTANDARD=LVTTL; # B0
NET WING_B(1) LOC="P97" | IOSTANDARD=LVTTL; # B1
NET WING_B(2) LOC="P92" | IOSTANDARD=LVTTL; # B2
NET WING_B(3) LOC="P87" | IOSTANDARD=LVTTL; # B3
NET WING_B(4) LOC="P84" | IOSTANDARD=LVTTL; # B4
NET WING_B(5) LOC="P82" | IOSTANDARD=LVTTL; # B5
NET WING_B(6) LOC="P80" | IOSTANDARD=LVTTL; # B6
NET WING_B(7) LOC="P78" | IOSTANDARD=LVTTL; # B7
NET WING_B(8) LOC="P74" | IOSTANDARD=LVTTL; # B8
NET WING_B(9) LOC="P95" | IOSTANDARD=LVTTL; # B9
NET WING_B(10) LOC="P62" | IOSTANDARD=LVTTL; # B10
NET WING_B(11) LOC="P59" | IOSTANDARD=LVTTL; # B11
NET WING_B(12) LOC="P57" | IOSTANDARD=LVTTL; # B12
NET WING_B(13) LOC="P55" | IOSTANDARD=LVTTL; # B13
NET WING_B(14) LOC="P50" | IOSTANDARD=LVTTL; # B14
NET WING_B(15) LOC="P47" | IOSTANDARD=LVTTL; # B15
NET WING_C(0) LOC="P114" | IOSTANDARD=LVTTL; # C0
NET WING_C(1) LOC="P115" | IOSTANDARD=LVTTL; # C1
NET WING_C(2) LOC="P116" | IOSTANDARD=LVTTL; # C2
NET WING_C(3) LOC="P117" | IOSTANDARD=LVTTL; # C3
NET WING_C(4) LOC="P118" | IOSTANDARD=LVTTL; # C4
NET WING_C(5) LOC="P119" | IOSTANDARD=LVTTL; # C5
NET WING_C(6) LOC="P120" | IOSTANDARD=LVTTL; # C6
NET WING_C(7) LOC="P121" | IOSTANDARD=LVTTL; # C7
NET WING_C(8) LOC="P123" | IOSTANDARD=LVTTL; # C8
NET WING_C(9) LOC="P124" | IOSTANDARD=LVTTL; # C9
NET WING_C(10) LOC="P126" | IOSTANDARD=LVTTL; # C10
NET WING_C(11) LOC="P127" | IOSTANDARD=LVTTL; # C11
NET WING_C(12) LOC="P131" | IOSTANDARD=LVTTL; # C12
NET WING_C(13) LOC="P132" | IOSTANDARD=LVTTL; # C13
NET WING_C(14) LOC="P133" | IOSTANDARD=LVTTL; # C14
NET WING_C(15) LOC="P134" | IOSTANDARD=LVTTL; # C15
NET DRAM_ADDR(0) LOC="P140" | IOSTANDARD=LVTTL | SLEW=FAST | NODELAY; # ADDR0
NET DRAM_ADDR(1) LOC="P139" | IOSTANDARD=LVTTL | SLEW=FAST | NODELAY; # ADDR1
NET DRAM_ADDR(2) LOC="P138" | IOSTANDARD=LVTTL | SLEW=FAST | NODELAY; # ADDR2
NET DRAM_ADDR(3) LOC="P137" | IOSTANDARD=LVTTL | SLEW=FAST | NODELAY; # ADDR3
NET DRAM_ADDR(4) LOC="P46" | IOSTANDARD=LVTTL | SLEW=FAST | NODELAY; # ADDR4
NET DRAM_ADDR(5) LOC="P45" | IOSTANDARD=LVTTL | SLEW=FAST | NODELAY; # ADDR5
NET DRAM_ADDR(6) LOC="P44" | IOSTANDARD=LVTTL | SLEW=FAST | NODELAY; # ADDR6
NET DRAM_ADDR(7) LOC="P43" | IOSTANDARD=LVTTL | SLEW=FAST | NODELAY; # ADDR7
NET DRAM_ADDR(8) LOC="P41" | IOSTANDARD=LVTTL | SLEW=FAST | NODELAY; # ADDR8
NET DRAM_ADDR(9) LOC="P40" | IOSTANDARD=LVTTL | SLEW=FAST | NODELAY; # ADDR9
NET DRAM_ADDR(10) LOC="P141" | IOSTANDARD=LVTTL | SLEW=FAST | NODELAY; # ADDR10
NET DRAM_ADDR(11) LOC="P35" | IOSTANDARD=LVTTL | SLEW=FAST | NODELAY; # ADDR11
NET DRAM_ADDR(12) LOC="P34" | IOSTANDARD=LVTTL | SLEW=FAST | NODELAY; # ADDR12
NET DRAM_DQ(0) LOC="P9" | IOSTANDARD=LVTTL | SLEW=FAST | NODELAY; # DATA0
NET DRAM_DQ(1) LOC="P10" | IOSTANDARD=LVTTL | SLEW=FAST | NODELAY; # DATA1
NET DRAM_DQ(2) LOC="P11" | IOSTANDARD=LVTTL | SLEW=FAST | NODELAY; # DATA2
NET DRAM_DQ(3) LOC="P12" | IOSTANDARD=LVTTL | SLEW=FAST | NODELAY; # DATA3
NET DRAM_DQ(4) LOC="P14" | IOSTANDARD=LVTTL | SLEW=FAST | NODELAY; # DATA4
NET DRAM_DQ(5) LOC="P15" | IOSTANDARD=LVTTL | SLEW=FAST | NODELAY; # DATA5
NET DRAM_DQ(6) LOC="P16" | IOSTANDARD=LVTTL | SLEW=FAST | NODELAY; # DATA6
NET DRAM_DQ(7) LOC="P8" | IOSTANDARD=LVTTL | SLEW=FAST | NODELAY; # DATA7
NET DRAM_DQ(8) LOC="P21" | IOSTANDARD=LVTTL | SLEW=FAST | NODELAY; # DATA8
NET DRAM_DQ(9) LOC="P22" | IOSTANDARD=LVTTL | SLEW=FAST | NODELAY; # DATA9
NET DRAM_DQ(10) LOC="P23" | IOSTANDARD=LVTTL | SLEW=FAST | NODELAY; # DATA10
NET DRAM_DQ(11) LOC="P24" | IOSTANDARD=LVTTL | SLEW=FAST | NODELAY; # DATA11
NET DRAM_DQ(12) LOC="P26" | IOSTANDARD=LVTTL | SLEW=FAST | NODELAY; # DATA12
NET DRAM_DQ(13) LOC="P27" | IOSTANDARD=LVTTL | SLEW=FAST | NODELAY; # DATA13
NET DRAM_DQ(14) LOC="P29" | IOSTANDARD=LVTTL | SLEW=FAST | NODELAY; # DATA14
NET DRAM_DQ(15) LOC="P30" | IOSTANDARD=LVTTL | SLEW=FAST | NODELAY; # DATA15
NET DRAM_DQM(0) LOC="P7" | IOSTANDARD=LVTTL | SLEW=FAST; # DQML OK
NET DRAM_DQM(1) LOC="P17" | IOSTANDARD=LVTTL | SLEW=FAST; # DQMH OK
NET DRAM_BA(0) LOC="P143" | IOSTANDARD=LVTTL | SLEW=FAST; # BA0 OK
NET DRAM_BA(1) LOC="P142" | IOSTANDARD=LVTTL | SLEW=FAST; # BA1 OK
NET DRAM_WE_N LOC="P6" | IOSTANDARD=LVTTL | SLEW=FAST; # nWE OK OK
NET DRAM_CAS_N LOC="P5" | IOSTANDARD=LVTTL | SLEW=FAST; # nCAS OK OK
NET DRAM_RAS_N LOC="P2" | IOSTANDARD=LVTTL | SLEW=FAST; # nRAS OK OK
NET DRAM_CS_N LOC="P1" | IOSTANDARD=LVTTL | SLEW=FAST; # nCS OK OK
NET DRAM_CLK LOC="P32" | IOSTANDARD=LVTTL | SLEW=FAST; # CLK OK
NET DRAM_CKE LOC="P33" | IOSTANDARD=LVTTL | SLEW=FAST; # CKE OK
NET SPI_CS LOC="P38" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_CS OK
NET SPI_SCK LOC="P70" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_CK OK
NET SPI_MOSI LOC="P64" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_SI OK
NET SPI_MISO LOC="P65" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # FLASH_SO OK
NET LED LOC="P112" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; # LED