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vivado.log
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#-----------------------------------------------------------
# Vivado v2016.2 (64-bit)
# SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016
# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
# Start of session at: Wed Jun 01 00:37:13 2022
# Process ID: 3144
# Current directory: D:/digital_logic/project/CPU31
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent11748 D:\digital_logic\project\CPU31\CPU31.xpr
# Log file: D:/digital_logic/project/CPU31/vivado.log
# Journal file: D:/digital_logic/project/CPU31\vivado.jou
#-----------------------------------------------------------
start_gui
open_project D:/digital_logic/project/CPU31/CPU31.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Vivado/2016.2/data/ip'.
update_compile_order -fileset sources_1
launch_simulation -install_path D:/digital_logic/modelsim_10.4c/_modelsim/win32 -noclean_dir
INFO: [USF-ModelSim-47] Finding simulator installation...
INFO: [USF-ModelSim-50] Using simulator executables from 'D:/digital_logic/modelsim_10.4c/_modelsim/win32/vsim.exe'
INFO: [USF-ModelSim-30] Simulation object is 'sim_1'...
INFO: [USF-modelsim-7] Finding pre-compiled libraries...
INFO: [USF-modelsim-11] File 'D:/xilinx_sim_lib/modelsim.ini' copied to run dir:'D:/digital_logic/project/CPU31/CPU31.sim/sim_1/behav'
INFO: [USF-ModelSim-40] Inspecting design source files for 'system' in fileset 'sim_1'...
INFO: [USF-ModelSim-107] Finding global include files...
INFO: [USF-ModelSim-108] Finding include directories and verilog header directory paths...
INFO: [USF-ModelSim-109] Fetching design files from 'sim_1'...
INFO: [USF-ModelSim-2] ModelSim::Compile design
INFO: [USF-ModelSim-15] Creating automatic 'do' files...
INFO: [USF-ModelSim-69] Executing 'COMPILE and ANALYZE' step in 'D:/digital_logic/project/CPU31/CPU31.sim/sim_1/behav'
Reading D:/digital_logic/modelsim_10.4c/_modelsim/tcl/vsim/pref.tcl
# 10.1c
# do {system_compile.do}
# Modifying modelsim.ini
# Model Technology ModelSim SE vlog 10.1c Compiler 2012.07 Jul 27 2012
# -- Compiling module Asynchronous_D_FF
# -- Compiling module gpr
# -- Compiling module nPC
# -- Compiling module add4
# -- Compiling module mux5
# -- Compiling module mux
# -- Compiling module II
# -- Compiling module ext5
# -- Compiling module ext18
# -- Compiling module ext
# -- Compiling module dec
# -- Compiling module CU
# -- Compiling module alu
# -- Compiling module add
# -- Compiling module pcreg
# -- Compiling module dm
# -- Compiling module cpu31
# -- Compiling module system
#
# Top level modules:
# system
# Model Technology ModelSim SE vlog 10.1c Compiler 2012.07 Jul 27 2012
# -- Compiling module glbl
#
# Top level modules:
# glbl
INFO: [USF-ModelSim-69] 'compile' step finished in '2' seconds
INFO: [USF-ModelSim-4] ModelSim::Simulate design
INFO: [USF-ModelSim-69] Executing 'SIMULATE' step in 'D:/digital_logic/project/CPU31/CPU31.sim/sim_1/behav'
Program launched (PID=3952)
launch_simulation -install_path D:/digital_logic/modelsim_10.4c/_modelsim/win32 -noclean_dir
INFO: [USF-ModelSim-47] Finding simulator installation...
INFO: [USF-ModelSim-50] Using simulator executables from 'D:/digital_logic/modelsim_10.4c/_modelsim/win32/vsim.exe'
INFO: [USF-ModelSim-30] Simulation object is 'sim_1'...
INFO: [USF-modelsim-7] Finding pre-compiled libraries...
INFO: [USF-modelsim-11] File 'D:/xilinx_sim_lib/modelsim.ini' copied to run dir:'D:/digital_logic/project/CPU31/CPU31.sim/sim_1/behav'
INFO: [USF-ModelSim-40] Inspecting design source files for 'system' in fileset 'sim_1'...
INFO: [USF-ModelSim-107] Finding global include files...
INFO: [USF-ModelSim-108] Finding include directories and verilog header directory paths...
INFO: [USF-ModelSim-109] Fetching design files from 'sim_1'...
INFO: [USF-ModelSim-2] ModelSim::Compile design
INFO: [USF-ModelSim-15] Creating automatic 'do' files...
INFO: [USF-ModelSim-69] Executing 'COMPILE and ANALYZE' step in 'D:/digital_logic/project/CPU31/CPU31.sim/sim_1/behav'
Reading D:/digital_logic/modelsim_10.4c/_modelsim/tcl/vsim/pref.tcl
# 10.1c
# do {system_compile.do}
# Modifying modelsim.ini
# Model Technology ModelSim SE vlog 10.1c Compiler 2012.07 Jul 27 2012
# -- Compiling module Asynchronous_D_FF
# -- Compiling module gpr
# -- Compiling module nPC
# -- Compiling module add4
# -- Compiling module mux5
# -- Compiling module mux
# -- Compiling module II
# -- Compiling module ext5
# -- Compiling module ext18
# -- Compiling module ext
# -- Compiling module dec
# -- Compiling module CU
# -- Compiling module alu
# -- Compiling module add
# -- Compiling module pcreg
# -- Compiling module dm
# -- Compiling module cpu31
# -- Compiling module system
#
# Top level modules:
# system
# Model Technology ModelSim SE vlog 10.1c Compiler 2012.07 Jul 27 2012
# -- Compiling module glbl
#
# Top level modules:
# glbl
INFO: [USF-ModelSim-69] 'compile' step finished in '2' seconds
INFO: [USF-ModelSim-4] ModelSim::Simulate design
INFO: [USF-ModelSim-69] Executing 'SIMULATE' step in 'D:/digital_logic/project/CPU31/CPU31.sim/sim_1/behav'
Program launched (PID=1468)
launch_simulation -install_path D:/digital_logic/modelsim_10.4c/_modelsim -noclean_dir
INFO: [USF-ModelSim-47] Finding simulator installation...
ERROR: [USF-ModelSim-51] Path to custom 'vsim.exe' executable program does not exist:D:/digital_logic/modelsim_10.4c/_modelsim/vsim.exe'
ERROR: [Common 17-39] 'send_msg_id' failed due to earlier errors.
while executing
"send_msg_id USF-ModelSim-051 ERROR "Path to custom '$tool_name' executable program does not exist:$tool_path'\n""
(procedure "::tclapp::xilinx::modelsim::usf_set_simulator_path" line 61)
invoked from within
"::tclapp::xilinx::modelsim::usf_set_simulator_path "modelsim""
(procedure "usf_modelsim_setup_simulation" line 8)
invoked from within
"usf_modelsim_setup_simulation"
(procedure "tclapp::xilinx::modelsim::setup" line 19)
invoked from within
"tclapp::xilinx::modelsim::setup { -simset sim_1 -mode behavioral -run_dir D:/digital_logic/project/CPU31/CPU31.sim/sim_1/behav -install_path D:/digita..."
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
compile_simlib -language all -dir {D:/xilinx_sim_lib} -simulator modelsim -simulator_exec_path {D:/digital_logic/modelsim_10.4c/_modelsim/win32} -library all -family all
INFO: [Vivado 12-4800] IP library compilation is currently not supported in project mode. Please re-run this command in either Vivado batch or tcl mode to compile IPs.
Compiling libraries for 'modelsim' simulator in 'D:\xilinx_sim_lib'
Creating modelsim.ini file...
Copying D:\digital_logic\modelsim_10.4c\_modelsim\win32/../modelsim.ini to modelsim.ini
** Warning: (vlib-34) Library already exists at "D:/xilinx_sim_lib/secureip".
Library verilog.secureip:verilog.axi_bfm will not be compiled, because precompiled library info is up to date.
** Warning: (vlib-34) Library already exists at "D:/xilinx_sim_lib/secureip".
Library verilog.secureip will not be compiled, because precompiled library info is up to date.
compile_simlib[verilog.secureip]: 0 error(s), 2 warning(s), 25.00 % complete
** Warning: (vlib-34) Library already exists at "D:/xilinx_sim_lib/unimacro".
Library vhdl.unisim:vhdl.unimacro will not be compiled, because precompiled library info is up to date.
** Warning: (vlib-34) Library already exists at "D:/xilinx_sim_lib/unifast".
Library vhdl.unisim:vhdl.unifast will not be compiled, because precompiled library info is up to date.
** Warning: (vlib-34) Library already exists at "D:/xilinx_sim_lib/unisim".
Library vhdl.unisim:vhdl.secureip_vhdl_unisim will not be compiled, because precompiled library info is up to date.
** Warning: (vlib-34) Library already exists at "D:/xilinx_sim_lib/unisim".
Library vhdl.unisim will not be compiled, because precompiled library info is up to date.
compile_simlib[vhdl.unisim]: 0 error(s), 3 warning(s), 50.00 % complete
** Warning: (vlib-34) Library already exists at "D:/xilinx_sim_lib/unimacro_ver".
Library verilog.unisim:verilog.unimacro will not be compiled, because precompiled library info is up to date.
** Warning: (vlib-34) Library already exists at "D:/xilinx_sim_lib/unifast_ver".
Library verilog.unisim:verilog.unifast will not be compiled, because precompiled library info is up to date.
** Warning: (vlib-34) Library already exists at "D:/xilinx_sim_lib/unisims_ver".
Library verilog.unisim will not be compiled, because precompiled library info is up to date.
compile_simlib[verilog.unisim]: 0 error(s), 3 warning(s), 75.00 % complete
** Warning: (vlib-34) Library already exists at "D:/xilinx_sim_lib/simprims_ver".
Library verilog.simprim will not be compiled, because precompiled library info is up to date.
compile_simlib[verilog.simprim]: 0 error(s), 1 warning(s), 100.00 % complete
Copying setup file 'modelsim.ini' to 'D:\xilinx_sim_lib/modelsim.ini' ...
compile_simlib: Time (s): cpu = 00:00:01 ; elapsed = 00:00:23 . Memory (MB): peak = 979.539 ; gain = 0.000
launch_simulation -install_path D:/digital_logic/modelsim_10.4c/_modelsim/win32 -noclean_dir
INFO: [USF-ModelSim-47] Finding simulator installation...
INFO: [USF-ModelSim-50] Using simulator executables from 'D:/digital_logic/modelsim_10.4c/_modelsim/win32/vsim.exe'
INFO: [USF-ModelSim-30] Simulation object is 'sim_1'...
INFO: [USF-modelsim-7] Finding pre-compiled libraries...
INFO: [USF-modelsim-11] File 'D:/xilinx_sim_lib/modelsim.ini' copied to run dir:'D:/digital_logic/project/CPU31/CPU31.sim/sim_1/behav'
INFO: [USF-ModelSim-40] Inspecting design source files for 'system' in fileset 'sim_1'...
INFO: [USF-ModelSim-107] Finding global include files...
INFO: [USF-ModelSim-108] Finding include directories and verilog header directory paths...
INFO: [USF-ModelSim-109] Fetching design files from 'sim_1'...
INFO: [USF-ModelSim-2] ModelSim::Compile design
INFO: [USF-ModelSim-15] Creating automatic 'do' files...
INFO: [USF-ModelSim-69] Executing 'COMPILE and ANALYZE' step in 'D:/digital_logic/project/CPU31/CPU31.sim/sim_1/behav'
Reading D:/digital_logic/modelsim_10.4c/_modelsim/tcl/vsim/pref.tcl
# 10.1c
# do {system_compile.do}
# ** Warning: (vlib-34) Library already exists at "work".
#
# ** Warning: (vlib-34) Library already exists at "msim".
#
# ** Warning: (vlib-34) Library already exists at "msim/xil_defaultlib".
#
# Modifying modelsim.ini
# Model Technology ModelSim SE vlog 10.1c Compiler 2012.07 Jul 27 2012
# -- Compiling module Asynchronous_D_FF
# -- Compiling module gpr
# -- Compiling module nPC
# -- Compiling module add4
# -- Compiling module mux5
# -- Compiling module mux
# -- Compiling module II
# -- Compiling module ext5
# -- Compiling module ext18
# -- Compiling module ext
# -- Compiling module dec
# -- Compiling module CU
# -- Compiling module alu
# -- Compiling module add
# -- Compiling module pcreg
# -- Compiling module dm
# -- Compiling module cpu31
# -- Compiling module system
#
# Top level modules:
# system
# Model Technology ModelSim SE vlog 10.1c Compiler 2012.07 Jul 27 2012
# -- Compiling module glbl
#
# Top level modules:
# glbl
INFO: [USF-ModelSim-69] 'compile' step finished in '2' seconds
INFO: [USF-ModelSim-4] ModelSim::Simulate design
INFO: [USF-ModelSim-69] Executing 'SIMULATE' step in 'D:/digital_logic/project/CPU31/CPU31.sim/sim_1/behav'
Program launched (PID=2036)
exit
INFO: [Common 17-206] Exiting Vivado at Wed Jun 01 00:44:53 2022...