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example.xml
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>customized_ip</spirit:library>
<spirit:name>AccelerometerCtl2_0</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>RESET</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>RESET</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_veriloginstantiationtemplate</spirit:name>
<spirit:displayName>Verilog Instantiation Template</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis.template</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:fileSetRef>
<spirit:localName>xilinx_veriloginstantiationtemplate_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Dec 13 13:53:45 UTC 2018</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
<spirit:value>1c38824a</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRCversion</spirit:name>
<spirit:value>1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>customizationCRC</spirit:name>
<spirit:value>d29f1e3a</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>customizationCRCversion</spirit:name>
<spirit:value>6</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
<spirit:displayName>Synthesis</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Dec 13 13:53:47 UTC 2018</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
<spirit:value>1c38824a</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRCversion</spirit:name>
<spirit:value>1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>customizationCRC</spirit:name>
<spirit:value>d29f1e3a</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>customizationCRCversion</spirit:name>
<spirit:value>6</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Dec 13 13:53:47 UTC 2018</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
<spirit:value>1c38824a</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRCversion</spirit:name>
<spirit:value>1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>customizationCRC</spirit:name>
<spirit:value>d29f1e3a</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>customizationCRCversion</spirit:name>
<spirit:value>6</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Dec 13 13:53:47 UTC 2018</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
<spirit:value>1c38824a</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRCversion</spirit:name>
<spirit:value>1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>customizationCRC</spirit:name>
<spirit:value>422282e8</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>customizationCRCversion</spirit:name>
<spirit:value>6</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Dec 13 13:53:47 UTC 2018</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
<spirit:value>1c38824a</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRCversion</spirit:name>
<spirit:value>1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>customizationCRC</spirit:name>
<spirit:value>422282e8</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>customizationCRCversion</spirit:name>
<spirit:value>6</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_externalfiles</spirit:name>
<spirit:displayName>External Files</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Dec 13 13:54:35 UTC 2018</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
<spirit:value>1c38824a</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRCversion</spirit:name>
<spirit:value>1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>customizationCRC</spirit:name>
<spirit:value>d29f1e3a</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>customizationCRCversion</spirit:name>
<spirit:value>6</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_xpgui</spirit:name>
<spirit:displayName>UI Layout</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>SYSCLK</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>RESET</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>SCLK</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>MOSI</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>MISO</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>SS</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>ACCEL_X_OUT</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">8</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>ACCEL_Y_OUT</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">8</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>ACCEL_MAG_OUT</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">11</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>ACCEL_TMP_OUT</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">11</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
</spirit:ports>
<spirit:modelParameters>
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
<spirit:name>SYSCLK_FREQUENCY_HZ</spirit:name>
<spirit:displayName>Sysclk Frequency Hz</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SYSCLK_FREQUENCY_HZ">100000000</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>SCLK_FREQUENCY_HZ</spirit:name>
<spirit:displayName>Sclk Frequency Hz</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SCLK_FREQUENCY_HZ">1000000</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>NUM_READS_AVG</spirit:name>
<spirit:displayName>Num Reads Avg</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_READS_AVG">16</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>UPDATE_FREQUENCY_HZ</spirit:name>
<spirit:displayName>Update Frequency Hz</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.UPDATE_FREQUENCY_HZ">100</spirit:value>
</spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_veriloginstantiationtemplate_view_fileset</spirit:name>
<spirit:file>
<spirit:name>AccelerometerCtl2_0.vho</spirit:name>
<spirit:userFileType>vhdlTemplate</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>AccelerometerCtl2_0.veo</spirit:name>
<spirit:userFileType>verilogTemplate</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>project_1.srcs/constrs_1/imports/Desktop/Nexys4DDR_Master.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>project_1.srcs/sources_1/ip/Square_Root/Square_Root.xci</spirit:name>
<spirit:userFileType>xci</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>project_1.srcs/sources_1/new/SPI_if.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>project_1.srcs/sources_1/new/ADXL362Ctrl.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>project_1.srcs/sources_1/new/AccelArithmetics.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>project_1.srcs/sources_1/new/AccelerometerCtl.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>synth/AccelerometerCtl2_0.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>project_1.srcs/sources_1/new/SPI_if.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>project_1.srcs/sources_1/ip/Square_Root/Square_Root.xci</spirit:name>
<spirit:userFileType>xci</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>project_1.srcs/sources_1/new/ADXL362Ctrl.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>project_1.srcs/sources_1/new/AccelArithmetics.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>project_1.srcs/sources_1/new/AccelerometerCtl.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>sim/AccelerometerCtl2_0.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
<spirit:file>
<spirit:name>AccelerometerCtl2_0.dcp</spirit:name>
<spirit:userFileType>dcp</spirit:userFileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>AccelerometerCtl2_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>AccelerometerCtl2_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>AccelerometerCtl2_0_sim_netlist.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>AccelerometerCtl2_0_sim_netlist.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
<spirit:file>
<spirit:name>xgui/AccelerometerCtl2_0_v1_0.tcl</spirit:name>
<spirit:fileType>tclSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_2808b0eb</spirit:userFileType>
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>AccelerometerCtl_v3_0</spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>SYSCLK_FREQUENCY_HZ</spirit:name>
<spirit:displayName>Sysclk Frequency Hz</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SYSCLK_FREQUENCY_HZ">100000000</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>SCLK_FREQUENCY_HZ</spirit:name>
<spirit:displayName>Sclk Frequency Hz</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SCLK_FREQUENCY_HZ">1000000</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_READS_AVG</spirit:name>
<spirit:displayName>Num Reads Avg</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_READS_AVG">16</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>UPDATE_FREQUENCY_HZ</spirit:name>
<spirit:displayName>Update Frequency Hz</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.UPDATE_FREQUENCY_HZ">100</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">AccelerometerCtl2_0</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:displayName>AccelerometerCtl_v3_0</xilinx:displayName>
<xilinx:coreRevision>4</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2019-12-06T06:30:43Z</xilinx:coreCreationDateTime>
<xilinx:tags>
<xilinx:tag xilinx:name="xilinx.com:user:AccelerometerCtl:1.0_ARCHIVE_LOCATION">C:/Users/fandahao/Desktop/project_</xilinx:tag>
<xilinx:tag xilinx:name="xilinx.com:user:AccelerometerCtl1:1.0_ARCHIVE_LOCATION">C:/Users/fandahao/Desktop/project_</xilinx:tag>
<xilinx:tag xilinx:name="xilinx.com:user:AccelerometerCtl1:2.0_ARCHIVE_LOCATION">C:/Users/fandahao/Desktop/project_</xilinx:tag>
<xilinx:tag xilinx:name="xilinx.com:user:AccelerometerCtl2:2.0_ARCHIVE_LOCATION">C:/Users/fandahao/Desktop/project_</xilinx:tag>
<xilinx:tag xilinx:name="xilinx.com:user:AccelerometerCtl2:3.0_ARCHIVE_LOCATION">C:/Users/fandahao/Desktop/project_</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@1defe09f_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@388cf729_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@a4f4d3_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7d71beba_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@3de6fc39_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@58032bd7_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@42dc36bb_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@192b68c5_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@701697d_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4cecd92a_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@1eb56def_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@64c08941_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4976711b_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@6944b034_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@41b3f169_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@1333249a_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7de68173_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@6359bb22_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7f18203e_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@3423d2f3_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7cc9f6fe_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@64808397_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@23b1c1e3_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@48642536_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@420b8fde_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@496380f1_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@723b44a_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@597f886a_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@6ff13b20_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@72468fcb_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@56edc1dc_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@174a267b_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@2ec95112_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7f268f95_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5ea5815a_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@3ed40e40_ARCHIVE_LOCATION">c:/Users/14832/Documents/study/CS/moshu/labs/lab10/balance</xilinx:tag>
</xilinx:tags>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2019.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="467bb3c9"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="8b9d6af0"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="8b6e43cd"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="d4bf3af8"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="b5c86b76"/>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>