2RP_GPIO_BRAM_in_RP_Interface_INI

Versal™ Adaptive SoC DFX Tutorials See Vivado™ Development Environment on amd.com

2 RP Design with NoC INI in the Static-RM Interface

Version: AMD Vivado™ 2024.2

This AMD Versal™ adaptive SoC DFX design has two RPs:

• AXI general purpose I/0 (GPIO) in the first RP.
• AXI block RAM in second RP.

Each RP has two RMs:

• RP1: RP1RM1, RP1RM2

• RP2: RP2RM1, RP2RM2

• GPIO in Static Region connected to Constant: 0XC00100F

• GPIO in RP1RM1 connected to Constant: 0XFACEFEED

• GPIO in RP1RM2 connected to Constant: 0XFEEDC0DE

• The Static-RP interface is using the NoC Inter NoC Interconnect (INI). Hence, there is no need for an additional DFX Decoupler in the static region.

Currently, block RAMs are not initialized to any memory initialization value in the design.

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