2RPs_Sharing_ClockRegion

Versal™ Adaptive SoC DFX Tutorials See Vivado™ Development Environment on amd.com

Clock Region Sharing Between Two Reconfigurable Partitions

Version: AMD Vivado™ 2024.2

Introduction

• This design demonstrates that a clock region in AMD Versal™ Adapative SoCs can be shared among multiple reconfigurable partitions (RP).
• Reconfigurable partition pblocks both having internal clocking resources can share one clock region.
• The RCLK row in the clock region is shared between two RPs.
• You can range pblocks one above RCLK row and one below the RCLK row of the clock region.
• RCLK sharing is automatically taken care of by the DFX flow in Vivado. You cannot range RCLK sites in your pblock.

Design Flow

Become familiar with the inter-processor interrupt (IPI) BDC based DFX flow in Vivado using the "2RP_GPIO_BRAM_in_RP_Interface_INI" example design. The same design flow is used in this tutorial.

IPI

• There are two RPs in the design.

• Both RPs have internal clocking resources.

  

Implementation

• These are the pblocks used for implementation. As you can see, pblocks for the two reconfigurable partitions share one clock region, above and below the RCLK row, which is the boundary between the two.

  

• This is the schematic of the two internal clocks of the RPs.

  

• This is the device view of a clock region being shared by two reconfiurable partitions: above and below the RP. Notice that RCLK row is being shared by internal clock nets from both partitions.

  

• This is the magnified view of the device view where the RCLK row is being shared by the internal clocks of two RPs.

  

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