From d9ba4fdaacaa95d97e6623c36addbd7c8dbca5c3 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 11 Dec 2024 10:25:50 +0100 Subject: [PATCH] Remove references to ilang --- examples/bitcnt/test_eq.sby | 2 +- examples/bitcnt/test_fm.sby | 2 +- examples/picorv32_primes/eq_bmc.sby | 2 +- examples/picorv32_primes/eq_bmc.sh | 4 ++-- examples/picorv32_primes/eq_sim3.sby | 2 +- examples/picorv32_primes/eq_sim3.sh | 4 ++-- examples/picorv32_primes/sim_simple.sh | 2 +- mcy.py | 6 +++--- scripts/create_mutated.sh | 4 ++-- 9 files changed, 14 insertions(+), 14 deletions(-) diff --git a/examples/bitcnt/test_eq.sby b/examples/bitcnt/test_eq.sby index 27c9f56..0695257 100644 --- a/examples/bitcnt/test_eq.sby +++ b/examples/bitcnt/test_eq.sby @@ -8,7 +8,7 @@ smtbmc yices [script] read_verilog -sv test_eq.sv -read_ilang mutated.il +read_rtlil mutated.il prep -top miter fmcombine miter ref uut flatten diff --git a/examples/bitcnt/test_fm.sby b/examples/bitcnt/test_fm.sby index a7c2708..76fbc5f 100644 --- a/examples/bitcnt/test_fm.sby +++ b/examples/bitcnt/test_fm.sby @@ -8,7 +8,7 @@ smtbmc boolector [script] read_verilog -sv test_fm.sv -read_ilang mutated.il +read_rtlil mutated.il prep -top testbench flatten opt -fast diff --git a/examples/picorv32_primes/eq_bmc.sby b/examples/picorv32_primes/eq_bmc.sby index fd05add..9db1714 100644 --- a/examples/picorv32_primes/eq_bmc.sby +++ b/examples/picorv32_primes/eq_bmc.sby @@ -16,7 +16,7 @@ smtbmc yices output("verilog_defines -Dmutidx=%s" % task) --pycode-end-- read_verilog -sv miter.sv -read_ilang mutated.il +read_rtlil mutated.il prep -top miter fmcombine miter ref uut flatten diff --git a/examples/picorv32_primes/eq_bmc.sh b/examples/picorv32_primes/eq_bmc.sh index 6aa1863..31dc483 100644 --- a/examples/picorv32_primes/eq_bmc.sh +++ b/examples/picorv32_primes/eq_bmc.sh @@ -4,11 +4,11 @@ exec 2>&1 set -ex { - echo "read_ilang ../../database/design.il" + echo "read_rtlil ../../database/design.il" while read -r idx mut; do echo "mutate -ctrl mutsel 8 ${idx} ${mut#* }" done < input.txt - echo "write_ilang mutated.il" + echo "write_rtlil mutated.il" } > mutate.ys yosys -ql mutate.log mutate.ys diff --git a/examples/picorv32_primes/eq_sim3.sby b/examples/picorv32_primes/eq_sim3.sby index 1b707df..a450d48 100644 --- a/examples/picorv32_primes/eq_sim3.sby +++ b/examples/picorv32_primes/eq_sim3.sby @@ -16,7 +16,7 @@ abc sim3 output("verilog_defines -Dmutidx=%s" % task) --pycode-end-- read_verilog -sv miter.sv -read_ilang mutated.il +read_rtlil mutated.il prep -top miter fmcombine miter ref uut diff --git a/examples/picorv32_primes/eq_sim3.sh b/examples/picorv32_primes/eq_sim3.sh index e891eff..6cf6a11 100644 --- a/examples/picorv32_primes/eq_sim3.sh +++ b/examples/picorv32_primes/eq_sim3.sh @@ -4,11 +4,11 @@ exec 2>&1 set -ex { - echo "read_ilang ../../database/design.il" + echo "read_rtlil ../../database/design.il" while read -r idx mut; do echo "mutate -ctrl mutsel 8 ${idx} ${mut#* }" done < input.txt - echo "write_ilang mutated.il" + echo "write_rtlil mutated.il" } > mutate.ys yosys -ql mutate.log mutate.ys diff --git a/examples/picorv32_primes/sim_simple.sh b/examples/picorv32_primes/sim_simple.sh index f75747f..e546ca1 100644 --- a/examples/picorv32_primes/sim_simple.sh +++ b/examples/picorv32_primes/sim_simple.sh @@ -6,7 +6,7 @@ exec 2>&1 set -ex { - echo "read_ilang ../../database/design.il" + echo "read_rtlil ../../database/design.il" while read -r idx mut; do echo "mutate -ctrl mutsel 8 ${idx} ${mut#* }" done < input.txt diff --git a/mcy.py b/mcy.py index 4dd6087..e2416f1 100644 --- a/mcy.py +++ b/mcy.py @@ -283,7 +283,7 @@ def reset_status(db, cfg, do_reset=False): log_step("Creating additional mutations script file.") with open("database/mutations2.ys", "w") as f: - print("read_ilang database/design.il", file=f) + print("read_rtlil database/design.il", file=f) print(f"mutate -list {cfg.opt_size} -seed {cfg.opt_seed} -none{''.join(' -cfg %s %d' % (k, v) for k, v, in sorted(cfg.mutopts.items()))}{' -mode ' + cfg.opt_mode if cfg.opt_mode else ''} -o database/mutations2.txt -s database/sources.txt{' ' + ' '.join(cfg.select) if len(cfg.select) else ''}", file=f) log_step("Creating additional mutations.") @@ -473,7 +473,7 @@ def init_command(force, nosetup, trace): with open("database/design.ys", "w") as f: for line in cfg.script: print(line, file=f) - print("write_ilang database/design.il", file=f) + print("write_rtlil database/design.il", file=f) log_step("Creating design RTL.") task = Task("yosys -ql database/design.log database/design.ys") @@ -481,7 +481,7 @@ def init_command(force, nosetup, trace): log_step("Creating mutations script file.") with open("database/mutations.ys", "w") as f: - print("read_ilang database/design.il", file=f) + print("read_rtlil database/design.il", file=f) print(f"mutate -list {cfg.opt_size} -seed {cfg.opt_seed} -none{''.join(' -cfg %s %d' % (k, v) for k, v, in sorted(cfg.mutopts.items()))}{' -mode ' + cfg.opt_mode if cfg.opt_mode else ''} -o database/mutations.txt -s database/sources.txt{' ' + ' '.join(cfg.select) if len(cfg.select) else ''}", file=f) log_step("Creating mutations.") diff --git a/scripts/create_mutated.sh b/scripts/create_mutated.sh index 054e62d..2aa2480 100644 --- a/scripts/create_mutated.sh +++ b/scripts/create_mutated.sh @@ -68,7 +68,7 @@ if [[ ( "$output_file" == *.v ) ]]; then elif [[ ( "$output_file" == *.sv ) ]]; then write_cmd="write_verilog -norename -sv $output_file" elif [[ ( "$output_file" == *.il ) ]]; then - write_cmd="write_ilang $output_file" + write_cmd="write_rtlil $output_file" else echo "Unrecognized file extension: '$output_file' (this script can write .v, .sv and .il files)" 1>&2 # usage 1>&2 @@ -76,7 +76,7 @@ else fi { - echo "read_ilang $design_file" + echo "read_rtlil $design_file" while read -r idx mut; do if [[ "$use_ctrl" -eq 1 ]]; then echo "mutate -ctrl mutsel ${ctrl_width} ${idx} ${mut#* }"