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ERROR: Unconstrained IO #1411
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That's very interesting. As I see it IBUF is in a module that is not a TOP module. Naturally it will be unconstrained because it is not connected to any pin in principle. How does this work? It is still unclear to me. |
did you set -D LEDS_NR=6 for when you run yosys?
did you set -D LEDS_NR=6 for when you run yosys? |
It seems to be a matter of the -noflatten key - which results in I/O buffers at all levels of the hierarchy. So far I am inclined to simply disallow the use of this key. |
I don't know much about synthesis or P&R tools - I'm just a user. And while I know a bit of Verilog, I have no idea about the json.
I have a design that I can synthesize with yosys without -noflatten, then route with nextpnr. But if I synthesize with yosys with -noflatten, routing with nextpnr fails. So I guess there is a problem in either yosys or nextpnr, but don't really know. Since I get the error message from nextpnr, I'm opening the ticket here. I used nextpnr from the master branch from today.
tangnano9k2_synth.json.gz
I encountered this issue on a Debian GNU/Linux testing system on amd64.
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