diff --git a/.gitignore b/.gitignore
index 8586c55..134b39b 100644
--- a/.gitignore
+++ b/.gitignore
@@ -5,4 +5,6 @@ test/logs/*
 gds/**/*.gltf
 
 .DS_Store
-results.xml
\ No newline at end of file
+results.xml
+
+sim_build/**
diff --git a/Makefile b/Makefile
index bc10f84..d8e1aa5 100644
--- a/Makefile
+++ b/Makefile
@@ -5,7 +5,7 @@ export LIBPYTHON_LOC=$(shell cocotb-config --libpython)
 test_%:
 	make compile
 	iverilog -o build/sim.vvp -s gpu -g2012 build/gpu.v
-	MODULE=test.test_$* vvp -M $$(cocotb-config --prefix)/cocotb/libs -m libcocotbvpi_icarus build/sim.vvp
+	MODULE=test.test_$* vvp -M $$(cocotb-config --prefix)/cocotb/libs -m libcocotbvpi_icarus build/sim.vvp -fst
 
 compile:
 	make compile_alu
@@ -19,7 +19,12 @@ compile:
 compile_%:
 	sv2v -w build/$*.v src/$*.sv
 
-# TODO: Get gtkwave visualizaiton
+# The gtkwave FST file -> sim_build/gpu.fst
+test.test_%: compile
+	make -f Makefile.cocotb.mk MODULE=$@
 
 show_%: %.vcd %.gtkw
 	gtkwave $^
+
+clean:
+	rm -rf build/* sim_build
\ No newline at end of file
diff --git a/Makefile.cocotb.mk b/Makefile.cocotb.mk
new file mode 100644
index 0000000..b6ea616
--- /dev/null
+++ b/Makefile.cocotb.mk
@@ -0,0 +1,19 @@
+# Makefile
+
+# defaults
+SIM ?= icarus
+TOPLEVEL_LANG ?= verilog
+
+# Enable wakeform
+WAVES=1
+
+VERILOG_SOURCES += build/gpu.v
+
+# TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
+TOPLEVEL = gpu
+
+# MODULE is the basename of the Python test file
+MODULE := test.test_matadd
+
+# include cocotb's make rules to take care of the simulator setup
+include $(shell cocotb-config --makefiles)/Makefile.sim