No rule to make target

[pitpg]

Hi, I'm trying to build a example project for KC705. I get an error: "No rule to make target '../lib/eth/rtl/oddr.v', needed by 'update_config.tcl'. Stop." What am I doing wrong?

Full listing of Cygwin64 Terminal commands and messages:
ppg@DESKTOP-24H7CNM /cygdrive/e/Project/Eth1G/Xilinx/verilog-ethernet/example/KC705/fpga_gmii
$ make
cd fpga && make
make[1]: Entering directory '/cygdrive/e/Project/Eth1G/Xilinx/verilog-ethernet/example/KC705/fpga_gmii/fpga'
make[1]: *** No rule to make target '../lib/eth/rtl/oddr.v', needed by 'update_config.tcl'. Stop.
make[1]: Leaving directory '/cygdrive/e/ProjectEth1G/Xilinx/verilog-ethernet/example/KC705/fpga_gmii/fpga'
make: *** [Makefile:14: fpga] Error 2

[saman-coder]

Hi pitpg,
Each example has a folder lib/eth which is a symbol link towards the rtl folder in the root of the repository. If you cloned the repository on Windows, the symbol link probably does not work.
to solve this error edit make file in this path
\verilog-eth\example\KC705\fpga_gmii\fpga
and replace all of lines same SYN_FILES += lib/eth/**** with SYN_FILES += ../../../******.
If you encounter any problems, leave a message.