issue#6 - csi_rx_align_word

[Juninho99]

Issue: Review of csi_rx_align_word.sv module

We need to review the implementation of csi_rx_align_word.sv module.

Modified version, as proposed in the issue#5 branch, works properly in simulation. However, something isn't right for the version that's currently on the main branch.

Below are two waveforms that show the difference.

What we see on the first wave is that valid_out is lined up with word_out, while also filtering out the B8 sync bytes, which is indeed the design intent.

On the second wave however, valid_out is encompassing the B8. That causes downstream failures. Also, few other signals (wait_for_sync, packet_done, etc.) are not looking right in the second wave.

[chili-chips-ba]

The original bug was about misalignment of VLD and DATA, and simple to fix. However we still cannot declare the align_word module fully tested, as the existing testbench does not exercise its primary function.

To close this issue, static lane-to-lane skew needs to be added to the traffic generator. The test should cover at least the following two cases:

1. when lane-to-lane skew is within deskewing range of this module, which is 2 clock cycles
2. when lane-to-lane skew exceed that range

Similarly, we cannot declare that align_byte module is fully tested without introducing bit skew into traffic generator for each lane.

@Juninho99, let's improve the sim setup with these must-have capabilities for further progress on this ticket.

[chili-chips-ba]

@Juninho99 please consider closing this ticket. If there are any outstanding DV-related activities, open a new task issue to track them.