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[Classification]

  1. Mixed Type Patterns

    • Fan, Mengying, Qin Wang, and Ben van der Waal. "Wafer defect patterns recognition based on OPTICS and multi-label classification." 2016 IEEE Advanced Information Management, Communicates, Electronic and Automation Control Conference (IMCEC). IEEE, 2016.

    • K. Kyeong and H. Kim, “Classification of mixed-type defect patterns in wafer bin maps using convolutional neural networks,” IEEE Transactions on Semiconductor Manufacturing, vol. 31, pp. 395–402, 8 2018

    • Tello, Ghalia, et al. "Deep-structured machine learning model for the recognition of mixed-defect patterns in semiconductor fabrication processes." IEEE Transactions on Semiconductor Manufacturing 31.2 (2018): 315-322.

    • Wang, Junliang, et al. "Deformable convolutional networks for efficient mixed-type wafer defect pattern recognition." IEEE Transactions on Semiconductor Manufacturing 33.4 (2020): 587-596.

    • Wang, Rui, and Nan Chen. "Defect pattern recognition on wafers using convolutional neural networks." Quality and Reliability Engineering International 36.4 (2020): 1245-1257.

    • Chen, Shouhong, et al. "Research on mixed type wafer map based on deep convolutional neural network." International Conference on Optics and Image Processing (ICOIP 2021). Vol. 11915. SPIE, 2021.

  2. Dataset Imbalance

    • Wang, Junliang, et al. "AdaBalGAN: An improved generative adversarial network with imbalanced learning for wafer defective pattern recognition." IEEE Transactions on Semiconductor Manufacturing 32.3 (2019): 310-319.
    • Hyun, Yunseung, and Heeyoung Kim. "Memory-augmented convolutional neural networks with triplet loss for imbalanced wafer defect pattern classification." IEEE Transactions on Semiconductor Manufacturing 33.4 (2020): 622-634.
    • Saqlain, Muhammad, Qasim Abbas, and Jong Yun Lee. "A deep convolutional neural network for wafer defect identification on an imbalanced dataset in semiconductor manufacturing processes." IEEE Transactions on Semiconductor Manufacturing 33.3 (2020): 436-444.

  3. Label Cost

    • Kong, Yuting, and Dong Ni. "Semi-supervised classification of wafer map based on ladder network." 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT). IEEE, 2018.
    • H. Lee and H. Kim, “Semi-supervised multi-label learning for classification of wafer bin maps with mixed-type defect patterns,” IEEE Transactions on Semiconductor Manufacturing, vol. 33, no. 4, pp. 653–662, 2020.
    • Shim, Jaewoong, Seokho Kang, and Sungzoon Cho. "Active learning of convolutional neural network for cost-effective wafer map pattern classification." IEEE Transactions on Semiconductor Manufacturing 33.2 (2020): 258-266.
    • H. Kahng and S. B. Kim, "Self-Supervised Representation Learning for Wafer Bin Map Defect Pattern Classification," in IEEE Transactions on Semiconductor Manufacturing, vol. 34, no. 1, pp. 74-86, Feb. 2021, doi: 10.1109/TSM.2020.3038165.
    • Shim, Jaewoong, Seokho Kang, and Sungzoon Cho. "Active cluster annotation for wafer map pattern classification in semiconductor manufacturing." Expert Systems with Applications (2021): 115429.

  4. Light-Weighted Model

    • Tsai, Tsung-Han, and Yu-Chen Lee. "A light-weight neural network for wafer map classification based on data augmentation." IEEE Transactions on Semiconductor Manufacturing 33.4 (2020): 663-672.

  5. Others

    • Dong, Hang, Nan Chen, and Kaibo Wang. "Wafer yield prediction using derived spatial variables." Quality and Reliability Engineering International 33.8 (2017): 2327-2342.

    • Piao, Minghao, et al. "Decision tree ensemble-based wafer map failure pattern recognition based on radon transform-based features." IEEE Transactions on Semiconductor Manufacturing 31.2 (2018): 250-257.

    • Nakazawa, Takeshi, and Deepak V. Kulkarni. "Wafer map defect pattern classification and image retrieval using convolutional neural network." IEEE Transactions on Semiconductor Manufacturing 31.2 (2018): 309-314.

    • Santos, Tiago, et al. "Feature extraction from analog wafermaps: A comparison of classical image processing and a deep generative model." IEEE Transactions on Semiconductor Manufacturing 32.2 (2019): 190-198.

    • Saqlain, Muhammad, Bilguun Jargalsaikhan, and Jong Yun Lee. "A voting ensemble classifier for wafer map defect patterns identification in semiconductor manufacturing." IEEE Transactions on Semiconductor Manufacturing 32.2 (2019): 171-182.

    • Yu, Naigong, Qiao Xu, and Honglu Wang. "Wafer defect pattern recognition and analysis based on convolutional neural network." IEEE Transactions on Semiconductor Manufacturing 32.4 (2019): 566-573.

    • Kim, Junhong, et al. "Bin2Vec: A better wafer bin map coloring scheme for comprehensible visualization and effective bad wafer classification." Applied Sciences 9.3 (2019): 597.

    • Wang, Yi, and Dong Ni. "Multi-bin wafer maps defect patterns classification." 2019 IEEE International Conference on Smart Manufacturing, Industrial & Logistics Engineering (SMILE). IEEE, 2019.

    • Yu, Jianbo, Xiaoyun Zheng, and Jiatong Liu. "Stacked convolutional sparse denoising auto-encoder for identification of defect patterns in semiconductor wafer map." Computers in Industry 109 (2019): 121-133

    • Yu, Jianbo. "Enhanced stacked denoising autoencoder-based feature learning for recognition of wafer map defects." IEEE Transactions on Semiconductor Manufacturing 32.4 (2019): 613-624.

    • Hsu, CY., Chien, JC. Ensemble convolutional neural networks with weighted majority for wafer bin map pattern classification. J Intell Manuf (2020). https://doi.org/10.1007/s10845-020-01687-7

    • Kang, Seokho. "Rotation-Invariant Wafer Map Pattern Classification With Convolutional Neural Networks." Ieee Access 8 (2020): 170650-170658.

    • Jin, Cheng Hao, et al. "Wafer map defect pattern classification based on convolutional neural network features and error-correcting output codes." Journal of Intelligent Manufacturing 31.8 (2020): 1861-1875.

    • Li, Katherine Shu-Min, et al. "Hidden Wafer Scratch Defects Projection for Diagnosis and Quality Enhancement." IEEE Transactions on Semiconductor Manufacturing 34.1 (2020): 9-16.

    • Yu, Jianbo, and Jiatong Liu. "Two-dimensional principal component analysis-based convolutional autoencoder for wafer map defect detection." IEEE Transactions on Industrial Electronics (2020).

    • Kang, Hyungu, and Seokho Kang. "A stacking ensemble classifier with handcrafted and convolutional features for wafer map pattern classification." Computers in Industry 129 (2021): 103450.

    • Yu, Jianbo, Zongli Shen, and Shijin Wang. "Wafer map defect recognition based on deep transfer learning-based densely connected convolutional network and deep forest." Engineering Applications of Artificial Intelligence 105 (2021): 104387.

[Clustering]

  • Taha, Kamal, Khaled Salah, and Paul D. Yoo. "Clustering the dominant defective patterns in semiconductor wafer maps." IEEE Transactions on Semiconductor Manufacturing 31.1 (2017): 156-165.
  • J. Kim, Y. Lee, and H. Kim, “Detection and clustering of mixed-type defect patterns in wafer bin maps,” IISE Transactions, vol. 50, pp. 99–111, 2 2018.
  • Tulala, Peter, et al. "Unsupervised wafermap patterns clustering via variational autoencoders." 2018 International Joint Conference on Neural Networks (IJCNN). IEEE, 2018.
  • Jin, Cheng Hao, et al. "A novel DBSCAN-based defect pattern detection and classification framework for wafer bin map." IEEE Transactions on Semiconductor Manufacturing 32.3 (2019): 286-292.
  • Hwang, Jonghyun, and Heeyoung Kim. "Variational deep clustering of wafer map patterns." IEEE Transactions on Semiconductor Manufacturing 33.3 (2020): 466-475.
  • Lee, Jea Hoon, Il-Chul Moon, and Rosy Oh. "Similarity Search on Wafer Bin Map through Nonparametric and Hierarchical Clustering." IEEE Transactions on Semiconductor Manufacturing (2021).
  • Kim, Donghwa, and Pilsung Kang. "Dynamic Clustering for Wafer Map Patterns using Self-Supervised Learning on Convolutional Autoencoders." IEEE Transactions on Semiconductor Manufacturing (2021).
  • Park, Seyoung, Jaeyeon Jang, and Chang Ouk Kim. "Discriminative feature learning and cluster-based defect label reconstruction for reducing uncertainty in wafer bin map labels." Journal of Intelligent Manufacturing 32.1 (2021): 251-263.
  • Ezzat, Ahmed Aziz, et al. "A Graph-Theoretic Approach for Spatial Filtering and Its Impact on Mixed-Type Spatial Pattern Recognition in Wafer Bin Maps." IEEE Transactions on Semiconductor Manufacturing 34.2 (2021): 194-206.

[Segmentation]

  • Lee, C. H., and S. B. Kim. "Identifying wafer defect patterns by variational autoencoder and SegNet." Journal of the Korean Institute of Industrial Engineers 45.2 (2019): 117-124.
  • T. Nakazawa and D. V. Kulkarni, “Anomaly detection and segmentation for wafer defect patterns using deep convolutional encoder-decoder neural network architectures in semiconductor manufacturing,” IEEE Transactions on Semiconductor Manufacturing, vol. 32, pp. 250–256, 5 2019.
  • Kong, Yuting, and Dong Ni. "Recognition and location of mixed-type patterns in wafer bin maps." 2019 IEEE International Conference on Smart Manufacturing, Industrial & Logistics Engineering (SMILE). IEEE, 2019.
  • Y. Kong and D. Ni, “Qualitative and quantitative analysis of multi-pattern wafer bin maps,” IEEE Transactions on Semiconductor Manufacturing, vol. 33, pp. 578–586, 9 2020.

[Object Detection]

  • San Kim, Tae, et al. "Novel method for detection of mixed-type defect patterns in wafer maps based on a single shot detector algorithm." Journal of Intelligent Manufacturing (2021): 1-10.