div instruction should not set fcsr/DZ when dividing by zero

[FanShupei]

In rvemu, div/divu/divw/divuw instructions set DZ bit when dividing by zero.

The spec says "The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic instruction since the field was last reset by software", so I think fscr should not be modified by integer arithmetic instructions. This should be a bug.