LiteDRAM DDR3 Core targeting Arty AXI read data appears on the Native port instead.

[dinaabdelbaky]

Hi,
I have generated LiteDRAM core targeting DDR3 with the configuration in Fig1. I have noticed for a read command issued from the AXI interface the rd_data is returned in the rd_data of native interface, not the AXI interface Fig2

[Qiange516]

@dinaabdelbaky
Hello, can you read and write AXI_Litedram normally?
I encountered the same type of problem as #342 （Axi port write data error #342）
If it's convenient, leave an email （[email protected]）to communicate, thank you.