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cpuboard.cpp
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/*
* UAE - The Un*x Amiga Emulator
*
* Misc accelerator board special features
* Blizzard 1230 IV, 1240/1260, 2040/2060, PPC
* CyberStorm MK1, MK2, MK3, PPC.
* TekMagic
* Warp Engine
*
* Copyright 2014 Toni Wilen
*
*/
#include "sysconfig.h"
#include "sysdeps.h"
#include "options.h"
#include "memory.h"
#include "zfile.h"
#include "rommgr.h"
#include "autoconf.h"
#include "cpuboard.h"
#include "custom.h"
#include "newcpu.h"
#include "ncr_scsi.h"
#include "ncr9x_scsi.h"
#include "debug.h"
#include "flashrom.h"
#include "uae.h"
#include "uae/ppc.h"
#include "idecontrollers.h"
#include "scsi.h"
#define CPUBOARD_IO_LOG 0
#define CPUBOARD_IRQ_LOG 0
#define F0_WAITSTATES (2 * CYCLE_UNIT)
// CS MK3/PPC
#define CYBERSTORM_MAPROM_BASE 0xfff00000
#define CSIII_NCR 0xf40000
#define CSIII_BASE 0xf60000
#define CSIII_REG_RESET 0x00 // 0x00
#define CSIII_REG_IRQ 0x01 // 0x08
#define CSIII_REG_WAITSTATE 0x02 // 0x10
#define CSIII_REG_SHADOW 0x03 // 0x18
#define CSIII_REG_LOCK 0x04 // 0x20
#define CSIII_REG_INT 0x05 // 0x28
#define CSIII_REG_IPL_EMU 0x06 // 0x30
#define CSIII_REG_INT_LVL 0x07 // 0x38
// BPPC only
#define BPPC_MAPROM_ON 0x12
#define BPPC_MAPROM_OFF 0x13
#define BPPC_UNLOCK_FLASH 0x92
#define BPPC_LOCK_FLASH 0x93
#define BPPC_MAGIC_UNLOCK_VALUE 0x42
/* bit definitions */
#define P5_SET_CLEAR 0x80
/* REQ_RESET 0x00 */
// M68K can only reset PPC and vice versa
// if P5_SELF_RESET is not active.
#define P5_PPC_RESET 0x10
#define P5_M68K_RESET 0x08
#define P5_AMIGA_RESET 0x04
#define P5_AUX_RESET 0x02
#define P5_SCSI_RESET 0x01
/* REG_IRQ 0x08 */
#define P5_IRQ_SCSI 0x01
#define P5_IRQ_SCSI_EN 0x02
// 0x04
#define P5_IRQ_PPC_1 0x08
#define P5_IRQ_PPC_2 0x10
#define P5_IRQ_PPC_3 0x20 // MOS sets this bit
// 0x40 always cleared
/* REG_WAITSTATE 0x10 */
#define P5_PPC_WRITE 0x08
#define P5_PPC_READ 0x04
#define P5_M68K_WRITE 0x02
#define P5_M68K_READ 0x01
/* REG_SHADOW 0x18 */
#define P5_SELF_RESET 0x40
// 0x20
// 0x10
// 0x08 always set
#define P5_FLASH 0x04 // Flash writable (CSMK3,CSPPC only)
// 0x02 (can be modified even when locked)
#define P5_SHADOW 0x01 // KS MAP ROM
/* REG_LOCK 0x20. CSMK3,CSPPC only */
#define P5_MAGIC1 0x60 // REG_SHADOW and flash write protection unlock sequence
#define P5_MAGIC2 0x50
#define P5_MAGIC3 0x30
#define P5_MAGIC4 0x70
// when cleared, another CPU gets either stopped or can't access memory until set again.
#define P5_LOCK_CPU 0x01
/* REG_INT 0x28 */
// 0x40 always set
// 0x20
// 0x10 always set
// 0x08
// 0x04 // MOS sets this bit
#define P5_ENABLE_IPL 0x02
#define P5_INT_MASTER 0x01 // 1=m68k gets interrupts, 0=ppc gets interrupts.
/* IPL_EMU 0x30 */
#define P5_DISABLE_INT 0x40 // if set: all CPU interrupts disabled?
#define P5_M68K_IPL2 0x20
#define P5_M68K_IPL1 0x10
#define P5_M68K_IPL0 0x08
#define P5_M68k_IPL_MASK 0x38
#define P5_PPC_IPL2 0x04
#define P5_PPC_IPL1 0x02
#define P5_PPC_IPL0 0x01
#define P5_PPC_IPL_MASK 0x07
/* INT_LVL 0x38 */
#define P5_LVL7 0x40
#define P5_LVL6 0x20
#define P5_LVL5 0x10
#define P5_LVL4 0x08
#define P5_LVL3 0x04
#define P5_LVL2 0x02
#define P5_LVL1 0x01
#define CS_RAM_BASE 0x0c000000
#define BLIZZARD_RAM_BASE_48 0x48000000
#define BLIZZARD_RAM_BASE_68 0x68000000
#define BLIZZARD_RAM_256M_BASE_40 0x40000000
#define BLIZZARD_RAM_256M_BASE_70 0x70000000
#define BLIZZARD_MAPROM_BASE 0x4ff80000
#define BLIZZARD_MAPROM_ENABLE 0x80ffff00
#define BLIZZARD_BOARD_DISABLE 0x80fa0000
#define CSMK2_BOARD_DISABLE 0x83000000
static int cpuboard_size = -1, cpuboard2_size = -1;
static int configured;
static int blizzard_jit;
static int maprom_state;
static uae_u32 maprom_base;
static int delayed_rom_protect;
static int f0rom_size, earom_size;
static uae_u8 io_reg[64];
static void *flashrom;
static struct zfile *flashrom_file;
static int flash_unlocked;
static int csmk2_flashaddressing;
static bool blizzardmaprom_bank_mapped, blizzardmaprom2_bank_mapped;
static bool cpuboard_non_byte_ea;
static uae_u16 a2630_io;
static bool ppc_irq_pending;
static void set_ppc_interrupt(void)
{
if (ppc_irq_pending)
return;
uae_ppc_interrupt(true);
ppc_irq_pending = true;
}
static void clear_ppc_interrupt(void)
{
if (!ppc_irq_pending)
return;
uae_ppc_interrupt(false);
ppc_irq_pending = false;
}
static void check_ppc_int_lvl(void)
{
bool m68kint = (io_reg[CSIII_REG_INT] & P5_INT_MASTER) != 0;
bool active = (io_reg[CSIII_REG_IPL_EMU] & P5_DISABLE_INT) == 0;
bool iplemu = (io_reg[CSIII_REG_INT] & P5_ENABLE_IPL) == 0;
if (m68kint && iplemu && active) {
uae_u8 ppcipl = (~io_reg[CSIII_REG_IPL_EMU]) & P5_PPC_IPL_MASK;
if (ppcipl < 7) {
uae_u8 ilvl = (~io_reg[CSIII_REG_INT_LVL]) & 0x7f;
if (ilvl) {
for (int i = ppcipl; i < 7; i++) {
if (ilvl & (1 << i)) {
set_ppc_interrupt();
return;
}
}
}
}
clear_ppc_interrupt();
}
}
bool ppc_interrupt(int new_m68k_ipl)
{
bool m68kint = (io_reg[CSIII_REG_INT] & P5_INT_MASTER) != 0;
bool active = (io_reg[CSIII_REG_IPL_EMU] & P5_DISABLE_INT) == 0;
bool iplemu = (io_reg[CSIII_REG_INT] & P5_ENABLE_IPL) == 0;
if (!active)
return false;
if (!m68kint && iplemu && active) {
uae_u8 ppcipl = (~io_reg[CSIII_REG_IPL_EMU]) & P5_PPC_IPL_MASK;
if (new_m68k_ipl < 0)
new_m68k_ipl = 0;
io_reg[CSIII_REG_IPL_EMU] &= ~P5_M68k_IPL_MASK;
io_reg[CSIII_REG_IPL_EMU] |= (new_m68k_ipl << 3) ^ P5_M68k_IPL_MASK;
if (new_m68k_ipl > ppcipl) {
set_ppc_interrupt();
} else {
clear_ppc_interrupt();
}
}
return m68kint;
}
static bool is_blizzard(void)
{
return currprefs.cpuboard_type == BOARD_BLIZZARD_1230_IV || currprefs.cpuboard_type == BOARD_BLIZZARD_1260;
}
static bool is_blizzard2060(void)
{
return currprefs.cpuboard_type == BOARD_BLIZZARD_2060;
}
static bool is_csmk1(void)
{
return currprefs.cpuboard_type == BOARD_CSMK1;
}
static bool is_csmk2(void)
{
return currprefs.cpuboard_type == BOARD_CSMK2;
}
static bool is_csmk3(void)
{
return currprefs.cpuboard_type == BOARD_CSMK3 || currprefs.cpuboard_type == BOARD_CSPPC;
}
static bool is_blizzardppc(void)
{
return currprefs.cpuboard_type == BOARD_BLIZZARDPPC;
}
static bool is_ppc(void)
{
return currprefs.cpuboard_type == BOARD_BLIZZARDPPC || currprefs.cpuboard_type == BOARD_CSPPC;
}
static bool is_tekmagic(void)
{
return currprefs.cpuboard_type == BOARD_TEKMAGIC;
}
static bool is_a2630(void)
{
return currprefs.cpuboard_type == BOARD_A2630;
}
static bool is_dkb(void)
{
return currprefs.cpuboard_type == BOARD_DKB1200;
}
static bool is_fusionforty(void)
{
return currprefs.cpuboard_type == BOARD_FUSIONFORTY;
}
static bool is_apollo(void)
{
return currprefs.cpuboard_type == BOARD_APOLLO;
}
DECLARE_MEMORY_FUNCTIONS(blizzardio);
static addrbank blizzardio_bank = {
blizzardio_lget, blizzardio_wget, blizzardio_bget,
blizzardio_lput, blizzardio_wput, blizzardio_bput,
default_xlate, default_check, NULL, NULL, _T("CPUBoard IO"),
blizzardio_wget, blizzardio_bget, ABFLAG_IO
};
DECLARE_MEMORY_FUNCTIONS(blizzardram);
static addrbank blizzardram_bank = {
blizzardram_lget, blizzardram_wget, blizzardram_bget,
blizzardram_lput, blizzardram_wput, blizzardram_bput,
blizzardram_xlate, blizzardram_check, NULL, NULL, _T("CPUBoard RAM"),
blizzardram_lget, blizzardram_wget, ABFLAG_RAM | ABFLAG_THREADSAFE
};
DECLARE_MEMORY_FUNCTIONS(blizzardea);
static addrbank blizzardea_bank = {
blizzardea_lget, blizzardea_wget, blizzardea_bget,
blizzardea_lput, blizzardea_wput, blizzardea_bput,
blizzardea_xlate, blizzardea_check, NULL, _T("rom_ea"), _T("CPUBoard EA Autoconfig"),
blizzardea_lget, blizzardea_wget, ABFLAG_IO | ABFLAG_SAFE
};
DECLARE_MEMORY_FUNCTIONS(blizzarde8);
static addrbank blizzarde8_bank = {
blizzarde8_lget, blizzarde8_wget, blizzarde8_bget,
blizzarde8_lput, blizzarde8_wput, blizzarde8_bput,
blizzarde8_xlate, blizzarde8_check, NULL, NULL, _T("CPUBoard E8 Autoconfig"),
blizzarde8_lget, blizzarde8_wget, ABFLAG_IO | ABFLAG_SAFE
};
DECLARE_MEMORY_FUNCTIONS(blizzardf0);
static addrbank blizzardf0_bank = {
blizzardf0_lget, blizzardf0_wget, blizzardf0_bget,
blizzardf0_lput, blizzardf0_wput, blizzardf0_bput,
blizzardf0_xlate, blizzardf0_check, NULL, _T("rom_f0_ppc"), _T("CPUBoard F00000"),
blizzardf0_lget, blizzardf0_wget, ABFLAG_ROM
};
DECLARE_MEMORY_FUNCTIONS(blizzardram_nojit);
static addrbank blizzardram_nojit_bank = {
blizzardram_nojit_lget, blizzardram_nojit_wget, blizzardram_nojit_bget,
blizzardram_nojit_lput, blizzardram_nojit_wput, blizzardram_nojit_bput,
blizzardram_nojit_xlate, blizzardram_nojit_check, NULL, NULL, _T("CPUBoard RAM"),
blizzardram_nojit_lget, blizzardram_nojit_wget, ABFLAG_RAM | ABFLAG_THREADSAFE
};
DECLARE_MEMORY_FUNCTIONS(blizzardmaprom);
static addrbank blizzardmaprom_bank = {
blizzardmaprom_lget, blizzardmaprom_wget, blizzardmaprom_bget,
blizzardmaprom_lput, blizzardmaprom_wput, blizzardmaprom_bput,
blizzardmaprom_xlate, blizzardmaprom_check, NULL, _T("maprom"), _T("CPUBoard MAPROM"),
blizzardmaprom_lget, blizzardmaprom_wget, ABFLAG_RAM
};
DECLARE_MEMORY_FUNCTIONS(blizzardmaprom2);
static addrbank blizzardmaprom2_bank = {
blizzardmaprom2_lget, blizzardmaprom2_wget, blizzardmaprom2_bget,
blizzardmaprom2_lput, blizzardmaprom2_wput, blizzardmaprom2_bput,
blizzardmaprom2_xlate, blizzardmaprom2_check, NULL, _T("maprom2"), _T("CPUBoard MAPROM2"),
blizzardmaprom2_lget, blizzardmaprom2_wget, ABFLAG_RAM
};
// hack to map F41000 SCSI SCRIPTS RAM to JIT friendly address
void cyberstorm_scsi_ram_put(uaecptr addr, uae_u32 v)
{
addr &= 0xffff;
addr += (CSIII_NCR & 0x7ffff);
blizzardf0_bank.baseaddr[addr] = v;
}
uae_u32 cyberstorm_scsi_ram_get(uaecptr addr)
{
uae_u32 v;
addr &= 0xffff;
addr += (CSIII_NCR & 0x7ffff);
v = blizzardf0_bank.baseaddr[addr];
return v;
}
uae_u8 *REGPARAM2 cyberstorm_scsi_ram_xlate(uaecptr addr)
{
addr &= 0xffff;
addr += (CSIII_NCR & 0x7ffff);
return blizzardf0_bank.baseaddr + addr;
}
int REGPARAM2 cyberstorm_scsi_ram_check(uaecptr a, uae_u32 b)
{
a &= 0xffff;
return a >= 0x1000 && a + b < 0x3000;
}
MEMORY_FUNCTIONS(blizzardram);
MEMORY_BGET(blizzardram_nojit, 1);
MEMORY_WGET(blizzardram_nojit, 1);
MEMORY_LGET(blizzardram_nojit, 1);
MEMORY_CHECK(blizzardram_nojit);
MEMORY_XLATE(blizzardram_nojit);
static void REGPARAM2 blizzardram_nojit_lput(uaecptr addr, uae_u32 l)
{
uae_u32 *m;
#ifdef JIT
special_mem |= S_WRITE;
#endif
addr &= blizzardram_nojit_bank.mask;
if (maprom_state && addr >= maprom_base)
return;
m = (uae_u32 *)(blizzardram_nojit_bank.baseaddr + addr);
do_put_mem_long(m, l);
}
static void REGPARAM2 blizzardram_nojit_wput(uaecptr addr, uae_u32 w)
{
uae_u16 *m;
#ifdef JIT
special_mem |= S_WRITE;
#endif
addr &= blizzardram_nojit_bank.mask;
if (maprom_state && addr >= maprom_base)
return;
m = (uae_u16 *)(blizzardram_nojit_bank.baseaddr + addr);
do_put_mem_word(m, w);
}
static void REGPARAM2 blizzardram_nojit_bput(uaecptr addr, uae_u32 b)
{
#ifdef JIT
special_mem |= S_WRITE;
#endif
addr &= blizzardram_nojit_bank.mask;
if (maprom_state && addr >= maprom_base)
return;
blizzardram_nojit_bank.baseaddr[addr] = b;
}
static void no_rom_protect(void)
{
if (delayed_rom_protect)
return;
delayed_rom_protect = 10;
protect_roms(false);
}
MEMORY_BGET(blizzardmaprom2, 1);
MEMORY_WGET(blizzardmaprom2, 1);
MEMORY_LGET(blizzardmaprom2, 1);
MEMORY_BPUT(blizzardmaprom2, 1);
MEMORY_WPUT(blizzardmaprom2, 1);
MEMORY_LPUT(blizzardmaprom2, 1);
MEMORY_CHECK(blizzardmaprom2);
MEMORY_XLATE(blizzardmaprom2);
MEMORY_BGET(blizzardmaprom, 1);
MEMORY_WGET(blizzardmaprom, 1);
MEMORY_LGET(blizzardmaprom, 1);
MEMORY_CHECK(blizzardmaprom);
MEMORY_XLATE(blizzardmaprom);
static void REGPARAM2 blizzardmaprom_lput(uaecptr addr, uae_u32 l)
{
uae_u32 *m;
#ifdef JIT
special_mem |= S_WRITE;
#endif
if (is_blizzard2060() && !maprom_state)
return;
addr &= blizzardmaprom_bank.mask;
m = (uae_u32 *)(blizzardmaprom_bank.baseaddr + addr);
do_put_mem_long(m, l);
if (maprom_state && !(addr & 0x80000)) {
no_rom_protect();
m = (uae_u32 *)(kickmem_bank.baseaddr + addr);
do_put_mem_long(m, l);
}
}
static void REGPARAM2 blizzardmaprom_wput(uaecptr addr, uae_u32 w)
{
uae_u16 *m;
#ifdef JIT
special_mem |= S_WRITE;
#endif
if (is_blizzard2060() && !maprom_state)
return;
addr &= blizzardmaprom_bank.mask;
m = (uae_u16 *)(blizzardmaprom_bank.baseaddr + addr);
do_put_mem_word(m, w);
if (maprom_state && !(addr & 0x80000)) {
no_rom_protect();
m = (uae_u16 *)(kickmem_bank.baseaddr + addr);
do_put_mem_word(m, w);
}
}
static void REGPARAM2 blizzardmaprom_bput(uaecptr addr, uae_u32 b)
{
#ifdef JIT
special_mem |= S_WRITE;
#endif
if (is_blizzard2060() && !maprom_state)
return;
addr &= blizzardmaprom_bank.mask;
blizzardmaprom_bank.baseaddr[addr] = b;
if (maprom_state && !(addr & 0x80000)) {
no_rom_protect();
kickmem_bank.baseaddr[addr] = b;
}
}
MEMORY_CHECK(blizzardea);
MEMORY_XLATE(blizzardea);
static void blizzardf0_slow(int size)
{
if (is_blizzard() || is_blizzardppc() || is_blizzard2060()) {
if (size == 4)
regs.memory_waitstate_cycles += F0_WAITSTATES * 6;
else if (size == 2)
regs.memory_waitstate_cycles += F0_WAITSTATES * 3;
else
regs.memory_waitstate_cycles += F0_WAITSTATES * 1;
}
}
static int REGPARAM2 blizzarde8_check(uaecptr addr, uae_u32 size)
{
return 0;
}
static uae_u8 *REGPARAM2 blizzarde8_xlate(uaecptr addr)
{
return NULL;
}
static uae_u32 REGPARAM2 blizzardf0_lget(uaecptr addr)
{
#ifdef JIT
special_mem |= S_READ;
#endif
uae_u32 *m;
//write_log(_T("F0 LONGGET %08x\n"), addr);
blizzardf0_slow(4);
addr &= blizzardf0_bank.mask;
m = (uae_u32 *)(blizzardf0_bank.baseaddr + addr);
return do_get_mem_long(m);
}
static uae_u32 REGPARAM2 blizzardf0_wget(uaecptr addr)
{
#ifdef JIT
special_mem |= S_READ;
#endif
uae_u16 *m, v;
blizzardf0_slow(2);
addr &= blizzardf0_bank.mask;
m = (uae_u16 *)(blizzardf0_bank.baseaddr + addr);
v = do_get_mem_word(m);
return v;
}
static uae_u32 REGPARAM2 blizzardf0_bget(uaecptr addr)
{
#ifdef JIT
special_mem |= S_READ;
#endif
uae_u8 v;
blizzardf0_slow(1);
if (is_csmk3() || is_blizzardppc()) {
if (flash_unlocked) {
return flash_read(flashrom, addr);
}
} else if (is_csmk2()) {
addr &= 65535;
addr += 65536;
return flash_read(flashrom, addr);
} else if (is_csmk1()) {
addr &= 65535;
addr += 65536;
return flash_read(flashrom, addr);
}
addr &= blizzardf0_bank.mask;
v = blizzardf0_bank.baseaddr[addr];
return v;
}
static void REGPARAM2 blizzardf0_lput(uaecptr addr, uae_u32 b)
{
#ifdef JIT
special_mem |= S_WRITE;
#endif
blizzardf0_slow(4);
}
static void REGPARAM2 blizzardf0_wput(uaecptr addr, uae_u32 b)
{
#ifdef JIT
special_mem |= S_WRITE;
#endif
blizzardf0_slow(2);
}
static void REGPARAM2 blizzardf0_bput(uaecptr addr, uae_u32 b)
{
#ifdef JIT
special_mem |= S_WRITE;
#endif
blizzardf0_slow(1);
if (is_csmk3() || is_blizzardppc()) {
if (flash_unlocked) {
flash_write(flashrom, addr, b);
}
} else if (is_csmk2()) {
addr &= 65535;
addr += 65536;
addr &= ~3;
addr |= csmk2_flashaddressing;
flash_write(flashrom, addr, b);
} else if (is_csmk1()) {
addr &= 65535;
addr += 65536;
flash_write(flashrom, addr, b);
}
}
MEMORY_CHECK(blizzardf0);
MEMORY_XLATE(blizzardf0);
static uae_u32 REGPARAM2 blizzardea_lget(uaecptr addr)
{
#ifdef JIT
special_mem |= S_READ;
#endif
uae_u32 v = 0;
if (cpuboard_non_byte_ea) {
v = blizzardea_bget(addr + 3) << 0;
v |= blizzardea_bget(addr + 2) << 8;
v |= blizzardea_bget(addr + 1) << 16;
v |= blizzardea_bget(addr + 0) << 24;
}
return v;
}
static uae_u32 REGPARAM2 blizzardea_wget(uaecptr addr)
{
#ifdef JIT
special_mem |= S_READ;
#endif
uae_u32 v = 0;
if (cpuboard_non_byte_ea) {
v = blizzardea_bget(addr + 1) << 0;
v |= blizzardea_bget(addr + 0) << 8;
}
return v;
}
static uae_u32 REGPARAM2 blizzardea_bget(uaecptr addr)
{
#ifdef JIT
special_mem |= S_READ;
#endif
uae_u8 v;
addr &= blizzardea_bank.mask;
if (is_tekmagic()) {
cpuboard_non_byte_ea = true;
v = cpuboard_ncr710_io_bget(addr);
} else if (is_blizzard2060() && addr >= BLIZZARD_2060_SCSI_OFFSET) {
v = cpuboard_ncr9x_scsi_get(addr);
} else if (currprefs.cpuboard_type == BOARD_BLIZZARD_1230_IV || currprefs.cpuboard_type == BOARD_BLIZZARD_1260) {
if (addr & BLIZZARD_SCSI_KIT_SCSI_OFFSET)
v = cpuboard_ncr9x_scsi_get(addr);
else
v = blizzardea_bank.baseaddr[addr];
} else if (is_csmk1()) {
if (addr >= CYBERSTORM_MK1_SCSI_OFFSET) {
v = cpuboard_ncr9x_scsi_get(addr);
} else if (flash_active(flashrom, addr)) {
v = flash_read(flashrom, addr);
} else {
v = blizzardea_bank.baseaddr[addr];
}
} else if (is_csmk2()) {
if (addr >= CYBERSTORM_MK2_SCSI_OFFSET) {
v = cpuboard_ncr9x_scsi_get(addr);
} else if (flash_active(flashrom, addr)) {
v = flash_read(flashrom, addr);
} else {
v = blizzardea_bank.baseaddr[addr];
}
} else {
v = blizzardea_bank.baseaddr[addr];
}
return v;
}
static void REGPARAM2 blizzardea_lput(uaecptr addr, uae_u32 l)
{
#ifdef JIT
special_mem |= S_WRITE;
#endif
if (cpuboard_non_byte_ea) {
blizzardea_bput(addr + 3, l >> 0);
blizzardea_bput(addr + 2, l >> 8);
blizzardea_bput(addr + 1, l >> 16);
blizzardea_bput(addr + 0, l >> 24);
}
}
static void REGPARAM2 blizzardea_wput(uaecptr addr, uae_u32 w)
{
#ifdef JIT
special_mem |= S_WRITE;
#endif
if (cpuboard_non_byte_ea) {
blizzardea_bput(addr + 1, w >> 0);
blizzardea_bput(addr + 0, w >> 8);
}
}
static void REGPARAM2 blizzardea_bput(uaecptr addr, uae_u32 b)
{
#ifdef JIT
special_mem |= S_WRITE;
#endif
addr &= blizzardea_bank.mask;
if (is_tekmagic()) {
cpuboard_non_byte_ea = true;
cpuboard_ncr710_io_bput(addr, b);
} else if (is_blizzard2060() && addr >= BLIZZARD_2060_SCSI_OFFSET) {
cpuboard_ncr9x_scsi_put(addr, b);
} else if ((currprefs.cpuboard_type == BOARD_BLIZZARD_1230_IV || currprefs.cpuboard_type == BOARD_BLIZZARD_1260) && addr >= BLIZZARD_SCSI_KIT_SCSI_OFFSET) {
cpuboard_ncr9x_scsi_put(addr, b);
} else if (is_csmk1()) {
if (addr >= CYBERSTORM_MK1_SCSI_OFFSET) {
cpuboard_ncr9x_scsi_put(addr, b);
} else {
flash_write(flashrom, addr, b);
}
} else if (is_csmk2()) {
if (addr >= CYBERSTORM_MK2_SCSI_OFFSET) {
cpuboard_ncr9x_scsi_put(addr, b);
} else {
addr &= ~3;
addr |= csmk2_flashaddressing;
flash_write(flashrom, addr, b);
}
}
}
static void REGPARAM2 blizzarde8_lput(uaecptr addr, uae_u32 b)
{
#ifdef JIT
special_mem |= S_WRITE;
#endif
}
static void REGPARAM2 blizzarde8_wput(uaecptr addr, uae_u32 b)
{
#ifdef JIT
special_mem |= S_WRITE;
#endif
if (is_a2630()) {
addr &= 65535;
if (addr == 0x0040) {
write_log(_T("A2630 write %04x PC=%08x\n"), b, M68K_GETPC);
a2630_io = b;
// bit 0: unmap 0x000000
// bit 1: unmap 0xf80000
if (b & 2) {
map_banks(&kickmem_bank, 0xf80000 >> 16, 131072 >> 16, 0);
write_log(_T("A2630 boot rom unmapped\n"));
}
// bit 2: autoconfig region enable
if (b & 4) {
write_log(_T("A2630 Autoconfig enabled\n"));
expamem_next(NULL, NULL);
}
// bit 3: unknown
// bit 4: 68000 mode
if (b & 0x10) {
write_log(_T("A2630 68000 mode!\n"));
cpu_halt(4);
}
}
}
}
static void REGPARAM2 blizzarde8_bput(uaecptr addr, uae_u32 b)
{
#ifdef JIT
special_mem |= S_WRITE;
#endif
b &= 0xff;
addr &= 65535;
if (addr == 0x48 && !configured) {
map_banks(&blizzardea_bank, b, 0x20000 >> 16, 0x20000);
write_log(_T("Accelerator Z2 board autoconfigured at %02X0000\n"), b);
configured = 1;
expamem_next (&blizzardea_bank, NULL);
return;
}
if (addr == 0x4c && !configured) {
write_log(_T("Blizzard Z2 SHUT-UP!\n"));
configured = 1;
expamem_next (NULL, NULL);
return;
}
}
static uae_u32 REGPARAM2 blizzarde8_bget(uaecptr addr)
{
uae_u32 v = 0xffff;
#ifdef JIT
special_mem |= S_READ;
#endif
v = blizzardea_bank.baseaddr[addr & blizzardea_bank.mask];
return v;
}
static uae_u32 REGPARAM2 blizzarde8_wget(uaecptr addr)
{
uae_u32 v = 0xffff;
#ifdef JIT
special_mem |= S_READ;
#endif
v = (blizzardea_bank.baseaddr[addr & blizzardea_bank.mask] << 8) | blizzardea_bank.baseaddr[(addr + 1) & blizzardea_bank.mask];
return v;
}
static uae_u32 REGPARAM2 blizzarde8_lget(uaecptr addr)
{
uae_u32 v = 0xffff;
#ifdef JIT
special_mem |= S_READ;
#endif
v = (blizzarde8_wget(addr) << 16) | blizzarde8_wget(addr + 2);
return v;
}
static void blizzard_copymaprom(void)
{
if (!maprom_state) {
reload_roms();
} else {
uae_u8 *src = get_real_address(BLIZZARD_MAPROM_BASE);
if (src) {
uae_u8 *dst = kickmem_bank.baseaddr;
protect_roms(false);
memcpy(dst, src, 524288);
protect_roms(true);
set_roms_modified();
}
}
}
static void cyberstorm_copymaprom(void)
{
if (!maprom_state) {
reload_roms();
} else if (blizzardmaprom_bank.baseaddr) {
uae_u8 *src = blizzardmaprom_bank.baseaddr;
uae_u8 *dst = kickmem_bank.baseaddr;
protect_roms(false);
memcpy(dst, src, 524288);
protect_roms(true);
set_roms_modified();
}
}
static void cyberstormmk2_copymaprom(void)
{
if (blizzardmaprom_bank.baseaddr) {
uae_u8 *src = a3000hmem_bank.baseaddr + a3000hmem_bank.allocated - 524288;
uae_u8 *dst = kickmem_bank.baseaddr;
protect_roms(false);
memcpy(dst, src, 524288);
protect_roms(true);
set_roms_modified();
}
}
static void cyberstormmk1_copymaprom(void)
{
if (blizzardmaprom_bank.baseaddr) {
uae_u8 *src = blizzardmaprom_bank.baseaddr;
uae_u8 *dst = kickmem_bank.baseaddr;
protect_roms(false);
memcpy(dst, src, 524288);
protect_roms(true);
set_roms_modified();
}
}
void cpuboard_rethink(void)
{
if (is_csmk3() || is_blizzardppc()) {
if (!(io_reg[CSIII_REG_IRQ] & (P5_IRQ_SCSI_EN | P5_IRQ_SCSI))) {
INTREQ_0(0x8000 | 0x0008);
} else if (!(io_reg[CSIII_REG_IRQ] & (P5_IRQ_PPC_1 | P5_IRQ_PPC_2))) {
INTREQ_0(0x8000 | 0x0008);
}
check_ppc_int_lvl();
ppc_interrupt(intlev());
}
}
static void blizzardppc_maprom(void)
{
if (cpuboard_size <= 2 * 524288)
return;
if (maprom_state) {
map_banks(&blizzardmaprom2_bank, CYBERSTORM_MAPROM_BASE >> 16, 524288 >> 16, 0);
} else {
map_banks(&blizzardmaprom_bank, CYBERSTORM_MAPROM_BASE >> 16, 524288 >> 16, 0);
}
}
static void cyberstorm_maprom(void)
{
if (a3000hmem_bank.allocated <= 2 * 524288)
return;
if (maprom_state && is_ppc())
map_banks(&blizzardmaprom2_bank, CYBERSTORM_MAPROM_BASE >> 16, 524288 >> 16, 0);
else
map_banks(&blizzardmaprom_bank, CYBERSTORM_MAPROM_BASE >> 16, 524288 >> 16, 0);
}
static void cyberstormmk2_maprom(void)
{
if (maprom_state)
map_banks_nojitdirect(&blizzardmaprom_bank, blizzardmaprom_bank.start >> 16, 524288 >> 16, 0);
}
void cyberstorm_irq(int level)
{
if (level)
io_reg[CSIII_REG_IRQ] &= ~P5_IRQ_SCSI;
else
io_reg[CSIII_REG_IRQ] |= P5_IRQ_SCSI;
cpuboard_rethink();
}
void blizzardppc_irq(int level)
{
if (level)
io_reg[CSIII_REG_IRQ] &= ~P5_IRQ_SCSI;
else
io_reg[CSIII_REG_IRQ] |= P5_IRQ_SCSI;
cpuboard_rethink();
}
static uae_u32 REGPARAM2 blizzardio_bget(uaecptr addr)
{
uae_u8 v = 0;
#ifdef JIT
special_mem |= S_READ;
#endif
//write_log(_T("CS IO XBGET %08x=%02X PC=%08x\n"), addr, v & 0xff, M68K_GETPC);
if (is_csmk3() || is_blizzardppc()) {
uae_u32 bank = addr & 0x10000;
if (bank == 0) {
int reg = (addr & 0xff) / 8;
v = io_reg[reg];
if (reg == CSIII_REG_LOCK) {
v &= 0x01;
v |= 0x10;
if (is_blizzardppc())
v |= 0x08; // BPPC identification
} else if (reg == CSIII_REG_IRQ) {
v &= 0x3f;
} else if (reg == CSIII_REG_INT) {
v |= 0x40 | 0x10;
} else if (reg == CSIII_REG_SHADOW) {
v |= 0x08;
} else if (reg == CSIII_REG_RESET) {
v &= 0x1f;
} else if (reg == CSIII_REG_IPL_EMU) {
// PPC not master: m68k IPL = all ones
if (io_reg[CSIII_REG_INT] & P5_INT_MASTER)
v |= P5_M68k_IPL_MASK;
}
#if CPUBOARD_IO_LOG > 0
if (reg != CSIII_REG_IRQ || CPUBOARD_IO_LOG > 2)
write_log(_T("CS IO BGET %08x=%02X PC=%08x\n"), addr, v & 0xff, M68K_GETPC);
#endif
} else {
#if CPUBOARD_IO_LOG > 0
write_log(_T("CS IO BGET %08x=%02X PC=%08x\n"), addr, v & 0xff, M68K_GETPC);
#endif
}
}
return v;
}
static uae_u32 REGPARAM2 blizzardio_wget(uaecptr addr)
{
#ifdef JIT
special_mem |= S_READ;
#endif
if (is_csmk3() || is_blizzardppc()) {
;//write_log(_T("CS IO WGET %08x\n"), addr);
//activate_debugger();
}
return 0;
}
static uae_u32 REGPARAM2 blizzardio_lget(uaecptr addr)
{
#ifdef JIT
special_mem |= S_READ;
#endif
write_log(_T("CS IO LGET %08x PC=%08x\n"), addr, M68K_GETPC);
if (is_blizzard2060() && currprefs.maprom) {
if (addr & 0x10000000) {
maprom_state = 0;
} else {
maprom_state = 1;
}
}
return 0;
}
static void REGPARAM2 blizzardio_bput(uaecptr addr, uae_u32 v)
{
#ifdef JIT
special_mem |= S_WRITE;
#endif
#if CPUBOARD_IO_LOG > 1
write_log(_T("CS IO XBPUT %08x %02x PC=%08x\n"), addr, v & 0xff, M68K_GETPC);
#endif
if (is_fusionforty()) {
;
} else if (is_csmk2()) {
csmk2_flashaddressing = addr & 3;
if (addr == 0x880000e3 && v == 0x2a) {
maprom_state = 1;
write_log(_T("CSMKII: MAPROM enabled\n"));
cyberstormmk2_copymaprom();
}