Assertion `range.low == range.high' failed: do not support bus yet

[c01dwater]

Dear Prof. @limbo018. When I use DreamPlace to place a netlist synthesized by DC, the following error is reported:

Verilog file：

I tried “set flatten_array” from DC, but it doesn't work.
How did this error occur? What can I do to solve this problem?

[limbo018]

Can you provide a sample case? Currently the database does not support to build bus, but it should not be easy to fix it.

[limbo018]

Hi, I cannot find any uploaded files. You may need to upload through github website.

[c01dwater]

mapped.v.zip

Hi, I cannot find any uploaded files. You may need to upload through GitHub website.
Dear Prof. @limbo018. Here is our Verilog file. I appreciate your help.

[limbo018]

Can you provide the full case with lef, def, and verilog? I cannot run with only verilog.

[limbo018]

Dear Prof. @limbo018. When I use DreamPlace to place a netlist synthesized by DC, the following error is reported:

Verilog file： 

I tried “set flatten_array” from DC, but it doesn't work. How did this error occur? What can I do to solve this problem?

The verilog file you provided does not contain such bus syntax.

[c01dwater]

Dear Prof. @limbo018. Do you know if this error is related to the def file? Because I noticed that my def file is a previous version.
aes128.zip

[limbo018]

Your def file does not match your verilog file. I need consistent files for one design to reproduce the issue you reported.