diff --git a/targets/ice40_hx8k_b_evn/base.py b/targets/ice40_hx8k_b_evn/base.py index 3323afc6a..9b7c86002 100644 --- a/targets/ice40_hx8k_b_evn/base.py +++ b/targets/ice40_hx8k_b_evn/base.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 import sys import struct import os.path @@ -15,7 +16,7 @@ from targets.utils import csr_map_update -from litex.soc.cores.uart import UARTWishboneBridge +from litex.soc.cores.uart import UARTWishboneBridge class _CRG(Module): def __init__(self, platform): @@ -44,19 +45,10 @@ def __init__(self, platform): class BaseSoC(SoCCore): - csr_peripherals = ( - "spiflash", - "cas", - ) - csr_map_update(SoCCore.csr_map, csr_peripherals) - - mem_map_overlay = { + mem_map = {**SoCSDRAM.mem_map, **{ "spiflash": 0x20000000, # (default shadow @0xa0000000) "sram": 0, - } - mem_map = dict(SoCCore.mem_map, **mem_map_overlay) - - #mem_map.update(SoCCore.mem_map) + }} def __init__(self, platform, **kwargs): if 'integrated_rom_size' not in kwargs: