From 6053936e349717b9d6c97d92b968f6cb8c89dc5d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E7=83=9F=E9=9B=A8=E6=9D=BE=20Yan=20Yusong?=
 <75596608+Jasonyanyusong@users.noreply.github.com>
Date: Tue, 19 Mar 2024 14:55:09 -0700
Subject: [PATCH] Update baseline.md

---
 src/2306/baseline/baseline.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/2306/baseline/baseline.md b/src/2306/baseline/baseline.md
index 072297e..b720125 100644
--- a/src/2306/baseline/baseline.md
+++ b/src/2306/baseline/baseline.md
@@ -15,7 +15,7 @@ In addition to DiffTest, you will also implement a simple debugger and various t
 These infrastructures will accompany you throughout the "One Student One Chip":
 Even in stages A and S, you will find that they can still greatly improve debugging efficiency;
 What's more? Without these infrastructures, you will have to pay a huge price if you want to survive the S stage.
-1. Design an RV32E single-cycle processor.
+1. Implement an RV32E single-cycle processor.
 But you will first implement an RV32IM (yes, RV32IM) simulator.
 Understand the behavior of RISC-V instructions and programs without considering RTL implementation details,
 Then apply these understandings to the real processor implemented in RTL.