From 3699526260cce24ee105812832878f503d67a279 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Mon, 19 Feb 2024 16:25:48 +0800 Subject: [PATCH 01/20] Add functional coverage exclusion files - assert, directive and interrupt Signed-off-by: dd-baoshan --- ...cv32e40pv2_func_asrt_n_directive_waiver.do | 2 ++ .../cv32e40pv2_func_uvme_interrupt_waiver.do | 36 +++++++++++++++++++ .../tools/vsim/exclusion/pulp/exclusion.do | 6 ++++ .../vsim/exclusion/pulp_fpu/exclusion.do | 6 ++++ 4 files changed, 50 insertions(+) create mode 100644 cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_func_asrt_n_directive_waiver.do create mode 100644 cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_func_uvme_interrupt_waiver.do create mode 100644 cv32e40p/sim/tools/vsim/exclusion/pulp/exclusion.do create mode 100644 cv32e40p/sim/tools/vsim/exclusion/pulp_fpu/exclusion.do diff --git a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_func_asrt_n_directive_waiver.do b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_func_asrt_n_directive_waiver.do new file mode 100644 index 0000000000..432dbe196c --- /dev/null +++ b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_func_asrt_n_directive_waiver.do @@ -0,0 +1,2 @@ +coverage exclude -assertpath /uvmt_cv32e40p_tb/dut_wrap/obi_instr_memory_assert_i/u_assert/a_be_not_zero -comment {dut instr obi interface is for read only transfer} +coverage exclude -assertpath /uvmt_cv32e40p_tb/dut_wrap/obi_instr_memory_assert_i/u_assert/a_be_contiguous -comment {dut instr obi interface is for read only transfer} diff --git a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_func_uvme_interrupt_waiver.do b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_func_uvme_interrupt_waiver.do new file mode 100644 index 0000000000..62b44a073d --- /dev/null +++ b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_func_uvme_interrupt_waiver.do @@ -0,0 +1,36 @@ +# cg_wfi_entry +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_entry/cp_insn_list/cv_starti0 -comment {exclude wfi coverage for hwloop usecase} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_entry/cp_insn_list/cv_start0 -comment {exclude wfi coverage for hwloop usecase} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_entry/cp_insn_list/cv_endi0 -comment {exclude wfi coverage for hwloop usecase} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_entry/cp_insn_list/cv_end0 -comment {exclude wfi coverage for hwloop usecase} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_entry/cp_insn_list/cv_counti0 -comment {exclude wfi coverage for hwloop usecase} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_entry/cp_insn_list/cv_count0 -comment {exclude wfi coverage for hwloop usecase} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_entry/cp_insn_list/cv_setupi0 -comment {exclude wfi coverage for hwloop usecase} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_entry/cp_insn_list/cv_setup0 -comment {exclude wfi coverage for hwloop usecase} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_entry/cp_insn_list/cv_starti1 -comment {exclude wfi coverage for hwloop usecase} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_entry/cp_insn_list/cv_start1 -comment {exclude wfi coverage for hwloop usecase} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_entry/cp_insn_list/cv_endi1 -comment {exclude wfi coverage for hwloop usecase} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_entry/cp_insn_list/cv_end1 -comment {exclude wfi coverage for hwloop usecase} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_entry/cp_insn_list/cv_counti1 -comment {exclude wfi coverage for hwloop usecase} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_entry/cp_insn_list/cv_count1 -comment {exclude wfi coverage for hwloop usecase} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_entry/cp_insn_list/cv_setupi1 -comment {exclude wfi coverage for hwloop usecase} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_entry/cp_insn_list/cv_setup1 -comment {exclude wfi coverage for hwloop usecase} + +# cg_wfi_exit +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_exit/cp_insn_list/cv_starti0 -comment {exclude wfi coverage for hwloop usecase} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_exit/cp_insn_list/cv_start0 -comment {exclude wfi coverage for hwloop usecase} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_exit/cp_insn_list/cv_endi0 -comment {exclude wfi coverage for hwloop usecase} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_exit/cp_insn_list/cv_end0 -comment {exclude wfi coverage for hwloop usecase} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_exit/cp_insn_list/cv_counti0 -comment {exclude wfi coverage for hwloop usecase} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_exit/cp_insn_list/cv_count0 -comment {exclude wfi coverage for hwloop usecase} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_exit/cp_insn_list/cv_setupi0 -comment {exclude wfi coverage for hwloop usecase} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_exit/cp_insn_list/cv_setup0 -comment {exclude wfi coverage for hwloop usecase} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_exit/cp_insn_list/cv_starti1 -comment {exclude wfi coverage for hwloop usecase} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_exit/cp_insn_list/cv_start1 -comment {exclude wfi coverage for hwloop usecase} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_exit/cp_insn_list/cv_endi1 -comment {exclude wfi coverage for hwloop usecase} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_exit/cp_insn_list/cv_end1 -comment {exclude wfi coverage for hwloop usecase} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_exit/cp_insn_list/cv_counti1 -comment {exclude wfi coverage for hwloop usecase} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_exit/cp_insn_list/cv_count1 -comment {exclude wfi coverage for hwloop usecase} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_exit/cp_insn_list/cv_setupi1 -comment {exclude wfi coverage for hwloop usecase} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_exit/cp_insn_list/cv_setup1 -comment {exclude wfi coverage for hwloop usecase} + diff --git a/cv32e40p/sim/tools/vsim/exclusion/pulp/exclusion.do b/cv32e40p/sim/tools/vsim/exclusion/pulp/exclusion.do new file mode 100644 index 0000000000..0b88992b82 --- /dev/null +++ b/cv32e40p/sim/tools/vsim/exclusion/pulp/exclusion.do @@ -0,0 +1,6 @@ +# functional : assertion and directive +do ../cv32e40pv2_func_asrt_n_directive_waiver.do + +# functional: uvme_interrupt_covg_v2 +do ../cv32e40pv2_func_uvme_interrupt_waiver.do + diff --git a/cv32e40p/sim/tools/vsim/exclusion/pulp_fpu/exclusion.do b/cv32e40p/sim/tools/vsim/exclusion/pulp_fpu/exclusion.do new file mode 100644 index 0000000000..0b88992b82 --- /dev/null +++ b/cv32e40p/sim/tools/vsim/exclusion/pulp_fpu/exclusion.do @@ -0,0 +1,6 @@ +# functional : assertion and directive +do ../cv32e40pv2_func_asrt_n_directive_waiver.do + +# functional: uvme_interrupt_covg_v2 +do ../cv32e40pv2_func_uvme_interrupt_waiver.do + From ee1e1a910202ea4100625558d5618b41e18d6960 Mon Sep 17 00:00:00 2001 From: Bee Nee Lim Date: Tue, 20 Feb 2024 16:38:35 +0800 Subject: [PATCH 02/20] Add code coverage exclusion file - common for all cfg and pulp cfg specific. Signed-off-by: Bee Nee Lim --- cv32e40p/sim/tools/vsim/exclusion/README | 47 +++++ .../cv32e40pv2_code_all_cfg_waiver.do | 184 ++++++++++++++++++ .../cv32e40pv2_code_pulp_cfg_waiver.do | 59 ++++++ .../tools/vsim/exclusion/pulp/exclusion.do | 5 + .../vsim/exclusion/pulp_fpu/exclusion.do | 2 + 5 files changed, 297 insertions(+) create mode 100644 cv32e40p/sim/tools/vsim/exclusion/README create mode 100644 cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do create mode 100644 cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_pulp_cfg_waiver.do diff --git a/cv32e40p/sim/tools/vsim/exclusion/README b/cv32e40p/sim/tools/vsim/exclusion/README new file mode 100644 index 0000000000..972ad4d00c --- /dev/null +++ b/cv32e40p/sim/tools/vsim/exclusion/README @@ -0,0 +1,47 @@ +This directory contains waiver files for cv32e40p v2 verification. +Tool specific: Visualizer. + +---------------------------------------------------- +Filenames are in following format for easy reference: +cv32e40pv2___waiver.do +---------------------------------------------------- + +e.g. +1. for RTL code coverage waiver + + cv32e40pv2_code_all_cfg_waiver.do : code coverage waiver common to all configurations. + cv32e40pv2_code_pulp_cfg_waiver.do : additional code coverage waiver applicable to pulp config only. + +2. For function coverage waiver + + cv32e40pv2_func_asrt_n_directive_waiver.do : func coverage waiver related to assert & directive. + cv32e40pv2_func_uvme_interrupt_waiver.do : func coverage waiver related to interrupt. + +3. One consolidated exclusion.do is available for each of the configurations. User shall load only this exclusion.do that will automatically load all the necessary waivers specific for that config. This helps to avoid possilibity of missing out or loading wrong exclusions. + + cv32e40p/sim/tools/vsim/exclusion/pulp/exclusion.do : for pulp config + cv32e40p/sim/tools/vsim/exclusion/pulp_fpu/exclusion.do : for pulp_fpu config + + +---------------------------------------------------- +Steps to load ucdb and apply exclusions: +---------------------------------------------------- +========================== +GUI mode - post-processing +========================== +1. Open ucdb file, change RTL source path to your repo (only needed if you want to view source code in the visualizer GUI) +visualizer -ucdbfile +change_file_path+= + +2. Load waivers + a. In visualizer command line, type: + do /cv32e40p/sim/tools/vsim/exclusion//exclusion.do + b. In "Pending Exclusions" window, click "Execute All Commands". + +=========================== +batch mode - automatic apply waiver +=========================== +Currently our Make flow does not take in waiver automatically. +To do this, the vsim.mk need to be enhance with following: + compile with +cover switch + vsim -coverage -do exclusions.do + run -all diff --git a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do new file mode 100644 index 0000000000..9c707b16d7 --- /dev/null +++ b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do @@ -0,0 +1,184 @@ +coverage exclude -line 114 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/int_controller_i -comment {All uncovered irq are unreachable. This is set by IRQ_MASK in cv32e40p_pkg.} +coverage exclude -line 116 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/int_controller_i -comment {All uncovered irq are unreachable. This is set by IRQ_MASK in cv32e40p_pkg.} +coverage exclude -line 118 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/int_controller_i -comment {All uncovered irq are unreachable. This is set by IRQ_MASK in cv32e40p_pkg.} +coverage exclude -line 120 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/int_controller_i -comment {All uncovered irq are unreachable. This is set by IRQ_MASK in cv32e40p_pkg.} +coverage exclude -line 127 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/int_controller_i -comment {All uncovered irq are unreachable. This is set by IRQ_MASK in cv32e40p_pkg.} +coverage exclude -line 129 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/int_controller_i -comment {All uncovered irq are unreachable. This is set by IRQ_MASK in cv32e40p_pkg.} +coverage exclude -line 131 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/int_controller_i -comment {All uncovered irq are unreachable. This is set by IRQ_MASK in cv32e40p_pkg.} +coverage exclude -line 134 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/int_controller_i -comment {All uncovered irq are unreachable. This is set by IRQ_MASK in cv32e40p_pkg.} +coverage exclude -line 136 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/int_controller_i -comment {All uncovered irq are unreachable. This is set by IRQ_MASK in cv32e40p_pkg.} +coverage exclude -line 138 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/int_controller_i -comment {All uncovered irq are unreachable. This is set by IRQ_MASK in cv32e40p_pkg.} +coverage exclude -line 141 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/int_controller_i -comment {All uncovered irq are unreachable. This is set by IRQ_MASK in cv32e40p_pkg.} +coverage exclude -line 143 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/int_controller_i -comment {All uncovered irq are unreachable. This is set by IRQ_MASK in cv32e40p_pkg.} +coverage exclude -line 145 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/int_controller_i -comment {All uncovered irq are unreachable. This is set by IRQ_MASK in cv32e40p_pkg.} +coverage exclude -line 113 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/int_controller_i -comment {All uncovered irq are unreachable. This is set by IRQ_MASK in cv32e40p_pkg.} +coverage exclude -line 115 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/int_controller_i -comment {All uncovered irq are unreachable. This is set by IRQ_MASK in cv32e40p_pkg.} +coverage exclude -line 117 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/int_controller_i -comment {All uncovered irq are unreachable. This is set by IRQ_MASK in cv32e40p_pkg.} +coverage exclude -line 119 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/int_controller_i -comment {All uncovered irq are unreachable. This is set by IRQ_MASK in cv32e40p_pkg.} +coverage exclude -line 126 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/int_controller_i -comment {All uncovered irq are unreachable. This is set by IRQ_MASK in cv32e40p_pkg.} +coverage exclude -line 128 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/int_controller_i -comment {All uncovered irq are unreachable. This is set by IRQ_MASK in cv32e40p_pkg.} +coverage exclude -line 130 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/int_controller_i -comment {All uncovered irq are unreachable. This is set by IRQ_MASK in cv32e40p_pkg.} +coverage exclude -line 133 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/int_controller_i -comment {All uncovered irq are unreachable. This is set by IRQ_MASK in cv32e40p_pkg.} +coverage exclude -line 135 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/int_controller_i -comment {All uncovered irq are unreachable. This is set by IRQ_MASK in cv32e40p_pkg.} +coverage exclude -line 137 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/int_controller_i -comment {All uncovered irq are unreachable. This is set by IRQ_MASK in cv32e40p_pkg.} +coverage exclude -line 140 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/int_controller_i -comment {All uncovered irq are unreachable. This is set by IRQ_MASK in cv32e40p_pkg.} +coverage exclude -line 142 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/int_controller_i -comment {All uncovered irq are unreachable. This is set by IRQ_MASK in cv32e40p_pkg.} +coverage exclude -line 144 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/int_controller_i -comment {All uncovered irq are unreachable. This is set by IRQ_MASK in cv32e40p_pkg.} +coverage exclude -line 1047 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/cs_registers_i/gen_no_pulp_secure_write_logic -comment {Never save exception pc in ex because no data error from PMP.} +coverage exclude -line 1105 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/cs_registers_i -comment {u_irq_enable_o never asserted. mstatus.uie never enabled.} +coverage exclude -line 1047 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/cs_registers_i/gen_no_pulp_secure_write_logic -comment {Never save exception pc in ex because no data error from PMP.} +coverage exclude -line 1048 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/cs_registers_i/gen_no_pulp_secure_write_logic -comment {Default of unique case not covered} +coverage exclude -line 134 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i -comment {We dont use USER mode.} +coverage exclude -line 140 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i -comment {We dont use USER mode.} +coverage exclude -line 165 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i -comment {We dont use USER mode.} +coverage exclude -line 134 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i -comment {We dont use USER mode.} +coverage exclude -line 140 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i -comment {We dont use USER mode.} +coverage exclude -line 165 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i -comment {We dont use USER mode.} +coverage exclude -line 113 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never fetch_valid == 0 when if_valid == 1. This case is impossible to reach since if_valid depends on fetch_valid to be asserted.} +coverage exclude -line 125 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never fetch_valid == 0 when if_valid == 1. This case is impossible to reach since if_valid depends on fetch_valid to be asserted.} +coverage exclude -line 141 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never fetch_valid == 0 when if_valid == 1. This case is impossible to reach since if_valid depends on fetch_valid to be asserted.} +coverage exclude -line 201 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never fetch_valid == 0 when if_valid == 1. This case is impossible to reach since if_valid depends on fetch_valid to be asserted.} +coverage exclude -line 212 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never fetch_valid == 0 when if_valid == 1. This case is impossible to reach since if_valid depends on fetch_valid to be asserted.} +coverage exclude -line 163 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never aligner_ready when entering misaligned 16 state. Always fetch valid the cycle before.} +coverage exclude -line 174 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never aligner_ready when entering misaligned 16 state. Always fetch valid the cycle before.} +coverage exclude -line 185 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never aligner_ready when entering misaligned 16 state. Always fetch valid the cycle before.} +coverage exclude -line 212 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {Hidden by branch line 205.} +coverage exclude -line 211 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {Hidden by branch line 205.} +coverage exclude -line 460 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {We dont support OBI error.} +coverage exclude -line 459 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {We dont support OBI error.} +coverage exclude -line 211 -code b -item 1 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {Hidden by branch line 205.} +coverage exclude -line 211 -code b -allfalse -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {Hidden by branch line 205.} +coverage exclude -line 549 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/alu_i -comment {Default part of uniqu_case for vector mode never reached.} +coverage exclude -line 579 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/alu_i -comment {Default part of uniqu_case for vector mode never reached.} +coverage exclude -line 608 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/alu_i -comment {Default part of uniqu_case for vector mode never reached.} +coverage exclude -line 628 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/alu_i -comment {Default part of uniqu_case for vector mode never reached.} +coverage exclude -line 648 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/alu_i -comment {Default part of uniqu_case for vector mode never reached.} +coverage exclude -line 667 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/alu_i -comment {Default part of uniqu_case for vector mode never reached.} +coverage exclude -line 528 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {reg_c = S1 never exist in the decoder. This is unreachable.} +coverage exclude -line 645 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {IMB_S3 never exists in the decoder. This is unreachable.} +coverage exclude -line 528 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {reg_c = S1 never exist in the decoder. This is unreachable.} +coverage exclude -line 645 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {IMB_S3 never exists in the decoder. This is unreachable.} +coverage exclude -line 362 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i -comment {No user mode in this configuration.} +coverage exclude -line 362 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i -comment {No user mode in this configuration. } +coverage exclude -line 81 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {We never overflow the fifo.} +coverage exclude -line 90 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {We never underflow the fifo.} +coverage exclude -line 81 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {We never overflow the fifo.} +coverage exclude -line 87 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {We never pop an element from the fifo while the fifo is empty} +coverage exclude -line 90 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {We never underflow the fifo.} +coverage exclude -line 97 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {Fifo never empty when trying to push and pop at the same time.} +coverage exclude -line 127 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {flush_but_first is dependent on !fifo_empty so this is unreachable.} +coverage exclude -line 128 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {flush_but_first is dependent on !fifo_empty so this is unreachable.} +coverage exclude -line 126 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {flush_but_first is dependent on !fifo_empty so this is unreachable.} +coverage exclude -line 81 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {We never overflow the fifo.} +coverage exclude -line 90 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {We never underflow the fifo.} +coverage exclude -line 126 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {flush_but_first is dependent on !fifo_empty so this is unreachable.} +coverage exclude -line 127 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {flush_but_first is dependent on !fifo_empty so this is unreachable.} +coverage exclude -line 128 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {flush_but_first is dependent on !fifo_empty so this is unreachable.} +coverage exclude -line 132 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {Case 2'b00 has been added for completion but is never used.} +coverage exclude -line 203 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No cv.elw in this configuration.} +coverage exclude -line 204 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No cv.elw in this configuration.} +coverage exclude -line 321 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {Data error not used.} +coverage exclude -line 322 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {Data error not used.} +coverage exclude -line 397 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {We are in PULP_OBI == 0 configuration. In this configuration, trans_valid is always asserted when used in this expression.} +coverage exclude -line 132 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {Case 2'b00 has been added for completion but is never used.} +coverage exclude -line 155 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {2'b11 choice that never exists in the decoder.} +coverage exclude -line 295 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {2'b11 choice that never exists in the decoder.} +coverage exclude -line 2770 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreacheable code as cur_priv_lvl_i is at maximum value.} +coverage exclude -line 2768 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreacheable code as cur_priv_lvl_i is at maximum value.} +coverage exclude -line 2768 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreacheable code as cur_priv_lvl_i is at maximum value.} +coverage exclude -line 419 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No Secure interrupt line. irq_sec_i tied to 0. } +coverage exclude -line 451 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } +coverage exclude -line 452 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } +coverage exclude -line 453 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } +coverage exclude -line 454 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } +coverage exclude -line 455 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } +coverage exclude -line 456 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } +coverage exclude -line 459 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } +coverage exclude -line 460 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } +coverage exclude -line 469 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0.} +coverage exclude -line 470 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0.} +coverage exclude -line 471 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0.} +coverage exclude -line 472 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0.} +coverage exclude -line 473 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0.} +coverage exclude -line 477 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0.} +coverage exclude -line 478 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0.} +coverage exclude -line 520 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No Secure interrupt line. irq_sec_i tied to 0. } +coverage exclude -line 604 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw} +coverage exclude -line 605 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw} +coverage exclude -line 742 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No Secure interrupt line. irq_sec_i tied to 0.} +coverage exclude -line 798 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw.} +coverage exclude -line 799 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw.} +coverage exclude -line 893 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error.} +coverage exclude -line 894 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error.} +coverage exclude -line 895 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error.} +coverage exclude -line 897 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error.} +coverage exclude -line 898 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error.} +coverage exclude -line 901 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error.} +coverage exclude -line 1006 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error.} +coverage exclude -line 1007 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error.} +coverage exclude -line 1008 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error.} +coverage exclude -line 1010 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error.} +coverage exclude -line 1011 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error.} +coverage exclude -line 1016 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0. } +coverage exclude -line 1017 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0. } +coverage exclude -line 1018 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0. } +coverage exclude -line 1019 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0. } +coverage exclude -line 1020 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0.} +coverage exclude -line 1061 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Can't be reached as uret instruction is illegal instruction.} +coverage exclude -line 1062 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Can't be reached as uret instruction is illegal instruction.} +coverage exclude -line 1117 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} +coverage exclude -line 1118 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} +coverage exclude -line 1119 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} +coverage exclude -line 1219 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error. data_err_i tied to 0. } +coverage exclude -line 1220 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error. data_err_i tied to 0. } +coverage exclude -line 1221 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error. data_err_i tied to 0. } +coverage exclude -line 1223 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error. data_err_i tied to 0. } +coverage exclude -line 1224 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error. data_err_i tied to 0. } +coverage exclude -line 421 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} +coverage exclude -line 522 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} +coverage exclude -line 744 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} +coverage exclude -line 921 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} +coverage exclude -line 1031 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Single-step not possible during debug mode.} +coverage exclude -line 1042 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Single-step not possible during debug mode.} +coverage exclude -line 1052 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Single-step not possible during debug mode.} +coverage exclude -line 299 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} +coverage exclude -line 824 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No PC = Hwloop1 end & Hwloop 1 counter = 0 in DECODE_HWLOOP FSM state.} +coverage exclude -line 418 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No Secure interrupt line. irq_sec_i tied to 0. } +coverage exclude -line 421 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} +coverage exclude -line 447 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } +coverage exclude -line 459 -code b -item 1 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } +coverage exclude -line 459 -code b -item 2 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } +coverage exclude -line 464 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0. } +coverage exclude -line 519 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No Secure interrupt line. irq_sec_i tied to 0. } +coverage exclude -line 522 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} +coverage exclude -line 603 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw.} +coverage exclude -line 604 -code b -item 1 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw.} +coverage exclude -line 604 -code b -item 2 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw.} +coverage exclude -line 741 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No Secure interrupt line. irq_sec_i tied to 0.} +coverage exclude -line 744 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} +coverage exclude -line 797 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw.} +coverage exclude -line 798 -code b -item 1 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw.} +coverage exclude -line 798 -code b -item 2 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw.} +coverage exclude -line 890 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } +coverage exclude -line 897 -code b -item 1 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } +coverage exclude -line 897 -code b -item 2 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } +coverage exclude -line 921 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} +coverage exclude -line 930 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw.} +coverage exclude -line 970 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw.} +coverage exclude -line 1004 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } +coverage exclude -line 1011 -code b -item 1 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } +coverage exclude -line 1011 -code b -item 2 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } +coverage exclude -line 1014 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0. } +coverage exclude -line 1019 -code b -item 1 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0. } +coverage exclude -line 1019 -code b -item 2 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0. } +coverage exclude -line 1060 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Can't be reached as uret instruction is illegal instruction.} +coverage exclude -line 1097 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Unreacheable default code.} +coverage exclude -line 1128 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Unreacheable default code.} +coverage exclude -line 1115 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} +coverage exclude -line 1117 -code b -item 1 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} +coverage exclude -line 1117 -code b -item 2 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} +coverage exclude -line 1216 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } +coverage exclude -line 1223 -code b -item 1 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } +coverage exclude -line 1223 -code b -item 2 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } +coverage exclude -code bcefs -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/interrupt_assert_i -recursive -comment {this is TB module bind to RTL. No need code coverage.} +coverage exclude -code bcefs -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/prefetch_controller_i/prefetch_controller_sva -recursive -comment {this is TB module bind to RTL. No need code coverage.} diff --git a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_pulp_cfg_waiver.do b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_pulp_cfg_waiver.do new file mode 100644 index 0000000000..438416f68b --- /dev/null +++ b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_pulp_cfg_waiver.do @@ -0,0 +1,59 @@ +coverage exclude -line 206 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} +coverage exclude -line 207 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} +coverage exclude -line 208 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} +coverage exclude -line 209 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} +coverage exclude -line 238 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} +coverage exclude -line 242 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} +coverage exclude -line 243 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} +coverage exclude -line 244 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} +coverage exclude -line 245 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} +coverage exclude -line 205 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} +coverage exclude -line 237 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} +coverage exclude -line 241 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} +coverage exclude -line 215 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} +coverage exclude -line 217 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} +coverage exclude -line 474 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} +coverage exclude -line 476 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} +coverage exclude -line 205 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} +coverage exclude -line 237 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} +coverage exclude -line 241 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} +coverage exclude -line 529 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {No FPU in this configuration.} +coverage exclude -line 1554 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {No FPU in this configuration.} +coverage exclude -line 1555 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {No FPU in this configuration.} +coverage exclude -line 1556 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {No FPU in this configuration.} +coverage exclude -line 1557 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {No FPU in this configuration.} +coverage exclude -line 1558 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {No FPU in this configuration.} +coverage exclude -line 920 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {No FPU in this configuration.} +coverage exclude -line 1675 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {No FPU in this configuration.} +coverage exclude -line 529 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {No FPU in this configuration.} +coverage exclude -line 724 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {No FPU in this configuration. } +coverage exclude -line 1553 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {No FPU in this configuration. } +coverage exclude -line 236 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} +coverage exclude -line 242 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} +coverage exclude -line 248 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} +coverage exclude -line 255 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} +coverage exclude -line 266 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} +coverage exclude -line 272 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} +coverage exclude -line 278 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} +coverage exclude -line 284 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} +coverage exclude -line 236 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} +coverage exclude -line 242 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} +coverage exclude -line 248 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} +coverage exclude -line 254 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} +coverage exclude -line 266 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} +coverage exclude -line 272 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} +coverage exclude -line 278 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} +coverage exclude -line 284 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} +coverage exclude -line 236 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} +coverage exclude -line 242 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} +coverage exclude -line 248 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} +coverage exclude -line 254 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} +coverage exclude -line 266 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} +coverage exclude -line 272 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} +coverage exclude -line 278 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} +coverage exclude -line 284 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} +coverage exclude -line 2986 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {No FPU in this configuration.} +coverage exclude -line 1376 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No FPU in this configuration.} +coverage exclude -line 89 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/register_file_i -comment {No FPU in this configuration.} +coverage exclude -line 90 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/register_file_i -comment {No FPU in this configuration.} +coverage exclude -line 91 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/register_file_i -comment {No FPU in this configuration.} diff --git a/cv32e40p/sim/tools/vsim/exclusion/pulp/exclusion.do b/cv32e40p/sim/tools/vsim/exclusion/pulp/exclusion.do index 0b88992b82..02450809f4 100644 --- a/cv32e40p/sim/tools/vsim/exclusion/pulp/exclusion.do +++ b/cv32e40p/sim/tools/vsim/exclusion/pulp/exclusion.do @@ -4,3 +4,8 @@ do ../cv32e40pv2_func_asrt_n_directive_waiver.do # functional: uvme_interrupt_covg_v2 do ../cv32e40pv2_func_uvme_interrupt_waiver.do +# code coverage : common waiver +do ../cv32e40pv2_code_all_cfg_waiver.do + +# code coverage : pulp_cfg specific waiver +do ../cv32e40pv2_code_pulp_cfg_waiver.do diff --git a/cv32e40p/sim/tools/vsim/exclusion/pulp_fpu/exclusion.do b/cv32e40p/sim/tools/vsim/exclusion/pulp_fpu/exclusion.do index 0b88992b82..34b74c435d 100644 --- a/cv32e40p/sim/tools/vsim/exclusion/pulp_fpu/exclusion.do +++ b/cv32e40p/sim/tools/vsim/exclusion/pulp_fpu/exclusion.do @@ -4,3 +4,5 @@ do ../cv32e40pv2_func_asrt_n_directive_waiver.do # functional: uvme_interrupt_covg_v2 do ../cv32e40pv2_func_uvme_interrupt_waiver.do +# code coverage : common waiver +do ../cv32e40pv2_code_all_cfg_waiver.do From 0834500bb4fe08e034f7931d2ebb9be6e19a0e05 Mon Sep 17 00:00:00 2001 From: Xavier Aubert Date: Tue, 20 Feb 2024 19:47:15 +0100 Subject: [PATCH 03/20] shell script generation now correclty supports multiple test_cfg file & correct log location --- bin/templates/regress_sh.j2 | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/bin/templates/regress_sh.j2 b/bin/templates/regress_sh.j2 index 41fe6880ec..3dc14fad2b 100644 --- a/bin/templates/regress_sh.j2 +++ b/bin/templates/regress_sh.j2 @@ -105,8 +105,12 @@ popd > /dev/null {% else %} {% set test_cfg = "" %} {% endif %} +{% set test_cfg_list = test_cfg|replace(" ",",")|replace("+",",") %} +{% set test_cfg_list = test_cfg_list.split(",")|unique|sort %} +{% set test_cfg_path = test_cfg_list|join("__") %} + # --> Test (Index: {{run_index}}): {{t.cmd}} : {{t.description}} -{% set cmd = test_cmd + ' CV_CORE=' + project + ' CFG=' + r.builds[build].cfg + ' ' + toolchain|upper + '=1' + ' RISCVDV_CFG=' + t.riscvdv_cfg + ' SIMULATOR=' + t.simulator + ' COMP=0 USE_ISS=' + regress_macros.yesorno(t.iss) + ' COV=' + regress_macros.yesorno(t.cov) + ' SEED=random GEN_START_INDEX=' + run_index|string + ' RUN_INDEX=' + run_index|string + ' TEST_CFG_FILE=' + test_cfg + ' ' + regress_macros.cv_results(results) + ' ' + makeargs %} +{% set cmd = test_cmd + ' CV_CORE=' + project + ' CFG=' + r.builds[build].cfg + ' ' + toolchain|upper + '=1' + ' RISCVDV_CFG=' + t.riscvdv_cfg + ' SIMULATOR=' + t.simulator + ' COMP=0 USE_ISS=' + regress_macros.yesorno(t.iss) + ' COV=' + regress_macros.yesorno(t.cov) + ' SEED=random GEN_START_INDEX=' + run_index|string + ' RUN_INDEX=' + run_index|string + ' TEST_CFG_FILE=\"' + test_cfg + '\" ' + regress_macros.cv_results(results) + ' ' + makeargs %} echo "{{session}}: Running test [cd {{t.abs_dir}} && {{cmd}}]" pushd {{t.abs_dir}} > /dev/null {{cmd}} >& /dev/null; @@ -118,13 +122,7 @@ popd > /dev/null {% else %} {% set results_dir = t.simulator + '_results' %} {% endif %} -{% if t.test_cfg is defined %} - {% set sim_log = t.simulator + '-' + test_log + '_' + t.test_cfg + '.log' %} - {% set test_cfg_path = t.test_cfg %} -{% else %} - {% set sim_log = t.simulator + '-' + test_log + '.log' %} - {% set test_cfg_path = '' %} -{% endif %} +{% set sim_log = t.simulator + '-' + test_log + '.log' %} {# Determine log location #} {% if t.results %} From 56b8889c0e214702feae584fdb6aebd2c708a8b1 Mon Sep 17 00:00:00 2001 From: Xavier Aubert Date: Tue, 20 Feb 2024 20:04:25 +0100 Subject: [PATCH 04/20] added README for commands to enter to generate v2 regress lists --- cv32e40p/regress/README.md | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 cv32e40p/regress/README.md diff --git a/cv32e40p/regress/README.md b/cv32e40p/regress/README.md new file mode 100644 index 0000000000..14a1fc4131 --- /dev/null +++ b/cv32e40p/regress/README.md @@ -0,0 +1,26 @@ +CV32E40P Regress Files +================================== + +For V2 core, all the regressions files should be generated using the following cv_regress commands, where *type* has to be chosen between `sh` and `rmdb`, and *sim* is the wanted simulator (vsim, xrun, ...) + +## pulp configuration + +> ./cv_regress --{type} --file=cv32e40pv2_xpulp_instr.yaml --simulator={sim} --outfile=xpulp_instr_pulp.{type} --cfg pulp +> ./cv_regress --{type} --file=cv32e40pv2_interrupt_debug.yaml --simulator={sim} --outfile=int_debug_pulp.{type} --cfg pulp + +## pulp_fpu configuration +> ./cv_regress --{type} --file=cv32e40pv2_xpulp_instr.yaml --simulator={sim} --outfile=xpulp_instr_pulp_fpu.{type} --cfg pulp_fpu --add_test_cfg floating_pt_instr_en +> ./cv_regress --{type} --file=cv32e40pv2_fpu_instr.yaml --simulator={sim} --outfile=fpu_instr_pulp_fpu.{type} --cfg pulp_fpu --add_test_cfg floating_pt_instr_en +> ./cv_regress --{type} --file=cv32e40pv2_interrupt_debug.yaml --simulator={sim} --outfile=int_debug_pulp_fpu.{type} --cfg pulp_fpu --add_test_cfg floating_pt_instr_en + +## pulp_fpu_zfinx configuration +> ./cv_regress --{type} --file=cv32e40pv2_xpulp_instr.yaml --simulator={sim} --outfile=xpulp_instr_pulp_fpu_zfinx.{type} --cfg pulp_fpu_zfinx --add_test_cfg floating_pt_zfinx_instr_en +> ./cv_regress --{type} --file=cv32e40pv2_fpu_instr.yaml --simulator={sim} --outfile=fpu_instr_pulp_fpu_zfinx.{type} --cfg pulp_fpu_zfinx --add_test_cfg floating_pt_zfinx_instr_en +> ./cv_regress --{type} --file=cv32e40pv2_interrupt_debug.yaml --simulator={sim} --outfile=int_debug_pulp_fpu_zfinx.{type} --cfg pulp_fpu_zfinx --add_test_cfg floating_pt_zfinx_instr_en + +## configurations with latency +To generate regressions with latency (e.g. pulp_fpu_zfinx_2cyclat), only the `--cfg` switch has to be updated: + +> ./cv_regress --{type} --file=cv32e40pv2_xpulp_instr.yaml --simulator={sim} --outfile=xpulp_instr_pulp_fpu_zfinx_2cyclat.{type} --cfg pulp_fpu_zfinx_2cyclat --add_test_cfg floating_pt_zfinx_instr_en +> ./cv_regress --{type} --file=cv32e40pv2_fpu_instr.yaml --simulator={sim} --outfile=fpu_instr_pulp_fpu_zfinx_2cyclat.{type} --cfg pulp_fpu_zfinx_2cyclat --add_test_cfg floating_pt_instr_en +> ./cv_regress --{type} --file=cv32e40pv2_interrupt_debug.yaml --simulator={sim} --outfile=int_debug_pulp_fpu_zfinx_2cyclat.{type} --cfg pulp_fpu_zfinx_2cyclat --add_test_cfg floating_pt_instr_en From 9e18a04372d677cb8dabfaf0690f93d904b87fea Mon Sep 17 00:00:00 2001 From: XavierAubert Date: Tue, 20 Feb 2024 20:08:16 +0100 Subject: [PATCH 05/20] Update README.md carriage return added --- cv32e40p/regress/README.md | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/cv32e40p/regress/README.md b/cv32e40p/regress/README.md index 14a1fc4131..b4b48d4b4f 100644 --- a/cv32e40p/regress/README.md +++ b/cv32e40p/regress/README.md @@ -5,22 +5,22 @@ For V2 core, all the regressions files should be generated using the following c ## pulp configuration -> ./cv_regress --{type} --file=cv32e40pv2_xpulp_instr.yaml --simulator={sim} --outfile=xpulp_instr_pulp.{type} --cfg pulp -> ./cv_regress --{type} --file=cv32e40pv2_interrupt_debug.yaml --simulator={sim} --outfile=int_debug_pulp.{type} --cfg pulp +> ./cv_regress --{type} --file=cv32e40pv2_xpulp_instr.yaml --simulator={sim} --outfile=xpulp_instr_pulp.{type} --cfg pulp
+> ./cv_regress --{type} --file=cv32e40pv2_interrupt_debug.yaml --simulator={sim} --outfile=int_debug_pulp.{type} --cfg pulp
## pulp_fpu configuration -> ./cv_regress --{type} --file=cv32e40pv2_xpulp_instr.yaml --simulator={sim} --outfile=xpulp_instr_pulp_fpu.{type} --cfg pulp_fpu --add_test_cfg floating_pt_instr_en -> ./cv_regress --{type} --file=cv32e40pv2_fpu_instr.yaml --simulator={sim} --outfile=fpu_instr_pulp_fpu.{type} --cfg pulp_fpu --add_test_cfg floating_pt_instr_en -> ./cv_regress --{type} --file=cv32e40pv2_interrupt_debug.yaml --simulator={sim} --outfile=int_debug_pulp_fpu.{type} --cfg pulp_fpu --add_test_cfg floating_pt_instr_en +> ./cv_regress --{type} --file=cv32e40pv2_xpulp_instr.yaml --simulator={sim} --outfile=xpulp_instr_pulp_fpu.{type} --cfg pulp_fpu --add_test_cfg floating_pt_instr_en
+> ./cv_regress --{type} --file=cv32e40pv2_fpu_instr.yaml --simulator={sim} --outfile=fpu_instr_pulp_fpu.{type} --cfg pulp_fpu --add_test_cfg floating_pt_instr_en
+> ./cv_regress --{type} --file=cv32e40pv2_interrupt_debug.yaml --simulator={sim} --outfile=int_debug_pulp_fpu.{type} --cfg pulp_fpu --add_test_cfg floating_pt_instr_en
## pulp_fpu_zfinx configuration -> ./cv_regress --{type} --file=cv32e40pv2_xpulp_instr.yaml --simulator={sim} --outfile=xpulp_instr_pulp_fpu_zfinx.{type} --cfg pulp_fpu_zfinx --add_test_cfg floating_pt_zfinx_instr_en -> ./cv_regress --{type} --file=cv32e40pv2_fpu_instr.yaml --simulator={sim} --outfile=fpu_instr_pulp_fpu_zfinx.{type} --cfg pulp_fpu_zfinx --add_test_cfg floating_pt_zfinx_instr_en -> ./cv_regress --{type} --file=cv32e40pv2_interrupt_debug.yaml --simulator={sim} --outfile=int_debug_pulp_fpu_zfinx.{type} --cfg pulp_fpu_zfinx --add_test_cfg floating_pt_zfinx_instr_en +> ./cv_regress --{type} --file=cv32e40pv2_xpulp_instr.yaml --simulator={sim} --outfile=xpulp_instr_pulp_fpu_zfinx.{type} --cfg pulp_fpu_zfinx --add_test_cfg floating_pt_zfinx_instr_en
+> ./cv_regress --{type} --file=cv32e40pv2_fpu_instr.yaml --simulator={sim} --outfile=fpu_instr_pulp_fpu_zfinx.{type} --cfg pulp_fpu_zfinx --add_test_cfg floating_pt_zfinx_instr_en
+> ./cv_regress --{type} --file=cv32e40pv2_interrupt_debug.yaml --simulator={sim} --outfile=int_debug_pulp_fpu_zfinx.{type} --cfg pulp_fpu_zfinx --add_test_cfg floating_pt_zfinx_instr_en
## configurations with latency To generate regressions with latency (e.g. pulp_fpu_zfinx_2cyclat), only the `--cfg` switch has to be updated: -> ./cv_regress --{type} --file=cv32e40pv2_xpulp_instr.yaml --simulator={sim} --outfile=xpulp_instr_pulp_fpu_zfinx_2cyclat.{type} --cfg pulp_fpu_zfinx_2cyclat --add_test_cfg floating_pt_zfinx_instr_en -> ./cv_regress --{type} --file=cv32e40pv2_fpu_instr.yaml --simulator={sim} --outfile=fpu_instr_pulp_fpu_zfinx_2cyclat.{type} --cfg pulp_fpu_zfinx_2cyclat --add_test_cfg floating_pt_instr_en +> ./cv_regress --{type} --file=cv32e40pv2_xpulp_instr.yaml --simulator={sim} --outfile=xpulp_instr_pulp_fpu_zfinx_2cyclat.{type} --cfg pulp_fpu_zfinx_2cyclat --add_test_cfg floating_pt_zfinx_instr_en
+> ./cv_regress --{type} --file=cv32e40pv2_fpu_instr.yaml --simulator={sim} --outfile=fpu_instr_pulp_fpu_zfinx_2cyclat.{type} --cfg pulp_fpu_zfinx_2cyclat --add_test_cfg floating_pt_instr_en
> ./cv_regress --{type} --file=cv32e40pv2_interrupt_debug.yaml --simulator={sim} --outfile=int_debug_pulp_fpu_zfinx_2cyclat.{type} --cfg pulp_fpu_zfinx_2cyclat --add_test_cfg floating_pt_instr_en From 94c6d7fd28edb85a17f178467f73d95ad8df2e41 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Mon, 26 Feb 2024 13:22:12 +0800 Subject: [PATCH 06/20] Fix typo in header file Signed-off-by: dd-baoshan --- cv32e40p/env/uvme/cov/uvme_interrupt_covg_v2.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cv32e40p/env/uvme/cov/uvme_interrupt_covg_v2.sv b/cv32e40p/env/uvme/cov/uvme_interrupt_covg_v2.sv index 1824a0bcd8..9be5805d1a 100644 --- a/cv32e40p/env/uvme/cov/uvme_interrupt_covg_v2.sv +++ b/cv32e40p/env/uvme/cov/uvme_interrupt_covg_v2.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////////////////////////////////////////// // // Copyright 2023 OpenHW Group -// Copyright 2023 Dolphin Design +// Copyright 2024 Dolphin Design // // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. From 39fa687abc5bdf5265c0c293421715a939385ce8 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Mon, 26 Feb 2024 13:24:31 +0800 Subject: [PATCH 07/20] Move macro definition into macro include file Signed-off-by: dd-baoshan --- cv32e40p/tb/uvmt/uvmt_cv32e40p_macros.sv | 26 ++++++++++++++++++++++++ cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv | 21 +------------------ 2 files changed, 27 insertions(+), 20 deletions(-) diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_macros.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_macros.sv index 66ad145f50..a27dd97a1f 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_macros.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_macros.sv @@ -221,4 +221,30 @@ `define CSR_MCONFIGPTR_ADDR 32'hF15 + // BELOW ARE USE FOR SPECIAL HACKS PURPOSE - START + + // 1 - To cover directives instr/data gnt assert-deassert when req is low + `define TB_HACK_1_OBI_GNT(TYPE) initial begin : hack_obi_intf_gnt_signal_1_``TYPE \ + if ($test$plusargs("tb_hack_1_obi_gnt_signal")) begin \ + int success_addr_phase_cnt = 0, hack_cnt = 0; \ + forever begin \ + @(posedge obi_memory_``TYPE``_if.clk); \ + if (obi_memory_``TYPE``_if.req && obi_memory_``TYPE``_if.gnt) success_addr_phase_cnt++; \ + if (success_addr_phase_cnt > 5) begin \ + if (!obi_memory_``TYPE``_if.req & !obi_memory_``TYPE``_if.gnt) begin \ + #1ps; \ + if (!obi_memory_``TYPE``_if.req & !obi_memory_``TYPE``_if.gnt) begin \ + force obi_memory_``TYPE``_if.gnt = 1; \ + @(posedge obi_memory_``TYPE``_if.clk); release obi_memory_``TYPE``_if.gnt; hack_cnt++; \ + end \ + end \ + end \ + if (hack_cnt > 2) break; \ + end // forever \ + end \ + end + + // BELOW ARE USE FOR SPECIAL HACKS PURPOSE - END + + `endif // __UVMT_CV32E40P_MACROS_SV__ diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv index 45b4cefa3d..f72ad3888f 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv @@ -960,27 +960,8 @@ module uvmt_cv32e40p_tb; // BELOW ARE USE FOR SPECIAL HACKS PURPOSE - START - + // 1 - To cover directives instr/data gnt assert-deassert when req is low - `define TB_HACK_1_OBI_GNT(TYPE) initial begin : hack_obi_intf_gnt_signal_1_``TYPE \ - if ($test$plusargs("tb_hack_1_obi_gnt_signal")) begin \ - int success_addr_phase_cnt = 0, hack_cnt = 0; \ - forever begin \ - @(posedge obi_memory_``TYPE``_if.clk); \ - if (obi_memory_``TYPE``_if.req && obi_memory_``TYPE``_if.gnt) success_addr_phase_cnt++; \ - if (success_addr_phase_cnt > 5) begin \ - if (!obi_memory_``TYPE``_if.req & !obi_memory_``TYPE``_if.gnt) begin \ - #1ps; \ - if (!obi_memory_``TYPE``_if.req & !obi_memory_``TYPE``_if.gnt) begin \ - force obi_memory_``TYPE``_if.gnt = 1; \ - @(posedge obi_memory_``TYPE``_if.clk); release obi_memory_``TYPE``_if.gnt; hack_cnt++; \ - end \ - end \ - end \ - if (hack_cnt > 2) break; \ - end // forever \ - end \ - end `TB_HACK_1_OBI_GNT(instr) `TB_HACK_1_OBI_GNT(data) From 354a90c28a7a22e6a074eaaffbd54185d0dc3223 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Mon, 26 Feb 2024 13:31:29 +0800 Subject: [PATCH 08/20] Revise the cross coverage of cover group Signed-off-by: dd-baoshan --- cv32e40p/env/uvme/cov/uvme_debug_covg.sv | 47 +++++++++++++++---- .../env/uvme/cov/uvme_rv32x_hwloop_covg.sv | 24 ++++++---- 2 files changed, 54 insertions(+), 17 deletions(-) diff --git a/cv32e40p/env/uvme/cov/uvme_debug_covg.sv b/cv32e40p/env/uvme/cov/uvme_debug_covg.sv index 74750003a2..8a5e89109c 100644 --- a/cv32e40p/env/uvme/cov/uvme_debug_covg.sv +++ b/cv32e40p/env/uvme/cov/uvme_debug_covg.sv @@ -288,11 +288,11 @@ class uvme_debug_covg extends uvm_component; } dreq_and_ill : cross dreq, ill; irq_and_dreq : cross dreq, irq; - irq_dreq_trig_ill : cross dreq, irq, trigger, ill; - irq_dreq_trig_cebreak : cross dreq, irq, trigger, cebreak; - irq_dreq_trig_ebreak : cross dreq, irq, trigger, ebreak; - irq_dreq_trig_branch : cross dreq, irq, trigger, branch; - irq_dreq_trig_multicycle : cross dreq, irq, trigger, mulhsu; + irq_dreq_trig_ill : cross dreq, irq, trigger, ill; // irq + haltreq + trigger (illegal) + irq_dreq_trig_cebreak : cross dreq, irq, trigger, cebreak; // irq + haltreq + trigger (cbreak) + irq_dreq_trig_ebreak : cross dreq, irq, trigger, ebreak; // irq + haltreq + trigger (ebreak) + irq_dreq_trig_branch : cross dreq, irq, trigger, branch; // irq + haltreq + trigger (branch) + irq_dreq_trig_multicycle : cross dreq, irq, trigger, mulhsu; // irq + haltreq + trigger (mc) endgroup // Cover access to dcsr, dpc and dscratch0/1 in D-mode @@ -528,9 +528,40 @@ class uvme_debug_covg extends uvm_component; cr_dbg_while_multi_cyc_f_A : cross cp_apu_req_valid, cp_apu_grant_valid, cp_dbg_req; cr_dbg_while_multi_cyc_f_B : cross cp_apu_busy, cp_dbg_req; - // debug_halt_req with irq during multi cycle fp inst - cr_dbg_irq_while_multi_cyc_f_A : cross cp_apu_req_valid, cp_apu_grant_valid, cp_dbg_req, cp_irq; - cr_dbg_irq_while_multi_cyc_f_B : cross cp_apu_busy, cp_dbg_req, cp_irq; + // debug_halt_req with irq during multi cycle fp inst (fixme: what is the benefit cross with this irq?) + cr_dbg_irq_while_multi_cyc_f_A : cross cp_apu_req_valid, cp_apu_grant_valid, cp_dbg_req, cp_irq { + bins irq_grp_upper16_multi_cyc_f_A = binsof(cp_dbg_req.dbg_req_active) && binsof(cp_apu_grant_valid) && ( + binsof(cp_irq.irq_31_trans_0_to_1) || binsof(cp_irq.irq_30_trans_0_to_1) || + binsof(cp_irq.irq_29_trans_0_to_1) || binsof(cp_irq.irq_28_trans_0_to_1) || + binsof(cp_irq.irq_27_trans_0_to_1) || binsof(cp_irq.irq_26_trans_0_to_1) || + binsof(cp_irq.irq_25_trans_0_to_1) || binsof(cp_irq.irq_24_trans_0_to_1) || + binsof(cp_irq.irq_23_trans_0_to_1) || binsof(cp_irq.irq_22_trans_0_to_1) || + binsof(cp_irq.irq_21_trans_0_to_1) || binsof(cp_irq.irq_20_trans_0_to_1) || + binsof(cp_irq.irq_19_trans_0_to_1) || binsof(cp_irq.irq_18_trans_0_to_1) || + binsof(cp_irq.irq_17_trans_0_to_1) || binsof(cp_irq.irq_16_trans_0_to_1)); + bins irq_grp_lower16_multi_cyc_f_A = binsof(cp_dbg_req.dbg_req_active) && binsof(cp_apu_grant_valid) && ( + binsof(cp_irq.irq_11_trans_0_to_1) || + binsof(cp_irq.irq_3_trans_0_to_1) || + binsof(cp_irq.irq_7_trans_0_to_1)); + ignore_bins dbg_req_others = binsof(cp_dbg_req.dbg_req_0_to_1); + } + cr_dbg_irq_while_multi_cyc_f_B : cross cp_apu_busy, cp_dbg_req, cp_irq { + bins irq_grp_upper16_multi_cyc_f_B = binsof(cp_dbg_req.dbg_req_active) && (binsof(cp_apu_busy.apu_busy) intersect {1}) && ( + binsof(cp_irq.irq_31_trans_0_to_1) || binsof(cp_irq.irq_30_trans_0_to_1) || + binsof(cp_irq.irq_29_trans_0_to_1) || binsof(cp_irq.irq_28_trans_0_to_1) || + binsof(cp_irq.irq_27_trans_0_to_1) || binsof(cp_irq.irq_26_trans_0_to_1) || + binsof(cp_irq.irq_25_trans_0_to_1) || binsof(cp_irq.irq_24_trans_0_to_1) || + binsof(cp_irq.irq_23_trans_0_to_1) || binsof(cp_irq.irq_22_trans_0_to_1) || + binsof(cp_irq.irq_21_trans_0_to_1) || binsof(cp_irq.irq_20_trans_0_to_1) || + binsof(cp_irq.irq_19_trans_0_to_1) || binsof(cp_irq.irq_18_trans_0_to_1) || + binsof(cp_irq.irq_17_trans_0_to_1) || binsof(cp_irq.irq_16_trans_0_to_1)); + bins irq_grp_lower16_multi_cyc_f_B = binsof(cp_dbg_req.dbg_req_active) && (binsof(cp_apu_busy.apu_busy) intersect {1}) && ( + binsof(cp_irq.irq_11_trans_0_to_1) || + binsof(cp_irq.irq_3_trans_0_to_1) || + binsof(cp_irq.irq_7_trans_0_to_1)); + ignore_bins dbg_apu_busy_others = (binsof(cp_apu_busy.apu_busy) intersect {0}) || binsof(cp_apu_busy.apu_busy_0_to_1) || binsof(cp_apu_busy.apu_busy_1_to_0); + ignore_bins dbg_req_others = binsof(cp_dbg_req.dbg_req_0_to_1); + } // debug_halt_req with illegal instr during multi cycle fp inst cr_dbg_ill_while_multi_cyc_f_A : cross cp_apu_req_valid, cp_apu_grant_valid, cp_dbg_req, cp_ill; diff --git a/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv index 87e90a30ef..a9be725755 100644 --- a/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv +++ b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv @@ -158,19 +158,25 @@ class uvme_rv32x_hwloop_covg # ( // higher counts are not covered now to reduced simtime (amend if needed) \ } \ ccp_lpstart_0_lpend_lpcount_``LOOP_IDX : cross cp_lpstart_``LOOP_IDX``, cp_lpend_``LOOP_IDX``, cp_lpcount_``LOOP_IDX`` { \ - ignore_bins ignore__lpstart_range_1 = binsof (cp_lpstart_``LOOP_IDX``) intersect {[32'h0000_0FFC : 32'h0000_0400]}; \ - ignore_bins ignore__lpstart_range_2 = binsof (cp_lpstart_``LOOP_IDX``) intersect {[32'h0000_FFFC : 32'h0000_1000]}; \ + ignore_bins ignore__lpstart_range_1 = binsof (cp_lpstart_``LOOP_IDX``.lpstart_range_1); \ + ignore_bins ignore__lpstart_range_2 = binsof (cp_lpstart_``LOOP_IDX``.lpstart_range_2); \ + // ignore below due to long simtime if cross higher count with large loop \ + ignore_bins ignore__lpcount_low4 = binsof (cp_lpcount_``LOOP_IDX``.lpcount_range_low_4); \ } \ ccp_lpstart_1_lpend_lpcount_``LOOP_IDX : cross cp_lpstart_``LOOP_IDX``, cp_lpend_``LOOP_IDX``, cp_lpcount_``LOOP_IDX`` { \ - ignore_bins ignore__lpstart_range_0 = binsof (cp_lpstart_``LOOP_IDX``) intersect {[32'h0000_03FC : 32'h0000_0004]}; \ - ignore_bins ignore__lpstart_range_2 = binsof (cp_lpstart_``LOOP_IDX``) intersect {[32'h0000_FFFC : 32'h0000_1000]}; \ - ignore_bins ignore__lpend_range_0 = binsof (cp_lpend_``LOOP_IDX``) intersect {[32'h0000_03FC : 32'h0000_0004]}; \ + ignore_bins ignore__lpstart_range_0 = binsof (cp_lpstart_``LOOP_IDX``.lpstart_range_0); \ + ignore_bins ignore__lpstart_range_2 = binsof (cp_lpstart_``LOOP_IDX``.lpstart_range_2); \ + ignore_bins ignore__lpend_range_0 = binsof (cp_lpend_``LOOP_IDX``.lpend_range_0); \ + // ignore below due to long simtime if cross higher count with large loop \ + ignore_bins ignore__lpcount_low4 = binsof (cp_lpcount_``LOOP_IDX``.lpcount_range_low_4); \ } \ ccp_lpstart_2_lpend_lpcount_``LOOP_IDX : cross cp_lpstart_``LOOP_IDX``, cp_lpend_``LOOP_IDX``, cp_lpcount_``LOOP_IDX`` { \ - ignore_bins ignore__lpstart_range_0 = binsof (cp_lpstart_``LOOP_IDX``) intersect {[32'h0000_03FC : 32'h0000_0004]}; \ - ignore_bins ignore__lpstart_range_1 = binsof (cp_lpstart_``LOOP_IDX``) intersect {[32'h0000_0FFC : 32'h0000_0400]}; \ - ignore_bins ignore__lpend_range_0 = binsof (cp_lpend_``LOOP_IDX``) intersect {[32'h0000_03FC : 32'h0000_0004]}; \ - ignore_bins ignore__lpend_range_1 = binsof (cp_lpend_``LOOP_IDX``) intersect {[32'h0000_0FFC : 32'h0000_0400]}; \ + ignore_bins ignore__lpstart_range_0 = binsof (cp_lpstart_``LOOP_IDX``.lpstart_range_0); \ + ignore_bins ignore__lpstart_range_1 = binsof (cp_lpstart_``LOOP_IDX``.lpstart_range_1); \ + ignore_bins ignore__lpend_range_0 = binsof (cp_lpend_``LOOP_IDX``.lpend_range_0); \ + ignore_bins ignore__lpend_range_1 = binsof (cp_lpend_``LOOP_IDX``.lpend_range_1); \ + // ignore below due to long simtime if cross higher count with large loop \ + ignore_bins ignore__lpcount_low4 = binsof (cp_lpcount_``LOOP_IDX``.lpcount_range_low_4); \ } \ endgroup : cg_csr_hwloop_``LOOP_IDX From 0e67f2a486619ddf4e88dfb5bb290843a15eea44 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Mon, 26 Feb 2024 13:32:16 +0800 Subject: [PATCH 09/20] Add logic to handle illegal insn in directed stream Signed-off-by: dd-baoshan --- .../env/corev-dv/cv32e40p_instr_sequence.sv | 22 ++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/cv32e40p/env/corev-dv/cv32e40p_instr_sequence.sv b/cv32e40p/env/corev-dv/cv32e40p_instr_sequence.sv index 3756295b06..a58f559f52 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_instr_sequence.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_instr_sequence.sv @@ -210,7 +210,7 @@ class cv32e40p_instr_sequence extends riscv_instr_sequence; end instr_stream.instr_list[i].has_label = 1'b1; end else begin - if(instr_stream.instr_list[i].has_label) begin + if(instr_stream.instr_list[i].has_label) begin : HAS_LABEL //check if it is hwloop label label_is_pulp_hwloop_body_label = check_str_pattern_match(instr_stream.instr_list[i].label, "hwloop"); if(!label_is_pulp_hwloop_body_label) begin @@ -265,14 +265,26 @@ class cv32e40p_instr_sequence extends riscv_instr_sequence; format_str_len = LABEL_STR_LEN; end end - end else begin + str = {prefix, instr_stream.instr_list[i].convert2asm()}; + end // HAS_LABEL + else if (instr_stream.instr_list[i].is_illegal_instr) begin : IS_ILLEGAL_INSTR + // insert illegal insn in directed stream + cv32_illegal_instr.init(cfg); + cv32_illegal_instr.cv32e40p_init(cfg); // Init legal_opcode for cv32e40p + `DV_CHECK_RANDOMIZE_WITH_FATAL(cv32_illegal_instr, exception != kHintInstr;) + str = {indent, $sformatf(".4byte 0x%s # %0s", cv32_illegal_instr.get_bin_str(), cv32_illegal_instr.comment)}; + end // IS_ILLEGAL_INSTR + else begin prefix = format_string(" ", format_str_len); + str = {prefix, instr_stream.instr_list[i].convert2asm()}; end - end - str = {prefix, instr_stream.instr_list[i].convert2asm()}; + end // i != 0 + + // str = {prefix, instr_stream.instr_list[i].convert2asm()}; instr_string_list.push_back(str); - end + end // instr_stream.instr_list.size + // If PMP is supported, need to align
to a 4-byte boundary. if (riscv_instr_pkg::support_pmp && !uvm_re_match(uvm_glob_to_re("*main*"), label_name)) begin instr_string_list.push_front(".align 2"); From 97c13e4498f0d6f4797367d4322b282c3e4c98d4 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Mon, 26 Feb 2024 13:37:07 +0800 Subject: [PATCH 10/20] Optimize conditional branch Signed-off-by: dd-baoshan --- .../uvmt/compliance-tests/uvmt_cv32e40p_firmware_test.sv | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/cv32e40p/tests/uvmt/compliance-tests/uvmt_cv32e40p_firmware_test.sv b/cv32e40p/tests/uvmt/compliance-tests/uvmt_cv32e40p_firmware_test.sv index 8876d1c1c6..41c920e856 100644 --- a/cv32e40p/tests/uvmt/compliance-tests/uvmt_cv32e40p_firmware_test.sv +++ b/cv32e40p/tests/uvmt/compliance-tests/uvmt_cv32e40p_firmware_test.sv @@ -127,7 +127,7 @@ task uvmt_cv32e40p_firmware_test_c::run_phase(uvm_phase phase); // start_clk() and watchdog_timer() are called in the base_test super.run_phase(phase); - if ($test$plusargs("gen_random_debug")) begin + if ($test$plusargs("gen_random_debug") || $test$plusargs("gen_reduced_rand_dbg_req")) begin fork random_debug(); join_none @@ -150,12 +150,6 @@ task uvmt_cv32e40p_firmware_test_c::run_phase(uvm_phase phase); join_none end - if ($test$plusargs("gen_reduced_rand_dbg_req")) begin - fork - random_debug(); - join_none - end - phase.raise_objection(this); @(posedge env_cntxt.clknrst_cntxt.vif.reset_n); repeat (33) @(posedge env_cntxt.clknrst_cntxt.vif.clk); From 9882d48e4a0fe9d2c2d52b2d8271dae5825ce0fb Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Mon, 26 Feb 2024 13:38:35 +0800 Subject: [PATCH 11/20] Add and Update tests to improve tb functional coverage holes (uvme_debug_covg) Signed-off-by: dd-baoshan --- .../instr_lib/cv32e40p_float_instr_lib.sv | 16 ++++- .../cv32e40p_instr_for_func_cvg_lib.sv | 72 ++++++++++++++++++- .../cv32e40p_pulp_hwloop_instr_lib.sv | 19 ++--- .../cv32e40pv2_for_func_cvg_improvement.yaml | 33 ++++++++- .../cv32e40pv2_interrupt_debug_short.yaml | 22 +++--- .../corev_rand_fp_instr_debug/corev-dv.yaml | 14 +--- .../corev_rand_fp_instr_debug/test.yaml | 4 +- 7 files changed, 140 insertions(+), 40 deletions(-) diff --git a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv index f2fc246748..b7499fe685 100644 --- a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv +++ b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv @@ -53,6 +53,7 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; bit use_prev_rd_on_next_operands; // previous instr rd is used for directed instr operands bit use_diff_regs_for_operands = 0; // to control rand instr uses different registers for instr oeprands bit more_weight_for_fdiv_fsqrt_gen; // more weight on generating fdiv and fsqrt directed_instr + bit use_only_for_fdiv_fsqrt_gen; // use only fdiv and fsqrt directed_instr bit init_gpr = (is_zfinx) ? 1 : 0; // initialize gpr registers in stream with rand value bit init_fpr = (is_zfinx) ? 0 : 1; // initialize fpr registers in stream with rand value bit en_clr_fflags_af_instr; // clear fflag to prevent residual fflags status of current f_instr @@ -415,9 +416,9 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; end end - if (more_weight_for_fdiv_fsqrt_gen) begin + if (more_weight_for_fdiv_fsqrt_gen || use_only_for_fdiv_fsqrt_gen) begin if (select_fp_instr) // is fp - if ($urandom_range(1)) // 50% rate of getting fdiv/fsqrt + if ($urandom_range(1) || use_only_for_fdiv_fsqrt_gen) include_instr = new[1] ($urandom_range(1) ? {FDIV_S} : {FSQRT_S}); end @@ -830,6 +831,17 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; instr_list[$].comment = {instr_list[$].comment, $sformatf(" [WFI Insertion] ")}; endfunction: insert_wfi_instr + // add illegal + virtual function void insert_illegal_instr(); + riscv_instr illegal_instr; + illegal_instr = new riscv_instr::get_rand_instr( + .include_instr({NOP}) // create a placholder insn + ); + illegal_instr.is_illegal_instr = 1; // tag this as illegal + instr_list.push_back(illegal_instr); + instr_list[$].comment = {instr_list[$].comment, $sformatf(" [Illegal Insertion] ")}; + endfunction: insert_illegal_instr + // for overriding direct instr operands with previous instruc rd/fd virtual function void f_use_prev_rd_on_next_operands( riscv_instr p_instr=null, diff --git a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_instr_for_func_cvg_lib.sv b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_instr_for_func_cvg_lib.sv index 0c5b67e515..a92d0fd572 100644 --- a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_instr_for_func_cvg_lib.sv +++ b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_instr_for_func_cvg_lib.sv @@ -1,5 +1,5 @@ /* - * Copyright 2023 Dolphin Design + * Copyright 2024 Dolphin Design * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -16,7 +16,9 @@ */ // [Dolphin Design updates] -// This file contains stream classes that use to generate streams that improve functional coverage holes +// Note: +// 1) This file contains streams that use to improve functional coverage holes +// 2) They are optional to be included in regression list // this stream is to improve func coverage for in uvme_interrupt_covg_v2 by cycle through all cv_* instructions multiple times for irq and wfi coverage purpose - START class cv32e40p_cv_instrs_multi_loops_streams extends cv32e40p_float_zfinx_base_instr_stream; @@ -43,7 +45,7 @@ class cv32e40p_cv_instrs_multi_loops_streams extends cv32e40p_float_zfinx_base_i reset_rand_instr_entry(); include_group = new[1] ({RV32X}); - exclude_instr = new[9] ({CV_START, CV_STARTI, CV_END, CV_ENDI, CV_COUNT, CV_COUNTI, CV_SETUP, CV_SETUPI, CV_ELW}); // TBD: exclude hwloop and cluster insn from wfi cg + exclude_instr = new[9] ({CV_START, CV_STARTI, CV_END, CV_ENDI, CV_COUNT, CV_COUNTI, CV_SETUP, CV_SETUPI, CV_ELW}); // these already covered in all cvg, can be ignored meantime - Start (note: users can modify this to focus on insn list to b ecovered) ignored_instr_cnt = 4; @@ -181,3 +183,67 @@ class cv32e40p_cv_instrs_w_wfi_multi_loops_streams extends cv32e40p_cv_instrs_mu endclass: cv32e40p_cv_instrs_w_wfi_multi_loops_streams // this stream is to improve func coverage for in uvme_interrupt_covg_v2 by cycle through all cv_* instructions multiple times for irq and wfi coverage purpose - END + +// this stream is to improve func coverage for in uvme_rv32x_hwloop_covg - START +class cv32e40p_xpulp_single_hwloop_stream_directed extends cv32e40p_xpulp_hwloop_base_stream; + + `uvm_object_utils(cv32e40p_xpulp_single_hwloop_stream_directed) + `uvm_object_new + + constraint gen_hwloop_count_c { + solve num_loops_active before gen_nested_loop; + solve gen_nested_loop before hwloop_count, hwloop_counti; + solve num_hwloop_instr before hwloop_count, hwloop_counti; + gen_nested_loop == 0; + num_loops_active == 1; + foreach(hwloop_count[i]) { + if (num_hwloop_instr[i] == 3) { + hwloop_count[i] == 4095; + } + else { + hwloop_count[i] inside {401, 1024}; + } + hwloop_counti[i] == hwloop_count[i]; + } + } + + constraint no_imm_hwloop_setup_instr_c { + use_loop_counti_inst[0] == 0; + use_loop_counti_inst[1] == 0; + use_loop_setupi_inst[0] == 0; + use_loop_setupi_inst[1] == 0; + } + + constraint num_hwloop_instr_c { + foreach (num_hwloop_instr[i]) { + num_hwloop_instr[i] dist { 3 := 1, 3074 := 5, 4092 := 1 }; + num_fill_instr_loop_ctrl_to_loop_start[i] inside {[0:7]}; + } + num_fill_instr_in_loop1_till_loop0_setup == 0; + } + +endclass : cv32e40p_xpulp_single_hwloop_stream_directed +// this stream is to improve func coverage for in uvme_rv32x_hwloop_covg - END + +// this stream is to improve func coverage for in uvme_debug_covg - START +class cv32e40p_fp_only_fdiv_fsqrt_stream extends cv32e40p_fp_n_mixed_instr_stream; + + `uvm_object_utils(cv32e40p_fp_only_fdiv_fsqrt_stream) + `uvm_object_new + + function void pre_randomize(); + super.pre_randomize(); + use_fp_only_for_directed_instr = 1; + use_only_for_fdiv_fsqrt_gen = 1; + en_clr_fflags_af_instr = 0; + endfunction: pre_randomize + + virtual function void add_instr_prior_directed_instr(riscv_instr instr, int idx=0); + if ($test$plusargs("add_b2b_illegal_insn")) begin + insert_illegal_instr(); + end + super.add_instr_prior_directed_instr(instr, idx); + endfunction : add_instr_prior_directed_instr + +endclass: cv32e40p_fp_only_fdiv_fsqrt_stream +// this stream is to improve func coverage for in uvme_debug_covg - END diff --git a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv index c496886201..c392c999dc 100644 --- a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv +++ b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv @@ -505,8 +505,9 @@ class cv32e40p_xpulp_hwloop_base_stream extends cv32e40p_xpulp_rand_stream; num_fill_instr_in_loop1_till_loop0_setup = num_fill_instr_in_loop1_till_loop0_setup-1; - if(num_fill_instr_in_loop1_till_loop0_setup>0) + if(num_fill_instr_in_loop1_till_loop0_setup>0) begin insert_rand_instr(num_fill_instr_in_loop1_till_loop0_setup); + end end else begin set_label_at_next_instr = 1; //no fill instr so next instr must have label @@ -536,8 +537,9 @@ class cv32e40p_xpulp_hwloop_base_stream extends cv32e40p_xpulp_rand_stream; //reserved_rd = {hwloop_avail_regs[2]}; //preserve count0 reg for nested loop - if(!use_setup_inst[0]) + if(!use_setup_inst[0]) begin insert_rand_instr(num_fill_instr_loop_ctrl_to_loop_start[0]); + end //LABEL HWLOOP0_NESTED_START: label_s = $sformatf("hwloop0_nested_start_stream%0d",stream_count); @@ -620,7 +622,6 @@ class cv32e40p_xpulp_hwloop_base_stream extends cv32e40p_xpulp_rand_stream; .set_label_for_first_instr(1), .str_lbl_str(start_label_s), .end_lbl_str(end_label_s), - .instr_label(label_s)); //Insert Random instructions till Loop HWLOOP_START0/1 label -> use_setup_inst ? 0 : num_fill_instr_loop_ctrl_to_loop_start[0/1] if(!use_setup_inst[hwloop_L]) @@ -1283,21 +1284,21 @@ class cv32e40p_xpulp_short_hwloop_stream_directed extends cv32e40p_xpulp_short_h // due to long run times if(gen_nested_loop) { if(loop0_high_count) { - hwloop_counti[0] dist {[1024:4094] := 50, 4095 := 5}; - hwloop_count[0] dist {[1024:4094] := 50, 4095 := 5}; + hwloop_counti[0] dist {[1024:4094] := 15, 4095 := 5}; + hwloop_count[0] dist {[1024:4094] := 15, 4095 := 5}; hwloop_counti[1] inside {[1:2]}; hwloop_count[1] inside {[1:2]}; } else { hwloop_counti[0] inside {[1:2]}; hwloop_count[0] inside {[1:2]}; - hwloop_counti[1] dist {[1024:4094] := 50, 4095 := 5}; - hwloop_count[1] dist {[1024:4094] := 50, 4095 := 5}; + hwloop_counti[1] dist {[1024:4094] := 15, 4095 := 5}; + hwloop_count[1] dist {[1024:4094] := 15, 4095 := 5}; } } else { foreach(hwloop_counti[i]) - hwloop_counti[i] dist {[1024:4094] := 50, 4095 := 5}; + hwloop_counti[i] dist {[1024:4094] := 15, 4095 := 5}; foreach(hwloop_count[i]) - hwloop_count[i] dist {[1024:4094] := 50, 4095 := 5}; + hwloop_count[i] dist {[1024:4094] := 15, 4095 := 5}; } } diff --git a/cv32e40p/regress/cv32e40pv2_for_func_cvg_improvement.yaml b/cv32e40p/regress/cv32e40pv2_for_func_cvg_improvement.yaml index 005d6a84f6..364b095b5b 100644 --- a/cv32e40p/regress/cv32e40pv2_for_func_cvg_improvement.yaml +++ b/cv32e40p/regress/cv32e40pv2_for_func_cvg_improvement.yaml @@ -1,9 +1,9 @@ -# Copyright 2023 Dolphin Design +# Copyright 2024 Dolphin Design # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 # Header name: cv32e40pv2_for_func_cvg_improvement -description: regression for CV32E40Pv2, focused on improving the functional coverage holes +description: regression for CV32E40Pv2, focus on improving the functional coverage holes # List of builds # cfg is set to pulp by default but can be overriden by arg command to any cfg. @@ -19,7 +19,7 @@ builds: dir: cv32e40p/sim/uvmt cfg: pulp -# List of tests + # List of tests (todo: all below tests have not run with Imperas ISS reference model) tests: corev_directed_for_interrupt_covg_test: build: uvmt_cv32e40p @@ -27,3 +27,30 @@ tests: dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test COREV=YES TEST=corev_directed_for_interrupt_covg_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000" num: 5 + + corev_directed_for_hwloop_covg_test: + description: This test is to improve func coverage holes in uvme_rv32x_hwloop_covg + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_for_hwloop_covg_test CFG_PLUSARGS="+UVM_TIMEOUT=60000000" + num: 5 + + corev_directed_fp_mulcyc_interleave_illegal_test_with_int_and_debug: + testname: corev_rand_fp_instr_debug + description: This test is to improve func coverage holes in uvme_debug_covg + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" VSIM_USER_FLAGS=+add_b2b_illegal_insn + test_cfg: gen_rand_int + skip_sim: pulp + num: 1 + + corev_directed_fp_mulcyc_test_with_int_and_debug: + testname: corev_rand_fp_instr_debug + description: This test is to improve func coverage holes in uvme_debug_covg + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" + test_cfg: gen_rand_int + skip_sim: pulp + num: 5 diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml index 6ec22adf6b..f16decb345 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml @@ -174,7 +174,7 @@ tests: description: fp instr random test with random interrupt and debug trigger build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" VSIM_USER_FLAGS=+gen_reduced_rand_dbg_req test_cfg: gen_rand_int,debug_single_step_en skip_sim: pulp @@ -202,7 +202,7 @@ tests: description: fp instr random test with random interrupt, debug trigger and single step build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" VSIM_USER_FLAGS=+gen_reduced_rand_dbg_req test_cfg: gen_rand_int,debug_trigger_basic,debug_single_step_en skip_sim: pulp @@ -273,7 +273,7 @@ tests: description: hwloop debug random test dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" - num: 1 + num: 2 corev_directed_pulp_hwloop_debug_ebreak: testname: corev_directed_pulp_hwloop_debug @@ -282,7 +282,7 @@ tests: dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: debug_ebreak - num: 1 + num: 2 corev_directed_pulp_hwloop_debug_trigger: testname: corev_directed_pulp_hwloop_debug @@ -291,7 +291,7 @@ tests: dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: debug_trigger_basic - num: 1 + num: 2 corev_directed_pulp_hwloop_debug_trigger_with_ebreak: testname: corev_directed_pulp_hwloop_debug @@ -300,7 +300,7 @@ tests: dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: debug_trigger_basic,debug_ebreak - num: 1 + num: 2 corev_directed_pulp_hwloop_debug_with_interrupt: testname: corev_directed_pulp_hwloop_debug @@ -309,7 +309,7 @@ tests: dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: gen_rand_int - num: 1 + num: 2 corev_directed_pulp_hwloop_debug_with_int_debug_trigger: testname: corev_directed_pulp_hwloop_debug @@ -318,7 +318,7 @@ tests: dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: gen_rand_int,debug_trigger_basic - num: 1 + num: 2 corev_directed_pulp_hwloop_debug_with_int_debug_ebreak: testname: corev_directed_pulp_hwloop_debug @@ -327,7 +327,7 @@ tests: dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: gen_rand_int,debug_ebreak - num: 1 + num: 2 # list of corev_directed_pulp_hwloop_debug - END @@ -360,7 +360,7 @@ tests: dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: gen_rand_debug_req - num: 1 + num: 2 corev_directed_pulp_hwloop_test_with_interrupt: testname: corev_directed_pulp_hwloop_test @@ -369,7 +369,7 @@ tests: dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: gen_rand_int - num: 1 + num: 2 # list of corev_directed_pulp_hwloop_test - END diff --git a/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/corev-dv.yaml b/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/corev-dv.yaml index c7c4d3e3b8..13dbd87705 100644 --- a/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/corev-dv.yaml +++ b/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/corev-dv.yaml @@ -8,21 +8,13 @@ uvm_test: $(CV_CORE_LC)_instr_base_test description: > RISCV-DV generated random fp instr with random debug plusargs: > - +instr_cnt=1000 + +instr_cnt=2000 +num_of_sub_program=0 - +insert_rand_directed_instr_stream=2 - +test_rand_directed_instr_stream_num=8 + +test_override_riscv_instr_stream=1 +directed_instr_0=cv32e40p_constraint_mc_fp_instr_stream,2 +directed_instr_1=cv32e40p_fp_op_fwd_instr_stream,2 +directed_instr_2=cv32e40p_fp_op_fwd_instr_w_loadstore_stream,2 - +rand_directed_instr_0=riscv_load_store_rand_instr_stream,1 - +rand_directed_instr_1=riscv_load_store_hazard_instr_stream,1 - +rand_directed_instr_2=riscv_multi_page_load_store_instr_stream,1 - +rand_directed_instr_3=riscv_jal_instr,1 - +rand_directed_instr_4=riscv_hazard_instr_stream,1 - +rand_directed_instr_5=cv32e40p_xpulp_simd_stream_test,1 - +rand_directed_instr_6=cv32e40p_xpulp_mac_stream_test,1 - +rand_directed_instr_7=riscv_int_numeric_corner_stream,1 + +directed_instr_3=cv32e40p_fp_only_fdiv_fsqrt_stream,5 +no_fence=0 +hint_instr_ratio=2 +no_data_page=0 diff --git a/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/test.yaml b/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/test.yaml index 14f38d205a..533e8dceed 100644 --- a/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/test.yaml +++ b/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/test.yaml @@ -7,4 +7,6 @@ uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c description: > Random debug in fp instruction stream plusargs: > - +gen_reduced_rand_dbg_req + +gen_random_debug + # +gen_reduced_rand_dbg_req -> produce not many dbg_req + # +gen_random_debug -> produce many dbg_req From 1512e0b48488ce4ff67d15db5407497590682fc8 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Mon, 26 Feb 2024 13:40:21 +0800 Subject: [PATCH 12/20] Sync file contents with short and long testlist Signed-off-by: dd-baoshan --- .../regress/cv32e40pv2_interrupt_debug.yaml | 460 ++++++++++++------ 1 file changed, 320 insertions(+), 140 deletions(-) diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml index 0c96228a56..647bdb3e01 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml @@ -21,171 +21,354 @@ builds: # List of tests tests: + # cv32e40pv2_interrupt_debug_long - START corev_rand_debug: build: uvmt_cv32e40p description: corev_rand_debug dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_debug CFG_PLUSARGS="+UVM_TIMEOUT=2000000" - num: 1 + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" corev_rand_debug_ebreak: build: uvmt_cv32e40p description: corev_rand_debug_ebreak dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_debug_ebreak CFG_PLUSARGS="+UVM_TIMEOUT=2000000" - num: 1 + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_debug_ebreak CFG_PLUSARGS="+UVM_TIMEOUT=30000000" corev_rand_debug_ebreak_xpulp: build: uvmt_cv32e40p description: corev_rand_debug_ebreak_xpulp dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_debug_ebreak_xpulp CFG_PLUSARGS="+UVM_TIMEOUT=10000000" - num: 1 + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_debug_ebreak_xpulp CFG_PLUSARGS="+UVM_TIMEOUT=30000000" corev_rand_debug_single_step: build: uvmt_cv32e40p description: corev_rand_debug_single_step dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_debug_single_step CFG_PLUSARGS="+UVM_TIMEOUT=10000000" - num: 1 + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_debug_single_step CFG_PLUSARGS="+UVM_TIMEOUT=30000000" corev_rand_debug_single_step_xpulp: build: uvmt_cv32e40p description: corev_rand_debug_single_step_xpulp dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_debug_single_step_xpulp CFG_PLUSARGS="+UVM_TIMEOUT=10000000" - num: 1 + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_debug_single_step_xpulp CFG_PLUSARGS="+UVM_TIMEOUT=30000000" corev_rand_interrupt: build: uvmt_cv32e40p description: corev_rand_interrupt dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt CFG_PLUSARGS="+UVM_TIMEOUT=10000000" - num: 1 + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt CFG_PLUSARGS="+UVM_TIMEOUT=30000000" corev_rand_interrupt_debug: build: uvmt_cv32e40p description: corev_rand_interrupt_debug dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_debug CFG_PLUSARGS="+UVM_TIMEOUT=2000000" - num: 1 + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" corev_rand_interrupt_exception: build: uvmt_cv32e40p description: corev_rand_interrupt_exception dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_exception CFG_PLUSARGS="+UVM_TIMEOUT=2000000" - num: 1 + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_exception CFG_PLUSARGS="+UVM_TIMEOUT=30000000" corev_rand_interrupt_nested: build: uvmt_cv32e40p description: corev_rand_interrupt_nested dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_nested CFG_PLUSARGS="+UVM_TIMEOUT=10000000" - num: 1 + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_nested CFG_PLUSARGS="+UVM_TIMEOUT=30000000" corev_rand_interrupt_wfi: build: uvmt_cv32e40p description: corev_rand_interrupt_wfi dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi CFG_PLUSARGS="+UVM_TIMEOUT=15000000" - num: 1 + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi CFG_PLUSARGS="+UVM_TIMEOUT=30000000" corev_rand_interrupt_wfi_mem_stress: build: uvmt_cv32e40p description: corev_rand_interrupt_wfi_mem_stress dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi_mem_stress CFG_PLUSARGS="+UVM_TIMEOUT=50000000" - num: 1 - debug_test: +# list of corev_rand_pulp_hwloop_debug - START + + corev_rand_pulp_hwloop_debug_single_step: + testname: corev_rand_pulp_hwloop_debug + description: hwloop single-step debug random test build: uvmt_cv32e40p - description: debug_test (adapted from v1) dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=debug_test CFG_PLUSARGS="+UVM_TIMEOUT=20000000" - num: 1 + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: debug_single_step_en - debug_test_boot_set: + corev_rand_pulp_hwloop_debug_trigger_with_single_step: + testname: corev_rand_pulp_hwloop_debug + description: hwloop debug random test with debug trigger and single step build: uvmt_cv32e40p - description: debug_test_boot_set (adapted from v1) dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=debug_test_boot_set CFG_PLUSARGS="+UVM_TIMEOUT=20000000" VSIM_USER_FLAGS=+fixed_instr_gnt_stall=10 - seed: 1 - num: 1 + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: debug_trigger_basic,debug_single_step_en - debug_test_known_miscompares: + corev_rand_pulp_hwloop_debug_with_int_debug_trigger_and_ebreak: + testname: corev_rand_pulp_hwloop_debug + description: hwloop debug with interrupt, debug trigger and ebreak random test build: uvmt_cv32e40p - description: debug_test_known_miscompares (adapted from v1) dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=debug_test_known_miscompares CFG_PLUSARGS="+UVM_TIMEOUT=20000000" - num: 1 + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: gen_rand_int,debug_trigger_basic,debug_ebreak - debug_test_reset: + corev_rand_pulp_hwloop_debug_with_int_debug_trigger_single_step: + testname: corev_rand_pulp_hwloop_debug + description: hwloop debug with interrupt, debug trigger and single step random test build: uvmt_cv32e40p - description: debug_test_reset (adapted from v1) dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=debug_test_reset CFG_PLUSARGS="+UVM_TIMEOUT=20000000" - num: 1 + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: gen_rand_int,debug_trigger_basic,debug_single_step_en - debug_test_reset: +# list of corev_rand_pulp_hwloop_debug - END + +# list of corev_directed_pulp_hwloop_debug - START + + corev_directed_pulp_hwloop_debug_single_step: + testname: corev_directed_pulp_hwloop_debug + description: hwloop single-step debug random test build: uvmt_cv32e40p - description: debug_test_reset (adapted from v1) dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=debug_test_reset CFG_PLUSARGS="+UVM_TIMEOUT=20000000" + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: debug_single_step_en num: 1 - interrupt_test: + corev_directed_pulp_hwloop_debug_trigger_with_single_step: + testname: corev_directed_pulp_hwloop_debug + description: hwloop debug random test with debug trigger and single step build: uvmt_cv32e40p - description: interrupt_test (adapted from v1) dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=interrupt_test CFG_PLUSARGS="+UVM_TIMEOUT=20000000" + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: debug_trigger_basic,debug_single_step_en num: 1 - interrupt_bootstrap: + corev_directed_pulp_hwloop_debug_with_int_debug_trigger_and_ebreak: + testname: corev_directed_pulp_hwloop_debug + description: hwloop debug with interrupt, debug trigger and ebreak random test build: uvmt_cv32e40p - description: interrupt_bootstrap (adapted from v1) dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=interrupt_bootstrap CFG_PLUSARGS="+UVM_TIMEOUT=20000000" + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: gen_rand_int,debug_trigger_basic,debug_ebreak num: 1 - riscv_ebreak_test_0: + corev_directed_pulp_hwloop_debug_with_int_debug_trigger_single_step: + testname: corev_directed_pulp_hwloop_debug + description: hwloop debug with interrupt, debug trigger and single step random test build: uvmt_cv32e40p - description: riscv_ebreak_test_0 (adapted from v1) dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=riscv_ebreak_test_0 CFG_PLUSARGS="+UVM_TIMEOUT=20000000" + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: gen_rand_int,debug_trigger_basic,debug_single_step_en num: 1 - corev_rand_pulp_instr_ebreak_debug_test: +# list of corev_directed_pulp_hwloop_debug - END + + corev_rand_pulp_hwloop_exception_single_step_debug: + testname: corev_rand_pulp_hwloop_exception + description: hwloop exception test with single step debug + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: debug_single_step_en + + corev_rand_pulp_hwloop_exception_with_int_debug_trigger: + testname: corev_rand_pulp_hwloop_exception + description: hwloop exception test with interrupt and debug trigger + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: gen_rand_int,debug_trigger_basic + + # cv32e40pv2_interrupt_debug_long - END + + # cv32e40pv2_interrupt_debug_short - START + corev_rand_pulp_instr_random_debug_test: testname: corev_rand_pulp_instr_test + description: pulp instr test with random debug halt req + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_debug_req + + corev_rand_pulp_instr_ebreak_debug_test: + testname: corev_rand_pulp_instr_debug description: pulp rand test with ebreak debug build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=5000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" test_cfg: debug_ebreak corev_rand_pulp_instr_single_step_debug_test: - testname: corev_rand_pulp_instr_test + testname: corev_rand_pulp_instr_debug description: pulp rand test with single-step debug build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=5000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" test_cfg: debug_single_step_en corev_rand_pulp_instr_debug_trigger_test: - testname: corev_rand_pulp_instr_test + testname: corev_rand_pulp_instr_debug description: pulp rand test with debug trigger build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=5000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" test_cfg: debug_trigger_basic + corev_rand_pulp_instr_debug_trigger_with_ebreak: + testname: corev_rand_pulp_instr_debug + description: pulp rand test with debug trigger and ebreak + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: debug_trigger_basic,debug_ebreak + + corev_rand_pulp_instr_debug_trigger_with_single_step: + testname: corev_rand_pulp_instr_debug + description: pulp rand test with debug trigger and single step + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: debug_trigger_basic,debug_single_step_en + + corev_rand_pulp_instr_debug_trigger_with_random_debug_req: + testname: corev_rand_pulp_instr_test + description: pulp rand test with debug trigger and random debug req + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: debug_trigger_basic,gen_rand_debug_req + + corev_rand_pulp_instr_debug_ebreak_with_random_debug_req: + testname: corev_rand_pulp_instr_test + description: pulp rand test with debug ebreak and random debug req + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: debug_ebreak,gen_rand_debug_req + + corev_rand_pulp_instr_debug_single_step_with_random_debug_req: + testname: corev_rand_pulp_instr_test + description: pulp rand test with debug ebreak and random debug req + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: debug_single_step_en,gen_rand_debug_req + corev_rand_pulp_instr_interrupt_test: testname: corev_rand_pulp_instr_test description: pulp instr test with random interrupts build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=5000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int + + corev_rand_pulp_instr_interrupt_debug_test: + testname: corev_rand_pulp_instr_test + description: pulp instr test with random interrupts and debug halt req + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int,gen_rand_debug_req + + corev_rand_pulp_instr_debug_test_with_int_and_debug_trigger: + testname: corev_rand_pulp_instr_debug + description: pulp instr random test with random interrupt and debug trigger + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int,debug_trigger_basic + + corev_rand_pulp_instr_debug_test_with_int_and_debug_single_step: + testname: corev_rand_pulp_instr_debug + description: pulp instr random test with random interrupt and debug trigger + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int,debug_single_step_en + + corev_rand_pulp_instr_debug_test_with_int_and_debug_ebreak: + testname: corev_rand_pulp_instr_debug + description: pulp instr random test with random interrupt and debug ebreak + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int,debug_ebreak + + corev_rand_pulp_instr_debug_test_with_int_debug_trigger_and_ebreak: + testname: corev_rand_pulp_instr_debug + description: pulp instr random test with random interrupt, debug trigger and debug ebreak + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int,debug_trigger_basic,debug_ebreak + + corev_rand_pulp_instr_debug_test_with_int_debug_trigger_and_single_step: + testname: corev_rand_pulp_instr_debug + description: pulp instr random test with random interrupt, debug trigger and single step + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int,debug_trigger_basic,debug_single_step_en + +# Add corev_rand_fp_instr_debug similar to corev_rand_pulp_instr_debug/test with f/zfinx insn included - START + + corev_rand_fp_instr_debug_test_with_int_and_debug: + testname: corev_rand_fp_instr_debug + description: fp instr random test with random interrupt and debug trigger + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" test_cfg: gen_rand_int + skip_sim: pulp + + corev_rand_fp_instr_debug_test_with_int_and_debug_trigger: + testname: corev_rand_fp_instr_debug + description: fp instr random test with random interrupt and debug trigger + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int,debug_trigger_basic + skip_sim: pulp + + corev_rand_fp_instr_debug_test_with_int_and_debug_single_step: + testname: corev_rand_fp_instr_debug + description: fp instr random test with random interrupt and debug trigger + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" VSIM_USER_FLAGS=+gen_reduced_rand_dbg_req + test_cfg: gen_rand_int,debug_single_step_en + skip_sim: pulp + +# note: current fp streams excluding ebreak insn +# corev_rand_fp_instr_debug_test_with_int_and_debug_ebreak: +# testname: corev_rand_fp_instr_debug +# description: pulp instr random test with random interrupt and debug ebreak +# build: uvmt_cv32e40p +# dir: cv32e40p/sim/uvmt +# cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" +# test_cfg: gen_rand_int,debug_ebreak +# skip_sim: pulp +# +# corev_rand_fp_instr_debug_test_with_int_debug_trigger_and_ebreak: +# testname: corev_rand_fp_instr_debug +# description: pulp instr random test with random interrupt, debug trigger and debug ebreak +# build: uvmt_cv32e40p +# dir: cv32e40p/sim/uvmt +# cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" +# test_cfg: gen_rand_int,debug_trigger_basic,debug_ebreak +# skip_sim: pulp + + corev_rand_fp_instr_debug_test_with_int_debug_trigger_and_single_step: + testname: corev_rand_fp_instr_debug + description: fp instr random test with random interrupt, debug trigger and single step + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" VSIM_USER_FLAGS=+gen_reduced_rand_dbg_req + test_cfg: gen_rand_int,debug_trigger_basic,debug_single_step_en + skip_sim: pulp + +# Add corev_rand_fp_instr_debug similar to corev_rand_pulp_instr_debug with f/zfinx insn included - END # list of corev_rand_pulp_hwloop_debug - START @@ -193,31 +376,22 @@ tests: build: uvmt_cv32e40p description: hwloop debug random test dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" corev_rand_pulp_hwloop_debug_ebreak: testname: corev_rand_pulp_hwloop_debug description: hwloop ebreak debug random test build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: debug_ebreak - corev_rand_pulp_hwloop_debug_single_step: - testname: corev_rand_pulp_hwloop_debug - description: hwloop single-step debug random test - build: uvmt_cv32e40p - dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" - test_cfg: debug_single_step_en - num: 1 - corev_rand_pulp_hwloop_debug_trigger: testname: corev_rand_pulp_hwloop_debug description: hwloop debug random test with debug trigger on instr addr match build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: debug_trigger_basic corev_rand_pulp_hwloop_debug_trigger_with_ebreak: @@ -225,24 +399,15 @@ tests: description: hwloop debug random test with debug trigger and ebreak build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: debug_trigger_basic,debug_ebreak - corev_rand_pulp_hwloop_debug_trigger_with_single_step: - testname: corev_rand_pulp_hwloop_debug - description: hwloop debug random test with debug trigger and single step - build: uvmt_cv32e40p - dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" - test_cfg: debug_trigger_basic,debug_single_step_en - num: 1 - corev_rand_pulp_hwloop_debug_with_interrupt: testname: corev_rand_pulp_hwloop_debug description: hwloop debug with interrupt random test build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: gen_rand_int corev_rand_pulp_hwloop_debug_with_int_debug_trigger: @@ -250,17 +415,16 @@ tests: description: hwloop debug with interrupt and debug trigger random test build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: gen_rand_int,debug_trigger_basic - corev_rand_pulp_hwloop_debug_with_int_debug_trigger_single_step: + corev_rand_pulp_hwloop_debug_with_int_debug_ebreak: testname: corev_rand_pulp_hwloop_debug - description: hwloop debug with interrupt, debug trigger and single step random test + description: hwloop debug with interrupt and debug ebreak random test build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" - test_cfg: gen_rand_int,debug_trigger_basic,debug_single_step_en - num: 1 + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: gen_rand_int,debug_ebreak # list of corev_rand_pulp_hwloop_debug - END @@ -270,92 +434,74 @@ tests: build: uvmt_cv32e40p description: hwloop debug random test dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" - num: 1 + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + num: 2 corev_directed_pulp_hwloop_debug_ebreak: testname: corev_directed_pulp_hwloop_debug description: hwloop ebreak debug random test build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: debug_ebreak - num: 1 - - corev_directed_pulp_hwloop_debug_single_step: - testname: corev_directed_pulp_hwloop_debug - description: hwloop single-step debug random test - build: uvmt_cv32e40p - dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" - test_cfg: debug_single_step_en - num: 1 + num: 2 corev_directed_pulp_hwloop_debug_trigger: testname: corev_directed_pulp_hwloop_debug description: hwloop debug random test with debug trigger on instr addr match build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: debug_trigger_basic - num: 1 + num: 2 corev_directed_pulp_hwloop_debug_trigger_with_ebreak: testname: corev_directed_pulp_hwloop_debug description: hwloop debug random test with debug trigger and ebreak build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: debug_trigger_basic,debug_ebreak - num: 1 - - corev_directed_pulp_hwloop_debug_trigger_with_single_step: - testname: corev_directed_pulp_hwloop_debug - description: hwloop debug random test with debug trigger and single step - build: uvmt_cv32e40p - dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" - test_cfg: debug_trigger_basic,debug_single_step_en - num: 1 + num: 2 corev_directed_pulp_hwloop_debug_with_interrupt: testname: corev_directed_pulp_hwloop_debug description: hwloop debug with interrupt random test build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: gen_rand_int - num: 1 + num: 2 corev_directed_pulp_hwloop_debug_with_int_debug_trigger: testname: corev_directed_pulp_hwloop_debug description: hwloop debug with interrupt and debug trigger random test build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: gen_rand_int,debug_trigger_basic - num: 1 + num: 2 - corev_directed_pulp_hwloop_debug_with_int_debug_trigger_single_step: + corev_directed_pulp_hwloop_debug_with_int_debug_ebreak: testname: corev_directed_pulp_hwloop_debug - description: hwloop debug with interrupt, debug trigger and single step random test + description: hwloop debug with interrupt and debug ebreak random test build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" - test_cfg: gen_rand_int,debug_trigger_basic,debug_single_step_en - num: 1 + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: gen_rand_int,debug_ebreak + num: 2 # list of corev_directed_pulp_hwloop_debug - END # list of corev_rand_pulp_hwloop_test - START - corev_rand_pulp_hwloop_test_interrupt: + corev_rand_pulp_hwloop_test_with_random_debug: testname: corev_rand_pulp_hwloop_test - description: hwloop test with random interrupts + description: hwloop random debug req test build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=40000000" - test_cfg: gen_rand_int + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: gen_rand_debug_req corev_rand_pulp_hwloop_interrupt_test: testname: corev_rand_pulp_hwloop_test @@ -376,7 +522,7 @@ tests: dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: gen_rand_debug_req - num: 1 + num: 2 corev_directed_pulp_hwloop_test_with_interrupt: testname: corev_directed_pulp_hwloop_test @@ -385,7 +531,7 @@ tests: dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: gen_rand_int - num: 1 + num: 2 # list of corev_directed_pulp_hwloop_test - END @@ -396,27 +542,61 @@ tests: cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_in_debug_rom CFG_PLUSARGS="+UVM_TIMEOUT=30000000" num: 4 - corev_rand_pulp_hwloop_exception_single_step_debug: + corev_rand_pulp_hwloop_exception_debug_trigger: testname: corev_rand_pulp_hwloop_exception - description: hwloop exception test with single step debug + description: hwloop exception test with debug trigger build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=20000000" - test_cfg: debug_single_step_en + test_cfg: debug_trigger_basic,gen_limit_debug_req + + debug_test: + build: uvmt_cv32e40p + description: debug_test (adapted from v1) + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=debug_test CFG_PLUSARGS="+UVM_TIMEOUT=20000000" num: 1 - corev_rand_pulp_hwloop_exception_debug_trigger: - testname: corev_rand_pulp_hwloop_exception - description: hwloop exception test with debug trigger + debug_test_boot_set: build: uvmt_cv32e40p + description: debug_test_boot_set (adapted from v1) dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=20000000" - test_cfg: debug_trigger_basic + cmd: make test COREV=YES TEST=debug_test_boot_set CFG_PLUSARGS="+UVM_TIMEOUT=20000000" VSIM_USER_FLAGS=+fixed_instr_gnt_stall=10 + seed: 1 + num: 1 - corev_rand_pulp_hwloop_exception_with_int_debug_trigger: - testname: corev_rand_pulp_hwloop_exception - description: hwloop exception test with interrupt and debug trigger + debug_test_known_miscompares: build: uvmt_cv32e40p + description: debug_test_known_miscompares (adapted from v1) dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=20000000" - test_cfg: gen_rand_int,debug_trigger_basic + cmd: make test COREV=YES TEST=debug_test_known_miscompares CFG_PLUSARGS="+UVM_TIMEOUT=20000000" + num: 1 + + debug_test_reset: + build: uvmt_cv32e40p + description: debug_test_reset (adapted from v1) + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=debug_test_reset CFG_PLUSARGS="+UVM_TIMEOUT=20000000" + num: 1 + + interrupt_test: + build: uvmt_cv32e40p + description: interrupt_test (adapted from v1) + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=interrupt_test CFG_PLUSARGS="+UVM_TIMEOUT=20000000" + num: 1 + + interrupt_bootstrap: + build: uvmt_cv32e40p + description: interrupt_bootstrap (adapted from v1) + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=interrupt_bootstrap CFG_PLUSARGS="+UVM_TIMEOUT=20000000" + num: 1 + + riscv_ebreak_test_0: + build: uvmt_cv32e40p + description: riscv_ebreak_test_0 (adapted from v1) + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=riscv_ebreak_test_0 CFG_PLUSARGS="+UVM_TIMEOUT=20000000" + num: 1 + # cv32e40pv2_interrupt_debug_short - END From bbfbc3cf5a02fdc1aab6579fd8b13856e9731fcb Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Mon, 26 Feb 2024 13:42:29 +0800 Subject: [PATCH 13/20] Add and Update tests to improve tb functional coverage holes (uvme_debug_covg) Signed-off-by: dd-baoshan --- .../corev-dv.yaml | 29 +++++++++++++++++++ .../test.yaml | 9 ++++++ 2 files changed, 38 insertions(+) create mode 100644 cv32e40p/tests/programs/corev-dv/corev_directed_for_hwloop_covg_test/corev-dv.yaml create mode 100644 cv32e40p/tests/programs/corev-dv/corev_directed_for_hwloop_covg_test/test.yaml diff --git a/cv32e40p/tests/programs/corev-dv/corev_directed_for_hwloop_covg_test/corev-dv.yaml b/cv32e40p/tests/programs/corev-dv/corev_directed_for_hwloop_covg_test/corev-dv.yaml new file mode 100644 index 0000000000..d1ec3aa3d3 --- /dev/null +++ b/cv32e40p/tests/programs/corev-dv/corev_directed_for_hwloop_covg_test/corev-dv.yaml @@ -0,0 +1,29 @@ +# Copyright 2023 Dolphin Design +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +# Test definition YAML for corev-dv test generator +# corev-dv generator test +name: corev_directed_for_hwloop_covg_test +uvm_test: $(CV_CORE_LC)_instr_base_test +description: > + This test is to improve func coverage holes in uvme_rv32x_hwloop_covg +plusargs: > + +instr_cnt=1000 + +num_of_sub_program=0 + +insert_rand_directed_instr_stream=1 + +test_rand_directed_instr_stream_num=2 + +rand_directed_instr_0=cv32e40p_xpulp_single_hwloop_stream_directed,1 + +rand_directed_instr_1=cv32e40p_xpulp_single_hwloop_stream_directed,1 + +no_fence=0 + +no_data_page=0 + +randomize_csr=1 + +no_branch_jump=1 + +boot_mode=m + +no_csr_instr=0 + +no_wfi=1 + +no_ebreak=1 + +no_dret=1 + +enable_misaligned_instr=0 + +set_dcsr_ebreak=0 + +test_override_riscv_instr_stream=1 + +test_override_riscv_instr_sequence=1 diff --git a/cv32e40p/tests/programs/corev-dv/corev_directed_for_hwloop_covg_test/test.yaml b/cv32e40p/tests/programs/corev-dv/corev_directed_for_hwloop_covg_test/test.yaml new file mode 100644 index 0000000000..197d9aedda --- /dev/null +++ b/cv32e40p/tests/programs/corev-dv/corev_directed_for_hwloop_covg_test/test.yaml @@ -0,0 +1,9 @@ +# Copyright 2023 Dolphin Design +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +# Test definition YAML for random pulp hwloop test +name: corev_directed_for_hwloop_covg_test +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +description: > + This test is to improve func coverage holes in uvme_rv32x_hwloop_covg +plusargs: > From e2844b845d91accc09ed0c75b0d725bdef5693db Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Mon, 26 Feb 2024 13:44:18 +0800 Subject: [PATCH 14/20] Add functional coverage exclusion file - debug Signed-off-by: dd-baoshan --- .../vsim/exclusion/cv32e40pv2_func_uvme_debug_waiver.do | 6 ++++++ cv32e40p/sim/tools/vsim/exclusion/pulp/exclusion.do | 3 +++ cv32e40p/sim/tools/vsim/exclusion/pulp_fpu/exclusion.do | 3 +++ 3 files changed, 12 insertions(+) create mode 100644 cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_func_uvme_debug_waiver.do diff --git a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_func_uvme_debug_waiver.do b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_func_uvme_debug_waiver.do new file mode 100644 index 0000000000..1fc6fb73d3 --- /dev/null +++ b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_func_uvme_debug_waiver.do @@ -0,0 +1,6 @@ +coverage exclude -cvgpath {/uvme_cv32e40p_pkg/uvme_debug_covg/cg_debug_with_xpulp_inst/\/uvme_cv32e40p_pkg::uvme_debug_covg::cg_debug_with_xpulp_inst /cr_dbg_req_at_xpulp_instr/} -comment {note: this waiver is not applicable for pulp_cluster config. elw is currently not tested thoroughly in non-cluster config tb} +coverage exclude -cvgpath {/uvme_cv32e40p_pkg/uvme_debug_covg/cg_debug_with_xpulp_inst/\/uvme_cv32e40p_pkg::uvme_debug_covg::cg_debug_with_xpulp_inst /cr_dbg_req_at_xpulp_instr/} -comment {note: this waiver is not applicable for pulp_cluster config. elw is currently not tested thoroughly in non-cluster config tb} +coverage exclude -cvgpath {/uvme_cv32e40p_pkg/uvme_debug_covg/cg_debug_with_xpulp_inst/\/uvme_cv32e40p_pkg::uvme_debug_covg::cg_debug_with_xpulp_inst /cr_trigger_with_xpulp_instr/} -comment {note: this waiver is not applicable for pulp_cluster config. elw is currently not tested thoroughly in non-cluster config tb} +coverage exclude -cvgpath {/uvme_cv32e40p_pkg/uvme_debug_covg/cg_debug_with_xpulp_inst/\/uvme_cv32e40p_pkg::uvme_debug_covg::cg_debug_with_xpulp_inst /cr_trigger_with_xpulp_instr/} -comment {note: this waiver is not applicable for pulp_cluster config. elw is currently not tested thoroughly in non-cluster config tb} +coverage exclude -cvgpath {/uvme_cv32e40p_pkg/uvme_debug_covg/cg_debug_with_xpulp_inst/\/uvme_cv32e40p_pkg::uvme_debug_covg::cg_debug_with_xpulp_inst /cr_dbg_single_step_xpulp_instr/} -comment {note: this waiver is not applicable for pulp_cluster config. elw is currently not tested thoroughly in non-cluster config tb} +coverage exclude -cvgpath {/uvme_cv32e40p_pkg/uvme_debug_covg/cg_debug_with_xpulp_inst/\/uvme_cv32e40p_pkg::uvme_debug_covg::cg_debug_with_xpulp_inst /cr_xpulp_instructions_in_dbg_mode/} -comment {note: this waiver is not applicable for pulp_cluster config. elw is currently not tested thoroughly in non-cluster config tb} diff --git a/cv32e40p/sim/tools/vsim/exclusion/pulp/exclusion.do b/cv32e40p/sim/tools/vsim/exclusion/pulp/exclusion.do index 02450809f4..ba5f1e50b7 100644 --- a/cv32e40p/sim/tools/vsim/exclusion/pulp/exclusion.do +++ b/cv32e40p/sim/tools/vsim/exclusion/pulp/exclusion.do @@ -4,6 +4,9 @@ do ../cv32e40pv2_func_asrt_n_directive_waiver.do # functional: uvme_interrupt_covg_v2 do ../cv32e40pv2_func_uvme_interrupt_waiver.do +# functional: uvme_debug_covg +do ../cv32e40pv2_func_uvme_debug_waiver.do + # code coverage : common waiver do ../cv32e40pv2_code_all_cfg_waiver.do diff --git a/cv32e40p/sim/tools/vsim/exclusion/pulp_fpu/exclusion.do b/cv32e40p/sim/tools/vsim/exclusion/pulp_fpu/exclusion.do index 34b74c435d..a65e045f6e 100644 --- a/cv32e40p/sim/tools/vsim/exclusion/pulp_fpu/exclusion.do +++ b/cv32e40p/sim/tools/vsim/exclusion/pulp_fpu/exclusion.do @@ -4,5 +4,8 @@ do ../cv32e40pv2_func_asrt_n_directive_waiver.do # functional: uvme_interrupt_covg_v2 do ../cv32e40pv2_func_uvme_interrupt_waiver.do +# functional: uvme_debug_covg +do ../cv32e40pv2_func_uvme_debug_waiver.do + # code coverage : common waiver do ../cv32e40pv2_code_all_cfg_waiver.do From a8956c8bce1f2c4b62f66f9798da51d07aadf649 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Mon, 26 Feb 2024 13:55:15 +0800 Subject: [PATCH 15/20] Remove fixme Signed-off-by: dd-baoshan --- cv32e40p/env/uvme/cov/uvme_debug_covg.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cv32e40p/env/uvme/cov/uvme_debug_covg.sv b/cv32e40p/env/uvme/cov/uvme_debug_covg.sv index 8a5e89109c..af949ae3ad 100644 --- a/cv32e40p/env/uvme/cov/uvme_debug_covg.sv +++ b/cv32e40p/env/uvme/cov/uvme_debug_covg.sv @@ -528,7 +528,7 @@ class uvme_debug_covg extends uvm_component; cr_dbg_while_multi_cyc_f_A : cross cp_apu_req_valid, cp_apu_grant_valid, cp_dbg_req; cr_dbg_while_multi_cyc_f_B : cross cp_apu_busy, cp_dbg_req; - // debug_halt_req with irq during multi cycle fp inst (fixme: what is the benefit cross with this irq?) + // debug_halt_req with irq during multi cycle fp inst cr_dbg_irq_while_multi_cyc_f_A : cross cp_apu_req_valid, cp_apu_grant_valid, cp_dbg_req, cp_irq { bins irq_grp_upper16_multi_cyc_f_A = binsof(cp_dbg_req.dbg_req_active) && binsof(cp_apu_grant_valid) && ( binsof(cp_irq.irq_31_trans_0_to_1) || binsof(cp_irq.irq_30_trans_0_to_1) || From e03f249f9314504470fd2c640637b847bbb666b4 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Mon, 26 Feb 2024 14:58:06 +0800 Subject: [PATCH 16/20] Change to fixme comments Signed-off-by: dd-baoshan --- .../exclusion/cv32e40pv2_func_uvme_debug_waiver.do | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_func_uvme_debug_waiver.do b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_func_uvme_debug_waiver.do index 1fc6fb73d3..14f406de24 100644 --- a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_func_uvme_debug_waiver.do +++ b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_func_uvme_debug_waiver.do @@ -1,6 +1,6 @@ -coverage exclude -cvgpath {/uvme_cv32e40p_pkg/uvme_debug_covg/cg_debug_with_xpulp_inst/\/uvme_cv32e40p_pkg::uvme_debug_covg::cg_debug_with_xpulp_inst /cr_dbg_req_at_xpulp_instr/} -comment {note: this waiver is not applicable for pulp_cluster config. elw is currently not tested thoroughly in non-cluster config tb} -coverage exclude -cvgpath {/uvme_cv32e40p_pkg/uvme_debug_covg/cg_debug_with_xpulp_inst/\/uvme_cv32e40p_pkg::uvme_debug_covg::cg_debug_with_xpulp_inst /cr_dbg_req_at_xpulp_instr/} -comment {note: this waiver is not applicable for pulp_cluster config. elw is currently not tested thoroughly in non-cluster config tb} -coverage exclude -cvgpath {/uvme_cv32e40p_pkg/uvme_debug_covg/cg_debug_with_xpulp_inst/\/uvme_cv32e40p_pkg::uvme_debug_covg::cg_debug_with_xpulp_inst /cr_trigger_with_xpulp_instr/} -comment {note: this waiver is not applicable for pulp_cluster config. elw is currently not tested thoroughly in non-cluster config tb} -coverage exclude -cvgpath {/uvme_cv32e40p_pkg/uvme_debug_covg/cg_debug_with_xpulp_inst/\/uvme_cv32e40p_pkg::uvme_debug_covg::cg_debug_with_xpulp_inst /cr_trigger_with_xpulp_instr/} -comment {note: this waiver is not applicable for pulp_cluster config. elw is currently not tested thoroughly in non-cluster config tb} -coverage exclude -cvgpath {/uvme_cv32e40p_pkg/uvme_debug_covg/cg_debug_with_xpulp_inst/\/uvme_cv32e40p_pkg::uvme_debug_covg::cg_debug_with_xpulp_inst /cr_dbg_single_step_xpulp_instr/} -comment {note: this waiver is not applicable for pulp_cluster config. elw is currently not tested thoroughly in non-cluster config tb} -coverage exclude -cvgpath {/uvme_cv32e40p_pkg/uvme_debug_covg/cg_debug_with_xpulp_inst/\/uvme_cv32e40p_pkg::uvme_debug_covg::cg_debug_with_xpulp_inst /cr_xpulp_instructions_in_dbg_mode/} -comment {note: this waiver is not applicable for pulp_cluster config. elw is currently not tested thoroughly in non-cluster config tb} +coverage exclude -cvgpath {/uvme_cv32e40p_pkg/uvme_debug_covg/cg_debug_with_xpulp_inst/\/uvme_cv32e40p_pkg::uvme_debug_covg::cg_debug_with_xpulp_inst /cr_dbg_req_at_xpulp_instr/} -comment {fixme: this waiver is not applicable for pulp_cluster config. elw is currently not tested thoroughly in non-cluster config tb} +coverage exclude -cvgpath {/uvme_cv32e40p_pkg/uvme_debug_covg/cg_debug_with_xpulp_inst/\/uvme_cv32e40p_pkg::uvme_debug_covg::cg_debug_with_xpulp_inst /cr_dbg_req_at_xpulp_instr/} -comment {fixme: this waiver is not applicable for pulp_cluster config. elw is currently not tested thoroughly in non-cluster config tb} +coverage exclude -cvgpath {/uvme_cv32e40p_pkg/uvme_debug_covg/cg_debug_with_xpulp_inst/\/uvme_cv32e40p_pkg::uvme_debug_covg::cg_debug_with_xpulp_inst /cr_trigger_with_xpulp_instr/} -comment {fixme: this waiver is not applicable for pulp_cluster config. elw is currently not tested thoroughly in non-cluster config tb} +coverage exclude -cvgpath {/uvme_cv32e40p_pkg/uvme_debug_covg/cg_debug_with_xpulp_inst/\/uvme_cv32e40p_pkg::uvme_debug_covg::cg_debug_with_xpulp_inst /cr_trigger_with_xpulp_instr/} -comment {fixme: this waiver is not applicable for pulp_cluster config. elw is currently not tested thoroughly in non-cluster config tb} +coverage exclude -cvgpath {/uvme_cv32e40p_pkg/uvme_debug_covg/cg_debug_with_xpulp_inst/\/uvme_cv32e40p_pkg::uvme_debug_covg::cg_debug_with_xpulp_inst /cr_dbg_single_step_xpulp_instr/} -comment {fixme: this waiver is not applicable for pulp_cluster config. elw is currently not tested thoroughly in non-cluster config tb} +coverage exclude -cvgpath {/uvme_cv32e40p_pkg/uvme_debug_covg/cg_debug_with_xpulp_inst/\/uvme_cv32e40p_pkg::uvme_debug_covg::cg_debug_with_xpulp_inst /cr_xpulp_instructions_in_dbg_mode/} -comment {fixme: this waiver is not applicable for pulp_cluster config. elw is currently not tested thoroughly in non-cluster config tb} From db2e14a18227d5d2fa9a90fd3da6574d6349f83e Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Mon, 26 Feb 2024 14:58:25 +0800 Subject: [PATCH 17/20] Add more waivers Signed-off-by: dd-baoshan --- .../vsim/exclusion/cv32e40pv2_func_uvme_interrupt_waiver.do | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_func_uvme_interrupt_waiver.do b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_func_uvme_interrupt_waiver.do index 62b44a073d..8fe5d0ed19 100644 --- a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_func_uvme_interrupt_waiver.do +++ b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_func_uvme_interrupt_waiver.do @@ -34,3 +34,8 @@ coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_ex coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_exit/cp_insn_list/cv_setupi1 -comment {exclude wfi coverage for hwloop usecase} coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_exit/cp_insn_list/cv_setup1 -comment {exclude wfi coverage for hwloop usecase} +# for cv_elw_pi_ri +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_irq_entry/cg_irq_entry/cp_insn_list/cv_elw_pi_ri -comment {fixme: this waiver is not applicable for pulp_cluster config. elw is currently not tested thoroughly in non-cluster config tb} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_irq_exit/cg_irq_exit/cp_insn_list/cv_elw_pi_ri -comment {fixme: this waiver is not applicable for pulp_cluster config. elw is currently not tested thoroughly in non-cluster config tb} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_entry/cg_wfi_entry/cp_insn_list/cv_elw_pi_ri -comment {fixme: this waiver is not applicable for pulp_cluster config. elw is currently not tested thoroughly in non-cluster config tb} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_interrupt_covg_v2__1/cg_wfi_exit/cg_wfi_exit/cp_insn_list/cv_elw_pi_ri -comment {fixme: this waiver is not applicable for pulp_cluster config. elw is currently not tested thoroughly in non-cluster config tb} From 94b5ddb11b28f68055af39990300ee11b9d22629 Mon Sep 17 00:00:00 2001 From: Xavier Aubert Date: Mon, 26 Feb 2024 15:49:11 +0100 Subject: [PATCH 18/20] reverted a deprecated feature now handled by TEST_CFG parameter (old feature introduced in commits 48dacb5d8e5d266eecd37897fb2138e511d38474 and 89e3869e52ed5b65bc93e312a4cec9a39da4ed61 --- bin/lib/cv_regression.py | 3 --- bin/templates/regress_sh.j2 | 2 +- bin/templates/regress_vsif.j2 | 2 +- mk/Common.mk | 9 +-------- mk/uvmt/uvmt.mk | 2 -- 5 files changed, 3 insertions(+), 15 deletions(-) diff --git a/bin/lib/cv_regression.py b/bin/lib/cv_regression.py index 076175f676..4dea5aeaf9 100644 --- a/bin/lib/cv_regression.py +++ b/bin/lib/cv_regression.py @@ -89,9 +89,6 @@ def __init__(self, **kwargs): if not hasattr(self, 'testname'): self.testname = self.name - if not hasattr(self, 'riscvdv_cfg'): - self.riscvdv_cfg = '' - # Log equals the test name if does not exist if not hasattr(self, 'log'): self.log = self.name diff --git a/bin/templates/regress_sh.j2 b/bin/templates/regress_sh.j2 index 3dc14fad2b..f861cfd28c 100644 --- a/bin/templates/regress_sh.j2 +++ b/bin/templates/regress_sh.j2 @@ -110,7 +110,7 @@ popd > /dev/null {% set test_cfg_path = test_cfg_list|join("__") %} # --> Test (Index: {{run_index}}): {{t.cmd}} : {{t.description}} -{% set cmd = test_cmd + ' CV_CORE=' + project + ' CFG=' + r.builds[build].cfg + ' ' + toolchain|upper + '=1' + ' RISCVDV_CFG=' + t.riscvdv_cfg + ' SIMULATOR=' + t.simulator + ' COMP=0 USE_ISS=' + regress_macros.yesorno(t.iss) + ' COV=' + regress_macros.yesorno(t.cov) + ' SEED=random GEN_START_INDEX=' + run_index|string + ' RUN_INDEX=' + run_index|string + ' TEST_CFG_FILE=\"' + test_cfg + '\" ' + regress_macros.cv_results(results) + ' ' + makeargs %} +{% set cmd = test_cmd + ' CV_CORE=' + project + ' CFG=' + r.builds[build].cfg + ' ' + toolchain|upper + '=1 SIMULATOR=' + t.simulator + ' COMP=0 USE_ISS=' + regress_macros.yesorno(t.iss) + ' COV=' + regress_macros.yesorno(t.cov) + ' SEED=random GEN_START_INDEX=' + run_index|string + ' RUN_INDEX=' + run_index|string + ' TEST_CFG_FILE=\"' + test_cfg + '\" ' + regress_macros.cv_results(results) + ' ' + makeargs %} echo "{{session}}: Running test [cd {{t.abs_dir}} && {{cmd}}]" pushd {{t.abs_dir}} > /dev/null {{cmd}} >& /dev/null; diff --git a/bin/templates/regress_vsif.j2 b/bin/templates/regress_vsif.j2 index 3886b33a4f..2695a0c9dd 100644 --- a/bin/templates/regress_vsif.j2 +++ b/bin/templates/regress_vsif.j2 @@ -64,7 +64,7 @@ group {{project}} { test precmd { sv_seed: gen_random; count: 1; - run_script: 'cd {{t.abs_dir}} && {{t.precmd}} CV_SIM_PREFIX= CV_CORE={{project}} CFG={{build.cfg}} RISCVDV_CFG={{t.riscvdv_cfg}} {{toolchain|upper}}=1 SIMULATOR={{t.simulator}} RNDSEED=$RUN_ENV(BRUN_SV_SEED) NUM_TESTS={{t.num}} {{regress_macros.cv_results(results)}} {{makeargs}}'; + run_script: 'cd {{t.abs_dir}} && {{t.precmd}} CV_SIM_PREFIX= CV_CORE={{project}} CFG={{build.cfg}} {{toolchain|upper}}=1 SIMULATOR={{t.simulator}} RNDSEED=$RUN_ENV(BRUN_SV_SEED) NUM_TESTS={{t.num}} {{regress_macros.cv_results(results)}} {{makeargs}}'; }; {% else %} {% endif %} diff --git a/mk/Common.mk b/mk/Common.mk index b46654ce28..ff2b163007 100644 --- a/mk/Common.mk +++ b/mk/Common.mk @@ -191,16 +191,9 @@ ifneq ($(filter gen_corev-dv,$(MAKECMDGOALS)),) ifeq ($(TEST),) $(error ERROR must specify a TEST variable with gen_corev-dv target) endif -ifeq ($(RISCVDV_CFG),) GEN_FLAGS_MAKE := $(shell $(YAML2MAKE) --test=$(TEST) --yaml=corev-dv.yaml $(YAML2MAKE_DEBUG) --prefix=GEN --core=$(CV_CORE)) ifeq ($(GEN_FLAGS_MAKE),) -$(error ERROR Could not find corev-dv.yaml of for test: $(TEST)) -endif -else -GEN_FLAGS_MAKE := $(shell $(YAML2MAKE) --test=$(TEST) --yaml=$(RISCVDV_CFG).yaml $(YAML2MAKE_DEBUG) --prefix=GEN --core=$(CV_CORE)) -ifeq ($(GEN_FLAGS_MAKE),) -$(error ERROR Could not find corev-dv_$(RISCVDV_CFG).yaml of for test: $(TEST)) -endif +$(error ERROR Could not find corev-dv.yaml for test: $(TEST)) endif include $(GEN_FLAGS_MAKE) endif diff --git a/mk/uvmt/uvmt.mk b/mk/uvmt/uvmt.mk index 5a29233170..f28f5d1e23 100644 --- a/mk/uvmt/uvmt.mk +++ b/mk/uvmt/uvmt.mk @@ -169,8 +169,6 @@ export RISCV_DV_ROOT = $(RISCVDV_PKG) export COREV_DV_ROOT = $(COREVDV_PKG) export CV_CORE_COREV_DV_ROOT = $(CV_CORE_COREVDV_PKG) -RISCVDV_CFG ?= - # EMBench benchmarking suite EMBENCH_PKG := $(CORE_V_VERIF)/$(CV_CORE_LC)/vendor_lib/embench EMBENCH_TESTS := $(CORE_V_VERIF)/$(CV_CORE_LC)/tests/programs/embench From dc161aeaa7c961d27d66703164d8365c2ed98d49 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Tue, 27 Feb 2024 13:31:34 +0800 Subject: [PATCH 19/20] Revert unintentional deleted line Signed-off-by: dd-baoshan --- .../env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv | 1 + 1 file changed, 1 insertion(+) diff --git a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv index c392c999dc..37bc5150a4 100644 --- a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv +++ b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv @@ -622,6 +622,7 @@ class cv32e40p_xpulp_hwloop_base_stream extends cv32e40p_xpulp_rand_stream; .set_label_for_first_instr(1), .str_lbl_str(start_label_s), .end_lbl_str(end_label_s), + .instr_label(label_s)); //Insert Random instructions till Loop HWLOOP_START0/1 label -> use_setup_inst ? 0 : num_fill_instr_loop_ctrl_to_loop_start[0/1] if(!use_setup_inst[hwloop_L]) From ca82bde20eead96b0e33dfb304ea898c5f5e4f7e Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Tue, 27 Feb 2024 13:32:18 +0800 Subject: [PATCH 20/20] Add test to improve functional coverage holes (uvme_debug_covg) Signed-off-by: dd-baoshan --- cv32e40p/regress/cv32e40pv2_for_func_cvg_improvement.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/cv32e40p/regress/cv32e40pv2_for_func_cvg_improvement.yaml b/cv32e40p/regress/cv32e40pv2_for_func_cvg_improvement.yaml index 364b095b5b..5d02f3f7d2 100644 --- a/cv32e40p/regress/cv32e40pv2_for_func_cvg_improvement.yaml +++ b/cv32e40p/regress/cv32e40pv2_for_func_cvg_improvement.yaml @@ -54,3 +54,10 @@ tests: test_cfg: gen_rand_int skip_sim: pulp num: 5 + + debug_test_trigger: + build: uvmt_cv32e40p + description: This custom legacy test is needed to improve func coverage holes in uvme_debug_covg + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=debug_test_trigger + num: 1