riscv-trace-spec.tex

%=======================================================================
% riscv-trace.tex
%-----------------------------------------------------------------------

\documentclass[twoside,11pt]{book}
\usepackage{footnote}

\makesavenoteenv{tabulary}
\setcounter{tocdepth}{4}
\setcounter{secnumdepth}{4}

\input{preamble}

% All registers are named here. That way when we rename one we'll get errors if
% there are still references to the old name.

\usepackage{makeidx}
\makeindex

\usepackage{xspace}
\usepackage{placeins}

\newcommand{\versionnum}{0.026-DRAFT}

\input{vc.tex}

\begin{document}
\setcounter{footnote}{0}

\title{RISC-V Processor Trace\\
Version \versionnum\\
\GITHash
}

\author{
  Gajinder Panesar, Iain Robertson \\
 \textless gajinder.panesar@ultrasoc.com\textgreater, \textless iain.robertson@ultrasoc.com\textgreater
 \and
 UltraSoC Technologies Ltd.
}


\maketitle

\markboth{RISC-V Processor Trace Version \versionnum}
{RISC-V Processor Trace Version \versionnum}
\thispagestyle{empty}

\frontmatter

\tableofcontents
\listoffigures
\listoftables

\mainmatter

\input{introduction}
\input{branchTrace.tex}
\input{ingressPort.tex}
\input{filtering.tex}
\input{exampleAlgorithm.tex}
\input{payload.tex}
\input{futures.tex}
\newpage


\end{document}