diff --git a/.flake8 b/.flake8 index 9d08bc1..8c1dc10 100644 --- a/.flake8 +++ b/.flake8 @@ -23,7 +23,7 @@ # F403: 'from module import *' used; unable to detect undefined names # F405: name may be undefined, or defined from star imports: module # N806: variable in function should be lowercase -ignore=F403,E266,W503,W291,W293 +ignore=F403,E266,W503,W291,W293,C901 exclude= qick/*.py @@ -32,11 +32,11 @@ exclude= # N802 : function name should be lowercase # N805 : first argument to method should be called 'self' per-file-ignores = - qickdawg/__init__.py:F401 - qickdawg/nvpulsing/__init__.py:F401 - qickdawg/fitfunctions/__init__.py:F401 - qickdawg/util/__init__.py:F401 + src/qickdawg/__init__.py:F401 + src/qickdawg/nvpulsing/__init__.py:F401 + src/qickdawg/fitfunctions/__init__.py:F401 + src/qickdawg/util/__init__.py:F401 # 120 characters is a more agreeable max line length for modern displays -max-line-length=120 +max-line-length=127 diff --git a/.github/workflows/python-app.yaml b/.github/workflows/python-app.yaml index 5539b41..d808f02 100644 --- a/.github/workflows/python-app.yaml +++ b/.github/workflows/python-app.yaml @@ -39,10 +39,8 @@ jobs: if [ -f requirements.txt ]; then pip install -r requirements.txt; fi - name: Lint with flake8 run: | - # stop the build if there are Python syntax errors or undefined names - flake8 ./qickdawg --count --select=E9,F63,F7,F82 --show-source --statistics # exit-zero treats all errors as warnings. The GitHub editor is 127 chars wide - flake8 ./qickdawg --count --exit-zero --max-complexity=10 --max-line-length=127 --statistics + flake8 ./src/qickdawg --count --max-complexity=10 --max-line-length=127 --statistics # - name: Test with pytest # run: | # pytest diff --git a/.github/workflows/semantic_release.yaml b/.github/workflows/semantic_release.yaml deleted file mode 100644 index ed98074..0000000 --- a/.github/workflows/semantic_release.yaml +++ /dev/null @@ -1,25 +0,0 @@ -name: Semantic Release - -on: - push: - branches: - - main - workflow_dispatch: - -jobs: - release: - runs-on: ubuntu-latest - concurrency: release - permissions: - id-token: write - contents: write - - steps: - - uses: actions/checkout@v3 - with: - fetch-depth: 0 - - - name: Python Semantic Release - uses: python-semantic-release/python-semantic-release@master - with: - github_token: ${{ secrets.GITHUB_TOKEN }} diff --git a/.github/workflows/version_changelog_release.yaml b/.github/workflows/version_changelog_release.yaml new file mode 100644 index 0000000..d9486bc --- /dev/null +++ b/.github/workflows/version_changelog_release.yaml @@ -0,0 +1,43 @@ +# This workflow will auto-version when pull-requests are merged to main. +# For more information see: https://docs.github.com/en/actions/automating-builds-and-tests/building-and-testing-python + +name: Version, Changelog, and Release + +on: + workflow_dispatch: + push: + branches: + - main + +permissions: + contents: write + +jobs: + vcr: + runs-on: ubuntu-latest + + steps: + - name: Git checkout + uses: actions/checkout@v4 + with: + token: ${{ secrets.AMM }} + fetch-depth: 0 + + - name: Conventional Changelog Action + id: changelog + uses: TriPSs/conventional-changelog-action@v5.2.1 + with: + github-token: ${{ secrets.AMM }} + version-file: 'src/qickdawg/version.json' + release-count: 0 + git-message: ${{ github.event.head_commit.message }} + + - name: Create Release + uses: actions/create-release@v1 + if: ${{ steps.changelog.outputs.skipped == 'false' }} + env: + GITHUB_TOKEN: ${{ secrets.AMM }} + with: + tag_name: ${{ steps.changelog.outputs.tag }} + release_name: ${{ steps.changelog.outputs.tag }} + body: ${{ steps.changelog.outputs.clean_changelog }} \ No newline at end of file diff --git a/.gitignore b/.gitignore index bff4a94..0d3ab2d 100644 --- a/.gitignore +++ b/.gitignore @@ -162,4 +162,5 @@ cython_debug/ .DS_Store .docs/html -.docs/doctrees \ No newline at end of file +.docs/doctrees +*test.ipynb \ No newline at end of file diff --git a/pyproject.toml b/pyproject.toml index 3f056e2..2ecf62c 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -1,10 +1,11 @@ [build-system] -requires = ["setuptools>=43.0.0", "wheel"] +requires = ["setuptools >= 64.0", "setuptools-scm[toml]>=8.0"] build-backend = "setuptools.build_meta" [project] name = "qickdawg" +dynamic = ["version"] dependencies = [ "numpy", "matplotlib", @@ -12,7 +13,7 @@ dependencies = [ "serpent", "tqdm", "scipy", - "qick==0.2.160" + "qick==0.2.289" ] requires-python = ">=3.7" description = """ @@ -25,15 +26,16 @@ keywords = ["quantum control", "nitrogen vacancy", "fpga", "xilinx", "rfsoc", "q authors = [ {name = "Andy Mounce", email = "amounce@sandia.gov"}, {name = "Emmeline Riendeau", email = "eriendeau@uchicago.edu"}] -dynamic = ["version"] + +[tool.setuptools_scm] [project.urls] Documentation = "https://readthedocs.org" Repository = "https://github.com/sandialabs/qick-dawg.git" "Bug Tracker" = "https://github.com/sandialabs/qick-dawg/issues" -[tool.semantic_release] -version_variables = ["pyproject.toml:data.project.version"] +[tools.setuptools] +packages = ["qickdawg"] [tool.setuptools.packages.find] exclude = ["qick", "graphics*", "installation*", "jupyter_notebooks*"] diff --git a/qick/.github/workflows/update_version.yml b/qick/.github/workflows/update_version.yml deleted file mode 100644 index dd93129..0000000 --- a/qick/.github/workflows/update_version.yml +++ /dev/null @@ -1,54 +0,0 @@ -# Automatically update the package version. -# The version has the format major.minor.PR, where PR is the number of the most recent pull request. -# This action runs automatically when a pull request is opened, or a commit is added to an open pull request. -# https://docs.github.com/en/actions/using-workflows/events-that-trigger-workflows#pull_request_target -# -# It checks the version number against the PR number; if it does not match, the version number is updated in a new commit. -# The commit will be credited to the GitHub Actions user. -# https://github.com/orgs/community/discussions/26560#discussioncomment-3252339 -# -# We need write access, which is only available using the pull_request_target trigger. -# It is dangerous to have write access at the same time that you are checking out untrusted code from a PR. -# However, we are only extracting a version number and (possibly) committing a new version number back to the PR, which is relatively safe. -# In other words, we are doing a bad thing ("pull_request_target with an explicit PR checkout") but our workflow is safe ("Reformat and commit the code"): -# https://securitylab.github.com/research/github-actions-preventing-pwn-requests/ -# -# If you don't want this action to run (e.g. if you want a different version number for a certain PR), include [skip actions] in the commit message. -# https://docs.github.com/en/actions/managing-workflow-runs/skipping-workflow-runs -name: Update version - -on: - pull_request_target: - types: [opened, reopened, synchronize] - -permissions: - contents: write - pull-requests: write - -jobs: - update_version: - runs-on: ubuntu-latest - env: - PR_NUMBER: ${{ github.event.pull_request.number }} - GH_TOKEN: ${{ github.token }} - VERSION_PATH: qick_lib/qick/VERSION - steps: - - uses: actions/checkout@v3 - - name: Checkout pull request - run: gh pr checkout $PR_NUMBER - - name: Compare version numbers - run: | - file_version=$(cut -d '.' -f 3 "$VERSION_PATH") - echo "PR number: $PR_NUMBER, VERSION number: $file_version" - echo "file_version=$file_version" >> $GITHUB_ENV - - name: Update VERSION if necessary - if: env.file_version != github.event.pull_request.number - run: | - echo "updating VERSION" - echo "$(cut -d '.' -f -2 $VERSION_PATH).$PR_NUMBER" > "$VERSION_PATH" - git config user.email "129547417+qickbot@users.noreply.github.com" - git config user.name "QICK actions [bot]" - git config push.default upstream - git add "$VERSION_PATH" - git commit -am "update version" - git push diff --git a/qick/.github/workflows/wheels.yml b/qick/.github/workflows/wheels.yml deleted file mode 100644 index 7e9669c..0000000 --- a/qick/.github/workflows/wheels.yml +++ /dev/null @@ -1,39 +0,0 @@ -# Build a wheel and publish to PyPI when a pull request merges. -# https://packaging.python.org/en/latest/guides/publishing-package-distribution-releases-using-github-actions-ci-cd-workflows/ -# -# We need access to the repo secrets, which are only available using the pull_request_target trigger. -# For security this requires us to use the repo HEAD and not the PR merge commit. -# But since this action only executes on merge, those are the same thing. -# https://docs.github.com/en/actions/using-workflows/events-that-trigger-workflows#pull_request_target - -name: Build wheel - -on: - pull_request_target: - types: - - closed - -permissions: - contents: read - pull-requests: read - id-token: write - -jobs: - build_and_publish: - if: github.event.pull_request.merged == true - runs-on: ubuntu-latest - - steps: - - uses: actions/checkout@v3 - - name: Set up Python - uses: actions/setup-python@v4 - with: - python-version: "3.x" - - name: Build wheel - run: | - python -m pip install --user --upgrade pip build wheel - python -m build - - name: Publish distribution to PyPI - uses: pypa/gh-action-pypi-publish@release/v1 - with: - password: ${{ secrets.PYPI_API_TOKEN }} diff --git a/qick/.gitignore b/qick/.gitignore deleted file mode 100644 index 823a817..0000000 --- a/qick/.gitignore +++ /dev/null @@ -1,73 +0,0 @@ -# Created by .ignore support plugin (hsz.mobi) -### JupyterNotebooks template -# gitignore template for Jupyter Notebooks -# website: http://jupyter.org/ - -.ipynb_checkpoints -*/.ipynb_checkpoints/* - -# IPython -profile_default/ -ipython_config.py - -.idea/* - -# Remove previous ipynb_checkpoints -# git rm -r .ipynb_checkpoints/ - -# Vivado -.Xil/ -*.log -*.jou -vivado_pid*.str - -### Python template -# Byte-compiled / optimized / DLL files -__pycache__/ -*.py[cod] -*$py.class - -# pip -*.egg-info/ -.installed.cfg -*.egg - -# Distribution / packaging -build/ -dist/ - -# Sphinx documentation -docs/_build/ -docs/_autosummary/ - -### macOS template -# General -.DS_Store -.AppleDouble -.LSOverride - -# Thumbnails -._* - -# Files that might appear in the root of a volume -.DocumentRevisions-V100 -.fseventsd -.Spotlight-V100 -.TemporaryItems -.Trashes -.VolumeIcon.icns -.com.apple.timemachine.donotpresent - -# Directories potentially created on remote AFP share -.AppleDB -.AppleDesktop -Network Trash Folder -Temporary Items -.apdisk - -### Linux template -*~ -.*.swp - -!/.gitignore -!/README.md diff --git a/qick/.readthedocs.yaml b/qick/.readthedocs.yaml deleted file mode 100644 index 700a3c5..0000000 --- a/qick/.readthedocs.yaml +++ /dev/null @@ -1,19 +0,0 @@ -# readthedocs.yml -# Read the Docs configuration file -# See https://docs.readthedocs.io/en/stable/config-file/v2.html for details - -# Required -version: 2 - -# Build documentation in the docs/ directory with Sphinx -sphinx: - configuration: docs/conf.py - -# Optionally build your docs in additional formats such as PDF and ePub -formats: [] - -# Optionally set the version of Python and requirements required to build your docs -python: - version: 3.7 - install: - - requirements: docs/requirements.txt diff --git a/qick/CITATION.cff b/qick/CITATION.cff deleted file mode 100644 index d2868b3..0000000 --- a/qick/CITATION.cff +++ /dev/null @@ -1,5 +0,0 @@ -cff-version: 1.2.0 -message: "If you use this software, please cite it as below." -title: "The QICK (Quantum Instrumentation Control Kit): Readout and control for qubits and detectors" -doi: https://doi.org/10.1063/5.0076249 -date-released: 2021-10-01 diff --git a/qick/LICENSE b/qick/LICENSE deleted file mode 100644 index 565945e..0000000 --- a/qick/LICENSE +++ /dev/null @@ -1,21 +0,0 @@ -MIT License - -Copyright (c) 2021 Open Quantum Hardware - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in all -copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. \ No newline at end of file diff --git a/qick/README.md b/qick/README.md deleted file mode 100644 index 26a7cba..0000000 --- a/qick/README.md +++ /dev/null @@ -1,73 +0,0 @@ - -

- QICK logo -

- -# QICK: Quantum Instrumentation Control Kit - -The QICK is a kit of firmware and software to use the Xilinx RFSoC to control quantum systems. - -It consists of: -* Firmware for the ZCU111, ZCU216, and RFSoC4x2 evaluation boards -* The `qick` Python package -* [A quick start guide](quick_start) for setting up your board and running a Jupyter notebook example -* [Jupyter notebook examples](qick_demos) demonstrating usage - -Note: The firmware and software here is still very much a work in progress. This is an alpha release. We strive to be consistent with the APIs but cannot guarantee backwards compatibility. - - -Download and Installation -------------------------- - -Follow the quick start guide located [here](quick_start) to set up your board, install `qick` on your board, and run a Jupyter notebook example. - -Documentation -------------- - -The API documentation for QICK is available at: https://qick-docs.readthedocs.io/ - -The [demo notebooks](qick_demos) are intended as a tutorial. -The first demos explain important features of the QICK system and walk you through how to write working QICK programs. -The later demos provide examples of useful measurements you might make with the QICK. -We recommend that new users read and understand all of the demos. - -Updates -------- - -Frequent updates to the QICK firmware and software are made as pull requests. -Each pull request will be documented with a description of the notable changes, including any changes that will require you to change your code. -We hope that this will help you decide whether or not to update your local code to the latest version. -We strive for, but cannot guarantee, bug-free and fully functional pull requests. -We also do not guarantee that the demo notebooks will keep pace with every pull request, though we make an effort to update the demos after major API changes. - -Our version numbering follows the format major.minor.PR, where PR is the number of the most recently merged pull request. -This will result in the PR number often skipping values, and occasionally decreasing. -The tagged release of a new minor version will have the format major.minor.0. - -Tagged releases can be expected periodically. -We recommend that everyone should be using at least the most recent release. -We guarantee the following for releases: -* The demo notebooks will be compatible with the QICK library, and will follow our current best recommendations for writing QICK programs. -* The firmware images for all supported boards will be fully compatible with the library and the demo notebooks. -* Release notes will summarize the pull request notes and explain both breaking API changes (what you need to change in your code) and improvements (why you should move to the new release). - -We recommend that you "watch" this repository on GitHub to get automatic notifications of pull requests and releases. - -Contribute ----------- - -You are welcome to contribute to QICK development by forking this repository and sending pull requests. - -All contributions are expected to be consistent with [PEP 8 -- Style Guide for Python Code](https://www.python.org/dev/peps/pep-0008/). - -We welcome comments, bug reports, and feature requests via GitHub Issues. - -You can chat with us in the #qick channel on the [Unitary Fund Discord](http://discord.unitary.fund/). - -License -------- -The QICK source code is licensed under the MIT license, which you can find in the LICENSE file. -The [QICK logo](graphics/logoQICK.svg) was designed by Dr. Christie Chiu. - -You are free to use this software, with or without modification, provided that the conditions listed in the LICENSE file are satisfied. - diff --git a/qick/aws/README.md b/qick/aws/README.md deleted file mode 100644 index 930a9bf..0000000 --- a/qick/aws/README.md +++ /dev/null @@ -1,30 +0,0 @@ -# SideQICK: AWS-based workload management for QICK - -SideQICK is a QICK interface to the [Cloud Queue for Quantum Devices](https://github.com/aws-samples/cloud-queue-for-quantum-devices), and was developed in collaboration with Amazon Web Services. - -The Cloud Queue for Quantum Devices is a cloud-based application for managing queues of workloads to be executed on quantum devices. -The application is composed of standard AWS services and can be deployed to an AWS account using the open-source code and instructions at https://github.com/aws-samples/cloud-queue-for-quantum-devices. -Once an instance of the application is deployed, its administrator can create queues for devices and user accounts for experimenters. - -Users use SideQICK to submit workloads (sets of programs to be executed by the QICK) to a queue, from which the QICK downloads them. -The QICK uploads results back to the queue, from which users can retrieve them at any time. -Workloads and results are stored securely and resiliently in AWS cloud storage. -SideQICK allows a QICK-based system to be shared with users anywhere in the world without allowing full remote access. - -SideQICK provides two components which interface to the Cloud Queue application: -* A "user client," which is a library and CLI tool that you run on your computer to make requests to the cloud application. This is used for admin operations (adding new devices or users to the application) or queue operations (Python access to workloads as an alternative to the web UI). The user client also includes a WorkloadManager class which can be used to encapsulate QickPrograms into a workload and process the results. -* A "device client," which is a systemd service that runs on the QICK board and executes workloads downloaded from a cloud queue. - -See the [demo notebook](aws_demo.ipynb) for an example of the user client in operation. - -## User client setup (as an admin) -As part of the Cloud Queue application setup, you will have obtained a set of URLs and IDs for the application, and created an admin user with an e-mail address. -Copy the [config.template](config.template) file to `~/.config/qick.conf` or `/etc/qick/config`, and fill out the `[service]` and `[user]` blocks with those parameters. - -## User client setup (as a user) -An admin will provide config parameters, to be copied to `~/.config/qick.conf` or `/etc/qick/config` on your computer. - -## Installing the device client -An admin will provide config and credentials parameters for your device, to be copied to `/etc/qick/config` and `/etc/qick/credentials` on the QICK board. - -* Follow instructions in [qick.service](qick.service) to install the systemd service. diff --git a/qick/aws/aws_demo.ipynb b/qick/aws/aws_demo.ipynb deleted file mode 100644 index 4021165..0000000 --- a/qick/aws/aws_demo.ipynb +++ /dev/null @@ -1,767 +0,0 @@ -{ - "cells": [ - { - "cell_type": "markdown", - "id": "2bba5f04", - "metadata": {}, - "source": [ - "# SideQICK demo notebook\n", - "This was used for the demo presentation on 2022-11-30." - ] - }, - { - "cell_type": "code", - "execution_count": 1, - "id": "valid-turning", - "metadata": {}, - "outputs": [ - { - "data": { - "application/javascript": [ - "\n", - "try {\n", - "require(['notebook/js/codecell'], function(codecell) {\n", - " codecell.CodeCell.options_default.highlight_modes[\n", - " 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n", - " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", - " Jupyter.notebook.get_cells().map(function(cell){\n", - " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", - " });\n", - "});\n", - "} catch (e) {};\n" - ] - }, - "metadata": {}, - "output_type": "display_data" - }, - { - "data": { - "application/javascript": [ - "\n", - "try {\n", - "require(['notebook/js/codecell'], function(codecell) {\n", - " codecell.CodeCell.options_default.highlight_modes[\n", - " 'magic_text/x-csrc'] = {'reg':[/^%%pybind11/]};\n", - " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", - " Jupyter.notebook.get_cells().map(function(cell){\n", - " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", - " });\n", - "});\n", - "} catch (e) {};\n" - ] - }, - "metadata": {}, - "output_type": "display_data" - }, - { - "name": "stdout", - "output_type": "stream", - "text": [ - "Could not import QickSoc: name 'xrfdc' is not defined\n", - "Populating the interactive namespace from numpy and matplotlib\n" - ] - } - ], - "source": [ - "# Import the QICK drivers and auxiliary libraries\n", - "from qick import *\n", - "from user_client import UserClient, WorkloadManager\n", - "from tqdm.auto import tqdm\n", - "%pylab inline" - ] - }, - { - "cell_type": "markdown", - "id": "eaec3057", - "metadata": {}, - "source": [ - "## Set up initial configuration\n", - "You should have a config file in ~/.config/qick.conf.admin with admin credentials, which we will use to create the demo device and user." - ] - }, - { - "cell_type": "code", - "execution_count": 2, - "id": "baking-brazil", - "metadata": {}, - "outputs": [], - "source": [ - "!rm ~/.cache/qick.tokens\n", - "# use admin config for the setup steps\n", - "!cp ~/.config/qick.conf.admin ~/.config/qick.conf\n", - "# start new client\n", - "client = UserClient()" - ] - }, - { - "cell_type": "markdown", - "id": "familiar-custody", - "metadata": {}, - "source": [ - "## add a device (and start the device client)" - ] - }, - { - "cell_type": "code", - "execution_count": 3, - "id": "sweet-chuck", - "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "initial auth for admin@example.com:\n", - "········\n", - "Device successfully added!\n", - "\n", - "Put the following in the config file /etc/qick/config:\n", - "[service]\n", - "api_url = [REDACTED]\n", - "oauth_url = [REDACTED]\n", - "[device]\n", - "name = QICK Demo Device AAA\n", - "id = [REDACTED]\n", - "\n", - "If using UserClient for workload submission, the [device] block is needed in the client config as well.\n", - "\n", - "Put the following in the device credentials file /etc/qick/credentials:\n", - "[credentials]\n", - "id = [REDACTED]\n", - "secret = [REDACTED]\n" - ] - } - ], - "source": [ - "client.add_device(\"QICK Demo Device\")\n", - "\n", - "# this is equivalent:\n", - "# ./user_client.py add_device \"QICK Demo Device\"" - ] - }, - { - "cell_type": "markdown", - "id": "sitting-diamond", - "metadata": {}, - "source": [ - "## add a user (and log in to the web UI)\n", - "You should of course use a real e-mail address, since a temporary password will be sent there." - ] - }, - { - "cell_type": "code", - "execution_count": 4, - "id": "posted-humanity", - "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "User successfully added! They should check their e-mail for a temporary password.\n", - "\n", - "They should put the following in ~/.config/qick.conf:\n", - "[service]\n", - "api_url = [REDACTED]\n", - "cognito_url = [REDACTED]\n", - "cognito_clientid = [REDACTED]\n", - "cognito_userpool = [REDACTED]\n", - "[user]\n", - "username = name@example.com\n" - ] - } - ], - "source": [ - "client.add_user(\"name@example.com\", \"Demo User\")\n", - "\n", - "# this is equivalent:\n", - "# ./user_client.py add_user name@example.com \"Demo User\"" - ] - }, - { - "cell_type": "markdown", - "id": "anticipated-toolbox", - "metadata": {}, - "source": [ - "## define the QICK program and the workload" - ] - }, - { - "cell_type": "code", - "execution_count": 5, - "id": "cloudy-double", - "metadata": {}, - "outputs": [], - "source": [ - "class FSGenLoopbackProgram(AveragerProgram):\n", - " def initialize(self):\n", - " cfg = self.cfg\n", - " style = cfg['style']\n", - " for iCh, ch in enumerate(cfg[\"gen_chs\"]): # configure the pulse lengths and upconversion frequencies\n", - " length_gen = self.us2cycles(cfg['length'], gen_ch=ch)\n", - " self.declare_gen(ch=ch, nqz=cfg['nqz'][iCh], ro_ch=cfg[\"ro_chs\"][0])\n", - " \n", - " self.default_pulse_registers(ch=ch, \n", - " freq=self.freq2reg(cfg['pulse_freq'],gen_ch=ch,ro_ch=cfg[\"ro_chs\"][0]),\n", - " gain=cfg['pulse_gain'],\n", - " phase=0)\n", - "\n", - " if style == \"const\":\n", - " self.set_pulse_registers(ch=ch, style=style, length=length_gen)\n", - " elif style == \"arb\":\n", - " self.add_gauss(ch=ch, name=\"measure\", sigma=length_gen/5, length=length_gen)\n", - " self.set_pulse_registers(ch=ch, style=style, waveform=\"measure\")\n", - "\n", - " for iCh, ch in enumerate(cfg[\"ro_chs\"]): # configure the readout lengths and downconversion frequencies\n", - " length_ro = self.us2cycles(cfg['length']+cfg['readout_padding'], ro_ch=ch)\n", - " \n", - " self.declare_readout(ch=ch, freq=cfg[\"pulse_freq\"],\n", - " length=length_ro,\n", - " gen_ch=cfg[\"gen_chs\"][0])\n", - "\n", - " self.synci(200) # give processor some time to configure pulses\n", - "\n", - " def body(self):\n", - " self.measure(pulse_ch=self.cfg[\"gen_chs\"],\n", - " adcs=self.ro_chs,\n", - " pins=[0], \n", - " adc_trig_offset=self.us2cycles(self.cfg[\"adc_trig_offset\"]-0.5*self.cfg['readout_padding']),\n", - " wait=True,\n", - " syncdelay=self.us2cycles(self.cfg[\"relax_delay\"]))\n", - "\n", - " \n", - "def noise(raw, length):\n", - " \"\"\"Helper function for analysis\n", - " \"\"\"\n", - " diq = np.dot(raw, np.array([1,1j]))/length\n", - " dmean = np.mean(diq,axis=1)\n", - " dmag = np.abs(dmean)\n", - " drotated = diq*np.exp(-1j*np.angle(dmean))[:,np.newaxis]\n", - " drmsmag = np.std(np.real(drotated),axis=1) # noise in the radial direction\n", - " drmsrot = np.std(np.imag(drotated), axis=1) # noise in the azimuth direction\n", - " return drmsmag, drmsrot\n", - "\n", - "class SweepWorkload(WorkloadManager):\n", - " def __init__(self, soccfg, start, stop, n_pts):\n", - " self.freqs = np.linspace(start=start, stop=stop, num=n_pts)\n", - " self.amps = np.zeros((n_pts,2))\n", - " self.noises_amp = np.zeros((n_pts,2))\n", - " self.noises_pha = np.zeros((n_pts,2))\n", - " \n", - " self.config = {\n", - " 'gen_chs': [0,4],\n", - " 'ro_chs': [0,1],\n", - " 'nqz': [1,2],\n", - " 'style': 'const',\n", - " 'pulse_gain': 32000,\n", - " 'adc_trig_offset': 0.45,\n", - " 'length': 4,\n", - " 'readout_padding': -0.1,\n", - " 'relax_delay': 1,\n", - " 'reps': 1000,\n", - " 'rounds': 1,\n", - " }\n", - " self.dec_config = {\n", - " 'pulse_freq': 4000,\n", - " 'length': 1,\n", - " 'readout_padding': 0.1,\n", - " 'reps': 1,\n", - " 'soft_avgs': 1000\n", - " }\n", - " super().__init__(soccfg)\n", - " \n", - " def do_stuff(self, make_progs=False, write_progs=False, read_results=False):\n", - " if make_progs:\n", - " # create and add a program\n", - " prog = FSGenLoopbackProgram(self.soccfg, {**self.config, **self.dec_config})\n", - " self.add_program(prog)\n", - " else:\n", - " prog = next(self.prog_iterator)\n", - " if write_progs:\n", - " # now call add_acquire\n", - " self.add_decimated(prog)\n", - " if read_results:\n", - " res = next(self.result_iterator)\n", - " # now do something with \"res\"\n", - " self.dec = res[\"dec\"][...]\n", - " self.dec_t = prog.cycles2us(np.arange(self.dec.shape[1]), ro_ch=self.config['ro_chs'][0])\n", - " \n", - " for i, f in tqdm(list(enumerate(self.freqs))):\n", - " self.config['pulse_freq'] = f\n", - " if make_progs:\n", - " # create and add a program\n", - " prog = FSGenLoopbackProgram(self.soccfg, self.config)\n", - " self.add_program(prog)\n", - " else:\n", - " prog = next(self.prog_iterator)\n", - " if write_progs:\n", - " # now call add_acquire\n", - " self.add_acquire(prog, save_raw=True)\n", - " if read_results:\n", - " res = next(self.result_iterator)\n", - " # now do something with \"res\"\n", - " avg = res[\"avg\"][...]\n", - " raw = res[\"raw\"][...]\n", - " self.amps[i] = np.abs(avg[:,0,:].dot(np.array([1,1j])))\n", - " noise_amp, noise_pha = noise(raw, prog.ro_chs[0]['length'])\n", - " self.noises_amp[i] = noise_amp\n", - " self.noises_pha[i] = noise_pha\n", - " \n", - " def display(self):\n", - " fig, axs = plt.subplots(4,1,figsize=(10,20))\n", - " for ii, iq in enumerate(self.dec):\n", - " plot = axs[2*ii]\n", - " plot.plot(self.dec_t, iq[:,0], label=\"I value, ADC %d\"%(self.config['ro_chs'][ii]))\n", - " plot.plot(self.dec_t, iq[:,1], label=\"Q value, ADC %d\"%(self.config['ro_chs'][ii]))\n", - " plot.plot(self.dec_t, np.abs(iq.dot([1, 1j])), label=\"mag, ADC %d\"%(self.config['ro_chs'][ii]))\n", - " plot.set_ylabel(\"a.u.\")\n", - " plot.set_xlabel(\"Time [us]\")\n", - " plot.set_title(\"Averages = \" + str(self.dec_config[\"soft_avgs\"]))\n", - " plot.legend()\n", - "\n", - " plot = axs[2*ii+1]\n", - " plot.semilogy(self.freqs, self.amps[:,ii], label=\"mean\")\n", - " plot.semilogy(self.freqs, self.noises_amp[:,ii], label=\"amplitude noise\")\n", - " plot.semilogy(self.freqs, self.noises_pha[:,ii], label=\"phase noise\")\n", - " plot.set_ylabel(\"avg a.u.\")\n", - " plot.set_xlabel(\"Frequency [MHz]\")\n", - " plot.set_title(\"Averages = \" + str(self.config[\"reps\"]))\n", - " plot.legend()" - ] - }, - { - "cell_type": "markdown", - "id": "optional-evolution", - "metadata": {}, - "source": [ - "## Manual upload and download (using WorkloadManager class, but not UserClient)" - ] - }, - { - "cell_type": "code", - "execution_count": 6, - "id": "purple-isolation", - "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "\n", - "QICK configuration:\n", - "\n", - "\tBoard: ZCU216\n", - "\n", - "\tGlobal clocks (MHz): tProcessor 430.080, RF reference 245.760\n", - "\n", - "\t7 signal generator channels:\n", - "\t0:\taxis_signal_gen_v6 - tProc output 1, envelope memory 65536 samples\n", - "\t\tDAC tile 2, ch 0, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\t1:\taxis_signal_gen_v6 - tProc output 2, envelope memory 65536 samples\n", - "\t\tDAC tile 2, ch 1, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\t2:\taxis_signal_gen_v6 - tProc output 3, envelope memory 65536 samples\n", - "\t\tDAC tile 2, ch 2, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\t3:\taxis_signal_gen_v6 - tProc output 4, envelope memory 65536 samples\n", - "\t\tDAC tile 2, ch 3, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\t4:\taxis_signal_gen_v6 - tProc output 5, envelope memory 65536 samples\n", - "\t\tDAC tile 3, ch 0, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\t5:\taxis_signal_gen_v6 - tProc output 6, envelope memory 65536 samples\n", - "\t\tDAC tile 3, ch 1, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\t6:\taxis_signal_gen_v6 - tProc output 7, envelope memory 65536 samples\n", - "\t\tDAC tile 3, ch 2, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\n", - "\t2 readout channels:\n", - "\t0:\taxis_readout_v2 - controlled by PYNQ\n", - "\t\tADC tile 2, ch 0, 32-bit DDS, fabric=307.200 MHz, fs=2457.600 MHz\n", - "\t\tmaxlen 16384 (avg) 1024 (decimated), trigger bit 14, tProc input 0\n", - "\t1:\taxis_readout_v2 - controlled by PYNQ\n", - "\t\tADC tile 2, ch 2, 32-bit DDS, fabric=307.200 MHz, fs=2457.600 MHz\n", - "\t\tmaxlen 16384 (avg) 1024 (decimated), trigger bit 15, tProc input 1\n", - "\n", - "\t7 DACs:\n", - "\t\tDAC tile 2, ch 0 is 0_230, on JHC3\n", - "\t\tDAC tile 2, ch 1 is 1_230, on JHC4\n", - "\t\tDAC tile 2, ch 2 is 2_230, on JHC3\n", - "\t\tDAC tile 2, ch 3 is 3_230, on JHC4\n", - "\t\tDAC tile 3, ch 0 is 0_231, on JHC3\n", - "\t\tDAC tile 3, ch 1 is 1_231, on JHC4\n", - "\t\tDAC tile 3, ch 2 is 2_231, on JHC3\n", - "\n", - "\t2 ADCs:\n", - "\t\tADC tile 2, ch 0 is 0_226, on JHC7\n", - "\t\tADC tile 2, ch 2 is 2_226, on JHC7\n", - "\n", - "\t8 digital output pins (tProc output 0):\n", - "\t0:\tPMOD0_0_LS\n", - "\t1:\tPMOD0_1_LS\n", - "\t2:\tPMOD0_2_LS\n", - "\t3:\tPMOD0_3_LS\n", - "\t4:\tPMOD0_4_LS\n", - "\t5:\tPMOD0_5_LS\n", - "\t6:\tPMOD0_6_LS\n", - "\t7:\tPMOD0_7_LS\n", - "\n", - "\ttProc: program memory 8192 words, data memory 4096 words\n", - "\t\texternal start pin: PMOD1_0_LS\n" - ] - } - ], - "source": [ - "import json\n", - "with open('/home/meeg/Downloads/664279d8-f236-4e28-83f4-27cce968d643-configuration.json', 'rt') as f:\n", - " soccfg = QickConfig(json.load(f))\n", - "print(soccfg)" - ] - }, - { - "cell_type": "code", - "execution_count": 7, - "id": "norman-poverty", - "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "initializing WorkloadManager:\n" - ] - }, - { - "data": { - "application/vnd.jupyter.widget-view+json": { - "model_id": "b060e9cbeacc40f2a91388105bb3c9af", - "version_major": 2, - "version_minor": 0 - }, - "text/plain": [ - " 0%| | 0/1001 [00:00" - ] - }, - "metadata": { - "needs_background": "light" - }, - "output_type": "display_data" - } - ], - "source": [ - "print(\"reading results:\")\n", - "with open('/home/meeg/Downloads/3707e60f-365b-40e8-b759-8942554ac96c-output', 'rb') as resultsfile:\n", - " expt.read_results(resultsfile)\n", - "\n", - "print(\"plotting results\")\n", - "expt.display()" - ] - }, - { - "cell_type": "markdown", - "id": "intellectual-solid", - "metadata": {}, - "source": [ - "## Using UserClient to upload work and download results" - ] - }, - { - "cell_type": "code", - "execution_count": 9, - "id": "permanent-festival", - "metadata": {}, - "outputs": [], - "source": [ - "# start new client\n", - "client = UserClient()" - ] - }, - { - "cell_type": "code", - "execution_count": 10, - "id": "widespread-winner", - "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "initial auth for [REDACTED]:\n", - "········\n", - "\n", - "QICK configuration:\n", - "\n", - "\tBoard: ZCU216\n", - "\n", - "\tGlobal clocks (MHz): tProcessor 430.080, RF reference 245.760\n", - "\n", - "\t7 signal generator channels:\n", - "\t0:\taxis_signal_gen_v6 - tProc output 1, envelope memory 65536 samples\n", - "\t\tDAC tile 2, ch 0, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\t1:\taxis_signal_gen_v6 - tProc output 2, envelope memory 65536 samples\n", - "\t\tDAC tile 2, ch 1, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\t2:\taxis_signal_gen_v6 - tProc output 3, envelope memory 65536 samples\n", - "\t\tDAC tile 2, ch 2, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\t3:\taxis_signal_gen_v6 - tProc output 4, envelope memory 65536 samples\n", - "\t\tDAC tile 2, ch 3, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\t4:\taxis_signal_gen_v6 - tProc output 5, envelope memory 65536 samples\n", - "\t\tDAC tile 3, ch 0, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\t5:\taxis_signal_gen_v6 - tProc output 6, envelope memory 65536 samples\n", - "\t\tDAC tile 3, ch 1, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\t6:\taxis_signal_gen_v6 - tProc output 7, envelope memory 65536 samples\n", - "\t\tDAC tile 3, ch 2, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\n", - "\t2 readout channels:\n", - "\t0:\taxis_readout_v2 - controlled by PYNQ\n", - "\t\tADC tile 2, ch 0, 32-bit DDS, fabric=307.200 MHz, fs=2457.600 MHz\n", - "\t\tmaxlen 16384 (avg) 1024 (decimated), trigger bit 14, tProc input 0\n", - "\t1:\taxis_readout_v2 - controlled by PYNQ\n", - "\t\tADC tile 2, ch 2, 32-bit DDS, fabric=307.200 MHz, fs=2457.600 MHz\n", - "\t\tmaxlen 16384 (avg) 1024 (decimated), trigger bit 15, tProc input 1\n", - "\n", - "\t7 DACs:\n", - "\t\tDAC tile 2, ch 0 is 0_230, on JHC3\n", - "\t\tDAC tile 2, ch 1 is 1_230, on JHC4\n", - "\t\tDAC tile 2, ch 2 is 2_230, on JHC3\n", - "\t\tDAC tile 2, ch 3 is 3_230, on JHC4\n", - "\t\tDAC tile 3, ch 0 is 0_231, on JHC3\n", - "\t\tDAC tile 3, ch 1 is 1_231, on JHC4\n", - "\t\tDAC tile 3, ch 2 is 2_231, on JHC3\n", - "\n", - "\t2 ADCs:\n", - "\t\tADC tile 2, ch 0 is 0_226, on JHC7\n", - "\t\tADC tile 2, ch 2 is 2_226, on JHC7\n", - "\n", - "\t8 digital output pins (tProc output 0):\n", - "\t0:\tPMOD0_0_LS\n", - "\t1:\tPMOD0_1_LS\n", - "\t2:\tPMOD0_2_LS\n", - "\t3:\tPMOD0_3_LS\n", - "\t4:\tPMOD0_4_LS\n", - "\t5:\tPMOD0_5_LS\n", - "\t6:\tPMOD0_6_LS\n", - "\t7:\tPMOD0_7_LS\n", - "\n", - "\ttProc: program memory 8192 words, data memory 4096 words\n", - "\t\texternal start pin: PMOD1_0_LS\n" - ] - } - ], - "source": [ - "# download QICK configuration\n", - "soccfg = QickConfig(client.get_soccfg())\n", - "print(soccfg)" - ] - }, - { - "cell_type": "code", - "execution_count": 11, - "id": "governing-presentation", - "metadata": { - "scrolled": false - }, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "initializing WorkloadManager:\n" - ] - }, - { - "data": { - "application/vnd.jupyter.widget-view+json": { - "model_id": "dcef4b8164844555804656badf2f34af", - "version_major": 2, - "version_minor": 0 - }, - "text/plain": [ - " 0%| | 0/1001 [00:00" - ] - }, - "metadata": { - "needs_background": "light" - }, - "output_type": "display_data" - } - ], - "source": [ - "print(\"initializing WorkloadManager:\")\n", - "expt = SweepWorkload(soccfg, start=1, stop=10000, n_pts=1001)\n", - "\n", - "print(\"writing programs to workload file:\")\n", - "with expt.write_progs() as workloadfile:\n", - " print(\"submitting workload:\")\n", - " work_id = client.create_work(workloadfile, priority=\"LOW\")\n", - "print(\"workload is submitted, work ID \" + work_id)\n", - "\n", - "client.wait_until_done(work_id, progress=True)\n", - "\n", - "print(\"reading results:\")\n", - "with client.get_results(work_id) as resultsfile:\n", - " expt.read_results(resultsfile)\n", - "\n", - "print(\"plotting results\")\n", - "expt.display()" - ] - } - ], - "metadata": { - "kernelspec": { - "display_name": "Python 3", - "language": "python", - "name": "python3" - }, - "language_info": { - "codemirror_mode": { - "name": "ipython", - "version": 3 - }, - "file_extension": ".py", - "mimetype": "text/x-python", - "name": "python", - "nbconvert_exporter": "python", - "pygments_lexer": "ipython3", - "version": "3.9.2" - } - }, - "nbformat": 4, - "nbformat_minor": 5 -} diff --git a/qick/aws/config.template b/qick/aws/config.template deleted file mode 100644 index ff9e255..0000000 --- a/qick/aws/config.template +++ /dev/null @@ -1,31 +0,0 @@ -# This is the QICK client config file. -# Because the device and user clients use a lot of the same parameters, the same config file can be used for both. -# Not all parameters are needed in all cases. -# -# The user client will check for this file in the following locations (in order): -# ~/.config/qick.conf -# /etc/qick/config -# -# The device client requires this file to be in /etc/qick/config. - -# needed for device and user clients -[service] -# only for user client -cognito_userpool = -cognito_url = -clientid = -# only for device client and device registration -oauth_endpoint = -# for all clients -api_endpoint = - -# needed for user client -[user] -username = - -# needed for device client -[device] -id = -# not needed, but useful to put here as a reminder of what device the ID corresponds to -name = - diff --git a/qick/aws/qick.service b/qick/aws/qick.service deleted file mode 100644 index 4f13bbb..0000000 --- a/qick/aws/qick.service +++ /dev/null @@ -1,23 +0,0 @@ -[Unit] -Description=QICK service -After=multi-user.target - -[Service] -Type=forking -ExecStart=/home/xilinx/jupyter_notebooks/qick/aws/start_qick_client.sh -PIDFile=/tmp/qick.pid -#Restart=always -#RestartSec=5 - -[Install] -WantedBy=multi-user.target - -# Note the ExecStart parameter must point to the actual location of the start script. -# -# The service can then be installed by doing: -# -# sudo cp qick.service /etc/systemd/system/ -# sudo systemctl daemon-reload -# sudo systemctl enable qick -# sudo systemctl start qick -# sudo systemctl status qick diff --git a/qick/aws/qick_client.py b/qick/aws/qick_client.py deleted file mode 100644 index 2623c9d..0000000 --- a/qick/aws/qick_client.py +++ /dev/null @@ -1,267 +0,0 @@ -#!/usr/bin/env python3 -import logging -import argparse -import requests -import multiprocessing -import json -import tempfile -import shutil -import sys -import time -import gzip -import h5py -from oauthlib.oauth2 import BackendApplicationClient -from requests_oauthlib import OAuth2Session -from configparser import ConfigParser -try: - from qick import QickSoc, QickProgram - from qick.helpers import json2progs -except: - pass - -class DummySoc: - def __init__(self): - self._cfg = {"cfg_a": "foo"} - - def get_cfg(self): - return self._cfg - - def dump_cfg(self): - return json.dumps(self._cfg, indent=4) - -class RefetchSession(OAuth2Session): - # requests-oauthlib doesn't support automatically requesting a new token in the "client credentials" flow: - # https://stackoverflow.com/questions/58697334/requests-oauthlib-auto-refresh-bearer-token-in-client-credentials-flow - # this workaround is based on this: - # https://github.com/requests/requests-oauthlib/issues/260 - def __init__(self, **kwargs): - super().__init__(**kwargs) - # define a no-op token_updater - self.token_updater = lambda token: None - - def fetch_token(self, token_url, **kwargs): - # cache the client secret (which is normally not stored) - self._client_secret = kwargs['client_secret'] - # copy token_url to auto_refresh_url (which could be passed in the constructor, but this is easier) - self.auto_refresh_url = token_url - return super().fetch_token(token_url, **kwargs) - - def refresh_token(self, token_url, **kwargs): - # use the previously cached client secret to fetch a fresh token - return super().fetch_token(token_url, client_id=self.client_id, client_secret=self._client_secret) - - -class QickClient: - - def __init__(self, api_endpoint, dummy_mode=False): - self.api_endpoint = api_endpoint - self.session = requests - self.cfg_path = "/etc/qick/config" - self.cred_path = "/etc/qick/credentials" - self.status = "ONLINE" - self.timeout = 24 * 60 * 60 # Run a workload for 24 hours max - if dummy_mode: - self.soc = DummySoc() - else: - self.soc = QickSoc() - - self.soccfg = self.soc.get_cfg() - - clientcfg = ConfigParser() - clientcfg.read(self.cfg_path) - - credcfg = ConfigParser() - credcfg.read(self.cred_path) - - if self.api_endpoint is None: - self.api_endpoint = clientcfg['service']['api_endpoint'] - token_url = clientcfg['service']['oauth_endpoint'] - - self.devid = clientcfg['device']['id'] - self.devname = clientcfg['device']['name'] - - # the OAuth ID is also used as the device ID - self.authid = credcfg['credentials']['id'] - client_secret = credcfg['credentials']['secret'] - - oauth_client = BackendApplicationClient(client_id=self.authid) - self.session = RefetchSession(client=oauth_client) - token = self.session.fetch_token(token_url=token_url+"/oauth2/token", client_id=self.authid, - client_secret=client_secret) - logging.info(f"Got OAuth2 token, expires in {token['expires_in']} seconds") - #force a token refetch - #oauth_client._expires_at -= 3700 - - - def _s3put(self, s3url, payload): - """payload can be byte string or open file handle - """ - rsp = requests.put(s3url, data=payload, headers={'Content-Type': 'application/octet-stream'}) - if rsp.status_code == 200: - logging.info(f"s3 upload success") - else: - logging.warning(f"s3 upload fail: {rsp.status_code}") - - def _s3get(self, s3url): - """return an open file handle - """ - with requests.get(s3url, stream=True) as rsp: - if rsp.status_code == 200: - getfile = tempfile.TemporaryFile() - shutil.copyfileobj(rsp.raw, getfile) - logging.info(f"s3 download success") - getfile.seek(0) - return getfile - else: - logging.warning(f"s3 download fail: {rsp.status_code}") - return None - - def update_status(self, update_config=False): - """ - Send the updated device status to the service. This is used as a heartbeat. - """ - data = { - "DeviceStatus": self.status, - "DeviceConfigurationFileExtension": "json" - } - rsp = self.session.put(self.api_endpoint + "/devices/" + self.devid, json=data) - if rsp.status_code == 200: - logging.info(f"UpdateDevice with status {data['DeviceStatus']}") - logging.debug(f"UpdateDevice request: {data}") - rsp = rsp.json() - logging.debug(f"UpdateDevice response: {rsp}") - #logging.info(f"ID check: {rsp['DeviceId']} {self.devid}") - # if you want to update the device config - if update_config: - logging.info(f"UpdateDevice: uploading soccfg") - self._s3put(rsp['UploadUrl'], json.dumps(self.soccfg)) - else: - logging.warning(f"UpdateDevice API error: {rsp.status_code}, {rsp.content}") - - def get_workload(self): - rsp = self.session.get(self.api_endpoint + "/devices/" + self.devid + "/workload") - if rsp.status_code == 200: - rsp = rsp.json() - logging.debug(f"GetDeviceWork response: {rsp}") - if not rsp: # if no workload is available, the response will be an empty list - logging.info(f"GetDeviceWork: no work for device") - return None - workid = rsp['WorkId'] - logging.info(f"GetDeviceWork: got work {workid}") - workurl = rsp['WorkloadUrl'] - try: - workfile = self._s3get(workurl) - return { - "id": workid, - "workload": workfile - } - except Exception as e: - logging.warning(f"GetDeviceWork S3 error: {e}") - return None - else: - logging.warning(f"GetDeviceWork API error: {rsp.status_code}, {rsp.content}") - return None - - def start_workload(self, workload): - self.resultsfile = tempfile.TemporaryFile() - logging.info("Started workload") - proc = multiprocessing.Process(target=self._run_workload, daemon=True, args=(self.soc, workload, self.resultsfile)) - proc.start() - return proc - - def _run_workload(self, soc, workfile, resultsfile): - - logging.info(f"Running workload") - #self.soc.run_workload(workload, resultsfile) - - if isinstance(soc, DummySoc): - workload = workfile.read() - workfile.close() - logging.info("DummySoc running workload: {workload}") - resultsfile.write(b"test") - resultsfile.seek(0) - time.sleep(10) - else: - with gzip.GzipFile(fileobj=workfile, mode='rb') as f: - proglist = json2progs(f) - logging.info(f"unpacked {len(proglist)} programs from workload") - with h5py.File(resultsfile,'w') as outf: - datagrp = outf.create_group("data", track_order=True) - newprog = QickProgram(soc) - for iProg, progdict in enumerate(proglist): - proggrp = datagrp.create_group(str(iProg)) - newprog.load_prog(progdict) - if progdict['acqtype']=='accumulated': - d_buf, d_avg, d_shots = newprog.acquire(soc, progress=False) - proggrp.create_dataset("avg", data=d_avg) - if progdict['save_raw']: - proggrp.create_dataset("raw", data=d_buf, compression="lzf") - if progdict['save_shots']: - proggrp.create_dataset("shots", data=d_shots, compression="lzf") - elif progdict['acqtype']=='decimated': - d_dec = newprog.acquire_decimated(soc, progress=False) - proggrp.create_dataset("dec", data=d_dec) - resultsfile.seek(0) - logging.info(f"Workload complete") - return - - def is_work_canceled(self, work_id): - # not yet implemented on the service - return False - #rsp = requests.get(self.api_endpoint + "/IsWorkCanceled") - #return rsp.json().get("IsCanceled") - - def upload_results(self, work_id): - self.resultsfile.seek(0) - logging.info(f"PutDeviceWork request for work {work_id}") - rsp = self.session.put(self.api_endpoint + "/devices/" + self.devid + "/workloads/" + work_id) - if rsp.status_code == 200: - rsp = rsp.json() - logging.debug(f"PutDeviceWork response: {rsp}") - try: - self._s3put(rsp['UploadUrl'], self.resultsfile) - logging.info("Uploaded results") - self.resultsfile.close() - except Exception as e: - logging.warning(f"PutDeviceWork S3 error: {e}") - else: - logging.warning(f"PutDeviceWork API error: {rsp.status_code}, {rsp.content}") - -if __name__ == "__main__": - #logging.getLogger().setLevel(logging.DEBUG) - logging.getLogger().setLevel(logging.INFO) - parser = argparse.ArgumentParser() - parser.add_argument("--api", type=str, default=None, help="URL of API endpoint") - parser.add_argument("-n", dest='interval', type=float, default=5.0, help="polling interval") - parser.add_argument("-d", action='store_true', help="run in dummy mode (use DummySoc instead of QickSoc)") - args = parser.parse_args() - - qick = QickClient(args.api, args.d) - - work = None - qick.update_status(update_config=True) - while True: - if qick.status == "ONLINE": - work = qick.get_workload() - if work: - qick.status = "BUSY" - work["process"] = qick.start_workload(work["workload"]) - work["timeout"] = time.time() + qick.timeout - time.sleep(args.interval) # sleep 5 seconds between polling - elif qick.status == "BUSY": - if qick.is_work_canceled(work["id"]) or time.time() > work["timeout"]: - logging.info("terminating workload due to cancel or timeout") - work["process"].terminate() - work["process"].join() - work["process"].close() - qick.upload_results(work["id"]) # upload partial results file - qick.status = "ONLINE" - elif not work["process"].is_alive(): - logging.info(f"workload completed, exit code {work['process'].exitcode}") - work["process"].close() - qick.upload_results(work["id"]) - time.sleep(args.interval) # sleep 5 seconds between polling TODO: this is a workaround - qick.status = "ONLINE" - else: - time.sleep(args.interval) # sleep 5 seconds between polling - qick.update_status() diff --git a/qick/aws/start_qick_client.sh b/qick/aws/start_qick_client.sh deleted file mode 100644 index 0828095..0000000 --- a/qick/aws/start_qick_client.sh +++ /dev/null @@ -1,12 +0,0 @@ -#!/bin/bash -# environment setup copied from /usr/local/bin/start_jupyter.sh -set -a -. /etc/environment -set +a -for f in /etc/profile.d/*.sh; do source $f; done - -dir=`dirname $0` -$dir/qick_client.py & -pid=$! -echo $pid > /tmp/qick.pid - diff --git a/qick/aws/user_client.py b/qick/aws/user_client.py deleted file mode 100644 index 0c82a93..0000000 --- a/qick/aws/user_client.py +++ /dev/null @@ -1,747 +0,0 @@ -#!/usr/bin/env python3 -# standard libraries -import logging -import argparse -import json -import gzip -import base64 -import getpass -import time -import datetime -import sys -import os -from configparser import ConfigParser -import tempfile -import shutil -# dependencies -import requests -# CLI dependency - not needed for the rest of the library -try: - from fire import Fire -except: - pass -# WorkloadManager dependencies - not needed for UserClient -try: - import h5py - from qick.helpers import progs2json -except: - pass - -class CognitoAuth(requests.auth.AuthBase): - TOKEN_PATH = os.path.expanduser('~/.cache/qick.tokens') - def __init__(self): - self.auth_url = None - self.client_id = None - self.username = None - self.pool_id = None - self.tokens = None - self.expire_time = None - self.token_email = None - - if os.path.exists(self.TOKEN_PATH): - with open(self.TOKEN_PATH, 'rt') as f: - self.update_tokens(json.load(f), replace_tokens=True, write_tokens=False) - - def __call__(self, r): - """This is called by the Session to set auth headers. - """ - if self.tokens is None or self.token_email != self.username: - self.initial_auth() - - # if we have less than 60 seconds till expiry, refresh tokens - if self.expire_time - time.time() < 60: - try: - self.refresh_auth() - except: - # if anything goes wrong with refresh, re-auth from scratch - # this should cover expired refresh tokens - self.initial_auth() - - r.headers['Authorization'] = self.auth_header - return r - - def update_tokens(self, new_tokens, replace_tokens=False, write_tokens=True): - if replace_tokens or self.tokens is None: - self.tokens = new_tokens - else: - self.tokens.update(new_tokens) - - # unpack the JWT to get the expiry timestamp - # JWT uses unpadded base64, need to add dummy padding: - # https://stackoverflow.com/questions/2941995/python-ignore-incorrect-padding-error-when-base64-decoding - access_token = self.tokens['AccessToken'] - access_payload = json.loads(base64.b64decode(access_token.split('.')[1] + '==')) - # the expiration time will tell us when to refresh - self.expire_time = access_payload['exp'] - - id_payload = json.loads(base64.b64decode(self.tokens['IdToken'].split('.')[1] + '==')) - # the e-mail will be checked against the config username - self.token_email = id_payload['email'] - logging.info(f"updated tokens: for user {self.token_email}, in groups {id_payload['cognito:groups']}") - - self.auth_header = ' '.join([self.tokens['TokenType'], access_token]) - - if write_tokens: - logging.info("writing updated tokens") - with open(self.TOKEN_PATH, 'wt') as f: - json.dump(self.tokens, f) - - def initial_auth(self): - print(f"initial auth for {self.username}:") - auth_response = self._do_auth_password() - """ - try: - auth_response = self._do_auth_srp() - #auth_response = self._do_auth_srp_warrant() - except: - auth_response = self._do_auth_password() - """ - if 'AuthenticationResult' not in auth_response: - raise RuntimeError("Login failed") - self.update_tokens(auth_response['AuthenticationResult'], replace_tokens=True) - - def refresh_auth(self): - logging.info("refreshing tokens") - refresh_response = self._auth_refresh(self.tokens['RefreshToken']) - if 'AuthenticationResult' not in refresh_response: - raise RuntimeError("Refresh failed") - # update tokens - self.update_tokens(refresh_response['AuthenticationResult']) - - def _do_auth_srp(self): - """this uses pysrp (standard SRP implementation) with patches from warrant (Cognito-specific) - https://stackoverflow.com/questions/41526205/implementing-user-srp-auth-with-python-boto3-for-aws-cognito - """ - logging.info("using pysrp-based SRP for initial auth") - import srp - import six, hmac, hashlib - def long_to_bytes(n): - l = list() - x = 0 - off = 0 - while x != n: - b = (n >> off) & 0xFF - l.append( chr(b) ) - x = x | (b << off) - off += 8 - # weird Cognito padding logic - if (b & 0x80) != 0: - l.append(chr(0)) - l.reverse() - return six.b(''.join(l)) - - def compute_hkdf(ikm, salt): - """ - Standard hkdf algorithm - :param {Buffer} ikm Input key material. - :param {Buffer} salt Salt value. - :return {Buffer} Strong key material. - @private - """ - info_bits = bytearray('Caldera Derived Key', 'utf-8') - prk = hmac.new(salt, ikm, hashlib.sha256).digest() - info_bits_update = info_bits + bytearray(chr(1), 'utf-8') - hmac_hash = hmac.new(prk, info_bits_update, hashlib.sha256).digest() - return hmac_hash[:16] - - def process_challenge(self, bytes_s, bytes_B): - - self.s = srp._pysrp.bytes_to_long( bytes_s ) - self.B = srp._pysrp.bytes_to_long( bytes_B ) - - N = self.N - g = self.g - k = self.k - - hash_class = self.hash_class - - # SRP-6a safety check - if (self.B % N) == 0: - return None - - self.u = srp._pysrp.H( hash_class, self.A, self.B, width=len(long_to_bytes(N)) ) - - # SRP-6a safety check - if self.u == 0: - return None - - self.x = srp._pysrp.gen_x( hash_class, self.s, self.I, self.p ) - self.v = pow(g, self.x, N) - self.S = pow((self.B - k*self.v), (self.a + self.u*self.x), N) - - hkdf = compute_hkdf(long_to_bytes(self.S), - long_to_bytes(self.u)) - return hkdf - - # patch pysrp with our hacked-up functions - srp._pysrp.long_to_bytes = long_to_bytes - srp._pysrp.User.process_challenge = process_challenge - - custom_n = 'FFFFFFFFFFFFFFFFC90FDAA22168C234C4C6628B80DC1CD1'\ - '29024E088A67CC74020BBEA63B139B22514A08798E3404DD' \ - 'EF9519B3CD3A431B302B0A6DF25F14374FE1356D6D51C245' \ - 'E485B576625E7EC6F44C42E9A637ED6B0BFF5CB6F406B7ED' \ - 'EE386BFB5A899FA5AE9F24117C4B1FE649286651ECE45B3D' \ - 'C2007CB8A163BF0598DA48361C55D39A69163FA8FD24CF5F' \ - '83655D23DCA3AD961C62F356208552BB9ED529077096966D' \ - '670C354E4ABC9804F1746C08CA18217C32905E462E36CE3B' \ - 'E39E772C180E86039B2783A2EC07A28FB5C55DF06F4C52C9' \ - 'DE2BCBF6955817183995497CEA956AE515D2261898FA0510' \ - '15728E5A8AAAC42DAD33170D04507A33A85521ABDF1CBA64' \ - 'ECFB850458DBEF0A8AEA71575D060C7DB3970F85A6E1E4C7' \ - 'ABF5AE8CDB0933D71E8C94E04A25619DCEE3D2261AD2EE6B' \ - 'F12FFA06D98A0864D87602733EC86A64521F2B18177B200C' \ - 'BBE117577A615D6C770988C0BAD946E208E24FA074E5AB31' \ - '43DB5BFCE0FD108E4B82D120A93AD2CAFFFFFFFFFFFFFFFF' - custom_g = "2" - - usr = srp.User("dummy", getpass.getpass(), hash_alg=srp.SHA256, ng_type=srp.NG_CUSTOM, - n_hex = custom_n, - g_hex = custom_g) - - _, A = usr.start_authentication() - data = {"AuthFlow": "USER_SRP_AUTH", - "ClientId": self.client_id, - "AuthParameters": {"USERNAME": self.username, - "SRP_A": A.hex()} - } - headers = {"X-Amz-Target": "AWSCognitoIdentityProviderService.InitiateAuth", - "Content-Type": "application/x-amz-json-1.1" - } - rsp = requests.post(self.auth_url, headers=headers, json=data) - if rsp.status_code == 200: - rsp = rsp.json() - else: - raise RuntimeError(f"SRP auth error: {rsp.status_code}, {rsp.content}") - - assert rsp['ChallengeName']=="PASSWORD_VERIFIER" - challenge = rsp['ChallengeParameters'] - - user_id_for_srp = challenge['USER_ID_FOR_SRP'] - usr.I = self.pool_id.split('_')[1]+user_id_for_srp - - salt = challenge['SALT'] - srp_b = challenge['SRP_B'] - secret_block = challenge['SECRET_BLOCK'] - timestamp = datetime.datetime.now(tz=datetime.timezone.utc).strftime("%a %b %d %H:%M:%S %Z %Y") - - hkdf = usr.process_challenge(bytes.fromhex(salt.zfill(32)), bytes.fromhex(srp_b.zfill(768))) - - secret_block_bytes = base64.standard_b64decode(secret_block) - msg = bytearray(self.pool_id.split('_')[1], 'utf-8') + bytearray(user_id_for_srp, 'utf-8') + \ - bytearray(secret_block_bytes) + bytearray(timestamp, 'utf-8') - hmac_obj = hmac.new(hkdf, msg, digestmod=hashlib.sha256) - signature_string = base64.standard_b64encode(hmac_obj.digest()).decode() - - data = {"ChallengeName": "PASSWORD_VERIFIER", - "ClientId": self.client_id, - "ChallengeResponses": {"USERNAME": challenge['USERNAME'], - "TIMESTAMP": timestamp, - "PASSWORD_CLAIM_SECRET_BLOCK": secret_block, - "PASSWORD_CLAIM_SIGNATURE": signature_string - } - } - headers["X-Amz-Target"] = "AWSCognitoIdentityProviderService.RespondToAuthChallenge" - - rsp = requests.post(self.auth_url, headers=headers, json=data) - if rsp.status_code == 200: - return rsp.json() - else: - raise RuntimeError(f"SRP challenge error: {rsp.status_code}, {rsp.content}") - - - def _do_auth_srp_warrant(self): - logging.info("using warrant-based SRP for initial auth") - """this uses aws_srp.py from https://github.com/capless/warrant - """ - from aws_srp import AWSSRP - aws = AWSSRP(username=self.username, password=getpass.getpass(), pool_id=self.pool_id, - client_id=self.client_id, pool_region=self.pool_id.split('_')[0]) - return aws.authenticate_user() - - - def _do_auth_password(self): - logging.info("using password for initial auth") - data = {"AuthFlow": "USER_PASSWORD_AUTH", - "ClientId": self.client_id, - "AuthParameters": {"USERNAME":self.username, "PASSWORD":getpass.getpass()} - } - headers = {"X-Amz-Target": "AWSCognitoIdentityProviderService.InitiateAuth", - "Content-Type": "application/x-amz-json-1.1" - } - rsp = requests.post(self.auth_url, headers=headers, json=data) - if rsp.status_code == 200: - return rsp.json() - else: - raise RuntimeError(f"password authentication error: {rsp.status_code}, {rsp.content}") - - def _auth_refresh(self, refresh_token): - data = {"AuthFlow": "REFRESH_TOKEN_AUTH", - "ClientId": self.client_id, - "AuthParameters": {"REFRESH_TOKEN": refresh_token} - } - headers = {"X-Amz-Target": "AWSCognitoIdentityProviderService.InitiateAuth", - "Content-Type": "application/x-amz-json-1.1" - } - rsp = requests.post(self.auth_url, headers=headers, json=data) - if rsp.status_code == 200: - return rsp.json() - else: - raise RuntimeError(f"token refresh error: {rsp.status_code}, {rsp.content}") - -class WorkloadManager(): - """A base class which allows you to encapsulate a list of programs as a workload. - You should overload the do_stuff() method to handle the creation of programs and processing of results. - - Parameters - ---------- - soccfg : QickConfig - Configuration for the device this workload will run on. - """ - def __init__(self, soccfg): - self.soccfg = soccfg - self.proglist = [] - self.progdicts = [] - self.results = None - self._make_progs() - - def add_program(self, prog): - """Add a program to the program list. - This should be called inside do_stuff() when make_progs=True. - - Parameters - ---------- - prog : QickProgram - A program to add to the workload - """ - self.proglist.append(prog) - - def add_acquire(self, prog, save_raw=False, save_shots=False): - """Add accumulated readout of a program. - This should be called inside do_stuff() when write_progs=True. - - Parameters - ---------- - prog : QickProgram - A program to execute - save_raw : bool - Save raw IQ values for each shot. - save_shots : bool - Save thresholded values for each shot. - """ - dump = prog.dump_prog() - dump['acqtype'] = "accumulated" - dump['save_raw'] = save_raw - dump['save_shots'] = save_shots - self.progdicts.append(dump) - - def add_decimated(self, prog): - """Add decimated readout of a program. - This should be called inside do_stuff() when write_progs=True. - """ - dump = prog.dump_prog() - dump['acqtype'] = "decimated" - self.progdicts.append(dump) - - def _make_progs(self): - """Make all the programs. - """ - self.do_stuff(make_progs=True) - - def _get_progs(self): - """Generator function that returns datasets from a results file. - """ - for prog in self.proglist: - yield prog - - def write_progs(self, filepath=None): - """Write all programs to a workload file. - - Parameters - ---------- - filepath : str or None - Path for the workload file. - If provided, write and close the file. - If None, create and return an open tempfile. - - Returns - ------- - file or None - Workload as a temporary file, if filepath was None. - """ - if filepath is None: - outfile = tempfile.TemporaryFile() - else: - outfile = open(filepath, 'wb') - self.prog_iterator = self._get_progs() - self.do_stuff(write_progs=True) - with gzip.GzipFile(fileobj=outfile, mode='wb') as f: - f.write(progs2json(self.progdicts).encode()) - if filepath is None: - return outfile - else: - outfile.close() - - def _get_results(self, outf): - """Generator function that returns datasets from a results file. - - Parameters - ---------- - outf : h5py.File - HDF5 results file. - """ - datagrp = outf["data"] - for name, proggrp in datagrp.items(): - yield proggrp - - def read_results(self, resultsfile): - """Iterate through a results file. - - Parameters - ---------- - resultsfile : str or file - HDF5 results file path or file object. - """ - self.prog_iterator = self._get_progs() - with h5py.File(resultsfile,'r') as outf: - self.result_iterator = self._get_results(outf) - self.do_stuff(read_results=True) - - def do_stuff(self, make_progs=False, write_progs=False, read_results=False): - """Initialize the workload and process results. - You will not call this method directly; it is called internally at initialization and by write_progs() and read_results(). - For each program you run as part of this workload, you must do the following: - - * If make_progs is True, create a QickProgram and call add_program() to add it to the program list. - If False, call next(self.prog_iterator) to pop a program from the program list. - - * If write_progs is True, call add_acquire() or add_decimated() to define how you want this program to be run. - - * If read_results is True, call next(self.result_iterator) to pop a dataset from the results file. - Process the dataset as needed. - - Parameters - ---------- - make_progs : bool - Create program objects and fill the program list. - write_progs : bool - For each program in the program list, define how to run it and what results to save. - read_results : bool - Read and analyze the results file. - """ - -class UserClient(): - """Provides a Python API to make requests to the cloud service. - A configuration file (containing API URLs and a username) is expected at ~/.config/qick.conf or /etc/qick/config. - A default device ID may also be included in the configuration file. - """ - def __init__(self): - configpaths = [os.path.expanduser('~/.config/qick.conf'), - '/etc/qick/config'] - - self.config = ConfigParser() - self.config.read(configpaths) - - - auth = CognitoAuth() - auth.username = self.config['user']['username'] - auth.auth_url = self.config['service']['cognito_url'] - auth.client_id = self.config['service']['clientid'] - auth.pool_id = self.config['service']['cognito_userpool'] # only needed for SRP - - self.api_endpoint = self.config['service']['api_endpoint'] - - self.session = requests.Session() - self.session.auth = auth - - def add_user(self, email, fullname): - """Create a user account on the cloud service. - A suggested config file will be printed. - The user will get an e-mail with a temporary password. - - Parameters - ---------- - email : str - A valid e-mail address for the user, required to be unique - fullname : str - A display name for the user, not required to be unique - """ - data = { - "Email": email, - "FullName": fullname - } - rsp = self.session.post(self.api_endpoint + '/users', json=data) - if rsp.status_code == 200: - print("User successfully added! They should check their e-mail for a temporary password.") - print() - print("They should put the following in ~/.config/qick.conf:") - print("[service]") - print(f"api_endpoint = {self.api_endpoint}") - print(f"cognito_url = {self.session.auth.auth_url}") - print(f"clientid = {self.session.auth.client_id}") - print(f"cognito_userpool = {self.session.auth.pool_id}") - print("[user]") - print(f"username = {email}") - - else: - logging.warning(f"AddUser API error: {rsp.status_code}, {rsp.content}") - - def add_device(self, device_name, refresh_timeout=60): - """Create a workload queue on the cloud service. - Suggested config and credentials files will be printed. - - Parameters - ---------- - device_name : str - A display name for the device, not required to be unique - refresh_timeout : int - A timeout (in seconds), after which the service will decide the device is offline if it hasn't received a status update. - The normal update interval for the device client is 5 seconds. - """ - data = { - "DeviceName": device_name, - "RefreshTimeout": refresh_timeout - } - rsp = self.session.post(self.api_endpoint + '/devices', json=data) - if rsp.status_code == 201: - rsp = rsp.json() - print("Device successfully added!") - print() - print("Put the following in the config file /etc/qick/config:") - print("[service]") - print(f"api_endpoint = {self.api_endpoint}") - print(f"oauth_endpoint = {self.config['service']['oauth_endpoint']}") - print("[device]") - print(f"name = {rsp['DeviceName']}") - print(f"id = {rsp['DeviceId']}") - print() - print("If using UserClient for workload submission, the [device] block is needed in the client config as well.") - print() - print("Put the following in the device credentials file /etc/qick/credentials:") - print("[credentials]") - print(f"id = {rsp['ClientId']}") - print(f"secret = {rsp['ClientSecret']}") - else: - logging.warning(f"AddDevice API error: {rsp.status_code}, {rsp.content}") - - def get_devices(self): - """Query the cloud service for a list of devices. - - Returns - ------- - list of dict - All devices - """ - rsp = self.session.get(self.api_endpoint + '/devices') - if rsp.status_code == 200: - return rsp.json() - else: - logging.warning(f"GetDevices API error: {rsp.status_code}, {rsp.content}") - return None - - def _s3put(self, s3url, payload): - """Upload a payload to a pre-signed S3 PUT URL. - - Parameters - ---------- - s3url : str - Pre-signed S3 URL - payload : file - A file to be uplaoded - """ - rsp = requests.put(s3url, data=payload, headers={'Content-Type': 'application/octet-stream'}) - if rsp.status_code == 200: - logging.info(f"s3 upload success") - else: - logging.warning(f"s3 upload fail: {rsp.status_code}") - - def _s3get(self, s3url): - """Download a pre-signed S3 GET URL. - - Parameters - ---------- - s3url : str - Pre-signed S3 URL - - Returns - ------- - file - The downloaded file, as a temporary file - """ - with requests.get(s3url, stream=True) as rsp: - if rsp.status_code == 200: - getfile = tempfile.TemporaryFile() - shutil.copyfileobj(rsp.raw, getfile) - getfile.seek(0) - return getfile - else: - logging.warning(f"s3 download fail: {rsp.status_code}") - return None - - def get_soccfg(self, device_id=None): - """Query the cloud service for the most recently uploaded configuration of a device. - The config file is parsed as JSON. - - Parameters - ---------- - device_id : str or None - The unique ID of the device. - If None, the device ID will be read from the user client configuration. - - Returns - ------- - dict - Device configuration, to be loaded into a QickCOnfig object - """ - if device_id is None: - device_id = self.config['device']['id'] - rsp = self.session.get(self.api_endpoint + '/devices/' + device_id) - if rsp.status_code == 200: - logging.info(f"GetDevice response: {rsp.json()}") - rsp = rsp.json() - deviceid = rsp['DeviceId'] - devicename = rsp['DeviceName'] - devicestatus = rsp['DeviceStatus'] - lastrefreshed = rsp['LastRefreshed'] - refreshtimeout = rsp['RefreshTimeout'] - configurl = rsp['DeviceConfigurationUrl'] - try: - cfgfile = self._s3get(configurl) - devcfg = json.load(cfgfile) - cfgfile.close() - except Exception as e: - logging.warning(f"GetDevice S3 error: {e}") - return None - logging.info(f"GetDevice device config from S3: {devcfg}") - return devcfg - else: - logging.warning(f"GetDevice API error: {rsp.status_code}, {rsp.content}") - return None - - def create_work(self, workloadfile, device_id=None, priority="LOW"): - """Upload a workload into a device queue on the cloud service. - The config file is parsed as JSON. - - Parameters - ---------- - workloadfile : file - A file-like object to be uploaded to the queue. - device_id : str or None - The unique ID of the device. - If None, the device ID will be read from the user client configuration. - priority : str - The priority to be assigned to this workload. - The valid values are defined by the cloud service. - - Returns - ------- - str - Workload ID, for checking status and downloading results - """ - workloadfile.seek(0) - if device_id is None: - device_id = self.config['device']['id'] - data = { - "DeviceId": device_id, - "Priority": priority - } - rsp = self.session.post(self.api_endpoint + "/workloads", json=data) - if rsp.status_code == 201: - logging.info(f"UpdateDevice request: {data}") - logging.info(f"UpdateDevice response: {rsp.json()}") - rsp = rsp.json() - work_id = rsp['WorkId'] - upload_url = rsp['UploadUrl'] - try: - self._s3put(rsp['UploadUrl'], workloadfile) - logging.info("Uploaded workload") - workloadfile.close() - except Exception as e: - logging.warning(f"CreateWork S3 error: {e}") - return work_id - else: - logging.warning(f"CreateWork API error: {rsp.status_code}, {rsp.content}") - return None - - def get_work(self, work_id): - """Query the cloud service for the status of a workload. - - Parameters - ---------- - work_id : str - The workload ID. - - Returns - ------- - dict - Information about the workload. - """ - rsp = self.session.get(self.api_endpoint + '/workloads/' + work_id) - if rsp.status_code == 200: - return rsp.json() - else: - logging.warning(f"GetWork API error: {rsp.status_code}, {rsp.content}") - return None - - def wait_until_done(self, work_id, interval=1.0, progress=True): - """Poll the cloud service until the workload reaches DONE status. - - Parameters - ---------- - work_id : str - The workload ID. - progress : bool - Print the workload status as it progresses. - interval : float - Polling interval (in seconds). - """ - last_state = None - while True: - state = self.get_work(work_id)['WorkStatus'] - if state != last_state: - if progress: - if last_state is not None: - print() - print("workload is " + state, end='') - if state == 'DONE': - if progress: print() - break - last_state = state - time.sleep(interval) - if progress: print('.', end='') - - def get_results(self, work_id): - """Download workload results from the cloud service. - If the workload is not in DONE status, raise an error. - - Parameters - ---------- - work_id : str - The workload ID. - - Returns - ------- - file - A temporary file with the workload results (typically an HDF5 file). - """ - rsp = self.session.get(self.api_endpoint + '/workloads/' + work_id) - if rsp.status_code == 200: - rsp = rsp.json() - if rsp['WorkStatus'] != 'DONE': - raise RuntimeError("get_results error: workload is not in DONE status") - try: - resultsfile = self._s3get(rsp['WorkloadResultUrl']) - return resultsfile - except Exception as e: - logging.warning(f"GetWork S3 error: {e}") - return None - else: - logging.warning(f"GetWork API error: {rsp.status_code}, {rsp.content}") - return None - - -if __name__ == "__main__": - logging.getLogger().setLevel(logging.WARNING) - - client = UserClient() - Fire(client) diff --git a/qick/docs/Makefile b/qick/docs/Makefile deleted file mode 100644 index e9e0245..0000000 --- a/qick/docs/Makefile +++ /dev/null @@ -1,192 +0,0 @@ -# Makefile for Sphinx documentation -# - -# You can set these variables from the command line. -SPHINXOPTS = -SPHINXBUILD = sphinx-build -PAPER = -BUILDDIR = _build - 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The pseudo-XML files are in $(BUILDDIR)/pseudoxml." diff --git a/qick/docs/README.md b/qick/docs/README.md deleted file mode 100644 index 8cbbaa6..0000000 --- a/qick/docs/README.md +++ /dev/null @@ -1,16 +0,0 @@ -QICK: Quantum Instrumentation Controller Kit -=========================================== - - -**This repository contains the source files for the documentation of the Quantum Instrumentation Controller Kit software, generated via Sphinx and available on ReadTheDocs.** - - -Documentation -------------- - -The documentation for QICK is available at: https://qick-docs.readthedocs.io - - -Documentation generated from this project: http://romanvm.github.io/sphinx_tutorial/ - -License: [Creative Commons Share Alike](http://creativecommons.org/licenses/by-sa/4.0/) diff --git a/qick/docs/_static/custom.css b/qick/docs/_static/custom.css deleted file mode 100644 index bb98d6d..0000000 --- a/qick/docs/_static/custom.css +++ /dev/null @@ -1,21 +0,0 @@ -body { - --themecolor: black; -} - -.wy-side-nav-search { - background-color: var(--themecolor); -} -.wy-nav-top { - background-color: var(--themecolor); -} - -/* override table width restrictions */ -.wy-table-responsive table td, .wy-table-responsive table th { - /* !important prevents the common CSS stylesheets from - overriding this as on RTD they are loaded after this stylesheet */ - white-space: normal !important; -} - -.wy-table-responsive { - overflow: visible !important; -} \ No newline at end of file diff --git a/qick/docs/cheatsheet.rst b/qick/docs/cheatsheet.rst deleted file mode 100644 index d26bc1f..0000000 --- a/qick/docs/cheatsheet.rst +++ /dev/null @@ -1,125 +0,0 @@ -QICK software quick reference -================================================= - -Quick reference -############### - -.. list-table:: - :widths: 50 50 - :header-rows: 1 - - * - Python calls - - - * - ``soc.tproc.single_write(addr=imm, data=variable)`` - - writes the value ``variable`` to the data memory address ``imm``. - -.. list-table:: - :widths: 50 50 - :header-rows: 1 - - * - ASM_Program calls - - - * - ``p.memri(p, r, imm, 'comment')`` - - reads the data memory at the address specified by ``imm`` and writes the result into page ``p``, register ``r``. - * - ``p.regwi(p,r,value)`` - - writes the ``value`` to page ``p``, register ``r``. - * - ``p.bitwi(p, rDst, rSrc, operation, value)`` - - performs the bitwise ``operation`` on the contents of page ``p``, register ``rSrc`` and ``value`` and writes the result in page ``p``, register ``rDst``. ``rSrc`` and ``rDst`` may be the same or different. - * - ``p.bitw(p, rDst, rSrc1, operation, rSrc2`` - - performs the bitwise ``operation`` on two source registers (``rSrc1`` and ``rSrc2``) and puts the result in the destination register ``rDst``, where all three registers are on the same page ``p``. - * - ``p.seti(channel, p, rSrc, time)`` - - takes the value at page ``p``, register ``rSrc`` and sends it to ``channel`` that the specified ``time``. - * - ``p.label(labelName)`` - - marks this location in the program, for use by the ``loopz`` and ``condj`` commands. - * - ``p.set(channel, p, ra, rb,rc,rd,re,time)`` - - sends the values on page ``p`` registers ``ra``, ``rb``, ``rc``, ``rd``, ``re`` to ``channel`` at ``time``. The registers ``ra`` through ``re`` contain, in order, 16-bit values of frequency, phase, address, gain, and ( ``nsamp`` , ``outsel`` , ``mode`` , ``stdysel`` ). - * - ``p.sync(p,r)`` - - synchronizes the internal time offset to the value specified by page ``p``,register ``r``. - * - ``p.synci(p,timeOffset)`` - - synchronizes the internal time offset by ``timeOffset``. - -.. list-table:: - :widths: 50 50 - :header-rows: 1 - - * - QickProgram bitwise operations - - - * - ``<<`` - - shifts bits left by ``value`` bits, ignores ``rSrc`` - * - ``|`` - - or - * - ``&`` - - and - * - ``^`` - - exclusive or - * - ``~`` - - not ``value``, ignores ``rSrc`` - -tProcessor register information -############################### - -The tproc contains 8 pages of 32 registers each, making 256 registers in total. Each register is 32 bits wide. - -Timing -###### - -* Every generator contains a timed FIFO queue. - There is only one master clock time `t_master`, which is shared by all timed queues. - - * Treat :meth:`~qick.qick_asm.QickProgram.trigger` as a generator channel, i.e. equivalent to :meth:`~qick.qick_asm.QickProgram.pulse` in terms of clocks. - -* The tproc executes commands as soon as possible, meaning it has no concept of the master time (aside from wait commands, explained later). - It only cares about what point it is at in your code. - There is a master time offset `t_off`, which is incremented by sync commands. - When executed by the tproc, ``trigger(t)`` and ``pulse(t)`` commands are appended to the appropriate queue with a timestamp of ``t_off + t``. - -* A generator plays pulses in the order received. - It waits to play each pulse until the previous pulse is complete and the master clock time equals (or exceeds) the command timestamp. - -* ``pulse(ch,t)`` will play the pulse at ``t`` relative to the clock as defined by the sync command that has been most recently executed by the tproc, UNLESS it is delayed by a wait command (the generator can't play a pulse before the tproc executes the command) or another pulse command (the generator can't cut one pulse short to play the next one). - In that case, it will play at time ``t`` or at the end of the wait time/previous pulse, whatever is latest. - - * To make life easier, you can just always call ``pulse(ch, t=0)``, which will just play the pulse at the next earliest possible time. Then insert simple waits between pulses using ``sync_all(t=wait_time)``. - -* wait commands pause the tproc (i.e. pauses execution of commands). - They do not affect the master time. - Any commands lower down in your code, even if scheduled for some time (defined by the master time) during the wait period, will execute, at the earliest, immediately after the end of the wait period. - - * wait commands are necessary to use with readout/data acquisition timing management, as the tproc does not know when pulses/readout finish and you need to force it to wait for readout to finish. - In other words, you should have a wait at the end of a loop (or the tproc will tell the software to read data from the buffer too soon), or before a ``read`` command (e.g. for feedback). - `This is the only reason to use wait commands.` - - * ``waiti(t)`` is the generic form of wait, which pauses the tproc until the master clock time equals ``t_off + t``. Note ``waiti`` has a channel argument, but the channel argument does nothing! - - * :meth:`~qick.qick_asm.QickProgram.wait_all` calculates the end of all readout pulses and waits until that time + ``t``. - -* sync commands increment the master time offset (used by all gen channels). - The effect is to push back the play time of subsequent commands by that increment. - - * ``sync_i(t)`` is the generic form of sync. - - * The safer version :meth:`~qick.qick_asm.QickProgram.sync_all` calculates the end of the last pulse played + ``t``, and sets the master time offset to that value. - - - -Signal generator options -######################## - -Use ``stdysel`` to select what value is output continuously by the signal generator after the generation of a pulse. - -* 0: the last calculated sample of the pulse -* 1: a zero value - -Use ``mode`` to select whether the output is periodic or one-shot. Here is what happens after generating the specified number of samples. Look in the queue to see if there is a new waveform to generate. If there is a new waveform in the queue, remove it from the queue and generate it. If there is not, use the value of ``mode`` to decide what to do. - -* 0: stop -* 1: repeat the current waveform - -Then continue looking for a new waveform. - -Use ``outsel`` to select the output source. The output is complex. Tables define envelopes for I and Q. - -* 0: product of table and DDS -* 1: DDS -* 2: from the table for the real part, and zeros for the imaginary part -* 3: always zero diff --git a/qick/docs/conf.py b/qick/docs/conf.py deleted file mode 100644 index 69366d3..0000000 --- a/qick/docs/conf.py +++ /dev/null @@ -1,342 +0,0 @@ -#!/usr/bin/env python3 -# -*- coding: utf-8 -*- -# -# Sphinx Apidoc Turorial documentation build configuration file, created by -# sphinx-quickstart on Fri Jan 8 20:52:00 2016. -# -# This file is execfile()d with the current directory set to its -# containing dir. -# -# Note that not all possible configuration values are present in this -# autogenerated file. -# -# All configuration values have a default; values that are commented out -# serve to show the default. - -import sys -import os -import pathlib - -## Make your modules available in sys.path -here = pathlib.Path(__file__).parent.resolve() -sys.path.insert(0, (here / '../qick_lib').resolve().as_posix()) -print(sys.path) - -def get_version(rel_path): - """ - qick_lib/qick/VERSION is a text file containing only the version number. - """ - return (here / rel_path).read_text().strip() - -# If extensions (or modules to document with autodoc) are in another directory, -# add these directories to sys.path here. If the directory is relative to the -# documentation root, use os.path.abspath to make it absolute, like shown here. -#sys.path.insert(0, os.path.abspath('.')) - -# -- General configuration ------------------------------------------------ - -# If your documentation needs a minimal Sphinx version, state it here. -#needs_sphinx = '1.0' - -# Add any Sphinx extension module names here, as strings. They can be -# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom -# ones. -extensions = [ - 'sphinx.ext.autodoc', - 'sphinx.ext.viewcode', - 'sphinx.ext.intersphinx', - 'sphinx.ext.mathjax', - ## Include autosymmary - 'sphinx.ext.autosummary', - 'sphinx.ext.napoleon', -] - -## Include Python objects as they appear in source files -## Default: alphabetically ('alphabetical') -autodoc_member_order = 'bysource' -## Default flags used by autodoc directives -autodoc_default_options = { - 'members': True, - 'show-inheritance': True, -} - -autodoc_mock_imports = ["pynq", "xrfclk", "xrfdc"] - -## Generate autodoc stubs with summaries from code -autosummary_generate = True - -# Add any paths that contain templates here, relative to this directory. -templates_path = ['_templates'] - -# The suffix(es) of source filenames. -# You can specify multiple suffix as a list of string: -# source_suffix = ['.rst', '.md'] -source_suffix = '.rst' - -# The encoding of source files. -#source_encoding = 'utf-8-sig' - -# The master toctree document. -master_doc = 'index' - -# General information about the project. -project = 'qick' -copyright = '2021, openquantumhardware' -author = 'openquantumhardware' - -# The version info for the project you're documenting, acts as replacement for -# |version| and |release|, also used in various other places throughout the -# built documents. -# -# The short X.Y version. -version = get_version("../qick_lib/qick/VERSION") -# The full version, including alpha/beta/rc tags. -release = version - -# The language for content autogenerated by Sphinx. Refer to documentation -# for a list of supported languages. -# -# This is also used if you do content translation via gettext catalogs. -# Usually you set "language" from the command line for these cases. -language = 'en' - -# There are two options for replacing |today|: either, you set today to some -# non-false value, then it is used: -#today = '' -# Else, today_fmt is used as the format for a strftime call. -#today_fmt = '%B %d, %Y' - -# List of patterns, relative to source directory, that match files and -# directories to ignore when looking for source files. -exclude_patterns = ['_build'] - -# The reST default role (used for this markup: `text`) to use for all -# documents. -#default_role = None - -# If true, '()' will be appended to :func: etc. cross-reference text. -#add_function_parentheses = True - -# If true, the current module name will be prepended to all description -# unit titles (such as .. function::). -#add_module_names = True - -# If true, sectionauthor and moduleauthor directives will be shown in the -# output. They are ignored by default. -#show_authors = False - -# The name of the Pygments (syntax highlighting) style to use. -pygments_style = 'sphinx' - -# A list of ignored prefixes for module index sorting. -#modindex_common_prefix = [] - -# If true, keep warnings as "system message" paragraphs in the built documents. -#keep_warnings = False - -# If true, `todo` and `todoList` produce output, else they produce nothing. -todo_include_todos = False - - -# -- Options for HTML output ---------------------------------------------- - -# The theme to use for HTML and HTML Help pages. See the documentation for -# a list of builtin themes. -html_theme = 'sphinx_rtd_theme' - -html_theme_options = { - 'logo_only': True, -} -# Theme options are theme-specific and customize the look and feel of a theme -# further. For a list of options available for each theme, see the -# documentation. - -# Add any paths that contain custom themes here, relative to this directory. -#html_theme_path = [] - -# The name for this set of Sphinx documents. If None, it defaults to -# " v documentation". -#html_title = None - -# A shorter title for the navigation bar. Default is the same as html_title. -#html_short_title = None - -# The name of an image file (relative to this directory) to place at the top -# of the sidebar. -html_logo = "../graphics/logoQICK.svg" - -# The name of an image file (within the static path) to use as favicon of the -# docs. This file should be a Windows icon file (.ico) being 16x16 or 32x32 -# pixels large. -#html_favicon = None - -# Add any paths that contain custom static files (such as style sheets) here, -# relative to this directory. They are copied after the builtin static files, -# so a file named "default.css" will overwrite the builtin "default.css". -html_static_path = ['_static'] - -# html_css_files = ['custom.css'] - -# Add any extra paths that contain custom files (such as robots.txt or -# .htaccess) here, relative to this directory. These files are copied -# directly to the root of the documentation. -#html_extra_path = [] - -# If not '', a 'Last updated on:' timestamp is inserted at every page bottom, -# using the given strftime format. -#html_last_updated_fmt = '%b %d, %Y' - -# If true, SmartyPants will be used to convert quotes and dashes to -# typographically correct entities. -#html_use_smartypants = True - -# Custom sidebar templates, maps document names to template names. -## Sidebars configuration for alabaster theme - -html_sidebars = { - '**': [ - 'about.html', - 'navigation.html', - 'searchbox.html', - ] -} - -# Additional templates that should be rendered to pages, maps page names to -# template names. -#html_additional_pages = {} - -# If false, no module index is generated. -#html_domain_indices = True - -# If false, no index is generated. -#html_use_index = True - -# If true, the index is split into individual pages for each letter. -#html_split_index = False - -# If true, links to the reST sources are added to the pages. - -## I don't like links to page reST sources -html_show_sourcelink = True - -# If true, "Created using Sphinx" is shown in the HTML footer. Default is True. -#html_show_sphinx = True - -# If true, "(C) Copyright ..." is shown in the HTML footer. Default is True. -#html_show_copyright = True - -# If true, an OpenSearch description file will be output, and all pages will -# contain a tag referring to it. The value of this option must be the -# base URL from which the finished HTML is served. -#html_use_opensearch = '' - -# This is the file name suffix for HTML files (e.g. ".xhtml"). -#html_file_suffix = None - -# Language to be used for generating the HTML full-text search index. -# Sphinx supports the following languages: -# 'da', 'de', 'en', 'es', 'fi', 'fr', 'h', 'it', 'ja' -# 'nl', 'no', 'pt', 'ro', 'r', 'sv', 'tr' -#html_search_language = 'en' - -# A dictionary with options for the search language support, empty by default. -# Now only 'ja' uses this config value -#html_search_options = {'type': 'default'} - -# The name of a javascript file (relative to the configuration directory) that -# implements a search results scorer. If empty, the default will be used. -#html_search_scorer = 'scorer.js' - -# Output file base name for HTML help builder. -htmlhelp_basename = 'SphinxApidocTurorialdoc' - -# -- Options for LaTeX output --------------------------------------------- - -latex_elements = { -# The paper size ('letterpaper' or 'a4paper'). -#'papersize': 'letterpaper', - -# The font size ('10pt', '11pt' or '12pt'). -#'pointsize': '10pt', - -# Additional stuff for the LaTeX preamble. -#'preamble': '', - -# Latex figure (float) alignment -#'figure_align': 'htbp', -} - -# Grouping the document tree into LaTeX files. List of tuples -# (source start file, target name, title, -# author, documentclass [howto, manual, or own class]). -latex_documents = [ - (master_doc, 'SphinxApidocTurorial.tex', 'Sphinx Apidoc Turorial Documentation', - 'Roman Miroshnychenko', 'manual'), -] - -# The name of an image file (relative to this directory) to place at the top of -# the title page. -#latex_logo = None - -# For "manual" documents, if this is true, then toplevel headings are parts, -# not chapters. -#latex_use_parts = False - -# If true, show page references after internal links. -#latex_show_pagerefs = False - -# If true, show URL addresses after external links. -#latex_show_urls = False - -# Documents to append as an appendix to all manuals. -#latex_appendices = [] - -# If false, no module index is generated. -#latex_domain_indices = True - - -# -- Options for manual page output --------------------------------------- - -# One entry per manual page. List of tuples -# (source start file, name, description, authors, manual section). -man_pages = [ - (master_doc, 'sphinxapidocturorial', 'Sphinx Apidoc Turorial Documentation', - [author], 1) -] - -# If true, show URL addresses after external links. -#man_show_urls = False - - -# -- Options for Texinfo output ------------------------------------------- - -# Grouping the document tree into Texinfo files. List of tuples -# (source start file, target name, title, author, -# dir menu entry, description, category) -texinfo_documents = [ - (master_doc, 'SphinxApidocTurorial', 'Sphinx Apidoc Turorial Documentation', - author, 'SphinxApidocTurorial', 'One line description of project.', - 'Miscellaneous'), -] - -# Documents to append as an appendix to all manuals. -#texinfo_appendices = [] - -# If false, no module index is generated. -#texinfo_domain_indices = True - -# How to display URL addresses: 'footnote', 'no', or 'inline'. -#texinfo_show_urls = 'footnote' - -# If true, do not generate a @detailmenu in the "Top" node's menu. -#texinfo_no_detailmenu = False - -# Example configuration for intersphinx: refer to the Python standard library. -## Add Python version number to the default address to corretcly reference -## the Python standard library -intersphinx_mapping = {'python': ('https://docs.python.org/3.7', None), - 'pynq': ('https://pynq.readthedocs.io/en/v2.7.0', None)} - - -def setup(app): - app.add_css_file("custom.css" ) diff --git a/qick/docs/firmware.rst b/qick/docs/firmware.rst deleted file mode 100644 index 76dce50..0000000 --- a/qick/docs/firmware.rst +++ /dev/null @@ -1,59 +0,0 @@ -QICK firmware -================================================= - -This system includes the following components: - -* 1 output channels connected to PMOD0-3 and triggers for Readout Block. -* 7 output channels connected to DACs. -* 2 input channels connected to ADCs. -* 1 instance of tProcessor 64-bit instructions, 32-bit registers. - -Sampling frequency of ADC blocks is given by the variable ``soc.fs_adc``. Sampling frequency of DACs is stored in variable ``soc.fs_adc``. Fast-speed buffers were removed to save memory space. Raw data can be captured after x8 down-sampling. - -Output channels driving DACs use the updated Signal Generator V4, which has the possibility to upload I/Q envelopes, and uses 32-bit resolution for both frequency and phase. The format of the control word was updated accordingly to accomodate the bits. See example asm files for a detailed description of the fields. The maximum length of the I/Q envelopes is given by the variable ``soc.gens[i].MAX_LENGTH``. - -The readout block is actually built around two IPs: readout and average + buffer. Readout block includes a digital down-convertion, FIR filtering and decimation by 8. DDS frequency is configured using a register of the readout block and it is not intended to support real-time frequency hopping as in the Signal Generator side. After frequency shifting, filtering and decimation, the data stream is sent to the Average + Buffer block, which internally can store raw samples or perform the sum of the specified number of samples. The process is started with the external trigger signal, connected to output Channel 0 of tProcessor. The user can opt to route the input, the DDS wave or the frequency shifted signal to the FIR and decimation by 8 stage. This is done using a output selection register of the readout block. Regarding the buffering capabilities, the average section of the block has a buffer of ``soc.avg_bufs[i].AVG_MAX_LENGTH``. - -.. figure:: ../graphics/qsystem-readout.svg - :width: 100% - :align: center - -tProcessor channel assignment -############################# - -tProcessor will be used to control the real-time operation of the experiment. Output channels (AXIS MASTER) of the tProcessor are assigned as follows: - -- Channel 0 : connected to PMOD0 0-3, and triggers for readout. Bits 0-3 are connected to PMOD0, bit 14 is connected to the trigger of the average/buffer block coming from the readout of ADC 224 CH0. Bit 15 is connected to the trigger of the average/buffer block coming from the readout of ADC 224 CH1. -- Channel 1 : connected to Signal Generator V4, which drives DAC 228 CH0. -- Channel 2 : connected to Signal Generator V4, which drives DAC 228 CH1. -- Channel 3 : connected to Signal Generator V4, which drives DAC 228 CH2. -- Channel 4 : connected to Signal Generator V4, which drives DAC 229 CH0. -- Channel 5 : connected to Signal Generator V4, which drives DAC 229 CH1. -- Channel 6 : connected to Signal Generator V4, which drives DAC 229 CH2. -- Channel 7 : connected to Signal Generator V4, which drives DAC 229 CH3. - -The updated version of the tProcessor has 4 input (AXIS SLAVE) channels, which can be used for feedback. These are 64-bit, and the updated ``read`` instruction can specify channel number and upper/lower 32-bits to be read and written into an internal register. See example below on how to use this new capability. - -* Channel 0 : connected to readout 0, which is driven by ADC 224 CH0 -* Channel 1 : connected to readout 1, which is driven by ADC 224 CH1 - -Signal Generators are organized on the array ``soc.gens``, which is composed of 7 instances. Array index 0 is connected to tProcessor Channel 1, array index 1 is connected to tProcessor Channel 2, and so on. As way of example, let's assume the user needs to create a pulse on DAC 229 CH1 and DAC 229 CH3. These are connected to Channels 5, and 7 or the tProcessor, respectively. However, let's also assume that a gaussian envelope needs to be uploaded into the corresponding signal generator. ``soc.gens[3]`` drives DAC 229 CH1, and ``soc.gens[6]`` drives DAC 229 CH3. - -Similarly, average and buffer inputs blocks are organized on ``soc.avg_bufs`` array, which has two instances of the Average + Buffer block. The user can access them using index 0 and 1. - -Timing -######## - -The clock frequency of the FPGA is 384 MHz. Therefore, each clock cycle has a period of 2.6 ns. - -Firmware parameters -################### - -* Pulse memory length: 65536 per channel x2 (I,Q), i.e., 128k total -* Decimated ADC buffer length: 1024 samples per component (I,Q), 2k total -* Accumulated ADC buffer length: 16384 samples per component (I,Q), 32 k total -* tProc program memory length: 8k instructions of 64 bits, 64k Bytes total -* tProc data memory length: 4096 samples of 32 bits, 16k Bytes total -* tProc stack size: 256 samples of 32 bits, 1k Byte total -* Phase conversion from deg to reg: Phase resolution is 32-bit, that is :math:`\Delta \phi = 2 \pi /2^{32}` or :math:`360/2^{32}` -* Gain is 16-bit signed [-32768,32767] diff --git a/qick/docs/index.rst b/qick/docs/index.rst deleted file mode 100644 index fc5c65e..0000000 --- a/qick/docs/index.rst +++ /dev/null @@ -1,43 +0,0 @@ -.. Sphinx Apidoc Turorial documentation master file, created by - sphinx-quickstart on Fri Jan 8 20:52:00 2016. - You can adapt this file completely to your liking, but it should at least - contain the root `toctree` directive. - -Welcome to the QICK documentation! -================================================= - -.. figure:: ../graphics/QICK.jpg - :width: 100% - :align: center - -The Quantum Instrumentation Control Kit (QICK for short) is a Xilinx RFSoC-based qubit controller which supports the direct synthesis of control pulses with carrier frequencies of up to 6 GHz. The QICK consists of a digital board hosting an RFSoC (RF System-on-Chip) FPGA, custom firmware and software, and an optional companion custom-designed analog front-end board. All of the schematics, firmware, and software are open-source and available on `Github `_. - -Getting started with QICK -######################### - - * First, for a global overview of the QICK and its capabilities, read `our instrumentation paper introducing the QICK `_. - - * If you have an RFSoC board and you want to configure it as a QICK board, follow `the quick start guide on our Github repository `_. - - * After you configure your board, you can test it with `our library of loopback demos `_. - - * The source code for the QICK software library is available `at this link `_. To learn more about the QICK software, see the next section. - - * Chat with us in the #qick channel on the `Unitary Fund Discord `_. - -QICK software -############# - -.. toctree:: - :maxdepth: 2 - - cheatsheet - firmware - modules - -QICK firmware -############# - - * If you are interested in learning more about the QICK firmware, the firmware and its documentation are available `here `_. - - * You also may want to learn more about how the QICK tProcessor works. In this case, you can reference the `QICK assembly language documentation `_. Note that this documentation may not be up to date with the current version of the QICK firmware. It is made available here as a learning tool for those interested in learning the principles of the QICK tProcessor. Those who have more specific questions can contact ``lstefana AT fnal.gov``. diff --git a/qick/docs/make.bat b/qick/docs/make.bat deleted file mode 100644 index 0e7cecd..0000000 --- a/qick/docs/make.bat +++ /dev/null @@ -1,263 +0,0 @@ -@ECHO OFF - -REM Command file for Sphinx documentation - -if "%SPHINXBUILD%" == "" ( - set SPHINXBUILD=sphinx-build -) -set BUILDDIR=_build -set ALLSPHINXOPTS=-d %BUILDDIR%/doctrees %SPHINXOPTS% . -set I18NSPHINXOPTS=%SPHINXOPTS% . -if NOT "%PAPER%" == "" ( - set ALLSPHINXOPTS=-D latex_paper_size=%PAPER% %ALLSPHINXOPTS% - set I18NSPHINXOPTS=-D latex_paper_size=%PAPER% %I18NSPHINXOPTS% -) - -if "%1" == "" goto help - -if "%1" == "help" ( - :help - echo.Please use `make ^` where ^ is one of - echo. html to make standalone HTML files - echo. dirhtml to make HTML files named index.html in directories - echo. singlehtml to make a single large HTML file - echo. pickle to make pickle files - echo. json to make JSON files - echo. htmlhelp to make HTML files and a HTML help project - echo. qthelp to make HTML files and a qthelp project - echo. devhelp to make HTML files and a Devhelp project - echo. epub to make an epub - echo. latex to make LaTeX files, you can set PAPER=a4 or PAPER=letter - echo. text to make text files - echo. man to make manual pages - echo. texinfo to make Texinfo files - echo. gettext to make PO message catalogs - echo. changes to make an overview over all changed/added/deprecated items - echo. xml to make Docutils-native XML files - echo. pseudoxml to make pseudoxml-XML files for display purposes - echo. linkcheck to check all external links for integrity - echo. doctest to run all doctests embedded in the documentation if enabled - echo. coverage to run coverage check of the documentation if enabled - goto end -) - -if "%1" == "clean" ( - for /d %%i in (%BUILDDIR%\*) do rmdir /q /s %%i - del /q /s %BUILDDIR%\* - goto end -) - - -REM Check if sphinx-build is available and fallback to Python version if any -%SPHINXBUILD% 1>NUL 2>NUL -if errorlevel 9009 goto sphinx_python -goto sphinx_ok - -:sphinx_python - -set SPHINXBUILD=python -m sphinx.__init__ -%SPHINXBUILD% 2> nul -if errorlevel 9009 ( - echo. - echo.The 'sphinx-build' command was not found. Make sure you have Sphinx - echo.installed, then set the SPHINXBUILD environment variable to point - echo.to the full path of the 'sphinx-build' executable. Alternatively you - echo.may add the Sphinx directory to PATH. - echo. - echo.If you don't have Sphinx installed, grab it from - echo.http://sphinx-doc.org/ - exit /b 1 -) - -:sphinx_ok - - -if "%1" == "html" ( - %SPHINXBUILD% -b html %ALLSPHINXOPTS% %BUILDDIR%/html - if errorlevel 1 exit /b 1 - echo. - echo.Build finished. The HTML pages are in %BUILDDIR%/html. - goto end -) - -if "%1" == "dirhtml" ( - %SPHINXBUILD% -b dirhtml %ALLSPHINXOPTS% %BUILDDIR%/dirhtml - if errorlevel 1 exit /b 1 - echo. - echo.Build finished. The HTML pages are in %BUILDDIR%/dirhtml. - goto end -) - -if "%1" == "singlehtml" ( - %SPHINXBUILD% -b singlehtml %ALLSPHINXOPTS% %BUILDDIR%/singlehtml - if errorlevel 1 exit /b 1 - echo. - echo.Build finished. The HTML pages are in %BUILDDIR%/singlehtml. - goto end -) - -if "%1" == "pickle" ( - %SPHINXBUILD% -b pickle %ALLSPHINXOPTS% %BUILDDIR%/pickle - if errorlevel 1 exit /b 1 - echo. - echo.Build finished; now you can process the pickle files. - goto end -) - -if "%1" == "json" ( - %SPHINXBUILD% -b json %ALLSPHINXOPTS% %BUILDDIR%/json - if errorlevel 1 exit /b 1 - echo. - echo.Build finished; now you can process the JSON files. - goto end -) - -if "%1" == "htmlhelp" ( - %SPHINXBUILD% -b htmlhelp %ALLSPHINXOPTS% %BUILDDIR%/htmlhelp - if errorlevel 1 exit /b 1 - echo. - echo.Build finished; now you can run HTML Help Workshop with the ^ -.hhp project file in %BUILDDIR%/htmlhelp. - goto end -) - -if "%1" == "qthelp" ( - %SPHINXBUILD% -b qthelp %ALLSPHINXOPTS% %BUILDDIR%/qthelp - if errorlevel 1 exit /b 1 - echo. - echo.Build finished; now you can run "qcollectiongenerator" with the ^ -.qhcp project file in %BUILDDIR%/qthelp, like this: - echo.^> qcollectiongenerator %BUILDDIR%\qthelp\SphinxApidocTurorial.qhcp - echo.To view the help file: - echo.^> assistant -collectionFile %BUILDDIR%\qthelp\SphinxApidocTurorial.ghc - goto end -) - -if "%1" == "devhelp" ( - %SPHINXBUILD% -b devhelp %ALLSPHINXOPTS% %BUILDDIR%/devhelp - if errorlevel 1 exit /b 1 - echo. - echo.Build finished. - goto end -) - -if "%1" == "epub" ( - %SPHINXBUILD% -b epub %ALLSPHINXOPTS% %BUILDDIR%/epub - if errorlevel 1 exit /b 1 - echo. - echo.Build finished. The epub file is in %BUILDDIR%/epub. - goto end -) - -if "%1" == "latex" ( - %SPHINXBUILD% -b latex %ALLSPHINXOPTS% %BUILDDIR%/latex - if errorlevel 1 exit /b 1 - echo. - echo.Build finished; the LaTeX files are in %BUILDDIR%/latex. - goto end -) - -if "%1" == "latexpdf" ( - %SPHINXBUILD% -b latex %ALLSPHINXOPTS% %BUILDDIR%/latex - cd %BUILDDIR%/latex - make all-pdf - cd %~dp0 - echo. - echo.Build finished; the PDF files are in %BUILDDIR%/latex. - goto end -) - -if "%1" == "latexpdfja" ( - %SPHINXBUILD% -b latex %ALLSPHINXOPTS% %BUILDDIR%/latex - cd %BUILDDIR%/latex - make all-pdf-ja - cd %~dp0 - echo. - echo.Build finished; the PDF files are in %BUILDDIR%/latex. - goto end -) - -if "%1" == "text" ( - %SPHINXBUILD% -b text %ALLSPHINXOPTS% %BUILDDIR%/text - if errorlevel 1 exit /b 1 - echo. - echo.Build finished. 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The message catalogs are in %BUILDDIR%/locale. - goto end -) - -if "%1" == "changes" ( - %SPHINXBUILD% -b changes %ALLSPHINXOPTS% %BUILDDIR%/changes - if errorlevel 1 exit /b 1 - echo. - echo.The overview file is in %BUILDDIR%/changes. - goto end -) - -if "%1" == "linkcheck" ( - %SPHINXBUILD% -b linkcheck %ALLSPHINXOPTS% %BUILDDIR%/linkcheck - if errorlevel 1 exit /b 1 - echo. - echo.Link check complete; look for any errors in the above output ^ -or in %BUILDDIR%/linkcheck/output.txt. - goto end -) - -if "%1" == "doctest" ( - %SPHINXBUILD% -b doctest %ALLSPHINXOPTS% %BUILDDIR%/doctest - if errorlevel 1 exit /b 1 - echo. - echo.Testing of doctests in the sources finished, look at the ^ -results in %BUILDDIR%/doctest/output.txt. - goto end -) - -if "%1" == "coverage" ( - %SPHINXBUILD% -b coverage %ALLSPHINXOPTS% %BUILDDIR%/coverage - if errorlevel 1 exit /b 1 - echo. - echo.Testing of coverage in the sources finished, look at the ^ -results in %BUILDDIR%/coverage/python.txt. - goto end -) - -if "%1" == "xml" ( - %SPHINXBUILD% -b xml %ALLSPHINXOPTS% %BUILDDIR%/xml - if errorlevel 1 exit /b 1 - echo. - echo.Build finished. The XML files are in %BUILDDIR%/xml. - goto end -) - -if "%1" == "pseudoxml" ( - %SPHINXBUILD% -b pseudoxml %ALLSPHINXOPTS% %BUILDDIR%/pseudoxml - if errorlevel 1 exit /b 1 - echo. - echo.Build finished. The pseudo-XML files are in %BUILDDIR%/pseudoxml. - goto end -) - -:end diff --git a/qick/docs/modules.rst b/qick/docs/modules.rst deleted file mode 100644 index 1a43d89..0000000 --- a/qick/docs/modules.rst +++ /dev/null @@ -1,18 +0,0 @@ -QICK software library -===================== - -.. autosummary:: - :toctree: _autosummary - - qick - qick.qick - qick.ip - qick.drivers.tproc - qick.drivers.generator - qick.drivers.readout - qick.qick_asm - qick.averager_program - qick.helpers - qick.parser - qick.streamer - qick.rfboard diff --git a/qick/docs/requirements.txt b/qick/docs/requirements.txt deleted file mode 100644 index eaa1718..0000000 --- a/qick/docs/requirements.txt +++ /dev/null @@ -1,2 +0,0 @@ -numpy>=1.14.2 -tqdm diff --git a/qick/firmware/.gitignore b/qick/firmware/.gitignore deleted file mode 100644 index 0695d6c..0000000 --- a/qick/firmware/.gitignore +++ /dev/null @@ -1 +0,0 @@ -top*/ diff --git a/qick/firmware/README.md b/qick/firmware/README.md deleted file mode 100644 index 9b81559..0000000 --- a/qick/firmware/README.md +++ /dev/null @@ -1,70 +0,0 @@ -QICK firmware -================================================= - -This system includes the following components: - -* 1 output channels connected to PMOD0-3 and triggers for Readout Block. -* 7 output channels connected to DACs. -* 2 input channels connected to ADCs. -* 1 instance of tProcessor 64-bit instructions, 32-bit registers. - -Sampling frequency of ADC blocks is given by the variable ``soc.fs_adc``. Sampling frequency of DACs is stored in variable ``soc.fs_adc``. Fast-speed buffers were removed to save memory space. Raw data can be captured after x8 down-sampling. - -Output channels driving DACs use the updated Signal Generator V4, which has the possibility to upload I/Q envelopes, and uses 32-bit resolution for both frequency and phase. The format of the control word was updated accordingly to accomodate the bits. See example asm files for a detailed description of the fields. The maximum length of the I/Q envelopes is given by the variable ``soc.gens[i].MAX_LENGTH``. - -The readout block is actually built around two IPs: readout and average + buffer. Readout block includes a digital down-convertion, FIR filtering and decimation by 8. DDS frequency is configured using a register of the readout block and it is not intended to support real-time frequency hopping as in the Signal Generator side. After frequency shifting, filtering and decimation, the data stream is sent to the Average + Buffer block, which internally can store raw samples or perform the sum of the specified number of samples. The process is started with the external trigger signal, connected to output Channel 0 of tProcessor. The user can opt to route the input, the DDS wave or the frequency shifted signal to the FIR and decimation by 8 stage. This is done using a output selection register of the readout block. Regarding the buffering capabilities, the average section of the block has a buffer of ``soc.avg_bufs[i].AVG_MAX_LENGTH``. - -

- QICK readout -

- -# tProcessor channel assignment - - -tProcessor will be used to control the real-time operation of the experiment. Output channels (AXIS MASTER) of the tProcessor are assigned as follows: - -- Channel 0 : connected to PMOD0 0-3, and triggers for readout. Bits 0-3 are connected to PMOD0, bit 14 is connected to the trigger of the average/buffer block coming from the readout of ADC 224 CH0. Bit 15 is connected to the trigger of the average/buffer block coming from the readout of ADC 224 CH1. -- Channel 1 : connected to Signal Generator V4, which drives DAC 228 CH0. -- Channel 2 : connected to Signal Generator V4, which drives DAC 228 CH1. -- Channel 3 : connected to Signal Generator V4, which drives DAC 228 CH2. -- Channel 4 : connected to Signal Generator V4, which drives DAC 229 CH0. -- Channel 5 : connected to Signal Generator V4, which drives DAC 229 CH1. -- Channel 6 : connected to Signal Generator V4, which drives DAC 229 CH2. -- Channel 7 : connected to Signal Generator V4, which drives DAC 229 CH3. - -**Note** that if you are using the Xilinx XM500 daughter board that comes with the ZCU111, be aware of the filters that are put on that XM500 board: DAC 229 channels 0 and 1 are high pass filtered by a 1 GHz high pass filter, so ensure that signals coming out of channels 4 and 5 are at least 1 GHz. Also, DAC 229 channels 2 and 3 are low pass filtered by a 1 GHz low pass filter, so ensure that signals coming out of channels 6 and 7 are less than 1 GHz. DAC 228 channels 0, 1 and 2 are not filtered by the XM500 daughter board. - -The updated version of the tProcessor has 4 input (AXIS SLAVE) channels, which can be used for feedback. These are 64-bit, and the updated ``read`` instruction can specify channel number and upper/lower 32-bits to be read and written into an internal register. See example below on how to use this new capability. - -* Channel 0 : connected to readout 0, which is driven by ADC 224 CH0 -* Channel 1 : connected to readout 1, which is driven by ADC 224 CH1 - -**Note** that if you are using the Xilinx XM500 daughter board that comes with the ZCU111, be aware of the filters that are put on that XM500 board: ADC 224 channels 0 and 1 are low pass filtered by a 1 GHz low pass filter, so ensure that the signal coming into your XM500 board is less than 1 GHz so that it can be read in properly. - -Signal Generators are organized on the array ``soc.gens``, which is composed of 7 instances. Array index 0 is connected to tProcessor Channel 1, array index 1 is connected to tProcessor Channel 2, and so on. As way of example, let's assume the user needs to create a pulse on DAC 229 CH1 and DAC 229 CH3. These are connected to Channels 5, and 7 or the tProcessor, respectively. However, let's also assume that a gaussian envelope needs to be uploaded into the corresponding signal generator. ``soc.gens[3]`` drives DAC 229 CH1, and ``soc.gens[6]`` drives DAC 229 CH3. - -Similarly, average and buffer inputs blocks are organized on ``soc.avg_bufs`` array, which has two instances of the Average + Buffer block. The user can access them using index 0 and 1. - -# Timing - -The DAC speed is ``384*16=6144 MHz`` (resolution ``~163 ps``) and the ADC speed is ``384*8 MHz`` but then the signal is decimated by a factor of ``8`` (resolution ``~2.6 ns``). The minimum DAC pulse length is 16 samples but if you want shorter pulses than that you can pad that pulse with zeros. - -# Firmware parameters - -* Pulse memory length: 65536 per channel x2 (I,Q), i.e., 128k total -* Decimated ADC buffer length: 1024 samples per component (I,Q), 2k total -* Accumulated ADC buffer length: 16384 samples per component (I,Q), 32k total -* tProc program memory length: 8k instructions of 64 bits, 64k Bytes total -* tProc data memory length: 4096 samples of 32 bits, 16k Bytes total -* tProc stack size: 256 samples of 32 bits, 1k Byte total -* Phase conversion from deg to reg: Phase resolution is 32-bit, that is \Delta \phi = 2 \pi /2^{32} or 360/2^{32} -* Gain is 16-bit signed [-32768,32767] - -# Building the firmware yourself - -If you want to make changes to the firmware, or you just want to look at the design and dig around: - -* Install Vivado 2020.2, with a license that is valid for the FPGA you are using (you will have received such a license with your board). Start Vivado. -* In the Tcl console at the bottom of the screen navigate to this directory, then run `source ./proj_111.tcl` (or whichever of the proj_ scripts matches the board you are using). This will create the firmware project and will end by showing you a block diagram of the firmware. -* Now click "Generate Bitstream" in the navigation menu at the left: this will compile the firmware. -* You need the .bit and .hwh files. These are not easy to find but the `qick/firmware/out` directory has symlinks to their locations. diff --git a/qick/firmware/bd/README.bd b/qick/firmware/bd/README.bd deleted file mode 100644 index b6d6030..0000000 --- a/qick/firmware/bd/README.bd +++ /dev/null @@ -1,23 +0,0 @@ -Todo if bd is re-written: - -Replace this original lines... - - # Create instance: axi_bram_ctrl_0_bram, and set properties - set axi_bram_ctrl_0_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 axi_bram_ctrl_0_bram ] - set_property -dict [ list \ - CONFIG.EN_SAFETY_CKT {false} \ - CONFIG.Memory_Type {True_Dual_Port_RAM} \ - ] $axi_bram_ctrl_0_bram - - -With these modified lines... - - # Create instance: axi_bram_ctrl_0_bram, and set properties - set axi_bram_ctrl_0_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 axi_bram_ctrl_0_bram ] - set_property -dict [ list \ - CONFIG.EN_SAFETY_CKT {false} \ - CONFIG.Memory_Type {True_Dual_Port_RAM} \ - CONFIG.WRITE_WIDTH_B {64} \ - CONFIG.READ_WIDTH_B {64} \ - ] $axi_bram_ctrl_0_bram - diff --git a/qick/firmware/bd/bd-2019-1.tcl b/qick/firmware/bd/bd-2019-1.tcl deleted file mode 100644 index 1dfc3fe..0000000 --- a/qick/firmware/bd/bd-2019-1.tcl +++ /dev/null @@ -1,1649 +0,0 @@ - -################################################################ -# This is a generated script based on design: d_1 -# -# Though there are limitations about the generated script, -# the main purpose of this utility is to make learning -# IP Integrator Tcl commands easier. -################################################################ - -namespace eval _tcl { -proc get_script_folder {} { - set script_path [file normalize [info script]] - set script_folder [file dirname $script_path] - return $script_folder -} -} -variable script_folder -set script_folder [_tcl::get_script_folder] - -################################################################ -# Check if script is running in correct Vivado version. -################################################################ -set scripts_vivado_version 2019.1 -set current_vivado_version [version -short] - -if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { - puts "" - catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} - - return 1 -} - -################################################################ -# START -################################################################ - -# To test this script, run the following commands from Vivado Tcl console: -# source d_1_script.tcl - - -# The design that will be created by this Tcl script contains the following -# module references: -# vect2bits_4 - -# Please add the sources of those modules before sourcing this Tcl script. - -# If there is no project opened, this script will create a -# project, but make sure you do not have an existing project -# <./myproj/project_1.xpr> in the current working folder. - -set list_projs [get_projects -quiet] -if { $list_projs eq "" } { - create_project project_1 myproj -part xczu28dr-ffvg1517-2-e - set_property BOARD_PART xilinx.com:zcu111:part0:1.1 [current_project] -} - - -# CHANGE DESIGN NAME HERE -variable design_name -set design_name d_1 - -# If you do not already have an existing IP Integrator design open, -# you can create a design using the following command: -# create_bd_design $design_name - -# Creating design if needed -set errMsg "" -set nRet 0 - -set cur_design [current_bd_design -quiet] -set list_cells [get_bd_cells -quiet] - -if { ${design_name} eq "" } { - # USE CASES: - # 1) Design_name not set - - set errMsg "Please set the variable to a non-empty value." - set nRet 1 - -} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { - # USE CASES: - # 2): Current design opened AND is empty AND names same. - # 3): Current design opened AND is empty AND names diff; design_name NOT in project. - # 4): Current design opened AND is empty AND names diff; design_name exists in project. - - if { $cur_design ne $design_name } { - common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." - set design_name [get_property NAME $cur_design] - } - common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." - -} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { - # USE CASES: - # 5) Current design opened AND has components AND same names. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 1 -} elseif { [get_files -quiet ${design_name}.bd] ne "" } { - # USE CASES: - # 6) Current opened design, has components, but diff names, design_name exists in project. - # 7) No opened design, design_name exists in project. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 2 - -} else { - # USE CASES: - # 8) No opened design, design_name not in project. - # 9) Current opened design, has components, but diff names, design_name not in project. - - common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." - - create_bd_design $design_name - - common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." - current_bd_design $design_name - -} - -common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." - -if { $nRet != 0 } { - catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} - return $nRet -} - -set bCheckIPsPassed 1 -################################################################## -# CHECK IPs -################################################################## -set bCheckIPs 1 -if { $bCheckIPs == 1 } { - set list_check_ips "\ -xilinx.com:ip:axi_bram_ctrl:4.1\ -xilinx.com:ip:blk_mem_gen:8.4\ -xilinx.com:ip:axi_dma:7.1\ -xilinx.com:ip:smartconnect:1.0\ -user.org:user:axis_avg_buffer:1.0\ -xilinx.com:ip:axis_clock_converter:1.1\ -user.org:user:axis_constant:1.0\ -user.org:user:axis_readout_v2:1.0\ -xilinx.com:ip:axis_register_slice:1.1\ -user.org:user:axis_set_reg:1.0\ -user.org:user:axis_signal_gen_v4:1.0\ -xilinx.com:ip:axis_switch:1.1\ -user.org:user:axis_terminator:1.0\ -user.org:user:axis_tproc64x32_x8:1.0\ -xilinx.com:ip:clk_wiz:6.0\ -xilinx.com:ip:proc_sys_reset:5.0\ -xilinx.com:ip:system_ila:1.1\ -xilinx.com:ip:usp_rf_data_converter:2.1\ -xilinx.com:ip:xlconstant:1.1\ -xilinx.com:ip:zynq_ultra_ps_e:3.3\ -" - - set list_ips_missing "" - common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." - - foreach ip_vlnv $list_check_ips { - set ip_obj [get_ipdefs -all $ip_vlnv] - if { $ip_obj eq "" } { - lappend list_ips_missing $ip_vlnv - } - } - - if { $list_ips_missing ne "" } { - catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } - set bCheckIPsPassed 0 - } - -} - -################################################################## -# CHECK Modules -################################################################## -set bCheckModules 1 -if { $bCheckModules == 1 } { - set list_check_mods "\ -vect2bits_4\ -" - - set list_mods_missing "" - common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." - - foreach mod_vlnv $list_check_mods { - if { [can_resolve_reference $mod_vlnv] == 0 } { - lappend list_mods_missing $mod_vlnv - } - } - - if { $list_mods_missing ne "" } { - catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } - common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above." - set bCheckIPsPassed 0 - } -} - -if { $bCheckIPsPassed != 1 } { - common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." - return 3 -} - -################################################################## -# DESIGN PROCs -################################################################## - - - -# Procedure to create entire design; Provide argument to make -# procedure reusable. If parentCell is "", will use root. -proc create_root_design { parentCell } { - - variable script_folder - variable design_name - - if { $parentCell eq "" } { - set parentCell [get_bd_cells /] - } - - # Get object for parentCell - set parentObj [get_bd_cells $parentCell] - if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} - return - } - - # Make sure parentObj is hier blk - set parentType [get_property TYPE $parentObj] - if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} - return - } - - # Save current instance; Restore later - set oldCurInst [current_bd_instance .] - - # Set parent object as current - current_bd_instance $parentObj - - - # Create interface ports - set adc0_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 adc0_clk ] - - set dac0_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac0_clk ] - - set dac1_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac1_clk ] - - set sysref_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:display_usp_rf_data_converter:diff_pins_rtl:1.0 sysref_in ] - - set vin0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vin0 ] - - set vin1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vin1 ] - - set vout0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout0 ] - - set vout1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout1 ] - - set vout2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout2 ] - - set vout3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout3 ] - - set vout4 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout4 ] - - set vout5 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout5 ] - - set vout6 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout6 ] - - - # Create ports - set PMOD0_0_LS [ create_bd_port -dir O PMOD0_0_LS ] - set PMOD0_1_LS [ create_bd_port -dir O PMOD0_1_LS ] - set PMOD0_2_LS [ create_bd_port -dir O PMOD0_2_LS ] - set PMOD0_3_LS [ create_bd_port -dir O PMOD0_3_LS ] - - # Create instance: axi_bram_ctrl_0, and set properties - set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {64} \ - CONFIG.ECC_TYPE {0} \ - CONFIG.SINGLE_PORT_BRAM {1} \ - ] $axi_bram_ctrl_0 - - # Create instance: axi_bram_ctrl_0_bram, and set properties - set axi_bram_ctrl_0_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 axi_bram_ctrl_0_bram ] - set_property -dict [ list \ - CONFIG.EN_SAFETY_CKT {false} \ - CONFIG.Memory_Type {True_Dual_Port_RAM} \ - CONFIG.Read_Width_B {64} \ - CONFIG.Write_Width_B {64} \ - ] $axi_bram_ctrl_0_bram - - # Create instance: axi_dma_avg, and set properties - set axi_dma_avg [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_avg ] - set_property -dict [ list \ - CONFIG.c_include_mm2s {0} \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_include_stscntrl_strm {0} \ - CONFIG.c_sg_length_width {26} \ - ] $axi_dma_avg - - # Create instance: axi_dma_buf, and set properties - set axi_dma_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_buf ] - set_property -dict [ list \ - CONFIG.c_include_mm2s {0} \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_include_stscntrl_strm {0} \ - CONFIG.c_sg_length_width {26} \ - ] $axi_dma_buf - - # Create instance: axi_dma_gen, and set properties - set axi_dma_gen [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_gen ] - set_property -dict [ list \ - CONFIG.c_include_mm2s {1} \ - CONFIG.c_include_s2mm {0} \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_include_stscntrl_strm {0} \ - CONFIG.c_sg_length_width {26} \ - ] $axi_dma_gen - - # Create instance: axi_dma_tproc, and set properties - set axi_dma_tproc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_tproc ] - set_property -dict [ list \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_include_stscntrl_strm {0} \ - CONFIG.c_sg_length_width {26} \ - ] $axi_dma_tproc - - # Create instance: axi_smc, and set properties - set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ] - set_property -dict [ list \ - CONFIG.NUM_SI {5} \ - ] $axi_smc - - # Create instance: axis_avg_buffer_0, and set properties - set axis_avg_buffer_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_avg_buffer:1.0 axis_avg_buffer_0 ] - - # Create instance: axis_avg_buffer_1, and set properties - set axis_avg_buffer_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_avg_buffer:1.0 axis_avg_buffer_1 ] - - # Create instance: axis_clk_cnvrt_avg_0, and set properties - set axis_clk_cnvrt_avg_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_avg_0 ] - - # Create instance: axis_clk_cnvrt_avg_1, and set properties - set axis_clk_cnvrt_avg_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_avg_1 ] - - # Create instance: axis_clk_cnvrt_gen_3, and set properties - set axis_clk_cnvrt_gen_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_gen_3 ] - - # Create instance: axis_clk_cnvrt_gen_4, and set properties - set axis_clk_cnvrt_gen_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_gen_4 ] - - # Create instance: axis_clk_cnvrt_gen_5, and set properties - set axis_clk_cnvrt_gen_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_gen_5 ] - - # Create instance: axis_clk_cnvrt_gen_6, and set properties - set axis_clk_cnvrt_gen_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_gen_6 ] - - # Create instance: axis_constant_0, and set properties - set axis_constant_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_constant:1.0 axis_constant_0 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {64} \ - ] $axis_constant_0 - - # Create instance: axis_constant_1, and set properties - set axis_constant_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_constant:1.0 axis_constant_1 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {64} \ - ] $axis_constant_1 - - # Create instance: axis_readout_v2_0, and set properties - set axis_readout_v2_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_readout_v2:1.0 axis_readout_v2_0 ] - - # Create instance: axis_readout_v2_1, and set properties - set axis_readout_v2_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_readout_v2:1.0 axis_readout_v2_1 ] - - # Create instance: axis_register_slice_0, and set properties - set axis_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_0 ] - - # Create instance: axis_register_slice_1, and set properties - set axis_register_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_1 ] - - # Create instance: axis_set_reg_0, and set properties - set axis_set_reg_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_set_reg:1.0 axis_set_reg_0 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {160} \ - ] $axis_set_reg_0 - - # Create instance: axis_signal_gen_v4_0, and set properties - set axis_signal_gen_v4_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v4:1.0 axis_signal_gen_v4_0 ] - - # Create instance: axis_signal_gen_v4_1, and set properties - set axis_signal_gen_v4_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v4:1.0 axis_signal_gen_v4_1 ] - - # Create instance: axis_signal_gen_v4_2, and set properties - set axis_signal_gen_v4_2 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v4:1.0 axis_signal_gen_v4_2 ] - - # Create instance: axis_signal_gen_v4_3, and set properties - set axis_signal_gen_v4_3 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v4:1.0 axis_signal_gen_v4_3 ] - - # Create instance: axis_signal_gen_v4_4, and set properties - set axis_signal_gen_v4_4 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v4:1.0 axis_signal_gen_v4_4 ] - - # Create instance: axis_signal_gen_v4_5, and set properties - set axis_signal_gen_v4_5 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v4:1.0 axis_signal_gen_v4_5 ] - - # Create instance: axis_signal_gen_v4_6, and set properties - set axis_signal_gen_v4_6 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v4:1.0 axis_signal_gen_v4_6 ] - - # Create instance: axis_switch_avg, and set properties - set axis_switch_avg [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_avg ] - set_property -dict [ list \ - CONFIG.ROUTING_MODE {1} \ - ] $axis_switch_avg - - # Create instance: axis_switch_buf, and set properties - set axis_switch_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_buf ] - set_property -dict [ list \ - CONFIG.ROUTING_MODE {1} \ - ] $axis_switch_buf - - # Create instance: axis_switch_gen, and set properties - set axis_switch_gen [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_gen ] - set_property -dict [ list \ - CONFIG.DECODER_REG {1} \ - CONFIG.NUM_MI {7} \ - CONFIG.NUM_SI {1} \ - CONFIG.ROUTING_MODE {1} \ - ] $axis_switch_gen - - # Create instance: axis_terminator_0, and set properties - set axis_terminator_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_terminator:1.0 axis_terminator_0 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {256} \ - ] $axis_terminator_0 - - # Create instance: axis_terminator_1, and set properties - set axis_terminator_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_terminator:1.0 axis_terminator_1 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {256} \ - ] $axis_terminator_1 - - # Create instance: axis_tproc64x32_x8_0, and set properties - set axis_tproc64x32_x8_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_tproc64x32_x8:1.0 axis_tproc64x32_x8_0 ] - set_property -dict [ list \ - CONFIG.DMEM_N {12} \ - CONFIG.PMEM_N {20} \ - ] $axis_tproc64x32_x8_0 - - # Create instance: clk_adc0_x2, and set properties - set clk_adc0_x2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_adc0_x2 ] - set_property -dict [ list \ - CONFIG.CLKOUT1_JITTER {81.938} \ - CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {384} \ - CONFIG.MMCM_CLKOUT0_DIVIDE_F {3.125} \ - ] $clk_adc0_x2 - - # Create instance: ps8_0_axi_periph, and set properties - set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ] - set_property -dict [ list \ - CONFIG.NUM_MI {21} \ - ] $ps8_0_axi_periph - - # Create instance: rst_100, and set properties - set rst_100 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_100 ] - - # Create instance: rst_adc0, and set properties - set rst_adc0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_adc0 ] - - # Create instance: rst_adc0_x2, and set properties - set rst_adc0_x2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_adc0_x2 ] - - # Create instance: rst_dac0, and set properties - set rst_dac0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_dac0 ] - - # Create instance: rst_dac1, and set properties - set rst_dac1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_dac1 ] - - # Create instance: system_ila_0, and set properties - set system_ila_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_0 ] - set_property -dict [ list \ - CONFIG.C_BRAM_CNT {0.5} \ - CONFIG.C_MON_TYPE {MIX} \ - CONFIG.C_NUM_MONITOR_SLOTS {1} \ - CONFIG.C_SLOT {0} \ - CONFIG.C_SLOT_0_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ - CONFIG.C_SLOT_1_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ - CONFIG.C_SLOT_2_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ - CONFIG.C_SLOT_3_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ - CONFIG.C_SLOT_4_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ - ] $system_ila_0 - - # Create instance: system_ila_1, and set properties - set system_ila_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_1 ] - set_property -dict [ list \ - CONFIG.C_BRAM_CNT {1.5} \ - CONFIG.C_MON_TYPE {MIX} \ - CONFIG.C_NUM_MONITOR_SLOTS {1} \ - CONFIG.C_SLOT {0} \ - CONFIG.C_SLOT_0_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ - CONFIG.C_SLOT_1_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ - CONFIG.C_SLOT_2_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ - CONFIG.C_SLOT_3_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ - CONFIG.C_SLOT_4_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ - ] $system_ila_1 - - # Create instance: usp_rf_data_converter_0, and set properties - set usp_rf_data_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:usp_rf_data_converter:2.1 usp_rf_data_converter_0 ] - set_property -dict [ list \ - CONFIG.ADC0_Enable {1} \ - CONFIG.ADC0_Fabric_Freq {384.000} \ - CONFIG.ADC0_Outclk_Freq {192.000} \ - CONFIG.ADC0_PLL_Enable {true} \ - CONFIG.ADC0_Refclk_Freq {204.800} \ - CONFIG.ADC0_Sampling_Rate {3.072} \ - CONFIG.ADC_Decimation_Mode00 {1} \ - CONFIG.ADC_Decimation_Mode01 {1} \ - CONFIG.ADC_Decimation_Mode02 {1} \ - CONFIG.ADC_Decimation_Mode03 {1} \ - CONFIG.ADC_Mixer_Type00 {0} \ - CONFIG.ADC_Mixer_Type01 {0} \ - CONFIG.ADC_Mixer_Type02 {0} \ - CONFIG.ADC_Mixer_Type03 {0} \ - CONFIG.ADC_Slice00_Enable {true} \ - CONFIG.ADC_Slice01_Enable {true} \ - CONFIG.ADC_Slice02_Enable {true} \ - CONFIG.ADC_Slice03_Enable {true} \ - CONFIG.DAC0_Enable {1} \ - CONFIG.DAC0_Fabric_Freq {384.000} \ - CONFIG.DAC0_Outclk_Freq {384.000} \ - CONFIG.DAC0_PLL_Enable {true} \ - CONFIG.DAC0_Refclk_Freq {204.800} \ - CONFIG.DAC0_Sampling_Rate {6.144} \ - CONFIG.DAC1_Enable {1} \ - CONFIG.DAC1_Fabric_Freq {384.000} \ - CONFIG.DAC1_Outclk_Freq {384.000} \ - CONFIG.DAC1_PLL_Enable {true} \ - CONFIG.DAC1_Refclk_Freq {204.800} \ - CONFIG.DAC1_Sampling_Rate {6.144} \ - CONFIG.DAC_Interpolation_Mode00 {1} \ - CONFIG.DAC_Interpolation_Mode01 {1} \ - CONFIG.DAC_Interpolation_Mode02 {1} \ - CONFIG.DAC_Interpolation_Mode10 {1} \ - CONFIG.DAC_Interpolation_Mode11 {1} \ - CONFIG.DAC_Interpolation_Mode12 {1} \ - CONFIG.DAC_Interpolation_Mode13 {1} \ - CONFIG.DAC_Mixer_Type00 {0} \ - CONFIG.DAC_Mixer_Type01 {0} \ - CONFIG.DAC_Mixer_Type02 {0} \ - CONFIG.DAC_Mixer_Type10 {0} \ - CONFIG.DAC_Mixer_Type11 {0} \ - CONFIG.DAC_Mixer_Type12 {0} \ - CONFIG.DAC_Mixer_Type13 {0} \ - CONFIG.DAC_Slice00_Enable {true} \ - CONFIG.DAC_Slice01_Enable {true} \ - CONFIG.DAC_Slice02_Enable {true} \ - CONFIG.DAC_Slice10_Enable {true} \ - CONFIG.DAC_Slice11_Enable {true} \ - CONFIG.DAC_Slice12_Enable {true} \ - CONFIG.DAC_Slice13_Enable {true} \ - ] $usp_rf_data_converter_0 - - # Create instance: vect2bits_4_0, and set properties - set block_name vect2bits_4 - set block_cell_name vect2bits_4_0 - if { [catch {set vect2bits_4_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { - catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} - return 1 - } elseif { $vect2bits_4_0 eq "" } { - catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} - return 1 - } - - # Create instance: xlconstant_0, and set properties - set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - CONFIG.CONST_WIDTH {64} \ - ] $xlconstant_0 - - # Create instance: xlconstant_1, and set properties - set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ] - set_property -dict [ list \ - CONFIG.CONST_WIDTH {1} \ - ] $xlconstant_1 - - # Create instance: xlconstant_2, and set properties - set xlconstant_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_2 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - CONFIG.CONST_WIDTH {1} \ - ] $xlconstant_2 - - # Create instance: xlconstant_3, and set properties - set xlconstant_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_3 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - CONFIG.CONST_WIDTH {8} \ - ] $xlconstant_3 - - # Create instance: zynq_ultra_ps_e_0, and set properties - set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ] - set_property -dict [ list \ - CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \ - CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \ - CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \ - CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \ - CONFIG.PSU_MIO_0_DIRECTION {out} \ - CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_0_POLARITY {Default} \ - CONFIG.PSU_MIO_10_DIRECTION {inout} \ - CONFIG.PSU_MIO_10_POLARITY {Default} \ - CONFIG.PSU_MIO_11_DIRECTION {inout} \ - CONFIG.PSU_MIO_11_POLARITY {Default} \ - CONFIG.PSU_MIO_12_DIRECTION {out} \ - CONFIG.PSU_MIO_12_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_12_POLARITY {Default} \ - CONFIG.PSU_MIO_13_DIRECTION {inout} \ - CONFIG.PSU_MIO_13_POLARITY {Default} \ - CONFIG.PSU_MIO_14_DIRECTION {inout} \ - CONFIG.PSU_MIO_14_POLARITY {Default} \ - CONFIG.PSU_MIO_15_DIRECTION {inout} \ - CONFIG.PSU_MIO_15_POLARITY {Default} \ - CONFIG.PSU_MIO_16_DIRECTION {inout} \ - CONFIG.PSU_MIO_16_POLARITY {Default} \ - CONFIG.PSU_MIO_17_DIRECTION {inout} \ - CONFIG.PSU_MIO_17_POLARITY {Default} \ - CONFIG.PSU_MIO_18_DIRECTION {in} \ - CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_18_POLARITY {Default} \ - CONFIG.PSU_MIO_18_SLEW {fast} \ - CONFIG.PSU_MIO_19_DIRECTION {out} \ - CONFIG.PSU_MIO_19_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_19_POLARITY {Default} \ - CONFIG.PSU_MIO_1_DIRECTION {inout} \ - CONFIG.PSU_MIO_1_POLARITY {Default} \ - CONFIG.PSU_MIO_20_DIRECTION {inout} \ - CONFIG.PSU_MIO_20_POLARITY {Default} \ - CONFIG.PSU_MIO_21_DIRECTION {inout} \ - CONFIG.PSU_MIO_21_POLARITY {Default} \ - CONFIG.PSU_MIO_22_DIRECTION {inout} \ - CONFIG.PSU_MIO_22_POLARITY {Default} \ - CONFIG.PSU_MIO_23_DIRECTION {inout} \ - CONFIG.PSU_MIO_23_POLARITY {Default} \ - CONFIG.PSU_MIO_24_DIRECTION {inout} \ - CONFIG.PSU_MIO_24_POLARITY {Default} \ - CONFIG.PSU_MIO_25_DIRECTION {inout} \ - CONFIG.PSU_MIO_25_POLARITY {Default} \ - CONFIG.PSU_MIO_26_DIRECTION {inout} \ - CONFIG.PSU_MIO_26_POLARITY {Default} \ - CONFIG.PSU_MIO_27_DIRECTION {out} \ - CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_27_POLARITY {Default} \ - CONFIG.PSU_MIO_28_DIRECTION {in} \ - CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_28_POLARITY {Default} \ - CONFIG.PSU_MIO_28_SLEW {fast} \ - CONFIG.PSU_MIO_29_DIRECTION {out} \ - CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_29_POLARITY {Default} \ - CONFIG.PSU_MIO_2_DIRECTION {inout} \ - CONFIG.PSU_MIO_2_POLARITY {Default} \ - CONFIG.PSU_MIO_30_DIRECTION {in} \ - CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_30_POLARITY {Default} \ - CONFIG.PSU_MIO_30_SLEW {fast} \ - CONFIG.PSU_MIO_31_DIRECTION {inout} \ - CONFIG.PSU_MIO_31_POLARITY {Default} \ - CONFIG.PSU_MIO_32_DIRECTION {out} \ - CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_32_POLARITY {Default} \ - CONFIG.PSU_MIO_33_DIRECTION {out} \ - CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_33_POLARITY {Default} \ - CONFIG.PSU_MIO_34_DIRECTION {out} \ - CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_34_POLARITY {Default} \ - CONFIG.PSU_MIO_35_DIRECTION {out} \ - CONFIG.PSU_MIO_35_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_35_POLARITY {Default} \ - CONFIG.PSU_MIO_36_DIRECTION {out} \ - CONFIG.PSU_MIO_36_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_36_POLARITY {Default} \ - CONFIG.PSU_MIO_37_DIRECTION {out} \ - CONFIG.PSU_MIO_37_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_37_POLARITY {Default} \ - CONFIG.PSU_MIO_38_DIRECTION {inout} \ - CONFIG.PSU_MIO_38_POLARITY {Default} \ - CONFIG.PSU_MIO_39_DIRECTION {inout} \ - CONFIG.PSU_MIO_39_POLARITY {Default} \ - CONFIG.PSU_MIO_3_DIRECTION {inout} \ - CONFIG.PSU_MIO_3_POLARITY {Default} \ - CONFIG.PSU_MIO_40_DIRECTION {inout} \ - CONFIG.PSU_MIO_40_POLARITY {Default} \ - CONFIG.PSU_MIO_41_DIRECTION {inout} \ - CONFIG.PSU_MIO_41_POLARITY {Default} \ - CONFIG.PSU_MIO_42_DIRECTION {inout} \ - CONFIG.PSU_MIO_42_POLARITY {Default} \ - CONFIG.PSU_MIO_43_DIRECTION {inout} \ - CONFIG.PSU_MIO_43_POLARITY {Default} \ - CONFIG.PSU_MIO_44_DIRECTION {inout} \ - CONFIG.PSU_MIO_44_POLARITY {Default} \ - CONFIG.PSU_MIO_45_DIRECTION {in} \ - CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_45_POLARITY {Default} \ - CONFIG.PSU_MIO_45_SLEW {fast} \ - CONFIG.PSU_MIO_46_DIRECTION {inout} \ - CONFIG.PSU_MIO_46_POLARITY {Default} \ - CONFIG.PSU_MIO_47_DIRECTION {inout} \ - CONFIG.PSU_MIO_47_POLARITY {Default} \ - CONFIG.PSU_MIO_48_DIRECTION {inout} \ - CONFIG.PSU_MIO_48_POLARITY {Default} \ - CONFIG.PSU_MIO_49_DIRECTION {inout} \ - CONFIG.PSU_MIO_49_POLARITY {Default} \ - CONFIG.PSU_MIO_4_DIRECTION {inout} \ - CONFIG.PSU_MIO_4_POLARITY {Default} \ - CONFIG.PSU_MIO_50_DIRECTION {inout} \ - CONFIG.PSU_MIO_50_POLARITY {Default} \ - CONFIG.PSU_MIO_51_DIRECTION {out} \ - CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_51_POLARITY {Default} \ - CONFIG.PSU_MIO_52_DIRECTION {in} \ - CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_52_POLARITY {Default} \ - CONFIG.PSU_MIO_52_SLEW {fast} \ - CONFIG.PSU_MIO_53_DIRECTION {in} \ - CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_53_POLARITY {Default} \ - CONFIG.PSU_MIO_53_SLEW {fast} \ - CONFIG.PSU_MIO_54_DIRECTION {inout} \ - CONFIG.PSU_MIO_54_POLARITY {Default} \ - CONFIG.PSU_MIO_55_DIRECTION {in} \ - CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_55_POLARITY {Default} \ - CONFIG.PSU_MIO_55_SLEW {fast} \ - CONFIG.PSU_MIO_56_DIRECTION {inout} \ - CONFIG.PSU_MIO_56_POLARITY {Default} \ - CONFIG.PSU_MIO_57_DIRECTION {inout} \ - CONFIG.PSU_MIO_57_POLARITY {Default} \ - CONFIG.PSU_MIO_58_DIRECTION {out} \ - CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_58_POLARITY {Default} \ - CONFIG.PSU_MIO_59_DIRECTION {inout} \ - CONFIG.PSU_MIO_59_POLARITY {Default} \ - CONFIG.PSU_MIO_5_DIRECTION {out} \ - CONFIG.PSU_MIO_5_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_5_POLARITY {Default} \ - CONFIG.PSU_MIO_60_DIRECTION {inout} \ - CONFIG.PSU_MIO_60_POLARITY {Default} \ - CONFIG.PSU_MIO_61_DIRECTION {inout} \ - CONFIG.PSU_MIO_61_POLARITY {Default} \ - CONFIG.PSU_MIO_62_DIRECTION {inout} \ - CONFIG.PSU_MIO_62_POLARITY {Default} \ - CONFIG.PSU_MIO_63_DIRECTION {inout} \ - CONFIG.PSU_MIO_63_POLARITY {Default} \ - CONFIG.PSU_MIO_64_DIRECTION {out} \ - CONFIG.PSU_MIO_64_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_64_POLARITY {Default} \ - CONFIG.PSU_MIO_65_DIRECTION {out} \ - CONFIG.PSU_MIO_65_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_65_POLARITY {Default} \ - CONFIG.PSU_MIO_66_DIRECTION {out} \ - CONFIG.PSU_MIO_66_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_66_POLARITY {Default} \ - CONFIG.PSU_MIO_67_DIRECTION {out} \ - CONFIG.PSU_MIO_67_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_67_POLARITY {Default} \ - CONFIG.PSU_MIO_68_DIRECTION {out} \ - CONFIG.PSU_MIO_68_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_68_POLARITY {Default} \ - CONFIG.PSU_MIO_69_DIRECTION {out} \ - CONFIG.PSU_MIO_69_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_69_POLARITY {Default} \ - CONFIG.PSU_MIO_6_DIRECTION {out} \ - CONFIG.PSU_MIO_6_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_6_POLARITY {Default} \ - CONFIG.PSU_MIO_70_DIRECTION {in} \ - CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_70_POLARITY {Default} \ - CONFIG.PSU_MIO_70_SLEW {fast} \ - CONFIG.PSU_MIO_71_DIRECTION {in} \ - CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_71_POLARITY {Default} \ - CONFIG.PSU_MIO_71_SLEW {fast} \ - CONFIG.PSU_MIO_72_DIRECTION {in} \ - CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_72_POLARITY {Default} \ - CONFIG.PSU_MIO_72_SLEW {fast} \ - CONFIG.PSU_MIO_73_DIRECTION {in} \ - CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_73_POLARITY {Default} \ - CONFIG.PSU_MIO_73_SLEW {fast} \ - CONFIG.PSU_MIO_74_DIRECTION {in} \ - CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_74_POLARITY {Default} \ - CONFIG.PSU_MIO_74_SLEW {fast} \ - CONFIG.PSU_MIO_75_DIRECTION {in} \ - CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_75_POLARITY {Default} \ - CONFIG.PSU_MIO_75_SLEW {fast} \ - CONFIG.PSU_MIO_76_DIRECTION {out} \ - CONFIG.PSU_MIO_76_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_76_POLARITY {Default} \ - CONFIG.PSU_MIO_77_DIRECTION {inout} \ - CONFIG.PSU_MIO_77_POLARITY {Default} \ - CONFIG.PSU_MIO_7_DIRECTION {out} \ - CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_7_POLARITY {Default} \ - CONFIG.PSU_MIO_8_DIRECTION {inout} \ - CONFIG.PSU_MIO_8_POLARITY {Default} \ - CONFIG.PSU_MIO_9_DIRECTION {inout} \ - CONFIG.PSU_MIO_9_POLARITY {Default} \ - CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO0 MIO#I2C 0#I2C 0#I2C 1#I2C 1#UART 0#UART 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO1 MIO#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#PMU GPO 3#PMU GPO 4#PMU GPO 5#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3} \ - CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#gpio0[13]#scl_out#sda_out#scl_out#sda_out#rxd#txd#gpio0[20]#gpio0[21]#gpio0[22]#gpio0[23]#gpio0[24]#gpio0[25]#gpio1[26]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpo[3]#gpo[4]#gpo[5]#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#gpio1[43]#gpio1[44]#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out} \ - CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {8} \ - CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \ - CONFIG.PSU__ACT_DDR_FREQ_MHZ {1066.656006} \ - CONFIG.PSU__AFI0_COHERENCY {0} \ - CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \ - CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1199.988037} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {249.997498} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {249.997498} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {533.328003} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {599.994019} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.999750} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.785446} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {14} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {299.997009} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \ - CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {599.994019} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \ - CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {249.997498} \ - CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {99.999001} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.328003} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {90} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {499.994995} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {49.999500} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {499.994995} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {249.997498} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1499.984985} \ - CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {124.998749} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {249.997498} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {99.999001} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {99.999001} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {249.997498} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {99.999001} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {499.994995} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.498123} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {99.999001} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {124.998749} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {45} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {7} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.498123} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {7} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {7} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {99.999001} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {99.999001} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {99.999001} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {249.997498} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {19.999800} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \ - CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \ - CONFIG.PSU__DDRC__ADDR_MIRROR {0} \ - CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \ - CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \ - CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \ - CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \ - CONFIG.PSU__DDRC__CL {15} \ - CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \ - CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \ - CONFIG.PSU__DDRC__COMPONENTS {UDIMM} \ - CONFIG.PSU__DDRC__CWL {14} \ - CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \ - CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \ - CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \ - CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \ - CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \ - CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \ - CONFIG.PSU__DDRC__DEVICE_CAPACITY {8192 MBits} \ - CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \ - CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \ - CONFIG.PSU__DDRC__DQMAP_0_3 {0} \ - CONFIG.PSU__DDRC__DQMAP_12_15 {0} \ - CONFIG.PSU__DDRC__DQMAP_16_19 {0} \ - CONFIG.PSU__DDRC__DQMAP_20_23 {0} \ - CONFIG.PSU__DDRC__DQMAP_24_27 {0} \ - CONFIG.PSU__DDRC__DQMAP_28_31 {0} \ - CONFIG.PSU__DDRC__DQMAP_32_35 {0} \ - CONFIG.PSU__DDRC__DQMAP_36_39 {0} \ - CONFIG.PSU__DDRC__DQMAP_40_43 {0} \ - CONFIG.PSU__DDRC__DQMAP_44_47 {0} \ - CONFIG.PSU__DDRC__DQMAP_48_51 {0} \ - CONFIG.PSU__DDRC__DQMAP_4_7 {0} \ - CONFIG.PSU__DDRC__DQMAP_52_55 {0} \ - CONFIG.PSU__DDRC__DQMAP_56_59 {0} \ - CONFIG.PSU__DDRC__DQMAP_60_63 {0} \ - CONFIG.PSU__DDRC__DQMAP_64_67 {0} \ - CONFIG.PSU__DDRC__DQMAP_68_71 {0} \ - CONFIG.PSU__DDRC__DQMAP_8_11 {0} \ - CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \ - CONFIG.PSU__DDRC__ECC {Disabled} \ - CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \ - CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \ - CONFIG.PSU__DDRC__FGRM {1X} \ - CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__LP_ASR {manual normal} \ - CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \ - CONFIG.PSU__DDRC__PARITY_ENABLE {0} \ - CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \ - CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \ - CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \ - CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \ - CONFIG.PSU__DDRC__SB_TARGET {15-15-15} \ - CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \ - CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \ - CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \ - CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \ - CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \ - CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \ - CONFIG.PSU__DDRC__T_FAW {30.0} \ - CONFIG.PSU__DDRC__T_RAS_MIN {33} \ - CONFIG.PSU__DDRC__T_RC {47.06} \ - CONFIG.PSU__DDRC__T_RCD {15} \ - CONFIG.PSU__DDRC__T_RP {15} \ - CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \ - CONFIG.PSU__DDRC__VREF {1} \ - CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \ - CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \ - CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \ - CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \ - CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \ - CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \ - CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__DLL__ISUSED {1} \ - CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \ - CONFIG.PSU__DP__LANE_SEL {Dual Lower} \ - CONFIG.PSU__DP__REF_CLK_FREQ {27} \ - CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \ - CONFIG.PSU__ENET3__FIFO__ENABLE {0} \ - CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \ - CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \ - CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \ - CONFIG.PSU__ENET3__PTP__ENABLE {0} \ - CONFIG.PSU__ENET3__TSU__ENABLE {0} \ - CONFIG.PSU__FPDMASTERS_COHERENCY {0} \ - CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {99.999001} \ - CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {99.999001} \ - CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \ - CONFIG.PSU__FPGA_PL0_ENABLE {1} \ - CONFIG.PSU__GEM3_COHERENCY {0} \ - CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__GEM__TSU__ENABLE {0} \ - CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \ - CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \ - CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__GT__LINK_SPEED {HBR} \ - CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \ - CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \ - CONFIG.PSU__HIGH_ADDRESS__ENABLE {1} \ - CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 14 .. 15} \ - CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \ - CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \ - CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \ - CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \ - CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \ - CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {99.999001} \ - CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {99.999001} \ - CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \ - CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \ - CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \ - CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \ - CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \ - CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \ - CONFIG.PSU__PL_CLK0_BUF {TRUE} \ - CONFIG.PSU__PMU_COHERENCY {0} \ - CONFIG.PSU__PMU__AIBACK__ENABLE {0} \ - CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \ - CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \ - CONFIG.PSU__PMU__GPI0__ENABLE {0} \ - CONFIG.PSU__PMU__GPI1__ENABLE {0} \ - CONFIG.PSU__PMU__GPI2__ENABLE {0} \ - CONFIG.PSU__PMU__GPI3__ENABLE {0} \ - CONFIG.PSU__PMU__GPI4__ENABLE {0} \ - CONFIG.PSU__PMU__GPI5__ENABLE {0} \ - CONFIG.PSU__PMU__GPO0__ENABLE {1} \ - CONFIG.PSU__PMU__GPO0__IO {MIO 32} \ - CONFIG.PSU__PMU__GPO1__ENABLE {1} \ - CONFIG.PSU__PMU__GPO1__IO {MIO 33} \ - CONFIG.PSU__PMU__GPO2__ENABLE {1} \ - CONFIG.PSU__PMU__GPO2__IO {MIO 34} \ - CONFIG.PSU__PMU__GPO2__POLARITY {low} \ - CONFIG.PSU__PMU__GPO3__ENABLE {1} \ - CONFIG.PSU__PMU__GPO3__IO {MIO 35} \ - CONFIG.PSU__PMU__GPO3__POLARITY {low} \ - CONFIG.PSU__PMU__GPO4__ENABLE {1} \ - CONFIG.PSU__PMU__GPO4__IO {MIO 36} \ - CONFIG.PSU__PMU__GPO4__POLARITY {low} \ - CONFIG.PSU__PMU__GPO5__ENABLE {1} \ - CONFIG.PSU__PMU__GPO5__IO {MIO 37} \ - CONFIG.PSU__PMU__GPO5__POLARITY {low} \ - CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__PMU__PLERROR__ENABLE {0} \ - CONFIG.PSU__PRESET_APPLIED {1} \ - CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;1|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \ - CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;0|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \ - CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333} \ - CONFIG.PSU__QSPI_COHERENCY {0} \ - CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \ - CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \ - CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \ - CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 12} \ - CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel} \ - CONFIG.PSU__SATA__LANE0__ENABLE {0} \ - CONFIG.PSU__SATA__LANE1__ENABLE {1} \ - CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \ - CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__SATA__REF_CLK_FREQ {125} \ - CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk3} \ - CONFIG.PSU__SAXIGP0__DATA_WIDTH {128} \ - CONFIG.PSU__SD1_COHERENCY {0} \ - CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__SD1__DATA_TRANSFER_MODE {8Bit} \ - CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \ - CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \ - CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \ - CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \ - CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 39 .. 51} \ - CONFIG.PSU__SD1__RESET__ENABLE {0} \ - CONFIG.PSU__SD1__SLOT_TYPE {SD 3.0} \ - CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \ - CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__SWDT0__RESET__ENABLE {0} \ - CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \ - CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__SWDT1__RESET__ENABLE {0} \ - CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \ - CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \ - CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \ - CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \ - CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \ - CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \ - CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \ - CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \ - CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \ - CONFIG.PSU__UART0__BAUD_RATE {115200} \ - CONFIG.PSU__UART0__MODEM__ENABLE {0} \ - CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \ - CONFIG.PSU__UART1__BAUD_RATE {115200} \ - CONFIG.PSU__UART1__MODEM__ENABLE {0} \ - CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__UART1__PERIPHERAL__IO {EMIO} \ - CONFIG.PSU__USB0_COHERENCY {0} \ - CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \ - CONFIG.PSU__USB0__REF_CLK_FREQ {26} \ - CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \ - CONFIG.PSU__USB0__RESET__ENABLE {0} \ - CONFIG.PSU__USB1__RESET__ENABLE {0} \ - CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \ - CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \ - CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \ - CONFIG.PSU__USB__RESET__MODE {Boot Pin} \ - CONFIG.PSU__USB__RESET__POLARITY {Active Low} \ - CONFIG.PSU__USE__IRQ0 {1} \ - CONFIG.PSU__USE__M_AXI_GP0 {1} \ - CONFIG.PSU__USE__M_AXI_GP1 {0} \ - CONFIG.PSU__USE__M_AXI_GP2 {0} \ - CONFIG.PSU__USE__S_AXI_GP0 {1} \ - CONFIG.SUBPRESET1 {Custom} \ - ] $zynq_ultra_ps_e_0 - - # Create interface connections - connect_bd_intf_net -intf_net adc0_clk_1 [get_bd_intf_ports adc0_clk] [get_bd_intf_pins usp_rf_data_converter_0/adc0_clk] - connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins axi_bram_ctrl_0_bram/BRAM_PORTA] - connect_bd_intf_net -intf_net axi_dma_0_M_AXIS_MM2S [get_bd_intf_pins axi_dma_tproc/M_AXIS_MM2S] [get_bd_intf_pins axis_tproc64x32_x8_0/s0_axis] - connect_bd_intf_net -intf_net axi_dma_0_M_AXI_MM2S [get_bd_intf_pins axi_dma_tproc/M_AXI_MM2S] [get_bd_intf_pins axi_smc/S00_AXI] - connect_bd_intf_net -intf_net axi_dma_0_M_AXI_S2MM [get_bd_intf_pins axi_dma_tproc/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S01_AXI] - connect_bd_intf_net -intf_net axi_dma_1_M_AXIS_MM2S [get_bd_intf_pins axi_dma_gen/M_AXIS_MM2S] [get_bd_intf_pins axis_switch_gen/S00_AXIS] - connect_bd_intf_net -intf_net axi_dma_1_M_AXI_MM2S [get_bd_intf_pins axi_dma_gen/M_AXI_MM2S] [get_bd_intf_pins axi_smc/S02_AXI] - connect_bd_intf_net -intf_net axi_dma_avg_M_AXI_S2MM [get_bd_intf_pins axi_dma_avg/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S03_AXI] - connect_bd_intf_net -intf_net axi_dma_buf_M_AXI_S2MM [get_bd_intf_pins axi_dma_buf/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S04_AXI] - connect_bd_intf_net -intf_net axi_smc_M00_AXI [get_bd_intf_pins axi_smc/M00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HPC0_FPD] - connect_bd_intf_net -intf_net axis_avg_buffer_0_m0_axis [get_bd_intf_pins axis_avg_buffer_0/m0_axis] [get_bd_intf_pins axis_switch_avg/S00_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_0_m1_axis [get_bd_intf_pins axis_avg_buffer_0/m1_axis] [get_bd_intf_pins axis_switch_buf/S00_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_0_m2_axis [get_bd_intf_pins axis_avg_buffer_0/m2_axis] [get_bd_intf_pins axis_clk_cnvrt_avg_0/S_AXIS] -connect_bd_intf_net -intf_net [get_bd_intf_nets axis_avg_buffer_0_m2_axis] [get_bd_intf_pins axis_clk_cnvrt_avg_0/S_AXIS] [get_bd_intf_pins system_ila_0/SLOT_0_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_1_m0_axis [get_bd_intf_pins axis_avg_buffer_1/m0_axis] [get_bd_intf_pins axis_switch_avg/S01_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_1_m1_axis [get_bd_intf_pins axis_avg_buffer_1/m1_axis] [get_bd_intf_pins axis_switch_buf/S01_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_1_m2_axis [get_bd_intf_pins axis_avg_buffer_1/m2_axis] [get_bd_intf_pins axis_clk_cnvrt_avg_1/S_AXIS] - connect_bd_intf_net -intf_net axis_clk_cnvrt_avg_0_M_AXIS [get_bd_intf_pins axis_clk_cnvrt_avg_0/M_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/s1_axis] -connect_bd_intf_net -intf_net [get_bd_intf_nets axis_clk_cnvrt_avg_0_M_AXIS] [get_bd_intf_pins axis_clk_cnvrt_avg_0/M_AXIS] [get_bd_intf_pins system_ila_1/SLOT_0_AXIS] - connect_bd_intf_net -intf_net axis_clk_cnvrt_avg_1_M_AXIS [get_bd_intf_pins axis_clk_cnvrt_avg_1/M_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/s2_axis] - connect_bd_intf_net -intf_net axis_clock_converter_3_M_AXIS [get_bd_intf_pins axis_clk_cnvrt_gen_3/M_AXIS] [get_bd_intf_pins axis_signal_gen_v4_3/s1_axis] - connect_bd_intf_net -intf_net axis_clock_converter_4_M_AXIS [get_bd_intf_pins axis_clk_cnvrt_gen_4/M_AXIS] [get_bd_intf_pins axis_signal_gen_v4_4/s1_axis] - connect_bd_intf_net -intf_net axis_clock_converter_5_M_AXIS [get_bd_intf_pins axis_clk_cnvrt_gen_5/M_AXIS] [get_bd_intf_pins axis_signal_gen_v4_5/s1_axis] - connect_bd_intf_net -intf_net axis_clock_converter_6_M_AXIS [get_bd_intf_pins axis_clk_cnvrt_gen_6/M_AXIS] [get_bd_intf_pins axis_signal_gen_v4_6/s1_axis] - connect_bd_intf_net -intf_net axis_constant_0_m_axis [get_bd_intf_pins axis_constant_0/m_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/s3_axis] - connect_bd_intf_net -intf_net axis_constant_1_m_axis [get_bd_intf_pins axis_constant_1/m_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/s4_axis] - connect_bd_intf_net -intf_net axis_readout_v2_0_m0_axis [get_bd_intf_pins axis_readout_v2_0/m0_axis] [get_bd_intf_pins axis_terminator_0/s_axis] - connect_bd_intf_net -intf_net axis_readout_v2_0_m1_axis [get_bd_intf_pins axis_avg_buffer_0/s_axis] [get_bd_intf_pins axis_readout_v2_0/m1_axis] - connect_bd_intf_net -intf_net axis_readout_v2_1_m0_axis [get_bd_intf_pins axis_readout_v2_1/m0_axis] [get_bd_intf_pins axis_terminator_1/s_axis] - connect_bd_intf_net -intf_net axis_readout_v2_1_m1_axis [get_bd_intf_pins axis_avg_buffer_1/s_axis] [get_bd_intf_pins axis_readout_v2_1/m1_axis] - connect_bd_intf_net -intf_net axis_register_slice_0_M_AXIS [get_bd_intf_pins axis_readout_v2_0/s_axis] [get_bd_intf_pins axis_register_slice_0/M_AXIS] - connect_bd_intf_net -intf_net axis_register_slice_1_M_AXIS [get_bd_intf_pins axis_readout_v2_1/s_axis] [get_bd_intf_pins axis_register_slice_1/M_AXIS] - connect_bd_intf_net -intf_net axis_signal_gen_v4_0_m_axis [get_bd_intf_pins axis_signal_gen_v4_0/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s00_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v4_1_m_axis [get_bd_intf_pins axis_signal_gen_v4_1/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s01_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v4_2_m_axis [get_bd_intf_pins axis_signal_gen_v4_2/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s02_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v4_3_m_axis [get_bd_intf_pins axis_signal_gen_v4_3/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s10_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v4_4_m_axis [get_bd_intf_pins axis_signal_gen_v4_4/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s11_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v4_5_m_axis [get_bd_intf_pins axis_signal_gen_v4_5/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s12_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v4_6_m_axis [get_bd_intf_pins axis_signal_gen_v4_6/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s13_axis] - connect_bd_intf_net -intf_net axis_switch_0_M00_AXIS [get_bd_intf_pins axis_signal_gen_v4_0/s0_axis] [get_bd_intf_pins axis_switch_gen/M00_AXIS] - connect_bd_intf_net -intf_net axis_switch_0_M01_AXIS [get_bd_intf_pins axis_signal_gen_v4_1/s0_axis] [get_bd_intf_pins axis_switch_gen/M01_AXIS] - connect_bd_intf_net -intf_net axis_switch_0_M02_AXIS [get_bd_intf_pins axis_signal_gen_v4_2/s0_axis] [get_bd_intf_pins axis_switch_gen/M02_AXIS] - connect_bd_intf_net -intf_net axis_switch_0_M03_AXIS [get_bd_intf_pins axis_signal_gen_v4_3/s0_axis] [get_bd_intf_pins axis_switch_gen/M03_AXIS] - connect_bd_intf_net -intf_net axis_switch_0_M04_AXIS [get_bd_intf_pins axis_signal_gen_v4_4/s0_axis] [get_bd_intf_pins axis_switch_gen/M04_AXIS] - connect_bd_intf_net -intf_net axis_switch_0_M05_AXIS [get_bd_intf_pins axis_signal_gen_v4_5/s0_axis] [get_bd_intf_pins axis_switch_gen/M05_AXIS] - connect_bd_intf_net -intf_net axis_switch_0_M06_AXIS [get_bd_intf_pins axis_signal_gen_v4_6/s0_axis] [get_bd_intf_pins axis_switch_gen/M06_AXIS] - connect_bd_intf_net -intf_net axis_switch_avg_M00_AXIS [get_bd_intf_pins axi_dma_avg/S_AXIS_S2MM] [get_bd_intf_pins axis_switch_avg/M00_AXIS] - connect_bd_intf_net -intf_net axis_switch_buf_M00_AXIS [get_bd_intf_pins axi_dma_buf/S_AXIS_S2MM] [get_bd_intf_pins axis_switch_buf/M00_AXIS] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m0_axis [get_bd_intf_pins axi_dma_tproc/S_AXIS_S2MM] [get_bd_intf_pins axis_tproc64x32_x8_0/m0_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m1_axis [get_bd_intf_pins axis_set_reg_0/s_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m1_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m2_axis [get_bd_intf_pins axis_signal_gen_v4_0/s1_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m2_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m3_axis [get_bd_intf_pins axis_signal_gen_v4_1/s1_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m3_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m4_axis [get_bd_intf_pins axis_signal_gen_v4_2/s1_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m4_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m5_axis [get_bd_intf_pins axis_clk_cnvrt_gen_3/S_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/m5_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m6_axis [get_bd_intf_pins axis_clk_cnvrt_gen_4/S_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/m6_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m7_axis [get_bd_intf_pins axis_clk_cnvrt_gen_5/S_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/m7_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m8_axis [get_bd_intf_pins axis_clk_cnvrt_gen_6/S_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/m8_axis] - connect_bd_intf_net -intf_net dac0_clk_1 [get_bd_intf_ports dac0_clk] [get_bd_intf_pins usp_rf_data_converter_0/dac0_clk] - connect_bd_intf_net -intf_net dac1_clk_1 [get_bd_intf_ports dac1_clk] [get_bd_intf_pins usp_rf_data_converter_0/dac1_clk] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins axi_dma_tproc/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M01_AXI [get_bd_intf_pins axis_tproc64x32_x8_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M01_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M02_AXI [get_bd_intf_pins axis_signal_gen_v4_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M02_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M03_AXI [get_bd_intf_pins axis_signal_gen_v4_1/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M03_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M04_AXI [get_bd_intf_pins axis_signal_gen_v4_2/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M04_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M05_AXI [get_bd_intf_pins axis_signal_gen_v4_3/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M05_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M06_AXI [get_bd_intf_pins axi_dma_gen/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M06_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M07_AXI [get_bd_intf_pins axis_switch_gen/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M07_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M08_AXI [get_bd_intf_pins ps8_0_axi_periph/M08_AXI] [get_bd_intf_pins usp_rf_data_converter_0/s_axi] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M09_AXI [get_bd_intf_pins axis_avg_buffer_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M09_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M10_AXI [get_bd_intf_pins axis_avg_buffer_1/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M10_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M11_AXI [get_bd_intf_pins axis_signal_gen_v4_4/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M11_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M12_AXI [get_bd_intf_pins axis_signal_gen_v4_5/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M12_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M13_AXI [get_bd_intf_pins axi_bram_ctrl_0/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M13_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M14_AXI [get_bd_intf_pins axis_signal_gen_v4_6/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M14_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M15_AXI [get_bd_intf_pins axis_readout_v2_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M15_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M16_AXI [get_bd_intf_pins axis_readout_v2_1/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M16_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M17_AXI [get_bd_intf_pins axis_switch_avg/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M17_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M18_AXI [get_bd_intf_pins axis_switch_buf/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M18_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M19_AXI [get_bd_intf_pins axi_dma_avg/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M19_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M20_AXI [get_bd_intf_pins axi_dma_buf/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M20_AXI] - connect_bd_intf_net -intf_net sysref_in_1 [get_bd_intf_ports sysref_in] [get_bd_intf_pins usp_rf_data_converter_0/sysref_in] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_m00_axis [get_bd_intf_pins axis_register_slice_0/S_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/m00_axis] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_m02_axis [get_bd_intf_pins axis_register_slice_1/S_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/m02_axis] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout00 [get_bd_intf_ports vout0] [get_bd_intf_pins usp_rf_data_converter_0/vout00] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout01 [get_bd_intf_ports vout1] [get_bd_intf_pins usp_rf_data_converter_0/vout01] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout02 [get_bd_intf_ports vout2] [get_bd_intf_pins usp_rf_data_converter_0/vout02] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout10 [get_bd_intf_ports vout3] [get_bd_intf_pins usp_rf_data_converter_0/vout10] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout11 [get_bd_intf_ports vout4] [get_bd_intf_pins usp_rf_data_converter_0/vout11] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout12 [get_bd_intf_ports vout5] [get_bd_intf_pins usp_rf_data_converter_0/vout12] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout13 [get_bd_intf_ports vout6] [get_bd_intf_pins usp_rf_data_converter_0/vout13] - connect_bd_intf_net -intf_net vin0_1 [get_bd_intf_ports vin0] [get_bd_intf_pins usp_rf_data_converter_0/vin0_01] - connect_bd_intf_net -intf_net vin1_1 [get_bd_intf_ports vin1] [get_bd_intf_pins usp_rf_data_converter_0/vin0_23] - connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD] - - # Create port connections - connect_bd_net -net axi_bram_ctrl_0_bram_doutb [get_bd_pins axi_bram_ctrl_0_bram/doutb] [get_bd_pins axis_tproc64x32_x8_0/pmem_do] - connect_bd_net -net axis_set_reg_0_dout [get_bd_pins axis_set_reg_0/dout] [get_bd_pins vect2bits_4_0/din] - connect_bd_net -net axis_tproc64x32_x8_0_pmem_addr [get_bd_pins axi_bram_ctrl_0_bram/addrb] [get_bd_pins axis_tproc64x32_x8_0/pmem_addr] - connect_bd_net -net clk_adc0_x2_clk_out1 [get_bd_pins axis_avg_buffer_0/s_axis_aclk] [get_bd_pins axis_avg_buffer_1/s_axis_aclk] [get_bd_pins axis_readout_v2_0/aclk] [get_bd_pins axis_readout_v2_1/aclk] [get_bd_pins axis_register_slice_0/aclk] [get_bd_pins axis_register_slice_1/aclk] [get_bd_pins axis_terminator_0/s_axis_aclk] [get_bd_pins axis_terminator_1/s_axis_aclk] [get_bd_pins clk_adc0_x2/clk_out1] [get_bd_pins rst_adc0_x2/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/m0_axis_aclk] - connect_bd_net -net clk_adc0_x2_locked [get_bd_pins clk_adc0_x2/locked] [get_bd_pins rst_adc0_x2/dcm_locked] - connect_bd_net -net rst_adc0_peripheral_reset [get_bd_pins clk_adc0_x2/reset] [get_bd_pins rst_adc0/peripheral_reset] - connect_bd_net -net rst_adc0_x2_peripheral_aresetn [get_bd_pins axis_avg_buffer_0/s_axis_aresetn] [get_bd_pins axis_avg_buffer_1/s_axis_aresetn] [get_bd_pins axis_readout_v2_0/aresetn] [get_bd_pins axis_readout_v2_1/aresetn] [get_bd_pins axis_register_slice_0/aresetn] [get_bd_pins axis_register_slice_1/aresetn] [get_bd_pins axis_terminator_0/s_axis_aresetn] [get_bd_pins axis_terminator_1/s_axis_aresetn] [get_bd_pins rst_adc0_x2/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/m0_axis_aresetn] - connect_bd_net -net rst_dac0_peripheral_aresetn [get_bd_pins axis_clk_cnvrt_avg_0/m_axis_aresetn] [get_bd_pins axis_clk_cnvrt_avg_1/m_axis_aresetn] [get_bd_pins axis_clk_cnvrt_gen_3/s_axis_aresetn] [get_bd_pins axis_clk_cnvrt_gen_4/s_axis_aresetn] [get_bd_pins axis_clk_cnvrt_gen_5/s_axis_aresetn] [get_bd_pins axis_clk_cnvrt_gen_6/s_axis_aresetn] [get_bd_pins axis_constant_0/m_axis_aresetn] [get_bd_pins axis_constant_1/m_axis_aresetn] [get_bd_pins axis_set_reg_0/s_axis_aresetn] [get_bd_pins axis_signal_gen_v4_0/aresetn] [get_bd_pins axis_signal_gen_v4_1/aresetn] [get_bd_pins axis_signal_gen_v4_2/aresetn] [get_bd_pins axis_tproc64x32_x8_0/aresetn] [get_bd_pins rst_dac0/peripheral_aresetn] [get_bd_pins system_ila_1/resetn] [get_bd_pins usp_rf_data_converter_0/s0_axis_aresetn] - connect_bd_net -net rst_dac1_peripheral_aresetn [get_bd_pins axis_clk_cnvrt_gen_3/m_axis_aresetn] [get_bd_pins axis_clk_cnvrt_gen_4/m_axis_aresetn] [get_bd_pins axis_clk_cnvrt_gen_5/m_axis_aresetn] [get_bd_pins axis_clk_cnvrt_gen_6/m_axis_aresetn] [get_bd_pins axis_signal_gen_v4_3/aresetn] [get_bd_pins axis_signal_gen_v4_4/aresetn] [get_bd_pins axis_signal_gen_v4_5/aresetn] [get_bd_pins axis_signal_gen_v4_6/aresetn] [get_bd_pins rst_dac1/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/s1_axis_aresetn] - connect_bd_net -net rst_ps8_0_99M_peripheral_aresetn [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_dma_avg/axi_resetn] [get_bd_pins axi_dma_buf/axi_resetn] [get_bd_pins axi_dma_gen/axi_resetn] [get_bd_pins axi_dma_tproc/axi_resetn] [get_bd_pins axi_smc/aresetn] [get_bd_pins axis_avg_buffer_0/m_axis_aresetn] [get_bd_pins axis_avg_buffer_0/s_axi_aresetn] [get_bd_pins axis_avg_buffer_1/m_axis_aresetn] [get_bd_pins axis_avg_buffer_1/s_axi_aresetn] [get_bd_pins axis_clk_cnvrt_avg_0/s_axis_aresetn] [get_bd_pins axis_clk_cnvrt_avg_1/s_axis_aresetn] [get_bd_pins axis_readout_v2_0/s_axi_aresetn] [get_bd_pins axis_readout_v2_1/s_axi_aresetn] [get_bd_pins axis_signal_gen_v4_0/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v4_0/s_axi_aresetn] [get_bd_pins axis_signal_gen_v4_1/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v4_1/s_axi_aresetn] [get_bd_pins axis_signal_gen_v4_2/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v4_2/s_axi_aresetn] [get_bd_pins axis_signal_gen_v4_3/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v4_3/s_axi_aresetn] [get_bd_pins axis_signal_gen_v4_4/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v4_4/s_axi_aresetn] [get_bd_pins axis_signal_gen_v4_5/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v4_5/s_axi_aresetn] [get_bd_pins axis_signal_gen_v4_6/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v4_6/s_axi_aresetn] [get_bd_pins axis_switch_avg/aresetn] [get_bd_pins axis_switch_avg/s_axi_ctrl_aresetn] [get_bd_pins axis_switch_buf/aresetn] [get_bd_pins axis_switch_buf/s_axi_ctrl_aresetn] [get_bd_pins axis_switch_gen/aresetn] [get_bd_pins axis_switch_gen/s_axi_ctrl_aresetn] [get_bd_pins axis_tproc64x32_x8_0/m0_axis_aresetn] [get_bd_pins axis_tproc64x32_x8_0/s0_axis_aresetn] [get_bd_pins axis_tproc64x32_x8_0/s_axi_aresetn] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/M01_ARESETN] [get_bd_pins ps8_0_axi_periph/M02_ARESETN] [get_bd_pins ps8_0_axi_periph/M03_ARESETN] [get_bd_pins ps8_0_axi_periph/M04_ARESETN] [get_bd_pins ps8_0_axi_periph/M05_ARESETN] [get_bd_pins ps8_0_axi_periph/M06_ARESETN] [get_bd_pins ps8_0_axi_periph/M07_ARESETN] [get_bd_pins ps8_0_axi_periph/M08_ARESETN] [get_bd_pins ps8_0_axi_periph/M09_ARESETN] [get_bd_pins ps8_0_axi_periph/M10_ARESETN] [get_bd_pins ps8_0_axi_periph/M11_ARESETN] [get_bd_pins ps8_0_axi_periph/M12_ARESETN] [get_bd_pins ps8_0_axi_periph/M13_ARESETN] [get_bd_pins ps8_0_axi_periph/M14_ARESETN] [get_bd_pins ps8_0_axi_periph/M15_ARESETN] [get_bd_pins ps8_0_axi_periph/M16_ARESETN] [get_bd_pins ps8_0_axi_periph/M17_ARESETN] [get_bd_pins ps8_0_axi_periph/M18_ARESETN] [get_bd_pins ps8_0_axi_periph/M19_ARESETN] [get_bd_pins ps8_0_axi_periph/M20_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins rst_100/peripheral_aresetn] [get_bd_pins system_ila_0/resetn] [get_bd_pins usp_rf_data_converter_0/s_axi_aresetn] - connect_bd_net -net usp_rf_data_converter_0_clk_adc0 [get_bd_pins clk_adc0_x2/clk_in1] [get_bd_pins rst_adc0/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/clk_adc0] - connect_bd_net -net usp_rf_data_converter_0_clk_dac0 [get_bd_pins axi_bram_ctrl_0_bram/clkb] [get_bd_pins axis_clk_cnvrt_avg_0/m_axis_aclk] [get_bd_pins axis_clk_cnvrt_avg_1/m_axis_aclk] [get_bd_pins axis_clk_cnvrt_gen_3/s_axis_aclk] [get_bd_pins axis_clk_cnvrt_gen_4/s_axis_aclk] [get_bd_pins axis_clk_cnvrt_gen_5/s_axis_aclk] [get_bd_pins axis_clk_cnvrt_gen_6/s_axis_aclk] [get_bd_pins axis_constant_0/m_axis_aclk] [get_bd_pins axis_constant_1/m_axis_aclk] [get_bd_pins axis_set_reg_0/s_axis_aclk] [get_bd_pins axis_signal_gen_v4_0/aclk] [get_bd_pins axis_signal_gen_v4_1/aclk] [get_bd_pins axis_signal_gen_v4_2/aclk] [get_bd_pins axis_tproc64x32_x8_0/aclk] [get_bd_pins rst_dac0/slowest_sync_clk] [get_bd_pins system_ila_1/clk] [get_bd_pins usp_rf_data_converter_0/clk_dac0] [get_bd_pins usp_rf_data_converter_0/s0_axis_aclk] - connect_bd_net -net usp_rf_data_converter_0_clk_dac1 [get_bd_pins axis_clk_cnvrt_gen_3/m_axis_aclk] [get_bd_pins axis_clk_cnvrt_gen_4/m_axis_aclk] [get_bd_pins axis_clk_cnvrt_gen_5/m_axis_aclk] [get_bd_pins axis_clk_cnvrt_gen_6/m_axis_aclk] [get_bd_pins axis_signal_gen_v4_3/aclk] [get_bd_pins axis_signal_gen_v4_4/aclk] [get_bd_pins axis_signal_gen_v4_5/aclk] [get_bd_pins axis_signal_gen_v4_6/aclk] [get_bd_pins rst_dac1/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/clk_dac1] [get_bd_pins usp_rf_data_converter_0/s1_axis_aclk] - connect_bd_net -net vect2bits_4_0_dout0 [get_bd_ports PMOD0_0_LS] [get_bd_pins vect2bits_4_0/dout0] - connect_bd_net -net vect2bits_4_0_dout1 [get_bd_ports PMOD0_1_LS] [get_bd_pins vect2bits_4_0/dout1] - connect_bd_net -net vect2bits_4_0_dout2 [get_bd_ports PMOD0_2_LS] [get_bd_pins vect2bits_4_0/dout2] - connect_bd_net -net vect2bits_4_0_dout3 [get_bd_ports PMOD0_3_LS] [get_bd_pins vect2bits_4_0/dout3] - connect_bd_net -net vect2bits_4_0_dout14 [get_bd_pins axis_avg_buffer_0/trigger] [get_bd_pins system_ila_0/probe0] [get_bd_pins system_ila_1/probe0] [get_bd_pins vect2bits_4_0/dout14] - connect_bd_net -net vect2bits_4_0_dout15 [get_bd_pins axis_avg_buffer_1/trigger] [get_bd_pins vect2bits_4_0/dout15] - connect_bd_net -net xlconstant_0_dout [get_bd_pins axi_bram_ctrl_0_bram/dinb] [get_bd_pins xlconstant_0/dout] - connect_bd_net -net xlconstant_1_dout [get_bd_pins axi_bram_ctrl_0_bram/enb] [get_bd_pins xlconstant_1/dout] - connect_bd_net -net xlconstant_2_dout [get_bd_pins axi_bram_ctrl_0_bram/rstb] [get_bd_pins axis_tproc64x32_x8_0/start] [get_bd_pins xlconstant_2/dout] - connect_bd_net -net xlconstant_3_dout [get_bd_pins axi_bram_ctrl_0_bram/web] [get_bd_pins xlconstant_3/dout] - connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_dma_avg/m_axi_s2mm_aclk] [get_bd_pins axi_dma_avg/s_axi_lite_aclk] [get_bd_pins axi_dma_buf/m_axi_s2mm_aclk] [get_bd_pins axi_dma_buf/s_axi_lite_aclk] [get_bd_pins axi_dma_gen/m_axi_mm2s_aclk] [get_bd_pins axi_dma_gen/s_axi_lite_aclk] [get_bd_pins axi_dma_tproc/m_axi_mm2s_aclk] [get_bd_pins axi_dma_tproc/m_axi_s2mm_aclk] [get_bd_pins axi_dma_tproc/s_axi_lite_aclk] [get_bd_pins axi_smc/aclk] [get_bd_pins axis_avg_buffer_0/m_axis_aclk] [get_bd_pins axis_avg_buffer_0/s_axi_aclk] [get_bd_pins axis_avg_buffer_1/m_axis_aclk] [get_bd_pins axis_avg_buffer_1/s_axi_aclk] [get_bd_pins axis_clk_cnvrt_avg_0/s_axis_aclk] [get_bd_pins axis_clk_cnvrt_avg_1/s_axis_aclk] [get_bd_pins axis_readout_v2_0/s_axi_aclk] [get_bd_pins axis_readout_v2_1/s_axi_aclk] [get_bd_pins axis_signal_gen_v4_0/s0_axis_aclk] [get_bd_pins axis_signal_gen_v4_0/s_axi_aclk] [get_bd_pins axis_signal_gen_v4_1/s0_axis_aclk] [get_bd_pins axis_signal_gen_v4_1/s_axi_aclk] [get_bd_pins axis_signal_gen_v4_2/s0_axis_aclk] [get_bd_pins axis_signal_gen_v4_2/s_axi_aclk] [get_bd_pins axis_signal_gen_v4_3/s0_axis_aclk] [get_bd_pins axis_signal_gen_v4_3/s_axi_aclk] [get_bd_pins axis_signal_gen_v4_4/s0_axis_aclk] [get_bd_pins axis_signal_gen_v4_4/s_axi_aclk] [get_bd_pins axis_signal_gen_v4_5/s0_axis_aclk] [get_bd_pins axis_signal_gen_v4_5/s_axi_aclk] [get_bd_pins axis_signal_gen_v4_6/s0_axis_aclk] [get_bd_pins axis_signal_gen_v4_6/s_axi_aclk] [get_bd_pins axis_switch_avg/aclk] [get_bd_pins axis_switch_avg/s_axi_ctrl_aclk] [get_bd_pins axis_switch_buf/aclk] [get_bd_pins axis_switch_buf/s_axi_ctrl_aclk] [get_bd_pins axis_switch_gen/aclk] [get_bd_pins axis_switch_gen/s_axi_ctrl_aclk] [get_bd_pins axis_tproc64x32_x8_0/m0_axis_aclk] [get_bd_pins axis_tproc64x32_x8_0/s0_axis_aclk] [get_bd_pins axis_tproc64x32_x8_0/s_axi_aclk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/M01_ACLK] [get_bd_pins ps8_0_axi_periph/M02_ACLK] [get_bd_pins ps8_0_axi_periph/M03_ACLK] [get_bd_pins ps8_0_axi_periph/M04_ACLK] [get_bd_pins ps8_0_axi_periph/M05_ACLK] [get_bd_pins ps8_0_axi_periph/M06_ACLK] [get_bd_pins ps8_0_axi_periph/M07_ACLK] [get_bd_pins ps8_0_axi_periph/M08_ACLK] [get_bd_pins ps8_0_axi_periph/M09_ACLK] [get_bd_pins ps8_0_axi_periph/M10_ACLK] [get_bd_pins ps8_0_axi_periph/M11_ACLK] [get_bd_pins ps8_0_axi_periph/M12_ACLK] [get_bd_pins ps8_0_axi_periph/M13_ACLK] [get_bd_pins ps8_0_axi_periph/M14_ACLK] [get_bd_pins ps8_0_axi_periph/M15_ACLK] [get_bd_pins ps8_0_axi_periph/M16_ACLK] [get_bd_pins ps8_0_axi_periph/M17_ACLK] [get_bd_pins ps8_0_axi_periph/M18_ACLK] [get_bd_pins ps8_0_axi_periph/M19_ACLK] [get_bd_pins ps8_0_axi_periph/M20_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins rst_100/slowest_sync_clk] [get_bd_pins system_ila_0/clk] [get_bd_pins usp_rf_data_converter_0/s_axi_aclk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins zynq_ultra_ps_e_0/saxihpc0_fpd_aclk] - connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins rst_100/ext_reset_in] [get_bd_pins rst_adc0/ext_reset_in] [get_bd_pins rst_adc0_x2/ext_reset_in] [get_bd_pins rst_dac0/ext_reset_in] [get_bd_pins rst_dac1/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] - - # Create address segments - create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] SEG_zynq_ultra_ps_e_0_HPC0_DDR_LOW - create_bd_addr_seg -range 0x20000000 -offset 0xC0000000 [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] SEG_zynq_ultra_ps_e_0_HPC0_QSPI - create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] SEG_zynq_ultra_ps_e_0_HPC0_DDR_LOW - create_bd_addr_seg -range 0x20000000 -offset 0xC0000000 [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] SEG_zynq_ultra_ps_e_0_HPC0_QSPI - create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] SEG_zynq_ultra_ps_e_0_HPC0_DDR_LOW - create_bd_addr_seg -range 0x20000000 -offset 0xC0000000 [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] SEG_zynq_ultra_ps_e_0_HPC0_QSPI - create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] SEG_zynq_ultra_ps_e_0_HPC0_DDR_LOW - create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] SEG_zynq_ultra_ps_e_0_HPC0_DDR_LOW - create_bd_addr_seg -range 0x20000000 -offset 0xC0000000 [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] SEG_zynq_ultra_ps_e_0_HPC0_QSPI - create_bd_addr_seg -range 0x20000000 -offset 0xC0000000 [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] SEG_zynq_ultra_ps_e_0_HPC0_QSPI - create_bd_addr_seg -range 0x00010000 -offset 0xA0000000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] SEG_axi_bram_ctrl_0_Mem0 - create_bd_addr_seg -range 0x00001000 -offset 0xA0040000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_avg/S_AXI_LITE/Reg] SEG_axi_dma_avg_Reg - create_bd_addr_seg -range 0x00001000 -offset 0xA0041000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_buf/S_AXI_LITE/Reg] SEG_axi_dma_buf_Reg - create_bd_addr_seg -range 0x00001000 -offset 0xA0042000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_gen/S_AXI_LITE/Reg] SEG_axi_dma_gen_Reg - create_bd_addr_seg -range 0x00001000 -offset 0xA0043000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_tproc/S_AXI_LITE/Reg] SEG_axi_dma_tproc_Reg - create_bd_addr_seg -range 0x00001000 -offset 0xA0044000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_avg_buffer_0/s_axi/reg0] SEG_axis_avg_buffer_0_reg0 - create_bd_addr_seg -range 0x00001000 -offset 0xA0045000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_avg_buffer_1/s_axi/reg0] SEG_axis_avg_buffer_1_reg0 - create_bd_addr_seg -range 0x00001000 -offset 0xA0046000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_readout_v2_0/s_axi/reg0] SEG_axis_readout_v2_0_reg0 - create_bd_addr_seg -range 0x00001000 -offset 0xA0047000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_readout_v2_1/s_axi/reg0] SEG_axis_readout_v2_1_reg0 - create_bd_addr_seg -range 0x00001000 -offset 0xA0048000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v4_0/s_axi/reg0] SEG_axis_signal_gen_v4_0_reg0 - create_bd_addr_seg -range 0x00001000 -offset 0xA0049000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v4_1/s_axi/reg0] SEG_axis_signal_gen_v4_1_reg0 - create_bd_addr_seg -range 0x00001000 -offset 0xA004A000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v4_2/s_axi/reg0] SEG_axis_signal_gen_v4_2_reg0 - create_bd_addr_seg -range 0x00001000 -offset 0xA004B000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v4_3/s_axi/reg0] SEG_axis_signal_gen_v4_3_reg0 - create_bd_addr_seg -range 0x00001000 -offset 0xA004C000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v4_4/s_axi/reg0] SEG_axis_signal_gen_v4_4_reg0 - create_bd_addr_seg -range 0x00001000 -offset 0xA004D000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v4_5/s_axi/reg0] SEG_axis_signal_gen_v4_5_reg0 - create_bd_addr_seg -range 0x00001000 -offset 0xA004E000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v4_6/s_axi/reg0] SEG_axis_signal_gen_v4_6_reg0 - create_bd_addr_seg -range 0x00001000 -offset 0xA004F000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_avg/S_AXI_CTRL/Reg] SEG_axis_switch_avg_Reg - create_bd_addr_seg -range 0x00001000 -offset 0xA0050000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_buf/S_AXI_CTRL/Reg] SEG_axis_switch_buf_Reg - create_bd_addr_seg -range 0x00001000 -offset 0xA0051000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_gen/S_AXI_CTRL/Reg] SEG_axis_switch_gen_Reg - create_bd_addr_seg -range 0x000100000000 -offset 0x000400000000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_tproc64x32_x8_0/s_axi/reg0] SEG_axis_tproc64x32_x8_0_reg0 - create_bd_addr_seg -range 0x00040000 -offset 0xA0080000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs usp_rf_data_converter_0/s_axi/Reg] SEG_usp_rf_data_converter_0_Reg - - # Exclude Address Segments - create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] SEG_zynq_ultra_ps_e_0_HPC0_LPS_OCM - exclude_bd_addr_seg [get_bd_addr_segs axi_dma_avg/Data_S2MM/SEG_zynq_ultra_ps_e_0_HPC0_LPS_OCM] - - create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] SEG_zynq_ultra_ps_e_0_HPC0_LPS_OCM - exclude_bd_addr_seg [get_bd_addr_segs axi_dma_buf/Data_S2MM/SEG_zynq_ultra_ps_e_0_HPC0_LPS_OCM] - - create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] SEG_zynq_ultra_ps_e_0_HPC0_LPS_OCM - exclude_bd_addr_seg [get_bd_addr_segs axi_dma_gen/Data_MM2S/SEG_zynq_ultra_ps_e_0_HPC0_LPS_OCM] - - create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] SEG_zynq_ultra_ps_e_0_HPC0_LPS_OCM - exclude_bd_addr_seg [get_bd_addr_segs axi_dma_tproc/Data_MM2S/SEG_zynq_ultra_ps_e_0_HPC0_LPS_OCM] - - create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] SEG_zynq_ultra_ps_e_0_HPC0_LPS_OCM - exclude_bd_addr_seg [get_bd_addr_segs axi_dma_tproc/Data_S2MM/SEG_zynq_ultra_ps_e_0_HPC0_LPS_OCM] - - - # Perform GUI Layout - regenerate_bd_layout -layout_string { - "ExpandedHierarchyInLayout":"", - "guistr":"# # String gsaved with Nlview 7.0.19 2019-03-26 bk=1.5019 VDI=41 GEI=35 GUI=JA:9.0 TLS -# -string -flagsOSRD -preplace port adc0_clk -pg 1 -lvl 9 -x 2750 -y 940 -defaultsOSRD -right -preplace port dac0_clk -pg 1 -lvl 9 -x 2750 -y 980 -defaultsOSRD -right -preplace port dac1_clk -pg 1 -lvl 9 -x 2750 -y 960 -defaultsOSRD -right -preplace port sysref_in -pg 1 -lvl 9 -x 2750 -y 920 -defaultsOSRD -right -preplace port vin0 -pg 1 -lvl 9 -x 2750 -y 840 -defaultsOSRD -right -preplace port vin1 -pg 1 -lvl 9 -x 2750 -y 860 -defaultsOSRD -right -preplace port vout0 -pg 1 -lvl 9 -x 2750 -y 490 -defaultsOSRD -preplace port vout1 -pg 1 -lvl 9 -x 2750 -y 510 -defaultsOSRD -preplace port vout2 -pg 1 -lvl 9 -x 2750 -y 530 -defaultsOSRD -preplace port vout3 -pg 1 -lvl 9 -x 2750 -y 550 -defaultsOSRD -preplace port vout4 -pg 1 -lvl 9 -x 2750 -y 570 -defaultsOSRD -preplace port vout5 -pg 1 -lvl 9 -x 2750 -y 590 -defaultsOSRD -preplace port vout6 -pg 1 -lvl 9 -x 2750 -y 610 -defaultsOSRD -preplace port PMOD0_0_LS -pg 1 -lvl 9 -x 2750 -y 100 -defaultsOSRD -preplace port PMOD0_1_LS -pg 1 -lvl 9 -x 2750 -y 120 -defaultsOSRD -preplace port PMOD0_2_LS -pg 1 -lvl 9 -x 2750 -y 140 -defaultsOSRD -preplace port PMOD0_3_LS -pg 1 -lvl 9 -x 2750 -y 160 -defaultsOSRD -preplace inst axi_bram_ctrl_0 -pg 1 -lvl 1 -x -940 -y 530 -defaultsOSRD -preplace inst axi_bram_ctrl_0_bram -pg 1 -lvl 2 -x -490 -y 850 -defaultsOSRD -preplace inst axi_dma_avg -pg 1 -lvl 2 -x -490 -y -1060 -defaultsOSRD -preplace inst axi_dma_buf -pg 1 -lvl 2 -x -490 -y -840 -defaultsOSRD -resize 320 156 -preplace inst axi_dma_gen -pg 1 -lvl 2 -x -490 -y -540 -defaultsOSRD -preplace inst axi_dma_tproc -pg 1 -lvl 2 -x -490 -y -200 -defaultsOSRD -preplace inst axi_smc -pg 1 -lvl 2 -x -490 -y -3260 -defaultsOSRD -preplace inst axis_clk_cnvrt_avg_0 -pg 1 -lvl 7 -x 2120 -y 2870 -defaultsOSRD -preplace inst axis_clk_cnvrt_avg_1 -pg 1 -lvl 7 -x 2120 -y 3750 -defaultsOSRD -resize 220 156 -preplace inst axis_clk_cnvrt_gen_3 -pg 1 -lvl 3 -x 160 -y 1220 -defaultsOSRD -preplace inst axis_clk_cnvrt_gen_4 -pg 1 -lvl 3 -x 160 -y 1480 -defaultsOSRD -resize 220 156 -preplace inst axis_clk_cnvrt_gen_5 -pg 1 -lvl 3 -x 160 -y 1740 -defaultsOSRD -resize 220 156 -preplace inst axis_clk_cnvrt_gen_6 -pg 1 -lvl 3 -x 160 -y 2000 -defaultsOSRD -resize 220 156 -preplace inst axis_register_slice_0 -pg 1 -lvl 4 -x 660 -y 2690 -defaultsOSRD -preplace inst axis_register_slice_1 -pg 1 -lvl 4 -x 660 -y 3570 -defaultsOSRD -resize 180 116 -preplace inst axis_switch_avg -pg 1 -lvl 7 -x 2120 -y 3100 -defaultsOSRD -preplace inst axis_switch_buf -pg 1 -lvl 7 -x 2120 -y 3320 -defaultsOSRD -resize 240 196 -preplace inst axis_switch_gen -pg 1 -lvl 3 -x 160 -y -500 -defaultsOSRD -preplace inst clk_adc0_x2 -pg 1 -lvl 3 -x 160 -y -1580 -defaultsOSRD -preplace inst ps8_0_axi_periph -pg 1 -lvl 5 -x 1170 -y -3230 -defaultsOSRD -preplace inst rst_100 -pg 1 -lvl 3 -x 160 -y -2540 -defaultsOSRD -preplace inst rst_adc0 -pg 1 -lvl 3 -x 160 -y -2360 -defaultsOSRD -resize 320 156 -preplace inst rst_adc0_x2 -pg 1 -lvl 3 -x 160 -y -2180 -defaultsOSRD -resize 320 156 -preplace inst rst_dac0 -pg 1 -lvl 3 -x 160 -y -2000 -defaultsOSRD -resize 320 156 -preplace inst rst_dac1 -pg 1 -lvl 3 -x 160 -y -1820 -defaultsOSRD -resize 320 156 -preplace inst usp_rf_data_converter_0 -pg 1 -lvl 8 -x 2550 -y 570 -defaultsOSRD -preplace inst vect2bits_4_0 -pg 1 -lvl 7 -x 2120 -y 150 -defaultsOSRD -preplace inst xlconstant_0 -pg 1 -lvl 1 -x -940 -y 820 -defaultsOSRD -preplace inst xlconstant_1 -pg 1 -lvl 1 -x -940 -y 930 -defaultsOSRD -resize 140 88 -preplace inst xlconstant_2 -pg 1 -lvl 1 -x -940 -y 1050 -defaultsOSRD -resize 140 88 -preplace inst xlconstant_3 -pg 1 -lvl 1 -x -940 -y 1160 -defaultsOSRD -resize 140 88 -preplace inst zynq_ultra_ps_e_0 -pg 1 -lvl 3 -x 160 -y -3090 -defaultsOSRD -preplace inst axis_constant_0 -pg 1 -lvl 1 -x -940 -y 10 -defaultsOSRD -preplace inst axis_constant_1 -pg 1 -lvl 1 -x -940 -y 130 -defaultsOSRD -resize 220 96 -preplace inst axis_set_reg_0 -pg 1 -lvl 5 -x 1170 -y 150 -defaultsOSRD -preplace inst axis_terminator_0 -pg 1 -lvl 6 -x 1680 -y 2430 -defaultsOSRD -preplace inst axis_terminator_1 -pg 1 -lvl 6 -x 1680 -y 3570 -defaultsOSRD -resize 160 116 -preplace inst axis_tproc64x32_x8_0 -pg 1 -lvl 2 -x -490 -y 200 -defaultsOSRD -preplace inst system_ila_1 -pg 1 -lvl 7 -x 2120 -y 4230 -defaultsOSRD -resize 157 152 -preplace inst system_ila_0 -pg 1 -lvl 7 -x 2120 -y 4030 -defaultsOSRD -resize 157 152 -preplace inst axis_avg_buffer_0 -pg 1 -lvl 6 -x 1680 -y 2910 -defaultsOSRD -preplace inst axis_avg_buffer_1 -pg 1 -lvl 6 -x 1680 -y 3790 -defaultsOSRD -resize 220 236 -preplace inst axis_signal_gen_v4_0 -pg 1 -lvl 5 -x 1170 -y 500 -defaultsOSRD -preplace inst axis_signal_gen_v4_1 -pg 1 -lvl 5 -x 1170 -y 760 -defaultsOSRD -resize 220 236 -preplace inst axis_signal_gen_v4_2 -pg 1 -lvl 5 -x 1170 -y 1020 -defaultsOSRD -resize 220 236 -preplace inst axis_signal_gen_v4_3 -pg 1 -lvl 5 -x 1170 -y 1280 -defaultsOSRD -resize 220 236 -preplace inst axis_signal_gen_v4_4 -pg 1 -lvl 5 -x 1170 -y 1540 -defaultsOSRD -resize 220 236 -preplace inst axis_signal_gen_v4_5 -pg 1 -lvl 5 -x 1170 -y 1800 -defaultsOSRD -resize 220 236 -preplace inst axis_signal_gen_v4_6 -pg 1 -lvl 5 -x 1170 -y 2060 -defaultsOSRD -resize 220 236 -preplace inst axis_readout_v2_0 -pg 1 -lvl 5 -x 1170 -y 2740 -defaultsOSRD -preplace inst axis_readout_v2_1 -pg 1 -lvl 5 -x 1170 -y 3620 -defaultsOSRD -preplace netloc axi_bram_ctrl_0_bram_doutb 1 1 1 -720 350n -preplace netloc axis_set_reg_0_dout 1 5 2 N 150 N -preplace netloc axis_tproc64x32_x8_0_pmem_addr 1 1 2 -710 410 -310 -preplace netloc clk_adc0_x2_clk_out1 1 2 6 -170 -1670 510 2600 780 2600 1490 700 N 700 N -preplace netloc clk_adc0_x2_locked 1 2 2 -180 -2650 480 -preplace netloc rst_adc0_peripheral_reset 1 2 2 -200 -2640 470 -preplace netloc rst_adc0_x2_peripheral_aresetn 1 3 5 520 2610 770 2610 1470 680 NJ 680 NJ -preplace netloc rst_dac0_peripheral_aresetn 1 0 8 -1250 200 -750 -10 -270J -10 500 -10 820 330 NJ 330 1810J 720 N -preplace netloc rst_dac1_peripheral_aresetn 1 2 6 -170 340 490 340 870 340 NJ 340 NJ 340 2310J -preplace netloc rst_ps8_0_99M_peripheral_aresetn 1 0 8 -1250 270 -770 -1690 -230 -2660 520J -2660 790 2890 1340 3070 1880 660 N -preplace netloc usp_rf_data_converter_0_clk_adc0 1 2 7 -190 -1650 NJ -1650 810 -2650 NJ -2650 1880J -640 NJ -640 2730 -preplace netloc usp_rf_data_converter_0_clk_dac0 1 0 9 -1260 -60 -780 -40 -250 210 NJ 210 920 350 NJ 350 1830J 350 2340J 290 2720 -preplace netloc usp_rf_data_converter_0_clk_dac1 1 2 7 -220 360 NJ 360 860 360 NJ 360 NJ 360 2320J 300 2710 -preplace netloc vect2bits_4_0_dout0 1 7 2 N 100 N -preplace netloc vect2bits_4_0_dout1 1 7 2 N 120 N -preplace netloc vect2bits_4_0_dout2 1 7 2 N 140 N -preplace netloc vect2bits_4_0_dout3 1 7 2 N 160 N -preplace netloc vect2bits_4_0_dout14 1 5 3 1510 3060 1840J 2980 2270 -preplace netloc vect2bits_4_0_dout15 1 5 3 1500 290 NJ 290 2260 -preplace netloc xlconstant_0_dout 1 1 1 -800 820n -preplace netloc xlconstant_1_dout 1 1 1 -770 890n -preplace netloc xlconstant_2_dout 1 1 1 -790 330n -preplace netloc xlconstant_3_dout 1 1 1 -750 930n -preplace netloc zynq_ultra_ps_e_0_pl_clk0 1 0 8 -1260 250 -800 -1700 -240 -3180 480 -3110 880 2870 1460 3080 1870 640 N -preplace netloc zynq_ultra_ps_e_0_pl_resetn0 1 2 2 -210 -2780 470 -preplace netloc axis_clock_converter_6_M_AXIS 1 3 2 N 2000 N -preplace netloc usp_rf_data_converter_0_vout11 1 8 1 N 570 -preplace netloc axi_smc_M00_AXI 1 2 1 -250 -3260n -preplace netloc axis_avg_buffer_1_m0_axis 1 6 1 1850 3060n -preplace netloc usp_rf_data_converter_0_vout13 1 8 1 N 610 -preplace netloc axis_avg_buffer_0_m2_axis 1 6 1 1920 2830n -preplace netloc ps8_0_axi_periph_M18_AXI 1 5 2 NJ -3070 1860 -preplace netloc axis_clock_converter_3_M_AXIS 1 3 2 N 1220 N -preplace netloc ps8_0_axi_periph_M10_AXI 1 5 1 1430 -3230n -preplace netloc ps8_0_axi_periph_M12_AXI 1 4 2 980 -2710 1370 -preplace netloc axi_dma_0_M_AXI_S2MM 1 1 2 -710 -3380 -280J -preplace netloc axis_avg_buffer_0_m0_axis 1 6 1 1850 2890n -preplace netloc vin0_1 1 7 2 2380J 840 N -preplace netloc axis_constant_0_m_axis 1 1 1 -760 10n -preplace netloc axi_dma_avg_M_AXI_S2MM 1 1 2 -720 -3140 -290 -preplace netloc usp_rf_data_converter_0_vout01 1 8 1 N 510 -preplace netloc axis_avg_buffer_0_m1_axis 1 6 1 1820 2910n -preplace netloc usp_rf_data_converter_0_vout02 1 8 1 N 530 -preplace netloc axis_avg_buffer_1_m2_axis 1 6 1 1910 3710n -preplace netloc zynq_ultra_ps_e_0_M_AXI_HPM0_FPD 1 3 2 NJ -3120 800 -preplace netloc axi_dma_1_M_AXI_MM2S 1 1 2 -730 -1710 -310J -preplace netloc dac0_clk_1 1 7 2 2350J 890 2690 -preplace netloc axis_clock_converter_4_M_AXIS 1 3 2 N 1480 N -preplace netloc axi_dma_0_M_AXI_MM2S 1 1 2 -770 -3390 -270 -preplace netloc ps8_0_axi_periph_M11_AXI 1 4 2 970 -3750 1320 -preplace netloc ps8_0_axi_periph_M09_AXI 1 5 1 1450 -3250n -preplace netloc axi_dma_0_M_AXIS_MM2S 1 1 2 -710 -80 -310 -preplace netloc axi_dma_1_M_AXIS_MM2S 1 2 1 N -550 -preplace netloc ps8_0_axi_periph_M15_AXI 1 4 2 1000 -2690 1350 -preplace netloc axis_tproc64x32_x8_0_m3_axis 1 2 3 NJ 170 N 170 780 -preplace netloc ps8_0_axi_periph_M05_AXI 1 4 2 960 -3760 1330 -preplace netloc axis_constant_1_m_axis 1 1 1 N 130 -preplace netloc ps8_0_axi_periph_M02_AXI 1 4 2 930 -3790 1390 -preplace netloc dac1_clk_1 1 7 2 2370J 880 2700 -preplace netloc axis_switch_0_M00_AXIS 1 3 2 N -560 910 -preplace netloc ps8_0_axi_periph_M08_AXI 1 5 3 N -3270 1920 -650 2330J -preplace netloc axis_tproc64x32_x8_0_m7_axis 1 2 1 -290 250n -preplace netloc axis_tproc64x32_x8_0_m4_axis 1 2 3 NJ 190 N 190 800 -preplace netloc usp_rf_data_converter_0_vout10 1 8 1 N 550 -preplace netloc axis_tproc64x32_x8_0_m5_axis 1 2 1 -260 210n -preplace netloc axis_switch_avg_M00_AXIS 1 1 7 -720 -630 NJ -630 NJ -630 N -630 NJ -630 NJ -630 2300 -preplace netloc ps8_0_axi_periph_M06_AXI 1 1 5 -710 -730 N -730 NJ -730 N -730 1400 -preplace netloc axis_tproc64x32_x8_0_m6_axis 1 2 1 -280 230n -preplace netloc ps8_0_axi_periph_M03_AXI 1 4 2 940 -3780 1350 -preplace netloc axis_signal_gen_v4_4_m_axis 1 5 3 1420 460 N 460 NJ -preplace netloc axis_signal_gen_v4_0_m_axis 1 5 3 1330 380 N 380 NJ -preplace netloc axis_tproc64x32_x8_0_m8_axis 1 2 1 -300 270n -preplace netloc usp_rf_data_converter_0_vout00 1 8 1 N 490 -preplace netloc axis_tproc64x32_x8_0_m1_axis 1 2 3 N 130 N 130 N -preplace netloc ps8_0_axi_periph_M00_AXI 1 1 5 -730 -740 N -740 NJ -740 920 -2640 1410J -preplace netloc axis_signal_gen_v4_2_m_axis 1 5 3 1390 420 N 420 NJ -preplace netloc usp_rf_data_converter_0_vout12 1 8 1 N 590 -preplace netloc axis_tproc64x32_x8_0_m0_axis 1 1 2 -720 -60 -310 -preplace netloc ps8_0_axi_periph_M01_AXI 1 1 5 -720 -50 N -50 NJ -50 N -50 1420 -preplace netloc axis_signal_gen_v4_5_m_axis 1 5 3 1440 480 N 480 NJ -preplace netloc axis_switch_0_M05_AXIS 1 3 2 N -460 810 -preplace netloc axis_switch_buf_M00_AXIS 1 1 7 -740 -360 NJ -360 NJ -360 N -360 NJ -360 NJ -360 2290 -preplace netloc axis_switch_0_M01_AXIS 1 3 2 N -540 900 -preplace netloc axis_switch_0_M03_AXIS 1 3 2 N -500 840 -preplace netloc axis_signal_gen_v4_6_m_axis 1 5 3 1460 500 N 500 NJ -preplace netloc axis_switch_0_M02_AXIS 1 3 2 N -520 890 -preplace netloc axis_switch_0_M04_AXIS 1 3 2 N -480 830 -preplace netloc axis_signal_gen_v4_3_m_axis 1 5 3 1410 440 N 440 NJ -preplace netloc ps8_0_axi_periph_M20_AXI 1 1 5 -730 -1660 NJ -1660 NJ -1660 800 -2660 1320 -preplace netloc ps8_0_axi_periph_M04_AXI 1 4 2 950 -3770 1340 -preplace netloc axis_signal_gen_v4_1_m_axis 1 5 3 1360 400 N 400 NJ -preplace netloc axis_tproc64x32_x8_0_m2_axis 1 2 3 NJ 150 N 150 850 -preplace netloc axis_switch_0_M06_AXIS 1 3 2 N -440 770 -preplace netloc axis_clk_cnvrt_avg_0_M_AXIS 1 1 7 -730 3050 NJ 3050 NJ 3050 N 3050 NJ 3050 1900J 2970 2260 -preplace netloc ps8_0_axi_periph_M07_AXI 1 2 4 -170 -620 NJ -620 N -620 1390 -preplace netloc ps8_0_axi_periph_M14_AXI 1 4 2 990 -2700 1360 -preplace netloc axis_clock_converter_5_M_AXIS 1 3 2 N 1740 N -preplace netloc ps8_0_axi_periph_M13_AXI 1 0 6 -1270 -70 N -70 NJ -70 NJ -70 N -70 1380 -preplace netloc ps8_0_axi_periph_M19_AXI 1 1 5 -740 -1680 NJ -1680 NJ -1680 770 -2670 1330 -preplace netloc axi_dma_buf_M_AXI_S2MM 1 1 2 -710 -3130 -300 -preplace netloc ps8_0_axi_periph_M17_AXI 1 5 2 NJ -3090 1890 -preplace netloc vin1_1 1 7 2 2390J 850 2730 -preplace netloc sysref_in_1 1 7 2 2400 860 2720 -preplace netloc usp_rf_data_converter_0_m02_axis 1 3 6 540 280 NJ 280 NJ 280 NJ 280 NJ 280 2690 -preplace netloc axi_bram_ctrl_0_BRAM_PORTA 1 1 1 -800 530n -preplace netloc axis_clk_cnvrt_avg_1_M_AXIS 1 1 7 -740 -320 NJ -320 NJ -320 N -320 NJ -320 NJ -320 2280 -preplace netloc axis_avg_buffer_1_m1_axis 1 6 1 1820 3280n -preplace netloc usp_rf_data_converter_0_m00_axis 1 3 6 530 40 NJ 40 NJ 40 NJ 40 NJ 40 2700 -preplace netloc adc0_clk_1 1 7 2 2360J 870 2710 -preplace netloc axis_readout_v2_0_m0_axis 1 5 1 1460 2410n -preplace netloc axis_register_slice_0_M_AXIS 1 4 1 N 2690 -preplace netloc ps8_0_axi_periph_M16_AXI 1 4 2 1010 -2680 1340 -preplace netloc axis_readout_v2_1_m0_axis 1 5 1 1480 3550n -preplace netloc axis_readout_v2_1_m1_axis 1 5 1 1370 3630n -preplace netloc axis_readout_v2_0_m1_axis 1 5 1 1440 2750n -preplace netloc axis_register_slice_1_M_AXIS 1 4 1 N 3570 -levelinfo -pg 1 -1290 -940 -490 160 660 1170 1680 2120 2550 2750 -pagesize -pg 1 -db -bbox -sgen -1290 -3800 2900 4350 -" -} - - # Restore current instance - current_bd_instance $oldCurInst - - validate_bd_design - save_bd_design -} -# End of create_root_design() - - -################################################################## -# MAIN FLOW -################################################################## - -create_root_design "" - - diff --git a/qick/firmware/bd/bd_111_2020-2.tcl b/qick/firmware/bd/bd_111_2020-2.tcl deleted file mode 100644 index 1cadc1a..0000000 --- a/qick/firmware/bd/bd_111_2020-2.tcl +++ /dev/null @@ -1,2557 +0,0 @@ - -################################################################ -# This is a generated script based on design: d_1 -# -# Though there are limitations about the generated script, -# the main purpose of this utility is to make learning -# IP Integrator Tcl commands easier. -################################################################ - -namespace eval _tcl { -proc get_script_folder {} { - set script_path [file normalize [info script]] - set script_folder [file dirname $script_path] - return $script_folder -} -} -variable script_folder -set script_folder [_tcl::get_script_folder] - -################################################################ -# Check if script is running in correct Vivado version. -################################################################ -set scripts_vivado_version 2020.2 -set current_vivado_version [version -short] - -if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { - puts "" - catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} - - return 1 -} - -################################################################ -# START -################################################################ - -# To test this script, run the following commands from Vivado Tcl console: -# source d_1_script.tcl - - -# The design that will be created by this Tcl script contains the following -# module references: -# vect2bits_16 - -# Please add the sources of those modules before sourcing this Tcl script. - -# If there is no project opened, this script will create a -# project, but make sure you do not have an existing project -# <./myproj/project_1.xpr> in the current working folder. - -set list_projs [get_projects -quiet] -if { $list_projs eq "" } { - create_project project_1 myproj -part xczu28dr-ffvg1517-2-e - set_property BOARD_PART xilinx.com:zcu111:part0:1.4 [current_project] -} - - -# CHANGE DESIGN NAME HERE -variable design_name -set design_name d_1 - -# If you do not already have an existing IP Integrator design open, -# you can create a design using the following command: -# create_bd_design $design_name - -# Creating design if needed -set errMsg "" -set nRet 0 - -set cur_design [current_bd_design -quiet] -set list_cells [get_bd_cells -quiet] - -if { ${design_name} eq "" } { - # USE CASES: - # 1) Design_name not set - - set errMsg "Please set the variable to a non-empty value." - set nRet 1 - -} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { - # USE CASES: - # 2): Current design opened AND is empty AND names same. - # 3): Current design opened AND is empty AND names diff; design_name NOT in project. - # 4): Current design opened AND is empty AND names diff; design_name exists in project. - - if { $cur_design ne $design_name } { - common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." - set design_name [get_property NAME $cur_design] - } - common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." - -} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { - # USE CASES: - # 5) Current design opened AND has components AND same names. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 1 -} elseif { [get_files -quiet ${design_name}.bd] ne "" } { - # USE CASES: - # 6) Current opened design, has components, but diff names, design_name exists in project. - # 7) No opened design, design_name exists in project. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 2 - -} else { - # USE CASES: - # 8) No opened design, design_name not in project. - # 9) Current opened design, has components, but diff names, design_name not in project. - - common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." - - create_bd_design $design_name - - common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." - current_bd_design $design_name - -} - -common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." - -if { $nRet != 0 } { - catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} - return $nRet -} - -set bCheckIPsPassed 1 -################################################################## -# CHECK IPs -################################################################## -set bCheckIPs 1 -if { $bCheckIPs == 1 } { - set list_check_ips "\ -xilinx.com:ip:axi_bram_ctrl:4.1\ -xilinx.com:ip:blk_mem_gen:8.4\ -xilinx.com:ip:axi_dma:7.1\ -xilinx.com:ip:smartconnect:1.0\ -user.org:user:axis_avg_buffer:1.0\ -user.org:user:axis_cdcsync_v1:1.0\ -xilinx.com:ip:axis_clock_converter:1.1\ -user.org:user:axis_constant:1.0\ -user.org:user:axis_readout_v2:1.0\ -xilinx.com:ip:axis_register_slice:1.1\ -user.org:user:axis_set_reg:1.0\ -user.org:user:axis_signal_gen_v6:1.0\ -xilinx.com:ip:axis_switch:1.1\ -user.org:user:axis_terminator:1.0\ -user.org:user:axis_tproc64x32_x8:1.0\ -xilinx.com:ip:clk_wiz:6.0\ -xilinx.com:ip:proc_sys_reset:5.0\ -xilinx.com:ip:system_ila:1.1\ -xilinx.com:ip:usp_rf_data_converter:2.4\ -xilinx.com:ip:xlconstant:1.1\ -xilinx.com:ip:zynq_ultra_ps_e:3.3\ -" - - set list_ips_missing "" - common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." - - foreach ip_vlnv $list_check_ips { - set ip_obj [get_ipdefs -all $ip_vlnv] - if { $ip_obj eq "" } { - lappend list_ips_missing $ip_vlnv - } - } - - if { $list_ips_missing ne "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } - set bCheckIPsPassed 0 - } - -} - -################################################################## -# CHECK Modules -################################################################## -set bCheckModules 1 -if { $bCheckModules == 1 } { - set list_check_mods "\ -vect2bits_16\ -" - - set list_mods_missing "" - common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." - - foreach mod_vlnv $list_check_mods { - if { [can_resolve_reference $mod_vlnv] == 0 } { - lappend list_mods_missing $mod_vlnv - } - } - - if { $list_mods_missing ne "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } - common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." - set bCheckIPsPassed 0 - } -} - -if { $bCheckIPsPassed != 1 } { - common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." - return 3 -} - -################################################################## -# DESIGN PROCs -################################################################## - - - -# Procedure to create entire design; Provide argument to make -# procedure reusable. If parentCell is "", will use root. -proc create_root_design { parentCell } { - - variable script_folder - variable design_name - - if { $parentCell eq "" } { - set parentCell [get_bd_cells /] - } - - # Get object for parentCell - set parentObj [get_bd_cells $parentCell] - if { $parentObj == "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} - return - } - - # Make sure parentObj is hier blk - set parentType [get_property TYPE $parentObj] - if { $parentType ne "hier" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} - return - } - - # Save current instance; Restore later - set oldCurInst [current_bd_instance .] - - # Set parent object as current - current_bd_instance $parentObj - - - # Create interface ports - set adc0_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 adc0_clk ] - - set dac0_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac0_clk ] - - set dac1_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac1_clk ] - - set sysref_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:display_usp_rf_data_converter:diff_pins_rtl:1.0 sysref_in ] - - set vin0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vin0 ] - - set vin1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vin1 ] - - set vout0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout0 ] - - set vout1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout1 ] - - set vout2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout2 ] - - set vout3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout3 ] - - set vout4 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout4 ] - - set vout5 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout5 ] - - set vout6 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout6 ] - - - # Create ports - set PMOD0_0_LS [ create_bd_port -dir O PMOD0_0_LS ] - set PMOD0_1_LS [ create_bd_port -dir O PMOD0_1_LS ] - set PMOD0_2_LS [ create_bd_port -dir O PMOD0_2_LS ] - set PMOD0_3_LS [ create_bd_port -dir O PMOD0_3_LS ] - set PMOD0_4_LS [ create_bd_port -dir O PMOD0_4_LS ] - set PMOD0_5_LS [ create_bd_port -dir O PMOD0_5_LS ] - set PMOD0_6_LS [ create_bd_port -dir O PMOD0_6_LS ] - set PMOD0_7_LS [ create_bd_port -dir O PMOD0_7_LS ] - set PMOD1_0_LS [ create_bd_port -dir I PMOD1_0_LS ] - - # Create instance: axi_bram_ctrl_0, and set properties - set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {64} \ - CONFIG.ECC_TYPE {0} \ - CONFIG.SINGLE_PORT_BRAM {1} \ - ] $axi_bram_ctrl_0 - - # Create instance: axi_bram_ctrl_0_bram, and set properties - set axi_bram_ctrl_0_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 axi_bram_ctrl_0_bram ] - set_property -dict [ list \ - CONFIG.EN_SAFETY_CKT {false} \ - CONFIG.Enable_B {Use_ENB_Pin} \ - CONFIG.Memory_Type {True_Dual_Port_RAM} \ - CONFIG.Port_B_Clock {100} \ - CONFIG.Port_B_Enable_Rate {100} \ - CONFIG.Port_B_Write_Rate {50} \ - CONFIG.Read_Width_B {64} \ - CONFIG.Use_RSTB_Pin {true} \ - CONFIG.Write_Width_B {64} \ - ] $axi_bram_ctrl_0_bram - - # Create instance: axi_dma_avg, and set properties - set axi_dma_avg [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_avg ] - set_property -dict [ list \ - CONFIG.c_include_mm2s {0} \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_include_stscntrl_strm {0} \ - CONFIG.c_sg_length_width {26} \ - ] $axi_dma_avg - - # Create instance: axi_dma_buf, and set properties - set axi_dma_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_buf ] - set_property -dict [ list \ - CONFIG.c_include_mm2s {0} \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_include_stscntrl_strm {0} \ - CONFIG.c_sg_length_width {26} \ - ] $axi_dma_buf - - # Create instance: axi_dma_gen, and set properties - set axi_dma_gen [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_gen ] - set_property -dict [ list \ - CONFIG.c_include_mm2s {1} \ - CONFIG.c_include_s2mm {0} \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_include_stscntrl_strm {0} \ - CONFIG.c_sg_length_width {26} \ - ] $axi_dma_gen - - # Create instance: axi_dma_tproc, and set properties - set axi_dma_tproc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_tproc ] - set_property -dict [ list \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_include_stscntrl_strm {0} \ - CONFIG.c_sg_length_width {26} \ - ] $axi_dma_tproc - - # Create instance: axi_smc, and set properties - set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ] - set_property -dict [ list \ - CONFIG.NUM_SI {5} \ - ] $axi_smc - - # Create instance: axis_avg_buffer_0, and set properties - set axis_avg_buffer_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_avg_buffer:1.0 axis_avg_buffer_0 ] - set_property -dict [ list \ - CONFIG.N_AVG {14} \ - ] $axis_avg_buffer_0 - - # Create instance: axis_avg_buffer_1, and set properties - set axis_avg_buffer_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_avg_buffer:1.0 axis_avg_buffer_1 ] - set_property -dict [ list \ - CONFIG.N_AVG {14} \ - ] $axis_avg_buffer_1 - - # Create instance: axis_cdcsync_v1_0, and set properties - set axis_cdcsync_v1_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_cdcsync_v1:1.0 axis_cdcsync_v1_0 ] - set_property -dict [ list \ - CONFIG.B {160} \ - CONFIG.N {4} \ - ] $axis_cdcsync_v1_0 - - # Create instance: axis_cdcsync_v1_1, and set properties - set axis_cdcsync_v1_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_cdcsync_v1:1.0 axis_cdcsync_v1_1 ] - set_property -dict [ list \ - CONFIG.B {160} \ - CONFIG.N {4} \ - ] $axis_cdcsync_v1_1 - - # Create instance: axis_clk_cnvrt_avg_0, and set properties - set axis_clk_cnvrt_avg_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_avg_0 ] - - # Create instance: axis_clk_cnvrt_avg_1, and set properties - set axis_clk_cnvrt_avg_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_avg_1 ] - - # Create instance: axis_constant_0, and set properties - set axis_constant_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_constant:1.0 axis_constant_0 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {64} \ - ] $axis_constant_0 - - # Create instance: axis_constant_1, and set properties - set axis_constant_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_constant:1.0 axis_constant_1 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {64} \ - ] $axis_constant_1 - - # Create instance: axis_constant_2, and set properties - set axis_constant_2 [ create_bd_cell -type ip -vlnv user.org:user:axis_constant:1.0 axis_constant_2 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {160} \ - ] $axis_constant_2 - - # Create instance: axis_readout_v2_0, and set properties - set axis_readout_v2_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_readout_v2:1.0 axis_readout_v2_0 ] - - # Create instance: axis_readout_v2_1, and set properties - set axis_readout_v2_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_readout_v2:1.0 axis_readout_v2_1 ] - - # Create instance: axis_register_slice_0, and set properties - set axis_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_0 ] - - # Create instance: axis_register_slice_1, and set properties - set axis_register_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_1 ] - - # Create instance: axis_set_reg_0, and set properties - set axis_set_reg_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_set_reg:1.0 axis_set_reg_0 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {160} \ - ] $axis_set_reg_0 - - # Create instance: axis_signal_gen_v6_0, and set properties - set axis_signal_gen_v6_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_0 ] - - # Create instance: axis_signal_gen_v6_1, and set properties - set axis_signal_gen_v6_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_1 ] - - # Create instance: axis_signal_gen_v6_2, and set properties - set axis_signal_gen_v6_2 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_2 ] - - # Create instance: axis_signal_gen_v6_3, and set properties - set axis_signal_gen_v6_3 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_3 ] - - # Create instance: axis_signal_gen_v6_4, and set properties - set axis_signal_gen_v6_4 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_4 ] - - # Create instance: axis_signal_gen_v6_5, and set properties - set axis_signal_gen_v6_5 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_5 ] - - # Create instance: axis_signal_gen_v6_6, and set properties - set axis_signal_gen_v6_6 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_6 ] - - # Create instance: axis_switch_avg, and set properties - set axis_switch_avg [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_avg ] - set_property -dict [ list \ - CONFIG.ROUTING_MODE {1} \ - ] $axis_switch_avg - - # Create instance: axis_switch_buf, and set properties - set axis_switch_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_buf ] - set_property -dict [ list \ - CONFIG.ROUTING_MODE {1} \ - ] $axis_switch_buf - - # Create instance: axis_switch_gen, and set properties - set axis_switch_gen [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_gen ] - set_property -dict [ list \ - CONFIG.DECODER_REG {1} \ - CONFIG.NUM_MI {7} \ - CONFIG.NUM_SI {1} \ - CONFIG.ROUTING_MODE {1} \ - ] $axis_switch_gen - - # Create instance: axis_terminator_0, and set properties - set axis_terminator_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_terminator:1.0 axis_terminator_0 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {256} \ - ] $axis_terminator_0 - - # Create instance: axis_terminator_1, and set properties - set axis_terminator_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_terminator:1.0 axis_terminator_1 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {256} \ - ] $axis_terminator_1 - - # Create instance: axis_terminator_2, and set properties - set axis_terminator_2 [ create_bd_cell -type ip -vlnv user.org:user:axis_terminator:1.0 axis_terminator_2 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {160} \ - ] $axis_terminator_2 - - # Create instance: axis_tproc64x32_x8_0, and set properties - set axis_tproc64x32_x8_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_tproc64x32_x8:1.0 axis_tproc64x32_x8_0 ] - set_property -dict [ list \ - CONFIG.DMEM_N {12} \ - CONFIG.PMEM_N {20} \ - ] $axis_tproc64x32_x8_0 - - # Create instance: clk_adc0_x2, and set properties - set clk_adc0_x2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_adc0_x2 ] - set_property -dict [ list \ - CONFIG.CLKIN1_JITTER_PS {39.06} \ - CONFIG.CLKOUT1_JITTER {73.505} \ - CONFIG.CLKOUT1_PHASE_ERROR {77.298} \ - CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {512} \ - CONFIG.MMCM_CLKFBOUT_MULT_F {4.750} \ - CONFIG.MMCM_CLKIN1_PERIOD {3.906} \ - CONFIG.MMCM_CLKIN2_PERIOD {10.0} \ - CONFIG.MMCM_CLKOUT0_DIVIDE_F {2.375} \ - CONFIG.MMCM_DIVCLK_DIVIDE {1} \ - ] $clk_adc0_x2 - - # Create instance: ps8_0_axi_periph, and set properties - set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ] - set_property -dict [ list \ - CONFIG.NUM_MI {21} \ - ] $ps8_0_axi_periph - - # Create instance: rst_100, and set properties - set rst_100 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_100 ] - - # Create instance: rst_adc0, and set properties - set rst_adc0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_adc0 ] - - # Create instance: rst_adc0_x2, and set properties - set rst_adc0_x2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_adc0_x2 ] - - # Create instance: rst_dac0, and set properties - set rst_dac0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_dac0 ] - - # Create instance: rst_dac1, and set properties - set rst_dac1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_dac1 ] - - # Create instance: system_ila_0, and set properties - set system_ila_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_0 ] - set_property -dict [ list \ - CONFIG.C_BRAM_CNT {6} \ - CONFIG.C_MON_TYPE {MIX} \ - CONFIG.C_NUM_MONITOR_SLOTS {1} \ - CONFIG.C_SLOT {0} \ - CONFIG.C_SLOT_0_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ - CONFIG.C_SLOT_1_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ - CONFIG.C_SLOT_2_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ - CONFIG.C_SLOT_3_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ - CONFIG.C_SLOT_4_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ - ] $system_ila_0 - - # Create instance: system_ila_1, and set properties - set system_ila_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_1 ] - set_property -dict [ list \ - CONFIG.C_BRAM_CNT {6} \ - CONFIG.C_MON_TYPE {MIX} \ - CONFIG.C_NUM_MONITOR_SLOTS {1} \ - CONFIG.C_SLOT {0} \ - CONFIG.C_SLOT_0_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ - CONFIG.C_SLOT_1_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ - CONFIG.C_SLOT_2_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ - CONFIG.C_SLOT_3_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ - CONFIG.C_SLOT_4_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ - ] $system_ila_1 - - # Create instance: usp_rf_data_converter_0, and set properties - set usp_rf_data_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:usp_rf_data_converter:2.4 usp_rf_data_converter_0 ] - set_property -dict [ list \ - CONFIG.ADC0_Enable {1} \ - CONFIG.ADC0_Fabric_Freq {512.000} \ - CONFIG.ADC0_Outclk_Freq {256.000} \ - CONFIG.ADC0_PLL_Enable {true} \ - CONFIG.ADC0_Refclk_Freq {204.800} \ - CONFIG.ADC0_Sampling_Rate {4.096} \ - CONFIG.ADC_Decimation_Mode00 {1} \ - CONFIG.ADC_Decimation_Mode01 {1} \ - CONFIG.ADC_Decimation_Mode02 {1} \ - CONFIG.ADC_Decimation_Mode03 {1} \ - CONFIG.ADC_Mixer_Type00 {0} \ - CONFIG.ADC_Mixer_Type01 {0} \ - CONFIG.ADC_Mixer_Type02 {0} \ - CONFIG.ADC_Mixer_Type03 {0} \ - CONFIG.ADC_RESERVED_1_00 {false} \ - CONFIG.ADC_RESERVED_1_02 {false} \ - CONFIG.ADC_Slice00_Enable {true} \ - CONFIG.ADC_Slice01_Enable {true} \ - CONFIG.ADC_Slice02_Enable {true} \ - CONFIG.ADC_Slice03_Enable {true} \ - CONFIG.DAC0_Enable {1} \ - CONFIG.DAC0_Fabric_Freq {384.000} \ - CONFIG.DAC0_Outclk_Freq {384.000} \ - CONFIG.DAC0_PLL_Enable {true} \ - CONFIG.DAC0_Refclk_Freq {204.800} \ - CONFIG.DAC0_Sampling_Rate {6.144} \ - CONFIG.DAC1_Enable {1} \ - CONFIG.DAC1_Fabric_Freq {384.000} \ - CONFIG.DAC1_Outclk_Freq {384.000} \ - CONFIG.DAC1_PLL_Enable {true} \ - CONFIG.DAC1_Refclk_Freq {204.800} \ - CONFIG.DAC1_Sampling_Rate {6.144} \ - CONFIG.DAC_Interpolation_Mode00 {1} \ - CONFIG.DAC_Interpolation_Mode01 {1} \ - CONFIG.DAC_Interpolation_Mode02 {1} \ - CONFIG.DAC_Interpolation_Mode10 {1} \ - CONFIG.DAC_Interpolation_Mode11 {1} \ - CONFIG.DAC_Interpolation_Mode12 {1} \ - CONFIG.DAC_Interpolation_Mode13 {1} \ - CONFIG.DAC_Mixer_Type00 {0} \ - CONFIG.DAC_Mixer_Type01 {0} \ - CONFIG.DAC_Mixer_Type02 {0} \ - CONFIG.DAC_Mixer_Type10 {0} \ - CONFIG.DAC_Mixer_Type11 {0} \ - CONFIG.DAC_Mixer_Type12 {0} \ - CONFIG.DAC_Mixer_Type13 {0} \ - CONFIG.DAC_Slice00_Enable {true} \ - CONFIG.DAC_Slice01_Enable {true} \ - CONFIG.DAC_Slice02_Enable {true} \ - CONFIG.DAC_Slice10_Enable {true} \ - CONFIG.DAC_Slice11_Enable {true} \ - CONFIG.DAC_Slice12_Enable {true} \ - CONFIG.DAC_Slice13_Enable {true} \ - ] $usp_rf_data_converter_0 - - # Create instance: vect2bits_16_0, and set properties - set block_name vect2bits_16 - set block_cell_name vect2bits_16_0 - if { [catch {set vect2bits_16_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { - catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} - return 1 - } elseif { $vect2bits_16_0 eq "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} - return 1 - } - - # Create instance: xlconstant_0, and set properties - set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - CONFIG.CONST_WIDTH {64} \ - ] $xlconstant_0 - - # Create instance: xlconstant_1, and set properties - set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ] - set_property -dict [ list \ - CONFIG.CONST_WIDTH {1} \ - ] $xlconstant_1 - - # Create instance: xlconstant_2, and set properties - set xlconstant_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_2 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - CONFIG.CONST_WIDTH {1} \ - ] $xlconstant_2 - - # Create instance: xlconstant_3, and set properties - set xlconstant_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_3 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - CONFIG.CONST_WIDTH {8} \ - ] $xlconstant_3 - - # Create instance: zynq_ultra_ps_e_0, and set properties - set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ] - set_property -dict [ list \ - CONFIG.CAN0_BOARD_INTERFACE {custom} \ - CONFIG.CAN1_BOARD_INTERFACE {custom} \ - CONFIG.CSU_BOARD_INTERFACE {custom} \ - CONFIG.DP_BOARD_INTERFACE {custom} \ - CONFIG.GEM0_BOARD_INTERFACE {custom} \ - CONFIG.GEM1_BOARD_INTERFACE {custom} \ - CONFIG.GEM2_BOARD_INTERFACE {custom} \ - CONFIG.GEM3_BOARD_INTERFACE {custom} \ - CONFIG.GPIO_BOARD_INTERFACE {custom} \ - CONFIG.IIC0_BOARD_INTERFACE {custom} \ - CONFIG.IIC1_BOARD_INTERFACE {custom} \ - CONFIG.NAND_BOARD_INTERFACE {custom} \ - CONFIG.PCIE_BOARD_INTERFACE {custom} \ - CONFIG.PJTAG_BOARD_INTERFACE {custom} \ - CONFIG.PMU_BOARD_INTERFACE {custom} \ - CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS33} \ - CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \ - CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \ - CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \ - CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \ - CONFIG.PSU_IMPORT_BOARD_PRESET {} \ - CONFIG.PSU_MIO_0_DIRECTION {out} \ - CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_0_POLARITY {Default} \ - CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_0_SLEW {fast} \ - CONFIG.PSU_MIO_10_DIRECTION {inout} \ - CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_10_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_10_POLARITY {Default} \ - CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_10_SLEW {fast} \ - CONFIG.PSU_MIO_11_DIRECTION {inout} \ - CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_11_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_11_POLARITY {Default} \ - CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_11_SLEW {fast} \ - CONFIG.PSU_MIO_12_DIRECTION {out} \ - CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_12_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_12_POLARITY {Default} \ - CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_12_SLEW {fast} \ - CONFIG.PSU_MIO_13_DIRECTION {inout} \ - CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_13_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_13_POLARITY {Default} \ - CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_13_SLEW {fast} \ - CONFIG.PSU_MIO_14_DIRECTION {inout} \ - CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_14_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_14_POLARITY {Default} \ - CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_14_SLEW {fast} \ - CONFIG.PSU_MIO_15_DIRECTION {inout} \ - CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_15_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_15_POLARITY {Default} \ - CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_15_SLEW {fast} \ - CONFIG.PSU_MIO_16_DIRECTION {inout} \ - CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_16_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_16_POLARITY {Default} \ - CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_16_SLEW {fast} \ - CONFIG.PSU_MIO_17_DIRECTION {inout} \ - CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_17_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_17_POLARITY {Default} \ - CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_17_SLEW {fast} \ - CONFIG.PSU_MIO_18_DIRECTION {in} \ - CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_18_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_18_POLARITY {Default} \ - CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_18_SLEW {fast} \ - CONFIG.PSU_MIO_19_DIRECTION {out} \ - CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_19_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_19_POLARITY {Default} \ - CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_19_SLEW {fast} \ - CONFIG.PSU_MIO_1_DIRECTION {inout} \ - CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_1_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_1_POLARITY {Default} \ - CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_1_SLEW {fast} \ - CONFIG.PSU_MIO_20_DIRECTION {inout} \ - CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_20_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_20_POLARITY {Default} \ - CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_20_SLEW {fast} \ - CONFIG.PSU_MIO_21_DIRECTION {inout} \ - CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_21_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_21_POLARITY {Default} \ - CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_21_SLEW {fast} \ - CONFIG.PSU_MIO_22_DIRECTION {inout} \ - CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_22_POLARITY {Default} \ - CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_22_SLEW {fast} \ - CONFIG.PSU_MIO_23_DIRECTION {inout} \ - CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_23_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_23_POLARITY {Default} \ - CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_23_SLEW {fast} \ - CONFIG.PSU_MIO_24_DIRECTION {inout} \ - CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_24_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_24_POLARITY {Default} \ - CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_24_SLEW {fast} \ - CONFIG.PSU_MIO_25_DIRECTION {inout} \ - CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_25_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_25_POLARITY {Default} \ - CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_25_SLEW {fast} \ - CONFIG.PSU_MIO_26_DIRECTION {inout} \ - CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_26_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_26_POLARITY {Default} \ - CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_26_SLEW {fast} \ - CONFIG.PSU_MIO_27_DIRECTION {out} \ - CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_27_POLARITY {Default} \ - CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_27_SLEW {fast} \ - CONFIG.PSU_MIO_28_DIRECTION {in} \ - CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_28_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_28_POLARITY {Default} \ - CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_28_SLEW {fast} \ - CONFIG.PSU_MIO_29_DIRECTION {out} \ - CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_29_POLARITY {Default} \ - CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_29_SLEW {fast} \ - CONFIG.PSU_MIO_2_DIRECTION {inout} \ - CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_2_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_2_POLARITY {Default} \ - CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_2_SLEW {fast} \ - CONFIG.PSU_MIO_30_DIRECTION {in} \ - CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_30_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_30_POLARITY {Default} \ - CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_30_SLEW {fast} \ - CONFIG.PSU_MIO_31_DIRECTION {inout} \ - CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_31_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_31_POLARITY {Default} \ - CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_31_SLEW {fast} \ - CONFIG.PSU_MIO_32_DIRECTION {out} \ - CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_32_POLARITY {Default} \ - CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_32_SLEW {fast} \ - CONFIG.PSU_MIO_33_DIRECTION {out} \ - CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_33_POLARITY {Default} \ - CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_33_SLEW {fast} \ - CONFIG.PSU_MIO_34_DIRECTION {out} \ - CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_34_POLARITY {Default} \ - CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_34_SLEW {fast} \ - CONFIG.PSU_MIO_35_DIRECTION {out} \ - CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_35_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_35_POLARITY {Default} \ - CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_35_SLEW {fast} \ - CONFIG.PSU_MIO_36_DIRECTION {out} \ - CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_36_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_36_POLARITY {Default} \ - CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_36_SLEW {fast} \ - CONFIG.PSU_MIO_37_DIRECTION {out} \ - CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_37_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_37_POLARITY {Default} \ - CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_37_SLEW {fast} \ - CONFIG.PSU_MIO_38_DIRECTION {inout} \ - CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_38_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_38_POLARITY {Default} \ - CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_38_SLEW {fast} \ - CONFIG.PSU_MIO_39_DIRECTION {inout} \ - CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_39_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_39_POLARITY {Default} \ - CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_39_SLEW {fast} \ - CONFIG.PSU_MIO_3_DIRECTION {inout} \ - CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_3_POLARITY {Default} \ - CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_3_SLEW {fast} \ - CONFIG.PSU_MIO_40_DIRECTION {inout} \ - CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_40_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_40_POLARITY {Default} \ - CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_40_SLEW {fast} \ - CONFIG.PSU_MIO_41_DIRECTION {inout} \ - CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_41_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_41_POLARITY {Default} \ - CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_41_SLEW {fast} \ - CONFIG.PSU_MIO_42_DIRECTION {inout} \ - CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_42_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_42_POLARITY {Default} \ - CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_42_SLEW {fast} \ - CONFIG.PSU_MIO_43_DIRECTION {inout} \ - CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_43_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_43_POLARITY {Default} \ - CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_43_SLEW {fast} \ - CONFIG.PSU_MIO_44_DIRECTION {inout} \ - CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_44_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_44_POLARITY {Default} \ - CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_44_SLEW {fast} \ - CONFIG.PSU_MIO_45_DIRECTION {in} \ - CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_45_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_45_POLARITY {Default} \ - CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_45_SLEW {fast} \ - CONFIG.PSU_MIO_46_DIRECTION {inout} \ - CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_46_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_46_POLARITY {Default} \ - CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_46_SLEW {fast} \ - CONFIG.PSU_MIO_47_DIRECTION {inout} \ - CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_47_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_47_POLARITY {Default} \ - CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_47_SLEW {fast} \ - CONFIG.PSU_MIO_48_DIRECTION {inout} \ - CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_48_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_48_POLARITY {Default} \ - CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_48_SLEW {fast} \ - CONFIG.PSU_MIO_49_DIRECTION {inout} \ - CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_49_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_49_POLARITY {Default} \ - CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_49_SLEW {fast} \ - CONFIG.PSU_MIO_4_DIRECTION {inout} \ - CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_4_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_4_POLARITY {Default} \ - CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_4_SLEW {fast} \ - CONFIG.PSU_MIO_50_DIRECTION {inout} \ - CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_50_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_50_POLARITY {Default} \ - CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_50_SLEW {fast} \ - CONFIG.PSU_MIO_51_DIRECTION {out} \ - CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_51_POLARITY {Default} \ - CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_51_SLEW {fast} \ - CONFIG.PSU_MIO_52_DIRECTION {in} \ - CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_52_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_52_POLARITY {Default} \ - CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_52_SLEW {fast} \ - CONFIG.PSU_MIO_53_DIRECTION {in} \ - CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_53_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_53_POLARITY {Default} \ - CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_53_SLEW {fast} \ - CONFIG.PSU_MIO_54_DIRECTION {inout} \ - CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_54_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_54_POLARITY {Default} \ - CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_54_SLEW {fast} \ - CONFIG.PSU_MIO_55_DIRECTION {in} \ - CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_55_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_55_POLARITY {Default} \ - CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_55_SLEW {fast} \ - CONFIG.PSU_MIO_56_DIRECTION {inout} \ - CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_56_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_56_POLARITY {Default} \ - CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_56_SLEW {fast} \ - CONFIG.PSU_MIO_57_DIRECTION {inout} \ - CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_57_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_57_POLARITY {Default} \ - CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_57_SLEW {fast} \ - CONFIG.PSU_MIO_58_DIRECTION {out} \ - CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_58_POLARITY {Default} \ - CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_58_SLEW {fast} \ - CONFIG.PSU_MIO_59_DIRECTION {inout} \ - CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_59_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_59_POLARITY {Default} \ - CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_59_SLEW {fast} \ - CONFIG.PSU_MIO_5_DIRECTION {out} \ - CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_5_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_5_POLARITY {Default} \ - CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_5_SLEW {fast} \ - CONFIG.PSU_MIO_60_DIRECTION {inout} \ - CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_60_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_60_POLARITY {Default} \ - CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_60_SLEW {fast} \ - CONFIG.PSU_MIO_61_DIRECTION {inout} \ - CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_61_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_61_POLARITY {Default} \ - CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_61_SLEW {fast} \ - CONFIG.PSU_MIO_62_DIRECTION {inout} \ - CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_62_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_62_POLARITY {Default} \ - CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_62_SLEW {fast} \ - CONFIG.PSU_MIO_63_DIRECTION {inout} \ - CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_63_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_63_POLARITY {Default} \ - CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_63_SLEW {fast} \ - CONFIG.PSU_MIO_64_DIRECTION {out} \ - CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_64_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_64_POLARITY {Default} \ - CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_64_SLEW {fast} \ - CONFIG.PSU_MIO_65_DIRECTION {out} \ - CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_65_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_65_POLARITY {Default} \ - CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_65_SLEW {fast} \ - CONFIG.PSU_MIO_66_DIRECTION {out} \ - CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_66_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_66_POLARITY {Default} \ - CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_66_SLEW {fast} \ - CONFIG.PSU_MIO_67_DIRECTION {out} \ - CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_67_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_67_POLARITY {Default} \ - CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_67_SLEW {fast} \ - CONFIG.PSU_MIO_68_DIRECTION {out} \ - CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_68_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_68_POLARITY {Default} \ - CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_68_SLEW {fast} \ - CONFIG.PSU_MIO_69_DIRECTION {out} \ - CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_69_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_69_POLARITY {Default} \ - CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_69_SLEW {fast} \ - CONFIG.PSU_MIO_6_DIRECTION {out} \ - CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_6_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_6_POLARITY {Default} \ - CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_6_SLEW {fast} \ - CONFIG.PSU_MIO_70_DIRECTION {in} \ - CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_70_POLARITY {Default} \ - CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_70_SLEW {fast} \ - CONFIG.PSU_MIO_71_DIRECTION {in} \ - CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_71_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_71_POLARITY {Default} \ - CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_71_SLEW {fast} \ - CONFIG.PSU_MIO_72_DIRECTION {in} \ - CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_72_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_72_POLARITY {Default} \ - CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_72_SLEW {fast} \ - CONFIG.PSU_MIO_73_DIRECTION {in} \ - CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_73_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_73_POLARITY {Default} \ - CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_73_SLEW {fast} \ - CONFIG.PSU_MIO_74_DIRECTION {in} \ - CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_74_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_74_POLARITY {Default} \ - CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_74_SLEW {fast} \ - CONFIG.PSU_MIO_75_DIRECTION {in} \ - CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_75_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_75_POLARITY {Default} \ - CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_75_SLEW {fast} \ - CONFIG.PSU_MIO_76_DIRECTION {out} \ - CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_76_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_76_POLARITY {Default} \ - CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_76_SLEW {fast} \ - CONFIG.PSU_MIO_77_DIRECTION {inout} \ - CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_77_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_77_POLARITY {Default} \ - CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_77_SLEW {fast} \ - CONFIG.PSU_MIO_7_DIRECTION {out} \ - CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_7_POLARITY {Default} \ - CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_7_SLEW {fast} \ - CONFIG.PSU_MIO_8_DIRECTION {inout} \ - CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_8_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_8_POLARITY {Default} \ - CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_8_SLEW {fast} \ - CONFIG.PSU_MIO_9_DIRECTION {inout} \ - CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_9_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_9_POLARITY {Default} \ - CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_9_SLEW {fast} \ - CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO0 MIO#I2C 0#I2C 0#I2C 1#I2C 1#UART 0#UART 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO1 MIO#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#PMU GPO 3#PMU GPO 4#PMU GPO 5#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3} \ - CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#gpio0[13]#scl_out#sda_out#scl_out#sda_out#rxd#txd#gpio0[20]#gpio0[21]#gpio0[22]#gpio0[23]#gpio0[24]#gpio0[25]#gpio1[26]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpo[3]#gpo[4]#gpo[5]#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#gpio1[43]#gpio1[44]#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out} \ - CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \ - CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \ - CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {8} \ - CONFIG.PSU_SMC_CYCLE_T0 {NA} \ - CONFIG.PSU_SMC_CYCLE_T1 {NA} \ - CONFIG.PSU_SMC_CYCLE_T2 {NA} \ - CONFIG.PSU_SMC_CYCLE_T3 {NA} \ - CONFIG.PSU_SMC_CYCLE_T4 {NA} \ - CONFIG.PSU_SMC_CYCLE_T5 {NA} \ - CONFIG.PSU_SMC_CYCLE_T6 {NA} \ - CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \ - CONFIG.PSU_VALUE_SILVERSION {3} \ - CONFIG.PSU__ACPU0__POWER__ON {1} \ - CONFIG.PSU__ACPU1__POWER__ON {1} \ - CONFIG.PSU__ACPU2__POWER__ON {1} \ - CONFIG.PSU__ACPU3__POWER__ON {1} \ - CONFIG.PSU__ACTUAL__IP {1} \ - CONFIG.PSU__ACT_DDR_FREQ_MHZ {1066.656006} \ - CONFIG.PSU__AFI0_COHERENCY {0} \ - CONFIG.PSU__AFI1_COHERENCY {0} \ - CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \ - CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \ - CONFIG.PSU__CAN0__GRP_CLK__ENABLE {0} \ - CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \ - CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1199.988037} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \ - CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \ - CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \ - CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \ - CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \ - CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \ - CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \ - CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \ - CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \ - CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {249.997498} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {249.997498} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {533.328003} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {599.994019} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.999750} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.785446} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {14} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {299.997009} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \ - CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {599.994019} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \ - CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {0} \ - CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \ - CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \ - CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \ - CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \ - CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \ - CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {249.997498} \ - CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {99.999001} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.328003} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {90} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {499.994995} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {49.999500} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {499.994995} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {180} \ - CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {180} \ - CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {SysOsc} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {249.997498} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \ - CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \ - CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1499.984985} \ - CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \ - CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {124.998749} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {249.997498} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {99.999001} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {99.999001} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {249.997498} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {99.999001} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {499.994995} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.498123} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {99.999001} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {124.998749} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {45} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {7} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.498123} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {214} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {7} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {214} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {7} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {99.999001} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {99.999001} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {99.999001} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {249.997498} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {19.999800} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \ - CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \ - CONFIG.PSU__CSU_COHERENCY {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__DDRC__ADDR_MIRROR {0} \ - CONFIG.PSU__DDRC__AL {0} \ - CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \ - CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \ - CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \ - CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \ - CONFIG.PSU__DDRC__CL {15} \ - CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \ - CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \ - CONFIG.PSU__DDRC__COMPONENTS {UDIMM} \ - CONFIG.PSU__DDRC__CWL {14} \ - CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \ - CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \ - CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \ - CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {0} \ - CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \ - CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \ - CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \ - CONFIG.PSU__DDRC__DEVICE_CAPACITY {8192 MBits} \ - CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \ - CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \ - CONFIG.PSU__DDRC__DQMAP_0_3 {0} \ - CONFIG.PSU__DDRC__DQMAP_12_15 {0} \ - CONFIG.PSU__DDRC__DQMAP_16_19 {0} \ - CONFIG.PSU__DDRC__DQMAP_20_23 {0} \ - CONFIG.PSU__DDRC__DQMAP_24_27 {0} \ - CONFIG.PSU__DDRC__DQMAP_28_31 {0} \ - CONFIG.PSU__DDRC__DQMAP_32_35 {0} \ - CONFIG.PSU__DDRC__DQMAP_36_39 {0} \ - CONFIG.PSU__DDRC__DQMAP_40_43 {0} \ - CONFIG.PSU__DDRC__DQMAP_44_47 {0} \ - CONFIG.PSU__DDRC__DQMAP_48_51 {0} \ - CONFIG.PSU__DDRC__DQMAP_4_7 {0} \ - CONFIG.PSU__DDRC__DQMAP_52_55 {0} \ - CONFIG.PSU__DDRC__DQMAP_56_59 {0} \ - CONFIG.PSU__DDRC__DQMAP_60_63 {0} \ - CONFIG.PSU__DDRC__DQMAP_64_67 {0} \ - CONFIG.PSU__DDRC__DQMAP_68_71 {0} \ - CONFIG.PSU__DDRC__DQMAP_8_11 {0} \ - CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \ - CONFIG.PSU__DDRC__ECC {Disabled} \ - CONFIG.PSU__DDRC__ECC_SCRUB {0} \ - CONFIG.PSU__DDRC__ENABLE {1} \ - CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \ - CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {0} \ - CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \ - CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \ - CONFIG.PSU__DDRC__EN_2ND_CLK {0} \ - CONFIG.PSU__DDRC__FGRM {1X} \ - CONFIG.PSU__DDRC__FREQ_MHZ {1} \ - CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP {0} \ - CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__LP_ASR {manual normal} \ - CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \ - CONFIG.PSU__DDRC__PARITY_ENABLE {0} \ - CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \ - CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \ - CONFIG.PSU__DDRC__PLL_BYPASS {0} \ - CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \ - CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \ - CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \ - CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \ - CONFIG.PSU__DDRC__SB_TARGET {15-15-15} \ - CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \ - CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \ - CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \ - CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \ - CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \ - CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \ - CONFIG.PSU__DDRC__T_FAW {30.0} \ - CONFIG.PSU__DDRC__T_RAS_MIN {33} \ - CONFIG.PSU__DDRC__T_RC {47.06} \ - CONFIG.PSU__DDRC__T_RCD {15} \ - CONFIG.PSU__DDRC__T_RP {15} \ - CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \ - CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \ - CONFIG.PSU__DDRC__VREF {1} \ - CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \ - CONFIG.PSU__DDR_QOS_ENABLE {0} \ - CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {} \ - CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {} \ - CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {} \ - CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {} \ - CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {} \ - CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {} \ - CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {} \ - CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {} \ - CONFIG.PSU__DDR_QOS_HP0_RDQOS {} \ - CONFIG.PSU__DDR_QOS_HP0_WRQOS {} \ - CONFIG.PSU__DDR_QOS_HP1_RDQOS {} \ - CONFIG.PSU__DDR_QOS_HP1_WRQOS {} \ - CONFIG.PSU__DDR_QOS_HP2_RDQOS {} \ - CONFIG.PSU__DDR_QOS_HP2_WRQOS {} \ - CONFIG.PSU__DDR_QOS_HP3_RDQOS {} \ - CONFIG.PSU__DDR_QOS_HP3_WRQOS {} \ - CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {} \ - CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {} \ - CONFIG.PSU__DDR_QOS_WR_THRSHLD {} \ - CONFIG.PSU__DDR_SW_REFRESH_ENABLED {1} \ - CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \ - CONFIG.PSU__DEVICE_TYPE {RFSOC} \ - CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \ - CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \ - CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \ - CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \ - CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__DLL__ISUSED {1} \ - CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \ - CONFIG.PSU__DP__LANE_SEL {Dual Lower} \ - CONFIG.PSU__DP__REF_CLK_FREQ {27} \ - CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \ - CONFIG.PSU__ENABLE__DDR__REFRESH__SIGNALS {0} \ - CONFIG.PSU__ENET0__FIFO__ENABLE {0} \ - CONFIG.PSU__ENET0__GRP_MDIO__ENABLE {0} \ - CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__ENET0__PTP__ENABLE {0} \ - CONFIG.PSU__ENET0__TSU__ENABLE {0} \ - CONFIG.PSU__ENET1__FIFO__ENABLE {0} \ - CONFIG.PSU__ENET1__GRP_MDIO__ENABLE {0} \ - CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__ENET1__PTP__ENABLE {0} \ - CONFIG.PSU__ENET1__TSU__ENABLE {0} \ - CONFIG.PSU__ENET2__FIFO__ENABLE {0} \ - CONFIG.PSU__ENET2__GRP_MDIO__ENABLE {0} \ - CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__ENET2__PTP__ENABLE {0} \ - CONFIG.PSU__ENET2__TSU__ENABLE {0} \ - CONFIG.PSU__ENET3__FIFO__ENABLE {0} \ - CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \ - CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \ - CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \ - CONFIG.PSU__ENET3__PTP__ENABLE {0} \ - CONFIG.PSU__ENET3__TSU__ENABLE {0} \ - CONFIG.PSU__EN_AXI_STATUS_PORTS {0} \ - CONFIG.PSU__EN_EMIO_TRACE {0} \ - CONFIG.PSU__EP__IP {0} \ - CONFIG.PSU__EXPAND__CORESIGHT {0} \ - CONFIG.PSU__EXPAND__FPD_SLAVES {0} \ - CONFIG.PSU__EXPAND__GIC {0} \ - CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \ - CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \ - CONFIG.PSU__FPDMASTERS_COHERENCY {0} \ - CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {99.999001} \ - CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {99.999001} \ - CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \ - CONFIG.PSU__FPGA_PL0_ENABLE {1} \ - CONFIG.PSU__FPGA_PL1_ENABLE {0} \ - CONFIG.PSU__FPGA_PL2_ENABLE {0} \ - CONFIG.PSU__FPGA_PL3_ENABLE {0} \ - CONFIG.PSU__FP__POWER__ON {1} \ - CONFIG.PSU__FTM__CTI_IN_0 {0} \ - CONFIG.PSU__FTM__CTI_IN_1 {0} \ - CONFIG.PSU__FTM__CTI_IN_2 {0} \ - CONFIG.PSU__FTM__CTI_IN_3 {0} \ - CONFIG.PSU__FTM__CTI_OUT_0 {0} \ - CONFIG.PSU__FTM__CTI_OUT_1 {0} \ - CONFIG.PSU__FTM__CTI_OUT_2 {0} \ - CONFIG.PSU__FTM__CTI_OUT_3 {0} \ - CONFIG.PSU__FTM__GPI {0} \ - CONFIG.PSU__FTM__GPO {0} \ - CONFIG.PSU__GEM0_COHERENCY {0} \ - CONFIG.PSU__GEM0_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__GEM1_COHERENCY {0} \ - CONFIG.PSU__GEM1_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__GEM2_COHERENCY {0} \ - CONFIG.PSU__GEM2_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__GEM3_COHERENCY {0} \ - CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__GEM__TSU__ENABLE {0} \ - CONFIG.PSU__GEN_IPI_0__MASTER {APU} \ - CONFIG.PSU__GEN_IPI_10__MASTER {NONE} \ - CONFIG.PSU__GEN_IPI_1__MASTER {RPU0} \ - CONFIG.PSU__GEN_IPI_2__MASTER {RPU1} \ - CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \ - CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \ - CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \ - CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \ - CONFIG.PSU__GEN_IPI_7__MASTER {NONE} \ - CONFIG.PSU__GEN_IPI_8__MASTER {NONE} \ - CONFIG.PSU__GEN_IPI_9__MASTER {NONE} \ - CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \ - CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \ - CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__GPIO_EMIO_WIDTH {1} \ - CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {} \ - CONFIG.PSU__GPIO_EMIO__WIDTH {[94:0]} \ - CONFIG.PSU__GPU_PP0__POWER__ON {0} \ - CONFIG.PSU__GPU_PP1__POWER__ON {0} \ - CONFIG.PSU__GT_REF_CLK__FREQMHZ {33.333} \ - CONFIG.PSU__GT__LINK_SPEED {HBR} \ - CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \ - CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \ - CONFIG.PSU__HIGH_ADDRESS__ENABLE {1} \ - CONFIG.PSU__HPM0_FPD__NUM_READ_THREADS {4} \ - CONFIG.PSU__HPM0_FPD__NUM_WRITE_THREADS {4} \ - CONFIG.PSU__HPM0_LPD__NUM_READ_THREADS {4} \ - CONFIG.PSU__HPM0_LPD__NUM_WRITE_THREADS {4} \ - CONFIG.PSU__HPM1_FPD__NUM_READ_THREADS {4} \ - CONFIG.PSU__HPM1_FPD__NUM_WRITE_THREADS {4} \ - CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \ - CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \ - CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 14 .. 15} \ - CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \ - CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \ - CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \ - CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \ - CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \ - CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \ - CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {99.999001} \ - CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {99.999001} \ - CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \ - CONFIG.PSU__IRQ_P2F_ADMA_CHAN__INT {0} \ - CONFIG.PSU__IRQ_P2F_AIB_AXI__INT {0} \ - CONFIG.PSU__IRQ_P2F_AMS__INT {0} \ - CONFIG.PSU__IRQ_P2F_APM_FPD__INT {0} \ - CONFIG.PSU__IRQ_P2F_APU_COMM__INT {0} \ - CONFIG.PSU__IRQ_P2F_APU_CPUMNT__INT {0} \ - CONFIG.PSU__IRQ_P2F_APU_CTI__INT {0} \ - CONFIG.PSU__IRQ_P2F_APU_EXTERR__INT {0} \ - CONFIG.PSU__IRQ_P2F_APU_IPI__INT {0} \ - CONFIG.PSU__IRQ_P2F_APU_L2ERR__INT {0} \ - CONFIG.PSU__IRQ_P2F_APU_PMU__INT {0} \ - CONFIG.PSU__IRQ_P2F_APU_REGS__INT {0} \ - CONFIG.PSU__IRQ_P2F_ATB_LPD__INT {0} \ - CONFIG.PSU__IRQ_P2F_CAN0__INT {0} \ - CONFIG.PSU__IRQ_P2F_CAN1__INT {0} \ - CONFIG.PSU__IRQ_P2F_CLKMON__INT {0} \ - CONFIG.PSU__IRQ_P2F_CSUPMU_WDT__INT {0} \ - CONFIG.PSU__IRQ_P2F_CSU_DMA__INT {0} \ - CONFIG.PSU__IRQ_P2F_CSU__INT {0} \ - CONFIG.PSU__IRQ_P2F_DDR_SS__INT {0} \ - CONFIG.PSU__IRQ_P2F_DPDMA__INT {0} \ - CONFIG.PSU__IRQ_P2F_DPORT__INT {0} \ - CONFIG.PSU__IRQ_P2F_EFUSE__INT {0} \ - CONFIG.PSU__IRQ_P2F_ENT0_WAKEUP__INT {0} \ - CONFIG.PSU__IRQ_P2F_ENT0__INT {0} \ - CONFIG.PSU__IRQ_P2F_ENT1_WAKEUP__INT {0} \ - CONFIG.PSU__IRQ_P2F_ENT1__INT {0} \ - CONFIG.PSU__IRQ_P2F_ENT2_WAKEUP__INT {0} \ - CONFIG.PSU__IRQ_P2F_ENT2__INT {0} \ - CONFIG.PSU__IRQ_P2F_ENT3_WAKEUP__INT {0} \ - CONFIG.PSU__IRQ_P2F_ENT3__INT {0} \ - CONFIG.PSU__IRQ_P2F_FPD_APB__INT {0} \ - CONFIG.PSU__IRQ_P2F_FPD_ATB_ERR__INT {0} \ - CONFIG.PSU__IRQ_P2F_FP_WDT__INT {0} \ - CONFIG.PSU__IRQ_P2F_GDMA_CHAN__INT {0} \ - CONFIG.PSU__IRQ_P2F_GPIO__INT {0} \ - CONFIG.PSU__IRQ_P2F_GPU__INT {0} \ - CONFIG.PSU__IRQ_P2F_I2C0__INT {0} \ - CONFIG.PSU__IRQ_P2F_I2C1__INT {0} \ - CONFIG.PSU__IRQ_P2F_LPD_APB__INT {0} \ - CONFIG.PSU__IRQ_P2F_LPD_APM__INT {0} \ - CONFIG.PSU__IRQ_P2F_LP_WDT__INT {0} \ - CONFIG.PSU__IRQ_P2F_NAND__INT {0} \ - CONFIG.PSU__IRQ_P2F_OCM_ERR__INT {0} \ - CONFIG.PSU__IRQ_P2F_PCIE_DMA__INT {0} \ - CONFIG.PSU__IRQ_P2F_PCIE_LEGACY__INT {0} \ - CONFIG.PSU__IRQ_P2F_PCIE_MSC__INT {0} \ - CONFIG.PSU__IRQ_P2F_PCIE_MSI__INT {0} \ - CONFIG.PSU__IRQ_P2F_PL_IPI__INT {0} \ - CONFIG.PSU__IRQ_P2F_QSPI__INT {0} \ - CONFIG.PSU__IRQ_P2F_R5_CORE0_ECC_ERR__INT {0} \ - CONFIG.PSU__IRQ_P2F_R5_CORE1_ECC_ERR__INT {0} \ - CONFIG.PSU__IRQ_P2F_RPU_IPI__INT {0} \ - CONFIG.PSU__IRQ_P2F_RPU_PERMON__INT {0} \ - CONFIG.PSU__IRQ_P2F_RTC_ALARM__INT {0} \ - CONFIG.PSU__IRQ_P2F_RTC_SECONDS__INT {0} \ - CONFIG.PSU__IRQ_P2F_SATA__INT {0} \ - CONFIG.PSU__IRQ_P2F_SDIO0_WAKE__INT {0} \ - CONFIG.PSU__IRQ_P2F_SDIO0__INT {0} \ - CONFIG.PSU__IRQ_P2F_SDIO1_WAKE__INT {0} \ - CONFIG.PSU__IRQ_P2F_SDIO1__INT {0} \ - CONFIG.PSU__IRQ_P2F_SPI0__INT {0} \ - CONFIG.PSU__IRQ_P2F_SPI1__INT {0} \ - CONFIG.PSU__IRQ_P2F_TTC0__INT0 {0} \ - CONFIG.PSU__IRQ_P2F_TTC0__INT1 {0} \ - CONFIG.PSU__IRQ_P2F_TTC0__INT2 {0} \ - CONFIG.PSU__IRQ_P2F_TTC1__INT0 {0} \ - CONFIG.PSU__IRQ_P2F_TTC1__INT1 {0} \ - CONFIG.PSU__IRQ_P2F_TTC1__INT2 {0} \ - CONFIG.PSU__IRQ_P2F_TTC2__INT0 {0} \ - CONFIG.PSU__IRQ_P2F_TTC2__INT1 {0} \ - CONFIG.PSU__IRQ_P2F_TTC2__INT2 {0} \ - CONFIG.PSU__IRQ_P2F_TTC3__INT0 {0} \ - CONFIG.PSU__IRQ_P2F_TTC3__INT1 {0} \ - CONFIG.PSU__IRQ_P2F_TTC3__INT2 {0} \ - CONFIG.PSU__IRQ_P2F_UART0__INT {0} \ - CONFIG.PSU__IRQ_P2F_UART1__INT {0} \ - CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT0 {0} \ - CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT1 {0} \ - CONFIG.PSU__IRQ_P2F_USB3_OTG__INT0 {0} \ - CONFIG.PSU__IRQ_P2F_USB3_OTG__INT1 {0} \ - CONFIG.PSU__IRQ_P2F_USB3_PMU_WAKEUP__INT {0} \ - CONFIG.PSU__IRQ_P2F_XMPU_FPD__INT {0} \ - CONFIG.PSU__IRQ_P2F_XMPU_LPD__INT {0} \ - CONFIG.PSU__IRQ_P2F__INTF_FPD_SMMU__INT {0} \ - CONFIG.PSU__IRQ_P2F__INTF_PPD_CCI__INT {0} \ - CONFIG.PSU__L2_BANK0__POWER__ON {1} \ - CONFIG.PSU__LPDMA0_COHERENCY {0} \ - CONFIG.PSU__LPDMA1_COHERENCY {0} \ - CONFIG.PSU__LPDMA2_COHERENCY {0} \ - CONFIG.PSU__LPDMA3_COHERENCY {0} \ - CONFIG.PSU__LPDMA4_COHERENCY {0} \ - CONFIG.PSU__LPDMA5_COHERENCY {0} \ - CONFIG.PSU__LPDMA6_COHERENCY {0} \ - CONFIG.PSU__LPDMA7_COHERENCY {0} \ - CONFIG.PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT {APB} \ - CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \ - CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \ - CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \ - CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \ - CONFIG.PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST {1} \ - CONFIG.PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST {1} \ - CONFIG.PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST {1} \ - CONFIG.PSU__NAND_COHERENCY {0} \ - CONFIG.PSU__NAND_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__NAND__CHIP_ENABLE__ENABLE {0} \ - CONFIG.PSU__NAND__DATA_STROBE__ENABLE {0} \ - CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__NAND__READY0_BUSY__ENABLE {0} \ - CONFIG.PSU__NAND__READY1_BUSY__ENABLE {0} \ - CONFIG.PSU__NAND__READY_BUSY__ENABLE {0} \ - CONFIG.PSU__NUM_FABRIC_RESETS {1} \ - CONFIG.PSU__OCM_BANK0__POWER__ON {1} \ - CONFIG.PSU__OCM_BANK1__POWER__ON {1} \ - CONFIG.PSU__OCM_BANK2__POWER__ON {1} \ - CONFIG.PSU__OCM_BANK3__POWER__ON {1} \ - CONFIG.PSU__OVERRIDE_HPX_QOS {0} \ - CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \ - CONFIG.PSU__PCIE__ACS_VIOLAION {0} \ - CONFIG.PSU__PCIE__ACS_VIOLATION {0} \ - CONFIG.PSU__PCIE__AER_CAPABILITY {0} \ - CONFIG.PSU__PCIE__ATOMICOP_EGRESS_BLOCKED {0} \ - CONFIG.PSU__PCIE__BAR0_64BIT {0} \ - CONFIG.PSU__PCIE__BAR0_ENABLE {0} \ - CONFIG.PSU__PCIE__BAR0_PREFETCHABLE {0} \ - CONFIG.PSU__PCIE__BAR0_VAL {} \ - CONFIG.PSU__PCIE__BAR1_64BIT {0} \ - CONFIG.PSU__PCIE__BAR1_ENABLE {0} \ - CONFIG.PSU__PCIE__BAR1_PREFETCHABLE {0} \ - CONFIG.PSU__PCIE__BAR1_VAL {} \ - CONFIG.PSU__PCIE__BAR2_64BIT {0} \ - CONFIG.PSU__PCIE__BAR2_ENABLE {0} \ - CONFIG.PSU__PCIE__BAR2_PREFETCHABLE {0} \ - CONFIG.PSU__PCIE__BAR2_VAL {} \ - CONFIG.PSU__PCIE__BAR3_64BIT {0} \ - CONFIG.PSU__PCIE__BAR3_ENABLE {0} \ - CONFIG.PSU__PCIE__BAR3_PREFETCHABLE {0} \ - CONFIG.PSU__PCIE__BAR3_VAL {} \ - CONFIG.PSU__PCIE__BAR4_64BIT {0} \ - CONFIG.PSU__PCIE__BAR4_ENABLE {0} \ - CONFIG.PSU__PCIE__BAR4_PREFETCHABLE {0} \ - CONFIG.PSU__PCIE__BAR4_VAL {} \ - CONFIG.PSU__PCIE__BAR5_64BIT {0} \ - CONFIG.PSU__PCIE__BAR5_ENABLE {0} \ - CONFIG.PSU__PCIE__BAR5_PREFETCHABLE {0} \ - CONFIG.PSU__PCIE__BAR5_VAL {} \ - CONFIG.PSU__PCIE__CLASS_CODE_BASE {} \ - CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {} \ - CONFIG.PSU__PCIE__CLASS_CODE_SUB {} \ - CONFIG.PSU__PCIE__CLASS_CODE_VALUE {} \ - CONFIG.PSU__PCIE__COMPLETER_ABORT {0} \ - CONFIG.PSU__PCIE__COMPLTION_TIMEOUT {0} \ - CONFIG.PSU__PCIE__CORRECTABLE_INT_ERR {0} \ - CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {0} \ - CONFIG.PSU__PCIE__DEVICE_ID {} \ - CONFIG.PSU__PCIE__ECRC_CHECK {0} \ - CONFIG.PSU__PCIE__ECRC_ERR {0} \ - CONFIG.PSU__PCIE__ECRC_GEN {0} \ - CONFIG.PSU__PCIE__EROM_ENABLE {0} \ - CONFIG.PSU__PCIE__EROM_VAL {} \ - CONFIG.PSU__PCIE__FLOW_CONTROL_ERR {0} \ - CONFIG.PSU__PCIE__FLOW_CONTROL_PROTOCOL_ERR {0} \ - CONFIG.PSU__PCIE__HEADER_LOG_OVERFLOW {0} \ - CONFIG.PSU__PCIE__INTX_GENERATION {0} \ - CONFIG.PSU__PCIE__LANE0__ENABLE {0} \ - CONFIG.PSU__PCIE__LANE1__ENABLE {0} \ - CONFIG.PSU__PCIE__LANE2__ENABLE {0} \ - CONFIG.PSU__PCIE__LANE3__ENABLE {0} \ - CONFIG.PSU__PCIE__MC_BLOCKED_TLP {0} \ - CONFIG.PSU__PCIE__MSIX_BAR_INDICATOR {} \ - CONFIG.PSU__PCIE__MSIX_CAPABILITY {0} \ - CONFIG.PSU__PCIE__MSIX_PBA_BAR_INDICATOR {} \ - CONFIG.PSU__PCIE__MSIX_PBA_OFFSET {0} \ - CONFIG.PSU__PCIE__MSIX_TABLE_OFFSET {0} \ - CONFIG.PSU__PCIE__MSIX_TABLE_SIZE {0} \ - CONFIG.PSU__PCIE__MSI_64BIT_ADDR_CAPABLE {0} \ - CONFIG.PSU__PCIE__MSI_CAPABILITY {0} \ - CONFIG.PSU__PCIE__MULTIHEADER {0} \ - CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {1} \ - CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {0} \ - CONFIG.PSU__PCIE__PERM_ROOT_ERR_UPDATE {0} \ - CONFIG.PSU__PCIE__RECEIVER_ERR {0} \ - CONFIG.PSU__PCIE__RECEIVER_OVERFLOW {0} \ - CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \ - CONFIG.PSU__PCIE__REVISION_ID {} \ - CONFIG.PSU__PCIE__SUBSYSTEM_ID {} \ - CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {} \ - CONFIG.PSU__PCIE__SURPRISE_DOWN {0} \ - CONFIG.PSU__PCIE__TLP_PREFIX_BLOCKED {0} \ - CONFIG.PSU__PCIE__UNCORRECTABL_INT_ERR {0} \ - CONFIG.PSU__PCIE__VENDOR_ID {} \ - CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__PL_CLK0_BUF {TRUE} \ - CONFIG.PSU__PL_CLK1_BUF {TRUE} \ - CONFIG.PSU__PL_CLK2_BUF {FALSE} \ - CONFIG.PSU__PL_CLK3_BUF {FALSE} \ - CONFIG.PSU__PL__POWER__ON {1} \ - CONFIG.PSU__PMU_COHERENCY {0} \ - CONFIG.PSU__PMU__AIBACK__ENABLE {0} \ - CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \ - CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \ - CONFIG.PSU__PMU__GPI0__ENABLE {0} \ - CONFIG.PSU__PMU__GPI1__ENABLE {0} \ - CONFIG.PSU__PMU__GPI2__ENABLE {0} \ - CONFIG.PSU__PMU__GPI3__ENABLE {0} \ - CONFIG.PSU__PMU__GPI4__ENABLE {0} \ - CONFIG.PSU__PMU__GPI5__ENABLE {0} \ - CONFIG.PSU__PMU__GPO0__ENABLE {1} \ - CONFIG.PSU__PMU__GPO0__IO {MIO 32} \ - CONFIG.PSU__PMU__GPO1__ENABLE {1} \ - CONFIG.PSU__PMU__GPO1__IO {MIO 33} \ - CONFIG.PSU__PMU__GPO2__ENABLE {1} \ - CONFIG.PSU__PMU__GPO2__IO {MIO 34} \ - CONFIG.PSU__PMU__GPO2__POLARITY {low} \ - CONFIG.PSU__PMU__GPO3__ENABLE {1} \ - CONFIG.PSU__PMU__GPO3__IO {MIO 35} \ - CONFIG.PSU__PMU__GPO3__POLARITY {low} \ - CONFIG.PSU__PMU__GPO4__ENABLE {1} \ - CONFIG.PSU__PMU__GPO4__IO {MIO 36} \ - CONFIG.PSU__PMU__GPO4__POLARITY {low} \ - CONFIG.PSU__PMU__GPO5__ENABLE {1} \ - CONFIG.PSU__PMU__GPO5__IO {MIO 37} \ - CONFIG.PSU__PMU__GPO5__POLARITY {low} \ - CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__PMU__PLERROR__ENABLE {0} \ - CONFIG.PSU__PRESET_APPLIED {1} \ - CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \ - CONFIG.PSU__PROTECTION__DEBUG {0} \ - CONFIG.PSU__PROTECTION__ENABLE {0} \ - CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD010000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD040000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD5D0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem} \ - CONFIG.PSU__PROTECTION__LOCK_UNUSED_SEGMENTS {0} \ - CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF5E0000; SIZE:2560; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFCC0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF180000; SIZE:768; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF410000; SIZE:640; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFA70000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|SA:0xFF5E0000 ; SIZE:2560; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFFCC0000 ; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF180000 ; SIZE:768; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF9A0000 ; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem} \ - CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;1|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \ - CONFIG.PSU__PROTECTION__MASTERS_TZ {GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure} \ - CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \ - CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \ - CONFIG.PSU__PROTECTION__SLAVES { \ - LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1 \ - } \ - CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU|Secure Subsystem:} \ - CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \ - CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \ - CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333} \ - CONFIG.PSU__QSPI_COHERENCY {0} \ - CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \ - CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \ - CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \ - CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 12} \ - CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel} \ - CONFIG.PSU__REPORT__DBGLOG {0} \ - CONFIG.PSU__RPU_COHERENCY {0} \ - CONFIG.PSU__RPU__POWER__ON {1} \ - CONFIG.PSU__SATA__LANE0__ENABLE {0} \ - CONFIG.PSU__SATA__LANE1__ENABLE {1} \ - CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \ - CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__SATA__REF_CLK_FREQ {125} \ - CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk3} \ - CONFIG.PSU__SAXIGP0__DATA_WIDTH {128} \ - CONFIG.PSU__SAXIGP1__DATA_WIDTH {128} \ - CONFIG.PSU__SAXIGP2__DATA_WIDTH {128} \ - CONFIG.PSU__SAXIGP3__DATA_WIDTH {128} \ - CONFIG.PSU__SAXIGP4__DATA_WIDTH {128} \ - CONFIG.PSU__SAXIGP5__DATA_WIDTH {128} \ - CONFIG.PSU__SAXIGP6__DATA_WIDTH {128} \ - CONFIG.PSU__SD0_COHERENCY {0} \ - CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__SD0__GRP_CD__ENABLE {0} \ - CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \ - CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \ - CONFIG.PSU__SD0__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__SD0__RESET__ENABLE {0} \ - CONFIG.PSU__SD1_COHERENCY {0} \ - CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__SD1__DATA_TRANSFER_MODE {8Bit} \ - CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \ - CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \ - CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \ - CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \ - CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 39 .. 51} \ - CONFIG.PSU__SD1__RESET__ENABLE {0} \ - CONFIG.PSU__SD1__SLOT_TYPE {SD 3.0} \ - CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE {0} \ - CONFIG.PSU__SPI0__GRP_SS0__ENABLE {0} \ - CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \ - CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \ - CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__SPI1__GRP_SS0__ENABLE {0} \ - CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \ - CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \ - CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \ - CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__SWDT0__PERIPHERAL__IO {NA} \ - CONFIG.PSU__SWDT0__RESET__ENABLE {0} \ - CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \ - CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__SWDT1__PERIPHERAL__IO {NA} \ - CONFIG.PSU__SWDT1__RESET__ENABLE {0} \ - CONFIG.PSU__TCM0A__POWER__ON {1} \ - CONFIG.PSU__TCM0B__POWER__ON {1} \ - CONFIG.PSU__TCM1A__POWER__ON {1} \ - CONFIG.PSU__TCM1B__POWER__ON {1} \ - CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__TRACE_PIPELINE_WIDTH {8} \ - CONFIG.PSU__TRACE__INTERNAL_WIDTH {32} \ - CONFIG.PSU__TRACE__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__TRISTATE__INVERTED {1} \ - CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \ - CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \ - CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__TTC0__PERIPHERAL__IO {NA} \ - CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \ - CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \ - CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__TTC1__PERIPHERAL__IO {NA} \ - CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \ - CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \ - CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__TTC2__PERIPHERAL__IO {NA} \ - CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \ - CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \ - CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__TTC3__PERIPHERAL__IO {NA} \ - CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \ - CONFIG.PSU__UART0_LOOP_UART1__ENABLE {0} \ - CONFIG.PSU__UART0__BAUD_RATE {115200} \ - CONFIG.PSU__UART0__MODEM__ENABLE {0} \ - CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \ - CONFIG.PSU__UART1__BAUD_RATE {115200} \ - CONFIG.PSU__UART1__MODEM__ENABLE {0} \ - CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__UART1__PERIPHERAL__IO {EMIO} \ - CONFIG.PSU__USB0_COHERENCY {0} \ - CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \ - CONFIG.PSU__USB0__REF_CLK_FREQ {26} \ - CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \ - CONFIG.PSU__USB0__RESET__ENABLE {0} \ - CONFIG.PSU__USB1_COHERENCY {0} \ - CONFIG.PSU__USB1__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__USB1__RESET__ENABLE {0} \ - CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \ - CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \ - CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \ - CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \ - CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \ - CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__USB__RESET__MODE {Boot Pin} \ - CONFIG.PSU__USB__RESET__POLARITY {Active Low} \ - CONFIG.PSU__USE_DIFF_RW_CLK_GP0 {0} \ - CONFIG.PSU__USE_DIFF_RW_CLK_GP1 {0} \ - CONFIG.PSU__USE_DIFF_RW_CLK_GP2 {0} \ - CONFIG.PSU__USE_DIFF_RW_CLK_GP3 {0} \ - CONFIG.PSU__USE_DIFF_RW_CLK_GP4 {0} \ - CONFIG.PSU__USE_DIFF_RW_CLK_GP5 {0} \ - CONFIG.PSU__USE_DIFF_RW_CLK_GP6 {0} \ - CONFIG.PSU__USE__ADMA {0} \ - CONFIG.PSU__USE__APU_LEGACY_INTERRUPT {0} \ - CONFIG.PSU__USE__AUDIO {0} \ - CONFIG.PSU__USE__CLK {0} \ - CONFIG.PSU__USE__CLK0 {0} \ - CONFIG.PSU__USE__CLK1 {0} \ - CONFIG.PSU__USE__CLK2 {0} \ - CONFIG.PSU__USE__CLK3 {0} \ - CONFIG.PSU__USE__CROSS_TRIGGER {0} \ - CONFIG.PSU__USE__DDR_INTF_REQUESTED {0} \ - CONFIG.PSU__USE__DEBUG__TEST {0} \ - CONFIG.PSU__USE__EVENT_RPU {0} \ - CONFIG.PSU__USE__FABRIC__RST {1} \ - CONFIG.PSU__USE__FTM {0} \ - CONFIG.PSU__USE__GDMA {0} \ - CONFIG.PSU__USE__IRQ {0} \ - CONFIG.PSU__USE__IRQ0 {1} \ - CONFIG.PSU__USE__IRQ1 {0} \ - CONFIG.PSU__USE__M_AXI_GP0 {1} \ - CONFIG.PSU__USE__M_AXI_GP1 {0} \ - CONFIG.PSU__USE__M_AXI_GP2 {0} \ - CONFIG.PSU__USE__PROC_EVENT_BUS {0} \ - CONFIG.PSU__USE__RPU_LEGACY_INTERRUPT {0} \ - CONFIG.PSU__USE__RST0 {0} \ - CONFIG.PSU__USE__RST1 {0} \ - CONFIG.PSU__USE__RST2 {0} \ - CONFIG.PSU__USE__RST3 {0} \ - CONFIG.PSU__USE__RTC {0} \ - CONFIG.PSU__USE__STM {0} \ - CONFIG.PSU__USE__S_AXI_ACE {0} \ - CONFIG.PSU__USE__S_AXI_ACP {0} \ - CONFIG.PSU__USE__S_AXI_GP0 {1} \ - CONFIG.PSU__USE__S_AXI_GP1 {0} \ - CONFIG.PSU__USE__S_AXI_GP2 {0} \ - CONFIG.PSU__USE__S_AXI_GP3 {0} \ - CONFIG.PSU__USE__S_AXI_GP4 {0} \ - CONFIG.PSU__USE__S_AXI_GP5 {0} \ - CONFIG.PSU__USE__S_AXI_GP6 {0} \ - CONFIG.PSU__USE__USB3_0_HUB {0} \ - CONFIG.PSU__USE__USB3_1_HUB {0} \ - CONFIG.PSU__USE__VIDEO {0} \ - CONFIG.PSU__VIDEO_REF_CLK__ENABLE {0} \ - CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ {33.333} \ - CONFIG.QSPI_BOARD_INTERFACE {custom} \ - CONFIG.SATA_BOARD_INTERFACE {custom} \ - CONFIG.SD0_BOARD_INTERFACE {custom} \ - CONFIG.SD1_BOARD_INTERFACE {custom} \ - CONFIG.SPI0_BOARD_INTERFACE {custom} \ - CONFIG.SPI1_BOARD_INTERFACE {custom} \ - CONFIG.SUBPRESET1 {Custom} \ - CONFIG.SUBPRESET2 {Custom} \ - CONFIG.SWDT0_BOARD_INTERFACE {custom} \ - CONFIG.SWDT1_BOARD_INTERFACE {custom} \ - CONFIG.TRACE_BOARD_INTERFACE {custom} \ - CONFIG.TTC0_BOARD_INTERFACE {custom} \ - CONFIG.TTC1_BOARD_INTERFACE {custom} \ - CONFIG.TTC2_BOARD_INTERFACE {custom} \ - CONFIG.TTC3_BOARD_INTERFACE {custom} \ - CONFIG.UART0_BOARD_INTERFACE {custom} \ - CONFIG.UART1_BOARD_INTERFACE {custom} \ - CONFIG.USB0_BOARD_INTERFACE {custom} \ - CONFIG.USB1_BOARD_INTERFACE {custom} \ - ] $zynq_ultra_ps_e_0 - - # Create interface connections - connect_bd_intf_net -intf_net adc0_clk_1 [get_bd_intf_ports adc0_clk] [get_bd_intf_pins usp_rf_data_converter_0/adc0_clk] - connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins axi_bram_ctrl_0_bram/BRAM_PORTA] - connect_bd_intf_net -intf_net axi_dma_0_M_AXIS_MM2S [get_bd_intf_pins axi_dma_tproc/M_AXIS_MM2S] [get_bd_intf_pins axis_tproc64x32_x8_0/s0_axis] - connect_bd_intf_net -intf_net axi_dma_0_M_AXI_MM2S [get_bd_intf_pins axi_dma_tproc/M_AXI_MM2S] [get_bd_intf_pins axi_smc/S00_AXI] - connect_bd_intf_net -intf_net axi_dma_0_M_AXI_S2MM [get_bd_intf_pins axi_dma_tproc/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S01_AXI] - connect_bd_intf_net -intf_net axi_dma_1_M_AXIS_MM2S [get_bd_intf_pins axi_dma_gen/M_AXIS_MM2S] [get_bd_intf_pins axis_switch_gen/S00_AXIS] - connect_bd_intf_net -intf_net axi_dma_1_M_AXI_MM2S [get_bd_intf_pins axi_dma_gen/M_AXI_MM2S] [get_bd_intf_pins axi_smc/S02_AXI] - connect_bd_intf_net -intf_net axi_dma_avg_M_AXI_S2MM [get_bd_intf_pins axi_dma_avg/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S03_AXI] - connect_bd_intf_net -intf_net axi_dma_buf_M_AXI_S2MM [get_bd_intf_pins axi_dma_buf/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S04_AXI] - connect_bd_intf_net -intf_net axi_smc_M00_AXI [get_bd_intf_pins axi_smc/M00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HPC0_FPD] - connect_bd_intf_net -intf_net axis_avg_buffer_0_m0_axis [get_bd_intf_pins axis_avg_buffer_0/m0_axis] [get_bd_intf_pins axis_switch_avg/S00_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_0_m1_axis [get_bd_intf_pins axis_avg_buffer_0/m1_axis] [get_bd_intf_pins axis_switch_buf/S00_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_0_m2_axis [get_bd_intf_pins axis_avg_buffer_0/m2_axis] [get_bd_intf_pins axis_clk_cnvrt_avg_0/S_AXIS] -connect_bd_intf_net -intf_net [get_bd_intf_nets axis_avg_buffer_0_m2_axis] [get_bd_intf_pins axis_clk_cnvrt_avg_0/S_AXIS] [get_bd_intf_pins system_ila_0/SLOT_0_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_1_m0_axis [get_bd_intf_pins axis_avg_buffer_1/m0_axis] [get_bd_intf_pins axis_switch_avg/S01_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_1_m1_axis [get_bd_intf_pins axis_avg_buffer_1/m1_axis] [get_bd_intf_pins axis_switch_buf/S01_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_1_m2_axis [get_bd_intf_pins axis_avg_buffer_1/m2_axis] [get_bd_intf_pins axis_clk_cnvrt_avg_1/S_AXIS] - connect_bd_intf_net -intf_net axis_clk_cnvrt_avg_0_M_AXIS [get_bd_intf_pins axis_clk_cnvrt_avg_0/M_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/s1_axis] -connect_bd_intf_net -intf_net [get_bd_intf_nets axis_clk_cnvrt_avg_0_M_AXIS] [get_bd_intf_pins axis_clk_cnvrt_avg_0/M_AXIS] [get_bd_intf_pins system_ila_1/SLOT_0_AXIS] - connect_bd_intf_net -intf_net axis_clk_cnvrt_avg_1_M_AXIS [get_bd_intf_pins axis_clk_cnvrt_avg_1/M_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/s2_axis] - connect_bd_intf_net -intf_net axis_clock_converter_3_M_AXIS [get_bd_intf_pins axis_clk_cnvrt_gen_3/M_AXIS] [get_bd_intf_pins axis_signal_gen_v6_3/s1_axis] - connect_bd_intf_net -intf_net axis_clock_converter_4_M_AXIS [get_bd_intf_pins axis_clk_cnvrt_gen_4/M_AXIS] [get_bd_intf_pins axis_signal_gen_v6_4/s1_axis] - connect_bd_intf_net -intf_net axis_clock_converter_5_M_AXIS [get_bd_intf_pins axis_clk_cnvrt_gen_5/M_AXIS] [get_bd_intf_pins axis_signal_gen_v6_5/s1_axis] - connect_bd_intf_net -intf_net axis_clock_converter_6_M_AXIS [get_bd_intf_pins axis_clk_cnvrt_gen_6/M_AXIS] [get_bd_intf_pins axis_signal_gen_v6_6/s1_axis] - connect_bd_intf_net -intf_net axis_constant_0_m_axis [get_bd_intf_pins axis_constant_0/m_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/s3_axis] - connect_bd_intf_net -intf_net axis_constant_1_m_axis [get_bd_intf_pins axis_constant_1/m_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/s4_axis] - connect_bd_intf_net -intf_net axis_readout_v2_0_m0_axis [get_bd_intf_pins axis_readout_v2_0/m0_axis] [get_bd_intf_pins axis_terminator_0/s_axis] - connect_bd_intf_net -intf_net axis_readout_v2_0_m1_axis [get_bd_intf_pins axis_avg_buffer_0/s_axis] [get_bd_intf_pins axis_readout_v2_0/m1_axis] - connect_bd_intf_net -intf_net axis_readout_v2_1_m0_axis [get_bd_intf_pins axis_readout_v2_1/m0_axis] [get_bd_intf_pins axis_terminator_1/s_axis] - connect_bd_intf_net -intf_net axis_readout_v2_1_m1_axis [get_bd_intf_pins axis_avg_buffer_1/s_axis] [get_bd_intf_pins axis_readout_v2_1/m1_axis] - connect_bd_intf_net -intf_net axis_register_slice_0_M_AXIS [get_bd_intf_pins axis_readout_v2_0/s_axis] [get_bd_intf_pins axis_register_slice_0/M_AXIS] - connect_bd_intf_net -intf_net axis_register_slice_1_M_AXIS [get_bd_intf_pins axis_readout_v2_1/s_axis] [get_bd_intf_pins axis_register_slice_1/M_AXIS] - connect_bd_intf_net -intf_net axis_signal_gen_v6_0_m_axis [get_bd_intf_pins axis_signal_gen_v6_0/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s00_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v6_1_m_axis [get_bd_intf_pins axis_signal_gen_v6_1/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s01_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v6_2_m_axis [get_bd_intf_pins axis_signal_gen_v6_2/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s02_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v6_3_m_axis [get_bd_intf_pins axis_signal_gen_v6_3/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s10_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v6_4_m_axis [get_bd_intf_pins axis_signal_gen_v6_4/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s11_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v6_5_m_axis [get_bd_intf_pins axis_signal_gen_v6_5/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s12_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v6_6_m_axis [get_bd_intf_pins axis_signal_gen_v6_6/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s13_axis] - connect_bd_intf_net -intf_net axis_switch_0_M00_AXIS [get_bd_intf_pins axis_signal_gen_v6_0/s0_axis] [get_bd_intf_pins axis_switch_gen/M00_AXIS] - connect_bd_intf_net -intf_net axis_switch_0_M01_AXIS [get_bd_intf_pins axis_signal_gen_v6_1/s0_axis] [get_bd_intf_pins axis_switch_gen/M01_AXIS] - connect_bd_intf_net -intf_net axis_switch_0_M02_AXIS [get_bd_intf_pins axis_signal_gen_v6_2/s0_axis] [get_bd_intf_pins axis_switch_gen/M02_AXIS] - connect_bd_intf_net -intf_net axis_switch_0_M03_AXIS [get_bd_intf_pins axis_signal_gen_v6_3/s0_axis] [get_bd_intf_pins axis_switch_gen/M03_AXIS] - connect_bd_intf_net -intf_net axis_switch_0_M04_AXIS [get_bd_intf_pins axis_signal_gen_v6_4/s0_axis] [get_bd_intf_pins axis_switch_gen/M04_AXIS] - connect_bd_intf_net -intf_net axis_switch_0_M05_AXIS [get_bd_intf_pins axis_signal_gen_v6_5/s0_axis] [get_bd_intf_pins axis_switch_gen/M05_AXIS] - connect_bd_intf_net -intf_net axis_switch_0_M06_AXIS [get_bd_intf_pins axis_signal_gen_v6_6/s0_axis] [get_bd_intf_pins axis_switch_gen/M06_AXIS] - connect_bd_intf_net -intf_net axis_switch_avg_M00_AXIS [get_bd_intf_pins axi_dma_avg/S_AXIS_S2MM] [get_bd_intf_pins axis_switch_avg/M00_AXIS] - connect_bd_intf_net -intf_net axis_switch_buf_M00_AXIS [get_bd_intf_pins axi_dma_buf/S_AXIS_S2MM] [get_bd_intf_pins axis_switch_buf/M00_AXIS] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m0_axis [get_bd_intf_pins axi_dma_tproc/S_AXIS_S2MM] [get_bd_intf_pins axis_tproc64x32_x8_0/m0_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m1_axis [get_bd_intf_pins axis_set_reg_0/s_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m1_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m2_axis [get_bd_intf_pins axis_signal_gen_v6_0/s1_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m2_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m3_axis [get_bd_intf_pins axis_signal_gen_v6_1/s1_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m3_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m4_axis [get_bd_intf_pins axis_signal_gen_v6_2/s1_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m4_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m5_axis [get_bd_intf_pins axis_clk_cnvrt_gen_3/S_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/m5_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m6_axis [get_bd_intf_pins axis_clk_cnvrt_gen_4/S_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/m6_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m7_axis [get_bd_intf_pins axis_clk_cnvrt_gen_5/S_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/m7_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m8_axis [get_bd_intf_pins axis_clk_cnvrt_gen_6/S_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/m8_axis] - connect_bd_intf_net -intf_net dac0_clk_1 [get_bd_intf_ports dac0_clk] [get_bd_intf_pins usp_rf_data_converter_0/dac0_clk] - connect_bd_intf_net -intf_net dac1_clk_1 [get_bd_intf_ports dac1_clk] [get_bd_intf_pins usp_rf_data_converter_0/dac1_clk] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins axi_dma_tproc/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M01_AXI [get_bd_intf_pins axis_tproc64x32_x8_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M01_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M02_AXI [get_bd_intf_pins axis_signal_gen_v6_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M02_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M03_AXI [get_bd_intf_pins axis_signal_gen_v6_1/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M03_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M04_AXI [get_bd_intf_pins axis_signal_gen_v6_2/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M04_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M05_AXI [get_bd_intf_pins axis_signal_gen_v6_3/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M05_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M06_AXI [get_bd_intf_pins axi_dma_gen/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M06_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M07_AXI [get_bd_intf_pins axis_switch_gen/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M07_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M08_AXI [get_bd_intf_pins ps8_0_axi_periph/M08_AXI] [get_bd_intf_pins usp_rf_data_converter_0/s_axi] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M09_AXI [get_bd_intf_pins axis_avg_buffer_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M09_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M10_AXI [get_bd_intf_pins axis_avg_buffer_1/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M10_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M11_AXI [get_bd_intf_pins axis_signal_gen_v6_4/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M11_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M12_AXI [get_bd_intf_pins axis_signal_gen_v6_5/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M12_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M13_AXI [get_bd_intf_pins axi_bram_ctrl_0/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M13_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M14_AXI [get_bd_intf_pins axis_signal_gen_v6_6/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M14_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M15_AXI [get_bd_intf_pins axis_readout_v2_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M15_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M16_AXI [get_bd_intf_pins axis_readout_v2_1/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M16_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M17_AXI [get_bd_intf_pins axis_switch_avg/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M17_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M18_AXI [get_bd_intf_pins axis_switch_buf/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M18_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M19_AXI [get_bd_intf_pins axi_dma_avg/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M19_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M20_AXI [get_bd_intf_pins axi_dma_buf/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M20_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M21_AXI [get_bd_intf_pins attn_spi/AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M21_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M23_AXI [get_bd_intf_pins dac_bias_spi/AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M23_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M24_AXI [get_bd_intf_pins lo_spi/AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M24_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M25_AXI [get_bd_intf_pins ps8_0_axi_periph/M25_AXI] [get_bd_intf_pins psf_spi/AXI_LITE] - connect_bd_intf_net -intf_net sysref_in_1 [get_bd_intf_ports sysref_in] [get_bd_intf_pins usp_rf_data_converter_0/sysref_in] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_m00_axis [get_bd_intf_pins axis_register_slice_0/S_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/m00_axis] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_m02_axis [get_bd_intf_pins axis_register_slice_1/S_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/m02_axis] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout00 [get_bd_intf_ports vout0] [get_bd_intf_pins usp_rf_data_converter_0/vout00] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout01 [get_bd_intf_ports vout1] [get_bd_intf_pins usp_rf_data_converter_0/vout01] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout02 [get_bd_intf_ports vout2] [get_bd_intf_pins usp_rf_data_converter_0/vout02] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout10 [get_bd_intf_ports vout3] [get_bd_intf_pins usp_rf_data_converter_0/vout10] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout11 [get_bd_intf_ports vout4] [get_bd_intf_pins usp_rf_data_converter_0/vout11] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout12 [get_bd_intf_ports vout5] [get_bd_intf_pins usp_rf_data_converter_0/vout12] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout13 [get_bd_intf_ports vout6] [get_bd_intf_pins usp_rf_data_converter_0/vout13] - connect_bd_intf_net -intf_net vin0_1 [get_bd_intf_ports vin0] [get_bd_intf_pins usp_rf_data_converter_0/vin0_01] - connect_bd_intf_net -intf_net vin1_1 [get_bd_intf_ports vin1] [get_bd_intf_pins usp_rf_data_converter_0/vin0_23] - connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD] - - # Create port connections - connect_bd_net -net LO_MISO0_1 [get_bd_ports LO_MISO0] [get_bd_pins lo_spi_mux_0/sdo0_in] - connect_bd_net -net LO_MISO1_1 [get_bd_ports LO_MISO1] [get_bd_pins lo_spi_mux_0/sdo1_in] - connect_bd_net -net PMOD1_0_LS_1 [get_bd_ports PMOD1_0_LS] [get_bd_pins axis_tproc64x32_x8_0/start] - connect_bd_net -net axi_bram_ctrl_0_bram_doutb [get_bd_pins axi_bram_ctrl_0_bram/doutb] [get_bd_pins axis_tproc64x32_x8_0/pmem_do] - connect_bd_net -net axi_quad_spi_0_io0_o [get_bd_ports ATTN_SI] [get_bd_pins attn_spi/io0_o] - connect_bd_net -net axi_quad_spi_0_sck_o [get_bd_ports ATTN_CLK] [get_bd_pins attn_spi/sck_o] - connect_bd_net -net axi_quad_spi_0_ss_o [get_bd_ports ATTN_LE] [get_bd_pins attn_spi/ss_o] - connect_bd_net -net axis_set_reg_0_dout [get_bd_pins axis_set_reg_0/dout] [get_bd_pins vect2bits_16_0/din] - connect_bd_net -net axis_tproc64x32_x8_0_pmem_addr [get_bd_pins axi_bram_ctrl_0_bram/addrb] [get_bd_pins axis_tproc64x32_x8_0/pmem_addr] - connect_bd_net -net bias_constant_0_dout [get_bd_ports BIAS_CE] [get_bd_pins bias_constant_0/dout] - connect_bd_net -net bias_constant_1_dout [get_bd_ports BIAS_CLR] [get_bd_ports BIAS_RESET] [get_bd_pins bias_constant_1/dout] - connect_bd_net -net clk_adc0_x2_clk_out1 [get_bd_pins axis_avg_buffer_0/s_axis_aclk] [get_bd_pins axis_avg_buffer_1/s_axis_aclk] [get_bd_pins axis_readout_v2_0/aclk] [get_bd_pins axis_readout_v2_1/aclk] [get_bd_pins axis_register_slice_0/aclk] [get_bd_pins axis_register_slice_1/aclk] [get_bd_pins axis_terminator_0/s_axis_aclk] [get_bd_pins axis_terminator_1/s_axis_aclk] [get_bd_pins clk_adc0_x2/clk_out1] [get_bd_pins rst_adc0_x2/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/m0_axis_aclk] - connect_bd_net -net clk_adc0_x2_locked [get_bd_pins clk_adc0_x2/locked] [get_bd_pins rst_adc0_x2/dcm_locked] - connect_bd_net -net dac_bias_spi_io0_o [get_bd_ports BIAS_SDI] [get_bd_pins dac_bias_spi/io0_o] - connect_bd_net -net dac_bias_spi_sck_o [get_bd_ports BIAS_SCLK] [get_bd_pins dac_bias_spi/sck_o] - connect_bd_net -net dac_bias_spi_ss_o [get_bd_ports BIAS_S] [get_bd_pins dac_bias_spi/ss_o] - connect_bd_net -net dig_lconstant_1_dout [get_bd_ports RST_5VEN] [get_bd_pins dig_lconstant_1/dout] - connect_bd_net -net io1_i_0_1 [get_bd_ports SDO] [get_bd_pins psf_spi/io1_i] - connect_bd_net -net io1_i_0_2 [get_bd_ports BIAS_SDO] [get_bd_pins dac_bias_spi/io1_i] - connect_bd_net -net lo_spi_io0_o [get_bd_ports LO_MOSI] [get_bd_pins lo_spi/io0_o] - connect_bd_net -net lo_spi_mux_0_sdo_out [get_bd_pins lo_spi/io1_i] [get_bd_pins lo_spi_mux_0/sdo_out] - connect_bd_net -net lo_spi_mux_0_ss0_out [get_bd_ports LO_CS0] [get_bd_pins lo_spi_mux_0/ss0_out] - connect_bd_net -net lo_spi_mux_0_ss1_out [get_bd_ports LO_CS1] [get_bd_pins lo_spi_mux_0/ss1_out] - connect_bd_net -net lo_spi_sck_o [get_bd_ports LO_SCLK] [get_bd_pins lo_spi/sck_o] - connect_bd_net -net lo_spi_ss_o [get_bd_pins lo_spi/ss_o] [get_bd_pins lo_spi_mux_0/ss_in] - connect_bd_net -net psf_spi_io0_o [get_bd_ports SDI] [get_bd_pins psf_spi/io0_o] - connect_bd_net -net psf_spi_sck_o [get_bd_ports SCLK] [get_bd_pins psf_spi/sck_o] - connect_bd_net -net psf_spi_ss_o [get_bd_ports S] [get_bd_pins psf_spi/ss_o] - connect_bd_net -net rst_adc0_peripheral_reset [get_bd_pins clk_adc0_x2/reset] [get_bd_pins rst_adc0/peripheral_reset] - connect_bd_net -net rst_adc0_x2_peripheral_aresetn [get_bd_pins axis_avg_buffer_0/s_axis_aresetn] [get_bd_pins axis_avg_buffer_1/s_axis_aresetn] [get_bd_pins axis_readout_v2_0/aresetn] [get_bd_pins axis_readout_v2_1/aresetn] [get_bd_pins axis_register_slice_0/aresetn] [get_bd_pins axis_register_slice_1/aresetn] [get_bd_pins axis_terminator_0/s_axis_aresetn] [get_bd_pins axis_terminator_1/s_axis_aresetn] [get_bd_pins rst_adc0_x2/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/m0_axis_aresetn] - connect_bd_net -net rst_dac0_peripheral_aresetn [get_bd_pins axis_clk_cnvrt_avg_0/m_axis_aresetn] [get_bd_pins axis_clk_cnvrt_avg_1/m_axis_aresetn] [get_bd_pins axis_clk_cnvrt_gen_3/s_axis_aresetn] [get_bd_pins axis_clk_cnvrt_gen_4/s_axis_aresetn] [get_bd_pins axis_clk_cnvrt_gen_5/s_axis_aresetn] [get_bd_pins axis_clk_cnvrt_gen_6/s_axis_aresetn] [get_bd_pins axis_constant_0/m_axis_aresetn] [get_bd_pins axis_constant_1/m_axis_aresetn] [get_bd_pins axis_set_reg_0/s_axis_aresetn] [get_bd_pins axis_signal_gen_v6_0/aresetn] [get_bd_pins axis_signal_gen_v6_1/aresetn] [get_bd_pins axis_signal_gen_v6_2/aresetn] [get_bd_pins axis_tproc64x32_x8_0/aresetn] [get_bd_pins rst_dac0/peripheral_aresetn] [get_bd_pins system_ila_1/resetn] [get_bd_pins usp_rf_data_converter_0/s0_axis_aresetn] - connect_bd_net -net rst_dac1_peripheral_aresetn [get_bd_pins axis_clk_cnvrt_gen_3/m_axis_aresetn] [get_bd_pins axis_clk_cnvrt_gen_4/m_axis_aresetn] [get_bd_pins axis_clk_cnvrt_gen_5/m_axis_aresetn] [get_bd_pins axis_clk_cnvrt_gen_6/m_axis_aresetn] [get_bd_pins axis_signal_gen_v6_3/aresetn] [get_bd_pins axis_signal_gen_v6_4/aresetn] [get_bd_pins axis_signal_gen_v6_5/aresetn] [get_bd_pins axis_signal_gen_v6_6/aresetn] [get_bd_pins rst_dac1/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/s1_axis_aresetn] - connect_bd_net -net rst_ps8_0_99M_peripheral_aresetn [get_bd_pins attn_spi/s_axi_aresetn] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_dma_avg/axi_resetn] [get_bd_pins axi_dma_buf/axi_resetn] [get_bd_pins axi_dma_gen/axi_resetn] [get_bd_pins axi_dma_tproc/axi_resetn] [get_bd_pins axi_smc/aresetn] [get_bd_pins axis_avg_buffer_0/m_axis_aresetn] [get_bd_pins axis_avg_buffer_0/s_axi_aresetn] [get_bd_pins axis_avg_buffer_1/m_axis_aresetn] [get_bd_pins axis_avg_buffer_1/s_axi_aresetn] [get_bd_pins axis_clk_cnvrt_avg_0/s_axis_aresetn] [get_bd_pins axis_clk_cnvrt_avg_1/s_axis_aresetn] [get_bd_pins axis_readout_v2_0/s_axi_aresetn] [get_bd_pins axis_readout_v2_1/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_0/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_0/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_1/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_1/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_2/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_2/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_3/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_3/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_4/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_4/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_5/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_5/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_6/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_6/s_axi_aresetn] [get_bd_pins axis_switch_avg/aresetn] [get_bd_pins axis_switch_avg/s_axi_ctrl_aresetn] [get_bd_pins axis_switch_buf/aresetn] [get_bd_pins axis_switch_buf/s_axi_ctrl_aresetn] [get_bd_pins axis_switch_gen/aresetn] [get_bd_pins axis_switch_gen/s_axi_ctrl_aresetn] [get_bd_pins axis_tproc64x32_x8_0/m0_axis_aresetn] [get_bd_pins axis_tproc64x32_x8_0/s0_axis_aresetn] [get_bd_pins axis_tproc64x32_x8_0/s_axi_aresetn] [get_bd_pins dac_bias_spi/s_axi_aresetn] [get_bd_pins lo_spi/s_axi_aresetn] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/M01_ARESETN] [get_bd_pins ps8_0_axi_periph/M02_ARESETN] [get_bd_pins ps8_0_axi_periph/M03_ARESETN] [get_bd_pins ps8_0_axi_periph/M04_ARESETN] [get_bd_pins ps8_0_axi_periph/M05_ARESETN] [get_bd_pins ps8_0_axi_periph/M06_ARESETN] [get_bd_pins ps8_0_axi_periph/M07_ARESETN] [get_bd_pins ps8_0_axi_periph/M08_ARESETN] [get_bd_pins ps8_0_axi_periph/M09_ARESETN] [get_bd_pins ps8_0_axi_periph/M10_ARESETN] [get_bd_pins ps8_0_axi_periph/M11_ARESETN] [get_bd_pins ps8_0_axi_periph/M12_ARESETN] [get_bd_pins ps8_0_axi_periph/M13_ARESETN] [get_bd_pins ps8_0_axi_periph/M14_ARESETN] [get_bd_pins ps8_0_axi_periph/M15_ARESETN] [get_bd_pins ps8_0_axi_periph/M16_ARESETN] [get_bd_pins ps8_0_axi_periph/M17_ARESETN] [get_bd_pins ps8_0_axi_periph/M18_ARESETN] [get_bd_pins ps8_0_axi_periph/M19_ARESETN] [get_bd_pins ps8_0_axi_periph/M20_ARESETN] [get_bd_pins ps8_0_axi_periph/M21_ARESETN] [get_bd_pins ps8_0_axi_periph/M22_ARESETN] [get_bd_pins ps8_0_axi_periph/M23_ARESETN] [get_bd_pins ps8_0_axi_periph/M24_ARESETN] [get_bd_pins ps8_0_axi_periph/M25_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins psf_spi/s_axi_aresetn] [get_bd_pins rst_100/peripheral_aresetn] [get_bd_pins system_ila_0/resetn] [get_bd_pins usp_rf_data_converter_0/s_axi_aresetn] - connect_bd_net -net usp_rf_data_converter_0_clk_adc0 [get_bd_pins clk_adc0_x2/clk_in1] [get_bd_pins rst_adc0/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/clk_adc0] - connect_bd_net -net usp_rf_data_converter_0_clk_dac0 [get_bd_pins axi_bram_ctrl_0_bram/clkb] [get_bd_pins axis_clk_cnvrt_avg_0/m_axis_aclk] [get_bd_pins axis_clk_cnvrt_avg_1/m_axis_aclk] [get_bd_pins axis_clk_cnvrt_gen_3/s_axis_aclk] [get_bd_pins axis_clk_cnvrt_gen_4/s_axis_aclk] [get_bd_pins axis_clk_cnvrt_gen_5/s_axis_aclk] [get_bd_pins axis_clk_cnvrt_gen_6/s_axis_aclk] [get_bd_pins axis_constant_0/m_axis_aclk] [get_bd_pins axis_constant_1/m_axis_aclk] [get_bd_pins axis_set_reg_0/s_axis_aclk] [get_bd_pins axis_signal_gen_v6_0/aclk] [get_bd_pins axis_signal_gen_v6_1/aclk] [get_bd_pins axis_signal_gen_v6_2/aclk] [get_bd_pins axis_tproc64x32_x8_0/aclk] [get_bd_pins rst_dac0/slowest_sync_clk] [get_bd_pins system_ila_1/clk] [get_bd_pins usp_rf_data_converter_0/clk_dac0] [get_bd_pins usp_rf_data_converter_0/s0_axis_aclk] - connect_bd_net -net usp_rf_data_converter_0_clk_dac1 [get_bd_pins axis_clk_cnvrt_gen_3/m_axis_aclk] [get_bd_pins axis_clk_cnvrt_gen_4/m_axis_aclk] [get_bd_pins axis_clk_cnvrt_gen_5/m_axis_aclk] [get_bd_pins axis_clk_cnvrt_gen_6/m_axis_aclk] [get_bd_pins axis_signal_gen_v6_3/aclk] [get_bd_pins axis_signal_gen_v6_4/aclk] [get_bd_pins axis_signal_gen_v6_5/aclk] [get_bd_pins axis_signal_gen_v6_6/aclk] [get_bd_pins rst_dac1/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/clk_dac1] [get_bd_pins usp_rf_data_converter_0/s1_axis_aclk] - connect_bd_net -net vect2bits_16_0_dout0 [get_bd_ports PMOD0_0_LS] [get_bd_pins vect2bits_16_0/dout0] - connect_bd_net -net vect2bits_16_0_dout1 [get_bd_ports PMOD0_1_LS] [get_bd_pins vect2bits_16_0/dout1] - connect_bd_net -net vect2bits_16_0_dout2 [get_bd_ports PMOD0_2_LS] [get_bd_pins vect2bits_16_0/dout2] - connect_bd_net -net vect2bits_16_0_dout3 [get_bd_ports PMOD0_3_LS] [get_bd_pins vect2bits_16_0/dout3] - connect_bd_net -net vect2bits_16_0_dout4 [get_bd_ports PMOD0_4_LS] [get_bd_pins vect2bits_16_0/dout4] - connect_bd_net -net vect2bits_16_0_dout5 [get_bd_ports PMOD0_5_LS] [get_bd_pins vect2bits_16_0/dout5] - connect_bd_net -net vect2bits_16_0_dout6 [get_bd_ports PMOD0_6_LS] [get_bd_pins vect2bits_16_0/dout6] - connect_bd_net -net vect2bits_16_0_dout7 [get_bd_ports PMOD0_7_LS] [get_bd_pins vect2bits_16_0/dout7] - connect_bd_net -net vect2bits_16_0_dout14 [get_bd_pins axis_avg_buffer_0/trigger] [get_bd_pins system_ila_0/probe0] [get_bd_pins system_ila_1/probe0] [get_bd_pins vect2bits_16_0/dout14] - connect_bd_net -net vect2bits_16_0_dout15 [get_bd_pins axis_avg_buffer_1/trigger] [get_bd_pins vect2bits_16_0/dout15] - connect_bd_net -net xlconstant_0_dout [get_bd_pins axi_bram_ctrl_0_bram/dinb] [get_bd_pins xlconstant_0/dout] - connect_bd_net -net xlconstant_1_dout [get_bd_pins axi_bram_ctrl_0_bram/enb] [get_bd_pins xlconstant_1/dout] - connect_bd_net -net xlconstant_2_dout [get_bd_pins axi_bram_ctrl_0_bram/rstb] [get_bd_pins xlconstant_2/dout] - connect_bd_net -net xlconstant_3_dout [get_bd_pins axi_bram_ctrl_0_bram/web] [get_bd_pins xlconstant_3/dout] - connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins attn_spi/ext_spi_clk] [get_bd_pins attn_spi/s_axi_aclk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_dma_avg/m_axi_s2mm_aclk] [get_bd_pins axi_dma_avg/s_axi_lite_aclk] [get_bd_pins axi_dma_buf/m_axi_s2mm_aclk] [get_bd_pins axi_dma_buf/s_axi_lite_aclk] [get_bd_pins axi_dma_gen/m_axi_mm2s_aclk] [get_bd_pins axi_dma_gen/s_axi_lite_aclk] [get_bd_pins axi_dma_tproc/m_axi_mm2s_aclk] [get_bd_pins axi_dma_tproc/m_axi_s2mm_aclk] [get_bd_pins axi_dma_tproc/s_axi_lite_aclk] [get_bd_pins axi_smc/aclk] [get_bd_pins axis_avg_buffer_0/m_axis_aclk] [get_bd_pins axis_avg_buffer_0/s_axi_aclk] [get_bd_pins axis_avg_buffer_1/m_axis_aclk] [get_bd_pins axis_avg_buffer_1/s_axi_aclk] [get_bd_pins axis_clk_cnvrt_avg_0/s_axis_aclk] [get_bd_pins axis_clk_cnvrt_avg_1/s_axis_aclk] [get_bd_pins axis_readout_v2_0/s_axi_aclk] [get_bd_pins axis_readout_v2_1/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_0/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_0/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_1/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_1/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_2/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_2/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_3/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_3/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_4/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_4/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_5/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_5/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_6/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_6/s_axi_aclk] [get_bd_pins axis_switch_avg/aclk] [get_bd_pins axis_switch_avg/s_axi_ctrl_aclk] [get_bd_pins axis_switch_buf/aclk] [get_bd_pins axis_switch_buf/s_axi_ctrl_aclk] [get_bd_pins axis_switch_gen/aclk] [get_bd_pins axis_switch_gen/s_axi_ctrl_aclk] [get_bd_pins axis_tproc64x32_x8_0/m0_axis_aclk] [get_bd_pins axis_tproc64x32_x8_0/s0_axis_aclk] [get_bd_pins axis_tproc64x32_x8_0/s_axi_aclk] [get_bd_pins dac_bias_spi/ext_spi_clk] [get_bd_pins dac_bias_spi/s_axi_aclk] [get_bd_pins lo_spi/ext_spi_clk] [get_bd_pins lo_spi/s_axi_aclk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/M01_ACLK] [get_bd_pins ps8_0_axi_periph/M02_ACLK] [get_bd_pins ps8_0_axi_periph/M03_ACLK] [get_bd_pins ps8_0_axi_periph/M04_ACLK] [get_bd_pins ps8_0_axi_periph/M05_ACLK] [get_bd_pins ps8_0_axi_periph/M06_ACLK] [get_bd_pins ps8_0_axi_periph/M07_ACLK] [get_bd_pins ps8_0_axi_periph/M08_ACLK] [get_bd_pins ps8_0_axi_periph/M09_ACLK] [get_bd_pins ps8_0_axi_periph/M10_ACLK] [get_bd_pins ps8_0_axi_periph/M11_ACLK] [get_bd_pins ps8_0_axi_periph/M12_ACLK] [get_bd_pins ps8_0_axi_periph/M13_ACLK] [get_bd_pins ps8_0_axi_periph/M14_ACLK] [get_bd_pins ps8_0_axi_periph/M15_ACLK] [get_bd_pins ps8_0_axi_periph/M16_ACLK] [get_bd_pins ps8_0_axi_periph/M17_ACLK] [get_bd_pins ps8_0_axi_periph/M18_ACLK] [get_bd_pins ps8_0_axi_periph/M19_ACLK] [get_bd_pins ps8_0_axi_periph/M20_ACLK] [get_bd_pins ps8_0_axi_periph/M21_ACLK] [get_bd_pins ps8_0_axi_periph/M22_ACLK] [get_bd_pins ps8_0_axi_periph/M23_ACLK] [get_bd_pins ps8_0_axi_periph/M24_ACLK] [get_bd_pins ps8_0_axi_periph/M25_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins psf_spi/ext_spi_clk] [get_bd_pins psf_spi/s_axi_aclk] [get_bd_pins rst_100/slowest_sync_clk] [get_bd_pins system_ila_0/clk] [get_bd_pins usp_rf_data_converter_0/s_axi_aclk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins zynq_ultra_ps_e_0/saxihpc0_fpd_aclk] - connect_bd_net -net zynq_ultra_ps_e_0_pl_clk1 [get_bd_ports PWR_SYNC] [get_bd_pins zynq_ultra_ps_e_0/pl_clk1] - connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins rst_100/ext_reset_in] [get_bd_pins rst_adc0/ext_reset_in] [get_bd_pins rst_adc0_x2/ext_reset_in] [get_bd_pins rst_dac0/ext_reset_in] [get_bd_pins rst_dac1/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] - - # Create address segments - assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force - assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] -force - assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force - assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] -force - assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force - assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] -force - assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force - assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force - assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] -force - assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] -force - assign_bd_address -offset 0xA0010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs attn_spi/AXI_LITE/Reg] -force - assign_bd_address -offset 0xA0000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force - assign_bd_address -offset 0xA0040000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_avg/S_AXI_LITE/Reg] -force - assign_bd_address -offset 0xA0041000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_buf/S_AXI_LITE/Reg] -force - assign_bd_address -offset 0xA0042000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_gen/S_AXI_LITE/Reg] -force - assign_bd_address -offset 0xA0043000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_tproc/S_AXI_LITE/Reg] -force - assign_bd_address -offset 0xA0044000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_avg_buffer_0/s_axi/reg0] -force - assign_bd_address -offset 0xA0045000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_avg_buffer_1/s_axi/reg0] -force - assign_bd_address -offset 0xA0046000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_readout_v2_0/s_axi/reg0] -force - assign_bd_address -offset 0xA0047000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_readout_v2_1/s_axi/reg0] -force - assign_bd_address -offset 0xA0048000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_0/s_axi/reg0] -force - assign_bd_address -offset 0xA0049000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_1/s_axi/reg0] -force - assign_bd_address -offset 0xA004A000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_2/s_axi/reg0] -force - assign_bd_address -offset 0xA004B000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_3/s_axi/reg0] -force - assign_bd_address -offset 0xA004C000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_4/s_axi/reg0] -force - assign_bd_address -offset 0xA004D000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_5/s_axi/reg0] -force - assign_bd_address -offset 0xA004E000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_6/s_axi/reg0] -force - assign_bd_address -offset 0xA004F000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_avg/S_AXI_CTRL/Reg] -force - assign_bd_address -offset 0xA0050000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_buf/S_AXI_CTRL/Reg] -force - assign_bd_address -offset 0xA0051000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_gen/S_AXI_CTRL/Reg] -force - assign_bd_address -offset 0x000400000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_tproc64x32_x8_0/s_axi/reg0] -force - assign_bd_address -offset 0xA0030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs dac_bias_spi/AXI_LITE/Reg] -force - assign_bd_address -offset 0xA0060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs lo_spi/AXI_LITE/Reg] -force - assign_bd_address -offset 0xA0070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs psf_spi/AXI_LITE/Reg] -force - assign_bd_address -offset 0xA0080000 -range 0x00040000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs usp_rf_data_converter_0/s_axi/Reg] -force - - # Perform GUI Layout - regenerate_bd_layout -layout_string { - "ActiveEmotionalView":"Default View", - "Default View_ScaleFactor":"0.397519", - "Default View_TopLeft":"-1892,0", - "ExpandedHierarchyInLayout":"", - "guistr":"# # String gsaved with Nlview 7.0r4 2019-12-20 bk=1.5203 VDI=41 GEI=36 GUI=JA:10.0 TLS -# -string -flagsOSRD -preplace port adc0_clk -pg 1 -lvl 9 -x 4020 -y 2430 -defaultsOSRD -right -preplace port dac0_clk -pg 1 -lvl 9 -x 4020 -y 2470 -defaultsOSRD -right -preplace port dac1_clk -pg 1 -lvl 9 -x 4020 -y 2450 -defaultsOSRD -right -preplace port sysref_in -pg 1 -lvl 9 -x 4020 -y 2410 -defaultsOSRD -right -preplace port vin0 -pg 1 -lvl 9 -x 4020 -y 2370 -defaultsOSRD -right -preplace port vin1 -pg 1 -lvl 9 -x 4020 -y 2390 -defaultsOSRD -right -preplace port vout0 -pg 1 -lvl 9 -x 4020 -y 2050 -defaultsOSRD -preplace port vout1 -pg 1 -lvl 9 -x 4020 -y 2070 -defaultsOSRD -preplace port vout2 -pg 1 -lvl 9 -x 4020 -y 2090 -defaultsOSRD -preplace port vout3 -pg 1 -lvl 9 -x 4020 -y 2110 -defaultsOSRD -preplace port vout4 -pg 1 -lvl 9 -x 4020 -y 2130 -defaultsOSRD -preplace port vout5 -pg 1 -lvl 9 -x 4020 -y 2150 -defaultsOSRD -preplace port vout6 -pg 1 -lvl 9 -x 4020 -y 2170 -defaultsOSRD -preplace port ATTN_CLK -pg 1 -lvl 9 -x 4020 -y 1320 -defaultsOSRD -preplace port ATTN_SI -pg 1 -lvl 9 -x 4020 -y 1300 -defaultsOSRD -preplace port BIAS_SCLK -pg 1 -lvl 9 -x 4020 -y 870 -defaultsOSRD -preplace port BIAS_SDI -pg 1 -lvl 9 -x 4020 -y 830 -defaultsOSRD -preplace port BIAS_SDO -pg 1 -lvl 9 -x 4020 -y 850 -defaultsOSRD -right -preplace port LO_CS0 -pg 1 -lvl 9 -x 4020 -y 1000 -defaultsOSRD -preplace port LO_CS1 -pg 1 -lvl 9 -x 4020 -y 810 -defaultsOSRD -preplace port LO_MISO0 -pg 1 -lvl 9 -x 4020 -y 960 -defaultsOSRD -right -preplace port LO_MISO1 -pg 1 -lvl 9 -x 4020 -y 980 -defaultsOSRD -right -preplace port LO_MOSI -pg 1 -lvl 9 -x 4020 -y 910 -defaultsOSRD -preplace port LO_SCLK -pg 1 -lvl 9 -x 4020 -y 940 -defaultsOSRD -preplace port PMOD0_0_LS -pg 1 -lvl 9 -x 4020 -y 1520 -defaultsOSRD -preplace port PMOD0_1_LS -pg 1 -lvl 9 -x 4020 -y 1540 -defaultsOSRD -preplace port PMOD0_2_LS -pg 1 -lvl 9 -x 4020 -y 1560 -defaultsOSRD -preplace port PMOD0_3_LS -pg 1 -lvl 9 -x 4020 -y 1580 -defaultsOSRD -preplace port PMOD0_4_LS -pg 1 -lvl 9 -x 4020 -y 1600 -defaultsOSRD -preplace port PMOD0_5_LS -pg 1 -lvl 9 -x 4020 -y 1620 -defaultsOSRD -preplace port PMOD0_6_LS -pg 1 -lvl 9 -x 4020 -y 1640 -defaultsOSRD -preplace port PMOD0_7_LS -pg 1 -lvl 9 -x 4020 -y 1660 -defaultsOSRD -preplace port PMOD1_0_LS -pg 1 -lvl 0 -x -30 -y 2030 -defaultsOSRD -preplace port SCLK -pg 1 -lvl 9 -x 4020 -y 1140 -defaultsOSRD -preplace port SDI -pg 1 -lvl 9 -x 4020 -y 1100 -defaultsOSRD -preplace port SDO -pg 1 -lvl 9 -x 4020 -y 1120 -defaultsOSRD -right -preplace portBus ATTN_LE -pg 1 -lvl 9 -x 4020 -y 1340 -defaultsOSRD -preplace portBus BIAS_CE -pg 1 -lvl 9 -x 4020 -y 560 -defaultsOSRD -preplace portBus BIAS_CLR -pg 1 -lvl 9 -x 4020 -y 650 -defaultsOSRD -preplace portBus BIAS_RESET -pg 1 -lvl 9 -x 4020 -y 670 -defaultsOSRD -preplace portBus BIAS_S -pg 1 -lvl 9 -x 4020 -y 890 -defaultsOSRD -preplace portBus PWR_SYNC -pg 1 -lvl 9 -x 4020 -y 1410 -defaultsOSRD -preplace portBus RST_5VEN -pg 1 -lvl 9 -x 4020 -y 450 -defaultsOSRD -preplace portBus S -pg 1 -lvl 9 -x 4020 -y 1160 -defaultsOSRD -preplace inst attn_spi -pg 1 -lvl 6 -x 2910 -y 1320 -defaultsOSRD -preplace inst axi_bram_ctrl_0 -pg 1 -lvl 1 -x 150 -y 2110 -defaultsOSRD -preplace inst axi_bram_ctrl_0_bram -pg 1 -lvl 2 -x 580 -y 2300 -defaultsOSRD -preplace inst axi_dma_avg -pg 1 -lvl 2 -x 580 -y 710 -defaultsOSRD -preplace inst axi_dma_buf -pg 1 -lvl 2 -x 580 -y 890 -defaultsOSRD -resize 320 156 -preplace inst axi_dma_gen -pg 1 -lvl 2 -x 580 -y 1060 -defaultsOSRD -preplace inst axi_dma_tproc -pg 1 -lvl 2 -x 580 -y 1250 -defaultsOSRD -preplace inst axi_smc -pg 1 -lvl 2 -x 580 -y 490 -defaultsOSRD -preplace inst axis_avg_buffer_0 -pg 1 -lvl 6 -x 2910 -y 3490 -defaultsOSRD -preplace inst axis_avg_buffer_1 -pg 1 -lvl 6 -x 2910 -y 3890 -defaultsOSRD -resize 220 236 -preplace inst axis_clk_cnvrt_avg_0 -pg 1 -lvl 7 -x 3360 -y 2400 -defaultsOSRD -preplace inst axis_clk_cnvrt_avg_1 -pg 1 -lvl 7 -x 3360 -y 3020 -defaultsOSRD -resize 220 156 -preplace inst axis_clk_cnvrt_gen_3 -pg 1 -lvl 3 -x 1240 -y 2430 -defaultsOSRD -preplace inst axis_clk_cnvrt_gen_4 -pg 1 -lvl 3 -x 1240 -y 2610 -defaultsOSRD -resize 220 156 -preplace inst axis_clk_cnvrt_gen_5 -pg 1 -lvl 3 -x 1240 -y 2790 -defaultsOSRD -resize 220 156 -preplace inst axis_clk_cnvrt_gen_6 -pg 1 -lvl 3 -x 1240 -y 2970 -defaultsOSRD -resize 220 156 -preplace inst axis_constant_0 -pg 1 -lvl 1 -x 150 -y 1840 -defaultsOSRD -preplace inst axis_constant_1 -pg 1 -lvl 1 -x 150 -y 1960 -defaultsOSRD -resize 220 96 -preplace inst axis_readout_v2_0 -pg 1 -lvl 5 -x 2280 -y 3550 -defaultsOSRD -preplace inst axis_readout_v2_1 -pg 1 -lvl 5 -x 2280 -y 3800 -defaultsOSRD -preplace inst axis_register_slice_0 -pg 1 -lvl 4 -x 1780 -y 3500 -defaultsOSRD -preplace inst axis_register_slice_1 -pg 1 -lvl 4 -x 1780 -y 3660 -defaultsOSRD -resize 180 116 -preplace inst axis_set_reg_0 -pg 1 -lvl 5 -x 2280 -y 1540 -defaultsOSRD -preplace inst axis_signal_gen_v6_0 -pg 1 -lvl 5 -x 2280 -y 1740 -defaultsOSRD -preplace inst axis_signal_gen_v6_1 -pg 1 -lvl 5 -x 2280 -y 2000 -defaultsOSRD -resize 220 236 -preplace inst axis_signal_gen_v6_2 -pg 1 -lvl 5 -x 2280 -y 2260 -defaultsOSRD -resize 220 236 -preplace inst axis_signal_gen_v6_3 -pg 1 -lvl 5 -x 2280 -y 2520 -defaultsOSRD -resize 220 236 -preplace inst axis_signal_gen_v6_4 -pg 1 -lvl 5 -x 2280 -y 2780 -defaultsOSRD -resize 220 236 -preplace inst axis_signal_gen_v6_5 -pg 1 -lvl 5 -x 2280 -y 3040 -defaultsOSRD -resize 220 236 -preplace inst axis_signal_gen_v6_6 -pg 1 -lvl 5 -x 2280 -y 3300 -defaultsOSRD -resize 220 236 -preplace inst axis_switch_avg -pg 1 -lvl 7 -x 3360 -y 2600 -defaultsOSRD -preplace inst axis_switch_buf -pg 1 -lvl 7 -x 3360 -y 2820 -defaultsOSRD -resize 240 196 -preplace inst axis_switch_gen -pg 1 -lvl 3 -x 1240 -y 2200 -defaultsOSRD -preplace inst axis_terminator_0 -pg 1 -lvl 6 -x 2910 -y 3240 -defaultsOSRD -preplace inst axis_terminator_1 -pg 1 -lvl 6 -x 2910 -y 3690 -defaultsOSRD -resize 160 116 -preplace inst axis_tproc64x32_x8_0 -pg 1 -lvl 2 -x 580 -y 1970 -defaultsOSRD -preplace inst bias_constant_0 -pg 1 -lvl 8 -x 3780 -y 560 -defaultsOSRD -preplace inst bias_constant_1 -pg 1 -lvl 8 -x 3780 -y 660 -defaultsOSRD -preplace inst clk_adc0_x2 -pg 1 -lvl 3 -x 1240 -y 1870 -defaultsOSRD -preplace inst dac_bias_spi -pg 1 -lvl 6 -x 2910 -y 730 -defaultsOSRD -preplace inst dig_lconstant_1 -pg 1 -lvl 8 -x 3780 -y 450 -defaultsOSRD -preplace inst lo_spi -pg 1 -lvl 6 -x 2910 -y 930 -defaultsOSRD -preplace inst lo_spi_mux_0 -pg 1 -lvl 7 -x 3360 -y 980 -defaultsOSRD -preplace inst ps8_0_axi_periph -pg 1 -lvl 5 -x 2280 -y 620 -defaultsOSRD -preplace inst psf_spi -pg 1 -lvl 6 -x 2910 -y 1130 -defaultsOSRD -preplace inst rst_100 -pg 1 -lvl 3 -x 1240 -y 560 -defaultsOSRD -preplace inst rst_adc0 -pg 1 -lvl 3 -x 1240 -y 740 -defaultsOSRD -resize 320 156 -preplace inst rst_adc0_x2 -pg 1 -lvl 3 -x 1240 -y 920 -defaultsOSRD -resize 320 156 -preplace inst rst_dac0 -pg 1 -lvl 3 -x 1240 -y 1100 -defaultsOSRD -resize 320 156 -preplace inst rst_dac1 -pg 1 -lvl 3 -x 1240 -y 1280 -defaultsOSRD -resize 320 156 -preplace inst system_ila_0 -pg 1 -lvl 7 -x 3360 -y 3200 -defaultsOSRD -resize 157 152 -preplace inst system_ila_1 -pg 1 -lvl 7 -x 3360 -y 3380 -defaultsOSRD -resize 157 152 -preplace inst usp_rf_data_converter_0 -pg 1 -lvl 8 -x 3780 -y 2130 -defaultsOSRD -preplace inst vect2bits_16_0 -pg 1 -lvl 8 -x 3780 -y 1670 -defaultsOSRD -preplace inst xlconstant_0 -pg 1 -lvl 1 -x 150 -y 2230 -defaultsOSRD -preplace inst xlconstant_1 -pg 1 -lvl 1 -x 150 -y 2340 -defaultsOSRD -resize 140 88 -preplace inst xlconstant_2 -pg 1 -lvl 1 -x 150 -y 2450 -defaultsOSRD -resize 140 88 -preplace inst xlconstant_3 -pg 1 -lvl 1 -x 150 -y 2560 -defaultsOSRD -resize 140 88 -preplace inst zynq_ultra_ps_e_0 -pg 1 -lvl 3 -x 1240 -y 360 -defaultsOSRD -preplace netloc PMOD1_0_LS_1 1 0 2 N 2030 320J -preplace netloc LO_MISO0_1 1 6 3 3160J 870 3500 950 3940 -preplace netloc LO_MISO1_1 1 6 3 3120J 860 3520 870 3950 -preplace netloc axi_bram_ctrl_0_bram_doutb 1 1 1 390 2120n -preplace netloc axi_quad_spi_0_io0_o 1 6 3 NJ 1300 NJ 1300 NJ -preplace netloc axi_quad_spi_0_sck_o 1 6 3 NJ 1320 NJ 1320 NJ -preplace netloc axi_quad_spi_0_ss_o 1 6 3 NJ 1340 NJ 1340 NJ -preplace netloc axis_set_reg_0_dout 1 5 3 NJ 1540 NJ 1540 3620 -preplace netloc axis_tproc64x32_x8_0_pmem_addr 1 1 2 400 2440 760 -preplace netloc bias_constant_0_dout 1 8 1 NJ 560 -preplace netloc bias_constant_1_dout 1 8 1 4000J 650n -preplace netloc clk_adc0_x2_clk_out1 1 2 6 930 1800 1620 3580 1900 3910 2710 2240 N 2240 3570 -preplace netloc clk_adc0_x2_locked 1 2 2 920 260 1560 -preplace netloc dac_bias_spi_io0_o 1 6 3 3120J 820 NJ 820 4000J -preplace netloc dac_bias_spi_sck_o 1 6 3 3090J 830 NJ 830 3990J -preplace netloc dac_bias_spi_ss_o 1 6 3 3040J 840 NJ 840 3970J -preplace netloc dig_lconstant_1_dout 1 8 1 NJ 450 -preplace netloc io1_i_0_1 1 6 3 N 1120 N 1120 N -preplace netloc io1_i_0_2 1 6 3 3080 850 3530 860 3950 -preplace netloc lo_spi_io0_o 1 6 3 3040J 880 3630J 910 NJ -preplace netloc lo_spi_mux_0_sdo_out 1 6 2 3060J 900 3520 -preplace netloc lo_spi_mux_0_ss0_out 1 7 2 NJ 960 3920J -preplace netloc lo_spi_mux_0_ss1_out 1 7 2 3610J 850 3920J -preplace netloc lo_spi_sck_o 1 6 3 3050J 890 3620J 940 NJ -preplace netloc lo_spi_ss_o 1 6 1 N 960 -preplace netloc psf_spi_io0_o 1 6 3 NJ 1100 NJ 1100 NJ -preplace netloc psf_spi_sck_o 1 6 3 NJ 1140 NJ 1140 NJ -preplace netloc psf_spi_ss_o 1 6 3 NJ 1160 NJ 1160 NJ -preplace netloc rst_adc0_peripheral_reset 1 2 2 900 460 1550 -preplace netloc rst_adc0_x2_peripheral_aresetn 1 3 5 1630 3740 2020 3920 2750 2250 NJ 2250 3580J -preplace netloc rst_dac0_peripheral_aresetn 1 0 8 0 1760 330 1760 800J 1760 1590 1560 2000 3660 2720J 3340 3160J 2280 N -preplace netloc rst_dac1_peripheral_aresetn 1 2 6 930 2320 1600 2320 1930 3670 2690J 2260 NJ 2260 3560J -preplace netloc rst_ps8_0_99M_peripheral_aresetn 1 0 8 10 2630 310 330 850 230 1580J 330 1980 3930 2660 2270 3040 2220 N -preplace netloc usp_rf_data_converter_0_clk_adc0 1 2 7 910 1460 1650J 1450 N 1450 NJ 1450 NJ 1450 NJ 1450 3950 -preplace netloc usp_rf_data_converter_0_clk_dac0 1 0 9 10 1770 340 1750 820 1770 NJ 1770 2040 3680 2730J 3320 3170J 2300 3580J 2440 3930 -preplace netloc usp_rf_data_converter_0_clk_dac1 1 2 7 880 2330 NJ 2330 1910 3690 2670J 2280 3050J 2270 3550J 2460 3920 -preplace netloc vect2bits_16_0_dout0 1 8 1 N 1520 -preplace netloc vect2bits_16_0_dout1 1 8 1 N 1540 -preplace netloc vect2bits_16_0_dout2 1 8 1 N 1560 -preplace netloc vect2bits_16_0_dout3 1 8 1 N 1580 -preplace netloc vect2bits_16_0_dout4 1 8 1 N 1600 -preplace netloc vect2bits_16_0_dout5 1 8 1 N 1620 -preplace netloc vect2bits_16_0_dout6 1 8 1 N 1640 -preplace netloc vect2bits_16_0_dout7 1 8 1 N 1660 -preplace netloc vect2bits_16_0_dout14 1 5 4 2780 3330 3200J 3490 N 3490 3970 -preplace netloc vect2bits_16_0_dout15 1 5 4 2770 2290 NJ 2290 3540J 2480 3940 -preplace netloc xlconstant_0_dout 1 1 1 290 2230n -preplace netloc xlconstant_1_dout 1 1 1 N 2340 -preplace netloc xlconstant_2_dout 1 1 1 320 2360n -preplace netloc xlconstant_3_dout 1 1 1 330 2380n -preplace netloc zynq_ultra_ps_e_0_pl_clk0 1 0 8 0 2640 300 320 870 240 1570 340 1950 3940 2650 2200 3120 2200 N -preplace netloc zynq_ultra_ps_e_0_pl_clk1 1 3 6 NJ 400 1920J 1320 2620J 1440 3040J 1410 NJ 1410 NJ -preplace netloc zynq_ultra_ps_e_0_pl_resetn0 1 2 2 890 250 1550 -preplace netloc usp_rf_data_converter_0_vout12 1 8 1 N 2150 -preplace netloc usp_rf_data_converter_0_vout10 1 8 1 N 2110 -preplace netloc ps8_0_axi_periph_M24_AXI 1 5 1 2780 850n -preplace netloc sysref_in_1 1 7 2 3640 2420 4000 -preplace netloc ps8_0_axi_periph_M17_AXI 1 5 2 2590J 610 3100 -preplace netloc ps8_0_axi_periph_M13_AXI 1 0 6 -10 1470 N 1470 NJ 1470 1640J 1420 N 1420 2570 -preplace netloc ps8_0_axi_periph_M09_AXI 1 5 1 2640 550n -preplace netloc ps8_0_axi_periph_M05_AXI 1 4 2 2090 1300 2530 -preplace netloc ps8_0_axi_periph_M03_AXI 1 4 2 2070 1250 2450 -preplace netloc ps8_0_axi_periph_M07_AXI 1 2 4 920 1480 NJ 1480 2040 1410 2580 -preplace netloc ps8_0_axi_periph_M11_AXI 1 4 2 2100 1330 2490 -preplace netloc ps8_0_axi_periph_M15_AXI 1 4 2 2120 1360 2470 -preplace netloc usp_rf_data_converter_0_vout01 1 8 1 N 2070 -preplace netloc usp_rf_data_converter_0_m02_axis 1 3 6 1660 1430 NJ 1430 NJ 1430 NJ 1430 NJ 1430 3960 -preplace netloc ps8_0_axi_periph_M21_AXI 1 5 1 2770 790n -preplace netloc ps8_0_axi_periph_M19_AXI 1 1 5 320 1440 NJ 1440 NJ 1440 N 1440 2500 -preplace netloc ps8_0_axi_periph_M14_AXI 1 4 2 2130 1370 2510 -preplace netloc ps8_0_axi_periph_M18_AXI 1 5 2 2610J 620 3070 -preplace netloc ps8_0_axi_periph_M20_AXI 1 1 5 330 1450 NJ 1450 1610J 1370 1910 1280 2430 -preplace netloc ps8_0_axi_periph_M23_AXI 1 5 1 2620 700n -preplace netloc usp_rf_data_converter_0_m00_axis 1 3 6 1670 1460 NJ 1460 NJ 1460 NJ 1460 NJ 1460 3920 -preplace netloc ps8_0_axi_periph_M12_AXI 1 4 2 2110 1340 2480 -preplace netloc ps8_0_axi_periph_M04_AXI 1 4 2 2080 1290 2540 -preplace netloc ps8_0_axi_periph_M06_AXI 1 1 5 380 1430 N 1430 1620J 1410 1970 1310 2520 -preplace netloc ps8_0_axi_periph_M16_AXI 1 4 2 2050 1350 2440 -preplace netloc usp_rf_data_converter_0_vout11 1 8 1 N 2130 -preplace netloc usp_rf_data_converter_0_vout00 1 8 1 N 2050 -preplace netloc ps8_0_axi_periph_M25_AXI 1 5 1 2750 870n -preplace netloc ps8_0_axi_periph_M10_AXI 1 5 1 2630 570n -preplace netloc ps8_0_axi_periph_M08_AXI 1 5 3 N 530 3160 810 3640J -preplace netloc usp_rf_data_converter_0_vout02 1 8 1 N 2090 -preplace netloc usp_rf_data_converter_0_vout13 1 8 1 N 2170 -preplace netloc axis_tproc64x32_x8_0_m1_axis 1 2 3 810 1730 1650 1550 2000 -preplace netloc axis_signal_gen_v6_5_m_axis 1 5 3 2580 2040 N 2040 NJ -preplace netloc axis_signal_gen_v6_1_m_axis 1 5 3 2440 1960 N 1960 NJ -preplace netloc axis_switch_0_M02_AXIS 1 3 2 N 2180 N -preplace netloc axis_switch_0_M04_AXIS 1 3 2 N 2220 2010 -preplace netloc axis_tproc64x32_x8_0_m3_axis 1 2 3 NJ 1940 N 1940 N -preplace netloc axis_tproc64x32_x8_0_m7_axis 1 2 1 780 2020n -preplace netloc axis_switch_buf_M00_AXIS 1 1 7 390 1400 NJ 1400 NJ 1400 N 1400 2600J 1420 NJ 1420 3530 -preplace netloc axis_signal_gen_v6_3_m_axis 1 5 3 2510 2000 N 2000 NJ -preplace netloc axis_constant_1_m_axis 1 1 1 290 1900n -preplace netloc axis_readout_v2_0_m1_axis 1 5 1 2740 3410n -preplace netloc axis_readout_v2_1_m1_axis 1 5 1 N 3810 -preplace netloc axis_switch_0_M00_AXIS 1 3 2 1640 1780 1970 -preplace netloc axis_switch_0_M06_AXIS 1 3 2 N 2260 1970 -preplace netloc axis_tproc64x32_x8_0_m5_axis 1 2 1 810 1980n -preplace netloc ps8_0_axi_periph_M02_AXI 1 4 2 2060 1240 2460 -preplace netloc ps8_0_axi_periph_M01_AXI 1 1 5 370 1420 N 1420 1580J 1360 1900 1270 2550 -preplace netloc axis_register_slice_1_M_AXIS 1 4 1 1890 3660n -preplace netloc dac1_clk_1 1 7 2 3610J 2450 N -preplace netloc axis_tproc64x32_x8_0_m4_axis 1 2 3 NJ 1960 N 1960 2030 -preplace netloc axis_switch_0_M05_AXIS 1 3 2 N 2240 1920 -preplace netloc axis_switch_0_M01_AXIS 1 3 2 1650 1920 N -preplace netloc axis_signal_gen_v6_4_m_axis 1 5 3 2550 2020 N 2020 NJ -preplace netloc axis_readout_v2_1_m0_axis 1 5 1 2760 3670n -preplace netloc axis_readout_v2_0_m0_axis 1 5 1 2680 3220n -preplace netloc axis_signal_gen_v6_0_m_axis 1 5 3 N 1740 3040 1940 NJ -preplace netloc axis_signal_gen_v6_6_m_axis 1 5 3 2610 2060 N 2060 NJ -preplace netloc axis_switch_0_M03_AXIS 1 3 2 N 2200 2020 -preplace netloc axis_tproc64x32_x8_0_m8_axis 1 2 1 770 2040n -preplace netloc axis_tproc64x32_x8_0_m2_axis 1 2 3 830J 1790 N 1790 2030 -preplace netloc axis_signal_gen_v6_2_m_axis 1 5 3 2470 1980 N 1980 NJ -preplace netloc axis_register_slice_0_M_AXIS 1 4 1 N 3500 -preplace netloc axis_tproc64x32_x8_0_m0_axis 1 1 2 340 1460 760 -preplace netloc axis_switch_avg_M00_AXIS 1 1 7 370 1390 NJ 1390 NJ 1390 N 1390 2590J 1480 NJ 1480 3500 -preplace netloc axis_tproc64x32_x8_0_m6_axis 1 2 1 790 2000n -preplace netloc axis_avg_buffer_0_m2_axis 1 6 1 3130 2360n -preplace netloc axi_dma_avg_M_AXI_S2MM 1 1 2 320 350 780 -preplace netloc axi_dma_1_M_AXIS_MM2S 1 2 1 840 1050n -preplace netloc axi_bram_ctrl_0_BRAM_PORTA 1 1 1 290 2110n -preplace netloc axi_dma_0_M_AXI_MM2S 1 1 2 400 360 790 -preplace netloc axis_avg_buffer_0_m1_axis 1 6 1 3140 2760n -preplace netloc axi_dma_0_M_AXI_S2MM 1 1 2 380 340 800J -preplace netloc axis_avg_buffer_1_m1_axis 1 6 1 3180 2780n -preplace netloc axi_dma_0_M_AXIS_MM2S 1 1 2 350 1370 760 -preplace netloc axis_avg_buffer_1_m2_axis 1 6 1 3190 2980n -preplace netloc axis_avg_buffer_0_m0_axis 1 6 1 3110 2540n -preplace netloc axis_clk_cnvrt_avg_1_M_AXIS 1 1 7 360 1380 NJ 1380 NJ 1380 N 1380 2610J 1470 NJ 1470 3520 -preplace netloc ps8_0_axi_periph_M00_AXI 1 1 5 400 1410 N 1410 1570J 1350 1890 1260 2560J -preplace netloc axi_dma_1_M_AXI_MM2S 1 1 2 390 370 770J -preplace netloc dac0_clk_1 1 7 2 3590J 2470 N -preplace netloc vin1_1 1 7 2 3630J 2410 3990 -preplace netloc vin0_1 1 7 2 3620J 2400 3980 -preplace netloc zynq_ultra_ps_e_0_M_AXI_HPM0_FPD 1 3 2 NJ 320 1890 -preplace netloc axis_clock_converter_5_M_AXIS 1 3 2 N 2790 1940 -preplace netloc axis_constant_0_m_axis 1 1 1 320 1840n -preplace netloc axis_clock_converter_6_M_AXIS 1 3 2 N 2970 1920 -preplace netloc axis_clock_converter_3_M_AXIS 1 3 2 N 2430 1990 -preplace netloc axis_clock_converter_4_M_AXIS 1 3 2 N 2610 1960 -preplace netloc axis_clk_cnvrt_avg_0_M_AXIS 1 1 7 350 3420 NJ 3420 NJ 3420 1890 3440 2700J 3350 3060J 3480 3510 -preplace netloc adc0_clk_1 1 7 2 3600J 2430 N -preplace netloc axi_smc_M00_AXI 1 2 1 860 330n -preplace netloc axis_avg_buffer_1_m0_axis 1 6 1 3150 2560n -preplace netloc axi_dma_buf_M_AXI_S2MM 1 1 2 400 610 760 -levelinfo -pg 1 -30 150 580 1240 1780 2280 2910 3360 3780 4020 -pagesize -pg 1 -db -bbox -sgen -180 0 4190 4030 -" -} - - # Restore current instance - current_bd_instance $oldCurInst - - validate_bd_design - save_bd_design -} -# End of create_root_design() - - -################################################################## -# MAIN FLOW -################################################################## - -create_root_design "" - - diff --git a/qick/firmware/bd/bd_111_rfbv2_2020-2.tcl b/qick/firmware/bd/bd_111_rfbv2_2020-2.tcl deleted file mode 100644 index 6573548..0000000 --- a/qick/firmware/bd/bd_111_rfbv2_2020-2.tcl +++ /dev/null @@ -1,2606 +0,0 @@ - -################################################################ -# This is a generated script based on design: d_1 -# -# Though there are limitations about the generated script, -# the main purpose of this utility is to make learning -# IP Integrator Tcl commands easier. -################################################################ - -namespace eval _tcl { -proc get_script_folder {} { - set script_path [file normalize [info script]] - set script_folder [file dirname $script_path] - return $script_folder -} -} -variable script_folder -set script_folder [_tcl::get_script_folder] - -################################################################ -# Check if script is running in correct Vivado version. -################################################################ -set scripts_vivado_version 2020.2 -set current_vivado_version [version -short] - -if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { - puts "" - catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} - - return 1 -} - -################################################################ -# START -################################################################ - -# To test this script, run the following commands from Vivado Tcl console: -# source d_1_script.tcl - - -# The design that will be created by this Tcl script contains the following -# module references: -# lo_spi_mux_v2, vect2bits_16 - -# Please add the sources of those modules before sourcing this Tcl script. - -# If there is no project opened, this script will create a -# project, but make sure you do not have an existing project -# <./myproj/project_1.xpr> in the current working folder. - -set list_projs [get_projects -quiet] -if { $list_projs eq "" } { - create_project project_1 myproj -part xczu28dr-ffvg1517-2-e - set_property BOARD_PART xilinx.com:zcu111:part0:1.4 [current_project] -} - - -# CHANGE DESIGN NAME HERE -variable design_name -set design_name d_1 - -# If you do not already have an existing IP Integrator design open, -# you can create a design using the following command: -# create_bd_design $design_name - -# Creating design if needed -set errMsg "" -set nRet 0 - -set cur_design [current_bd_design -quiet] -set list_cells [get_bd_cells -quiet] - -if { ${design_name} eq "" } { - # USE CASES: - # 1) Design_name not set - - set errMsg "Please set the variable to a non-empty value." - set nRet 1 - -} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { - # USE CASES: - # 2): Current design opened AND is empty AND names same. - # 3): Current design opened AND is empty AND names diff; design_name NOT in project. - # 4): Current design opened AND is empty AND names diff; design_name exists in project. - - if { $cur_design ne $design_name } { - common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." - set design_name [get_property NAME $cur_design] - } - common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." - -} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { - # USE CASES: - # 5) Current design opened AND has components AND same names. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 1 -} elseif { [get_files -quiet ${design_name}.bd] ne "" } { - # USE CASES: - # 6) Current opened design, has components, but diff names, design_name exists in project. - # 7) No opened design, design_name exists in project. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 2 - -} else { - # USE CASES: - # 8) No opened design, design_name not in project. - # 9) Current opened design, has components, but diff names, design_name not in project. - - common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." - - create_bd_design $design_name - - common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." - current_bd_design $design_name - -} - -common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." - -if { $nRet != 0 } { - catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} - return $nRet -} - -set bCheckIPsPassed 1 -################################################################## -# CHECK IPs -################################################################## -set bCheckIPs 1 -if { $bCheckIPs == 1 } { - set list_check_ips "\ -xilinx.com:ip:axi_quad_spi:3.2\ -xilinx.com:ip:axi_bram_ctrl:4.1\ -xilinx.com:ip:blk_mem_gen:8.4\ -xilinx.com:ip:axi_dma:7.1\ -xilinx.com:ip:smartconnect:1.0\ -user.org:user:axis_avg_buffer:1.0\ -user.org:user:axis_cdcsync_v1:1.0\ -xilinx.com:ip:axis_clock_converter:1.1\ -user.org:user:axis_constant:1.0\ -user.org:user:axis_readout_v2:1.0\ -xilinx.com:ip:axis_register_slice:1.1\ -user.org:user:axis_set_reg:1.0\ -user.org:user:axis_signal_gen_v6:1.0\ -xilinx.com:ip:axis_switch:1.1\ -user.org:user:axis_tproc64x32_x8:1.0\ -xilinx.com:ip:xlconstant:1.1\ -xilinx.com:ip:clk_wiz:6.0\ -xilinx.com:ip:proc_sys_reset:5.0\ -xilinx.com:ip:usp_rf_data_converter:2.4\ -xilinx.com:ip:zynq_ultra_ps_e:3.3\ -" - - set list_ips_missing "" - common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." - - foreach ip_vlnv $list_check_ips { - set ip_obj [get_ipdefs -all $ip_vlnv] - if { $ip_obj eq "" } { - lappend list_ips_missing $ip_vlnv - } - } - - if { $list_ips_missing ne "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } - set bCheckIPsPassed 0 - } - -} - -################################################################## -# CHECK Modules -################################################################## -set bCheckModules 1 -if { $bCheckModules == 1 } { - set list_check_mods "\ -lo_spi_mux_v2\ -vect2bits_16\ -" - - set list_mods_missing "" - common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." - - foreach mod_vlnv $list_check_mods { - if { [can_resolve_reference $mod_vlnv] == 0 } { - lappend list_mods_missing $mod_vlnv - } - } - - if { $list_mods_missing ne "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } - common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." - set bCheckIPsPassed 0 - } -} - -if { $bCheckIPsPassed != 1 } { - common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." - return 3 -} - -################################################################## -# DESIGN PROCs -################################################################## - - - -# Procedure to create entire design; Provide argument to make -# procedure reusable. If parentCell is "", will use root. -proc create_root_design { parentCell } { - - variable script_folder - variable design_name - - if { $parentCell eq "" } { - set parentCell [get_bd_cells /] - } - - # Get object for parentCell - set parentObj [get_bd_cells $parentCell] - if { $parentObj == "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} - return - } - - # Make sure parentObj is hier blk - set parentType [get_property TYPE $parentObj] - if { $parentType ne "hier" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} - return - } - - # Save current instance; Restore later - set oldCurInst [current_bd_instance .] - - # Set parent object as current - current_bd_instance $parentObj - - - # Create interface ports - set adc0_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 adc0_clk ] - - set dac0_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac0_clk ] - - set dac1_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac1_clk ] - - set sysref_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:display_usp_rf_data_converter:diff_pins_rtl:1.0 sysref_in ] - - set vin0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vin0 ] - - set vin1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vin1 ] - - set vout0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout0 ] - - set vout1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout1 ] - - set vout2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout2 ] - - set vout3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout3 ] - - set vout4 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout4 ] - - set vout5 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout5 ] - - set vout6 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout6 ] - - - # Create ports - set ATTN_CLK [ create_bd_port -dir O ATTN_CLK ] - set ATTN_LE [ create_bd_port -dir O -from 2 -to 0 ATTN_LE ] - set ATTN_SI [ create_bd_port -dir O ATTN_SI ] - set BIAS_CLR [ create_bd_port -dir O -from 0 -to 0 BIAS_CLR ] - set BIAS_S [ create_bd_port -dir O -from 3 -to 0 BIAS_S ] - set BIAS_SCLK [ create_bd_port -dir O BIAS_SCLK ] - set BIAS_SDI [ create_bd_port -dir O BIAS_SDI ] - set BIAS_SDO [ create_bd_port -dir I BIAS_SDO ] - set LO_CS0 [ create_bd_port -dir O LO_CS0 ] - set LO_CS1 [ create_bd_port -dir O LO_CS1 ] - set LO_CS2 [ create_bd_port -dir O LO_CS2 ] - set LO_MISO0 [ create_bd_port -dir I LO_MISO0 ] - set LO_MISO1 [ create_bd_port -dir I LO_MISO1 ] - set LO_MISO2 [ create_bd_port -dir I LO_MISO2 ] - set LO_MOSI [ create_bd_port -dir O LO_MOSI ] - set LO_SCLK [ create_bd_port -dir O LO_SCLK ] - set LO_SYNC [ create_bd_port -dir O -from 0 -to 0 LO_SYNC ] - set PMOD0_0_LS [ create_bd_port -dir O PMOD0_0_LS ] - set PMOD0_1_LS [ create_bd_port -dir O PMOD0_1_LS ] - set PMOD0_2_LS [ create_bd_port -dir O PMOD0_2_LS ] - set PMOD0_3_LS [ create_bd_port -dir O PMOD0_3_LS ] - set PMOD0_4_LS [ create_bd_port -dir O PMOD0_4_LS ] - set PMOD0_5_LS [ create_bd_port -dir O PMOD0_5_LS ] - set PMOD0_6_LS [ create_bd_port -dir O PMOD0_6_LS ] - set PMOD0_7_LS [ create_bd_port -dir O PMOD0_7_LS ] - set PMOD1_0_LS [ create_bd_port -dir I PMOD1_0_LS ] - set PWR_SYNC [ create_bd_port -dir O -from 0 -to 0 PWR_SYNC ] - set S [ create_bd_port -dir O -from 3 -to 0 S ] - set SCLK [ create_bd_port -dir O SCLK ] - set SDI [ create_bd_port -dir O SDI ] - set SDO [ create_bd_port -dir I SDO ] - - # Create instance: attn_spi, and set properties - set attn_spi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 attn_spi ] - set_property -dict [ list \ - CONFIG.C_NUM_SS_BITS {3} \ - CONFIG.C_NUM_TRANSFER_BITS {16} \ - ] $attn_spi - - # Create instance: axi_bram_ctrl_0, and set properties - set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {64} \ - CONFIG.SINGLE_PORT_BRAM {1} \ - ] $axi_bram_ctrl_0 - - # Create instance: axi_bram_ctrl_0_bram, and set properties - set axi_bram_ctrl_0_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 axi_bram_ctrl_0_bram ] - set_property -dict [ list \ - CONFIG.EN_SAFETY_CKT {false} \ - CONFIG.Enable_B {Use_ENB_Pin} \ - CONFIG.Memory_Type {True_Dual_Port_RAM} \ - CONFIG.Port_B_Clock {100} \ - CONFIG.Port_B_Enable_Rate {100} \ - CONFIG.Port_B_Write_Rate {50} \ - CONFIG.Read_Width_B {64} \ - CONFIG.Use_RSTB_Pin {true} \ - CONFIG.Write_Width_B {64} \ - ] $axi_bram_ctrl_0_bram - - # Create instance: axi_dma_avg, and set properties - set axi_dma_avg [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_avg ] - set_property -dict [ list \ - CONFIG.c_include_mm2s {0} \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_length_width {26} \ - ] $axi_dma_avg - - # Create instance: axi_dma_buf, and set properties - set axi_dma_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_buf ] - set_property -dict [ list \ - CONFIG.c_include_mm2s {0} \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_length_width {26} \ - ] $axi_dma_buf - - # Create instance: axi_dma_gen, and set properties - set axi_dma_gen [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_gen ] - set_property -dict [ list \ - CONFIG.c_include_mm2s {1} \ - CONFIG.c_include_s2mm {0} \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_length_width {26} \ - ] $axi_dma_gen - - # Create instance: axi_dma_tproc, and set properties - set axi_dma_tproc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_tproc ] - set_property -dict [ list \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_length_width {26} \ - ] $axi_dma_tproc - - # Create instance: axi_smc, and set properties - set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ] - set_property -dict [ list \ - CONFIG.NUM_SI {5} \ - ] $axi_smc - - # Create instance: axis_avg_buffer_0, and set properties - set axis_avg_buffer_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_avg_buffer:1.0 axis_avg_buffer_0 ] - set_property -dict [ list \ - CONFIG.N_AVG {14} \ - ] $axis_avg_buffer_0 - - # Create instance: axis_avg_buffer_1, and set properties - set axis_avg_buffer_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_avg_buffer:1.0 axis_avg_buffer_1 ] - set_property -dict [ list \ - CONFIG.N_AVG {14} \ - ] $axis_avg_buffer_1 - - # Create instance: axis_cdcsync_v1_0, and set properties - set axis_cdcsync_v1_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_cdcsync_v1:1.0 axis_cdcsync_v1_0 ] - set_property -dict [ list \ - CONFIG.B {160} \ - CONFIG.N {4} \ - ] $axis_cdcsync_v1_0 - - # Create instance: axis_cdcsync_v1_1, and set properties - set axis_cdcsync_v1_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_cdcsync_v1:1.0 axis_cdcsync_v1_1 ] - set_property -dict [ list \ - CONFIG.B {160} \ - CONFIG.N {4} \ - ] $axis_cdcsync_v1_1 - - # Create instance: axis_clk_cnvrt_avg_0, and set properties - set axis_clk_cnvrt_avg_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_avg_0 ] - - # Create instance: axis_clk_cnvrt_avg_1, and set properties - set axis_clk_cnvrt_avg_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_avg_1 ] - - # Create instance: axis_constant_0, and set properties - set axis_constant_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_constant:1.0 axis_constant_0 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {64} \ - ] $axis_constant_0 - - # Create instance: axis_constant_1, and set properties - set axis_constant_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_constant:1.0 axis_constant_1 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {64} \ - ] $axis_constant_1 - - # Create instance: axis_constant_2, and set properties - set axis_constant_2 [ create_bd_cell -type ip -vlnv user.org:user:axis_constant:1.0 axis_constant_2 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {160} \ - ] $axis_constant_2 - - # Create instance: axis_readout_v2_0, and set properties - set axis_readout_v2_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_readout_v2:1.0 axis_readout_v2_0 ] - set_property -dict [ list \ - CONFIG.FULLSPEED_OUTPUT {false} \ - ] $axis_readout_v2_0 - - # Create instance: axis_readout_v2_1, and set properties - set axis_readout_v2_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_readout_v2:1.0 axis_readout_v2_1 ] - set_property -dict [ list \ - CONFIG.FULLSPEED_OUTPUT {false} \ - ] $axis_readout_v2_1 - - # Create instance: axis_register_slice_0, and set properties - set axis_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_0 ] - - # Create instance: axis_register_slice_1, and set properties - set axis_register_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_1 ] - - # Create instance: axis_set_reg_0, and set properties - set axis_set_reg_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_set_reg:1.0 axis_set_reg_0 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {160} \ - ] $axis_set_reg_0 - - # Create instance: axis_signal_gen_v6_0, and set properties - set axis_signal_gen_v6_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_0 ] - - # Create instance: axis_signal_gen_v6_1, and set properties - set axis_signal_gen_v6_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_1 ] - - # Create instance: axis_signal_gen_v6_2, and set properties - set axis_signal_gen_v6_2 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_2 ] - - # Create instance: axis_signal_gen_v6_3, and set properties - set axis_signal_gen_v6_3 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_3 ] - - # Create instance: axis_signal_gen_v6_4, and set properties - set axis_signal_gen_v6_4 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_4 ] - - # Create instance: axis_signal_gen_v6_5, and set properties - set axis_signal_gen_v6_5 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_5 ] - - # Create instance: axis_signal_gen_v6_6, and set properties - set axis_signal_gen_v6_6 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_6 ] - - # Create instance: axis_switch_avg, and set properties - set axis_switch_avg [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_avg ] - set_property -dict [ list \ - CONFIG.ROUTING_MODE {1} \ - ] $axis_switch_avg - - # Create instance: axis_switch_buf, and set properties - set axis_switch_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_buf ] - set_property -dict [ list \ - CONFIG.ROUTING_MODE {1} \ - ] $axis_switch_buf - - # Create instance: axis_switch_gen, and set properties - set axis_switch_gen [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_gen ] - set_property -dict [ list \ - CONFIG.DECODER_REG {1} \ - CONFIG.NUM_MI {7} \ - CONFIG.NUM_SI {1} \ - CONFIG.ROUTING_MODE {1} \ - ] $axis_switch_gen - - # Create instance: axis_tproc64x32_x8_0, and set properties - set axis_tproc64x32_x8_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_tproc64x32_x8:1.0 axis_tproc64x32_x8_0 ] - set_property -dict [ list \ - CONFIG.DMEM_N {12} \ - CONFIG.PMEM_N {20} \ - ] $axis_tproc64x32_x8_0 - - # Create instance: bias_constant_1, and set properties - set bias_constant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 bias_constant_1 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {1} \ - ] $bias_constant_1 - - # Create instance: clk_adc0_x2, and set properties - set clk_adc0_x2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_adc0_x2 ] - set_property -dict [ list \ - CONFIG.CLKIN1_JITTER_PS {39.06} \ - CONFIG.CLKOUT1_JITTER {73.505} \ - CONFIG.CLKOUT1_PHASE_ERROR {77.298} \ - CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {512} \ - CONFIG.MMCM_CLKFBOUT_MULT_F {4.750} \ - CONFIG.MMCM_CLKIN1_PERIOD {3.906} \ - CONFIG.MMCM_CLKIN2_PERIOD {10.0} \ - CONFIG.MMCM_CLKOUT0_DIVIDE_F {2.375} \ - CONFIG.MMCM_DIVCLK_DIVIDE {1} \ - ] $clk_adc0_x2 - - # Create instance: dac_bias_spi, and set properties - set dac_bias_spi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 dac_bias_spi ] - set_property -dict [ list \ - CONFIG.C_NUM_SS_BITS {4} \ - CONFIG.C_NUM_TRANSFER_BITS {8} \ - ] $dac_bias_spi - - # Create instance: lo_spi, and set properties - set lo_spi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 lo_spi ] - set_property -dict [ list \ - CONFIG.C_NUM_SS_BITS {3} \ - CONFIG.C_NUM_TRANSFER_BITS {8} \ - ] $lo_spi - - # Create instance: lo_spi_mux_v2_0, and set properties - set block_name lo_spi_mux_v2 - set block_cell_name lo_spi_mux_v2_0 - if { [catch {set lo_spi_mux_v2_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { - catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} - return 1 - } elseif { $lo_spi_mux_v2_0 eq "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} - return 1 - } - - # Create instance: lo_sync_constant_0, and set properties - set lo_sync_constant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 lo_sync_constant_0 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - ] $lo_sync_constant_0 - - # Create instance: ps8_0_axi_periph, and set properties - set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ] - set_property -dict [ list \ - CONFIG.NUM_MI {25} \ - ] $ps8_0_axi_periph - - # Create instance: psf_spi, and set properties - set psf_spi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 psf_spi ] - set_property -dict [ list \ - CONFIG.C_NUM_SS_BITS {4} \ - CONFIG.C_NUM_TRANSFER_BITS {8} \ - ] $psf_spi - - # Create instance: rst_100, and set properties - set rst_100 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_100 ] - - # Create instance: rst_adc0, and set properties - set rst_adc0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_adc0 ] - - # Create instance: rst_adc0_x2, and set properties - set rst_adc0_x2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_adc0_x2 ] - - # Create instance: rst_dac0, and set properties - set rst_dac0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_dac0 ] - - # Create instance: rst_dac1, and set properties - set rst_dac1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_dac1 ] - - # Create instance: usp_rf_data_converter_0, and set properties - set usp_rf_data_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:usp_rf_data_converter:2.4 usp_rf_data_converter_0 ] - set_property -dict [ list \ - CONFIG.ADC0_Fabric_Freq {512.000} \ - CONFIG.ADC0_Outclk_Freq {256.000} \ - CONFIG.ADC0_PLL_Enable {true} \ - CONFIG.ADC0_Refclk_Freq {409.600} \ - CONFIG.ADC0_Sampling_Rate {4.096} \ - CONFIG.ADC_Decimation_Mode00 {1} \ - CONFIG.ADC_Decimation_Mode02 {1} \ - CONFIG.ADC_Mixer_Type00 {0} \ - CONFIG.ADC_Mixer_Type01 {0} \ - CONFIG.ADC_Mixer_Type02 {0} \ - CONFIG.ADC_Mixer_Type03 {0} \ - CONFIG.ADC_RESERVED_1_00 {false} \ - CONFIG.ADC_RESERVED_1_02 {false} \ - CONFIG.ADC_Slice00_Enable {true} \ - CONFIG.ADC_Slice02_Enable {true} \ - CONFIG.DAC0_Fabric_Freq {409.600} \ - CONFIG.DAC0_Outclk_Freq {409.600} \ - CONFIG.DAC0_PLL_Enable {true} \ - CONFIG.DAC0_Refclk_Freq {409.600} \ - CONFIG.DAC0_Sampling_Rate {6.5536} \ - CONFIG.DAC1_Fabric_Freq {409.600} \ - CONFIG.DAC1_Outclk_Freq {409.600} \ - CONFIG.DAC1_PLL_Enable {true} \ - CONFIG.DAC1_Refclk_Freq {409.600} \ - CONFIG.DAC1_Sampling_Rate {6.5536} \ - CONFIG.DAC_Interpolation_Mode00 {1} \ - CONFIG.DAC_Interpolation_Mode01 {1} \ - CONFIG.DAC_Interpolation_Mode02 {1} \ - CONFIG.DAC_Interpolation_Mode10 {1} \ - CONFIG.DAC_Interpolation_Mode11 {1} \ - CONFIG.DAC_Interpolation_Mode12 {1} \ - CONFIG.DAC_Interpolation_Mode13 {1} \ - CONFIG.DAC_Mixer_Type00 {0} \ - CONFIG.DAC_Mixer_Type01 {0} \ - CONFIG.DAC_Mixer_Type02 {0} \ - CONFIG.DAC_Mixer_Type10 {0} \ - CONFIG.DAC_Mixer_Type11 {0} \ - CONFIG.DAC_Mixer_Type12 {0} \ - CONFIG.DAC_Mixer_Type13 {0} \ - CONFIG.DAC_Slice00_Enable {true} \ - CONFIG.DAC_Slice01_Enable {true} \ - CONFIG.DAC_Slice02_Enable {true} \ - CONFIG.DAC_Slice10_Enable {true} \ - CONFIG.DAC_Slice11_Enable {true} \ - CONFIG.DAC_Slice12_Enable {true} \ - CONFIG.DAC_Slice13_Enable {true} \ - ] $usp_rf_data_converter_0 - - # Create instance: vect2bits_16_0, and set properties - set block_name vect2bits_16 - set block_cell_name vect2bits_16_0 - if { [catch {set vect2bits_16_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { - catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} - return 1 - } elseif { $vect2bits_16_0 eq "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} - return 1 - } - - # Create instance: xlconstant_0, and set properties - set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - CONFIG.CONST_WIDTH {64} \ - ] $xlconstant_0 - - # Create instance: xlconstant_1, and set properties - set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ] - set_property -dict [ list \ - CONFIG.CONST_WIDTH {1} \ - ] $xlconstant_1 - - # Create instance: xlconstant_2, and set properties - set xlconstant_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_2 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - CONFIG.CONST_WIDTH {1} \ - ] $xlconstant_2 - - # Create instance: xlconstant_3, and set properties - set xlconstant_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_3 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - CONFIG.CONST_WIDTH {8} \ - ] $xlconstant_3 - - # Create instance: zynq_ultra_ps_e_0, and set properties - set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ] - set_property -dict [ list \ - CONFIG.CAN0_BOARD_INTERFACE {custom} \ - CONFIG.CAN1_BOARD_INTERFACE {custom} \ - CONFIG.CSU_BOARD_INTERFACE {custom} \ - CONFIG.DP_BOARD_INTERFACE {custom} \ - CONFIG.GEM0_BOARD_INTERFACE {custom} \ - CONFIG.GEM1_BOARD_INTERFACE {custom} \ - CONFIG.GEM2_BOARD_INTERFACE {custom} \ - CONFIG.GEM3_BOARD_INTERFACE {custom} \ - CONFIG.GPIO_BOARD_INTERFACE {custom} \ - CONFIG.IIC0_BOARD_INTERFACE {custom} \ - CONFIG.IIC1_BOARD_INTERFACE {custom} \ - CONFIG.NAND_BOARD_INTERFACE {custom} \ - CONFIG.PCIE_BOARD_INTERFACE {custom} \ - CONFIG.PJTAG_BOARD_INTERFACE {custom} \ - CONFIG.PMU_BOARD_INTERFACE {custom} \ - CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS33} \ - CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \ - CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \ - CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \ - CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \ - CONFIG.PSU_MIO_0_DIRECTION {out} \ - CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_0_POLARITY {Default} \ - CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_0_SLEW {fast} \ - CONFIG.PSU_MIO_10_DIRECTION {inout} \ - CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_10_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_10_POLARITY {Default} \ - CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_10_SLEW {fast} \ - CONFIG.PSU_MIO_11_DIRECTION {inout} \ - CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_11_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_11_POLARITY {Default} \ - CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_11_SLEW {fast} \ - CONFIG.PSU_MIO_12_DIRECTION {out} \ - CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_12_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_12_POLARITY {Default} \ - CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_12_SLEW {fast} \ - CONFIG.PSU_MIO_13_DIRECTION {inout} \ - CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_13_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_13_POLARITY {Default} \ - CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_13_SLEW {fast} \ - CONFIG.PSU_MIO_14_DIRECTION {inout} \ - CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_14_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_14_POLARITY {Default} \ - CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_14_SLEW {fast} \ - CONFIG.PSU_MIO_15_DIRECTION {inout} \ - CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_15_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_15_POLARITY {Default} \ - CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_15_SLEW {fast} \ - CONFIG.PSU_MIO_16_DIRECTION {inout} \ - CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_16_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_16_POLARITY {Default} \ - CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_16_SLEW {fast} \ - CONFIG.PSU_MIO_17_DIRECTION {inout} \ - CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_17_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_17_POLARITY {Default} \ - CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_17_SLEW {fast} \ - CONFIG.PSU_MIO_18_DIRECTION {in} \ - CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_18_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_18_POLARITY {Default} \ - CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_18_SLEW {fast} \ - CONFIG.PSU_MIO_19_DIRECTION {out} \ - CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_19_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_19_POLARITY {Default} \ - CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_19_SLEW {fast} \ - CONFIG.PSU_MIO_1_DIRECTION {inout} \ - CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_1_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_1_POLARITY {Default} \ - CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_1_SLEW {fast} \ - CONFIG.PSU_MIO_20_DIRECTION {inout} \ - CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_20_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_20_POLARITY {Default} \ - CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_20_SLEW {fast} \ - CONFIG.PSU_MIO_21_DIRECTION {inout} \ - CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_21_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_21_POLARITY {Default} \ - CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_21_SLEW {fast} \ - CONFIG.PSU_MIO_22_DIRECTION {inout} \ - CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_22_POLARITY {Default} \ - CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_22_SLEW {fast} \ - CONFIG.PSU_MIO_23_DIRECTION {inout} \ - CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_23_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_23_POLARITY {Default} \ - CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_23_SLEW {fast} \ - CONFIG.PSU_MIO_24_DIRECTION {inout} \ - CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_24_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_24_POLARITY {Default} \ - CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_24_SLEW {fast} \ - CONFIG.PSU_MIO_25_DIRECTION {inout} \ - CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_25_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_25_POLARITY {Default} \ - CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_25_SLEW {fast} \ - CONFIG.PSU_MIO_26_DIRECTION {inout} \ - CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_26_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_26_POLARITY {Default} \ - CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_26_SLEW {fast} \ - CONFIG.PSU_MIO_27_DIRECTION {out} \ - CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_27_POLARITY {Default} \ - CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_27_SLEW {fast} \ - CONFIG.PSU_MIO_28_DIRECTION {in} \ - CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_28_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_28_POLARITY {Default} \ - CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_28_SLEW {fast} \ - CONFIG.PSU_MIO_29_DIRECTION {out} \ - CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_29_POLARITY {Default} \ - CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_29_SLEW {fast} \ - CONFIG.PSU_MIO_2_DIRECTION {inout} \ - CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_2_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_2_POLARITY {Default} \ - CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_2_SLEW {fast} \ - CONFIG.PSU_MIO_30_DIRECTION {in} \ - CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_30_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_30_POLARITY {Default} \ - CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_30_SLEW {fast} \ - CONFIG.PSU_MIO_31_DIRECTION {inout} \ - CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_31_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_31_POLARITY {Default} \ - CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_31_SLEW {fast} \ - CONFIG.PSU_MIO_32_DIRECTION {out} \ - CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_32_POLARITY {Default} \ - CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_32_SLEW {fast} \ - CONFIG.PSU_MIO_33_DIRECTION {out} \ - CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_33_POLARITY {Default} \ - CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_33_SLEW {fast} \ - CONFIG.PSU_MIO_34_DIRECTION {out} \ - CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_34_POLARITY {Default} \ - CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_34_SLEW {fast} \ - CONFIG.PSU_MIO_35_DIRECTION {out} \ - CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_35_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_35_POLARITY {Default} \ - CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_35_SLEW {fast} \ - CONFIG.PSU_MIO_36_DIRECTION {out} \ - CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_36_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_36_POLARITY {Default} \ - CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_36_SLEW {fast} \ - CONFIG.PSU_MIO_37_DIRECTION {out} \ - CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_37_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_37_POLARITY {Default} \ - CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_37_SLEW {fast} \ - CONFIG.PSU_MIO_38_DIRECTION {inout} \ - CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_38_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_38_POLARITY {Default} \ - CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_38_SLEW {fast} \ - CONFIG.PSU_MIO_39_DIRECTION {inout} \ - CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_39_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_39_POLARITY {Default} \ - CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_39_SLEW {fast} \ - CONFIG.PSU_MIO_3_DIRECTION {inout} \ - CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_3_POLARITY {Default} \ - CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_3_SLEW {fast} \ - CONFIG.PSU_MIO_40_DIRECTION {inout} \ - CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_40_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_40_POLARITY {Default} \ - CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_40_SLEW {fast} \ - CONFIG.PSU_MIO_41_DIRECTION {inout} \ - CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_41_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_41_POLARITY {Default} \ - CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_41_SLEW {fast} \ - CONFIG.PSU_MIO_42_DIRECTION {inout} \ - CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_42_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_42_POLARITY {Default} \ - CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_42_SLEW {fast} \ - CONFIG.PSU_MIO_43_DIRECTION {inout} \ - CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_43_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_43_POLARITY {Default} \ - CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_43_SLEW {fast} \ - CONFIG.PSU_MIO_44_DIRECTION {inout} \ - CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_44_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_44_POLARITY {Default} \ - CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_44_SLEW {fast} \ - CONFIG.PSU_MIO_45_DIRECTION {in} \ - CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_45_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_45_POLARITY {Default} \ - CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_45_SLEW {fast} \ - CONFIG.PSU_MIO_46_DIRECTION {inout} \ - CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_46_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_46_POLARITY {Default} \ - CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_46_SLEW {fast} \ - CONFIG.PSU_MIO_47_DIRECTION {inout} \ - CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_47_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_47_POLARITY {Default} \ - CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_47_SLEW {fast} \ - CONFIG.PSU_MIO_48_DIRECTION {inout} \ - CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_48_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_48_POLARITY {Default} \ - CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_48_SLEW {fast} \ - CONFIG.PSU_MIO_49_DIRECTION {inout} \ - CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_49_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_49_POLARITY {Default} \ - CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_49_SLEW {fast} \ - CONFIG.PSU_MIO_4_DIRECTION {inout} \ - CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_4_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_4_POLARITY {Default} \ - CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_4_SLEW {fast} \ - CONFIG.PSU_MIO_50_DIRECTION {inout} \ - CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_50_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_50_POLARITY {Default} \ - CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_50_SLEW {fast} \ - CONFIG.PSU_MIO_51_DIRECTION {out} \ - CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_51_POLARITY {Default} \ - CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_51_SLEW {fast} \ - CONFIG.PSU_MIO_52_DIRECTION {in} \ - CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_52_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_52_POLARITY {Default} \ - CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_52_SLEW {fast} \ - CONFIG.PSU_MIO_53_DIRECTION {in} \ - CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_53_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_53_POLARITY {Default} \ - CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_53_SLEW {fast} \ - CONFIG.PSU_MIO_54_DIRECTION {inout} \ - CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_54_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_54_POLARITY {Default} \ - CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_54_SLEW {fast} \ - CONFIG.PSU_MIO_55_DIRECTION {in} \ - CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_55_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_55_POLARITY {Default} \ - CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_55_SLEW {fast} \ - CONFIG.PSU_MIO_56_DIRECTION {inout} \ - CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_56_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_56_POLARITY {Default} \ - CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_56_SLEW {fast} \ - CONFIG.PSU_MIO_57_DIRECTION {inout} \ - CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_57_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_57_POLARITY {Default} \ - CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_57_SLEW {fast} \ - CONFIG.PSU_MIO_58_DIRECTION {out} \ - CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_58_POLARITY {Default} \ - CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_58_SLEW {fast} \ - CONFIG.PSU_MIO_59_DIRECTION {inout} \ - CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_59_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_59_POLARITY {Default} \ - CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_59_SLEW {fast} \ - CONFIG.PSU_MIO_5_DIRECTION {out} \ - CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_5_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_5_POLARITY {Default} \ - CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_5_SLEW {fast} \ - CONFIG.PSU_MIO_60_DIRECTION {inout} \ - CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_60_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_60_POLARITY {Default} \ - CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_60_SLEW {fast} \ - CONFIG.PSU_MIO_61_DIRECTION {inout} \ - CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_61_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_61_POLARITY {Default} \ - CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_61_SLEW {fast} \ - CONFIG.PSU_MIO_62_DIRECTION {inout} \ - CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_62_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_62_POLARITY {Default} \ - CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_62_SLEW {fast} \ - CONFIG.PSU_MIO_63_DIRECTION {inout} \ - CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_63_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_63_POLARITY {Default} \ - CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_63_SLEW {fast} \ - CONFIG.PSU_MIO_64_DIRECTION {out} \ - CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_64_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_64_POLARITY {Default} \ - CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_64_SLEW {fast} \ - CONFIG.PSU_MIO_65_DIRECTION {out} \ - CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_65_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_65_POLARITY {Default} \ - CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_65_SLEW {fast} \ - CONFIG.PSU_MIO_66_DIRECTION {out} \ - CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_66_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_66_POLARITY {Default} \ - CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_66_SLEW {fast} \ - CONFIG.PSU_MIO_67_DIRECTION {out} \ - CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_67_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_67_POLARITY {Default} \ - CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_67_SLEW {fast} \ - CONFIG.PSU_MIO_68_DIRECTION {out} \ - CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_68_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_68_POLARITY {Default} \ - CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_68_SLEW {fast} \ - CONFIG.PSU_MIO_69_DIRECTION {out} \ - CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_69_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_69_POLARITY {Default} \ - CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_69_SLEW {fast} \ - CONFIG.PSU_MIO_6_DIRECTION {out} \ - CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_6_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_6_POLARITY {Default} \ - CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_6_SLEW {fast} \ - CONFIG.PSU_MIO_70_DIRECTION {in} \ - CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_70_POLARITY {Default} \ - CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_70_SLEW {fast} \ - CONFIG.PSU_MIO_71_DIRECTION {in} \ - CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_71_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_71_POLARITY {Default} \ - CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_71_SLEW {fast} \ - CONFIG.PSU_MIO_72_DIRECTION {in} \ - CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_72_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_72_POLARITY {Default} \ - CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_72_SLEW {fast} \ - CONFIG.PSU_MIO_73_DIRECTION {in} \ - CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_73_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_73_POLARITY {Default} \ - CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_73_SLEW {fast} \ - CONFIG.PSU_MIO_74_DIRECTION {in} \ - CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_74_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_74_POLARITY {Default} \ - CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_74_SLEW {fast} \ - CONFIG.PSU_MIO_75_DIRECTION {in} \ - CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_75_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_75_POLARITY {Default} \ - CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_75_SLEW {fast} \ - CONFIG.PSU_MIO_76_DIRECTION {out} \ - CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_76_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_76_POLARITY {Default} \ - CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_76_SLEW {fast} \ - CONFIG.PSU_MIO_77_DIRECTION {inout} \ - CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_77_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_77_POLARITY {Default} \ - CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_77_SLEW {fast} \ - CONFIG.PSU_MIO_7_DIRECTION {out} \ - CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_7_POLARITY {Default} \ - CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_7_SLEW {fast} \ - CONFIG.PSU_MIO_8_DIRECTION {inout} \ - CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_8_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_8_POLARITY {Default} \ - CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_8_SLEW {fast} \ - CONFIG.PSU_MIO_9_DIRECTION {inout} \ - CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_9_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_9_POLARITY {Default} \ - CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_9_SLEW {fast} \ - CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO0 MIO#I2C 0#I2C 0#I2C 1#I2C 1#UART 0#UART 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO1 MIO#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#PMU GPO 3#PMU GPO 4#PMU GPO 5#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3} \ - CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#gpio0[13]#scl_out#sda_out#scl_out#sda_out#rxd#txd#gpio0[20]#gpio0[21]#gpio0[22]#gpio0[23]#gpio0[24]#gpio0[25]#gpio1[26]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpo[3]#gpo[4]#gpo[5]#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#gpio1[43]#gpio1[44]#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out} \ - CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \ - CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {8} \ - CONFIG.PSU_SMC_CYCLE_T0 {NA} \ - CONFIG.PSU_SMC_CYCLE_T1 {NA} \ - CONFIG.PSU_SMC_CYCLE_T2 {NA} \ - CONFIG.PSU_SMC_CYCLE_T3 {NA} \ - CONFIG.PSU_SMC_CYCLE_T4 {NA} \ - CONFIG.PSU_SMC_CYCLE_T5 {NA} \ - CONFIG.PSU_SMC_CYCLE_T6 {NA} \ - CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \ - CONFIG.PSU_VALUE_SILVERSION {3} \ - CONFIG.PSU__ACPU0__POWER__ON {1} \ - CONFIG.PSU__ACPU1__POWER__ON {1} \ - CONFIG.PSU__ACPU2__POWER__ON {1} \ - CONFIG.PSU__ACPU3__POWER__ON {1} \ - CONFIG.PSU__ACTUAL__IP {1} \ - CONFIG.PSU__ACT_DDR_FREQ_MHZ {1050.000000} \ - CONFIG.PSU__AFI0_COHERENCY {0} \ - CONFIG.PSU__AFI1_COHERENCY {0} \ - CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \ - CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \ - CONFIG.PSU__CAN0__GRP_CLK__ENABLE {0} \ - CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \ - CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \ - CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \ - CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \ - CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \ - CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \ - CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \ - CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \ - CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \ - CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \ - CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {525.000000} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {63} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25.000000} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.785715} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {14} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {300.000000} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \ - CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \ - CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {0} \ - CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \ - CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \ - CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \ - CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \ - CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \ - CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250.000000} \ - CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {525.000000} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {90} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {50.000000} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {180} \ - CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {180} \ - CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {SysOsc} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \ - CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \ - CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \ - CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \ - CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {125.000000} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {250.000000} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {2.000000} \ - CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {50} \ - CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {15} \ - CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {2} \ - CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {125.000000} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {45} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {7} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {214} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {7} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {214} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {7} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \ - CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \ - CONFIG.PSU__CSU_COHERENCY {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__DDRC__ADDR_MIRROR {0} \ - CONFIG.PSU__DDRC__AL {0} \ - CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \ - CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \ - CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \ - CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \ - CONFIG.PSU__DDRC__CL {15} \ - CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \ - CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \ - CONFIG.PSU__DDRC__COMPONENTS {UDIMM} \ - CONFIG.PSU__DDRC__CWL {14} \ - CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \ - CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \ - CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \ - CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {0} \ - CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \ - CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \ - CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \ - CONFIG.PSU__DDRC__DEVICE_CAPACITY {8192 MBits} \ - CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \ - CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \ - CONFIG.PSU__DDRC__DQMAP_0_3 {0} \ - CONFIG.PSU__DDRC__DQMAP_12_15 {0} \ - CONFIG.PSU__DDRC__DQMAP_16_19 {0} \ - CONFIG.PSU__DDRC__DQMAP_20_23 {0} \ - CONFIG.PSU__DDRC__DQMAP_24_27 {0} \ - CONFIG.PSU__DDRC__DQMAP_28_31 {0} \ - CONFIG.PSU__DDRC__DQMAP_32_35 {0} \ - CONFIG.PSU__DDRC__DQMAP_36_39 {0} \ - CONFIG.PSU__DDRC__DQMAP_40_43 {0} \ - CONFIG.PSU__DDRC__DQMAP_44_47 {0} \ - CONFIG.PSU__DDRC__DQMAP_48_51 {0} \ - CONFIG.PSU__DDRC__DQMAP_4_7 {0} \ - CONFIG.PSU__DDRC__DQMAP_52_55 {0} \ - CONFIG.PSU__DDRC__DQMAP_56_59 {0} \ - CONFIG.PSU__DDRC__DQMAP_60_63 {0} \ - CONFIG.PSU__DDRC__DQMAP_64_67 {0} \ - CONFIG.PSU__DDRC__DQMAP_68_71 {0} \ - CONFIG.PSU__DDRC__DQMAP_8_11 {0} \ - CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \ - CONFIG.PSU__DDRC__ECC {Disabled} \ - CONFIG.PSU__DDRC__ECC_SCRUB {0} \ - CONFIG.PSU__DDRC__ENABLE {1} \ - CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \ - CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {0} \ - CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \ - CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \ - CONFIG.PSU__DDRC__EN_2ND_CLK {0} \ - CONFIG.PSU__DDRC__FGRM {1X} \ - CONFIG.PSU__DDRC__FREQ_MHZ {1} \ - CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP {0} \ - CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__LP_ASR {manual normal} \ - CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \ - CONFIG.PSU__DDRC__PARITY_ENABLE {0} \ - CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \ - CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \ - CONFIG.PSU__DDRC__PLL_BYPASS {0} \ - CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \ - CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \ - CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \ - CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \ - CONFIG.PSU__DDRC__SB_TARGET {15-15-15} \ - CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \ - CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \ - CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \ - CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \ - CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \ - CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \ - CONFIG.PSU__DDRC__T_FAW {30.0} \ - CONFIG.PSU__DDRC__T_RAS_MIN {33} \ - CONFIG.PSU__DDRC__T_RC {47.06} \ - CONFIG.PSU__DDRC__T_RCD {15} \ - CONFIG.PSU__DDRC__T_RP {15} \ - CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \ - CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \ - CONFIG.PSU__DDRC__VREF {1} \ - CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \ - CONFIG.PSU__DDR_QOS_ENABLE {0} \ - CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {} \ - CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {} \ - CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {} \ - CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {} \ - CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {} \ - CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {} \ - CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {} \ - CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {} \ - CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {} \ - CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {} \ - CONFIG.PSU__DDR_QOS_WR_THRSHLD {} \ - CONFIG.PSU__DDR_SW_REFRESH_ENABLED {1} \ - CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \ - CONFIG.PSU__DEVICE_TYPE {RFSOC} \ - CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \ - CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \ - CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \ - CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \ - CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__DLL__ISUSED {1} \ - CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \ - CONFIG.PSU__DP__LANE_SEL {Dual Lower} \ - CONFIG.PSU__DP__REF_CLK_FREQ {27} \ - CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \ - CONFIG.PSU__ENABLE__DDR__REFRESH__SIGNALS {0} \ - CONFIG.PSU__ENET0__FIFO__ENABLE {0} \ - CONFIG.PSU__ENET0__GRP_MDIO__ENABLE {0} \ - CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__ENET0__PTP__ENABLE {0} \ - CONFIG.PSU__ENET0__TSU__ENABLE {0} \ - CONFIG.PSU__ENET1__FIFO__ENABLE {0} \ - CONFIG.PSU__ENET1__GRP_MDIO__ENABLE {0} \ - CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__ENET1__PTP__ENABLE {0} \ - CONFIG.PSU__ENET1__TSU__ENABLE {0} \ - CONFIG.PSU__ENET2__FIFO__ENABLE {0} \ - CONFIG.PSU__ENET2__GRP_MDIO__ENABLE {0} \ - CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__ENET2__PTP__ENABLE {0} \ - CONFIG.PSU__ENET2__TSU__ENABLE {0} \ - CONFIG.PSU__ENET3__FIFO__ENABLE {0} \ - CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \ - CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \ - CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \ - CONFIG.PSU__ENET3__PTP__ENABLE {0} \ - CONFIG.PSU__ENET3__TSU__ENABLE {0} \ - CONFIG.PSU__EN_AXI_STATUS_PORTS {0} \ - CONFIG.PSU__EN_EMIO_TRACE {0} \ - CONFIG.PSU__EP__IP {0} \ - CONFIG.PSU__EXPAND__CORESIGHT {0} \ - CONFIG.PSU__EXPAND__FPD_SLAVES {0} \ - CONFIG.PSU__EXPAND__GIC {0} \ - CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \ - CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \ - CONFIG.PSU__FPDMASTERS_COHERENCY {0} \ - CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \ - CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \ - CONFIG.PSU__FPGA_PL0_ENABLE {1} \ - CONFIG.PSU__FPGA_PL1_ENABLE {1} \ - CONFIG.PSU__FPGA_PL2_ENABLE {0} \ - CONFIG.PSU__FPGA_PL3_ENABLE {0} \ - CONFIG.PSU__FP__POWER__ON {1} \ - CONFIG.PSU__FTM__CTI_IN_0 {0} \ - CONFIG.PSU__FTM__CTI_IN_1 {0} \ - CONFIG.PSU__FTM__CTI_IN_2 {0} \ - CONFIG.PSU__FTM__CTI_IN_3 {0} \ - CONFIG.PSU__FTM__CTI_OUT_0 {0} \ - CONFIG.PSU__FTM__CTI_OUT_1 {0} \ - CONFIG.PSU__FTM__CTI_OUT_2 {0} \ - CONFIG.PSU__FTM__CTI_OUT_3 {0} \ - CONFIG.PSU__FTM__GPI {0} \ - CONFIG.PSU__FTM__GPO {0} \ - CONFIG.PSU__GEM0_COHERENCY {0} \ - CONFIG.PSU__GEM0_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__GEM1_COHERENCY {0} \ - CONFIG.PSU__GEM1_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__GEM2_COHERENCY {0} \ - CONFIG.PSU__GEM2_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__GEM3_COHERENCY {0} \ - CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__GEM__TSU__ENABLE {0} \ - CONFIG.PSU__GEN_IPI_0__MASTER {APU} \ - CONFIG.PSU__GEN_IPI_10__MASTER {NONE} \ - CONFIG.PSU__GEN_IPI_1__MASTER {RPU0} \ - CONFIG.PSU__GEN_IPI_2__MASTER {RPU1} \ - CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \ - CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \ - CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \ - CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \ - CONFIG.PSU__GEN_IPI_7__MASTER {NONE} \ - CONFIG.PSU__GEN_IPI_8__MASTER {NONE} \ - CONFIG.PSU__GEN_IPI_9__MASTER {NONE} \ - CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \ - CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \ - CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__GPIO_EMIO_WIDTH {1} \ - CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__GPIO_EMIO__WIDTH {[94:0]} \ - CONFIG.PSU__GPU_PP0__POWER__ON {0} \ - CONFIG.PSU__GPU_PP1__POWER__ON {0} \ - CONFIG.PSU__GT_REF_CLK__FREQMHZ {33.333} \ - CONFIG.PSU__GT__LINK_SPEED {HBR} \ - CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \ - CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \ - CONFIG.PSU__HIGH_ADDRESS__ENABLE {1} \ - CONFIG.PSU__HPM0_FPD__NUM_READ_THREADS {4} \ - CONFIG.PSU__HPM0_FPD__NUM_WRITE_THREADS {4} \ - CONFIG.PSU__HPM0_LPD__NUM_READ_THREADS {4} \ - CONFIG.PSU__HPM0_LPD__NUM_WRITE_THREADS {4} \ - CONFIG.PSU__HPM1_FPD__NUM_READ_THREADS {4} \ - CONFIG.PSU__HPM1_FPD__NUM_WRITE_THREADS {4} \ - CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \ - CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \ - CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 14 .. 15} \ - CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \ - CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \ - CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \ - CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \ - CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \ - CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \ - CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \ - CONFIG.PSU__IRQ_P2F_ADMA_CHAN__INT {0} \ - CONFIG.PSU__IRQ_P2F_AIB_AXI__INT {0} \ - CONFIG.PSU__IRQ_P2F_AMS__INT {0} \ - CONFIG.PSU__IRQ_P2F_APM_FPD__INT {0} \ - CONFIG.PSU__IRQ_P2F_APU_COMM__INT {0} \ - CONFIG.PSU__IRQ_P2F_APU_CPUMNT__INT {0} \ - CONFIG.PSU__IRQ_P2F_APU_CTI__INT {0} \ - CONFIG.PSU__IRQ_P2F_APU_EXTERR__INT {0} \ - CONFIG.PSU__IRQ_P2F_APU_IPI__INT {0} \ - CONFIG.PSU__IRQ_P2F_APU_L2ERR__INT {0} \ - CONFIG.PSU__IRQ_P2F_APU_PMU__INT {0} \ - CONFIG.PSU__IRQ_P2F_APU_REGS__INT {0} \ - CONFIG.PSU__IRQ_P2F_ATB_LPD__INT {0} \ - CONFIG.PSU__IRQ_P2F_CLKMON__INT {0} \ - CONFIG.PSU__IRQ_P2F_CSUPMU_WDT__INT {0} \ - CONFIG.PSU__IRQ_P2F_DDR_SS__INT {0} \ - CONFIG.PSU__IRQ_P2F_DPDMA__INT {0} \ - CONFIG.PSU__IRQ_P2F_DPORT__INT {0} \ - CONFIG.PSU__IRQ_P2F_EFUSE__INT {0} \ - CONFIG.PSU__IRQ_P2F_ENT3_WAKEUP__INT {0} \ - CONFIG.PSU__IRQ_P2F_ENT3__INT {0} \ - CONFIG.PSU__IRQ_P2F_FPD_APB__INT {0} \ - CONFIG.PSU__IRQ_P2F_FPD_ATB_ERR__INT {0} \ - CONFIG.PSU__IRQ_P2F_FP_WDT__INT {0} \ - CONFIG.PSU__IRQ_P2F_GDMA_CHAN__INT {0} \ - CONFIG.PSU__IRQ_P2F_GPIO__INT {0} \ - CONFIG.PSU__IRQ_P2F_GPU__INT {0} \ - CONFIG.PSU__IRQ_P2F_I2C0__INT {0} \ - CONFIG.PSU__IRQ_P2F_I2C1__INT {0} \ - CONFIG.PSU__IRQ_P2F_LPD_APB__INT {0} \ - CONFIG.PSU__IRQ_P2F_LPD_APM__INT {0} \ - CONFIG.PSU__IRQ_P2F_LP_WDT__INT {0} \ - CONFIG.PSU__IRQ_P2F_OCM_ERR__INT {0} \ - CONFIG.PSU__IRQ_P2F_PCIE_DMA__INT {0} \ - CONFIG.PSU__IRQ_P2F_PCIE_LEGACY__INT {0} \ - CONFIG.PSU__IRQ_P2F_PCIE_MSC__INT {0} \ - CONFIG.PSU__IRQ_P2F_PCIE_MSI__INT {0} \ - CONFIG.PSU__IRQ_P2F_PL_IPI__INT {0} \ - CONFIG.PSU__IRQ_P2F_QSPI__INT {0} \ - CONFIG.PSU__IRQ_P2F_R5_CORE0_ECC_ERR__INT {0} \ - CONFIG.PSU__IRQ_P2F_R5_CORE1_ECC_ERR__INT {0} \ - CONFIG.PSU__IRQ_P2F_RPU_IPI__INT {0} \ - CONFIG.PSU__IRQ_P2F_RPU_PERMON__INT {0} \ - CONFIG.PSU__IRQ_P2F_RTC_ALARM__INT {0} \ - CONFIG.PSU__IRQ_P2F_RTC_SECONDS__INT {0} \ - CONFIG.PSU__IRQ_P2F_SATA__INT {0} \ - CONFIG.PSU__IRQ_P2F_SDIO1_WAKE__INT {0} \ - CONFIG.PSU__IRQ_P2F_SDIO1__INT {0} \ - CONFIG.PSU__IRQ_P2F_TTC0__INT0 {0} \ - CONFIG.PSU__IRQ_P2F_TTC0__INT1 {0} \ - CONFIG.PSU__IRQ_P2F_TTC0__INT2 {0} \ - CONFIG.PSU__IRQ_P2F_TTC1__INT0 {0} \ - CONFIG.PSU__IRQ_P2F_TTC1__INT1 {0} \ - CONFIG.PSU__IRQ_P2F_TTC1__INT2 {0} \ - CONFIG.PSU__IRQ_P2F_TTC2__INT0 {0} \ - CONFIG.PSU__IRQ_P2F_TTC2__INT1 {0} \ - CONFIG.PSU__IRQ_P2F_TTC2__INT2 {0} \ - CONFIG.PSU__IRQ_P2F_TTC3__INT0 {0} \ - CONFIG.PSU__IRQ_P2F_TTC3__INT1 {0} \ - CONFIG.PSU__IRQ_P2F_TTC3__INT2 {0} \ - CONFIG.PSU__IRQ_P2F_UART0__INT {0} \ - CONFIG.PSU__IRQ_P2F_UART1__INT {0} \ - CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT0 {0} \ - CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT1 {0} \ - CONFIG.PSU__IRQ_P2F_USB3_OTG__INT0 {0} \ - CONFIG.PSU__IRQ_P2F_USB3_OTG__INT1 {0} \ - CONFIG.PSU__IRQ_P2F_USB3_PMU_WAKEUP__INT {0} \ - CONFIG.PSU__IRQ_P2F_XMPU_FPD__INT {0} \ - CONFIG.PSU__IRQ_P2F_XMPU_LPD__INT {0} \ - CONFIG.PSU__IRQ_P2F__INTF_FPD_SMMU__INT {0} \ - CONFIG.PSU__IRQ_P2F__INTF_PPD_CCI__INT {0} \ - CONFIG.PSU__L2_BANK0__POWER__ON {1} \ - CONFIG.PSU__LPDMA0_COHERENCY {0} \ - CONFIG.PSU__LPDMA1_COHERENCY {0} \ - CONFIG.PSU__LPDMA2_COHERENCY {0} \ - CONFIG.PSU__LPDMA3_COHERENCY {0} \ - CONFIG.PSU__LPDMA4_COHERENCY {0} \ - CONFIG.PSU__LPDMA5_COHERENCY {0} \ - CONFIG.PSU__LPDMA6_COHERENCY {0} \ - CONFIG.PSU__LPDMA7_COHERENCY {0} \ - CONFIG.PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT {APB} \ - CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \ - CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \ - CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \ - CONFIG.PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST {1} \ - CONFIG.PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST {1} \ - CONFIG.PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST {1} \ - CONFIG.PSU__NAND_COHERENCY {0} \ - CONFIG.PSU__NAND_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__NAND__CHIP_ENABLE__ENABLE {0} \ - CONFIG.PSU__NAND__DATA_STROBE__ENABLE {0} \ - CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__NAND__READY0_BUSY__ENABLE {0} \ - CONFIG.PSU__NAND__READY1_BUSY__ENABLE {0} \ - CONFIG.PSU__NAND__READY_BUSY__ENABLE {0} \ - CONFIG.PSU__NUM_FABRIC_RESETS {1} \ - CONFIG.PSU__OCM_BANK0__POWER__ON {1} \ - CONFIG.PSU__OCM_BANK1__POWER__ON {1} \ - CONFIG.PSU__OCM_BANK2__POWER__ON {1} \ - CONFIG.PSU__OCM_BANK3__POWER__ON {1} \ - CONFIG.PSU__OVERRIDE_HPX_QOS {0} \ - CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \ - CONFIG.PSU__PCIE__ACS_VIOLAION {0} \ - CONFIG.PSU__PCIE__ACS_VIOLATION {0} \ - CONFIG.PSU__PCIE__AER_CAPABILITY {0} \ - CONFIG.PSU__PCIE__ATOMICOP_EGRESS_BLOCKED {0} \ - CONFIG.PSU__PCIE__BAR0_64BIT {0} \ - CONFIG.PSU__PCIE__BAR0_ENABLE {0} \ - CONFIG.PSU__PCIE__BAR0_PREFETCHABLE {0} \ - CONFIG.PSU__PCIE__BAR0_VAL {} \ - CONFIG.PSU__PCIE__BAR1_64BIT {0} \ - CONFIG.PSU__PCIE__BAR1_ENABLE {0} \ - CONFIG.PSU__PCIE__BAR1_PREFETCHABLE {0} \ - CONFIG.PSU__PCIE__BAR1_VAL {} \ - CONFIG.PSU__PCIE__BAR2_64BIT {0} \ - CONFIG.PSU__PCIE__BAR2_ENABLE {0} \ - CONFIG.PSU__PCIE__BAR2_PREFETCHABLE {0} \ - CONFIG.PSU__PCIE__BAR2_VAL {} \ - CONFIG.PSU__PCIE__BAR3_64BIT {0} \ - CONFIG.PSU__PCIE__BAR3_ENABLE {0} \ - CONFIG.PSU__PCIE__BAR3_PREFETCHABLE {0} \ - CONFIG.PSU__PCIE__BAR3_VAL {} \ - CONFIG.PSU__PCIE__BAR4_64BIT {0} \ - CONFIG.PSU__PCIE__BAR4_ENABLE {0} \ - CONFIG.PSU__PCIE__BAR4_PREFETCHABLE {0} \ - CONFIG.PSU__PCIE__BAR4_VAL {} \ - CONFIG.PSU__PCIE__BAR5_64BIT {0} \ - CONFIG.PSU__PCIE__BAR5_ENABLE {0} \ - CONFIG.PSU__PCIE__BAR5_PREFETCHABLE {0} \ - CONFIG.PSU__PCIE__BAR5_VAL {} \ - CONFIG.PSU__PCIE__CLASS_CODE_VALUE {} \ - CONFIG.PSU__PCIE__COMPLETER_ABORT {0} \ - CONFIG.PSU__PCIE__COMPLTION_TIMEOUT {0} \ - CONFIG.PSU__PCIE__CORRECTABLE_INT_ERR {0} \ - CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {0} \ - CONFIG.PSU__PCIE__ECRC_CHECK {0} \ - CONFIG.PSU__PCIE__ECRC_ERR {0} \ - CONFIG.PSU__PCIE__ECRC_GEN {0} \ - CONFIG.PSU__PCIE__EROM_ENABLE {0} \ - CONFIG.PSU__PCIE__EROM_VAL {} \ - CONFIG.PSU__PCIE__FLOW_CONTROL_ERR {0} \ - CONFIG.PSU__PCIE__FLOW_CONTROL_PROTOCOL_ERR {0} \ - CONFIG.PSU__PCIE__HEADER_LOG_OVERFLOW {0} \ - CONFIG.PSU__PCIE__INTX_GENERATION {0} \ - CONFIG.PSU__PCIE__LANE0__ENABLE {0} \ - CONFIG.PSU__PCIE__LANE1__ENABLE {0} \ - CONFIG.PSU__PCIE__LANE2__ENABLE {0} \ - CONFIG.PSU__PCIE__LANE3__ENABLE {0} \ - CONFIG.PSU__PCIE__MC_BLOCKED_TLP {0} \ - CONFIG.PSU__PCIE__MSIX_BAR_INDICATOR {} \ - CONFIG.PSU__PCIE__MSIX_CAPABILITY {0} \ - CONFIG.PSU__PCIE__MSIX_PBA_BAR_INDICATOR {} \ - CONFIG.PSU__PCIE__MSIX_PBA_OFFSET {0} \ - CONFIG.PSU__PCIE__MSIX_TABLE_OFFSET {0} \ - CONFIG.PSU__PCIE__MSIX_TABLE_SIZE {0} \ - CONFIG.PSU__PCIE__MSI_64BIT_ADDR_CAPABLE {0} \ - CONFIG.PSU__PCIE__MSI_CAPABILITY {0} \ - CONFIG.PSU__PCIE__MULTIHEADER {0} \ - CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {1} \ - CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {0} \ - CONFIG.PSU__PCIE__PERM_ROOT_ERR_UPDATE {0} \ - CONFIG.PSU__PCIE__RECEIVER_ERR {0} \ - CONFIG.PSU__PCIE__RECEIVER_OVERFLOW {0} \ - CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \ - CONFIG.PSU__PCIE__SURPRISE_DOWN {0} \ - CONFIG.PSU__PCIE__TLP_PREFIX_BLOCKED {0} \ - CONFIG.PSU__PCIE__UNCORRECTABL_INT_ERR {0} \ - CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__PL_CLK0_BUF {TRUE} \ - CONFIG.PSU__PL_CLK1_BUF {TRUE} \ - CONFIG.PSU__PL_CLK2_BUF {FALSE} \ - CONFIG.PSU__PL_CLK3_BUF {FALSE} \ - CONFIG.PSU__PL__POWER__ON {1} \ - CONFIG.PSU__PMU_COHERENCY {0} \ - CONFIG.PSU__PMU__AIBACK__ENABLE {0} \ - CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \ - CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \ - CONFIG.PSU__PMU__GPI0__ENABLE {0} \ - CONFIG.PSU__PMU__GPI1__ENABLE {0} \ - CONFIG.PSU__PMU__GPI2__ENABLE {0} \ - CONFIG.PSU__PMU__GPI3__ENABLE {0} \ - CONFIG.PSU__PMU__GPI4__ENABLE {0} \ - CONFIG.PSU__PMU__GPI5__ENABLE {0} \ - CONFIG.PSU__PMU__GPO0__ENABLE {1} \ - CONFIG.PSU__PMU__GPO0__IO {MIO 32} \ - CONFIG.PSU__PMU__GPO1__ENABLE {1} \ - CONFIG.PSU__PMU__GPO1__IO {MIO 33} \ - CONFIG.PSU__PMU__GPO2__ENABLE {1} \ - CONFIG.PSU__PMU__GPO2__IO {MIO 34} \ - CONFIG.PSU__PMU__GPO2__POLARITY {low} \ - CONFIG.PSU__PMU__GPO3__ENABLE {1} \ - CONFIG.PSU__PMU__GPO3__IO {MIO 35} \ - CONFIG.PSU__PMU__GPO3__POLARITY {low} \ - CONFIG.PSU__PMU__GPO4__ENABLE {1} \ - CONFIG.PSU__PMU__GPO4__IO {MIO 36} \ - CONFIG.PSU__PMU__GPO4__POLARITY {low} \ - CONFIG.PSU__PMU__GPO5__ENABLE {1} \ - CONFIG.PSU__PMU__GPO5__IO {MIO 37} \ - CONFIG.PSU__PMU__GPO5__POLARITY {low} \ - CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__PMU__PLERROR__ENABLE {0} \ - CONFIG.PSU__PRESET_APPLIED {1} \ - CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \ - CONFIG.PSU__PROTECTION__DEBUG {0} \ - CONFIG.PSU__PROTECTION__ENABLE {0} \ - CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD010000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD040000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD5D0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem} \ - CONFIG.PSU__PROTECTION__LOCK_UNUSED_SEGMENTS {0} \ - CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF5E0000; SIZE:2560; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFCC0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF180000; SIZE:768; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF410000; SIZE:640; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFA70000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|SA:0xFF5E0000 ; SIZE:2560; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFFCC0000 ; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF180000 ; SIZE:768; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF9A0000 ; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem} \ - CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;1|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \ - CONFIG.PSU__PROTECTION__MASTERS_TZ {GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure} \ - CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \ - CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \ - CONFIG.PSU__PROTECTION__SLAVES { \ - LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1 \ - } \ - CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU|Secure Subsystem:} \ - CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \ - CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \ - CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \ - CONFIG.PSU__QSPI_COHERENCY {0} \ - CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \ - CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \ - CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \ - CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 12} \ - CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel} \ - CONFIG.PSU__REPORT__DBGLOG {0} \ - CONFIG.PSU__RPU_COHERENCY {0} \ - CONFIG.PSU__RPU__POWER__ON {1} \ - CONFIG.PSU__SATA__LANE0__ENABLE {0} \ - CONFIG.PSU__SATA__LANE1__ENABLE {1} \ - CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \ - CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__SATA__REF_CLK_FREQ {125} \ - CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk3} \ - CONFIG.PSU__SAXIGP0__DATA_WIDTH {128} \ - CONFIG.PSU__SD0_COHERENCY {0} \ - CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__SD0__GRP_CD__ENABLE {0} \ - CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \ - CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \ - CONFIG.PSU__SD0__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__SD0__RESET__ENABLE {0} \ - CONFIG.PSU__SD1_COHERENCY {0} \ - CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__SD1__DATA_TRANSFER_MODE {8Bit} \ - CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \ - CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \ - CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \ - CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \ - CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 39 .. 51} \ - CONFIG.PSU__SD1__RESET__ENABLE {0} \ - CONFIG.PSU__SD1__SLOT_TYPE {SD 3.0} \ - CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE {0} \ - CONFIG.PSU__SPI0__GRP_SS0__ENABLE {0} \ - CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \ - CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \ - CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__SPI1__GRP_SS0__ENABLE {0} \ - CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \ - CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \ - CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \ - CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__SWDT0__PERIPHERAL__IO {NA} \ - CONFIG.PSU__SWDT0__RESET__ENABLE {0} \ - CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \ - CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__SWDT1__PERIPHERAL__IO {NA} \ - CONFIG.PSU__SWDT1__RESET__ENABLE {0} \ - CONFIG.PSU__TCM0A__POWER__ON {1} \ - CONFIG.PSU__TCM0B__POWER__ON {1} \ - CONFIG.PSU__TCM1A__POWER__ON {1} \ - CONFIG.PSU__TCM1B__POWER__ON {1} \ - CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__TRACE__INTERNAL_WIDTH {32} \ - CONFIG.PSU__TRACE__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__TRISTATE__INVERTED {1} \ - CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \ - CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \ - CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__TTC0__PERIPHERAL__IO {NA} \ - CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \ - CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \ - CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__TTC1__PERIPHERAL__IO {NA} \ - CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \ - CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \ - CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__TTC2__PERIPHERAL__IO {NA} \ - CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \ - CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \ - CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__TTC3__PERIPHERAL__IO {NA} \ - CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \ - CONFIG.PSU__UART0_LOOP_UART1__ENABLE {0} \ - CONFIG.PSU__UART0__BAUD_RATE {115200} \ - CONFIG.PSU__UART0__MODEM__ENABLE {0} \ - CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \ - CONFIG.PSU__UART1__BAUD_RATE {115200} \ - CONFIG.PSU__UART1__MODEM__ENABLE {0} \ - CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__UART1__PERIPHERAL__IO {EMIO} \ - CONFIG.PSU__USB0_COHERENCY {0} \ - CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \ - CONFIG.PSU__USB0__REF_CLK_FREQ {26} \ - CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \ - CONFIG.PSU__USB0__RESET__ENABLE {0} \ - CONFIG.PSU__USB1_COHERENCY {0} \ - CONFIG.PSU__USB1__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__USB1__RESET__ENABLE {0} \ - CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \ - CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \ - CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \ - CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \ - CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \ - CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__USB__RESET__MODE {Boot Pin} \ - CONFIG.PSU__USB__RESET__POLARITY {Active Low} \ - CONFIG.PSU__USE_DIFF_RW_CLK_GP0 {0} \ - CONFIG.PSU__USE__ADMA {0} \ - CONFIG.PSU__USE__APU_LEGACY_INTERRUPT {0} \ - CONFIG.PSU__USE__AUDIO {0} \ - CONFIG.PSU__USE__CLK {0} \ - CONFIG.PSU__USE__CLK0 {0} \ - CONFIG.PSU__USE__CLK1 {0} \ - CONFIG.PSU__USE__CLK2 {0} \ - CONFIG.PSU__USE__CLK3 {0} \ - CONFIG.PSU__USE__CROSS_TRIGGER {0} \ - CONFIG.PSU__USE__DDR_INTF_REQUESTED {0} \ - CONFIG.PSU__USE__DEBUG__TEST {0} \ - CONFIG.PSU__USE__EVENT_RPU {0} \ - CONFIG.PSU__USE__FABRIC__RST {1} \ - CONFIG.PSU__USE__FTM {0} \ - CONFIG.PSU__USE__GDMA {0} \ - CONFIG.PSU__USE__IRQ {0} \ - CONFIG.PSU__USE__IRQ0 {1} \ - CONFIG.PSU__USE__IRQ1 {0} \ - CONFIG.PSU__USE__M_AXI_GP0 {1} \ - CONFIG.PSU__USE__M_AXI_GP1 {0} \ - CONFIG.PSU__USE__M_AXI_GP2 {0} \ - CONFIG.PSU__USE__PROC_EVENT_BUS {0} \ - CONFIG.PSU__USE__RPU_LEGACY_INTERRUPT {0} \ - CONFIG.PSU__USE__RST0 {0} \ - CONFIG.PSU__USE__RST1 {0} \ - CONFIG.PSU__USE__RST2 {0} \ - CONFIG.PSU__USE__RST3 {0} \ - CONFIG.PSU__USE__RTC {0} \ - CONFIG.PSU__USE__STM {0} \ - CONFIG.PSU__USE__S_AXI_ACE {0} \ - CONFIG.PSU__USE__S_AXI_ACP {0} \ - CONFIG.PSU__USE__S_AXI_GP0 {1} \ - CONFIG.PSU__USE__S_AXI_GP1 {0} \ - CONFIG.PSU__USE__S_AXI_GP2 {0} \ - CONFIG.PSU__USE__S_AXI_GP3 {0} \ - CONFIG.PSU__USE__S_AXI_GP4 {0} \ - CONFIG.PSU__USE__S_AXI_GP5 {0} \ - CONFIG.PSU__USE__S_AXI_GP6 {0} \ - CONFIG.PSU__USE__USB3_0_HUB {0} \ - CONFIG.PSU__USE__USB3_1_HUB {0} \ - CONFIG.PSU__USE__VIDEO {0} \ - CONFIG.PSU__VIDEO_REF_CLK__ENABLE {0} \ - CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ {33.333} \ - CONFIG.QSPI_BOARD_INTERFACE {custom} \ - CONFIG.SATA_BOARD_INTERFACE {custom} \ - CONFIG.SD0_BOARD_INTERFACE {custom} \ - CONFIG.SD1_BOARD_INTERFACE {custom} \ - CONFIG.SPI0_BOARD_INTERFACE {custom} \ - CONFIG.SPI1_BOARD_INTERFACE {custom} \ - CONFIG.SUBPRESET1 {Custom} \ - CONFIG.SUBPRESET2 {Custom} \ - CONFIG.SWDT0_BOARD_INTERFACE {custom} \ - CONFIG.SWDT1_BOARD_INTERFACE {custom} \ - CONFIG.TRACE_BOARD_INTERFACE {custom} \ - CONFIG.TTC0_BOARD_INTERFACE {custom} \ - CONFIG.TTC1_BOARD_INTERFACE {custom} \ - CONFIG.TTC2_BOARD_INTERFACE {custom} \ - CONFIG.TTC3_BOARD_INTERFACE {custom} \ - CONFIG.UART0_BOARD_INTERFACE {custom} \ - CONFIG.UART1_BOARD_INTERFACE {custom} \ - CONFIG.USB0_BOARD_INTERFACE {custom} \ - CONFIG.USB1_BOARD_INTERFACE {custom} \ - ] $zynq_ultra_ps_e_0 - - # Create interface connections - connect_bd_intf_net -intf_net adc0_clk_1 [get_bd_intf_ports adc0_clk] [get_bd_intf_pins usp_rf_data_converter_0/adc0_clk] - connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins axi_bram_ctrl_0_bram/BRAM_PORTA] - connect_bd_intf_net -intf_net axi_dma_0_M_AXIS_MM2S [get_bd_intf_pins axi_dma_tproc/M_AXIS_MM2S] [get_bd_intf_pins axis_tproc64x32_x8_0/s0_axis] - connect_bd_intf_net -intf_net axi_dma_0_M_AXI_MM2S [get_bd_intf_pins axi_dma_tproc/M_AXI_MM2S] [get_bd_intf_pins axi_smc/S00_AXI] - connect_bd_intf_net -intf_net axi_dma_0_M_AXI_S2MM [get_bd_intf_pins axi_dma_tproc/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S01_AXI] - connect_bd_intf_net -intf_net axi_dma_1_M_AXIS_MM2S [get_bd_intf_pins axi_dma_gen/M_AXIS_MM2S] [get_bd_intf_pins axis_switch_gen/S00_AXIS] - connect_bd_intf_net -intf_net axi_dma_1_M_AXI_MM2S [get_bd_intf_pins axi_dma_gen/M_AXI_MM2S] [get_bd_intf_pins axi_smc/S02_AXI] - connect_bd_intf_net -intf_net axi_dma_avg_M_AXI_S2MM [get_bd_intf_pins axi_dma_avg/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S03_AXI] - connect_bd_intf_net -intf_net axi_dma_buf_M_AXI_S2MM [get_bd_intf_pins axi_dma_buf/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S04_AXI] - connect_bd_intf_net -intf_net axi_smc_M00_AXI [get_bd_intf_pins axi_smc/M00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HPC0_FPD] - connect_bd_intf_net -intf_net axis_avg_buffer_0_m0_axis [get_bd_intf_pins axis_avg_buffer_0/m0_axis] [get_bd_intf_pins axis_switch_avg/S00_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_0_m1_axis [get_bd_intf_pins axis_avg_buffer_0/m1_axis] [get_bd_intf_pins axis_switch_buf/S00_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_0_m2_axis [get_bd_intf_pins axis_avg_buffer_0/m2_axis] [get_bd_intf_pins axis_clk_cnvrt_avg_0/S_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_1_m0_axis [get_bd_intf_pins axis_avg_buffer_1/m0_axis] [get_bd_intf_pins axis_switch_avg/S01_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_1_m1_axis [get_bd_intf_pins axis_avg_buffer_1/m1_axis] [get_bd_intf_pins axis_switch_buf/S01_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_1_m2_axis [get_bd_intf_pins axis_avg_buffer_1/m2_axis] [get_bd_intf_pins axis_clk_cnvrt_avg_1/S_AXIS] - connect_bd_intf_net -intf_net axis_cdcsync_v1_0_m0_axis [get_bd_intf_pins axis_cdcsync_v1_0/m0_axis] [get_bd_intf_pins axis_signal_gen_v6_0/s1_axis] - connect_bd_intf_net -intf_net axis_cdcsync_v1_0_m1_axis [get_bd_intf_pins axis_cdcsync_v1_0/m1_axis] [get_bd_intf_pins axis_signal_gen_v6_1/s1_axis] - connect_bd_intf_net -intf_net axis_cdcsync_v1_0_m2_axis [get_bd_intf_pins axis_cdcsync_v1_0/m2_axis] [get_bd_intf_pins axis_signal_gen_v6_2/s1_axis] - connect_bd_intf_net -intf_net axis_cdcsync_v1_1_m0_axis [get_bd_intf_pins axis_cdcsync_v1_1/m0_axis] [get_bd_intf_pins axis_signal_gen_v6_3/s1_axis] - connect_bd_intf_net -intf_net axis_cdcsync_v1_1_m1_axis [get_bd_intf_pins axis_cdcsync_v1_1/m1_axis] [get_bd_intf_pins axis_signal_gen_v6_4/s1_axis] - connect_bd_intf_net -intf_net axis_cdcsync_v1_1_m2_axis [get_bd_intf_pins axis_cdcsync_v1_1/m2_axis] [get_bd_intf_pins axis_signal_gen_v6_5/s1_axis] - connect_bd_intf_net -intf_net axis_cdcsync_v1_1_m3_axis [get_bd_intf_pins axis_cdcsync_v1_1/m3_axis] [get_bd_intf_pins axis_signal_gen_v6_6/s1_axis] - connect_bd_intf_net -intf_net axis_clk_cnvrt_avg_0_M_AXIS [get_bd_intf_pins axis_clk_cnvrt_avg_0/M_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/s1_axis] - connect_bd_intf_net -intf_net axis_clk_cnvrt_avg_1_M_AXIS [get_bd_intf_pins axis_clk_cnvrt_avg_1/M_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/s2_axis] - connect_bd_intf_net -intf_net axis_constant_0_m_axis [get_bd_intf_pins axis_constant_0/m_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/s3_axis] - connect_bd_intf_net -intf_net axis_constant_1_m_axis [get_bd_intf_pins axis_constant_1/m_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/s4_axis] - connect_bd_intf_net -intf_net axis_constant_2_m_axis [get_bd_intf_pins axis_cdcsync_v1_0/s3_axis] [get_bd_intf_pins axis_constant_2/m_axis] - connect_bd_intf_net -intf_net axis_readout_v2_0_m1_axis [get_bd_intf_pins axis_avg_buffer_0/s_axis] [get_bd_intf_pins axis_readout_v2_0/m1_axis] - connect_bd_intf_net -intf_net axis_readout_v2_1_m1_axis [get_bd_intf_pins axis_avg_buffer_1/s_axis] [get_bd_intf_pins axis_readout_v2_1/m1_axis] - connect_bd_intf_net -intf_net axis_register_slice_0_M_AXIS [get_bd_intf_pins axis_readout_v2_0/s_axis] [get_bd_intf_pins axis_register_slice_0/M_AXIS] - connect_bd_intf_net -intf_net axis_register_slice_1_M_AXIS [get_bd_intf_pins axis_readout_v2_1/s_axis] [get_bd_intf_pins axis_register_slice_1/M_AXIS] - connect_bd_intf_net -intf_net axis_signal_gen_v6_0_m_axis [get_bd_intf_pins axis_signal_gen_v6_0/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s00_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v6_1_m_axis [get_bd_intf_pins axis_signal_gen_v6_1/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s01_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v6_2_m_axis [get_bd_intf_pins axis_signal_gen_v6_2/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s02_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v6_3_m_axis [get_bd_intf_pins axis_signal_gen_v6_3/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s10_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v6_4_m_axis [get_bd_intf_pins axis_signal_gen_v6_4/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s11_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v6_5_m_axis [get_bd_intf_pins axis_signal_gen_v6_5/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s12_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v6_6_m_axis [get_bd_intf_pins axis_signal_gen_v6_6/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s13_axis] - connect_bd_intf_net -intf_net axis_switch_0_M00_AXIS [get_bd_intf_pins axis_signal_gen_v6_0/s0_axis] [get_bd_intf_pins axis_switch_gen/M00_AXIS] - connect_bd_intf_net -intf_net axis_switch_0_M01_AXIS [get_bd_intf_pins axis_signal_gen_v6_1/s0_axis] [get_bd_intf_pins axis_switch_gen/M01_AXIS] - connect_bd_intf_net -intf_net axis_switch_0_M02_AXIS [get_bd_intf_pins axis_signal_gen_v6_2/s0_axis] [get_bd_intf_pins axis_switch_gen/M02_AXIS] - connect_bd_intf_net -intf_net axis_switch_0_M03_AXIS [get_bd_intf_pins axis_signal_gen_v6_3/s0_axis] [get_bd_intf_pins axis_switch_gen/M03_AXIS] - connect_bd_intf_net -intf_net axis_switch_0_M04_AXIS [get_bd_intf_pins axis_signal_gen_v6_4/s0_axis] [get_bd_intf_pins axis_switch_gen/M04_AXIS] - connect_bd_intf_net -intf_net axis_switch_0_M05_AXIS [get_bd_intf_pins axis_signal_gen_v6_5/s0_axis] [get_bd_intf_pins axis_switch_gen/M05_AXIS] - connect_bd_intf_net -intf_net axis_switch_0_M06_AXIS [get_bd_intf_pins axis_signal_gen_v6_6/s0_axis] [get_bd_intf_pins axis_switch_gen/M06_AXIS] - connect_bd_intf_net -intf_net axis_switch_avg_M00_AXIS [get_bd_intf_pins axi_dma_avg/S_AXIS_S2MM] [get_bd_intf_pins axis_switch_avg/M00_AXIS] - connect_bd_intf_net -intf_net axis_switch_buf_M00_AXIS [get_bd_intf_pins axi_dma_buf/S_AXIS_S2MM] [get_bd_intf_pins axis_switch_buf/M00_AXIS] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m0_axis [get_bd_intf_pins axi_dma_tproc/S_AXIS_S2MM] [get_bd_intf_pins axis_tproc64x32_x8_0/m0_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m1_axis [get_bd_intf_pins axis_set_reg_0/s_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m1_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m2_axis [get_bd_intf_pins axis_cdcsync_v1_0/s0_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m2_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m3_axis [get_bd_intf_pins axis_cdcsync_v1_0/s1_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m3_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m4_axis [get_bd_intf_pins axis_cdcsync_v1_0/s2_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m4_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m5_axis [get_bd_intf_pins axis_cdcsync_v1_1/s0_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m5_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m6_axis [get_bd_intf_pins axis_cdcsync_v1_1/s1_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m6_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m7_axis [get_bd_intf_pins axis_cdcsync_v1_1/s2_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m7_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m8_axis [get_bd_intf_pins axis_cdcsync_v1_1/s3_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m8_axis] - connect_bd_intf_net -intf_net dac0_clk_1 [get_bd_intf_ports dac0_clk] [get_bd_intf_pins usp_rf_data_converter_0/dac0_clk] - connect_bd_intf_net -intf_net dac1_clk_1 [get_bd_intf_ports dac1_clk] [get_bd_intf_pins usp_rf_data_converter_0/dac1_clk] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins axi_dma_tproc/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M01_AXI [get_bd_intf_pins axis_tproc64x32_x8_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M01_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M02_AXI [get_bd_intf_pins axis_signal_gen_v6_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M02_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M03_AXI [get_bd_intf_pins axis_signal_gen_v6_1/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M03_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M04_AXI [get_bd_intf_pins axis_signal_gen_v6_2/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M04_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M05_AXI [get_bd_intf_pins axis_signal_gen_v6_3/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M05_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M06_AXI [get_bd_intf_pins axi_dma_gen/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M06_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M07_AXI [get_bd_intf_pins axis_switch_gen/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M07_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M08_AXI [get_bd_intf_pins ps8_0_axi_periph/M08_AXI] [get_bd_intf_pins usp_rf_data_converter_0/s_axi] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M09_AXI [get_bd_intf_pins axis_avg_buffer_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M09_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M10_AXI [get_bd_intf_pins axis_avg_buffer_1/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M10_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M11_AXI [get_bd_intf_pins axis_signal_gen_v6_4/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M11_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M12_AXI [get_bd_intf_pins axis_signal_gen_v6_5/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M12_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M13_AXI [get_bd_intf_pins axi_bram_ctrl_0/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M13_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M14_AXI [get_bd_intf_pins axis_signal_gen_v6_6/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M14_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M15_AXI [get_bd_intf_pins axis_readout_v2_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M15_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M16_AXI [get_bd_intf_pins axis_readout_v2_1/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M16_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M17_AXI [get_bd_intf_pins axis_switch_avg/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M17_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M18_AXI [get_bd_intf_pins axis_switch_buf/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M18_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M19_AXI [get_bd_intf_pins axi_dma_avg/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M19_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M20_AXI [get_bd_intf_pins axi_dma_buf/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M20_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M21_AXI [get_bd_intf_pins attn_spi/AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M21_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M22_AXI [get_bd_intf_pins dac_bias_spi/AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M22_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M23_AXI [get_bd_intf_pins lo_spi/AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M23_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M24_AXI [get_bd_intf_pins ps8_0_axi_periph/M24_AXI] [get_bd_intf_pins psf_spi/AXI_LITE] - connect_bd_intf_net -intf_net sysref_in_1 [get_bd_intf_ports sysref_in] [get_bd_intf_pins usp_rf_data_converter_0/sysref_in] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_m00_axis [get_bd_intf_pins axis_register_slice_0/S_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/m00_axis] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_m02_axis [get_bd_intf_pins axis_register_slice_1/S_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/m02_axis] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout00 [get_bd_intf_ports vout0] [get_bd_intf_pins usp_rf_data_converter_0/vout00] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout01 [get_bd_intf_ports vout1] [get_bd_intf_pins usp_rf_data_converter_0/vout01] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout02 [get_bd_intf_ports vout2] [get_bd_intf_pins usp_rf_data_converter_0/vout02] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout10 [get_bd_intf_ports vout3] [get_bd_intf_pins usp_rf_data_converter_0/vout10] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout11 [get_bd_intf_ports vout4] [get_bd_intf_pins usp_rf_data_converter_0/vout11] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout12 [get_bd_intf_ports vout5] [get_bd_intf_pins usp_rf_data_converter_0/vout12] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout13 [get_bd_intf_ports vout6] [get_bd_intf_pins usp_rf_data_converter_0/vout13] - connect_bd_intf_net -intf_net vin0_1 [get_bd_intf_ports vin0] [get_bd_intf_pins usp_rf_data_converter_0/vin0_01] - connect_bd_intf_net -intf_net vin1_1 [get_bd_intf_ports vin1] [get_bd_intf_pins usp_rf_data_converter_0/vin0_23] - connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD] - - # Create port connections - connect_bd_net -net LO_MISO0_1 [get_bd_ports LO_MISO0] [get_bd_pins lo_spi_mux_v2_0/sdo0_in] - connect_bd_net -net LO_MISO1_1 [get_bd_ports LO_MISO1] [get_bd_pins lo_spi_mux_v2_0/sdo1_in] - connect_bd_net -net LO_MISO2_1 [get_bd_ports LO_MISO2] [get_bd_pins lo_spi_mux_v2_0/sdo2_in] - connect_bd_net -net PMOD1_0_LS_1 [get_bd_ports PMOD1_0_LS] [get_bd_pins axis_tproc64x32_x8_0/start] - connect_bd_net -net axi_bram_ctrl_0_bram_doutb [get_bd_pins axi_bram_ctrl_0_bram/doutb] [get_bd_pins axis_tproc64x32_x8_0/pmem_do] - connect_bd_net -net axi_quad_spi_0_io0_o [get_bd_ports ATTN_SI] [get_bd_pins attn_spi/io0_o] - connect_bd_net -net axi_quad_spi_0_sck_o [get_bd_ports ATTN_CLK] [get_bd_pins attn_spi/sck_o] - connect_bd_net -net axi_quad_spi_0_ss_o [get_bd_ports ATTN_LE] [get_bd_pins attn_spi/ss_o] - connect_bd_net -net axis_set_reg_0_dout [get_bd_pins axis_set_reg_0/dout] [get_bd_pins vect2bits_16_0/din] - connect_bd_net -net axis_tproc64x32_x8_0_pmem_addr [get_bd_pins axi_bram_ctrl_0_bram/addrb] [get_bd_pins axis_tproc64x32_x8_0/pmem_addr] - connect_bd_net -net bias_constant_0_dout [get_bd_ports LO_SYNC] [get_bd_pins lo_sync_constant_0/dout] - connect_bd_net -net bias_constant_1_dout [get_bd_ports BIAS_CLR] [get_bd_pins bias_constant_1/dout] - connect_bd_net -net clk_adc0_x2_clk_out1 [get_bd_pins axis_avg_buffer_0/s_axis_aclk] [get_bd_pins axis_avg_buffer_1/s_axis_aclk] [get_bd_pins axis_readout_v2_0/aclk] [get_bd_pins axis_readout_v2_1/aclk] [get_bd_pins axis_register_slice_0/aclk] [get_bd_pins axis_register_slice_1/aclk] [get_bd_pins clk_adc0_x2/clk_out1] [get_bd_pins rst_adc0_x2/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/m0_axis_aclk] - connect_bd_net -net clk_adc0_x2_locked [get_bd_pins clk_adc0_x2/locked] [get_bd_pins rst_adc0_x2/dcm_locked] - connect_bd_net -net dac_bias_spi_io0_o [get_bd_ports BIAS_SDI] [get_bd_pins dac_bias_spi/io0_o] - connect_bd_net -net dac_bias_spi_sck_o [get_bd_ports BIAS_SCLK] [get_bd_pins dac_bias_spi/sck_o] - connect_bd_net -net dac_bias_spi_ss_o [get_bd_ports BIAS_S] [get_bd_pins dac_bias_spi/ss_o] - connect_bd_net -net io1_i_0_1 [get_bd_ports SDO] [get_bd_pins psf_spi/io1_i] - connect_bd_net -net io1_i_0_2 [get_bd_ports BIAS_SDO] [get_bd_pins dac_bias_spi/io1_i] - connect_bd_net -net lo_spi_io0_o [get_bd_ports LO_MOSI] [get_bd_pins lo_spi/io0_o] - connect_bd_net -net lo_spi_mux_v2_0_sdo_out [get_bd_pins lo_spi/io1_i] [get_bd_pins lo_spi_mux_v2_0/sdo_out] - connect_bd_net -net lo_spi_mux_v2_0_ss0_out [get_bd_ports LO_CS0] [get_bd_pins lo_spi_mux_v2_0/ss0_out] - connect_bd_net -net lo_spi_mux_v2_0_ss1_out [get_bd_ports LO_CS1] [get_bd_pins lo_spi_mux_v2_0/ss1_out] - connect_bd_net -net lo_spi_mux_v2_0_ss2_out [get_bd_ports LO_CS2] [get_bd_pins lo_spi_mux_v2_0/ss2_out] - connect_bd_net -net lo_spi_sck_o [get_bd_ports LO_SCLK] [get_bd_pins lo_spi/sck_o] - connect_bd_net -net lo_spi_ss_o [get_bd_pins lo_spi/ss_o] [get_bd_pins lo_spi_mux_v2_0/ss_in] - connect_bd_net -net psf_spi_io0_o [get_bd_ports SDI] [get_bd_pins psf_spi/io0_o] - connect_bd_net -net psf_spi_sck_o [get_bd_ports SCLK] [get_bd_pins psf_spi/sck_o] - connect_bd_net -net psf_spi_ss_o [get_bd_ports S] [get_bd_pins psf_spi/ss_o] - connect_bd_net -net rst_adc0_peripheral_reset [get_bd_pins clk_adc0_x2/reset] [get_bd_pins rst_adc0/peripheral_reset] - connect_bd_net -net rst_adc0_x2_peripheral_aresetn [get_bd_pins axis_avg_buffer_0/s_axis_aresetn] [get_bd_pins axis_avg_buffer_1/s_axis_aresetn] [get_bd_pins axis_readout_v2_0/aresetn] [get_bd_pins axis_readout_v2_1/aresetn] [get_bd_pins axis_register_slice_0/aresetn] [get_bd_pins axis_register_slice_1/aresetn] [get_bd_pins rst_adc0_x2/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/m0_axis_aresetn] - connect_bd_net -net rst_dac0_peripheral_aresetn [get_bd_pins axis_cdcsync_v1_0/m_axis_aresetn] [get_bd_pins axis_cdcsync_v1_0/s_axis_aresetn] [get_bd_pins axis_cdcsync_v1_1/s_axis_aresetn] [get_bd_pins axis_clk_cnvrt_avg_0/m_axis_aresetn] [get_bd_pins axis_clk_cnvrt_avg_1/m_axis_aresetn] [get_bd_pins axis_constant_0/m_axis_aresetn] [get_bd_pins axis_constant_1/m_axis_aresetn] [get_bd_pins axis_constant_2/m_axis_aresetn] [get_bd_pins axis_set_reg_0/s_axis_aresetn] [get_bd_pins axis_signal_gen_v6_0/aresetn] [get_bd_pins axis_signal_gen_v6_1/aresetn] [get_bd_pins axis_signal_gen_v6_2/aresetn] [get_bd_pins axis_tproc64x32_x8_0/aresetn] [get_bd_pins rst_dac0/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/s0_axis_aresetn] - connect_bd_net -net rst_dac1_peripheral_aresetn [get_bd_pins axis_cdcsync_v1_1/m_axis_aresetn] [get_bd_pins axis_signal_gen_v6_3/aresetn] [get_bd_pins axis_signal_gen_v6_4/aresetn] [get_bd_pins axis_signal_gen_v6_5/aresetn] [get_bd_pins axis_signal_gen_v6_6/aresetn] [get_bd_pins rst_dac1/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/s1_axis_aresetn] - connect_bd_net -net rst_ps8_0_99M_peripheral_aresetn [get_bd_pins attn_spi/s_axi_aresetn] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_dma_avg/axi_resetn] [get_bd_pins axi_dma_buf/axi_resetn] [get_bd_pins axi_dma_gen/axi_resetn] [get_bd_pins axi_dma_tproc/axi_resetn] [get_bd_pins axi_smc/aresetn] [get_bd_pins axis_avg_buffer_0/m_axis_aresetn] [get_bd_pins axis_avg_buffer_0/s_axi_aresetn] [get_bd_pins axis_avg_buffer_1/m_axis_aresetn] [get_bd_pins axis_avg_buffer_1/s_axi_aresetn] [get_bd_pins axis_clk_cnvrt_avg_0/s_axis_aresetn] [get_bd_pins axis_clk_cnvrt_avg_1/s_axis_aresetn] [get_bd_pins axis_readout_v2_0/s_axi_aresetn] [get_bd_pins axis_readout_v2_1/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_0/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_0/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_1/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_1/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_2/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_2/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_3/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_3/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_4/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_4/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_5/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_5/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_6/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_6/s_axi_aresetn] [get_bd_pins axis_switch_avg/aresetn] [get_bd_pins axis_switch_avg/s_axi_ctrl_aresetn] [get_bd_pins axis_switch_buf/aresetn] [get_bd_pins axis_switch_buf/s_axi_ctrl_aresetn] [get_bd_pins axis_switch_gen/aresetn] [get_bd_pins axis_switch_gen/s_axi_ctrl_aresetn] [get_bd_pins axis_tproc64x32_x8_0/m0_axis_aresetn] [get_bd_pins axis_tproc64x32_x8_0/s0_axis_aresetn] [get_bd_pins axis_tproc64x32_x8_0/s_axi_aresetn] [get_bd_pins dac_bias_spi/s_axi_aresetn] [get_bd_pins lo_spi/s_axi_aresetn] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/M01_ARESETN] [get_bd_pins ps8_0_axi_periph/M02_ARESETN] [get_bd_pins ps8_0_axi_periph/M03_ARESETN] [get_bd_pins ps8_0_axi_periph/M04_ARESETN] [get_bd_pins ps8_0_axi_periph/M05_ARESETN] [get_bd_pins ps8_0_axi_periph/M06_ARESETN] [get_bd_pins ps8_0_axi_periph/M07_ARESETN] [get_bd_pins ps8_0_axi_periph/M08_ARESETN] [get_bd_pins ps8_0_axi_periph/M09_ARESETN] [get_bd_pins ps8_0_axi_periph/M10_ARESETN] [get_bd_pins ps8_0_axi_periph/M11_ARESETN] [get_bd_pins ps8_0_axi_periph/M12_ARESETN] [get_bd_pins ps8_0_axi_periph/M13_ARESETN] [get_bd_pins ps8_0_axi_periph/M14_ARESETN] [get_bd_pins ps8_0_axi_periph/M15_ARESETN] [get_bd_pins ps8_0_axi_periph/M16_ARESETN] [get_bd_pins ps8_0_axi_periph/M17_ARESETN] [get_bd_pins ps8_0_axi_periph/M18_ARESETN] [get_bd_pins ps8_0_axi_periph/M19_ARESETN] [get_bd_pins ps8_0_axi_periph/M20_ARESETN] [get_bd_pins ps8_0_axi_periph/M21_ARESETN] [get_bd_pins ps8_0_axi_periph/M22_ARESETN] [get_bd_pins ps8_0_axi_periph/M23_ARESETN] [get_bd_pins ps8_0_axi_periph/M24_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins psf_spi/s_axi_aresetn] [get_bd_pins rst_100/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/s_axi_aresetn] - connect_bd_net -net usp_rf_data_converter_0_clk_adc0 [get_bd_pins clk_adc0_x2/clk_in1] [get_bd_pins rst_adc0/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/clk_adc0] - connect_bd_net -net usp_rf_data_converter_0_clk_dac0 [get_bd_pins axi_bram_ctrl_0_bram/clkb] [get_bd_pins axis_cdcsync_v1_0/m_axis_aclk] [get_bd_pins axis_cdcsync_v1_0/s_axis_aclk] [get_bd_pins axis_cdcsync_v1_1/s_axis_aclk] [get_bd_pins axis_clk_cnvrt_avg_0/m_axis_aclk] [get_bd_pins axis_clk_cnvrt_avg_1/m_axis_aclk] [get_bd_pins axis_constant_0/m_axis_aclk] [get_bd_pins axis_constant_1/m_axis_aclk] [get_bd_pins axis_constant_2/m_axis_aclk] [get_bd_pins axis_set_reg_0/s_axis_aclk] [get_bd_pins axis_signal_gen_v6_0/aclk] [get_bd_pins axis_signal_gen_v6_1/aclk] [get_bd_pins axis_signal_gen_v6_2/aclk] [get_bd_pins axis_tproc64x32_x8_0/aclk] [get_bd_pins rst_dac0/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/clk_dac0] [get_bd_pins usp_rf_data_converter_0/s0_axis_aclk] - connect_bd_net -net usp_rf_data_converter_0_clk_dac1 [get_bd_pins axis_cdcsync_v1_1/m_axis_aclk] [get_bd_pins axis_signal_gen_v6_3/aclk] [get_bd_pins axis_signal_gen_v6_4/aclk] [get_bd_pins axis_signal_gen_v6_5/aclk] [get_bd_pins axis_signal_gen_v6_6/aclk] [get_bd_pins rst_dac1/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/clk_dac1] [get_bd_pins usp_rf_data_converter_0/s1_axis_aclk] - connect_bd_net -net vect2bits_16_0_dout0 [get_bd_ports PMOD0_0_LS] [get_bd_pins vect2bits_16_0/dout0] - connect_bd_net -net vect2bits_16_0_dout1 [get_bd_ports PMOD0_1_LS] [get_bd_pins vect2bits_16_0/dout1] - connect_bd_net -net vect2bits_16_0_dout2 [get_bd_ports PMOD0_2_LS] [get_bd_pins vect2bits_16_0/dout2] - connect_bd_net -net vect2bits_16_0_dout3 [get_bd_ports PMOD0_3_LS] [get_bd_pins vect2bits_16_0/dout3] - connect_bd_net -net vect2bits_16_0_dout4 [get_bd_ports PMOD0_4_LS] [get_bd_pins vect2bits_16_0/dout4] - connect_bd_net -net vect2bits_16_0_dout5 [get_bd_ports PMOD0_5_LS] [get_bd_pins vect2bits_16_0/dout5] - connect_bd_net -net vect2bits_16_0_dout6 [get_bd_ports PMOD0_6_LS] [get_bd_pins vect2bits_16_0/dout6] - connect_bd_net -net vect2bits_16_0_dout7 [get_bd_ports PMOD0_7_LS] [get_bd_pins vect2bits_16_0/dout7] - connect_bd_net -net vect2bits_16_0_dout14 [get_bd_pins axis_avg_buffer_0/trigger] [get_bd_pins vect2bits_16_0/dout14] - connect_bd_net -net vect2bits_16_0_dout15 [get_bd_pins axis_avg_buffer_1/trigger] [get_bd_pins vect2bits_16_0/dout15] - connect_bd_net -net xlconstant_0_dout [get_bd_pins axi_bram_ctrl_0_bram/dinb] [get_bd_pins xlconstant_0/dout] - connect_bd_net -net xlconstant_1_dout [get_bd_pins axi_bram_ctrl_0_bram/enb] [get_bd_pins xlconstant_1/dout] - connect_bd_net -net xlconstant_2_dout [get_bd_pins axi_bram_ctrl_0_bram/rstb] [get_bd_pins xlconstant_2/dout] - connect_bd_net -net xlconstant_3_dout [get_bd_pins axi_bram_ctrl_0_bram/web] [get_bd_pins xlconstant_3/dout] - connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins attn_spi/ext_spi_clk] [get_bd_pins attn_spi/s_axi_aclk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_dma_avg/m_axi_s2mm_aclk] [get_bd_pins axi_dma_avg/s_axi_lite_aclk] [get_bd_pins axi_dma_buf/m_axi_s2mm_aclk] [get_bd_pins axi_dma_buf/s_axi_lite_aclk] [get_bd_pins axi_dma_gen/m_axi_mm2s_aclk] [get_bd_pins axi_dma_gen/s_axi_lite_aclk] [get_bd_pins axi_dma_tproc/m_axi_mm2s_aclk] [get_bd_pins axi_dma_tproc/m_axi_s2mm_aclk] [get_bd_pins axi_dma_tproc/s_axi_lite_aclk] [get_bd_pins axi_smc/aclk] [get_bd_pins axis_avg_buffer_0/m_axis_aclk] [get_bd_pins axis_avg_buffer_0/s_axi_aclk] [get_bd_pins axis_avg_buffer_1/m_axis_aclk] [get_bd_pins axis_avg_buffer_1/s_axi_aclk] [get_bd_pins axis_clk_cnvrt_avg_0/s_axis_aclk] [get_bd_pins axis_clk_cnvrt_avg_1/s_axis_aclk] [get_bd_pins axis_readout_v2_0/s_axi_aclk] [get_bd_pins axis_readout_v2_1/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_0/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_0/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_1/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_1/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_2/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_2/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_3/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_3/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_4/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_4/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_5/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_5/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_6/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_6/s_axi_aclk] [get_bd_pins axis_switch_avg/aclk] [get_bd_pins axis_switch_avg/s_axi_ctrl_aclk] [get_bd_pins axis_switch_buf/aclk] [get_bd_pins axis_switch_buf/s_axi_ctrl_aclk] [get_bd_pins axis_switch_gen/aclk] [get_bd_pins axis_switch_gen/s_axi_ctrl_aclk] [get_bd_pins axis_tproc64x32_x8_0/m0_axis_aclk] [get_bd_pins axis_tproc64x32_x8_0/s0_axis_aclk] [get_bd_pins axis_tproc64x32_x8_0/s_axi_aclk] [get_bd_pins dac_bias_spi/ext_spi_clk] [get_bd_pins dac_bias_spi/s_axi_aclk] [get_bd_pins lo_spi/ext_spi_clk] [get_bd_pins lo_spi/s_axi_aclk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/M01_ACLK] [get_bd_pins ps8_0_axi_periph/M02_ACLK] [get_bd_pins ps8_0_axi_periph/M03_ACLK] [get_bd_pins ps8_0_axi_periph/M04_ACLK] [get_bd_pins ps8_0_axi_periph/M05_ACLK] [get_bd_pins ps8_0_axi_periph/M06_ACLK] [get_bd_pins ps8_0_axi_periph/M07_ACLK] [get_bd_pins ps8_0_axi_periph/M08_ACLK] [get_bd_pins ps8_0_axi_periph/M09_ACLK] [get_bd_pins ps8_0_axi_periph/M10_ACLK] [get_bd_pins ps8_0_axi_periph/M11_ACLK] [get_bd_pins ps8_0_axi_periph/M12_ACLK] [get_bd_pins ps8_0_axi_periph/M13_ACLK] [get_bd_pins ps8_0_axi_periph/M14_ACLK] [get_bd_pins ps8_0_axi_periph/M15_ACLK] [get_bd_pins ps8_0_axi_periph/M16_ACLK] [get_bd_pins ps8_0_axi_periph/M17_ACLK] [get_bd_pins ps8_0_axi_periph/M18_ACLK] [get_bd_pins ps8_0_axi_periph/M19_ACLK] [get_bd_pins ps8_0_axi_periph/M20_ACLK] [get_bd_pins ps8_0_axi_periph/M21_ACLK] [get_bd_pins ps8_0_axi_periph/M22_ACLK] [get_bd_pins ps8_0_axi_periph/M23_ACLK] [get_bd_pins ps8_0_axi_periph/M24_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins psf_spi/ext_spi_clk] [get_bd_pins psf_spi/s_axi_aclk] [get_bd_pins rst_100/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/s_axi_aclk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins zynq_ultra_ps_e_0/saxihpc0_fpd_aclk] - connect_bd_net -net zynq_ultra_ps_e_0_pl_clk1 [get_bd_ports PWR_SYNC] [get_bd_pins zynq_ultra_ps_e_0/pl_clk1] - connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins rst_100/ext_reset_in] [get_bd_pins rst_adc0/ext_reset_in] [get_bd_pins rst_adc0_x2/ext_reset_in] [get_bd_pins rst_dac0/ext_reset_in] [get_bd_pins rst_dac1/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] - - # Create address segments - assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force - assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] -force - assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force - assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] -force - assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force - assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] -force - assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force - assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force - assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] -force - assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] -force - assign_bd_address -offset 0xA0010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs attn_spi/AXI_LITE/Reg] -force - assign_bd_address -offset 0xA0000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force - assign_bd_address -offset 0xA0040000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_avg/S_AXI_LITE/Reg] -force - assign_bd_address -offset 0xA0041000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_buf/S_AXI_LITE/Reg] -force - assign_bd_address -offset 0xA0042000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_gen/S_AXI_LITE/Reg] -force - assign_bd_address -offset 0xA0043000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_tproc/S_AXI_LITE/Reg] -force - assign_bd_address -offset 0xA0044000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_avg_buffer_0/s_axi/reg0] -force - assign_bd_address -offset 0xA0045000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_avg_buffer_1/s_axi/reg0] -force - assign_bd_address -offset 0xA0046000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_readout_v2_0/s_axi/reg0] -force - assign_bd_address -offset 0xA0047000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_readout_v2_1/s_axi/reg0] -force - assign_bd_address -offset 0xA0048000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_0/s_axi/reg0] -force - assign_bd_address -offset 0xA0049000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_1/s_axi/reg0] -force - assign_bd_address -offset 0xA004A000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_2/s_axi/reg0] -force - assign_bd_address -offset 0xA004B000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_3/s_axi/reg0] -force - assign_bd_address -offset 0xA004C000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_4/s_axi/reg0] -force - assign_bd_address -offset 0xA004D000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_5/s_axi/reg0] -force - assign_bd_address -offset 0xA004E000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_6/s_axi/reg0] -force - assign_bd_address -offset 0xA004F000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_avg/S_AXI_CTRL/Reg] -force - assign_bd_address -offset 0xA0050000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_buf/S_AXI_CTRL/Reg] -force - assign_bd_address -offset 0xA0051000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_gen/S_AXI_CTRL/Reg] -force - assign_bd_address -offset 0x000400000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_tproc64x32_x8_0/s_axi/reg0] -force - assign_bd_address -offset 0xA0030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs dac_bias_spi/AXI_LITE/Reg] -force - assign_bd_address -offset 0xA0060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs lo_spi/AXI_LITE/Reg] -force - assign_bd_address -offset 0xA0070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs psf_spi/AXI_LITE/Reg] -force - assign_bd_address -offset 0xA0080000 -range 0x00040000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs usp_rf_data_converter_0/s_axi/Reg] -force - - # Perform GUI Layout - regenerate_bd_layout -layout_string { - "ActiveEmotionalView":"Default View", - "Default View_ScaleFactor":"0.391687", - "Default View_TopLeft":"-1884,-61", - "ExpandedHierarchyInLayout":"", - "guistr":"# # String gsaved with Nlview 7.0r4 2019-12-20 bk=1.5203 VDI=41 GEI=36 GUI=JA:10.0 TLS -# -string -flagsOSRD -preplace port adc0_clk -pg 1 -lvl 9 -x 4210 -y 2520 -defaultsOSRD -right -preplace port dac0_clk -pg 1 -lvl 9 -x 4210 -y 2500 -defaultsOSRD -right -preplace port dac1_clk -pg 1 -lvl 9 -x 4210 -y 2480 -defaultsOSRD -right -preplace port sysref_in -pg 1 -lvl 9 -x 4210 -y 2460 -defaultsOSRD -right -preplace port vin0 -pg 1 -lvl 9 -x 4210 -y 2420 -defaultsOSRD -right -preplace port vin1 -pg 1 -lvl 9 -x 4210 -y 2440 -defaultsOSRD -right -preplace port vout0 -pg 1 -lvl 9 -x 4210 -y 2050 -defaultsOSRD -preplace port vout1 -pg 1 -lvl 9 -x 4210 -y 2070 -defaultsOSRD -preplace port vout2 -pg 1 -lvl 9 -x 4210 -y 2090 -defaultsOSRD -preplace port vout3 -pg 1 -lvl 9 -x 4210 -y 2110 -defaultsOSRD -preplace port vout4 -pg 1 -lvl 9 -x 4210 -y 2130 -defaultsOSRD -preplace port vout5 -pg 1 -lvl 9 -x 4210 -y 2150 -defaultsOSRD -preplace port vout6 -pg 1 -lvl 9 -x 4210 -y 2170 -defaultsOSRD -preplace port ATTN_CLK -pg 1 -lvl 9 -x 4210 -y 430 -defaultsOSRD -preplace port ATTN_SI -pg 1 -lvl 9 -x 4210 -y 410 -defaultsOSRD -preplace port BIAS_SCLK -pg 1 -lvl 9 -x 4210 -y 660 -defaultsOSRD -preplace port BIAS_SDI -pg 1 -lvl 9 -x 4210 -y 620 -defaultsOSRD -preplace port BIAS_SDO -pg 1 -lvl 9 -x 4210 -y 640 -defaultsOSRD -right -preplace port LO_CS0 -pg 1 -lvl 9 -x 4210 -y 940 -defaultsOSRD -preplace port LO_CS1 -pg 1 -lvl 9 -x 4210 -y 960 -defaultsOSRD -preplace port LO_CS2 -pg 1 -lvl 9 -x 4210 -y 980 -defaultsOSRD -preplace port LO_MISO0 -pg 1 -lvl 9 -x 4210 -y 1100 -defaultsOSRD -right -preplace port LO_MISO1 -pg 1 -lvl 9 -x 4210 -y 1080 -defaultsOSRD -right -preplace port LO_MISO2 -pg 1 -lvl 9 -x 4210 -y 1060 -defaultsOSRD -right -preplace port LO_MOSI -pg 1 -lvl 9 -x 4210 -y 840 -defaultsOSRD -preplace port LO_SCLK -pg 1 -lvl 9 -x 4210 -y 880 -defaultsOSRD -preplace port PMOD0_0_LS -pg 1 -lvl 9 -x 4210 -y 1520 -defaultsOSRD -preplace port PMOD0_1_LS -pg 1 -lvl 9 -x 4210 -y 1540 -defaultsOSRD -preplace port PMOD0_2_LS -pg 1 -lvl 9 -x 4210 -y 1560 -defaultsOSRD -preplace port PMOD0_3_LS -pg 1 -lvl 9 -x 4210 -y 1580 -defaultsOSRD -preplace port PMOD0_4_LS -pg 1 -lvl 9 -x 4210 -y 1600 -defaultsOSRD -preplace port PMOD0_5_LS -pg 1 -lvl 9 -x 4210 -y 1620 -defaultsOSRD -preplace port PMOD0_6_LS -pg 1 -lvl 9 -x 4210 -y 1640 -defaultsOSRD -preplace port PMOD0_7_LS -pg 1 -lvl 9 -x 4210 -y 1660 -defaultsOSRD -preplace port PMOD1_0_LS -pg 1 -lvl 0 -x -50 -y 2030 -defaultsOSRD -preplace port SCLK -pg 1 -lvl 9 -x 4210 -y 1210 -defaultsOSRD -preplace port SDI -pg 1 -lvl 9 -x 4210 -y 1170 -defaultsOSRD -preplace port SDO -pg 1 -lvl 9 -x 4210 -y 1190 -defaultsOSRD -right -preplace portBus ATTN_LE -pg 1 -lvl 9 -x 4210 -y 450 -defaultsOSRD -preplace portBus BIAS_CLR -pg 1 -lvl 9 -x 4210 -y 560 -defaultsOSRD -preplace portBus BIAS_S -pg 1 -lvl 9 -x 4210 -y 680 -defaultsOSRD -preplace portBus LO_SYNC -pg 1 -lvl 9 -x 4210 -y 780 -defaultsOSRD -preplace portBus PWR_SYNC -pg 1 -lvl 9 -x 4210 -y 290 -defaultsOSRD -preplace portBus S -pg 1 -lvl 9 -x 4210 -y 1230 -defaultsOSRD -preplace inst attn_spi -pg 1 -lvl 7 -x 3550 -y 430 -defaultsOSRD -preplace inst axi_bram_ctrl_0 -pg 1 -lvl 1 -x 150 -y 2110 -defaultsOSRD -preplace inst axi_bram_ctrl_0_bram -pg 1 -lvl 2 -x 620 -y 2300 -defaultsOSRD -preplace inst axi_dma_avg -pg 1 -lvl 2 -x 620 -y 710 -defaultsOSRD -preplace inst axi_dma_buf -pg 1 -lvl 2 -x 620 -y 890 -defaultsOSRD -resize 320 156 -preplace inst axi_dma_gen -pg 1 -lvl 2 -x 620 -y 1060 -defaultsOSRD -preplace inst axi_dma_tproc -pg 1 -lvl 2 -x 620 -y 1250 -defaultsOSRD -preplace inst axi_smc -pg 1 -lvl 2 -x 620 -y 490 -defaultsOSRD -preplace inst axis_avg_buffer_0 -pg 1 -lvl 6 -x 2970 -y 3490 -defaultsOSRD -preplace inst axis_avg_buffer_1 -pg 1 -lvl 6 -x 2970 -y 3890 -defaultsOSRD -resize 220 236 -preplace inst axis_clk_cnvrt_avg_0 -pg 1 -lvl 7 -x 3550 -y 2400 -defaultsOSRD -preplace inst axis_clk_cnvrt_avg_1 -pg 1 -lvl 7 -x 3550 -y 3020 -defaultsOSRD -resize 220 156 -preplace inst axis_constant_0 -pg 1 -lvl 1 -x 150 -y 1840 -defaultsOSRD -preplace inst axis_constant_1 -pg 1 -lvl 1 -x 150 -y 1960 -defaultsOSRD -resize 220 96 -preplace inst axis_register_slice_0 -pg 1 -lvl 4 -x 1840 -y 3500 -defaultsOSRD -preplace inst axis_register_slice_1 -pg 1 -lvl 4 -x 1840 -y 3660 -defaultsOSRD -resize 180 116 -preplace inst axis_set_reg_0 -pg 1 -lvl 5 -x 2390 -y 1540 -defaultsOSRD -preplace inst axis_signal_gen_v6_0 -pg 1 -lvl 5 -x 2390 -y 1740 -defaultsOSRD -preplace inst axis_signal_gen_v6_1 -pg 1 -lvl 5 -x 2390 -y 2000 -defaultsOSRD -resize 220 236 -preplace inst axis_signal_gen_v6_2 -pg 1 -lvl 5 -x 2390 -y 2260 -defaultsOSRD -resize 220 236 -preplace inst axis_signal_gen_v6_3 -pg 1 -lvl 5 -x 2390 -y 2520 -defaultsOSRD -resize 220 236 -preplace inst axis_signal_gen_v6_4 -pg 1 -lvl 5 -x 2390 -y 2780 -defaultsOSRD -resize 220 236 -preplace inst axis_signal_gen_v6_5 -pg 1 -lvl 5 -x 2390 -y 3040 -defaultsOSRD -resize 220 236 -preplace inst axis_signal_gen_v6_6 -pg 1 -lvl 5 -x 2390 -y 3300 -defaultsOSRD -resize 220 236 -preplace inst axis_switch_avg -pg 1 -lvl 7 -x 3550 -y 2600 -defaultsOSRD -preplace inst axis_switch_buf -pg 1 -lvl 7 -x 3550 -y 2820 -defaultsOSRD -resize 240 196 -preplace inst axis_switch_gen -pg 1 -lvl 3 -x 1290 -y 1730 -defaultsOSRD -preplace inst axis_tproc64x32_x8_0 -pg 1 -lvl 2 -x 620 -y 1970 -defaultsOSRD -preplace inst bias_constant_1 -pg 1 -lvl 8 -x 3970 -y 560 -defaultsOSRD -preplace inst clk_adc0_x2 -pg 1 -lvl 3 -x 1290 -y 1520 -defaultsOSRD -preplace inst dac_bias_spi -pg 1 -lvl 7 -x 3550 -y 650 -defaultsOSRD -preplace inst lo_spi -pg 1 -lvl 7 -x 3550 -y 870 -defaultsOSRD -preplace inst lo_spi_mux_v2_0 -pg 1 -lvl 8 -x 3970 -y 970 -defaultsOSRD -preplace inst lo_sync_constant_0 -pg 1 -lvl 8 -x 3970 -y 780 -defaultsOSRD -preplace inst ps8_0_axi_periph -pg 1 -lvl 5 -x 2390 -y 620 -defaultsOSRD -preplace inst psf_spi -pg 1 -lvl 7 -x 3550 -y 1200 -defaultsOSRD -preplace inst rst_100 -pg 1 -lvl 3 -x 1290 -y 560 -defaultsOSRD -preplace inst rst_adc0 -pg 1 -lvl 3 -x 1290 -y 740 -defaultsOSRD -resize 320 156 -preplace inst rst_adc0_x2 -pg 1 -lvl 3 -x 1290 -y 920 -defaultsOSRD -resize 320 156 -preplace inst rst_dac0 -pg 1 -lvl 3 -x 1290 -y 1100 -defaultsOSRD -resize 320 156 -preplace inst rst_dac1 -pg 1 -lvl 3 -x 1290 -y 1280 -defaultsOSRD -resize 320 156 -preplace inst usp_rf_data_converter_0 -pg 1 -lvl 8 -x 3970 -y 2130 -defaultsOSRD -preplace inst vect2bits_16_0 -pg 1 -lvl 8 -x 3970 -y 1670 -defaultsOSRD -preplace inst xlconstant_0 -pg 1 -lvl 1 -x 150 -y 2230 -defaultsOSRD -preplace inst xlconstant_1 -pg 1 -lvl 1 -x 150 -y 2340 -defaultsOSRD -resize 140 88 -preplace inst xlconstant_2 -pg 1 -lvl 1 -x 150 -y 2450 -defaultsOSRD -resize 140 88 -preplace inst xlconstant_3 -pg 1 -lvl 1 -x 150 -y 2560 -defaultsOSRD -resize 140 88 -preplace inst zynq_ultra_ps_e_0 -pg 1 -lvl 3 -x 1290 -y 360 -defaultsOSRD -preplace inst axis_cdcsync_v1_0 -pg 1 -lvl 3 -x 1290 -y 1960 -defaultsOSRD -preplace inst axis_constant_2 -pg 1 -lvl 3 -x 1290 -y 2140 -defaultsOSRD -preplace inst axis_cdcsync_v1_1 -pg 1 -lvl 3 -x 1290 -y 2380 -defaultsOSRD -preplace inst axis_readout_v2_0 -pg 1 -lvl 5 -x 2390 -y 3550 -defaultsOSRD -preplace inst axis_readout_v2_1 -pg 1 -lvl 5 -x 2390 -y 3800 -defaultsOSRD -preplace netloc LO_MISO0_1 1 7 2 3790 1100 N -preplace netloc LO_MISO1_1 1 7 2 3800 1080 N -preplace netloc LO_MISO2_1 1 7 2 3810J 1060 NJ -preplace netloc PMOD1_0_LS_1 1 0 2 N 2030 290J -preplace netloc axi_bram_ctrl_0_bram_doutb 1 1 1 440 2120n -preplace netloc axi_quad_spi_0_io0_o 1 7 2 NJ 410 NJ -preplace netloc axi_quad_spi_0_sck_o 1 7 2 NJ 430 NJ -preplace netloc axi_quad_spi_0_ss_o 1 7 2 NJ 450 NJ -preplace netloc axis_set_reg_0_dout 1 5 3 NJ 1540 NJ 1540 3770 -preplace netloc axis_tproc64x32_x8_0_pmem_addr 1 1 2 410 1760 800 -preplace netloc bias_constant_0_dout 1 8 1 NJ 780 -preplace netloc bias_constant_1_dout 1 8 1 NJ 560 -preplace netloc clk_adc0_x2_clk_out1 1 2 6 970 1450 1630 3580 1950 3910 2760 2260 N 2260 N -preplace netloc clk_adc0_x2_locked 1 2 2 960 460 1600 -preplace netloc dac_bias_spi_io0_o 1 7 2 NJ 620 NJ -preplace netloc dac_bias_spi_sck_o 1 7 2 NJ 660 NJ -preplace netloc dac_bias_spi_ss_o 1 7 2 NJ 680 NJ -preplace netloc io1_i_0_1 1 7 2 N 1190 N -preplace netloc io1_i_0_2 1 7 2 N 640 N -preplace netloc lo_spi_io0_o 1 7 2 NJ 840 NJ -preplace netloc lo_spi_mux_v2_0_sdo_out 1 7 2 N 860 4150 -preplace netloc lo_spi_mux_v2_0_ss0_out 1 8 1 NJ 940 -preplace netloc lo_spi_mux_v2_0_ss1_out 1 8 1 NJ 960 -preplace netloc lo_spi_mux_v2_0_ss2_out 1 8 1 NJ 980 -preplace netloc lo_spi_sck_o 1 7 2 NJ 880 NJ -preplace netloc lo_spi_ss_o 1 7 1 3810 900n -preplace netloc psf_spi_io0_o 1 7 2 NJ 1170 NJ -preplace netloc psf_spi_sck_o 1 7 2 NJ 1210 NJ -preplace netloc psf_spi_ss_o 1 7 2 NJ 1230 NJ -preplace netloc rst_adc0_peripheral_reset 1 2 2 920 250 1610 -preplace netloc rst_adc0_x2_peripheral_aresetn 1 3 5 1650 3420 1960 3920 2780 2240 NJ 2240 NJ -preplace netloc rst_dac0_peripheral_aresetn 1 0 8 -10 1740 310 1740 880J 1600 1610 1560 2080 3440 2750J 3020 3160J 2280 N -preplace netloc rst_dac1_peripheral_aresetn 1 2 6 970 2250 1620 2250 1980 3660 2740J 2270 NJ 2270 3740J -preplace netloc rst_ps8_0_99M_peripheral_aresetn 1 0 8 -20 1750 300 330 890 230 1650J 330 2050 3690 2790 3000 3110 2220 N -preplace netloc usp_rf_data_converter_0_clk_adc0 1 2 7 940 1440 NJ 1440 N 1440 NJ 1440 NJ 1440 NJ 1440 4150 -preplace netloc usp_rf_data_converter_0_clk_dac0 1 0 9 10 1760 320 1750 850 1590 NJ 1590 2100 3670 2800J 3060 3180J 2300 3750J 2400 4120 -preplace netloc usp_rf_data_converter_0_clk_dac1 1 2 7 930 2580 NJ 2580 2030 3680 2770J 2290 NJ 2290 3730J 2410 4110 -preplace netloc vect2bits_16_0_dout0 1 8 1 N 1520 -preplace netloc vect2bits_16_0_dout1 1 8 1 N 1540 -preplace netloc vect2bits_16_0_dout2 1 8 1 N 1560 -preplace netloc vect2bits_16_0_dout3 1 8 1 N 1580 -preplace netloc vect2bits_16_0_dout4 1 8 1 N 1600 -preplace netloc vect2bits_16_0_dout5 1 8 1 N 1620 -preplace netloc vect2bits_16_0_dout6 1 8 1 N 1640 -preplace netloc vect2bits_16_0_dout7 1 8 1 N 1660 -preplace netloc vect2bits_16_0_dout14 1 5 4 2820 1430 NJ 1430 N 1430 4130 -preplace netloc vect2bits_16_0_dout15 1 5 4 2810 1420 NJ 1420 NJ 1420 4140 -preplace netloc xlconstant_0_dout 1 1 1 290 2230n -preplace netloc xlconstant_1_dout 1 1 1 N 2340 -preplace netloc xlconstant_2_dout 1 1 1 340 2360n -preplace netloc xlconstant_3_dout 1 1 1 430 2380n -preplace netloc zynq_ultra_ps_e_0_pl_clk0 1 0 8 0 1770 340 320 910 240 1620 340 2020 3930 2710 3040 3140 2200 N -preplace netloc zynq_ultra_ps_e_0_pl_clk1 1 3 6 1680J 0 NJ 0 NJ 0 NJ 0 NJ 0 4150J -preplace netloc zynq_ultra_ps_e_0_pl_resetn0 1 2 2 950 260 1600 -preplace netloc adc0_clk_1 1 7 2 3760J 2470 4110 -preplace netloc axi_bram_ctrl_0_BRAM_PORTA 1 1 1 290 2110n -preplace netloc axi_dma_0_M_AXIS_MM2S 1 1 2 420 1370 800 -preplace netloc axi_dma_0_M_AXI_MM2S 1 1 2 440 370 810 -preplace netloc axi_dma_0_M_AXI_S2MM 1 1 2 420 350 840J -preplace netloc axi_dma_1_M_AXIS_MM2S 1 2 1 900 1050n -preplace netloc axi_dma_1_M_AXI_MM2S 1 1 2 430 360 820J -preplace netloc axi_dma_avg_M_AXI_S2MM 1 1 2 440 610 800 -preplace netloc axi_dma_buf_M_AXI_S2MM 1 1 2 410 340 830 -preplace netloc axi_smc_M00_AXI 1 2 1 900 330n -preplace netloc axis_avg_buffer_0_m0_axis 1 6 1 3100 2540n -preplace netloc axis_avg_buffer_0_m1_axis 1 6 1 3150 2760n -preplace netloc axis_avg_buffer_0_m2_axis 1 6 1 3120 2360n -preplace netloc axis_avg_buffer_1_m0_axis 1 6 1 3170 2560n -preplace netloc axis_avg_buffer_1_m1_axis 1 6 1 3190 2780n -preplace netloc axis_avg_buffer_1_m2_axis 1 6 1 3200 2980n -preplace netloc axis_clk_cnvrt_avg_0_M_AXIS 1 1 7 350 -50 NJ -50 NJ -50 N -50 NJ -50 NJ -50 3710 -preplace netloc axis_clk_cnvrt_avg_1_M_AXIS 1 1 7 360 -40 NJ -40 NJ -40 N -40 NJ -40 NJ -40 3720 -preplace netloc axis_constant_0_m_axis 1 1 1 330 1840n -preplace netloc axis_constant_1_m_axis 1 1 1 290 1900n -preplace netloc axis_readout_v2_0_m1_axis 1 5 1 2640 3410n -preplace netloc axis_readout_v2_1_m1_axis 1 5 1 2550 3800n -preplace netloc axis_register_slice_0_M_AXIS 1 4 1 N 3500 -preplace netloc axis_register_slice_1_M_AXIS 1 4 1 1970 3660n -preplace netloc axis_signal_gen_v6_0_m_axis 1 5 3 N 1740 3120 1940 NJ -preplace netloc axis_signal_gen_v6_1_m_axis 1 5 3 2560 1960 N 1960 NJ -preplace netloc axis_signal_gen_v6_2_m_axis 1 5 3 2610 1980 N 1980 NJ -preplace netloc axis_signal_gen_v6_3_m_axis 1 5 3 2650 2000 N 2000 NJ -preplace netloc axis_signal_gen_v6_4_m_axis 1 5 3 2680 2020 N 2020 NJ -preplace netloc axis_signal_gen_v6_5_m_axis 1 5 3 2690 2040 N 2040 NJ -preplace netloc axis_signal_gen_v6_6_m_axis 1 5 3 2700 2060 N 2060 NJ -preplace netloc axis_switch_0_M00_AXIS 1 3 2 1660 1660 N -preplace netloc axis_switch_0_M01_AXIS 1 3 2 N 1690 2120 -preplace netloc axis_switch_0_M02_AXIS 1 3 2 N 1710 2110 -preplace netloc axis_switch_0_M03_AXIS 1 3 2 N 1730 2090 -preplace netloc axis_switch_0_M04_AXIS 1 3 2 N 1750 2070 -preplace netloc axis_switch_0_M05_AXIS 1 3 2 N 1770 2040 -preplace netloc axis_switch_0_M06_AXIS 1 3 2 N 1790 2010 -preplace netloc axis_switch_avg_M00_AXIS 1 1 7 380 -30 NJ -30 NJ -30 N -30 NJ -30 NJ -30 3700 -preplace netloc axis_switch_buf_M00_AXIS 1 1 7 370 -20 NJ -20 NJ -20 N -20 NJ -20 NJ -20 3690 -preplace netloc axis_tproc64x32_x8_0_m0_axis 1 1 2 440 1390 810 -preplace netloc axis_tproc64x32_x8_0_m1_axis 1 2 3 820 1400 N 1400 2120 -preplace netloc dac0_clk_1 1 7 2 3770J 2460 4120 -preplace netloc dac1_clk_1 1 7 2 3780J 2450 4130 -preplace netloc ps8_0_axi_periph_M00_AXI 1 1 5 430 1380 N 1380 NJ 1380 2040 1300 2670J -preplace netloc ps8_0_axi_periph_M01_AXI 1 1 5 400 1410 N 1410 NJ 1410 N 1410 2680 -preplace netloc ps8_0_axi_periph_M02_AXI 1 4 2 2180 1220 2600 -preplace netloc ps8_0_axi_periph_M03_AXI 1 4 2 2190 1230 2590 -preplace netloc ps8_0_axi_periph_M04_AXI 1 4 2 2200 1240 2580 -preplace netloc ps8_0_axi_periph_M05_AXI 1 4 2 2130 20 2610 -preplace netloc ps8_0_axi_periph_M06_AXI 1 1 5 390 1420 N 1420 NJ 1420 N 1420 2660 -preplace netloc ps8_0_axi_periph_M07_AXI 1 2 4 960 1390 1630J 1370 2030 1290 2620 -preplace netloc ps8_0_axi_periph_M08_AXI 1 5 3 NJ 540 NJ 540 3780 -preplace netloc ps8_0_axi_periph_M09_AXI 1 5 1 2730 560n -preplace netloc ps8_0_axi_periph_M10_AXI 1 5 1 2720 580n -preplace netloc ps8_0_axi_periph_M11_AXI 1 4 2 2160 1250 2570 -preplace netloc ps8_0_axi_periph_M12_AXI 1 4 2 2170 1260 2560 -preplace netloc ps8_0_axi_periph_M13_AXI 1 0 6 -30 1430 N 1430 NJ 1430 NJ 1430 N 1430 2650 -preplace netloc ps8_0_axi_periph_M14_AXI 1 4 2 2210 1400 2610 -preplace netloc ps8_0_axi_periph_M15_AXI 1 4 2 2140 1270 2550 -preplace netloc ps8_0_axi_periph_M16_AXI 1 4 2 2150 1280 2540 -preplace netloc ps8_0_axi_periph_M17_AXI 1 5 2 NJ 720 3150 -preplace netloc ps8_0_axi_periph_M18_AXI 1 5 2 NJ 740 3130 -preplace netloc ps8_0_axi_periph_M19_AXI 1 1 5 400 -10 NJ -10 NJ -10 N -10 2640 -preplace netloc ps8_0_axi_periph_M20_AXI 1 1 5 390 10 NJ 10 NJ 10 N 10 2630 -preplace netloc ps8_0_axi_periph_M21_AXI 1 5 2 2690 400 N -preplace netloc ps8_0_axi_periph_M22_AXI 1 5 2 2700J 710 3100 -preplace netloc ps8_0_axi_periph_M23_AXI 1 5 2 NJ 840 N -preplace netloc ps8_0_axi_periph_M24_AXI 1 5 2 NJ 860 3100 -preplace netloc sysref_in_1 1 7 2 3810 2440 4140 -preplace netloc usp_rf_data_converter_0_m00_axis 1 3 6 1670 1450 NJ 1450 NJ 1450 NJ 1450 NJ 1450 4120 -preplace netloc usp_rf_data_converter_0_m02_axis 1 3 6 1680 1460 NJ 1460 NJ 1460 NJ 1460 NJ 1460 4110 -preplace netloc usp_rf_data_converter_0_vout00 1 8 1 N 2050 -preplace netloc usp_rf_data_converter_0_vout01 1 8 1 N 2070 -preplace netloc usp_rf_data_converter_0_vout02 1 8 1 N 2090 -preplace netloc usp_rf_data_converter_0_vout10 1 8 1 N 2110 -preplace netloc usp_rf_data_converter_0_vout11 1 8 1 N 2130 -preplace netloc usp_rf_data_converter_0_vout12 1 8 1 N 2150 -preplace netloc usp_rf_data_converter_0_vout13 1 8 1 N 2170 -preplace netloc vin0_1 1 7 2 3790J 2420 N -preplace netloc vin1_1 1 7 2 3800J 2430 4150 -preplace netloc zynq_ultra_ps_e_0_M_AXI_HPM0_FPD 1 3 2 NJ 320 2010 -preplace netloc axis_cdcsync_v1_0_m0_axis 1 3 2 1660 1680 NJ -preplace netloc axis_cdcsync_v1_0_m2_axis 1 3 2 NJ 1970 2060 -preplace netloc axis_cdcsync_v1_0_m1_axis 1 3 2 1660 1940 NJ -preplace netloc axis_tproc64x32_x8_0_m2_axis 1 2 1 860 1890n -preplace netloc axis_tproc64x32_x8_0_m3_axis 1 2 1 870 1910n -preplace netloc axis_tproc64x32_x8_0_m4_axis 1 2 1 910 1930n -preplace netloc axis_constant_2_m_axis 1 2 2 970 1610 1600 -preplace netloc axis_cdcsync_v1_1_m0_axis 1 3 2 1640 2380 2030J -preplace netloc axis_cdcsync_v1_1_m1_axis 1 3 2 1610 2390 2000J -preplace netloc axis_cdcsync_v1_1_m2_axis 1 3 2 1600J 2400 1990 -preplace netloc axis_cdcsync_v1_1_m3_axis 1 3 2 NJ 2410 1960 -preplace netloc axis_tproc64x32_x8_0_m5_axis 1 2 1 840 1980n -preplace netloc axis_tproc64x32_x8_0_m6_axis 1 2 1 830 2000n -preplace netloc axis_tproc64x32_x8_0_m7_axis 1 2 1 820 2020n -preplace netloc axis_tproc64x32_x8_0_m8_axis 1 2 1 810 2040n -levelinfo -pg 1 -50 150 620 1290 1840 2390 2970 3550 3970 4210 -pagesize -pg 1 -db -bbox -sgen -200 -60 4380 4190 -" -} - - # Restore current instance - current_bd_instance $oldCurInst - - validate_bd_design - save_bd_design -} -# End of create_root_design() - - -################################################################## -# MAIN FLOW -################################################################## - -create_root_design "" - - diff --git a/qick/firmware/bd/bd_216_2020-2.tcl b/qick/firmware/bd/bd_216_2020-2.tcl deleted file mode 100644 index 3029960..0000000 --- a/qick/firmware/bd/bd_216_2020-2.tcl +++ /dev/null @@ -1,1718 +0,0 @@ - -################################################################ -# This is a generated script based on design: d_1 -# -# Though there are limitations about the generated script, -# the main purpose of this utility is to make learning -# IP Integrator Tcl commands easier. -################################################################ - -namespace eval _tcl { -proc get_script_folder {} { - set script_path [file normalize [info script]] - set script_folder [file dirname $script_path] - return $script_folder -} -} -variable script_folder -set script_folder [_tcl::get_script_folder] - -################################################################ -# Check if script is running in correct Vivado version. -################################################################ -set scripts_vivado_version 2020.2 -set current_vivado_version [version -short] - -if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { - puts "" - catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} - - return 1 -} - -################################################################ -# START -################################################################ - -# To test this script, run the following commands from Vivado Tcl console: -# source d_1_script.tcl - - -# The design that will be created by this Tcl script contains the following -# module references: -# vect2bits_16 - -# Please add the sources of those modules before sourcing this Tcl script. - -# If there is no project opened, this script will create a -# project, but make sure you do not have an existing project -# <./myproj/project_1.xpr> in the current working folder. - -set list_projs [get_projects -quiet] -if { $list_projs eq "" } { - create_project project_1 myproj -part xczu49dr-ffvf1760-2-e - set_property BOARD_PART xilinx.com:zcu216:part0:2.0 [current_project] -} - - -# CHANGE DESIGN NAME HERE -variable design_name -set design_name d_1 - -# If you do not already have an existing IP Integrator design open, -# you can create a design using the following command: -# create_bd_design $design_name - -# Creating design if needed -set errMsg "" -set nRet 0 - -set cur_design [current_bd_design -quiet] -set list_cells [get_bd_cells -quiet] - -if { ${design_name} eq "" } { - # USE CASES: - # 1) Design_name not set - - set errMsg "Please set the variable to a non-empty value." - set nRet 1 - -} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { - # USE CASES: - # 2): Current design opened AND is empty AND names same. - # 3): Current design opened AND is empty AND names diff; design_name NOT in project. - # 4): Current design opened AND is empty AND names diff; design_name exists in project. - - if { $cur_design ne $design_name } { - common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." - set design_name [get_property NAME $cur_design] - } - common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." - -} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { - # USE CASES: - # 5) Current design opened AND has components AND same names. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 1 -} elseif { [get_files -quiet ${design_name}.bd] ne "" } { - # USE CASES: - # 6) Current opened design, has components, but diff names, design_name exists in project. - # 7) No opened design, design_name exists in project. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 2 - -} else { - # USE CASES: - # 8) No opened design, design_name not in project. - # 9) Current opened design, has components, but diff names, design_name not in project. - - common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." - - create_bd_design $design_name - - common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." - current_bd_design $design_name - -} - -common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." - -if { $nRet != 0 } { - catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} - return $nRet -} - -set bCheckIPsPassed 1 -################################################################## -# CHECK IPs -################################################################## -set bCheckIPs 1 -if { $bCheckIPs == 1 } { - set list_check_ips "\ -xilinx.com:ip:axi_bram_ctrl:4.1\ -xilinx.com:ip:blk_mem_gen:8.4\ -xilinx.com:ip:axi_dma:7.1\ -xilinx.com:ip:smartconnect:1.0\ -user.org:user:axis_avg_buffer:1.0\ -user.org:user:axis_cdcsync_v1:1.0\ -xilinx.com:ip:axis_clock_converter:1.1\ -user.org:user:axis_constant:1.0\ -user.org:user:axis_readout_v2:1.0\ -xilinx.com:ip:axis_register_slice:1.1\ -user.org:user:axis_set_reg:1.0\ -user.org:user:axis_signal_gen_v6:1.0\ -xilinx.com:ip:axis_switch:1.1\ -user.org:user:axis_terminator:1.0\ -user.org:user:axis_tproc64x32_x8:1.0\ -xilinx.com:ip:proc_sys_reset:5.0\ -xilinx.com:ip:usp_rf_data_converter:2.4\ -xilinx.com:ip:xlconcat:2.1\ -xilinx.com:ip:xlconstant:1.1\ -xilinx.com:ip:zynq_ultra_ps_e:3.3\ -" - - set list_ips_missing "" - common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." - - foreach ip_vlnv $list_check_ips { - set ip_obj [get_ipdefs -all $ip_vlnv] - if { $ip_obj eq "" } { - lappend list_ips_missing $ip_vlnv - } - } - - if { $list_ips_missing ne "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } - set bCheckIPsPassed 0 - } - -} - -################################################################## -# CHECK Modules -################################################################## -set bCheckModules 1 -if { $bCheckModules == 1 } { - set list_check_mods "\ -vect2bits_16\ -" - - set list_mods_missing "" - common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." - - foreach mod_vlnv $list_check_mods { - if { [can_resolve_reference $mod_vlnv] == 0 } { - lappend list_mods_missing $mod_vlnv - } - } - - if { $list_mods_missing ne "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } - common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." - set bCheckIPsPassed 0 - } -} - -if { $bCheckIPsPassed != 1 } { - common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." - return 3 -} - -################################################################## -# DESIGN PROCs -################################################################## - - - -# Procedure to create entire design; Provide argument to make -# procedure reusable. If parentCell is "", will use root. -proc create_root_design { parentCell } { - - variable script_folder - variable design_name - - if { $parentCell eq "" } { - set parentCell [get_bd_cells /] - } - - # Get object for parentCell - set parentObj [get_bd_cells $parentCell] - if { $parentObj == "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} - return - } - - # Make sure parentObj is hier blk - set parentType [get_property TYPE $parentObj] - if { $parentType ne "hier" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} - return - } - - # Save current instance; Restore later - set oldCurInst [current_bd_instance .] - - # Set parent object as current - current_bd_instance $parentObj - - - # Create interface ports - set adc2_clk_0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 adc2_clk_0 ] - - set dac2_clk_0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac2_clk_0 ] - - set sysref_in_0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:display_usp_rf_data_converter:diff_pins_rtl:1.0 sysref_in_0 ] - - set vin20_0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vin20_0 ] - - set vin22_0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vin22_0 ] - - set vout0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout0 ] - - set vout1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout1 ] - - set vout2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout2 ] - - set vout3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout3 ] - - set vout4 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout4 ] - - set vout5 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout5 ] - - set vout6 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout6 ] - - - # Create ports - set PMOD0_0_LS [ create_bd_port -dir O PMOD0_0_LS ] - set PMOD0_1_LS [ create_bd_port -dir O PMOD0_1_LS ] - set PMOD0_2_LS [ create_bd_port -dir O PMOD0_2_LS ] - set PMOD0_3_LS [ create_bd_port -dir O PMOD0_3_LS ] - set PMOD0_4_LS [ create_bd_port -dir O PMOD0_4_LS ] - set PMOD0_5_LS [ create_bd_port -dir O PMOD0_5_LS ] - set PMOD0_6_LS [ create_bd_port -dir O PMOD0_6_LS ] - set PMOD0_7_LS [ create_bd_port -dir O PMOD0_7_LS ] - set PMOD1_0_LS [ create_bd_port -dir I PMOD1_0_LS ] - - # Create instance: axi_bram_ctrl_0, and set properties - set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {64} \ - CONFIG.SINGLE_PORT_BRAM {1} \ - ] $axi_bram_ctrl_0 - - # Create instance: axi_bram_ctrl_0_bram, and set properties - set axi_bram_ctrl_0_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 axi_bram_ctrl_0_bram ] - set_property -dict [ list \ - CONFIG.Byte_Size {8} \ - CONFIG.EN_SAFETY_CKT {false} \ - CONFIG.Enable_32bit_Address {true} \ - CONFIG.Enable_B {Use_ENB_Pin} \ - CONFIG.Memory_Type {True_Dual_Port_RAM} \ - CONFIG.Port_B_Clock {100} \ - CONFIG.Port_B_Enable_Rate {100} \ - CONFIG.Port_B_Write_Rate {50} \ - CONFIG.Read_Width_B {64} \ - CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \ - CONFIG.Register_PortB_Output_of_Memory_Primitives {false} \ - CONFIG.Use_Byte_Write_Enable {true} \ - CONFIG.Use_RSTA_Pin {true} \ - CONFIG.Use_RSTB_Pin {true} \ - CONFIG.Write_Width_B {64} \ - CONFIG.use_bram_block {BRAM_Controller} \ - ] $axi_bram_ctrl_0_bram - - # Create instance: axi_dma_avg, and set properties - set axi_dma_avg [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_avg ] - set_property -dict [ list \ - CONFIG.c_include_mm2s {0} \ - CONFIG.c_include_s2mm {1} \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_length_width {26} \ - ] $axi_dma_avg - - # Create instance: axi_dma_buf, and set properties - set axi_dma_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_buf ] - set_property -dict [ list \ - CONFIG.c_include_mm2s {0} \ - CONFIG.c_include_s2mm {1} \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_length_width {26} \ - ] $axi_dma_buf - - # Create instance: axi_dma_gen, and set properties - set axi_dma_gen [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_gen ] - set_property -dict [ list \ - CONFIG.c_include_s2mm {0} \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_length_width {26} \ - ] $axi_dma_gen - - # Create instance: axi_dma_tproc, and set properties - set axi_dma_tproc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_tproc ] - set_property -dict [ list \ - CONFIG.c_include_s2mm {1} \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_length_width {26} \ - ] $axi_dma_tproc - - # Create instance: axi_smc, and set properties - set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ] - set_property -dict [ list \ - CONFIG.NUM_SI {5} \ - ] $axi_smc - - # Create instance: axis_avg_buffer_0, and set properties - set axis_avg_buffer_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_avg_buffer:1.0 axis_avg_buffer_0 ] - set_property -dict [ list \ - CONFIG.N_AVG {14} \ - ] $axis_avg_buffer_0 - - # Create instance: axis_avg_buffer_1, and set properties - set axis_avg_buffer_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_avg_buffer:1.0 axis_avg_buffer_1 ] - set_property -dict [ list \ - CONFIG.N_AVG {14} \ - ] $axis_avg_buffer_1 - - # Create instance: axis_cdcsync_v1_0, and set properties - set axis_cdcsync_v1_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_cdcsync_v1:1.0 axis_cdcsync_v1_0 ] - set_property -dict [ list \ - CONFIG.B {160} \ - CONFIG.N {4} \ - ] $axis_cdcsync_v1_0 - - # Create instance: axis_cdcsync_v1_1, and set properties - set axis_cdcsync_v1_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_cdcsync_v1:1.0 axis_cdcsync_v1_1 ] - set_property -dict [ list \ - CONFIG.B {160} \ - CONFIG.N {4} \ - ] $axis_cdcsync_v1_1 - - # Create instance: axis_clk_cnvrt_avg_0, and set properties - set axis_clk_cnvrt_avg_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_avg_0 ] - - # Create instance: axis_clk_cnvrt_avg_1, and set properties - set axis_clk_cnvrt_avg_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_avg_1 ] - - # Create instance: axis_constant_0, and set properties - set axis_constant_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_constant:1.0 axis_constant_0 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {64} \ - ] $axis_constant_0 - - # Create instance: axis_constant_1, and set properties - set axis_constant_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_constant:1.0 axis_constant_1 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {64} \ - ] $axis_constant_1 - - # Create instance: axis_constant_2, and set properties - set axis_constant_2 [ create_bd_cell -type ip -vlnv user.org:user:axis_constant:1.0 axis_constant_2 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {160} \ - ] $axis_constant_2 - - # Create instance: axis_readout_v2_0, and set properties - set axis_readout_v2_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_readout_v2:1.0 axis_readout_v2_0 ] - - # Create instance: axis_readout_v2_1, and set properties - set axis_readout_v2_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_readout_v2:1.0 axis_readout_v2_1 ] - - # Create instance: axis_register_slice_0, and set properties - set axis_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_0 ] - - # Create instance: axis_register_slice_1, and set properties - set axis_register_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_1 ] - - # Create instance: axis_register_slice_2, and set properties - set axis_register_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_2 ] - - # Create instance: axis_register_slice_3, and set properties - set axis_register_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_3 ] - - # Create instance: axis_register_slice_4, and set properties - set axis_register_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_4 ] - - # Create instance: axis_register_slice_5, and set properties - set axis_register_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_5 ] - - # Create instance: axis_register_slice_6, and set properties - set axis_register_slice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_6 ] - - # Create instance: axis_register_slice_7, and set properties - set axis_register_slice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_7 ] - - # Create instance: axis_register_slice_8, and set properties - set axis_register_slice_8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_8 ] - - # Create instance: axis_set_reg_0, and set properties - set axis_set_reg_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_set_reg:1.0 axis_set_reg_0 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {160} \ - ] $axis_set_reg_0 - - # Create instance: axis_signal_gen_v6_0, and set properties - set axis_signal_gen_v6_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_0 ] - - # Create instance: axis_signal_gen_v6_1, and set properties - set axis_signal_gen_v6_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_1 ] - - # Create instance: axis_signal_gen_v6_2, and set properties - set axis_signal_gen_v6_2 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_2 ] - - # Create instance: axis_signal_gen_v6_3, and set properties - set axis_signal_gen_v6_3 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_3 ] - - # Create instance: axis_signal_gen_v6_4, and set properties - set axis_signal_gen_v6_4 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_4 ] - - # Create instance: axis_signal_gen_v6_5, and set properties - set axis_signal_gen_v6_5 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_5 ] - - # Create instance: axis_signal_gen_v6_6, and set properties - set axis_signal_gen_v6_6 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_6 ] - - # Create instance: axis_switch_avg, and set properties - set axis_switch_avg [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_avg ] - set_property -dict [ list \ - CONFIG.ROUTING_MODE {1} \ - ] $axis_switch_avg - - # Create instance: axis_switch_buf, and set properties - set axis_switch_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_buf ] - set_property -dict [ list \ - CONFIG.ROUTING_MODE {1} \ - ] $axis_switch_buf - - # Create instance: axis_switch_gen, and set properties - set axis_switch_gen [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_gen ] - set_property -dict [ list \ - CONFIG.DECODER_REG {1} \ - CONFIG.NUM_MI {7} \ - CONFIG.NUM_SI {1} \ - CONFIG.ROUTING_MODE {1} \ - ] $axis_switch_gen - - # Create instance: axis_terminator_0, and set properties - set axis_terminator_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_terminator:1.0 axis_terminator_0 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {256} \ - ] $axis_terminator_0 - - # Create instance: axis_terminator_1, and set properties - set axis_terminator_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_terminator:1.0 axis_terminator_1 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {256} \ - ] $axis_terminator_1 - - # Create instance: axis_tproc64x32_x8_0, and set properties - set axis_tproc64x32_x8_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_tproc64x32_x8:1.0 axis_tproc64x32_x8_0 ] - set_property -dict [ list \ - CONFIG.DMEM_N {12} \ - CONFIG.PMEM_N {20} \ - ] $axis_tproc64x32_x8_0 - - # Create instance: ps8_0_axi_periph, and set properties - set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ] - set_property -dict [ list \ - CONFIG.NUM_MI {21} \ - ] $ps8_0_axi_periph - - # Create instance: rst_100, and set properties - set rst_100 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_100 ] - - # Create instance: rst_adc, and set properties - set rst_adc [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_adc ] - set_property -dict [ list \ - CONFIG.RESET_BOARD_INTERFACE {Custom} \ - CONFIG.USE_BOARD_FLOW {true} \ - ] $rst_adc - - # Create instance: rst_dac2, and set properties - set rst_dac2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_dac2 ] - set_property -dict [ list \ - CONFIG.RESET_BOARD_INTERFACE {Custom} \ - CONFIG.USE_BOARD_FLOW {true} \ - ] $rst_dac2 - - # Create instance: rst_dac3, and set properties - set rst_dac3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_dac3 ] - set_property -dict [ list \ - CONFIG.RESET_BOARD_INTERFACE {Custom} \ - CONFIG.USE_BOARD_FLOW {true} \ - ] $rst_dac3 - - # Create instance: usp_rf_data_converter_0, and set properties - set usp_rf_data_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:usp_rf_data_converter:2.4 usp_rf_data_converter_0 ] - set_property -dict [ list \ - CONFIG.ADC2_Clock_Dist {0} \ - CONFIG.ADC2_Fabric_Freq {307.200} \ - CONFIG.ADC2_Outclk_Freq {307.200} \ - CONFIG.ADC2_PLL_Enable {true} \ - CONFIG.ADC2_Refclk_Freq {245.760} \ - CONFIG.ADC2_Sampling_Rate {2.4576} \ - CONFIG.ADC3_Enable {0} \ - CONFIG.ADC3_Fabric_Freq {0.0} \ - CONFIG.ADC_Coarse_Mixer_Freq20 {3} \ - CONFIG.ADC_Coarse_Mixer_Freq22 {3} \ - CONFIG.ADC_Coarse_Mixer_Freq30 {0} \ - CONFIG.ADC_Data_Width20 {8} \ - CONFIG.ADC_Decimation_Mode20 {1} \ - CONFIG.ADC_Decimation_Mode22 {1} \ - CONFIG.ADC_Decimation_Mode30 {0} \ - CONFIG.ADC_Mixer_Type20 {1} \ - CONFIG.ADC_Mixer_Type22 {1} \ - CONFIG.ADC_Mixer_Type30 {3} \ - CONFIG.ADC_OBS22 {false} \ - CONFIG.ADC_OBS31 {false} \ - CONFIG.ADC_OBS32 {false} \ - CONFIG.ADC_OBS33 {false} \ - CONFIG.ADC_RESERVED_1_20 {false} \ - CONFIG.ADC_RESERVED_1_21 {false} \ - CONFIG.ADC_RESERVED_1_22 {false} \ - CONFIG.ADC_RESERVED_1_23 {false} \ - CONFIG.ADC_RESERVED_1_30 {false} \ - CONFIG.ADC_RESERVED_1_31 {false} \ - CONFIG.ADC_RESERVED_1_32 {false} \ - CONFIG.ADC_RESERVED_1_33 {false} \ - CONFIG.ADC_Slice00_Enable {false} \ - CONFIG.ADC_Slice20_Enable {true} \ - CONFIG.ADC_Slice21_Enable {false} \ - CONFIG.ADC_Slice22_Enable {true} \ - CONFIG.ADC_Slice30_Enable {false} \ - CONFIG.DAC2_Clock_Dist {1} \ - CONFIG.DAC2_Fabric_Freq {430.080} \ - CONFIG.DAC2_Outclk_Freq {430.080} \ - CONFIG.DAC2_PLL_Enable {true} \ - CONFIG.DAC2_Refclk_Freq {245.760} \ - CONFIG.DAC2_Sampling_Rate {6.88128} \ - CONFIG.DAC3_Clock_Source {6} \ - CONFIG.DAC3_Fabric_Freq {430.080} \ - CONFIG.DAC3_Outclk_Freq {430.080} \ - CONFIG.DAC3_PLL_Enable {true} \ - CONFIG.DAC3_Refclk_Freq {245.760} \ - CONFIG.DAC3_Sampling_Rate {6.88128} \ - CONFIG.DAC_Coarse_Mixer_Freq20 {3} \ - CONFIG.DAC_Coarse_Mixer_Freq21 {3} \ - CONFIG.DAC_Coarse_Mixer_Freq22 {3} \ - CONFIG.DAC_Coarse_Mixer_Freq23 {3} \ - CONFIG.DAC_Coarse_Mixer_Freq30 {3} \ - CONFIG.DAC_Coarse_Mixer_Freq31 {3} \ - CONFIG.DAC_Coarse_Mixer_Freq32 {3} \ - CONFIG.DAC_Interpolation_Mode20 {1} \ - CONFIG.DAC_Interpolation_Mode21 {1} \ - CONFIG.DAC_Interpolation_Mode22 {1} \ - CONFIG.DAC_Interpolation_Mode23 {1} \ - CONFIG.DAC_Interpolation_Mode30 {1} \ - CONFIG.DAC_Interpolation_Mode31 {1} \ - CONFIG.DAC_Interpolation_Mode32 {1} \ - CONFIG.DAC_Mixer_Type20 {1} \ - CONFIG.DAC_Mixer_Type21 {1} \ - CONFIG.DAC_Mixer_Type22 {1} \ - CONFIG.DAC_Mixer_Type23 {1} \ - CONFIG.DAC_Mixer_Type30 {1} \ - CONFIG.DAC_Mixer_Type31 {1} \ - CONFIG.DAC_Mixer_Type32 {1} \ - CONFIG.DAC_Mode20 {3} \ - CONFIG.DAC_Mode21 {3} \ - CONFIG.DAC_Mode22 {3} \ - CONFIG.DAC_Mode23 {3} \ - CONFIG.DAC_Mode30 {3} \ - CONFIG.DAC_Mode31 {3} \ - CONFIG.DAC_Mode32 {3} \ - CONFIG.DAC_Slice20_Enable {true} \ - CONFIG.DAC_Slice21_Enable {true} \ - CONFIG.DAC_Slice22_Enable {true} \ - CONFIG.DAC_Slice23_Enable {true} \ - CONFIG.DAC_Slice30_Enable {true} \ - CONFIG.DAC_Slice31_Enable {true} \ - CONFIG.DAC_Slice32_Enable {true} \ - CONFIG.DAC_Slice33_Enable {false} \ - CONFIG.DAC_VOP_Mode {0} \ - ] $usp_rf_data_converter_0 - - # Create instance: vect2bits_16_0, and set properties - set block_name vect2bits_16 - set block_cell_name vect2bits_16_0 - if { [catch {set vect2bits_16_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { - catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} - return 1 - } elseif { $vect2bits_16_0 eq "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} - return 1 - } - - # Create instance: xlconcat_0, and set properties - set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] - - # Create instance: xlconstant_0, and set properties - set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - CONFIG.CONST_WIDTH {64} \ - ] $xlconstant_0 - - # Create instance: xlconstant_1, and set properties - set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {1} \ - CONFIG.CONST_WIDTH {1} \ - ] $xlconstant_1 - - # Create instance: xlconstant_2, and set properties - set xlconstant_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_2 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - CONFIG.CONST_WIDTH {8} \ - ] $xlconstant_2 - - # Create instance: xlconstant_3, and set properties - set xlconstant_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_3 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - CONFIG.CONST_WIDTH {1} \ - ] $xlconstant_3 - - # Create instance: xlconstant_4, and set properties - set xlconstant_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_4 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - CONFIG.CONST_WIDTH {12} \ - ] $xlconstant_4 - - # Create instance: zynq_ultra_ps_e_0, and set properties - set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ] - set_property -dict [ list \ - CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \ - CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \ - CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \ - CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {1} \ - CONFIG.PSU_MIO_0_DIRECTION {out} \ - CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_0_POLARITY {Default} \ - CONFIG.PSU_MIO_10_DIRECTION {inout} \ - CONFIG.PSU_MIO_10_POLARITY {Default} \ - CONFIG.PSU_MIO_11_DIRECTION {inout} \ - CONFIG.PSU_MIO_11_POLARITY {Default} \ - CONFIG.PSU_MIO_12_DIRECTION {out} \ - CONFIG.PSU_MIO_12_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_12_POLARITY {Default} \ - CONFIG.PSU_MIO_13_DIRECTION {inout} \ - CONFIG.PSU_MIO_13_POLARITY {Default} \ - CONFIG.PSU_MIO_14_DIRECTION {inout} \ - CONFIG.PSU_MIO_14_POLARITY {Default} \ - CONFIG.PSU_MIO_15_DIRECTION {inout} \ - CONFIG.PSU_MIO_15_POLARITY {Default} \ - CONFIG.PSU_MIO_16_DIRECTION {inout} \ - CONFIG.PSU_MIO_16_POLARITY {Default} \ - CONFIG.PSU_MIO_17_DIRECTION {inout} \ - CONFIG.PSU_MIO_17_POLARITY {Default} \ - CONFIG.PSU_MIO_18_DIRECTION {in} \ - CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_18_POLARITY {Default} \ - CONFIG.PSU_MIO_18_SLEW {fast} \ - CONFIG.PSU_MIO_19_DIRECTION {out} \ - CONFIG.PSU_MIO_19_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_19_POLARITY {Default} \ - CONFIG.PSU_MIO_1_DIRECTION {inout} \ - CONFIG.PSU_MIO_1_POLARITY {Default} \ - CONFIG.PSU_MIO_20_DIRECTION {inout} \ - CONFIG.PSU_MIO_20_POLARITY {Default} \ - CONFIG.PSU_MIO_21_DIRECTION {inout} \ - CONFIG.PSU_MIO_21_POLARITY {Default} \ - CONFIG.PSU_MIO_22_DIRECTION {inout} \ - CONFIG.PSU_MIO_22_POLARITY {Default} \ - CONFIG.PSU_MIO_23_DIRECTION {inout} \ - CONFIG.PSU_MIO_23_POLARITY {Default} \ - CONFIG.PSU_MIO_24_DIRECTION {inout} \ - CONFIG.PSU_MIO_24_POLARITY {Default} \ - CONFIG.PSU_MIO_25_DIRECTION {inout} \ - CONFIG.PSU_MIO_25_POLARITY {Default} \ - CONFIG.PSU_MIO_26_DIRECTION {inout} \ - CONFIG.PSU_MIO_26_POLARITY {Default} \ - CONFIG.PSU_MIO_27_DIRECTION {inout} \ - CONFIG.PSU_MIO_27_POLARITY {Default} \ - CONFIG.PSU_MIO_28_DIRECTION {inout} \ - CONFIG.PSU_MIO_28_POLARITY {Default} \ - CONFIG.PSU_MIO_29_DIRECTION {inout} \ - CONFIG.PSU_MIO_29_POLARITY {Default} \ - CONFIG.PSU_MIO_2_DIRECTION {inout} \ - CONFIG.PSU_MIO_2_POLARITY {Default} \ - CONFIG.PSU_MIO_30_DIRECTION {inout} \ - CONFIG.PSU_MIO_30_POLARITY {Default} \ - CONFIG.PSU_MIO_31_DIRECTION {inout} \ - CONFIG.PSU_MIO_31_POLARITY {Default} \ - CONFIG.PSU_MIO_32_DIRECTION {out} \ - CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_32_POLARITY {Default} \ - CONFIG.PSU_MIO_33_DIRECTION {out} \ - CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_33_POLARITY {Default} \ - CONFIG.PSU_MIO_34_DIRECTION {out} \ - CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_34_POLARITY {Default} \ - CONFIG.PSU_MIO_35_DIRECTION {out} \ - CONFIG.PSU_MIO_35_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_35_POLARITY {Default} \ - CONFIG.PSU_MIO_36_DIRECTION {out} \ - CONFIG.PSU_MIO_36_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_36_POLARITY {Default} \ - CONFIG.PSU_MIO_37_DIRECTION {out} \ - CONFIG.PSU_MIO_37_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_37_POLARITY {Default} \ - CONFIG.PSU_MIO_38_DIRECTION {inout} \ - CONFIG.PSU_MIO_38_POLARITY {Default} \ - CONFIG.PSU_MIO_39_DIRECTION {inout} \ - CONFIG.PSU_MIO_39_POLARITY {Default} \ - CONFIG.PSU_MIO_3_DIRECTION {inout} \ - CONFIG.PSU_MIO_3_POLARITY {Default} \ - CONFIG.PSU_MIO_40_DIRECTION {inout} \ - CONFIG.PSU_MIO_40_POLARITY {Default} \ - CONFIG.PSU_MIO_41_DIRECTION {inout} \ - CONFIG.PSU_MIO_41_POLARITY {Default} \ - CONFIG.PSU_MIO_42_DIRECTION {inout} \ - CONFIG.PSU_MIO_42_POLARITY {Default} \ - CONFIG.PSU_MIO_43_DIRECTION {inout} \ - CONFIG.PSU_MIO_43_POLARITY {Default} \ - CONFIG.PSU_MIO_44_DIRECTION {inout} \ - CONFIG.PSU_MIO_44_POLARITY {Default} \ - CONFIG.PSU_MIO_45_DIRECTION {in} \ - CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_45_POLARITY {Default} \ - CONFIG.PSU_MIO_45_SLEW {fast} \ - CONFIG.PSU_MIO_46_DIRECTION {inout} \ - CONFIG.PSU_MIO_46_POLARITY {Default} \ - CONFIG.PSU_MIO_47_DIRECTION {inout} \ - CONFIG.PSU_MIO_47_POLARITY {Default} \ - CONFIG.PSU_MIO_48_DIRECTION {inout} \ - CONFIG.PSU_MIO_48_POLARITY {Default} \ - CONFIG.PSU_MIO_49_DIRECTION {inout} \ - CONFIG.PSU_MIO_49_POLARITY {Default} \ - CONFIG.PSU_MIO_4_DIRECTION {inout} \ - CONFIG.PSU_MIO_4_POLARITY {Default} \ - CONFIG.PSU_MIO_50_DIRECTION {inout} \ - CONFIG.PSU_MIO_50_POLARITY {Default} \ - CONFIG.PSU_MIO_51_DIRECTION {out} \ - CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_51_POLARITY {Default} \ - CONFIG.PSU_MIO_52_DIRECTION {in} \ - CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_52_POLARITY {Default} \ - CONFIG.PSU_MIO_52_SLEW {fast} \ - CONFIG.PSU_MIO_53_DIRECTION {in} \ - CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_53_POLARITY {Default} \ - CONFIG.PSU_MIO_53_SLEW {fast} \ - CONFIG.PSU_MIO_54_DIRECTION {inout} \ - CONFIG.PSU_MIO_54_POLARITY {Default} \ - CONFIG.PSU_MIO_55_DIRECTION {in} \ - CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_55_POLARITY {Default} \ - CONFIG.PSU_MIO_55_SLEW {fast} \ - CONFIG.PSU_MIO_56_DIRECTION {inout} \ - CONFIG.PSU_MIO_56_POLARITY {Default} \ - CONFIG.PSU_MIO_57_DIRECTION {inout} \ - CONFIG.PSU_MIO_57_POLARITY {Default} \ - CONFIG.PSU_MIO_58_DIRECTION {out} \ - CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_58_POLARITY {Default} \ - CONFIG.PSU_MIO_59_DIRECTION {inout} \ - CONFIG.PSU_MIO_59_POLARITY {Default} \ - CONFIG.PSU_MIO_5_DIRECTION {out} \ - CONFIG.PSU_MIO_5_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_5_POLARITY {Default} \ - CONFIG.PSU_MIO_60_DIRECTION {inout} \ - CONFIG.PSU_MIO_60_POLARITY {Default} \ - CONFIG.PSU_MIO_61_DIRECTION {inout} \ - CONFIG.PSU_MIO_61_POLARITY {Default} \ - CONFIG.PSU_MIO_62_DIRECTION {inout} \ - CONFIG.PSU_MIO_62_POLARITY {Default} \ - CONFIG.PSU_MIO_63_DIRECTION {inout} \ - CONFIG.PSU_MIO_63_POLARITY {Default} \ - CONFIG.PSU_MIO_64_DIRECTION {out} \ - CONFIG.PSU_MIO_64_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_64_POLARITY {Default} \ - CONFIG.PSU_MIO_65_DIRECTION {out} \ - CONFIG.PSU_MIO_65_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_65_POLARITY {Default} \ - CONFIG.PSU_MIO_66_DIRECTION {out} \ - CONFIG.PSU_MIO_66_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_66_POLARITY {Default} \ - CONFIG.PSU_MIO_67_DIRECTION {out} \ - CONFIG.PSU_MIO_67_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_67_POLARITY {Default} \ - CONFIG.PSU_MIO_68_DIRECTION {out} \ - CONFIG.PSU_MIO_68_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_68_POLARITY {Default} \ - CONFIG.PSU_MIO_69_DIRECTION {out} \ - CONFIG.PSU_MIO_69_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_69_POLARITY {Default} \ - CONFIG.PSU_MIO_6_DIRECTION {out} \ - CONFIG.PSU_MIO_6_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_6_POLARITY {Default} \ - CONFIG.PSU_MIO_70_DIRECTION {in} \ - CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_70_POLARITY {Default} \ - CONFIG.PSU_MIO_70_SLEW {fast} \ - CONFIG.PSU_MIO_71_DIRECTION {in} \ - CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_71_POLARITY {Default} \ - CONFIG.PSU_MIO_71_SLEW {fast} \ - CONFIG.PSU_MIO_72_DIRECTION {in} \ - CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_72_POLARITY {Default} \ - CONFIG.PSU_MIO_72_SLEW {fast} \ - CONFIG.PSU_MIO_73_DIRECTION {in} \ - CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_73_POLARITY {Default} \ - CONFIG.PSU_MIO_73_SLEW {fast} \ - CONFIG.PSU_MIO_74_DIRECTION {in} \ - CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_74_POLARITY {Default} \ - CONFIG.PSU_MIO_74_SLEW {fast} \ - CONFIG.PSU_MIO_75_DIRECTION {in} \ - CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_75_POLARITY {Default} \ - CONFIG.PSU_MIO_75_SLEW {fast} \ - CONFIG.PSU_MIO_76_DIRECTION {out} \ - CONFIG.PSU_MIO_76_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_76_POLARITY {Default} \ - CONFIG.PSU_MIO_77_DIRECTION {inout} \ - CONFIG.PSU_MIO_77_POLARITY {Default} \ - CONFIG.PSU_MIO_7_DIRECTION {out} \ - CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_7_POLARITY {Default} \ - CONFIG.PSU_MIO_8_DIRECTION {inout} \ - CONFIG.PSU_MIO_8_POLARITY {Default} \ - CONFIG.PSU_MIO_9_DIRECTION {inout} \ - CONFIG.PSU_MIO_9_POLARITY {Default} \ - CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO0 MIO#I2C 0#I2C 0#I2C 1#I2C 1#UART 0#UART 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#PMU GPO 3#PMU GPO 4#PMU GPO 5#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3} \ - CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#gpio0[13]#scl_out#sda_out#scl_out#sda_out#rxd#txd#gpio0[20]#gpio0[21]#gpio0[22]#gpio0[23]#gpio0[24]#gpio0[25]#gpio1[26]#gpio1[27]#gpio1[28]#gpio1[29]#gpio1[30]#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpo[3]#gpo[4]#gpo[5]#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#gpio1[43]#gpio1[44]#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out} \ - CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {8} \ - CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \ - CONFIG.PSU__ACT_DDR_FREQ_MHZ {1049.999878} \ - CONFIG.PSU__AFI0_COHERENCY {0} \ - CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \ - CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1199.999756} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {249.999954} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {249.999954} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {524.999939} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1066} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {599.999878} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {63} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {63} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {10} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {599.999878} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \ - CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {249.999954} \ - CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {99.999985} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {524.999939} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {90} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {499.999908} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {49.999992} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {499.999908} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {249.999954} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1499.999756} \ - CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {124.999977} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {249.999954} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {99.999985} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {99.999985} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {249.999954} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {99.999985} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {499.999908} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.499969} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {99.999985} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {124.999977} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {90} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {7} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.499969} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {7} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {7} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {99.999985} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {99.999985} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {99.999001} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {249.999954} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {19.999996} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \ - CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \ - CONFIG.PSU__DDRC__ADDR_MIRROR {0} \ - CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \ - CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \ - CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \ - CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \ - CONFIG.PSU__DDRC__CL {15} \ - CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \ - CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \ - CONFIG.PSU__DDRC__COMPONENTS {UDIMM} \ - CONFIG.PSU__DDRC__CWL {11} \ - CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \ - CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \ - CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \ - CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \ - CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \ - CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \ - CONFIG.PSU__DDRC__DEVICE_CAPACITY {8192 MBits} \ - CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \ - CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \ - CONFIG.PSU__DDRC__DQMAP_0_3 {0} \ - CONFIG.PSU__DDRC__DQMAP_12_15 {0} \ - CONFIG.PSU__DDRC__DQMAP_16_19 {0} \ - CONFIG.PSU__DDRC__DQMAP_20_23 {0} \ - CONFIG.PSU__DDRC__DQMAP_24_27 {0} \ - CONFIG.PSU__DDRC__DQMAP_28_31 {0} \ - CONFIG.PSU__DDRC__DQMAP_32_35 {0} \ - CONFIG.PSU__DDRC__DQMAP_36_39 {0} \ - CONFIG.PSU__DDRC__DQMAP_40_43 {0} \ - CONFIG.PSU__DDRC__DQMAP_44_47 {0} \ - CONFIG.PSU__DDRC__DQMAP_48_51 {0} \ - CONFIG.PSU__DDRC__DQMAP_4_7 {0} \ - CONFIG.PSU__DDRC__DQMAP_52_55 {0} \ - CONFIG.PSU__DDRC__DQMAP_56_59 {0} \ - CONFIG.PSU__DDRC__DQMAP_60_63 {0} \ - CONFIG.PSU__DDRC__DQMAP_64_67 {0} \ - CONFIG.PSU__DDRC__DQMAP_68_71 {0} \ - CONFIG.PSU__DDRC__DQMAP_8_11 {0} \ - CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \ - CONFIG.PSU__DDRC__ECC {Disabled} \ - CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \ - CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \ - CONFIG.PSU__DDRC__FGRM {1X} \ - CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__LP_ASR {manual normal} \ - CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \ - CONFIG.PSU__DDRC__PARITY_ENABLE {0} \ - CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \ - CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \ - CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \ - CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \ - CONFIG.PSU__DDRC__SB_TARGET {15-15-15} \ - CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \ - CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \ - CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \ - CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \ - CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \ - CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \ - CONFIG.PSU__DDRC__T_FAW {30.0} \ - CONFIG.PSU__DDRC__T_RAS_MIN {33} \ - CONFIG.PSU__DDRC__T_RC {46.5} \ - CONFIG.PSU__DDRC__T_RCD {15} \ - CONFIG.PSU__DDRC__T_RP {15} \ - CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \ - CONFIG.PSU__DDRC__VREF {1} \ - CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \ - CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.000} \ - CONFIG.PSU__DLL__ISUSED {1} \ - CONFIG.PSU__ENET3__FIFO__ENABLE {0} \ - CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \ - CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \ - CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \ - CONFIG.PSU__ENET3__PTP__ENABLE {0} \ - CONFIG.PSU__ENET3__TSU__ENABLE {0} \ - CONFIG.PSU__FPDMASTERS_COHERENCY {0} \ - CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {99.999985} \ - CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {99.999985} \ - CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \ - CONFIG.PSU__FPGA_PL0_ENABLE {1} \ - CONFIG.PSU__GEM3_COHERENCY {0} \ - CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__GEM__TSU__ENABLE {0} \ - CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \ - CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \ - CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__HIGH_ADDRESS__ENABLE {1} \ - CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 14 .. 15} \ - CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \ - CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \ - CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \ - CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \ - CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \ - CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {99.999985} \ - CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {99.999985} \ - CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \ - CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \ - CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \ - CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \ - CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \ - CONFIG.PSU__PL_CLK0_BUF {TRUE} \ - CONFIG.PSU__PMU_COHERENCY {0} \ - CONFIG.PSU__PMU__AIBACK__ENABLE {0} \ - CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \ - CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \ - CONFIG.PSU__PMU__GPI0__ENABLE {0} \ - CONFIG.PSU__PMU__GPI1__ENABLE {0} \ - CONFIG.PSU__PMU__GPI2__ENABLE {0} \ - CONFIG.PSU__PMU__GPI3__ENABLE {0} \ - CONFIG.PSU__PMU__GPI4__ENABLE {0} \ - CONFIG.PSU__PMU__GPI5__ENABLE {0} \ - CONFIG.PSU__PMU__GPO0__ENABLE {1} \ - CONFIG.PSU__PMU__GPO0__IO {MIO 32} \ - CONFIG.PSU__PMU__GPO1__ENABLE {1} \ - CONFIG.PSU__PMU__GPO1__IO {MIO 33} \ - CONFIG.PSU__PMU__GPO2__ENABLE {1} \ - CONFIG.PSU__PMU__GPO2__IO {MIO 34} \ - CONFIG.PSU__PMU__GPO2__POLARITY {low} \ - CONFIG.PSU__PMU__GPO3__ENABLE {1} \ - CONFIG.PSU__PMU__GPO3__IO {MIO 35} \ - CONFIG.PSU__PMU__GPO3__POLARITY {low} \ - CONFIG.PSU__PMU__GPO4__ENABLE {1} \ - CONFIG.PSU__PMU__GPO4__IO {MIO 36} \ - CONFIG.PSU__PMU__GPO4__POLARITY {low} \ - CONFIG.PSU__PMU__GPO5__ENABLE {1} \ - CONFIG.PSU__PMU__GPO5__IO {MIO 37} \ - CONFIG.PSU__PMU__GPO5__POLARITY {low} \ - CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__PMU__PLERROR__ENABLE {0} \ - CONFIG.PSU__PRESET_APPLIED {1} \ - CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;1|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;0|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \ - CONFIG.PSU__PROTECTION__SLAVES { \ - LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;0|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1 \ - } \ - CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.33333} \ - CONFIG.PSU__QSPI_COHERENCY {0} \ - CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \ - CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \ - CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \ - CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 12} \ - CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel} \ - CONFIG.PSU__SATA__LANE0__ENABLE {0} \ - CONFIG.PSU__SATA__LANE1__ENABLE {1} \ - CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \ - CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__SATA__REF_CLK_FREQ {125} \ - CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk3} \ - CONFIG.PSU__SAXIGP0__DATA_WIDTH {128} \ - CONFIG.PSU__SD1_COHERENCY {0} \ - CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__SD1__DATA_TRANSFER_MODE {8Bit} \ - CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \ - CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \ - CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \ - CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \ - CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 39 .. 51} \ - CONFIG.PSU__SD1__RESET__ENABLE {0} \ - CONFIG.PSU__SD1__SLOT_TYPE {SD 3.0} \ - CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \ - CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__SWDT0__RESET__ENABLE {0} \ - CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \ - CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__SWDT1__RESET__ENABLE {0} \ - CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \ - CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \ - CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \ - CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \ - CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \ - CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \ - CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \ - CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \ - CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \ - CONFIG.PSU__UART0__BAUD_RATE {115200} \ - CONFIG.PSU__UART0__MODEM__ENABLE {0} \ - CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \ - CONFIG.PSU__UART1__MODEM__ENABLE {0} \ - CONFIG.PSU__UART1__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__USB0_COHERENCY {0} \ - CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \ - CONFIG.PSU__USB0__REF_CLK_FREQ {26} \ - CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \ - CONFIG.PSU__USB0__RESET__ENABLE {0} \ - CONFIG.PSU__USB1__RESET__ENABLE {0} \ - CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \ - CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \ - CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \ - CONFIG.PSU__USB__RESET__MODE {Boot Pin} \ - CONFIG.PSU__USB__RESET__POLARITY {Active Low} \ - CONFIG.PSU__USE__IRQ0 {1} \ - CONFIG.PSU__USE__M_AXI_GP0 {1} \ - CONFIG.PSU__USE__M_AXI_GP1 {0} \ - CONFIG.PSU__USE__M_AXI_GP2 {0} \ - CONFIG.PSU__USE__S_AXI_GP0 {1} \ - CONFIG.SUBPRESET1 {Custom} \ - ] $zynq_ultra_ps_e_0 - - # Create interface connections - connect_bd_intf_net -intf_net adc2_clk_0_1 [get_bd_intf_ports adc2_clk_0] [get_bd_intf_pins usp_rf_data_converter_0/adc2_clk] - connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins axi_bram_ctrl_0_bram/BRAM_PORTA] - connect_bd_intf_net -intf_net axi_dma_0_M_AXIS_MM2S [get_bd_intf_pins axi_dma_tproc/M_AXIS_MM2S] [get_bd_intf_pins axis_tproc64x32_x8_0/s0_axis] - connect_bd_intf_net -intf_net axi_dma_0_M_AXIS_MM2S1 [get_bd_intf_pins axi_dma_gen/M_AXIS_MM2S] [get_bd_intf_pins axis_switch_gen/S00_AXIS] - connect_bd_intf_net -intf_net axi_dma_0_M_AXI_MM2S [get_bd_intf_pins axi_dma_tproc/M_AXI_MM2S] [get_bd_intf_pins axi_smc/S00_AXI] - connect_bd_intf_net -intf_net axi_dma_0_M_AXI_MM2S1 [get_bd_intf_pins axi_dma_gen/M_AXI_MM2S] [get_bd_intf_pins axi_smc/S02_AXI] - connect_bd_intf_net -intf_net axi_dma_0_M_AXI_S2MM [get_bd_intf_pins axi_dma_tproc/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S01_AXI] - connect_bd_intf_net -intf_net axi_dma_avg_M_AXI_S2MM [get_bd_intf_pins axi_dma_avg/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S03_AXI] - connect_bd_intf_net -intf_net axi_dma_buf_M_AXI_S2MM [get_bd_intf_pins axi_dma_buf/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S04_AXI] - connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins axi_dma_tproc/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI] - connect_bd_intf_net -intf_net axi_interconnect_0_M08_AXI [get_bd_intf_pins ps8_0_axi_periph/M08_AXI] [get_bd_intf_pins usp_rf_data_converter_0/s_axi] - connect_bd_intf_net -intf_net axis_avg_buffer_0_m0_axis [get_bd_intf_pins axis_avg_buffer_0/m0_axis] [get_bd_intf_pins axis_switch_avg/S00_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_0_m1_axis [get_bd_intf_pins axis_avg_buffer_0/m1_axis] [get_bd_intf_pins axis_switch_buf/S00_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_0_m2_axis [get_bd_intf_pins axis_avg_buffer_0/m2_axis] [get_bd_intf_pins axis_clk_cnvrt_avg_0/S_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_1_m0_axis [get_bd_intf_pins axis_avg_buffer_1/m0_axis] [get_bd_intf_pins axis_switch_avg/S01_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_1_m1_axis [get_bd_intf_pins axis_avg_buffer_1/m1_axis] [get_bd_intf_pins axis_switch_buf/S01_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_1_m2_axis [get_bd_intf_pins axis_avg_buffer_1/m2_axis] [get_bd_intf_pins axis_clk_cnvrt_avg_1/S_AXIS] - connect_bd_intf_net -intf_net axis_cdcsync_v1_0_m0_axis [get_bd_intf_pins axis_cdcsync_v1_0/m0_axis] [get_bd_intf_pins axis_signal_gen_v6_0/s1_axis] - connect_bd_intf_net -intf_net axis_cdcsync_v1_0_m1_axis [get_bd_intf_pins axis_cdcsync_v1_0/m1_axis] [get_bd_intf_pins axis_signal_gen_v6_1/s1_axis] - connect_bd_intf_net -intf_net axis_cdcsync_v1_0_m2_axis [get_bd_intf_pins axis_cdcsync_v1_0/m2_axis] [get_bd_intf_pins axis_signal_gen_v6_2/s1_axis] - connect_bd_intf_net -intf_net axis_cdcsync_v1_0_m3_axis [get_bd_intf_pins axis_cdcsync_v1_0/m3_axis] [get_bd_intf_pins axis_signal_gen_v6_3/s1_axis] - connect_bd_intf_net -intf_net axis_cdcsync_v1_1_m0_axis [get_bd_intf_pins axis_cdcsync_v1_1/m0_axis] [get_bd_intf_pins axis_signal_gen_v6_4/s1_axis] - connect_bd_intf_net -intf_net axis_cdcsync_v1_1_m1_axis [get_bd_intf_pins axis_cdcsync_v1_1/m1_axis] [get_bd_intf_pins axis_signal_gen_v6_5/s1_axis] - connect_bd_intf_net -intf_net axis_cdcsync_v1_1_m2_axis [get_bd_intf_pins axis_cdcsync_v1_1/m2_axis] [get_bd_intf_pins axis_signal_gen_v6_6/s1_axis] - connect_bd_intf_net -intf_net axis_clk_cnvrt_avg_0_M_AXIS [get_bd_intf_pins axis_clk_cnvrt_avg_0/M_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/s1_axis] - connect_bd_intf_net -intf_net axis_clk_cnvrt_avg_1_M_AXIS [get_bd_intf_pins axis_clk_cnvrt_avg_1/M_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/s2_axis] - connect_bd_intf_net -intf_net axis_constant_0_m_axis [get_bd_intf_pins axis_constant_0/m_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/s3_axis] - connect_bd_intf_net -intf_net axis_constant_1_m_axis [get_bd_intf_pins axis_constant_1/m_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/s4_axis] - connect_bd_intf_net -intf_net axis_constant_2_m_axis [get_bd_intf_pins axis_cdcsync_v1_1/s3_axis] [get_bd_intf_pins axis_constant_2/m_axis] - connect_bd_intf_net -intf_net axis_readout_v2_0_m0_axis [get_bd_intf_pins axis_readout_v2_0/m0_axis] [get_bd_intf_pins axis_terminator_0/s_axis] - connect_bd_intf_net -intf_net axis_readout_v2_0_m1_axis [get_bd_intf_pins axis_avg_buffer_0/s_axis] [get_bd_intf_pins axis_readout_v2_0/m1_axis] - connect_bd_intf_net -intf_net axis_readout_v2_1_m0_axis [get_bd_intf_pins axis_readout_v2_1/m0_axis] [get_bd_intf_pins axis_terminator_1/s_axis] - connect_bd_intf_net -intf_net axis_readout_v2_1_m1_axis [get_bd_intf_pins axis_avg_buffer_1/s_axis] [get_bd_intf_pins axis_readout_v2_1/m1_axis] - connect_bd_intf_net -intf_net axis_register_slice_0_M_AXIS [get_bd_intf_pins axis_readout_v2_0/s_axis] [get_bd_intf_pins axis_register_slice_0/M_AXIS] - connect_bd_intf_net -intf_net axis_register_slice_1_M_AXIS [get_bd_intf_pins axis_readout_v2_1/s_axis] [get_bd_intf_pins axis_register_slice_1/M_AXIS] - connect_bd_intf_net -intf_net axis_register_slice_2_M_AXIS [get_bd_intf_pins axis_register_slice_2/M_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/s20_axis] - connect_bd_intf_net -intf_net axis_register_slice_3_M_AXIS [get_bd_intf_pins axis_register_slice_3/M_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/s21_axis] - connect_bd_intf_net -intf_net axis_register_slice_4_M_AXIS [get_bd_intf_pins axis_register_slice_4/M_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/s22_axis] - connect_bd_intf_net -intf_net axis_register_slice_5_M_AXIS [get_bd_intf_pins axis_register_slice_5/M_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/s23_axis] - connect_bd_intf_net -intf_net axis_register_slice_6_M_AXIS [get_bd_intf_pins axis_register_slice_6/M_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/s30_axis] - connect_bd_intf_net -intf_net axis_register_slice_7_M_AXIS [get_bd_intf_pins axis_register_slice_7/M_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/s31_axis] - connect_bd_intf_net -intf_net axis_register_slice_8_M_AXIS [get_bd_intf_pins axis_register_slice_8/M_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/s32_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v6_0_m_axis [get_bd_intf_pins axis_register_slice_2/S_AXIS] [get_bd_intf_pins axis_signal_gen_v6_0/m_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v6_1_m_axis [get_bd_intf_pins axis_register_slice_3/S_AXIS] [get_bd_intf_pins axis_signal_gen_v6_1/m_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v6_2_m_axis [get_bd_intf_pins axis_register_slice_4/S_AXIS] [get_bd_intf_pins axis_signal_gen_v6_2/m_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v6_3_m_axis [get_bd_intf_pins axis_register_slice_5/S_AXIS] [get_bd_intf_pins axis_signal_gen_v6_3/m_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v6_4_m_axis [get_bd_intf_pins axis_register_slice_6/S_AXIS] [get_bd_intf_pins axis_signal_gen_v6_4/m_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v6_5_m_axis [get_bd_intf_pins axis_register_slice_7/S_AXIS] [get_bd_intf_pins axis_signal_gen_v6_5/m_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v6_6_m_axis [get_bd_intf_pins axis_register_slice_8/S_AXIS] [get_bd_intf_pins axis_signal_gen_v6_6/m_axis] - connect_bd_intf_net -intf_net axis_switch_0_M00_AXIS [get_bd_intf_pins axis_signal_gen_v6_0/s0_axis] [get_bd_intf_pins axis_switch_gen/M00_AXIS] - connect_bd_intf_net -intf_net axis_switch_0_M01_AXIS [get_bd_intf_pins axis_signal_gen_v6_1/s0_axis] [get_bd_intf_pins axis_switch_gen/M01_AXIS] - connect_bd_intf_net -intf_net axis_switch_0_M02_AXIS [get_bd_intf_pins axis_signal_gen_v6_2/s0_axis] [get_bd_intf_pins axis_switch_gen/M02_AXIS] - connect_bd_intf_net -intf_net axis_switch_0_M03_AXIS [get_bd_intf_pins axis_signal_gen_v6_3/s0_axis] [get_bd_intf_pins axis_switch_gen/M03_AXIS] - connect_bd_intf_net -intf_net axis_switch_0_M04_AXIS [get_bd_intf_pins axis_signal_gen_v6_4/s0_axis] [get_bd_intf_pins axis_switch_gen/M04_AXIS] - connect_bd_intf_net -intf_net axis_switch_0_M05_AXIS [get_bd_intf_pins axis_signal_gen_v6_5/s0_axis] [get_bd_intf_pins axis_switch_gen/M05_AXIS] - connect_bd_intf_net -intf_net axis_switch_0_M06_AXIS [get_bd_intf_pins axis_signal_gen_v6_6/s0_axis] [get_bd_intf_pins axis_switch_gen/M06_AXIS] - connect_bd_intf_net -intf_net axis_switch_avg_M00_AXIS [get_bd_intf_pins axi_dma_avg/S_AXIS_S2MM] [get_bd_intf_pins axis_switch_avg/M00_AXIS] - connect_bd_intf_net -intf_net axis_switch_buf_M00_AXIS [get_bd_intf_pins axi_dma_buf/S_AXIS_S2MM] [get_bd_intf_pins axis_switch_buf/M00_AXIS] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m0_axis [get_bd_intf_pins axi_dma_tproc/S_AXIS_S2MM] [get_bd_intf_pins axis_tproc64x32_x8_0/m0_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m1_axis [get_bd_intf_pins axis_set_reg_0/s_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m1_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m2_axis [get_bd_intf_pins axis_cdcsync_v1_0/s0_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m2_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m3_axis [get_bd_intf_pins axis_cdcsync_v1_0/s1_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m3_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m4_axis [get_bd_intf_pins axis_cdcsync_v1_0/s2_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m4_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m5_axis [get_bd_intf_pins axis_cdcsync_v1_0/s3_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m5_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m6_axis [get_bd_intf_pins axis_cdcsync_v1_1/s0_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m6_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m7_axis [get_bd_intf_pins axis_cdcsync_v1_1/s1_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m7_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m8_axis [get_bd_intf_pins axis_cdcsync_v1_1/s2_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m8_axis] - connect_bd_intf_net -intf_net dac2_clk_0_1 [get_bd_intf_ports dac2_clk_0] [get_bd_intf_pins usp_rf_data_converter_0/dac2_clk] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M01_AXI [get_bd_intf_pins axis_tproc64x32_x8_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M01_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M02_AXI [get_bd_intf_pins axis_signal_gen_v6_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M02_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M03_AXI [get_bd_intf_pins axis_signal_gen_v6_1/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M03_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M04_AXI [get_bd_intf_pins axis_signal_gen_v6_2/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M04_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M05_AXI [get_bd_intf_pins axis_signal_gen_v6_3/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M05_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M06_AXI [get_bd_intf_pins axi_dma_gen/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M06_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M07_AXI [get_bd_intf_pins axis_switch_gen/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M07_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M09_AXI [get_bd_intf_pins axis_avg_buffer_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M09_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M10_AXI [get_bd_intf_pins axis_avg_buffer_1/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M10_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M11_AXI [get_bd_intf_pins axis_signal_gen_v6_4/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M11_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M12_AXI [get_bd_intf_pins axis_signal_gen_v6_5/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M12_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M13_AXI [get_bd_intf_pins axi_bram_ctrl_0/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M13_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M14_AXI [get_bd_intf_pins axis_signal_gen_v6_6/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M14_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M15_AXI [get_bd_intf_pins axis_readout_v2_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M15_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M16_AXI [get_bd_intf_pins axis_readout_v2_1/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M16_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M17_AXI [get_bd_intf_pins axis_switch_avg/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M17_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M18_AXI [get_bd_intf_pins axis_switch_buf/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M18_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M19_AXI [get_bd_intf_pins axi_dma_avg/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M19_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M20_AXI [get_bd_intf_pins axi_dma_buf/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M20_AXI] - connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins axi_smc/M00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HPC0_FPD] - connect_bd_intf_net -intf_net sysref_in_0_1 [get_bd_intf_ports sysref_in_0] [get_bd_intf_pins usp_rf_data_converter_0/sysref_in] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_m20_axis [get_bd_intf_pins axis_register_slice_0/S_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/m20_axis] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_m22_axis [get_bd_intf_pins axis_register_slice_1/S_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/m22_axis] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout20 [get_bd_intf_ports vout0] [get_bd_intf_pins usp_rf_data_converter_0/vout20] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout21 [get_bd_intf_ports vout1] [get_bd_intf_pins usp_rf_data_converter_0/vout21] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout22 [get_bd_intf_ports vout2] [get_bd_intf_pins usp_rf_data_converter_0/vout22] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout23 [get_bd_intf_ports vout3] [get_bd_intf_pins usp_rf_data_converter_0/vout23] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout30 [get_bd_intf_ports vout4] [get_bd_intf_pins usp_rf_data_converter_0/vout30] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout31 [get_bd_intf_ports vout5] [get_bd_intf_pins usp_rf_data_converter_0/vout31] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout32 [get_bd_intf_ports vout6] [get_bd_intf_pins usp_rf_data_converter_0/vout32] - connect_bd_intf_net -intf_net vin20_0_1 [get_bd_intf_ports vin20_0] [get_bd_intf_pins usp_rf_data_converter_0/vin20] - connect_bd_intf_net -intf_net vin22_0_1 [get_bd_intf_ports vin22_0] [get_bd_intf_pins usp_rf_data_converter_0/vin22] - connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD] - - # Create port connections - connect_bd_net -net PMOD1_0_LS_1 [get_bd_ports PMOD1_0_LS] [get_bd_pins axis_tproc64x32_x8_0/start] - connect_bd_net -net axi_bram_ctrl_0_bram_doutb [get_bd_pins axi_bram_ctrl_0_bram/doutb] [get_bd_pins axis_tproc64x32_x8_0/pmem_do] - connect_bd_net -net axis_set_reg_0_dout [get_bd_pins axis_set_reg_0/dout] [get_bd_pins vect2bits_16_0/din] - connect_bd_net -net axis_tproc64x32_x8_0_pmem_addr [get_bd_pins axis_tproc64x32_x8_0/pmem_addr] [get_bd_pins xlconcat_0/In0] - connect_bd_net -net rst_adc_peripheral_aresetn [get_bd_pins axis_avg_buffer_0/s_axis_aresetn] [get_bd_pins axis_avg_buffer_1/s_axis_aresetn] [get_bd_pins axis_readout_v2_0/aresetn] [get_bd_pins axis_readout_v2_1/aresetn] [get_bd_pins axis_register_slice_0/aresetn] [get_bd_pins axis_register_slice_1/aresetn] [get_bd_pins axis_terminator_0/s_axis_aresetn] [get_bd_pins axis_terminator_1/s_axis_aresetn] [get_bd_pins rst_adc/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/m2_axis_aresetn] - connect_bd_net -net rst_dac2_peripheral_aresetn [get_bd_pins axis_cdcsync_v1_0/m_axis_aresetn] [get_bd_pins axis_cdcsync_v1_0/s_axis_aresetn] [get_bd_pins axis_cdcsync_v1_1/s_axis_aresetn] [get_bd_pins axis_clk_cnvrt_avg_0/m_axis_aresetn] [get_bd_pins axis_clk_cnvrt_avg_1/m_axis_aresetn] [get_bd_pins axis_constant_0/m_axis_aresetn] [get_bd_pins axis_constant_1/m_axis_aresetn] [get_bd_pins axis_constant_2/m_axis_aresetn] [get_bd_pins axis_register_slice_2/aresetn] [get_bd_pins axis_register_slice_3/aresetn] [get_bd_pins axis_register_slice_4/aresetn] [get_bd_pins axis_register_slice_5/aresetn] [get_bd_pins axis_set_reg_0/s_axis_aresetn] [get_bd_pins axis_signal_gen_v6_0/aresetn] [get_bd_pins axis_signal_gen_v6_1/aresetn] [get_bd_pins axis_signal_gen_v6_2/aresetn] [get_bd_pins axis_signal_gen_v6_3/aresetn] [get_bd_pins axis_tproc64x32_x8_0/aresetn] [get_bd_pins rst_dac2/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/s2_axis_aresetn] - connect_bd_net -net rst_dac3_peripheral_aresetn [get_bd_pins axis_cdcsync_v1_1/m_axis_aresetn] [get_bd_pins axis_register_slice_6/aresetn] [get_bd_pins axis_register_slice_7/aresetn] [get_bd_pins axis_register_slice_8/aresetn] [get_bd_pins axis_signal_gen_v6_4/aresetn] [get_bd_pins axis_signal_gen_v6_5/aresetn] [get_bd_pins axis_signal_gen_v6_6/aresetn] [get_bd_pins rst_dac3/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/s3_axis_aresetn] - connect_bd_net -net rst_ps8_0_99M_peripheral_aresetn [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_dma_avg/axi_resetn] [get_bd_pins axi_dma_buf/axi_resetn] [get_bd_pins axi_dma_gen/axi_resetn] [get_bd_pins axi_dma_tproc/axi_resetn] [get_bd_pins axi_smc/aresetn] [get_bd_pins axis_avg_buffer_0/m_axis_aresetn] [get_bd_pins axis_avg_buffer_0/s_axi_aresetn] [get_bd_pins axis_avg_buffer_1/m_axis_aresetn] [get_bd_pins axis_avg_buffer_1/s_axi_aresetn] [get_bd_pins axis_clk_cnvrt_avg_0/s_axis_aresetn] [get_bd_pins axis_clk_cnvrt_avg_1/s_axis_aresetn] [get_bd_pins axis_readout_v2_0/s_axi_aresetn] [get_bd_pins axis_readout_v2_1/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_0/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_0/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_1/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_1/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_2/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_2/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_3/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_3/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_4/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_4/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_5/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_5/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_6/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_6/s_axi_aresetn] [get_bd_pins axis_switch_avg/aresetn] [get_bd_pins axis_switch_avg/s_axi_ctrl_aresetn] [get_bd_pins axis_switch_buf/aresetn] [get_bd_pins axis_switch_buf/s_axi_ctrl_aresetn] [get_bd_pins axis_switch_gen/aresetn] [get_bd_pins axis_switch_gen/s_axi_ctrl_aresetn] [get_bd_pins axis_tproc64x32_x8_0/m0_axis_aresetn] [get_bd_pins axis_tproc64x32_x8_0/s0_axis_aresetn] [get_bd_pins axis_tproc64x32_x8_0/s_axi_aresetn] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/M01_ARESETN] [get_bd_pins ps8_0_axi_periph/M02_ARESETN] [get_bd_pins ps8_0_axi_periph/M03_ARESETN] [get_bd_pins ps8_0_axi_periph/M04_ARESETN] [get_bd_pins ps8_0_axi_periph/M05_ARESETN] [get_bd_pins ps8_0_axi_periph/M06_ARESETN] [get_bd_pins ps8_0_axi_periph/M07_ARESETN] [get_bd_pins ps8_0_axi_periph/M08_ARESETN] [get_bd_pins ps8_0_axi_periph/M09_ARESETN] [get_bd_pins ps8_0_axi_periph/M10_ARESETN] [get_bd_pins ps8_0_axi_periph/M11_ARESETN] [get_bd_pins ps8_0_axi_periph/M12_ARESETN] [get_bd_pins ps8_0_axi_periph/M13_ARESETN] [get_bd_pins ps8_0_axi_periph/M14_ARESETN] [get_bd_pins ps8_0_axi_periph/M15_ARESETN] [get_bd_pins ps8_0_axi_periph/M16_ARESETN] [get_bd_pins ps8_0_axi_periph/M17_ARESETN] [get_bd_pins ps8_0_axi_periph/M18_ARESETN] [get_bd_pins ps8_0_axi_periph/M19_ARESETN] [get_bd_pins ps8_0_axi_periph/M20_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins rst_100/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/s_axi_aresetn] - connect_bd_net -net usp_rf_data_converter_0_clk_adc2 [get_bd_pins axis_avg_buffer_0/s_axis_aclk] [get_bd_pins axis_avg_buffer_1/s_axis_aclk] [get_bd_pins axis_readout_v2_0/aclk] [get_bd_pins axis_readout_v2_1/aclk] [get_bd_pins axis_register_slice_0/aclk] [get_bd_pins axis_register_slice_1/aclk] [get_bd_pins axis_terminator_0/s_axis_aclk] [get_bd_pins axis_terminator_1/s_axis_aclk] [get_bd_pins rst_adc/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/clk_adc2] [get_bd_pins usp_rf_data_converter_0/m2_axis_aclk] - connect_bd_net -net usp_rf_data_converter_0_clk_dac2 [get_bd_pins axi_bram_ctrl_0_bram/clkb] [get_bd_pins axis_cdcsync_v1_0/m_axis_aclk] [get_bd_pins axis_cdcsync_v1_0/s_axis_aclk] [get_bd_pins axis_cdcsync_v1_1/s_axis_aclk] [get_bd_pins axis_clk_cnvrt_avg_0/m_axis_aclk] [get_bd_pins axis_clk_cnvrt_avg_1/m_axis_aclk] [get_bd_pins axis_constant_0/m_axis_aclk] [get_bd_pins axis_constant_1/m_axis_aclk] [get_bd_pins axis_constant_2/m_axis_aclk] [get_bd_pins axis_register_slice_2/aclk] [get_bd_pins axis_register_slice_3/aclk] [get_bd_pins axis_register_slice_4/aclk] [get_bd_pins axis_register_slice_5/aclk] [get_bd_pins axis_set_reg_0/s_axis_aclk] [get_bd_pins axis_signal_gen_v6_0/aclk] [get_bd_pins axis_signal_gen_v6_1/aclk] [get_bd_pins axis_signal_gen_v6_2/aclk] [get_bd_pins axis_signal_gen_v6_3/aclk] [get_bd_pins axis_tproc64x32_x8_0/aclk] [get_bd_pins rst_dac2/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/clk_dac2] [get_bd_pins usp_rf_data_converter_0/s2_axis_aclk] - connect_bd_net -net usp_rf_data_converter_0_clk_dac3 [get_bd_pins axis_cdcsync_v1_1/m_axis_aclk] [get_bd_pins axis_register_slice_6/aclk] [get_bd_pins axis_register_slice_7/aclk] [get_bd_pins axis_register_slice_8/aclk] [get_bd_pins axis_signal_gen_v6_4/aclk] [get_bd_pins axis_signal_gen_v6_5/aclk] [get_bd_pins axis_signal_gen_v6_6/aclk] [get_bd_pins rst_dac3/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/clk_dac3] [get_bd_pins usp_rf_data_converter_0/s3_axis_aclk] - connect_bd_net -net vect2bits_16_0_dout0 [get_bd_ports PMOD0_0_LS] [get_bd_pins vect2bits_16_0/dout0] - connect_bd_net -net vect2bits_16_0_dout1 [get_bd_ports PMOD0_1_LS] [get_bd_pins vect2bits_16_0/dout1] - connect_bd_net -net vect2bits_16_0_dout2 [get_bd_ports PMOD0_2_LS] [get_bd_pins vect2bits_16_0/dout2] - connect_bd_net -net vect2bits_16_0_dout3 [get_bd_ports PMOD0_3_LS] [get_bd_pins vect2bits_16_0/dout3] - connect_bd_net -net vect2bits_16_0_dout4 [get_bd_ports PMOD0_4_LS] [get_bd_pins vect2bits_16_0/dout4] - connect_bd_net -net vect2bits_16_0_dout5 [get_bd_ports PMOD0_5_LS] [get_bd_pins vect2bits_16_0/dout5] - connect_bd_net -net vect2bits_16_0_dout6 [get_bd_ports PMOD0_6_LS] [get_bd_pins vect2bits_16_0/dout6] - connect_bd_net -net vect2bits_16_0_dout7 [get_bd_ports PMOD0_7_LS] [get_bd_pins vect2bits_16_0/dout7] - connect_bd_net -net vect2bits_16_0_dout14 [get_bd_pins axis_avg_buffer_0/trigger] [get_bd_pins vect2bits_16_0/dout14] - connect_bd_net -net vect2bits_16_0_dout15 [get_bd_pins axis_avg_buffer_1/trigger] [get_bd_pins vect2bits_16_0/dout15] - connect_bd_net -net xlconcat_0_dout [get_bd_pins axi_bram_ctrl_0_bram/addrb] [get_bd_pins xlconcat_0/dout] - connect_bd_net -net xlconstant_0_dout [get_bd_pins axi_bram_ctrl_0_bram/dinb] [get_bd_pins xlconstant_0/dout] - connect_bd_net -net xlconstant_1_dout [get_bd_pins axi_bram_ctrl_0_bram/enb] [get_bd_pins xlconstant_1/dout] - connect_bd_net -net xlconstant_2_dout [get_bd_pins axi_bram_ctrl_0_bram/web] [get_bd_pins xlconstant_2/dout] - connect_bd_net -net xlconstant_3_dout [get_bd_pins axi_bram_ctrl_0_bram/rstb] [get_bd_pins xlconstant_3/dout] - connect_bd_net -net xlconstant_4_dout [get_bd_pins xlconcat_0/In1] [get_bd_pins xlconstant_4/dout] - connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_dma_avg/m_axi_s2mm_aclk] [get_bd_pins axi_dma_avg/s_axi_lite_aclk] [get_bd_pins axi_dma_buf/m_axi_s2mm_aclk] [get_bd_pins axi_dma_buf/s_axi_lite_aclk] [get_bd_pins axi_dma_gen/m_axi_mm2s_aclk] [get_bd_pins axi_dma_gen/s_axi_lite_aclk] [get_bd_pins axi_dma_tproc/m_axi_mm2s_aclk] [get_bd_pins axi_dma_tproc/m_axi_s2mm_aclk] [get_bd_pins axi_dma_tproc/s_axi_lite_aclk] [get_bd_pins axi_smc/aclk] [get_bd_pins axis_avg_buffer_0/m_axis_aclk] [get_bd_pins axis_avg_buffer_0/s_axi_aclk] [get_bd_pins axis_avg_buffer_1/m_axis_aclk] [get_bd_pins axis_avg_buffer_1/s_axi_aclk] [get_bd_pins axis_clk_cnvrt_avg_0/s_axis_aclk] [get_bd_pins axis_clk_cnvrt_avg_1/s_axis_aclk] [get_bd_pins axis_readout_v2_0/s_axi_aclk] [get_bd_pins axis_readout_v2_1/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_0/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_0/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_1/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_1/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_2/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_2/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_3/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_3/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_4/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_4/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_5/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_5/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_6/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_6/s_axi_aclk] [get_bd_pins axis_switch_avg/aclk] [get_bd_pins axis_switch_avg/s_axi_ctrl_aclk] [get_bd_pins axis_switch_buf/aclk] [get_bd_pins axis_switch_buf/s_axi_ctrl_aclk] [get_bd_pins axis_switch_gen/aclk] [get_bd_pins axis_switch_gen/s_axi_ctrl_aclk] [get_bd_pins axis_tproc64x32_x8_0/m0_axis_aclk] [get_bd_pins axis_tproc64x32_x8_0/s0_axis_aclk] [get_bd_pins axis_tproc64x32_x8_0/s_axi_aclk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/M01_ACLK] [get_bd_pins ps8_0_axi_periph/M02_ACLK] [get_bd_pins ps8_0_axi_periph/M03_ACLK] [get_bd_pins ps8_0_axi_periph/M04_ACLK] [get_bd_pins ps8_0_axi_periph/M05_ACLK] [get_bd_pins ps8_0_axi_periph/M06_ACLK] [get_bd_pins ps8_0_axi_periph/M07_ACLK] [get_bd_pins ps8_0_axi_periph/M08_ACLK] [get_bd_pins ps8_0_axi_periph/M09_ACLK] [get_bd_pins ps8_0_axi_periph/M10_ACLK] [get_bd_pins ps8_0_axi_periph/M11_ACLK] [get_bd_pins ps8_0_axi_periph/M12_ACLK] [get_bd_pins ps8_0_axi_periph/M13_ACLK] [get_bd_pins ps8_0_axi_periph/M14_ACLK] [get_bd_pins ps8_0_axi_periph/M15_ACLK] [get_bd_pins ps8_0_axi_periph/M16_ACLK] [get_bd_pins ps8_0_axi_periph/M17_ACLK] [get_bd_pins ps8_0_axi_periph/M18_ACLK] [get_bd_pins ps8_0_axi_periph/M19_ACLK] [get_bd_pins ps8_0_axi_periph/M20_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins rst_100/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/s_axi_aclk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins zynq_ultra_ps_e_0/saxihpc0_fpd_aclk] - connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins rst_100/ext_reset_in] [get_bd_pins rst_adc/ext_reset_in] [get_bd_pins rst_dac2/ext_reset_in] [get_bd_pins rst_dac3/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] - - # Create address segments - assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force - assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] -force - assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force - assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] -force - assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force - assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] -force - assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force - assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force - assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] -force - assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] -force - assign_bd_address -offset 0xA0000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force - assign_bd_address -offset 0xA0010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_avg/S_AXI_LITE/Reg] -force - assign_bd_address -offset 0xA0020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_buf/S_AXI_LITE/Reg] -force - assign_bd_address -offset 0xA0030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_gen/S_AXI_LITE/Reg] -force - assign_bd_address -offset 0xA0040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_tproc/S_AXI_LITE/Reg] -force - assign_bd_address -offset 0xA0050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_avg_buffer_0/s_axi/reg0] -force - assign_bd_address -offset 0xA0060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_avg_buffer_1/s_axi/reg0] -force - assign_bd_address -offset 0xA0070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_readout_v2_0/s_axi/reg0] -force - assign_bd_address -offset 0xA0080000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_readout_v2_1/s_axi/reg0] -force - assign_bd_address -offset 0xA0090000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_0/s_axi/reg0] -force - assign_bd_address -offset 0xA00A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_1/s_axi/reg0] -force - assign_bd_address -offset 0xA00B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_2/s_axi/reg0] -force - assign_bd_address -offset 0xA00C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_3/s_axi/reg0] -force - assign_bd_address -offset 0xA00D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_4/s_axi/reg0] -force - assign_bd_address -offset 0xA00E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_5/s_axi/reg0] -force - assign_bd_address -offset 0xA00F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_6/s_axi/reg0] -force - assign_bd_address -offset 0xA0100000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_avg/S_AXI_CTRL/Reg] -force - assign_bd_address -offset 0xA0110000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_buf/S_AXI_CTRL/Reg] -force - assign_bd_address -offset 0xA0120000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_gen/S_AXI_CTRL/Reg] -force - assign_bd_address -offset 0x000400000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_tproc64x32_x8_0/s_axi/reg0] -force - assign_bd_address -offset 0xA0140000 -range 0x00040000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs usp_rf_data_converter_0/s_axi/Reg] -force - - # Exclude Address Segments - exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] - exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] - exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] - exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] - exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] - exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] - exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] - exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] - exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] - exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] - - # Perform GUI Layout - regenerate_bd_layout -layout_string { - "ActiveEmotionalView":"Default View", - "Default View_ScaleFactor":"0.936385", - "Default View_TopLeft":"-885,670", - "ExpandedHierarchyInLayout":"", - "guistr":"# # String gsaved with Nlview 7.0r4 2019-12-20 bk=1.5203 VDI=41 GEI=36 GUI=JA:10.0 TLS -# -string -flagsOSRD -preplace port adc2_clk_0 -pg 1 -lvl 7 -x 3400 -y 2270 -defaultsOSRD -right -preplace port dac2_clk_0 -pg 1 -lvl 7 -x 3400 -y 2250 -defaultsOSRD -right -preplace port sysref_in_0 -pg 1 -lvl 7 -x 3400 -y 2190 -defaultsOSRD -right -preplace port vin20_0 -pg 1 -lvl 7 -x 3400 -y 2230 -defaultsOSRD -right -preplace port vin22_0 -pg 1 -lvl 7 -x 3400 -y 2210 -defaultsOSRD -right -preplace port vout0 -pg 1 -lvl 7 -x 3400 -y 1870 -defaultsOSRD -preplace port vout1 -pg 1 -lvl 7 -x 3400 -y 1890 -defaultsOSRD -preplace port vout2 -pg 1 -lvl 7 -x 3400 -y 1910 -defaultsOSRD -preplace port vout3 -pg 1 -lvl 7 -x 3400 -y 1930 -defaultsOSRD -preplace port vout4 -pg 1 -lvl 7 -x 3400 -y 1950 -defaultsOSRD -preplace port vout5 -pg 1 -lvl 7 -x 3400 -y 1970 -defaultsOSRD -preplace port vout6 -pg 1 -lvl 7 -x 3400 -y 1990 -defaultsOSRD -preplace port PMOD0_0_LS -pg 1 -lvl 7 -x 3400 -y 1350 -defaultsOSRD -preplace port PMOD0_1_LS -pg 1 -lvl 7 -x 3400 -y 1370 -defaultsOSRD -preplace port PMOD0_2_LS -pg 1 -lvl 7 -x 3400 -y 1390 -defaultsOSRD -preplace port PMOD0_3_LS -pg 1 -lvl 7 -x 3400 -y 1410 -defaultsOSRD -preplace port PMOD0_4_LS -pg 1 -lvl 7 -x 3400 -y 1430 -defaultsOSRD -preplace port PMOD0_5_LS -pg 1 -lvl 7 -x 3400 -y 1450 -defaultsOSRD -preplace port PMOD0_6_LS -pg 1 -lvl 7 -x 3400 -y 1470 -defaultsOSRD -preplace port PMOD0_7_LS -pg 1 -lvl 7 -x 3400 -y 1490 -defaultsOSRD -preplace port PMOD1_0_LS -pg 1 -lvl 0 -x 0 -y 1510 -defaultsOSRD -preplace inst axi_bram_ctrl_0 -pg 1 -lvl 1 -x 200 -y 1800 -defaultsOSRD -preplace inst axi_bram_ctrl_0_bram -pg 1 -lvl 2 -x 690 -y 1880 -defaultsOSRD -preplace inst axi_dma_avg -pg 1 -lvl 2 -x 690 -y 340 -defaultsOSRD -preplace inst axi_dma_buf -pg 1 -lvl 2 -x 690 -y 520 -defaultsOSRD -preplace inst axi_dma_gen -pg 1 -lvl 2 -x 690 -y 690 -defaultsOSRD -preplace inst axi_dma_tproc -pg 1 -lvl 2 -x 690 -y 880 -defaultsOSRD -preplace inst axi_smc -pg 1 -lvl 3 -x 1170 -y 680 -defaultsOSRD -preplace inst axis_avg_buffer_0 -pg 1 -lvl 4 -x 1900 -y 3350 -defaultsOSRD -preplace inst axis_avg_buffer_1 -pg 1 -lvl 4 -x 1900 -y 3750 -defaultsOSRD -preplace inst axis_clk_cnvrt_avg_0 -pg 1 -lvl 5 -x 2500 -y 2590 -defaultsOSRD -preplace inst axis_clk_cnvrt_avg_1 -pg 1 -lvl 5 -x 2500 -y 3210 -defaultsOSRD -preplace inst axis_constant_0 -pg 1 -lvl 1 -x 200 -y 1290 -defaultsOSRD -preplace inst axis_constant_1 -pg 1 -lvl 1 -x 200 -y 1410 -defaultsOSRD -preplace inst axis_readout_v2_0 -pg 1 -lvl 3 -x 1170 -y 3140 -defaultsOSRD -preplace inst axis_readout_v2_1 -pg 1 -lvl 3 -x 1170 -y 3370 -defaultsOSRD -preplace inst axis_register_slice_0 -pg 1 -lvl 2 -x 690 -y 3090 -defaultsOSRD -preplace inst axis_register_slice_1 -pg 1 -lvl 2 -x 690 -y 3260 -defaultsOSRD -preplace inst axis_register_slice_2 -pg 1 -lvl 5 -x 2500 -y 1520 -defaultsOSRD -preplace inst axis_register_slice_3 -pg 1 -lvl 5 -x 2500 -y 1660 -defaultsOSRD -preplace inst axis_register_slice_4 -pg 1 -lvl 5 -x 2500 -y 1810 -defaultsOSRD -preplace inst axis_register_slice_5 -pg 1 -lvl 5 -x 2500 -y 1980 -defaultsOSRD -preplace inst axis_register_slice_6 -pg 1 -lvl 5 -x 2500 -y 2150 -defaultsOSRD -preplace inst axis_register_slice_7 -pg 1 -lvl 5 -x 2500 -y 2290 -defaultsOSRD -preplace inst axis_register_slice_8 -pg 1 -lvl 5 -x 2500 -y 2430 -defaultsOSRD -preplace inst axis_set_reg_0 -pg 1 -lvl 5 -x 2500 -y 1380 -defaultsOSRD -preplace inst axis_signal_gen_v6_0 -pg 1 -lvl 4 -x 1900 -y 1370 -defaultsOSRD -preplace inst axis_signal_gen_v6_1 -pg 1 -lvl 4 -x 1900 -y 1630 -defaultsOSRD -preplace inst axis_signal_gen_v6_2 -pg 1 -lvl 4 -x 1900 -y 1890 -defaultsOSRD -preplace inst axis_signal_gen_v6_3 -pg 1 -lvl 4 -x 1900 -y 2150 -defaultsOSRD -preplace inst axis_signal_gen_v6_4 -pg 1 -lvl 4 -x 1900 -y 2410 -defaultsOSRD -preplace inst axis_signal_gen_v6_5 -pg 1 -lvl 4 -x 1900 -y 2670 -defaultsOSRD -preplace inst axis_signal_gen_v6_6 -pg 1 -lvl 4 -x 1900 -y 2930 -defaultsOSRD -preplace inst axis_switch_avg -pg 1 -lvl 5 -x 2500 -y 2790 -defaultsOSRD -preplace inst axis_switch_buf -pg 1 -lvl 5 -x 2500 -y 3010 -defaultsOSRD -preplace inst axis_switch_gen -pg 1 -lvl 3 -x 1170 -y 1270 -defaultsOSRD -preplace inst axis_terminator_0 -pg 1 -lvl 4 -x 1900 -y 3150 -defaultsOSRD -preplace inst axis_terminator_1 -pg 1 -lvl 4 -x 1900 -y 3550 -defaultsOSRD -preplace inst axis_tproc64x32_x8_0 -pg 1 -lvl 2 -x 690 -y 1380 -defaultsOSRD -preplace inst ps8_0_axi_periph -pg 1 -lvl 5 -x 2500 -y 770 -defaultsOSRD -preplace inst rst_100 -pg 1 -lvl 4 -x 1900 -y 530 -defaultsOSRD -preplace inst rst_adc -pg 1 -lvl 4 -x 1900 -y 710 -defaultsOSRD -preplace inst rst_dac2 -pg 1 -lvl 4 -x 1900 -y 890 -defaultsOSRD -preplace inst rst_dac3 -pg 1 -lvl 4 -x 1900 -y 1070 -defaultsOSRD -preplace inst usp_rf_data_converter_0 -pg 1 -lvl 6 -x 3190 -y 1950 -defaultsOSRD -preplace inst xlconcat_0 -pg 1 -lvl 2 -x 690 -y 1670 -defaultsOSRD -preplace inst xlconstant_0 -pg 1 -lvl 1 -x 200 -y 1920 -defaultsOSRD -preplace inst xlconstant_1 -pg 1 -lvl 1 -x 200 -y 2020 -defaultsOSRD -preplace inst xlconstant_2 -pg 1 -lvl 1 -x 200 -y 2220 -defaultsOSRD -preplace inst xlconstant_3 -pg 1 -lvl 1 -x 200 -y 2120 -defaultsOSRD -preplace inst xlconstant_4 -pg 1 -lvl 1 -x 200 -y 1680 -defaultsOSRD -preplace inst zynq_ultra_ps_e_0 -pg 1 -lvl 4 -x 1900 -y 350 -defaultsOSRD -preplace inst vect2bits_16_0 -pg 1 -lvl 6 -x 3190 -y 1500 -defaultsOSRD -preplace inst axis_cdcsync_v1_0 -pg 1 -lvl 3 -x 1170 -y 1670 -defaultsOSRD -preplace inst axis_cdcsync_v1_1 -pg 1 -lvl 3 -x 1170 -y 1990 -defaultsOSRD -preplace inst axis_constant_2 -pg 1 -lvl 2 -x 690 -y 2100 -defaultsOSRD -preplace netloc axi_bram_ctrl_0_bram_doutb 1 1 1 490 1530n -preplace netloc axis_set_reg_0_dout 1 5 1 3030 1380n -preplace netloc axis_tproc64x32_x8_0_pmem_addr 1 1 2 500J 1590 870 -preplace netloc rst_adc_peripheral_aresetn 1 1 5 510 3170 980 3250 1420 3070 2250 3310 2950J -preplace netloc rst_dac2_peripheral_aresetn 1 0 6 50 1190 370 1170 920 1400 1480 1190 2280J 3320 2980 -preplace netloc rst_dac3_peripheral_aresetn 1 2 4 1010 2120 1440 1200 2290J 2070 2920 -preplace netloc rst_ps8_0_99M_peripheral_aresetn 1 0 6 40 1210 360 170 950 1150 1340 1180 2300 3330 2970 -preplace netloc usp_rf_data_converter_0_clk_adc2 1 1 6 500 3180 890 3260 1380 3890 N 3890 2990 2260 3350 -preplace netloc usp_rf_data_converter_0_clk_dac2 1 0 7 60 1220 350 1740 980 1800 1470 1210 2220 3350 3000 2280 3340 -preplace netloc usp_rf_data_converter_0_clk_dac3 1 2 5 1020 2130 1330 1220 2270 2060 2930 2240 3330 -preplace netloc vect2bits_16_0_dout0 1 6 1 N 1350 -preplace netloc vect2bits_16_0_dout1 1 6 1 N 1370 -preplace netloc vect2bits_16_0_dout2 1 6 1 N 1390 -preplace netloc vect2bits_16_0_dout3 1 6 1 N 1410 -preplace netloc vect2bits_16_0_dout4 1 6 1 N 1430 -preplace netloc vect2bits_16_0_dout5 1 6 1 NJ 1450 -preplace netloc vect2bits_16_0_dout6 1 6 1 NJ 1470 -preplace netloc vect2bits_16_0_dout7 1 6 1 NJ 1490 -preplace netloc vect2bits_16_0_dout14 1 3 4 1550 220 NJ 220 NJ 220 3330 -preplace netloc vect2bits_16_0_dout15 1 3 4 1590 3900 NJ 3900 NJ 3900 3360 -preplace netloc xlconcat_0_dout 1 1 2 510 1600 870 -preplace netloc xlconstant_0_dout 1 1 1 360 1880n -preplace netloc xlconstant_1_dout 1 1 1 390 1920n -preplace netloc xlconstant_2_dout 1 1 1 410 1960n -preplace netloc xlconstant_3_dout 1 1 1 400 1940n -preplace netloc xlconstant_4_dout 1 1 1 N 1680 -preplace netloc zynq_ultra_ps_e_0_pl_clk0 1 0 6 30 1200 380 180 940 340 1370 1170 2310 3340 2960 -preplace netloc zynq_ultra_ps_e_0_pl_resetn0 1 3 2 1590 260 2220 -preplace netloc PMOD1_0_LS_1 1 0 2 N 1510 NJ -preplace netloc vin20_0_1 1 5 2 3030 2230 N -preplace netloc axis_signal_gen_v6_3_m_axis 1 4 1 2210 1960n -preplace netloc vin22_0_1 1 5 2 3040 2220 3380 -preplace netloc axis_avg_buffer_1_m1_axis 1 4 1 2340 2970n -preplace netloc axis_switch_0_M06_AXIS 1 3 1 1360 1330n -preplace netloc dac2_clk_0_1 1 5 2 3020 2250 N -preplace netloc zynq_ultra_ps_e_0_M_AXI_HPM0_FPD 1 4 1 2300 310n -preplace netloc axi_interconnect_0_M00_AXI 1 1 5 410 -10 NJ -10 N -10 NJ -10 2840 -preplace netloc axis_avg_buffer_0_m0_axis 1 4 1 2290 2730n -preplace netloc axi_interconnect_0_M08_AXI 1 5 1 3040 730n -preplace netloc axi_dma_0_M_AXIS_MM2S 1 1 2 490 240 870 -preplace netloc ps8_0_axi_periph_M04_AXI 1 3 3 1530 70 NJ 70 2780 -preplace netloc ps8_0_axi_periph_M01_AXI 1 1 5 420 40 NJ 40 NJ 40 NJ 40 2810 -preplace netloc ps8_0_axi_periph_M13_AXI 1 0 6 20 150 NJ 150 NJ 150 NJ 150 NJ 150 2700 -preplace netloc ps8_0_axi_periph_M15_AXI 1 2 4 990 170 NJ 170 NJ 170 2680 -preplace netloc usp_rf_data_converter_0_vout32 1 6 1 N 1990 -preplace netloc axis_tproc64x32_x8_0_m0_axis 1 1 2 480 210 880 -preplace netloc ps8_0_axi_periph_M17_AXI 1 4 2 2340 240 2660 -preplace netloc usp_rf_data_converter_0_vout21 1 6 1 N 1890 -preplace netloc usp_rf_data_converter_0_vout20 1 6 1 N 1870 -preplace netloc usp_rf_data_converter_0_vout30 1 6 1 N 1950 -preplace netloc smartconnect_0_M00_AXI 1 3 1 1330 320n -preplace netloc axis_avg_buffer_0_m2_axis 1 4 1 2320 2550n -preplace netloc axis_clk_cnvrt_avg_1_M_AXIS 1 1 5 400 10 NJ 10 NJ 10 NJ 10 2880 -preplace netloc usp_rf_data_converter_0_vout31 1 6 1 N 1970 -preplace netloc axis_switch_0_M04_AXIS 1 3 1 1410 1290n -preplace netloc usp_rf_data_converter_0_m20_axis 1 1 6 430 220 NJ 220 1330 210 NJ 210 NJ 210 3350 -preplace netloc axis_tproc64x32_x8_0_m1_axis 1 2 3 980 1390 1320 1230 2230J -preplace netloc axis_constant_0_m_axis 1 1 1 N 1290 -preplace netloc axis_switch_buf_M00_AXIS 1 1 5 450 30 NJ 30 NJ 30 NJ 30 2850 -preplace netloc adc2_clk_0_1 1 5 2 3010 2270 N -preplace netloc axis_avg_buffer_1_m2_axis 1 4 1 2350 3170n -preplace netloc ps8_0_axi_periph_M20_AXI 1 1 5 500 200 NJ 200 NJ 200 NJ 200 2820 -preplace netloc axi_bram_ctrl_0_BRAM_PORTA 1 1 1 NJ 1800 -preplace netloc ps8_0_axi_periph_M16_AXI 1 2 4 1000 180 NJ 180 NJ 180 2670 -preplace netloc usp_rf_data_converter_0_vout22 1 6 1 N 1910 -preplace netloc ps8_0_axi_periph_M11_AXI 1 3 3 1560 130 NJ 130 2720 -preplace netloc ps8_0_axi_periph_M03_AXI 1 3 3 1520 60 NJ 60 2790 -preplace netloc ps8_0_axi_periph_M07_AXI 1 2 4 1020 100 NJ 100 NJ 100 2750 -preplace netloc ps8_0_axi_periph_M14_AXI 1 3 3 1580 160 NJ 160 2690 -preplace netloc ps8_0_axi_periph_M05_AXI 1 3 3 1540 80 NJ 80 2770 -preplace netloc ps8_0_axi_periph_M18_AXI 1 4 2 2350 250 2650 -preplace netloc ps8_0_axi_periph_M12_AXI 1 3 3 1570 140 NJ 140 2710 -preplace netloc ps8_0_axi_periph_M06_AXI 1 1 5 470 90 NJ 90 N 90 NJ 90 2760 -preplace netloc axis_constant_1_m_axis 1 1 1 340 1310n -preplace netloc ps8_0_axi_periph_M02_AXI 1 3 3 1510 50 NJ 50 2800 -preplace netloc ps8_0_axi_periph_M10_AXI 1 3 3 1490 120 NJ 120 2730 -preplace netloc ps8_0_axi_periph_M19_AXI 1 1 5 510 190 NJ 190 NJ 190 NJ 190 2830 -preplace netloc usp_rf_data_converter_0_vout23 1 6 1 N 1930 -preplace netloc sysref_in_0_1 1 5 2 3050 2210 3370 -preplace netloc usp_rf_data_converter_0_m22_axis 1 1 6 440 230 NJ 230 N 230 NJ 230 NJ 230 3340 -preplace netloc ps8_0_axi_periph_M09_AXI 1 3 3 1500 110 NJ 110 2740 -preplace netloc axis_signal_gen_v6_0_m_axis 1 4 1 2230 1370n -preplace netloc axi_dma_0_M_AXI_MM2S1 1 2 1 N 660 -preplace netloc axi_dma_avg_M_AXI_S2MM 1 2 1 980 320n -preplace netloc axis_register_slice_7_M_AXIS 1 5 1 2910 1870n -preplace netloc axis_register_slice_0_M_AXIS 1 2 1 N 3090 -preplace netloc axis_avg_buffer_1_m0_axis 1 4 1 2330 2750n -preplace netloc axi_dma_buf_M_AXI_S2MM 1 2 1 970 500n -preplace netloc axis_register_slice_3_M_AXIS 1 5 1 3020 1660n -preplace netloc axis_register_slice_2_M_AXIS 1 5 1 3030 1520n -preplace netloc axi_dma_0_M_AXI_S2MM 1 2 1 920 640n -preplace netloc axis_readout_v2_0_m0_axis 1 3 1 N 3130 -preplace netloc axis_clk_cnvrt_avg_0_M_AXIS 1 1 5 390 0 NJ 0 NJ 0 NJ 0 2870 -preplace netloc axis_register_slice_1_M_AXIS 1 2 1 870 3260n -preplace netloc axis_readout_v2_1_m1_axis 1 3 1 1310 3380n -preplace netloc axis_readout_v2_1_m0_axis 1 3 1 1320 3360n -preplace netloc axis_signal_gen_v6_6_m_axis 1 4 1 2260 2410n -preplace netloc axis_switch_0_M02_AXIS 1 3 1 1450 1250n -preplace netloc axis_signal_gen_v6_1_m_axis 1 4 1 2230 1630n -preplace netloc axis_signal_gen_v6_2_m_axis 1 4 1 2210 1790n -preplace netloc axis_register_slice_6_M_AXIS 1 5 1 2900 1850n -preplace netloc axis_signal_gen_v6_5_m_axis 1 4 1 2240 2270n -preplace netloc axis_switch_avg_M00_AXIS 1 1 5 460 20 NJ 20 NJ 20 NJ 20 2860 -preplace netloc axis_switch_0_M05_AXIS 1 3 1 1390 1310n -preplace netloc axis_register_slice_4_M_AXIS 1 5 1 N 1810 -preplace netloc axis_register_slice_8_M_AXIS 1 5 1 2940 1890n -preplace netloc axis_switch_0_M00_AXIS 1 3 1 1460 1210n -preplace netloc axis_readout_v2_0_m1_axis 1 3 1 1310 3150n -preplace netloc axis_signal_gen_v6_4_m_axis 1 4 1 2230 2130n -preplace netloc axis_switch_0_M03_AXIS 1 3 1 1430 1270n -preplace netloc axis_register_slice_5_M_AXIS 1 5 1 2890 1830n -preplace netloc axis_switch_0_M01_AXIS 1 3 1 1310 1230n -preplace netloc axi_dma_0_M_AXI_MM2S 1 2 1 910 620n -preplace netloc axis_avg_buffer_0_m1_axis 1 4 1 2210 2950n -preplace netloc axi_dma_0_M_AXIS_MM2S1 1 2 1 960 680n -preplace netloc axis_tproc64x32_x8_0_m2_axis 1 2 1 970 1330n -preplace netloc axis_tproc64x32_x8_0_m3_axis 1 2 1 960 1350n -preplace netloc axis_tproc64x32_x8_0_m4_axis 1 2 1 930 1370n -preplace netloc axis_tproc64x32_x8_0_m5_axis 1 2 1 910 1390n -preplace netloc axis_cdcsync_v1_0_m0_axis 1 3 1 1400 1310n -preplace netloc axis_cdcsync_v1_0_m1_axis 1 3 1 1420 1570n -preplace netloc axis_cdcsync_v1_0_m2_axis 1 3 1 1420 1680n -preplace netloc axis_cdcsync_v1_0_m3_axis 1 3 1 1400 1700n -preplace netloc axis_cdcsync_v1_1_m0_axis 1 3 1 1350 1960n -preplace netloc axis_cdcsync_v1_1_m1_axis 1 3 1 1320 1980n -preplace netloc axis_cdcsync_v1_1_m2_axis 1 3 1 1310 2000n -preplace netloc axis_tproc64x32_x8_0_m6_axis 1 2 1 900 1410n -preplace netloc axis_tproc64x32_x8_0_m7_axis 1 2 1 890 1430n -preplace netloc axis_tproc64x32_x8_0_m8_axis 1 2 1 880 1450n -preplace netloc axis_constant_2_m_axis 1 2 1 970 1980n -levelinfo -pg 1 0 200 690 1170 1900 2500 3190 3400 -pagesize -pg 1 -db -bbox -sgen -150 -20 3550 3910 -" -} - - # Restore current instance - current_bd_instance $oldCurInst - - validate_bd_design - save_bd_design -} -# End of create_root_design() - - -################################################################## -# MAIN FLOW -################################################################## - -create_root_design "" - - diff --git a/qick/firmware/bd/bd_4x2_2020-2.tcl b/qick/firmware/bd/bd_4x2_2020-2.tcl deleted file mode 100644 index e8b74c4..0000000 --- a/qick/firmware/bd/bd_4x2_2020-2.tcl +++ /dev/null @@ -1,1570 +0,0 @@ - -################################################################ -# This is a generated script based on design: d_1 -# -# Though there are limitations about the generated script, -# the main purpose of this utility is to make learning -# IP Integrator Tcl commands easier. -################################################################ - -namespace eval _tcl { -proc get_script_folder {} { - set script_path [file normalize [info script]] - set script_folder [file dirname $script_path] - return $script_folder -} -} -variable script_folder -set script_folder [_tcl::get_script_folder] - -################################################################ -# Check if script is running in correct Vivado version. -################################################################ -set scripts_vivado_version 2020.2 -set current_vivado_version [version -short] - -if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { - puts "" - catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} - - return 1 -} - -################################################################ -# START -################################################################ - -# To test this script, run the following commands from Vivado Tcl console: -# source d_1_script.tcl - - -# The design that will be created by this Tcl script contains the following -# module references: -# vect2bits_16 - -# Please add the sources of those modules before sourcing this Tcl script. - -# If there is no project opened, this script will create a -# project, but make sure you do not have an existing project -# <./myproj/project_1.xpr> in the current working folder. - -set list_projs [get_projects -quiet] -if { $list_projs eq "" } { - create_project project_1 myproj -part xczu48dr-ffvg1517-2-e - set_property BOARD_PART realdigital.org:rfsoc4x2:part0:1.0 [current_project] -} - - -# CHANGE DESIGN NAME HERE -variable design_name -set design_name d_1 - -# If you do not already have an existing IP Integrator design open, -# you can create a design using the following command: -# create_bd_design $design_name - -# Creating design if needed -set errMsg "" -set nRet 0 - -set cur_design [current_bd_design -quiet] -set list_cells [get_bd_cells -quiet] - -if { ${design_name} eq "" } { - # USE CASES: - # 1) Design_name not set - - set errMsg "Please set the variable to a non-empty value." - set nRet 1 - -} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { - # USE CASES: - # 2): Current design opened AND is empty AND names same. - # 3): Current design opened AND is empty AND names diff; design_name NOT in project. - # 4): Current design opened AND is empty AND names diff; design_name exists in project. - - if { $cur_design ne $design_name } { - common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." - set design_name [get_property NAME $cur_design] - } - common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." - -} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { - # USE CASES: - # 5) Current design opened AND has components AND same names. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 1 -} elseif { [get_files -quiet ${design_name}.bd] ne "" } { - # USE CASES: - # 6) Current opened design, has components, but diff names, design_name exists in project. - # 7) No opened design, design_name exists in project. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 2 - -} else { - # USE CASES: - # 8) No opened design, design_name not in project. - # 9) Current opened design, has components, but diff names, design_name not in project. - - common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." - - create_bd_design $design_name - - common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." - current_bd_design $design_name - -} - -common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." - -if { $nRet != 0 } { - catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} - return $nRet -} - -set bCheckIPsPassed 1 -################################################################## -# CHECK IPs -################################################################## -set bCheckIPs 1 -if { $bCheckIPs == 1 } { - set list_check_ips "\ -xilinx.com:ip:axi_bram_ctrl:4.1\ -xilinx.com:ip:blk_mem_gen:8.4\ -xilinx.com:ip:axi_dma:7.1\ -xilinx.com:ip:smartconnect:1.0\ -user.org:user:axis_avg_buffer:1.0\ -xilinx.com:ip:axis_clock_converter:1.1\ -user.org:user:axis_constant:1.0\ -user.org:user:axis_readout_v2:1.0\ -user.org:user:axis_register_slice_nb:1.0\ -xilinx.com:ip:axis_register_slice:1.1\ -user.org:user:axis_set_reg:1.0\ -user.org:user:axis_signal_gen_v6:1.0\ -xilinx.com:ip:axis_switch:1.1\ -user.org:user:axis_tproc64x32_x8:1.0\ -xilinx.com:ip:clk_wiz:6.0\ -user.org:user:mr_buffer_et:1.0\ -xilinx.com:ip:proc_sys_reset:5.0\ -xilinx.com:ip:usp_rf_data_converter:2.4\ -xilinx.com:ip:xlconstant:1.1\ -xilinx.com:ip:zynq_ultra_ps_e:3.3\ -" - - set list_ips_missing "" - common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." - - foreach ip_vlnv $list_check_ips { - set ip_obj [get_ipdefs -all $ip_vlnv] - if { $ip_obj eq "" } { - lappend list_ips_missing $ip_vlnv - } - } - - if { $list_ips_missing ne "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } - set bCheckIPsPassed 0 - } - -} - -################################################################## -# CHECK Modules -################################################################## -set bCheckModules 1 -if { $bCheckModules == 1 } { - set list_check_mods "\ -vect2bits_16\ -" - - set list_mods_missing "" - common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." - - foreach mod_vlnv $list_check_mods { - if { [can_resolve_reference $mod_vlnv] == 0 } { - lappend list_mods_missing $mod_vlnv - } - } - - if { $list_mods_missing ne "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } - common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." - set bCheckIPsPassed 0 - } -} - -if { $bCheckIPsPassed != 1 } { - common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." - return 3 -} - -################################################################## -# DESIGN PROCs -################################################################## - - - -# Procedure to create entire design; Provide argument to make -# procedure reusable. If parentCell is "", will use root. -proc create_root_design { parentCell } { - - variable script_folder - variable design_name - - if { $parentCell eq "" } { - set parentCell [get_bd_cells /] - } - - # Get object for parentCell - set parentObj [get_bd_cells $parentCell] - if { $parentObj == "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} - return - } - - # Make sure parentObj is hier blk - set parentType [get_property TYPE $parentObj] - if { $parentType ne "hier" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} - return - } - - # Save current instance; Restore later - set oldCurInst [current_bd_instance .] - - # Set parent object as current - current_bd_instance $parentObj - - - # Create interface ports - set adc0_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 adc0_clk ] - - set dac0_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac0_clk ] - - set dac2_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac2_clk ] - - set sysref_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:display_usp_rf_data_converter:diff_pins_rtl:1.0 sysref_in ] - - set vin0_01 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vin0_01 ] - - set vin0_23 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vin0_23 ] - - set vout00 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout00 ] - - set vout20 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout20 ] - - - # Create ports - set PMOD0_0 [ create_bd_port -dir O PMOD0_0 ] - set PMOD0_1 [ create_bd_port -dir O PMOD0_1 ] - set PMOD0_2 [ create_bd_port -dir O PMOD0_2 ] - set PMOD0_3 [ create_bd_port -dir O PMOD0_3 ] - - # Create instance: axi_bram_ctrl_0, and set properties - set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {64} \ - CONFIG.ECC_TYPE {0} \ - CONFIG.SINGLE_PORT_BRAM {1} \ - ] $axi_bram_ctrl_0 - - # Create instance: axi_bram_ctrl_0_bram, and set properties - set axi_bram_ctrl_0_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 axi_bram_ctrl_0_bram ] - set_property -dict [ list \ - CONFIG.Byte_Size {8} \ - CONFIG.EN_SAFETY_CKT {false} \ - CONFIG.Enable_32bit_Address {true} \ - CONFIG.Memory_Type {True_Dual_Port_RAM} \ - CONFIG.Read_Width_B {64} \ - CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \ - CONFIG.Register_PortB_Output_of_Memory_Primitives {false} \ - CONFIG.Use_Byte_Write_Enable {true} \ - CONFIG.Use_RSTA_Pin {true} \ - CONFIG.Use_RSTB_Pin {true} \ - CONFIG.Write_Width_B {64} \ - CONFIG.use_bram_block {BRAM_Controller} \ - ] $axi_bram_ctrl_0_bram - - # Create instance: axi_dma_avg, and set properties - set axi_dma_avg [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_avg ] - set_property -dict [ list \ - CONFIG.c_include_mm2s {0} \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_include_stscntrl_strm {0} \ - CONFIG.c_sg_length_width {26} \ - ] $axi_dma_avg - - # Create instance: axi_dma_buf, and set properties - set axi_dma_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_buf ] - set_property -dict [ list \ - CONFIG.c_include_mm2s {0} \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_include_stscntrl_strm {0} \ - CONFIG.c_sg_length_width {26} \ - ] $axi_dma_buf - - # Create instance: axi_dma_gen, and set properties - set axi_dma_gen [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_gen ] - set_property -dict [ list \ - CONFIG.c_include_s2mm {0} \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_include_stscntrl_strm {0} \ - CONFIG.c_sg_length_width {26} \ - ] $axi_dma_gen - - # Create instance: axi_dma_readout, and set properties - set axi_dma_readout [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_readout ] - set_property -dict [ list \ - CONFIG.c_include_mm2s {0} \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_include_stscntrl_strm {0} \ - CONFIG.c_sg_length_width {26} \ - ] $axi_dma_readout - - # Create instance: axi_dma_tproc, and set properties - set axi_dma_tproc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_tproc ] - set_property -dict [ list \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_include_stscntrl_strm {0} \ - ] $axi_dma_tproc - - # Create instance: axi_smc, and set properties - set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ] - set_property -dict [ list \ - CONFIG.NUM_SI {6} \ - ] $axi_smc - - # Create instance: axis_avg_buffer_0, and set properties - set axis_avg_buffer_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_avg_buffer:1.0 axis_avg_buffer_0 ] - set_property -dict [ list \ - CONFIG.N_BUF {14} \ - ] $axis_avg_buffer_0 - - # Create instance: axis_avg_buffer_1, and set properties - set axis_avg_buffer_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_avg_buffer:1.0 axis_avg_buffer_1 ] - set_property -dict [ list \ - CONFIG.N_BUF {14} \ - ] $axis_avg_buffer_1 - - # Create instance: axis_cc_avg_0, and set properties - set axis_cc_avg_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_cc_avg_0 ] - - # Create instance: axis_cc_avg_1, and set properties - set axis_cc_avg_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_cc_avg_1 ] - - # Create instance: axis_cc_sg_0, and set properties - set axis_cc_sg_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_cc_sg_0 ] - set_property -dict [ list \ - CONFIG.SYNCHRONIZATION_STAGES {2} \ - ] $axis_cc_sg_0 - - # Create instance: axis_cc_sg_1, and set properties - set axis_cc_sg_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_cc_sg_1 ] - set_property -dict [ list \ - CONFIG.SYNCHRONIZATION_STAGES {2} \ - ] $axis_cc_sg_1 - - # Create instance: axis_constant_0, and set properties - set axis_constant_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_constant:1.0 axis_constant_0 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {64} \ - ] $axis_constant_0 - - # Create instance: axis_constant_1, and set properties - set axis_constant_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_constant:1.0 axis_constant_1 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {64} \ - ] $axis_constant_1 - - # Create instance: axis_readout_v2_0, and set properties - set axis_readout_v2_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_readout_v2:1.0 axis_readout_v2_0 ] - - # Create instance: axis_readout_v2_1, and set properties - set axis_readout_v2_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_readout_v2:1.0 axis_readout_v2_1 ] - - # Create instance: axis_register_slice_0, and set properties - set axis_register_slice_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_register_slice_nb:1.0 axis_register_slice_0 ] - set_property -dict [ list \ - CONFIG.B {256} \ - ] $axis_register_slice_0 - - # Create instance: axis_register_slice_1, and set properties - set axis_register_slice_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_register_slice_nb:1.0 axis_register_slice_1 ] - set_property -dict [ list \ - CONFIG.B {256} \ - ] $axis_register_slice_1 - - # Create instance: axis_register_slice_2, and set properties - set axis_register_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_2 ] - set_property -dict [ list \ - CONFIG.REG_CONFIG {16} \ - ] $axis_register_slice_2 - - # Create instance: axis_register_slice_3, and set properties - set axis_register_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_3 ] - set_property -dict [ list \ - CONFIG.REG_CONFIG {16} \ - ] $axis_register_slice_3 - - # Create instance: axis_set_reg_0, and set properties - set axis_set_reg_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_set_reg:1.0 axis_set_reg_0 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {160} \ - ] $axis_set_reg_0 - - # Create instance: axis_signal_gen_v6_0, and set properties - set axis_signal_gen_v6_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_0 ] - - # Create instance: axis_signal_gen_v6_1, and set properties - set axis_signal_gen_v6_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_1 ] - - # Create instance: axis_switch_avg, and set properties - set axis_switch_avg [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_avg ] - set_property -dict [ list \ - CONFIG.ROUTING_MODE {1} \ - ] $axis_switch_avg - - # Create instance: axis_switch_buf, and set properties - set axis_switch_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_buf ] - set_property -dict [ list \ - CONFIG.ROUTING_MODE {1} \ - ] $axis_switch_buf - - # Create instance: axis_switch_gen, and set properties - set axis_switch_gen [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_gen ] - set_property -dict [ list \ - CONFIG.DECODER_REG {1} \ - CONFIG.NUM_MI {2} \ - CONFIG.NUM_SI {1} \ - CONFIG.ROUTING_MODE {1} \ - ] $axis_switch_gen - - # Create instance: axis_switch_readout, and set properties - set axis_switch_readout [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_readout ] - set_property -dict [ list \ - CONFIG.ROUTING_MODE {1} \ - ] $axis_switch_readout - - # Create instance: axis_tproc64x32_x8_0, and set properties - set axis_tproc64x32_x8_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_tproc64x32_x8:1.0 axis_tproc64x32_x8_0 ] - - # Create instance: clk_adc0_x2, and set properties - set clk_adc0_x2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_adc0_x2 ] - set_property -dict [ list \ - CONFIG.CLKOUT1_JITTER {123.875} \ - CONFIG.CLKOUT1_PHASE_ERROR {183.542} \ - CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {491.52} \ - CONFIG.MMCM_CLKFBOUT_MULT_F {40.000} \ - CONFIG.MMCM_CLKOUT0_DIVIDE_F {2.500} \ - CONFIG.MMCM_DIVCLK_DIVIDE {9} \ - CONFIG.RESET_PORT {resetn} \ - CONFIG.RESET_TYPE {ACTIVE_LOW} \ - ] $clk_adc0_x2 - - # Create instance: clk_tproc, and set properties - set clk_tproc [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_tproc ] - set_property -dict [ list \ - CONFIG.CLKOUT1_JITTER {79.602} \ - CONFIG.CLKOUT1_PHASE_ERROR {81.720} \ - CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {409.6} \ - CONFIG.MMCM_CLKFBOUT_MULT_F {5.750} \ - CONFIG.MMCM_CLKOUT0_DIVIDE_F {2.875} \ - CONFIG.MMCM_DIVCLK_DIVIDE {3} \ - CONFIG.RESET_PORT {resetn} \ - CONFIG.RESET_TYPE {ACTIVE_LOW} \ - ] $clk_tproc - - # Create instance: mr_buffer_et_0, and set properties - set mr_buffer_et_0 [ create_bd_cell -type ip -vlnv user.org:user:mr_buffer_et:1.0 mr_buffer_et_0 ] - set_property -dict [ list \ - CONFIG.B {32} \ - ] $mr_buffer_et_0 - - # Create instance: ps8_0_axi_periph, and set properties - set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ] - set_property -dict [ list \ - CONFIG.NUM_MI {19} \ - ] $ps8_0_axi_periph - - # Create instance: rst_100, and set properties - set rst_100 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_100 ] - - # Create instance: rst_adc0, and set properties - set rst_adc0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_adc0 ] - - # Create instance: rst_adc0_x2, and set properties - set rst_adc0_x2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_adc0_x2 ] - - # Create instance: rst_dac0, and set properties - set rst_dac0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_dac0 ] - - # Create instance: rst_dac1, and set properties - set rst_dac1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_dac1 ] - - # Create instance: rst_tproc, and set properties - set rst_tproc [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_tproc ] - - # Create instance: usp_rf_data_converter_0, and set properties - set usp_rf_data_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:usp_rf_data_converter:2.4 usp_rf_data_converter_0 ] - set_property -dict [ list \ - CONFIG.ADC0_Fabric_Freq {552.960} \ - CONFIG.ADC0_Outclk_Freq {276.480} \ - CONFIG.ADC0_PLL_Enable {true} \ - CONFIG.ADC0_Refclk_Freq {491.520} \ - CONFIG.ADC0_Sampling_Rate {4.42368} \ - CONFIG.ADC_Coarse_Mixer_Freq02 {3} \ - CONFIG.ADC_Coarse_Mixer_Freq03 {3} \ - CONFIG.ADC_Data_Width00 {8} \ - CONFIG.ADC_Data_Width01 {8} \ - CONFIG.ADC_Data_Width02 {8} \ - CONFIG.ADC_Data_Width03 {8} \ - CONFIG.ADC_Decimation_Mode02 {1} \ - CONFIG.ADC_Decimation_Mode03 {1} \ - CONFIG.ADC_Mixer_Type02 {1} \ - CONFIG.ADC_Mixer_Type03 {1} \ - CONFIG.ADC_RESERVED_1_00 {false} \ - CONFIG.ADC_RESERVED_1_02 {false} \ - CONFIG.ADC_Slice02_Enable {true} \ - CONFIG.ADC_Slice03_Enable {true} \ - CONFIG.DAC0_Enable {1} \ - CONFIG.DAC0_Fabric_Freq {614.400} \ - CONFIG.DAC0_Outclk_Freq {614.400} \ - CONFIG.DAC0_PLL_Enable {true} \ - CONFIG.DAC0_Refclk_Freq {491.520} \ - CONFIG.DAC0_Sampling_Rate {9.8304} \ - CONFIG.DAC2_Enable {1} \ - CONFIG.DAC2_Fabric_Freq {614.400} \ - CONFIG.DAC2_Outclk_Freq {614.400} \ - CONFIG.DAC2_PLL_Enable {true} \ - CONFIG.DAC2_Refclk_Freq {491.520} \ - CONFIG.DAC2_Sampling_Rate {9.8304} \ - CONFIG.DAC_Coarse_Mixer_Freq00 {3} \ - CONFIG.DAC_Coarse_Mixer_Freq20 {3} \ - CONFIG.DAC_Interpolation_Mode00 {1} \ - CONFIG.DAC_Interpolation_Mode20 {1} \ - CONFIG.DAC_Mixer_Type00 {1} \ - CONFIG.DAC_Mixer_Type20 {1} \ - CONFIG.DAC_Mode00 {3} \ - CONFIG.DAC_Mode20 {3} \ - CONFIG.DAC_RESERVED_1_00 {false} \ - CONFIG.DAC_RESERVED_1_01 {false} \ - CONFIG.DAC_RESERVED_1_02 {false} \ - CONFIG.DAC_RESERVED_1_03 {false} \ - CONFIG.DAC_RESERVED_1_20 {false} \ - CONFIG.DAC_RESERVED_1_21 {false} \ - CONFIG.DAC_RESERVED_1_22 {false} \ - CONFIG.DAC_RESERVED_1_23 {false} \ - CONFIG.DAC_Slice00_Enable {true} \ - CONFIG.DAC_Slice20_Enable {true} \ - ] $usp_rf_data_converter_0 - - # Create instance: vect2bits_16_0, and set properties - set block_name vect2bits_16 - set block_cell_name vect2bits_16_0 - if { [catch {set vect2bits_16_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { - catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} - return 1 - } elseif { $vect2bits_16_0 eq "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} - return 1 - } - - # Create instance: xlconstant_0, and set properties - set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - CONFIG.CONST_WIDTH {64} \ - ] $xlconstant_0 - - # Create instance: xlconstant_1, and set properties - set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {1} \ - CONFIG.CONST_WIDTH {1} \ - ] $xlconstant_1 - - # Create instance: xlconstant_2, and set properties - set xlconstant_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_2 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - CONFIG.CONST_WIDTH {1} \ - ] $xlconstant_2 - - # Create instance: xlconstant_3, and set properties - set xlconstant_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_3 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - CONFIG.CONST_WIDTH {8} \ - ] $xlconstant_3 - - # Create instance: zynq_ultra_ps_e_0, and set properties - set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ] - set_property -dict [ list \ - CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS33} \ - CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \ - CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \ - CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \ - CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \ - CONFIG.PSU_MIO_0_DIRECTION {inout} \ - CONFIG.PSU_MIO_0_POLARITY {Default} \ - CONFIG.PSU_MIO_10_DIRECTION {inout} \ - CONFIG.PSU_MIO_10_POLARITY {Default} \ - CONFIG.PSU_MIO_11_DIRECTION {inout} \ - CONFIG.PSU_MIO_11_POLARITY {Default} \ - CONFIG.PSU_MIO_12_DIRECTION {inout} \ - CONFIG.PSU_MIO_12_POLARITY {Default} \ - CONFIG.PSU_MIO_13_DIRECTION {inout} \ - CONFIG.PSU_MIO_13_POLARITY {Default} \ - CONFIG.PSU_MIO_14_DIRECTION {inout} \ - CONFIG.PSU_MIO_14_POLARITY {Default} \ - CONFIG.PSU_MIO_15_DIRECTION {inout} \ - CONFIG.PSU_MIO_15_POLARITY {Default} \ - CONFIG.PSU_MIO_16_DIRECTION {inout} \ - CONFIG.PSU_MIO_16_POLARITY {Default} \ - CONFIG.PSU_MIO_17_DIRECTION {inout} \ - CONFIG.PSU_MIO_17_POLARITY {Default} \ - CONFIG.PSU_MIO_18_DIRECTION {inout} \ - CONFIG.PSU_MIO_18_POLARITY {Default} \ - CONFIG.PSU_MIO_19_DIRECTION {inout} \ - CONFIG.PSU_MIO_19_POLARITY {Default} \ - CONFIG.PSU_MIO_1_DIRECTION {out} \ - CONFIG.PSU_MIO_1_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_1_POLARITY {Default} \ - CONFIG.PSU_MIO_20_DIRECTION {inout} \ - CONFIG.PSU_MIO_20_POLARITY {Default} \ - CONFIG.PSU_MIO_21_DIRECTION {inout} \ - CONFIG.PSU_MIO_21_POLARITY {Default} \ - CONFIG.PSU_MIO_22_DIRECTION {out} \ - CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_22_POLARITY {Default} \ - CONFIG.PSU_MIO_23_DIRECTION {inout} \ - CONFIG.PSU_MIO_23_POLARITY {Default} \ - CONFIG.PSU_MIO_24_DIRECTION {in} \ - CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_24_POLARITY {Default} \ - CONFIG.PSU_MIO_24_SLEW {fast} \ - CONFIG.PSU_MIO_25_DIRECTION {in} \ - CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_25_POLARITY {Default} \ - CONFIG.PSU_MIO_25_SLEW {fast} \ - CONFIG.PSU_MIO_26_DIRECTION {inout} \ - CONFIG.PSU_MIO_26_POLARITY {Default} \ - CONFIG.PSU_MIO_27_DIRECTION {out} \ - CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_27_POLARITY {Default} \ - CONFIG.PSU_MIO_28_DIRECTION {in} \ - CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_28_POLARITY {Default} \ - CONFIG.PSU_MIO_28_SLEW {fast} \ - CONFIG.PSU_MIO_29_DIRECTION {out} \ - CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_29_POLARITY {Default} \ - CONFIG.PSU_MIO_2_DIRECTION {out} \ - CONFIG.PSU_MIO_2_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_2_POLARITY {Default} \ - CONFIG.PSU_MIO_30_DIRECTION {in} \ - CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_30_POLARITY {Default} \ - CONFIG.PSU_MIO_30_SLEW {fast} \ - CONFIG.PSU_MIO_31_DIRECTION {inout} \ - CONFIG.PSU_MIO_31_POLARITY {Default} \ - CONFIG.PSU_MIO_32_DIRECTION {out} \ - CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_32_POLARITY {Default} \ - CONFIG.PSU_MIO_33_DIRECTION {in} \ - CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_33_POLARITY {Default} \ - CONFIG.PSU_MIO_33_SLEW {fast} \ - CONFIG.PSU_MIO_34_DIRECTION {inout} \ - CONFIG.PSU_MIO_34_POLARITY {Default} \ - CONFIG.PSU_MIO_35_DIRECTION {inout} \ - CONFIG.PSU_MIO_35_POLARITY {Default} \ - CONFIG.PSU_MIO_36_DIRECTION {inout} \ - CONFIG.PSU_MIO_36_POLARITY {Default} \ - CONFIG.PSU_MIO_37_DIRECTION {inout} \ - CONFIG.PSU_MIO_37_POLARITY {Default} \ - CONFIG.PSU_MIO_38_DIRECTION {out} \ - CONFIG.PSU_MIO_38_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_38_POLARITY {Default} \ - CONFIG.PSU_MIO_39_DIRECTION {out} \ - CONFIG.PSU_MIO_39_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_39_POLARITY {Default} \ - CONFIG.PSU_MIO_3_DIRECTION {inout} \ - CONFIG.PSU_MIO_3_POLARITY {Default} \ - CONFIG.PSU_MIO_40_DIRECTION {out} \ - CONFIG.PSU_MIO_40_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_40_POLARITY {Default} \ - CONFIG.PSU_MIO_41_DIRECTION {out} \ - CONFIG.PSU_MIO_41_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_41_POLARITY {Default} \ - CONFIG.PSU_MIO_42_DIRECTION {out} \ - CONFIG.PSU_MIO_42_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_42_POLARITY {Default} \ - CONFIG.PSU_MIO_43_DIRECTION {out} \ - CONFIG.PSU_MIO_43_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_43_POLARITY {Default} \ - CONFIG.PSU_MIO_44_DIRECTION {in} \ - CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_44_POLARITY {Default} \ - CONFIG.PSU_MIO_44_SLEW {fast} \ - CONFIG.PSU_MIO_45_DIRECTION {in} \ - CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_45_POLARITY {Default} \ - CONFIG.PSU_MIO_45_SLEW {fast} \ - CONFIG.PSU_MIO_46_DIRECTION {in} \ - CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_46_POLARITY {Default} \ - CONFIG.PSU_MIO_46_SLEW {fast} \ - CONFIG.PSU_MIO_47_DIRECTION {in} \ - CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_47_POLARITY {Default} \ - CONFIG.PSU_MIO_47_SLEW {fast} \ - CONFIG.PSU_MIO_48_DIRECTION {in} \ - CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_48_POLARITY {Default} \ - CONFIG.PSU_MIO_48_SLEW {fast} \ - CONFIG.PSU_MIO_49_DIRECTION {in} \ - CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_49_POLARITY {Default} \ - CONFIG.PSU_MIO_49_SLEW {fast} \ - CONFIG.PSU_MIO_4_DIRECTION {inout} \ - CONFIG.PSU_MIO_4_POLARITY {Default} \ - CONFIG.PSU_MIO_50_DIRECTION {out} \ - CONFIG.PSU_MIO_50_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_50_POLARITY {Default} \ - CONFIG.PSU_MIO_51_DIRECTION {inout} \ - CONFIG.PSU_MIO_51_POLARITY {Default} \ - CONFIG.PSU_MIO_52_DIRECTION {in} \ - CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_52_POLARITY {Default} \ - CONFIG.PSU_MIO_52_SLEW {fast} \ - CONFIG.PSU_MIO_53_DIRECTION {in} \ - CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_53_POLARITY {Default} \ - CONFIG.PSU_MIO_53_SLEW {fast} \ - CONFIG.PSU_MIO_54_DIRECTION {inout} \ - CONFIG.PSU_MIO_54_POLARITY {Default} \ - CONFIG.PSU_MIO_55_DIRECTION {in} \ - CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_55_POLARITY {Default} \ - CONFIG.PSU_MIO_55_SLEW {fast} \ - CONFIG.PSU_MIO_56_DIRECTION {inout} \ - CONFIG.PSU_MIO_56_POLARITY {Default} \ - CONFIG.PSU_MIO_57_DIRECTION {inout} \ - CONFIG.PSU_MIO_57_POLARITY {Default} \ - CONFIG.PSU_MIO_58_DIRECTION {out} \ - CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_58_POLARITY {Default} \ - CONFIG.PSU_MIO_59_DIRECTION {inout} \ - CONFIG.PSU_MIO_59_POLARITY {Default} \ - CONFIG.PSU_MIO_5_DIRECTION {inout} \ - CONFIG.PSU_MIO_5_POLARITY {Default} \ - CONFIG.PSU_MIO_60_DIRECTION {inout} \ - CONFIG.PSU_MIO_60_POLARITY {Default} \ - CONFIG.PSU_MIO_61_DIRECTION {inout} \ - CONFIG.PSU_MIO_61_POLARITY {Default} \ - CONFIG.PSU_MIO_62_DIRECTION {inout} \ - CONFIG.PSU_MIO_62_POLARITY {Default} \ - CONFIG.PSU_MIO_63_DIRECTION {inout} \ - CONFIG.PSU_MIO_63_POLARITY {Default} \ - CONFIG.PSU_MIO_64_DIRECTION {in} \ - CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_64_POLARITY {Default} \ - CONFIG.PSU_MIO_64_SLEW {fast} \ - CONFIG.PSU_MIO_65_DIRECTION {in} \ - CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_65_POLARITY {Default} \ - CONFIG.PSU_MIO_65_SLEW {fast} \ - CONFIG.PSU_MIO_66_DIRECTION {inout} \ - CONFIG.PSU_MIO_66_POLARITY {Default} \ - CONFIG.PSU_MIO_67_DIRECTION {in} \ - CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_67_POLARITY {Default} \ - CONFIG.PSU_MIO_67_SLEW {fast} \ - CONFIG.PSU_MIO_68_DIRECTION {inout} \ - CONFIG.PSU_MIO_68_POLARITY {Default} \ - CONFIG.PSU_MIO_69_DIRECTION {inout} \ - CONFIG.PSU_MIO_69_POLARITY {Default} \ - CONFIG.PSU_MIO_6_DIRECTION {inout} \ - CONFIG.PSU_MIO_6_POLARITY {Default} \ - CONFIG.PSU_MIO_70_DIRECTION {out} \ - CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_70_POLARITY {Default} \ - CONFIG.PSU_MIO_71_DIRECTION {inout} \ - CONFIG.PSU_MIO_71_POLARITY {Default} \ - CONFIG.PSU_MIO_72_DIRECTION {inout} \ - CONFIG.PSU_MIO_72_POLARITY {Default} \ - CONFIG.PSU_MIO_73_DIRECTION {inout} \ - CONFIG.PSU_MIO_73_POLARITY {Default} \ - CONFIG.PSU_MIO_74_DIRECTION {inout} \ - CONFIG.PSU_MIO_74_POLARITY {Default} \ - CONFIG.PSU_MIO_75_DIRECTION {inout} \ - CONFIG.PSU_MIO_75_POLARITY {Default} \ - CONFIG.PSU_MIO_76_DIRECTION {inout} \ - CONFIG.PSU_MIO_76_POLARITY {Default} \ - CONFIG.PSU_MIO_77_DIRECTION {inout} \ - CONFIG.PSU_MIO_77_POLARITY {Default} \ - CONFIG.PSU_MIO_7_DIRECTION {inout} \ - CONFIG.PSU_MIO_7_POLARITY {Default} \ - CONFIG.PSU_MIO_8_DIRECTION {inout} \ - CONFIG.PSU_MIO_8_POLARITY {Default} \ - CONFIG.PSU_MIO_9_DIRECTION {inout} \ - CONFIG.PSU_MIO_9_POLARITY {Default} \ - CONFIG.PSU_MIO_TREE_PERIPHERALS {SPI 0#SPI 0#SPI 0#SPI 0#SPI 0#SPI 0#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#I2C 0#I2C 0#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#SD 0#GPIO1 MIO#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#UART 1#UART 1#GPIO1 MIO#GPIO1 MIO#I2C 1#I2C 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#MDIO 1#MDIO 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \ - CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#n_ss_out[2]#n_ss_out[1]#n_ss_out[0]#miso#mosi#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#scl_out#sda_out#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#sdio0_wp#gpio1[26]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#txd#rxd#gpio1[34]#gpio1[35]#scl_out#sda_out#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem1_mdc#gem1_mdio_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]} \ - CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \ - CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \ - CONFIG.PSU__ACT_DDR_FREQ_MHZ {1199.999756} \ - CONFIG.PSU__AFI0_COHERENCY {0} \ - CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \ - CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1199.999756} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {249.999954} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {249.999954} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {599.999878} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1200} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {599.999878} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {72} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.999996} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {21} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.249996} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {20} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {299.999939} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {599.999878} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {600} \ - CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {99.999985} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {399.999908} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {90} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {524.999939} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {533.333} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {49.999992} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {499.999908} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {249.999954} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1499.999756} \ - CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {124.999977} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {249.999954} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {99.999985} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {99.999985} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {262.499969} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {267} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {99.999985} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {524.999939} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {533.333} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.499969} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {99.999985} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {63} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {187.499969} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {8} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {7} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {187.499969} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {8} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {187.499969} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {8} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {33.333328} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {1} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {99.999985} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {249.999954} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {249.999954} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {19.999996} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \ - CONFIG.PSU__DDRC__ADDR_MIRROR {0} \ - CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \ - CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \ - CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \ - CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \ - CONFIG.PSU__DDRC__CL {16} \ - CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \ - CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \ - CONFIG.PSU__DDRC__COMPONENTS {Components} \ - CONFIG.PSU__DDRC__CWL {12} \ - CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {1} \ - CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \ - CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \ - CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \ - CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \ - CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \ - CONFIG.PSU__DDRC__DEVICE_CAPACITY {8192 MBits} \ - CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \ - CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \ - CONFIG.PSU__DDRC__DQMAP_0_3 {0} \ - CONFIG.PSU__DDRC__DQMAP_12_15 {0} \ - CONFIG.PSU__DDRC__DQMAP_16_19 {0} \ - CONFIG.PSU__DDRC__DQMAP_20_23 {0} \ - CONFIG.PSU__DDRC__DQMAP_24_27 {0} \ - CONFIG.PSU__DDRC__DQMAP_28_31 {0} \ - CONFIG.PSU__DDRC__DQMAP_32_35 {0} \ - CONFIG.PSU__DDRC__DQMAP_36_39 {0} \ - CONFIG.PSU__DDRC__DQMAP_40_43 {0} \ - CONFIG.PSU__DDRC__DQMAP_44_47 {0} \ - CONFIG.PSU__DDRC__DQMAP_48_51 {0} \ - CONFIG.PSU__DDRC__DQMAP_4_7 {0} \ - CONFIG.PSU__DDRC__DQMAP_52_55 {0} \ - CONFIG.PSU__DDRC__DQMAP_56_59 {0} \ - CONFIG.PSU__DDRC__DQMAP_60_63 {0} \ - CONFIG.PSU__DDRC__DQMAP_64_67 {0} \ - CONFIG.PSU__DDRC__DQMAP_68_71 {0} \ - CONFIG.PSU__DDRC__DQMAP_8_11 {0} \ - CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \ - CONFIG.PSU__DDRC__ECC {Disabled} \ - CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \ - CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \ - CONFIG.PSU__DDRC__FGRM {1X} \ - CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__LP_ASR {manual normal} \ - CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \ - CONFIG.PSU__DDRC__PARITY_ENABLE {0} \ - CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \ - CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \ - CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \ - CONFIG.PSU__DDRC__ROW_ADDR_COUNT {17} \ - CONFIG.PSU__DDRC__SB_TARGET {16-16-16} \ - CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \ - CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2400R} \ - CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \ - CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \ - CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \ - CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \ - CONFIG.PSU__DDRC__T_FAW {30.0} \ - CONFIG.PSU__DDRC__T_RAS_MIN {32.0} \ - CONFIG.PSU__DDRC__T_RC {45.32} \ - CONFIG.PSU__DDRC__T_RCD {16} \ - CONFIG.PSU__DDRC__T_RP {16} \ - CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \ - CONFIG.PSU__DDRC__VREF {1} \ - CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \ - CONFIG.PSU__DDR__INTERFACE__FREQMHZ {600.000} \ - CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \ - CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \ - CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \ - CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \ - CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__DLL__ISUSED {1} \ - CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \ - CONFIG.PSU__DP__LANE_SEL {Dual Lower} \ - CONFIG.PSU__DP__REF_CLK_FREQ {27} \ - CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk0} \ - CONFIG.PSU__ENET1__FIFO__ENABLE {0} \ - CONFIG.PSU__ENET1__GRP_MDIO__ENABLE {1} \ - CONFIG.PSU__ENET1__GRP_MDIO__IO {MIO 50 .. 51} \ - CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__ENET1__PERIPHERAL__IO {MIO 38 .. 49} \ - CONFIG.PSU__ENET1__PTP__ENABLE {0} \ - CONFIG.PSU__ENET1__TSU__ENABLE {0} \ - CONFIG.PSU__FPGA_PL0_ENABLE {1} \ - CONFIG.PSU__GEM1_COHERENCY {0} \ - CONFIG.PSU__GEM1_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__GEM__TSU__ENABLE {0} \ - CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \ - CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \ - CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__GPIO2_MIO__IO {MIO 52 .. 77} \ - CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__GPIO_EMIO_WIDTH {41} \ - CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {41} \ - CONFIG.PSU__GT__LINK_SPEED {HBR} \ - CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \ - CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \ - CONFIG.PSU__HIGH_ADDRESS__ENABLE {1} \ - CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 18 .. 19} \ - CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 36 .. 37} \ - CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \ - CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \ - CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \ - CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \ - CONFIG.PSU__PL_CLK0_BUF {TRUE} \ - CONFIG.PSU__PMU_COHERENCY {0} \ - CONFIG.PSU__PMU__AIBACK__ENABLE {0} \ - CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \ - CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \ - CONFIG.PSU__PMU__GPI0__ENABLE {0} \ - CONFIG.PSU__PMU__GPI1__ENABLE {0} \ - CONFIG.PSU__PMU__GPI2__ENABLE {0} \ - CONFIG.PSU__PMU__GPI3__ENABLE {0} \ - CONFIG.PSU__PMU__GPI4__ENABLE {0} \ - CONFIG.PSU__PMU__GPI5__ENABLE {0} \ - CONFIG.PSU__PMU__GPO0__ENABLE {0} \ - CONFIG.PSU__PMU__GPO1__ENABLE {0} \ - CONFIG.PSU__PMU__GPO2__ENABLE {0} \ - CONFIG.PSU__PMU__GPO3__ENABLE {0} \ - CONFIG.PSU__PMU__GPO4__ENABLE {0} \ - CONFIG.PSU__PMU__GPO5__ENABLE {0} \ - CONFIG.PSU__PMU__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__PMU__PLERROR__ENABLE {0} \ - CONFIG.PSU__PRESET_APPLIED {1} \ - CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;1|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;1|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;0|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;1|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \ - CONFIG.PSU__PROTECTION__SLAVES { \ - LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;0|LPD;TTC3;FF140000;FF14FFFF;0|LPD;TTC2;FF130000;FF13FFFF;0|LPD;TTC1;FF120000;FF12FFFF;0|LPD;TTC0;FF110000;FF11FFFF;0|FPD;SWDT1;FD4D0000;FD4DFFFF;0|LPD;SWDT0;FF150000;FF15FFFF;0|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;0|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;1|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1 \ - } \ - CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.33333} \ - CONFIG.PSU__QSPI_COHERENCY {0} \ - CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \ - CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__SAXIGP0__DATA_WIDTH {128} \ - CONFIG.PSU__SD0_COHERENCY {0} \ - CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__SD0__DATA_TRANSFER_MODE {4Bit} \ - CONFIG.PSU__SD0__GRP_CD__ENABLE {1} \ - CONFIG.PSU__SD0__GRP_CD__IO {MIO 24} \ - CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \ - CONFIG.PSU__SD0__GRP_WP__ENABLE {1} \ - CONFIG.PSU__SD0__GRP_WP__IO {MIO 25} \ - CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 16 21 22} \ - CONFIG.PSU__SD0__RESET__ENABLE {0} \ - CONFIG.PSU__SD0__SLOT_TYPE {SD 2.0} \ - CONFIG.PSU__SPI0__GRP_SS0__ENABLE {1} \ - CONFIG.PSU__SPI0__GRP_SS0__IO {MIO 3} \ - CONFIG.PSU__SPI0__GRP_SS1__ENABLE {1} \ - CONFIG.PSU__SPI0__GRP_SS1__IO {MIO 2} \ - CONFIG.PSU__SPI0__GRP_SS2__ENABLE {1} \ - CONFIG.PSU__SPI0__GRP_SS2__IO {MIO 1} \ - CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__SPI0__PERIPHERAL__IO {MIO 0 .. 5} \ - CONFIG.PSU__SPI1__GRP_SS0__ENABLE {1} \ - CONFIG.PSU__SPI1__GRP_SS0__IO {MIO 9} \ - CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \ - CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \ - CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__SPI1__PERIPHERAL__IO {MIO 6 .. 11} \ - CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \ - CONFIG.PSU__UART0__MODEM__ENABLE {0} \ - CONFIG.PSU__UART0__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__UART1__BAUD_RATE {115200} \ - CONFIG.PSU__UART1__MODEM__ENABLE {0} \ - CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 32 .. 33} \ - CONFIG.PSU__USB0_COHERENCY {0} \ - CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \ - CONFIG.PSU__USB0__REF_CLK_FREQ {100} \ - CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk1} \ - CONFIG.PSU__USB0__RESET__ENABLE {0} \ - CONFIG.PSU__USB1_COHERENCY {0} \ - CONFIG.PSU__USB1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__USB1__PERIPHERAL__IO {MIO 64 .. 75} \ - CONFIG.PSU__USB1__REF_CLK_FREQ {100} \ - CONFIG.PSU__USB1__REF_CLK_SEL {Ref Clk1} \ - CONFIG.PSU__USB1__RESET__ENABLE {0} \ - CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \ - CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \ - CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \ - CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \ - CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \ - CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__USB3_1__PERIPHERAL__IO {GT Lane3} \ - CONFIG.PSU__USB__RESET__MODE {Boot Pin} \ - CONFIG.PSU__USB__RESET__POLARITY {Active Low} \ - CONFIG.PSU__USE__IRQ0 {1} \ - CONFIG.PSU__USE__IRQ1 {1} \ - CONFIG.PSU__USE__M_AXI_GP0 {1} \ - CONFIG.PSU__USE__M_AXI_GP1 {0} \ - CONFIG.PSU__USE__M_AXI_GP2 {0} \ - CONFIG.PSU__USE__S_AXI_GP0 {1} \ - CONFIG.SUBPRESET1 {Custom} \ - ] $zynq_ultra_ps_e_0 - - # Create interface connections - connect_bd_intf_net -intf_net adc0_clk_1 [get_bd_intf_ports adc0_clk] [get_bd_intf_pins usp_rf_data_converter_0/adc0_clk] - connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins axi_bram_ctrl_0_bram/BRAM_PORTA] - connect_bd_intf_net -intf_net axi_dma_avg_M_AXI_S2MM [get_bd_intf_pins axi_dma_avg/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S00_AXI] - connect_bd_intf_net -intf_net axi_dma_buf_M_AXI_S2MM [get_bd_intf_pins axi_dma_buf/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S01_AXI] - connect_bd_intf_net -intf_net axi_dma_gen_M_AXIS_MM2S [get_bd_intf_pins axi_dma_gen/M_AXIS_MM2S] [get_bd_intf_pins axis_switch_gen/S00_AXIS] - connect_bd_intf_net -intf_net axi_dma_gen_M_AXI_MM2S [get_bd_intf_pins axi_dma_gen/M_AXI_MM2S] [get_bd_intf_pins axi_smc/S03_AXI] - connect_bd_intf_net -intf_net axi_dma_readout_M_AXI_S2MM [get_bd_intf_pins axi_dma_readout/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S02_AXI] - connect_bd_intf_net -intf_net axi_dma_tproc_M_AXIS_MM2S [get_bd_intf_pins axi_dma_tproc/M_AXIS_MM2S] [get_bd_intf_pins axis_tproc64x32_x8_0/s0_axis] - connect_bd_intf_net -intf_net axi_dma_tproc_M_AXI_MM2S [get_bd_intf_pins axi_dma_tproc/M_AXI_MM2S] [get_bd_intf_pins axi_smc/S04_AXI] - connect_bd_intf_net -intf_net axi_dma_tproc_M_AXI_S2MM [get_bd_intf_pins axi_dma_tproc/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S05_AXI] - connect_bd_intf_net -intf_net axi_smc_M00_AXI [get_bd_intf_pins axi_smc/M00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HPC0_FPD] - connect_bd_intf_net -intf_net axis_avg_buffer_0_m0_axis [get_bd_intf_pins axis_avg_buffer_0/m0_axis] [get_bd_intf_pins axis_switch_avg/S00_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_0_m1_axis [get_bd_intf_pins axis_avg_buffer_0/m1_axis] [get_bd_intf_pins axis_switch_buf/S00_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_0_m2_axis [get_bd_intf_pins axis_avg_buffer_0/m2_axis] [get_bd_intf_pins axis_cc_avg_0/S_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_1_m0_axis [get_bd_intf_pins axis_avg_buffer_1/m0_axis] [get_bd_intf_pins axis_switch_avg/S01_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_1_m1_axis [get_bd_intf_pins axis_avg_buffer_1/m1_axis] [get_bd_intf_pins axis_switch_buf/S01_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_1_m2_axis [get_bd_intf_pins axis_avg_buffer_1/m2_axis] [get_bd_intf_pins axis_cc_avg_1/S_AXIS] - connect_bd_intf_net -intf_net axis_cc_avg_0_M_AXIS [get_bd_intf_pins axis_cc_avg_0/M_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/s1_axis] - connect_bd_intf_net -intf_net axis_cc_avg_1_M_AXIS [get_bd_intf_pins axis_cc_avg_1/M_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/s2_axis] - connect_bd_intf_net -intf_net axis_cc_sg_0_M_AXIS [get_bd_intf_pins axis_cc_sg_0/M_AXIS] [get_bd_intf_pins axis_signal_gen_v6_0/s1_axis] - connect_bd_intf_net -intf_net axis_cc_sg_1_M_AXIS [get_bd_intf_pins axis_cc_sg_1/M_AXIS] [get_bd_intf_pins axis_signal_gen_v6_1/s1_axis] - connect_bd_intf_net -intf_net axis_constant_0_m_axis [get_bd_intf_pins axis_constant_0/m_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/s3_axis] - connect_bd_intf_net -intf_net axis_constant_1_m_axis [get_bd_intf_pins axis_constant_1/m_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/s4_axis] - connect_bd_intf_net -intf_net axis_readout_v2_0_m0_axis [get_bd_intf_pins axis_readout_v2_0/m0_axis] [get_bd_intf_pins axis_switch_readout/S00_AXIS] - connect_bd_intf_net -intf_net axis_readout_v2_0_m1_axis [get_bd_intf_pins axis_avg_buffer_0/s_axis] [get_bd_intf_pins axis_readout_v2_0/m1_axis] - connect_bd_intf_net -intf_net axis_readout_v2_1_m0_axis [get_bd_intf_pins axis_readout_v2_1/m0_axis] [get_bd_intf_pins axis_switch_readout/S01_AXIS] - connect_bd_intf_net -intf_net axis_readout_v2_1_m1_axis [get_bd_intf_pins axis_avg_buffer_1/s_axis] [get_bd_intf_pins axis_readout_v2_1/m1_axis] - connect_bd_intf_net -intf_net axis_register_slice_2_M_AXIS [get_bd_intf_pins axis_readout_v2_0/s_axis] [get_bd_intf_pins axis_register_slice_2/M_AXIS] - connect_bd_intf_net -intf_net axis_register_slice_3_M_AXIS [get_bd_intf_pins axis_readout_v2_1/s_axis] [get_bd_intf_pins axis_register_slice_3/M_AXIS] - connect_bd_intf_net -intf_net axis_register_slice_4_m_axis [get_bd_intf_pins axis_register_slice_1/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s20_axis] - connect_bd_intf_net -intf_net axis_register_slice_6_m_axis [get_bd_intf_pins axis_register_slice_0/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s00_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v6_0_m_axis [get_bd_intf_pins axis_register_slice_0/s_axis] [get_bd_intf_pins axis_signal_gen_v6_0/m_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v6_1_m_axis [get_bd_intf_pins axis_register_slice_1/s_axis] [get_bd_intf_pins axis_signal_gen_v6_1/m_axis] - connect_bd_intf_net -intf_net axis_switch_0_M00_AXIS [get_bd_intf_pins axis_switch_readout/M00_AXIS] [get_bd_intf_pins mr_buffer_et_0/s00_axis] - connect_bd_intf_net -intf_net axis_switch_avg_M00_AXIS [get_bd_intf_pins axi_dma_avg/S_AXIS_S2MM] [get_bd_intf_pins axis_switch_avg/M00_AXIS] - connect_bd_intf_net -intf_net axis_switch_buf_M00_AXIS [get_bd_intf_pins axi_dma_buf/S_AXIS_S2MM] [get_bd_intf_pins axis_switch_buf/M00_AXIS] - connect_bd_intf_net -intf_net axis_switch_gen_M00_AXIS [get_bd_intf_pins axis_signal_gen_v6_0/s0_axis] [get_bd_intf_pins axis_switch_gen/M00_AXIS] - connect_bd_intf_net -intf_net axis_switch_gen_M01_AXIS [get_bd_intf_pins axis_signal_gen_v6_1/s0_axis] [get_bd_intf_pins axis_switch_gen/M01_AXIS] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m0_axis [get_bd_intf_pins axi_dma_tproc/S_AXIS_S2MM] [get_bd_intf_pins axis_tproc64x32_x8_0/m0_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m1_axis [get_bd_intf_pins axis_cc_sg_0/S_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/m1_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m2_axis [get_bd_intf_pins axis_cc_sg_1/S_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/m2_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m8_axis [get_bd_intf_pins axis_set_reg_0/s_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m8_axis] - connect_bd_intf_net -intf_net dac0_clk_1 [get_bd_intf_ports dac0_clk] [get_bd_intf_pins usp_rf_data_converter_0/dac0_clk] - connect_bd_intf_net -intf_net dac2_clk_1 [get_bd_intf_ports dac2_clk] [get_bd_intf_pins usp_rf_data_converter_0/dac2_clk] - connect_bd_intf_net -intf_net mr_buffer_et_0_m00_axis [get_bd_intf_pins axi_dma_readout/S_AXIS_S2MM] [get_bd_intf_pins mr_buffer_et_0/m00_axis] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins axi_dma_avg/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M01_AXI [get_bd_intf_pins axi_dma_buf/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M01_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M02_AXI [get_bd_intf_pins axi_dma_readout/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M02_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M03_AXI [get_bd_intf_pins axis_avg_buffer_1/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M03_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M04_AXI [get_bd_intf_pins axis_readout_v2_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M04_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M05_AXI [get_bd_intf_pins axis_readout_v2_1/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M05_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M06_AXI [get_bd_intf_pins axis_switch_avg/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M06_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M07_AXI [get_bd_intf_pins axis_switch_buf/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M07_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M08_AXI [get_bd_intf_pins axis_switch_readout/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M08_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M09_AXI [get_bd_intf_pins axis_tproc64x32_x8_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M09_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M10_AXI [get_bd_intf_pins mr_buffer_et_0/s00_axi] [get_bd_intf_pins ps8_0_axi_periph/M10_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M11_AXI [get_bd_intf_pins ps8_0_axi_periph/M11_AXI] [get_bd_intf_pins usp_rf_data_converter_0/s_axi] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M12_AXI [get_bd_intf_pins axis_avg_buffer_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M12_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M13_AXI [get_bd_intf_pins axis_signal_gen_v6_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M13_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M14_AXI [get_bd_intf_pins axis_signal_gen_v6_1/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M14_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M15_AXI [get_bd_intf_pins axi_dma_gen/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M15_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M16_AXI [get_bd_intf_pins axis_switch_gen/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M16_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M17_AXI [get_bd_intf_pins axi_dma_tproc/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M17_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M18_AXI [get_bd_intf_pins axi_bram_ctrl_0/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M18_AXI] - connect_bd_intf_net -intf_net sysref_in_1 [get_bd_intf_ports sysref_in] [get_bd_intf_pins usp_rf_data_converter_0/sysref_in] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_m00_axis [get_bd_intf_pins axis_register_slice_2/S_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/m00_axis] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_m02_axis [get_bd_intf_pins axis_register_slice_3/S_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/m02_axis] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout00 [get_bd_intf_ports vout00] [get_bd_intf_pins usp_rf_data_converter_0/vout00] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout20 [get_bd_intf_ports vout20] [get_bd_intf_pins usp_rf_data_converter_0/vout20] - connect_bd_intf_net -intf_net vin0_01_1 [get_bd_intf_ports vin0_01] [get_bd_intf_pins usp_rf_data_converter_0/vin0_01] - connect_bd_intf_net -intf_net vin0_23_1 [get_bd_intf_ports vin0_23] [get_bd_intf_pins usp_rf_data_converter_0/vin0_23] - connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD] - - # Create port connections - connect_bd_net -net axi_bram_ctrl_0_bram_doutb [get_bd_pins axi_bram_ctrl_0_bram/doutb] [get_bd_pins axis_tproc64x32_x8_0/pmem_do] - connect_bd_net -net axis_set_reg_0_dout [get_bd_pins axis_set_reg_0/dout] [get_bd_pins vect2bits_16_0/din] - connect_bd_net -net axis_tproc64x32_x8_0_pmem_addr [get_bd_pins axi_bram_ctrl_0_bram/addrb] [get_bd_pins axis_tproc64x32_x8_0/pmem_addr] - connect_bd_net -net clk_adc0_x2_clk_out1 [get_bd_pins axis_avg_buffer_0/s_axis_aclk] [get_bd_pins axis_avg_buffer_1/s_axis_aclk] [get_bd_pins axis_readout_v2_0/aclk] [get_bd_pins axis_readout_v2_1/aclk] [get_bd_pins axis_register_slice_2/aclk] [get_bd_pins axis_register_slice_3/aclk] [get_bd_pins axis_switch_readout/aclk] [get_bd_pins clk_adc0_x2/clk_out1] [get_bd_pins mr_buffer_et_0/s00_axis_aclk] [get_bd_pins rst_adc0_x2/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/m0_axis_aclk] - connect_bd_net -net clk_adc0_x2_locked [get_bd_pins clk_adc0_x2/locked] [get_bd_pins rst_adc0_x2/dcm_locked] - connect_bd_net -net clk_tproc_clk_out1 [get_bd_pins axi_bram_ctrl_0_bram/clkb] [get_bd_pins axis_cc_avg_0/m_axis_aclk] [get_bd_pins axis_cc_avg_1/m_axis_aclk] [get_bd_pins axis_cc_sg_0/s_axis_aclk] [get_bd_pins axis_cc_sg_1/s_axis_aclk] [get_bd_pins axis_constant_0/m_axis_aclk] [get_bd_pins axis_constant_1/m_axis_aclk] [get_bd_pins axis_set_reg_0/s_axis_aclk] [get_bd_pins axis_tproc64x32_x8_0/aclk] [get_bd_pins clk_tproc/clk_out1] [get_bd_pins rst_tproc/slowest_sync_clk] - connect_bd_net -net clk_tproc_locked [get_bd_pins clk_tproc/locked] [get_bd_pins rst_tproc/dcm_locked] - connect_bd_net -net rst_adc0_peripheral_aresetn [get_bd_pins clk_adc0_x2/resetn] [get_bd_pins rst_adc0/peripheral_aresetn] - connect_bd_net -net rst_adc0_x2_peripheral_aresetn [get_bd_pins axis_avg_buffer_0/s_axis_aresetn] [get_bd_pins axis_avg_buffer_1/s_axis_aresetn] [get_bd_pins axis_readout_v2_0/aresetn] [get_bd_pins axis_readout_v2_1/aresetn] [get_bd_pins axis_register_slice_2/aresetn] [get_bd_pins axis_register_slice_3/aresetn] [get_bd_pins axis_switch_readout/aresetn] [get_bd_pins mr_buffer_et_0/s00_axis_aresetn] [get_bd_pins rst_adc0_x2/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/m0_axis_aresetn] - connect_bd_net -net rst_dac0_peripheral_aresetn [get_bd_pins axis_cc_sg_0/m_axis_aresetn] [get_bd_pins axis_register_slice_0/aresetn] [get_bd_pins axis_signal_gen_v6_0/aresetn] [get_bd_pins clk_tproc/resetn] [get_bd_pins rst_dac0/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/s0_axis_aresetn] - connect_bd_net -net rst_dac1_peripheral_aresetn [get_bd_pins axis_cc_sg_1/m_axis_aresetn] [get_bd_pins axis_register_slice_1/aresetn] [get_bd_pins axis_signal_gen_v6_1/aresetn] [get_bd_pins rst_dac1/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/s2_axis_aresetn] - connect_bd_net -net rst_ps8_0_99M_peripheral_aresetn [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_dma_avg/axi_resetn] [get_bd_pins axi_dma_buf/axi_resetn] [get_bd_pins axi_dma_gen/axi_resetn] [get_bd_pins axi_dma_readout/axi_resetn] [get_bd_pins axi_dma_tproc/axi_resetn] [get_bd_pins axi_smc/aresetn] [get_bd_pins axis_avg_buffer_0/m_axis_aresetn] [get_bd_pins axis_avg_buffer_0/s_axi_aresetn] [get_bd_pins axis_avg_buffer_1/m_axis_aresetn] [get_bd_pins axis_avg_buffer_1/s_axi_aresetn] [get_bd_pins axis_cc_avg_0/s_axis_aresetn] [get_bd_pins axis_cc_avg_1/s_axis_aresetn] [get_bd_pins axis_readout_v2_0/s_axi_aresetn] [get_bd_pins axis_readout_v2_1/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_0/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_0/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_1/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_1/s_axi_aresetn] [get_bd_pins axis_switch_avg/aresetn] [get_bd_pins axis_switch_avg/s_axi_ctrl_aresetn] [get_bd_pins axis_switch_buf/aresetn] [get_bd_pins axis_switch_buf/s_axi_ctrl_aresetn] [get_bd_pins axis_switch_gen/aresetn] [get_bd_pins axis_switch_gen/s_axi_ctrl_aresetn] [get_bd_pins axis_switch_readout/s_axi_ctrl_aresetn] [get_bd_pins axis_tproc64x32_x8_0/m0_axis_aresetn] [get_bd_pins axis_tproc64x32_x8_0/s0_axis_aresetn] [get_bd_pins axis_tproc64x32_x8_0/s_axi_aresetn] [get_bd_pins mr_buffer_et_0/m00_axis_aresetn] [get_bd_pins mr_buffer_et_0/s00_axi_aresetn] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/M01_ARESETN] [get_bd_pins ps8_0_axi_periph/M02_ARESETN] [get_bd_pins ps8_0_axi_periph/M03_ARESETN] [get_bd_pins ps8_0_axi_periph/M04_ARESETN] [get_bd_pins ps8_0_axi_periph/M05_ARESETN] [get_bd_pins ps8_0_axi_periph/M06_ARESETN] [get_bd_pins ps8_0_axi_periph/M07_ARESETN] [get_bd_pins ps8_0_axi_periph/M08_ARESETN] [get_bd_pins ps8_0_axi_periph/M09_ARESETN] [get_bd_pins ps8_0_axi_periph/M10_ARESETN] [get_bd_pins ps8_0_axi_periph/M11_ARESETN] [get_bd_pins ps8_0_axi_periph/M12_ARESETN] [get_bd_pins ps8_0_axi_periph/M13_ARESETN] [get_bd_pins ps8_0_axi_periph/M14_ARESETN] [get_bd_pins ps8_0_axi_periph/M15_ARESETN] [get_bd_pins ps8_0_axi_periph/M16_ARESETN] [get_bd_pins ps8_0_axi_periph/M17_ARESETN] [get_bd_pins ps8_0_axi_periph/M18_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins rst_100/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/s_axi_aresetn] - connect_bd_net -net rst_tproc_peripheral_aresetn [get_bd_pins axis_cc_avg_0/m_axis_aresetn] [get_bd_pins axis_cc_avg_1/m_axis_aresetn] [get_bd_pins axis_cc_sg_0/s_axis_aresetn] [get_bd_pins axis_cc_sg_1/s_axis_aresetn] [get_bd_pins axis_constant_0/m_axis_aresetn] [get_bd_pins axis_constant_1/m_axis_aresetn] [get_bd_pins axis_set_reg_0/s_axis_aresetn] [get_bd_pins axis_tproc64x32_x8_0/aresetn] [get_bd_pins rst_tproc/peripheral_aresetn] - connect_bd_net -net usp_rf_data_converter_0_clk_adc0 [get_bd_pins clk_adc0_x2/clk_in1] [get_bd_pins rst_adc0/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/clk_adc0] - connect_bd_net -net usp_rf_data_converter_0_clk_dac0 [get_bd_pins axis_cc_sg_0/m_axis_aclk] [get_bd_pins axis_register_slice_0/aclk] [get_bd_pins axis_signal_gen_v6_0/aclk] [get_bd_pins clk_tproc/clk_in1] [get_bd_pins rst_dac0/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/clk_dac0] [get_bd_pins usp_rf_data_converter_0/s0_axis_aclk] - connect_bd_net -net usp_rf_data_converter_0_clk_dac2 [get_bd_pins axis_cc_sg_1/m_axis_aclk] [get_bd_pins axis_register_slice_1/aclk] [get_bd_pins axis_signal_gen_v6_1/aclk] [get_bd_pins rst_dac1/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/clk_dac2] [get_bd_pins usp_rf_data_converter_0/s2_axis_aclk] - connect_bd_net -net vect2bits_16_0_dout0 [get_bd_ports PMOD0_0] [get_bd_pins vect2bits_16_0/dout0] - connect_bd_net -net vect2bits_16_0_dout1 [get_bd_ports PMOD0_1] [get_bd_pins vect2bits_16_0/dout1] - connect_bd_net -net vect2bits_16_0_dout2 [get_bd_ports PMOD0_2] [get_bd_pins vect2bits_16_0/dout2] - connect_bd_net -net vect2bits_16_0_dout3 [get_bd_ports PMOD0_3] [get_bd_pins vect2bits_16_0/dout3] - connect_bd_net -net vect2bits_16_0_dout4 [get_bd_pins axis_avg_buffer_0/trigger] [get_bd_pins vect2bits_16_0/dout4] - connect_bd_net -net vect2bits_16_0_dout5 [get_bd_pins axis_avg_buffer_1/trigger] [get_bd_pins vect2bits_16_0/dout5] - connect_bd_net -net vect2bits_16_0_dout6 [get_bd_pins mr_buffer_et_0/trigger] [get_bd_pins vect2bits_16_0/dout6] - connect_bd_net -net xlconstant_0_dout [get_bd_pins axi_bram_ctrl_0_bram/dinb] [get_bd_pins xlconstant_0/dout] - connect_bd_net -net xlconstant_1_dout [get_bd_pins axi_bram_ctrl_0_bram/enb] [get_bd_pins axis_tproc64x32_x8_0/start] [get_bd_pins xlconstant_1/dout] - connect_bd_net -net xlconstant_2_dout [get_bd_pins axi_bram_ctrl_0_bram/rstb] [get_bd_pins xlconstant_2/dout] - connect_bd_net -net xlconstant_3_dout [get_bd_pins axi_bram_ctrl_0_bram/web] [get_bd_pins xlconstant_3/dout] - connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_dma_avg/m_axi_s2mm_aclk] [get_bd_pins axi_dma_avg/s_axi_lite_aclk] [get_bd_pins axi_dma_buf/m_axi_s2mm_aclk] [get_bd_pins axi_dma_buf/s_axi_lite_aclk] [get_bd_pins axi_dma_gen/m_axi_mm2s_aclk] [get_bd_pins axi_dma_gen/s_axi_lite_aclk] [get_bd_pins axi_dma_readout/m_axi_s2mm_aclk] [get_bd_pins axi_dma_readout/s_axi_lite_aclk] [get_bd_pins axi_dma_tproc/m_axi_mm2s_aclk] [get_bd_pins axi_dma_tproc/m_axi_s2mm_aclk] [get_bd_pins axi_dma_tproc/s_axi_lite_aclk] [get_bd_pins axi_smc/aclk] [get_bd_pins axis_avg_buffer_0/m_axis_aclk] [get_bd_pins axis_avg_buffer_0/s_axi_aclk] [get_bd_pins axis_avg_buffer_1/m_axis_aclk] [get_bd_pins axis_avg_buffer_1/s_axi_aclk] [get_bd_pins axis_cc_avg_0/s_axis_aclk] [get_bd_pins axis_cc_avg_1/s_axis_aclk] [get_bd_pins axis_readout_v2_0/s_axi_aclk] [get_bd_pins axis_readout_v2_1/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_0/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_0/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_1/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_1/s_axi_aclk] [get_bd_pins axis_switch_avg/aclk] [get_bd_pins axis_switch_avg/s_axi_ctrl_aclk] [get_bd_pins axis_switch_buf/aclk] [get_bd_pins axis_switch_buf/s_axi_ctrl_aclk] [get_bd_pins axis_switch_gen/aclk] [get_bd_pins axis_switch_gen/s_axi_ctrl_aclk] [get_bd_pins axis_switch_readout/s_axi_ctrl_aclk] [get_bd_pins axis_tproc64x32_x8_0/m0_axis_aclk] [get_bd_pins axis_tproc64x32_x8_0/s0_axis_aclk] [get_bd_pins axis_tproc64x32_x8_0/s_axi_aclk] [get_bd_pins mr_buffer_et_0/m00_axis_aclk] [get_bd_pins mr_buffer_et_0/s00_axi_aclk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/M01_ACLK] [get_bd_pins ps8_0_axi_periph/M02_ACLK] [get_bd_pins ps8_0_axi_periph/M03_ACLK] [get_bd_pins ps8_0_axi_periph/M04_ACLK] [get_bd_pins ps8_0_axi_periph/M05_ACLK] [get_bd_pins ps8_0_axi_periph/M06_ACLK] [get_bd_pins ps8_0_axi_periph/M07_ACLK] [get_bd_pins ps8_0_axi_periph/M08_ACLK] [get_bd_pins ps8_0_axi_periph/M09_ACLK] [get_bd_pins ps8_0_axi_periph/M10_ACLK] [get_bd_pins ps8_0_axi_periph/M11_ACLK] [get_bd_pins ps8_0_axi_periph/M12_ACLK] [get_bd_pins ps8_0_axi_periph/M13_ACLK] [get_bd_pins ps8_0_axi_periph/M14_ACLK] [get_bd_pins ps8_0_axi_periph/M15_ACLK] [get_bd_pins ps8_0_axi_periph/M16_ACLK] [get_bd_pins ps8_0_axi_periph/M17_ACLK] [get_bd_pins ps8_0_axi_periph/M18_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins rst_100/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/s_axi_aclk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins zynq_ultra_ps_e_0/saxihpc0_fpd_aclk] - connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins rst_100/ext_reset_in] [get_bd_pins rst_adc0/ext_reset_in] [get_bd_pins rst_adc0_x2/ext_reset_in] [get_bd_pins rst_dac0/ext_reset_in] [get_bd_pins rst_dac1/ext_reset_in] [get_bd_pins rst_tproc/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] - - # Create address segments - assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force - assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force - assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force - assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_readout/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force - assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force - assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force - assign_bd_address -offset 0xA0140000 -range 0x00002000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force - assign_bd_address -offset 0xA0000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_avg/S_AXI_LITE/Reg] -force - assign_bd_address -offset 0xA0010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_buf/S_AXI_LITE/Reg] -force - assign_bd_address -offset 0xA0110000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_gen/S_AXI_LITE/Reg] -force - assign_bd_address -offset 0xA0020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_readout/S_AXI_LITE/Reg] -force - assign_bd_address -offset 0xA0130000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_tproc/S_AXI_LITE/Reg] -force - assign_bd_address -offset 0xA00A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_avg_buffer_0/s_axi/reg0] -force - assign_bd_address -offset 0xA0030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_avg_buffer_1/s_axi/reg0] -force - assign_bd_address -offset 0xA0040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_readout_v2_0/s_axi/reg0] -force - assign_bd_address -offset 0xA0050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_readout_v2_1/s_axi/reg0] -force - assign_bd_address -offset 0xA00B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_0/s_axi/reg0] -force - assign_bd_address -offset 0xA0100000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_1/s_axi/reg0] -force - assign_bd_address -offset 0xA0060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_avg/S_AXI_CTRL/Reg] -force - assign_bd_address -offset 0xA0070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_buf/S_AXI_CTRL/Reg] -force - assign_bd_address -offset 0xA0120000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_gen/S_AXI_CTRL/Reg] -force - assign_bd_address -offset 0xA0080000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_readout/S_AXI_CTRL/Reg] -force - assign_bd_address -offset 0x000400000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_tproc64x32_x8_0/s_axi/reg0] -force - assign_bd_address -offset 0xA0090000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs mr_buffer_et_0/s00_axi/reg0] -force - assign_bd_address -offset 0xA00C0000 -range 0x00040000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs usp_rf_data_converter_0/s_axi/Reg] -force - - # Exclude Address Segments - exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] - exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] - exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] - exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] - exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] - exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] - exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_readout/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] - exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_readout/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] - exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] - exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] - exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] - exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] - - # Perform GUI Layout - regenerate_bd_layout -layout_string { - "ActiveEmotionalView":"Default View", - "Default View_ScaleFactor":"0.527226", - "Default View_TopLeft":"795,1498", - "ExpandedHierarchyInLayout":"", - "guistr":"# # String gsaved with Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:10.0 non-TLS -# -string -flagsOSRD -preplace port adc0_clk -pg 1 -lvl 0 -x -10 -y 2500 -defaultsOSRD -preplace port dac0_clk -pg 1 -lvl 0 -x -10 -y 2520 -defaultsOSRD -preplace port dac2_clk -pg 1 -lvl 0 -x -10 -y 2540 -defaultsOSRD -preplace port sysref_in -pg 1 -lvl 0 -x -10 -y 2600 -defaultsOSRD -preplace port vin0_01 -pg 1 -lvl 0 -x -10 -y 2560 -defaultsOSRD -preplace port vin0_23 -pg 1 -lvl 0 -x -10 -y 2580 -defaultsOSRD -preplace port vout00 -pg 1 -lvl 11 -x 4650 -y 2620 -defaultsOSRD -preplace port vout20 -pg 1 -lvl 11 -x 4650 -y 2640 -defaultsOSRD -preplace port PMOD0_0 -pg 1 -lvl 11 -x 4650 -y 2660 -defaultsOSRD -preplace port PMOD0_1 -pg 1 -lvl 11 -x 4650 -y 2680 -defaultsOSRD -preplace port PMOD0_2 -pg 1 -lvl 11 -x 4650 -y 2700 -defaultsOSRD -preplace port PMOD0_3 -pg 1 -lvl 11 -x 4650 -y 2720 -defaultsOSRD -preplace inst axi_bram_ctrl_0 -pg 1 -lvl 1 -x 180 -y 2010 -defaultsOSRD -preplace inst axi_bram_ctrl_0_bram -pg 1 -lvl 2 -x 650 -y 2250 -defaultsOSRD -preplace inst axi_dma_avg -pg 1 -lvl 10 -x 4430 -y 1960 -defaultsOSRD -preplace inst axi_dma_buf -pg 1 -lvl 10 -x 4430 -y 2140 -defaultsOSRD -resize 320 156 -preplace inst axi_dma_gen -pg 1 -lvl 2 -x 650 -y 1290 -defaultsOSRD -preplace inst axi_dma_readout -pg 1 -lvl 10 -x 4430 -y 2320 -defaultsOSRD -resize 320 156 -preplace inst axi_dma_tproc -pg 1 -lvl 2 -x 650 -y 1520 -defaultsOSRD -preplace inst axi_smc -pg 1 -lvl 5 -x 1820 -y 1040 -defaultsOSRD -preplace inst axis_avg_buffer_0 -pg 1 -lvl 8 -x 3620 -y 1690 -defaultsOSRD -preplace inst axis_avg_buffer_1 -pg 1 -lvl 8 -x 3620 -y 2020 -defaultsOSRD -resize 220 236 -preplace inst axis_cc_avg_0 -pg 1 -lvl 9 -x 4030 -y 1560 -defaultsOSRD -preplace inst axis_cc_avg_1 -pg 1 -lvl 9 -x 4030 -y 1740 -defaultsOSRD -resize 220 156 -preplace inst axis_cc_sg_0 -pg 1 -lvl 3 -x 1120 -y 1620 -defaultsOSRD -preplace inst axis_cc_sg_1 -pg 1 -lvl 3 -x 1120 -y 1840 -defaultsOSRD -resize 220 156 -preplace inst axis_constant_0 -pg 1 -lvl 1 -x 180 -y 1730 -defaultsOSRD -preplace inst axis_constant_1 -pg 1 -lvl 1 -x 180 -y 1850 -defaultsOSRD -resize 220 96 -preplace inst axis_register_slice_0 -pg 1 -lvl 5 -x 1820 -y 2120 -defaultsOSRD -preplace inst axis_register_slice_1 -pg 1 -lvl 5 -x 1820 -y 2440 -defaultsOSRD -preplace inst axis_register_slice_2 -pg 1 -lvl 6 -x 2490 -y 1770 -defaultsOSRD -resize 180 116 -preplace inst axis_register_slice_3 -pg 1 -lvl 6 -x 2490 -y 2010 -defaultsOSRD -resize 180 116 -preplace inst axis_set_reg_0 -pg 1 -lvl 6 -x 2490 -y 2870 -defaultsOSRD -preplace inst axis_signal_gen_v6_0 -pg 1 -lvl 4 -x 1490 -y 2100 -defaultsOSRD -preplace inst axis_signal_gen_v6_1 -pg 1 -lvl 4 -x 1490 -y 2390 -defaultsOSRD -resize 220 236 -preplace inst axis_switch_avg -pg 1 -lvl 9 -x 4030 -y 1980 -defaultsOSRD -resize 240 196 -preplace inst axis_switch_buf -pg 1 -lvl 9 -x 4030 -y 2250 -defaultsOSRD -resize 240 196 -preplace inst axis_switch_gen -pg 1 -lvl 3 -x 1120 -y 1430 -defaultsOSRD -preplace inst axis_switch_readout -pg 1 -lvl 8 -x 3620 -y 2320 -defaultsOSRD -preplace inst axis_tproc64x32_x8_0 -pg 1 -lvl 2 -x 650 -y 1880 -defaultsOSRD -preplace inst clk_adc0_x2 -pg 1 -lvl 6 -x 2490 -y 690 -defaultsOSRD -preplace inst clk_tproc -pg 1 -lvl 6 -x 2490 -y 1410 -defaultsOSRD -resize 160 96 -preplace inst mr_buffer_et_0 -pg 1 -lvl 9 -x 4030 -y 2490 -defaultsOSRD -preplace inst ps8_0_axi_periph -pg 1 -lvl 7 -x 3120 -y 1090 -defaultsOSRD -preplace inst rst_100 -pg 1 -lvl 6 -x 2490 -y 290 -defaultsOSRD -preplace inst rst_adc0 -pg 1 -lvl 6 -x 2490 -y 490 -defaultsOSRD -preplace inst rst_adc0_x2 -pg 1 -lvl 6 -x 2490 -y 840 -defaultsOSRD -resize 320 156 -preplace inst rst_dac0 -pg 1 -lvl 6 -x 2490 -y 1060 -defaultsOSRD -resize 320 156 -preplace inst rst_dac1 -pg 1 -lvl 6 -x 2490 -y 1240 -defaultsOSRD -resize 320 156 -preplace inst rst_tproc -pg 1 -lvl 6 -x 2490 -y 1560 -defaultsOSRD -resize 320 156 -preplace inst usp_rf_data_converter_0 -pg 1 -lvl 6 -x 2490 -y 2560 -defaultsOSRD -preplace inst vect2bits_16_0 -pg 1 -lvl 7 -x 3120 -y 2810 -defaultsOSRD -preplace inst xlconstant_0 -pg 1 -lvl 1 -x 180 -y 2130 -defaultsOSRD -preplace inst xlconstant_1 -pg 1 -lvl 1 -x 180 -y 2240 -defaultsOSRD -resize 140 88 -preplace inst xlconstant_2 -pg 1 -lvl 1 -x 180 -y 2350 -defaultsOSRD -resize 140 88 -preplace inst xlconstant_3 -pg 1 -lvl 1 -x 180 -y 2460 -defaultsOSRD -resize 140 88 -preplace inst zynq_ultra_ps_e_0 -pg 1 -lvl 6 -x 2490 -y 110 -defaultsOSRD -preplace inst axis_readout_v2_0 -pg 1 -lvl 7 -x 3120 -y 1730 -defaultsOSRD -preplace inst axis_readout_v2_1 -pg 1 -lvl 7 -x 3120 -y 2050 -defaultsOSRD -resize 200 176 -preplace netloc axi_bram_ctrl_0_bram_doutb 1 1 1 410 2030n -preplace netloc axis_set_reg_0_dout 1 6 1 2880 2810n -preplace netloc axis_tproc64x32_x8_0_pmem_addr 1 1 2 420 2090 820 -preplace netloc clk_adc0_x2_clk_out1 1 5 4 2140 940 2900 1860 3470 2510 N -preplace netloc clk_adc0_x2_locked 1 5 2 2170 620 2830 -preplace netloc clk_tproc_clk_out1 1 0 9 20 1640 340 1640 850 1730 N 1730 N 1730 2030 1860 2850 1570 3330 1500 3890 -preplace netloc clk_tproc_locked 1 5 2 2180 1340 2810 -preplace netloc rst_adc0_peripheral_aresetn 1 5 2 2180 600 2830 -preplace netloc rst_adc0_x2_peripheral_aresetn 1 5 4 2150 1890 2890 1840 3480 2530 N -preplace netloc rst_dac0_peripheral_aresetn 1 2 5 890 2180 1310 2240 1660J 2210 2070J 960 2830 -preplace netloc rst_dac1_peripheral_aresetn 1 2 5 900 2470 1270 2620 1680J 2600 1970J 2300 2830 -preplace netloc rst_ps8_0_99M_peripheral_aresetn 1 0 10 20 1920 370 1380 860 1310 1300 1110 1630 910 2020 950 2920 1890 3460 1830 3870J 2100 4200 -preplace netloc rst_tproc_peripheral_aresetn 1 0 9 30 1660 350 1660 880 1740 N 1740 NJ 1740 2040 1690 2880 1600 3340J 1520 3760 -preplace netloc usp_rf_data_converter_0_clk_adc0 1 5 2 2160 610 2840 -preplace netloc usp_rf_data_converter_0_clk_dac0 1 2 5 910 2160 1320 2250 1630 2200 2080 2340 2800 -preplace netloc usp_rf_data_converter_0_clk_dac2 1 2 5 920 2450 1320 2630 1660 2360 2050 2310 2830 -preplace netloc vect2bits_16_0_dout0 1 7 4 3270 2670 NJ 2670 4220J 2660 NJ -preplace netloc vect2bits_16_0_dout1 1 7 4 N 2680 NJ 2680 NJ 2680 NJ -preplace netloc vect2bits_16_0_dout2 1 7 4 N 2700 NJ 2700 NJ 2700 NJ -preplace netloc vect2bits_16_0_dout3 1 7 4 N 2720 NJ 2720 NJ 2720 NJ -preplace netloc vect2bits_16_0_dout4 1 7 1 3410 1690n -preplace netloc vect2bits_16_0_dout5 1 7 1 3450 2020n -preplace netloc vect2bits_16_0_dout6 1 7 2 3460 2450 NJ -preplace netloc xlconstant_0_dout 1 1 1 320 2130n -preplace netloc xlconstant_1_dout 1 1 1 360 2010n -preplace netloc xlconstant_2_dout 1 1 1 330 2310n -preplace netloc xlconstant_3_dout 1 1 1 350 2330n -preplace netloc zynq_ultra_ps_e_0_pl_clk0 1 0 10 30 1930 330 1390 890 1320 1290 1090 1620 900 2100 1900 2940 1580 3440 1510 3790J 2110 4230 -preplace netloc zynq_ultra_ps_e_0_pl_resetn0 1 5 2 2150 590 2840 -preplace netloc axis_constant_1_m_axis 1 1 1 320 1810n -preplace netloc ps8_0_axi_periph_M12_AXI 1 7 1 3400 1150n -preplace netloc axis_tproc64x32_x8_0_m8_axis 1 2 4 NJ 1950 NJ 1950 NJ 1950 1960 -preplace netloc axis_avg_buffer_1_m1_axis 1 8 1 3760 2020n -preplace netloc ps8_0_axi_periph_M04_AXI 1 6 2 2970 610 3270J -preplace netloc axis_register_slice_6_m_axis 1 5 1 1990 2120n -preplace netloc axis_cc_avg_1_M_AXIS 1 1 9 390 2550 N 2550 N 2550 1640J 2350 2010 2330 NJ 2330 3370J 2440 3780J 2640 4170 -preplace netloc axi_dma_gen_M_AXIS_MM2S 1 2 1 880 1280n -preplace netloc dac0_clk_1 1 0 6 20 2560 N 2560 N 2560 N 2560 N 2560 2110 -preplace netloc ps8_0_axi_periph_M08_AXI 1 7 1 3380 1070n -preplace netloc axi_dma_buf_M_AXI_S2MM 1 4 7 1660J 1180 2090 1670 2860J 1590 3350J 1550 3830J 1840 NJ 1840 4630 -preplace netloc ps8_0_axi_periph_M00_AXI 1 7 3 3480 1430 3890 1440 4230J -preplace netloc ps8_0_axi_periph_M14_AXI 1 3 5 1330 -10 NJ -10 NJ -10 NJ -10 3310 -preplace netloc axis_avg_buffer_1_m0_axis 1 8 1 3840 1940n -preplace netloc ps8_0_axi_periph_M09_AXI 1 1 7 400 2580 N 2580 N 2580 1630J 2330 1980 2160 NJ 2160 3320J -preplace netloc axis_signal_gen_v6_0_m_axis 1 4 1 N 2100 -preplace netloc ps8_0_axi_periph_M13_AXI 1 3 5 1340 1870 NJ 1870 NJ 1870 NJ 1870 3280 -preplace netloc axis_register_slice_4_m_axis 1 5 1 NJ 2440 -preplace netloc axis_readout_v2_0_m0_axis 1 7 1 3350 1720n -preplace netloc ps8_0_axi_periph_M11_AXI 1 5 3 2170 1880 NJ 1880 3300J -preplace netloc dac2_clk_1 1 0 6 N 2540 360 2570 N 2570 N 2570 1650 2520 2090 -preplace netloc axi_dma_gen_M_AXI_MM2S 1 2 3 830 1030 N 1030 N -preplace netloc axis_switch_buf_M00_AXIS 1 9 1 4190 2120n -preplace netloc vin0_01_1 1 0 6 10 2570 340 2610 N 2610 N 2610 N 2610 2120 -preplace netloc ps8_0_axi_periph_M02_AXI 1 7 3 3460 1460 N 1460 4210J -preplace netloc mr_buffer_et_0_m00_axis 1 9 1 4190 2300n -preplace netloc axis_signal_gen_v6_1_m_axis 1 4 1 1650 2390n -preplace netloc axi_dma_readout_M_AXI_S2MM 1 4 7 1680J 1190 2040 1680 2910J 1620 3360J 1530 3850J 1860 NJ 1860 4620 -preplace netloc axi_smc_M00_AXI 1 5 1 1960 70n -preplace netloc zynq_ultra_ps_e_0_M_AXI_HPM0_FPD 1 6 1 2950J 80n -preplace netloc axis_switch_0_M00_AXIS 1 8 1 3760 2320n -preplace netloc ps8_0_axi_periph_M10_AXI 1 7 2 3410 1490 3810 -preplace netloc axis_avg_buffer_0_m1_axis 1 8 1 3770 1690n -preplace netloc axi_dma_tproc_M_AXI_S2MM 1 2 3 850 1070 NJ 1070 N -preplace netloc axis_readout_v2_1_m1_axis 1 7 1 3430 1940n -preplace netloc axis_tproc64x32_x8_0_m2_axis 1 2 1 870 1800n -preplace netloc ps8_0_axi_periph_M15_AXI 1 1 7 400 390 N 390 N 390 NJ 390 NJ 390 NJ 390 3290 -preplace netloc axis_tproc64x32_x8_0_m1_axis 1 2 1 860 1580n -preplace netloc axis_switch_gen_M00_AXIS 1 3 1 1320 1420n -preplace netloc ps8_0_axi_periph_M05_AXI 1 6 2 2960 600 3280J -preplace netloc ps8_0_axi_periph_M06_AXI 1 7 2 3450 1470 3880 -preplace netloc ps8_0_axi_periph_M17_AXI 1 1 7 390 10 NJ 10 NJ 10 NJ 10 NJ 10 NJ 10 3330 -preplace netloc ps8_0_axi_periph_M16_AXI 1 2 6 910 0 N 0 N 0 NJ 0 NJ 0 3340 -preplace netloc axis_readout_v2_0_m1_axis 1 7 1 3390 1610n -preplace netloc axi_dma_avg_M_AXI_S2MM 1 4 7 1640 1170 2120 1660 2870 1610 3370 1540 3840 1850 N 1850 4610 -preplace netloc usp_rf_data_converter_0_m00_axis 1 5 2 2160 1920 2820 -preplace netloc axis_avg_buffer_1_m2_axis 1 8 1 3820 1700n -preplace netloc axis_cc_sg_0_M_AXIS 1 3 1 1280 1620n -preplace netloc usp_rf_data_converter_0_m02_axis 1 5 2 2180 1930 2810 -preplace netloc ps8_0_axi_periph_M18_AXI 1 0 8 10 1650 NJ 1650 840J 1720 NJ 1720 NJ 1720 1960J 1850 NJ 1850 3270 -preplace netloc axis_constant_0_m_axis 1 1 1 360 1730n -preplace netloc axi_bram_ctrl_0_BRAM_PORTA 1 1 1 330 2010n -preplace netloc axis_tproc64x32_x8_0_m0_axis 1 1 2 400 1400 830 -preplace netloc axis_register_slice_2_M_AXIS 1 6 1 2930 1680n -preplace netloc axi_dma_tproc_M_AXI_MM2S 1 2 3 840 1050 NJ 1050 N -preplace netloc axis_cc_sg_1_M_AXIS 1 3 1 1260 1840n -preplace netloc vin0_23_1 1 0 6 N 2580 330 2600 N 2600 N 2600 1670 2540 N -preplace netloc axis_readout_v2_1_m0_axis 1 7 1 3330 2040n -preplace netloc axis_register_slice_3_M_AXIS 1 6 1 2950 2000n -preplace netloc adc0_clk_1 1 0 6 30 2530 N 2530 N 2530 N 2530 N 2530 2060 -preplace netloc axis_switch_gen_M01_AXIS 1 3 1 1270 1440n -preplace netloc usp_rf_data_converter_0_vout20 1 6 5 N 2550 N 2550 3760 2650 4220 2640 N -preplace netloc sysref_in_1 1 0 6 NJ 2600 320J 2590 NJ 2590 NJ 2590 NJ 2590 2130 -preplace netloc ps8_0_axi_periph_M07_AXI 1 7 2 3440 1480 3860 -preplace netloc axis_avg_buffer_0_m0_axis 1 8 1 3800 1670n -preplace netloc axis_switch_avg_M00_AXIS 1 9 1 4200 1940n -preplace netloc axis_cc_avg_0_M_AXIS 1 1 9 380 2540 N 2540 N 2540 1620J 2340 2000 2320 NJ 2320 3310J 2660 NJ 2660 4180 -preplace netloc ps8_0_axi_periph_M01_AXI 1 7 3 3470 1450 N 1450 4220J -preplace netloc usp_rf_data_converter_0_vout00 1 6 5 N 2530 3270 2540 3770 2630 4210 2620 N -preplace netloc ps8_0_axi_periph_M03_AXI 1 7 1 3420 970n -preplace netloc axis_avg_buffer_0_m2_axis 1 8 1 3780 1520n -preplace netloc axi_dma_tproc_M_AXIS_MM2S 1 1 2 400 1670 820 -levelinfo -pg 1 -10 180 650 1120 1490 1820 2490 3120 3620 4030 4430 4650 -pagesize -pg 1 -db -bbox -sgen -120 -20 4770 3020 -" -} - - # Restore current instance - current_bd_instance $oldCurInst - - validate_bd_design - save_bd_design -} -# End of create_root_design() - - -################################################################## -# MAIN FLOW -################################################################## - -create_root_design "" - - diff --git a/qick/firmware/board_files/rfsoc4x2/1.0/LICENSE b/qick/firmware/board_files/rfsoc4x2/1.0/LICENSE deleted file mode 100644 index 1097dfe..0000000 --- a/qick/firmware/board_files/rfsoc4x2/1.0/LICENSE +++ /dev/null @@ -1,15 +0,0 @@ -######################################################################### -Copyright (C) 2019, Xilinx Inc - All rights reserved - -Licensed under the Apache License, Version 2.0 (the "License"). You may -not use this file except in compliance with the License. A copy of the -License is located at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -License for the specific language governing permissions and limitations -under the License. -######################################################################### diff --git a/qick/firmware/board_files/rfsoc4x2/1.0/board.xml b/qick/firmware/board_files/rfsoc4x2/1.0/board.xml deleted file mode 100644 index f12184b..0000000 --- a/qick/firmware/board_files/rfsoc4x2/1.0/board.xml +++ /dev/null @@ -1,328 +0,0 @@ - - - - - - RFSoC 4x2 Board File Image - - - - Rev 1.0 - - 1.0 - Zynq UltraScale+ RFSoC 4x2 Development Board - - - - - - - - - - - FPGA part on the board - - - - - - - - - - - - - - - - - - - - - - - - - 4-position user DIP Switch - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CPU Reset Push Button, Active Low - - - DIP Switches 3 to 0 - - - LEDs, 3 to 0, Active Low - - - Push Buttons, Active Low - - - RGBLED0, Active Low - - - RGBLED1, Active Low - - - Pmod0 Connector - - - Pmod1 Connector - - - Pmod01 Connector - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/qick/firmware/board_files/rfsoc4x2/1.0/part0_pins.xml b/qick/firmware/board_files/rfsoc4x2/1.0/part0_pins.xml deleted file mode 100644 index a92f689..0000000 --- a/qick/firmware/board_files/rfsoc4x2/1.0/part0_pins.xml +++ /dev/null @@ -1,57 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/qick/firmware/board_files/rfsoc4x2/1.0/preset.xml b/qick/firmware/board_files/rfsoc4x2/1.0/preset.xml deleted file mode 100644 index 8012c79..0000000 --- a/qick/firmware/board_files/rfsoc4x2/1.0/preset.xml +++ /dev/null @@ -1,573 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/qick/firmware/board_files/rfsoc4x2/1.0/rfsoc4x2_board.png b/qick/firmware/board_files/rfsoc4x2/1.0/rfsoc4x2_board.png deleted file mode 100644 index 4005891..0000000 Binary files a/qick/firmware/board_files/rfsoc4x2/1.0/rfsoc4x2_board.png and /dev/null differ diff --git a/qick/firmware/board_files/rfsoc4x2/1.0/xitem.json b/qick/firmware/board_files/rfsoc4x2/1.0/xitem.json deleted file mode 100644 index befb202..0000000 --- a/qick/firmware/board_files/rfsoc4x2/1.0/xitem.json +++ /dev/null @@ -1,37 +0,0 @@ -{ - "config": { - "items": [ - { - "infra": { - "name": "rfsoc4x2", - "display": "Zynq UltraScale+ RFSoC 4x2 Development Board", - "revision": "1.0", - "description": "Zynq UltraScale+ RFSoC 4x2 Development Board", - "company": "realdigital.org", - "company_display": "Real Digital", - "author": "rhoover", - "contributors": [ - { - "group": "RealDigital", - "url": "https://www.realdigital.org/" - "group": "Xilinx", - "url": "https://www.xilinx.com/" - } - ], - "category": "Single Part", - "website": "https://www.rfsoc-pynq.io", - "logo": "rfsoc4x2_board.png", - "search-keywords": [ - "rfsoc4x2", - "realdigital.org", - "xilinx.com", - "board", - "Single Part" - ] - } - } - ] - }, - "_major": 1, - "_minor": 0 -} diff --git a/qick/firmware/hdl/lo_spi_mux.vhd b/qick/firmware/hdl/lo_spi_mux.vhd deleted file mode 100644 index da514c5..0000000 --- a/qick/firmware/hdl/lo_spi_mux.vhd +++ /dev/null @@ -1,55 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11/16/2017 02:49:57 PM --- Design Name: --- Module Name: lo_spi_mux - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity lo_spi_mux is - Port ( ss_in : in STD_LOGIC_VECTOR (1 downto 0); - ss0_out : out STD_LOGIC; - ss1_out : out STD_LOGIC; - sdo0_in : in STD_LOGIC; - sdo1_in : in STD_LOGIC; - sdo_out : out STD_LOGIC); -end lo_spi_mux; - -architecture Behavioral of lo_spi_mux is - -begin - --- Assign ss outputs. -ss0_out <= ss_in(0); -ss1_out <= ss_in(1); - -sdo_out <= sdo0_in when (ss_in(1) = '1' and ss_in(0) = '0') else - sdo1_in when (ss_in(1) = '0' and ss_in(0) = '1') else - '1'; - -end Behavioral; diff --git a/qick/firmware/hdl/lo_spi_mux_v2.vhd b/qick/firmware/hdl/lo_spi_mux_v2.vhd deleted file mode 100644 index 3da62c9..0000000 --- a/qick/firmware/hdl/lo_spi_mux_v2.vhd +++ /dev/null @@ -1,59 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11/16/2017 02:49:57 PM --- Design Name: --- Module Name: lo_spi_mux - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity lo_spi_mux_v2 is - Port ( ss_in : in STD_LOGIC_VECTOR (2 downto 0); - ss0_out : out STD_LOGIC; - ss1_out : out STD_LOGIC; - ss2_out : out STD_LOGIC; - sdo0_in : in STD_LOGIC; - sdo1_in : in STD_LOGIC; - sdo2_in : in STD_LOGIC; - sdo_out : out STD_LOGIC); -end lo_spi_mux_v2; - -architecture Behavioral of lo_spi_mux_v2 is - -begin - --- Assign ss outputs. -ss0_out <= ss_in(0); -ss1_out <= ss_in(1); -ss2_out <= ss_in(2); - -sdo_out <= sdo0_in when (ss_in(2) = '1' and ss_in(1) = '1' and ss_in(0) = '0') else - sdo1_in when (ss_in(2) = '1' and ss_in(1) = '0' and ss_in(0) = '1') else - sdo2_in when (ss_in(2) = '0' and ss_in(1) = '1' and ss_in(0) = '1') else - '1'; - -end Behavioral; diff --git a/qick/firmware/hdl/vect2bits_16.v b/qick/firmware/hdl/vect2bits_16.v deleted file mode 100644 index 4b9a9d3..0000000 --- a/qick/firmware/hdl/vect2bits_16.v +++ /dev/null @@ -1,59 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 12/14/2020 04:56:49 PM -// Design Name: -// Module Name: vect2bits_16 -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module vect2bits_16( - input [159:0] din, - output dout0, - output dout1, - output dout2, - output dout3, - output dout4, - output dout5, - output dout6, - output dout7, - output dout8, - output dout9, - output dout10, - output dout11, - output dout12, - output dout13, - output dout14, - output dout15 - ); - - assign dout0 = din[0]; - assign dout1 = din[1]; - assign dout2 = din[2]; - assign dout3 = din[3]; - assign dout4 = din[4]; - assign dout5 = din[5]; - assign dout6 = din[6]; - assign dout7 = din[7]; - assign dout8 = din[8]; - assign dout9 = din[9]; - assign dout10 = din[10]; - assign dout11 = din[11]; - assign dout12 = din[12]; - assign dout13 = din[13]; - assign dout14 = din[14]; - assign dout15 = din[15]; -endmodule diff --git a/qick/firmware/ip/README.md b/qick/firmware/ip/README.md deleted file mode 100644 index 523b577..0000000 --- a/qick/firmware/ip/README.md +++ /dev/null @@ -1,2 +0,0 @@ -# ip -Various ip blocks for ASIC/FPGA. diff --git a/qick/firmware/ip/axis_avg_buffer/component.xml b/qick/firmware/ip/axis_avg_buffer/component.xml deleted file mode 100644 index ef0f4f9..0000000 --- a/qick/firmware/ip/axis_avg_buffer/component.xml +++ /dev/null @@ -1,1473 +0,0 @@ - - - user.org - user - axis_avg_buffer - 1.0 - - - m0_axis - - - - - - - TDATA - - - m0_axis_tdata - - - - - TLAST - - - m0_axis_tlast - - - - - TVALID - - - m0_axis_tvalid - - - - - TREADY - - - m0_axis_tready - - - - - - m1_axis - - - - - - - TDATA - - - m1_axis_tdata - - - - - TLAST - - - m1_axis_tlast - - - - - TVALID - - - m1_axis_tvalid - - - - - TREADY - - - m1_axis_tready - - - - - - s_axis - - - - - - - TDATA - - - s_axis_tdata - - - - - TVALID - - - s_axis_tvalid - - - - - TREADY - - - s_axis_tready - - - - - - s_axi - - - - - - - - - AWADDR - - - s_axi_awaddr - - - - - AWPROT - - - s_axi_awprot - - - - - AWVALID - - - s_axi_awvalid - - - - - AWREADY - - - s_axi_awready - - - - - WDATA - - - s_axi_wdata - - - - - WSTRB - - - s_axi_wstrb - - - - - WVALID - - - s_axi_wvalid - - - - - WREADY - - - s_axi_wready - - - - - BRESP - - - s_axi_bresp - - - - - BVALID - - - s_axi_bvalid - - - - - BREADY - - - s_axi_bready - - - - - ARADDR - - - s_axi_araddr - - - - - ARPROT - - - s_axi_arprot - - - - - ARVALID - - - s_axi_arvalid - - - - - ARREADY - - - s_axi_arready - - - - - RDATA - - - s_axi_rdata - - - - - RRESP - - - s_axi_rresp - - - - - RVALID - - - s_axi_rvalid - - - - - RREADY - - - s_axi_rready - - - - - - s_axi_aclk - - - - - - - CLK - - - s_axi_aclk - - - - - - ASSOCIATED_BUSIF - s_axi - - - ASSOCIATED_RESET - s_axi_aresetn - - - - - s_axi_aresetn - - - - - - - RST - - - s_axi_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - s_axis_aclk - - - - - - - CLK - - - s_axis_aclk - - - - - - ASSOCIATED_BUSIF - s_axis - - - ASSOCIATED_RESET - s_axis_aresetn - - - - - s_axis_aresetn - - - - - - - RST - - - s_axis_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - m_axis_aclk - - - - - - - CLK - - - m_axis_aclk - - - - - - ASSOCIATED_RESET - m_axis_aresetn - - - ASSOCIATED_BUSIF - m0_axis:m1_axis:m2_axis - - - - - m_axis_aresetn - - - - - - - RST - - - m_axis_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - m2_axis - - - - - - - TDATA - - - m2_axis_tdata - - - - - TVALID - - - m2_axis_tvalid - - - - - TREADY - - - m2_axis_tready - - - - - - - - s_axi - - reg0 - 0 - 64 - 32 - register - - - - - - - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis - Verilog - axis_avg_buffer - - xilinx_anylanguagesynthesis_view_fileset - - - - viewChecksum - 7ebfc17e - - - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - Verilog - axis_avg_buffer - - xilinx_anylanguagebehavioralsimulation_view_fileset - - - - viewChecksum - 7ebfc17e - - - - - xilinx_xpgui - UI Layout - :vivado.xilinx.com:xgui.ui - - xilinx_xpgui_view_fileset - - - - viewChecksum - be680c07 - - - - - - - s_axi_aclk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_aresetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_awaddr - - in - - 5 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_awprot - - in - - 2 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_awvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_awready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_wdata - - in - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_wstrb - - in - - 3 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 1 - - - - - s_axi_wvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_wready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_bresp - - out - - 1 - 0 - - - - std_logic_vector - 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azynq - spartan7 - aspartan7 - virtexu - zynquplus - virtexuplus - virtexuplusHBM - kintexuplus - kintexu - - - /UserIP - - AXIS Average + Buffer - package_project - 6 - 2021-06-15T19:18:03Z - - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - 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/home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/v19.1/ip/axis_avg_buffer - /home/lstefana/qsystem_2/ip/axis_avg_buffer - /home/lstefana/qsystem_2/ip/axis_avg_buffer - /home/lstefana/qsystem_2/ip/axis_avg_buffer - /home/lstefana/qsystem_2/ip/axis_avg_buffer - /home/lstefana/qsystem_2/ip/axis_avg_buffer - /home/lstefana/qsystem_2/ip/axis_avg_buffer - /home/lstefana/qsystem_2/ip/axis_avg_buffer - /home/lstefana/qsystem_2/ip/axis_avg_buffer - /home/lstefana/qsystem_2/ip/axis_avg_buffer - /home/lstefana/qsystem_2/ip/axis_avg_buffer - /home/lstefana/qsystem_2/ip/axis_avg_buffer - /home/lstefana/qsystem_2/ip/axis_avg_buffer - /home/lstefana/qsystem_2/ip/axis_avg_buffer - /home/lstefana/qsystem_2/ip/axis_avg_buffer - - - - 2019.1 - - - - - - - - - diff --git a/qick/firmware/ip/axis_avg_buffer/src/avg.sv b/qick/firmware/ip/axis_avg_buffer/src/avg.sv deleted file mode 100644 index 6772e9e..0000000 --- a/qick/firmware/ip/axis_avg_buffer/src/avg.sv +++ /dev/null @@ -1,224 +0,0 @@ -// Data is I,Q. -// I: lower B bits. -// Q: upper B bits. -module avg ( - // Reset and clock. - rstn , - clk , - - // Trigger input. - trigger_i , - - // Data input. - din_i , - - // Memory interface. - mem_we_o , - mem_addr_o , - mem_di_o , - - // Registers. - START_REG , - ADDR_REG , - LEN_REG - ); - -//////////////// -// Parameters // -//////////////// -// Memory depth. -parameter N = 10; - -// Number of bits. -parameter B = 16; - -/////////// -// Ports // -/////////// -input rstn; -input clk; - -input trigger_i; - -input [2*B-1:0] din_i; - -output mem_we_o; -output [N-1:0] mem_addr_o; -output [4*B-1:0] mem_di_o; - -input START_REG; -input [N-1:0] ADDR_REG; -input [31:0] LEN_REG; - -////////////////////// -// Internal signals // -////////////////////// -// States. -typedef enum { INIT_ST , - START_ST , - TRIGGER_ST , - AVG_ST , - QOUT_ST , - WRITE_MEM_ST , - WAIT_TRIGGER_ST - } state_t; - -// State register. -(* fsm_encoding = "one_hot" *) state_t state; - -reg start_state; -reg trigger_state; -reg avg_state; -reg qout_state; -reg write_mem_state; - -// Counter. -reg [31:0] cnt; - -// Registers. -reg [N-1:0] addr_r; -reg [31:0] len_r; - -// Input data. -wire signed [B-1:0] din_ii, din_qq; - -// Accumulators. -reg signed [2*B-1:0] acc_i, acc_q; - -// Quantized outputs. -reg signed [2*B-1:0] out_i_r, out_q_r; - - -////////////////// -// Architecture // -////////////////// - -assign din_ii = din_i[B-1:0]; -assign din_qq = din_i[2*B-1:B]; - -// Registers. -always @(posedge clk) begin - if (~rstn) begin - // State register. - state <= INIT_ST; - - // Counter. - cnt <= 0; - - // Registers. - addr_r <= 0; - len_r <= 0; - - // Accumulators. - acc_i <= 0; - acc_q <= 0; - - // Quantized outputs. - out_i_r <= 0; - out_q_r <= 0; - end - else begin - // State register. - case (state) - INIT_ST: - state <= START_ST; - - START_ST: - if ( START_REG == 1'b1) - state <= TRIGGER_ST; - - TRIGGER_ST: - if ( START_REG == 1'b0 ) - state <= START_ST; - else if ( trigger_i == 1'b1 ) - state <= AVG_ST; - - AVG_ST: - if ( cnt == len_r-1 ) - state <= QOUT_ST; - - QOUT_ST: - state <= WRITE_MEM_ST; - - WRITE_MEM_ST: - state <= WAIT_TRIGGER_ST; - - WAIT_TRIGGER_ST: - if ( START_REG == 1'b0 ) - state <= START_ST; - else if ( trigger_i == 1'b0 ) begin - state <= TRIGGER_ST; - end - endcase - - // Counter. - if ( avg_state == 1'b1 ) - cnt <= cnt + 1; - else - cnt <= 0; - - // Registers. - if ( start_state == 1'b1 ) begin - addr_r <= ADDR_REG; - len_r <= LEN_REG; - end - else if ( write_mem_state == 1'b1 ) begin - addr_r <= addr_r + 1; - end - - // Accumulators. - if ( trigger_state == 1'b1) begin - acc_i <= 0; - acc_q <= 0; - end - else if ( avg_state == 1'b1 ) begin - acc_i <= acc_i + din_ii; - acc_q <= acc_q + din_qq; - end - - // Quantized outputs. - if ( qout_state == 1'b1) begin - out_i_r <= acc_i; - out_q_r <= acc_q; - end - end -end - -// FSM outputs. -always_comb begin - // Default. - start_state = 0; - trigger_state = 0; - avg_state = 0; - qout_state = 0; - write_mem_state = 0; - - case (state) - //INIT_ST: - - START_ST: - start_state = 1'b1; - - TRIGGER_ST: - trigger_state = 1'b1; - - AVG_ST: - avg_state = 1'b1; - - QOUT_ST: - qout_state = 1'b1; - - WRITE_MEM_ST: - write_mem_state = 1'b1; - - //WAIT_TRIGGER_ST: - endcase -end - -// Assign outputs. -assign mem_we_o = write_mem_state; -assign mem_addr_o = addr_r; -assign mem_di_o = {out_q_r,out_i_r}; - -endmodule - diff --git a/qick/firmware/ip/axis_avg_buffer/src/avg_buffer.v b/qick/firmware/ip/axis_avg_buffer/src/avg_buffer.v deleted file mode 100644 index 1373d0a..0000000 --- a/qick/firmware/ip/axis_avg_buffer/src/avg_buffer.v +++ /dev/null @@ -1,208 +0,0 @@ -// Data is I,Q. -// I: lower B bits. -// Q: upper B bits. -module avg_buffer ( - // Reset and clock for s. - s_axis_aclk , - s_axis_aresetn , - - // Trigger input. - trigger , - - // AXIS Slave for input data. - s_axis_tvalid , - s_axis_tready , - s_axis_tdata , - - // Reset and clock for m0, m1 and m2. - m_axis_aclk , - m_axis_aresetn , - - // AXIS Master for averaged output. - m0_axis_tvalid , - m0_axis_tready , - m0_axis_tdata , - m0_axis_tlast , - - // AXIS Master for raw output. - m1_axis_tvalid , - m1_axis_tready , - m1_axis_tdata , - m1_axis_tlast , - - // AXIS Master for register output. - m2_axis_tvalid , - m2_axis_tready , - m2_axis_tdata , - - // Registers. - AVG_START_REG , - AVG_ADDR_REG , - AVG_LEN_REG , - AVG_DR_START_REG , - AVG_DR_ADDR_REG , - AVG_DR_LEN_REG , - BUF_START_REG , - BUF_ADDR_REG , - BUF_LEN_REG , - BUF_DR_START_REG , - BUF_DR_ADDR_REG , - BUF_DR_LEN_REG - ); - -//////////////// -// Parameters // -//////////////// -// Memory depth. -parameter N_AVG = 10; -parameter N_BUF = 10; - -// Number of bits. -parameter B = 16; - -/////////// -// Ports // -/////////// -input s_axis_aclk; -input s_axis_aresetn; - -input trigger; - -input s_axis_tvalid; -output s_axis_tready; -input [2*B-1:0] s_axis_tdata; - -input m_axis_aclk; -input m_axis_aresetn; - -output m0_axis_tvalid; -input m0_axis_tready; -output [4*B-1:0] m0_axis_tdata; -output m0_axis_tlast; - -output m1_axis_tvalid; -input m1_axis_tready; -output [2*B-1:0] m1_axis_tdata; -output m1_axis_tlast; - -output m2_axis_tvalid; -input m2_axis_tready; -output [4*B-1:0] m2_axis_tdata; - -input AVG_START_REG; -input [N_AVG-1:0] AVG_ADDR_REG; -input [31:0] AVG_LEN_REG; -input AVG_DR_START_REG; -input [N_AVG-1:0] AVG_DR_ADDR_REG; -input [N_AVG-1:0] AVG_DR_LEN_REG; -input BUF_START_REG; -input [N_BUF-1:0] BUF_ADDR_REG; -input [N_BUF-1:0] BUF_LEN_REG; -input BUF_DR_START_REG; -input [N_BUF-1:0] BUF_DR_ADDR_REG; -input [N_BUF-1:0] BUF_DR_LEN_REG; - -////////////////////// -// Internal signals // -////////////////////// - -wire trigger_resync; - -////////////////// -// Architecture // -////////////////// - -// trigger_resync -synchronizer_n - #( - .N (2) - ) - trigger_resync_i ( - .rstn (s_axis_aresetn ), - .clk (s_axis_aclk ), - .data_in (trigger ), - .data_out (trigger_resync ) - ); - -// Average block. -avg_top - #( - .N (N_AVG ), - .B (B ) - ) - avg_top_i - ( - // Reset and clock. - .rstn (s_axis_aresetn ), - .clk (s_axis_aclk ), - - // Trigger input. - .trigger_i (trigger_resync ), - - // Data input. - .din_i (s_axis_tdata ), - - // Reset and clock for M_AXIS_* - .m_axis_aclk (m_axis_aclk ), - .m_axis_aresetn (m_axis_aresetn ), - - // AXIS Master for output. - .m0_axis_tvalid (m0_axis_tvalid ), - .m0_axis_tready (m0_axis_tready ), - .m0_axis_tdata (m0_axis_tdata ), - .m0_axis_tlast (m0_axis_tlast ), - - // AXIS Master for register output. - .m1_axis_tvalid (m2_axis_tvalid ), - .m1_axis_tready (m2_axis_tready ), - .m1_axis_tdata (m2_axis_tdata ), - - // Registers. - .AVG_START_REG (AVG_START_REG ), - .AVG_ADDR_REG (AVG_ADDR_REG ), - .AVG_LEN_REG (AVG_LEN_REG ), - .DR_START_REG (AVG_DR_START_REG ), - .DR_ADDR_REG (AVG_DR_ADDR_REG ), - .DR_LEN_REG (AVG_DR_LEN_REG ) - ); - -// Buffer block. -buffer_top - #( - .N (N_BUF ), - .B (B ) - ) - buffer_top_i - ( - // Reset and clock. - .rstn (s_axis_aresetn ), - .clk (s_axis_aclk ), - - // Trigger input. - .trigger_i (trigger_resync ), - - // Data input. - .din_i (s_axis_tdata ), - - // AXIS Master for output. - .m_axis_aclk (m_axis_aclk ), - .m_axis_aresetn (m_axis_aresetn ), - .m_axis_tvalid (m1_axis_tvalid ), - .m_axis_tready (m1_axis_tready ), - .m_axis_tdata (m1_axis_tdata ), - .m_axis_tlast (m1_axis_tlast ), - - // Registers. - .BUF_START_REG (BUF_START_REG ), - .BUF_ADDR_REG (BUF_ADDR_REG ), - .BUF_LEN_REG (BUF_LEN_REG ), - .DR_START_REG (BUF_DR_START_REG ), - .DR_ADDR_REG (BUF_DR_ADDR_REG ), - .DR_LEN_REG (BUF_DR_LEN_REG ) - ); - -// Assign outputs. -assign s_axis_tready = 1'b1; - -endmodule - diff --git a/qick/firmware/ip/axis_avg_buffer/src/avg_top.v b/qick/firmware/ip/axis_avg_buffer/src/avg_top.v deleted file mode 100644 index a5c22c4..0000000 --- a/qick/firmware/ip/axis_avg_buffer/src/avg_top.v +++ /dev/null @@ -1,229 +0,0 @@ -module avg_top ( - // Reset and clock. - rstn , - clk , - - // Trigger input. - trigger_i , - - // Data input. - din_i , - - // Reset and clock for M_AXIS_* - m_axis_aclk , - m_axis_aresetn , - - // AXIS Master for output. - m0_axis_tvalid , - m0_axis_tready , - m0_axis_tdata , - m0_axis_tlast , - - // AXIS Master for register output. - m1_axis_tvalid , - m1_axis_tready , - m1_axis_tdata , - - // Registers. - AVG_START_REG , - AVG_ADDR_REG , - AVG_LEN_REG , - DR_START_REG , - DR_ADDR_REG , - DR_LEN_REG - ); - -//////////////// -// Parameters // -//////////////// -// Memory depth. -parameter N = 10; - -// Number of bits. -parameter B = 16; - -/////////// -// Ports // -/////////// -input rstn; -input clk; - -input trigger_i; - -input [2*B-1:0] din_i; - -input m_axis_aclk; -input m_axis_aresetn; - -output m0_axis_tvalid; -input m0_axis_tready; -output [4*B-1:0] m0_axis_tdata; -output m0_axis_tlast; - -output m1_axis_tvalid; -input m1_axis_tready; -output [4*B-1:0] m1_axis_tdata; - -input AVG_START_REG; -input [N-1:0] AVG_ADDR_REG; -input [31:0] AVG_LEN_REG; -input DR_START_REG; -input [N-1:0] DR_ADDR_REG; -input [N-1:0] DR_LEN_REG; - -////////////////////// -// Internal signals // -////////////////////// -wire mem_we_int; -wire [N-1:0] mem_addra_int, mem_addrb_int; -wire [4*B-1:0] mem_di_int, mem_do_int; - -wire AVG_START_REG_resync; -wire DR_START_REG_resync; - -wire fifo_empty; - -////////////////// -// Architecture // -////////////////// - -// AVG_START_REG_resync -synchronizer_n - #( - .N (2) - ) - AVG_START_REG_resync_i ( - .rstn (rstn ), - .clk (clk ), - .data_in (AVG_START_REG ), - .data_out (AVG_START_REG_resync ) - ); - -// DR_START_REG_resync -synchronizer_n - #( - .N (2) - ) - DR_START_REG_resync_i ( - .rstn (m_axis_aresetn ), - .clk (m_axis_aclk ), - .data_in (DR_START_REG ), - .data_out (DR_START_REG_resync ) - ); - -// Average block. -avg - #( - .N (N), - .B (B) - ) - avg_i - ( - // Reset and clock. - .rstn (rstn ), - .clk (clk ), - - // Trigger input. - .trigger_i (trigger_i ), - - // Data input. - .din_i (din_i ), - - // Memory interface. - .mem_we_o (mem_we_int ), - .mem_addr_o (mem_addra_int ), - .mem_di_o (mem_di_int ), - - // Registers. - .START_REG (AVG_START_REG_resync ), - .ADDR_REG (AVG_ADDR_REG ), - .LEN_REG (AVG_LEN_REG ) - ); - -// Dual port BRAM. -bram_dp - #( - .N (N ), - .B (4*B) - ) - bram_i - ( - .clka (clk ), - .clkb (m_axis_aclk ), - .ena (1'b1 ), - .enb (1'b1 ), - .wea (mem_we_int ), - .web (1'b0 ), - .addra (mem_addra_int ), - .addrb (mem_addrb_int ), - .dia (mem_di_int ), - .dib ({4*B{1'b0}} ), - .doa ( ), - .dob (mem_do_int ) - ); - -// Data reader. -data_reader - #( - .N (N ), - .B (4*B) - ) - data_reader_i - ( - // Reset and clock. - .rstn (m_axis_aresetn ), - .clk (m_axis_aclk ), - - // Memory I/F. - .mem_en ( ), - .mem_we ( ), - .mem_addr (mem_addrb_int ), - .mem_dout (mem_do_int ), - - // Data out. - .dout (m0_axis_tdata ), - .dready (m0_axis_tready ), - .dvalid (m0_axis_tvalid ), - .dlast (m0_axis_tlast ), - - // Registers. - .START_REG (DR_START_REG_resync ), - .ADDR_REG (DR_ADDR_REG ), - .LEN_REG (DR_LEN_REG ) - ); - -// Output data register (dc fifo to cross domain). -fifo_dc_axi - #( - // Data width. - .B (4*B ), - - // Fifo depth. - .N (4 ) - ) - fifo_i - ( - .wr_rstn (rstn ), - .wr_clk (clk ), - - .rd_rstn (m_axis_aresetn ), - .rd_clk (m_axis_aclk ), - - // Write I/F. - .wr_en (mem_we_int ), - .din (mem_di_int ), - - // Read I/F. - .rd_en (m1_axis_tready ), - .dout (m1_axis_tdata ), - - // Flags. - .full ( ), - .empty (fifo_empty ) - ); - -// Assign outputs. -assign m1_axis_tvalid = ~fifo_empty; - -endmodule - diff --git a/qick/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.veo b/qick/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.veo deleted file mode 100644 index 5f33135..0000000 --- a/qick/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.veo +++ /dev/null @@ -1,85 +0,0 @@ -// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -// IP VLNV: xilinx.com:ip:axi_vip:1.1 -// IP Revision: 5 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -axi_mst_0 your_instance_name ( - .aclk(aclk), // input wire aclk - .aresetn(aresetn), // input wire aresetn - .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr - .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot - .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid - .m_axi_awready(m_axi_awready), // input wire m_axi_awready - .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata - .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb - .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid - .m_axi_wready(m_axi_wready), // input wire m_axi_wready - .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp - .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid - .m_axi_bready(m_axi_bready), // output wire m_axi_bready - .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr - .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot - .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid - .m_axi_arready(m_axi_arready), // input wire m_axi_arready - .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata - .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp - .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid - .m_axi_rready(m_axi_rready) // output wire m_axi_rready -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file axi_mst_0.v when simulating -// the core, axi_mst_0. When compiling the wrapper file, be sure to -// reference the Verilog simulation library. - diff --git a/qick/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.vho b/qick/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.vho deleted file mode 100644 index 5c4d9a9..0000000 --- a/qick/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.vho +++ /dev/null @@ -1,115 +0,0 @@ --- (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:axi_vip:1.1 --- IP Revision: 5 - --- The following code must appear in the VHDL architecture header. - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT axi_mst_0 - PORT ( - aclk : IN STD_LOGIC; - aresetn : IN STD_LOGIC; - m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - m_axi_awvalid : OUT STD_LOGIC; - m_axi_awready : IN STD_LOGIC; - m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - m_axi_wvalid : OUT STD_LOGIC; - m_axi_wready : IN STD_LOGIC; - m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - m_axi_bvalid : IN STD_LOGIC; - m_axi_bready : OUT STD_LOGIC; - m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - m_axi_arvalid : OUT STD_LOGIC; - m_axi_arready : IN STD_LOGIC; - m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - m_axi_rvalid : IN STD_LOGIC; - m_axi_rready : OUT STD_LOGIC - ); -END COMPONENT; --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : axi_mst_0 - PORT MAP ( - aclk => aclk, - aresetn => aresetn, - m_axi_awaddr => m_axi_awaddr, - m_axi_awprot => m_axi_awprot, - m_axi_awvalid => m_axi_awvalid, - m_axi_awready => m_axi_awready, - m_axi_wdata => m_axi_wdata, - m_axi_wstrb => m_axi_wstrb, - m_axi_wvalid => m_axi_wvalid, - m_axi_wready => m_axi_wready, - m_axi_bresp => m_axi_bresp, - m_axi_bvalid => m_axi_bvalid, - m_axi_bready => m_axi_bready, - m_axi_araddr => m_axi_araddr, - m_axi_arprot => m_axi_arprot, - m_axi_arvalid => m_axi_arvalid, - m_axi_arready => m_axi_arready, - m_axi_rdata => m_axi_rdata, - m_axi_rresp => m_axi_rresp, - m_axi_rvalid => m_axi_rvalid, - m_axi_rready => m_axi_rready - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file axi_mst_0.vhd when simulating --- the core, axi_mst_0. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/qick/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.xci b/qick/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.xci deleted file mode 100644 index 34f0b12..0000000 --- a/qick/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.xci +++ /dev/null @@ -1,187 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - axi_mst_0 - - - ACTIVE_LOW - - 100000000 - 0 - 0.000 - 32 - 0 - 0 - 0 - - 32 - 100000000 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 32 - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 0 - 2 - 32 - 0 - 0 - 0 - 32 - 0 - 0 - 32 - 0 - 0 - 0 - axi_mst_0 - 32 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 0 - 0 - 1 - 0 - MASTER - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - virtex7 - - - xc7vx485t - ffg1157 - VERILOG - - MIXED - -1 - - - TRUE - TRUE - IP_Flow - 5 - TRUE - . - - . - 2019.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/qick/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.xml b/qick/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.xml deleted file mode 100644 index 58db142..0000000 --- a/qick/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.xml +++ /dev/null @@ -1,4751 +0,0 @@ - - - xilinx.com - customized_ip - axi_mst_0 - 1.0 - - - M_AXI - - - - - - - - - ARADDR - - - m_axi_araddr - - - - - ARBURST - - - m_axi_arburst - - - - - ARCACHE - - - m_axi_arcache - - - - - ARID - - - m_axi_arid - - - - - ARLEN - - - m_axi_arlen - - - - - ARLOCK - - - m_axi_arlock - - - - - ARPROT - - - m_axi_arprot - - - - - ARQOS - - - m_axi_arqos - - - - - ARREADY - - - m_axi_arready - - - - - ARREGION - - - m_axi_arregion - - - - - ARSIZE - - - m_axi_arsize - - - - - ARUSER - - - m_axi_aruser - - - - - ARVALID - - - m_axi_arvalid - - - - - AWADDR - - - m_axi_awaddr - - - - - AWBURST - - - m_axi_awburst - - - - - AWCACHE - - - m_axi_awcache - - - - - AWID - - - m_axi_awid - - - - - AWLEN - - - m_axi_awlen - - - - - AWLOCK - - - m_axi_awlock - - - - - AWPROT - - - m_axi_awprot - - - - - AWQOS - - - m_axi_awqos - - - - - AWREADY - - - m_axi_awready - - - - - AWREGION - - - m_axi_awregion - - - - - AWSIZE - - - m_axi_awsize - - - - - AWUSER - - - m_axi_awuser - - - - - AWVALID - - - m_axi_awvalid - - - - - BID - - - m_axi_bid - - - - - BREADY - - - m_axi_bready - - - - - BRESP - - - m_axi_bresp - - - - - BUSER - - - m_axi_buser - - - - - BVALID - - - m_axi_bvalid - - - - - RDATA - - - m_axi_rdata - - - - - RID - - - m_axi_rid - - - - - RLAST - - - m_axi_rlast - - - - - RREADY - - - m_axi_rready - - - - - RRESP - - - m_axi_rresp - - - - - RUSER - - - m_axi_ruser - - - - - RVALID - - - m_axi_rvalid - - - - - WDATA - - - m_axi_wdata - - - - - WID - - - m_axi_wid - - - - - WLAST - - - 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- - tlm - - - name - rd_socket - - - - - - - 1 - - - - - - - C_AXI_PROTOCOL - 2 - - - C_AXI_INTERFACE_MODE - 0 - - - C_AXI_ADDR_WIDTH - 32 - - - C_AXI_WDATA_WIDTH - 32 - - - C_AXI_RDATA_WIDTH - 32 - - - C_AXI_WID_WIDTH - 0 - - - C_AXI_RID_WIDTH - 0 - - - C_AXI_AWUSER_WIDTH - 0 - - - C_AXI_ARUSER_WIDTH - 0 - - - C_AXI_WUSER_WIDTH - 0 - - - C_AXI_RUSER_WIDTH - 0 - - - C_AXI_BUSER_WIDTH - 0 - - - C_AXI_SUPPORTS_NARROW - 0 - - - C_AXI_HAS_BURST - 0 - - - C_AXI_HAS_LOCK - 0 - - - C_AXI_HAS_CACHE - 0 - - - C_AXI_HAS_REGION - 0 - - - C_AXI_HAS_PROT - 1 - - - C_AXI_HAS_QOS - 0 - - - C_AXI_HAS_WSTRB - 1 - - - C_AXI_HAS_BRESP - 1 - - - C_AXI_HAS_RRESP - 1 - - - C_AXI_HAS_ARESETN - 1 - - - - - - choice_list_04fafd91 - AXI3 - AXI4 - AXI4LITE - - - choice_list_6240decd - READ_ONLY - READ_WRITE - WRITE_ONLY - - - choice_list_642e7122 - MASTER - PASS_THROUGH - SLAVE - - - choice_list_99ba8646 - 32 - 64 - - - choice_list_9d8b0d81 - ACTIVE_HIGH - ACTIVE_LOW - - - choice_pairs_0fc128e8 - 0 - 0 - - - - - xilinx_veriloginstantiationtemplate_view_fileset - - axi_mst_0.vho - vhdlTemplate - - - axi_mst_0.veo - verilogTemplate - - - - xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset - - hdl/axi_infrastructure_v1_1_0.vh - verilogSource - true - axi_infrastructure_v1_1_0 - - - hdl/axi_infrastructure_v1_1_vl_rfs.v - verilogSource - axi_infrastructure_v1_1_0 - - - - - - - - - - - xilinx_verilogsynthesis_view_fileset - - hdl/axi_vip_v1_1_vlsyn_rfs.sv - systemVerilogSource - axi_vip_v1_1_5 - - - - xilinx_synthesisconstraints_view_fileset - - axi_mst_0_ooc.xdc - xdc - USED_IN_implementation - USED_IN_out_of_context - USED_IN_synthesis - - - - xilinx_verilogsynthesiswrapper_view_fileset - - synth/axi_mst_0.sv - systemVerilogSource - xil_defaultlib - - - - xilinx_versioninformation_view_fileset - - doc/axi_vip_v1_1_changelog.txt - text - axi_vip_v1_1_5 - - - - xilinx_externalfiles_view_fileset - - axi_mst_0.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - axi_mst_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - axi_mst_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - axi_mst_0_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - axi_mst_0_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - - xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset - - hdl/axi_infrastructure_v1_1_0.vh - verilogSource - USED_IN_ipstatic - true - axi_infrastructure_v1_1_0 - - - hdl/axi_infrastructure_v1_1_vl_rfs.v - verilogSource - USED_IN_ipstatic - axi_infrastructure_v1_1_0 - - - - - - - - - - - xilinx_verilogbehavioralsimulation_view_fileset - - sim/axi_mst_0_pkg.sv - systemVerilogSource - - - hdl/axi_vip_v1_1_vl_rfs.sv - systemVerilogSource - USED_IN_ipstatic - axi_vip_v1_1_5 - - - - xilinx_systemcsimulation_view_fileset - - sysc/axi_vip.cpp - systemCSource - axi_vip_v1_1_5 - - - sysc/axi_vip.h - systemCSource - true - axi_vip_v1_1_5 - - - - xilinx_verilogsimulationwrapper_view_fileset - - sim/axi_mst_0.sv - systemVerilogSource - xil_defaultlib - - - - xilinx_systemcsimulationwrapper_view_fileset - - sim/axi_mst_0_sc.h - systemCSource - true - - - sim/axi_mst_0_sc.cpp - systemCSource - - - sim/axi_mst_0.h - systemCSource - true - - - sim/axi_mst_0.cpp - systemCSource - - - sim/axi_mst_0_stub.sv - systemVerilogSource - - - - The AXI Verification IP. - - - Component_Name - Component Name - axi_mst_0 - - - PROTOCOL - PROTOCOL - AXI4LITE - - - READ_WRITE_MODE - READ_WRITE MODE - READ_WRITE - - - INTERFACE_MODE - INTERFACE MODE - MASTER - - - ADDR_WIDTH - ADDRESS WIDTH - 32 - - - DATA_WIDTH - DATA WIDTH - 32 - - - ID_WIDTH - ID WIDTH - 0 - - - - false - - - - - - AWUSER_WIDTH - AWUSER WIDTH - 0 - - - - false - - - - - - ARUSER_WIDTH - ARUSER WIDTH - 0 - - - - false - - - - - - RUSER_WIDTH - RUSER WIDTH - 0 - - - - false - - - - - - WUSER_WIDTH - WUSER WIDTH - 0 - - - - false - - - - - - BUSER_WIDTH - BUSER WIDTH - 0 - - - - false - - - - - - WUSER_BITS_PER_BYTE - WUSER BITS PER BYTE - 0 - - - - false - - - - - - RUSER_BITS_PER_BYTE - RUSER BITS PER BYTE - 0 - - - - false - - - - - - HAS_USER_BITS_PER_BYTE - HAS USER_BITS_PER_BYTE - 0 - - - - false - - - - - - SUPPORTS_NARROW - SUPPORTS NARROW - 0 - - - - false - - - - - - HAS_SIZE - HAS SIZE - 0 - - - - false - - - - - - HAS_BURST - HAS BURST - 0 - - - - false - - - - - - HAS_LOCK - HAS LOCK - 0 - - - - false - - - - - - HAS_CACHE - HAS CACHE - 0 - - - - false - - - - - - HAS_REGION - HAS REGION - 0 - - - - false - - - - - - HAS_QOS - HAS QOS - 0 - - - - false - - - - - - HAS_PROT - HAS PROT - 1 - - - HAS_WSTRB - HAS WSTRB - 1 - - - HAS_BRESP - HAS BRESP - 1 - - - HAS_RRESP - HAS RRESP - 1 - - - HAS_ACLKEN - HAS ACLKEN - 0 - - - HAS_ARESETN - HAS ARESETN - 1 - - - - - AXI Verification IP - - xtlm - - 5 - true - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2019.1 - - - - - - - - - - diff --git a/qick/firmware/ip/axis_avg_buffer/src/axi_slv.vhd b/qick/firmware/ip/axis_avg_buffer/src/axi_slv.vhd deleted file mode 100644 index a1be63e..0000000 --- a/qick/firmware/ip/axis_avg_buffer/src/axi_slv.vhd +++ /dev/null @@ -1,534 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity axi_slv is - Generic - ( - DATA_WIDTH : integer := 32; - ADDR_WIDTH : integer := 6 - ); - Port - ( - aclk : in std_logic; - aresetn : in std_logic; - - -- Write Address Channel. - awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); - awprot : in std_logic_vector(2 downto 0); - awvalid : in std_logic; - awready : out std_logic; - - -- Write Data Channel. - wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); - wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); - wvalid : in std_logic; - wready : out std_logic; - - -- Write Response Channel. - bresp : out std_logic_vector(1 downto 0); - bvalid : out std_logic; - bready : in std_logic; - - -- Read Address Channel. - araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); - arprot : in std_logic_vector(2 downto 0); - arvalid : in std_logic; - arready : out std_logic; - - -- Read Data Channel. - rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); - rresp : out std_logic_vector(1 downto 0); - rvalid : out std_logic; - rready : in std_logic; - - -- Registers. - AVG_START_REG : out std_logic; - AVG_ADDR_REG : out std_logic_vector (31 downto 0); - AVG_LEN_REG : out std_logic_vector (31 downto 0); - AVG_DR_START_REG: out std_logic; - AVG_DR_ADDR_REG : out std_logic_vector (31 downto 0); - AVG_DR_LEN_REG : out std_logic_vector (31 downto 0); - BUF_START_REG : out std_logic; - BUF_ADDR_REG : out std_logic_vector (31 downto 0); - BUF_LEN_REG : out std_logic_vector (31 downto 0); - BUF_DR_START_REG: out std_logic; - BUF_DR_ADDR_REG : out std_logic_vector (31 downto 0); - BUF_DR_LEN_REG : out std_logic_vector (31 downto 0) - ); -end axi_slv; - -architecture rtl of axi_slv is - - -- AXI4LITE signals - signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); - signal axi_awready : std_logic; - signal axi_wready : std_logic; - signal axi_bresp : std_logic_vector(1 downto 0); - signal axi_bvalid : std_logic; - signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); - signal axi_arready : std_logic; - signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); - signal axi_rresp : std_logic_vector(1 downto 0); - signal axi_rvalid : std_logic; - - -- Example-specific design signals - -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH - -- ADDR_LSB is used for addressing 32/64 bit registers/memories - -- ADDR_LSB = 2 for 32 bits (n downto 2) - -- ADDR_LSB = 3 for 64 bits (n downto 3) - constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; - constant OPT_MEM_ADDR_BITS : integer := 3; - ------------------------------------------------ - ---- Signals for user logic register space example - -------------------------------------------------- - ---- Number of Slave Registers 16 - signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg_rden : std_logic; - signal slv_reg_wren : std_logic; - signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); - signal byte_index : integer; - signal aw_en : std_logic; - -begin - -- I/O Connections assignments - - awreadY <= axi_awready; - wready <= axi_wready; - bresp <= axi_bresp; - bvalid <= axi_bvalid; - arreadY <= axi_arready; - rdata <= axi_rdata; - rresp <= axi_rresp; - rvalid <= axi_rvalid; - -- Implement axi_awready generation - -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is - -- de-asserted when reset is low. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_awready <= '0'; - aw_en <= '1'; - else - if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then - -- slave is ready to accept write address when - -- there is a valid write address and write data - -- on the write address and data bus. This design - -- expects no outstanding transactions. - axi_awready <= '1'; - aw_en <= '0'; - elsif (bready = '1' and axi_bvalid = '1') then - aw_en <= '1'; - axi_awready <= '0'; - else - axi_awready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement axi_awaddr latching - -- This process is used to latch the address when both - -- S_AXI_AWVALID and S_AXI_WVALID are valid. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_awaddr <= (others => '0'); - else - if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then - -- Write Address latching - axi_awaddr <= awaddr; - end if; - end if; - end if; - end process; - - -- Implement axi_wready generation - -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is - -- de-asserted when reset is low. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_wready <= '0'; - else - if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then - -- slave is ready to accept write data when - -- there is a valid write address and write data - -- on the write address and data bus. This design - -- expects no outstanding transactions. - axi_wready <= '1'; - else - axi_wready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement memory mapped register select and write logic generation - -- The write data is accepted and written to memory mapped registers when - -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to - -- select byte enables of slave registers while writing. - -- These registers are cleared when reset (active low) is applied. - -- Slave register write enable is asserted when valid address and data are available - -- and the slave is ready to accept the write address and write data. - slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; - - process (aclk) - variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); - begin - if rising_edge(aclk) then - if aresetn = '0' then - slv_reg0 <= (others => '0'); - slv_reg1 <= (others => '0'); - slv_reg2 <= (others => '0'); - slv_reg3 <= (others => '0'); - slv_reg4 <= (others => '0'); - slv_reg5 <= (others => '0'); - slv_reg6 <= (others => '0'); - slv_reg7 <= (others => '0'); - slv_reg8 <= (others => '0'); - slv_reg9 <= (others => '0'); - slv_reg10 <= (others => '0'); - slv_reg11 <= (others => '0'); - slv_reg12 <= (others => '0'); - slv_reg13 <= (others => '0'); - slv_reg14 <= (others => '0'); - slv_reg15 <= (others => '0'); - else - loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); - if (slv_reg_wren = '1') then - case loc_addr is - when b"0000" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 0 - slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0001" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 1 - slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0010" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 2 - slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0011" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 3 - slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0100" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 4 - slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0101" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 5 - slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0110" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 6 - slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0111" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 7 - slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1000" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 8 - slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1001" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 9 - slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1010" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 10 - slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1011" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 11 - slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1100" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 12 - slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1101" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 13 - slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1110" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 14 - slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1111" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 15 - slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when others => - slv_reg0 <= slv_reg0; - slv_reg1 <= slv_reg1; - slv_reg2 <= slv_reg2; - slv_reg3 <= slv_reg3; - slv_reg4 <= slv_reg4; - slv_reg5 <= slv_reg5; - slv_reg6 <= slv_reg6; - slv_reg7 <= slv_reg7; - slv_reg8 <= slv_reg8; - slv_reg9 <= slv_reg9; - slv_reg10 <= slv_reg10; - slv_reg11 <= slv_reg11; - slv_reg12 <= slv_reg12; - slv_reg13 <= slv_reg13; - slv_reg14 <= slv_reg14; - slv_reg15 <= slv_reg15; - end case; - end if; - end if; - end if; - end process; - - -- Implement write response logic generation - -- The write response and response valid signals are asserted by the slave - -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. - -- This marks the acceptance of address and indicates the status of - -- write transaction. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_bvalid <= '0'; - axi_bresp <= "00"; --need to work more on the responses - else - if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then - axi_bvalid <= '1'; - axi_bresp <= "00"; - elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) - axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) - end if; - end if; - end if; - end process; - - -- Implement axi_arready generation - -- axi_arready is asserted for one S_AXI_ACLK clock cycle when - -- S_AXI_ARVALID is asserted. axi_awready is - -- de-asserted when reset (active low) is asserted. - -- The read address is also latched when S_AXI_ARVALID is - -- asserted. axi_araddr is reset to zero on reset assertion. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_arready <= '0'; - axi_araddr <= (others => '1'); - else - if (axi_arready = '0' and arvalid = '1') then - -- indicates that the slave has acceped the valid read address - axi_arready <= '1'; - -- Read Address latching - axi_araddr <= araddr; - else - axi_arready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement axi_arvalid generation - -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_ARVALID and axi_arready are asserted. The slave registers - -- data are available on the axi_rdata bus at this instance. The - -- assertion of axi_rvalid marks the validity of read data on the - -- bus and axi_rresp indicates the status of read transaction.axi_rvalid - -- is deasserted on reset (active low). axi_rresp and axi_rdata are - -- cleared to zero on reset (active low). - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_rvalid <= '0'; - axi_rresp <= "00"; - else - if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then - -- Valid read data is available at the read data bus - axi_rvalid <= '1'; - axi_rresp <= "00"; -- 'OKAY' response - elsif (axi_rvalid = '1' and rready = '1') then - -- Read data is accepted by the master - axi_rvalid <= '0'; - end if; - end if; - end if; - end process; - - -- Implement memory mapped register select and read logic generation - -- Slave register read enable is asserted when valid address is available - -- and the slave is ready to accept the read address. - slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; - - process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) - variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); - begin - -- Address decoding for reading registers - loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); - case loc_addr is - when b"0000" => - reg_data_out <= slv_reg0; - when b"0001" => - reg_data_out <= slv_reg1; - when b"0010" => - reg_data_out <= slv_reg2; - when b"0011" => - reg_data_out <= slv_reg3; - when b"0100" => - reg_data_out <= slv_reg4; - when b"0101" => - reg_data_out <= slv_reg5; - when b"0110" => - reg_data_out <= slv_reg6; - when b"0111" => - reg_data_out <= slv_reg7; - when b"1000" => - reg_data_out <= slv_reg8; - when b"1001" => - reg_data_out <= slv_reg9; - when b"1010" => - reg_data_out <= slv_reg10; - when b"1011" => - reg_data_out <= slv_reg11; - when b"1100" => - reg_data_out <= slv_reg12; - when b"1101" => - reg_data_out <= slv_reg13; - when b"1110" => - reg_data_out <= slv_reg14; - when b"1111" => - reg_data_out <= slv_reg15; - when others => - reg_data_out <= (others => '0'); - end case; - end process; - - -- Output register or memory read data - process( aclk ) is - begin - if (rising_edge (aclk)) then - if ( aresetn = '0' ) then - axi_rdata <= (others => '0'); - else - if (slv_reg_rden = '1') then - -- When there is a valid read address (S_AXI_ARVALID) with - -- acceptance of read address by the slave (axi_arready), - -- output the read dada - -- Read address mux - axi_rdata <= reg_data_out; -- register read data - end if; - end if; - end if; - end process; - - -- Register Map. - - -- Output Registers. - AVG_START_REG <= slv_reg0(0); - AVG_ADDR_REG <= slv_reg1; - AVG_LEN_REG <= slv_reg2; - AVG_DR_START_REG <= slv_reg3(0); - AVG_DR_ADDR_REG <= slv_reg4; - AVG_DR_LEN_REG <= slv_reg5; - BUF_START_REG <= slv_reg6(0); - BUF_ADDR_REG <= slv_reg7; - BUF_LEN_REG <= slv_reg8; - BUF_DR_START_REG <= slv_reg9(0); - BUF_DR_ADDR_REG <= slv_reg10; - BUF_DR_LEN_REG <= slv_reg11; - -end rtl; - diff --git a/qick/firmware/ip/axis_avg_buffer/src/axis_avg_buffer.v b/qick/firmware/ip/axis_avg_buffer/src/axis_avg_buffer.v deleted file mode 100644 index f891daa..0000000 --- a/qick/firmware/ip/axis_avg_buffer/src/axis_avg_buffer.v +++ /dev/null @@ -1,263 +0,0 @@ -// AXIS AVG BUFFER. -// s_axi_aclk : clock for s_axi_* -// s_axis_aclk : clock for s_axis_* -// m_axis_aclk : clock for m0_axis_* and m1_axis_* -// -module axis_avg_buffer - ( - // AXI Slave I/F for configuration. - s_axi_aclk , - s_axi_aresetn , - - s_axi_awaddr , - s_axi_awprot , - s_axi_awvalid , - s_axi_awready , - - s_axi_wdata , - s_axi_wstrb , - s_axi_wvalid , - s_axi_wready , - - s_axi_bresp , - s_axi_bvalid , - s_axi_bready , - - s_axi_araddr , - s_axi_arprot , - s_axi_arvalid , - s_axi_arready , - - s_axi_rdata , - s_axi_rresp , - s_axi_rvalid , - s_axi_rready , - - // Trigger input. - trigger , - - // AXIS Slave for input data. - s_axis_aclk , - s_axis_aresetn , - s_axis_tvalid , - s_axis_tready , - s_axis_tdata , - - // Reset and clock for m0 and m1. - m_axis_aclk , - m_axis_aresetn , - - // AXIS Master for averaged output. - m0_axis_tvalid , - m0_axis_tready , - m0_axis_tdata , - m0_axis_tlast , - - // AXIS Master for raw output. - m1_axis_tvalid , - m1_axis_tready , - m1_axis_tdata , - m1_axis_tlast , - - // AXIS Master for register output. - m2_axis_tvalid , - m2_axis_tready , - m2_axis_tdata - ); - -/**************/ -/* Parameters */ -/**************/ -// Memory depth. -parameter N_AVG = 10; -parameter N_BUF = 10; - -// Number of bits. -parameter B = 16; - -/*********/ -/* Ports */ -/*********/ -input s_axi_aclk; -input s_axi_aresetn; - -input [5:0] s_axi_awaddr; -input [2:0] s_axi_awprot; -input s_axi_awvalid; -output s_axi_awready; - -input [31:0] s_axi_wdata; -input [3:0] s_axi_wstrb; -input s_axi_wvalid; -output s_axi_wready; - -output [1:0] s_axi_bresp; -output s_axi_bvalid; -input s_axi_bready; - -input [5:0] s_axi_araddr; -input [2:0] s_axi_arprot; -input s_axi_arvalid; -output s_axi_arready; - -output [31:0] s_axi_rdata; -output [1:0] s_axi_rresp; -output s_axi_rvalid; -input s_axi_rready; - -input trigger; - -input s_axis_aclk; -input s_axis_aresetn; -input s_axis_tvalid; -output s_axis_tready; -input [2*B-1:0] s_axis_tdata; - -input m_axis_aclk; -input m_axis_aresetn; - -output m0_axis_tvalid; -input m0_axis_tready; -output [4*B-1:0] m0_axis_tdata; -output m0_axis_tlast; - -output m1_axis_tvalid; -input m1_axis_tready; -output [2*B-1:0] m1_axis_tdata; -output m1_axis_tlast; - -output m2_axis_tvalid; -input m2_axis_tready; -output [4*B-1:0] m2_axis_tdata; - - -/********************/ -/* Internal signals */ -/********************/ -// Registers. -wire AVG_START_REG; -wire [N_AVG-1:0] AVG_ADDR_REG; -wire [31:0] AVG_LEN_REG; -wire AVG_DR_START_REG; -wire [N_AVG-1:0] AVG_DR_ADDR_REG; -wire [N_AVG-1:0] AVG_DR_LEN_REG; -wire BUF_START_REG; -wire [N_BUF-1:0] BUF_ADDR_REG; -wire [N_BUF-1:0] BUF_LEN_REG; -wire BUF_DR_START_REG; -wire [N_BUF-1:0] BUF_DR_ADDR_REG; -wire [N_BUF-1:0] BUF_DR_LEN_REG; - - -/**********************/ -/* Begin Architecture */ -/**********************/ -// AXI Slave. -axi_slv axi_slv_i - ( - .aclk (s_axi_aclk ), - .aresetn (s_axi_aresetn ), - - // Write Address Channel. - .awaddr (s_axi_awaddr ), - .awprot (s_axi_awprot ), - .awvalid (s_axi_awvalid ), - .awready (s_axi_awready ), - - // Write Data Channel. - .wdata (s_axi_wdata ), - .wstrb (s_axi_wstrb ), - .wvalid (s_axi_wvalid ), - .wready (s_axi_wready ), - - // Write Response Channel. - .bresp (s_axi_bresp ), - .bvalid (s_axi_bvalid ), - .bready (s_axi_bready ), - - // Read Address Channel. - .araddr (s_axi_araddr ), - .arprot (s_axi_arprot ), - .arvalid (s_axi_arvalid ), - .arready (s_axi_arready ), - - // Read Data Channel. - .rdata (s_axi_rdata ), - .rresp (s_axi_rresp ), - .rvalid (s_axi_rvalid ), - .rready (s_axi_rready ), - - // Registers. - .AVG_START_REG (AVG_START_REG ), - .AVG_ADDR_REG (AVG_ADDR_REG ), - .AVG_LEN_REG (AVG_LEN_REG ), - .AVG_DR_START_REG (AVG_DR_START_REG ), - .AVG_DR_ADDR_REG (AVG_DR_ADDR_REG ), - .AVG_DR_LEN_REG (AVG_DR_LEN_REG ), - .BUF_START_REG (BUF_START_REG ), - .BUF_ADDR_REG (BUF_ADDR_REG ), - .BUF_LEN_REG (BUF_LEN_REG ), - .BUF_DR_START_REG (BUF_DR_START_REG ), - .BUF_DR_ADDR_REG (BUF_DR_ADDR_REG ), - .BUF_DR_LEN_REG (BUF_DR_LEN_REG ) - ); - -// Averager + Buffer Top. -avg_buffer - #( - .N_AVG (N_AVG ), - .N_BUF (N_BUF ), - .B (B ) - ) - avg_buffer_i - ( - // Reset and clock for s. - .s_axis_aclk (s_axis_aclk ), - .s_axis_aresetn (s_axis_aresetn ), - - // Trigger input. - .trigger (trigger ), - - // AXIS Slave for input data. - .s_axis_tvalid (s_axis_tvalid ), - .s_axis_tready (s_axis_tready ), - .s_axis_tdata (s_axis_tdata ), - - // Reset and clock for m0 and m1. - .m_axis_aclk (m_axis_aclk ), - .m_axis_aresetn (m_axis_aresetn ), - - // AXIS Master for averaged output. - .m0_axis_tvalid (m0_axis_tvalid ), - .m0_axis_tready (m0_axis_tready ), - .m0_axis_tdata (m0_axis_tdata ), - .m0_axis_tlast (m0_axis_tlast ), - - // AXIS Master for raw output. - .m1_axis_tvalid (m1_axis_tvalid ), - .m1_axis_tready (m1_axis_tready ), - .m1_axis_tdata (m1_axis_tdata ), - .m1_axis_tlast (m1_axis_tlast ), - - // AXIS Master for register output. - .m2_axis_tvalid (m2_axis_tvalid ), - .m2_axis_tready (m2_axis_tready ), - .m2_axis_tdata (m2_axis_tdata ), - - // Registers. - .AVG_START_REG (AVG_START_REG ), - .AVG_ADDR_REG (AVG_ADDR_REG ), - .AVG_LEN_REG (AVG_LEN_REG ), - .AVG_DR_START_REG (AVG_DR_START_REG ), - .AVG_DR_ADDR_REG (AVG_DR_ADDR_REG ), - .AVG_DR_LEN_REG (AVG_DR_LEN_REG ), - .BUF_START_REG (BUF_START_REG ), - .BUF_ADDR_REG (BUF_ADDR_REG ), - .BUF_LEN_REG (BUF_LEN_REG ), - .BUF_DR_START_REG (BUF_DR_START_REG ), - .BUF_DR_ADDR_REG (BUF_DR_ADDR_REG ), - .BUF_DR_LEN_REG (BUF_DR_LEN_REG ) - ); - -endmodule - diff --git a/qick/firmware/ip/axis_avg_buffer/src/buffer.sv b/qick/firmware/ip/axis_avg_buffer/src/buffer.sv deleted file mode 100644 index 6606de7..0000000 --- a/qick/firmware/ip/axis_avg_buffer/src/buffer.sv +++ /dev/null @@ -1,169 +0,0 @@ -// Data is I,Q. -// I: lower B bits. -// Q: upper B bits. -module buffer ( - // Reset and clock. - rstn , - clk , - - // Trigger input. - trigger_i , - - // Data input. - din_i , - - // Memory interface. - mem_we_o , - mem_addr_o , - mem_di_o , - - // Registers. - START_REG , - ADDR_REG , - LEN_REG - ); - -//////////////// -// Parameters // -//////////////// -// Memory depth. -parameter N = 10; - -// Number of bits. -parameter B = 16; - -/////////// -// Ports // -/////////// -input rstn; -input clk; - -input trigger_i; - -input [2*B-1:0] din_i; - -output mem_we_o; -output [N-1:0] mem_addr_o; -output [2*B-1:0] mem_di_o; - -input START_REG; -input [N-1:0] ADDR_REG; -input [N-1:0] LEN_REG; - -////////////////////// -// Internal signals // -////////////////////// -// States. -typedef enum { INIT_ST , - START_ST , - TRIGGER_ST , - MEMW_ST , - WAIT_TRIGGER_ST - } state_t; - -// State register. -(* fsm_encoding = "one_hot" *) state_t state; - -reg start_state; -reg trigger_state; -reg memw_state; - -// Counter. -reg [N-1:0] cnt; - -// Registers. -reg [N-1:0] addr_r; -reg [N-1:0] len_r; - -////////////////// -// Architecture // -////////////////// - -// Registers. -always @(posedge clk) begin - if (~rstn) begin - // State register. - state <= INIT_ST; - - // Counter. - cnt <= 0; - - // Registers. - addr_r <= 0; - len_r <= 0; - end - else begin - // State register. - case (state) - INIT_ST: - state <= START_ST; - - START_ST: - if ( START_REG == 1'b1) - state <= TRIGGER_ST; - - TRIGGER_ST: - if ( START_REG == 1'b0 ) - state <= START_ST; - else if ( trigger_i == 1'b1 ) - state <= MEMW_ST; - - MEMW_ST: - if ( cnt == len_r-1 ) - state <= WAIT_TRIGGER_ST; - - WAIT_TRIGGER_ST: - if ( START_REG == 1'b0 ) - state <= START_ST; - else if ( trigger_i == 1'b0 ) begin - state <= TRIGGER_ST; - end - endcase - - // Counter. - if ( memw_state == 1'b1 ) - cnt <= cnt + 1; - else - cnt <= 0; - - // Registers. - if ( start_state == 1'b1 ) begin - addr_r <= ADDR_REG; - len_r <= LEN_REG; - end - else if ( memw_state == 1'b1 ) begin - addr_r <= addr_r + 1; - end - end -end - -// FSM outputs. -always_comb begin - // Default. - start_state = 0; - trigger_state = 0; - memw_state = 0; - - case (state) - //INIT_ST: - - START_ST: - start_state = 1'b1; - - TRIGGER_ST: - trigger_state = 1'b1; - - MEMW_ST: - memw_state = 1'b1; - - //WAIT_TRIGGER_ST: - endcase -end - -// Assign outputs. -assign mem_we_o = memw_state; -assign mem_addr_o = addr_r; -assign mem_di_o = din_i; - -endmodule - diff --git a/qick/firmware/ip/axis_avg_buffer/src/buffer_top.v b/qick/firmware/ip/axis_avg_buffer/src/buffer_top.v deleted file mode 100644 index b9af09f..0000000 --- a/qick/firmware/ip/axis_avg_buffer/src/buffer_top.v +++ /dev/null @@ -1,182 +0,0 @@ -module buffer_top ( - // Reset and clock. - rstn , - clk , - - // Trigger input. - trigger_i , - - // Data input. - din_i , - - // AXIS Master for output. - m_axis_aclk , - m_axis_aresetn , - m_axis_tvalid , - m_axis_tready , - m_axis_tdata , - m_axis_tlast , - - // Registers. - BUF_START_REG , - BUF_ADDR_REG , - BUF_LEN_REG , - DR_START_REG , - DR_ADDR_REG , - DR_LEN_REG - ); - -//////////////// -// Parameters // -//////////////// -// Memory depth. -parameter N = 10; - -// Number of bits. -parameter B = 16; - -/////////// -// Ports // -/////////// -input rstn; -input clk; - -input trigger_i; - -input [2*B-1:0] din_i; - -input m_axis_aclk; -input m_axis_aresetn; -output m_axis_tvalid; -input m_axis_tready; -output [2*B-1:0] m_axis_tdata; -output m_axis_tlast; - -input BUF_START_REG; -input [N-1:0] BUF_ADDR_REG; -input [N-1:0] BUF_LEN_REG; -input DR_START_REG; -input [N-1:0] DR_ADDR_REG; -input [N-1:0] DR_LEN_REG; - -////////////////////// -// Internal signals // -////////////////////// -wire mem_we_int; -wire [N-1:0] mem_addra_int, mem_addrb_int; -wire [2*B-1:0] mem_di_int, mem_do_int; - -wire BUF_START_REG_resync; -wire DR_START_REG_resync; - -////////////////// -// Architecture // -////////////////// - -// BUF_START_REG_resync -synchronizer_n - #( - .N (2) - ) - BUF_START_REG_resync_i ( - .rstn (rstn ), - .clk (clk ), - .data_in (BUF_START_REG ), - .data_out (BUF_START_REG_resync ) - ); - -//DR_START_REG_resync -synchronizer_n - #( - .N (2) - ) - DR_START_REG_resync_i ( - .rstn (m_axis_aresetn ), - .clk (m_axis_aclk ), - .data_in (DR_START_REG ), - .data_out (DR_START_REG_resync ) - ); - -// Buffer block. -buffer - #( - .N (N), - .B (B) - ) - buffer_i - ( - // Reset and clock. - .rstn (rstn ), - .clk (clk ), - - // Trigger input. - .trigger_i (trigger_i ), - - // Data input. - .din_i (din_i ), - - // Memory interface. - .mem_we_o (mem_we_int ), - .mem_addr_o (mem_addra_int ), - .mem_di_o (mem_di_int ), - - // Registers. - .START_REG (BUF_START_REG_resync ), - .ADDR_REG (BUF_ADDR_REG ), - .LEN_REG (BUF_LEN_REG ) - ); - -// Dual port BRAM. -bram_dp - #( - .N (N ), - .B (2*B) - ) - bram_i - ( - .clka (clk ), - .clkb (m_axis_aclk ), - .ena (1'b1 ), - .enb (1'b1 ), - .wea (mem_we_int ), - .web (1'b0 ), - .addra (mem_addra_int ), - .addrb (mem_addrb_int ), - .dia (mem_di_int ), - .dib ({4*B{1'b0}} ), - .doa ( ), - .dob (mem_do_int ) - ); - -// Data reader. -data_reader - #( - .N (N ), - .B (2*B) - ) - data_reader_i - ( - // Reset and clock. - .rstn (m_axis_aresetn ), - .clk (m_axis_aclk ), - - // Memory I/F. - .mem_en ( ), - .mem_we ( ), - .mem_addr (mem_addrb_int ), - .mem_dout (mem_do_int ), - - // Data out. - .dout (m_axis_tdata ), - .dready (m_axis_tready ), - .dvalid (m_axis_tvalid ), - .dlast (m_axis_tlast ), - - // Registers. - .START_REG (DR_START_REG_resync ), - .ADDR_REG (DR_ADDR_REG ), - .LEN_REG (DR_LEN_REG ) - ); - -endmodule - diff --git a/qick/firmware/ip/axis_avg_buffer/src/data_reader.vhd b/qick/firmware/ip/axis_avg_buffer/src/data_reader.vhd deleted file mode 100644 index a566ef5..0000000 --- a/qick/firmware/ip/axis_avg_buffer/src/data_reader.vhd +++ /dev/null @@ -1,300 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity data_reader is - Generic - ( - -- Address map of memory. - N : Integer := 8; - -- Data width. - B : Integer := 16 - ); - Port - ( - -- Reset and clock. - rstn : in std_logic; - clk : in std_logic; - - -- Memory I/F. - mem_en : out std_logic; - mem_we : out std_logic; - mem_addr : out std_logic_vector (N-1 downto 0); - mem_dout : in std_logic_vector (B-1 downto 0); - - -- Data out. - dout : out std_logic_vector (B-1 downto 0); - dready : in std_logic; - dvalid : out std_logic; - dlast : out std_logic; - - -- Registers. - START_REG : in std_logic; - ADDR_REG : in std_logic_vector (N-1 downto 0); - LEN_REG : in std_logic_vector (N-1 downto 0) - ); -end entity; - -architecture rtl of data_reader is - -constant NPOW : Integer := 2**N; - --- Fifo to drive AXI Stream Master I/F. -component fifo_axi is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end component; - -type fsm_state is ( INIT_ST, - REGS_ST, - READ_ST, - WRITE_ST, - READ_LAST_ST, - WRITE_LAST_ST, - FIFO_ST, - END_ST); -signal current_state, next_state : fsm_state; - -signal init_state : std_logic; -signal regs_state : std_logic; -signal read_state : std_logic; -signal write_state : std_logic; -signal fifo_state : std_logic; -signal read_en : std_logic; - --- Counter for memory address and samples. -signal cnt : unsigned(N-1 downto 0); -signal addr_cnt : unsigned(N-1 downto 0); - --- Length register. -signal len_r : unsigned(N-1 downto 0); - --- Fifo signals. -signal fifo_wr_en : std_logic; -signal fifo_rd_en : std_logic; -signal fifo_din : std_logic_vector (B-1 downto 0); -signal fifo_dout : std_logic_vector (B-1 downto 0); -signal fifo_full : std_logic; -signal fifo_empty : std_logic; - --- Fifof pipeline. -signal fifo_dout_r : std_logic_vector (B-1 downto 0); -signal fifo_empty_r : std_logic; - -signal mem_dout_r : std_logic_vector (B-1 downto 0); - -signal dlast_i : std_logic; - -begin - --- Fifo to drive AXI Stream Master I/F. -fifo_i : fifo_axi - Generic map - ( - -- Data width. - B => B , - - -- Fifo depth. - N => 4 - ) - Port map - ( - rstn => rstn , - clk => clk , - - -- Write I/F. - wr_en => fifo_wr_en , - din => fifo_din , - - -- Read I/F. - rd_en => fifo_rd_en , - dout => fifo_dout , - - -- Flags. - full => fifo_full , - empty => fifo_empty - ); - --- Fifo connections. -fifo_wr_en <= write_state; -fifo_din <= mem_dout_r; -fifo_rd_en <= dready when read_en = '1' else - '0'; - --- dlast generation. -dlast_i <= fifo_state and fifo_empty; - -process(clk) -begin - if ( rising_edge(clk) ) then - if ( rstn = '0' ) then - -- State register. - current_state <= INIT_ST; - - -- Counter for memory address and samples. - cnt <= (others => '0'); - addr_cnt <= (others => '0'); - mem_dout_r <= (others => '0'); - - -- Length register. - len_r <= (others => '0'); - - -- Fifo pipeline. - fifo_dout_r <= (others => '0'); - fifo_empty_r <= '1'; - else - -- State register. - current_state <= next_state; - - -- Memory address and data. - if ( init_state = '1' ) then - mem_dout_r <= (others => '0'); - cnt <= (others => '0'); - addr_cnt <= (others => '0'); - len_r <= (others => '0'); - elsif ( regs_state = '1' ) then - cnt <= (others => '0'); - addr_cnt <= unsigned(ADDR_REG); - len_r <= unsigned(LEN_REG); - elsif ( read_state = '1' ) then - mem_dout_r <= mem_dout; - cnt <= cnt + 1; - addr_cnt <= addr_cnt + 1; - end if; - - -- Fifo pipeline. - if ( dready = '1' ) then - fifo_dout_r <= fifo_dout; - fifo_empty_r <= fifo_empty; - end if; - end if; - end if; -end process; - --- Next state logic. -process (current_state, START_REG, len_r, cnt, addr_cnt, fifo_full, fifo_empty, dready) -begin - case current_state is - when INIT_ST => - if (START_REG = '0') then - next_state <= INIT_ST; - else - next_state <= REGS_ST; - end if; - - when REGS_ST => - next_state <= READ_ST; - - when READ_ST => - next_state <= WRITE_ST; - - when WRITE_ST => - if ( fifo_full = '1' ) then - next_state <= WRITE_ST; - elsif ( cnt < len_r-1 ) then - next_state <= READ_ST; - else - next_state <= READ_LAST_ST; - end if; - - when READ_LAST_ST => - next_state <= WRITE_LAST_ST; - - when WRITE_LAST_ST => - if ( fifo_full = '1' ) then - next_state <= WRITE_LAST_ST; - else - next_state <= FIFO_ST; - end if; - - when FIFO_ST => - if ( fifo_empty = '1' and dready = '1' ) then - next_state <= END_ST; - else - next_state <= FIFO_ST; - end if; - - when END_ST => - if ( START_REG = '1' ) then - next_state <= END_ST; - else - next_state <= INIT_ST; - end if; - end case; -end process; - --- Output logic. -process (current_state) -begin -init_state <= '0'; -regs_state <= '0'; -read_state <= '0'; -write_state <= '0'; -fifo_state <= '0'; -read_en <= '0'; - case current_state is - when INIT_ST => - init_state <= '1'; - - when REGS_ST => - regs_state <= '1'; - - when READ_ST => - read_state <= '1'; - read_en <= '1'; - - when WRITE_ST => - write_state <= '1'; - read_en <= '1'; - - when READ_LAST_ST => - read_state <= '1'; - read_en <= '1'; - - when WRITE_LAST_ST => - write_state <= '1'; - read_en <= '1'; - - when FIFO_ST => - fifo_state <= '1'; - read_en <= '1'; - - when END_ST => - - end case; -end process; - --- Assign outputs. -mem_en <= '1'; -mem_we <= '0'; -mem_addr <= std_logic_vector(addr_cnt); - -dout <= fifo_dout_r; -dvalid <= not(fifo_empty_r); -dlast <= dlast_i; - -end rtl; diff --git a/qick/firmware/ip/axis_avg_buffer/src/fifo/bin2gray.vhd b/qick/firmware/ip/axis_avg_buffer/src/fifo/bin2gray.vhd deleted file mode 100644 index 4ecc09b..0000000 --- a/qick/firmware/ip/axis_avg_buffer/src/fifo/bin2gray.vhd +++ /dev/null @@ -1,37 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity bin2gray is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end bin2gray; - -architecture rtl of bin2gray is - -signal gray : std_logic_vector (B-1 downto 0); - -begin - --- MSB always match. -gray(B-1) <= din(B-1); - -GEN: for I in 0 to B-2 generate -begin - gray(I) <= din(I+1) xor din(I); -end generate; - --- Assign output. -dout <= gray; - -end rtl; - diff --git a/qick/firmware/ip/axis_avg_buffer/src/fifo/bram_dp.vhd b/qick/firmware/ip/axis_avg_buffer/src/fifo/bram_dp.vhd deleted file mode 100644 index d57aad1..0000000 --- a/qick/firmware/ip/axis_avg_buffer/src/fifo/bram_dp.vhd +++ /dev/null @@ -1,63 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity bram_dp is - Generic ( - -- Memory address size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - ena : in STD_LOGIC; - enb : in STD_LOGIC; - wea : in STD_LOGIC; - web : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR (N-1 downto 0); - addrb : in STD_LOGIC_VECTOR (N-1 downto 0); - dia : in STD_LOGIC_VECTOR (B-1 downto 0); - dib : in STD_LOGIC_VECTOR (B-1 downto 0); - doa : out STD_LOGIC_VECTOR (B-1 downto 0); - dob : out STD_LOGIC_VECTOR (B-1 downto 0) - ); -end bram_dp; - -architecture rtl of bram_dp is - --- Ram type. -type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); -shared variable RAM : ram_type; - -begin - --- CLKA port. -process (clka) -begin - if (clka'event and clka = '1') then - if (ena = '1') then - doa <= RAM(conv_integer(addra)); - if (wea = '1') then - RAM(conv_integer(addra)) := dia; - end if; - end if; - end if; -end process; - --- CLKB port. -process (clkb) -begin - if (clkb'event and clkb = '1') then - if (enb = '1') then - dob <= RAM(conv_integer(addrb)); - if (web = '1') then - RAM(conv_integer(addrb)) := dib; - end if; - end if; - end if; -end process; - -end rtl; - diff --git a/qick/firmware/ip/axis_avg_buffer/src/fifo/bram_simple_dp.vhd b/qick/firmware/ip/axis_avg_buffer/src/fifo/bram_simple_dp.vhd deleted file mode 100644 index 1494332..0000000 --- a/qick/firmware/ip/axis_avg_buffer/src/fifo/bram_simple_dp.vhd +++ /dev/null @@ -1,53 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity bram_simple_dp is - Generic ( - -- Memory address size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port ( - clk : in STD_LOGIC; - ena : in STD_LOGIC; - enb : in STD_LOGIC; - wea : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR (N-1 downto 0); - addrb : in STD_LOGIC_VECTOR (N-1 downto 0); - dia : in STD_LOGIC_VECTOR (B-1 downto 0); - dob : out STD_LOGIC_VECTOR (B-1 downto 0) - ); -end bram_simple_dp; - -architecture rtl of bram_simple_dp is - --- Ram type. -type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); -shared variable RAM : ram_type; - -begin - -process (clk) -begin - if (clk'event and clk = '1') then - if (ena = '1') then - if (wea = '1') then - RAM(conv_integer(addra)) := dia; - end if; - end if; - end if; -end process; - -process (clk) -begin - if (clk'event and clk = '1') then - if (enb = '1') then - dob <= RAM(conv_integer(addrb)); - end if; - end if; -end process; - -end rtl; - diff --git a/qick/firmware/ip/axis_avg_buffer/src/fifo/fifo.vhd b/qick/firmware/ip/axis_avg_buffer/src/fifo/fifo.vhd deleted file mode 100644 index 957362b..0000000 --- a/qick/firmware/ip/axis_avg_buffer/src/fifo/fifo.vhd +++ /dev/null @@ -1,135 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo; - -architecture rtl of fifo is - --- Number of bits of depth. -constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); - --- Dual port, single clock BRAM. -component bram_simple_dp is - Generic ( - -- Memory address size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port ( - clk : in STD_LOGIC; - ena : in STD_LOGIC; - enb : in STD_LOGIC; - wea : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR (N-1 downto 0); - addrb : in STD_LOGIC_VECTOR (N-1 downto 0); - dia : in STD_LOGIC_VECTOR (B-1 downto 0); - dob : out STD_LOGIC_VECTOR (B-1 downto 0) - ); -end component; - --- Pointers. -signal wptr : unsigned (N_LOG2-1 downto 0); -signal rptr : unsigned (N_LOG2-1 downto 0); - --- Memory signals. -signal mem_wea : std_logic; -signal mem_dob : std_logic_vector (B-1 downto 0); - --- Flags. -signal full_i : std_logic; -signal empty_i : std_logic; - -begin - --- FIFO memory. -mem_i : bram_simple_dp - Generic map ( - -- Memory address size. - N => N_LOG2, - -- Data width. - B => B - ) - Port map ( - clk => clk , - ena => '1' , - enb => rd_en , - wea => mem_wea , - addra => std_logic_vector(wptr) , - addrb => std_logic_vector(rptr) , - dia => din , - dob => mem_dob - ); - --- Memory connections. -mem_wea <= wr_en when full_i = '0' else - '0'; - --- Full/empty signals. -full_i <= '1' when wptr = rptr - 1 else - '0'; -empty_i <= '1' when wptr = rptr else - '0'; - --- wr_clk registers. -process (clk) -begin - if ( rising_edge(clk) ) then - if ( rstn = '0' ) then - wptr <= (others => '0'); - rptr <= (others => '0'); - else - -- Write. - if ( wr_en = '1' and full_i = '0' ) then - -- Write data. - - -- Increment pointer. - wptr <= wptr + 1; - end if; - - -- Read. - if ( rd_en = '1' and empty_i = '0' ) then - -- Read data. - - -- Increment pointer. - rptr <= rptr + 1; - end if; - end if; - end if; -end process; - --- Assign outputs. -dout <= mem_dob; -full <= full_i; -empty <= empty_i; - -end rtl; - diff --git a/qick/firmware/ip/axis_avg_buffer/src/fifo/fifo_axi.vhd b/qick/firmware/ip/axis_avg_buffer/src/fifo/fifo_axi.vhd deleted file mode 100644 index e1f76f7..0000000 --- a/qick/firmware/ip/axis_avg_buffer/src/fifo/fifo_axi.vhd +++ /dev/null @@ -1,147 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo_axi is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo_axi; - -architecture rtl of fifo_axi is - --- FIFO. -component fifo is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end component; - --- FIFO read to AXI adapter. -component rd2axi is - Generic - ( - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- FIFO Read I/F. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (B-1 downto 0); - fifo_empty : in std_logic; - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - empty : out std_logic - ); -end component; - -signal rd_en_i : std_logic; -signal dout_i : std_logic_vector (B-1 downto 0); -signal empty_i : std_logic; - -begin - --- FIFO. -fifo_i : fifo - Generic map - ( - -- Data width. - B => B, - - -- Fifo depth. - N => N - ) - Port map - ( - rstn => rstn , - clk => clk , - - -- Write I/F. - wr_en => wr_en , - din => din , - - -- Read I/F. - rd_en => rd_en_i , - dout => dout_i , - - -- Flags. - full => full , - empty => empty_i - ); - --- FIFO read to AXI adapter. -rd2axi_i : rd2axi - Generic map - ( - -- Data width. - B => B - ) - Port map - ( - rstn => rstn , - clk => clk , - - -- FIFO Read I/F. - fifo_rd_en => rd_en_i , - fifo_dout => dout_i , - fifo_empty => empty_i , - - -- Read I/F. - rd_en => rd_en , - dout => dout , - empty => empty - ); - -end rtl; - diff --git a/qick/firmware/ip/axis_avg_buffer/src/fifo/fifo_dc.vhd b/qick/firmware/ip/axis_avg_buffer/src/fifo/fifo_dc.vhd deleted file mode 100644 index c214fae..0000000 --- a/qick/firmware/ip/axis_avg_buffer/src/fifo/fifo_dc.vhd +++ /dev/null @@ -1,291 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo_dc is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - wr_rstn : in std_logic; - wr_clk : in std_logic; - - rd_rstn : in std_logic; - rd_clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo_dc; - -architecture rtl of fifo_dc is - --- Number of bits of depth. -constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); - --- Binary to gray converter. -component bin2gray is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end component; - --- Gray to binary converter. -component gray2bin is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end component; - --- Vector synchronizer (only for gray coded). -component synchronizer_vect is - generic ( - -- Sync stages. - N : Integer := 2; - - -- Data width. - B : Integer := 8 - ); - port ( - rstn : in std_logic; - clk : in std_logic; - data_in : in std_logic_vector (B-1 downto 0); - data_out : out std_logic_vector (B-1 downto 0) - ); -end component; - --- Dual port BRAM. -component bram_dp is - Generic ( - -- Memory address size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - ena : in STD_LOGIC; - enb : in STD_LOGIC; - wea : in STD_LOGIC; - web : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR (N-1 downto 0); - addrb : in STD_LOGIC_VECTOR (N-1 downto 0); - dia : in STD_LOGIC_VECTOR (B-1 downto 0); - dib : in STD_LOGIC_VECTOR (B-1 downto 0); - doa : out STD_LOGIC_VECTOR (B-1 downto 0); - dob : out STD_LOGIC_VECTOR (B-1 downto 0) - ); -end component; - --- Pointers. -signal wptr : unsigned (N_LOG2-1 downto 0); -signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); -signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); -signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); -signal rptr : unsigned (N_LOG2-1 downto 0); -signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); -signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); -signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); - --- Memory signals. -signal mem_wea : std_logic; -signal mem_dib : std_logic_vector (B-1 downto 0); -signal mem_doa : std_logic_vector (B-1 downto 0); -signal mem_dob : std_logic_vector (B-1 downto 0); - --- Flags. -signal full_i : std_logic; -signal empty_i : std_logic; - -begin - --- wptr_i: binary to gray. -wptr_i : bin2gray - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => std_logic_vector(wptr), - dout => wptr_g - ); - --- wptr_g: write to read domain. -wptr_g_i : synchronizer_vect - generic map ( - -- Sync stages. - N => 2, - - -- Data width. - B => N_LOG2 - ) - port map ( - rstn => rd_rstn, - clk => rd_clk, - data_in => wptr_g, - data_out => wptr_gc - ); - --- wptr_gc_i -wptr_gc_i : gray2bin - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => wptr_gc, - dout => wptr_c - ); - --- rptr_i: binary to gray. -rptr_i : bin2gray - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => std_logic_vector(rptr), - dout => rptr_g - ); - --- rptr_g: read to write domain. -rptr_g_i : synchronizer_vect - generic map ( - -- Sync stages. - N => 2, - - -- Data width. - B => N_LOG2 - ) - port map ( - rstn => wr_rstn, - clk => wr_clk, - data_in => rptr_g, - data_out => rptr_gc - ); - --- rptr_gc_i -rptr_gc_i : gray2bin - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => rptr_gc, - dout => rptr_c - ); - --- FIFO memory. -mem_i : bram_dp - Generic map ( - -- Memory address size. - N => N_LOG2, - -- Data width. - B => B - ) - Port map ( - clka => wr_clk, - clkb => rd_clk, - ena => '1', - enb => rd_en, - wea => mem_wea, - web => '0', - addra => std_logic_vector(wptr), - addrb => std_logic_vector(rptr), - dia => din, - dib => mem_dib, - doa => mem_doa, - dob => mem_dob - ); --- Memory connections. -mem_wea <= wr_en when full_i = '0' else - '0'; -mem_dib <= (others => '0'); - --- Full/empty signals. -full_i <= '1' when wptr = unsigned(rptr_c) - 1 else - '0'; -empty_i <= '1' when unsigned(wptr_c) = rptr else - '0'; - --- wr_clk registers. -process (wr_clk) -begin - if ( rising_edge(wr_clk) ) then - if ( wr_rstn = '0' ) then - wptr <= (others => '0'); - else - -- Write. - if ( wr_en = '1' and full_i = '0' ) then - -- Write data. - - -- Increment pointer. - wptr <= wptr + 1; - end if; - end if; - end if; -end process; - --- rd_clk registers. -process (rd_clk) -begin - if ( rising_edge(rd_clk) ) then - if ( rd_rstn = '0' ) then - rptr <= (others => '0'); - else - -- Read. - if ( rd_en = '1' and empty_i = '0' ) then - -- Read data. - - -- Increment pointer. - rptr <= rptr + 1; - end if; - end if; - end if; -end process; - --- Assign outputs. -dout <= mem_dob; -full <= full_i; -empty <= empty_i; - -end rtl; diff --git a/qick/firmware/ip/axis_avg_buffer/src/fifo/fifo_dc_axi.vhd b/qick/firmware/ip/axis_avg_buffer/src/fifo/fifo_dc_axi.vhd deleted file mode 100644 index eb83d1a..0000000 --- a/qick/firmware/ip/axis_avg_buffer/src/fifo/fifo_dc_axi.vhd +++ /dev/null @@ -1,156 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo_dc_axi is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - wr_rstn : in std_logic; - wr_clk : in std_logic; - - rd_rstn : in std_logic; - rd_clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo_dc_axi; - -architecture rtl of fifo_dc_axi is - --- Dual-clock FIFO. -component fifo_dc is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - wr_rstn : in std_logic; - wr_clk : in std_logic; - - rd_rstn : in std_logic; - rd_clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end component; - --- FIFO read to AXI adapter. -component rd2axi is - Generic - ( - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- FIFO Read I/F. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (B-1 downto 0); - fifo_empty : in std_logic; - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - empty : out std_logic - ); -end component; - -signal rd_en_i : std_logic; -signal dout_i : std_logic_vector (B-1 downto 0); -signal empty_i : std_logic; - -begin - --- Dual-clock FIFO. -fifo_i : fifo_dc - Generic map - ( - -- Data width. - B => B, - - -- Fifo depth. - N => N - ) - Port map - ( - wr_rstn => wr_rstn , - wr_clk => wr_clk , - - rd_rstn => rd_rstn , - rd_clk => rd_clk , - - -- Write I/F. - wr_en => wr_en , - din => din , - - -- Read I/F. - rd_en => rd_en_i , - dout => dout_i , - - -- Flags. - full => full , - empty => empty_i - ); - --- FIFO read to AXI adapter. -rd2axi_i : rd2axi - Generic map - ( - -- Data width. - B => B - ) - Port map - ( - rstn => rd_rstn , - clk => rd_clk , - - -- FIFO Read I/F. - fifo_rd_en => rd_en_i , - fifo_dout => dout_i , - fifo_empty => empty_i , - - -- Read I/F. - rd_en => rd_en , - dout => dout , - empty => empty - ); - -end rtl; - diff --git a/qick/firmware/ip/axis_avg_buffer/src/fifo/gray2bin.vhd b/qick/firmware/ip/axis_avg_buffer/src/fifo/gray2bin.vhd deleted file mode 100644 index e23f8af..0000000 --- a/qick/firmware/ip/axis_avg_buffer/src/fifo/gray2bin.vhd +++ /dev/null @@ -1,37 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity gray2bin is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end gray2bin; - -architecture rtl of gray2bin is - -signal bin : std_logic_vector (B-1 downto 0); - -begin - --- MSB always match. -bin(B-1) <= din(B-1); - -GEN: for I in 0 to B-2 generate -begin - bin(I) <= bin(I+1) xor din(I); -end generate GEN; - --- Assign output. -dout <= bin; - -end rtl; - diff --git a/qick/firmware/ip/axis_avg_buffer/src/fifo/rd2axi.vhd b/qick/firmware/ip/axis_avg_buffer/src/fifo/rd2axi.vhd deleted file mode 100644 index babadc6..0000000 --- a/qick/firmware/ip/axis_avg_buffer/src/fifo/rd2axi.vhd +++ /dev/null @@ -1,138 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity rd2axi is - Generic - ( - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- FIFO Read I/F. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (B-1 downto 0); - fifo_empty : in std_logic; - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - empty : out std_logic - ); -end rd2axi; - -architecture rtl of rd2axi is - -type fsm_state is ( WAIT_EMPTY_ST, - READ_FIRST_ST, - READ_ST, - READ_LAST_ST); -signal current_state, next_state : fsm_state; - -signal wait_empty_state : std_logic; -signal read_first_state : std_logic; -signal read_state : std_logic; - -signal fifo_rd_en_i : std_logic; -signal empty_i : std_logic; - -begin - -process(clk) -begin - if (rising_edge(clk)) then - if (rstn = '0') then - current_state <= WAIT_EMPTY_ST; - else - current_state <= next_state; - end if; - end if; -end process; - --- Next state logic. -process(current_state, fifo_empty, rd_en) -begin - case current_state is - when WAIT_EMPTY_ST => - if (fifo_empty = '1') then - next_state <= WAIT_EMPTY_ST; - else - next_state <= READ_FIRST_ST; - end if; - - when READ_FIRST_ST => - next_state <= READ_ST; - - when READ_ST => - if (fifo_empty = '0') then - next_state <= READ_ST; - else - if (rd_en = '1') then - next_state <= WAIT_EMPTY_ST; - else - next_state <= READ_LAST_ST; - end if; - end if; - - when READ_LAST_ST => - if (rd_en = '0') then - next_state <= READ_LAST_ST; - else - next_state <= WAIT_EMPTY_ST; - end if; - - end case; -end process; - --- Output logic. -process(current_state) -begin -wait_empty_state <= '0'; -read_first_state <= '0'; -read_state <= '0'; -empty_i <= '0'; - case current_state is - when WAIT_EMPTY_ST => - wait_empty_state <= '1'; - read_first_state <= '0'; - read_state <= '0'; - empty_i <= '1'; - - when READ_FIRST_ST => - wait_empty_state <= '0'; - read_first_state <= '1'; - read_state <= '0'; - empty_i <= '1'; - - when READ_ST => - wait_empty_state <= '0'; - read_first_state <= '0'; - read_state <= '1'; - empty_i <= '0'; - - when READ_LAST_ST => - wait_empty_state <= '0'; - read_first_state <= '0'; - read_state <= '0'; - empty_i <= '0'; - - end case; -end process; - --- FIFO Read enable signal. -fifo_rd_en_i <= read_first_state or (read_state and rd_en); - --- Assign outputs. -fifo_rd_en <= fifo_rd_en_i; --- TODO: add register to freeze last value. -dout <= fifo_dout when empty_i = '0' else - (others => '0'); -empty <= empty_i; - -end rtl; - diff --git a/qick/firmware/ip/axis_avg_buffer/src/fifo/synchronizer_vect.vhd b/qick/firmware/ip/axis_avg_buffer/src/fifo/synchronizer_vect.vhd deleted file mode 100644 index 2fbb696..0000000 --- a/qick/firmware/ip/axis_avg_buffer/src/fifo/synchronizer_vect.vhd +++ /dev/null @@ -1,49 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - --- This block is intended to use to sync gray coded vectors. - --- NOTE: Do not use with generic vector data, as it may result --- in corrupted re-sync data. - -entity synchronizer_vect is - generic ( - -- Sync stages. - N : Integer := 2; - - -- Data width. - B : Integer := 8 - ); - port ( - rstn : in std_logic; - clk : in std_logic; - data_in : in std_logic_vector (B-1 downto 0); - data_out : out std_logic_vector (B-1 downto 0) - ); -end synchronizer_vect; - -architecture rtl of synchronizer_vect is - --- Internal register. -type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); -signal data_int_reg : reg_t; - -begin - -process(clk) -begin - if (rising_edge(clk)) then - if (rstn = '0') then - data_int_reg <= (others => (others => '0')); -- 1 FF. - else - data_int_reg <= data_int_reg(N-2 downto 0) & data_in; - end if; - end if; -end process; - --- Assign output. -data_out <= data_int_reg(N-1); - -end rtl; - diff --git a/qick/firmware/ip/axis_avg_buffer/src/outreg.sv b/qick/firmware/ip/axis_avg_buffer/src/outreg.sv deleted file mode 100644 index d35357a..0000000 --- a/qick/firmware/ip/axis_avg_buffer/src/outreg.sv +++ /dev/null @@ -1,113 +0,0 @@ -// Data is I,Q. -// I: lower B bits. -// Q: upper B bits. -module outreg ( - // Reset and clock. - rstn , - clk , - - // Data input. - wen , - din , - - // M_AXIS. - m_axis_tdata , - m_axis_tready , - m_axis_tvalid - ); - -//////////////// -// Parameters // -//////////////// -// Number of bits. -parameter B = 16; - -/////////// -// Ports // -/////////// -input rstn; -input clk; - -input wen; -input [B-1:0] din; - -output [B-1:0] m_axis_tdata; -input m_axis_tready; -output m_axis_tvalid; - -////////////////////// -// Internal signals // -////////////////////// -// States. -typedef enum { WAIT_IN_ST , - READ_IN_ST , - WRITE_OUT_ST - } state_t; - -// State register. -(* fsm_encoding = "one_hot" *) state_t state; - -// Data register. -reg [B-1:0] din_r; - -reg din_en_i; -reg valid_i; - -////////////////// -// Architecture // -////////////////// - -// Registers. -always @(posedge clk) begin - if (~rstn) begin - // State register. - state <= WAIT_IN_ST; - - // Data register. - din_r <= 0; - end - else begin - // State register. - case (state) - WAIT_IN_ST: - if ( wen == 1'b1) - state <= READ_IN_ST; - - READ_IN_ST: - if ( wen == 1'b0 ) - state <= WRITE_OUT_ST; - - WRITE_OUT_ST: - if ( m_axis_tready == 1'b1 ) - state <= WAIT_IN_ST; - endcase - - // Data register. - if (din_en_i == 1'b1) - din_r <= din; - end -end - -// FSM outputs. -always_comb begin - // Default. - din_en_i = 0; - valid_i = 0; - - case (state) - //WAIT_IN_ST: - - READ_IN_ST: - din_en_i = 1'b1; - - WRITE_OUT_ST: - valid_i = 1'b1; - endcase -end - -// Assign outputs. -assign m_axis_tdata = din_r; -assign m_axis_tvalid = valid_i; - -endmodule - diff --git a/qick/firmware/ip/axis_avg_buffer/src/synchronizer_n.vhd b/qick/firmware/ip/axis_avg_buffer/src/synchronizer_n.vhd deleted file mode 100644 index 925425d..0000000 --- a/qick/firmware/ip/axis_avg_buffer/src/synchronizer_n.vhd +++ /dev/null @@ -1,42 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library common_lib; -use common_lib.all; - -entity synchronizer_n is - generic ( - N : Integer := 2 - ); - port ( - rstn : in std_logic; - clk : in std_logic; - data_in : in std_logic; - data_out : out std_logic - ); -end synchronizer_n; - -architecture rtl of synchronizer_n is - --- Internal register. -signal data_int_reg : std_logic_vector (N-1 downto 0); - -begin - -process(clk) -begin - if (rising_edge(clk)) then - if (rstn = '0') then - data_int_reg <= (others => '0'); - else - data_int_reg <= data_int_reg(N-2 downto 0) & data_in; - end if; - end if; -end process; - --- Assign output. -data_out <= data_int_reg(N-1); - -end rtl; - diff --git a/qick/firmware/ip/axis_avg_buffer/src/tb/data_iq.txt b/qick/firmware/ip/axis_avg_buffer/src/tb/data_iq.txt deleted file mode 100644 index 29e5f7e..0000000 --- a/qick/firmware/ip/axis_avg_buffer/src/tb/data_iq.txt +++ /dev/null @@ -1,6400 +0,0 @@ --11,0 --11,0 --18,0 --12,0 --2,0 --9,0 --17,0 --10,0 --8,0 --13,0 --7,0 --4,0 --9,0 --4,0 --4,0 --7,0 -0,0 --3,0 --10,0 --10,0 --9,0 --5,0 --7,0 --13,0 --4,0 -2,0 --7,0 --7,0 -1,0 -2,0 --4,0 --5,0 -5,0 -6,0 --5,0 --3,0 -5,0 -3,0 --6,0 --3,0 -6,0 -2,0 --1,0 -1,0 --3,0 --1,0 --2,0 --6,0 -2,0 -1,0 --5,0 --2,0 -2,0 -2,0 --6,0 --5,0 -10,0 -9,0 -0,0 -4,0 -9,0 -7,0 --1,0 --3,0 -5,0 -6,0 -2,0 -9,0 -9,0 -1,0 -1,0 --3,0 -1,0 -11,0 -4,0 -3,0 -13,0 -9,0 --1,0 -6,0 -12,0 -6,0 -4,0 -9,0 -9,0 -8,0 -7,0 -5,0 -8,0 -12,0 -11,0 -4,0 -8,0 -13,0 -8,0 -5,0 -8,0 -8,0 -7,0 -10,0 -13,0 -14,0 -7,0 -1,0 -14,0 -18,0 -1,0 -3,0 -16,0 -12,0 -0,0 -2,0 -15,0 -19,0 -16,0 -13,0 -10,0 -8,0 -6,0 -8,0 -10,0 -12,0 -16,0 -14,0 -14,0 -15,0 -12,0 -15,0 -18,0 -18,0 -15,0 -10,0 -15,0 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a/qick/firmware/ip/axis_avg_buffer/src/tb/tb.sv b/qick/firmware/ip/axis_avg_buffer/src/tb/tb.sv deleted file mode 100644 index be78bac..0000000 --- a/qick/firmware/ip/axis_avg_buffer/src/tb/tb.sv +++ /dev/null @@ -1,382 +0,0 @@ -// VIP: axi_mst_0 -// DUT: axis_readout_v1 -// IF: s_axi -> axi_mst_0 - -import axi_vip_pkg::*; -import axi_mst_0_pkg::*; - -module tb(); - -localparam N_AVG = 10; -localparam N_BUF = 16; -localparam B = 16; - -// s_axi interfase. -reg s_axi_aclk; -reg s_axi_aresetn; -wire [5:0] s_axi_araddr; -wire [2:0] s_axi_arprot; -wire s_axi_arready; -wire s_axi_arvalid; -wire [5:0] s_axi_awaddr; -wire [2:0] s_axi_awprot; -wire s_axi_awready; -wire s_axi_awvalid; -wire s_axi_bready; -wire [1:0] s_axi_bresp; -wire s_axi_bvalid; -wire [31:0] s_axi_rdata; -wire s_axi_rready; -wire [1:0] s_axi_rresp; -wire s_axi_rvalid; -wire [31:0] s_axi_wdata; -wire s_axi_wready; -wire [3:0] s_axi_wstrb; -wire s_axi_wvalid; - -reg trigger; - -reg s_axis_aclk; -reg s_axis_aresetn; -reg s_axis_tvalid; -wire s_axis_tready; -reg [2*B-1:0] s_axis_tdata; - -reg m_axis_aclk; -reg m_axis_aresetn; - -wire m0_axis_tvalid; -reg m0_axis_tready; -wire [4*B-1:0] m0_axis_tdata; -wire m0_axis_tlast; - -wire m1_axis_tvalid; -reg m1_axis_tready; -wire [2*B-1:0] m1_axis_tdata; -wire m1_axis_tlast; - -wire m2_axis_tvalid; -reg m2_axis_tready; -wire [4*B-1:0] m2_axis_tdata; - -// AXI VIP master address. -xil_axi_ulong avg_start_reg = 0; -xil_axi_ulong avg_addr_reg = 1; -xil_axi_ulong avg_len_reg = 2; -xil_axi_ulong avg_dr_start_reg = 3; -xil_axi_ulong avg_dr_addr_reg = 4; -xil_axi_ulong avg_dr_len_reg = 5; -xil_axi_ulong buf_start_reg = 6; -xil_axi_ulong buf_addr_reg = 7; -xil_axi_ulong buf_len_reg = 8; -xil_axi_ulong buf_dr_start_reg = 9; -xil_axi_ulong buf_dr_addr_reg = 10; -xil_axi_ulong buf_dr_len_reg = 11; - -xil_axi_prot_t prot = 0; -reg[31:0] data_wr = 32'h12345678; -reg[31:0] data; -xil_axi_resp_t resp; - -// Test bench control. -reg tb_input = 0; -reg tb_input_done = 0; - -// axi_mst_0. -axi_mst_0 axi_mst_0_i - ( - .aclk (s_axi_aclk ), - .aresetn (s_axi_aresetn ), - .m_axi_araddr (s_axi_araddr ), - .m_axi_arprot (s_axi_arprot ), - .m_axi_arready (s_axi_arready ), - .m_axi_arvalid (s_axi_arvalid ), - .m_axi_awaddr (s_axi_awaddr ), - .m_axi_awprot (s_axi_awprot ), - .m_axi_awready (s_axi_awready ), - .m_axi_awvalid (s_axi_awvalid ), - .m_axi_bready (s_axi_bready ), - .m_axi_bresp (s_axi_bresp ), - .m_axi_bvalid (s_axi_bvalid ), - .m_axi_rdata (s_axi_rdata ), - .m_axi_rready (s_axi_rready ), - .m_axi_rresp (s_axi_rresp ), - .m_axi_rvalid (s_axi_rvalid ), - .m_axi_wdata (s_axi_wdata ), - .m_axi_wready (s_axi_wready ), - .m_axi_wstrb (s_axi_wstrb ), - .m_axi_wvalid (s_axi_wvalid ) - ); - -axis_avg_buffer - # - ( - .N_AVG (N_AVG ), - .N_BUF (N_BUF ), - .B (B ) - ) - DUT - ( - // AXI Slave I/F for configuration. - .s_axi_aclk (s_axi_aclk ), - .s_axi_aresetn (s_axi_aresetn ), - .s_axi_araddr (s_axi_araddr ), - .s_axi_arprot (s_axi_arprot ), - .s_axi_arready (s_axi_arready ), - .s_axi_arvalid (s_axi_arvalid ), - .s_axi_awaddr (s_axi_awaddr ), - .s_axi_awprot (s_axi_awprot ), - .s_axi_awready (s_axi_awready ), - .s_axi_awvalid (s_axi_awvalid ), - .s_axi_bready (s_axi_bready ), - .s_axi_bresp (s_axi_bresp ), - .s_axi_bvalid (s_axi_bvalid ), - .s_axi_rdata (s_axi_rdata ), - .s_axi_rready (s_axi_rready ), - .s_axi_rresp (s_axi_rresp ), - .s_axi_rvalid (s_axi_rvalid ), - .s_axi_wdata (s_axi_wdata ), - .s_axi_wready (s_axi_wready ), - .s_axi_wstrb (s_axi_wstrb ), - .s_axi_wvalid (s_axi_wvalid ), - - // Trigger input. - .trigger (trigger ), - - // AXIS Slave for input data. - .s_axis_aclk (s_axis_aclk ), - .s_axis_aresetn (s_axis_aresetn ), - .s_axis_tvalid (s_axis_tvalid ), - .s_axis_tready (s_axis_tready ), - .s_axis_tdata (s_axis_tdata ), - - // Reset and clock for m0 and m1. - .m_axis_aclk (m_axis_aclk ), - .m_axis_aresetn (m_axis_aresetn ), - - // AXIS Master for averaged output. - .m0_axis_tvalid (m0_axis_tvalid ), - .m0_axis_tready (m0_axis_tready ), - .m0_axis_tdata (m0_axis_tdata ), - .m0_axis_tlast (m0_axis_tlast ), - - // AXIS Master for raw output. - .m1_axis_tvalid (m1_axis_tvalid ), - .m1_axis_tready (m1_axis_tready ), - .m1_axis_tdata (m1_axis_tdata ), - .m1_axis_tlast (m1_axis_tlast ), - - // AXIS Master for register output. - .m2_axis_tvalid (m2_axis_tvalid ), - .m2_axis_tready (m2_axis_tready ), - .m2_axis_tdata (m2_axis_tdata ) - ); - -// VIP Agents -axi_mst_0_mst_t axi_mst_0_agent; - -// Main TB Control. -initial begin - // Create agents. - axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); - - // Set tag for agents. - axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); - - // Start agents. - axi_mst_0_agent.start_master(); - - // Reset sequence. - s_axi_aresetn <= 0; - s_axis_aresetn <= 0; - m_axis_aresetn <= 0; - m0_axis_tready <= 1; - m1_axis_tready <= 1; - m2_axis_tready <= 1; - trigger <= 0; - #500; - s_axi_aresetn <= 1; - s_axis_aresetn <= 1; - m_axis_aresetn <= 1; - - #1000; - - $display("##############"); - $display("### Test 0 ###"); - $display("##############"); - $display("t = %0t", $time); - // Average/buffer: - // * addr = 0. - // * len = 1280. - - // avg_addr_reg - data_wr = 0; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*avg_addr_reg, prot, data_wr, resp); - #10; - - // avg_len_reg - data_wr = 1280; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*avg_len_reg, prot, data_wr, resp); - #10; - - // buf_addr_reg - data_wr = 0; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*buf_addr_reg, prot, data_wr, resp); - #10; - - // buf_len_reg - data_wr = 1280; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*buf_len_reg, prot, data_wr, resp); - #10; - - // avg_start_reg - data_wr = 1; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*avg_start_reg, prot, data_wr, resp); - #10; - - // buf_start_reg - data_wr = 1; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*buf_start_reg, prot, data_wr, resp); - #10; - - // Start sending input data. - tb_input <= 1; - - trigger_gen(5,1280); - - wait (tb_input_done); - - tb_input <= 0; - - // avg_start_reg - data_wr = 0; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*avg_start_reg, prot, data_wr, resp); - #10; - - // buf_start_reg - data_wr = 0; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*buf_start_reg, prot, data_wr, resp); - #10; - - // Average DR. - // * addr = 0. - // * len = 10; - - // avg_dr_addr_reg - data_wr = 0; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*avg_dr_addr_reg, prot, data_wr, resp); - #10; - - // avg_dr_len_reg - data_wr = 10; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*avg_dr_len_reg, prot, data_wr, resp); - #10; - - // avg_dr_start_reg - data_wr = 1; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*avg_dr_start_reg, prot, data_wr, resp); - #10; - - // avg_dr_start_reg - data_wr = 0; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*avg_dr_start_reg, prot, data_wr, resp); - #10; - - #100; - - // Buffer DR. - // * addr = 0. - // * len = 1280*5 = 6400, I use 7000; - - // buf_dr_addr_reg - data_wr = 0; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*buf_dr_addr_reg, prot, data_wr, resp); - #10; - - // buf_dr_len_reg - data_wr = 7000; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*buf_dr_len_reg, prot, data_wr, resp); - #10; - - // buf_dr_start_reg - data_wr = 1; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*buf_dr_start_reg, prot, data_wr, resp); - #10; - - // buf_dr_start_reg - data_wr = 0; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*buf_dr_start_reg, prot, data_wr, resp); - #10; - - #20000; -end - -// Input data. -initial begin - int fd; - int vali, valq; - - s_axis_tvalid <= 1; - s_axis_tdata <= 0; - tb_input_done <= 0; - - wait (tb_input); - - fd = $fopen("../../../../../tb/data_iq.txt","r"); - - while ($fscanf(fd,"%d,%d", vali, valq) == 2) begin - $display("Time %t: I = %d, Q = %d", $time, vali, valq); - @(posedge s_axis_aclk); - s_axis_tdata[0 +: 16] <= vali; - s_axis_tdata[16 +: 16] <= valq; - end - - @(posedge s_axis_aclk); - s_axis_tvalid <= 0; - tb_input_done <= 1; - -end - -// s_axi_aclk. -always begin - s_axi_aclk <= 0; - #10; - s_axi_aclk <= 1; - #10; -end - -// s_axis_aclk. -always begin - s_axis_aclk <= 0; - #7; - s_axis_aclk <= 1; - #7; -end - -// m_axis_aclk. -always begin - m_axis_aclk <= 0; - #3; - m_axis_aclk <= 1; - #3; -end - -task trigger_gen (input int cnt, input int waitc); - for (int i=0; i - - user.org - user - axis_cdcsync_v1 - 1.0 - - - m0_axis - - - - - - - TDATA - - - m0_axis_tdata - - - - - TVALID - - - m0_axis_tvalid - - - - - - m1_axis - - - - - - - TDATA - - - m1_axis_tdata - - - - - TVALID - - - m1_axis_tvalid - - - - - - m2_axis - - - - - - - TDATA - - - m2_axis_tdata - - - - - TVALID - - - m2_axis_tvalid - - - - - - - false - - - - - - m3_axis - - - - - - - TDATA - - - m3_axis_tdata - - - - - TVALID - - - m3_axis_tvalid - - - - - - - false - - - - - - m4_axis - - - - - - - TDATA - - - m4_axis_tdata - - - - - TVALID - - - m4_axis_tvalid - - - - - - - false - - - - - - m5_axis - - - - - - - TDATA - - - m5_axis_tdata - - - - - TVALID - - - m5_axis_tvalid - - - - - - - false - - - - - - m6_axis - - - - - - - TDATA - - - m6_axis_tdata - - - - - TVALID - - - m6_axis_tvalid - - - - - - - false - - - - - - m7_axis - - - - - - - TDATA - - - m7_axis_tdata - - - - - TVALID - - - m7_axis_tvalid - - - - - - - false - - - - - - s0_axis - - - - - - - TDATA - - - s0_axis_tdata - - - - - TVALID - - - s0_axis_tvalid - - - - - TREADY - - - s0_axis_tready - - - - - - s1_axis - - - - - - - TDATA - - - s1_axis_tdata - - - - - TVALID - - - s1_axis_tvalid - - - - - TREADY - - - s1_axis_tready - - - - - - s2_axis - - - - - - - TDATA - - - s2_axis_tdata - - - - - TVALID - - - s2_axis_tvalid - - - - - TREADY - - - s2_axis_tready - - - - - - - false - - - - - - s3_axis - - - - - - - TDATA - - - s3_axis_tdata - - - - - TVALID - - - s3_axis_tvalid - - - - - TREADY - - - s3_axis_tready - - - - - - - false - - - - - - s4_axis - - - - - - - TDATA - - - s4_axis_tdata - - - - - TVALID - - - s4_axis_tvalid - - - - - TREADY - - - s4_axis_tready - - - - - - - false - - - - - - s5_axis - - - - - - - TDATA - - - s5_axis_tdata - - - - - TVALID - - - s5_axis_tvalid - - - - - TREADY - - - s5_axis_tready - - - - - - - false - - - - - - s6_axis - - - - - - - TDATA - - - s6_axis_tdata - - - - - TVALID - - - s6_axis_tvalid - - - - - TREADY - - - s6_axis_tready - - - - - - - false - - - - - - s7_axis - - - - - - - TDATA - - - s7_axis_tdata - - - - - TVALID - - - s7_axis_tvalid - - - - - TREADY - - - s7_axis_tready - - - - - - - false - - - - - - s_axis_aresetn - - - - - - - RST - - - s_axis_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - s_axis_aclk - - - - - - - CLK - - - s_axis_aclk - - - - - - ASSOCIATED_RESET - s_axis_aresetn - - - ASSOCIATED_BUSIF - s0_axis:s1_axis:s2_axis:s3_axis:s4_axis:s5_axis:s6_axis:s7_axis - - - - - m_axis_aclk - - - - - - - CLK - - - m_axis_aclk - - - - - - ASSOCIATED_RESET - m_axis_aresetn - - - ASSOCIATED_BUSIF - m0_axis:m1_axis:m2_axis:m3_axis:m4_axis:m5_axis:m6_axis:m7_axis - - - - - m_axis_aresetn - - - - - - - RST - - - m_axis_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - - - - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis - SystemVerilog - axis_cdcsync_v1 - - xilinx_anylanguagesynthesis_view_fileset - - - - viewChecksum - 0a125baa - - - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - SystemVerilog - axis_cdcsync_v1 - - xilinx_anylanguagebehavioralsimulation_view_fileset - - - - viewChecksum - 0a125baa - - - - - xilinx_xpgui - UI Layout - :vivado.xilinx.com:xgui.ui - - xilinx_xpgui_view_fileset - - - - viewChecksum - 5752b26c - - - - - - - s_axis_aresetn - - in - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axis_aclk - - in - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s0_axis_tready - - out - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s0_axis_tvalid - - in - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s0_axis_tdata - - in - - 7 - 0 - - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s1_axis_tready - - out - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s1_axis_tvalid - - in - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s1_axis_tdata - - in - - 7 - 0 - - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s2_axis_tready - - out - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s2_axis_tvalid - - in - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s2_axis_tdata - - in - - 7 - 0 - - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s3_axis_tready - - out - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s3_axis_tvalid - - in - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s3_axis_tdata - - in - - 7 - 0 - - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s4_axis_tready - - out - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s4_axis_tvalid - - in - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s4_axis_tdata - - in - - 7 - 0 - - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s5_axis_tready - - out - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s5_axis_tvalid - - in - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s5_axis_tdata - - in - - 7 - 0 - - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s6_axis_tready - - out - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s6_axis_tvalid - - in - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s6_axis_tdata - - in - - 7 - 0 - - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s7_axis_tready - - out - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s7_axis_tvalid - - in - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s7_axis_tdata - - in - - 7 - 0 - - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - m_axis_aresetn - - in - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m_axis_aclk - - in - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m0_axis_tvalid - - out - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m0_axis_tdata - - out - - 7 - 0 - - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m1_axis_tvalid - - out - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m1_axis_tdata - - out - - 7 - 0 - - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m2_axis_tvalid - - out - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m2_axis_tdata - - out - - 7 - 0 - - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m3_axis_tvalid - - out - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m3_axis_tdata - - out - - 7 - 0 - - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m4_axis_tvalid - - out - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m4_axis_tdata - - out - - 7 - 0 - - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m5_axis_tvalid - - out - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m5_axis_tdata - - out - - 7 - 0 - - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m6_axis_tvalid - - out - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m6_axis_tdata - - out - - 7 - 0 - - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m7_axis_tvalid - - out - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m7_axis_tdata - - out - - 7 - 0 - - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - - N - N - 2 - - - B - B - 8 - - - - - - choice_list_9699f758 - 2 - 4 - 8 - - - choice_list_9d8b0d81 - ACTIVE_HIGH - ACTIVE_LOW - - - - - xilinx_anylanguagesynthesis_view_fileset - - src/cdcsync.sv - systemVerilogSource - - - src/fifo/bin2gray.vhd - vhdlSource - - - src/fifo/bram_dp.vhd - vhdlSource - - - src/fifo/fifo_dc.vhd - vhdlSource - - - src/fifo/fifo_dc_axi.vhd - vhdlSource - - - src/fifo/gray2bin.vhd - vhdlSource - - - src/fifo/rd2axi.vhd - vhdlSource - - - src/fifo/synchronizer_vect.vhd - vhdlSource - - - src/axis_cdcsync_v1.sv - systemVerilogSource - CHECKSUM_629d8d94 - - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - src/cdcsync.sv - systemVerilogSource - - - src/fifo/bin2gray.vhd - vhdlSource - - - src/fifo/bram_dp.vhd - vhdlSource - - - src/fifo/fifo_dc.vhd - vhdlSource - - - src/fifo/fifo_dc_axi.vhd - vhdlSource - - - src/fifo/gray2bin.vhd - vhdlSource - - - src/fifo/rd2axi.vhd - vhdlSource - - - src/fifo/synchronizer_vect.vhd - vhdlSource - - - src/axis_cdcsync_v1.sv - systemVerilogSource - - - - xilinx_xpgui_view_fileset - - xgui/axis_cdcsync_v1_v1_0.tcl - tclSource - CHECKSUM_5752b26c - XGUI_VERSION_2 - - - - AXIS CDC Synchronous, V1. - - - N - N - 2 - - - B - B - 8 - - - Component_Name - axis_cdcsync_v1_v1_0 - - - - - - virtex7 - qvirtex7 - versal - kintex7 - kintex7l - qkintex7 - qkintex7l - akintex7 - artix7 - artix7l - aartix7 - qartix7 - zynq - qzynq - azynq - spartan7 - aspartan7 - virtexu - zynquplus - virtexuplus - virtexuplusHBM - virtexuplus58g - kintexuplus - kintexu - - - /UserIP - - AXIS CDCSYNC V1 - package_project - 3 - 2022-09-12T15:49:36Z - - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - /home/lstefana/v20.2/ip/axis_cdcsync_v1 - - - - 2020.2 - - - - - - - - diff --git a/qick/firmware/ip/axis_cdcsync_v1/src/axis_cdcsync_v1.sv b/qick/firmware/ip/axis_cdcsync_v1/src/axis_cdcsync_v1.sv deleted file mode 100644 index f930137..0000000 --- a/qick/firmware/ip/axis_cdcsync_v1/src/axis_cdcsync_v1.sv +++ /dev/null @@ -1,154 +0,0 @@ -module axis_cdcsync_v1 - #( - // Number of inputs/outputs. - parameter N = 2 , - - // Number of data bits. - parameter B = 8 - ) - ( - // S_AXIS for input data. - input wire s_axis_aresetn , - input wire s_axis_aclk , - - output wire s0_axis_tready , - input wire s0_axis_tvalid , - input wire [B-1:0] s0_axis_tdata , - - output wire s1_axis_tready , - input wire s1_axis_tvalid , - input wire [B-1:0] s1_axis_tdata , - - output wire s2_axis_tready , - input wire s2_axis_tvalid , - input wire [B-1:0] s2_axis_tdata , - - output wire s3_axis_tready , - input wire s3_axis_tvalid , - input wire [B-1:0] s3_axis_tdata , - - output wire s4_axis_tready , - input wire s4_axis_tvalid , - input wire [B-1:0] s4_axis_tdata , - - output wire s5_axis_tready , - input wire s5_axis_tvalid , - input wire [B-1:0] s5_axis_tdata , - - output wire s6_axis_tready , - input wire s6_axis_tvalid , - input wire [B-1:0] s6_axis_tdata , - - output wire s7_axis_tready , - input wire s7_axis_tvalid , - input wire [B-1:0] s7_axis_tdata , - - // M_AXIS for output data. - input wire m_axis_aresetn , - input wire m_axis_aclk , - - output wire m0_axis_tvalid , - output wire [B-1:0] m0_axis_tdata , - - output wire m1_axis_tvalid , - output wire [B-1:0] m1_axis_tdata , - - output wire m2_axis_tvalid , - output wire [B-1:0] m2_axis_tdata , - - output wire m3_axis_tvalid , - output wire [B-1:0] m3_axis_tdata , - - output wire m4_axis_tvalid , - output wire [B-1:0] m4_axis_tdata , - - output wire m5_axis_tvalid , - output wire [B-1:0] m5_axis_tdata , - - output wire m6_axis_tvalid , - output wire [B-1:0] m6_axis_tdata , - - output wire m7_axis_tvalid , - output wire [B-1:0] m7_axis_tdata - ); - -/**********************/ -/* Begin Architecture */ -/**********************/ -cdcsync - #( - // Number of inputs/outputs. - .N(N), - - // Number of data bits. - .B(B) - ) - cdcsync_i - ( - // S_AXIS for input data. - .s_axis_aresetn (s_axis_aresetn ), - .s_axis_aclk (s_axis_aclk ), - - .s0_axis_tready (s0_axis_tready ), - .s0_axis_tvalid (s0_axis_tvalid ), - .s0_axis_tdata (s0_axis_tdata ), - - .s1_axis_tready (s1_axis_tready ), - .s1_axis_tvalid (s1_axis_tvalid ), - .s1_axis_tdata (s1_axis_tdata ), - - .s2_axis_tready (s2_axis_tready ), - .s2_axis_tvalid (s2_axis_tvalid ), - .s2_axis_tdata (s2_axis_tdata ), - - .s3_axis_tready (s3_axis_tready ), - .s3_axis_tvalid (s3_axis_tvalid ), - .s3_axis_tdata (s3_axis_tdata ), - - .s4_axis_tready (s4_axis_tready ), - .s4_axis_tvalid (s4_axis_tvalid ), - .s4_axis_tdata (s4_axis_tdata ), - - .s5_axis_tready (s5_axis_tready ), - .s5_axis_tvalid (s5_axis_tvalid ), - .s5_axis_tdata (s5_axis_tdata ), - - .s6_axis_tready (s6_axis_tready ), - .s6_axis_tvalid (s6_axis_tvalid ), - .s6_axis_tdata (s6_axis_tdata ), - - .s7_axis_tready (s7_axis_tready ), - .s7_axis_tvalid (s7_axis_tvalid ), - .s7_axis_tdata (s7_axis_tdata ), - - // M_AXIS for output data. - .m_axis_aresetn (m_axis_aresetn ), - .m_axis_aclk (m_axis_aclk ), - - .m0_axis_tvalid (m0_axis_tvalid ), - .m0_axis_tdata (m0_axis_tdata ), - - .m1_axis_tvalid (m1_axis_tvalid ), - .m1_axis_tdata (m1_axis_tdata ), - - .m2_axis_tvalid (m2_axis_tvalid ), - .m2_axis_tdata (m2_axis_tdata ), - - .m3_axis_tvalid (m3_axis_tvalid ), - .m3_axis_tdata (m3_axis_tdata ), - - .m4_axis_tvalid (m4_axis_tvalid ), - .m4_axis_tdata (m4_axis_tdata ), - - .m5_axis_tvalid (m5_axis_tvalid ), - .m5_axis_tdata (m5_axis_tdata ), - - .m6_axis_tvalid (m6_axis_tvalid ), - .m6_axis_tdata (m6_axis_tdata ), - - .m7_axis_tvalid (m7_axis_tvalid ), - .m7_axis_tdata (m7_axis_tdata ) - ); - -endmodule - diff --git a/qick/firmware/ip/axis_cdcsync_v1/src/cdcsync.sv b/qick/firmware/ip/axis_cdcsync_v1/src/cdcsync.sv deleted file mode 100644 index 4782d1c..0000000 --- a/qick/firmware/ip/axis_cdcsync_v1/src/cdcsync.sv +++ /dev/null @@ -1,194 +0,0 @@ -module cdcsync - #( - // Number of inputs/outputs. - parameter N = 2 , - - // Number of data bits. - parameter B = 8 - ) - ( - // S_AXIS for input data. - input wire s_axis_aresetn , - input wire s_axis_aclk , - - output wire s0_axis_tready , - input wire s0_axis_tvalid , - input wire [B-1:0] s0_axis_tdata , - - output wire s1_axis_tready , - input wire s1_axis_tvalid , - input wire [B-1:0] s1_axis_tdata , - - output wire s2_axis_tready , - input wire s2_axis_tvalid , - input wire [B-1:0] s2_axis_tdata , - - output wire s3_axis_tready , - input wire s3_axis_tvalid , - input wire [B-1:0] s3_axis_tdata , - - output wire s4_axis_tready , - input wire s4_axis_tvalid , - input wire [B-1:0] s4_axis_tdata , - - output wire s5_axis_tready , - input wire s5_axis_tvalid , - input wire [B-1:0] s5_axis_tdata , - - output wire s6_axis_tready , - input wire s6_axis_tvalid , - input wire [B-1:0] s6_axis_tdata , - - output wire s7_axis_tready , - input wire s7_axis_tvalid , - input wire [B-1:0] s7_axis_tdata , - - // M_AXIS for output data. - input wire m_axis_aresetn , - input wire m_axis_aclk , - - output wire m0_axis_tvalid , - output wire [B-1:0] m0_axis_tdata , - - output wire m1_axis_tvalid , - output wire [B-1:0] m1_axis_tdata , - - output wire m2_axis_tvalid , - output wire [B-1:0] m2_axis_tdata , - - output wire m3_axis_tvalid , - output wire [B-1:0] m3_axis_tdata , - - output wire m4_axis_tvalid , - output wire [B-1:0] m4_axis_tdata , - - output wire m5_axis_tvalid , - output wire [B-1:0] m5_axis_tdata , - - output wire m6_axis_tvalid , - output wire [B-1:0] m6_axis_tdata , - - output wire m7_axis_tvalid , - output wire [B-1:0] m7_axis_tdata - ); - -/********************/ -/* Internal signals */ -/********************/ -// Total bits. -localparam BD = B + 1; -localparam BT = N*BD; - -// Input data to vector. -wire [B-1:0] din_data_v [8] ; -wire [7:0] din_valid_v ; - -// Output vector to data. -wire [B-1:0] dout_data_v [8] ; -wire [7:0] dout_valid_v ; - -wire fifo_wr_en ; -wire [BT-1:0] fifo_din ; -wire [BT-1:0] fifo_dout ; -wire fifo_full ; -wire fifo_empty ; - -/**********************/ -/* Begin Architecture */ -/**********************/ - -// Input data to vector. -assign din_data_v [0] = s0_axis_tdata ; -assign din_data_v [1] = s1_axis_tdata ; -assign din_data_v [2] = s2_axis_tdata ; -assign din_data_v [3] = s3_axis_tdata ; -assign din_data_v [4] = s4_axis_tdata ; -assign din_data_v [5] = s5_axis_tdata ; -assign din_data_v [6] = s6_axis_tdata ; -assign din_data_v [7] = s7_axis_tdata ; - -assign din_valid_v [0] = s0_axis_tvalid ; -assign din_valid_v [1] = s1_axis_tvalid ; -assign din_valid_v [2] = s2_axis_tvalid ; -assign din_valid_v [3] = s3_axis_tvalid ; -assign din_valid_v [4] = s4_axis_tvalid ; -assign din_valid_v [5] = s5_axis_tvalid ; -assign din_valid_v [6] = s6_axis_tvalid ; -assign din_valid_v [7] = s7_axis_tvalid ; - -// Output vector to data. -assign m0_axis_tdata = dout_data_v [0] ; -assign m1_axis_tdata = dout_data_v [1] ; -assign m2_axis_tdata = dout_data_v [2] ; -assign m3_axis_tdata = dout_data_v [3] ; -assign m4_axis_tdata = dout_data_v [4] ; -assign m5_axis_tdata = dout_data_v [5] ; -assign m6_axis_tdata = dout_data_v [6] ; -assign m7_axis_tdata = dout_data_v [7] ; - -assign m0_axis_tvalid = dout_valid_v [0] & ~fifo_empty; -assign m1_axis_tvalid = dout_valid_v [1] & ~fifo_empty; -assign m2_axis_tvalid = dout_valid_v [2] & ~fifo_empty; -assign m3_axis_tvalid = dout_valid_v [3] & ~fifo_empty; -assign m4_axis_tvalid = dout_valid_v [4] & ~fifo_empty; -assign m5_axis_tvalid = dout_valid_v [5] & ~fifo_empty; -assign m6_axis_tvalid = dout_valid_v [6] & ~fifo_empty; -assign m7_axis_tvalid = dout_valid_v [7] & ~fifo_empty; - -genvar i; -generate - for (i=0; i N_LOG2, - -- Data width. - B => B - ) - Port map ( - clk => clk , - ena => '1' , - enb => rd_en , - wea => mem_wea , - addra => std_logic_vector(wptr) , - addrb => std_logic_vector(rptr) , - dia => din , - dob => mem_dob - ); - --- Memory connections. -mem_wea <= wr_en when full_i = '0' else - '0'; - --- Full/empty signals. -full_i <= '1' when wptr = rptr - 1 else - '0'; -empty_i <= '1' when wptr = rptr else - '0'; - --- wr_clk registers. -process (clk) -begin - if ( rising_edge(clk) ) then - if ( rstn = '0' ) then - wptr <= (others => '0'); - rptr <= (others => '0'); - else - -- Write. - if ( wr_en = '1' and full_i = '0' ) then - -- Write data. - - -- Increment pointer. - wptr <= wptr + 1; - end if; - - -- Read. - if ( rd_en = '1' and empty_i = '0' ) then - -- Read data. - - -- Increment pointer. - rptr <= rptr + 1; - end if; - end if; - end if; -end process; - --- Assign outputs. -dout <= mem_dob; -full <= full_i; -empty <= empty_i; - -end rtl; - diff --git a/qick/firmware/ip/axis_cdcsync_v1/src/fifo/fifo_axi.vhd b/qick/firmware/ip/axis_cdcsync_v1/src/fifo/fifo_axi.vhd deleted file mode 100644 index e1f76f7..0000000 --- a/qick/firmware/ip/axis_cdcsync_v1/src/fifo/fifo_axi.vhd +++ /dev/null @@ -1,147 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo_axi is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo_axi; - -architecture rtl of fifo_axi is - --- FIFO. -component fifo is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end component; - --- FIFO read to AXI adapter. -component rd2axi is - Generic - ( - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- FIFO Read I/F. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (B-1 downto 0); - fifo_empty : in std_logic; - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - empty : out std_logic - ); -end component; - -signal rd_en_i : std_logic; -signal dout_i : std_logic_vector (B-1 downto 0); -signal empty_i : std_logic; - -begin - --- FIFO. -fifo_i : fifo - Generic map - ( - -- Data width. - B => B, - - -- Fifo depth. - N => N - ) - Port map - ( - rstn => rstn , - clk => clk , - - -- Write I/F. - wr_en => wr_en , - din => din , - - -- Read I/F. - rd_en => rd_en_i , - dout => dout_i , - - -- Flags. - full => full , - empty => empty_i - ); - --- FIFO read to AXI adapter. -rd2axi_i : rd2axi - Generic map - ( - -- Data width. - B => B - ) - Port map - ( - rstn => rstn , - clk => clk , - - -- FIFO Read I/F. - fifo_rd_en => rd_en_i , - fifo_dout => dout_i , - fifo_empty => empty_i , - - -- Read I/F. - rd_en => rd_en , - dout => dout , - empty => empty - ); - -end rtl; - diff --git a/qick/firmware/ip/axis_cdcsync_v1/src/fifo/fifo_dc.vhd b/qick/firmware/ip/axis_cdcsync_v1/src/fifo/fifo_dc.vhd deleted file mode 100644 index c214fae..0000000 --- a/qick/firmware/ip/axis_cdcsync_v1/src/fifo/fifo_dc.vhd +++ /dev/null @@ -1,291 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo_dc is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - wr_rstn : in std_logic; - wr_clk : in std_logic; - - rd_rstn : in std_logic; - rd_clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo_dc; - -architecture rtl of fifo_dc is - --- Number of bits of depth. -constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); - --- Binary to gray converter. -component bin2gray is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end component; - --- Gray to binary converter. -component gray2bin is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end component; - --- Vector synchronizer (only for gray coded). -component synchronizer_vect is - generic ( - -- Sync stages. - N : Integer := 2; - - -- Data width. - B : Integer := 8 - ); - port ( - rstn : in std_logic; - clk : in std_logic; - data_in : in std_logic_vector (B-1 downto 0); - data_out : out std_logic_vector (B-1 downto 0) - ); -end component; - --- Dual port BRAM. -component bram_dp is - Generic ( - -- Memory address size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - ena : in STD_LOGIC; - enb : in STD_LOGIC; - wea : in STD_LOGIC; - web : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR (N-1 downto 0); - addrb : in STD_LOGIC_VECTOR (N-1 downto 0); - dia : in STD_LOGIC_VECTOR (B-1 downto 0); - dib : in STD_LOGIC_VECTOR (B-1 downto 0); - doa : out STD_LOGIC_VECTOR (B-1 downto 0); - dob : out STD_LOGIC_VECTOR (B-1 downto 0) - ); -end component; - --- Pointers. -signal wptr : unsigned (N_LOG2-1 downto 0); -signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); -signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); -signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); -signal rptr : unsigned (N_LOG2-1 downto 0); -signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); -signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); -signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); - --- Memory signals. -signal mem_wea : std_logic; -signal mem_dib : std_logic_vector (B-1 downto 0); -signal mem_doa : std_logic_vector (B-1 downto 0); -signal mem_dob : std_logic_vector (B-1 downto 0); - --- Flags. -signal full_i : std_logic; -signal empty_i : std_logic; - -begin - --- wptr_i: binary to gray. -wptr_i : bin2gray - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => std_logic_vector(wptr), - dout => wptr_g - ); - --- wptr_g: write to read domain. -wptr_g_i : synchronizer_vect - generic map ( - -- Sync stages. - N => 2, - - -- Data width. - B => N_LOG2 - ) - port map ( - rstn => rd_rstn, - clk => rd_clk, - data_in => wptr_g, - data_out => wptr_gc - ); - --- wptr_gc_i -wptr_gc_i : gray2bin - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => wptr_gc, - dout => wptr_c - ); - --- rptr_i: binary to gray. -rptr_i : bin2gray - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => std_logic_vector(rptr), - dout => rptr_g - ); - --- rptr_g: read to write domain. -rptr_g_i : synchronizer_vect - generic map ( - -- Sync stages. - N => 2, - - -- Data width. - B => N_LOG2 - ) - port map ( - rstn => wr_rstn, - clk => wr_clk, - data_in => rptr_g, - data_out => rptr_gc - ); - --- rptr_gc_i -rptr_gc_i : gray2bin - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => rptr_gc, - dout => rptr_c - ); - --- FIFO memory. -mem_i : bram_dp - Generic map ( - -- Memory address size. - N => N_LOG2, - -- Data width. - B => B - ) - Port map ( - clka => wr_clk, - clkb => rd_clk, - ena => '1', - enb => rd_en, - wea => mem_wea, - web => '0', - addra => std_logic_vector(wptr), - addrb => std_logic_vector(rptr), - dia => din, - dib => mem_dib, - doa => mem_doa, - dob => mem_dob - ); --- Memory connections. -mem_wea <= wr_en when full_i = '0' else - '0'; -mem_dib <= (others => '0'); - --- Full/empty signals. -full_i <= '1' when wptr = unsigned(rptr_c) - 1 else - '0'; -empty_i <= '1' when unsigned(wptr_c) = rptr else - '0'; - --- wr_clk registers. -process (wr_clk) -begin - if ( rising_edge(wr_clk) ) then - if ( wr_rstn = '0' ) then - wptr <= (others => '0'); - else - -- Write. - if ( wr_en = '1' and full_i = '0' ) then - -- Write data. - - -- Increment pointer. - wptr <= wptr + 1; - end if; - end if; - end if; -end process; - --- rd_clk registers. -process (rd_clk) -begin - if ( rising_edge(rd_clk) ) then - if ( rd_rstn = '0' ) then - rptr <= (others => '0'); - else - -- Read. - if ( rd_en = '1' and empty_i = '0' ) then - -- Read data. - - -- Increment pointer. - rptr <= rptr + 1; - end if; - end if; - end if; -end process; - --- Assign outputs. -dout <= mem_dob; -full <= full_i; -empty <= empty_i; - -end rtl; diff --git a/qick/firmware/ip/axis_cdcsync_v1/src/fifo/fifo_dc_axi.vhd b/qick/firmware/ip/axis_cdcsync_v1/src/fifo/fifo_dc_axi.vhd deleted file mode 100644 index eb83d1a..0000000 --- a/qick/firmware/ip/axis_cdcsync_v1/src/fifo/fifo_dc_axi.vhd +++ /dev/null @@ -1,156 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo_dc_axi is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - wr_rstn : in std_logic; - wr_clk : in std_logic; - - rd_rstn : in std_logic; - rd_clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo_dc_axi; - -architecture rtl of fifo_dc_axi is - --- Dual-clock FIFO. -component fifo_dc is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - wr_rstn : in std_logic; - wr_clk : in std_logic; - - rd_rstn : in std_logic; - rd_clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end component; - --- FIFO read to AXI adapter. -component rd2axi is - Generic - ( - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- FIFO Read I/F. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (B-1 downto 0); - fifo_empty : in std_logic; - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - empty : out std_logic - ); -end component; - -signal rd_en_i : std_logic; -signal dout_i : std_logic_vector (B-1 downto 0); -signal empty_i : std_logic; - -begin - --- Dual-clock FIFO. -fifo_i : fifo_dc - Generic map - ( - -- Data width. - B => B, - - -- Fifo depth. - N => N - ) - Port map - ( - wr_rstn => wr_rstn , - wr_clk => wr_clk , - - rd_rstn => rd_rstn , - rd_clk => rd_clk , - - -- Write I/F. - wr_en => wr_en , - din => din , - - -- Read I/F. - rd_en => rd_en_i , - dout => dout_i , - - -- Flags. - full => full , - empty => empty_i - ); - --- FIFO read to AXI adapter. -rd2axi_i : rd2axi - Generic map - ( - -- Data width. - B => B - ) - Port map - ( - rstn => rd_rstn , - clk => rd_clk , - - -- FIFO Read I/F. - fifo_rd_en => rd_en_i , - fifo_dout => dout_i , - fifo_empty => empty_i , - - -- Read I/F. - rd_en => rd_en , - dout => dout , - empty => empty - ); - -end rtl; - diff --git a/qick/firmware/ip/axis_cdcsync_v1/src/fifo/gray2bin.vhd b/qick/firmware/ip/axis_cdcsync_v1/src/fifo/gray2bin.vhd deleted file mode 100644 index e23f8af..0000000 --- a/qick/firmware/ip/axis_cdcsync_v1/src/fifo/gray2bin.vhd +++ /dev/null @@ -1,37 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity gray2bin is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end gray2bin; - -architecture rtl of gray2bin is - -signal bin : std_logic_vector (B-1 downto 0); - -begin - --- MSB always match. -bin(B-1) <= din(B-1); - -GEN: for I in 0 to B-2 generate -begin - bin(I) <= bin(I+1) xor din(I); -end generate GEN; - --- Assign output. -dout <= bin; - -end rtl; - diff --git a/qick/firmware/ip/axis_cdcsync_v1/src/fifo/rd2axi.vhd b/qick/firmware/ip/axis_cdcsync_v1/src/fifo/rd2axi.vhd deleted file mode 100644 index babadc6..0000000 --- a/qick/firmware/ip/axis_cdcsync_v1/src/fifo/rd2axi.vhd +++ /dev/null @@ -1,138 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity rd2axi is - Generic - ( - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- FIFO Read I/F. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (B-1 downto 0); - fifo_empty : in std_logic; - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - empty : out std_logic - ); -end rd2axi; - -architecture rtl of rd2axi is - -type fsm_state is ( WAIT_EMPTY_ST, - READ_FIRST_ST, - READ_ST, - READ_LAST_ST); -signal current_state, next_state : fsm_state; - -signal wait_empty_state : std_logic; -signal read_first_state : std_logic; -signal read_state : std_logic; - -signal fifo_rd_en_i : std_logic; -signal empty_i : std_logic; - -begin - -process(clk) -begin - if (rising_edge(clk)) then - if (rstn = '0') then - current_state <= WAIT_EMPTY_ST; - else - current_state <= next_state; - end if; - end if; -end process; - --- Next state logic. -process(current_state, fifo_empty, rd_en) -begin - case current_state is - when WAIT_EMPTY_ST => - if (fifo_empty = '1') then - next_state <= WAIT_EMPTY_ST; - else - next_state <= READ_FIRST_ST; - end if; - - when READ_FIRST_ST => - next_state <= READ_ST; - - when READ_ST => - if (fifo_empty = '0') then - next_state <= READ_ST; - else - if (rd_en = '1') then - next_state <= WAIT_EMPTY_ST; - else - next_state <= READ_LAST_ST; - end if; - end if; - - when READ_LAST_ST => - if (rd_en = '0') then - next_state <= READ_LAST_ST; - else - next_state <= WAIT_EMPTY_ST; - end if; - - end case; -end process; - --- Output logic. -process(current_state) -begin -wait_empty_state <= '0'; -read_first_state <= '0'; -read_state <= '0'; -empty_i <= '0'; - case current_state is - when WAIT_EMPTY_ST => - wait_empty_state <= '1'; - read_first_state <= '0'; - read_state <= '0'; - empty_i <= '1'; - - when READ_FIRST_ST => - wait_empty_state <= '0'; - read_first_state <= '1'; - read_state <= '0'; - empty_i <= '1'; - - when READ_ST => - wait_empty_state <= '0'; - read_first_state <= '0'; - read_state <= '1'; - empty_i <= '0'; - - when READ_LAST_ST => - wait_empty_state <= '0'; - read_first_state <= '0'; - read_state <= '0'; - empty_i <= '0'; - - end case; -end process; - --- FIFO Read enable signal. -fifo_rd_en_i <= read_first_state or (read_state and rd_en); - --- Assign outputs. -fifo_rd_en <= fifo_rd_en_i; --- TODO: add register to freeze last value. -dout <= fifo_dout when empty_i = '0' else - (others => '0'); -empty <= empty_i; - -end rtl; - diff --git a/qick/firmware/ip/axis_cdcsync_v1/src/fifo/synchronizer_vect.vhd b/qick/firmware/ip/axis_cdcsync_v1/src/fifo/synchronizer_vect.vhd deleted file mode 100644 index 2fbb696..0000000 --- a/qick/firmware/ip/axis_cdcsync_v1/src/fifo/synchronizer_vect.vhd +++ /dev/null @@ -1,49 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - --- This block is intended to use to sync gray coded vectors. - --- NOTE: Do not use with generic vector data, as it may result --- in corrupted re-sync data. - -entity synchronizer_vect is - generic ( - -- Sync stages. - N : Integer := 2; - - -- Data width. - B : Integer := 8 - ); - port ( - rstn : in std_logic; - clk : in std_logic; - data_in : in std_logic_vector (B-1 downto 0); - data_out : out std_logic_vector (B-1 downto 0) - ); -end synchronizer_vect; - -architecture rtl of synchronizer_vect is - --- Internal register. -type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); -signal data_int_reg : reg_t; - -begin - -process(clk) -begin - if (rising_edge(clk)) then - if (rstn = '0') then - data_int_reg <= (others => (others => '0')); -- 1 FF. - else - data_int_reg <= data_int_reg(N-2 downto 0) & data_in; - end if; - end if; -end process; - --- Assign output. -data_out <= data_int_reg(N-1); - -end rtl; - diff --git a/qick/firmware/ip/axis_cdcsync_v1/src/tb.sv b/qick/firmware/ip/axis_cdcsync_v1/src/tb.sv deleted file mode 100644 index 3a74097..0000000 --- a/qick/firmware/ip/axis_cdcsync_v1/src/tb.sv +++ /dev/null @@ -1,240 +0,0 @@ -module tb; - -// Number of inputs/outputs. -parameter N = 8 ; - -// Number of data bits. -parameter B = 8 ; - - -// S_AXIS for input data. -reg s_axis_aresetn ; -reg s_axis_aclk ; - -wire s0_axis_tready ; -reg s0_axis_tvalid ; -reg [B-1:0] s0_axis_tdata ; - -wire s1_axis_tready ; -reg s1_axis_tvalid ; -reg [B-1:0] s1_axis_tdata ; - -wire s2_axis_tready ; -reg s2_axis_tvalid ; -reg [B-1:0] s2_axis_tdata ; - -wire s3_axis_tready ; -reg s3_axis_tvalid ; -reg [B-1:0] s3_axis_tdata ; - -wire s4_axis_tready ; -reg s4_axis_tvalid ; -reg [B-1:0] s4_axis_tdata ; - -wire s5_axis_tready ; -reg s5_axis_tvalid ; -reg [B-1:0] s5_axis_tdata ; - -wire s6_axis_tready ; -reg s6_axis_tvalid ; -reg [B-1:0] s6_axis_tdata ; - -wire s7_axis_tready ; -reg s7_axis_tvalid ; -reg [B-1:0] s7_axis_tdata ; - -// M_AXIS for output data. -reg m_axis_aresetn ; -reg m_axis_aclk ; - -wire m0_axis_tvalid ; -wire[B-1:0] m0_axis_tdata ; - -wire m1_axis_tvalid ; -wire[B-1:0] m1_axis_tdata ; - -wire m2_axis_tvalid ; -wire[B-1:0] m2_axis_tdata ; - -wire m3_axis_tvalid ; -wire[B-1:0] m3_axis_tdata ; - -wire m4_axis_tvalid ; -wire[B-1:0] m4_axis_tdata ; - -wire m5_axis_tvalid ; -wire[B-1:0] m5_axis_tdata ; - -wire m6_axis_tvalid ; -wire[B-1:0] m6_axis_tdata ; - -wire m7_axis_tvalid ; -wire[B-1:0] m7_axis_tdata ; - -// DUT. -axis_cdcsync_v1 - #( - // Number of inputs/outputs. - .N(N), - - // Number of data bits. - .B(B) - ) - DUT - ( - // S_AXIS for input data. - .s_axis_aresetn , - .s_axis_aclk , - - .s0_axis_tready , - .s0_axis_tvalid , - .s0_axis_tdata , - - .s1_axis_tready , - .s1_axis_tvalid , - .s1_axis_tdata , - - .s2_axis_tready , - .s2_axis_tvalid , - .s2_axis_tdata , - - .s3_axis_tready , - .s3_axis_tvalid , - .s3_axis_tdata , - - .s4_axis_tready , - .s4_axis_tvalid , - .s4_axis_tdata , - - .s5_axis_tready , - .s5_axis_tvalid , - .s5_axis_tdata , - - .s6_axis_tready , - .s6_axis_tvalid , - .s6_axis_tdata , - - .s7_axis_tready , - .s7_axis_tvalid , - .s7_axis_tdata , - - // M_AXIS for output data. - .m_axis_aresetn , - .m_axis_aclk , - - .m0_axis_tvalid , - .m0_axis_tdata , - - .m1_axis_tvalid , - .m1_axis_tdata , - - .m2_axis_tvalid , - .m2_axis_tdata , - - .m3_axis_tvalid , - .m3_axis_tdata , - - .m4_axis_tvalid , - .m4_axis_tdata , - - .m5_axis_tvalid , - .m5_axis_tdata , - - .m6_axis_tvalid , - .m6_axis_tdata , - - .m7_axis_tvalid , - .m7_axis_tdata - ); - -// Main TB. -initial begin - s_axis_aresetn <= 0; - m_axis_aresetn <= 0; - s0_axis_tvalid <= 0; - s0_axis_tdata <= 0; - s1_axis_tvalid <= 0; - s1_axis_tdata <= 0; - s2_axis_tvalid <= 0; - s2_axis_tdata <= 0; - s3_axis_tvalid <= 0; - s3_axis_tdata <= 0; - s4_axis_tvalid <= 0; - s4_axis_tdata <= 0; - s5_axis_tvalid <= 0; - s5_axis_tdata <= 0; - s6_axis_tvalid <= 0; - s6_axis_tdata <= 0; - s7_axis_tvalid <= 0; - s7_axis_tdata <= 0; - #300; - s_axis_aresetn <= 1; - m_axis_aresetn <= 1; - - #1000; - - @(posedge s_axis_aclk); - s0_axis_tvalid <= 1'b1; - s0_axis_tdata <= $random; - - @(posedge s_axis_aclk); - s0_axis_tvalid <= 1'b0; - - #200; - - @(posedge s_axis_aclk); - s1_axis_tvalid <= 1'b1; - s1_axis_tdata <= $random; - - @(posedge s_axis_aclk); - s1_axis_tvalid <= 1'b0; - - for (int i=0; i<5; i=i+1) begin - @(posedge s_axis_aclk); - s0_axis_tvalid <= 1'b1; - s0_axis_tdata <= $random; - s1_axis_tvalid <= 1'b1; - s1_axis_tdata <= $random; - end - - @(posedge s_axis_aclk); - s1_axis_tvalid <= 1'b0; - - for (int i=0; i<7; i=i+1) begin - @(posedge s_axis_aclk); - s0_axis_tvalid <= 1'b1; - s0_axis_tdata <= $random; - end - - @(posedge s_axis_aclk); - s0_axis_tvalid <= 1'b0; - - #2000; - - @(posedge s_axis_aclk); - s7_axis_tvalid <= 1'b1; - s7_axis_tdata <= $random; - - @(posedge s_axis_aclk); - s7_axis_tvalid <= 1'b0; - -end - -// s_axis_aclk; -always begin - s_axis_aclk <= 0; - #7; - s_axis_aclk <= 1; - #7; -end - -// m_axis_aclk; -always begin - m_axis_aclk <= 0; - #3; - m_axis_aclk <= 1; - #3; -end - -endmodule - diff --git a/qick/firmware/ip/axis_cdcsync_v1/xgui/axis_cdcsync_v1_v1_0.tcl b/qick/firmware/ip/axis_cdcsync_v1/xgui/axis_cdcsync_v1_v1_0.tcl deleted file mode 100644 index f41c028..0000000 --- a/qick/firmware/ip/axis_cdcsync_v1/xgui/axis_cdcsync_v1_v1_0.tcl +++ /dev/null @@ -1,40 +0,0 @@ -# Definitional proc to organize widgets for parameters. -proc init_gui { IPINST } { - ipgui::add_param $IPINST -name "Component_Name" - #Adding Page - set Page_0 [ipgui::add_page $IPINST -name "Page 0"] - ipgui::add_param $IPINST -name "B" -parent ${Page_0} - ipgui::add_param $IPINST -name "N" -parent ${Page_0} -widget comboBox - - -} - -proc update_PARAM_VALUE.B { PARAM_VALUE.B } { - # Procedure called to update B when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.B { PARAM_VALUE.B } { - # Procedure called to validate B - return true -} - -proc update_PARAM_VALUE.N { PARAM_VALUE.N } { - # Procedure called to update N when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.N { PARAM_VALUE.N } { - # Procedure called to validate N - return true -} - - -proc update_MODELPARAM_VALUE.N { MODELPARAM_VALUE.N PARAM_VALUE.N } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.N}] ${MODELPARAM_VALUE.N} -} - -proc update_MODELPARAM_VALUE.B { MODELPARAM_VALUE.B PARAM_VALUE.B } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.B}] ${MODELPARAM_VALUE.B} -} - diff --git a/qick/firmware/ip/axis_constant/component.xml b/qick/firmware/ip/axis_constant/component.xml deleted file mode 100644 index 7347f1e..0000000 --- a/qick/firmware/ip/axis_constant/component.xml +++ /dev/null @@ -1,364 +0,0 @@ - - - user.org - user - axis_constant - 1.0 - - - m_axis - - - - - - - TDATA - - - m_axis_tdata - - - - - TSTRB - - - m_axis_tstrb - - - - - TLAST - - - m_axis_tlast - - - - - TVALID - - - m_axis_tvalid - - - - - TREADY - - - m_axis_tready - - - - - - m_axis_aresetn - - - - - - - RST - - - m_axis_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - m_axis_aclk - - - - - - - CLK - - - m_axis_aclk - - - - - - ASSOCIATED_BUSIF - m_axis - - - ASSOCIATED_RESET - m_axis_aresetn - - - - - - - - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis - VHDL - axis_constant - - xilinx_anylanguagesynthesis_view_fileset - - - - viewChecksum - 9417364f - - - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - VHDL - axis_constant - - xilinx_anylanguagebehavioralsimulation_view_fileset - - - - viewChecksum - 9417364f - - - - - xilinx_xpgui - UI Layout - :vivado.xilinx.com:xgui.ui - - xilinx_xpgui_view_fileset - - - - viewChecksum - 35ebc586 - - - - - - - m_axis_aclk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m_axis_aresetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m_axis_tready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 1 - - - - - m_axis_tdata - - out - - 15 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m_axis_tstrb - - out - - 1 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m_axis_tlast - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m_axis_tvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - - DATA_WIDTH - Data Width - 16 - - - - - - choice_list_74b5137e - ACTIVE_HIGH - ACTIVE_LOW - - - - - xilinx_anylanguagesynthesis_view_fileset - - src/axis_constant.vhd - vhdlSource - CHECKSUM_9417364f - - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - src/axis_constant.vhd - vhdlSource - - - - xilinx_xpgui_view_fileset - - xgui/axis_constant_v1_0.tcl - tclSource - CHECKSUM_35ebc586 - XGUI_VERSION_2 - - - - AXIS Constant IP to properly terminate inputs. - - - DATA_WIDTH - Data Width - 16 - - - Component_Name - axis_constant_v1_0 - - - - - - virtex7 - qvirtex7 - kintex7 - kintex7l - qkintex7 - qkintex7l - akintex7 - artix7 - artix7l - aartix7 - qartix7 - zynq - qzynq - azynq - spartan7 - aspartan7 - virtexu - zynquplus - virtexuplus - virtexuplusHBM - kintexuplus - kintexu - - - /UserIP - - AXIS Constant - package_project - 2 - 2021-06-10T13:34:21Z - - /home/lstefana/v19.1/ip/axis_constant - /home/lstefana/v19.1/ip/axis_constant - /home/lstefana/v19.1/ip/axis_constant - /home/lstefana/v19.1/ip/axis_constant - /home/lstefana/v19.1/ip/axis_constant - /home/lstefana/v19.1/ip/axis_constant - /home/lstefana/v19.1/ip/axis_constant - /home/lstefana/v19.1/ip/axis_constant - - - - 2019.1 - - - - - - - - diff --git a/qick/firmware/ip/axis_constant/src/axis_constant.vhd b/qick/firmware/ip/axis_constant/src/axis_constant.vhd deleted file mode 100644 index 359a234..0000000 --- a/qick/firmware/ip/axis_constant/src/axis_constant.vhd +++ /dev/null @@ -1,34 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity axis_constant is - generic - ( - -- Data width. - DATA_WIDTH : Integer := 16 - ); - port - ( - -- AXIS Slave I/F. - m_axis_aclk : in std_logic; - m_axis_aresetn : in std_logic; - m_axis_tready : in std_logic; - m_axis_tdata : out std_logic_vector(DATA_WIDTH-1 downto 0); - m_axis_tstrb : out std_logic_vector((DATA_WIDTH/8)-1 downto 0); - m_axis_tlast : out std_logic; - m_axis_tvalid : out std_logic - ); -end axis_constant; - -architecture rtl of axis_constant is - -begin - -m_axis_tdata <= (others => '0'); -m_axis_tstrb <= (others => '0'); -m_axis_tlast <= '0'; -m_axis_tvalid <= '0'; - -end rtl; - diff --git a/qick/firmware/ip/axis_constant/xgui/axis_constant_v1_0.tcl b/qick/firmware/ip/axis_constant/xgui/axis_constant_v1_0.tcl deleted file mode 100644 index 55a2622..0000000 --- a/qick/firmware/ip/axis_constant/xgui/axis_constant_v1_0.tcl +++ /dev/null @@ -1,25 +0,0 @@ -# Definitional proc to organize widgets for parameters. -proc init_gui { IPINST } { - ipgui::add_param $IPINST -name "Component_Name" - #Adding Page - set Page_0 [ipgui::add_page $IPINST -name "Page 0"] - ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${Page_0} - - -} - -proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { - # Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { - # Procedure called to validate DATA_WIDTH - return true -} - - -proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH} -} - diff --git a/qick/firmware/ip/axis_constant_iq/component.xml b/qick/firmware/ip/axis_constant_iq/component.xml deleted file mode 100644 index 283f0af..0000000 --- a/qick/firmware/ip/axis_constant_iq/component.xml +++ /dev/null @@ -1,886 +0,0 @@ - - - user.org - user - axis_constant_iq - 1.0 - - - m_axis - - - - - - - TDATA - - - m_axis_tdata - - - - - TVALID - - - m_axis_tvalid - - - - - - s_axi - - - - - - - - - AWADDR - - - s_axi_awaddr - - - - - AWPROT - - - s_axi_awprot - - - - - AWVALID - - - s_axi_awvalid - - - - - AWREADY - - - s_axi_awready - - - - - WDATA - - - s_axi_wdata - - - - - WSTRB - - - s_axi_wstrb - - - - - WVALID - - - s_axi_wvalid - - - - - WREADY - - - s_axi_wready - - - - - BRESP - - - s_axi_bresp - - - - - BVALID - - - s_axi_bvalid - - - - - BREADY - - - s_axi_bready - - - - - ARADDR - - - s_axi_araddr - - - - - ARPROT - - - s_axi_arprot - - - - - ARVALID - - - s_axi_arvalid - - - - - ARREADY - - - s_axi_arready - - - - - RDATA - - - s_axi_rdata - - - - - RRESP - - - s_axi_rresp - - - - - RVALID - - - s_axi_rvalid - - - - - RREADY - - - s_axi_rready - - - - - - m_axis_aresetn - - - - - - - RST - - - m_axis_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - s_axi_aresetn - - - - - - - RST - - - s_axi_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - m_axis_aclk - - - - - - - CLK - - - m_axis_aclk - - - - - - ASSOCIATED_BUSIF - m_axis - - - ASSOCIATED_RESET - m_axis_aresetn - - - - - s_axi_aclk - - - - - - - CLK - - - s_axi_aclk - - - - - - ASSOCIATED_BUSIF - s_axi - - - ASSOCIATED_RESET - s_axi_aresetn - - - - - - - s_axi - - reg0 - 0 - 64 - 32 - register - - - - - - - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis - VHDL - axis_constant_iq - - xilinx_anylanguagesynthesis_view_fileset - - - - viewChecksum - 05173ec9 - - - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - VHDL - axis_constant_iq - - xilinx_anylanguagebehavioralsimulation_view_fileset - - - - viewChecksum - 05173ec9 - - - - - xilinx_xpgui - UI Layout - :vivado.xilinx.com:xgui.ui - - xilinx_xpgui_view_fileset - - - - viewChecksum - 2c3a0701 - - - - - - - s_axi_aclk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_aresetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_awaddr - - in - - 5 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_awprot - - in - - 2 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_awvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_awready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_wdata - - in - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_wstrb - - in - - 3 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 1 - - - - - s_axi_wvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_wready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_bresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_bvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_bready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_araddr - - in - - 5 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_arprot - - in - - 2 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_arvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_arready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_rdata - - out - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_rresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_rvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_rready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - m_axis_aclk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m_axis_aresetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m_axis_tdata - - out - - 127 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m_axis_tvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - - B - B - 16 - - - N - N - 4 - - - - - - choice_list_74b5137e - ACTIVE_HIGH - ACTIVE_LOW - - - - - xilinx_anylanguagesynthesis_view_fileset - - src/axi_slv.vhd - vhdlSource - - - src/synchronizer_n.vhd - vhdlSource - - - src/axis_constant_iq.vhd - vhdlSource - CHECKSUM_d08b65cf - - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - src/axi_slv.vhd - vhdlSource - - - src/synchronizer_n.vhd - vhdlSource - - - src/axis_constant_iq.vhd - vhdlSource - - - - xilinx_xpgui_view_fileset - - xgui/axis_constant_iq_v1_0.tcl - tclSource - CHECKSUM_2c3a0701 - XGUI_VERSION_2 - - - - AXIS Constant IQ with parallel outputs for DAC. - - - B - B - 16 - - - N - N - 4 - - - Component_Name - axis_constant_iq_v1_0 - - - - - - virtex7 - qvirtex7 - kintex7 - kintex7l - qkintex7 - qkintex7l - akintex7 - artix7 - artix7l - aartix7 - qartix7 - zynq - qzynq - azynq - spartan7 - aspartan7 - virtexu - zynquplus - virtexuplus - virtexuplusHBM - kintexuplus - kintexu - - - /UserIP - - AXIS Constant IQ - package_project - 2 - 2021-09-02T14:55:11Z - - /home/lstefana/v19.1/zcu111/fft_avg_ad_da/ip/axis_constant_iq - /home/lstefana/v19.1/zcu111/fft_avg_ad_da/ip/axis_constant_iq - /home/lstefana/v19.1/zcu111/fft_avg_ad_da/ip/axis_constant_iq - /home/lstefana/v19.1/zcu111/fft_avg_ad_da/ip/axis_constant_iq - /home/lstefana/v19.1/zcu111/fft_avg_ad_da/ip/axis_constant_iq - /home/lstefana/v19.1/zcu111/fft_avg_ad_da/ip/axis_constant_iq - /home/lstefana/v19.1/zcu111/fft_avg_ad_da/ip/axis_constant_iq - /home/lstefana/v19.1/zcu111/fft_avg_ad_da/ip/axis_constant_iq - /home/lstefana/v19.1/zcu111/fft_avg_ad_da/ip/axis_constant_iq - - - - 2019.1 - - - - - - - - - diff --git a/qick/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.veo b/qick/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.veo deleted file mode 100644 index 5f33135..0000000 --- a/qick/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.veo +++ /dev/null @@ -1,85 +0,0 @@ -// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -// IP VLNV: xilinx.com:ip:axi_vip:1.1 -// IP Revision: 5 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -axi_mst_0 your_instance_name ( - .aclk(aclk), // input wire aclk - .aresetn(aresetn), // input wire aresetn - .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr - .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot - .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid - .m_axi_awready(m_axi_awready), // input wire m_axi_awready - .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata - .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb - .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid - .m_axi_wready(m_axi_wready), // input wire m_axi_wready - .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp - .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid - .m_axi_bready(m_axi_bready), // output wire m_axi_bready - .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr - .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot - .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid - .m_axi_arready(m_axi_arready), // input wire m_axi_arready - .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata - .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp - .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid - .m_axi_rready(m_axi_rready) // output wire m_axi_rready -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file axi_mst_0.v when simulating -// the core, axi_mst_0. When compiling the wrapper file, be sure to -// reference the Verilog simulation library. - diff --git a/qick/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.vho b/qick/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.vho deleted file mode 100644 index 5c4d9a9..0000000 --- a/qick/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.vho +++ /dev/null @@ -1,115 +0,0 @@ --- (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:axi_vip:1.1 --- IP Revision: 5 - --- The following code must appear in the VHDL architecture header. - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT axi_mst_0 - PORT ( - aclk : IN STD_LOGIC; - aresetn : IN STD_LOGIC; - m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - m_axi_awvalid : OUT STD_LOGIC; - m_axi_awready : IN STD_LOGIC; - m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - m_axi_wvalid : OUT STD_LOGIC; - m_axi_wready : IN STD_LOGIC; - m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - m_axi_bvalid : IN STD_LOGIC; - m_axi_bready : OUT STD_LOGIC; - m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - m_axi_arvalid : OUT STD_LOGIC; - m_axi_arready : IN STD_LOGIC; - m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - m_axi_rvalid : IN STD_LOGIC; - m_axi_rready : OUT STD_LOGIC - ); -END COMPONENT; --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : axi_mst_0 - PORT MAP ( - aclk => aclk, - aresetn => aresetn, - m_axi_awaddr => m_axi_awaddr, - m_axi_awprot => m_axi_awprot, - m_axi_awvalid => m_axi_awvalid, - m_axi_awready => m_axi_awready, - m_axi_wdata => m_axi_wdata, - m_axi_wstrb => m_axi_wstrb, - m_axi_wvalid => m_axi_wvalid, - m_axi_wready => m_axi_wready, - m_axi_bresp => m_axi_bresp, - m_axi_bvalid => m_axi_bvalid, - m_axi_bready => m_axi_bready, - m_axi_araddr => m_axi_araddr, - m_axi_arprot => m_axi_arprot, - m_axi_arvalid => m_axi_arvalid, - m_axi_arready => m_axi_arready, - m_axi_rdata => m_axi_rdata, - m_axi_rresp => m_axi_rresp, - m_axi_rvalid => m_axi_rvalid, - m_axi_rready => m_axi_rready - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file axi_mst_0.vhd when simulating --- the core, axi_mst_0. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/qick/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.xci b/qick/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.xci deleted file mode 100644 index 34f0b12..0000000 --- a/qick/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.xci +++ /dev/null @@ -1,187 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - axi_mst_0 - - - ACTIVE_LOW - - 100000000 - 0 - 0.000 - 32 - 0 - 0 - 0 - - 32 - 100000000 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 32 - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 0 - 2 - 32 - 0 - 0 - 0 - 32 - 0 - 0 - 32 - 0 - 0 - 0 - axi_mst_0 - 32 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 0 - 0 - 1 - 0 - MASTER - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - virtex7 - - - xc7vx485t - ffg1157 - VERILOG - - MIXED - -1 - - - TRUE - TRUE - IP_Flow - 5 - TRUE - . - - . - 2019.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/qick/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.xml b/qick/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.xml deleted file mode 100644 index 0a6987b..0000000 --- a/qick/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.xml +++ /dev/null @@ -1,4751 +0,0 @@ - - - xilinx.com - customized_ip - axi_mst_0 - 1.0 - - - M_AXI - - - - - - - - - ARADDR - - - m_axi_araddr - - - - - ARBURST - - - m_axi_arburst - - - - - ARCACHE - - - m_axi_arcache - - - - - ARID - - - m_axi_arid - - - - - ARLEN - - - m_axi_arlen - - - - - ARLOCK - - - m_axi_arlock - - - - - ARPROT - - - m_axi_arprot - - - - - ARQOS - - - m_axi_arqos - - - - - ARREADY - - - m_axi_arready - - - - - ARREGION - - - m_axi_arregion - - - - - ARSIZE - - - m_axi_arsize - - - - - ARUSER - - - m_axi_aruser - - - - - ARVALID - - - m_axi_arvalid - - - - - AWADDR - - - m_axi_awaddr - - - - - AWBURST - - - m_axi_awburst - - - - - AWCACHE - - - m_axi_awcache - - - - - AWID - - - m_axi_awid - - - - - AWLEN - - - m_axi_awlen - - - - - AWLOCK - - - m_axi_awlock - - - - - AWPROT - - - m_axi_awprot - - - - - AWQOS - - - m_axi_awqos - - - - - AWREADY - - - m_axi_awready - - - - - AWREGION - - - m_axi_awregion - - - - - AWSIZE - - - m_axi_awsize - - - - - AWUSER - - - m_axi_awuser - - - - - AWVALID - - - m_axi_awvalid - - - - - BID - - - m_axi_bid - - - - - BREADY - - - m_axi_bready - - - - - BRESP - - - m_axi_bresp - - - - - BUSER - - - m_axi_buser - - - - - BVALID - - - m_axi_bvalid - - - - - RDATA - - - m_axi_rdata - - - - - RID - - - m_axi_rid - - - - - RLAST - - - m_axi_rlast - - - - - RREADY - - - m_axi_rready - - - - - RRESP - - - m_axi_rresp - - - - - RUSER - - - m_axi_ruser - - - - - RVALID - - - m_axi_rvalid - - - - - WDATA - - - m_axi_wdata - - - - - WID - - - m_axi_wid - - - - - WLAST - - - m_axi_wlast - - - - - WREADY - - - m_axi_wready - - - - - WSTRB - - - m_axi_wstrb - - - - - WUSER - - - m_axi_wuser - - - - - WVALID - - - m_axi_wvalid - - - - - - DATA_WIDTH - 32 - - - simulation.tlm - - - - - PROTOCOL - AXI4LITE - - - simulation.tlm - - - - - FREQ_HZ - 100000000 - - - simulation.tlm - - - - - ID_WIDTH - 0 - - - simulation.tlm - - - - - ADDR_WIDTH - 32 - - - simulation.tlm - - - - - AWUSER_WIDTH - 0 - - - simulation.tlm - - - - - ARUSER_WIDTH - 0 - - - simulation.tlm - - - - - WUSER_WIDTH - 0 - - - simulation.tlm - - - - - RUSER_WIDTH - 0 - - - simulation.tlm - - - - - BUSER_WIDTH - 0 - - - simulation.tlm - - - - - READ_WRITE_MODE - READ_WRITE - - - simulation.tlm - - - - - HAS_BURST - 0 - - - simulation.tlm - - - - - HAS_LOCK - 0 - - - simulation.tlm - - - - - HAS_PROT - 1 - - - simulation.tlm - - - - - HAS_CACHE - 0 - - - simulation.tlm - - - - - HAS_QOS - 0 - - - simulation.tlm - - - - - HAS_REGION - 0 - - - simulation.tlm - - - - - HAS_WSTRB - 1 - - - simulation.tlm - - - - - HAS_BRESP - 1 - - - simulation.tlm - - - - - HAS_RRESP - 1 - - - simulation.tlm - - - - - SUPPORTS_NARROW_BURST - 0 - - - simulation.tlm - - - - - NUM_READ_OUTSTANDING - 1 - - - simulation.tlm - - - - - NUM_WRITE_OUTSTANDING - 1 - - - simulation.tlm - - - - - MAX_BURST_LENGTH - 1 - - - simulation.tlm - - - - - PHASE - 0.000 - - - simulation.tlm - - - - - CLK_DOMAIN - - - - simulation.tlm - - - - - NUM_READ_THREADS - 1 - - - simulation.tlm - - - - - NUM_WRITE_THREADS - 1 - - - simulation.tlm - - - - - RUSER_BITS_PER_BYTE - 0 - - - simulation.tlm - - - - - WUSER_BITS_PER_BYTE - 0 - - - simulation.tlm - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - S_AXI - - - - - - - ARADDR - - - s_axi_araddr - - - - - ARBURST - - - s_axi_arburst - - - - - ARCACHE - - - s_axi_arcache - - - - - ARID - - - s_axi_arid - - - - - ARLEN - - - s_axi_arlen - - - - - ARLOCK - - - s_axi_arlock - - - - - ARPROT - - - s_axi_arprot - - - - - ARQOS - - - s_axi_arqos - - - - - ARREADY - - - s_axi_arready - - - - - ARREGION - - - s_axi_arregion - - - - - ARSIZE - - - s_axi_arsize - - - - - ARUSER - - - s_axi_aruser - - - - - ARVALID - - - s_axi_arvalid - - - - - AWADDR - - - s_axi_awaddr - - - - - AWBURST - - - s_axi_awburst - - - - - AWCACHE - - - s_axi_awcache - - - - - AWID - - - s_axi_awid - - - - - AWLEN - - - s_axi_awlen - - - - - AWLOCK - - - s_axi_awlock - - - - - AWPROT - - - s_axi_awprot - - - - - AWQOS - - - s_axi_awqos - - - - - AWREADY - - - s_axi_awready - - - - - AWREGION - - - s_axi_awregion - - - - - AWSIZE - - - s_axi_awsize - - - - - AWUSER - - - s_axi_awuser - - - - - AWVALID - - - s_axi_awvalid - - - - - BID - - - s_axi_bid - - - - - BREADY - - - s_axi_bready - - - - - BRESP - - - s_axi_bresp - - - - - BUSER - - - s_axi_buser - - - - - BVALID - - - s_axi_bvalid - - - - - RDATA - - - s_axi_rdata - - - - - RID - - - s_axi_rid - - - - - RLAST - - - s_axi_rlast - - - - - RREADY - - - s_axi_rready - - - - - RRESP - - - s_axi_rresp - - - - - RUSER - - - s_axi_ruser - - - - - RVALID - - - s_axi_rvalid - - - - - WDATA - - - s_axi_wdata - - - - - WID - - - s_axi_wid - - - - - WLAST - - - s_axi_wlast - - - - - WREADY - - - s_axi_wready - - - - - WSTRB - - - s_axi_wstrb - - - - - WUSER - - - s_axi_wuser - - - - - WVALID - - - s_axi_wvalid - - - - - - DATA_WIDTH - 1 - - - simulation.tlm - - - - - PROTOCOL - AXI4LITE - - - simulation.tlm - - - - - FREQ_HZ - 100000000 - - - simulation.tlm - - - - - ID_WIDTH - 0 - - - simulation.tlm - - - - - ADDR_WIDTH - 1 - - - simulation.tlm - - - - - AWUSER_WIDTH - 0 - - - simulation.tlm - - - - - ARUSER_WIDTH - 0 - - - simulation.tlm - - - - - WUSER_WIDTH - 0 - - - simulation.tlm - - - - - RUSER_WIDTH - 0 - - - simulation.tlm - - - - - BUSER_WIDTH - 0 - - - simulation.tlm - - - - - READ_WRITE_MODE - READ_WRITE - - - simulation.tlm - - - - - HAS_BURST - 0 - - - simulation.tlm - - - - - HAS_LOCK - 0 - - - simulation.tlm - - - - - HAS_PROT - 0 - - - simulation.tlm - - - - - HAS_CACHE - 0 - - - simulation.tlm - - - - - HAS_QOS - 0 - - - simulation.tlm - - - - - HAS_REGION - 0 - - - simulation.tlm - - - - - HAS_WSTRB - 0 - - - simulation.tlm - - - - - HAS_BRESP - 0 - - - simulation.tlm - - - - - HAS_RRESP - 0 - - - simulation.tlm - - - - - SUPPORTS_NARROW_BURST - 0 - - - simulation.tlm - - - - - NUM_READ_OUTSTANDING - 1 - - - simulation.tlm - - - - - NUM_WRITE_OUTSTANDING - 1 - - - simulation.tlm - - - - - MAX_BURST_LENGTH - 1 - - - simulation.tlm - - - - - PHASE - 0.000 - - - simulation.tlm - - - - - CLK_DOMAIN - - - - simulation.tlm - - - - - NUM_READ_THREADS - 1 - - - simulation.tlm - - - - - NUM_WRITE_THREADS - 1 - - - simulation.tlm - - - - - RUSER_BITS_PER_BYTE - 0 - - - simulation.tlm - - - - - WUSER_BITS_PER_BYTE - 0 - - - simulation.tlm - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - RESET - - - - - - - RST - - - aresetn - - - - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - ACLKEN - - - - - - - CE - - - aclken - - - - - - POLARITY - ACTIVE_LOW - - - none - - - - - - - - false - - - - - - CLOCK - - - - - - - CLK - - - aclk - - - - - - ASSOCIATED_BUSIF - M_AXI:S_AXI - - - ASSOCIATED_RESET - aresetn - - - FREQ_HZ - 100000000 - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - M_AXI_TLM - - - - - - - AXIMM_READ_SOCKET - - - M_INITIATOR_rd_socket - - - - - AXIMM_WRITE_SOCKET - - - M_INITIATOR_wr_socket - - - - - - S_AXI_TLM - - - - - - - AXIMM_READ_SOCKET - - - S_TARGET_rd_socket - - - - - AXIMM_WRITE_SOCKET - - - S_TARGET_wr_socket - - - - - - - - Master_AXI - 4294967296 - 32 - - - - true - - - - - - - - S_AXI - - Reg - 0 - 65536 - 32 - read-write - - - - false - - - - - - - - - - xilinx_veriloginstantiationtemplate - Verilog Instantiation Template - verilogSource:vivado.xilinx.com:synthesis.template - verilog - - xilinx_veriloginstantiationtemplate_view_fileset - - - - GENtimestamp - Wed Apr 08 16:47:30 UTC 2020 - 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- - sysc/axi_vip.h - systemCSource - true - axi_vip_v1_1_5 - - - - xilinx_verilogsimulationwrapper_view_fileset - - sim/axi_mst_0.sv - systemVerilogSource - xil_defaultlib - - - - xilinx_systemcsimulationwrapper_view_fileset - - sim/axi_mst_0_sc.h - systemCSource - true - - - sim/axi_mst_0_sc.cpp - systemCSource - - - sim/axi_mst_0.h - systemCSource - true - - - sim/axi_mst_0.cpp - systemCSource - - - sim/axi_mst_0_stub.sv - systemVerilogSource - - - - The AXI Verification IP. - - - Component_Name - Component Name - axi_mst_0 - - - PROTOCOL - PROTOCOL - AXI4LITE - - - READ_WRITE_MODE - READ_WRITE MODE - READ_WRITE - - - INTERFACE_MODE - INTERFACE MODE - MASTER - - - ADDR_WIDTH - ADDRESS WIDTH - 32 - - - DATA_WIDTH - DATA WIDTH - 32 - - - ID_WIDTH - ID WIDTH - 0 - - - - false - - - - - - AWUSER_WIDTH - AWUSER WIDTH - 0 - - - - false - - - - - - ARUSER_WIDTH - ARUSER WIDTH - 0 - - - - false - - - - - - RUSER_WIDTH - RUSER WIDTH - 0 - - - - false - - - - - - WUSER_WIDTH - WUSER WIDTH - 0 - - - - false - - - - - - BUSER_WIDTH - BUSER WIDTH - 0 - - - - false - - - - - - WUSER_BITS_PER_BYTE - WUSER BITS PER BYTE - 0 - - - - false - - - - - - RUSER_BITS_PER_BYTE - RUSER BITS PER BYTE - 0 - - - - false - - - - - - HAS_USER_BITS_PER_BYTE - HAS USER_BITS_PER_BYTE - 0 - - - - false - - - - - - SUPPORTS_NARROW - SUPPORTS NARROW - 0 - - - - false - - - - - - HAS_SIZE - HAS SIZE - 0 - - - - false - - - - - - HAS_BURST - HAS BURST - 0 - - - - false - - - - - - HAS_LOCK - HAS LOCK - 0 - - - - false - - - - - - HAS_CACHE - HAS CACHE - 0 - - - - false - - - - - - HAS_REGION - HAS REGION - 0 - - - - false - - - - - - HAS_QOS - HAS QOS - 0 - - - - false - - - - - - HAS_PROT - HAS PROT - 1 - - - HAS_WSTRB - HAS WSTRB - 1 - - - HAS_BRESP - HAS BRESP - 1 - - - HAS_RRESP - HAS RRESP - 1 - - - HAS_ACLKEN - HAS ACLKEN - 0 - - - HAS_ARESETN - HAS ARESETN - 1 - - - - - AXI Verification IP - - xtlm - - 5 - true - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2019.1 - - - - - - - - - - diff --git a/qick/firmware/ip/axis_constant_iq/src/axi_slv.vhd b/qick/firmware/ip/axis_constant_iq/src/axi_slv.vhd deleted file mode 100644 index 208a6d4..0000000 --- a/qick/firmware/ip/axis_constant_iq/src/axi_slv.vhd +++ /dev/null @@ -1,517 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity axi_slv is - Generic - ( - DATA_WIDTH : integer := 32; - ADDR_WIDTH : integer := 6 - ); - Port - ( - aclk : in std_logic; - aresetn : in std_logic; - - -- Write Address Channel. - awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); - awprot : in std_logic_vector(2 downto 0); - awvalid : in std_logic; - awready : out std_logic; - - -- Write Data Channel. - wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); - wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); - wvalid : in std_logic; - wready : out std_logic; - - -- Write Response Channel. - bresp : out std_logic_vector(1 downto 0); - bvalid : out std_logic; - bready : in std_logic; - - -- Read Address Channel. - araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); - arprot : in std_logic_vector(2 downto 0); - arvalid : in std_logic; - arready : out std_logic; - - -- Read Data Channel. - rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); - rresp : out std_logic_vector(1 downto 0); - rvalid : out std_logic; - rready : in std_logic; - - -- Registers. - REAL_REG : out std_logic_vector (31 downto 0); - IMAG_REG : out std_logic_vector (31 downto 0); - WE_REG : out std_logic - ); -end axi_slv; - -architecture rtl of axi_slv is - - -- AXI4LITE signals - signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); - signal axi_awready : std_logic; - signal axi_wready : std_logic; - signal axi_bresp : std_logic_vector(1 downto 0); - signal axi_bvalid : std_logic; - signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); - signal axi_arready : std_logic; - signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); - signal axi_rresp : std_logic_vector(1 downto 0); - signal axi_rvalid : std_logic; - - -- Example-specific design signals - -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH - -- ADDR_LSB is used for addressing 32/64 bit registers/memories - -- ADDR_LSB = 2 for 32 bits (n downto 2) - -- ADDR_LSB = 3 for 64 bits (n downto 3) - constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; - constant OPT_MEM_ADDR_BITS : integer := 3; - ------------------------------------------------ - ---- Signals for user logic register space example - -------------------------------------------------- - ---- Number of Slave Registers 16 - signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg_rden : std_logic; - signal slv_reg_wren : std_logic; - signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); - signal byte_index : integer; - signal aw_en : std_logic; - -begin - -- I/O Connections assignments - - awreadY <= axi_awready; - wready <= axi_wready; - bresp <= axi_bresp; - bvalid <= axi_bvalid; - arreadY <= axi_arready; - rdata <= axi_rdata; - rresp <= axi_rresp; - rvalid <= axi_rvalid; - -- Implement axi_awready generation - -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is - -- de-asserted when reset is low. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_awready <= '0'; - aw_en <= '1'; - else - if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then - -- slave is ready to accept write address when - -- there is a valid write address and write data - -- on the write address and data bus. This design - -- expects no outstanding transactions. - axi_awready <= '1'; - aw_en <= '0'; - elsif (bready = '1' and axi_bvalid = '1') then - aw_en <= '1'; - axi_awready <= '0'; - else - axi_awready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement axi_awaddr latching - -- This process is used to latch the address when both - -- S_AXI_AWVALID and S_AXI_WVALID are valid. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_awaddr <= (others => '0'); - else - if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then - -- Write Address latching - axi_awaddr <= awaddr; - end if; - end if; - end if; - end process; - - -- Implement axi_wready generation - -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is - -- de-asserted when reset is low. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_wready <= '0'; - else - if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then - -- slave is ready to accept write data when - -- there is a valid write address and write data - -- on the write address and data bus. This design - -- expects no outstanding transactions. - axi_wready <= '1'; - else - axi_wready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement memory mapped register select and write logic generation - -- The write data is accepted and written to memory mapped registers when - -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to - -- select byte enables of slave registers while writing. - -- These registers are cleared when reset (active low) is applied. - -- Slave register write enable is asserted when valid address and data are available - -- and the slave is ready to accept the write address and write data. - slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; - - process (aclk) - variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); - begin - if rising_edge(aclk) then - if aresetn = '0' then - slv_reg0 <= (others => '0'); - slv_reg1 <= (others => '0'); - slv_reg2 <= (others => '0'); - slv_reg3 <= (others => '0'); - slv_reg4 <= (others => '0'); - slv_reg5 <= (others => '0'); - slv_reg6 <= (others => '0'); - slv_reg7 <= (others => '0'); - slv_reg8 <= (others => '0'); - slv_reg9 <= (others => '0'); - slv_reg10 <= (others => '0'); - slv_reg11 <= (others => '0'); - slv_reg12 <= (others => '0'); - slv_reg13 <= (others => '0'); - slv_reg14 <= (others => '0'); - slv_reg15 <= (others => '0'); - else - loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); - if (slv_reg_wren = '1') then - case loc_addr is - when b"0000" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 0 - slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0001" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 1 - slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0010" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 2 - slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0011" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 3 - slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0100" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 4 - slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0101" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 5 - slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0110" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 6 - slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0111" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 7 - slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1000" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 8 - slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1001" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 9 - slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1010" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 10 - slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1011" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 11 - slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1100" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 12 - slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1101" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 13 - slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1110" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 14 - slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1111" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 15 - slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when others => - slv_reg0 <= slv_reg0; - slv_reg1 <= slv_reg1; - slv_reg2 <= slv_reg2; - slv_reg3 <= slv_reg3; - slv_reg4 <= slv_reg4; - slv_reg5 <= slv_reg5; - slv_reg6 <= slv_reg6; - slv_reg7 <= slv_reg7; - slv_reg8 <= slv_reg8; - slv_reg9 <= slv_reg9; - slv_reg10 <= slv_reg10; - slv_reg11 <= slv_reg11; - slv_reg12 <= slv_reg12; - slv_reg13 <= slv_reg13; - slv_reg14 <= slv_reg14; - slv_reg15 <= slv_reg15; - end case; - end if; - end if; - end if; - end process; - - -- Implement write response logic generation - -- The write response and response valid signals are asserted by the slave - -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. - -- This marks the acceptance of address and indicates the status of - -- write transaction. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_bvalid <= '0'; - axi_bresp <= "00"; --need to work more on the responses - else - if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then - axi_bvalid <= '1'; - axi_bresp <= "00"; - elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) - axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) - end if; - end if; - end if; - end process; - - -- Implement axi_arready generation - -- axi_arready is asserted for one S_AXI_ACLK clock cycle when - -- S_AXI_ARVALID is asserted. axi_awready is - -- de-asserted when reset (active low) is asserted. - -- The read address is also latched when S_AXI_ARVALID is - -- asserted. axi_araddr is reset to zero on reset assertion. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_arready <= '0'; - axi_araddr <= (others => '1'); - else - if (axi_arready = '0' and arvalid = '1') then - -- indicates that the slave has acceped the valid read address - axi_arready <= '1'; - -- Read Address latching - axi_araddr <= araddr; - else - axi_arready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement axi_arvalid generation - -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_ARVALID and axi_arready are asserted. The slave registers - -- data are available on the axi_rdata bus at this instance. The - -- assertion of axi_rvalid marks the validity of read data on the - -- bus and axi_rresp indicates the status of read transaction.axi_rvalid - -- is deasserted on reset (active low). axi_rresp and axi_rdata are - -- cleared to zero on reset (active low). - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_rvalid <= '0'; - axi_rresp <= "00"; - else - if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then - -- Valid read data is available at the read data bus - axi_rvalid <= '1'; - axi_rresp <= "00"; -- 'OKAY' response - elsif (axi_rvalid = '1' and rready = '1') then - -- Read data is accepted by the master - axi_rvalid <= '0'; - end if; - end if; - end if; - end process; - - -- Implement memory mapped register select and read logic generation - -- Slave register read enable is asserted when valid address is available - -- and the slave is ready to accept the read address. - slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; - - -- 4 : TAVG_LOW_REG (r). - -- 5 : TAVG_HIGH_REG(r). - - process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) - variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); - begin - -- Address decoding for reading registers - loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); - case loc_addr is - when b"0000" => - reg_data_out <= slv_reg0; - when b"0001" => - reg_data_out <= slv_reg1; - when b"0010" => - reg_data_out <= slv_reg2; - when b"0011" => - reg_data_out <= slv_reg3; - when b"0100" => - reg_data_out <= slv_reg4; - when b"0101" => - reg_data_out <= slv_reg5; - when b"0110" => - reg_data_out <= slv_reg6; - when b"0111" => - reg_data_out <= slv_reg7; - when b"1000" => - reg_data_out <= slv_reg8; - when b"1001" => - reg_data_out <= slv_reg9; - when b"1010" => - reg_data_out <= slv_reg10; - when b"1011" => - reg_data_out <= slv_reg11; - when b"1100" => - reg_data_out <= slv_reg12; - when b"1101" => - reg_data_out <= slv_reg13; - when b"1110" => - reg_data_out <= slv_reg14; - when b"1111" => - reg_data_out <= slv_reg15; - when others => - reg_data_out <= (others => '0'); - end case; - end process; - - -- Output register or memory read data - process( aclk ) is - begin - if (rising_edge (aclk)) then - if ( aresetn = '0' ) then - axi_rdata <= (others => '0'); - else - if (slv_reg_rden = '1') then - -- When there is a valid read address (S_AXI_ARVALID) with - -- acceptance of read address by the slave (axi_arready), - -- output the read dada - -- Read address mux - axi_rdata <= reg_data_out; -- register read data - end if; - end if; - end if; - end process; - - -- Output Registers. - REAL_REG <= slv_reg0(31 downto 0); - IMAG_REG <= slv_reg1(31 downto 0); - WE_REG <= slv_reg2(0); - -end rtl; - diff --git a/qick/firmware/ip/axis_constant_iq/src/axis_constant_iq.vhd b/qick/firmware/ip/axis_constant_iq/src/axis_constant_iq.vhd deleted file mode 100644 index 616a408..0000000 --- a/qick/firmware/ip/axis_constant_iq/src/axis_constant_iq.vhd +++ /dev/null @@ -1,219 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity axis_constant_iq is - Generic - ( - -- Number of bits of I/Q. - B : Integer := 16; - -- Number of parallel outputs. - N : Integer := 4 - ); - Port - ( - -- AXI-Lite Slave I/F. - s_axi_aclk : in std_logic; - s_axi_aresetn : in std_logic; - - s_axi_awaddr : in std_logic_vector(5 downto 0); - s_axi_awprot : in std_logic_vector(2 downto 0); - s_axi_awvalid : in std_logic; - s_axi_awready : out std_logic; - - s_axi_wdata : in std_logic_vector(31 downto 0); - s_axi_wstrb : in std_logic_vector(3 downto 0); - s_axi_wvalid : in std_logic; - s_axi_wready : out std_logic; - - s_axi_bresp : out std_logic_vector(1 downto 0); - s_axi_bvalid : out std_logic; - s_axi_bready : in std_logic; - - s_axi_araddr : in std_logic_vector(5 downto 0); - s_axi_arprot : in std_logic_vector(2 downto 0); - s_axi_arvalid : in std_logic; - s_axi_arready : out std_logic; - - s_axi_rdata : out std_logic_vector(31 downto 0); - s_axi_rresp : out std_logic_vector(1 downto 0); - s_axi_rvalid : out std_logic; - s_axi_rready : in std_logic; - - -- AXIS Master I/F. - m_axis_aclk : in std_logic; - m_axis_aresetn : in std_logic; - m_axis_tdata : out std_logic_vector(2*B*N-1 downto 0); - m_axis_tvalid : out std_logic - ); -end axis_constant_iq; - -architecture rtl of axis_constant_iq is - --- Synchronizer. -component synchronizer_n is - generic ( - N : Integer := 2 - ); - port ( - rstn : in std_logic; - clk : in std_logic; - data_in : in std_logic; - data_out : out std_logic - ); -end component; - --- AXI Slave. -component axi_slv is - Generic - ( - DATA_WIDTH : integer := 32; - ADDR_WIDTH : integer := 6 - ); - Port - ( - aclk : in std_logic; - aresetn : in std_logic; - - -- Write Address Channel. - awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); - awprot : in std_logic_vector(2 downto 0); - awvalid : in std_logic; - awready : out std_logic; - - -- Write Data Channel. - wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); - wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); - wvalid : in std_logic; - wready : out std_logic; - - -- Write Response Channel. - bresp : out std_logic_vector(1 downto 0); - bvalid : out std_logic; - bready : in std_logic; - - -- Read Address Channel. - araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); - arprot : in std_logic_vector(2 downto 0); - arvalid : in std_logic; - arready : out std_logic; - - -- Read Data Channel. - rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); - rresp : out std_logic_vector(1 downto 0); - rvalid : out std_logic; - rready : in std_logic; - - -- Registers. - REAL_REG : out std_logic_vector (31 downto 0); - IMAG_REG : out std_logic_vector (31 downto 0); - WE_REG : out std_logic - ); -end component; - --- Number of bits of IQ combined. -constant BIQ : Integer := 2*B; - --- Registers. -signal REAL_REG : std_logic_vector (31 downto 0); -signal IMAG_REG : std_logic_vector (31 downto 0); -signal WE_REG : std_logic; - --- we. -signal we : std_logic; -signal we_r : std_logic; -signal we_int : std_logic; - --- i/q. -signal real_r : std_logic_vector (B-1 downto 0); -signal imag_r : std_logic_vector (B-1 downto 0); - -begin - --- Synchronizer. -WE_REG_resync_i : synchronizer_n - port map ( - rstn => m_axis_aresetn , - clk => m_axis_aclk , - data_in => WE_REG , - data_out => we - ); - --- AXI Slave. -axi_slv_i : axi_slv - Port map - ( - aclk => s_axi_aclk , - aresetn => s_axi_aresetn , - - -- Write Address Channel. - awaddr => s_axi_awaddr , - awprot => s_axi_awprot , - awvalid => s_axi_awvalid , - awready => s_axi_awready , - - -- Write Data Channel. - wdata => s_axi_wdata , - wstrb => s_axi_wstrb , - wvalid => s_axi_wvalid , - wready => s_axi_wready , - - -- Write Response Channel. - bresp => s_axi_bresp , - bvalid => s_axi_bvalid , - bready => s_axi_bready , - - -- Read Address Channel. - araddr => s_axi_araddr , - arprot => s_axi_arprot , - arvalid => s_axi_arvalid , - arready => s_axi_arready , - - -- Read Data Channel. - rdata => s_axi_rdata , - rresp => s_axi_rresp , - rvalid => s_axi_rvalid , - rready => s_axi_rready , - - -- Registers. - REAL_REG => REAL_REG , - IMAG_REG => IMAG_REG , - WE_REG => WE_REG - ); - -process (m_axis_aclk) -begin - if (rising_edge(m_axis_aclk)) then - if ( m_axis_aresetn = '0' ) then - -- we. - we_r <= '0'; - - -- i/q. - real_r <= (others => '0'); - imag_r <= (others => '0'); - else - -- we. - we_r <= we; - - -- i/q. - if (we_int = '1') then - real_r <= REAL_REG(B-1 downto 0); - imag_r <= IMAG_REG(B-1 downto 0); - end if; - end if; - end if; -end process; - --- we generation. -we_int <= not(we_r) and we; - --- Output generation. -GEN_OUT: for I in 0 to N-1 generate - m_axis_tdata ( B + BIQ*I-1 downto BIQ*I ) <= real_r; - m_axis_tdata (2*B + BIQ*I-1 downto BIQ*I + B ) <= imag_r; -end generate GEN_OUT; - -m_axis_tvalid <= '1'; - -end rtl; - diff --git a/qick/firmware/ip/axis_constant_iq/src/synchronizer_n.vhd b/qick/firmware/ip/axis_constant_iq/src/synchronizer_n.vhd deleted file mode 100644 index 925425d..0000000 --- a/qick/firmware/ip/axis_constant_iq/src/synchronizer_n.vhd +++ /dev/null @@ -1,42 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library common_lib; -use common_lib.all; - -entity synchronizer_n is - generic ( - N : Integer := 2 - ); - port ( - rstn : in std_logic; - clk : in std_logic; - data_in : in std_logic; - data_out : out std_logic - ); -end synchronizer_n; - -architecture rtl of synchronizer_n is - --- Internal register. -signal data_int_reg : std_logic_vector (N-1 downto 0); - -begin - -process(clk) -begin - if (rising_edge(clk)) then - if (rstn = '0') then - data_int_reg <= (others => '0'); - else - data_int_reg <= data_int_reg(N-2 downto 0) & data_in; - end if; - end if; -end process; - --- Assign output. -data_out <= data_int_reg(N-1); - -end rtl; - diff --git a/qick/firmware/ip/axis_constant_iq/src/tb.sv b/qick/firmware/ip/axis_constant_iq/src/tb.sv deleted file mode 100644 index 9ed93fc..0000000 --- a/qick/firmware/ip/axis_constant_iq/src/tb.sv +++ /dev/null @@ -1,198 +0,0 @@ -// VIP: axi_mst_0 -// DUT: axis_chsel_pfb -// IF: s_axi -> axi_mst_0 - -import axi_vip_pkg::*; -import axi_mst_0_pkg::*; - -module tb(); - -// DUT generics. -parameter B = 16; -parameter N = 8; - -// s_axi interfase. -reg s_axi_aclk; -wire [5:0] s_axi_araddr; -reg s_axi_aresetn; -wire [2:0] s_axi_arprot; -wire s_axi_arready; -wire s_axi_arvalid; -wire [5:0] s_axi_awaddr; -wire [2:0] s_axi_awprot; -wire s_axi_awready; -wire s_axi_awvalid; -wire s_axi_bready; -wire [1:0] s_axi_bresp; -wire s_axi_bvalid; -wire [31:0] s_axi_rdata; -wire s_axi_rready; -wire [1:0] s_axi_rresp; -wire s_axi_rvalid; -wire [31:0] s_axi_wdata; -wire s_axi_wready; -wire [3:0] s_axi_wstrb; -wire s_axi_wvalid; - -// m_axis interfase. -reg m_axis_aclk; -reg m_axis_aresetn; -wire [2*B*N-1:0] m_axis_tdata; -wire m_axis_tvalid; - -xil_axi_prot_t prot = 0; -reg[31:0] data_wr = 32'h12345678; -reg[31:0] data_rd; -reg[31:0] data; -xil_axi_resp_t resp; - -// TB control. -reg tb_start; - -axi_mst_0 axi_mst_0_i - ( - .aclk (s_axi_aclk), - .aresetn (s_axi_aresetn), - .m_axi_araddr (s_axi_araddr), - .m_axi_arprot (s_axi_arprot), - .m_axi_arready (s_axi_arready), - .m_axi_arvalid (s_axi_arvalid), - .m_axi_awaddr (s_axi_awaddr), - .m_axi_awprot (s_axi_awprot), - .m_axi_awready (s_axi_awready), - .m_axi_awvalid (s_axi_awvalid), - .m_axi_bready (s_axi_bready), - .m_axi_bresp (s_axi_bresp), - .m_axi_bvalid (s_axi_bvalid), - .m_axi_rdata (s_axi_rdata), - .m_axi_rready (s_axi_rready), - .m_axi_rresp (s_axi_rresp), - .m_axi_rvalid (s_axi_rvalid), - .m_axi_wdata (s_axi_wdata), - .m_axi_wready (s_axi_wready), - .m_axi_wstrb (s_axi_wstrb), - .m_axi_wvalid (s_axi_wvalid) - ); - -axis_constant_iq - #( - .B(B), - .N(N) - ) - axis_constant_iq - ( - // s_axi interfase. - .s_axi_aclk (s_axi_aclk), - .s_axi_araddr (s_axi_araddr), - .s_axi_aresetn (s_axi_aresetn), - .s_axi_arprot (s_axi_arprot), - .s_axi_arready (s_axi_arready), - .s_axi_arvalid (s_axi_arvalid), - .s_axi_awaddr (s_axi_awaddr), - .s_axi_awprot (s_axi_awprot), - .s_axi_awready (s_axi_awready), - .s_axi_awvalid (s_axi_awvalid), - .s_axi_bready (s_axi_bready), - .s_axi_bresp (s_axi_bresp), - .s_axi_bvalid (s_axi_bvalid), - .s_axi_rdata (s_axi_rdata), - .s_axi_rready (s_axi_rready), - .s_axi_rresp (s_axi_rresp), - .s_axi_rvalid (s_axi_rvalid), - .s_axi_wdata (s_axi_wdata), - .s_axi_wready (s_axi_wready), - .s_axi_wstrb (s_axi_wstrb), - .s_axi_wvalid (s_axi_wvalid), - - // m_axis interfase. - .m_axis_aclk (m_axis_aclk ), - .m_axis_aresetn (m_axis_aresetn ), - .m_axis_tdata (m_axis_tdata ), - .m_axis_tvalid (m_axis_tvalid ) - ); - -// VIP Agents -axi_mst_0_mst_t axi_mst_0_agent; - -initial begin - // Create agents. - axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); - - // Set tag for agents. - axi_mst_0_agent.set_agent_tag("axi_mst_0 VIP"); - - // Start agents. - axi_mst_0_agent.start_master(); - - /* ************* */ - /* Main TB Start */ - /* ************* */ - - // Reset sequence. - s_axi_aresetn <= 0; - m_axis_aresetn <= 0; - tb_start <= 0; - #500; - s_axi_aresetn <= 1; - m_axis_aresetn <= 1; - - #1000; - - // Start data. - tb_start <= 1; - - // REAL_REG - data_wr = 123; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(0*4, prot, data_wr, resp); - #10; - - // IMAG_REG - data_wr = 14; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(1*4, prot, data_wr, resp); - #10; - - // WE_REG - data_wr = 1; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(2*4, prot, data_wr, resp); - #10; - - #1000; - - // REAL_REG - data_wr = 55; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(0*4, prot, data_wr, resp); - #10; - - // IMAG_REG - data_wr = 66; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(1*4, prot, data_wr, resp); - #10; - - // WE_REG - data_wr = 0; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(2*4, prot, data_wr, resp); - #10; - - // WE_REG - data_wr = 1; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(2*4, prot, data_wr, resp); - #10; - -end - -always begin - s_axi_aclk <= 0; - #10; - s_axi_aclk <= 1; - #10; -end - -always begin - m_axis_aclk <= 0; - #3; - m_axis_aclk <= 1; - #3; -end - -endmodule - diff --git a/qick/firmware/ip/axis_constant_iq/xgui/axis_constant_iq_v1_0.tcl b/qick/firmware/ip/axis_constant_iq/xgui/axis_constant_iq_v1_0.tcl deleted file mode 100644 index 1717489..0000000 --- a/qick/firmware/ip/axis_constant_iq/xgui/axis_constant_iq_v1_0.tcl +++ /dev/null @@ -1,40 +0,0 @@ -# Definitional proc to organize widgets for parameters. -proc init_gui { IPINST } { - ipgui::add_param $IPINST -name "Component_Name" - #Adding Page - set Page_0 [ipgui::add_page $IPINST -name "Page 0"] - ipgui::add_param $IPINST -name "B" -parent ${Page_0} - ipgui::add_param $IPINST -name "N" -parent ${Page_0} - - -} - -proc update_PARAM_VALUE.B { PARAM_VALUE.B } { - # Procedure called to update B when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.B { PARAM_VALUE.B } { - # Procedure called to validate B - return true -} - -proc update_PARAM_VALUE.N { PARAM_VALUE.N } { - # Procedure called to update N when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.N { PARAM_VALUE.N } { - # Procedure called to validate N - return true -} - - -proc update_MODELPARAM_VALUE.B { MODELPARAM_VALUE.B PARAM_VALUE.B } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.B}] ${MODELPARAM_VALUE.B} -} - -proc update_MODELPARAM_VALUE.N { MODELPARAM_VALUE.N PARAM_VALUE.N } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.N}] ${MODELPARAM_VALUE.N} -} - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/README b/qick/firmware/ip/axis_pfb_readout_v2/README deleted file mode 100644 index 3a17d6a..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/README +++ /dev/null @@ -1,5 +0,0 @@ -This block integrates a 8 Channels PFB with 50 % overlap. -The output channels are multiplied by 8 individual DDSs. -This block has 4 outpus. Routing of channels to inputs -is done using CHXSEL_REG. - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/component.xml b/qick/firmware/ip/axis_pfb_readout_v2/component.xml deleted file mode 100644 index f2904f2..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/component.xml +++ /dev/null @@ -1,1488 +0,0 @@ - - - user.org - user - axis_pfb_readout_v2 - 1.0 - - - m0_axis - - - - - - - TDATA - - - m0_axis_tdata - - - - - TVALID - - - m0_axis_tvalid - - - - - - m1_axis - - - - - - - TDATA - - - m1_axis_tdata - - - - - TVALID - - - m1_axis_tvalid - - - - - - m2_axis - - - - - - - TDATA - - - m2_axis_tdata - - - - - TVALID - - - m2_axis_tvalid - - - - - - m3_axis - - - - - - - TDATA - - - m3_axis_tdata - - - - - TVALID - - - m3_axis_tvalid - - - - - - s_axis - - - - - - - TDATA - - - s_axis_tdata - - - - - TVALID - - - s_axis_tvalid - - - - - TREADY - - - s_axis_tready - - - - - - s_axi - - - - - - - - - AWADDR - - - s_axi_awaddr - - - - - AWPROT - - - s_axi_awprot - - - - - AWVALID - - - s_axi_awvalid - - - - - AWREADY - - - s_axi_awready - - - - - WDATA - - - s_axi_wdata - - - - - WSTRB - - - s_axi_wstrb - - - - - WVALID - - - s_axi_wvalid - - - - - WREADY - - - s_axi_wready - - - - - BRESP - - - s_axi_bresp - - - - - BVALID - - - s_axi_bvalid - - - - - BREADY - - - s_axi_bready - - - - - ARADDR - - - s_axi_araddr - - - - - ARPROT - - - s_axi_arprot - - - - - ARVALID - - - s_axi_arvalid - - - - - ARREADY - - - s_axi_arready - - - - - RDATA - - - s_axi_rdata - - - - - RRESP - - - s_axi_rresp - - - - - RVALID - - - s_axi_rvalid - - - - - RREADY - - - s_axi_rready - - - - - - s_axi_aclk - - - - - - - CLK - - - s_axi_aclk - - - - - - ASSOCIATED_BUSIF - s_axi - - - ASSOCIATED_RESET - s_axi_aresetn - - - - - s_axi_aresetn - - - - - - - RST - - - s_axi_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - aclk - - - - - - - CLK - - - aclk - - - - - - ASSOCIATED_BUSIF - m0_axis:m1_axis:m2_axis:m3_axis:s_axis - - - ASSOCIATED_RESET - aresetn - - - - - aresetn - - - - - - - RST - - - aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - - - s_axi - - reg0 - 0 - 64 - 32 - register - - - - - - - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis - Verilog - axis_pfb_readout_v2 - - xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset - - - xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset - - - xilinx_anylanguagesynthesis_view_fileset - - - - viewChecksum - b7fc229d - - - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - Verilog - axis_pfb_readout_v2 - - xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset - - - xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - - - viewChecksum - b7fc229d - - - - - xilinx_xpgui - UI Layout - :vivado.xilinx.com:xgui.ui - - xilinx_xpgui_view_fileset - - - - viewChecksum - cb6eaf6e - - - - - - - s_axi_aclk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_aresetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_awaddr - - in - - 5 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_awprot - - in - - 2 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_awvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_awready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_wdata - - in - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_wstrb - - in - - 3 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 1 - - - - - s_axi_wvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_wready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_bresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_bvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_bready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_araddr - - in - - 5 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_arprot - - in - - 2 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_arvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_arready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_rdata - - out - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_rresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_rvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_rready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - aclk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - aresetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axis_tvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axis_tready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axis_tdata - - in - - 127 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - m0_axis_tvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m0_axis_tdata - - out - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m1_axis_tvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m1_axis_tdata - - out - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m2_axis_tvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m2_axis_tdata - - out - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m3_axis_tvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m3_axis_tdata - - out - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - - INTERLEAVED_INPUT - Interleaved Input - true - - - - - - choice_list_9d8b0d81 - ACTIVE_HIGH - ACTIVE_LOW - - - - - xilinx_anylanguagesynthesis_view_fileset - - src/dds_0/dds_0.xci - xci - CELL_NAME_pfb_dds_mux_i/ddsprod_v_i/genblk1[0].ddsprod_i/dds_i/dds_0 - - - src/fir/fir_7/fir_7.xci - xci - CELL_NAME_pfb_dds_mux_i/pfb_i/firs_i/fir7_i/fir_7 - - - src/fir/fir_5/fir_5.xci - xci - CELL_NAME_pfb_dds_mux_i/pfb_i/firs_i/fir6_i/fir_5 - - - src/fir/fir_3/fir_3.xci - xci - CELL_NAME_pfb_dds_mux_i/pfb_i/firs_i/fir5_i/fir_3 - - - src/fir/fir_1/fir_1.xci - xci - CELL_NAME_pfb_dds_mux_i/pfb_i/firs_i/fir4_i/fir_1 - - - src/fir/fir_6/fir_6.xci - xci - CELL_NAME_pfb_dds_mux_i/pfb_i/firs_i/fir3_i/fir_6 - - - src/fir/fir_4/fir_4.xci - xci - CELL_NAME_pfb_dds_mux_i/pfb_i/firs_i/fir2_i/fir_4 - - - src/fir/fir_2/fir_2.xci - xci - CELL_NAME_pfb_dds_mux_i/pfb_i/firs_i/fir1_i/fir_2 - - - src/fir/fir_0/fir_0.xci - xci - CELL_NAME_pfb_dds_mux_i/pfb_i/firs_i/fir0_i/fir_0 - - - src/fir/coef/fir_7.coe - coe - - - src/fir/coef/fir_5.coe - coe - - - src/fir/coef/fir_3.coe - coe - - - src/fir/coef/fir_1.coe - coe - - - src/fir/coef/fir_6.coe - coe - - - src/fir/coef/fir_4.coe - coe - - - src/fir/coef/fir_2.coe - coe - - - src/fir/coef/fir_0.coe - coe - - - src/ddsprod.sv - systemVerilogSource - - - src/ddsprod_v.sv - systemVerilogSource - - - src/firs.sv - systemVerilogSource - - - src/pfb.sv - systemVerilogSource - - - src/pfb_dds_mux.sv - systemVerilogSource - - - src/pfb_mux.sv - systemVerilogSource - - - src/axi_slv.vhd - vhdlSource - - - src/ssrfft_8x8/ssr_fft_8x8/conv_pkg.vhd - vhdlSource - - - src/pimod.vhd - vhdlSource - - - src/ssrfft_8x8/ssr_fft_8x8/single_reg_w_init.vhd - vhdlSource - - - src/ssrfft_8x8/ssr_fft_8x8/srl33e.vhd - vhdlSource - - - src/ssrfft_8x8/ssr_fft_8x8/ssr_8x8_entity_declarations.vhd - vhdlSource - - - src/ssrfft_8x8/ssr_fft_8x8/xlclockdriver_rd.vhd - vhdlSource - - - src/ssrfft_8x8/ssr_fft_8x8/ssr_8x8.vhd - vhdlSource - - - src/ssrfft_8x8/ssrfft_8x8.vhd - vhdlSource - - - src/ssrfft_8x8/ssr_fft_8x8/synth_reg.vhd - vhdlSource - - - src/ssrfft_8x8/ssr_fft_8x8/synth_reg_reg.vhd - vhdlSource - - - src/ssrfft_8x8/ssr_fft_8x8/synth_reg_w_init.vhd - vhdlSource - - - src/axis_pfb_readout_v2.v - verilogSource - CHECKSUM_197f4331 - - - - xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset - - - - - - - - - - xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset - - - - - - - - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - src/dds_0/dds_0.xci - xci - CELL_NAME_pfb_dds_mux_i/ddsprod_v_i/genblk1[0].ddsprod_i/dds_i/dds_0 - - - src/fir/fir_7/fir_7.xci - xci - CELL_NAME_pfb_dds_mux_i/pfb_i/firs_i/fir7_i/fir_7 - - - src/fir/fir_5/fir_5.xci - xci - CELL_NAME_pfb_dds_mux_i/pfb_i/firs_i/fir6_i/fir_5 - - - src/fir/fir_3/fir_3.xci - xci - CELL_NAME_pfb_dds_mux_i/pfb_i/firs_i/fir5_i/fir_3 - - - src/fir/fir_1/fir_1.xci - xci - CELL_NAME_pfb_dds_mux_i/pfb_i/firs_i/fir4_i/fir_1 - - - src/fir/fir_6/fir_6.xci - xci - CELL_NAME_pfb_dds_mux_i/pfb_i/firs_i/fir3_i/fir_6 - - - src/fir/fir_4/fir_4.xci - xci - CELL_NAME_pfb_dds_mux_i/pfb_i/firs_i/fir2_i/fir_4 - - - src/fir/fir_2/fir_2.xci - xci - CELL_NAME_pfb_dds_mux_i/pfb_i/firs_i/fir1_i/fir_2 - - - src/fir/fir_0/fir_0.xci - xci - CELL_NAME_pfb_dds_mux_i/pfb_i/firs_i/fir0_i/fir_0 - - - src/fir/coef/fir_7.coe - coe - - - src/fir/coef/fir_5.coe - coe - - - src/fir/coef/fir_3.coe - coe - - - src/fir/coef/fir_1.coe - coe - - - src/fir/coef/fir_6.coe - coe - - - src/fir/coef/fir_4.coe - coe - - - src/fir/coef/fir_2.coe - coe - - - src/fir/coef/fir_0.coe - coe - - - src/ddsprod.sv - systemVerilogSource - - - src/ddsprod_v.sv - systemVerilogSource - - - src/firs.sv - systemVerilogSource - - - src/pfb.sv - systemVerilogSource - - - src/pfb_dds_mux.sv - systemVerilogSource - - - src/pfb_mux.sv - systemVerilogSource - - - src/axi_slv.vhd - vhdlSource - - - src/ssrfft_8x8/ssr_fft_8x8/conv_pkg.vhd - vhdlSource - - - src/pimod.vhd - vhdlSource - - - src/ssrfft_8x8/ssr_fft_8x8/single_reg_w_init.vhd - vhdlSource - - - src/ssrfft_8x8/ssr_fft_8x8/srl33e.vhd - vhdlSource - - - src/ssrfft_8x8/ssr_fft_8x8/ssr_8x8_entity_declarations.vhd - vhdlSource - - - src/ssrfft_8x8/ssr_fft_8x8/xlclockdriver_rd.vhd - vhdlSource - - - src/ssrfft_8x8/ssr_fft_8x8/ssr_8x8.vhd - vhdlSource - - - src/ssrfft_8x8/ssrfft_8x8.vhd - vhdlSource - - - src/ssrfft_8x8/ssr_fft_8x8/synth_reg.vhd - vhdlSource - - - src/ssrfft_8x8/ssr_fft_8x8/synth_reg_reg.vhd - vhdlSource - - - src/ssrfft_8x8/ssr_fft_8x8/synth_reg_w_init.vhd - vhdlSource - - - src/axis_pfb_readout_v2.v - verilogSource - - - - xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset - - - - - - - - - - xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset - - - - - - - - - - xilinx_xpgui_view_fileset - - xgui/axis_pfb_readout_v2_v1_0.tcl - tclSource - CHECKSUM_cb6eaf6e - XGUI_VERSION_2 - - - - AXIS PFB Readout, 8 Channels (4 outputs), Overlap 50%, 32-bit DDS per channel. - - - Component_Name - axis_pfb_readout_v2_v1_0 - - - INTERLEAVED_INPUT - Interleaved Input - true - - - - - - zynquplus - - - /UserIP - - AXIS PFB Readout x8 V2 - package_project - 4 - 2022-08-19T21:02:47Z - - /home/lstefana/v20.2/ip/axis_pfb_readout_v2 - /home/lstefana/v20.2/ip/axis_pfb_readout_v2 - /home/lstefana/v20.2/ip/axis_pfb_readout_v2 - /home/lstefana/v20.2/ip/axis_pfb_readout_v2 - /home/lstefana/v20.2/ip/axis_pfb_readout_v2 - /home/lstefana/v20.2/ip/axis_pfb_readout_v2 - /home/lstefana/v20.2/ip/axis_pfb_readout_v2 - /home/lstefana/v20.2/ip/axis_pfb_readout_v2 - /home/lstefana/v20.2/ip/axis_pfb_readout_v2 - /home/lstefana/v20.2/ip/axis_pfb_readout_v2 - /home/lstefana/v20.2/ip/axis_pfb_readout_v2 - /home/lstefana/v20.2/ip/axis_pfb_readout_v2 - /home/lstefana/v20.2/ip/axis_pfb_readout_v2 - /home/lstefana/v20.2/ip/axis_pfb_readout_v2 - /home/lstefana/v20.2/ip/axis_pfb_readout_v2 - /home/lstefana/v20.2/ip/axis_pfb_readout_v2 - /home/lstefana/v20.2/ip/axis_pfb_readout_v2 - /home/lstefana/v20.2/ip/axis_pfb_readout_v2 - /home/lstefana/v20.2/ip/axis_pfb_readout_v2 - /home/lstefana/v20.2/ip/axis_pfb_readout_v2 - /home/lstefana/v20.2/ip/axis_pfb_readout_v2 - /home/lstefana/v20.2/ip/axis_pfb_readout_v2 - /home/lstefana/v20.2/ip/axis_pfb_readout_v2 - /home/lstefana/v20.2/ip/axis_pfb_readout_v2 - /home/lstefana/v20.2/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 - - - - 2020.2 - - - - - - - - - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.veo b/qick/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.veo deleted file mode 100644 index 7cfbd51..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.veo +++ /dev/null @@ -1,85 +0,0 @@ -// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -// IP VLNV: xilinx.com:ip:axi_vip:1.1 -// IP Revision: 8 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -axi_mst_0 your_instance_name ( - .aclk(aclk), // input wire aclk - .aresetn(aresetn), // input wire aresetn - .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr - .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot - .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid - .m_axi_awready(m_axi_awready), // input wire m_axi_awready - .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata - .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb - .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid - .m_axi_wready(m_axi_wready), // input wire m_axi_wready - .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp - .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid - .m_axi_bready(m_axi_bready), // output wire m_axi_bready - .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr - .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot - .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid - .m_axi_arready(m_axi_arready), // input wire m_axi_arready - .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata - .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp - .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid - .m_axi_rready(m_axi_rready) // output wire m_axi_rready -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file axi_mst_0.v when simulating -// the core, axi_mst_0. When compiling the wrapper file, be sure to -// reference the Verilog simulation library. - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.vho b/qick/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.vho deleted file mode 100644 index a53be60..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.vho +++ /dev/null @@ -1,115 +0,0 @@ --- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:axi_vip:1.1 --- IP Revision: 8 - --- The following code must appear in the VHDL architecture header. - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT axi_mst_0 - PORT ( - aclk : IN STD_LOGIC; - aresetn : IN STD_LOGIC; - m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - m_axi_awvalid : OUT STD_LOGIC; - m_axi_awready : IN STD_LOGIC; - m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - m_axi_wvalid : OUT STD_LOGIC; - m_axi_wready : IN STD_LOGIC; - m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - m_axi_bvalid : IN STD_LOGIC; - m_axi_bready : OUT STD_LOGIC; - m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - m_axi_arvalid : OUT STD_LOGIC; - m_axi_arready : IN STD_LOGIC; - m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - m_axi_rvalid : IN STD_LOGIC; - m_axi_rready : OUT STD_LOGIC - ); -END COMPONENT; --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : axi_mst_0 - PORT MAP ( - aclk => aclk, - aresetn => aresetn, - m_axi_awaddr => m_axi_awaddr, - m_axi_awprot => m_axi_awprot, - m_axi_awvalid => m_axi_awvalid, - m_axi_awready => m_axi_awready, - m_axi_wdata => m_axi_wdata, - m_axi_wstrb => m_axi_wstrb, - m_axi_wvalid => m_axi_wvalid, - m_axi_wready => m_axi_wready, - m_axi_bresp => m_axi_bresp, - m_axi_bvalid => m_axi_bvalid, - m_axi_bready => m_axi_bready, - m_axi_araddr => m_axi_araddr, - m_axi_arprot => m_axi_arprot, - m_axi_arvalid => m_axi_arvalid, - m_axi_arready => m_axi_arready, - m_axi_rdata => m_axi_rdata, - m_axi_rresp => m_axi_rresp, - m_axi_rvalid => m_axi_rvalid, - m_axi_rready => m_axi_rready - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file axi_mst_0.vhd when simulating --- the core, axi_mst_0. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.xci b/qick/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.xci deleted file mode 100644 index ac9cf04..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.xci +++ /dev/null @@ -1,200 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - axi_mst_0 - - - ACTIVE_LOW - - 100000000 - 0 - 0 - 0.000 - 32 - 0 - 0 - 0 - - 32 - 100000000 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 32 - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 0 - 2 - 32 - 0 - 0 - 0 - 32 - 0 - 0 - 32 - 0 - 0 - 0 - axi_mst_0 - 32 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 0 - 0 - 1 - 0 - MASTER - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - zynquplusRFSOC - xilinx.com:zcu216:part0:2.0 - - xczu49dr - ffvf1760 - VERILOG - - MIXED - -2 - - E - TRUE - TRUE - IP_Flow - 8 - TRUE - . - - . - 2020.2 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.xml b/qick/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.xml deleted file mode 100644 index 491fd33..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.xml +++ /dev/null @@ -1,4760 +0,0 @@ - - - xilinx.com - customized_ip - axi_mst_0 - 1.0 - - - M_AXI - - - - - - - - - ARADDR - - - m_axi_araddr - - - - - ARBURST - - - m_axi_arburst - - - - - ARCACHE - - - m_axi_arcache - - - - - ARID - - - m_axi_arid - - - - - ARLEN - - - m_axi_arlen - - - - - ARLOCK - - - m_axi_arlock - - - - - ARPROT - - - m_axi_arprot - - - - - ARQOS - - - m_axi_arqos - - - - - ARREADY - - - m_axi_arready - - - - - ARREGION - - - m_axi_arregion - - - - - ARSIZE - - - m_axi_arsize - - - - - ARUSER - - - m_axi_aruser - - - - - ARVALID - - - m_axi_arvalid - - - - - AWADDR - - - m_axi_awaddr - - - - - AWBURST - - - m_axi_awburst - - - - - AWCACHE - - - m_axi_awcache - - - - - AWID - - - m_axi_awid - - - - - AWLEN - - - m_axi_awlen - - - - - AWLOCK - - - m_axi_awlock - - - - - AWPROT - - - m_axi_awprot - - - - - AWQOS - - - m_axi_awqos - - - - - AWREADY - - - m_axi_awready - - - - - AWREGION - - - m_axi_awregion - - - - - AWSIZE - - - m_axi_awsize - - - - - AWUSER - - - m_axi_awuser - - - - - AWVALID - - - m_axi_awvalid - - - - - BID - - - m_axi_bid - - - - - BREADY - - - m_axi_bready - - - - - BRESP - - - m_axi_bresp - - - - - BUSER - - - m_axi_buser - - - - - BVALID - - - m_axi_bvalid - - - - - RDATA - - - m_axi_rdata - - - - - RID - - - m_axi_rid - - - - - RLAST - - - m_axi_rlast - - - - - RREADY - - - m_axi_rready - - - - - RRESP - - - m_axi_rresp - - - - - RUSER - - - m_axi_ruser - - - - - RVALID - - - m_axi_rvalid - - - - - WDATA - - - m_axi_wdata - - - - - WID - - - m_axi_wid - - - - - WLAST - - - m_axi_wlast - - - - - WREADY - - - m_axi_wready - - - - - WSTRB - - - m_axi_wstrb - - - - - WUSER - - - m_axi_wuser - - - - - WVALID - - - m_axi_wvalid - - - - - - DATA_WIDTH - 32 - - - simulation.tlm - - - - - PROTOCOL - AXI4LITE - - - simulation.tlm - - - - - FREQ_HZ - 100000000 - - - simulation.tlm - - - - - ID_WIDTH - 0 - - - simulation.tlm - - - - - ADDR_WIDTH - 32 - - - simulation.tlm - - - - - AWUSER_WIDTH - 0 - - - simulation.tlm - - - - - ARUSER_WIDTH - 0 - - - simulation.tlm - - - - - WUSER_WIDTH - 0 - - - simulation.tlm - - - - - RUSER_WIDTH - 0 - - - simulation.tlm - - - - - BUSER_WIDTH - 0 - - - simulation.tlm - - - - - READ_WRITE_MODE - READ_WRITE - - - simulation.tlm - - - - - HAS_BURST - 0 - - - simulation.tlm - - - - - HAS_LOCK - 0 - - - simulation.tlm - - - - - HAS_PROT - 1 - - - simulation.tlm - - - - - HAS_CACHE - 0 - - - simulation.tlm - - - - - HAS_QOS - 0 - - - simulation.tlm - - - - - HAS_REGION - 0 - - - simulation.tlm - - - - - HAS_WSTRB - 1 - - - simulation.tlm - - - - - HAS_BRESP - 1 - - - simulation.tlm - - - - - HAS_RRESP - 1 - - - simulation.tlm - - - - - SUPPORTS_NARROW_BURST - 0 - - - simulation.tlm - - - - - NUM_READ_OUTSTANDING - 1 - - - simulation.tlm - - - - - NUM_WRITE_OUTSTANDING - 1 - - - simulation.tlm - - - - - MAX_BURST_LENGTH - 1 - - - simulation.tlm - - - - - PHASE - 0.000 - - - simulation.tlm - - - - - CLK_DOMAIN - - - - simulation.tlm - - - - - NUM_READ_THREADS - 1 - - - simulation.tlm - - - - - NUM_WRITE_THREADS - 1 - - - simulation.tlm - - - - - RUSER_BITS_PER_BYTE - 0 - - - simulation.tlm - - - - - WUSER_BITS_PER_BYTE - 0 - - - simulation.tlm - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - S_AXI - - - - - - - ARADDR - - - s_axi_araddr - - - - - ARBURST - - - s_axi_arburst - - - - - ARCACHE - - - s_axi_arcache - - - - - ARID - - - s_axi_arid - - - - - ARLEN - - - s_axi_arlen - - - - - ARLOCK - - - s_axi_arlock - - - - - ARPROT - - - s_axi_arprot - - - - - ARQOS - - - s_axi_arqos - - - - - ARREADY - - - s_axi_arready - - - - - ARREGION - - - s_axi_arregion - - - - - ARSIZE - - - s_axi_arsize - - - - - ARUSER - - - s_axi_aruser - - - - - ARVALID - - - s_axi_arvalid - - - - - AWADDR - - - s_axi_awaddr - - - - - AWBURST - - - s_axi_awburst - - - - - AWCACHE - - - s_axi_awcache - - - - - AWID - - - s_axi_awid - - - - - AWLEN - - - s_axi_awlen - - - - - AWLOCK - - - s_axi_awlock - - - - - AWPROT - - - s_axi_awprot - - - - - AWQOS - - - s_axi_awqos - - - - - AWREADY - - - s_axi_awready - - - - - AWREGION - - - s_axi_awregion - - - - - AWSIZE - - - s_axi_awsize - - - - - AWUSER - - - s_axi_awuser - - - - - AWVALID - - - s_axi_awvalid - - - - - BID - - - s_axi_bid - - - - - BREADY - - - s_axi_bready - - - - - BRESP - - - s_axi_bresp - - - - - BUSER - - - s_axi_buser - - - - - BVALID - - - s_axi_bvalid - - - - - RDATA - - - s_axi_rdata - - - - - RID - - - s_axi_rid - - - - - RLAST - - - s_axi_rlast - - - - - RREADY - - - s_axi_rready - - - - - RRESP - - - s_axi_rresp - - - - - RUSER - - - s_axi_ruser - - - - - RVALID - - - s_axi_rvalid - - - - - WDATA - - - s_axi_wdata - - - - - WID - - - s_axi_wid - - - - - WLAST - - - s_axi_wlast - - - - - WREADY - - - s_axi_wready - - - - - WSTRB - - - s_axi_wstrb - - - - - WUSER - - - s_axi_wuser - - - - - WVALID - - - s_axi_wvalid - - - - - - DATA_WIDTH - 1 - - - simulation.tlm - - - - - PROTOCOL - AXI4LITE - - - simulation.tlm - - - - - FREQ_HZ - 100000000 - - - simulation.tlm - - - - - ID_WIDTH - 0 - - - simulation.tlm - - - - - ADDR_WIDTH - 1 - - - simulation.tlm - - - - - AWUSER_WIDTH - 0 - - - simulation.tlm - - - - - ARUSER_WIDTH - 0 - - - simulation.tlm - - - - - WUSER_WIDTH - 0 - - - simulation.tlm - - - - - RUSER_WIDTH - 0 - - - simulation.tlm - - - - - BUSER_WIDTH - 0 - - - simulation.tlm - - - - - READ_WRITE_MODE - READ_WRITE - - - simulation.tlm - - - - - HAS_BURST - 0 - - - simulation.tlm - - - - - HAS_LOCK - 0 - - - simulation.tlm - - - - - HAS_PROT - 0 - - - simulation.tlm - - - - - HAS_CACHE - 0 - - - simulation.tlm - - - - - HAS_QOS - 0 - - - simulation.tlm - - - - - HAS_REGION - 0 - - - simulation.tlm - - - - - HAS_WSTRB - 0 - - - simulation.tlm - - - - - HAS_BRESP - 0 - - - simulation.tlm - - - - - HAS_RRESP - 0 - - - simulation.tlm - - - - - SUPPORTS_NARROW_BURST - 0 - - - simulation.tlm - - - - - NUM_READ_OUTSTANDING - 1 - - - simulation.tlm - - - - - NUM_WRITE_OUTSTANDING - 1 - - - simulation.tlm - - - - - MAX_BURST_LENGTH - 1 - - - simulation.tlm - - - - - PHASE - 0.000 - - - simulation.tlm - - - - - CLK_DOMAIN - - - - simulation.tlm - - - - - NUM_READ_THREADS - 1 - - - simulation.tlm - - - - - NUM_WRITE_THREADS - 1 - - - simulation.tlm - - - - - RUSER_BITS_PER_BYTE - 0 - - - simulation.tlm - - - - - WUSER_BITS_PER_BYTE - 0 - - - simulation.tlm - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - RESET - - - - - - - RST - - - aresetn - - - - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - ACLKEN - - - - - - - CE - - - aclken - - - - - - POLARITY - ACTIVE_LOW - - - none - - - - - - - - false - - - - - - CLOCK - - - - - - - CLK - - - aclk - - - - - - ASSOCIATED_BUSIF - M_AXI:S_AXI - - - ASSOCIATED_RESET - aresetn - - - FREQ_HZ - 100000000 - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - M_AXI_TLM - - - - - - - AXIMM_READ_SOCKET - - - M_INITIATOR_rd_socket - - - - - AXIMM_WRITE_SOCKET - - - M_INITIATOR_wr_socket - - - - - - S_AXI_TLM - - - - - - - AXIMM_READ_SOCKET - - - S_TARGET_rd_socket - - - - - AXIMM_WRITE_SOCKET - - - S_TARGET_wr_socket - - - - - - - - Master_AXI - 4294967296 - 32 - - - - true - - - - - - - - S_AXI - - Reg - 0 - 65536 - 32 - read-write - - - - false - - - - - - - - - - xilinx_veriloginstantiationtemplate - Verilog Instantiation Template - verilogSource:vivado.xilinx.com:synthesis.template - verilog - - xilinx_veriloginstantiationtemplate_view_fileset - - - - GENtimestamp - Wed Feb 02 19:13:37 UTC 2022 - - - outputProductCRC - 9:b40c5c85 - - - - - xilinx_verilogsynthesis - Verilog Synthesis - verilogSource:vivado.xilinx.com:synthesis - verilog - axi_vip_v1_1_8_top - - xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset - - - xilinx_verilogsynthesis_view_fileset - - - - GENtimestamp - Wed Feb 02 19:13:41 UTC 2022 - - - outputProductCRC - 9:b40c5c85 - - - - - xilinx_synthesisconstraints - Synthesis Constraints - :vivado.xilinx.com:synthesis.constraints - - xilinx_synthesisconstraints_view_fileset - - - - GENtimestamp - Wed Feb 02 19:13:41 UTC 2022 - - - outputProductCRC - 9:b40c5c85 - - - - - xilinx_verilogsynthesiswrapper - Verilog Synthesis Wrapper - verilogSource:vivado.xilinx.com:synthesis.wrapper - verilog - axi_mst_0 - - xilinx_verilogsynthesiswrapper_view_fileset - - - - GENtimestamp - Wed Feb 02 19:13:41 UTC 2022 - - - outputProductCRC - 9:b40c5c85 - - - - - xilinx_versioninformation - Version Information - :vivado.xilinx.com:docs.versioninfo - axi_vip_v1_1_8_top - - xilinx_versioninformation_view_fileset - - - - GENtimestamp - Wed Feb 02 19:13:41 UTC 2022 - - - outputProductCRC - 9:b40c5c85 - - - - - xilinx_externalfiles - External Files - :vivado.xilinx.com:external.files - - xilinx_externalfiles_view_fileset - - - - GENtimestamp - Wed Feb 02 19:14:59 UTC 2022 - - - outputProductCRC - 9:b40c5c85 - - - - - xilinx_verilogbehavioralsimulation - Verilog Simulation - verilogSource:vivado.xilinx.com:simulation - verilog - axi_vip_v1_1_8_top - - xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset - - - xilinx_verilogbehavioralsimulation_view_fileset - - - - GENtimestamp - Fri Mar 04 16:10:38 UTC 2022 - - - outputProductCRC - 9:a9f86b20 - - - - - xilinx_systemcsimulation - SystemC Simulation - systemCSource:vivado.xilinx.com:simulation - systemc - axi_vip - - xilinx_systemcsimulation_view_fileset - - - - GENtimestamp - Fri Mar 04 16:10:38 UTC 2022 - - - outputProductCRC - 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- sysc/axi_vip.cpp - systemCSource - axi_vip_v1_1_8 - - - sysc/axi_vip.h - systemCSource - true - axi_vip_v1_1_8 - - - - xilinx_verilogsimulationwrapper_view_fileset - - sim/axi_mst_0.sv - systemVerilogSource - xil_defaultlib - - - - xilinx_systemcsimulationwrapper_view_fileset - - sim/axi_mst_0_sc.h - systemCSource - true - - - sim/axi_mst_0_sc.cpp - systemCSource - - - sim/axi_mst_0.h - systemCSource - true - - - sim/axi_mst_0.cpp - systemCSource - - - sim/axi_mst_0_stub.sv - systemVerilogSource - - - - The AXI Verification IP. - - - Component_Name - Component Name - axi_mst_0 - - - PROTOCOL - PROTOCOL - AXI4LITE - - - READ_WRITE_MODE - READ_WRITE MODE - READ_WRITE - - - INTERFACE_MODE - INTERFACE MODE - MASTER - - - ADDR_WIDTH - ADDRESS WIDTH - 32 - - - DATA_WIDTH - DATA WIDTH - 32 - - - ID_WIDTH - ID WIDTH - 0 - - - - false - - - - - - AWUSER_WIDTH - AWUSER WIDTH - 0 - - - - false - - - - - - ARUSER_WIDTH - ARUSER WIDTH - 0 - - - - false - - - - - - RUSER_WIDTH - RUSER WIDTH - 0 - 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- - - - - - - - - - - - - - - - 2020.2 - - - - - - - - - - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/axi_slv.vhd b/qick/firmware/ip/axis_pfb_readout_v2/src/axi_slv.vhd deleted file mode 100644 index abafe46..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/axi_slv.vhd +++ /dev/null @@ -1,534 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity axi_slv is - Generic - ( - DATA_WIDTH : integer := 32; - ADDR_WIDTH : integer := 6 - ); - Port - ( - aclk : in std_logic; - aresetn : in std_logic; - - -- Write Address Channel. - awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); - awprot : in std_logic_vector(2 downto 0); - awvalid : in std_logic; - awready : out std_logic; - - -- Write Data Channel. - wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); - wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); - wvalid : in std_logic; - wready : out std_logic; - - -- Write Response Channel. - bresp : out std_logic_vector(1 downto 0); - bvalid : out std_logic; - bready : in std_logic; - - -- Read Address Channel. - araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); - arprot : in std_logic_vector(2 downto 0); - arvalid : in std_logic; - arready : out std_logic; - - -- Read Data Channel. - rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); - rresp : out std_logic_vector(1 downto 0); - rvalid : out std_logic; - rready : in std_logic; - - -- Registers. - FREQ0_REG : out std_logic_vector (31 downto 0); - FREQ1_REG : out std_logic_vector (31 downto 0); - FREQ2_REG : out std_logic_vector (31 downto 0); - FREQ3_REG : out std_logic_vector (31 downto 0); - FREQ4_REG : out std_logic_vector (31 downto 0); - FREQ5_REG : out std_logic_vector (31 downto 0); - FREQ6_REG : out std_logic_vector (31 downto 0); - FREQ7_REG : out std_logic_vector (31 downto 0); - OUTSEL_REG : out std_logic_vector (1 downto 0); - CH0SEL_REG : out std_logic_vector (2 downto 0); - CH1SEL_REG : out std_logic_vector (2 downto 0); - CH2SEL_REG : out std_logic_vector (2 downto 0); - CH3SEL_REG : out std_logic_vector (2 downto 0) - ); -end axi_slv; - -architecture rtl of axi_slv is - - -- AXI4LITE signals - signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); - signal axi_awready : std_logic; - signal axi_wready : std_logic; - signal axi_bresp : std_logic_vector(1 downto 0); - signal axi_bvalid : std_logic; - signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); - signal axi_arready : std_logic; - signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); - signal axi_rresp : std_logic_vector(1 downto 0); - signal axi_rvalid : std_logic; - - -- Example-specific design signals - -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH - -- ADDR_LSB is used for addressing 32/64 bit registers/memories - -- ADDR_LSB = 2 for 32 bits (n downto 2) - -- ADDR_LSB = 3 for 64 bits (n downto 3) - constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; - constant OPT_MEM_ADDR_BITS : integer := 3; - ------------------------------------------------ - ---- Signals for user logic register space example - -------------------------------------------------- - ---- Number of Slave Registers 16 - signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg_rden : std_logic; - signal slv_reg_wren : std_logic; - signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); - signal byte_index : integer; - signal aw_en : std_logic; - -begin - -- I/O Connections assignments - - awreadY <= axi_awready; - wready <= axi_wready; - bresp <= axi_bresp; - bvalid <= axi_bvalid; - arreadY <= axi_arready; - rdata <= axi_rdata; - rresp <= axi_rresp; - rvalid <= axi_rvalid; - -- Implement axi_awready generation - -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is - -- de-asserted when reset is low. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_awready <= '0'; - aw_en <= '1'; - else - if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then - -- slave is ready to accept write address when - -- there is a valid write address and write data - -- on the write address and data bus. This design - -- expects no outstanding transactions. - axi_awready <= '1'; - aw_en <= '0'; - elsif (bready = '1' and axi_bvalid = '1') then - aw_en <= '1'; - axi_awready <= '0'; - else - axi_awready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement axi_awaddr latching - -- This process is used to latch the address when both - -- S_AXI_AWVALID and S_AXI_WVALID are valid. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_awaddr <= (others => '0'); - else - if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then - -- Write Address latching - axi_awaddr <= awaddr; - end if; - end if; - end if; - end process; - - -- Implement axi_wready generation - -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is - -- de-asserted when reset is low. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_wready <= '0'; - else - if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then - -- slave is ready to accept write data when - -- there is a valid write address and write data - -- on the write address and data bus. This design - -- expects no outstanding transactions. - axi_wready <= '1'; - else - axi_wready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement memory mapped register select and write logic generation - -- The write data is accepted and written to memory mapped registers when - -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to - -- select byte enables of slave registers while writing. - -- These registers are cleared when reset (active low) is applied. - -- Slave register write enable is asserted when valid address and data are available - -- and the slave is ready to accept the write address and write data. - slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; - - process (aclk) - variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); - begin - if rising_edge(aclk) then - if aresetn = '0' then - slv_reg0 <= (others => '0'); - slv_reg1 <= (others => '0'); - slv_reg2 <= (others => '0'); - slv_reg3 <= (others => '0'); - slv_reg4 <= (others => '0'); - slv_reg5 <= (others => '0'); - slv_reg6 <= (others => '0'); - slv_reg7 <= (others => '0'); - slv_reg8 <= (others => '0'); - slv_reg9 <= (others => '0'); - slv_reg10 <= (others => '0'); - slv_reg11 <= (others => '0'); - slv_reg12 <= (others => '0'); - slv_reg13 <= (others => '0'); - slv_reg14 <= (others => '0'); - slv_reg15 <= (others => '0'); - else - loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); - if (slv_reg_wren = '1') then - case loc_addr is - when b"0000" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 0 - slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0001" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 1 - slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0010" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 2 - slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0011" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 3 - slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0100" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 4 - slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0101" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 5 - slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0110" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 6 - slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0111" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 7 - slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1000" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 8 - slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1001" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 9 - slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1010" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 10 - slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1011" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 11 - slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1100" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 12 - slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1101" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 13 - slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1110" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 14 - slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1111" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 15 - slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when others => - slv_reg0 <= slv_reg0; - slv_reg1 <= slv_reg1; - slv_reg2 <= slv_reg2; - slv_reg3 <= slv_reg3; - slv_reg4 <= slv_reg4; - slv_reg5 <= slv_reg5; - slv_reg6 <= slv_reg6; - slv_reg7 <= slv_reg7; - slv_reg8 <= slv_reg8; - slv_reg9 <= slv_reg9; - slv_reg10 <= slv_reg10; - slv_reg11 <= slv_reg11; - slv_reg12 <= slv_reg12; - slv_reg13 <= slv_reg13; - slv_reg14 <= slv_reg14; - slv_reg15 <= slv_reg15; - end case; - end if; - end if; - end if; - end process; - - -- Implement write response logic generation - -- The write response and response valid signals are asserted by the slave - -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. - -- This marks the acceptance of address and indicates the status of - -- write transaction. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_bvalid <= '0'; - axi_bresp <= "00"; --need to work more on the responses - else - if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then - axi_bvalid <= '1'; - axi_bresp <= "00"; - elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) - axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) - end if; - end if; - end if; - end process; - - -- Implement axi_arready generation - -- axi_arready is asserted for one S_AXI_ACLK clock cycle when - -- S_AXI_ARVALID is asserted. axi_awready is - -- de-asserted when reset (active low) is asserted. - -- The read address is also latched when S_AXI_ARVALID is - -- asserted. axi_araddr is reset to zero on reset assertion. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_arready <= '0'; - axi_araddr <= (others => '1'); - else - if (axi_arready = '0' and arvalid = '1') then - -- indicates that the slave has acceped the valid read address - axi_arready <= '1'; - -- Read Address latching - axi_araddr <= araddr; - else - axi_arready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement axi_arvalid generation - -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_ARVALID and axi_arready are asserted. The slave registers - -- data are available on the axi_rdata bus at this instance. The - -- assertion of axi_rvalid marks the validity of read data on the - -- bus and axi_rresp indicates the status of read transaction.axi_rvalid - -- is deasserted on reset (active low). axi_rresp and axi_rdata are - -- cleared to zero on reset (active low). - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_rvalid <= '0'; - axi_rresp <= "00"; - else - if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then - -- Valid read data is available at the read data bus - axi_rvalid <= '1'; - axi_rresp <= "00"; -- 'OKAY' response - elsif (axi_rvalid = '1' and rready = '1') then - -- Read data is accepted by the master - axi_rvalid <= '0'; - end if; - end if; - end if; - end process; - - -- Implement memory mapped register select and read logic generation - -- Slave register read enable is asserted when valid address is available - -- and the slave is ready to accept the read address. - slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; - - process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) - variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); - begin - -- Address decoding for reading registers - loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); - case loc_addr is - when b"0000" => - reg_data_out <= slv_reg0; - when b"0001" => - reg_data_out <= slv_reg1; - when b"0010" => - reg_data_out <= slv_reg2; - when b"0011" => - reg_data_out <= slv_reg3; - when b"0100" => - reg_data_out <= slv_reg4; - when b"0101" => - reg_data_out <= slv_reg5; - when b"0110" => - reg_data_out <= slv_reg6; - when b"0111" => - reg_data_out <= slv_reg7; - when b"1000" => - reg_data_out <= slv_reg8; - when b"1001" => - reg_data_out <= slv_reg9; - when b"1010" => - reg_data_out <= slv_reg10; - when b"1011" => - reg_data_out <= slv_reg11; - when b"1100" => - reg_data_out <= slv_reg12; - when b"1101" => - reg_data_out <= slv_reg13; - when b"1110" => - reg_data_out <= slv_reg14; - when b"1111" => - reg_data_out <= slv_reg15; - when others => - reg_data_out <= (others => '0'); - end case; - end process; - - -- Output register or memory read data - process( aclk ) is - begin - if (rising_edge (aclk)) then - if ( aresetn = '0' ) then - axi_rdata <= (others => '0'); - else - if (slv_reg_rden = '1') then - -- When there is a valid read address (S_AXI_ARVALID) with - -- acceptance of read address by the slave (axi_arready), - -- output the read dada - -- Read address mux - axi_rdata <= reg_data_out; -- register read data - end if; - end if; - end if; - end process; - - -- Output Registers. - FREQ0_REG <= slv_reg0; - FREQ1_REG <= slv_reg1; - FREQ2_REG <= slv_reg2; - FREQ3_REG <= slv_reg3; - FREQ4_REG <= slv_reg4; - FREQ5_REG <= slv_reg5; - FREQ6_REG <= slv_reg6; - FREQ7_REG <= slv_reg7; - OUTSEL_REG <= slv_reg8(1 downto 0); - CH0SEL_REG <= slv_reg9(2 downto 0); - CH1SEL_REG <= slv_reg10(2 downto 0); - CH2SEL_REG <= slv_reg11(2 downto 0); - CH3SEL_REG <= slv_reg12(2 downto 0); - -end rtl; - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/axis_pfb_readout_v2.v b/qick/firmware/ip/axis_pfb_readout_v2/src/axis_pfb_readout_v2.v deleted file mode 100644 index e7977bb..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/axis_pfb_readout_v2.v +++ /dev/null @@ -1,234 +0,0 @@ -module axis_pfb_readout_v2 - ( - // AXI Slave I/F for configuration. - s_axi_aclk , - s_axi_aresetn , - - s_axi_awaddr , - s_axi_awprot , - s_axi_awvalid , - s_axi_awready , - - s_axi_wdata , - s_axi_wstrb , - s_axi_wvalid , - s_axi_wready , - - s_axi_bresp , - s_axi_bvalid , - s_axi_bready , - - s_axi_araddr , - s_axi_arprot , - s_axi_arvalid , - s_axi_arready , - - s_axi_rdata , - s_axi_rresp , - s_axi_rvalid , - s_axi_rready , - - // s_* and m_* reset/clock. - aclk , - aresetn , - - // S_AXIS for input samples - s_axis_tvalid , - s_axis_tready , - s_axis_tdata , - - // M_AXIS for CH0 output. - m0_axis_tvalid , - m0_axis_tdata , - - // M_AXIS for CH1 output. - m1_axis_tvalid , - m1_axis_tdata , - - // M_AXIS for CH2 output. - m2_axis_tvalid , - m2_axis_tdata , - - // M_AXIS for CH3 output. - m3_axis_tvalid , - m3_axis_tdata - ); - -/**************/ -/* Parameters */ -/**************/ -// Input is interleaved I+Q, compatible with quad ADC (if false, input is not interleaved - compatible with dual ADC + combiner) -parameter INTERLEAVED_INPUT = 1; - -/*********/ -/* Ports */ -/*********/ -input s_axi_aclk; -input s_axi_aresetn; - -input [5:0] s_axi_awaddr; -input [2:0] s_axi_awprot; -input s_axi_awvalid; -output s_axi_awready; - -input [31:0] s_axi_wdata; -input [3:0] s_axi_wstrb; -input s_axi_wvalid; -output s_axi_wready; - -output [1:0] s_axi_bresp; -output s_axi_bvalid; -input s_axi_bready; - -input [5:0] s_axi_araddr; -input [2:0] s_axi_arprot; -input s_axi_arvalid; -output s_axi_arready; - -output [31:0] s_axi_rdata; -output [1:0] s_axi_rresp; -output s_axi_rvalid; -input s_axi_rready; - -input aresetn; -input aclk; - -input s_axis_tvalid; -output s_axis_tready; -input [4*32-1:0] s_axis_tdata; - -output m0_axis_tvalid; -output [31:0] m0_axis_tdata; - -output m1_axis_tvalid; -output [31:0] m1_axis_tdata; - -output m2_axis_tvalid; -output [31:0] m2_axis_tdata; - -output m3_axis_tvalid; -output [31:0] m3_axis_tdata; - -/********************/ -/* Internal signals */ -/********************/ -// Registers. -wire [31:0] FREQ0_REG; -wire [31:0] FREQ1_REG; -wire [31:0] FREQ2_REG; -wire [31:0] FREQ3_REG; -wire [31:0] FREQ4_REG; -wire [31:0] FREQ5_REG; -wire [31:0] FREQ6_REG; -wire [31:0] FREQ7_REG; -wire [1:0] OUTSEL_REG; -wire [2:0] CH0SEL_REG; -wire [2:0] CH1SEL_REG; -wire [2:0] CH2SEL_REG; -wire [2:0] CH3SEL_REG; - - -/**********************/ -/* Begin Architecture */ -/**********************/ -// AXI Slave. -axi_slv axi_slv_i - ( - .aclk (s_axi_aclk ), - .aresetn (s_axi_aresetn ), - - // Write Address Channel. - .awaddr (s_axi_awaddr ), - .awprot (s_axi_awprot ), - .awvalid (s_axi_awvalid ), - .awready (s_axi_awready ), - - // Write Data Channel. - .wdata (s_axi_wdata ), - .wstrb (s_axi_wstrb ), - .wvalid (s_axi_wvalid ), - .wready (s_axi_wready ), - - // Write Response Channel. - .bresp (s_axi_bresp ), - .bvalid (s_axi_bvalid ), - .bready (s_axi_bready ), - - // Read Address Channel. - .araddr (s_axi_araddr ), - .arprot (s_axi_arprot ), - .arvalid (s_axi_arvalid ), - .arready (s_axi_arready ), - - // Read Data Channel. - .rdata (s_axi_rdata ), - .rresp (s_axi_rresp ), - .rvalid (s_axi_rvalid ), - .rready (s_axi_rready ), - - // Registers. - .FREQ0_REG (FREQ0_REG ), - .FREQ1_REG (FREQ1_REG ), - .FREQ2_REG (FREQ2_REG ), - .FREQ3_REG (FREQ3_REG ), - .FREQ4_REG (FREQ4_REG ), - .FREQ5_REG (FREQ5_REG ), - .FREQ6_REG (FREQ6_REG ), - .FREQ7_REG (FREQ7_REG ), - .OUTSEL_REG (OUTSEL_REG ), - .CH0SEL_REG (CH0SEL_REG ), - .CH1SEL_REG (CH1SEL_REG ), - .CH2SEL_REG (CH2SEL_REG ), - .CH3SEL_REG (CH3SEL_REG ) - ); - -// PFB with DDS product. -pfb_dds_mux - #( - .INTERLEAVED_INPUT(INTERLEAVED_INPUT) - ) - pfb_dds_mux_i - ( - // Reset and clock. - .aresetn (aresetn ), - .aclk (aclk ), - - // S_AXIS for input data. - .s_axis_tready (s_axis_tready ), - .s_axis_tvalid (s_axis_tvalid ), - .s_axis_tdata (s_axis_tdata ), - - // M_AXIS for CH0 output. - .m0_axis_tvalid (m0_axis_tvalid ), - .m0_axis_tdata (m0_axis_tdata ), - - // M_AXIS for CH1 output. - .m1_axis_tvalid (m1_axis_tvalid ), - .m1_axis_tdata (m1_axis_tdata ), - - // M_AXIS for CH2 output. - .m2_axis_tvalid (m2_axis_tvalid ), - .m2_axis_tdata (m2_axis_tdata ), - - // M_AXIS for CH3 output. - .m3_axis_tvalid (m3_axis_tvalid ), - .m3_axis_tdata (m3_axis_tdata ), - - // Registers. - .FREQ0_REG (FREQ0_REG ), - .FREQ1_REG (FREQ1_REG ), - .FREQ2_REG (FREQ2_REG ), - .FREQ3_REG (FREQ3_REG ), - .FREQ4_REG (FREQ4_REG ), - .FREQ5_REG (FREQ5_REG ), - .FREQ6_REG (FREQ6_REG ), - .FREQ7_REG (FREQ7_REG ), - .OUTSEL_REG (OUTSEL_REG ), - .CH0SEL_REG (CH0SEL_REG ), - .CH1SEL_REG (CH1SEL_REG ), - .CH2SEL_REG (CH2SEL_REG ), - .CH3SEL_REG (CH3SEL_REG ) - ); - -endmodule - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/dds_0/dds_0.veo b/qick/firmware/ip/axis_pfb_readout_v2/src/dds_0/dds_0.veo deleted file mode 100644 index 2aa6467..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/dds_0/dds_0.veo +++ /dev/null @@ -1,69 +0,0 @@ -// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -// IP VLNV: xilinx.com:ip:dds_compiler:6.0 -// IP Revision: 20 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -dds_0 your_instance_name ( - .aclk(aclk), // input wire aclk - .s_axis_phase_tvalid(s_axis_phase_tvalid), // input wire s_axis_phase_tvalid - .s_axis_phase_tdata(s_axis_phase_tdata), // input wire [31 : 0] s_axis_phase_tdata - .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid - .m_axis_data_tdata(m_axis_data_tdata) // output wire [31 : 0] m_axis_data_tdata -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file dds_0.v when simulating -// the core, dds_0. When compiling the wrapper file, be sure to -// reference the Verilog simulation library. - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/dds_0/dds_0.xci b/qick/firmware/ip/axis_pfb_readout_v2/src/dds_0/dds_0.xci deleted file mode 100644 index f65db0d..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/dds_0/dds_0.xci +++ /dev/null @@ -1,312 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - dds_0 - - - - 100000000 - 0 - 0 - 0.000 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - 32 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 1 - 0 - 1 - 0 - 1 - 0 - 0 - 4 - 1 - 0 - 9 - 0 - 32 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 2 - 0 - 16 - 14 - 3 - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - 0 - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - 0 - 0 - 0 - 1 - 0 - 32 - 1 - 0 - zynquplus - Full_Range - 1 - dds_0 - Not_Required - 256 - Minimal - 0.06 - Coregen - false - false - false - false - 4 - Configurable - Not_Required - Not_Required - Auto - Standard - 9 - false - true - Auto - Twos_Complement - Auto - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Sine_and_Cosine - 16 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - false - System_Parameters - Phase_Generator_and_SIN_COS_LUT - Streaming - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 32 - None - false - On_Vector - Not_Required - 1 - 96 - false - 1 - zynquplusRFSOC - xilinx.com:zcu216:part0:2.0 - - xczu49dr - ffvf1760 - VERILOG - - MIXED - -2 - - E - TRUE - TRUE - IP_Flow - 20 - TRUE - ../../../../project_1.gen/sources_1/ip/dds_0 - - . - 2020.2 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/ddsprod.sv b/qick/firmware/ip/axis_pfb_readout_v2/src/ddsprod.sv deleted file mode 100644 index 985c391..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/ddsprod.sv +++ /dev/null @@ -1,183 +0,0 @@ -module ddsprod - ( - // Reset and clock. - aresetn , - aclk , - - // S_AXIS for input data. - s_axis_tvalid , - s_axis_tdata , - - // M_AXIS for output data. - m_axis_tvalid , - m_axis_tdata , - - // Registers. - FREQ_REG , - OUTSEL_REG - ); - -/*********/ -/* Ports */ -/*********/ -input aresetn; -input aclk; - -input s_axis_tvalid; -input [31:0] s_axis_tdata; - -output m_axis_tvalid; -output [31:0] m_axis_tdata; - -input [31:0] FREQ_REG; -input [1:0] OUTSEL_REG; - -/********************/ -/* Internal signals */ -/********************/ -// Input valid. -reg tvalid_r1; -reg tvalid_r2; -reg tvalid_r3; - -// DDS valid input. -reg dds_valid_r; - -// Input data. -reg [31:0] di_r1; -reg [31:0] di_r2; -reg [31:0] di_r3; -wire signed [15:0] di_real; -wire signed [15:0] di_imag; - -// DDS output. -wire [31:0] dds_dout; -reg [31:0] dds_dout_r1; -reg [31:0] dds_dout_r2; -reg [31:0] dds_dout_r3; -wire signed [15:0] dds_real; -wire signed [15:0] dds_imag; - -// Partial products. -wire signed [31:0] do_real_a; -wire signed [31:0] do_real_b; -reg signed [31:0] do_real_a_r1; -reg signed [31:0] do_real_b_r1; -wire signed [31:0] do_imag_a; -wire signed [31:0] do_imag_b; -reg signed [31:0] do_imag_a_r1; -reg signed [31:0] do_imag_b_r1; - -// Full out. -wire signed [31:0] do_real; -reg signed [15:0] do_real_r1; -wire signed [31:0] do_imag; -reg signed [15:0] do_imag_r1; - -// Muxed output. -wire [31:0] do_mux; - -/**********************/ -/* Begin Architecture */ -/**********************/ -// DDS instance. -dds_0 dds_i - ( - .aclk (aclk ), - .s_axis_phase_tvalid(dds_valid_r ), - .s_axis_phase_tdata (FREQ_REG ), - .m_axis_data_tvalid ( ), - .m_axis_data_tdata (dds_dout ) - ); - -// Input data. -assign di_real = di_r1[15:0]; -assign di_imag = di_r1[31:16]; - -// DDS output. -assign dds_real = dds_dout_r1[15:0]; -assign dds_imag = dds_dout_r1[31:16]; - -// Partial products. -assign do_real_a = di_real*dds_real; -assign do_real_b = di_imag*dds_imag; -assign do_imag_a = di_real*dds_imag; -assign do_imag_b = di_imag*dds_real; - -// Full out. -assign do_real = do_real_a_r1 - do_real_b_r1; -assign do_imag = do_imag_a_r1 + do_imag_b_r1; - -// Muxed output. -assign do_mux = (OUTSEL_REG == 0)? {do_imag_r1,do_real_r1} : - (OUTSEL_REG == 1)? di_r3 : - (OUTSEL_REG == 2)? dds_dout_r3 : 32'h0000_0000; - -// Registers. -always @(posedge aclk) begin - if (~aresetn) begin - // Input valid. - tvalid_r1 <= 0; - tvalid_r2 <= 0; - tvalid_r3 <= 0; - - // DDS valid input. - dds_valid_r <= 0; - - // Input data. - di_r1 <= 0; - di_r2 <= 0; - di_r3 <= 0; - - // DDS output. - dds_dout_r1 <= 0; - dds_dout_r2 <= 0; - dds_dout_r3 <= 0; - - // Partial products. - do_real_a_r1 <= 0; - do_real_b_r1 <= 0; - do_imag_a_r1 <= 0; - do_imag_b_r1 <= 0; - - // Full out. - do_real_r1 <= 0; - do_imag_r1 <= 0; - end - else begin - // Input valid. - tvalid_r1 <= s_axis_tvalid; - tvalid_r2 <= tvalid_r1; - tvalid_r3 <= tvalid_r2; - - // DDS valid input. - dds_valid_r <= 1; - - // Input data. - di_r1 <= s_axis_tdata; - di_r2 <= di_r1; - di_r3 <= di_r2; - - // DDS output. - dds_dout_r1 <= dds_dout; - dds_dout_r2 <= dds_dout_r1; - dds_dout_r3 <= dds_dout_r2; - - // Partial products. - do_real_a_r1 <= do_real_a; - do_real_b_r1 <= do_real_b; - do_imag_a_r1 <= do_imag_a; - do_imag_b_r1 <= do_imag_b; - - // Full out. - do_real_r1 <= do_real[30:15]; - do_imag_r1 <= do_imag[30:15]; - end -end - -// Assign outputs. -assign m_axis_tvalid = tvalid_r3; -assign m_axis_tdata = do_mux; - -endmodule - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/ddsprod_v.sv b/qick/firmware/ip/axis_pfb_readout_v2/src/ddsprod_v.sv deleted file mode 100644 index 64ba5e6..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/ddsprod_v.sv +++ /dev/null @@ -1,116 +0,0 @@ -module ddsprod_v - ( - // Reset and clock. - aresetn , - aclk , - - // S_AXIS for input data. - s_axis_tvalid , - s_axis_tdata , - - // M_AXIS for output data. - m_axis_tvalid , - m_axis_tdata , - - // Registers. - FREQ0_REG , - FREQ1_REG , - FREQ2_REG , - FREQ3_REG , - FREQ4_REG , - FREQ5_REG , - FREQ6_REG , - FREQ7_REG , - OUTSEL_REG - ); - -/*********/ -/* Ports */ -/*********/ -input aresetn; -input aclk; - -input s_axis_tvalid; -input [8*32-1:0] s_axis_tdata; - -output m_axis_tvalid; -output [8*32-1:0] m_axis_tdata; - -input [31:0] FREQ0_REG; -input [31:0] FREQ1_REG; -input [31:0] FREQ2_REG; -input [31:0] FREQ3_REG; -input [31:0] FREQ4_REG; -input [31:0] FREQ5_REG; -input [31:0] FREQ6_REG; -input [31:0] FREQ7_REG; -input [1:0] OUTSEL_REG; - -/********************/ -/* Internal signals */ -/********************/ -localparam L = 8; - -// Input data vector. -wire [31:0] din_v [0:L-1]; - -// Frequency registers. -wire [31:0] freq_reg_v [0:7]; - -// Output data vector. -wire [31:0] dout_v [0:L-1]; - -/**********************/ -/* Begin Architecture */ -/**********************/ -// Frequency registers. -assign freq_reg_v[0] = FREQ0_REG; -assign freq_reg_v[1] = FREQ1_REG; -assign freq_reg_v[2] = FREQ2_REG; -assign freq_reg_v[3] = FREQ3_REG; -assign freq_reg_v[4] = FREQ4_REG; -assign freq_reg_v[5] = FREQ5_REG; -assign freq_reg_v[6] = FREQ6_REG; -assign freq_reg_v[7] = FREQ7_REG; - -genvar i; -generate - for (i=0; i - - xilinx.com - xci - unknown - 1.0 - - - fir_0 - - - - 100000000 - 0 - 0 - 0.000 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 1 - 0 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - 31,31 - 31,31 - fixed - fir_0.mif - 7 - 2 - 0 - 0,0 - 0,0 - 16,16 - 0 - 16 - 7 - 1 - 4 - fir_0 - 0 - 0 - 1 - 0 - 0 - 16,16 - 0 - 0 - 0 - 0,0 - 0,1 - 16,16 - 16,16 - 16 - 1 - ./ - none - 5 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 13 - 2 - 0 - 0 - 32 - 1 - 1 - 1 - 7 - 1 - 7 - 0 - 0 - none - 0 - 16,16 - 1 - 16 - 1 - 0,1 - 1 - 2 - 0 - 1 - 0 - 32 - 1 - zynquplus - 2 - false - false - Basic - 300.0 - COE_File - 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 - Automatic - false - ../coef/fir_0.coe - 0 - false - 1 - Signed - Non_Symmetric - 16 - 7 - fir_0 - false - false - false - false - Not_Required - 1 - Automatic - 0 - false - false - Signed - 16 - 1 - false - false - Systolic_Multiply_Accumulate - 1 - Interpolated - Coregen - false - false - false - 1 - false - false - Automatic - 4 - 1 - false - Not_Required - Automatic - false - false - 1 - 1 - 2 - false - Area - None - None - false - Automatic - Symmetric_Rounding_to_Zero - 16 - 0.5 - 0.0 - P4-0,P4-1,P4-2,P4-3,P4-4 - false - Automatic - Integer_Coefficients - Input_Sample_Period - Integer - no_coe_file_loaded - true - Single - On_Vector - true - Not_Required - 1 - 0.001 - All - 1.0 - 0.5 - 2 - zynquplusRFSOC - xilinx.com:zcu216:part0:2.0 - - xczu49dr - ffvf1760 - VERILOG - - MIXED - -2 - - E - TRUE - TRUE - IP_Flow - 15 - TRUE - ../../../../ipgen.gen/sources_1/ip/fir_0 - - . - 2020.2 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/fir/fir_1/fir_1.xci b/qick/firmware/ip/axis_pfb_readout_v2/src/fir/fir_1/fir_1.xci deleted file mode 100644 index 1db52de..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/fir/fir_1/fir_1.xci +++ /dev/null @@ -1,312 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - fir_1 - - - - 100000000 - 0 - 0 - 0.000 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 1 - 0 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - 31,31 - 31,31 - fixed - fir_1.mif - 7 - 2 - 0 - 0,0 - 0,0 - 16,16 - 0 - 16 - 7 - 1 - 4 - fir_1 - 0 - 0 - 1 - 0 - 0 - 16,16 - 0 - 0 - 0 - 0,0 - 0,1 - 16,16 - 16,16 - 16 - 1 - ./ - none - 5 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 13 - 2 - 0 - 0 - 32 - 1 - 1 - 1 - 7 - 1 - 7 - 0 - 0 - none - 0 - 16,16 - 1 - 16 - 1 - 0,1 - 1 - 2 - 0 - 1 - 0 - 32 - 1 - zynquplus - 2 - false - false - Basic - 300.0 - COE_File - 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 - Automatic - false - ../coef/fir_1.coe - 0 - false - 1 - Signed - Non_Symmetric - 16 - 7 - fir_1 - false - false - false - false - Not_Required - 1 - Automatic - 0 - false - false - Signed - 16 - 1 - false - false - Systolic_Multiply_Accumulate - 1 - Interpolated - Coregen - false - false - false - 1 - false - false - Automatic - 4 - 1 - false - Not_Required - Automatic - false - false - 1 - 1 - 2 - false - Area - None - None - false - Automatic - Symmetric_Rounding_to_Zero - 16 - 0.5 - 0.0 - P4-0,P4-1,P4-2,P4-3,P4-4 - false - Automatic - Integer_Coefficients - Input_Sample_Period - Integer - no_coe_file_loaded - true - Single - On_Vector - true - Not_Required - 1 - 0.001 - All - 1.0 - 0.5 - 2 - zynquplusRFSOC - xilinx.com:zcu216:part0:2.0 - - xczu49dr - ffvf1760 - VERILOG - - MIXED - -2 - - E - TRUE - TRUE - IP_Flow - 15 - TRUE - ../../../../ipgen.gen/sources_1/ip/fir_1 - - . - 2020.2 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/fir/fir_2/fir_2.xci b/qick/firmware/ip/axis_pfb_readout_v2/src/fir/fir_2/fir_2.xci deleted file mode 100644 index 0f0a644..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/fir/fir_2/fir_2.xci +++ /dev/null @@ -1,312 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - fir_2 - - - - 100000000 - 0 - 0 - 0.000 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 1 - 0 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - 31,31 - 31,31 - fixed - fir_2.mif - 7 - 2 - 0 - 0,0 - 0,0 - 16,16 - 0 - 16 - 7 - 1 - 4 - fir_2 - 0 - 0 - 1 - 0 - 0 - 16,16 - 0 - 0 - 0 - 0,0 - 0,1 - 16,16 - 16,16 - 16 - 1 - ./ - none - 5 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 13 - 2 - 0 - 0 - 32 - 1 - 1 - 1 - 7 - 1 - 7 - 0 - 0 - none - 0 - 16,16 - 1 - 16 - 1 - 0,1 - 1 - 2 - 0 - 1 - 0 - 32 - 1 - zynquplus - 2 - false - false - Basic - 300.0 - COE_File - 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 - Automatic - false - ../coef/fir_2.coe - 0 - false - 1 - Signed - Non_Symmetric - 16 - 7 - fir_2 - false - false - false - false - Not_Required - 1 - Automatic - 0 - false - false - Signed - 16 - 1 - false - false - Systolic_Multiply_Accumulate - 1 - Interpolated - Coregen - false - false - false - 1 - false - false - Automatic - 4 - 1 - false - Not_Required - Automatic - false - false - 1 - 1 - 2 - false - Area - None - None - false - Automatic - Symmetric_Rounding_to_Zero - 16 - 0.5 - 0.0 - P4-0,P4-1,P4-2,P4-3,P4-4 - false - Automatic - Integer_Coefficients - Input_Sample_Period - Integer - no_coe_file_loaded - true - Single - On_Vector - true - Not_Required - 1 - 0.001 - All - 1.0 - 0.5 - 2 - zynquplusRFSOC - xilinx.com:zcu216:part0:2.0 - - xczu49dr - ffvf1760 - VERILOG - - MIXED - -2 - - E - TRUE - TRUE - IP_Flow - 15 - TRUE - ../../../../ipgen.gen/sources_1/ip/fir_2 - - . - 2020.2 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/fir/fir_3/fir_3.xci b/qick/firmware/ip/axis_pfb_readout_v2/src/fir/fir_3/fir_3.xci deleted file mode 100644 index d0fd7e8..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/fir/fir_3/fir_3.xci +++ /dev/null @@ -1,312 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - fir_3 - - - - 100000000 - 0 - 0 - 0.000 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 1 - 0 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - 31,31 - 31,31 - fixed - fir_3.mif - 7 - 2 - 0 - 0,0 - 0,0 - 16,16 - 0 - 16 - 7 - 1 - 4 - fir_3 - 0 - 0 - 1 - 0 - 0 - 16,16 - 0 - 0 - 0 - 0,0 - 0,1 - 16,16 - 16,16 - 16 - 1 - ./ - none - 5 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 13 - 2 - 0 - 0 - 32 - 1 - 1 - 1 - 7 - 1 - 7 - 0 - 0 - none - 0 - 16,16 - 1 - 16 - 1 - 0,1 - 1 - 2 - 0 - 1 - 0 - 32 - 1 - zynquplus - 2 - false - false - Basic - 300.0 - COE_File - 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 - Automatic - false - ../coef/fir_3.coe - 0 - false - 1 - Signed - Non_Symmetric - 16 - 7 - fir_3 - false - false - false - false - Not_Required - 1 - Automatic - 0 - false - false - Signed - 16 - 1 - false - false - Systolic_Multiply_Accumulate - 1 - Interpolated - Coregen - false - false - false - 1 - false - false - Automatic - 4 - 1 - false - Not_Required - Automatic - false - false - 1 - 1 - 2 - false - Area - None - None - false - Automatic - Symmetric_Rounding_to_Zero - 16 - 0.5 - 0.0 - P4-0,P4-1,P4-2,P4-3,P4-4 - false - Automatic - Integer_Coefficients - Input_Sample_Period - Integer - no_coe_file_loaded - true - Single - On_Vector - true - Not_Required - 1 - 0.001 - All - 1.0 - 0.5 - 2 - zynquplusRFSOC - xilinx.com:zcu216:part0:2.0 - - xczu49dr - ffvf1760 - VERILOG - - MIXED - -2 - - E - TRUE - TRUE - IP_Flow - 15 - TRUE - ../../../../ipgen.gen/sources_1/ip/fir_3 - - . - 2020.2 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/fir/fir_4/fir_4.xci b/qick/firmware/ip/axis_pfb_readout_v2/src/fir/fir_4/fir_4.xci deleted file mode 100644 index 48cef3a..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/fir/fir_4/fir_4.xci +++ /dev/null @@ -1,312 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - fir_4 - - - - 100000000 - 0 - 0 - 0.000 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 1 - 0 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - 31,31 - 31,31 - fixed - fir_4.mif - 7 - 2 - 0 - 0,0 - 0,0 - 16,16 - 0 - 16 - 7 - 1 - 4 - fir_4 - 0 - 0 - 1 - 0 - 0 - 16,16 - 0 - 0 - 0 - 0,0 - 0,1 - 16,16 - 16,16 - 16 - 1 - ./ - none - 5 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 13 - 2 - 0 - 0 - 32 - 1 - 1 - 1 - 7 - 1 - 7 - 0 - 0 - none - 0 - 16,16 - 1 - 16 - 1 - 0,1 - 1 - 2 - 0 - 1 - 0 - 32 - 1 - zynquplus - 2 - false - false - Basic - 300.0 - COE_File - 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 - Automatic - false - ../coef/fir_4.coe - 0 - false - 1 - Signed - Non_Symmetric - 16 - 7 - fir_4 - false - false - false - false - Not_Required - 1 - Automatic - 0 - false - false - Signed - 16 - 1 - false - false - Systolic_Multiply_Accumulate - 1 - Interpolated - Coregen - false - false - false - 1 - false - false - Automatic - 4 - 1 - false - Not_Required - Automatic - false - false - 1 - 1 - 2 - false - Area - None - None - false - Automatic - Symmetric_Rounding_to_Zero - 16 - 0.5 - 0.0 - P4-0,P4-1,P4-2,P4-3,P4-4 - false - Automatic - Integer_Coefficients - Input_Sample_Period - Integer - no_coe_file_loaded - true - Single - On_Vector - true - Not_Required - 1 - 0.001 - All - 1.0 - 0.5 - 2 - zynquplusRFSOC - xilinx.com:zcu216:part0:2.0 - - xczu49dr - ffvf1760 - VERILOG - - MIXED - -2 - - E - TRUE - TRUE - IP_Flow - 15 - TRUE - ../../../../ipgen.gen/sources_1/ip/fir_4 - - . - 2020.2 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/fir/fir_5/fir_5.xci b/qick/firmware/ip/axis_pfb_readout_v2/src/fir/fir_5/fir_5.xci deleted file mode 100644 index be396b4..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/fir/fir_5/fir_5.xci +++ /dev/null @@ -1,312 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - fir_5 - - - - 100000000 - 0 - 0 - 0.000 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 1 - 0 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - 31,31 - 31,31 - fixed - fir_5.mif - 7 - 2 - 0 - 0,0 - 0,0 - 16,16 - 0 - 16 - 7 - 1 - 4 - fir_5 - 0 - 0 - 1 - 0 - 0 - 16,16 - 0 - 0 - 0 - 0,0 - 0,1 - 16,16 - 16,16 - 16 - 1 - ./ - none - 5 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 13 - 2 - 0 - 0 - 32 - 1 - 1 - 1 - 7 - 1 - 7 - 0 - 0 - none - 0 - 16,16 - 1 - 16 - 1 - 0,1 - 1 - 2 - 0 - 1 - 0 - 32 - 1 - zynquplus - 2 - false - false - Basic - 300.0 - COE_File - 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 - Automatic - false - ../coef/fir_5.coe - 0 - false - 1 - Signed - Non_Symmetric - 16 - 7 - fir_5 - false - false - false - false - Not_Required - 1 - Automatic - 0 - false - false - Signed - 16 - 1 - false - false - Systolic_Multiply_Accumulate - 1 - Interpolated - Coregen - false - false - false - 1 - false - false - Automatic - 4 - 1 - false - Not_Required - Automatic - false - false - 1 - 1 - 2 - false - Area - None - None - false - Automatic - Symmetric_Rounding_to_Zero - 16 - 0.5 - 0.0 - P4-0,P4-1,P4-2,P4-3,P4-4 - false - Automatic - Integer_Coefficients - Input_Sample_Period - Integer - no_coe_file_loaded - true - Single - On_Vector - true - Not_Required - 1 - 0.001 - All - 1.0 - 0.5 - 2 - zynquplusRFSOC - xilinx.com:zcu216:part0:2.0 - - xczu49dr - ffvf1760 - VERILOG - - MIXED - -2 - - E - TRUE - TRUE - IP_Flow - 15 - TRUE - ../../../../ipgen.gen/sources_1/ip/fir_5 - - . - 2020.2 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/fir/fir_6/fir_6.xci b/qick/firmware/ip/axis_pfb_readout_v2/src/fir/fir_6/fir_6.xci deleted file mode 100644 index fb143ce..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/fir/fir_6/fir_6.xci +++ /dev/null @@ -1,312 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - fir_6 - - - - 100000000 - 0 - 0 - 0.000 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 1 - 0 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - 31,31 - 31,31 - fixed - fir_6.mif - 7 - 2 - 0 - 0,0 - 0,0 - 16,16 - 0 - 16 - 7 - 1 - 4 - fir_6 - 0 - 0 - 1 - 0 - 0 - 16,16 - 0 - 0 - 0 - 0,0 - 0,1 - 16,16 - 16,16 - 16 - 1 - ./ - none - 5 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 13 - 2 - 0 - 0 - 32 - 1 - 1 - 1 - 7 - 1 - 7 - 0 - 0 - none - 0 - 16,16 - 1 - 16 - 1 - 0,1 - 1 - 2 - 0 - 1 - 0 - 32 - 1 - zynquplus - 2 - false - false - Basic - 300.0 - COE_File - 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 - Automatic - false - ../coef/fir_6.coe - 0 - false - 1 - Signed - Non_Symmetric - 16 - 7 - fir_6 - false - false - false - false - Not_Required - 1 - Automatic - 0 - false - false - Signed - 16 - 1 - false - false - Systolic_Multiply_Accumulate - 1 - Interpolated - Coregen - false - false - false - 1 - false - false - Automatic - 4 - 1 - false - Not_Required - Automatic - false - false - 1 - 1 - 2 - false - Area - None - None - false - Automatic - Symmetric_Rounding_to_Zero - 16 - 0.5 - 0.0 - P4-0,P4-1,P4-2,P4-3,P4-4 - false - Automatic - Integer_Coefficients - Input_Sample_Period - Integer - no_coe_file_loaded - true - Single - On_Vector - true - Not_Required - 1 - 0.001 - All - 1.0 - 0.5 - 2 - zynquplusRFSOC - xilinx.com:zcu216:part0:2.0 - - xczu49dr - ffvf1760 - VERILOG - - MIXED - -2 - - E - TRUE - TRUE - IP_Flow - 15 - TRUE - ../../../../ipgen.gen/sources_1/ip/fir_6 - - . - 2020.2 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/fir/fir_7/fir_7.xci b/qick/firmware/ip/axis_pfb_readout_v2/src/fir/fir_7/fir_7.xci deleted file mode 100644 index bcf4c74..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/fir/fir_7/fir_7.xci +++ /dev/null @@ -1,312 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - fir_7 - - - - 100000000 - 0 - 0 - 0.000 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 1 - 0 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - 31,31 - 31,31 - fixed - fir_7.mif - 7 - 2 - 0 - 0,0 - 0,0 - 16,16 - 0 - 16 - 7 - 1 - 4 - fir_7 - 0 - 0 - 1 - 0 - 0 - 16,16 - 0 - 0 - 0 - 0,0 - 0,1 - 16,16 - 16,16 - 16 - 1 - ./ - none - 5 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 13 - 2 - 0 - 0 - 32 - 1 - 1 - 1 - 7 - 1 - 7 - 0 - 0 - none - 0 - 16,16 - 1 - 16 - 1 - 0,1 - 1 - 2 - 0 - 1 - 0 - 32 - 1 - zynquplus - 2 - false - false - Basic - 300.0 - COE_File - 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 - Automatic - false - ../coef/fir_7.coe - 0 - false - 1 - Signed - Non_Symmetric - 16 - 7 - fir_7 - false - false - false - false - Not_Required - 1 - Automatic - 0 - false - false - Signed - 16 - 1 - false - false - Systolic_Multiply_Accumulate - 1 - Interpolated - Coregen - false - false - false - 1 - false - false - Automatic - 4 - 1 - false - Not_Required - Automatic - false - false - 1 - 1 - 2 - false - Area - None - None - false - Automatic - Symmetric_Rounding_to_Zero - 16 - 0.5 - 0.0 - P4-0,P4-1,P4-2,P4-3,P4-4 - false - Automatic - Integer_Coefficients - Input_Sample_Period - Integer - no_coe_file_loaded - true - Single - On_Vector - true - Not_Required - 1 - 0.001 - All - 1.0 - 0.5 - 2 - zynquplusRFSOC - xilinx.com:zcu216:part0:2.0 - - xczu49dr - ffvf1760 - VERILOG - - MIXED - -2 - - E - TRUE - TRUE - IP_Flow - 15 - TRUE - ../../../../ipgen.gen/sources_1/ip/fir_7 - - . - 2020.2 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/fir/gen.pl b/qick/firmware/ip/axis_pfb_readout_v2/src/fir/gen.pl deleted file mode 100644 index deba046..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/fir/gen.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/perl -# This file generates the fir.tcl file to be run from vivado. -# Copy fir coefficient files. One IP per .coe file will be created. -# Copy generated .xci files to avoid generating FIR cores every time. - -open(my $file, "$ARGV[0]") or die "Could not open file '$ARGV[0]' $!"; -my @lines = <$file>; - -open(my $out_tcl, ">", "fir.tcl") or die "Could not open file fir.tcl $!"; -open(my $out_add, ">", "add.tcl") or die "Could not open file fir.tcl $!"; - -@out = `ls coef/*.coe`; -foreach (@out) -{ - chomp($_); - $fir = $_; - $fir =~ s/coef\///g; - $fir =~ s/.coe//g; - - print $out_add ("add_files ./fir/$fir/$fir.xci\n"); - - foreach my $line (@lines) - { - my $temp = $line; - chomp($temp); - $temp =~ s//$fir/g; - print $out_tcl ("$temp\n"); - } -} - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/fir/tcl/fir.tcl.template b/qick/firmware/ip/axis_pfb_readout_v2/src/fir/tcl/fir.tcl.template deleted file mode 100644 index 0264c07..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/fir/tcl/fir.tcl.template +++ /dev/null @@ -1,26 +0,0 @@ -create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name -set_property -dict [list \ - CONFIG.CoefficientSource {COE_File} \ - CONFIG.Coefficient_File {/home/lstefana/v20.2/ip/axis_pfb_readout/src/fir/coef/.coe} \ - CONFIG.Filter_Type {Interpolated} \ - CONFIG.Number_Paths {2} \ - CONFIG.RateSpecification {Input_Sample_Period} \ - CONFIG.Coefficient_Structure {Non_Symmetric} \ - CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ - CONFIG.Output_Width {16} \ - CONFIG.Coefficient_Sets {1} \ - CONFIG.Interpolation_Rate {1} \ - CONFIG.Decimation_Rate {1} \ - CONFIG.Zero_Pack_Factor {2} \ - CONFIG.Number_Channels {1} \ - CONFIG.SamplePeriod {1} \ - CONFIG.Sample_Frequency {0.001} \ - CONFIG.Clock_Frequency {300.0} \ - CONFIG.Coefficient_Sign {Signed} \ - CONFIG.Quantization {Integer_Coefficients} \ - CONFIG.Coefficient_Width {16} \ - CONFIG.Coefficient_Fractional_Bits {0} \ - CONFIG.Data_Width {16} \ - CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ - CONFIG.ColumnConfig {7}] \ -[get_ips ] diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/fir/tcl/ipgen.tcl b/qick/firmware/ip/axis_pfb_readout_v2/src/fir/tcl/ipgen.tcl deleted file mode 100644 index e1a3705..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/fir/tcl/ipgen.tcl +++ /dev/null @@ -1,13 +0,0 @@ -# Create project. -create_project ipgen ./ipgen -part xczu49dr-ffvf1760-2-e - -# Set language options. -set_property simulator_language Mixed [current_project] -set_property target_language Verilog [current_project] - -# Create IPs. -source fir.tcl - -# Generate instantiation templates. -generate_target instantiation_template [get_ips *] - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/firs.sv b/qick/firmware/ip/axis_pfb_readout_v2/src/firs.sv deleted file mode 100644 index c602e2b..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/firs.sv +++ /dev/null @@ -1,196 +0,0 @@ -module firs - ( - // Reset and clock. - aresetn , - aclk , - - // S_AXIS for input data. - s_axis_tready , - s_axis_tvalid , - s_axis_tdata , - - // M_AXIS for output data. - m_axis_tvalid , - m_axis_tdata - ); - -/**************/ -/* Parameters */ -/**************/ -// Number of Lanes (Input). -parameter L = 4; - -// Input is interleaved I+Q, compatible with quad ADC (if false, input is not interleaved - compatible with dual ADC + combiner) -parameter INTERLEAVED_INPUT = 1; - -/*********/ -/* Ports */ -/*********/ -input aresetn; -input aclk; - -output s_axis_tready; -input s_axis_tvalid; -input [L*32-1:0] s_axis_tdata; - -output m_axis_tvalid; -output [2*L*32-1:0] m_axis_tdata; - -/********************/ -/* Internal signals */ -/********************/ -// Input delay. -wire[31:0] data_v [0:L-1]; -reg [31:0] data_r1 [0:L-1]; -reg [31:0] data_r2 [0:L-1]; - -// Valid input. -reg valid_r; - -// FIR outputs. -wire[2*L-1:0] valid_v; -wire[31:0] dout_v [0:2*L-1]; - -/**********************/ -/* Begin Architecture */ -/**********************/ -genvar i; -generate - for (i=0; i '0'); - - -- sel register. - sel <= (others => '0'); - - -- Pipeline registers. - din_r <= (others => '0'); - din_rr <= (others => '0'); - valid_r <= '0'; - valid_rr <= '0'; - else - -- Signals combined after pm. - d_pm_r <= d_pm; - - -- sel register. - if (valid_r = '1') then - sel <= sel + 1; - end if; - - -- Pipeline registers. - din_r <= s_axis_tdata; - din_rr <= din_r; - valid_r <= s_axis_tvalid; - valid_rr <= valid_r; - end if; - end if; -end process; - --- Slice input. -GEN_SLICE_IN: for I in 0 to N-1 generate - dv_i(I) <= signed(din_r ( (I+1)*B-1 downto I*B)); - dv_q(I) <= signed(din_r ( N*B+ (I+1)*B-1 downto N*B+ I*B)); -end generate GEN_SLICE_IN; - --- Multiply by -1 only odd samples. -GEN_PM: for I in 0 to N/2-1 generate - -- Even samples: multiply always by 1. - dv_i_pm(2*I) <= dv_i(2*I); - - -- Odd samples: multiply by -1. Check maximum negative number. - dv_i_pm(2*I+1) <= to_signed(MAX_P,B) when dv_i(2*I+1) = to_signed(MIN_N,B) else - -dv_i(2*I+1); - - -- Even samples: multiply always by 1. - dv_q_pm(2*I) <= dv_q(2*I); - - -- Odd samples: multiply by -1. Check maximum negative number. - dv_q_pm(2*I+1) <= to_signed(MAX_P,B) when dv_q(2*I+1) = to_signed(MIN_N,B) else - -dv_q(2*I+1); -end generate GEN_PM; - --- Combine signals back. -GEN_COMBINE_PM: for I in 0 to N-1 generate - d_pm ( (I+1)*B-1 downto I*B) <= std_logic_vector(dv_i_pm(I)); - d_pm ( N*B+ (I+1)*B-1 downto N*B+I*B) <= std_logic_vector(dv_q_pm(I)); -end generate GEN_COMBINE_PM; - --- Data mux. -dout_mux <= din_rr when sel = to_unsigned(0,sel'length) else - d_pm_r; - - --- Assign outputs. -m_axis_tdata <= dout_mux; -m_axis_tvalid <= valid_rr; - -end rtl; - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/conv_pkg.vhd b/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/conv_pkg.vhd deleted file mode 100644 index b8f1a8f..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/conv_pkg.vhd +++ /dev/null @@ -1,1922 +0,0 @@ ---------------------------------------------------------------------- --- --- Package : conv_pkg --- --- Filename : conv_pkg.vhd --- --- Date : 8/16/99 --- --- Description : Package that defines constant values that is used in the --- XBS and functions that convert one type to another. --- --- Note : This package uses a VHDL 93 constructs therefore when --- compiling with ModelTech use: vcom -93 --- ---------------------------------------------------------------------- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -package conv_pkg is - --------------------------------------------------------------------------- - -- Constant that tells whether we're simulating - --------------------------------------------------------------------------- - constant simulating : boolean := false - -- synthesis translate_off - or true - -- synthesis translate_on - ; - - --------------------------------------------------------------------------- - -- Constants for XBS - --------------------------------------------------------------------------- - -- Arithmetic types - constant xlUnsigned : integer := 1; - constant xlSigned : integer := 2; - constant xlFloat : integer := 3; - - -- Constants for Quantization and Overflow - constant xlWrap : integer := 1; - constant xlSaturate : integer := 2; - constant xlTruncate : integer := 1; - constant xlRound : integer := 2; - constant xlRoundBanker : integer := 3; - - -- Constants for xladdsub s-function - constant xlAddMode : integer := 1; - constant xlSubMode : integer := 2; - - --------------------------------------------------------------------------- - -- Black Box Attributes - --------------------------------------------------------------------------- - attribute black_box : boolean; -- for Synplicity (obsolete) - attribute syn_black_box : boolean; -- for Synplicity Version 6.0 - attribute fpga_dont_touch: string; -- for FPGA Express - attribute box_type : string; -- for XST - - --------------------------------------------------------------------------- - -- Attributes to keep clock enable signals - --------------------------------------------------------------------------- - attribute keep : string; - attribute syn_keep : boolean; - - --------------------------------------------------------------------------- - -- Arithmetic conversion functions - --------------------------------------------------------------------------- - -- convert a std_logic_vector to a unsigned type and vice versa - function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned; - function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector; - - -- convert a std_logic_vector to a signed type and vice versa - function std_logic_vector_to_signed(inp : std_logic_vector) return signed; - function signed_to_std_logic_vector(inp : signed) return std_logic_vector; - -- convert signed to unsigned and vice versa - function unsigned_to_signed(inp : unsigned) return signed; - function signed_to_unsigned(inp : signed) return unsigned; - -- Tests used in convert_type - function pos(inp : std_logic_vector; arith : INTEGER) return boolean; - function all_same(inp: std_logic_vector) return boolean; - function all_zeros(inp: std_logic_vector) return boolean; - function is_point_five(inp: std_logic_vector) return boolean; - function all_ones(inp: std_logic_vector) return boolean; - - - - -- Convert a fixed point type to another fixed point type with a - -- different bin_pt, width, and arithmetic type - function convert_type (inp : std_logic_vector; old_width, old_bin_pt, - old_arith, new_width, new_bin_pt, new_arith, - quantization, overflow : INTEGER) - return std_logic_vector; - - -- Cast type by zero pading or Sign extending MSB and - -- zero pading or truncating LSB - function cast (inp : std_logic_vector; old_bin_pt, - new_width, new_bin_pt, new_arith : INTEGER) - return std_logic_vector; - - function shift_division_result(quotient, fraction: std_logic_vector; - fraction_width, shift_value, shift_dir: INTEGER) - return std_logic_vector; - - function shift_op (inp: std_logic_vector; - result_width, shift_value, shift_dir: INTEGER) - return std_logic_vector; - - -- slice a vector - function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) - return std_logic_vector; - - -- slice a signed - function s2u_slice (inp : signed; upper, lower : INTEGER) - return unsigned; - - -- slice a unsigned - function u2u_slice (inp : unsigned; upper, lower : INTEGER) - return unsigned; - - -- Cast signed to signed - function s2s_cast (inp : signed; old_bin_pt, - new_width, new_bin_pt : INTEGER) - return signed; - -- Cast unsigned to signed - function u2s_cast (inp : unsigned; old_bin_pt, - new_width, new_bin_pt : INTEGER) - return signed; - -- Cast signed to unsigned - function s2u_cast (inp : signed; old_bin_pt, - new_width, new_bin_pt : INTEGER) - return unsigned; - -- Cast unsigned to unsigned - function u2u_cast (inp : unsigned; old_bin_pt, - new_width, new_bin_pt : INTEGER) - return unsigned; - -- Cast unsigned to std_logic_vector - function u2v_cast (inp : unsigned; old_bin_pt, - new_width, new_bin_pt : INTEGER) - return std_logic_vector; - -- Cast signed to std_logic_vector - function s2v_cast (inp : signed; old_bin_pt, - new_width, new_bin_pt : INTEGER) - return std_logic_vector; - -- Quantization Functions - function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, - new_width, new_bin_pt, new_arith : INTEGER) - return std_logic_vector; - function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, - old_arith, new_width, new_bin_pt, - new_arith : INTEGER) return std_logic_vector; - function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, - old_arith, new_width, new_bin_pt, - new_arith : INTEGER) return std_logic_vector; - - -- Overflow functions - function max_signed(width : INTEGER) return std_logic_vector; - function min_signed(width : INTEGER) return std_logic_vector; - function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, - old_arith, new_width, new_bin_pt, new_arith - : INTEGER) return std_logic_vector; - function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, - old_arith, new_width, new_bin_pt, new_arith : INTEGER) - return std_logic_vector; - - --------------------------------------------------------------------------- - -- Binary point alignment functions - --------------------------------------------------------------------------- - - -- Returns the number of fractional bits after alignment of fixed point num - function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER; - - -- Returns the number of integer bits after alignment of fixed point num. - function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) - return INTEGER; - - - -- sign extend the MSB - function sign_ext(inp : std_logic_vector; new_width : INTEGER) - return std_logic_vector; - - -- zero extend the MSB - function zero_ext(inp : std_logic_vector; new_width : INTEGER) - return std_logic_vector; - - -- zero extend the MSB - function zero_ext(inp : std_logic; new_width : INTEGER) - return std_logic_vector; - - -- zero or sign extend the MSB - function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) - return std_logic_vector; - - -- Align input by padding LSB with zeros and sign or zero extening - function align_input(inp : std_logic_vector; old_width, delta, new_arith, - new_width: INTEGER) - return std_logic_vector; - - -- Pad LSB with zeros - function pad_LSB(inp : std_logic_vector; new_width: integer) - return std_logic_vector; - -- Pad LSB with zeros and add a zero or sign extend the MSB - function pad_LSB(inp : std_logic_vector; new_width, arith : integer) - return std_logic_vector; - - -- Find the max & min integer. - function max(L, R: INTEGER) return INTEGER; - function min(L, R: INTEGER) return INTEGER; - - -- Test is two strings are equal - function "="(left,right: STRING) return boolean; - - -- convert a boolean into a signed - function boolean_to_signed (inp : boolean; width: integer) - return signed; - -- convert a boolean into an unsigned - function boolean_to_unsigned (inp : boolean; width: integer) - return unsigned; - -- convert a boolean into std_logic_vector - function boolean_to_vector (inp : boolean) - return std_logic_vector; - -- convert a std_logic into std_logic_vector - function std_logic_to_vector (inp : std_logic) - return std_logic_vector; - -- convert an integer into a std_logic_vector - function integer_to_std_logic_vector (inp : integer; width, arith : integer) - return std_logic_vector; - - -- Convert std_logic or std_logic_vector to an integer - function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) - return integer; - function std_logic_to_integer(constant inp : std_logic := '0') - return integer; - - -- Convert a binary string array element into a std_logic_vector - function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) - return std_logic_vector; - -- convert a binary string into a std_logic_vector (e.g., 0b10.1 = 101) - function bin_string_to_std_logic_vector (inp : string) - return std_logic_vector; - -- convert a hex string to a std_logic_vector - function hex_string_to_std_logic_vector (inp : string; width : integer) - return std_logic_vector; - - -- Make a binary string that represents zero - function makeZeroBinStr (width : integer) return STRING; - - - --------------------------------------------------------------------------- - -- Debugging functions - --------------------------------------------------------------------------- - -- synthesis translate_off - - -- Check for all X's (i.e., 0bXX.X) - function is_binary_string_invalid (inp : string) - return boolean; - -- Check for all U's (i.e., 0bUU.U) - function is_binary_string_undefined (inp : string) - return boolean; - - -- Check for Undefined values - function is_XorU(inp : std_logic_vector) - return boolean; - - - -- convert a std_logic_vector to a real type and vice versa - function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) - return real; - function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) - return real; - - - -- convert a real into a std_logic_vector - function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) - return std_logic_vector; - -- convert a real string into a std_logic_vector - function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) - return std_logic_vector; - - -- display_precision is the number of digits to display in ModelTech's - -- waveform viewer ( used in to_string(inp : real) ) - constant display_precision : integer := 20; - -- convert a real into a string type - function real_to_string (inp : real) return string; - - -- Check of 0b and the beginning of a string - function valid_bin_string(inp : string) return boolean; - - -- Convert a std_logic_vector to a binary string - function std_logic_vector_to_bin_string(inp : std_logic_vector) return string; - -- Convert a std_logic to a binary string - function std_logic_to_bin_string(inp : std_logic) return string; - -- convert a std_logic_vector to a binary string and add a binary point - function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) - return string; - -- Convert a real to a binary string - function real_to_bin_string(inp : real; width, bin_pt, arith : integer) - return string; - - -- convert a std_logic_vector value to a character - type stdlogic_to_char_t is array(std_logic) of character; - constant to_char : stdlogic_to_char_t := ( - 'U' => 'U', - 'X' => 'X', - '0' => '0', - '1' => '1', - 'Z' => 'Z', - 'W' => 'W', - 'L' => 'L', - 'H' => 'H', - '-' => '-'); - - -- synthesis translate_on - -end conv_pkg; - -package body conv_pkg is - - --------------------------------------------------------------------------- - -- Arithmetic conversion functions - --------------------------------------------------------------------------- - -- convert a std_logic_vector to a unsigned type - function std_logic_vector_to_unsigned(inp : std_logic_vector) - return unsigned - is - begin - return unsigned (inp); - end; - - -- convert an unsigend to a std_logic_vector - function unsigned_to_std_logic_vector(inp : unsigned) - return std_logic_vector - is - begin - return std_logic_vector(inp); - end; - - -- convert an std_logic_vector to a signed - function std_logic_vector_to_signed(inp : std_logic_vector) - return signed - is - begin - return signed (inp); - end; - - -- convert an std_logic_vector to a sigend - function signed_to_std_logic_vector(inp : signed) - return std_logic_vector - is - begin - return std_logic_vector(inp); - end; - - -- convert unsigned to signed - function unsigned_to_signed (inp : unsigned) - return signed - is - begin -- unsigned_to_signed - return signed(std_logic_vector(inp)); - end; - - - -- convert signed to unsigned - function signed_to_unsigned (inp : signed) - return unsigned - is - begin -- signed_to_unsigned - return unsigned(std_logic_vector(inp)); - end; - - -- Test if a number is positive - function pos(inp : std_logic_vector; arith : INTEGER) - return boolean - is - constant width : integer := inp'length; - variable vec : std_logic_vector(width-1 downto 0); - - begin - vec := inp; - if arith = xlUnsigned then - return true; - else - if vec(width-1) = '0' then - return true; - else - return false; - end if; - end if; - - -- Error - return true; - end; - - function max_signed(width : INTEGER) - return std_logic_vector - is - variable ones : std_logic_vector(width-2 downto 0); - variable result : std_logic_vector(width-1 downto 0); - begin - ones := (others => '1'); - result(width-1) := '0'; - result(width-2 downto 0) := ones; - return result; - end; - - function min_signed(width : INTEGER) - return std_logic_vector - is - variable zeros : std_logic_vector(width-2 downto 0); - variable result : std_logic_vector(width-1 downto 0); - begin - zeros := (others => '0'); - result(width-1) := '1'; - result(width-2 downto 0) := zeros; - return result; - end; - - -- Check if all the bits are the same - function all_same(inp: std_logic_vector) return boolean - is - variable result: boolean; - constant width : integer := inp'length; - variable vec : std_logic_vector(width-1 downto 0); - begin - vec := inp; - result := true; - if width > 0 then - for i in 1 to width-1 loop - if vec(i) /= vec(0) then - result := false; - end if; - end loop; - end if; - return result; - end; - - - -- Check if a number is all zeros - function all_zeros(inp: std_logic_vector) - return boolean - is - constant width : integer := inp'length; - variable vec : std_logic_vector(width-1 downto 0); - variable zero : std_logic_vector(width-1 downto 0); - variable result : boolean; - begin - zero := (others => '0'); - vec := inp; - -- synthesis translate_off - if (is_XorU(vec)) then - return false; - end if; - -- synthesis translate_on - - if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then - result := true; - else - result := false; - end if; - return result; - end; - - -- Check if a number is point five - function is_point_five(inp: std_logic_vector) - return boolean - is - constant width : integer := inp'length; - variable vec : std_logic_vector(width-1 downto 0); - variable result : boolean; - begin - vec := inp; - -- synthesis translate_off - if (is_XorU(vec)) then - return false; - end if; - -- synthesis translate_on - if (width > 1) then - if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then - result := true; - else - result := false; - end if; - else - if (vec(width-1) = '1') then - result := true; - else - result := false; - end if; - end if; - - return result; - end; - - -- Check if a number is all ones - function all_ones(inp: std_logic_vector) - return boolean - is - constant width : integer := inp'length; - variable vec : std_logic_vector(width-1 downto 0); - variable one : std_logic_vector(width-1 downto 0); - variable result : boolean; - begin - one := (others => '1'); - vec := inp; - -- synthesis translate_off - if (is_XorU(vec)) then - return false; - end if; - -- synthesis translate_on - if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then - result := true; - else - result := false; - end if; - return result; - end; - - - --------------------------------------------------------------------------- - -- Type conersion functions - --------------------------------------------------------------------------- - - - -- Calculate the width of the temp. full precision representation - function full_precision_num_width(quantization, overflow, old_width, - old_bin_pt, old_arith, - new_width, new_bin_pt, new_arith : INTEGER) - return integer - is - variable result : integer; - begin - result := old_width + 2; - return result; - end; - - -- Calculate the width of the temp. quantized representation - -- ASSUMES POSITIVE BIN_PT - function quantized_num_width(quantization, overflow, old_width, old_bin_pt, - old_arith, new_width, new_bin_pt, new_arith - : INTEGER) - return integer - is - variable right_of_dp, left_of_dp, result : integer; - begin - - right_of_dp := max(new_bin_pt, old_bin_pt); - left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt)); - - result := (old_width + 2) + (new_bin_pt - old_bin_pt); - return result; - end; - - - - -- Convert one Fix point type to another fixed point type with a - -- different bin_pt, width, and arithmetic type - function convert_type (inp : std_logic_vector; old_width, old_bin_pt, - old_arith, new_width, new_bin_pt, new_arith, - quantization, overflow : INTEGER) - return std_logic_vector - is - constant fp_width : integer := - full_precision_num_width(quantization, overflow, old_width, - old_bin_pt, old_arith, new_width, - new_bin_pt, new_arith); - constant fp_bin_pt : integer := old_bin_pt; - constant fp_arith : integer := old_arith; - variable full_precision_result : std_logic_vector(fp_width-1 downto 0); - - constant q_width : integer := - quantized_num_width(quantization, overflow, old_width, old_bin_pt, - old_arith, new_width, new_bin_pt, new_arith); - constant q_bin_pt : integer := new_bin_pt; - constant q_arith : integer := old_arith; - variable quantized_result : std_logic_vector(q_width-1 downto 0); - - variable result : std_logic_vector(new_width-1 downto 0); - begin - result := (others => '0'); - - full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt, - fp_arith); - - -- Apply quantization functions. This will remove LSB bits. - if (quantization = xlRound) then - - quantized_result := round_towards_inf(full_precision_result, - fp_width, fp_bin_pt, - fp_arith, q_width, q_bin_pt, - q_arith); - elsif (quantization = xlRoundBanker) then - quantized_result := round_towards_even(full_precision_result, - fp_width, fp_bin_pt, - fp_arith, q_width, q_bin_pt, - q_arith); - else - quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt, - fp_arith, q_width, q_bin_pt, q_arith); - end if; - - - -- Apply overflow function. This will remove MSB bits. - if (overflow = xlSaturate) then - result := saturation_arith(quantized_result, q_width, q_bin_pt, - q_arith, new_width, new_bin_pt, new_arith); - else - result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith, - new_width, new_bin_pt, new_arith); - end if; - - - return result; - end; - - -- Cast type by zero pading or Sign extending MSB and - -- zero pading or truncating LSB - function cast (inp : std_logic_vector; old_bin_pt, new_width, - new_bin_pt, new_arith : INTEGER) - return std_logic_vector - is - constant old_width : integer := inp'length; - -- Number of digits to add/subract to the left of the decimal point - constant left_of_dp : integer := (new_width - new_bin_pt) - - (old_width - old_bin_pt); - -- Number of digits to add/subract to the right of the decimal point - constant right_of_dp : integer := (new_bin_pt - old_bin_pt); - - variable vec : std_logic_vector(old_width-1 downto 0); - variable result : std_logic_vector(new_width-1 downto 0); - variable j : integer; - - begin - vec := inp; - for i in new_width-1 downto 0 loop - j := i - right_of_dp; - if ( j > old_width-1) then - -- Bits to the left of the decimal point - if (new_arith = xlUnsigned) then - -- If unsigned zero pad MSB - result(i) := '0'; - else - -- If signed, sign extend MSB - result(i) := vec(old_width-1); - end if; - elsif ( j >= 0) then - -- Copy bits from input - result(i) := vec(j); - else - -- zero pad LSB - result(i) := '0'; - end if; - end loop; - - return result; - end; - - function shift_division_result(quotient, fraction: std_logic_vector; - fraction_width, shift_value, shift_dir: INTEGER) - return std_logic_vector - is - constant q_width : integer := quotient'length; - constant f_width : integer := fraction'length; - constant vec_MSB : integer := q_width+f_width-1; - constant result_MSB : integer := q_width+fraction_width-1; - constant result_LSB : integer := vec_MSB-result_MSB; - variable vec : std_logic_vector(vec_MSB downto 0); - variable result : std_logic_vector(result_MSB downto 0); - begin - vec := ( quotient & fraction ); - if shift_dir = 1 then - for i in vec_MSB downto 0 loop - if (i < shift_value) then - vec(i) := '0'; - else - vec(i) := vec(i-shift_value); - end if; - end loop; - --vec := vec sll shift_value; - else - for i in 0 to vec_MSB loop - if (i > vec_MSB-shift_value) then - vec(i) := vec(vec_MSB); - else - vec(i) := vec(i+shift_value); - end if; - end loop; - --vec := vec srl shift_value; - end if; - result := vec(vec_MSB downto result_LSB); - return result; - end; - - - function shift_op (inp: std_logic_vector; - result_width, shift_value, shift_dir: INTEGER) - return std_logic_vector - is - constant inp_width : integer := inp'length; - constant vec_MSB : integer := inp_width-1; - constant result_MSB : integer := result_width-1; - constant result_LSB : integer := vec_MSB-result_MSB; - variable vec : std_logic_vector(vec_MSB downto 0); - variable result : std_logic_vector(result_MSB downto 0); - begin - vec := inp; - if shift_dir = 1 then - for i in vec_MSB downto 0 loop - if (i < shift_value) then - vec(i) := '0'; - else - vec(i) := vec(i-shift_value); - end if; - end loop; - --vec := vec sll shift_value; - else - for i in 0 to vec_MSB loop - if (i > vec_MSB-shift_value) then - vec(i) := vec(vec_MSB); - else - vec(i) := vec(i+shift_value); - end if; - end loop; - --vec := vec srl shift_value; - end if; - result := vec(vec_MSB downto result_LSB); - return result; - end; - - - -- vector slice - function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) - return std_logic_vector - is - begin - return inp(upper downto lower); - end; - - -- signed slice - function s2u_slice (inp : signed; upper, lower : INTEGER) - return unsigned - is - begin - return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); - end; - - -- unsigned slice - function u2u_slice (inp : unsigned; upper, lower : INTEGER) - return unsigned - is - begin - return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); - end; - - -- Cast signed to signed - function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) - return signed - is - begin - return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); - end; - - -- Cast signed to unsigned - function s2u_cast (inp : signed; old_bin_pt, new_width, - new_bin_pt : INTEGER) - return unsigned - is - begin - return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); - end; - - -- Cast unsigned to signed - function u2s_cast (inp : unsigned; old_bin_pt, new_width, - new_bin_pt : INTEGER) - return signed - is - begin - return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); - end; - - -- Cast unsigned to unsigned - function u2u_cast (inp : unsigned; old_bin_pt, new_width, - new_bin_pt : INTEGER) - return unsigned - is - begin - return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); - end; - - -- Cast unsigned to std_logic_vector - function u2v_cast (inp : unsigned; old_bin_pt, new_width, - new_bin_pt : INTEGER) - return std_logic_vector - is - begin - return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned); - end; - - -- Cast signed to std_logic_vector - function s2v_cast (inp : signed; old_bin_pt, new_width, - new_bin_pt : INTEGER) - return std_logic_vector - is - begin - return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned); - end; - - function boolean_to_signed (inp : boolean; width : integer) - return signed - is - variable result : signed(width - 1 downto 0); - begin - result := (others => '0'); - if inp then - result(0) := '1'; - else - result(0) := '0'; - end if; - return result; - end; - - function boolean_to_unsigned (inp : boolean; width : integer) - return unsigned - is - variable result : unsigned(width - 1 downto 0); - begin - result := (others => '0'); - if inp then - result(0) := '1'; - else - result(0) := '0'; - end if; - return result; - end; - - function boolean_to_vector (inp : boolean) - return std_logic_vector - is - variable result : std_logic_vector(1 - 1 downto 0); - begin - result := (others => '0'); - if inp then - result(0) := '1'; - else - result(0) := '0'; - end if; - return result; - end; - - function std_logic_to_vector (inp : std_logic) - return std_logic_vector - is - variable result : std_logic_vector(1 - 1 downto 0); - begin - result(0) := inp; - return result; - end; - - --------------------------------------------------------------------------- - -- Quantization Functions - --------------------------------------------------------------------------- - - -- Truncate LSB bits - function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, - new_width, new_bin_pt, new_arith : INTEGER) - return std_logic_vector - is - -- Number of binary digits to add/subract to the right of the decimal - -- point - constant right_of_dp : integer := (old_bin_pt - new_bin_pt); - variable vec : std_logic_vector(old_width-1 downto 0); - variable result : std_logic_vector(new_width-1 downto 0); - begin - vec := inp; - - if right_of_dp >= 0 then - -- Sign Extent or zero extend if necessary - if new_arith = xlUnsigned then - result := zero_ext(vec(old_width-1 downto right_of_dp), new_width); - else - result := sign_ext(vec(old_width-1 downto right_of_dp), new_width); - end if; - else - -- Pad LSB with zeros and sign extend by one bit - if new_arith = xlUnsigned then - result := zero_ext(pad_LSB(vec, old_width + - abs(right_of_dp)), new_width); - else - result := sign_ext(pad_LSB(vec, old_width + - abs(right_of_dp)), new_width); - end if; - end if; - return result; - end; - - - -- Round towards infinity - function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, - old_arith, new_width, new_bin_pt, new_arith - : INTEGER) - return std_logic_vector - is - -- Number of binary digits to add/subract to the right of the decimal - -- point - constant right_of_dp : integer := (old_bin_pt - new_bin_pt); - - constant expected_new_width : integer := old_width - right_of_dp + 1; - variable vec : std_logic_vector(old_width-1 downto 0); - variable one_or_zero : std_logic_vector(new_width-1 downto 0); - variable truncated_val : std_logic_vector(new_width-1 downto 0); - variable result : std_logic_vector(new_width-1 downto 0); - begin - vec := inp; - - - if right_of_dp >= 0 then - -- Sign extend or zero extend to size of output - if new_arith = xlUnsigned then - truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), - new_width); - else - truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), - new_width); - end if; - else - -- Pad LSB with zeros and sign extend by one bit - if new_arith = xlUnsigned then - truncated_val := zero_ext(pad_LSB(vec, old_width + - abs(right_of_dp)), new_width); - else - truncated_val := sign_ext(pad_LSB(vec, old_width + - abs(right_of_dp)), new_width); - end if; - end if; - - - -- Figure out if '1' should be added to the truncated number - one_or_zero := (others => '0'); - - if (new_arith = xlSigned) then - -- Roundeing logic for signed numbers - -- Example: - -- Fix(5,-2) = 101.11 (bin) -2.25 (dec) - -- Converted to: Fix(4,-1) = 101.1 (bin) -2.5 (dec) - -- Note: same algorithm used for unsigned numbers can't be used. - - -- 1st check the sign bit of the input to see if it is a positive - -- number - if (vec(old_width-1) = '0') then - one_or_zero(0) := '1'; - end if; - - -- 2nd check if digits being truncated are all zeros - -- (in example it is bit zero) - if (right_of_dp >= 2) and (right_of_dp <= old_width) then - if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then - one_or_zero(0) := '1'; - end if; - end if; - - -- 3rd check if the bit right before the truncation point is '1' - -- or '0' (in example it is bit one) - if (right_of_dp >= 1) and (right_of_dp <= old_width) then - if vec(right_of_dp-1) = '0' then - one_or_zero(0) := '0'; - end if; - else - -- No rounding to be performed - one_or_zero(0) := '0'; - end if; - else - -- For an unsigned number just check if the bit right before the - -- truncation point is '1' or '0' - if (right_of_dp >= 1) and (right_of_dp <= old_width) then - one_or_zero(0) := vec(right_of_dp-1); - end if; - end if; - - - if new_arith = xlSigned then - result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + - std_logic_vector_to_signed(one_or_zero)); - else - result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + - std_logic_vector_to_unsigned(one_or_zero)); - end if; - - return result; - end; - - -- Round towards even values - function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, - old_arith, new_width, new_bin_pt, new_arith - : INTEGER) - return std_logic_vector - is - -- Number of binary digits to add/subract to the right of the decimal - -- point - constant right_of_dp : integer := (old_bin_pt - new_bin_pt); - - constant expected_new_width : integer := old_width - right_of_dp + 1; - variable vec : std_logic_vector(old_width-1 downto 0); - variable one_or_zero : std_logic_vector(new_width-1 downto 0); - variable truncated_val : std_logic_vector(new_width-1 downto 0); - variable result : std_logic_vector(new_width-1 downto 0); - begin - vec := inp; - - if right_of_dp >= 0 then - -- Sign extend or zero extend to size of output - if new_arith = xlUnsigned then - truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), - new_width); - else - truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), - new_width); - end if; - - else - -- Pad LSB with zeros and sign extend by one bit - if new_arith = xlUnsigned then - truncated_val := zero_ext(pad_LSB(vec, old_width + - abs(right_of_dp)), new_width); - else - truncated_val := sign_ext(pad_LSB(vec, old_width + - abs(right_of_dp)), new_width); - end if; - end if; - - -- Figure out if '1' should be added to the truncated number - one_or_zero := (others => '0'); - - -- For the truncated bits just check if the bits after the - -- truncation point are 0.5 - if (right_of_dp >= 1) and (right_of_dp <= old_width) then - if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then - one_or_zero(0) := vec(right_of_dp-1); - else - one_or_zero(0) := vec(right_of_dp); - end if; - end if; - - if new_arith = xlSigned then - result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + - std_logic_vector_to_signed(one_or_zero)); - else - result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + - std_logic_vector_to_unsigned(one_or_zero)); - end if; - - return result; - end; - - --------------------------------------------------------------------------- - -- Overflow Functions - --------------------------------------------------------------------------- - - -- Apply Saturation arithmetic. The new_bin_pt and old bin_pt should be - -- equal. The function chops bits off MSB bits. - function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, - old_arith, new_width, new_bin_pt, new_arith - : INTEGER) - return std_logic_vector - is - -- Number of digits to add/subract to the left of the decimal point - constant left_of_dp : integer := (old_width - old_bin_pt) - - (new_width - new_bin_pt); - variable vec : std_logic_vector(old_width-1 downto 0); - variable result : std_logic_vector(new_width-1 downto 0); - variable overflow : boolean; - begin - vec := inp; - overflow := true; - result := (others => '0'); - - ----------------------------------------------------------------------- - -- Check for cases when overflow does not occur - ----------------------------------------------------------------------- - - -- Output width is >= input width - if (new_width >= old_width) then - overflow := false; - end if; - - -- Case #1: - -- Both the input and output are signed and the bits that will - -- be truncated plus the sign bit are all the same - -- (i.e., number has been sign extended) - if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then - if all_same(vec(old_width-1 downto new_width-1)) then - overflow := false; - end if; - end if; - - -- Case #2: - -- If the input is converted to a unsigned from an signed then only - -- check the bits that will be truncated are all zero - if (old_arith = xlSigned and new_arith = xlUnsigned) then - if (old_width > new_width) then - if all_zeros(vec(old_width-1 downto new_width)) then - overflow := false; - end if; - else - if (old_width = new_width) then - -- Check if input is positive - if (vec(new_width-1) = '0') then - overflow := false; - end if; - end if; - end if; - end if; - - -- Case #3: - -- Input is unsigned and the bits that will be truncated are all zero - if (old_arith = xlUnsigned and new_arith = xlUnsigned) then - if (old_width > new_width) then - if all_zeros(vec(old_width-1 downto new_width)) then - overflow := false; - end if; - else - if (old_width = new_width) then - overflow := false; - end if; - end if; - end if; - - -- Case #4: - -- Input is unsigned but output signed and the bits that will be - -- truncated are all zero - if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then - if all_same(vec(old_width-1 downto new_width-1)) then - overflow := false; - end if; - end if; - - - if overflow then - -- Overflow occured - if new_arith = xlSigned then - -- Check sign bit and set to max signed or min signed value - if vec(old_width-1) = '0' then - result := max_signed(new_width); - else - result := min_signed(new_width); - end if; - else - -- Check sign bit and set to zero if negative - if ((old_arith = xlSigned) and vec(old_width-1) = '1') then - result := (others => '0'); - else - -- Set to max unsigned positive value - result := (others => '1'); - end if; - end if; - else - -- Overflow did not occur - - -- Check for case when input type is signed and output type - -- unsigned - if (old_arith = xlSigned) and (new_arith = xlUnsigned) then - -- if negative number set vec to zero - if (vec(old_width-1) = '1') then - vec := (others => '0'); - end if; - end if; - - if new_width <= old_width then - result := vec(new_width-1 downto 0); - else - -- Sign or zero extend number depending on arith of new number - if new_arith = xlUnsigned then - result := zero_ext(vec, new_width); - else - result := sign_ext(vec, new_width); - end if; - - end if; - end if; - - return result; - end; - - function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, - old_arith, new_width, new_bin_pt, new_arith : INTEGER) - return std_logic_vector - is - variable result : std_logic_vector(new_width-1 downto 0); - variable result_arith : integer; - begin - -- Check for case when input type is signed and output type unsigned - if (old_arith = xlSigned) and (new_arith = xlUnsigned) then - result_arith := xlSigned; - end if; - - result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith); - - return result; - end; - - - -- Returns the number of fractional bits after alignment of fixed point num - function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is - begin - return max(a_bin_pt, b_bin_pt); - end; - - -- Returns the number of integer bits after alignment of fixed point num - function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) - return INTEGER is - begin - return max(a_width - a_bin_pt, b_width - b_bin_pt); - end; - - function pad_LSB(inp : std_logic_vector; new_width: integer) - return STD_LOGIC_VECTOR - is - constant orig_width : integer := inp'length; - variable vec : std_logic_vector(orig_width-1 downto 0); - variable result : std_logic_vector(new_width-1 downto 0); - variable pos : integer; - -- Added for XST - constant pad_pos : integer := new_width - orig_width - 1; - - begin - vec := inp; - pos := new_width-1; - if (new_width >= orig_width) then - for i in orig_width-1 downto 0 loop - result(pos) := vec(i); - pos := pos - 1; - end loop; - if pad_pos >= 0 then - for i in pad_pos downto 0 loop - result(i) := '0'; - end loop; - end if; - end if; - - return result; - end; - - - -- sign extend the MSB - function sign_ext(inp : std_logic_vector; new_width : INTEGER) - return std_logic_vector - is - constant old_width : integer := inp'length; - variable vec : std_logic_vector(old_width-1 downto 0); - variable result : std_logic_vector(new_width-1 downto 0); - begin - vec := inp; - -- sign extend - if new_width >= old_width then - result(old_width-1 downto 0) := vec; - if new_width-1 >= old_width then - for i in new_width-1 downto old_width loop - result(i) := vec(old_width-1); - end loop; - end if; - else - result(new_width-1 downto 0) := vec(new_width-1 downto 0); - end if; - - return result; - end; - - - - -- zero extend the MSB - function zero_ext(inp : std_logic_vector; new_width : INTEGER) - return std_logic_vector - is - constant old_width : integer := inp'length; - variable vec : std_logic_vector(old_width-1 downto 0); - variable result : std_logic_vector(new_width-1 downto 0); - begin - vec := inp; - - -- zero extend - if new_width >= old_width then - result(old_width-1 downto 0) := vec; - if new_width-1 >= old_width then - for i in new_width-1 downto old_width loop - result(i) := '0'; - end loop; - end if; - else - result(new_width-1 downto 0) := vec(new_width-1 downto 0); - end if; - - return result; - end; - - -- zero extend the MSB - function zero_ext(inp : std_logic; new_width : INTEGER) - return std_logic_vector - is - variable result : std_logic_vector(new_width-1 downto 0); - begin - result(0) := inp; - for i in new_width-1 downto 1 loop - result(i) := '0'; - end loop; - - return result; - end; - - -- zero or sign extend the MSB - function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) - return std_logic_vector - is - constant orig_width : integer := inp'length; - variable vec : std_logic_vector(orig_width-1 downto 0); - variable result : std_logic_vector(new_width-1 downto 0); - begin - vec := inp; - - if arith = xlUnsigned then - result := zero_ext(vec, new_width); - else - result := sign_ext(vec, new_width); - end if; - - return result; - end; - - -- Pad LSB with zeros and add a zero or sign extend the MSB - function pad_LSB(inp : std_logic_vector; new_width, arith: integer) - return STD_LOGIC_VECTOR - is - constant orig_width : integer := inp'length; - variable vec : std_logic_vector(orig_width-1 downto 0); - variable result : std_logic_vector(new_width-1 downto 0); - variable pos : integer; - begin - vec := inp; - pos := new_width-1; - - if (arith = xlUnsigned) then - -- set MSB to zero - result(pos) := '0'; - pos := pos - 1; - else - -- sign extend - result(pos) := vec(orig_width-1); - pos := pos - 1; - end if; - - if (new_width >= orig_width) then - for i in orig_width-1 downto 0 loop - result(pos) := vec(i); - pos := pos - 1; - end loop; - if pos >= 0 then - for i in pos downto 0 loop - result(i) := '0'; - end loop; - end if; - end if; - - return result; - end; - - -- Align input by padding LSB with zeros and sign or zero extening - function align_input(inp : std_logic_vector; old_width, delta, new_arith, - new_width: INTEGER) - return std_logic_vector - is - variable vec : std_logic_vector(old_width-1 downto 0); - variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0); - variable result : std_logic_vector(new_width-1 downto 0); - begin - vec := inp; - - if delta > 0 then - padded_inp := pad_LSB(vec, old_width+delta); - - -- sign or zero extend zero padded input depending on arith type - result := extend_MSB(padded_inp, new_width, new_arith); - else - -- sign or zero extend input depending on arith type - result := extend_MSB(vec, new_width, new_arith); - end if; - - return result; - end; - - function max(L, R: INTEGER) return INTEGER is - begin - if L > R then - return L; - else - return R; - end if; - end; - - function min(L, R: INTEGER) return INTEGER is - begin - if L < R then - return L; - else - return R; - end if; - end; - - -- Test is two strings are equal - function "="(left,right: STRING) return boolean is --- constant NULL_Str : string := ""; - begin - if (left'length /= right'length) then - return false; - else - -- Check for NULL string - -- FPGA Express does not like empty strings --- if (left'length = NULL_Str'length) or --- (right'length = NULL_Str'length) then --- return true; --- end if; - test : for i in 1 to left'length loop - if left(i) /= right(i) then - return false; - end if; - end loop test; - return true; - end if; - end; - - - --------------------------------------------------------------------------- - -- Debugging and Simulation only functions - --------------------------------------------------------------------------- - -- synthesis translate_off - - -- Check for all X's - function is_binary_string_invalid (inp : string) - return boolean - is - variable vec : string(1 to inp'length); - variable result : boolean; - begin - vec := inp; - result := false; - - for i in 1 to vec'length loop - if ( vec(i) = 'X' ) then - result := true; - end if; - end loop; - return result; - end; - - -- Check for all U's - function is_binary_string_undefined (inp : string) - return boolean - is - variable vec : string(1 to inp'length); - variable result : boolean; - begin - vec := inp; - result := false; - - for i in 1 to vec'length loop - if ( vec(i) = 'U' ) then - result := true; - end if; - end loop; - return result; - end; - - - - - -- Check for Undefined values - function is_XorU(inp : std_logic_vector) - return boolean - is - constant width : integer := inp'length; - variable vec : std_logic_vector(width-1 downto 0); - variable result : boolean; - begin - vec := inp; - result := false; - for i in 0 to width-1 loop - if (vec(i) = 'U') or (vec(i) = 'X') then - result := true; - end if; - end loop; - return result; - end; - - -- Converts a std_logic_vector to a real - function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) - return real - is - variable vec : std_logic_vector(inp'length-1 downto 0); - variable result, shift_val, undefined_real : real; - variable neg_num : boolean; - begin - vec := inp; - result := 0.0; - neg_num := false; - if vec(inp'length-1) = '1' then - neg_num := true; - end if; - - for i in 0 to inp'length-1 loop - if vec(i) = 'U' or vec(i) = 'X' then - return undefined_real; - end if; - if arith = xlSigned then - if neg_num then - -- Perform 1's count if negative number - if vec(i) = '0' then - result := result + 2.0**i; - end if; - else - if vec(i) = '1' then - result := result + 2.0**i; - end if; - end if; - else - -- Unsigned numbers - if vec(i) = '1' then - result := result + 2.0**i; - end if; - end if; - end loop; - - if arith = xlSigned then - if neg_num then - -- Add one to 1's comp number to make 2's comp number - result := result + 1.0; - result := result * (-1.0); - end if; - end if; - -- Realign based on binary point - shift_val := 2.0**(-1*bin_pt); - result := result * shift_val; - return result; - end; - - -- This function is just for consistancy - -- bin_pt and arith not used. - function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) - return real - is - variable result : real := 0.0; - begin - if inp = '1' then - result := 1.0; - end if; - - if arith = xlSigned then - assert false - report "It doesn't make sense to convert a 1 bit number to a signed real."; - end if; - return result; - end; - - -- synthesis translate_on - -- Convert an integer into a std_logic_vector - function integer_to_std_logic_vector (inp : integer; width, arith : integer) - return std_logic_vector - is - variable result : std_logic_vector(width-1 downto 0); - variable unsigned_val : unsigned(width-1 downto 0); - variable signed_val : signed(width-1 downto 0); - begin - - if (arith = xlSigned) then - signed_val := to_signed(inp, width); - result := signed_to_std_logic_vector(signed_val); - else - unsigned_val := to_unsigned(inp, width); - result := unsigned_to_std_logic_vector(unsigned_val); - end if; - - return result; - end; - - - -- Convert an std_logic or std_logic_vector to an integer - function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) - return integer - is - constant width : integer := inp'length; - variable unsigned_val : unsigned(width-1 downto 0); - variable signed_val : signed(width-1 downto 0); - variable result : integer; - begin - - if (arith = xlSigned) then - signed_val := std_logic_vector_to_signed(inp); - result := to_integer(signed_val); - else - unsigned_val := std_logic_vector_to_unsigned(inp); - result := to_integer(unsigned_val); - end if; - - return result; - end; - - function std_logic_to_integer(constant inp : std_logic := '0') - return integer - is - begin - if inp = '1' then - return 1; - else - return 0; - end if; - end; - - - function makeZeroBinStr (width : integer) return STRING is - variable result : string(1 to width+3); - begin - result(1) := '0'; - result(2) := 'b'; - for i in 3 to width+2 loop - result(i) := '0'; - end loop; -- i - result(width+3) := '.'; - - return result; - end; - - - - -- synthesis translate_off - -- Convert a real string into a std_logic_vector - function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) - return std_logic_vector - is - variable result : std_logic_vector(width-1 downto 0); - begin - --result := to_std_logic_vector(real'value(inp), width, bin_pt, arith); - result := (others => '0'); - return result; - end; - - -- Convert a real into a std_logic_vector - function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) - return std_logic_vector - is - variable real_val : real; - variable int_val : integer; - variable result : std_logic_vector(width-1 downto 0) := (others => '0'); - variable unsigned_val : unsigned(width-1 downto 0) := (others => '0'); - variable signed_val : signed(width-1 downto 0) := (others => '0'); - begin - - real_val := inp; - - -- Scale double and make it an integer - int_val := integer(real_val * 2.0**(bin_pt)); - - if (arith = xlSigned) then - signed_val := to_signed(int_val, width); - result := signed_to_std_logic_vector(signed_val); - else - unsigned_val := to_unsigned(int_val, width); - result := unsigned_to_std_logic_vector(unsigned_val); - end if; - - return result; - end; - - - -- synthesis translate_on - -- Check of 0b and the beginning of a string - function valid_bin_string (inp : string) - return boolean - is - variable vec : string(1 to inp'length); - begin - vec := inp; - if (vec(1) = '0' and vec(2) = 'b') then - return true; - else - return false; - end if; - end; - - -- convert a hex string to a std_logic_vector - function hex_string_to_std_logic_vector(inp: string; width : integer) - return std_logic_vector is - - constant strlen : integer := inp'LENGTH; - variable result : std_logic_vector(width-1 downto 0); - variable bitval : std_logic_vector((strlen*4)-1 downto 0); - variable posn : integer; - variable ch : character; - variable vec : string(1 to strlen); - begin - vec := inp; - - -- default value is zero - result := (others => '0'); - posn := (strlen*4)-1; - - for i in 1 to strlen loop - ch := vec(i); - case ch is - when '0' => bitval(posn downto posn-3) := "0000"; - when '1' => bitval(posn downto posn-3) := "0001"; - when '2' => bitval(posn downto posn-3) := "0010"; - when '3' => bitval(posn downto posn-3) := "0011"; - when '4' => bitval(posn downto posn-3) := "0100"; - when '5' => bitval(posn downto posn-3) := "0101"; - when '6' => bitval(posn downto posn-3) := "0110"; - when '7' => bitval(posn downto posn-3) := "0111"; - when '8' => bitval(posn downto posn-3) := "1000"; - when '9' => bitval(posn downto posn-3) := "1001"; - when 'A' | 'a' => bitval(posn downto posn-3) := "1010"; - when 'B' | 'b' => bitval(posn downto posn-3) := "1011"; - when 'C' | 'c' => bitval(posn downto posn-3) := "1100"; - when 'D' | 'd' => bitval(posn downto posn-3) := "1101"; - when 'E' | 'e' => bitval(posn downto posn-3) := "1110"; - when 'F' | 'f' => bitval(posn downto posn-3) := "1111"; - when others => bitval(posn downto posn-3) := "XXXX"; - -- synthesis translate_off - ASSERT false - REPORT "Invalid hex value" SEVERITY ERROR; - -- synthesis translate_on - end case; - posn := posn - 4; - end loop; - - if (width <= strlen*4) then - -- bitval larger than desired width - result := bitval(width-1 downto 0); - else - -- bitval smaller than desired width - -- MSB is padded with zeros since default value for result is all 0s - result((strlen*4)-1 downto 0) := bitval; - end if; - return result; - end; - - - -- convert a binary string into a std_logic_vector (e.g., 0b10.1 = 101) - function bin_string_to_std_logic_vector (inp : string) - return std_logic_vector - is - variable pos : integer; - variable vec : string(1 to inp'length); - variable result : std_logic_vector(inp'length-1 downto 0); - begin - vec := inp; - pos := inp'length-1; - -- Set default value - result := (others => '0'); - - for i in 1 to vec'length loop - -- synthesis translate_off - if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then - assert false - report "Input string is larger than output std_logic_vector. Truncating output."; - return result; - end if; - -- synthesis translate_on - - if vec(i) = '0' then - result(pos) := '0'; - pos := pos - 1; - end if; - if vec(i) = '1' then - result(pos) := '1'; - pos := pos - 1; - end if; - -- synthesis translate_off - if (vec(i) = 'X' or vec(i) = 'U') then - result(pos) := 'U'; - pos := pos - 1; - end if; - -- synthesis translate_on - end loop; - return result; - end; - - - -- Convert a binary string array element into a std_logic_vector - -- Example "0b000.0000000 0b001.0000000" - -- string_pos: 123456789111111111122222222 - -- 012345678901234567 - -- - -- "0b000.0000000" = inp(0) - -- "0b001.0000000" = inp(1) - function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) - return std_logic_vector - is - constant str_width : integer := width + 4; -- +4 for '0b' '.' & ' ' - constant inp_len : integer := inp'length; - constant num_elements : integer := (inp_len + 1)/str_width; - constant reverse_index : integer := (num_elements-1) - index; - - -- Calc position of desired str - variable left_pos : integer; - variable right_pos : integer; - variable vec : string(1 to inp'length); - variable result : std_logic_vector(width-1 downto 0); - begin - -- Can't pad input with a space (Synplicity crashes) - vec := inp; - - -- Set default value - result := (others => '0'); - - -- Special Case for string like "0b01.0" without extra ' ' after string - if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then - left_pos := 1; - right_pos := width + 3; - result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); - end if; - - if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then - left_pos := (reverse_index * str_width) + 1; - right_pos := left_pos + width + 2; - result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); - end if; - - return result; - end; - -- synthesis translate_off - - -- - -- convert a std_logic_vector to a string - -- - function std_logic_vector_to_bin_string(inp : std_logic_vector) - return string - is - variable vec : std_logic_vector(1 to inp'length); - variable result : string(vec'range); - begin - vec := inp; - for i in vec'range loop - result(i) := to_char(vec(i)); - end loop; - return result; - end; - - -- - -- convert a std_logic to a string - -- - function std_logic_to_bin_string(inp : std_logic) - return string - is - variable result : string(1 to 3); - begin - -- Add 0b prefix - result(1) := '0'; - result(2) := 'b'; - result(3) := to_char(inp); - return result; - end; - - -- - -- convert a std_logic_vector to a string and add a binary point - -- - function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) - return string - is - variable width : integer := inp'length; - variable vec : std_logic_vector(width-1 downto 0); - variable str_pos : integer; - variable result : string(1 to width+3); - begin - vec := inp; - -- Add 0b prefeix - str_pos := 1; - result(str_pos) := '0'; - str_pos := 2; - result(str_pos) := 'b'; - str_pos := 3; - for i in width-1 downto 0 loop - -- Insert decimal point - -- if i = (width - bin_pt + 1) then - if (((width+3) - bin_pt) = str_pos) then - result(str_pos) := '.'; - str_pos := str_pos + 1; - end if; - result(str_pos) := to_char(vec(i)); - str_pos := str_pos + 1; - end loop; - -- Add binary point at end of string when bin_pt = 0 - if (bin_pt = 0) then - result(str_pos) := '.'; - end if; - - return result; - end; - - -- Convert a real to a binary string - function real_to_bin_string(inp : real; width, bin_pt, arith : integer) - return string - is - variable result : string(1 to width); - variable vec : std_logic_vector(width-1 downto 0); - - begin - vec := real_to_std_logic_vector(inp, width, bin_pt, arith); - result := std_logic_vector_to_bin_string(vec); - - return result; - end; - - - -- Convert a real to string - -- Note: the size of the string returned is 'display_precision' chars long - function real_to_string (inp : real) return string - is - variable result : string(1 to display_precision) := (others => ' '); - begin - result(real'image(inp)'range) := real'image(inp); - return result; - end; - - -- synthesis translate_on - - -end conv_pkg; - - - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/single_reg_w_init.vhd b/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/single_reg_w_init.vhd deleted file mode 100644 index 26af1d6..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/single_reg_w_init.vhd +++ /dev/null @@ -1,109 +0,0 @@ -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - ----------------------------------------------------------------------------- --- --- Filename : single_reg_w_init.vhd --- --- Created : 6/28/2013 --- --- Description : splitted from synth_reg_w_init.vhd --- ----------------------------------------------------------------------------- - --- synthesis translate_off -library unisim; -use unisim.vcomponents.all; --- synthesis translate_on - -library IEEE; -use IEEE.std_logic_1164.all; - -entity single_reg_w_init is - generic ( - width: integer := 8; - init_index: integer := 0; - init_value: bit_vector := b"0000" - ); - port ( - i: in std_logic_vector(width - 1 downto 0); - ce: in std_logic; - clr: in std_logic; - clk: in std_logic; - o: out std_logic_vector(width - 1 downto 0) - ); -end single_reg_w_init; - -architecture structural of single_reg_w_init is - function build_init_const(width: integer; - init_index: integer; - init_value: bit_vector) - return std_logic_vector - is - variable result: std_logic_vector(width - 1 downto 0); - begin - if init_index = 0 then - result := (others => '0'); - elsif init_index = 1 then - result := (others => '0'); - result(0) := '1'; - else - result := to_stdlogicvector(init_value); - end if; - return result; - end; - - component fdre - port ( - q: out std_ulogic; - d: in std_ulogic; - c: in std_ulogic; - ce: in std_ulogic; - r: in std_ulogic - ); - end component; -- end fdre - attribute syn_black_box of fdre: component is true; - attribute fpga_dont_touch of fdre: component is "true"; - - component fdse - port ( - q: out std_ulogic; - d: in std_ulogic; - c: in std_ulogic; - ce: in std_ulogic; - s: in std_ulogic - ); - end component; -- end fdse - attribute syn_black_box of fdse: component is true; - attribute fpga_dont_touch of fdse: component is "true"; - - constant init_const: std_logic_vector(width - 1 downto 0) - := build_init_const(width, init_index, init_value); -begin - fd_prim_array: for index in 0 to width - 1 generate - - bit_is_0: if (init_const(index) = '0') generate - fdre_comp: fdre - port map ( - c => clk, - d => i(index), - q => o(index), - ce => ce, - r => clr - ); - end generate; -- end bit_is_0 - - bit_is_1: if (init_const(index) = '1') generate - fdse_comp: fdse - port map ( - c => clk, - d => i(index), - q => o(index), - ce => ce, - s => clr - ); - end generate; -- end bit_is_1 - end generate; -- end fd_prim_array -end architecture structural; - - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/srl17e.vhd b/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/srl17e.vhd deleted file mode 100644 index 8ec9c8d..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/srl17e.vhd +++ /dev/null @@ -1,93 +0,0 @@ -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - ----------------------------------------------------------------------------- --- --- Filename : srl17e.vhd --- --- Created : 6/28/2013 --- --- Description : splitted from synth_reg.vhd --- ----------------------------------------------------------------------------- - --- synthesis translate_off -library unisim; -use unisim.vcomponents.all; --- synthesis translate_on - -library IEEE; -use IEEE.std_logic_1164.all; - -entity srl17e is - generic (width : integer:=16; - latency : integer :=8); -- Max 17 - port (clk : in std_logic; - ce : in std_logic; - d : in std_logic_vector(width-1 downto 0); - q : out std_logic_vector(width-1 downto 0)); -end srl17e; - -architecture structural of srl17e is - - component SRL16E - port (D : in STD_ULOGIC; - CE : in STD_ULOGIC; - CLK : in STD_ULOGIC; - A0 : in STD_ULOGIC; - A1 : in STD_ULOGIC; - A2 : in STD_ULOGIC; - A3 : in STD_ULOGIC; - Q : out STD_ULOGIC); - end component; - attribute syn_black_box of SRL16E : component is true; - attribute fpga_dont_touch of SRL16E : component is "true"; - - component FDE - port( - Q : out STD_ULOGIC; - D : in STD_ULOGIC; - C : in STD_ULOGIC; - CE : in STD_ULOGIC); - end component; - attribute syn_black_box of FDE : component is true; - attribute fpga_dont_touch of FDE : component is "true"; - - - constant a : std_logic_vector(4 downto 0) := - integer_to_std_logic_vector(latency-2,5,xlSigned); - signal d_delayed : std_logic_vector(width-1 downto 0); - signal srl16_out : std_logic_vector(width-1 downto 0); - -begin - d_delayed <= d after 200 ps; - - reg_array : for i in 0 to width-1 generate - srl16_used: if latency > 1 generate - u1 : srl16e port map(clk => clk, - d => d_delayed(i), - q => srl16_out(i), - ce => ce, - a0 => a(0), - a1 => a(1), - a2 => a(2), - a3 => a(3)); - end generate; - srl16_not_used: if latency <= 1 generate - srl16_out(i) <= d_delayed(i); - end generate; - - fde_used: if latency /= 0 generate - u2 : fde port map(c => clk, - d => srl16_out(i), - q => q(i), - ce => ce); - end generate; - fde_not_used: if latency = 0 generate - q(i) <= srl16_out(i); - end generate; - - end generate; - end structural; - - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/srl33e.vhd b/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/srl33e.vhd deleted file mode 100644 index c943462..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/srl33e.vhd +++ /dev/null @@ -1,87 +0,0 @@ -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - ----------------------------------------------------------------------------- --- --- Filename : srlc17e.vhd --- --- Created : 6/28/2013 --- --- Description : splitted from synth_reg.vhd --- ----------------------------------------------------------------------------- - --- synthesis translate_off -library unisim; -use unisim.vcomponents.all; --- synthesis translate_on - -library IEEE; -use IEEE.std_logic_1164.all; - -entity srlc33e is - generic (width : integer:=16; - latency : integer :=8); -- Max 17 - port (clk : in std_logic; - ce : in std_logic; - d : in std_logic_vector(width-1 downto 0); - q : out std_logic_vector(width-1 downto 0)); -end srlc33e; - -architecture structural of srlc33e is - - component SRLC32E - port (D : in STD_ULOGIC; - CE : in STD_ULOGIC; - CLK : in STD_ULOGIC; - A : in std_logic_vector(4 downto 0); - Q : out STD_ULOGIC); - end component; - attribute syn_black_box of SRLC32E : component is true; - attribute fpga_dont_touch of SRLC32E : component is "true"; - - component FDE - port( - Q : out STD_ULOGIC; - D : in STD_ULOGIC; - C : in STD_ULOGIC; - CE : in STD_ULOGIC); - end component; - attribute syn_black_box of FDE : component is true; - attribute fpga_dont_touch of FDE : component is "true"; - - - constant a : std_logic_vector(4 downto 0) := - integer_to_std_logic_vector(latency-2,5,xlSigned); - signal d_delayed : std_logic_vector(width-1 downto 0); - signal srlc32_out : std_logic_vector(width-1 downto 0); - -begin - d_delayed <= d after 200 ps; - - reg_array : for i in 0 to width-1 generate - srlc32_used: if latency > 1 generate - u1 : srlc32e port map(clk => clk, - d => d_delayed(i), - q => srlc32_out(i), - ce => ce, - a => a); - end generate; - srlc32_not_used: if latency <= 1 generate - srlc32_out(i) <= d_delayed(i); - end generate; - - fde_used: if latency /= 0 generate - u2 : fde port map(c => clk, - d => srlc32_out(i), - q => q(i), - ce => ce); - end generate; - fde_not_used: if latency = 0 generate - q(i) <= srlc32_out(i); - end generate; - - end generate; - end structural; - - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/ssr_8x8.vhd b/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/ssr_8x8.vhd deleted file mode 100644 index 47cdad1..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/ssr_8x8.vhd +++ /dev/null @@ -1,2133 +0,0 @@ --- Generated from Simulink block ssr_8x8/Vector FFT/Scalar2Vector -library IEEE; -use IEEE.std_logic_1164.all; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; -entity ssr_8x8_scalar2vector is - port ( - i : in std_logic_vector( 432-1 downto 0 ); - o_1 : out std_logic_vector( 54-1 downto 0 ); - o_2 : out std_logic_vector( 54-1 downto 0 ); - o_3 : out std_logic_vector( 54-1 downto 0 ); - o_4 : out std_logic_vector( 54-1 downto 0 ); - o_5 : out std_logic_vector( 54-1 downto 0 ); - o_6 : out std_logic_vector( 54-1 downto 0 ); - o_7 : out std_logic_vector( 54-1 downto 0 ); - o_8 : out std_logic_vector( 54-1 downto 0 ) - ); -end ssr_8x8_scalar2vector; -architecture structural of ssr_8x8_scalar2vector is - signal slice1_y_net : std_logic_vector( 54-1 downto 0 ); - signal slice0_y_net : std_logic_vector( 54-1 downto 0 ); - signal slice2_y_net : std_logic_vector( 54-1 downto 0 ); - signal slice3_y_net : std_logic_vector( 54-1 downto 0 ); - signal slice4_y_net : std_logic_vector( 54-1 downto 0 ); - signal slice5_y_net : std_logic_vector( 54-1 downto 0 ); - signal slice6_y_net : std_logic_vector( 54-1 downto 0 ); - signal slice7_y_net : std_logic_vector( 54-1 downto 0 ); - signal test_systolicfft_vhdl_black_box_o_net : std_logic_vector( 432-1 downto 0 ); -begin - o_1 <= slice0_y_net; - o_2 <= slice1_y_net; - o_3 <= slice2_y_net; - o_4 <= slice3_y_net; - o_5 <= slice4_y_net; - o_6 <= slice5_y_net; - o_7 <= slice6_y_net; - o_8 <= slice7_y_net; - test_systolicfft_vhdl_black_box_o_net <= i; - slice0 : entity xil_defaultlib.ssr_8x8_xlslice - generic map ( - new_lsb => 0, - new_msb => 53, - x_width => 432, - y_width => 54 - ) - port map ( - x => test_systolicfft_vhdl_black_box_o_net, - y => slice0_y_net - ); - slice1 : entity xil_defaultlib.ssr_8x8_xlslice - generic map ( - new_lsb => 54, - new_msb => 107, - x_width => 432, - y_width => 54 - ) - port map ( - x => test_systolicfft_vhdl_black_box_o_net, - y => slice1_y_net - ); - slice2 : entity xil_defaultlib.ssr_8x8_xlslice - generic map ( - new_lsb => 108, - new_msb => 161, - x_width => 432, - y_width => 54 - ) - port map ( - x => test_systolicfft_vhdl_black_box_o_net, - y => slice2_y_net - ); - slice3 : entity xil_defaultlib.ssr_8x8_xlslice - generic map ( - new_lsb => 162, - new_msb => 215, - x_width => 432, - y_width => 54 - ) - port map ( - x => test_systolicfft_vhdl_black_box_o_net, - y => slice3_y_net - ); - slice4 : entity xil_defaultlib.ssr_8x8_xlslice - generic map ( - new_lsb => 216, - new_msb => 269, - x_width => 432, - y_width => 54 - ) - port map ( - x => test_systolicfft_vhdl_black_box_o_net, - y => slice4_y_net - ); - slice5 : entity xil_defaultlib.ssr_8x8_xlslice - generic map ( - new_lsb => 270, - new_msb => 323, - x_width => 432, - y_width => 54 - ) - port map ( - x => test_systolicfft_vhdl_black_box_o_net, - y => slice5_y_net - ); - slice6 : entity xil_defaultlib.ssr_8x8_xlslice - generic map ( - new_lsb => 324, - new_msb => 377, - x_width => 432, - y_width => 54 - ) - port map ( - x => test_systolicfft_vhdl_black_box_o_net, - y => slice6_y_net - ); - slice7 : entity xil_defaultlib.ssr_8x8_xlslice - generic map ( - new_lsb => 378, - new_msb => 431, - x_width => 432, - y_width => 54 - ) - port map ( - x => test_systolicfft_vhdl_black_box_o_net, - y => slice7_y_net - ); -end structural; --- Generated from Simulink block ssr_8x8/Vector FFT/Vector Concat -library IEEE; -use IEEE.std_logic_1164.all; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; -entity ssr_8x8_vector_concat is - port ( - hi_1 : in std_logic_vector( 16-1 downto 0 ); - lo_1 : in std_logic_vector( 16-1 downto 0 ); - hi_2 : in std_logic_vector( 16-1 downto 0 ); - hi_3 : in std_logic_vector( 16-1 downto 0 ); - hi_4 : in std_logic_vector( 16-1 downto 0 ); - hi_5 : in std_logic_vector( 16-1 downto 0 ); - hi_6 : in std_logic_vector( 16-1 downto 0 ); - hi_7 : in std_logic_vector( 16-1 downto 0 ); - hi_8 : in std_logic_vector( 16-1 downto 0 ); - lo_2 : in std_logic_vector( 16-1 downto 0 ); - lo_3 : in std_logic_vector( 16-1 downto 0 ); - lo_4 : in std_logic_vector( 16-1 downto 0 ); - lo_5 : in std_logic_vector( 16-1 downto 0 ); - lo_6 : in std_logic_vector( 16-1 downto 0 ); - lo_7 : in std_logic_vector( 16-1 downto 0 ); - lo_8 : in std_logic_vector( 16-1 downto 0 ); - out_1 : out std_logic_vector( 32-1 downto 0 ); - out_2 : out std_logic_vector( 32-1 downto 0 ); - out_3 : out std_logic_vector( 32-1 downto 0 ); - out_4 : out std_logic_vector( 32-1 downto 0 ); - out_5 : out std_logic_vector( 32-1 downto 0 ); - out_6 : out std_logic_vector( 32-1 downto 0 ); - out_7 : out std_logic_vector( 32-1 downto 0 ); - out_8 : out std_logic_vector( 32-1 downto 0 ) - ); -end ssr_8x8_vector_concat; -architecture structural of ssr_8x8_vector_concat is - signal reinterpret6_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); - signal reinterpret4_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); - signal concat2_y_net : std_logic_vector( 32-1 downto 0 ); - signal reinterpret0_output_port_net : std_logic_vector( 16-1 downto 0 ); - signal reinterpret2_output_port_net : std_logic_vector( 16-1 downto 0 ); - signal reinterpret3_output_port_net : std_logic_vector( 16-1 downto 0 ); - signal concat1_y_net : std_logic_vector( 32-1 downto 0 ); - signal concat4_y_net : std_logic_vector( 32-1 downto 0 ); - signal concat5_y_net : std_logic_vector( 32-1 downto 0 ); - signal reinterpret0_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); - signal reinterpret1_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); - signal reinterpret3_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); - signal reinterpret7_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); - signal reinterpret1_output_port_net : std_logic_vector( 16-1 downto 0 ); - signal reinterpret4_output_port_net : std_logic_vector( 16-1 downto 0 ); - signal concat3_y_net : std_logic_vector( 32-1 downto 0 ); - signal concat0_y_net : std_logic_vector( 32-1 downto 0 ); - signal concat7_y_net : std_logic_vector( 32-1 downto 0 ); - signal reinterpret2_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); - signal concat6_y_net : std_logic_vector( 32-1 downto 0 ); - signal reinterpret5_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); - signal reinterpret6_output_port_net : std_logic_vector( 16-1 downto 0 ); - signal reinterpret5_output_port_net : std_logic_vector( 16-1 downto 0 ); - signal reinterpret7_output_port_net : std_logic_vector( 16-1 downto 0 ); -begin - out_1 <= concat0_y_net; - out_2 <= concat1_y_net; - out_3 <= concat2_y_net; - out_4 <= concat3_y_net; - out_5 <= concat4_y_net; - out_6 <= concat5_y_net; - out_7 <= concat6_y_net; - out_8 <= concat7_y_net; - reinterpret0_output_port_net_x0 <= hi_1; - reinterpret0_output_port_net <= lo_1; - reinterpret1_output_port_net_x0 <= hi_2; - reinterpret2_output_port_net_x0 <= hi_3; - reinterpret3_output_port_net_x0 <= hi_4; - reinterpret4_output_port_net_x0 <= hi_5; - reinterpret5_output_port_net_x0 <= hi_6; - reinterpret6_output_port_net_x0 <= hi_7; - reinterpret7_output_port_net_x0 <= hi_8; - reinterpret1_output_port_net <= lo_2; - reinterpret2_output_port_net <= lo_3; - reinterpret3_output_port_net <= lo_4; - reinterpret4_output_port_net <= lo_5; - reinterpret5_output_port_net <= lo_6; - reinterpret6_output_port_net <= lo_7; - reinterpret7_output_port_net <= lo_8; - concat0 : entity xil_defaultlib.sysgen_concat_965a32611a - port map ( - clk => '0', - ce => '0', - clr => '0', - in0 => reinterpret0_output_port_net_x0, - in1 => reinterpret0_output_port_net, - y => concat0_y_net - ); - concat1 : entity xil_defaultlib.sysgen_concat_965a32611a - port map ( - clk => '0', - ce => '0', - clr => '0', - in0 => reinterpret1_output_port_net_x0, - in1 => reinterpret1_output_port_net, - y => concat1_y_net - ); - concat2 : entity xil_defaultlib.sysgen_concat_965a32611a - port map ( - clk => '0', - ce => '0', - clr => '0', - in0 => reinterpret2_output_port_net_x0, - in1 => reinterpret2_output_port_net, - y => concat2_y_net - ); - concat3 : entity xil_defaultlib.sysgen_concat_965a32611a - port map ( - clk => '0', - ce => '0', - clr => '0', - in0 => reinterpret3_output_port_net_x0, - in1 => reinterpret3_output_port_net, - y => concat3_y_net - ); - concat4 : entity xil_defaultlib.sysgen_concat_965a32611a - port map ( - clk => '0', - ce => '0', - clr => '0', - in0 => reinterpret4_output_port_net_x0, - in1 => reinterpret4_output_port_net, - y => concat4_y_net - ); - concat5 : entity xil_defaultlib.sysgen_concat_965a32611a - port map ( - clk => '0', - ce => '0', - clr => '0', - in0 => reinterpret5_output_port_net_x0, - in1 => reinterpret5_output_port_net, - y => concat5_y_net - ); - concat6 : entity xil_defaultlib.sysgen_concat_965a32611a - port map ( - clk => '0', - ce => '0', - clr => '0', - in0 => reinterpret6_output_port_net_x0, - in1 => reinterpret6_output_port_net, - y => concat6_y_net - ); - concat7 : entity xil_defaultlib.sysgen_concat_965a32611a - port map ( - clk => '0', - ce => '0', - clr => '0', - in0 => reinterpret7_output_port_net_x0, - in1 => reinterpret7_output_port_net, - y => concat7_y_net - ); -end structural; --- Generated from Simulink block ssr_8x8/Vector FFT/Vector Delay -library IEEE; -use IEEE.std_logic_1164.all; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; -entity ssr_8x8_vector_delay is - port ( - d_1 : in std_logic_vector( 32-1 downto 0 ); - d_2 : in std_logic_vector( 32-1 downto 0 ); - d_3 : in std_logic_vector( 32-1 downto 0 ); - d_4 : in std_logic_vector( 32-1 downto 0 ); - d_5 : in std_logic_vector( 32-1 downto 0 ); - d_6 : in std_logic_vector( 32-1 downto 0 ); - d_7 : in std_logic_vector( 32-1 downto 0 ); - d_8 : in std_logic_vector( 32-1 downto 0 ); - clk_1 : in std_logic; - ce_1 : in std_logic; - q_1 : out std_logic_vector( 32-1 downto 0 ); - q_2 : out std_logic_vector( 32-1 downto 0 ); - q_3 : out std_logic_vector( 32-1 downto 0 ); - q_4 : out std_logic_vector( 32-1 downto 0 ); - q_5 : out std_logic_vector( 32-1 downto 0 ); - q_6 : out std_logic_vector( 32-1 downto 0 ); - q_7 : out std_logic_vector( 32-1 downto 0 ); - q_8 : out std_logic_vector( 32-1 downto 0 ) - ); -end ssr_8x8_vector_delay; -architecture structural of ssr_8x8_vector_delay is - signal delay3_q_net : std_logic_vector( 32-1 downto 0 ); - signal delay4_q_net : std_logic_vector( 32-1 downto 0 ); - signal delay2_q_net : std_logic_vector( 32-1 downto 0 ); - signal delay1_q_net : std_logic_vector( 32-1 downto 0 ); - signal delay0_q_net : std_logic_vector( 32-1 downto 0 ); - signal delay6_q_net : std_logic_vector( 32-1 downto 0 ); - signal concat0_y_net : std_logic_vector( 32-1 downto 0 ); - signal concat1_y_net : std_logic_vector( 32-1 downto 0 ); - signal concat4_y_net : std_logic_vector( 32-1 downto 0 ); - signal concat5_y_net : std_logic_vector( 32-1 downto 0 ); - signal ce_net : std_logic; - signal concat3_y_net : std_logic_vector( 32-1 downto 0 ); - signal delay5_q_net : std_logic_vector( 32-1 downto 0 ); - signal delay7_q_net : std_logic_vector( 32-1 downto 0 ); - signal concat2_y_net : std_logic_vector( 32-1 downto 0 ); - signal clk_net : std_logic; - signal concat6_y_net : std_logic_vector( 32-1 downto 0 ); - signal concat7_y_net : std_logic_vector( 32-1 downto 0 ); -begin - q_1 <= delay0_q_net; - q_2 <= delay1_q_net; - q_3 <= delay2_q_net; - q_4 <= delay3_q_net; - q_5 <= delay4_q_net; - q_6 <= delay5_q_net; - q_7 <= delay6_q_net; - q_8 <= delay7_q_net; - concat0_y_net <= d_1; - concat1_y_net <= d_2; - concat2_y_net <= d_3; - concat3_y_net <= d_4; - concat4_y_net <= d_5; - concat5_y_net <= d_6; - concat6_y_net <= d_7; - concat7_y_net <= d_8; - clk_net <= clk_1; - ce_net <= ce_1; - delay0 : entity xil_defaultlib.ssr_8x8_xldelay - generic map ( - latency => 4, - reg_retiming => 0, - reset => 0, - width => 32 - ) - port map ( - en => '1', - rst => '0', - d => concat0_y_net, - clk => clk_net, - ce => ce_net, - q => delay0_q_net - ); - delay1 : entity xil_defaultlib.ssr_8x8_xldelay - generic map ( - latency => 4, - reg_retiming => 0, - reset => 0, - width => 32 - ) - port map ( - en => '1', - rst => '0', - d => concat1_y_net, - clk => clk_net, - ce => ce_net, - q => delay1_q_net - ); - delay2 : entity xil_defaultlib.ssr_8x8_xldelay - generic map ( - latency => 4, - reg_retiming => 0, - reset => 0, - width => 32 - ) - port map ( - en => '1', - rst => '0', - d => concat2_y_net, - clk => clk_net, - ce => ce_net, - q => delay2_q_net - ); - delay3 : entity xil_defaultlib.ssr_8x8_xldelay - generic map ( - latency => 4, - reg_retiming => 0, - reset => 0, - width => 32 - ) - port map ( - en => '1', - rst => '0', - d => concat3_y_net, - clk => clk_net, - ce => ce_net, - q => delay3_q_net - ); - delay4 : entity xil_defaultlib.ssr_8x8_xldelay - generic map ( - latency => 4, - reg_retiming => 0, - reset => 0, - width => 32 - ) - port map ( - en => '1', - rst => '0', - d => concat4_y_net, - clk => clk_net, - ce => ce_net, - q => delay4_q_net - ); - delay5 : entity xil_defaultlib.ssr_8x8_xldelay - generic map ( - latency => 4, - reg_retiming => 0, - reset => 0, - width => 32 - ) - port map ( - en => '1', - rst => '0', - d => concat5_y_net, - clk => clk_net, - ce => ce_net, - q => delay5_q_net - ); - delay6 : entity xil_defaultlib.ssr_8x8_xldelay - generic map ( - latency => 4, - reg_retiming => 0, - reset => 0, - width => 32 - ) - port map ( - en => '1', - rst => '0', - d => concat6_y_net, - clk => clk_net, - ce => ce_net, - q => delay6_q_net - ); - delay7 : entity xil_defaultlib.ssr_8x8_xldelay - generic map ( - latency => 4, - reg_retiming => 0, - reset => 0, - width => 32 - ) - port map ( - en => '1', - rst => '0', - d => concat7_y_net, - clk => clk_net, - ce => ce_net, - q => delay7_q_net - ); -end structural; --- Generated from Simulink block ssr_8x8/Vector FFT/Vector Reinterpret -library IEEE; -use IEEE.std_logic_1164.all; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; -entity ssr_8x8_vector_reinterpret is - port ( - in_1 : in std_logic_vector( 16-1 downto 0 ); - in_2 : in std_logic_vector( 16-1 downto 0 ); - in_3 : in std_logic_vector( 16-1 downto 0 ); - in_4 : in std_logic_vector( 16-1 downto 0 ); - in_5 : in std_logic_vector( 16-1 downto 0 ); - in_6 : in std_logic_vector( 16-1 downto 0 ); - in_7 : in std_logic_vector( 16-1 downto 0 ); - in_8 : in std_logic_vector( 16-1 downto 0 ); - out_1 : out std_logic_vector( 16-1 downto 0 ); - out_2 : out std_logic_vector( 16-1 downto 0 ); - out_3 : out std_logic_vector( 16-1 downto 0 ); - out_4 : out std_logic_vector( 16-1 downto 0 ); - out_5 : out std_logic_vector( 16-1 downto 0 ); - out_6 : out std_logic_vector( 16-1 downto 0 ); - out_7 : out std_logic_vector( 16-1 downto 0 ); - out_8 : out std_logic_vector( 16-1 downto 0 ) - ); -end ssr_8x8_vector_reinterpret; -architecture structural of ssr_8x8_vector_reinterpret is - signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); - signal reinterpret6_output_port_net : std_logic_vector( 16-1 downto 0 ); - signal reinterpret7_output_port_net : std_logic_vector( 16-1 downto 0 ); - signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); - signal reinterpret4_output_port_net : std_logic_vector( 16-1 downto 0 ); - signal reinterpret5_output_port_net : std_logic_vector( 16-1 downto 0 ); - signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); - signal reinterpret1_output_port_net : std_logic_vector( 16-1 downto 0 ); - signal reinterpret2_output_port_net : std_logic_vector( 16-1 downto 0 ); - signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); - signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); - signal reinterpret0_output_port_net : std_logic_vector( 16-1 downto 0 ); - signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); - signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); - signal reinterpret3_output_port_net : std_logic_vector( 16-1 downto 0 ); - signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); -begin - out_1 <= reinterpret0_output_port_net; - out_2 <= reinterpret1_output_port_net; - out_3 <= reinterpret2_output_port_net; - out_4 <= reinterpret3_output_port_net; - out_5 <= reinterpret4_output_port_net; - out_6 <= reinterpret5_output_port_net; - out_7 <= reinterpret6_output_port_net; - out_8 <= reinterpret7_output_port_net; - i_re_0_net <= in_1; - i_re_1_net <= in_2; - i_re_2_net <= in_3; - i_re_3_net <= in_4; - i_re_4_net <= in_5; - i_re_5_net <= in_6; - i_re_6_net <= in_7; - i_re_7_net <= in_8; - reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 - port map ( - clk => '0', - ce => '0', - clr => '0', - input_port => i_re_0_net, - output_port => reinterpret0_output_port_net - ); - reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 - port map ( - clk => '0', - ce => '0', - clr => '0', - input_port => i_re_1_net, - output_port => reinterpret1_output_port_net - ); - reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 - port map ( - clk => '0', - ce => '0', - clr => '0', - input_port => i_re_2_net, - output_port => reinterpret2_output_port_net - ); - reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 - port map ( - clk => '0', - ce => '0', - clr => '0', - input_port => i_re_3_net, - output_port => reinterpret3_output_port_net - ); - reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 - port map ( - clk => '0', - ce => '0', - clr => '0', - input_port => i_re_4_net, - output_port => reinterpret4_output_port_net - ); - reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 - port map ( - clk => '0', - ce => '0', - clr => '0', - input_port => i_re_5_net, - output_port => reinterpret5_output_port_net - ); - reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 - port map ( - clk => '0', - ce => '0', - clr => '0', - input_port => i_re_6_net, - output_port => reinterpret6_output_port_net - ); - reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 - port map ( - clk => '0', - ce => '0', - clr => '0', - input_port => i_re_7_net, - output_port => reinterpret7_output_port_net - ); -end structural; --- Generated from Simulink block ssr_8x8/Vector FFT/Vector Reinterpret1 -library IEEE; -use IEEE.std_logic_1164.all; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; -entity ssr_8x8_vector_reinterpret1 is - port ( - in_1 : in std_logic_vector( 16-1 downto 0 ); - in_2 : in std_logic_vector( 16-1 downto 0 ); - in_3 : in std_logic_vector( 16-1 downto 0 ); - in_4 : in std_logic_vector( 16-1 downto 0 ); - in_5 : in std_logic_vector( 16-1 downto 0 ); - in_6 : in std_logic_vector( 16-1 downto 0 ); - in_7 : in std_logic_vector( 16-1 downto 0 ); - in_8 : in std_logic_vector( 16-1 downto 0 ); - out_1 : out std_logic_vector( 16-1 downto 0 ); - out_2 : out std_logic_vector( 16-1 downto 0 ); - out_3 : out std_logic_vector( 16-1 downto 0 ); - out_4 : out std_logic_vector( 16-1 downto 0 ); - out_5 : out std_logic_vector( 16-1 downto 0 ); - out_6 : out std_logic_vector( 16-1 downto 0 ); - out_7 : out std_logic_vector( 16-1 downto 0 ); - out_8 : out std_logic_vector( 16-1 downto 0 ) - ); -end ssr_8x8_vector_reinterpret1; -architecture structural of ssr_8x8_vector_reinterpret1 is - signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); - signal reinterpret7_output_port_net : std_logic_vector( 16-1 downto 0 ); - signal reinterpret5_output_port_net : std_logic_vector( 16-1 downto 0 ); - signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); - signal reinterpret2_output_port_net : std_logic_vector( 16-1 downto 0 ); - signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); - signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); - signal reinterpret1_output_port_net : std_logic_vector( 16-1 downto 0 ); - signal reinterpret6_output_port_net : std_logic_vector( 16-1 downto 0 ); - signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); - signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); - signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); - signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); - signal reinterpret0_output_port_net : std_logic_vector( 16-1 downto 0 ); - signal reinterpret3_output_port_net : std_logic_vector( 16-1 downto 0 ); - signal reinterpret4_output_port_net : std_logic_vector( 16-1 downto 0 ); -begin - out_1 <= reinterpret0_output_port_net; - out_2 <= reinterpret1_output_port_net; - out_3 <= reinterpret2_output_port_net; - out_4 <= reinterpret3_output_port_net; - out_5 <= reinterpret4_output_port_net; - out_6 <= reinterpret5_output_port_net; - out_7 <= reinterpret6_output_port_net; - out_8 <= reinterpret7_output_port_net; - i_im_0_net <= in_1; - i_im_1_net <= in_2; - i_im_2_net <= in_3; - i_im_3_net <= in_4; - i_im_4_net <= in_5; - i_im_5_net <= in_6; - i_im_6_net <= in_7; - i_im_7_net <= in_8; - reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 - port map ( - clk => '0', - ce => '0', - clr => '0', - input_port => i_im_0_net, - output_port => reinterpret0_output_port_net - ); - reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 - port map ( - clk => '0', - ce => '0', - clr => '0', - input_port => i_im_1_net, - output_port => reinterpret1_output_port_net - ); - reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 - port map ( - clk => '0', - ce => '0', - clr => '0', - input_port => i_im_2_net, - output_port => reinterpret2_output_port_net - ); - reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 - port map ( - clk => '0', - ce => '0', - clr => '0', - input_port => i_im_3_net, - output_port => reinterpret3_output_port_net - ); - reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 - port map ( - clk => '0', - ce => '0', - clr => '0', - input_port => i_im_4_net, - output_port => reinterpret4_output_port_net - ); - reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 - port map ( - clk => '0', - ce => '0', - clr => '0', - input_port => i_im_5_net, - output_port => reinterpret5_output_port_net - ); - reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 - port map ( - clk => '0', - ce => '0', - clr => '0', - input_port => i_im_6_net, - output_port => reinterpret6_output_port_net - ); - reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 - port map ( - clk => '0', - ce => '0', - clr => '0', - input_port => i_im_7_net, - output_port => reinterpret7_output_port_net - ); -end structural; --- Generated from Simulink block ssr_8x8/Vector FFT/Vector Reinterpret2 -library IEEE; -use IEEE.std_logic_1164.all; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; -entity ssr_8x8_vector_reinterpret2 is - port ( - in_1 : in std_logic_vector( 27-1 downto 0 ); - in_2 : in std_logic_vector( 27-1 downto 0 ); - in_3 : in std_logic_vector( 27-1 downto 0 ); - in_4 : in std_logic_vector( 27-1 downto 0 ); - in_5 : in std_logic_vector( 27-1 downto 0 ); - in_6 : in std_logic_vector( 27-1 downto 0 ); - in_7 : in std_logic_vector( 27-1 downto 0 ); - in_8 : in std_logic_vector( 27-1 downto 0 ); - out_1 : out std_logic_vector( 27-1 downto 0 ); - out_2 : out std_logic_vector( 27-1 downto 0 ); - out_3 : out std_logic_vector( 27-1 downto 0 ); - out_4 : out std_logic_vector( 27-1 downto 0 ); - out_5 : out std_logic_vector( 27-1 downto 0 ); - out_6 : out std_logic_vector( 27-1 downto 0 ); - out_7 : out std_logic_vector( 27-1 downto 0 ); - out_8 : out std_logic_vector( 27-1 downto 0 ) - ); -end ssr_8x8_vector_reinterpret2; -architecture structural of ssr_8x8_vector_reinterpret2 is - signal slice2_y_net : std_logic_vector( 27-1 downto 0 ); - signal slice7_y_net : std_logic_vector( 27-1 downto 0 ); - signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); - signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); - signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); - signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); - signal slice0_y_net : std_logic_vector( 27-1 downto 0 ); - signal slice5_y_net : std_logic_vector( 27-1 downto 0 ); - signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); - signal slice3_y_net : std_logic_vector( 27-1 downto 0 ); - signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); - signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); - signal slice1_y_net : std_logic_vector( 27-1 downto 0 ); - signal slice4_y_net : std_logic_vector( 27-1 downto 0 ); - signal slice6_y_net : std_logic_vector( 27-1 downto 0 ); - signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); -begin - out_1 <= reinterpret0_output_port_net; - out_2 <= reinterpret1_output_port_net; - out_3 <= reinterpret2_output_port_net; - out_4 <= reinterpret3_output_port_net; - out_5 <= reinterpret4_output_port_net; - out_6 <= reinterpret5_output_port_net; - out_7 <= reinterpret6_output_port_net; - out_8 <= reinterpret7_output_port_net; - slice0_y_net <= in_1; - slice1_y_net <= in_2; - slice2_y_net <= in_3; - slice3_y_net <= in_4; - slice4_y_net <= in_5; - slice5_y_net <= in_6; - slice6_y_net <= in_7; - slice7_y_net <= in_8; - reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_4035468568 - port map ( - clk => '0', - ce => '0', - clr => '0', - input_port => slice0_y_net, - output_port => reinterpret0_output_port_net - ); - reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_4035468568 - port map ( - clk => '0', - ce => '0', - clr => '0', - input_port => slice1_y_net, - output_port => reinterpret1_output_port_net - ); - reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_4035468568 - port map ( - clk => '0', - ce => '0', - clr => '0', - input_port => slice2_y_net, - output_port => reinterpret2_output_port_net - ); - reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_4035468568 - port map ( - clk => '0', - ce => '0', - clr => '0', - input_port => slice3_y_net, - output_port => reinterpret3_output_port_net - ); - reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_4035468568 - port map ( - clk => '0', - ce => '0', - clr => '0', - input_port => slice4_y_net, - output_port => reinterpret4_output_port_net - ); - reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_4035468568 - port map ( - clk => '0', - ce => '0', - clr => '0', - input_port => slice5_y_net, - output_port => reinterpret5_output_port_net - ); - reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_4035468568 - port map ( - clk => '0', - ce => '0', - clr => '0', - input_port => slice6_y_net, - output_port => reinterpret6_output_port_net - ); - reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_4035468568 - port map ( - clk => '0', - ce => '0', - clr => '0', - input_port => slice7_y_net, - output_port => reinterpret7_output_port_net - ); -end structural; --- Generated from Simulink block ssr_8x8/Vector FFT/Vector Reinterpret3 -library IEEE; -use IEEE.std_logic_1164.all; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; -entity ssr_8x8_vector_reinterpret3 is - port ( - in_1 : in std_logic_vector( 27-1 downto 0 ); - in_2 : in std_logic_vector( 27-1 downto 0 ); - in_3 : in std_logic_vector( 27-1 downto 0 ); - in_4 : in std_logic_vector( 27-1 downto 0 ); - in_5 : in std_logic_vector( 27-1 downto 0 ); - in_6 : in std_logic_vector( 27-1 downto 0 ); - in_7 : in std_logic_vector( 27-1 downto 0 ); - in_8 : in std_logic_vector( 27-1 downto 0 ); - out_1 : out std_logic_vector( 27-1 downto 0 ); - out_2 : out std_logic_vector( 27-1 downto 0 ); - out_3 : out std_logic_vector( 27-1 downto 0 ); - out_4 : out std_logic_vector( 27-1 downto 0 ); - out_5 : out std_logic_vector( 27-1 downto 0 ); - out_6 : out std_logic_vector( 27-1 downto 0 ); - out_7 : out std_logic_vector( 27-1 downto 0 ); - out_8 : out std_logic_vector( 27-1 downto 0 ) - ); -end ssr_8x8_vector_reinterpret3; -architecture structural of ssr_8x8_vector_reinterpret3 is - signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); - signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); - signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); - signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); - signal slice0_y_net : std_logic_vector( 27-1 downto 0 ); - signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); - signal slice1_y_net : std_logic_vector( 27-1 downto 0 ); - signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); - signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); - signal slice2_y_net : std_logic_vector( 27-1 downto 0 ); - signal slice3_y_net : std_logic_vector( 27-1 downto 0 ); - signal slice4_y_net : std_logic_vector( 27-1 downto 0 ); - signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); - signal slice6_y_net : std_logic_vector( 27-1 downto 0 ); - signal slice5_y_net : std_logic_vector( 27-1 downto 0 ); - signal slice7_y_net : std_logic_vector( 27-1 downto 0 ); -begin - out_1 <= reinterpret0_output_port_net; - out_2 <= reinterpret1_output_port_net; - out_3 <= reinterpret2_output_port_net; - out_4 <= reinterpret3_output_port_net; - out_5 <= reinterpret4_output_port_net; - out_6 <= reinterpret5_output_port_net; - out_7 <= reinterpret6_output_port_net; - out_8 <= reinterpret7_output_port_net; - slice0_y_net <= in_1; - slice1_y_net <= in_2; - slice2_y_net <= in_3; - slice3_y_net <= in_4; - slice4_y_net <= in_5; - slice5_y_net <= in_6; - slice6_y_net <= in_7; - slice7_y_net <= in_8; - reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_4035468568 - port map ( - clk => '0', - ce => '0', - clr => '0', - input_port => slice0_y_net, - output_port => reinterpret0_output_port_net - ); - reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_4035468568 - port map ( - clk => '0', - ce => '0', - clr => '0', - input_port => slice1_y_net, - output_port => reinterpret1_output_port_net - ); - reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_4035468568 - port map ( - clk => '0', - ce => '0', - clr => '0', - input_port => slice2_y_net, - output_port => reinterpret2_output_port_net - ); - reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_4035468568 - port map ( - clk => '0', - ce => '0', - clr => '0', - input_port => slice3_y_net, - output_port => reinterpret3_output_port_net - ); - reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_4035468568 - port map ( - clk => '0', - ce => '0', - clr => '0', - input_port => slice4_y_net, - output_port => reinterpret4_output_port_net - ); - reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_4035468568 - port map ( - clk => '0', - ce => '0', - clr => '0', - input_port => slice5_y_net, - output_port => reinterpret5_output_port_net - ); - reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_4035468568 - port map ( - clk => '0', - ce => '0', - clr => '0', - input_port => slice6_y_net, - output_port => reinterpret6_output_port_net - ); - reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_4035468568 - port map ( - clk => '0', - ce => '0', - clr => '0', - input_port => slice7_y_net, - output_port => reinterpret7_output_port_net - ); -end structural; --- Generated from Simulink block ssr_8x8/Vector FFT/Vector Slice Im -library IEEE; -use IEEE.std_logic_1164.all; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; -entity ssr_8x8_vector_slice_im is - port ( - in_1 : in std_logic_vector( 54-1 downto 0 ); - in_2 : in std_logic_vector( 54-1 downto 0 ); - in_3 : in std_logic_vector( 54-1 downto 0 ); - in_4 : in std_logic_vector( 54-1 downto 0 ); - in_5 : in std_logic_vector( 54-1 downto 0 ); - in_6 : in std_logic_vector( 54-1 downto 0 ); - in_7 : in std_logic_vector( 54-1 downto 0 ); - in_8 : in std_logic_vector( 54-1 downto 0 ); - out_1 : out std_logic_vector( 27-1 downto 0 ); - out_2 : out std_logic_vector( 27-1 downto 0 ); - out_3 : out std_logic_vector( 27-1 downto 0 ); - out_4 : out std_logic_vector( 27-1 downto 0 ); - out_5 : out std_logic_vector( 27-1 downto 0 ); - out_6 : out std_logic_vector( 27-1 downto 0 ); - out_7 : out std_logic_vector( 27-1 downto 0 ); - out_8 : out std_logic_vector( 27-1 downto 0 ) - ); -end ssr_8x8_vector_slice_im; -architecture structural of ssr_8x8_vector_slice_im is - signal slice0_y_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal slice3_y_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal slice7_y_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal slice2_y_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal slice4_y_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal slice5_y_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal slice1_y_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal slice6_y_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal slice5_y_net : std_logic_vector( 54-1 downto 0 ); - signal slice3_y_net : std_logic_vector( 54-1 downto 0 ); - signal slice7_y_net : std_logic_vector( 54-1 downto 0 ); - signal slice0_y_net : std_logic_vector( 54-1 downto 0 ); - signal slice4_y_net : std_logic_vector( 54-1 downto 0 ); - signal slice6_y_net : std_logic_vector( 54-1 downto 0 ); - signal slice1_y_net : std_logic_vector( 54-1 downto 0 ); - signal slice2_y_net : std_logic_vector( 54-1 downto 0 ); -begin - out_1 <= slice0_y_net_x0; - out_2 <= slice1_y_net_x0; - out_3 <= slice2_y_net_x0; - out_4 <= slice3_y_net_x0; - out_5 <= slice4_y_net_x0; - out_6 <= slice5_y_net_x0; - out_7 <= slice6_y_net_x0; - out_8 <= slice7_y_net_x0; - slice0_y_net <= in_1; - slice1_y_net <= in_2; - slice2_y_net <= in_3; - slice3_y_net <= in_4; - slice4_y_net <= in_5; - slice5_y_net <= in_6; - slice6_y_net <= in_7; - slice7_y_net <= in_8; - slice0 : entity xil_defaultlib.ssr_8x8_xlslice - generic map ( - new_lsb => 27, - new_msb => 53, - x_width => 54, - y_width => 27 - ) - port map ( - x => slice0_y_net, - y => slice0_y_net_x0 - ); - slice1 : entity xil_defaultlib.ssr_8x8_xlslice - generic map ( - new_lsb => 27, - new_msb => 53, - x_width => 54, - y_width => 27 - ) - port map ( - x => slice1_y_net, - y => slice1_y_net_x0 - ); - slice2 : entity xil_defaultlib.ssr_8x8_xlslice - generic map ( - new_lsb => 27, - new_msb => 53, - x_width => 54, - y_width => 27 - ) - port map ( - x => slice2_y_net, - y => slice2_y_net_x0 - ); - slice3 : entity xil_defaultlib.ssr_8x8_xlslice - generic map ( - new_lsb => 27, - new_msb => 53, - x_width => 54, - y_width => 27 - ) - port map ( - x => slice3_y_net, - y => slice3_y_net_x0 - ); - slice4 : entity xil_defaultlib.ssr_8x8_xlslice - generic map ( - new_lsb => 27, - new_msb => 53, - x_width => 54, - y_width => 27 - ) - port map ( - x => slice4_y_net, - y => slice4_y_net_x0 - ); - slice5 : entity xil_defaultlib.ssr_8x8_xlslice - generic map ( - new_lsb => 27, - new_msb => 53, - x_width => 54, - y_width => 27 - ) - port map ( - x => slice5_y_net, - y => slice5_y_net_x0 - ); - slice6 : entity xil_defaultlib.ssr_8x8_xlslice - generic map ( - new_lsb => 27, - new_msb => 53, - x_width => 54, - y_width => 27 - ) - port map ( - x => slice6_y_net, - y => slice6_y_net_x0 - ); - slice7 : entity xil_defaultlib.ssr_8x8_xlslice - generic map ( - new_lsb => 27, - new_msb => 53, - x_width => 54, - y_width => 27 - ) - port map ( - x => slice7_y_net, - y => slice7_y_net_x0 - ); -end structural; --- Generated from Simulink block ssr_8x8/Vector FFT/Vector Slice Re -library IEEE; -use IEEE.std_logic_1164.all; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; -entity ssr_8x8_vector_slice_re is - port ( - in_1 : in std_logic_vector( 54-1 downto 0 ); - in_2 : in std_logic_vector( 54-1 downto 0 ); - in_3 : in std_logic_vector( 54-1 downto 0 ); - in_4 : in std_logic_vector( 54-1 downto 0 ); - in_5 : in std_logic_vector( 54-1 downto 0 ); - in_6 : in std_logic_vector( 54-1 downto 0 ); - in_7 : in std_logic_vector( 54-1 downto 0 ); - in_8 : in std_logic_vector( 54-1 downto 0 ); - out_1 : out std_logic_vector( 27-1 downto 0 ); - out_2 : out std_logic_vector( 27-1 downto 0 ); - out_3 : out std_logic_vector( 27-1 downto 0 ); - out_4 : out std_logic_vector( 27-1 downto 0 ); - out_5 : out std_logic_vector( 27-1 downto 0 ); - out_6 : out std_logic_vector( 27-1 downto 0 ); - out_7 : out std_logic_vector( 27-1 downto 0 ); - out_8 : out std_logic_vector( 27-1 downto 0 ) - ); -end ssr_8x8_vector_slice_re; -architecture structural of ssr_8x8_vector_slice_re is - signal slice4_y_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal slice2_y_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal slice5_y_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal slice6_y_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal slice0_y_net : std_logic_vector( 54-1 downto 0 ); - signal slice2_y_net : std_logic_vector( 54-1 downto 0 ); - signal slice3_y_net : std_logic_vector( 54-1 downto 0 ); - signal slice0_y_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal slice1_y_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal slice1_y_net : std_logic_vector( 54-1 downto 0 ); - signal slice4_y_net : std_logic_vector( 54-1 downto 0 ); - signal slice7_y_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal slice5_y_net : std_logic_vector( 54-1 downto 0 ); - signal slice3_y_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal slice6_y_net : std_logic_vector( 54-1 downto 0 ); - signal slice7_y_net : std_logic_vector( 54-1 downto 0 ); -begin - out_1 <= slice0_y_net_x0; - out_2 <= slice1_y_net_x0; - out_3 <= slice2_y_net_x0; - out_4 <= slice3_y_net_x0; - out_5 <= slice4_y_net_x0; - out_6 <= slice5_y_net_x0; - out_7 <= slice6_y_net_x0; - out_8 <= slice7_y_net_x0; - slice0_y_net <= in_1; - slice1_y_net <= in_2; - slice2_y_net <= in_3; - slice3_y_net <= in_4; - slice4_y_net <= in_5; - slice5_y_net <= in_6; - slice6_y_net <= in_7; - slice7_y_net <= in_8; - slice0 : entity xil_defaultlib.ssr_8x8_xlslice - generic map ( - new_lsb => 0, - new_msb => 26, - x_width => 54, - y_width => 27 - ) - port map ( - x => slice0_y_net, - y => slice0_y_net_x0 - ); - slice1 : entity xil_defaultlib.ssr_8x8_xlslice - generic map ( - new_lsb => 0, - new_msb => 26, - x_width => 54, - y_width => 27 - ) - port map ( - x => slice1_y_net, - y => slice1_y_net_x0 - ); - slice2 : entity xil_defaultlib.ssr_8x8_xlslice - generic map ( - new_lsb => 0, - new_msb => 26, - x_width => 54, - y_width => 27 - ) - port map ( - x => slice2_y_net, - y => slice2_y_net_x0 - ); - slice3 : entity xil_defaultlib.ssr_8x8_xlslice - generic map ( - new_lsb => 0, - new_msb => 26, - x_width => 54, - y_width => 27 - ) - port map ( - x => slice3_y_net, - y => slice3_y_net_x0 - ); - slice4 : entity xil_defaultlib.ssr_8x8_xlslice - generic map ( - new_lsb => 0, - new_msb => 26, - x_width => 54, - y_width => 27 - ) - port map ( - x => slice4_y_net, - y => slice4_y_net_x0 - ); - slice5 : entity xil_defaultlib.ssr_8x8_xlslice - generic map ( - new_lsb => 0, - new_msb => 26, - x_width => 54, - y_width => 27 - ) - port map ( - x => slice5_y_net, - y => slice5_y_net_x0 - ); - slice6 : entity xil_defaultlib.ssr_8x8_xlslice - generic map ( - new_lsb => 0, - new_msb => 26, - x_width => 54, - y_width => 27 - ) - port map ( - x => slice6_y_net, - y => slice6_y_net_x0 - ); - slice7 : entity xil_defaultlib.ssr_8x8_xlslice - generic map ( - new_lsb => 0, - new_msb => 26, - x_width => 54, - y_width => 27 - ) - port map ( - x => slice7_y_net, - y => slice7_y_net_x0 - ); -end structural; --- Generated from Simulink block ssr_8x8/Vector FFT/Vector2Scalar -library IEEE; -use IEEE.std_logic_1164.all; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; -entity ssr_8x8_vector2scalar is - port ( - i_1 : in std_logic_vector( 32-1 downto 0 ); - i_2 : in std_logic_vector( 32-1 downto 0 ); - i_3 : in std_logic_vector( 32-1 downto 0 ); - i_4 : in std_logic_vector( 32-1 downto 0 ); - i_5 : in std_logic_vector( 32-1 downto 0 ); - i_6 : in std_logic_vector( 32-1 downto 0 ); - i_7 : in std_logic_vector( 32-1 downto 0 ); - i_8 : in std_logic_vector( 32-1 downto 0 ); - o : out std_logic_vector( 256-1 downto 0 ) - ); -end ssr_8x8_vector2scalar; -architecture structural of ssr_8x8_vector2scalar is - signal delay1_q_net : std_logic_vector( 32-1 downto 0 ); - signal delay3_q_net : std_logic_vector( 32-1 downto 0 ); - signal delay4_q_net : std_logic_vector( 32-1 downto 0 ); - signal concat1_y_net : std_logic_vector( 256-1 downto 0 ); - signal delay0_q_net : std_logic_vector( 32-1 downto 0 ); - signal delay5_q_net : std_logic_vector( 32-1 downto 0 ); - signal delay6_q_net : std_logic_vector( 32-1 downto 0 ); - signal delay7_q_net : std_logic_vector( 32-1 downto 0 ); - signal delay2_q_net : std_logic_vector( 32-1 downto 0 ); -begin - o <= concat1_y_net; - delay0_q_net <= i_1; - delay1_q_net <= i_2; - delay2_q_net <= i_3; - delay3_q_net <= i_4; - delay4_q_net <= i_5; - delay5_q_net <= i_6; - delay6_q_net <= i_7; - delay7_q_net <= i_8; - concat1 : entity xil_defaultlib.sysgen_concat_7ca5184bef - port map ( - clk => '0', - ce => '0', - clr => '0', - in0 => delay7_q_net, - in1 => delay6_q_net, - in2 => delay5_q_net, - in3 => delay4_q_net, - in4 => delay3_q_net, - in5 => delay2_q_net, - in6 => delay1_q_net, - in7 => delay0_q_net, - y => concat1_y_net - ); -end structural; --- Generated from Simulink block ssr_8x8/Vector FFT -library IEEE; -use IEEE.std_logic_1164.all; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; -entity ssr_8x8_vector_fft is - port ( - i_re_1 : in std_logic_vector( 16-1 downto 0 ); - i_im_1 : in std_logic_vector( 16-1 downto 0 ); - vi : in std_logic_vector( 1-1 downto 0 ); - si : in std_logic_vector( 3-1 downto 0 ); - i_re_2 : in std_logic_vector( 16-1 downto 0 ); - i_re_3 : in std_logic_vector( 16-1 downto 0 ); - i_re_4 : in std_logic_vector( 16-1 downto 0 ); - i_re_5 : in std_logic_vector( 16-1 downto 0 ); - i_re_6 : in std_logic_vector( 16-1 downto 0 ); - i_re_7 : in std_logic_vector( 16-1 downto 0 ); - i_re_8 : in std_logic_vector( 16-1 downto 0 ); - i_im_2 : in std_logic_vector( 16-1 downto 0 ); - i_im_3 : in std_logic_vector( 16-1 downto 0 ); - i_im_4 : in std_logic_vector( 16-1 downto 0 ); - i_im_5 : in std_logic_vector( 16-1 downto 0 ); - i_im_6 : in std_logic_vector( 16-1 downto 0 ); - i_im_7 : in std_logic_vector( 16-1 downto 0 ); - i_im_8 : in std_logic_vector( 16-1 downto 0 ); - clk_1 : in std_logic; - ce_1 : in std_logic; - o_re_1 : out std_logic_vector( 27-1 downto 0 ); - o_im_1 : out std_logic_vector( 27-1 downto 0 ); - vo : out std_logic; - so : out std_logic_vector( 3-1 downto 0 ); - o_re_2 : out std_logic_vector( 27-1 downto 0 ); - o_re_3 : out std_logic_vector( 27-1 downto 0 ); - o_re_4 : out std_logic_vector( 27-1 downto 0 ); - o_re_5 : out std_logic_vector( 27-1 downto 0 ); - o_re_6 : out std_logic_vector( 27-1 downto 0 ); - o_re_7 : out std_logic_vector( 27-1 downto 0 ); - o_re_8 : out std_logic_vector( 27-1 downto 0 ); - o_im_2 : out std_logic_vector( 27-1 downto 0 ); - o_im_3 : out std_logic_vector( 27-1 downto 0 ); - o_im_4 : out std_logic_vector( 27-1 downto 0 ); - o_im_5 : out std_logic_vector( 27-1 downto 0 ); - o_im_6 : out std_logic_vector( 27-1 downto 0 ); - o_im_7 : out std_logic_vector( 27-1 downto 0 ); - o_im_8 : out std_logic_vector( 27-1 downto 0 ) - ); -end ssr_8x8_vector_fft; -architecture structural of ssr_8x8_vector_fft is - signal slice5_y_net : std_logic_vector( 27-1 downto 0 ); - signal reinterpret2_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); - signal slice1_y_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal slice3_y_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal reinterpret0_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); - signal slice6_y_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal delay5_q_net : std_logic_vector( 32-1 downto 0 ); - signal reinterpret4_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); - signal concat3_y_net : std_logic_vector( 32-1 downto 0 ); - signal slice0_y_net : std_logic_vector( 27-1 downto 0 ); - signal slice4_y_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal concat7_y_net : std_logic_vector( 32-1 downto 0 ); - signal slice0_y_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal delay4_q_net : std_logic_vector( 32-1 downto 0 ); - signal delay6_q_net : std_logic_vector( 32-1 downto 0 ); - signal concat1_y_net : std_logic_vector( 256-1 downto 0 ); - signal delay_q_net : std_logic_vector( 1-1 downto 0 ); - signal delay7_q_net : std_logic_vector( 32-1 downto 0 ); - signal slice5_y_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal reinterpret0_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); - signal reinterpret5_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); - signal concat0_y_net : std_logic_vector( 32-1 downto 0 ); - signal delay1_q_net : std_logic_vector( 32-1 downto 0 ); - signal slice2_y_net : std_logic_vector( 27-1 downto 0 ); - signal reinterpret2_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); - signal reinterpret1_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); - signal reinterpret7_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); - signal slice2_y_net_x1 : std_logic_vector( 54-1 downto 0 ); - signal slice6_y_net_x1 : std_logic_vector( 54-1 downto 0 ); - signal reinterpret7_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); - signal delay2_q_net : std_logic_vector( 32-1 downto 0 ); - signal concat4_y_net : std_logic_vector( 32-1 downto 0 ); - signal reinterpret6_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); - signal slice3_y_net : std_logic_vector( 27-1 downto 0 ); - signal concat2_y_net : std_logic_vector( 32-1 downto 0 ); - signal reinterpret1_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); - signal slice3_y_net_x1 : std_logic_vector( 54-1 downto 0 ); - signal reinterpret6_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); - signal reinterpret3_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); - signal slice7_y_net_x1 : std_logic_vector( 54-1 downto 0 ); - signal delay0_q_net : std_logic_vector( 32-1 downto 0 ); - signal slice1_y_net : std_logic_vector( 27-1 downto 0 ); - signal slice4_y_net : std_logic_vector( 27-1 downto 0 ); - signal slice6_y_net : std_logic_vector( 27-1 downto 0 ); - signal concat1_y_net_x0 : std_logic_vector( 32-1 downto 0 ); - signal slice7_y_net : std_logic_vector( 27-1 downto 0 ); - signal slice2_y_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal slice7_y_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal slice4_y_net_x1 : std_logic_vector( 54-1 downto 0 ); - signal slice5_y_net_x1 : std_logic_vector( 54-1 downto 0 ); - signal test_systolicfft_vhdl_black_box_o_net : std_logic_vector( 432-1 downto 0 ); - signal concat5_y_net : std_logic_vector( 32-1 downto 0 ); - signal delay3_q_net : std_logic_vector( 32-1 downto 0 ); - signal reinterpret3_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); - signal reinterpret4_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); - signal concat6_y_net : std_logic_vector( 32-1 downto 0 ); - signal reinterpret5_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); - signal delay1_q_net_x0 : std_logic_vector( 3-1 downto 0 ); - signal reinterpret4_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); - signal test_systolicfft_vhdl_black_box_vo_net : std_logic; - signal test_systolicfft_vhdl_black_box_so_net : std_logic_vector( 3-1 downto 0 ); - signal reinterpret1_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal reinterpret2_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal reinterpret0_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal reinterpret3_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal reinterpret5_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); - signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); - signal clk_net : std_logic; - signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); - signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); - signal i_valid_net : std_logic_vector( 1-1 downto 0 ); - signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); - signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); - signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); - signal slice0_y_net_x1 : std_logic_vector( 54-1 downto 0 ); - signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); - signal slice1_y_net_x1 : std_logic_vector( 54-1 downto 0 ); - signal reinterpret6_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); - signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); - signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); - signal reinterpret7_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); - signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); - signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); - signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); - signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); - signal i_scale_net : std_logic_vector( 3-1 downto 0 ); - signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); - signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); - signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); - signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); - signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); - signal ce_net : std_logic; - signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); - signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); -begin - o_re_1 <= reinterpret0_output_port_net_x0; - o_im_1 <= reinterpret0_output_port_net; - vo <= test_systolicfft_vhdl_black_box_vo_net; - so <= test_systolicfft_vhdl_black_box_so_net; - o_re_2 <= reinterpret1_output_port_net_x0; - o_re_3 <= reinterpret2_output_port_net_x0; - o_re_4 <= reinterpret3_output_port_net_x0; - o_re_5 <= reinterpret4_output_port_net_x0; - o_re_6 <= reinterpret5_output_port_net_x0; - o_re_7 <= reinterpret6_output_port_net_x0; - o_re_8 <= reinterpret7_output_port_net_x0; - o_im_2 <= reinterpret1_output_port_net; - o_im_3 <= reinterpret2_output_port_net; - o_im_4 <= reinterpret3_output_port_net; - o_im_5 <= reinterpret4_output_port_net; - o_im_6 <= reinterpret5_output_port_net; - o_im_7 <= reinterpret6_output_port_net; - o_im_8 <= reinterpret7_output_port_net; - i_re_0_net <= i_re_1; - i_im_0_net <= i_im_1; - i_valid_net <= vi; - i_scale_net <= si; - i_re_1_net <= i_re_2; - i_re_2_net <= i_re_3; - i_re_3_net <= i_re_4; - i_re_4_net <= i_re_5; - i_re_5_net <= i_re_6; - i_re_6_net <= i_re_7; - i_re_7_net <= i_re_8; - i_im_1_net <= i_im_2; - i_im_2_net <= i_im_3; - i_im_3_net <= i_im_4; - i_im_4_net <= i_im_5; - i_im_5_net <= i_im_6; - i_im_6_net <= i_im_7; - i_im_7_net <= i_im_8; - clk_net <= clk_1; - ce_net <= ce_1; - scalar2vector : entity xil_defaultlib.ssr_8x8_scalar2vector - port map ( - i => test_systolicfft_vhdl_black_box_o_net, - o_1 => slice0_y_net_x1, - o_2 => slice1_y_net_x1, - o_3 => slice2_y_net_x1, - o_4 => slice3_y_net_x1, - o_5 => slice4_y_net_x1, - o_6 => slice5_y_net_x1, - o_7 => slice6_y_net_x1, - o_8 => slice7_y_net_x1 - ); - vector_concat : entity xil_defaultlib.ssr_8x8_vector_concat - port map ( - hi_1 => reinterpret0_output_port_net_x1, - lo_1 => reinterpret0_output_port_net_x2, - hi_2 => reinterpret1_output_port_net_x1, - hi_3 => reinterpret2_output_port_net_x1, - hi_4 => reinterpret3_output_port_net_x1, - hi_5 => reinterpret4_output_port_net_x1, - hi_6 => reinterpret5_output_port_net_x1, - hi_7 => reinterpret6_output_port_net_x1, - hi_8 => reinterpret7_output_port_net_x1, - lo_2 => reinterpret1_output_port_net_x2, - lo_3 => reinterpret2_output_port_net_x2, - lo_4 => reinterpret3_output_port_net_x2, - lo_5 => reinterpret4_output_port_net_x2, - lo_6 => reinterpret5_output_port_net_x2, - lo_7 => reinterpret6_output_port_net_x2, - lo_8 => reinterpret7_output_port_net_x2, - out_1 => concat0_y_net, - out_2 => concat1_y_net_x0, - out_3 => concat2_y_net, - out_4 => concat3_y_net, - out_5 => concat4_y_net, - out_6 => concat5_y_net, - out_7 => concat6_y_net, - out_8 => concat7_y_net - ); - vector_delay : entity xil_defaultlib.ssr_8x8_vector_delay - port map ( - d_1 => concat0_y_net, - d_2 => concat1_y_net_x0, - d_3 => concat2_y_net, - d_4 => concat3_y_net, - d_5 => concat4_y_net, - d_6 => concat5_y_net, - d_7 => concat6_y_net, - d_8 => concat7_y_net, - clk_1 => clk_net, - ce_1 => ce_net, - q_1 => delay0_q_net, - q_2 => delay1_q_net, - q_3 => delay2_q_net, - q_4 => delay3_q_net, - q_5 => delay4_q_net, - q_6 => delay5_q_net, - q_7 => delay6_q_net, - q_8 => delay7_q_net - ); - vector_reinterpret : entity xil_defaultlib.ssr_8x8_vector_reinterpret - port map ( - in_1 => i_re_0_net, - in_2 => i_re_1_net, - in_3 => i_re_2_net, - in_4 => i_re_3_net, - in_5 => i_re_4_net, - in_6 => i_re_5_net, - in_7 => i_re_6_net, - in_8 => i_re_7_net, - out_1 => reinterpret0_output_port_net_x2, - out_2 => reinterpret1_output_port_net_x2, - out_3 => reinterpret2_output_port_net_x2, - out_4 => reinterpret3_output_port_net_x2, - out_5 => reinterpret4_output_port_net_x2, - out_6 => reinterpret5_output_port_net_x2, - out_7 => reinterpret6_output_port_net_x2, - out_8 => reinterpret7_output_port_net_x2 - ); - vector_reinterpret1 : entity xil_defaultlib.ssr_8x8_vector_reinterpret1 - port map ( - in_1 => i_im_0_net, - in_2 => i_im_1_net, - in_3 => i_im_2_net, - in_4 => i_im_3_net, - in_5 => i_im_4_net, - in_6 => i_im_5_net, - in_7 => i_im_6_net, - in_8 => i_im_7_net, - out_1 => reinterpret0_output_port_net_x1, - out_2 => reinterpret1_output_port_net_x1, - out_3 => reinterpret2_output_port_net_x1, - out_4 => reinterpret3_output_port_net_x1, - out_5 => reinterpret4_output_port_net_x1, - out_6 => reinterpret5_output_port_net_x1, - out_7 => reinterpret6_output_port_net_x1, - out_8 => reinterpret7_output_port_net_x1 - ); - vector_reinterpret2 : entity xil_defaultlib.ssr_8x8_vector_reinterpret2 - port map ( - in_1 => slice0_y_net, - in_2 => slice1_y_net, - in_3 => slice2_y_net, - in_4 => slice3_y_net, - in_5 => slice4_y_net, - in_6 => slice5_y_net, - in_7 => slice6_y_net, - in_8 => slice7_y_net, - out_1 => reinterpret0_output_port_net_x0, - out_2 => reinterpret1_output_port_net_x0, - out_3 => reinterpret2_output_port_net_x0, - out_4 => reinterpret3_output_port_net_x0, - out_5 => reinterpret4_output_port_net_x0, - out_6 => reinterpret5_output_port_net_x0, - out_7 => reinterpret6_output_port_net_x0, - out_8 => reinterpret7_output_port_net_x0 - ); - vector_reinterpret3 : entity xil_defaultlib.ssr_8x8_vector_reinterpret3 - port map ( - in_1 => slice0_y_net_x0, - in_2 => slice1_y_net_x0, - in_3 => slice2_y_net_x0, - in_4 => slice3_y_net_x0, - in_5 => slice4_y_net_x0, - in_6 => slice5_y_net_x0, - in_7 => slice6_y_net_x0, - in_8 => slice7_y_net_x0, - out_1 => reinterpret0_output_port_net, - out_2 => reinterpret1_output_port_net, - out_3 => reinterpret2_output_port_net, - out_4 => reinterpret3_output_port_net, - out_5 => reinterpret4_output_port_net, - out_6 => reinterpret5_output_port_net, - out_7 => reinterpret6_output_port_net, - out_8 => reinterpret7_output_port_net - ); - vector_slice_im : entity xil_defaultlib.ssr_8x8_vector_slice_im - port map ( - in_1 => slice0_y_net_x1, - in_2 => slice1_y_net_x1, - in_3 => slice2_y_net_x1, - in_4 => slice3_y_net_x1, - in_5 => slice4_y_net_x1, - in_6 => slice5_y_net_x1, - in_7 => slice6_y_net_x1, - in_8 => slice7_y_net_x1, - out_1 => slice0_y_net_x0, - out_2 => slice1_y_net_x0, - out_3 => slice2_y_net_x0, - out_4 => slice3_y_net_x0, - out_5 => slice4_y_net_x0, - out_6 => slice5_y_net_x0, - out_7 => slice6_y_net_x0, - out_8 => slice7_y_net_x0 - ); - vector_slice_re : entity xil_defaultlib.ssr_8x8_vector_slice_re - port map ( - in_1 => slice0_y_net_x1, - in_2 => slice1_y_net_x1, - in_3 => slice2_y_net_x1, - in_4 => slice3_y_net_x1, - in_5 => slice4_y_net_x1, - in_6 => slice5_y_net_x1, - in_7 => slice6_y_net_x1, - in_8 => slice7_y_net_x1, - out_1 => slice0_y_net, - out_2 => slice1_y_net, - out_3 => slice2_y_net, - out_4 => slice3_y_net, - out_5 => slice4_y_net, - out_6 => slice5_y_net, - out_7 => slice6_y_net, - out_8 => slice7_y_net - ); - vector2scalar : entity xil_defaultlib.ssr_8x8_vector2scalar - port map ( - i_1 => delay0_q_net, - i_2 => delay1_q_net, - i_3 => delay2_q_net, - i_4 => delay3_q_net, - i_5 => delay4_q_net, - i_6 => delay5_q_net, - i_7 => delay6_q_net, - i_8 => delay7_q_net, - o => concat1_y_net - ); - delay : entity xil_defaultlib.ssr_8x8_xldelay - generic map ( - latency => 4, - reg_retiming => 0, - reset => 0, - width => 1 - ) - port map ( - en => '1', - rst => '0', - d => i_valid_net, - clk => clk_net, - ce => ce_net, - q => delay_q_net - ); - delay1 : entity xil_defaultlib.ssr_8x8_xldelay - generic map ( - latency => 4, - reg_retiming => 0, - reset => 0, - width => 3 - ) - port map ( - en => '1', - rst => '0', - d => i_scale_net, - clk => clk_net, - ce => ce_net, - q => delay1_q_net_x0 - ); - test_systolicfft_vhdl_black_box : entity xil_defaultlib.WRAPPER_VECTOR_FFT_29450ae4dbd3eb51515dab58c9ac6776 - generic map ( - BRAM_THRESHOLD => 258, - DSP48E => 2, - I_high => -2, - I_low => -17, - L2N => 3, - N => 8, - O_high => 9, - O_low => -17, - SSR => 8, - W_high => 1, - W_low => -17 - ) - port map ( - i => concat1_y_net, - vi => delay_q_net(0), - si => delay1_q_net_x0, - CLK => clk_net, - CE => ce_net, - o => test_systolicfft_vhdl_black_box_o_net, - vo => test_systolicfft_vhdl_black_box_vo_net, - so => test_systolicfft_vhdl_black_box_so_net - ); -end structural; --- Generated from Simulink block ssr_8x8/i_im -library IEEE; -use IEEE.std_logic_1164.all; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; -entity ssr_8x8_i_im is - port ( - i_im_0 : in std_logic_vector( 16-1 downto 0 ); - i_im_1 : in std_logic_vector( 16-1 downto 0 ); - i_im_2 : in std_logic_vector( 16-1 downto 0 ); - i_im_3 : in std_logic_vector( 16-1 downto 0 ); - i_im_4 : in std_logic_vector( 16-1 downto 0 ); - i_im_5 : in std_logic_vector( 16-1 downto 0 ); - i_im_6 : in std_logic_vector( 16-1 downto 0 ); - i_im_7 : in std_logic_vector( 16-1 downto 0 ) - ); -end ssr_8x8_i_im; -architecture structural of ssr_8x8_i_im is - signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); - signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); - signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); - signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); - signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); - signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); - signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); - signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); -begin - i_im_0_net <= i_im_0; - i_im_1_net <= i_im_1; - i_im_2_net <= i_im_2; - i_im_3_net <= i_im_3; - i_im_4_net <= i_im_4; - i_im_5_net <= i_im_5; - i_im_6_net <= i_im_6; - i_im_7_net <= i_im_7; -end structural; --- Generated from Simulink block ssr_8x8/i_re -library IEEE; -use IEEE.std_logic_1164.all; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; -entity ssr_8x8_i_re is - port ( - i_re_0 : in std_logic_vector( 16-1 downto 0 ); - i_re_1 : in std_logic_vector( 16-1 downto 0 ); - i_re_2 : in std_logic_vector( 16-1 downto 0 ); - i_re_3 : in std_logic_vector( 16-1 downto 0 ); - i_re_4 : in std_logic_vector( 16-1 downto 0 ); - i_re_5 : in std_logic_vector( 16-1 downto 0 ); - i_re_6 : in std_logic_vector( 16-1 downto 0 ); - i_re_7 : in std_logic_vector( 16-1 downto 0 ) - ); -end ssr_8x8_i_re; -architecture structural of ssr_8x8_i_re is - signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); - signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); - signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); - signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); - signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); - signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); - signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); - signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); -begin - i_re_0_net <= i_re_0; - i_re_1_net <= i_re_1; - i_re_2_net <= i_re_2; - i_re_3_net <= i_re_3; - i_re_4_net <= i_re_4; - i_re_5_net <= i_re_5; - i_re_6_net <= i_re_6; - i_re_7_net <= i_re_7; -end structural; --- Generated from Simulink block ssr_8x8_struct -library IEEE; -use IEEE.std_logic_1164.all; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; -entity ssr_8x8_struct is - port ( - i_scale : in std_logic_vector( 3-1 downto 0 ); - i_valid : in std_logic_vector( 1-1 downto 0 ); - i_im_0 : in std_logic_vector( 16-1 downto 0 ); - i_im_1 : in std_logic_vector( 16-1 downto 0 ); - i_im_2 : in std_logic_vector( 16-1 downto 0 ); - i_im_3 : in std_logic_vector( 16-1 downto 0 ); - i_im_4 : in std_logic_vector( 16-1 downto 0 ); - i_im_5 : in std_logic_vector( 16-1 downto 0 ); - i_im_6 : in std_logic_vector( 16-1 downto 0 ); - i_im_7 : in std_logic_vector( 16-1 downto 0 ); - i_re_0 : in std_logic_vector( 16-1 downto 0 ); - i_re_1 : in std_logic_vector( 16-1 downto 0 ); - i_re_2 : in std_logic_vector( 16-1 downto 0 ); - i_re_3 : in std_logic_vector( 16-1 downto 0 ); - i_re_4 : in std_logic_vector( 16-1 downto 0 ); - i_re_5 : in std_logic_vector( 16-1 downto 0 ); - i_re_6 : in std_logic_vector( 16-1 downto 0 ); - i_re_7 : in std_logic_vector( 16-1 downto 0 ); - clk_1 : in std_logic; - ce_1 : in std_logic; - o_scale : out std_logic_vector( 3-1 downto 0 ); - o_valid : out std_logic_vector( 1-1 downto 0 ); - o_im_0 : out std_logic_vector( 27-1 downto 0 ); - o_im_1 : out std_logic_vector( 27-1 downto 0 ); - o_im_2 : out std_logic_vector( 27-1 downto 0 ); - o_im_3 : out std_logic_vector( 27-1 downto 0 ); - o_im_4 : out std_logic_vector( 27-1 downto 0 ); - o_im_5 : out std_logic_vector( 27-1 downto 0 ); - o_im_6 : out std_logic_vector( 27-1 downto 0 ); - o_im_7 : out std_logic_vector( 27-1 downto 0 ); - o_re_0 : out std_logic_vector( 27-1 downto 0 ); - o_re_1 : out std_logic_vector( 27-1 downto 0 ); - o_re_2 : out std_logic_vector( 27-1 downto 0 ); - o_re_3 : out std_logic_vector( 27-1 downto 0 ); - o_re_4 : out std_logic_vector( 27-1 downto 0 ); - o_re_5 : out std_logic_vector( 27-1 downto 0 ); - o_re_6 : out std_logic_vector( 27-1 downto 0 ); - o_re_7 : out std_logic_vector( 27-1 downto 0 ) - ); -end ssr_8x8_struct; -architecture structural of ssr_8x8_struct is - signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); - signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); - signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); - signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); - signal reinterpret3_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); - signal reinterpret0_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); - signal reinterpret7_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal reinterpret2_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); - signal ce_net : std_logic; - signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); - signal reinterpret1_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal reinterpret6_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal reinterpret5_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal reinterpret4_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); - signal clk_net : std_logic; - signal i_scale_net : std_logic_vector( 3-1 downto 0 ); - signal i_valid_net : std_logic_vector( 1-1 downto 0 ); - signal test_systolicfft_vhdl_black_box_vo_net : std_logic_vector( 1-1 downto 0 ); - signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); - signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); - signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); - signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); - signal test_systolicfft_vhdl_black_box_so_net : std_logic_vector( 3-1 downto 0 ); - signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); - signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); - signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); - signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); - signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); - signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); - signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); - signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); - signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); - signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); - signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); - signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); -begin - i_scale_net <= i_scale; - i_valid_net <= i_valid; - o_scale <= test_systolicfft_vhdl_black_box_so_net; - o_valid <= test_systolicfft_vhdl_black_box_vo_net; - i_im_0_net <= i_im_0; - i_im_1_net <= i_im_1; - i_im_2_net <= i_im_2; - i_im_3_net <= i_im_3; - i_im_4_net <= i_im_4; - i_im_5_net <= i_im_5; - i_im_6_net <= i_im_6; - i_im_7_net <= i_im_7; - i_re_0_net <= i_re_0; - i_re_1_net <= i_re_1; - i_re_2_net <= i_re_2; - i_re_3_net <= i_re_3; - i_re_4_net <= i_re_4; - i_re_5_net <= i_re_5; - i_re_6_net <= i_re_6; - i_re_7_net <= i_re_7; - o_im_0 <= reinterpret0_output_port_net; - o_im_1 <= reinterpret1_output_port_net; - o_im_2 <= reinterpret2_output_port_net; - o_im_3 <= reinterpret3_output_port_net; - o_im_4 <= reinterpret4_output_port_net_x0; - o_im_5 <= reinterpret5_output_port_net; - o_im_6 <= reinterpret6_output_port_net; - o_im_7 <= reinterpret7_output_port_net; - o_re_0 <= reinterpret0_output_port_net_x0; - o_re_1 <= reinterpret1_output_port_net_x0; - o_re_2 <= reinterpret2_output_port_net_x0; - o_re_3 <= reinterpret3_output_port_net_x0; - o_re_4 <= reinterpret4_output_port_net; - o_re_5 <= reinterpret5_output_port_net_x0; - o_re_6 <= reinterpret6_output_port_net_x0; - o_re_7 <= reinterpret7_output_port_net_x0; - clk_net <= clk_1; - ce_net <= ce_1; - vector_fft : entity xil_defaultlib.ssr_8x8_vector_fft - port map ( - i_re_1 => i_re_0_net, - i_im_1 => i_im_0_net, - vi => i_valid_net, - si => i_scale_net, - i_re_2 => i_re_1_net, - i_re_3 => i_re_2_net, - i_re_4 => i_re_3_net, - i_re_5 => i_re_4_net, - i_re_6 => i_re_5_net, - i_re_7 => i_re_6_net, - i_re_8 => i_re_7_net, - i_im_2 => i_im_1_net, - i_im_3 => i_im_2_net, - i_im_4 => i_im_3_net, - i_im_5 => i_im_4_net, - i_im_6 => i_im_5_net, - i_im_7 => i_im_6_net, - i_im_8 => i_im_7_net, - clk_1 => clk_net, - ce_1 => ce_net, - o_re_1 => reinterpret0_output_port_net_x0, - o_im_1 => reinterpret0_output_port_net, - vo => test_systolicfft_vhdl_black_box_vo_net(0), - so => test_systolicfft_vhdl_black_box_so_net, - o_re_2 => reinterpret1_output_port_net_x0, - o_re_3 => reinterpret2_output_port_net_x0, - o_re_4 => reinterpret3_output_port_net_x0, - o_re_5 => reinterpret4_output_port_net, - o_re_6 => reinterpret5_output_port_net_x0, - o_re_7 => reinterpret6_output_port_net_x0, - o_re_8 => reinterpret7_output_port_net_x0, - o_im_2 => reinterpret1_output_port_net, - o_im_3 => reinterpret2_output_port_net, - o_im_4 => reinterpret3_output_port_net, - o_im_5 => reinterpret4_output_port_net_x0, - o_im_6 => reinterpret5_output_port_net, - o_im_7 => reinterpret6_output_port_net, - o_im_8 => reinterpret7_output_port_net - ); - i_im : entity xil_defaultlib.ssr_8x8_i_im - port map ( - i_im_0 => i_im_0_net, - i_im_1 => i_im_1_net, - i_im_2 => i_im_2_net, - i_im_3 => i_im_3_net, - i_im_4 => i_im_4_net, - i_im_5 => i_im_5_net, - i_im_6 => i_im_6_net, - i_im_7 => i_im_7_net - ); - i_re : entity xil_defaultlib.ssr_8x8_i_re - port map ( - i_re_0 => i_re_0_net, - i_re_1 => i_re_1_net, - i_re_2 => i_re_2_net, - i_re_3 => i_re_3_net, - i_re_4 => i_re_4_net, - i_re_5 => i_re_5_net, - i_re_6 => i_re_6_net, - i_re_7 => i_re_7_net - ); -end structural; --- Generated from Simulink block -library IEEE; -use IEEE.std_logic_1164.all; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; -entity ssr_8x8_default_clock_driver is - port ( - ssr_8x8_sysclk : in std_logic; - ssr_8x8_sysce : in std_logic; - ssr_8x8_sysclr : in std_logic; - ssr_8x8_clk1 : out std_logic; - ssr_8x8_ce1 : out std_logic - ); -end ssr_8x8_default_clock_driver; -architecture structural of ssr_8x8_default_clock_driver is -begin - clockdriver : entity xil_defaultlib.xlclockdriver - generic map ( - period => 1, - log_2_period => 1 - ) - port map ( - sysclk => ssr_8x8_sysclk, - sysce => ssr_8x8_sysce, - sysclr => ssr_8x8_sysclr, - clk => ssr_8x8_clk1, - ce => ssr_8x8_ce1 - ); -end structural; --- Generated from Simulink block -library IEEE; -use IEEE.std_logic_1164.all; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; -entity ssr_8x8 is - port ( - i_scale : in std_logic_vector( 3-1 downto 0 ); - i_valid : in std_logic_vector( 1-1 downto 0 ); - i_im_0 : in std_logic_vector( 16-1 downto 0 ); - i_im_1 : in std_logic_vector( 16-1 downto 0 ); - i_im_2 : in std_logic_vector( 16-1 downto 0 ); - i_im_3 : in std_logic_vector( 16-1 downto 0 ); - i_im_4 : in std_logic_vector( 16-1 downto 0 ); - i_im_5 : in std_logic_vector( 16-1 downto 0 ); - i_im_6 : in std_logic_vector( 16-1 downto 0 ); - i_im_7 : in std_logic_vector( 16-1 downto 0 ); - i_re_0 : in std_logic_vector( 16-1 downto 0 ); - i_re_1 : in std_logic_vector( 16-1 downto 0 ); - i_re_2 : in std_logic_vector( 16-1 downto 0 ); - i_re_3 : in std_logic_vector( 16-1 downto 0 ); - i_re_4 : in std_logic_vector( 16-1 downto 0 ); - i_re_5 : in std_logic_vector( 16-1 downto 0 ); - i_re_6 : in std_logic_vector( 16-1 downto 0 ); - i_re_7 : in std_logic_vector( 16-1 downto 0 ); - clk : in std_logic; - o_scale : out std_logic_vector( 3-1 downto 0 ); - o_valid : out std_logic_vector( 1-1 downto 0 ); - o_im_0 : out std_logic_vector( 27-1 downto 0 ); - o_im_1 : out std_logic_vector( 27-1 downto 0 ); - o_im_2 : out std_logic_vector( 27-1 downto 0 ); - o_im_3 : out std_logic_vector( 27-1 downto 0 ); - o_im_4 : out std_logic_vector( 27-1 downto 0 ); - o_im_5 : out std_logic_vector( 27-1 downto 0 ); - o_im_6 : out std_logic_vector( 27-1 downto 0 ); - o_im_7 : out std_logic_vector( 27-1 downto 0 ); - o_re_0 : out std_logic_vector( 27-1 downto 0 ); - o_re_1 : out std_logic_vector( 27-1 downto 0 ); - o_re_2 : out std_logic_vector( 27-1 downto 0 ); - o_re_3 : out std_logic_vector( 27-1 downto 0 ); - o_re_4 : out std_logic_vector( 27-1 downto 0 ); - o_re_5 : out std_logic_vector( 27-1 downto 0 ); - o_re_6 : out std_logic_vector( 27-1 downto 0 ); - o_re_7 : out std_logic_vector( 27-1 downto 0 ) - ); -end ssr_8x8; -architecture structural of ssr_8x8 is - attribute core_generation_info : string; - attribute core_generation_info of structural : architecture is "ssr_8x8,sysgen_core_2019_2,{,compilation=HDL Netlist,block_icon_display=Default,family=zynquplusRFSOC,part=xczu28dr,speed=-2-e,package=ffvg1517,synthesis_language=vhdl,hdl_library=xil_defaultlib,synthesis_strategy=Vivado Synthesis Defaults,implementation_strategy=Vivado Implementation Defaults,testbench=0,interface_doc=0,ce_clr=0,clock_period=10,system_simulink_period=1,waveform_viewer=0,axilite_interface=0,ip_catalog_plugin=0,hwcosim_burst_mode=0,simulation_time=10,blackbox2=1,concat=9,delay=10,reinterpret=32,slice=24,}"; - signal ce_1_net : std_logic; - signal clk_1_net : std_logic; -begin - ssr_8x8_default_clock_driver : entity xil_defaultlib.ssr_8x8_default_clock_driver - port map ( - ssr_8x8_sysclk => clk, - ssr_8x8_sysce => '1', - ssr_8x8_sysclr => '0', - ssr_8x8_clk1 => clk_1_net, - ssr_8x8_ce1 => ce_1_net - ); - ssr_8x8_struct : entity xil_defaultlib.ssr_8x8_struct - port map ( - i_scale => i_scale, - i_valid => i_valid, - i_im_0 => i_im_0, - i_im_1 => i_im_1, - i_im_2 => i_im_2, - i_im_3 => i_im_3, - i_im_4 => i_im_4, - i_im_5 => i_im_5, - i_im_6 => i_im_6, - i_im_7 => i_im_7, - i_re_0 => i_re_0, - i_re_1 => i_re_1, - i_re_2 => i_re_2, - i_re_3 => i_re_3, - i_re_4 => i_re_4, - i_re_5 => i_re_5, - i_re_6 => i_re_6, - i_re_7 => i_re_7, - clk_1 => clk_1_net, - ce_1 => ce_1_net, - o_scale => o_scale, - o_valid => o_valid, - o_im_0 => o_im_0, - o_im_1 => o_im_1, - o_im_2 => o_im_2, - o_im_3 => o_im_3, - o_im_4 => o_im_4, - o_im_5 => o_im_5, - o_im_6 => o_im_6, - o_im_7 => o_im_7, - o_re_0 => o_re_0, - o_re_1 => o_re_1, - o_re_2 => o_re_2, - o_re_3 => o_re_3, - o_re_4 => o_re_4, - o_re_5 => o_re_5, - o_re_6 => o_re_6, - o_re_7 => o_re_7 - ); -end structural; diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/ssr_8x8_entity_declarations.vhd b/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/ssr_8x8_entity_declarations.vhd deleted file mode 100644 index 2d133a7..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/ssr_8x8_entity_declarations.vhd +++ /dev/null @@ -1,6159 +0,0 @@ -------------------------------------------------------------------- --- System Generator version 2019.2 VHDL source file. --- --- Copyright(C) 2019 by Xilinx, Inc. All rights reserved. This --- text/file contains proprietary, confidential information of Xilinx, --- Inc., is distributed under license from Xilinx, Inc., and may be used, --- copied and/or disclosed only pursuant to the terms of a valid license --- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use --- this text/file solely for design, simulation, implementation and --- creation of design files limited to Xilinx devices or technologies. --- Use with non-Xilinx devices or technologies is expressly prohibited --- and immediately terminates your license unless covered by a separate --- agreement. --- --- Xilinx is providing this design, code, or information "as is" solely --- for use in developing programs and solutions for Xilinx devices. By --- providing this design, code, or information as one possible --- implementation of this feature, application or standard, Xilinx is --- making no representation that this implementation is free from any --- claims of infringement. You are responsible for obtaining any rights --- you may require for your implementation. Xilinx expressly disclaims --- any warranty whatsoever with respect to the adequacy of the --- implementation, including but not limited to warranties of --- merchantability or fitness for a particular purpose. --- --- Xilinx products are not intended for use in life support appliances, --- devices, or systems. Use in such applications is expressly prohibited. --- --- Any modifications that are made to the source code are done at the user's --- sole risk and will be unsupported. --- --- This copyright and support notice must be retained as part of this --- text at all times. (c) Copyright 1995-2019 Xilinx, Inc. All rights --- reserved. -------------------------------------------------------------------- - -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - -library IEEE; -use IEEE.std_logic_1164.all; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - - -entity ssr_8x8_xldelay is - generic(width : integer := -1; - latency : integer := -1; - reg_retiming : integer := 0; - reset : integer := 0); - port(d : in std_logic_vector (width-1 downto 0); - ce : in std_logic; - clk : in std_logic; - en : in std_logic; - rst : in std_logic; - q : out std_logic_vector (width-1 downto 0)); - -end ssr_8x8_xldelay; - -architecture behavior of ssr_8x8_xldelay is - component synth_reg - generic (width : integer; - latency : integer); - port (i : in std_logic_vector(width-1 downto 0); - ce : in std_logic; - clr : in std_logic; - clk : in std_logic; - o : out std_logic_vector(width-1 downto 0)); - end component; -- end component synth_reg - - component synth_reg_reg - generic (width : integer; - latency : integer); - port (i : in std_logic_vector(width-1 downto 0); - ce : in std_logic; - clr : in std_logic; - clk : in std_logic; - o : out std_logic_vector(width-1 downto 0)); - end component; - - signal internal_ce : std_logic; - -begin - internal_ce <= ce and en; - - srl_delay: if ((reg_retiming = 0) and (reset = 0)) or (latency < 1) generate - synth_reg_srl_inst : synth_reg - generic map ( - width => width, - latency => latency) - port map ( - i => d, - ce => internal_ce, - clr => '0', - clk => clk, - o => q); - end generate srl_delay; - - reg_delay: if ((reg_retiming = 1) or (reset = 1)) and (latency >= 1) generate - synth_reg_reg_inst : synth_reg_reg - generic map ( - width => width, - latency => latency) - port map ( - i => d, - ce => internal_ce, - clr => rst, - clk => clk, - o => q); - end generate reg_delay; -end architecture behavior; - -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - --- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 ------------------------------------------------------------------------------------------------ --- © Copyright 2018 Xilinx, Inc. All rights reserved. --- This file contains confidential and proprietary information of Xilinx, Inc. and is --- protected under U.S. and international copyright and other intellectual property laws. ------------------------------------------------------------------------------------------------ --- --- Disclaimer: --- This disclaimer is not a license and does not grant any rights to the materials --- distributed herewith. Except as otherwise provided in a valid license issued to you --- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS --- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL --- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED --- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR --- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including --- negligence, or under any other theory of liability) for any loss or damage of any --- kind or nature related to, arising under or in connection with these materials, --- including for any direct, or any indirect, special, incidental, or consequential --- loss or damage (including loss of data, profits, goodwill, or any type of loss or --- damage suffered as a result of any action brought by a third party) even if such --- damage or loss was reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail-safe, or for use in any --- application requiring fail-safe performance, such as life-support or safety devices --- or systems, Class III medical devices, nuclear facilities, applications related to --- the deployment of airbags, or any other applications that could lead to death, --- personal injury, or severe property or environmental damage (individually and --- collectively, "Critical Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical Applications, subject only to --- applicable laws and regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. --- --- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx --- Worldwide Technical Support (WTS), for support please contact the author --- ____ ____ --- / /\/ / --- /___/ \ / Vendor: Xilinx Inc. --- \ \ \/ Version: 0.14 --- \ \ Filename: COMPLEX_FIXED_PKG.vhd --- / / Date Last Modified: 16 Apr 2018 --- /___/ /\ Date Created: --- \ \ / \ --- \___\/\___\ --- --- Device: Any UltraScale Xilinx FPGA --- Author: Catalin Baetoniu --- Package Name: COMPLEX_FIXED_PKG --- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) --- --- Revision History: --- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support --------------------------------------------------------------------------------- --- --- Module Description: Unconstrained Size Vectors and Matrices of Complex Arbitrary Precision Fixed Point Numbers --- --------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use ieee.math_real.all; -use ieee.math_complex.all; - -package COMPLEX_FIXED_PKG is - type BOOLEAN_VECTOR is array(NATURAL range <>) of BOOLEAN; - type INTEGER_VECTOR is array(NATURAL range <>) of INTEGER; - type REAL_VECTOR is array(NATURAL range <>) of REAL; ---2008 type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED; - type COMPLEX_VECTOR is array(INTEGER range <>) of COMPLEX; - - type SFIXED is array(INTEGER range <>) of STD_LOGIC; -- arbitrary precision fixed point signed number, like SIGNED but lower bound can be negative ---2008 type SFIXED_VECTOR is array(INTEGER range <>) of SFIXED; -- unconstrained array of SFIXED ---2008 type CFIXED is record RE,IM:SFIXED; end record; -- arbitrary precision fixed point complex signed number ---2008 type CFIXED_VECTOR is array(INTEGER range <>) of CFIXED; -- unconstrained array of CFIXED ---2008 type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR; -- unconstrained array of CFIXED_VECTOR - type SFIXED_VECTOR is array(INTEGER range <>) of STD_LOGIC; -- unconstrained array of SFIXED, vector size must be given by a separate generic - type CFIXED is array(INTEGER range <>) of STD_LOGIC; -- arbitrary precision fixed point complex signed number, CFIXED'low is always even and CFIXED'high is always odd - type CFIXED_VECTOR is array(INTEGER range <>) of STD_LOGIC; -- unconstrained array of CFIXED, vector size must be given by a separate generic - --- function ELEMENT(X:CFIXED;K,N:INTEGER) return CFIXED; -- returns the CFIXED range for X(K) --- function RE(X:CFIXED;K,N:INTEGER) return SFIXED; -- returns the CFIXED range for X(K).RE --- function IM(X:CFIXED;K,N:INTEGER) return SFIXED; -- returns the CFIXED range for X(K).IM - - function MIN(A,B:INTEGER) return INTEGER; - function MIN(A,B,C:INTEGER) return INTEGER; - function MIN(A,B,C,D:INTEGER) return INTEGER; - function MED(A,B,C:INTEGER) return INTEGER; - function MAX(A,B:INTEGER) return INTEGER; - function MAX(A,B,C:INTEGER) return INTEGER; - function MAX(A,B,C,D:INTEGER) return INTEGER; - function "+"(X,Y:SFIXED) return SFIXED; -- full precision add with SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)) result - function "-"(X,Y:SFIXED) return SFIXED; -- full precision subtract with SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)) result - function "-"(X:SFIXED) return SFIXED; -- full precision negate with SFIXED(X'high+1 downto X'low) result - function "*"(X,Y:SFIXED) return SFIXED; -- full precision multiply with SFIXED(X'high+Y'high+1 downto X'low+Y'low) result - function "*"(X:SFIXED;Y:STD_LOGIC) return SFIXED; -- multiply by 0 or 1 with SFIXED(X'high downto X'low) result - function RESIZE(X:SFIXED;H,L:INTEGER) return SFIXED; -- resizes X and returns SFIXED(H downto L) - function RESIZE(X:SFIXED;HL:SFIXED) return SFIXED; -- resizes X to match HL and returns SFIXED(HL'high downto HL'low) - function SHIFT_RIGHT(X:SFIXED;N:INTEGER) return SFIXED; -- returns SFIXED(X'high-N downto X'low-N) result - function SHIFT_LEFT(X:SFIXED;N:INTEGER) return SFIXED; -- returns SFIXED(X'high+N downto X'low+N) result - function TO_SFIXED(R:REAL;H,L:INTEGER) return SFIXED; -- returns SFIXED(H downto L) result - function TO_SFIXED(R:REAL;HL:SFIXED) return SFIXED; -- returns SFIXED(HL'high downto HL'low) result - function TO_REAL(S:SFIXED) return REAL; -- returns REAL result --- function ELEMENT(X:SFIXED_VECTOR;K,N:INTEGER) return SFIXED; -- returns element K out of an N-size array X - - function RE(X:CFIXED) return SFIXED; -- returns SFIXED(X'high/2 downto X'low/2) result --- procedure vRE(X:out CFIXED;S:SFIXED); -- use when X is a variable, X'low is always even and X'high is always odd --- procedure RE(signal X:out CFIXED;S:SFIXED); -- use when X is a signal, X'low is always even and X'high is always odd - function IM(X:CFIXED) return SFIXED; -- returns SFIXED(X'high/2 downto X'low/2) result --- procedure vIM(X:out CFIXED;S:SFIXED); -- use when X is a variable, X'low is always even and X'high is always odd --- procedure IM(signal X:out CFIXED;S:SFIXED); -- use when X is a signal, X'low is always even and X'high is always odd - function "+"(X,Y:CFIXED) return CFIXED; -- full precision add with CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result - function "-"(X,Y:CFIXED) return CFIXED; -- full precision subtract with CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result - function "*"(X,Y:CFIXED) return CFIXED; -- full precision multiply with CFIXED(X'high+Y'high+2 downto X'low+Y'low) result - function "*"(X:CFIXED;Y:SFIXED) return CFIXED; -- full precision multiply with CFIXED(X'high+Y'high downto X'low+Y'low) result - function "*"(X:SFIXED;Y:CFIXED) return CFIXED; - function RESIZE(X:CFIXED;H,L:INTEGER) return CFIXED; -- resizes X and returns CFIXED(H downto L) - function RESIZE(X:CFIXED;HL:CFIXED) return CFIXED; -- resizes X to match HL and returns CFIXED(HL'high downto HL'low) - function PLUS_i_TIMES(X:CFIXED) return CFIXED; -- returns CFIXED(X'high+2 downto X'low) result - function "-"(X:CFIXED) return CFIXED; -- full precision negate with CFIXED(X'high+2 downto X'low) result - function MINUS_i_TIMES(X:CFIXED) return CFIXED; -- returns CFIXED(X'high+2 downto X'low) result - function X_PLUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED; -- returns CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result - function X_MINUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED; -- returns CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result - function SWAP(X:CFIXED) return CFIXED; -- returns CFIXED(X'high downto X'low) result - function CONJ(X:CFIXED) return CFIXED; -- returns CFIXED(X'high+2 downto X'low) result - function SHIFT_RIGHT(X:CFIXED;N:INTEGER) return CFIXED; -- returns CFIXED(X'high-N downto X'low-N) result - function SHIFT_LEFT(X:CFIXED;N:INTEGER) return CFIXED; -- returns CFIXED(X'high+N downto X'low+N) result - function TO_CFIXED(R,I:REAL;H,L:INTEGER) return CFIXED; -- returns CFIXED(H downto L) result - function TO_CFIXED(R,I:REAL;HL:CFIXED) return CFIXED; -- returns CFIXED(HL'high downto HL'low) result - function TO_CFIXED(C:COMPLEX;HL:CFIXED) return CFIXED; -- returns CFIXED(RE(HL.RE'high downto HL.RE'low),IM(RE(HL.IM'high downto HL.IM'low)) result - function TO_CFIXED(R,I:SFIXED) return CFIXED; -- returns CFIXED(2*MAX(R'high,I'high)+1 downto 2*MIN(R'low,I'low)) result - function TO_COMPLEX(C:CFIXED) return COMPLEX; -- returns COMPLEX result - function TO_CFIXED_VECTOR(C:COMPLEX_VECTOR;HL:CFIXED) return CFIXED_VECTOR; -- returns CFIXED_VECTOR(RE(HL.RE'high downto HL.RE'low),IM(RE(HL.IM'high downto HL.IM'low)) result - function TO_COMPLEX_VECTOR(C:CFIXED_VECTOR;N:INTEGER) return COMPLEX_VECTOR; -- returns COMPLEX_VECTOR result - function "*"(R:REAL;C:COMPLEX_VECTOR) return COMPLEX_VECTOR; -- returns R*C - - function ELEMENT(X:CFIXED_VECTOR;K,N:INTEGER) return CFIXED; -- returns element K out of an N-size array X - procedure vELEMENT(X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED); -- use when X is a variable, set element K out of an N-size array X to C - procedure ELEMENT(signal X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED); -- use when X is a signal, set element K out of an N-size array X to C - - function LOG2(N:INTEGER) return INTEGER; -- returns ceil(log2(N)) -end COMPLEX_FIXED_PKG; - -package body COMPLEX_FIXED_PKG is --- function ELEMENT(X:CFIXED;K,N:INTEGER) return CFIXED is -- returns the CFIXED range for X(K) --- variable O:CFIXED(X'length/N*(K+1)-1+X'low/N downto X'length/N*K+X'low/N); --- begin --- return O; --- end; - --- function RE(X:CFIXED;K,N:INTEGER) return SFIXED is -- returns the CFIXED range for X(K).RE --- begin --- return RE(ELEMENT(X,K,N)); --- end; - --- function IM(X:CFIXED;K,N:INTEGER) return SFIXED is -- returns the CFIXED range for X(K).IM --- begin --- return IM(ELEMENT(X,K,N)); --- end; - - function MIN(A,B:INTEGER) return INTEGER is - begin - if AB then - return A; - else - return B; - end if; - end; - - function MAX(A,B,C:INTEGER) return INTEGER is - begin - return MAX(MAX(A,B),C); - end; - - function MAX(A,B,C,D:INTEGER) return INTEGER is - begin - return MAX(MAX(A,B),MAX(C,D)); - end; - - function "+"(X,Y:SFIXED) return SFIXED is - variable SX,SY,SR:SIGNED(MAX(X'high,Y'high)+1-MIN(X'low,Y'low) downto 0); - variable R:SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)); - begin - for K in SX'range loop - if KX'high-R'low then - SX(K):=X(X'high); -- sign extend X MSBs - else - SX(K):=X(R'low+K); - end if; - end loop; - for K in SY'range loop - if KY'high-R'low then - SY(K):=Y(Y'high); -- sign extend Y MSBs - else - SY(K):=Y(R'low+K); - end if; - end loop; - SR:=SX+SY; -- SIGNED addition - for K in SR'range loop - R(R'low+K):=SR(K); - end loop; - return R; - end; - - function "-"(X,Y:SFIXED) return SFIXED is - variable SX,SY,SR:SIGNED(MAX(X'high,Y'high)+1-MIN(X'low,Y'low) downto 0); - variable R:SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)); - begin - for K in SX'range loop - if KX'high-R'low then - SX(K):=X(X'high); -- sign extend X MSBs - else - SX(K):=X(R'low+K); - end if; - end loop; - for K in SY'range loop - if KY'high-R'low then - SY(K):=Y(Y'high); -- sign extend Y MSBs - else - SY(K):=Y(R'low+K); - end if; - end loop; - SR:=SX-SY; -- SIGNED subtraction - for K in SR'range loop - R(R'low+K):=SR(K); - end loop; - return R; - end; - - function "-"(X:SFIXED) return SFIXED is - variable SX:SIGNED(X'high-X'low downto 0); - variable SR:SIGNED(X'high-X'low+1 downto 0); - variable R:SFIXED(X'high+1 downto X'low); - begin - for K in SX'range loop - SX(K):=X(X'low+K); - end loop; - SR:=-RESIZE(SX,SR'length); -- SIGNED negation - for K in SR'range loop - R(R'low+K):=SR(K); - end loop; - return R; - end; - - function "*"(X,Y:SFIXED) return SFIXED is - variable SX:SIGNED(X'high-X'low downto 0); - variable SY:SIGNED(Y'high-Y'low downto 0); - variable SR:SIGNED(SX'high+SY'high+1 downto 0); - variable R:SFIXED(X'high+Y'high+1 downto X'low+Y'low); - begin - for K in SX'range loop - SX(K):=X(X'low+K); - end loop; - for K in SY'range loop - SY(K):=Y(Y'low+K); - end loop; - SR:=SX*SY; -- SIGNED multiplication - for K in SR'range loop - R(R'low+K):=SR(K); - end loop; - return R; - end; - - function "*"(X:SFIXED;Y:STD_LOGIC) return SFIXED is - begin - if Y='1' then - return X; - else - return TO_SFIXED(0.0,X); - end if; - end; - - function RESIZE(X:SFIXED;H,L:INTEGER) return SFIXED is - variable R:SFIXED(H downto L); - begin - for K in R'range loop - if KX'high then - R(K):=X(X'high); -- sign extend X MSBs - else - R(K):=X(K); - end if; - end loop; - return R; - end; - - function RESIZE(X:SFIXED;HL:SFIXED) return SFIXED is - begin - return RESIZE(X,HL'high,HL'low); - end; - - function SHIFT_RIGHT(X:SFIXED;N:INTEGER) return SFIXED is - variable R:SFIXED(X'high-N downto X'low-N); - begin - for K in R'range loop - R(K):=X(K+N); - end loop; - return R; - end; - - function SHIFT_LEFT(X:SFIXED;N:INTEGER) return SFIXED is - variable R:SFIXED(X'high+N downto X'low+N); - begin - for K in R'range loop - R(K):=X(K-N); - end loop; - return R; - end; - - function TO_SFIXED(R:REAL;H,L:INTEGER) return SFIXED is - variable RR:REAL; - variable V:SFIXED(H downto L); - begin - assert (R<2.0**H) and (R>=-2.0**H) report "TO_SFIXED vector truncation!" severity warning; - if R<0.0 then - V(V'high):='1'; - RR:=R+2.0**V'high; - else - V(V'high):='0'; - RR:=R; - end if; - for K in V'high-1 downto V'low loop - if RR>=2.0**K then - V(K):='1'; - RR:=RR-2.0**K; - else - V(K):='0'; - end if; - end loop; - return V; - end; - - function TO_SFIXED(R:REAL;HL:SFIXED) return SFIXED is - begin - return TO_SFIXED(R,HL'high,HL'low); - end; - - function TO_REAL(S:SFIXED) return REAL is - variable R:REAL; - begin - R:=0.0; - for K in S'range loop - if K=S'high then - if S(K)='1' then - R:=R-2.0**K; - end if; - else - if S(K)='1' then - R:=R+2.0**K; - end if; - end if; - end loop; - return R; - end; - --- function ELEMENT(X:SFIXED_VECTOR;K,N:INTEGER) return SFIXED is -- X'low and X'length are always multiples of N --- variable R:SFIXED(X'length/N-1+X'low/N downto X'low/N); --- begin --- R:=SFIXED(X((K+1)*R'length-1+X'low downto K*R'length+X'low)); --- return R; -- element K out of N of X --- end; - - function RE(X:CFIXED) return SFIXED is -- X'low is always even and X'high is always odd - variable R:SFIXED((X'high+1)/2-1 downto X'low/2); - begin - R:=SFIXED(X(R'length-1+X'low downto X'low)); - return R; --lower half of X - end; - --- procedure vRE(X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd --- begin --- X(S'length-1+X'low downto X'low):=CFIXED(S); -- set lower half of X --- end; - --- procedure RE(signal X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd --- begin --- X(S'length-1+X'low downto X'low)<=CFIXED(S); -- set lower half of X --- end; - - function IM(X:CFIXED) return SFIXED is -- X'low is always even and X'high is always odd - variable R:SFIXED((X'high+1)/2-1 downto X'low/2); - begin - R:=SFIXED(X(X'high downto R'length+X'low)); - return R; --upper half of X - end; - --- procedure vIM(X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd --- begin --- X(X'high downto S'length+X'low):=CFIXED(S); -- set upper half of X --- end; - --- procedure IM(signal X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd --- begin --- X(X'high downto S'length+X'low)<=CFIXED(S); -- set upper half of X --- end; - - function "+"(X,Y:CFIXED) return CFIXED is - begin - return TO_CFIXED(RE(X)+RE(Y),IM(X)+IM(Y)); - end; - - function "-"(X,Y:CFIXED) return CFIXED is - begin - return TO_CFIXED(RE(X)-RE(Y),IM(X)-IM(Y)); - end; - - function "*"(X,Y:CFIXED) return CFIXED is - begin - return TO_CFIXED(RE(X)*RE(Y)-IM(X)*IM(Y),RE(X)*IM(Y)+IM(X)*RE(Y)); - end; - - function "*"(X:CFIXED;Y:SFIXED) return CFIXED is - begin - return TO_CFIXED(RE(X)*Y,IM(X)*Y); - end; - - function "*"(X:SFIXED;Y:CFIXED) return CFIXED is - begin - return TO_CFIXED(X*RE(Y),X*IM(Y)); - end; - - function RESIZE(X:CFIXED;H,L:INTEGER) return CFIXED is - begin - return TO_CFIXED(RESIZE(RE(X),H,L),RESIZE(IM(X),H,L)); - end; - - function RESIZE(X:CFIXED;HL:CFIXED) return CFIXED is - begin - return RESIZE(X,HL'high/2,HL'low/2); - end; - - function PLUS_i_TIMES(X:CFIXED) return CFIXED is - begin - return TO_CFIXED(-IM(X),RE(X)); - end; - - function "-"(X:CFIXED) return CFIXED is - begin - return TO_CFIXED(-RE(X),-IM(X)); - end; - - function MINUS_i_TIMES(X:CFIXED) return CFIXED is - begin - return TO_CFIXED(IM(X),-RE(X)); - end; - - function X_PLUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED is - begin - return TO_CFIXED(RE(X)-IM(Y)+RE(RND),IM(X)+RE(Y)+IM(RND)); - end; - - function X_MINUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED is - begin - return TO_CFIXED(RE(X)+IM(Y)+RE(RND),IM(X)-RE(Y)+IM(RND)); - end; - - function SWAP(X:CFIXED) return CFIXED is - begin - return TO_CFIXED(IM(X),RE(X)); - end; - - function CONJ(X:CFIXED) return CFIXED is - begin - return TO_CFIXED(RE(X),-IM(X)); - end; - - function SHIFT_RIGHT(X:CFIXED;N:INTEGER) return CFIXED is - begin - return TO_CFIXED(SHIFT_RIGHT(RE(X),N),SHIFT_RIGHT(IM(X),N)); - end; - - function SHIFT_LEFT(X:CFIXED;N:INTEGER) return CFIXED is - begin - return TO_CFIXED(SHIFT_LEFT(RE(X),N),SHIFT_LEFT(IM(X),N)); - end; - - function TO_CFIXED(R,I:REAL;H,L:INTEGER) return CFIXED is - begin - return TO_CFIXED(TO_SFIXED(R,H,L),TO_SFIXED(I,H,L)); - end; - - function TO_CFIXED(R,I:REAL;HL:CFIXED) return CFIXED is - begin - return TO_CFIXED(R,I,HL'high/2,HL'low/2); - end; - - function TO_CFIXED(C:COMPLEX;HL:CFIXED) return CFIXED is - begin - return TO_CFIXED(C.RE,C.IM,HL); - end; - - function TO_CFIXED(R,I:SFIXED) return CFIXED is - constant H:INTEGER:=MAX(R'high,I'high); - constant L:INTEGER:=MIN(R'low,I'low); - variable C:CFIXED(2*H+1 downto 2*L); - begin - C:=CFIXED(RESIZE(I,H,L))&CFIXED(RESIZE(R,H,L)); - return C; -- I&R - end; - - function ELEMENT(X:CFIXED_VECTOR;K,N:INTEGER) return CFIXED is -- X'low and X'length are always multiples of N - variable R:CFIXED(X'length/N-1+X'low/N downto X'low/N); - begin - R:=CFIXED(X((K+1)*R'length-1+X'low downto K*R'length+X'low)); - return R; -- element K out of N of X - end; - - procedure vELEMENT(X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED) is -- X'low and X'length are always multiples of N - begin - X((K+1)*C'length-1+X'low downto K*C'length+X'low):=CFIXED_VECTOR(C); -- element K out of N of X - end; - - procedure ELEMENT(signal X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED) is -- X'low and X'length are always multiples of N - begin - X((K+1)*C'length-1+X'low downto K*C'length+X'low)<=CFIXED_VECTOR(C); -- element K out of N of X - end; - - function TO_COMPLEX(C:CFIXED) return COMPLEX is - variable R:COMPLEX; - begin - R.RE:=TO_REAL(RE(C)); - R.IM:=TO_REAL(IM(C)); - return R; - end; - - function TO_CFIXED_VECTOR(C:COMPLEX_VECTOR;HL:CFIXED) return CFIXED_VECTOR is - variable R:CFIXED_VECTOR(C'length*(HL'high+1)-1 downto C'length*HL'low); - begin - for K in C'range loop - R((K-C'low+1)*HL'length-1+R'low downto (K-C'low)*HL'length+R'low):=CFIXED_VECTOR(TO_CFIXED(C(K),HL)); - end loop; - return R; - end; - - function TO_COMPLEX_VECTOR(C:CFIXED_VECTOR;N:INTEGER) return COMPLEX_VECTOR is - variable R:COMPLEX_VECTOR(0 to N-1); - begin - for K in 0 to N-1 loop - R(K):=TO_COMPLEX(ELEMENT(C,K,N)); - end loop; - return R; - end; - - function "*"(R:REAL;C:COMPLEX_VECTOR) return COMPLEX_VECTOR is - variable X:COMPLEX_VECTOR(C'range); - begin - for K in C'range loop - X(K):=R*C(K); - end loop; - return X; - end; - - function LOG2(N:INTEGER) return INTEGER is - variable TEMP:INTEGER; - variable RESULT:INTEGER; - begin - TEMP:=N; - RESULT:=0; - while TEMP>1 loop - RESULT:=RESULT+1; - TEMP:=(TEMP+1)/2; - end loop; - return RESULT; - end; -end COMPLEX_FIXED_PKG; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - --- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 ------------------------------------------------------------------------------------------------ --- ? Copyright 2018 Xilinx, Inc. All rights reserved. --- This file contains confidential and proprietary information of Xilinx, Inc. and is --- protected under U.S. and international copyright and other intellectual property laws. ------------------------------------------------------------------------------------------------ --- --- Disclaimer: --- This disclaimer is not a license and does not grant any rights to the materials --- distributed herewith. Except as otherwise provided in a valid license issued to you --- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS --- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL --- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED --- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR --- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including --- negligence, or under any other theory of liability) for any loss or damage of any --- kind or nature related to, arising under or in connection with these materials, --- including for any direct, or any indirect, special, incidental, or consequential --- loss or damage (including loss of data, profits, goodwill, or any type of loss or --- damage suffered as a result of any action brought by a third party) even if such --- damage or loss was reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail-safe, or for use in any --- application requiring fail-safe performance, such as life-support or safety devices --- or systems, Class III medical devices, nuclear facilities, applications related to --- the deployment of airbags, or any other applications that could lead to death, --- personal injury, or severe property or environmental damage (individually and --- collectively, "Critical Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical Applications, subject only to --- applicable laws and regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. --- --- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx --- Worldwide Technical Support (WTS), for support please contact the author --- ____ ____ --- / /\/ / --- /___/ \ / Vendor: Xilinx Inc. --- \ \ \/ Version: 0.14 --- \ \ Filename: BDELAY.vhd --- / / Date Last Modified: 16 Apr 2018 --- /___/ /\ Date Created: --- \ \ / \ --- \___\/\___\ --- --- Device: Any UltraScale Xilinx FPGA --- Author: Catalin Baetoniu --- Entity Name: BDELAY --- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) --- --- Revision History: --- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support --------------------------------------------------------------------------------- --- --- Module Description: Generic BOOLEAN Delay Module --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.NUMERIC_STD.all; - -use work.COMPLEX_FIXED_PKG.all; - -library UNISIM; -use UNISIM.VComponents.all; - -entity BDELAY is - generic(SIZE:INTEGER:=1; - BRAM_THRESHOLD:INTEGER:=258); - port(CLK:in STD_LOGIC; - I:in BOOLEAN; - O:out BOOLEAN); -end BDELAY; - -architecture TEST of BDELAY is - attribute rloc:STRING; - - component BDELAY - generic(SIZE:INTEGER:=1); - port(CLK:in STD_LOGIC; - I:in BOOLEAN; - O:out BOOLEAN); - end component; - -begin - l0:if SIZE=0 generate - begin - O<=I; - end generate l0; - -- end; - - l1:if SIZE=1 generate - signal iO:BOOLEAN:=FALSE; - begin - process(CLK) - begin - if rising_edge(CLK) then - iO<=I; - end if; - end process; - O<=iO; - end generate l1; - -- end; - - l17: if SIZE>=2 and SIZE<18 generate - signal A:UNSIGNED(3 downto 0); - signal D,Q:STD_LOGIC; - signal RQ:STD_LOGIC:='0'; - --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); - begin - A<=TO_UNSIGNED(SIZE-2,A'length); - D<='1' when I else '0'; - sr:SRL16E port map(CLK=>CLK, - CE=>'1', - A0=>A(0), - A1=>A(1), - A2=>A(2), - A3=>A(3), - D=>D, - Q=>Q); - process(CLK) - begin - if rising_edge(CLK) then - RQ<=Q; - end if; - end process; - O<=RQ='1'; - end generate l17; - -- end; - - l33: if SIZE>=18 and SIZE<34 generate --- signal MEM:UFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); - signal A:UNSIGNED(LOG2(SIZE-1)-1 downto 0):=(others=>'0'); --- attribute ram_style:STRING; --- attribute ram_style of MEM:signal is "distributed"; - signal D,Q:STD_LOGIC; - signal RQ:STD_LOGIC:='0'; - begin - process(CLK) - begin - if rising_edge(CLK) then - if A=SIZE-2 then - A<=(others=>'0'); - else - A<=A+1; - end if; --- MEM(TO_INTEGER(A))<=I; --- O<=MEM(TO_INTEGER(A)); - end if; - end process; --- O<=RESIZE(iO,O); - D<='1' when I else '0'; - rs:RAM32X1S port map(A0=>A(0), - A1=>A(1), - A2=>A(2), - A3=>A(3), - A4=>A(4), - D=>D, - WCLK=>CLK, - WE=>'1', - O=>Q); - process(CLK) - begin - if rising_edge(CLK) then - RQ<=Q; - end if; - end process; - O<=RQ='1'; - end generate l33; - -- end; - - l257: if SIZE>=34 and SIZE33, - BRAM_THRESHOLD=>BRAM_THRESHOLD) - port map(CLK=>CLK, - I=>I, - O=>iO); - hd:entity work.BDELAY generic map(SIZE=>SIZE-33, - BRAM_THRESHOLD=>BRAM_THRESHOLD) - port map(CLK=>CLK, - I=>iO, - O=>O); - -- end; - end generate l257; - - ln: if SIZE>=BRAM_THRESHOLD generate --- signal MEM:UNSIGNED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); - type TUV is array(0 to SIZE-3) of UNSIGNED(0 downto 0); ---2008 signal MEM:UNSIGNED_VECTOR(0 to SIZE-3)(0 downto 0):=(others=>(others=>'0')); - signal MEM:TUV:=(others=>(others=>'0')); - signal RA,WA:UNSIGNED(LOG2(SIZE-2)-1 downto 0):=(others=>'0'); - signal iO1E,iO:UNSIGNED(0 downto 0):=(others=>'0'); - signal D,Q:UNSIGNED(0 downto 0); - attribute ram_style:STRING; - attribute ram_style of MEM:signal is "block"; - begin - D<="1" when I else "0"; - process(CLK) - begin - if rising_edge(CLK) then --- if RA=SIZE-2 then - if RA=SIZE-3 then - RA<=(others=>'0'); - else - RA<=RA+1; - end if; - WA<=RA; - MEM(TO_INTEGER(WA))<=D; --- iO<=MEM(TO_INTEGER(RA)); - iO1E<=MEM(TO_INTEGER(RA)); - iO<=iO1E; - O<=iO="1"; - end if; - end process; - -- end; - end generate; -end TEST; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - --- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 ------------------------------------------------------------------------------------------------ --- Copyright 2018 Xilinx, Inc. All rights reserved. --- This file contains confidential and proprietary information of Xilinx, Inc. and is --- protected under U.S. and international copyright and other intellectual property laws. ------------------------------------------------------------------------------------------------ --- --- Disclaimer: --- This disclaimer is not a license and does not grant any rights to the materials --- distributed herewith. Except as otherwise provided in a valid license issued to you --- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS --- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL --- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED --- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR --- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including --- negligence, or under any other theory of liability) for any loss or damage of any --- kind or nature related to, arising under or in connection with these materials, --- including for any direct, or any indirect, special, incidental, or consequential --- loss or damage (including loss of data, profits, goodwill, or any type of loss or --- damage suffered as a result of any action brought by a third party) even if such --- damage or loss was reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail-safe, or for use in any --- application requiring fail-safe performance, such as life-support or safety devices --- or systems, Class III medical devices, nuclear facilities, applications related to --- the deployment of airbags, or any other applications that could lead to death, --- personal injury, or severe property or environmental damage (individually and --- collectively, "Critical Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical Applications, subject only to --- applicable laws and regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. --- --- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx --- Worldwide Technical Support (WTS), for support please contact the author --- ____ ____ --- / /\/ / --- /___/ \ / Vendor: Xilinx Inc. --- \ \ \/ Version: 0.14 --- \ \ Filename: UDELAY.vhd --- / / Date Last Modified: 16 Apr 2018 --- /___/ /\ Date Created: --- \ \ / \ --- \___\/\___\ --- --- Device: Any UltraScale Xilinx FPGA --- Author: Catalin Baetoniu --- Entity Name: UDELAY --- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) --- --- Revision History: --- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support --------------------------------------------------------------------------------- --- --- Module Description: Generic UNSIGNED Delay Module --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.NUMERIC_STD.ALL; - -use work.COMPLEX_FIXED_PKG.all; - -library UNISIM; -use UNISIM.VComponents.all; - -entity UDELAY is - generic(SIZE:INTEGER:=1; - BRAM_THRESHOLD:INTEGER:=258); - port(CLK:in STD_LOGIC; - I:in UNSIGNED; - O:out UNSIGNED); -end UDELAY; - -architecture TEST of UDELAY is - attribute syn_hier:STRING; - attribute syn_hier of all:architecture is "hard"; - attribute rloc:STRING; -begin - assert I'length=O'length report "Ports I and O must have the same length" severity error; - - l0:if SIZE=0 generate - begin - O<=I; --- end; - end generate; --- elsif l1: SIZE=1 generate - l1:if SIZE=1 generate - signal iO:UNSIGNED(O'range):=(others=>'0'); - begin - process(CLK) - begin - if rising_edge(CLK) then - iO<=I; - end if; - end process; - O<=iO; --- end; - end generate; --- elsif l17: SIZE>=2 and SIZE<18 generate - l17:if SIZE>=2 and SIZE<18 generate - lk:for K in 0 to O'length-1 generate - signal A:UNSIGNED(3 downto 0); - signal Q:STD_LOGIC; - signal RQ:STD_LOGIC:='0'; - --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); - begin - A<=TO_UNSIGNED(SIZE-2,A'length); - sr:SRL16E port map(CLK=>CLK, - CE=>'1', - A0=>A(0), - A1=>A(1), - A2=>A(2), - A3=>A(3), - D=>I(I'low+K), - Q=>Q); - process(CLK) - begin - if rising_edge(CLK) then - RQ<=Q; - end if; - end process; - O(O'low+K)<=RQ; - end generate; --- end; - end generate; --- elsif l33: SIZE>=18 and SIZE<34 generate - l33:if SIZE>=18 and SIZE<34 generate --- signal MEM:UFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); - signal A:UNSIGNED(LOG2(SIZE-1)-1 downto 0):=(others=>'0'); --- attribute ram_style:STRING; --- attribute ram_style of MEM:signal is "distributed"; - begin - process(CLK) - begin - if rising_edge(CLK) then - if A=SIZE-2 then - A<=(others=>'0'); - else - A<=A+1; - end if; --- MEM(TO_INTEGER(A))<=I; --- O<=MEM(TO_INTEGER(A)); - end if; - end process; --- O<=RESIZE(iO,O); - lk:for K in 0 to I'length-1 generate - signal Q:STD_LOGIC; - signal RQ:STD_LOGIC:='0'; - --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); - begin - rs:RAM32X1S port map(A0=>A(0), - A1=>A(1), - A2=>A(2), - A3=>A(3), - A4=>A(4), - D=>I(I'low+K), - WCLK=>CLK, - WE=>'1', - O=>Q); - process(CLK) - begin - if rising_edge(CLK) then - RQ<=Q; - end if; - end process; - O(O'low+K)<=RQ; - end generate; --- end; - end generate; --- elsif l257: SIZE>=34 and SIZE=34 and SIZE33, - BRAM_THRESHOLD=>BRAM_THRESHOLD) - port map(CLK=>CLK, - I=>I, - O=>iO); - hd:entity work.UDELAY generic map(SIZE=>SIZE-33, - BRAM_THRESHOLD=>BRAM_THRESHOLD) - port map(CLK=>CLK, - I=>iO, - O=>O); --- end; - end generate; --- elsif ln: SIZE>=BRAM_THRESHOLD generate - ln:if SIZE>=BRAM_THRESHOLD generate --- signal MEM:UNSIGNED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); ---2008 signal MEM:UNSIGNED_VECTOR(0 to SIZE-3)(I'range):=(others=>(others=>'0')); - type TMEM is array(0 to SIZE-3) of UNSIGNED(I'range); - signal MEM:TMEM:=(others=>(others=>'0')); - signal RA,WA:UNSIGNED(LOG2(SIZE-2)-1 downto 0):=(others=>'0'); - signal iO1E,iO:UNSIGNED(I'range):=(others=>'0'); - attribute ram_style:STRING; - attribute ram_style of MEM:signal is "block"; - begin - process(CLK) - begin - if rising_edge(CLK) then --- if RA=SIZE-2 then - if RA=SIZE-3 then - RA<=(others=>'0'); - else - RA<=RA+1; - end if; - WA<=RA; - MEM(TO_INTEGER(WA))<=I; --- iO<=MEM(TO_INTEGER(RA)); - iO1E<=MEM(TO_INTEGER(RA)); - iO<=iO1E; - O<=iO; - end if; - end process; --- end; - end generate; -end TEST; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - --- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 ------------------------------------------------------------------------------------------------ --- Copyright 2018 Xilinx, Inc. All rights reserved. --- This file contains confidential and proprietary information of Xilinx, Inc. and is --- protected under U.S. and international copyright and other intellectual property laws. ------------------------------------------------------------------------------------------------ --- --- Disclaimer: --- This disclaimer is not a license and does not grant any rights to the materials --- distributed herewith. Except as otherwise provided in a valid license issued to you --- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS --- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL --- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED --- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR --- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including --- negligence, or under any other theory of liability) for any loss or damage of any --- kind or nature related to, arising under or in connection with these materials, --- including for any direct, or any indirect, special, incidental, or consequential --- loss or damage (including loss of data, profits, goodwill, or any type of loss or --- damage suffered as a result of any action brought by a third party) even if such --- damage or loss was reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail-safe, or for use in any --- application requiring fail-safe performance, such as life-support or safety devices --- or systems, Class III medical devices, nuclear facilities, applications related to --- the deployment of airbags, or any other applications that could lead to death, --- personal injury, or severe property or environmental damage (individually and --- collectively, "Critical Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical Applications, subject only to --- applicable laws and regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. --- --- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx --- Worldwide Technical Support (WTS), for support please contact the author --- ____ ____ --- / /\/ / --- /___/ \ / Vendor: Xilinx Inc. --- \ \ \/ Version: 0.14 --- \ \ Filename: SDELAY.vhd --- / / Date Last Modified: 16 Apr 2018 --- /___/ /\ Date Created: --- \ \ / \ --- \___\/\___\ --- --- Device: Any UltraScale Xilinx FPGA --- Author: Catalin Baetoniu --- Entity Name: SDELAY --- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) --- --- Revision History: --- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support --------------------------------------------------------------------------------- --- --- Module Description: Generic SFIXED Delay Module --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.NUMERIC_STD.ALL; - -use work.COMPLEX_FIXED_PKG.all; - -library UNISIM; -use UNISIM.VComponents.all; - -entity SDELAY is - generic(SIZE:INTEGER:=1; - BRAM_THRESHOLD:INTEGER:=258); - port(CLK:in STD_LOGIC; - I:in SFIXED; - O:out SFIXED); -end SDELAY; - -architecture TEST of SDELAY is - attribute syn_hier:STRING; - attribute syn_hier of all:architecture is "hard"; - attribute rloc:STRING; -begin --- assert I'length=O'length report "Ports I and O must have the same length" severity error; - - l0:if SIZE=0 generate - begin - O<=RESIZE(I,O'high,O'low); - end generate l0; - --end; - - l1:if SIZE=1 generate - signal iO:SFIXED(O'range):=(others=>'0'); - begin - process(CLK) - begin - if rising_edge(CLK) then - iO<=RESIZE(I,iO); - end if; - end process; - O<=iO; - end generate l1; - --end; - - l17:if SIZE>=2 and SIZE<18 generate --- signal iO:SFIXED(I'range):=(others=>'0'); - signal iO:SFIXED(I'range); - begin - lk:for K in 0 to I'length-1 generate - signal A:UNSIGNED(3 downto 0); - signal Q:STD_LOGIC; - signal RQ:STD_LOGIC:='0'; - --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); - begin - A<=TO_UNSIGNED(SIZE-2,A'length); - sr:SRL16E port map(CLK=>CLK, - CE=>'1', - A0=>A(0), - A1=>A(1), - A2=>A(2), - A3=>A(3), - D=>I(I'low+K), - Q=>Q); - process(CLK) - begin - if rising_edge(CLK) then - RQ<=Q; - end if; - end process; - iO(iO'low+K)<=RQ; - end generate; - O<=RESIZE(iO,O'high,O'low); - end generate l17; - --end; - - l33:if SIZE>=18 and SIZE<34 generate --- signal MEM:SFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); - signal A:UNSIGNED(LOG2(SIZE-1)-1 downto 0):=(others=>'0'); --- signal iO:SFIXED(I'range):=(others=>'0'); - signal iO:SFIXED(I'range); --- attribute ram_style:STRING; --- attribute ram_style of MEM:signal is "distributed"; - begin - process(CLK) - begin - if rising_edge(CLK) then - if A=SIZE-2 then - A<=(others=>'0'); - else - A<=A+1; - end if; --- MEM(TO_INTEGER(A))<=I; --- iO<=MEM(TO_INTEGER(A)); - end if; - end process; --- O<=RESIZE(iO,O); - lk:for K in 0 to I'length-1 generate - signal Q:STD_LOGIC; - signal RQ:STD_LOGIC:='0'; - --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); - begin - rs:RAM32X1S port map(A0=>A(0), - A1=>A(1), - A2=>A(2), - A3=>A(3), - A4=>A(4), - D=>I(I'low+K), - WCLK=>CLK, - WE=>'1', - O=>Q); - process(CLK) - begin - if rising_edge(CLK) then - RQ<=Q; - end if; - end process; - iO(iO'low+K)<=RQ; - end generate; - O<=RESIZE(iO,O'high,O'low); - end generate l33; - --end; - - l257:if SIZE>=34 and SIZE33, - BRAM_THRESHOLD=>BRAM_THRESHOLD) - port map(CLK=>CLK, - I=>I, - O=>iO); - hd:entity work.SDELAY generic map(SIZE=>SIZE-33, - BRAM_THRESHOLD=>BRAM_THRESHOLD) - port map(CLK=>CLK, - I=>iO, - O=>O); - --end; - end generate l257; - - ln:if SIZE>=BRAM_THRESHOLD generate --- signal MEM:SFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); ---2008 signal MEM:SFIXED_VECTOR(0 to SIZE-3)(I'range):=(others=>(others=>'0')); - type TMEM is array(0 to SIZE-3) of SFIXED(I'range); - signal MEM:TMEM:=(others=>(others=>'0')); - signal RA,WA:UNSIGNED(LOG2(SIZE-2)-1 downto 0):=(others=>'0'); - signal iO1E,iO:SFIXED(I'range):=(others=>'0'); - attribute ram_style:STRING; - attribute ram_style of MEM:signal is "block"; - begin - process(CLK) - begin - if rising_edge(CLK) then --- if RA=SIZE-2 then - if RA=SIZE-3 then - RA<=(others=>'0'); - else - RA<=RA+1; - end if; - WA<=RA; - MEM(TO_INTEGER(WA))<=I; --- iO<=MEM(TO_INTEGER(RA)); - iO1E<=MEM(TO_INTEGER(RA)); - iO<=iO1E; - O<=RESIZE(iO,O'high,O'low); - end if; - end process; - -- end; - end generate; -end TEST; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - --- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 ------------------------------------------------------------------------------------------------ --- Copyright 2018 Xilinx, Inc. All rights reserved. --- This file contains confidential and proprietary information of Xilinx, Inc. and is --- protected under U.S. and international copyright and other intellectual property laws. ------------------------------------------------------------------------------------------------ --- --- Disclaimer: --- This disclaimer is not a license and does not grant any rights to the materials --- distributed herewith. Except as otherwise provided in a valid license issued to you --- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS --- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL --- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED --- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR --- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including --- negligence, or under any other theory of liability) for any loss or damage of any --- kind or nature related to, arising under or in connection with these materials, --- including for any direct, or any indirect, special, incidental, or consequential --- loss or damage (including loss of data, profits, goodwill, or any type of loss or --- damage suffered as a result of any action brought by a third party) even if such --- damage or loss was reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail-safe, or for use in any --- application requiring fail-safe performance, such as life-support or safety devices --- or systems, Class III medical devices, nuclear facilities, applications related to --- the deployment of airbags, or any other applications that could lead to death, --- personal injury, or severe property or environmental damage (individually and --- collectively, "Critical Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical Applications, subject only to --- applicable laws and regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. --- --- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx --- Worldwide Technical Support (WTS), for support please contact the author --- ____ ____ --- / /\/ / --- /___/ \ / Vendor: Xilinx Inc. --- \ \ \/ Version: 0.14 --- \ \ Filename: CDELAY.vhd --- / / Date Last Modified: 16 Apr 2018 --- /___/ /\ Date Created: --- \ \ / \ --- \___\/\___\ --- --- Device: Any UltraScale Xilinx FPGA --- Author: Catalin Baetoniu --- Entity Name: CDELAY --- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) --- --- Revision History: --- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support --------------------------------------------------------------------------------- --- --- Module Description: Generic CFIXED Delay Module --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.NUMERIC_STD.ALL; - -use work.COMPLEX_FIXED_PKG.all; - -library UNISIM; -use UNISIM.VComponents.all; - -entity CDELAY is - generic(SIZE:INTEGER:=1; - BRAM_THRESHOLD:INTEGER:=258); - port(CLK:in STD_LOGIC; - I:in CFIXED; - O:out CFIXED); -end CDELAY; - -architecture TEST of CDELAY is - attribute syn_hier:STRING; - attribute syn_hier of all:architecture is "hard"; - attribute rloc:STRING; - signal IRE,IIM:SFIXED((I'high+1)/2-1 downto I'low/2); - signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); -begin - IRE<=RE(I); - IIM<=IM(I); - dr:entity work.SDELAY generic map(SIZE=>SIZE, - BRAM_THRESHOLD=>BRAM_THRESHOLD) - port map(CLK=>CLK, ---2008 I=>I.RE, ---2008 O=>O.RE); - I=>IRE, - O=>ORE); - di:entity work.SDELAY generic map(SIZE=>SIZE, - BRAM_THRESHOLD=>BRAM_THRESHOLD) - port map(CLK=>CLK, ---2008 I=>I.IM, ---2008 O=>O.IM); - I=>IIM, - O=>OIM); - O<=TO_CFIXED(ORE,OIM); -end TEST; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - --- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 ------------------------------------------------------------------------------------------------ --- © Copyright 2018 Xilinx, Inc. All rights reserved. --- This file contains confidential and proprietary information of Xilinx, Inc. and is --- protected under U.S. and international copyright and other intellectual property laws. ------------------------------------------------------------------------------------------------ --- --- Disclaimer: --- This disclaimer is not a license and does not grant any rights to the materials --- distributed herewith. Except as otherwise provided in a valid license issued to you --- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS --- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL --- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED --- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR --- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including --- negligence, or under any other theory of liability) for any loss or damage of any --- kind or nature related to, arising under or in connection with these materials, --- including for any direct, or any indirect, special, incidental, or consequential --- loss or damage (including loss of data, profits, goodwill, or any type of loss or --- damage suffered as a result of any action brought by a third party) even if such --- damage or loss was reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail-safe, or for use in any --- application requiring fail-safe performance, such as life-support or safety devices --- or systems, Class III medical devices, nuclear facilities, applications related to --- the deployment of airbags, or any other applications that could lead to death, --- personal injury, or severe property or environmental damage (individually and --- collectively, "Critical Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical Applications, subject only to --- applicable laws and regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. --- --- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx --- Worldwide Technical Support (WTS), for support please contact the author --- ____ ____ --- / /\/ / --- /___/ \ / Vendor: Xilinx Inc. --- \ \ \/ Version: 0.14 --- \ \ Filename: CB.vhd --- / / Date Last Modified: 14 Feb 2018 --- /___/ /\ Date Created: --- \ \ / \ --- \___\/\___\ --- --- Device: Any UltraScale Xilinx FPGA --- Author: Catalin Baetoniu --- Entity Name: CB --- Purpose: Generic Parallel FFT Module (powers of 2 only) --- --- Revision History: --- Revision 0.14 2018-Feb-14 Version with workarounds for Vivado Simulator limited VHDL-2008 support --------------------------------------------------------------------------------- --- --- Module Description: Generic, Arbitrary Size, Matrix Transposer (Corner Bender) Module Stage --- It does an RxR matrix transposition where R=I'length --- and each matrix element is a group of PACKING_FACTOR consecutive samples --- LATENCY=(I'length-1)*PACKING_FACTOR+1 when I'length>1 or 0 when I'length=1 --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.NUMERIC_STD.all; - -use work.COMPLEX_FIXED_PKG.all; - -entity CB is - generic(SSR:INTEGER:=4; --93 - F:INTEGER:=0; - PACKING_FACTOR:INTEGER:=1; - INPUT_PACKING_FACTOR_ADJUST:INTEGER:=0; - OUTPUT_PACKING_FACTOR_ADJUST:INTEGER:=0; - SHORTEN_VO_BY:INTEGER:=0; - BRAM_THRESHOLD:INTEGER:=258); - port(CLK:in STD_LOGIC; - I:in CFIXED_VECTOR; - VI:in BOOLEAN; - SI:in UNSIGNED; - O:out CFIXED_VECTOR; - VO:out BOOLEAN; - SO:out UNSIGNED); -end CB; - -architecture TEST of CB is - attribute syn_keep:STRING; - attribute syn_keep of all:architecture is "hard"; - attribute rloc:STRING; - - type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(LOG2(SSR)-1 downto 0); --93 local constrained UNSIGNED_VECTOR type - type iCFIXED_VECTOR is array(NATURAL range <>) of CFIXED((I'high+1)/SSR-1 downto I'low/SSR); --93 local constrained CFIXED_VECTOR type - - signal CNTP:UNSIGNED(LOG2(PACKING_FACTOR) downto 0):=(others=>'0'); - signal CNT:UNSIGNED(LOG2(SSR)-1 downto 0):=(others=>'0'); ---2008 signal A:UNSIGNED_VECTOR(0 to I'length):=(others=>(others=>'0')); ---2008 signal EN:BOOLEAN_VECTOR(0 to I'length):=(others=>FALSE); ---2008 signal DI:CFIXED_VECTOR(0 to I'length-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); ---2008 signal DO:CFIXED_VECTOR(0 to I'length-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(0 to I'length-1=>(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).IM'range=>'0'))); - signal A:UNSIGNED_VECTOR(0 to SSR):=(others=>(others=>'0')); - signal EN:BOOLEAN_VECTOR(0 to SSR):=(others=>FALSE); - signal II,DI,OO:iCFIXED_VECTOR(0 to SSR-1); - signal DO:iCFIXED_VECTOR(0 to SSR-1):=(others=>(others=>'0')); -begin - assert I'length=O'length report "Ports I and O must have the same length!" severity error; ---2008 assert I'length=2**LOG2(I'length) report "Port I length must be a power of 2!" severity error; - assert SSR=2**LOG2(SSR) report "SSR must be a power of 2!" severity error; - assert SI'length=SO'length report "Ports SI and SO must have the same length!" severity error; - - f0:if F=0 generate - begin ---2008 i0:if I'length=1 generate - i0:if SSR=1 generate - O<=I; - VO<=VI; - SO<=SI; - end generate; ---2008 else generate ---2008 i1:if I'length>1 generate - i1:if SSR>1 generate - process(CLK) - begin - if rising_edge(CLK) then - if VI then - if CNTP=PACKING_FACTOR-1 then - CNTP<=(others=>'0'); - CNT<=CNT+1; - else - CNTP<=CNTP+1; - end if; - else - CNTP<=(others=>'0'); - CNT<=(others=>'0'); - end if; - end if; - end process; - - A(0)<=CNT; - EN(0)<=CNTP=PACKING_FACTOR-1; ---2008 lk:for K in 0 to I'length-1 generate - lk:for K in 0 to SSR-1 generate - begin - II(K)<=CFIXED(I(I'length/SSR*(K+1)-1+I'low downto I'length/SSR*K+I'low)); --93 - i1:entity work.CDELAY generic map(SIZE=>K*(PACKING_FACTOR+INPUT_PACKING_FACTOR_ADJUST), - BRAM_THRESHOLD=>BRAM_THRESHOLD) - port map(CLK=>CLK, - I=>II(K), --93 I(I'low+K), - O=>DI(K)); - process(CLK) - begin - if rising_edge(CLK) then - DO(K)<=DI(TO_INTEGER(A(K))); - if EN(K) then - A(K+1)<=A(K); - end if; - end if; - end process; - bd:entity work.BDELAY generic map(SIZE=>PACKING_FACTOR) - port map(CLK=>CLK, - I=>EN(K), - O=>EN(K+1)); - o1:entity work.CDELAY generic map(SIZE=>(SSR-1-K)*(PACKING_FACTOR+OUTPUT_PACKING_FACTOR_ADJUST), - BRAM_THRESHOLD=>BRAM_THRESHOLD) - port map(CLK=>CLK, - I=>DO(K), - O=>OO(K)); --93 O(O'low+K)); - O(O'length/SSR*(K+1)-1+O'low downto O'length/SSR*K+O'low)<=CFIXED_VECTOR(OO(K)); --93 - end generate; - - bd:entity work.BDELAY generic map(SIZE=>(SSR-1)*PACKING_FACTOR+1-SHORTEN_VO_BY) - port map(CLK=>CLK, - I=>VI, - O=>VO); - - ud:entity work.UDELAY generic map(SIZE=>(SSR-1)*PACKING_FACTOR+1-SHORTEN_VO_BY, - BRAM_THRESHOLD=>BRAM_THRESHOLD) - port map(CLK=>CLK, - I=>SI, - O=>SO); - end generate; --- end; --- else generate - end generate; - i1:if F>0 generate - constant G:INTEGER:=2**F; -- size of each PARFFT - constant H:INTEGER:=SSR/G; -- number of PARFFTs ---2008 signal S:UNSIGNED_VECTOR(0 to H)(SO'range); - type TUV is array(0 to H) of UNSIGNED(SO'range); - signal S:TUV; - signal V:BOOLEAN_VECTOR(0 to H-1); - begin - S(S'low)<=(others=>'0'); - lk:for K in 0 to H-1 generate - signal SK:UNSIGNED(SO'range); ---workaround for QuestaSim bug ---2008 signal II:CFIXED_VECTOR(0 to G-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); ---2008 signal OO:CFIXED_VECTOR(0 to G-1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); - signal II:CFIXED_VECTOR((I'high+1)/H-1 downto I'low/H); - signal OO:CFIXED_VECTOR((O'high+1)/H-1 downto O'low/H); - begin ---2008 II<=I(I'low+G*K+0 to I'low+G*K+G-1); - II<=I(I'length/H*(K+1)-1+I'low downto I'length/H*K+I'low); - bc:entity work.CB generic map(SSR=>G, - F=>0, - PACKING_FACTOR=>PACKING_FACTOR, - INPUT_PACKING_FACTOR_ADJUST=>INPUT_PACKING_FACTOR_ADJUST, - OUTPUT_PACKING_FACTOR_ADJUST=>OUTPUT_PACKING_FACTOR_ADJUST, - SHORTEN_VO_BY=>SHORTEN_VO_BY, - BRAM_THRESHOLD=>BRAM_THRESHOLD) - port map(CLK=>CLK, - I=>II, - VI=>VI, - SI=>SI, - O=>OO, - VO=>V(K), - SO=>SK); ---workaround for QuestaSim bug --- O(O'low+G*K+0 to O'low+G*K+G-1)<=OO; ---2008 lo:for J in 0 to G-1 generate ---2008 O(O'low+G*K+J)<=OO(J); ---2008 end generate; - O(O'length/H*(K+1)-1+O'low downto O'length/H*K+O'low)<=OO; - S(K+1)<=S(K) or SK; - end generate; - SO<=S(S'high); - VO<=V(V'high); --- end; - end generate; -end TEST; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - --- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 ------------------------------------------------------------------------------------------------ --- Copyright 2018 Xilinx, Inc. All rights reserved. --- This file contains confidential and proprietary information of Xilinx, Inc. and is --- protected under U.S. and international copyright and other intellectual property laws. ------------------------------------------------------------------------------------------------ --- --- Disclaimer: --- This disclaimer is not a license and does not grant any rights to the materials --- distributed herewith. Except as otherwise provided in a valid license issued to you --- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS --- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL --- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED --- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR --- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including --- negligence, or under any other theory of liability) for any loss or damage of any --- kind or nature related to, arising under or in connection with these materials, --- including for any direct, or any indirect, special, incidental, or consequential --- loss or damage (including loss of data, profits, goodwill, or any type of loss or --- damage suffered as a result of any action brought by a third party) even if such --- damage or loss was reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail-safe, or for use in any --- application requiring fail-safe performance, such as life-support or safety devices --- or systems, Class III medical devices, nuclear facilities, applications related to --- the deployment of airbags, or any other applications that could lead to death, --- personal injury, or severe property or environmental damage (individually and --- collectively, "Critical Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical Applications, subject only to --- applicable laws and regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. --- --- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx --- Worldwide Technical Support (WTS), for support please contact the author --- ____ ____ --- / /\/ / --- /___/ \ / Vendor: Xilinx Inc. --- \ \ \/ Version: 0.14 --- \ \ Filename: BFS.vhd --- / / Date Last Modified: 16 Apr 2018 --- /___/ /\ Date Created: --- \ \ / \ --- \___\/\___\ --- --- Device: Any UltraScale Xilinx FPGA --- Author: Catalin Baetoniu --- Entity Name: BFS --- Purpose: Generic Add/Subtract Module --- --- Revision History: --- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support --------------------------------------------------------------------------------- --- --- Module Description: Generic, Real Arbitrary Fixed Point Size, Add/Subtract FFT Module with scaling and overflow detection --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.NUMERIC_STD.all; - -use work.COMPLEX_FIXED_PKG.all; - -library UNISIM; -use UNISIM.VComponents.all; - -entity BFS is - generic(PIPELINE:BOOLEAN:=TRUE; - SUB:BOOLEAN:=FALSE; - DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ - EXTRA_MSBs:INTEGER:=1); - port(CLK:in STD_LOGIC:='0'; --- A,B:in SIGNED; -- if SIGNED, A, B and P must be LSB aligned - A,B:in SFIXED; -- if SFIXED, A, B and P can be any size - SCALE:in STD_LOGIC; --- P:out SIGNED); -- O=AB - P:out SFIXED; -- O=AB - OVR:out STD_LOGIC); -end BFS; - -architecture FAST of BFS is - constant SH:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'high,B'high)+EXTRA_MSBs; - constant SM:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'low,B'low); - constant SL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(A'low,B'low); --- signal SA,SB,M:SIGNED(SH+1 downto SM-1); --- signal S:SIGNED(SH+1 downto SL); - signal SA,SB:SFIXED(SH+1 downto SM-1); - signal S:SFIXED(SH+1 downto SL); - - signal O5:SIGNED(SH-SM+1 downto 0); - signal O6:SIGNED(SH-SM+1 downto 0); - signal CY:STD_LOGIC_VECTOR((SH-SM+1)/8*8+8 downto 0); - signal SI,DI,O:STD_LOGIC_VECTOR((SH-SM+1)/8*8+7 downto 0); -begin - SA<=RESIZE(A,SA); - SB<=RESIZE(B,SB); - - CY(0)<='1' when SUB else '0'; - lk:for K in SM to SH+1 generate - constant I0:BIT_VECTOR(63 downto 0):=X"AAAAAAAAAAAAAAAA" xor (63 downto 0=>BIT'val(BOOLEAN'pos(SUB))); - constant I1:BIT_VECTOR(63 downto 0):=X"CCCCCCCCCCCCCCCC"; - constant I2:BIT_VECTOR(63 downto 0):=X"F0F0F0F0F0F0F0F0" xor (63 downto 0=>BIT'val(BOOLEAN'pos(SUB))); - constant I3:BIT_VECTOR(63 downto 0):=X"FF00FF00FF00FF00"; - constant I4:BIT_VECTOR(63 downto 0):=X"FFFF0000FFFF0000"; - constant I5:BIT_VECTOR(63 downto 0):=X"FFFFFFFF00000000"; - begin - l6:LUT6_2 generic map(INIT=>(I5 and (((I0 and not I4) or (I2 and I4)) xor ((I1 and not I4) or (I3 and I4)))) or (not I5 and ((I1 and not I4) or (I3 and I4)))) - port map(I0=>SB(K-1),I1=>SA(K-1),I2=>SB(K),I3=>SA(K),I4=>SCALE,I5=>'1',O5=>O5(K-SM),O6=>O6(K-SM)); - end generate; - - SI<=STD_LOGIC_VECTOR(RESIZE(O6,SI'length)); - DI<=STD_LOGIC_VECTOR(RESIZE(O5,DI'length)); - lj:for J in 0 to (SH-SM+1)/8 generate - begin - i1:if DSP48E=1 generate -- 7-series - cl:CARRY4 port map(CI=>CY(8*J), -- 1-bit carry cascade input - CYINIT=>'0', -- 1-bit carry initialization - DI=>DI(8*J+3 downto 8*J), -- 4-bit carry-MUX data in - S=>SI(8*J+3 downto 8*J), -- 4-bit carry-MUX select input - CO=>CY(8*J+4 downto 8*J+1), -- 4-bit carry out - O=>O(8*J+3 downto 8*J)); -- 4-bit carry chain XOR data out - ch:CARRY4 port map(CI=>CY(8*J+4), -- 1-bit carry cascade input - CYINIT=>'0', -- 1-bit carry initialization - DI=>DI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX data in - S=>SI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX select input - CO=>CY(8*J+8 downto 8*J+5), -- 4-bit carry out - O=>O(8*J+7 downto 8*J+4)); -- 4-bit carry chain XOR data out - end generate; - i2:if DSP48E=2 generate -- US/US+ - c8:CARRY8 generic map(CARRY_TYPE=>"SINGLE_CY8") -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8) - port map(CI=>CY(8*J), -- 1-bit input: Lower Carry-In - CI_TOP=>'0', -- 1-bit input: Upper Carry-In - DI=>DI(8*J+7 downto 8*J), -- 8-bit input: Carry-MUX data in - S=>SI(8*J+7 downto 8*J), -- 8-bit input: Carry-mux select - CO=>CY(8*J+8 downto 8*J+1), -- 8-bit output: Carry-out - O=>O(8*J+7 downto 8*J)); -- 8-bit output: Carry chain XOR data out - end generate; - end generate; - - ll:for L in SM to SH generate - S(L)<=O(L-SM+1); - end generate; - S(SH+1)<=O(O'high); - - ia:if A'low'0'); - signal iOVR:STD_LOGIC:='0'; - begin - process(CLK) - begin - if rising_edge(CLK) then - iP<=RESIZE(S,P'high,P'low); - iOVR<=S(S'high) xor S(S'high-1); - end if; - end process; - P<=iP; - OVR<=iOVR; - end generate; -end FAST; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - --- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 ------------------------------------------------------------------------------------------------ --- Copyright 2018 Xilinx, Inc. All rights reserved. --- This file contains confidential and proprietary information of Xilinx, Inc. and is --- protected under U.S. and international copyright and other intellectual property laws. ------------------------------------------------------------------------------------------------ --- --- Disclaimer: --- This disclaimer is not a license and does not grant any rights to the materials --- distributed herewith. Except as otherwise provided in a valid license issued to you --- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS --- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL --- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED --- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR --- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including --- negligence, or under any other theory of liability) for any loss or damage of any --- kind or nature related to, arising under or in connection with these materials, --- including for any direct, or any indirect, special, incidental, or consequential --- loss or damage (including loss of data, profits, goodwill, or any type of loss or --- damage suffered as a result of any action brought by a third party) even if such --- damage or loss was reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail-safe, or for use in any --- application requiring fail-safe performance, such as life-support or safety devices --- or systems, Class III medical devices, nuclear facilities, applications related to --- the deployment of airbags, or any other applications that could lead to death, --- personal injury, or severe property or environmental damage (individually and --- collectively, "Critical Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical Applications, subject only to --- applicable laws and regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. --- --- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx --- Worldwide Technical Support (WTS), for support please contact the author --- ____ ____ --- / /\/ / --- /___/ \ / Vendor: Xilinx Inc. --- \ \ \/ Version: 0.14 --- \ \ Filename: CBFS.vhd --- / / Date Last Modified: 16 Apr 2018 --- /___/ /\ Date Created: --- \ \ / \ --- \___\/\___\ --- --- Device: Any UltraScale Xilinx FPGA --- Author: Catalin Baetoniu --- Entity Name: CBFS --- Purpose: Generic Add/Subtract Module --- --- Revision History: --- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support --------------------------------------------------------------------------------- --- --- Module Description: Generic, Complex Arbitrary Fixed Point Size, Add/Subtract FFT Module with scaling and overflow detection --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.NUMERIC_STD.all; - -use work.COMPLEX_FIXED_PKG.all; - -entity CBFS is -- O0=I0+I1, O1=I0-I1 - generic(ROUNDING:BOOLEAN:=TRUE; - PIPELINE:BOOLEAN:=TRUE; - DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ - EXTRA_MSBs:INTEGER:=1); - port(CLK:in STD_LOGIC; - I0,I1:in CFIXED; - SCALE:in STD_LOGIC; - O0,O1:out CFIXED; - OVR:out STD_LOGIC); -end CBFS; - -architecture TEST of CBFS is - signal I0RE,I0IM,I1RE,I1IM:SFIXED(I0'high/2 downto I0'low/2); - signal O0RE,O0IM,O1RE,O1IM:SFIXED(O0'high/2 downto O0'low/2); - signal OVR4:STD_LOGIC_VECTOR(3 downto 0); -begin - I0RE<=RE(I0); - I0IM<=IM(I0); - I1RE<=RE(I1); - I1IM<=IM(I1); - - u0:entity work.BFS generic map(DSP48E=>DSP48E, - SUB=>FALSE) -- O0RE=I0RE+I1RE - port map(CLK=>CLK, - A=>I0RE, - B=>I1RE, - SCALE=>SCALE, - P=>O0RE, - OVR=>OVR4(0)); - - u1:entity work.BFS generic map(DSP48E=>DSP48E, - SUB=>FALSE) -- O0IM=I0IM+I1IM - port map(CLK=>CLK, - A=>I0IM, - B=>I1IM, - SCALE=>SCALE, - P=>O0IM, - OVR=>OVR4(1)); - - u2:entity work.BFS generic map(DSP48E=>DSP48E, - SUB=>TRUE) -- O1RE=I0RE-I1RE - port map(CLK=>CLK, - A=>I0RE, - B=>I1RE, - SCALE=>SCALE, - P=>O1RE, - OVR=>OVR4(2)); - - u3:entity work.BFS generic map(DSP48E=>DSP48E, - SUB=>TRUE) -- O1IM=I0IM-I1IM - port map(CLK=>CLK, - A=>I0IM, - B=>I1IM, - SCALE=>SCALE, - P=>O1IM, - OVR=>OVR4(3)); - - O0<=TO_CFIXED(O0RE,O0IM); - O1<=TO_CFIXED(O1RE,O1IM); - OVR<=OVR4(0) or OVR4(1) or OVR4(2) or OVR4(3); -end TEST; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - --- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 ------------------------------------------------------------------------------------------------ --- Copyright 2018 Xilinx, Inc. All rights reserved. --- This file contains confidential and proprietary information of Xilinx, Inc. and is --- protected under U.S. and international copyright and other intellectual property laws. ------------------------------------------------------------------------------------------------ --- --- Disclaimer: --- This disclaimer is not a license and does not grant any rights to the materials --- distributed herewith. Except as otherwise provided in a valid license issued to you --- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS --- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL --- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED --- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR --- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including --- negligence, or under any other theory of liability) for any loss or damage of any --- kind or nature related to, arising under or in connection with these materials, --- including for any direct, or any indirect, special, incidental, or consequential --- loss or damage (including loss of data, profits, goodwill, or any type of loss or --- damage suffered as a result of any action brought by a third party) even if such --- damage or loss was reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail-safe, or for use in any --- application requiring fail-safe performance, such as life-support or safety devices --- or systems, Class III medical devices, nuclear facilities, applications related to --- the deployment of airbags, or any other applications that could lead to death, --- personal injury, or severe property or environmental damage (individually and --- collectively, "Critical Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical Applications, subject only to --- applicable laws and regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. --- --- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx --- Worldwide Technical Support (WTS), for support please contact the author --- ____ ____ --- / /\/ / --- /___/ \ / Vendor: Xilinx Inc. --- \ \ \/ Version: 0.14 --- \ \ Filename: CSA3.vhd --- / / Date Last Modified: 16 Apr 2018 --- /___/ /\ Date Created: --- \ \ / \ --- \___\/\___\ --- --- Device: Any UltraScale Xilinx FPGA --- Author: Catalin Baetoniu --- Entity Name: CSA3 --- Purpose: Generic 3-input Add/Sub Module --- --- Revision History: --- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support --------------------------------------------------------------------------------- --- --- Module Description: Generic, Carry Save 3-input Adder/Subtracter --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.NUMERIC_STD.all; - -use work.COMPLEX_FIXED_PKG.all; - -library UNISIM; -use UNISIM.VComponents.all; - -entity CSA3 is - generic(PIPELINE:BOOLEAN:=TRUE; - DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ - NEGATIVE_A:BOOLEAN:=FALSE; - NEGATIVE_B:BOOLEAN:=FALSE; - EXTRA_MSBs:INTEGER:=2); - port(CLK:in STD_LOGIC:='0'; --- A,B,C:in SIGNED; -- if SIGNED, A, B, C and P must be LSB aligned - A,B,C:in SFIXED; -- if SFIXED, A, B, C and P can be any size - CY1,CY2:in BOOLEAN:=FALSE; -- the number of CYs TRUE must equal the number of negative A and B terms --- P:out SIGNED); -- O=CAB - P:out SFIXED); -- O=CAB -end CSA3; - -architecture FAST of CSA3 is - constant SH:INTEGER:=MAX(A'high,B'high,C'high)+EXTRA_MSBs; - constant SM:INTEGER:=work.COMPLEX_FIXED_PKG.MED(A'low,B'low,C'low); - constant SL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(A'low,B'low,C'low); --- signal SA,SB,SC,M:SIGNED(SH downto SM); --- signal S:SIGNED(SH downto SL); - signal SA,SB,SC:SFIXED(SH downto SM); - signal S:SFIXED(SH downto SL); - - signal O5:SIGNED(SH-SM+1 downto 0); - signal O6:SIGNED(SH-SM downto 0); - signal CY:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8 downto 0); - signal SI,DI,O:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8-1 downto 0); -begin - SA<=RESIZE(A,SA); - SB<=RESIZE(B,SB); - SC<=RESIZE(C,SC); - O5(0)<='1' when CY1 else '0'; - CY(0)<='1' when CY2 else '0'; - lk:for K in SM to SH generate - constant I0:BIT_VECTOR(63 downto 0):=X"AAAAAAAAAAAAAAAA"; - constant I1:BIT_VECTOR(63 downto 0):=X"CCCCCCCCCCCCCCCC"; - constant I2:BIT_VECTOR(63 downto 0):=X"F0F0F0F0F0F0F0F0" xor (63 downto 0=>BIT'val(BOOLEAN'pos(NEGATIVE_B))); - constant I3:BIT_VECTOR(63 downto 0):=X"FF00FF00FF00FF00" xor (63 downto 0=>BIT'val(BOOLEAN'pos(NEGATIVE_A))); - constant I4:BIT_VECTOR(63 downto 0):=X"FFFF0000FFFF0000"; - constant I5:BIT_VECTOR(63 downto 0):=X"FFFFFFFF00000000"; - begin - l6:LUT6_2 generic map(INIT=>(I5 and (I1 xor I2 xor I3 xor I4)) or (not I5 and ((I2 and I3) or (I3 and I1) or (I1 and I2)))) - port map(I0=>'0',I1=>SC(K),I2=>SB(K),I3=>SA(K),I4=>O5(K-SM),I5=>'1',O5=>O5(K+1-SM),O6=>O6(K-SM)); - end generate; - - SI<=STD_LOGIC_VECTOR(RESIZE(O6,SI'length)); - DI<=STD_LOGIC_VECTOR(RESIZE(O5,DI'length)); - lj:for J in 0 to (SH-SM)/8 generate - begin - i1:if DSP48E=1 generate -- 7-series - cl:CARRY4 port map(CI=>CY(8*J), -- 1-bit carry cascade input - CYINIT=>'0', -- 1-bit carry initialization - DI=>DI(8*J+3 downto 8*J), -- 4-bit carry-MUX data in - S=>SI(8*J+3 downto 8*J), -- 4-bit carry-MUX select input - CO=>CY(8*J+4 downto 8*J+1), -- 4-bit carry out - O=>O(8*J+3 downto 8*J)); -- 4-bit carry chain XOR data out - ch:CARRY4 port map(CI=>CY(8*J+4), -- 1-bit carry cascade input - CYINIT=>'0', -- 1-bit carry initialization - DI=>DI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX data in - S=>SI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX select input - CO=>CY(8*J+8 downto 8*J+5), -- 4-bit carry out - O=>O(8*J+7 downto 8*J+4)); -- 4-bit carry chain XOR data out - end generate; - i2:if DSP48E=2 generate -- US/US+ - c8:CARRY8 generic map(CARRY_TYPE=>"SINGLE_CY8") -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8) - port map(CI=>CY(8*J), -- 1-bit input: Lower Carry-In - CI_TOP=>'0', -- 1-bit input: Upper Carry-In - DI=>DI(8*J+7 downto 8*J), -- 8-bit input: Carry-MUX data in - S=>SI(8*J+7 downto 8*J), -- 8-bit input: Carry-mux select - CO=>CY(8*J+8 downto 8*J+1), -- 8-bit output: Carry-out - O=>O(8*J+7 downto 8*J)); -- 8-bit output: Carry chain XOR data out - end generate; - end generate; - - ll:for L in SM to SH generate - S(L)<=O(L-SM); - end generate; - - ia:if (A'low'0'); - begin - process(CLK) - begin - if rising_edge(CLK) then - iP<=RESIZE(S,P'high,P'low); - end if; - end process; - P<=iP; - end generate; -end FAST; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - --- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 ---***************************************************************************** --- Copyright 2008 - 2018 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- ---***************************************************************************** --- ____ ____ --- / /\/ / --- /___/ \ / Vendor : Xilinx --- \ \ \/ Version : v1.2 --- \ \ Application : DSP48E2 generic wrapper --- / / Filename : DSP48E2GW.vhd --- /___/ /\ Date Last Modified : Oct 11 2017 --- \ \ / \ Date Created : Nov 14 2014 --- \___\/\___\ --- ---Device : UltraScale and UltraScale+ ---Design Name : DSP48E2GW ---Purpose : DSP48E2 Generic Wrapper makes DSP48E2 primitive instantiation easier ---Reference : ---Revision History : v1.0 - original version ---Revision History : v1.1 - smart SFIXED resizing ---Revision History : v1.2 - fix for output resizing ---***************************************************************************** - -library IEEE; -use IEEE.STD_LOGIC_1164.all; ---use IEEE.NUMERIC_STD.all; - -use work.COMPLEX_FIXED_PKG.all; - -library UNISIM; -use UNISIM.vcomponents.all; - -entity DSP48E2GW is - generic(X,Y:INTEGER:=-1; - DSP48E:INTEGER:=2; -- use 1 for DSP48E1 and 2 for DSP48E2 - -- Feature Control Attributes: Data Path Selection - AMULTSEL:STRING:="A"; -- Selects A input to multiplier (A, AD) - A_INPUT:STRING:="DIRECT"; -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) - BMULTSEL:STRING:="B"; -- Selects B input to multiplier (AD, B) - B_INPUT:STRING:="DIRECT"; -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) - PREADDINSEL:STRING:="A"; -- Selects input to preadder (A, B) - RND:STD_LOGIC_VECTOR(47 downto 0):=X"000000000000"; -- Rounding Constant - USE_MULT:STRING:="MULTIPLY"; -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) - USE_SIMD:STRING:="ONE48"; -- SIMD selection (FOUR12, ONE48, TWO24) - USE_WIDEXOR:STRING:="FALSE"; -- Use the Wide XOR function (FALSE, TRUE) - XORSIMD:STRING:="XOR24_48_96"; -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) - -- Pattern Detector Attributes: Pattern Detection Configuration - AUTORESET_PATDET:STRING:="NO_RESET"; -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH - AUTORESET_PRIORITY:STRING:="RESET"; -- Priority of AUTORESET vs.CEP (CEP, RESET). - MASK:STD_LOGIC_VECTOR(47 downto 0):=X"3fffffffffff"; -- 48-bit mask value for pattern detect (1=ignore) - PATTERN:STD_LOGIC_VECTOR(47 downto 0):=X"000000000000"; -- 48-bit pattern match for pattern detect - SEL_MASK:STRING:="MASK"; -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 - SEL_PATTERN:STRING:="PATTERN"; -- Select pattern value (C, PATTERN) - USE_PATTERN_DETECT:STRING:="NO_PATDET"; -- Enable pattern detect (NO_PATDET, PATDET) - -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins - IS_ALUMODE_INVERTED:STD_LOGIC_VECTOR(3 downto 0):=X"0"; -- Optional inversion for ALUMODE - IS_CARRYIN_INVERTED:BIT:='0'; -- Optional inversion for CARRYIN - IS_CLK_INVERTED:BIT:='0'; -- Optional inversion for CLK - IS_INMODE_INVERTED:STD_LOGIC_VECTOR(4 downto 0):="00000"; -- Optional inversion for INMODE - IS_OPMODE_INVERTED:STD_LOGIC_VECTOR(8 downto 0):="000000000"; -- Optional inversion for OPMODE - IS_RSTALLCARRYIN_INVERTED:BIT:='0'; -- Optional inversion for RSTALLCARRYIN - IS_RSTALUMODE_INVERTED:BIT:='0'; -- Optional inversion for RSTALUMODE - IS_RSTA_INVERTED:BIT:='0'; -- Optional inversion for RSTA - IS_RSTB_INVERTED:BIT:='0'; -- Optional inversion for RSTB - IS_RSTCTRL_INVERTED:BIT:='0'; -- Optional inversion for RSTCTRL - IS_RSTC_INVERTED:BIT:='0'; -- Optional inversion for RSTC - IS_RSTD_INVERTED:BIT:='0'; -- Optional inversion for RSTD - IS_RSTINMODE_INVERTED:BIT:='0'; -- Optional inversion for RSTINMODE - IS_RSTM_INVERTED:BIT:='0'; -- Optional inversion for RSTM - IS_RSTP_INVERTED:BIT:='0'; -- Optional inversion for RSTP - -- Register Control Attributes: Pipeline Register Configuration - ACASCREG:INTEGER:=1; -- Number of pipeline stages between A/ACIN and ACOUT (0-2) - ADREG:INTEGER:=1; -- Pipeline stages for pre-adder (0-1) - ALUMODEREG:INTEGER:=1; -- Pipeline stages for ALUMODE (0-1) - AREG:INTEGER:=1; -- Pipeline stages for A (0-2) - BCASCREG:INTEGER:=1; -- Number of pipeline stages between B/BCIN and BCOUT (0-2) - BREG:INTEGER:=1; -- Pipeline stages for B (0-2) - CARRYINREG:INTEGER:=1; -- Pipeline stages for CARRYIN (0-1) - CARRYINSELREG:INTEGER:=1; -- Pipeline stages for CARRYINSEL (0-1) - CREG:INTEGER:=1; -- Pipeline stages for C (0-1) - DREG:INTEGER:=1; -- Pipeline stages for D (0-1) - INMODEREG:INTEGER:=1; -- Pipeline stages for INMODE (0-1) - MREG:INTEGER:=1; -- Multiplier pipeline stages (0-1) - OPMODEREG:INTEGER:=1; -- Pipeline stages for OPMODE (0-1) - PREG:INTEGER:=1); -- Number of pipeline stages for P (0-1) - port(-- Cascade inputs: Cascade Ports - ACIN:in STD_LOGIC_VECTOR(29 downto 0):=(others=>'0'); -- 30-bit input: A cascade data - BCIN:in STD_LOGIC_VECTOR(17 downto 0):=(others=>'0'); -- 18-bit input: B cascade - CARRYCASCIN:in STD_LOGIC:='0'; -- 1-bit input: Cascade carry - MULTSIGNIN:in STD_LOGIC:='0'; -- 1-bit input: Multiplier sign cascade - PCIN:in STD_LOGIC_VECTOR(47 downto 0):=(others=>'0'); -- 48-bit input: P cascade - -- Control inputs: Control Inputs/Status Bits - ALUMODE:in STD_LOGIC_VECTOR(3 downto 0):=X"0"; -- 4-bit input: ALU control - CARRYINSEL:in STD_LOGIC_VECTOR(2 downto 0):="000"; -- 3-bit input: Carry select - CLK:in STD_LOGIC:='0'; -- 1-bit input: Clock - INMODE:in STD_LOGIC_VECTOR(4 downto 0):="00000"; -- 5-bit input: INMODE control - OPMODE:in STD_LOGIC_VECTOR(8 downto 0):="000110101"; -- 9-bit input: Operation mode - default is P<=C+A*B - -- Data inputs: Data Ports - A:in SFIXED;--(Ahi downto Alo):=(others=>'0'); -- 30-bit input: A data - B:in SFIXED;--(Bhi downto Blo):=(others=>'0'); -- 18-bit input: B data - C:in SFIXED;--(Chi downto Clo):=(others=>'0'); -- 48-bit input: C data - CARRYIN:in STD_LOGIC:='0'; -- 1-bit input: Carry-in - D:in SFIXED;--(Dhi downto Dlo):=(others=>'0'); -- 27-bit input: D data - -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs - CEA1:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 1st stage AREG - CEA2:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 2nd stage AREG - CEAD:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for ADREG - CEALUMODE:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for ALUMODE - CEB1:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 1st stage BREG - CEB2:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 2nd stage BREG - CEC:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for CREG - CECARRYIN:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for CARRYINREG - CECTRL:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG - CED:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for DREG - CEINMODE:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for INMODEREG - CEM:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for MREG - CEP:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for PREG - RSTA:in STD_LOGIC:='0'; -- 1-bit input: Reset for AREG - RSTALLCARRYIN:in STD_LOGIC:='0'; -- 1-bit input: Reset for CARRYINREG - RSTALUMODE:in STD_LOGIC:='0'; -- 1-bit input: Reset for ALUMODEREG - RSTB:in STD_LOGIC:='0'; -- 1-bit input: Reset for BREG - RSTC:in STD_LOGIC:='0'; -- 1-bit input: Reset for CREG - RSTCTRL:in STD_LOGIC:='0'; -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG - RSTD:in STD_LOGIC:='0'; -- 1-bit input: Reset for DREG and ADREG - RSTINMODE:in STD_LOGIC:='0'; -- 1-bit input: Reset for INMODEREG - RSTM:in STD_LOGIC:='0'; -- 1-bit input: Reset for MREG - RSTP:in STD_LOGIC:='0'; -- 1-bit input: Reset for PREG - -- Cascade outputs: Cascade Ports - ACOUT:out STD_LOGIC_VECTOR(29 downto 0); -- 30-bit output: A port cascade - BCOUT:out STD_LOGIC_VECTOR(17 downto 0); -- 18-bit output: B cascade - CARRYCASCOUT:out STD_LOGIC; -- 1-bit output: Cascade carry - MULTSIGNOUT:out STD_LOGIC; -- 1-bit output: Multiplier sign cascade - PCOUT:out STD_LOGIC_VECTOR(47 downto 0); -- 48-bit output: Cascade output - -- Control outputs: Control Inputs/Status Bits - OVERFLOW:out STD_LOGIC; -- 1-bit output: Overflow in add/acc - PATTERNBDETECT:out STD_LOGIC; -- 1-bit output: Pattern bar detect - PATTERNDETECT:out STD_LOGIC; -- 1-bit output: Pattern detect - UNDERFLOW:out STD_LOGIC; -- 1-bit output: Underflow in add/acc - -- Data outputs: Data Ports - CARRYOUT:out STD_LOGIC_VECTOR(3 downto 0); -- 4-bit output: Carry - P:out SFIXED;--(Phi downto Plo); -- 48-bit output: Primary data - XOROUT:out STD_LOGIC_VECTOR(7 downto 0)); -- 8-bit output: XOR data -end entity; - -architecture WRAPPER of DSP48E2GW is - signal slvA:STD_LOGIC_VECTOR(29 downto 0); - signal slvB:STD_LOGIC_VECTOR(17 downto 0); - signal slvD:STD_LOGIC_VECTOR(26 downto 0); - signal slvC,slvP:STD_LOGIC_VECTOR(47 downto 0); --- resize SFIXED and convert to STD_LOGIC_VECTOR - function SFIXED_TO_SLV_RESIZE(I:SFIXED;hi,lo:INTEGER) return STD_LOGIC_VECTOR is - variable O:STD_LOGIC_VECTOR(hi-lo downto 0); - begin - for K in O'range loop - if K=0) and (Y>=0) generate - begin - i1:if DSP48E=1 generate - attribute loc:STRING; - attribute loc of ds:label is "DSP48E2_X"&INTEGER'image(X)&"Y"&INTEGER'image(Y); - begin - ds:DSP48E1 generic map(-- Feature Control Attributes: Data Path Selection - A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) - B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) - USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) - USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) - -- Pattern Detector Attributes: Pattern Detection Configuration - AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH --- MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) --- PATTERN => PATTERN, -- 48-bit pattern match for pattern detect - SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 - SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) - USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) - -- Register Control Attributes: Pipeline Register Configuration - ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) - ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) - ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) - AREG => AREG, -- Pipeline stages for A (0-2) - BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) - BREG => BREG, -- Pipeline stages for B (0-2) - CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) - CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) - CREG => CREG, -- Pipeline stages for C (0-1) - DREG => DREG, -- Pipeline stages for D (0-1) - INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) - MREG => MREG, -- Multiplier pipeline stages (0-1) - OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) - PREG => PREG) -- Number of pipeline stages for P (0-1) - port map(-- Cascade inputs: Cascade Ports - ACIN => ACIN, -- 30-bit input: A cascade data - BCIN => BCIN, -- 18-bit input: B cascade - CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry - MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade - PCIN => PCIN, -- 48-bit input: P cascade - -- Control inputs: Control Inputs/Status Bits - ALUMODE => ALUMODE, -- 4-bit input: ALU control - CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select - CLK => CLK, -- 1-bit input: Clock - INMODE => INMODE, -- 5-bit input: INMODE control - OPMODE => OPMODE(6 downto 0), -- 7-bit input: Operation mode - -- Data inputs: Data Ports - A => slvA, -- 30-bit input: A data - B => slvB, -- 18-bit input: B data - C => slvC, -- 48-bit input: C data - CARRYIN => CARRYIN, -- 1-bit input: Carry-in - D => slvD(24 downto 0), -- 25-bit input: D data - -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs - CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG - CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG - CEAD => CEAD, -- 1-bit input: Clock enable for ADREG - CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE - CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG - CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG - CEC => CEC, -- 1-bit input: Clock enable for CREG - CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG - CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG - CED => CED, -- 1-bit input: Clock enable for DREG - CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG - CEM => CEM, -- 1-bit input: Clock enable for MREG - CEP => CEP, -- 1-bit input: Clock enable for PREG - RSTA => RSTA, -- 1-bit input: Reset for AREG - RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG - RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG - RSTB => RSTB, -- 1-bit input: Reset for BREG - RSTC => RSTC, -- 1-bit input: Reset for CREG - RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG - RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG - RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG - RSTM => RSTM, -- 1-bit input: Reset for MREG - RSTP => RSTP, -- 1-bit input: Reset for PREG - -- Cascade outputs: Cascade Ports - ACOUT => ACOUT, -- 30-bit output: A port cascade - BCOUT => BCOUT, -- 18-bit output: B cascade - CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry - MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade - PCOUT => PCOUT, -- 48-bit output: Cascade output - -- Control outputs: Control Inputs/Status Bits - OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc - PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect - PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect - UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc - -- Data outputs: Data Ports - CARRYOUT => CARRYOUT, -- 4-bit output: Carry - P => slvP); -- 48-bit output: Primary data - end generate; - i2:if DSP48E=2 generate - attribute loc:STRING; - attribute loc of ds:label is "DSP48E2_X"&INTEGER'image(X)&"Y"&INTEGER'image(Y); - begin - ds:DSP48E2 generic map(-- Feature Control Attributes: Data Path Selection - AMULTSEL => AMULTSEL, -- Selects A input to multiplier (A, AD) - A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) - BMULTSEL => BMULTSEL, -- Selects B input to multiplier (AD, B) - B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) - PREADDINSEL => PREADDINSEL, -- Selects input to preadder (A, B) - RND => RND, -- Rounding Constant - USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) - USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) - USE_WIDEXOR => USE_WIDEXOR, -- Use the Wide XOR function (FALSE, TRUE) - XORSIMD => XORSIMD, -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) - -- Pattern Detector Attributes: Pattern Detection Configuration - AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH - AUTORESET_PRIORITY => AUTORESET_PRIORITY, -- Priority of AUTORESET vs.CEP (CEP, RESET). - MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) - PATTERN => PATTERN, -- 48-bit pattern match for pattern detect - SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 - SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) - USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) - -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins - IS_ALUMODE_INVERTED => IS_ALUMODE_INVERTED, -- Optional inversion for ALUMODE - IS_CARRYIN_INVERTED => IS_CARRYIN_INVERTED, -- Optional inversion for CARRYIN - IS_CLK_INVERTED => IS_CLK_INVERTED, -- Optional inversion for CLK - IS_INMODE_INVERTED => IS_INMODE_INVERTED, -- Optional inversion for INMODE - IS_OPMODE_INVERTED => IS_OPMODE_INVERTED, -- Optional inversion for OPMODE - IS_RSTALLCARRYIN_INVERTED => IS_RSTALLCARRYIN_INVERTED, -- Optional inversion for RSTALLCARRYIN - IS_RSTALUMODE_INVERTED => IS_RSTALUMODE_INVERTED, -- Optional inversion for RSTALUMODE - IS_RSTA_INVERTED => IS_RSTA_INVERTED, -- Optional inversion for RSTA - IS_RSTB_INVERTED => IS_RSTB_INVERTED, -- Optional inversion for RSTB - IS_RSTCTRL_INVERTED => IS_RSTCTRL_INVERTED, -- Optional inversion for RSTCTRL - IS_RSTC_INVERTED => IS_RSTC_INVERTED, -- Optional inversion for RSTC - IS_RSTD_INVERTED => IS_RSTD_INVERTED, -- Optional inversion for RSTD - IS_RSTINMODE_INVERTED => IS_RSTINMODE_INVERTED, -- Optional inversion for RSTINMODE - IS_RSTM_INVERTED => IS_RSTM_INVERTED, -- Optional inversion for RSTM - IS_RSTP_INVERTED => IS_RSTP_INVERTED, -- Optional inversion for RSTP - -- Register Control Attributes: Pipeline Register Configuration - ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) - ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) - ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) - AREG => AREG, -- Pipeline stages for A (0-2) - BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) - BREG => BREG, -- Pipeline stages for B (0-2) - CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) - CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) - CREG => CREG, -- Pipeline stages for C (0-1) - DREG => DREG, -- Pipeline stages for D (0-1) - INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) - MREG => MREG, -- Multiplier pipeline stages (0-1) - OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) - PREG => PREG) -- Number of pipeline stages for P (0-1) - port map(-- Cascade inputs: Cascade Ports - ACIN => ACIN, -- 30-bit input: A cascade data - BCIN => BCIN, -- 18-bit input: B cascade - CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry - MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade - PCIN => PCIN, -- 48-bit input: P cascade - -- Control inputs: Control Inputs/Status Bits - ALUMODE => ALUMODE, -- 4-bit input: ALU control - CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select - CLK => CLK, -- 1-bit input: Clock - INMODE => INMODE, -- 5-bit input: INMODE control - OPMODE => OPMODE, -- 9-bit input: Operation mode - -- Data inputs: Data Ports - A => slvA, -- 30-bit input: A data - B => slvB, -- 18-bit input: B data - C => slvC, -- 48-bit input: C data - CARRYIN => CARRYIN, -- 1-bit input: Carry-in - D => slvD, -- 27-bit input: D data - -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs - CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG - CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG - CEAD => CEAD, -- 1-bit input: Clock enable for ADREG - CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE - CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG - CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG - CEC => CEC, -- 1-bit input: Clock enable for CREG - CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG - CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG - CED => CED, -- 1-bit input: Clock enable for DREG - CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG - CEM => CEM, -- 1-bit input: Clock enable for MREG - CEP => CEP, -- 1-bit input: Clock enable for PREG - RSTA => RSTA, -- 1-bit input: Reset for AREG - RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG - RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG - RSTB => RSTB, -- 1-bit input: Reset for BREG - RSTC => RSTC, -- 1-bit input: Reset for CREG - RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG - RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG - RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG - RSTM => RSTM, -- 1-bit input: Reset for MREG - RSTP => RSTP, -- 1-bit input: Reset for PREG - -- Cascade outputs: Cascade Ports - ACOUT => ACOUT, -- 30-bit output: A port cascade - BCOUT => BCOUT, -- 18-bit output: B cascade - CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry - MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade - PCOUT => PCOUT, -- 48-bit output: Cascade output - -- Control outputs: Control Inputs/Status Bits - OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc - PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect - PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect - UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc - -- Data outputs: Data Ports - CARRYOUT => CARRYOUT, -- 4-bit output: Carry - P => slvP, -- 48-bit output: Primary data - XOROUT => XOROUT); -- 8-bit output: XOR data - end generate; --- end; - end generate; --- else generate - i2:if (X<0) or (Y<0) generate - begin - i1:if DSP48E=1 generate - ds:DSP48E1 generic map(-- Feature Control Attributes: Data Path Selection - A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) - B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) - USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) - USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) - -- Pattern Detector Attributes: Pattern Detection Configuration - AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH --- MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) --- PATTERN => PATTERN, -- 48-bit pattern match for pattern detect - SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 - SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) - USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) - -- Register Control Attributes: Pipeline Register Configuration - ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) - ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) - ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) - AREG => AREG, -- Pipeline stages for A (0-2) - BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) - BREG => BREG, -- Pipeline stages for B (0-2) - CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) - CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) - CREG => CREG, -- Pipeline stages for C (0-1) - DREG => DREG, -- Pipeline stages for D (0-1) - INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) - MREG => MREG, -- Multiplier pipeline stages (0-1) - OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) - PREG => PREG) -- Number of pipeline stages for P (0-1) - port map(-- Cascade inputs: Cascade Ports - ACIN => ACIN, -- 30-bit input: A cascade data - BCIN => BCIN, -- 18-bit input: B cascade - CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry - MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade - PCIN => PCIN, -- 48-bit input: P cascade - -- Control inputs: Control Inputs/Status Bits - ALUMODE => ALUMODE, -- 4-bit input: ALU control - CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select - CLK => CLK, -- 1-bit input: Clock - INMODE => INMODE, -- 5-bit input: INMODE control - OPMODE => OPMODE(6 downto 0), -- 7-bit input: Operation mode - -- Data inputs: Data Ports - A => slvA, -- 30-bit input: A data - B => slvB, -- 18-bit input: B data - C => slvC, -- 48-bit input: C data - CARRYIN => CARRYIN, -- 1-bit input: Carry-in - D => slvD(24 downto 0), -- 25-bit input: D data - -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs - CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG - CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG - CEAD => CEAD, -- 1-bit input: Clock enable for ADREG - CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE - CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG - CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG - CEC => CEC, -- 1-bit input: Clock enable for CREG - CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG - CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG - CED => CED, -- 1-bit input: Clock enable for DREG - CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG - CEM => CEM, -- 1-bit input: Clock enable for MREG - CEP => CEP, -- 1-bit input: Clock enable for PREG - RSTA => RSTA, -- 1-bit input: Reset for AREG - RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG - RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG - RSTB => RSTB, -- 1-bit input: Reset for BREG - RSTC => RSTC, -- 1-bit input: Reset for CREG - RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG - RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG - RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG - RSTM => RSTM, -- 1-bit input: Reset for MREG - RSTP => RSTP, -- 1-bit input: Reset for PREG - -- Cascade outputs: Cascade Ports - ACOUT => ACOUT, -- 30-bit output: A port cascade - BCOUT => BCOUT, -- 18-bit output: B cascade - CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry - MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade - PCOUT => PCOUT, -- 48-bit output: Cascade output - -- Control outputs: Control Inputs/Status Bits - OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc - PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect - PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect - UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc - -- Data outputs: Data Ports - CARRYOUT => CARRYOUT, -- 4-bit output: Carry - P => slvP); -- 48-bit output: Primary data - end generate; - i2:if DSP48E=2 generate - ds:DSP48E2 generic map(-- Feature Control Attributes: Data Path Selection - AMULTSEL => AMULTSEL, -- Selects A input to multiplier (A, AD) - A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) - BMULTSEL => BMULTSEL, -- Selects B input to multiplier (AD, B) - B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) - PREADDINSEL => PREADDINSEL, -- Selects input to preadder (A, B) - RND => RND, -- Rounding Constant - USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) - USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) - USE_WIDEXOR => USE_WIDEXOR, -- Use the Wide XOR function (FALSE, TRUE) - XORSIMD => XORSIMD, -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) - -- Pattern Detector Attributes: Pattern Detection Configuration - AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH - AUTORESET_PRIORITY => AUTORESET_PRIORITY, -- Priority of AUTORESET vs.CEP (CEP, RESET). - MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) - PATTERN => PATTERN, -- 48-bit pattern match for pattern detect - SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 - SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) - USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) - -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins - IS_ALUMODE_INVERTED => IS_ALUMODE_INVERTED, -- Optional inversion for ALUMODE - IS_CARRYIN_INVERTED => IS_CARRYIN_INVERTED, -- Optional inversion for CARRYIN - IS_CLK_INVERTED => IS_CLK_INVERTED, -- Optional inversion for CLK - IS_INMODE_INVERTED => IS_INMODE_INVERTED, -- Optional inversion for INMODE - IS_OPMODE_INVERTED => IS_OPMODE_INVERTED, -- Optional inversion for OPMODE - IS_RSTALLCARRYIN_INVERTED => IS_RSTALLCARRYIN_INVERTED, -- Optional inversion for RSTALLCARRYIN - IS_RSTALUMODE_INVERTED => IS_RSTALUMODE_INVERTED, -- Optional inversion for RSTALUMODE - IS_RSTA_INVERTED => IS_RSTA_INVERTED, -- Optional inversion for RSTA - IS_RSTB_INVERTED => IS_RSTB_INVERTED, -- Optional inversion for RSTB - IS_RSTCTRL_INVERTED => IS_RSTCTRL_INVERTED, -- Optional inversion for RSTCTRL - IS_RSTC_INVERTED => IS_RSTC_INVERTED, -- Optional inversion for RSTC - IS_RSTD_INVERTED => IS_RSTD_INVERTED, -- Optional inversion for RSTD - IS_RSTINMODE_INVERTED => IS_RSTINMODE_INVERTED, -- Optional inversion for RSTINMODE - IS_RSTM_INVERTED => IS_RSTM_INVERTED, -- Optional inversion for RSTM - IS_RSTP_INVERTED => IS_RSTP_INVERTED, -- Optional inversion for RSTP - -- Register Control Attributes: Pipeline Register Configuration - ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) - ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) - ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) - AREG => AREG, -- Pipeline stages for A (0-2) - BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) - BREG => BREG, -- Pipeline stages for B (0-2) - CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) - CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) - CREG => CREG, -- Pipeline stages for C (0-1) - DREG => DREG, -- Pipeline stages for D (0-1) - INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) - MREG => MREG, -- Multiplier pipeline stages (0-1) - OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) - PREG => PREG) -- Number of pipeline stages for P (0-1) - port map(-- Cascade inputs: Cascade Ports - ACIN => ACIN, -- 30-bit input: A cascade data - BCIN => BCIN, -- 18-bit input: B cascade - CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry - MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade - PCIN => PCIN, -- 48-bit input: P cascade - -- Control inputs: Control Inputs/Status Bits - ALUMODE => ALUMODE, -- 4-bit input: ALU control - CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select - CLK => CLK, -- 1-bit input: Clock - INMODE => INMODE, -- 5-bit input: INMODE control - OPMODE => OPMODE, -- 9-bit input: Operation mode - -- Data inputs: Data Ports - A => slvA, -- 30-bit input: A data - B => slvB, -- 18-bit input: B data - C => slvC, -- 48-bit input: C data - CARRYIN => CARRYIN, -- 1-bit input: Carry-in - D => slvD, -- 27-bit input: D data - -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs - CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG - CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG - CEAD => CEAD, -- 1-bit input: Clock enable for ADREG - CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE - CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG - CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG - CEC => CEC, -- 1-bit input: Clock enable for CREG - CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG - CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG - CED => CED, -- 1-bit input: Clock enable for DREG - CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG - CEM => CEM, -- 1-bit input: Clock enable for MREG - CEP => CEP, -- 1-bit input: Clock enable for PREG - RSTA => RSTA, -- 1-bit input: Reset for AREG - RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG - RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG - RSTB => RSTB, -- 1-bit input: Reset for BREG - RSTC => RSTC, -- 1-bit input: Reset for CREG - RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG - RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG - RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG - RSTM => RSTM, -- 1-bit input: Reset for MREG - RSTP => RSTP, -- 1-bit input: Reset for PREG - -- Cascade outputs: Cascade Ports - ACOUT => ACOUT, -- 30-bit output: A port cascade - BCOUT => BCOUT, -- 18-bit output: B cascade - CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry - MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade - PCOUT => PCOUT, -- 48-bit output: Cascade output - -- Control outputs: Control Inputs/Status Bits - OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc - PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect - PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect - UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc - -- Data outputs: Data Ports - CARRYOUT => CARRYOUT, -- 4-bit output: Carry - P => slvP, -- 48-bit output: Primary data - XOROUT => XOROUT); -- 8-bit output: XOR data - end generate; --- end; - end generate; - P<=SLV_TO_SFIXED_RESIZE(slvP,P'high,P'low,A'low+B'low-P'low); -end WRAPPER; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - --- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 ------------------------------------------------------------------------------------------------ --- © Copyright 2018 Xilinx, Inc. All rights reserved. --- This file contains confidential and proprietary information of Xilinx, Inc. and is --- protected under U.S. and international copyright and other intellectual property laws. ------------------------------------------------------------------------------------------------ --- --- Disclaimer: --- This disclaimer is not a license and does not grant any rights to the materials --- distributed herewith. Except as otherwise provided in a valid license issued to you --- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS --- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL --- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED --- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR --- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including --- negligence, or under any other theory of liability) for any loss or damage of any --- kind or nature related to, arising under or in connection with these materials, --- including for any direct, or any indirect, special, incidental, or consequential --- loss or damage (including loss of data, profits, goodwill, or any type of loss or --- damage suffered as a result of any action brought by a third party) even if such --- damage or loss was reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail-safe, or for use in any --- application requiring fail-safe performance, such as life-support or safety devices --- or systems, Class III medical devices, nuclear facilities, applications related to --- the deployment of airbags, or any other applications that could lead to death, --- personal injury, or severe property or environmental damage (individually and --- collectively, "Critical Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical Applications, subject only to --- applicable laws and regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. --- --- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx --- Worldwide Technical Support (WTS), for support please contact the author --- ____ ____ --- / /\/ / --- /___/ \ / Vendor: Xilinx Inc. --- \ \ \/ Version: 0.14 --- \ \ Filename: CKCM.vhd --- / / Date Last Modified: 16 Apr 2018 --- /___/ /\ Date Created: --- \ \ / \ --- \___\/\___\ --- --- Device: Any UltraScale Xilinx FPGA --- Author: Catalin Baetoniu --- Entity Name: CKCM --- Purpose: Generic Parallel FFT Module (powers of 2 only) --- --- Revision History: --- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support --------------------------------------------------------------------------------- --- --- Module Description: Constant Coeficient Complex Multiplier --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.NUMERIC_STD.all; -use ieee.math_real.all; - -use work.COMPLEX_FIXED_PKG.all; - -entity CKCM is -- LATENCY=3 - generic(M:INTEGER:=1; -- must be 0, 1, 2 or 3 to multiply I by (1.0,0.0), (Sqrt(0.5),-Sqrt(0.5)), (0.0,-1.0), (-Sqrt(0.5),-Sqrt(0.5)) - DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ - ROUNDING:BOOLEAN:=FALSE; -- set to TRUE to round the result - CONJUGATE:BOOLEAN:=FALSE); -- set to TRUE for IFFT - port(CLK:in STD_LOGIC; - I:in CFIXED; - O:out CFIXED); -end CKCM; - -architecture TEST of CKCM is - attribute use_dsp48:STRING; - attribute use_dsp48 of TEST:architecture is "no"; ---2008 signal RND:SFIXED(O.RE'high downto O.RE'low-1); - signal RND:SFIXED((O'high+1)/2-1 downto O'low/2-1); - constant nCONJUGATE:BOOLEAN:=not CONJUGATE; -begin - i0:if M=0 generate - cd:entity work.CDELAY generic map(SIZE=>3) - port map(CLK=>CLK, - I=>I, - O=>O); - end generate; ---elsif i1: M=2 generate - i1:if M=2 generate - ic:if CONJUGATE generate ---2008 signal NIIM1D:SFIXED(I.IM'range):=TO_SFIXED(0.0,I.IM'high,I.IM'low); - signal NIIM1D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); - signal IRE:SFIXED((I'high+1)/2-1 downto I'low/2); - signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); - begin - process(CLK) - begin - if rising_edge(CLK) then ---2008 NIIM1D<=RESIZE(-I.IM,I.IM); - NIIM1D<=RESIZE(-IM(I),NIIM1D); - end if; - end process; - r2:entity work.SDELAY generic map(SIZE=>2) - port map(CLK=>CLK, - I=>NIIM1D, ---2008 O=>O.RE); - O=>ORE); - IRE<=RE(I); - i3:entity work.SDELAY generic map(SIZE=>3) - port map(CLK=>CLK, ---2008 I=>I.RE, ---2008 O=>O.IM); - I=>IRE, - O=>OIM); - O<=TO_CFIXED(ORE,OIM); --- end; - end generate; - ---else generate - nc:if not CONJUGATE generate ---2008 signal NIRE1D:SFIXED(I.RE'range):=TO_SFIXED(0.0,I.RE'high,I.RE'low); - signal NIRE1D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); - signal IIM:SFIXED((I'high+1)/2-1 downto I'low/2); - signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); - begin - IIM<=IM(I); - r3:entity work.SDELAY generic map(SIZE=>3) - port map(CLK=>CLK, ---2008 I=>I.IM, ---2008 O=>O.RE); - I=>IIM, - O=>ORE); - process(CLK) - begin - if rising_edge(CLK) then ---2008 NIRE1D<=RESIZE(-I.RE,I.RE); - NIRE1D<=RESIZE(-RE(I),RE(I)); - end if; - end process; - i2:entity work.SDELAY generic map(SIZE=>2) - port map(CLK=>CLK, - I=>NIRE1D, ---2008 O=>O.IM); - O=>OIM); - O<=TO_CFIXED(ORE,OIM); --- end; - end generate; - end generate; --- else generate -- M=1 or 3 - i2:if (M=1) or (M=3) generate -- M=1 or 3 - constant K:SFIXED(0 downto -18):="0101101010000010100"; -- SQRT(0.5) - ---2008 signal X1,Y1:SFIXED(I.RE'high downto I.RE'low-14); ---2008 signal X2,Y2:SFIXED(I.RE'range); ---2008 signal KIRE,KIIM:SFIXED(I.RE'range); - - - - signal X1,Y1:SFIXED((I'high+1)/2-1 downto I'low/2-14); - signal X2,Y2:SFIXED((I'high+1)/2-1 downto I'low/2):=(others=>'0'); - signal KIRE,KIIM:SFIXED((I'high+1)/2-1 downto I'low/2); ---2008 signal I_1:CFIXED(RE(I.RE'high-1 downto I.RE'low-1),IM(I.IM'high-1 downto I.IM'low-1)); ---2008 signal I_6:CFIXED(RE(I.RE'high-6 downto I.RE'low-6),IM(I.IM'high-6 downto I.IM'low-6)); ---2008 signal I_14:CFIXED(RE(I.RE'high-14 downto I.RE'low-14),IM(I.IM'high-14 downto I.IM'low-14)); - signal I_1:CFIXED(I'high-2*1 downto I'low-2*1); - signal I_6:CFIXED(I'high-2*6 downto I'low-2*6); - signal I_14:CFIXED(I'high-2*14 downto I'low-2*14); - signal I_1RE,I_1IM:SFIXED((I_1'high+1)/2-1 downto I_1'low/2); - signal I_6RE,I_6IM:SFIXED((I_6'high+1)/2-1 downto I_6'low/2); - signal I_14RE,I_14IM:SFIXED((I_14'high+1)/2-1 downto I_14'low/2); - signal X1_2:SFIXED(X1'high-2 downto X1'low-2); - signal X2_4:SFIXED(X2'high-4 downto X2'low-4); - signal Y1_2:SFIXED(Y1'high-2 downto Y1'low-2); - signal Y2_4:SFIXED(Y2'high-4 downto Y2'low-4); - signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); - constant MEQ3:BOOLEAN:=M=3; - begin ---2008 RND<=TO_SFIXED(2.0**(O.RE'low-1),RND) when ROUNDING else (others=>'0'); - RND<=TO_SFIXED(2.0**(O'low/2-1),RND) when ROUNDING else (others=>'0'); - process(CLK) - begin - if rising_edge(CLK) then ---2008 X2<=I.RE; ---2008 Y2<=I.IM; - X2<=RE(I); - Y2<=IM(I); - end if; - end process; - - I_1<=SHIFT_RIGHT(I,1); - I_6<=SHIFT_RIGHT(I,6); - I_14<=SHIFT_RIGHT(I,14); - X1_2<=SHIFT_RIGHT(X1,2); - X2_4<=SHIFT_RIGHT(X2,4); - Y1_2<=SHIFT_RIGHT(Y1,2); - Y2_4<=SHIFT_RIGHT(Y2,4); - I_1RE<=RE(I_1); - I_6RE<=RE(I_6); - I_14RE<=RE(I_14); - - a1:entity work.CSA3 generic map(DSP48E=>DSP48E, - EXTRA_MSBs=>0) - port map(CLK=>CLK, ---2008 A=>I_1.RE, ---2008 B=>I_6.RE, ---2008 C=>I_14.RE, - A=>I_1RE, - B=>I_6RE, - C=>I_14RE, - P=>X1); -- P=C+A+B - - a2:entity work.CSA3 generic map(DSP48E=>DSP48E, - EXTRA_MSBs=>0) - port map(CLK=>CLK, - A=>X1, - B=>X1_2, - C=>X2_4, - P=>KIRE); -- P=C+A+B - - I_1IM<=IM(I_1); - I_6IM<=IM(I_6); - I_14IM<=IM(I_14); - a3:entity work.CSA3 generic map(DSP48E=>DSP48E, - EXTRA_MSBs=>0) - port map(CLK=>CLK, ---2008 A=>I_1.IM, ---2008 B=>I_6.IM, ---2008 C=>I_14.IM, - A=>I_1IM, - B=>I_6IM, - C=>I_14IM, - P=>Y1); -- P=C+A+B - - a4:entity work.CSA3 generic map(DSP48E=>DSP48E, - EXTRA_MSBs=>0) - port map(CLK=>CLK, - A=>Y1, - B=>Y1_2, - C=>Y2_4, - P=>KIIM); -- P=C+A+B - - a5:entity work.CSA3 generic map(DSP48E=>DSP48E, - NEGATIVE_A=>MEQ3, --2008 M=3, - NEGATIVE_B=>CONJUGATE, - EXTRA_MSBs=>0) - port map(CLK=>CLK, - A=>KIRE, - B=>KIIM, - C=>RND, - CY1=>MEQ3, --2008 M=3, - CY2=>CONJUGATE, ---2008 P=>O.RE); -- P=C+A+B - P=>ORE); -- P=C+A+B - - a6:entity work.CSA3 generic map(DSP48E=>DSP48E, - NEGATIVE_A=>nCONJUGATE, - NEGATIVE_B=>MEQ3, --2008 M=3, - EXTRA_MSBs=>0) - port map(CLK=>CLK, - A=>KIRE, - B=>KIIM, - C=>RND, - CY1=>nCONJUGATE, - CY2=>MEQ3, --2008 M=3, ---2008 P=>O.IM); -- P=C+A+B - P=>OIM); -- P=C+A+B - O<=TO_CFIXED(ORE,OIM); - --end; - end generate; -end TEST; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - --- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 ------------------------------------------------------------------------------------------------ --- Copyright 2018 Xilinx, Inc. All rights reserved. --- This file contains confidential and proprietary information of Xilinx, Inc. and is --- protected under U.S. and international copyright and other intellectual property laws. ------------------------------------------------------------------------------------------------ --- --- Disclaimer: --- This disclaimer is not a license and does not grant any rights to the materials --- distributed herewith. Except as otherwise provided in a valid license issued to you --- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS --- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL --- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED --- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR --- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including --- negligence, or under any other theory of liability) for any loss or damage of any --- kind or nature related to, arising under or in connection with these materials, --- including for any direct, or any indirect, special, incidental, or consequential --- loss or damage (including loss of data, profits, goodwill, or any type of loss or --- damage suffered as a result of any action brought by a third party) even if such --- damage or loss was reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail-safe, or for use in any --- application requiring fail-safe performance, such as life-support or safety devices --- or systems, Class III medical devices, nuclear facilities, applications related to --- the deployment of airbags, or any other applications that could lead to death, --- personal injury, or severe property or environmental damage (individually and --- collectively, "Critical Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical Applications, subject only to --- applicable laws and regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. --- --- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx --- Worldwide Technical Support (WTS), for support please contact the author --- ____ ____ --- / /\/ / --- /___/ \ / Vendor: Xilinx Inc. --- \ \ \/ Version: 0.14 --- \ \ Filename: ADDSUB.vhd --- / / Date Last Modified: 16 Apr 2018 --- /___/ /\ Date Created: --- \ \ / \ --- \___\/\___\ --- --- Device: Any UltraScale Xilinx FPGA --- Author: Catalin Baetoniu --- Entity Name: PARFFT --- Purpose: Generic Add/Subtract Module --- --- Revision History: --- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support --------------------------------------------------------------------------------- --- --- Module Description: Generic, Arbitrary Size, Parallel FFT Module --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.NUMERIC_STD.all; - -use work.COMPLEX_FIXED_PKG.all; - -library UNISIM; -use UNISIM.VComponents.all; - -entity ADDSUB is - generic(PIPELINE:BOOLEAN:=TRUE; - DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ - EXTRA_MSBs:INTEGER:=1); - port(CLK:in STD_LOGIC:='0'; --- A,B:in SIGNED; -- if SIGNED, A, B and P must be LSB aligned - A,B:in SFIXED; -- if SFIXED, A, B and P can be any size - SUB:in BOOLEAN:=FALSE; --- P:out SIGNED); -- O=AB - P:out SFIXED); -- O=AB -end ADDSUB; - -architecture FAST of ADDSUB is - constant SH:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'high,B'high)+EXTRA_MSBs; - constant SM:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'low,B'low); - constant SL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(A'low,B'low); --- signal SA,SB,M:SIGNED(SH downto SM); --- signal S:SIGNED(SH downto SL); - signal SA,SB:SFIXED(SH downto SM); - signal S:SFIXED(SH+1 downto SL); - - signal O5:SIGNED(SH-SM downto 0); - signal O6:SIGNED(SH-SM downto 0); - signal CY:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8 downto 0); - signal SI,DI,O:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8-1 downto 0); -begin - SA<=RESIZE(A,SA); - SB<=RESIZE(B,SB); - CY(0)<='1' when SUB else '0'; - lk:for K in SM to SH generate - constant I0:BIT_VECTOR(63 downto 0):=X"AAAAAAAAAAAAAAAA"; - constant I1:BIT_VECTOR(63 downto 0):=X"CCCCCCCCCCCCCCCC"; - constant I2:BIT_VECTOR(63 downto 0):=X"F0F0F0F0F0F0F0F0"; - constant I3:BIT_VECTOR(63 downto 0):=X"FF00FF00FF00FF00"; - constant I4:BIT_VECTOR(63 downto 0):=X"FFFF0000FFFF0000"; - constant I5:BIT_VECTOR(63 downto 0):=X"FFFFFFFF00000000"; - signal I_4:STD_LOGIC; - begin - I_4<='1' when SUB else '0'; - l6:LUT6_2 generic map(INIT=>(I5 and (I2 xor I3 xor I4)) or (not I5 and ((I2 xor I4) and I3))) - port map(I0=>'0',I1=>'0',I2=>SB(K),I3=>SA(K),I4=>I_4,I5=>'1',O5=>O5(K-SM),O6=>O6(K-SM)); - end generate; - - SI<=STD_LOGIC_VECTOR(RESIZE(O6,SI'length)); - DI<=STD_LOGIC_VECTOR(RESIZE(O5,DI'length)); - lj:for J in 0 to (SH-SM)/8 generate - begin - i1:if DSP48E=1 generate -- 7-series - cl:CARRY4 port map(CI=>CY(8*J), -- 1-bit carry cascade input - CYINIT=>'0', -- 1-bit carry initialization - DI=>DI(8*J+3 downto 8*J), -- 4-bit carry-MUX data in - S=>SI(8*J+3 downto 8*J), -- 4-bit carry-MUX select input - CO=>CY(8*J+4 downto 8*J+1), -- 4-bit carry out - O=>O(8*J+3 downto 8*J)); -- 4-bit carry chain XOR data out - ch:CARRY4 port map(CI=>CY(8*J+4), -- 1-bit carry cascade input - CYINIT=>'0', -- 1-bit carry initialization - DI=>DI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX data in - S=>SI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX select input - CO=>CY(8*J+8 downto 8*J+5), -- 4-bit carry out - O=>O(8*J+7 downto 8*J+4)); -- 4-bit carry chain XOR data out - end generate; - i2:if DSP48E=2 generate -- US/US+ - c8:CARRY8 generic map(CARRY_TYPE=>"SINGLE_CY8") -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8) - port map(CI=>CY(8*J), -- 1-bit input: Lower Carry-In - CI_TOP=>'0', -- 1-bit input: Upper Carry-In - DI=>DI(8*J+7 downto 8*J), -- 8-bit input: Carry-MUX data in - S=>SI(8*J+7 downto 8*J), -- 8-bit input: Carry-mux select - CO=>CY(8*J+8 downto 8*J+1), -- 8-bit output: Carry-out - O=>O(8*J+7 downto 8*J)); -- 8-bit output: Carry chain XOR data out - end generate; - end generate; - --- ll:for L in SM to SH+1 generate - ll:for L in SM to SH generate --- S(L)<=O(L-SM+1); - S(L)<=O(L-SM); - end generate; - S(SH+1)<=S(SH); - - ia:if A'low'0'); - begin - process(CLK) - begin - if rising_edge(CLK) then - iP<=RESIZE(S,P'high,P'low); - end if; - end process; - P<=iP; - end generate; -end FAST; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - --- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 ------------------------------------------------------------------------------------------------ --- © Copyright 2018 Xilinx, Inc. All rights reserved. --- This file contains confidential and proprietary information of Xilinx, Inc. and is --- protected under U.S. and international copyright and other intellectual property laws. ------------------------------------------------------------------------------------------------ --- --- Disclaimer: --- This disclaimer is not a license and does not grant any rights to the materials --- distributed herewith. Except as otherwise provided in a valid license issued to you --- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS --- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL --- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED --- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR --- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including --- negligence, or under any other theory of liability) for any loss or damage of any --- kind or nature related to, arising under or in connection with these materials, --- including for any direct, or any indirect, special, incidental, or consequential --- loss or damage (including loss of data, profits, goodwill, or any type of loss or --- damage suffered as a result of any action brought by a third party) even if such --- damage or loss was reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail-safe, or for use in any --- application requiring fail-safe performance, such as life-support or safety devices --- or systems, Class III medical devices, nuclear facilities, applications related to --- the deployment of airbags, or any other applications that could lead to death, --- personal injury, or severe property or environmental damage (individually and --- collectively, "Critical Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical Applications, subject only to --- applicable laws and regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. --- --- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx --- Worldwide Technical Support (WTS), for support please contact the author --- ____ ____ --- / /\/ / --- /___/ \ / Vendor: Xilinx Inc. --- \ \ \/ Version: 0.14 --- \ \ Filename: TABLE.vhd --- / / Date Last Modified: 16 Apr 2018 --- /___/ /\ Date Created: --- \ \ / \ --- \___\/\___\ --- --- Device: Any UltraScale Xilinx FPGA --- Author: Catalin Baetoniu --- Entity Name: TABLE --- Purpose: Generic Parallel FFT Module (powers of 2 only) --- --- Revision History: --- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support --------------------------------------------------------------------------------- --- --- Module Description: Generic, Arbitrary Size, SinCos Table Module --- --- Latency is always 2 --- when INV_FFT=FALSE W=exp(-2.0*PI*i*JK/N) and when INV_FFT=TRUE W=exp(2.0*PI*i*JK/N) --- to maximize W output bit size utilization W.RE and W.IM are always negative (MSB='1') and that bit could be ignored, this is why W.RE'length can be 19 bits but a single BRAM would still be used --- when W.RE or W.IM need to be positive CS respectively SS are TRUE, same thing when they are 0.0 CZ respectively SZ are TRUE - the complex multiplier has to use CS, SS, CZ and SZ, not just W to produce the correct result --- the SIN and COS ROM table sizes are N/4 deep and W.RE'length-1 wide (it is implictly assumed that W.RE and W.IM always have the same range) --- if STYLE="block" a single dual port BRAM is used for both tables --- if STYLE="distributed" then two fabric LUT based ROMs are used --- as a general rule for N<2048 "distributed" should be used, otherwise "block" makes more sense but this is not a hard rule --- W range is unconstrained but W.RE'high and W.IM'high really have to be 0 all the time, do not use other values --- the maximum SNR without using extra BRAMs is achieved when W.RE'low and W.IM'low are -18 so W.RE'length and W.IM'length are 19 bits but they can be less than that - this would reduce SNR and save resources only when STYLE="distributed" --- TABLE.VHD also works with more than 19 bits but the current complex multiplier implementation does not support that - this would essentially double the number of BRAMs and DSP48s used and seems too high a price to pay for a few extra dB of SNR --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.NUMERIC_STD.all; -use IEEE.MATH_REAL.all; - -use work.COMPLEX_FIXED_PKG.all; - ---!! entity TABLE is -- LATENCY=3 (2 if SEPARATE_SIGN is TRUE) -entity TABLE is -- LATENCY=4 (3 if SEPARATE_SIGN is TRUE) when SPLIT_RADIX=0 else LATENCY=0 - generic(N:INTEGER:=1024; - SPLIT_RADIX:INTEGER:=0; -- 0 for use in systolic FFT and J*1 or J*3 with J>0 for use in parallel Split Radix FFT - INV_FFT:BOOLEAN:=FALSE; - SEPARATE_SIGN:BOOLEAN:=FALSE; - DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ - STYLE:STRING:="block"); -- use only "block" or "distributed" - port(CLK:in STD_LOGIC; - JK:in UNSIGNED; - VI:in BOOLEAN; - W:out CFIXED; - CS,SS,CZ,SZ:out BOOLEAN; - VO:out BOOLEAN); -end TABLE; - -architecture TEST of TABLE is ---2008 constant WH:INTEGER:=W.RE'high-1+BOOLEAN'pos(SEPARATE_SIGN); ---2008 constant WL:INTEGER:=W.RE'low; -- SNR=110.06dB with WL=-17 and 116.27dB with WL=-18 - constant WH:INTEGER:=(W'high+1)/2-1-1+BOOLEAN'pos(SEPARATE_SIGN); - constant WL:INTEGER:=W'low/2; -- SNR=110.06dB with WL=-17 and 116.27dB with WL=-18 -begin - i0:if SPLIT_RADIX=0 generate - type wSFIXED_VECTOR is array(INTEGER range <>) of SFIXED(WH-1 downto WL); -- local constrained array of SFIXED type ---2008 function LUT_VALUE(N,WH,WL:INTEGER) return SFIXED_VECTOR is ---2008 variable RESULT:SFIXED_VECTOR(0 to N/4-1)(WH-1 downto WL); - function LUT_VALUE(N,WH,WL:INTEGER) return wSFIXED_VECTOR is - variable RESULT:wSFIXED_VECTOR(0 to N/4-1); - begin - RESULT(0):=TO_SFIXED(-1.0,WH,WL)(WH-1 downto WL); -- round and drop MSB, it is always 1 - for J in 1 to N/4-1 loop - RESULT(J):=TO_SFIXED(-COS(-2.0*MATH_PI*REAL(J)/REAL(N))+2.0**(WL-1),WH,WL)(WH-1 downto WL); -- round and drop MSB, it is always 1 - if RESULT(J)=TO_SFIXED(-1.0,WH,WL)(WH-1 downto WL) then - RESULT(J):=TO_SFIXED(-1.0+2.0**WL,WH,WL)(WH-1 downto WL); - end if; - end loop; - return RESULT; - end; - - signal JKD:UNSIGNED(JK'range):=(others=>'0'); - signal KC,KS:UNSIGNED(JK'range):=(others=>'0');--!! - signal DC,C,DS,S:SFIXED(WH-1 downto WL):=(others=>'0'); ---2008 signal LUT:SFIXED_VECTOR(0 to N/4-1)(WH-1 downto WL):=LUT_VALUE(N,WH,WL); - signal LUT:wSFIXED_VECTOR(0 to N/4-1):=LUT_VALUE(N,WH,WL); - attribute rom_style:STRING; - attribute rom_style of LUT:signal is STYLE; - signal RC,RS:BOOLEAN:=FALSE; - signal MC,MS:STD_LOGIC:='0'; - signal CS1,SS1,CS2,SS2:BOOLEAN:=FALSE; - signal W_RE,W_IM:SFIXED((W'high+1)/2-1 downto W'low/2); - begin - process(CLK) - begin - if rising_edge(CLK) then ---!! ---2008 KC<=JK when JK(JK'high-1)='0' else (not JK)+1; ---2008 KS<=(not JK)+1 when JK(JK'high-1)='0' else JK; - if JK(JK'high-1)='0' then - KC<=JK; - KS<=(not JK)+1; - else - KC<=(not JK)+1; - KS<=JK; - end if; - JKD<=JK; - if (JKD and TO_UNSIGNED(2**(JK'length-2)-1,JK'length))=0 then --mask first two MSBs of JK - RC<=JKD(JK'high-1)='1'; - RS<=JKD(JK'high-1)='0'; - else - RC<=FALSE; - RS<=FALSE; - end if; - DC<=LUT(TO_INTEGER(KC and TO_UNSIGNED(2**(KC'length-2)-1,KC'length))); - DS<=LUT(TO_INTEGER(KS and TO_UNSIGNED(2**(KS'length-2)-1,KS'length))); - if RC then - C<=(others=>'0'); - MC<='0'; - else - C<=DC; - MC<='1'; - end if; - if RS then - S<=(others=>'0'); - MS<='0'; - else - S<=DS; - MS<='1'; - end if; - CS1<=JKD(JK'high)=JKD(JK'high-1); - SS1<=(JKD(JK'high)='1') xor INV_FFT; - CS2<=CS1; - SS2<=SS1; - end if; - end process; - - i0:if SEPARATE_SIGN generate ---2008 W.RE<=MC&C; ---2008 W.IM<=MS&S; - W(W'length/2-1+W'low downto W'low)<=CFIXED(MC&C); - W(W'high downto W'length/2+W'low)<=CFIXED(MS&S); - CS<=CS2; - SS<=SS2; --- else generate - end generate; - i1:if not SEPARATE_SIGN generate - signal WRE,WIM:SFIXED(WH downto WL):=(others=>'0'); - attribute keep:STRING; - attribute keep of WRE:signal is "yes"; - attribute keep of WIM:signal is "yes"; - signal ZERO:SFIXED(WH downto WL):=TO_SFIXED(0.0,WH,WL); - begin - WRE<=MC&C; - WIM<=MS&S; - - process(CLK) - begin - if rising_edge(CLK) then - CS<=CS2; - SS<=SS2; - CZ<=WRE(WRE'high)='0'; - SZ<=WIM(WIM'high)='0'; - end if; - end process; - ar:entity work.ADDSUB generic map(DSP48E=>DSP48E) - port map(CLK=>CLK, - A=>ZERO, - B=>WRE, - SUB=>CS2, ---2008 P=>W.RE); -- P=±B - P=>W_RE); -- P=±B - ai:entity work.ADDSUB generic map(DSP48E=>DSP48E) - port map(CLK=>CLK, - A=>ZERO, - B=>WIM, - SUB=>SS2, ---2008 P=>W.IM); -- P=±B - P=>W_IM); -- P=±B - W(W'length/2-1+W'low downto W'low)<=CFIXED(W_RE); - W(W'high downto W'length/2+W'low)<=CFIXED(W_IM); --- end; - end generate; - ---!! b2:entity work.BDELAY generic map(SIZE=>3-BOOLEAN'pos(SEPARATE_SIGN)) - b2:entity work.BDELAY generic map(SIZE=>4-BOOLEAN'pos(SEPARATE_SIGN)) - port map(CLK=>CLK, - I=>VI, - O=>VO); --- end; - end generate; --- else generate - i1:if SPLIT_RADIX>0 generate - begin - i0:if SEPARATE_SIGN generate ---2008 W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W); - W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W'high/2,W'low/2); - CS<=FALSE; - SS<=FALSE; - end generate; --- else generate - ii:if not SEPARATE_SIGN generate - begin ---2008 W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W); - W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W'high/2,W'low/2); - CS<=FALSE; - SS<=FALSE; - CZ<=(SPLIT_RADIX=N/4) or (SPLIT_RADIX=3*N/4); - SZ<=(SPLIT_RADIX=0) or (SPLIT_RADIX=N/2); --- end; - end generate; - VO<=VI; - end generate; -end TEST; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - --- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 ------------------------------------------------------------------------------------------------ --- © Copyright 2018 Xilinx, Inc. All rights reserved. --- This file contains confidential and proprietary information of Xilinx, Inc. and is --- protected under U.S. and international copyright and other intellectual property laws. ------------------------------------------------------------------------------------------------ --- --- Disclaimer: --- This disclaimer is not a license and does not grant any rights to the materials --- distributed herewith. Except as otherwise provided in a valid license issued to you --- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS --- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL --- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED --- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR --- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including --- negligence, or under any other theory of liability) for any loss or damage of any --- kind or nature related to, arising under or in connection with these materials, --- including for any direct, or any indirect, special, incidental, or consequential --- loss or damage (including loss of data, profits, goodwill, or any type of loss or --- damage suffered as a result of any action brought by a third party) even if such --- damage or loss was reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail-safe, or for use in any --- application requiring fail-safe performance, such as life-support or safety devices --- or systems, Class III medical devices, nuclear facilities, applications related to --- the deployment of airbags, or any other applications that could lead to death, --- personal injury, or severe property or environmental damage (individually and --- collectively, "Critical Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical Applications, subject only to --- applicable laws and regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. --- --- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx --- Worldwide Technical Support (WTS), for support please contact the author --- ____ ____ --- / /\/ / --- /___/ \ / Vendor: Xilinx Inc. --- \ \ \/ Version: 0.14 --- \ \ Filename: CM3.vhd --- / / Date Last Modified: 16 Apr 2018 --- /___/ /\ Date Created: --- \ \ / \ --- \___\/\___\ --- --- Device: Any UltraScale Xilinx FPGA --- Author: Catalin Baetoniu --- Entity Name: CM3 --- Purpose: Generic Parallel FFT Module (powers of 2 only) --- --- Revision History: --- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support --------------------------------------------------------------------------------- --- --- Module Description: Complex Multiplier Using 3 DSP48E2s --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.NUMERIC_STD.all; - -use work.COMPLEX_FIXED_PKG.all; - -entity CM3 is -- LATENCY=6 - generic(ROUNDING:BOOLEAN:=FALSE; - DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 - port(CLK:in STD_LOGIC; - I:in CFIXED; -- I.RE'length and I.IM'length<27 - W:in CFIXED; -- W must be (1 downto -16) or (1 downto -17) - CS,SS,CZ,SZ:in BOOLEAN:=FALSE; - VI:in BOOLEAN; - O:out CFIXED; - VO:out BOOLEAN); -end CM3; - -architecture TEST of CM3 is - attribute keep_hierarchy:STRING; - attribute keep_hierarchy of all:architecture is "yes"; - attribute syn_hier:STRING; - attribute syn_hier of all:architecture is "hard"; - attribute loc:STRING; - ---2008 constant HMAX:INTEGER:=MAX(I.RE'high,I.IM'high)+MAX(W.RE'high,W.IM'high)+3; ---2008 constant LMIN:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(I.RE'low,I.IM'low)+work.COMPLEX_FIXED_PKG.MIN(W.RE'low,W.IM'low); - constant HMAX:INTEGER:=(I'high+1)/2-1+(W'high+1)/2-1+3; - constant LMIN:INTEGER:=I'low/2+W'low/2; - --- signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W.RE'high,1) downto MAX(W.RE'low,-16)); --- signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W.RE'high,0) downto MAX(W.RE'low,-17)); ---2008 signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W.RE'low+17,1) downto W.RE'low); -- we only have 18 bits max to work with ---2008 signal WRE1D,nWRE2D:SFIXED(WRE'range):=TO_SFIXED(0.0,WRE'high,WRE'low); ---2008 signal IRE1D,IRE2D:SFIXED(I.IM'range):=TO_SFIXED(0.0,I.RE'high,I.RE'low); ---2008 signal IIM1D,IIM2D:SFIXED(I.IM'range):=TO_SFIXED(0.0,I.IM'high,I.IM'low); - signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W'low/2+17,1) downto W'low/2); -- we only have 18 bits max to work with - signal WRE1D,nWRE2D:SFIXED(WRE'range):=TO_SFIXED(0.0,WRE'high,WRE'low); - signal IRE,IRE1D,IRE2D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); - signal IIM,IIM1D,IIM2D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); - signal CS2D,SS2D:BOOLEAN; - signal C0S1:BOOLEAN:=FALSE; - signal P1,P2,P3:SFIXED(HMAX downto LMIN); - signal P2D:SFIXED(HMAX downto LMIN):=(others=>'0'); - signal C1,C2,C3:SFIXED(HMAX downto LMIN):=(others=>'0'); - signal AC1,AC2:STD_LOGIC_VECTOR(29 downto 0); - signal BC1:STD_LOGIC_VECTOR(17 downto 0); - signal PC1,PC2:STD_LOGIC_VECTOR(47 downto 0); ---2008 signal A_ZERO:SFIXED(I.RE'range):=TO_SFIXED(0.0,I.RE'high,I.RE'low); - signal A_ZERO:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); - signal B_ZERO:SFIXED(WRE'range):=TO_SFIXED(0.0,WRE'high,WRE'low); - signal C_ZERO:SFIXED(HMAX downto LMIN):=TO_SFIXED(0.0,HMAX,LMIN); - signal BR,BI:BOOLEAN; - signal iO:CFIXED(O'range); -begin ---!! ---2008 WRE<=RESIZE(W.RE,WRE); - WRE<=RESIZE(RE(W),WRE); ---!! WRE<=TO_SFIXED(1.0-2.0**WRE'low,WRE) when W.RE=TO_SFIXED(1.0,W.RE) else RESIZE(W.RE,WRE); ---!! ---2008 WIM<=RESIZE(W.IM,WIM); - WIM<=RESIZE(IM(W),WIM); - process(CLK) - begin - if rising_edge(CLK) then - WRE1D<=WRE; ---2008 IRE1D<=I.RE; ---2008 IIM1D<=I.IM; - IRE1D<=RE(I); - IIM1D<=IM(I); ---2008 C0S1<=CZ and (W.IM(W.IM'high)='0'); - C0S1<=CZ and (W(W'high)='0'); ---!! - NWRE2D<=RESIZE(-WRE1D,NWRE2D); ---!! if WRE1D=TO_SFIXED(-1.0,WRE1D) then ---!! for K in NWRE2D'range loop ---!! NWRE2D(K)<=not WRE1D(K); ---!! end loop; ---!! else ---!! NWRE2D<=RESIZE(-WRE1D,NWRE2D); ---!! end if; ---!! - IRE2D<=IRE1D; - IIM2D<=IIM1D; - end if; - end process; - - process(CLK) - begin - if rising_edge(CLK) then ---2008 if (W.RE'low=-17) and C0S1 then - if (W'low/2=-17) and C0S1 then - C1<=RESIZE(SHIFT_LEFT(IRE1D+IIM1D,1),C1); - else - C1<=TO_SFIXED(0.0,C1); - end if; - end if; - end process; - - IRE<=RE(I); - IIM<=IM(I); - dsp1:entity work.DSP48E2GW generic map(DSP48E=>DSP48E, -- 1 for DSP48E1, 2 for DSP48E2 - AMULTSEL=>"AD", -- Selects A input to multiplier (A, AD) - BREG=>2) -- Pipeline stages for B (0-2) - port map(CLK=>CLK, - INMODE=>"00101", -- (D+A1)*B2 - ALUMODE=>"0011", -- Z-W-X-Y - OPMODE=>"110000101", -- PCOUT=-C-(D+A1)*B2 ---2008 A=>I.RE, - A=>IRE, - B=>WIM, - C=>C1, ---2008 D=>I.IM, - D=>IIM, - ACOUT=>AC1, - BCOUT=>BC1, - P=>P1, - PCOUT=>PC1); - --- C2<=TO_SFIXED(2.0**(O.RE'low-1),C2) when ROUNDING else TO_SFIXED(0.0,C2); - BR<=W(W'length/2-1+W'low)='0'; - BI<=W(W'high)='0'; - cd:entity work.BDELAY generic map(SIZE=>2) - port map(CLK=>CLK, ---2008 I=>W.RE(W.RE'high)='0', - I=>BR, - O=>CS2D); - sd:entity work.BDELAY generic map(SIZE=>2) - port map(CLK=>CLK, ---2008 I=>W.IM(W.IM'high)='0', - I=>BI, - O=>SS2D); - process(CLK) - begin - if rising_edge(CLK) then ---2008 if (W.RE'low=-17) and CS2D=SS2D then - if (W'low/2=-17) and CS2D=SS2D then - if CS2D then - if ROUNDING then ---2008 C2<=RESIZE(TO_SFIXED(2.0**(O.RE'low-1),C2)+SHIFT_LEFT(IRE2D,1),C2); - C2<=RESIZE(TO_SFIXED(2.0**(O'low/2-1),C2)+SHIFT_LEFT(IRE2D,1),C2); - else ---2008 C2<=RESIZE(I.RE,C2); - C2<=RESIZE(SHIFT_LEFT(IRE2D,1),C2); - end if; - else - if ROUNDING then ---2008 C2<=RESIZE(TO_SFIXED(2.0**(O.RE'low-1),C2)-SHIFT_LEFT(IRE2D,1),C2); - C2<=RESIZE(TO_SFIXED(2.0**(O'low/2-1),C2)-SHIFT_LEFT(IRE2D,1),C2); - else ---2008 C2<=RESIZE(-I.RE,C2); - C2<=RESIZE(-SHIFT_LEFT(IRE2D,1),C2); - end if; - end if; - else - if ROUNDING then ---2008 C2<=TO_SFIXED(2.0**(O.RE'low-1),C2); - C2<=TO_SFIXED(2.0**(O'low/2-1),C2); - else - C2<=TO_SFIXED(0.0,C2); - end if; - end if; - end if; - end process; - - dsp2:entity work.DSP48E2GW generic map(DSP48E=>DSP48E, -- 1 for DSP48E1, 2 for DSP48E2 - A_INPUT=>"CASCADE", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) - BMULTSEL=>"AD", -- Selects B input to multiplier (AD, B) - B_INPUT=>"CASCADE", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) - PREADDINSEL=>"B", -- Selects input to preadder (A, B) - AREG=>2) -- Pipeline stages for A (0-2) - port map(CLK=>CLK, - INMODE=>"10100", -- (D+B1)*A2 - ALUMODE=>"0000", -- Z+W+X+Y - OPMODE=>"110010101", -- PCOUT=PCIN+C+(D+B1)*A2 - A=>A_ZERO, - B=>B_ZERO, - C=>C2, - D=>WRE1D, - ACIN=>AC1, - BCIN=>BC1, - PCIN=>PC1, - ACOUT=>AC2, - P=>P2, - PCOUT=>PC2); - --- C3<=RESIZE(SHIFT_RIGHT(P1,-16-W.RE'low),P1); - C3<=P1; - dsp3:entity work.DSP48E2GW generic map(DSP48E=>DSP48E, -- 1 for DSP48E1, 2 for DSP48E2 - AMULTSEL=>"AD", -- Selects A input to multiplier (A, AD) - A_INPUT=>"CASCADE", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) - BREG=>2) -- Pipeline stages for B (0-2) - port map(CLK=>CLK, - INMODE=>"01101", --5x"0C", -- (D-A1)*B2 - ALUMODE=>"0011", -- Z-W-X-Y - OPMODE=>"110010101", -- PCOUT=PCIN-C-(D-A1)*B2 - A=>A_ZERO, - B=>NWRE2D, - C=>C3, - D=>IIM2D, - ACIN=>AC2, - PCIN=>PC2, - P=>P3); - - process(CLK) - begin - if rising_edge(CLK) then ---2008 O.RE<=RESIZE(P2,O.RE); - P2D<=P2; - end if; - end process; ---2008 O.IM<=RESIZE(P3,O.IM); --- O<=RESIZE(TO_CFIXED(P2D,P3),O); - O<=RESIZE(TO_CFIXED(P2D,P3),iO); - - bd:entity work.BDELAY generic map(SIZE=>6) - port map(CLK=>CLK, - I=>VI, - O=>VO); -end TEST; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - --- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 ------------------------------------------------------------------------------------------------ --- © Copyright 2018 Xilinx, Inc. All rights reserved. --- This file contains confidential and proprietary information of Xilinx, Inc. and is --- protected under U.S. and international copyright and other intellectual property laws. ------------------------------------------------------------------------------------------------ --- --- Disclaimer: --- This disclaimer is not a license and does not grant any rights to the materials --- distributed herewith. Except as otherwise provided in a valid license issued to you --- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS --- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL --- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED --- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR --- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including --- negligence, or under any other theory of liability) for any loss or damage of any --- kind or nature related to, arising under or in connection with these materials, --- including for any direct, or any indirect, special, incidental, or consequential --- loss or damage (including loss of data, profits, goodwill, or any type of loss or --- damage suffered as a result of any action brought by a third party) even if such --- damage or loss was reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail-safe, or for use in any --- application requiring fail-safe performance, such as life-support or safety devices --- or systems, Class III medical devices, nuclear facilities, applications related to --- the deployment of airbags, or any other applications that could lead to death, --- personal injury, or severe property or environmental damage (individually and --- collectively, "Critical Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical Applications, subject only to --- applicable laws and regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. 3 --- --- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx --- Worldwide Technical Support (WTS), for support please contact the author --- ____ ____ --- / /\/ / --- /___/ \ / Vendor: Xilinx Inc. --- \ \ \/ Version: 0.14 --- \ \ Filename: CM3FFT.vhd --- / / Date Last Modified: 16 Apr 2018 --- /___/ /\ Date Created: --- \ \ / \ --- \___\/\___\ --- --- Device: Any UltraScale Xilinx FPGA --- Author: Catalin Baetoniu --- Entity Name: CM3FFT --- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) --- --- Revision History: --- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support --------------------------------------------------------------------------------- --- --- Module Description: Generic Complex Multiplier Stage Module - uses 3 DSP48s/complex multiplication --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.NUMERIC_STD.all; - -use work.COMPLEX_FIXED_PKG.all; - -entity CM3FFT is -- LATENCY=10 - generic(N:INTEGER; - RADIX:INTEGER; - SPLIT_RADIX:INTEGER:=0; -- 0 for use in systolic FFT and 1 or 3 for use in parallel Split Radix FFT - INV_FFT:BOOLEAN:=FALSE; - W_high:INTEGER:=1; - W_low:INTEGER:=-17; - ROUNDING:BOOLEAN:=TRUE; - BRAM_THRESHOLD:INTEGER:=256; -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs - DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 - port(CLK:in STD_LOGIC; - I:in CFIXED_VECTOR; - VI:in BOOLEAN; - SI:in UNSIGNED; - O:out CFIXED_VECTOR; - VO:out BOOLEAN; - SO:out UNSIGNED); -end CM3FFT; - -architecture TEST of CM3FFT is - attribute syn_hier:STRING; - attribute syn_hier of all:architecture is "hard"; - attribute keep_hierarchy:STRING; - attribute keep_hierarchy of all:architecture is "yes"; - - function STYLE(N:INTEGER) return STRING is - begin - if N>BRAM_THRESHOLD then - return "block"; - else - return "distributed"; - end if; - end; - - function TABLE_LATENCY(SPLIT_RADIX:INTEGER) return INTEGER is - begin - if SPLIT_RADIX=0 then - return 4; - else - return 0; - end if; - end; - ---2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR - constant L2N:INTEGER:=LOG2(N); - constant L2R:INTEGER:=LOG2(RADIX); - signal CNT:UNSIGNED(L2N-L2R-1 downto 0):=(others=>'0'); - signal I0:CFIXED((I'high+1)/RADIX-1 downto I'low/RADIX); - signal O0:CFIXED((O'high+1)/RADIX-1 downto O'low/RADIX); -begin - assert I'length=O'length report "Ports I and O must have the same length!" severity warning; - assert SI'length=SO'length report "Ports SI and SO must have the same length!" severity warning; - ---!! cd:entity work.CDELAY generic map(SIZE=>3+6) - I0<=ELEMENT(I,0,RADIX); - cd:entity work.CDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)+6) - port map(CLK=>CLK, ---2008 I=>I(I'low), ---2008 O=>O(O'low)); - I=>I0, - O=>O0); - O(O'length/RADIX-1+O'low downto O'low)<=CFIXED_VECTOR(O0); - - process(CLK) - begin - if rising_edge(CLK) then - if not VI or (SPLIT_RADIX/=0) then - CNT<=(others=>'0'); - else - CNT<=CNT+1; - end if; - end if; - end process; - ---2008 lk:for J in 1 to I'length-1 generate - lk:for J in 1 to RADIX-1 generate - signal JK:UNSIGNED(L2N-1 downto 0):=(others=>'0'); ---2008 signal W:CFIXED(RE(W_high downto W_low),IM(W_high downto W_low)); - signal W:CFIXED(2*(W_high+1)-1 downto 2*W_low); - signal V,CZ:BOOLEAN; ---2008 signal ID:CFIXED(RE(I(I'low).RE'high downto I(I'low).RE'low),IM(I(I'low).IM'high downto I(I'low).IM'low)); - signal ID:CFIXED((I'high+1)/RADIX-1 downto I'low/RADIX); - signal IJ:CFIXED((I'high+1)/RADIX-1 downto I'low/RADIX); - signal OJ:CFIXED((O'high+1)/RADIX-1 downto O'low/RADIX); - begin - process(CLK) - begin - if rising_edge(CLK) then - if SPLIT_RADIX=0 then - if not VI or (CNT=N/RADIX-1) then - JK<=(others=>'0'); - else - JK<=JK+J; - end if; - else - JK<=TO_UNSIGNED(J*SPLIT_RADIX,JK'length); - end if; - end if; - end process; - - ut:entity work.TABLE generic map(N=>N, - INV_FFT=>INV_FFT, - DSP48E=>DSP48E, - STYLE=>STYLE(N/4)) - port map(CLK=>CLK, - JK=>JK, - VI=>VI, - CZ=>CZ, - W=>W, - VO=>V); - - IJ<=ELEMENT(I,J,RADIX); ---!! cd:entity work.CDELAY generic map(SIZE=>3) - cd:entity work.CDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)) - port map(CLK=>CLK, ---2008 I=>I(I'low+J), - I=>IJ, - O=>ID); - - u1:entity work.CM3 generic map(ROUNDING=>ROUNDING, - DSP48E=>DSP48E) - port map(CLK=>CLK, - I=>ID, - W=>W, - CZ=>CZ, - VI=>V, ---2008 O=>O(O'low+J), - O=>OJ, - VO=>open); - O((J+1)*O'length/RADIX-1+O'low downto J*O'length/RADIX+O'low)<=CFIXED_VECTOR(OJ); - end generate; - ---!! bd:entity work.BDELAY generic map(SIZE=>3+6) - bd:entity work.BDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)+6) - port map(CLK=>CLK, - I=>VI, - O=>VO); - ---!! ud:entity work.UDELAY generic map(SIZE=>3+6) - ud:entity work.UDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)+6) - port map(CLK=>CLK, - I=>SI, - O=>SO); -end TEST; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - --- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 ------------------------------------------------------------------------------------------------ --- © Copyright 2018 Xilinx, Inc. All rights reserved. --- This file contains confidential and proprietary information of Xilinx, Inc. and is --- protected under U.S. and international copyright and other intellectual property laws. ------------------------------------------------------------------------------------------------ --- --- Disclaimer: --- This disclaimer is not a license and does not grant any rights to the materials --- distributed herewith. Except as otherwise provided in a valid license issued to you --- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS --- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL --- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED --- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR --- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including --- negligence, or under any other theory of liability) for any loss or damage of any --- kind or nature related to, arising under or in connection with these materials, --- including for any direct, or any indirect, special, incidental, or consequential --- loss or damage (including loss of data, profits, goodwill, or any type of loss or --- damage suffered as a result of any action brought by a third party) even if such --- damage or loss was reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail-safe, or for use in any --- application requiring fail-safe performance, such as life-support or safety devices --- or systems, Class III medical devices, nuclear facilities, applications related to --- the deployment of airbags, or any other applications that could lead to death, --- personal injury, or severe property or environmental damage (individually and --- collectively, "Critical Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical Applications, subject only to --- applicable laws and regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. --- --- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx --- Worldwide Technical Support (WTS), for support please contact the author --- ____ ____ --- / /\/ / --- /___/ \ / Vendor: Xilinx Inc. --- \ \ \/ Version: 0.14 --- \ \ Filename: PARFFT.vhd --- / / Date Last Modified: 16 Apr 2018 --- /___/ /\ Date Created: --- \ \ / \ --- \___\/\___\ --- --- Device: Any UltraScale Xilinx FPGA --- Author: Catalin Baetoniu --- Entity Name: PARFFT --- Purpose: Generic Parallel FFT Module (powers of 2 only) --- --- Revision History: --- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support --------------------------------------------------------------------------------- --- --- Module Description: Generic, Arbitrary Size, Parallel FFT Module --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.NUMERIC_STD.all; -use ieee.math_real.all; -use ieee.math_complex.all; - -use work.COMPLEX_FIXED_PKG.all; - -entity PARFFT is - generic(N:INTEGER:=4; - F:INTEGER:=0; - INV_FFT:BOOLEAN:=FALSE; - ROUNDING:BOOLEAN:=FALSE; - W_high:INTEGER:=1; - W_low:INTEGER:=-16; - BRAM_THRESHOLD:INTEGER:=256; - DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 - port(CLK:in STD_LOGIC; - I:in CFIXED_VECTOR; - VI:in BOOLEAN; - SI:in UNSIGNED; - O:out CFIXED_VECTOR; - VO:out BOOLEAN; - SO:out UNSIGNED); -end PARFFT; - -architecture TEST of PARFFT is - constant I_low:INTEGER:=I'low/2/N; - constant I_high:INTEGER:=I'length/2/N-1+I_low; - constant O_low:INTEGER:=O'low/2/N; - constant O_high:INTEGER:=O'length/2/N-1+O_low; - - attribute syn_hier:STRING; - attribute syn_hier of all:architecture is "hard"; - attribute keep_hierarchy:STRING; - attribute keep_hierarchy of all:architecture is "yes"; - - constant L2N:INTEGER:=LOG2(N); -begin ---2008 assert I'length=O'length report "Ports I and O must have the same length!" severity warning; - assert SI'length=SO'length report "Ports SI and SO must have the same length!" severity warning; - - f0:if F=0 generate - begin - l2:if N=2 generate -- FFT2 case - signal I0,I1:CFIXED(2*I_high+1 downto 2*I_low); - signal O0,O1:CFIXED(2*O_high+1 downto 2*O_low); - signal iSO:UNSIGNED(SO'high-1 downto SO'low):=(others=>'0'); - begin --- unpack CFIXED_VECTOR I - I0<=ELEMENT(I,0,2); - I1<=ELEMENT(I,1,2); --- complex add/sub butterfly with scaling and overflow detection - bf:entity work.CBFS generic map(DSP48E=>DSP48E) - port map(CLK=>CLK, - I0=>I0, - I1=>I1, - SCALE=>SI(SI'low), - O0=>O0, - O1=>O1, - OVR=>SO(SO'high)); --- pack CFIXED_VECTOR O - O((0+1)*O'length/2-1+O'low downto 0*O'length/2+O'low)<=CFIXED_VECTOR(O0); - O((1+1)*O'length/2-1+O'low downto 1*O'length/2+O'low)<=CFIXED_VECTOR(O1); - - process(CLK) - begin - if rising_edge(CLK) then - iSO<=SI(SI'high downto SI'low+1); - end if; - end process; - SO(SO'high-1 downto SO'low)<=iSO; - - bd:entity work.BDELAY generic map(SIZE=>1) - port map(CLK=>CLK, - I=>VI, - O=>VO); --- end; - end generate; --- elsif N=4 generate -- FFT4 case - l4:if N=4 generate -- FFT4 case - signal I0,I1,I2,I3:CFIXED(2*I_high+1 downto 2*I_low); - signal P0,P1,P2,P3,P3S:CFIXED(2*I_high+3 downto 2*I_low); - signal O0,O1,O2,O3,O1S,O3S:CFIXED(2*O_high+1 downto 2*O_low); - signal S:UNSIGNED(SI'range):=(others=>'0'); - signal OVR1,OVR2:UNSIGNED(1 downto 0); - signal iSO:UNSIGNED(SO'high-1 downto SO'low):=(others=>'0'); - begin --- unpack CFIXED_VECTOR I - I0<=ELEMENT(I,0,4); - I1<=ELEMENT(I,1,4); - I2<=ELEMENT(I,2,4); - I3<=ELEMENT(I,3,4); --- complex add/sub butterflies with scaling and overflow detection - u0:entity work.CBFS generic map(DSP48E=>DSP48E) - port map(CLK=>CLK, - I0=>I0, - I1=>I2, - SCALE=>SI(SI'low), - O0=>P0, - O1=>P1, - OVR=>OVR1(0)); - - u1:entity work.CBFS generic map(DSP48E=>DSP48E) - port map(CLK=>CLK, - I0=>I1, - I1=>I3, - SCALE=>SI(SI'low), - O0=>P2, - O1=>P3, - OVR=>OVR1(1)); - - process(CLK) - begin - if rising_edge(CLK) then - S<=(OVR1(0) or OVR1(1))&SI(SI'high downto SI'low+1); - end if; - end process; - - u2:entity work.CBFS generic map(DSP48E=>DSP48E) - port map(CLK=>CLK, - I0=>P0, - I1=>P2, - SCALE=>S(S'low), - O0=>O0, - O1=>O2, - OVR=>OVR2(0)); - - P3S<=SWAP(P3); - u3:entity work.CBFS generic map(DSP48E=>DSP48E) - port map(CLK=>CLK, - I0=>P1, - I1=>P3S, - SCALE=>S(S'low), - O0=>O1S, - O1=>O3S, - OVR=>OVR2(1)); - O1<=TO_CFIXED(RE(O1S),IM(O3S)); - O3<=TO_CFIXED(RE(O3S),IM(O1S)); --- pack CFIXED_VECTOR O - O((0+1)*O'length/4-1+O'low downto 0*O'length/4+O'low)<=CFIXED_VECTOR(O0); - O((1+1)*O'length/4-1+O'low downto 1*O'length/4+O'low)<=CFIXED_VECTOR(O1); - O((2+1)*O'length/4-1+O'low downto 2*O'length/4+O'low)<=CFIXED_VECTOR(O2); - O((3+1)*O'length/4-1+O'low downto 3*O'length/4+O'low)<=CFIXED_VECTOR(O3); - - SO(SO'high)<=(OVR2(0) or OVR2(1)); - process(CLK) - begin - if rising_edge(CLK) then - iSO<=S(S'high downto S'low+1); - end if; - end process; - SO(SO'high-1 downto SO'low)<=iSO; - - bd:entity work.BDELAY generic map(SIZE=>2) - port map(CLK=>CLK, - I=>VI, - O=>VO); --- end; - end generate; --- elsif N=8 generate -- FFT8 case - l8:if N=8 generate -- FFT8 case ---2008 constant BIT_GROWTH:INTEGER:=MAX(O(O'low).RE'high,O(O'low).IM'high)-MAX(I(I'low).RE'high,I(I'low).IM'high); - constant BIT_GROWTH:INTEGER:=(O'high+1)/8/2-(I'high+1)/8/2; - constant X:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(BIT_GROWTH,1); -- ModelSim workaround - signal iV:BOOLEAN_VECTOR(0 to 3); ---2008 signal S:UNSIGNED_VECTOR(0 to 3)(SI'range); - type TUV is array(NATURAL range <>) of UNSIGNED(SI'range); - signal S:TUV(0 to 3); - signal SS:UNSIGNED(SI'range); - signal P:CFIXED_VECTOR(I'high+8*2*X downto I'low); - signal VP:BOOLEAN; - signal SP:UNSIGNED(SI'range); - signal oV:BOOLEAN_VECTOR(0 to 1); ---2008 signal oS:UNSIGNED_VECTOR(0 to 1)(SO'range); - signal oS:TUV(0 to 1); - begin - s1:for K in 0 to 3 generate ---2008 signal II:CFIXED_VECTOR(0 to 1)(RE(I(0).RE'high downto I(0).RE'low),IM(I(0).IM'high downto I(0).IM'low)); ---2008 signal OO:CFIXED_VECTOR(0 to 1)(RE(P(0).RE'high downto P(0).RE'low),IM(P(0).IM'high downto P(0).IM'low)); - signal II:CFIXED_VECTOR(4*(I_high+1)-1 downto 4*I_low); - signal OO:CFIXED_VECTOR(4*(I_high+1+2*X)-1 downto 4*I_low); - signal OO0,OO1:CFIXED(2*(I_high+1+2*X)-1 downto 2*I_low); - signal P0,P1:CFIXED(I'length/8+2*X-1+I'low/8 downto I'low/8); - signal SS:UNSIGNED(SI'range); - begin ---2008 II(0)<=I(K); ---2008 II(1)<=I(K+4); - II((0+1)*II'length/2-1+II'low downto 0*II'length/2+II'low)<=CFIXED_VECTOR(ELEMENT(I,K,8)); - II((1+1)*II'length/2-1+II'low downto 1*II'length/2+II'low)<=CFIXED_VECTOR(ELEMENT(I,K+4,8)); - p2:entity work.PARFFT generic map(N=>2, - INV_FFT=>INV_FFT, - ROUNDING=>ROUNDING, - W_high=>W_high, - W_low=>W_low, - BRAM_THRESHOLD=>BRAM_THRESHOLD, - DSP48E=>DSP48E) - port map(CLK=>CLK, - I=>II, - VI=>VI, - SI=>SI, - O=>OO, - VO=>iV(K), - SO=>S(K)); - OO0<=ELEMENT(OO,0,2); - OO1<=ELEMENT(OO,1,2); - cd:entity work.CDELAY generic map(SIZE=>3) - port map(CLK=>CLK, ---2008 I=>OO(0), ---2008 O=>P(2*K+0)); - I=>OO0, - O=>P0); - ck:entity work.CKCM generic map(DSP48E=>DSP48E, - M=>K, - ROUNDING=>ROUNDING, - CONJUGATE=>INV_FFT) - port map(CLK=>CLK, ---2008 I=>OO(1), ---2008 O=>P(2*K+1)); - I=>OO1, - O=>P1); - P((2*K+1)*P'length/8-1+P'low downto (2*K+0)*P'length/8+P'low)<=CFIXED_VECTOR(P0); - P((2*K+2)*P'length/8-1+P'low downto (2*K+1)*P'length/8+P'low)<=CFIXED_VECTOR(P1); - end generate; - SS(SI'high)<=S(0)(SI'high) or S(1)(SI'high) or S(2)(SI'high) or S(3)(SI'high) when iV(0) else '0'; - SS(SI'high-1 downto SI'low)<=S(0)(SI'high-1 downto SI'low); - ud:entity work.UDELAY generic map(SIZE=>3) - port map(CLK=>CLK, - I=>SS, - O=>SP); - bd:entity work.BDELAY generic map(SIZE=>3) - port map(CLK=>CLK, - I=>iV(0), - O=>VP); - s2:for K in 0 to 1 generate ---2008 signal II:CFIXED_VECTOR(0 to 3)(RE(P(0).RE'high downto P(0).RE'low),IM(P(0).IM'high downto P(0).IM'low)); ---2008 signal OO:CFIXED_VECTOR(0 to 3)(RE(O(0).RE'high downto O(0).RE'low),IM(O(0).IM'high downto O(0).IM'low)); - signal II:CFIXED_VECTOR((P'high+1)/2-1 downto P'low/2); - signal OO:CFIXED_VECTOR((O'high+1)/2-1 downto O'low/2); - signal SS:UNSIGNED(SI'range); - begin ---2008 II(0)<=P(K+0); ---2008 II(1)<=P(K+2); ---2008 II(2)<=P(K+4); ---2008 II(3)<=P(K+6); - II((0+1)*II'length/4-1+II'low downto 0*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+0,8)); - II((1+1)*II'length/4-1+II'low downto 1*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+2,8)); - II((2+1)*II'length/4-1+II'low downto 2*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+4,8)); - II((3+1)*II'length/4-1+II'low downto 3*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+6,8)); - p2:entity work.PARFFT generic map(N=>4, - INV_FFT=>INV_FFT, - ROUNDING=>ROUNDING, - W_high=>W_high, - W_low=>W_low, - BRAM_THRESHOLD=>BRAM_THRESHOLD, - DSP48E=>DSP48E) - port map(CLK=>CLK, - I=>II, - VI=>VP, - SI=>SP, - O=>OO, - VO=>oV(K), - SO=>oS(K)); ---2008 O(K+0)<=OO(0); ---2008 O(K+2)<=OO(1); ---2008 O(K+4)<=OO(2); ---2008 O(K+6)<=OO(3); - O((K+0+1)*O'length/8-1+O'low downto (K+0)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,0,4)); - O((K+2+1)*O'length/8-1+O'low downto (K+2)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,1,4)); - O((K+4+1)*O'length/8-1+O'low downto (K+4)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,2,4)); - O((K+6+1)*O'length/8-1+O'low downto (K+6)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,3,4)); - end generate; - VO<=oV(0); - SO(SO'high downto SO'high-1)<=oS(0)(SO'high downto SO'high-1) or oS(1)(SO'high downto SO'high-1) when oV(0) else "00"; - SO(SO'high-2 downto SO'low)<=oS(0)(SO'high-2 downto SO'low); --- end; - end generate; --- elsif N=2**L2N generate -- FFT2**n case using Split Radix decomposition, uses recursive PARFFT instantiation - ln:if (N>8) and (N=2**L2N) generate -- FFT2**n case using Split Radix decomposition, uses recursive PARFFT instantiation ---2008 constant BIT_GROWTH:INTEGER:=MAX(O(O'low).RE'high,O(O'low).IM'high)-MAX(I(I'low).RE'high,I(I'low).IM'high); - constant BIT_GROWTH:INTEGER:=(O'high+1)/N/2-(I'high+1)/N/2; - constant X1:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(0,work.COMPLEX_FIXED_PKG.MIN(BIT_GROWTH,L2N)-2); -- ModelSim workaround - constant X2:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(0,work.COMPLEX_FIXED_PKG.MIN(BIT_GROWTH,L2N)-1); -- ModelSim workaround - function MUL_LATENCY(N:INTEGER) return INTEGER is - begin - return 6; - end; - function LATENCY(N:INTEGER) return INTEGER is - begin - return LOG2(N)*4-6; - end; ---2008 signal IU:CFIXED_VECTOR(0 to N/2-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); ---2008 signal U,UD:CFIXED_VECTOR(0 to N/2-1)(RE(I(I'low).RE'high+X2 downto I(I'low).RE'low),IM(I(I'low).IM'high+X2 downto I(I'low).IM'low)); - signal IU:CFIXED_VECTOR((I'high+1)/2-1 downto I'low/2); - signal U,UD:CFIXED_VECTOR((I'high+1)/2-1+N/2*2*X2 downto I'low/2); - signal SU,SUD:UNSIGNED(SI'range); - signal VU,VU4D:BOOLEAN; ---2008 signal ZO:CFIXED_MATRIX(0 to N/4-1)(0 to 1)(RE(I(I'low).RE'high+X1 downto I(I'low).RE'low),IM(I(I'low).IM'high+X1 downto I(I'low).IM'low)); - type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR(2*2*(I_high+X1+1)-1 downto 2*2*I_low); -- unconstrained array of CFIXED_VECTOR - signal ZO:CFIXED_MATRIX(0 to N/4-1); - type TUV is array(NATURAL range <>) of UNSIGNED(SI'range); ---2008 signal S1:UNSIGNED_VECTOR(0 to 1)(SI'range); - signal S1:TUV(0 to 1); - signal S1I:UNSIGNED(SI'range); ---2008 signal S2:UNSIGNED_VECTOR(0 to N/4-1)(SI'range); - signal S2:TUV(0 to N/4-1); - signal S2I:UNSIGNED(SI'range):=(others=>'0'); ---2008 signal S:UNSIGNED_VECTOR(0 to N/2-1)(SI'range); - signal S:TUV(0 to N/2-1); - begin - lk:for K in 0 to N/2-1 generate ---2008 IU(K)<=I(I'low+2*K); - IU((K+1)*IU'length/N*2-1+IU'low downto K*IU'length/N*2+IU'low)<=CFIXED_VECTOR(ELEMENT(I,2*K,N)); - end generate; - pu:entity work.PARFFT generic map(N=>N/2, - ROUNDING=>ROUNDING, - W_high=>W_high, - W_low=>W_low, - INV_FFT=>INV_FFT, - BRAM_THRESHOLD=>BRAM_THRESHOLD, - DSP48E=>DSP48E) - port map(CLK=>CLK, - I=>IU, - VI=>VI, - SI=>SI, - O=>U, - VO=>VU, - SO=>SU); - du:for K in 0 to N/2-1 generate - signal UK,UDK:CFIXED((UD'high+1)/N*2-1 downto UD'low/N*2); - begin - UK<=ELEMENT(U,K,N/2); - cd:entity work.CDELAY generic map(SIZE=>LATENCY(N/4)+MUL_LATENCY(N)+1-LATENCY(N/2))--3) -- when CMUL latency is 6 - port map(CLK=>CLK, ---2008 I=>U(K), ---2008 O=>UD(K)); - I=>UK, - O=>UDK); - UD((K+1)*UD'length/N*2-1+UD'low downto K*UD'length/N*2+UD'low)<=CFIXED_VECTOR(UDK); - end generate; - u4:entity work.UDELAY generic map(SIZE=>LATENCY(N/4)+MUL_LATENCY(N)+2-LATENCY(N/2))--4) -- when CMUL latency is 6 - port map(CLK=>CLK, - I=>SU, - O=>SUD); - b5:entity work.BDELAY generic map(SIZE=>LATENCY(N/4)+MUL_LATENCY(N)+2-LATENCY(N/2))--4) -- when CMUL latency is 6 - port map(CLK=>CLK, - I=>VU, - O=>VO); - ll:for L in 0 to 1 generate ---2008 signal IZ:CFIXED_VECTOR(0 to N/4-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); ---2008 signal Z,OZ:CFIXED_VECTOR(0 to N/4-1)(RE(I(I'low).RE'high+X1 downto I(I'low).RE'low),IM(I(I'low).IM'high+X1 downto I(I'low).IM'low)); - signal IZ:CFIXED_VECTOR((I'high+1)/4-1 downto I'low/4); - signal Z,OZ:CFIXED_VECTOR((I'high+1)/4-1+N/4*2*X1 downto I'low/4); - signal SZ:UNSIGNED(SI'range); - signal SM:UNSIGNED(SI'range); - signal VZ:BOOLEAN; - begin - li:for J in 0 to N/4-1 generate ---2008 IZ(J)<=I(I'low+4*J+2*L+1); - IZ(2*(J+1)*(I_high-I_low+1)-1+IZ'low downto 2*J*(I_high-I_low+1)+IZ'low)<=CFIXED_VECTOR(ELEMENT(I,4*J+2*L+1,N)); - end generate; - pe:entity work.PARFFT generic map(N=>N/4, - ROUNDING=>ROUNDING, - W_high=>W_high, - W_low=>W_low, - INV_FFT=>INV_FFT, - BRAM_THRESHOLD=>BRAM_THRESHOLD, - DSP48E=>DSP48E) - port map(CLK=>CLK, - I=>IZ, - VI=>VI, - SI=>SI, - O=>Z, - VO=>VZ, - SO=>SZ); - me:entity work.CM3FFT generic map(N=>N, - RADIX=>N/4, - SPLIT_RADIX=>2*L+1, - INV_FFT=>INV_FFT, - ROUNDING=>ROUNDING, - BRAM_THRESHOLD=>BRAM_THRESHOLD, - DSP48E=>DSP48E) - port map(CLK=>CLK, - I=>Z, - VI=>VZ, - SI=>SZ, - O=>OZ, - VO=>open, - SO=>S1(L)); - lo:for J in 0 to N/4-1 generate ---2008 ZO(J)(L)<=OZ(J); - ZO(J)((L+1)*ZO(J)'length/2-1+ZO(J)'low downto L*ZO(J)'length/2+ZO(J)'low)<=CFIXED_VECTOR(ELEMENT(OZ,J,N/4)); - end generate; - end generate; - S1I<=S1(0) or S1(1); - l2:for J in 0 to N/4-1 generate ---2008 signal O2:CFIXED_VECTOR(0 to 1)(RE(I(I'low).RE'high+X2 downto I(I'low).RE'low),IM(I(I'low).IM'high+X2 downto I(I'low).IM'low)); ---2008 signal IE,IO:CFIXED_VECTOR(0 to 1)(RE(I(I'low).RE'high+X2 downto I(I'low).RE'low),IM(I(I'low).IM'high+X2 downto I(I'low).IM'low)); ---2008 signal OE,OO:CFIXED_VECTOR(0 to 1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); - signal O2:CFIXED_VECTOR(2*2*(I_high+X2+1)-1 downto 2*2*I_low); - signal IE,IO:CFIXED_VECTOR(2*2*(I_high+X2+1)-1 downto 2*2*I_low); - signal OE,OO:CFIXED_VECTOR(2*2*(O_high+1)-1 downto 2*2*O_low); - begin - p2:entity work.PARFFT generic map(N=>2, - ROUNDING=>ROUNDING, - W_high=>W_high, - W_low=>W_low, - INV_FFT=>INV_FFT, - BRAM_THRESHOLD=>BRAM_THRESHOLD, - DSP48E=>DSP48E) - port map(CLK=>CLK, - I=>ZO(J), - VI=>TRUE, - SI=>S1I, - O=>O2, - VO=>open, - SO=>S2(J)); ---2008 IE(0)<=UD(J); ---2008 IE(1)<=O2(0); - IE((0+1)*IE'length/2-1+IE'low downto 0*IE'length/2+IE'low)<=CFIXED_VECTOR(ELEMENT(UD,J,N/2)); - IE((1+1)*IE'length/2-1+IE'low downto 1*IE'length/2+IE'low)<=CFIXED_VECTOR(ELEMENT(O2,0,2)); - pe:entity work.PARFFT generic map(N=>2, - ROUNDING=>ROUNDING, - W_high=>W_high, - W_low=>W_low, - INV_FFT=>INV_FFT, - BRAM_THRESHOLD=>BRAM_THRESHOLD, - DSP48E=>DSP48E) - port map(CLK=>CLK, - I=>IE, - VI=>TRUE, - SI=>S2I, - O=>OE, - VO=>open, - SO=>S(2*J)); ---2008 O(O'low+J)<=OE(0); ---2008 O(O'low+J+N/2)<=OE(1); ---2008 IO(0)<=UD(J+N/4); ---2008 IO(1).RE<=O2(1).IM; ---2008 IO(1).IM<=O2(1).RE; --- O((J+1)*O'length/N-1+O'low downto J*O'length/N+O'low)<=CFIXED_VECTOR(ELEMENT(OE,0,2)); --- O((J+N/2+1)*O'length/N-1+O'low downto (J+N/2)*O'length/N+O'low)<=CFIXED_VECTOR(ELEMENT(OE,1,2)); - O(2*(J+1)*(O_high-O_low+1)-1+O'low downto 2*J*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(ELEMENT(OE,0,2)); - O(2*(J+N/2+1)*(O_high-O_low+1)-1+O'low downto 2*(J+N/2)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(ELEMENT(OE,1,2)); - IO((0+1)*IO'length/2-1+IO'low downto 0*IO'length/2+IO'low)<=CFIXED_VECTOR(ELEMENT(UD,J+N/4,N/2)); - IO((1+1)*IO'length/2-1+IO'low downto 1*IO'length/2+IO'low)<=CFIXED_VECTOR(TO_CFIXED(IM(ELEMENT(O2,1,2)),RE(ELEMENT(O2,1,2)))); - po:entity work.PARFFT generic map(N=>2, - ROUNDING=>ROUNDING, - W_high=>W_high, - W_low=>W_low, - INV_FFT=>INV_FFT, - BRAM_THRESHOLD=>BRAM_THRESHOLD, - DSP48E=>DSP48E) - port map(CLK=>CLK, - I=>IO, - VI=>TRUE, - SI=>S2I, - O=>OO, - VO=>open, - SO=>S(2*J+1)); - ii:if INV_FFT generate - begin ---2008 O(O'low+J+N/4).RE<=OO(1).RE; ---2008 O(O'low+J+N/4).IM<=OO(0).IM; ---2008 O(O'low+J+3*N/4).RE<=OO(0).RE; ---2008 O(O'low+J+3*N/4).IM<=OO(1).IM; --- O((J+N/4+1)*O'length/N-1+O'low downto (J+N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); --- O((J+3*N/4+1)*O'length/N-1+O'low downto (J+3*N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); - O(2*(J+N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); - O(2*(J+3*N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+3*N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); --- end; - end generate; --- else generate - id:if not INV_FFT generate - begin ---2008 O(O'low+J+N/4).RE<=OO(0).RE; ---2008 O(O'low+J+N/4).IM<=OO(1).IM; ---2008 O(O'low+J+3*N/4).RE<=OO(1).RE; ---2008 O(O'low+J+3*N/4).IM<=OO(0).IM; --- O((J+N/4+1)*O'length/N-1+O'low downto (J+N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); --- O((J+3*N/4+1)*O'length/N-1+O'low downto (J+3*N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); - O(2*(J+N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); - O(2*(J+3*N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+3*N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); --- end; - end generate; - end generate; - process(S2) - variable vS2:UNSIGNED(SI'range); - begin - vS2:=SUD; - for K in S2'range loop - vS2:=vS2 or S2(K); - end loop; - S2I<=vS2; - end process; - process(S) - variable vS:UNSIGNED(SI'range); - begin - vS:=(others=>'0'); - for K in S'range loop - vS:=vS or S(K); - end loop; - SO<=vS; - end process; --- end; - end generate; --- else generate - end generate; - i1:if F>0 generate - constant G:INTEGER:=2**F; -- size of each PARFFT - constant H:INTEGER:=N/G; -- number of PARFFTs ---2008 signal S:UNSIGNED_VECTOR(0 to H)(SO'range); - type TUV is array(0 to H) of UNSIGNED(SO'range); - signal S:TUV; - signal V:BOOLEAN_VECTOR(0 to H-1); - begin - S(S'low)<=(others=>'0'); - lk:for K in 0 to H-1 generate - signal SK:UNSIGNED(SO'range); ---workaround for QuestaSim bug ---2008 signal II:CFIXED_VECTOR(0 to G-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); ---2008 signal OO:CFIXED_VECTOR(0 to G-1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); - signal II:CFIXED_VECTOR((I'high+1)/H-1 downto I'low/H); - signal OO:CFIXED_VECTOR((O'high+1)/H-1 downto O'low/H); - begin ---2008 II<=I(I'low+G*K+0 to I'low+G*K+G-1); - II<=I(I'length/H*(K+1)-1+I'low downto I'length/H*K+I'low); - bc:entity work.PARFFT generic map(N=>G, - F=>0, - INV_FFT=>INV_FFT, - ROUNDING=>ROUNDING, - W_high=>W_high, - W_low=>W_low, - BRAM_THRESHOLD=>BRAM_THRESHOLD, - DSP48E=>DSP48E) - port map(CLK=>CLK, - I=>II, - VI=>VI, - SI=>SI, - O=>OO, - VO=>V(K), - SO=>SK); ---workaround for QuestaSim bug --- O(O'low+G*K+0 to O'low+G*K+G-1)<=OO; ---2008 lo:for J in 0 to G-1 generate ---2008 O(O'low+G*K+J)<=OO(J); ---2008 end generate; - O(O'length/H*(K+1)-1+O'low downto O'length/H*K+O'low)<=OO; - S(K+1)<=S(K) or SK; - end generate; - SO<=S(S'high); - VO<=V(V'high); --- end; - end generate; -end TEST; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - --- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 ------------------------------------------------------------------------------------------------ --- ?? Copyright 2018 Xilinx, Inc. All rights reserved. --- This file contains confidential and proprietary information of Xilinx, Inc. and is --- protected under U.S. and international copyright and other intellectual property laws. ------------------------------------------------------------------------------------------------ --- --- Disclaimer: --- This disclaimer is not a license and does not grant any rights to the materials --- distributed herewith. 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Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical Applications, subject only to --- applicable laws and regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. --- --- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx --- Worldwide Technical Support (WTS), for support please contact the author --- ____ ____ --- / /\/ / --- /___/ \ / Vendor: Xilinx Inc. --- \ \ \/ Version: 0.14 --- \ \ Filename: INPUT_SWAP.vhd --- / / Date Last Modified: 14 February 2018 --- /___/ /\ Date Created: --- \ \ / \ --- \___\/\___\ --- --- Device: Any UltraScale Xilinx FPGA --- Author: Catalin Baetoniu --- Entity Name: INPUT_SWAP --- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) --- --- Revision History: --- Revision 0.14 2018-Feb-14 Initial final release --------------------------------------------------------------------------------- --- --- Module Description: Input Order Swap Module for Systolic FFT --- The module takes N samples, I'length per clock, in natural input order --- and outputs them in natural transposed order --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.NUMERIC_STD.all; - -use work.COMPLEX_FIXED_PKG.all; - -entity INPUT_SWAP is - generic(N:INTEGER; -- N must be a power of 2 - SSR:INTEGER; -- SSR must be a power of 2 - BRAM_THRESHOLD:INTEGER:=256; -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs - USE_CB:BOOLEAN:=TRUE); -- if FALSE use alternate architecture - port(CLK:in STD_LOGIC; - I:in CFIXED_VECTOR; -- I'length must be a divisor of N, so it is also a power of 2 - VI:in BOOLEAN; - SI:in UNSIGNED; - O:out CFIXED_VECTOR; - VO:out BOOLEAN; - SO:out UNSIGNED); -end INPUT_SWAP; - -architecture TEST of INPUT_SWAP is - attribute syn_keep:STRING; - attribute syn_keep of all:architecture is "hard"; - attribute ram_style:STRING; - ---2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR - constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR - constant L2N:INTEGER:=LOG2(N); - constant L2R:INTEGER:=LOG2(RADIX); - constant F:INTEGER:=L2N mod L2R; -- if F is not zero there will be a partial last stage - constant G:INTEGER:=2**F; -- size of each CB in last stage - constant H:INTEGER:=RADIX/G; -- number of CBs in last stage - - function RS(K:INTEGER) return STRING is - begin - if K) of CFIXED_VECTOR(I'range); -begin - assert I'length=O'length report "Ports I and O must have the same length!" severity error; ---2008 assert I'length=2**LOG2(I'length) report "Port I length must be a power of 2!" severity error; - assert SSR=2**LOG2(SSR) report "SSR must be a power of 2!" severity error; - - i0:if USE_CB or (L2N<=2*L2R) generate - constant SIZE:INTEGER:=L2N/L2R; -- floor(LOG2(N)/LOG2(RADIX)) - - signal V:BOOLEAN_VECTOR(0 to SIZE-1); ---2008 signal S:UNSIGNED_VECTOR(0 to SIZE-1)(SI'range); ---2008 signal D:CFIXED_MATRIX(0 to SIZE-1)(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); - type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(SI'range); - signal S:UNSIGNED_VECTOR(0 to SIZE-1); - signal D:iCFIXED_MATRIX(0 to SIZE-1); - begin - D(D'low)<=I; - V(V'low)<=VI; - S(S'low)<=SI; - lk:for K in 0 to SIZE-2 generate - bc:entity work.CB generic map(SSR=>SSR, --93 - PACKING_FACTOR=>RADIX**K, - INPUT_PACKING_FACTOR_ADJUST=>-(RADIX**K/RADIX), -- this helps reduce - OUTPUT_PACKING_FACTOR_ADJUST=>-(RADIX**K mod RADIX**(SIZE-2)), -- RAM count and - SHORTEN_VO_BY=>(RADIX-1)*RADIX**K mod ((RADIX-1)*RADIX**(SIZE-2))) -- latency by N/RADIX/RADIX-1 clocks - port map(CLK=>CLK, - I=>D(K), - VI=>V(K), - SI=>S(K), - O=>D(K+1), - VO=>V(K+1), - SO=>S(K+1)); - end generate; ---Last stage, it becomes a trivial assignment if F=0 - bl:block - signal OV:BOOLEAN_VECTOR(0 to H-1); ---2008 signal OS:UNSIGNED_VECTOR(0 to H-1)(SI'range); - signal OS:UNSIGNED_VECTOR(0 to H-1); - begin - lj:for J in OV'range generate ---2008 signal OO:CFIXED_VECTOR(0 to G-1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); - signal OO:CFIXED_VECTOR((O'high+1)/H-1 downto O'low/H); - begin - bc:entity work.CB generic map(SSR=>G, --93 - PACKING_FACTOR=>RADIX**(SIZE-1)) - port map(CLK=>CLK, ---2008 I=>D(D'high)(I'low+G*J+0 to I'low+G*J+G-1), - I=>D(D'high)(I'length/H*(J+1)-1+I'low downto I'length/H*J+I'low), - VI=>V(V'high), - SI=>S(S'high), - O=>OO, - VO=>OV(J), - SO=>OS(J)); - lk:for K in 0 to G-1 generate ---2008 O(O'low+J+H*K)<=OO(K); - O(O'length/SSR*(J+H*K+1)-1+O'low downto O'length/SSR*(J+H*K)+O'low)<=OO(O'length/SSR*(K+1)-1+OO'low downto O'length/SSR*K+OO'low); - end generate; - end generate; - VO<=OV(OV'low); - SO<=OS(OS'low); - end block; ---2008 end; - end generate; ---2008 else generate - i1:if (not USE_CB) and (L2N>2*L2R) generate - signal VI1D:BOOLEAN:=FALSE; - signal V:BOOLEAN; ---2008 signal I1D:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(I'range=>(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0'))); - signal I1D:CFIXED_VECTOR(I'range):=(others=>'0'); - signal WCNT,RCNT:UNSIGNED(LOG2(N/RADIX)-1 downto 0):=(others=>'0'); - signal WA:UNSIGNED(WCNT'range):=(others=>'0'); - signal RA:UNSIGNED(RCNT'range):=(others=>'0'); - signal WSEL:UNSIGNED(LOG2(WCNT'length)-1 downto 0):=TO_UNSIGNED(0,LOG2(RCNT'length)); - signal RSEL:UNSIGNED(LOG2(RCNT'length)-1 downto 0):=TO_UNSIGNED(L2N-2*L2R,LOG2(RCNT'length)); ---2008 signal IO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); - signal IO:CFIXED_VECTOR(I'range); - signal OV:BOOLEAN; - signal S:UNSIGNED(SO'range); - begin - bd:entity work.BDELAY generic map(SIZE=>N/RADIX-RADIX-N/RADIX/RADIX+2) - port map(CLK=>CLK, - I=>VI, - O=>V); - - process(CLK) - begin - if rising_edge(CLK) then - if VI then - if WCNT=N/RADIX-1 then - WSEL<=RSEL; - end if; - WCNT<=WCNT+1; - else - WCNT<=(others=>'0'); - end if; - end if; - end process; - - process(CLK) - begin - if rising_edge(CLK) then - if V then - if RCNT=N/RADIX-1 then - if RSEL'0'); - end if; - VI1D<=VI; - I1D<=I; - end if; - end process; --- Write Address Digit Swapping - process(CLK) - begin - if rising_edge(CLK) then - WA<=ROTATE_LEFT(WCNT,TO_INTEGER(WSEL)); - end if; - end process; --- Read Address Digit Swapping - process(CLK) - begin - if rising_edge(CLK) then - RA<=ROTATE_LEFT(RCNT,TO_INTEGER(RSEL)); - end if; - end process; - ---2008 lk:for K in 0 to I'length-1 generate - lk:if TRUE generate ---? Vivado synthesis does not infer RAM from this code, just LUTs and FFs --- signal MEM:CFIXED_VECTOR(0 to 2**(CNT'length+1)-1)(RE(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).RE)),IM(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).IM))):=(0 to 2**(CNT'length+1)-1=>(RE=>(I(low_f(I)).RE'range=>'0'),IM=>(I(low_f(I)).IM'range=>'0'))); ---2008 signal MEMR:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); ---2008 signal MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).IM'range):=(0 to 2**WCNT'length-1=>(I(I'low).IM'range=>'0')); ---2008 signal Q:CFIXED(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0')); - signal MEM:iCFIXED_MATRIX(0 to 2**WCNT'length-1):=(0 to 2**WCNT'length-1=>(others=>'0')); - signal Q:CFIXED_VECTOR(I'range):=(others=>'0'); ---WBR shared variable MEMR,MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); ---2008 attribute ram_style of MEMR:signal is RS(N/RADIX); ---2008 attribute ram_style of MEMI:signal is RS(N/RADIX); - attribute ram_style of MEM:signal is RS(N/RADIX); - begin - process(CLK) - begin - if rising_edge(CLK) then - if VI1D then - MEM(TO_INTEGER(WA))<=I1D; ---2008 MEMR(TO_INTEGER(WA))<=I1D(K).RE; ---2008 MEMI(TO_INTEGER(WA))<=I1D(K).IM; --- MEMR(TO_INTEGER(WA)):=I1D(K).RE; --- MEMI(TO_INTEGER(WA)):=I1D(K).IM; ---WBR Q.RE<=I1D(K).RE; ---WBR Q.IM<=I1D(K).IM; ---WBR else ---WBR Q.RE<=MEMR(TO_INTEGER(WA)); ---WBR Q.IM<=MEMI(TO_INTEGER(WA)); - end if; - Q<=MEM(TO_INTEGER(RA)); ---2008 Q.RE<=MEMR(TO_INTEGER(RA)); ---2008 Q.IM<=MEMI(TO_INTEGER(RA)); - IO<=Q; - end if; - end process; - end generate; - - bo:entity work.BDELAY generic map(SIZE=>3) - port map(CLK=>CLK, - I=>V, - O=>OV); - - sd:entity work.UDELAY generic map(SIZE=>N/RADIX-RADIX-N/RADIX/RADIX+5) - port map(CLK=>CLK, - I=>SI, - O=>S); - - ci:entity work.CB generic map(SSR=>SSR, --93 - PACKING_FACTOR=>1) - port map(CLK=>CLK, - I=>IO, - VI=>OV, - SI=>S, - O=>O, - VO=>VO, - SO=>SO); - end generate; -end TEST; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - --- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 ------------------------------------------------------------------------------------------------ --- ? Copyright 2018 Xilinx, Inc. All rights reserved. --- This file contains confidential and proprietary information of Xilinx, Inc. and is --- protected under U.S. and international copyright and other intellectual property laws. ------------------------------------------------------------------------------------------------ --- --- Disclaimer: --- This disclaimer is not a license and does not grant any rights to the materials --- distributed herewith. Except as otherwise provided in a valid license issued to you --- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS --- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL --- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED --- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR --- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including --- negligence, or under any other theory of liability) for any loss or damage of any --- kind or nature related to, arising under or in connection with these materials, --- including for any direct, or any indirect, special, incidental, or consequential --- loss or damage (including loss of data, profits, goodwill, or any type of loss or --- damage suffered as a result of any action brought by a third party) even if such --- damage or loss was reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail-safe, or for use in any --- application requiring fail-safe performance, such as life-support or safety devices --- or systems, Class III medical devices, nuclear facilities, applications related to --- the deployment of airbags, or any other applications that could lead to death, --- personal injury, or severe property or environmental damage (individually and --- collectively, "Critical Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical Applications, subject only to --- applicable laws and regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. --- --- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx --- Worldwide Technical Support (WTS), for support please contact the author --- ____ ____ --- / /\/ / --- /___/ \ / Vendor: Xilinx Inc. --- \ \ \/ Version: 0.14 --- \ \ Filename: SYSTOLIC_FFT.vhd --- / / Date Last Modified: 9 Mar 2018 --- /___/ /\ Date Created: --- \ \ / \ --- \___\/\___\ --- --- Device: Any UltraScale Xilinx FPGA --- Author: Catalin Baetoniu --- Entity Name: SYSTOLIC_FFT --- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) --- --- Revision History: --- Revision 0.14 2018-Mar-09 Version with workarounds for Vivado Simulator limited VHDL-2008 support --------------------------------------------------------------------------------- --- --- Module Description: Generic, Arbitrary Size, Systolic FFT Module --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.NUMERIC_STD.all; - -use work.COMPLEX_FIXED_PKG.all; - -entity SYSTOLIC_FFT is - generic(N:INTEGER; - SSR:INTEGER; --93 - W_high:INTEGER:=1; - W_low:INTEGER:=-17; - ROUNDING:BOOLEAN:=TRUE; - BRAM_THRESHOLD:INTEGER:=256; - DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 - port(CLK:in STD_LOGIC; - I:in CFIXED_VECTOR; - VI:in BOOLEAN; - SI:in UNSIGNED; - O:out CFIXED_VECTOR; - VO:out BOOLEAN; - SO:out UNSIGNED); -end SYSTOLIC_FFT; - -architecture TEST of SYSTOLIC_FFT is - attribute syn_hier:STRING; - attribute syn_hier of all:architecture is "hard"; - attribute keep_hierarchy:STRING; - attribute keep_hierarchy of all:architecture is "yes"; - ---2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR - constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR - constant L2N:INTEGER:=LOG2(N); - constant L2R:INTEGER:=LOG2(RADIX); - constant F:INTEGER:=L2N mod L2R; -- if F is not zero there will be a partial last stage - constant G:INTEGER:=2**F; -- size of each CB and PARFFT in last stage - constant H:INTEGER:=RADIX/G; -- number of CBs and PARFFTsin last stage - constant SIZE:INTEGER:=(L2N-1)/L2R; -- ceil(LOG2(N)/LOG2(RADIX)), number of stages ---2008 constant BIT_GROWTH:INTEGER:=MAX(O(O'low).RE'high,O(O'low).IM'high)-MAX(I(I'low).RE'high,I(I'low).IM'high); - constant BIT_GROWTH:INTEGER:=(O'high+1)/2/SSR-(I'high+1)/2/SSR; - --- constant XL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN((SIZE-1)*L2R,BIT_GROWTH); - constant XL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(SIZE*L2R,BIT_GROWTH); ---2008 signal D:CFIXED_MATRIX(0 to SIZE)(I'range)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); - type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR(O'range); -- unconstrained array of CFIXED_VECTOR - signal D:CFIXED_MATRIX(0 to SIZE); - signal V:BOOLEAN_VECTOR(0 to SIZE); ---2008 signal S:UNSIGNED_VECTOR(0 to SIZE)(SI'range); - type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(SI'range); --93 - signal S:UNSIGNED_VECTOR(0 to SIZE); - --- constant XI:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(SIZE*L2R,BIT_GROWTH); - constant XI:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(L2N,BIT_GROWTH); ---2008 signal DI:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'high+XI downto I(I'low).RE'low),IM(I(I'low).IM'high+XI downto I(I'low).IM'low)); ---2008 signal OO:CFIXED_VECTOR(O'range)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); - signal DI:CFIXED_VECTOR(I'high+2*SSR*XI downto I'low); - signal OO:CFIXED_VECTOR(O'range); -begin ---2008 lj:for J in I'range generate ---2008 D(D'low)(J)<=RESIZE(I(J),D(D'low)(J)); - lj:for J in 0 to SSR-1 generate - D(D'low)(O'length/SSR*(J+1)-1+O'low downto O'length/SSR*J+O'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(I,J,SSR),(O'high+1)/2/SSR-1,O'low/2/SSR)); - end generate; - V(V'low)<=VI; - S(S'low)<=SI; - lk:for K in 0 to SIZE-1 generate - constant XI:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(K*L2R,BIT_GROWTH); - constant XO:INTEGER:=work.COMPLEX_FIXED_PKG.MIN((K+1)*L2R,BIT_GROWTH); ---2008 signal DI:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'high+XI downto I(I'low).RE'low),IM(I(I'low).IM'high+XI downto I(I'low).IM'low)); ---2008 signal DM,DB,DO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'high+XO downto I(I'low).RE'low),IM(I(I'low).IM'high+XO downto I(I'low).IM'low)); - signal DI:CFIXED_VECTOR(I'high+2*SSR*XI downto I'low); - signal DM,DB,DO:CFIXED_VECTOR(I'high+2*SSR*XO downto I'low); - signal VM,VB:BOOLEAN; - signal SM,SB:UNSIGNED(SI'range); - begin ---2008 li:for J in 0 to I'length-1 generate ---2008 DI(DI'low+J)<=RESIZE(D(K)(J),DI(DI'low+J)); - li:for J in 0 to SSR-1 generate - DI(DI'length/SSR*(J+1)-1+DI'low downto DI'length/SSR*J+DI'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(D(K),J,SSR),(DI'high+1)/2/SSR-1,DI'low/2/SSR)); - end generate; - pf:entity work.PARFFT generic map(N=>RADIX, --93 - INV_FFT=>FALSE, - ROUNDING=>ROUNDING, - W_high=>W_high, - W_low=>W_low, - BRAM_THRESHOLD=>BRAM_THRESHOLD, - DSP48E=>DSP48E) - port map(CLK=>CLK, - I=>DI, - VI=>V(K), - SI=>S(K), - O=>DM, - VO=>VM, - SO=>SM); - cm:entity work.CM3FFT generic map(N=>N/(RADIX**K), - RADIX=>RADIX, --93 - INV_FFT=>FALSE, - W_high=>W_high, - W_low=>W_low, - ROUNDING=>ROUNDING, - BRAM_THRESHOLD=>BRAM_THRESHOLD, - DSP48E=>DSP48E) - port map(CLK=>CLK, - I=>DM, - VI=>VM, - SI=>SM, - O=>DB, - VO=>VB, - SO=>SB); - - bc:entity work.CB generic map(SSR=>RADIX, --93 - F=>F*BOOLEAN'pos(K=SIZE-1), - PACKING_FACTOR=>N/(RADIX**(K+2))*BOOLEAN'pos(KBRAM_THRESHOLD) - port map(CLK=>CLK, - I=>DB, - VI=>VB, - SI=>SB, - O=>DO, - VO=>V(K+1), - SO=>S(K+1)); ---2008 lo:for J in 0 to I'length-1 generate ---2008 D(K+1)(J)<=RESIZE(DO(DO'low+J),D(K+1)(J)); - lo:for J in 0 to SSR-1 generate - D(K+1)(O'length/SSR*(J+1)-1+O'low downto O'length/SSR*J+O'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(DO,J,SSR),(O'high+1)/2/SSR-1,O'low/2/SSR)); - end generate; - end generate; ---last PARFFT stage ---2008 li:for J in 0 to I'length-1 generate ---2008 DI(DI'low+J)<=RESIZE(D(D'high)(J),DI(DI'low+J)); - li:for J in 0 to SSR-1 generate - DI(DI'length/SSR*(J+1)-1+DI'low downto DI'length/SSR*J+DI'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(D(D'high),J,SSR),(DI'high+1)/2/SSR-1,DI'low/2/SSR)); - end generate; - pf:entity work.PARFFT generic map(N=>RADIX, - F=>F, - INV_FFT=>FALSE, - ROUNDING=>ROUNDING, - W_high=>W_high, - W_low=>W_low, - BRAM_THRESHOLD=>BRAM_THRESHOLD, - DSP48E=>DSP48E) - port map(CLK=>CLK, - I=>DI, - VI=>V(V'high), - SI=>S(S'high), - O=>OO, - VO=>VO, - SO=>SO); - lo:for J in 0 to H-1 generate - lk:for K in 0 to G-1 generate ---2008 O(O'low+J+H*K)<=OO(OO'low+K+G*J); - O(O'length/SSR*(J+H*K+1)-1+O'low downto O'length/SSR*(J+H*K)+O'low)<=OO(O'length/SSR*(K+G*J+1)-1+OO'low downto O'length/SSR*(K+G*J)+OO'low); - end generate; - end generate; -end TEST; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - --- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 ------------------------------------------------------------------------------------------------ --- Copyright 2018 Xilinx, Inc. All rights reserved. --- This file contains confidential and proprietary information of Xilinx, Inc. and is --- protected under U.S. and international copyright and other intellectual property laws. ------------------------------------------------------------------------------------------------ --- --- Disclaimer: --- This disclaimer is not a license and does not grant any rights to the materials --- distributed herewith. Except as otherwise provided in a valid license issued to you --- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS --- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL --- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED --- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR --- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including --- negligence, or under any other theory of liability) for any loss or damage of any --- kind or nature related to, arising under or in connection with these materials, --- including for any direct, or any indirect, special, incidental, or consequential --- loss or damage (including loss of data, profits, goodwill, or any type of loss or --- damage suffered as a result of any action brought by a third party) even if such --- damage or loss was reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail-safe, or for use in any --- application requiring fail-safe performance, such as life-support or safety devices --- or systems, Class III medical devices, nuclear facilities, applications related to --- the deployment of airbags, or any other applications that could lead to death, --- personal injury, or severe property or environmental damage (individually and --- collectively, "Critical Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical Applications, subject only to --- applicable laws and regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. --- --- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx --- Worldwide Technical Support (WTS), for support please contact the author --- ____ ____ --- / /\/ / --- /___/ \ / Vendor: Xilinx Inc. --- \ \ \/ Version: 0.14 --- \ \ Filename: DS.vhd --- / / Date Last Modified: 14 Feb 2018 --- /___/ /\ Date Created: --- \ \ / \ --- \___\/\___\ --- --- Device: Any UltraScale Xilinx FPGA --- Author: Catalin Baetoniu --- Entity Name: DS --- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) --- --- Revision History: --- Revision 0.14 2018-Feb-14 Initial final release --------------------------------------------------------------------------------- --- --- Module Description: Output Order Swap Module for Systolic FFT (Digit Swap) --- Produces Transposed Output Order --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.NUMERIC_STD.all; - -use work.COMPLEX_FIXED_PKG.all; - -entity DS is -- LATENCY=0 when N=2*SSR else LATENCY=N/SSR+1 - generic(N:INTEGER; - SSR:INTEGER; -- SSR must be a power of 2 - BRAM_THRESHOLD:INTEGER:=256); -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs - port(CLK:in STD_LOGIC; - I:in CFIXED_VECTOR; - VI:in BOOLEAN; - SI:in UNSIGNED; - O:out CFIXED_VECTOR; - VO:out BOOLEAN; - SO:out UNSIGNED); -end DS; - -architecture TEST of DS is - attribute syn_keep:STRING; - attribute syn_keep of all:architecture is "hard"; - attribute ram_style:STRING; - ---2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR - constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR - constant L2N:INTEGER:=LOG2(N); - constant L2R:INTEGER:=LOG2(RADIX); - constant F:INTEGER:=L2N mod L2R; - constant G:INTEGER:=2**F; - - signal VI1D:BOOLEAN:=FALSE; - signal V:BOOLEAN; ---2008 signal I1D:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(I'range=>(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0'))); - signal I1D:CFIXED_VECTOR(I'range):=(others=>'0'); - signal WCNT,RCNT:UNSIGNED(LOG2(N/RADIX)-1 downto 0):=(others=>'0'); - signal WA:UNSIGNED(WCNT'range):=(others=>'0'); - signal RA:UNSIGNED(RCNT'range):=(others=>'0'); - - function RS(K:INTEGER) return STRING is - begin - if K) of UNSIGNED(RCNT'range); --93 - function IDENTITY(K:INTEGER) return UNSIGNED_VECTOR is - variable RESULT:UNSIGNED_VECTOR(0 to K-1);--93 (LOG2(K)-1 downto 0); - begin - for J in RESULT'range loop - RESULT(J):=TO_UNSIGNED(J,RESULT(J)'length); - end loop; - return RESULT; - end; - - function PERMUTE(A:UNSIGNED_VECTOR) return UNSIGNED_VECTOR is - variable RESULT:UNSIGNED_VECTOR(A'range);--93 (A(A'low)'range); - begin - for J in RESULT'range loop - for J in 0 to A'length/L2R-1 loop - for K in 0 to L2R-1 loop - RESULT((A'length/L2R-1-J)*L2R+K+F):=A(J*L2R+K); - end loop; - end loop; - for K in 0 to F-1 loop - RESULT(K):=A(A'length/L2R*L2R+K); - end loop; - end loop; - return RESULT; - end; - - function INVERSE_PERMUTE(A:UNSIGNED_VECTOR) return UNSIGNED_VECTOR is - variable RESULT:UNSIGNED_VECTOR(A'range);--93 (A(A'low)'range); - begin - for J in RESULT'range loop - for J in 0 to A'length/L2R-1 loop - for K in 0 to L2R-1 loop - RESULT(J*L2R+K):=A((A'length/L2R-1-J)*L2R+K+F); - end loop; - end loop; - for K in 0 to F-1 loop - RESULT(A'length/L2R*L2R+K):=A(K); - end loop; - end loop; - return RESULT; - end; - ---2008 signal WSEL:UNSIGNED_VECTOR(0 to WCNT'length-1)(LOG2(WCNT'length)-1 downto 0):=INVERSE_PERMUTE(IDENTITY(WCNT'length)); ---2008 signal RSEL:UNSIGNED_VECTOR(0 to RCNT'length-1)(LOG2(RCNT'length)-1 downto 0):=IDENTITY(RCNT'length); - signal WSEL:UNSIGNED_VECTOR(0 to WCNT'length-1):=INVERSE_PERMUTE(IDENTITY(WCNT'length)); - signal RSEL:UNSIGNED_VECTOR(0 to RCNT'length-1):=IDENTITY(RCNT'length); -begin - assert I'length=O'length report "Ports I and O must have the same length!" severity error; ---2008 assert I'length=2**L2R report "Port I length must be a power of 2!" severity error; - assert SSR=2**L2R report "Port I length must be a power of 2!" severity error; - - i0:if L2N-L2R<2 generate - O<=I; - VO<=VI; - SO<=SI; ---2008 else generate - end generate; - i1:if L2N-L2R>=2 generate - bd:entity work.BDELAY generic map(SIZE=>N/RADIX-2) - port map(CLK=>CLK, - I=>VI, - O=>V); - - process(CLK) - begin - if rising_edge(CLK) then - if VI then - if WCNT=N/RADIX-1 then - WSEL<=RSEL; - end if; - WCNT<=WCNT+1; - else - WCNT<=(others=>'0'); - end if; - end if; - end process; - - process(CLK) - begin - if rising_edge(CLK) then - if V then - if RCNT=N/RADIX-1 then - RSEL<=PERMUTE(WSEL); - end if; - RCNT<=RCNT+1; - else - RCNT<=(others=>'0'); - end if; - VI1D<=VI; - I1D<=I; - end if; - end process; --- Write Address Digit Swapping - process(CLK) - begin - if rising_edge(CLK) then - for K in WCNT'range loop - WA(K)<=WCNT(TO_INTEGER(WSEL(K))); - end loop; - end if; - end process; --- Read Address Digit Swapping - process(CLK) - begin - if rising_edge(CLK) then - for K in RCNT'range loop - RA(K)<=RCNT(TO_INTEGER(RSEL(K))); - end loop; - end if; - end process; - ---2008 lk:for K in 0 to I'length-1 generate - lk:if TRUE generate ---? Vivado synthesis does not infer RAM from this code, just LUTs and FFs --- signal MEM:CFIXED_VECTOR(0 to 2**(CNT'length+1)-1)(RE(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).RE)),IM(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).IM))):=(0 to 2**(CNT'length+1)-1=>(RE=>(I(low_f(I)).RE'range=>'0'),IM=>(I(low_f(I)).IM'range=>'0'))); ---2008 signal MEMR:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); ---2008 signal MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).IM'range):=(0 to 2**WCNT'length-1=>(I(I'low).IM'range=>'0')); ---2008 signal Q:CFIXED(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0')); - type iCFIXED_MATRIX is array(NATURAL range <>) of CFIXED_VECTOR(I'range); - signal MEM:iCFIXED_MATRIX(0 to 2**WCNT'length-1):=(0 to 2**WCNT'length-1=>(others=>'0')); - signal Q:CFIXED_VECTOR(I'range):=(others=>'0'); ---WBR shared variable MEMR,MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); ---2008 attribute ram_style of MEMR:signal is RS(N/RADIX); ---2008 attribute ram_style of MEMI:signal is RS(N/RADIX); - attribute ram_style of MEM:signal is RS(N/RADIX); - begin - process(CLK) - begin - if rising_edge(CLK) then - if VI1D then - MEM(TO_INTEGER(WA))<=I1D; ---2008 MEMR(TO_INTEGER(WA))<=I1D(K).RE; ---2008 MEMI(TO_INTEGER(WA))<=I1D(K).IM; --- MEMR(TO_INTEGER(WA)):=I1D(K).RE; --- MEMI(TO_INTEGER(WA)):=I1D(K).IM; ---WBR Q.RE<=I1D(K).RE; ---WBR Q.IM<=I1D(K).IM; ---WBR else ---WBR Q.RE<=MEMR(TO_INTEGER(WA)); ---WBR Q.IM<=MEMI(TO_INTEGER(WA)); - end if; - Q<=MEM(TO_INTEGER(RA)); ---2008 Q.RE<=MEMR(TO_INTEGER(RA)); ---2008 Q.IM<=MEMI(TO_INTEGER(RA)); ---2008 O(K)<=Q; - O<=Q; - end if; - end process; - end generate; - - bo:entity work.BDELAY generic map(SIZE=>3) - port map(CLK=>CLK, - I=>V, - O=>VO); - - sd:entity work.UDELAY generic map(SIZE=>N/RADIX+1) - port map(CLK=>CLK, - I=>SI, - O=>SO); - end generate; -end TEST; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - --- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 ------------------------------------------------------------------------------------------------ --- © Copyright 2018 Xilinx, Inc. All rights reserved. --- This file contains confidential and proprietary information of Xilinx, Inc. and is --- protected under U.S. and international copyright and other intellectual property laws. ------------------------------------------------------------------------------------------------ --- --- Disclaimer: --- This disclaimer is not a license and does not grant any rights to the materials --- distributed herewith. Except as otherwise provided in a valid license issued to you --- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS --- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL --- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED --- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR --- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including --- negligence, or under any other theory of liability) for any loss or damage of any --- kind or nature related to, arising under or in connection with these materials, --- including for any direct, or any indirect, special, incidental, or consequential --- loss or damage (including loss of data, profits, goodwill, or any type of loss or --- damage suffered as a result of any action brought by a third party) even if such --- damage or loss was reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail-safe, or for use in any --- application requiring fail-safe performance, such as life-support or safety devices --- or systems, Class III medical devices, nuclear facilities, applications related to --- the deployment of airbags, or any other applications that could lead to death, --- personal injury, or severe property or environmental damage (individually and --- collectively, "Critical Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical Applications, subject only to --- applicable laws and regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. --- --- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx --- Worldwide Technical Support (WTS), for support please contact the author --- ____ ____ --- / /\/ / --- /___/ \ / Vendor: Xilinx Inc. --- \ \ \/ Version: 0.14 --- \ \ Filename: DSN.vhd --- / / Date Last Modified: 14 Feb 2018 --- /___/ /\ Date Created: --- \ \ / \ --- \___\/\___\ --- --- Device: Any UltraScale Xilinx FPGA --- Author: Catalin Baetoniu --- Entity Name: DSN --- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) --- --- Revision History: --- Revision 0.14 2018-Feb-14 Initial final release --------------------------------------------------------------------------------- --- --- Module Description: Output Order Swap Module for Systolic FFT (Digit Swap) --- Produces Natural Output Order --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.NUMERIC_STD.all; - -use work.COMPLEX_FIXED_PKG.all; - -entity DSN is - generic(N:INTEGER; - SSR:INTEGER; -- SSR must be a power of 2 - BRAM_THRESHOLD:INTEGER:=256); -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs - port(CLK:in STD_LOGIC; - I:in CFIXED_VECTOR; - VI:in BOOLEAN; - SI:in UNSIGNED; - O:out CFIXED_VECTOR; - VO:out BOOLEAN; - SO:out UNSIGNED); -end DSN; - -architecture TEST of DSN is - attribute syn_keep:STRING; - attribute syn_keep of all:architecture is "hard"; - attribute rloc:STRING; - ---2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR - constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR - constant L2N:INTEGER:=LOG2(N); - constant L2R:INTEGER:=LOG2(RADIX); - constant F:INTEGER:=L2N mod L2R; - constant G:INTEGER:=2**F; - constant H:INTEGER:=RADIX/G; -begin - assert I'length=O'length report "Ports I and O must have the same length!" severity error; ---2008 assert I'length=2**L2R report "Port I length must be a power of 2!" severity error; - assert SSR=2**L2R report "Port I length must be a power of 2!" severity error; - - i1:if L2N<2*L2R generate ---2008 signal IO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); - signal IO:CFIXED_VECTOR(I'range); - signal V:BOOLEAN; - signal S:UNSIGNED(SI'range); - signal OV:BOOLEAN_VECTOR(0 to H-1); ---2008 signal OS:UNSIGNED_VECTOR(0 to H-1)(SO'range); - type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(SO'range); --93 - signal OS:UNSIGNED_VECTOR(0 to H-1); - begin - sd:entity work.DS generic map(N=>N, - SSR=>SSR, --93 - BRAM_THRESHOLD=>BRAM_THRESHOLD) - port map(CLK=>CLK, - I=>I, - VI=>VI, - SI=>SI, - O=>IO, - VO=>V, - SO=>S); - lk:for K in 0 to H-1 generate -----2008 signal II,OO:CFIXED_VECTOR(0 to G-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); - signal II,OO:CFIXED_VECTOR((I'high+1)/H-1 downto I'low/H); - begin - li:for J in 0 to G-1 generate ---2008 II(J)<=IO(IO'low+K+H*J); - II(I'length/SSR*(J+1)-1+II'low downto I'length/SSR*J+II'low)<=IO(I'length/SSR*(K+H*J+1)-1+I'low downto I'length/SSR*(K+H*J)+I'low); - end generate; - ci:entity work.CB generic map(SSR=>G, --93 - PACKING_FACTOR=>1) - port map(CLK=>CLK, - I=>II, - VI=>V, - SI=>S, - O=>OO, - VO=>OV(K), - SO=>OS(K)); - lo:for J in 0 to G-1 generate -----2008 O(O'low+K*G+J)<=OO(J); - O(O'length/SSR*(K*G+J+1)-1+O'low downto O'length/SSR*(K*G+J)+O'low)<=OO(O'length/SSR*(J+1)-1+OO'low downto O'length/SSR*J+OO'low); - end generate; - end generate; - VO<=OV(OV'low); - SO<=OS(OS'low); ---2008 end; - end generate; ---2008 elsif L2N=2*L2R generate - i2:if L2N=2*L2R generate - ci:entity work.CB generic map(SSR=>SSR, --93 - PACKING_FACTOR=>1) - port map(CLK=>CLK, - I=>I, - VI=>VI, - SI=>SI, - O=>O, - VO=>VO, - SO=>SO); ---2008 else generate - end generate; - i3:if L2N>2*L2R generate ---2008 signal IO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); - signal IO:CFIXED_VECTOR(I'range); - signal V:BOOLEAN; - signal S:UNSIGNED(SO'range); - begin - ci:entity work.CB generic map(SSR=>SSR, --93 - PACKING_FACTOR=>N/RADIX/RADIX, - BRAM_THRESHOLD=>BRAM_THRESHOLD) - port map(CLK=>CLK, - I=>I, - VI=>VI, - SI=>SI, - O=>IO, - VO=>V, - SO=>S); - - sd:entity work.DS generic map(N=>N/RADIX, - SSR=>SSR, --93 - BRAM_THRESHOLD=>BRAM_THRESHOLD) - port map(CLK=>CLK, - I=>IO, - VI=>V, - SI=>S, - O=>O, - VO=>VO, - SO=>SO); - end generate; -end TEST; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - --- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 ------------------------------------------------------------------------------------------------ --- ? Copyright 2018 Xilinx, Inc. All rights reserved. --- This file contains confidential and proprietary information of Xilinx, Inc. and is --- protected under U.S. and international copyright and other intellectual property laws. ------------------------------------------------------------------------------------------------ --- --- Disclaimer: --- This disclaimer is not a license and does not grant any rights to the materials --- distributed herewith. Except as otherwise provided in a valid license issued to you --- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS --- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL --- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED --- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR --- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including --- negligence, or under any other theory of liability) for any loss or damage of any --- kind or nature related to, arising under or in connection with these materials, --- including for any direct, or any indirect, special, incidental, or consequential --- loss or damage (including loss of data, profits, goodwill, or any type of loss or --- damage suffered as a result of any action brought by a third party) even if such --- damage or loss was reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail-safe, or for use in any --- application requiring fail-safe performance, such as life-support or safety devices --- or systems, Class III medical devices, nuclear facilities, applications related to --- the deployment of airbags, or any other applications that could lead to death, --- personal injury, or severe property or environmental damage (individually and --- collectively, "Critical Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical Applications, subject only to --- applicable laws and regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. --- --- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx --- Worldwide Technical Support (WTS), for support please contact the author --- ____ ____ --- / /\/ / --- /___/ \ / Vendor: Xilinx Inc. --- \ \ \/ Version: 0.14 --- \ \ Filename: VECTOR_FFT.vhd --- / / Date Last Modified: 9 Mar 2018 --- /___/ /\ Date Created: --- \ \ / \ --- \___\/\___\ --- --- Device: Any UltraScale Xilinx FPGA --- Author: Catalin Baetoniu --- Entity Name: VECTOR_FFT --- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) --- --- Revision History: --- Revision 0.14 2018-Mar-09 Version with workarounds for Vivado Simulator limited VHDL-2008 support --------------------------------------------------------------------------------- --- --- Module Description: Top Level Test Module for SYSTOLIC_FFT --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.NUMERIC_STD.all; - -use work.COMPLEX_FIXED_PKG.all; - -entity VECTOR_FFT is - generic(SSR:INTEGER:=8;--4; - N:INTEGER:=16384;--8192;--4096;--1024; - I_high:INTEGER:=0; - I_low:INTEGER:=-17; - W_high:INTEGER:=1; - W_low:INTEGER:=-17; - O_high:INTEGER:=0; - O_low:INTEGER:=-17; - ROUNDING:BOOLEAN:=TRUE; - BRAM_THRESHOLD:INTEGER:=512; - USE_CB:BOOLEAN:=FALSE; - DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 - port(CLK:in STD_LOGIC; ---2008 I:in CFIXED_VECTOR(0 to RADIX-1)(RE(I_high downto I_low),IM(I_high downto I_low)); - I:in CFIXED_VECTOR(SSR*2*(I_high-I_low+1)-1 downto 0); - VI:in BOOLEAN; - SI:in UNSIGNED(LOG2(N)-1 downto 0); ---2008 O:out CFIXED_VECTOR(0 to RADIX-1)(RE(O_high downto O_low),IM(O_high downto O_low)); - O:out CFIXED_VECTOR(SSR*2*(O_high-O_low+1)-1 downto 0); - VO:out BOOLEAN; - SO:out UNSIGNED(LOG2(N)-1 downto 0)); -end VECTOR_FFT; - -architecture TEST of VECTOR_FFT is - function TO_SFIXED(S:STD_LOGIC_VECTOR;I:SFIXED) return SFIXED is - variable R:SFIXED(I'range); - begin - for K in 0 to R'length-1 loop - R(R'low+K):=S(S'low+K); - end loop; - return R; - end; - - function TO_STD_LOGIC_VECTOR(S:SFIXED) return STD_LOGIC_VECTOR is - variable R:STD_LOGIC_VECTOR(S'length-1 downto 0); - begin - for K in 0 to R'length-1 loop - R(R'low+K):=S(S'low+K); - end loop; - return R; - end; - ---2008 signal II:CFIXED_VECTOR(I'range)(RE(I_high downto I_low),IM(I_high downto I_low)); - signal II:CFIXED_VECTOR(I'range); - signal V,VOFFT,VODS:BOOLEAN; - signal S,SFFT,SODS:UNSIGNED(SI'range); ---2008 signal OFFT,ODS:CFIXED_VECTOR(O'range)(RE(O_high downto O_low),IM(O_high downto O_low)); - signal OFFT,ODS:CFIXED_VECTOR(O'range); -begin - u0:entity work.INPUT_SWAP generic map(N=>N, - SSR=>SSR, --93 - BRAM_THRESHOLD=>BRAM_THRESHOLD, - USE_CB=>USE_CB) - port map(CLK=>CLK, - I=>I, - VI=>VI, - SI=>SI, - O=>II, - VO=>V, - SO=>S); - - u1:entity work.SYSTOLIC_FFT generic map(N=>N, - SSR=>SSR, --93 - W_high=>W_high, - W_low=>W_low, - ROUNDING=>ROUNDING, - BRAM_THRESHOLD=>BRAM_THRESHOLD, - DSP48E=>DSP48E) - port map(CLK=>CLK, - I=>II, - VI=>V, - SI=>S, - O=>OFFT, - VO=>VOFFT, - SO=>SFFT); - - u2:entity work.DSN generic map(N=>N, - SSR=>SSR, --93 - BRAM_THRESHOLD=>BRAM_THRESHOLD) - port map(CLK=>CLK, - I=>OFFT, - VI=>VOFFT, - SI=>SFFT, - O=>O, - VO=>VO, - SO=>SO); --- O<=OFFT; --- VO<=VOFFT; --- SO<=SFFT; -end TEST; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - --- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.NUMERIC_STD.all; -use work.COMPLEX_FIXED_PKG.all; - -entity WRAPPER_VECTOR_FFT is - generic(SSR:INTEGER:=8; - N:INTEGER:=512; - L2N:INTEGER:=9; -- L2N must be set equal to log2(N)!!! - I_high:INTEGER:=0; - I_low:INTEGER:=-15; - W_high:INTEGER:=1; - W_low:INTEGER:=-17; - O_high:INTEGER:=0; - O_low:INTEGER:=-15; - ROUNDING:BOOLEAN:=TRUE; - BRAM_THRESHOLD:INTEGER:=512; - USE_CB:BOOLEAN:=FALSE; - DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 - port(CLK:in STD_LOGIC; - CE:in STD_LOGIC:='1'; -- not used, for SysGen only - I:in STD_LOGIC_VECTOR(2*SSR*(I_high-I_low+1)-1 downto 0); - VI:in STD_LOGIC; - SI:in STD_LOGIC_VECTOR(L2N-1 downto 0):=(L2N-1 downto 0=>'0'); -- can be left unconnected if internal scaling is not used, must be a (LOG2(N)-1 downto 0) port - O:out STD_LOGIC_VECTOR(2*SSR*(O_high-O_low+1)-1 downto 0); - VO:out STD_LOGIC; - SO:out STD_LOGIC_VECTOR(L2N-1 downto 0)); -- can be left unconnected if internal overflow is not possible, must be a (LOG2(N)-1 downto 0) port -end WRAPPER_VECTOR_FFT; - -architecture WRAPPER of WRAPPER_VECTOR_FFT is --- resize SFIXED and convert to STD_LOGIC_VECTOR - function SFIXED_TO_SLV_RESIZE(I:SFIXED;hi,lo:INTEGER) return STD_LOGIC_VECTOR is - variable O:STD_LOGIC_VECTOR(hi-lo downto 0); - begin - for K in O'range loop - if KSSR, - N=>N, - I_high=>I_high, - I_low=>I_low, - W_high=>W_high, - W_low=>W_low, - O_high=>O_high, - O_low=>O_low, - ROUNDING=>ROUNDING, - BRAM_THRESHOLD=>BRAM_THRESHOLD, - USE_CB=>USE_CB, - DSP48E=>DSP48E) -- 1 for DSP48E1, 2 for DSP48E2 - port map(CLK=>CLK, - I=>II, - VI=>VII, - SI=>SII, - O=>OO, - VO=>VOO, - SO=>SOO); - O<=STD_LOGIC_VECTOR(OO); - VO<='1' when VOO else '0'; - SO<=STD_LOGIC_VECTOR(SOO); -end WRAPPER; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -entity WRAPPER_VECTOR_FFT_29450ae4dbd3eb51515dab58c9ac6776 is - generic ( - BRAM_THRESHOLD : integer := 258; - DSP48E : integer := 2; - I_high : integer := -2; - I_low : integer := -17; - L2N : integer := 3; - N : integer := 8; - O_high : integer := 9; - O_low : integer := -17; - SSR : integer := 8; - W_high : integer := 1; - W_low : integer := -17 - ); - port( - I : in std_logic_vector(255 downto 0); - VI : in std_logic; - SI : in std_logic_vector(2 downto 0); - O : out std_logic_vector(431 downto 0); - VO : out std_logic; - SO : out std_logic_vector(2 downto 0); - CLK : in std_logic; - CE : in std_logic - ); -end WRAPPER_VECTOR_FFT_29450ae4dbd3eb51515dab58c9ac6776; -architecture structural of WRAPPER_VECTOR_FFT_29450ae4dbd3eb51515dab58c9ac6776 is - signal I_net : std_logic_vector(255 downto 0); - signal VI_net : std_logic; - signal SI_net : std_logic_vector(2 downto 0); - signal O_net : std_logic_vector(431 downto 0); - signal VO_net : std_logic; - signal SO_net : std_logic_vector(2 downto 0); - signal CLK_net : std_logic; - signal CE_net : std_logic; - component WRAPPER_VECTOR_FFT is - generic ( - BRAM_THRESHOLD : integer := 258; - DSP48E : integer := 2; - I_high : integer := -2; - I_low : integer := -17; - L2N : integer := 3; - N : integer := 8; - O_high : integer := 9; - O_low : integer := -17; - SSR : integer := 8; - W_high : integer := 1; - W_low : integer := -17 - ); - port( - I : in std_logic_vector(255 downto 0); - VI : in std_logic; - SI : in std_logic_vector(2 downto 0); - O : out std_logic_vector(431 downto 0); - VO : out std_logic; - SO : out std_logic_vector(2 downto 0); - CLK : in std_logic; - CE : in std_logic - ); - end component; -begin - I_net <= I; - VI_net <= VI; - SI_net <= SI; - O <= O_net; - VO <= VO_net; - SO <= SO_net; - CLK_net <= CLK; - CE_net <= CE; - WRAPPER_VECTOR_FFT_inst : WRAPPER_VECTOR_FFT - generic map( - BRAM_THRESHOLD => 258, - DSP48E => 2, - I_high => -2, - I_low => -17, - L2N => 3, - N => 8, - O_high => 9, - O_low => -17, - SSR => 8, - W_high => 1, - W_low => -17 - ) - port map( - I => I_net, - VI => VI_net, - SI => SI_net, - O => O_net, - VO => VO_net, - SO => SO_net, - CLK => CLK_net, - CE => CE_net - ); -end structural; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - ---------------------------------------------------------------------- --- --- Filename : xlslice.vhd --- --- Description : VHDL description of a block that sets the output to a --- specified range of the input bits. The output is always --- set to an unsigned type with it's binary point at zero. --- ---------------------------------------------------------------------- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_arith.all; -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - - -entity ssr_8x8_xlslice is - generic ( - new_msb : integer := 9; -- position of new msb - new_lsb : integer := 1; -- position of new lsb - x_width : integer := 16; -- Width of x input - y_width : integer := 8); -- Width of y output - port ( - x : in std_logic_vector (x_width-1 downto 0); - y : out std_logic_vector (y_width-1 downto 0)); -end ssr_8x8_xlslice; - -architecture behavior of ssr_8x8_xlslice is -begin - y <= x(new_msb downto new_lsb); -end behavior; - -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -entity sysgen_concat_965a32611a is - port ( - in0 : in std_logic_vector((16 - 1) downto 0); - in1 : in std_logic_vector((16 - 1) downto 0); - y : out std_logic_vector((32 - 1) downto 0); - clk : in std_logic; - ce : in std_logic; - clr : in std_logic); -end sysgen_concat_965a32611a; -architecture behavior of sysgen_concat_965a32611a -is - signal in0_1_23: unsigned((16 - 1) downto 0); - signal in1_1_27: unsigned((16 - 1) downto 0); - signal y_2_1_concat: unsigned((32 - 1) downto 0); -begin - in0_1_23 <= std_logic_vector_to_unsigned(in0); - in1_1_27 <= std_logic_vector_to_unsigned(in1); - y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27)); - y <= unsigned_to_std_logic_vector(y_2_1_concat); -end behavior; - -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -entity sysgen_reinterpret_d1aaeed629 is - port ( - input_port : in std_logic_vector((16 - 1) downto 0); - output_port : out std_logic_vector((16 - 1) downto 0); - clk : in std_logic; - ce : in std_logic; - clr : in std_logic); -end sysgen_reinterpret_d1aaeed629; -architecture behavior of sysgen_reinterpret_d1aaeed629 -is - signal input_port_1_40: signed((16 - 1) downto 0); - signal output_port_5_5_force: unsigned((16 - 1) downto 0); -begin - input_port_1_40 <= std_logic_vector_to_signed(input_port); - output_port_5_5_force <= signed_to_unsigned(input_port_1_40); - output_port <= unsigned_to_std_logic_vector(output_port_5_5_force); -end behavior; - -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -entity sysgen_reinterpret_4035468568 is - port ( - input_port : in std_logic_vector((27 - 1) downto 0); - output_port : out std_logic_vector((27 - 1) downto 0); - clk : in std_logic; - ce : in std_logic; - clr : in std_logic); -end sysgen_reinterpret_4035468568; -architecture behavior of sysgen_reinterpret_4035468568 -is - signal input_port_1_40: unsigned((27 - 1) downto 0); - signal output_port_5_5_force: signed((27 - 1) downto 0); -begin - input_port_1_40 <= std_logic_vector_to_unsigned(input_port); - output_port_5_5_force <= unsigned_to_signed(input_port_1_40); - output_port <= signed_to_std_logic_vector(output_port_5_5_force); -end behavior; - -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -entity sysgen_concat_7ca5184bef is - port ( - in0 : in std_logic_vector((32 - 1) downto 0); - in1 : in std_logic_vector((32 - 1) downto 0); - in2 : in std_logic_vector((32 - 1) downto 0); - in3 : in std_logic_vector((32 - 1) downto 0); - in4 : in std_logic_vector((32 - 1) downto 0); - in5 : in std_logic_vector((32 - 1) downto 0); - in6 : in std_logic_vector((32 - 1) downto 0); - in7 : in std_logic_vector((32 - 1) downto 0); - y : out std_logic_vector((256 - 1) downto 0); - clk : in std_logic; - ce : in std_logic; - clr : in std_logic); -end sysgen_concat_7ca5184bef; -architecture behavior of sysgen_concat_7ca5184bef -is - signal in0_1_23: unsigned((32 - 1) downto 0); - signal in1_1_27: unsigned((32 - 1) downto 0); - signal in2_1_31: unsigned((32 - 1) downto 0); - signal in3_1_35: unsigned((32 - 1) downto 0); - signal in4_1_39: unsigned((32 - 1) downto 0); - signal in5_1_43: unsigned((32 - 1) downto 0); - signal in6_1_47: unsigned((32 - 1) downto 0); - signal in7_1_51: unsigned((32 - 1) downto 0); - signal y_2_1_concat: unsigned((256 - 1) downto 0); -begin - in0_1_23 <= std_logic_vector_to_unsigned(in0); - in1_1_27 <= std_logic_vector_to_unsigned(in1); - in2_1_31 <= std_logic_vector_to_unsigned(in2); - in3_1_35 <= std_logic_vector_to_unsigned(in3); - in4_1_39 <= std_logic_vector_to_unsigned(in4); - in5_1_43 <= std_logic_vector_to_unsigned(in5); - in6_1_47 <= std_logic_vector_to_unsigned(in6); - in7_1_51 <= std_logic_vector_to_unsigned(in7); - y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31) & unsigned_to_std_logic_vector(in3_1_35) & unsigned_to_std_logic_vector(in4_1_39) & unsigned_to_std_logic_vector(in5_1_43) & unsigned_to_std_logic_vector(in6_1_47) & unsigned_to_std_logic_vector(in7_1_51)); - y <= unsigned_to_std_logic_vector(y_2_1_concat); -end behavior; - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/synth_reg.vhd b/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/synth_reg.vhd deleted file mode 100644 index 770ff70..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/synth_reg.vhd +++ /dev/null @@ -1,95 +0,0 @@ -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - --- $Header: /devl/xcs/repo/env/Jobs/sysgen/src/xbs/hdl_pkg/synth_reg.vhd,v 1.2 2005/01/11 00:33:32 stroomer Exp $ ----------------------------------------------------------------------------- --- --- Filename : synth_reg.vhd --- --- Created : 6/10/2000 --- --- Description : Synthesizable VHDL description of parallel register without --- an init value and a clear. SRLC32E components are used. The --- initial value is always 0 --- ----------------------------------------------------------------------------- - -library IEEE; -use IEEE.std_logic_1164.all; - -entity synth_reg is - generic (width : integer := 8; - latency : integer := 1); - port (i : in std_logic_vector(width-1 downto 0); - ce : in std_logic; - clr : in std_logic; -- Not used since implemented w/ SRLC32s - clk : in std_logic; - o : out std_logic_vector(width-1 downto 0)); -end synth_reg; - -architecture structural of synth_reg is - component srlc33e - generic (width : integer:=16; - latency : integer :=8); - port (clk : in std_logic; - ce : in std_logic; - d : in std_logic_vector(width-1 downto 0); - q : out std_logic_vector(width-1 downto 0)); - end component; - - function calc_num_srlc33es (latency : integer) - return integer - is - variable remaining_latency : integer; - variable result : integer; - begin - result := latency / 33; - - remaining_latency := latency - (result * 33); - -- If latency is not an even multiple of 33 then add one more - -- srlc33e to the pipeline - if (remaining_latency /= 0) then - result := result + 1; - end if; - - return result; - end; - - - constant complete_num_srlc33es : integer := latency / 33; - constant num_srlc33es : integer := calc_num_srlc33es(latency); - constant remaining_latency : integer := latency - (complete_num_srlc33es * 33); - -- Array for std_logic_vectors - type register_array is array (num_srlc33es downto 0) of - std_logic_vector(width-1 downto 0); - signal z : register_array; - -begin - - z(0) <= i; - complete_ones : if complete_num_srlc33es > 0 generate - srlc33e_array: for i in 0 to complete_num_srlc33es-1 generate - delay_comp : srlc33e - generic map (width => width, - latency => 33) - port map (clk => clk, - ce => ce, - d => z(i), - q => z(i+1)); - - end generate; - end generate; - - partial_one : if remaining_latency > 0 generate - last_srlc33e : srlc33e - generic map (width => width, - latency => remaining_latency) - port map (clk => clk, - ce => ce, - d => z(num_srlc33es-1), - q => z(num_srlc33es)); - end generate; - o <= z(num_srlc33es); -end structural; - - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/synth_reg_reg.vhd b/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/synth_reg_reg.vhd deleted file mode 100644 index 5d837de..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/synth_reg_reg.vhd +++ /dev/null @@ -1,64 +0,0 @@ -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - --- $Header: /devl/xcs/repo/env/Jobs/sysgen/src/xbs/hdl_pkg/synth_reg.vhd,v 1.2 2005/01/11 00:33:32 stroomer Exp $ ----------------------------------------------------------------------------- --- --- Filename : synth_reg_reg.vhd --- --- Created : 6/28/2013 --- --- Description : splitted from synth_reg.vhd --- ----------------------------------------------------------------------------- - -library IEEE; -use IEEE.std_logic_1164.all; - -entity synth_reg_reg is - generic (width : integer := 8; - latency : integer := 1); - port (i : in std_logic_vector(width-1 downto 0); - ce : in std_logic; - clr : in std_logic; -- Not used since implemented w/ SRL16s - clk : in std_logic; - o : out std_logic_vector(width-1 downto 0)); -end synth_reg_reg; - -architecture behav of synth_reg_reg is - type reg_array_type is array (latency downto 0) of std_logic_vector(width -1 downto 0); - signal reg_bank : reg_array_type := (others => (others => '0')); - signal reg_bank_in : reg_array_type := (others => (others => '0')); - attribute syn_allow_retiming : boolean; - attribute syn_srlstyle : string; - attribute syn_allow_retiming of reg_bank : signal is true; - attribute syn_allow_retiming of reg_bank_in : signal is true; - attribute syn_srlstyle of reg_bank : signal is "registers"; - attribute syn_srlstyle of reg_bank_in : signal is "registers"; -begin -- behav - - latency_eq_0: if latency = 0 generate - o <= i; - end generate latency_eq_0; - - latency_gt_0: if latency >= 1 generate - o <= reg_bank(latency); - reg_bank(0) <= i; - - sync_loop: for sync_idx in latency downto 1 generate - sync_proc: process (clk) - begin -- process sync_proc - if clk'event and clk = '1' then -- rising clock edge - if clr = '1' then - reg_bank(sync_idx) <= (others => '0'); - elsif ce = '1' then - reg_bank(sync_idx) <= reg_bank(sync_idx-1); - end if; - end if; - end process sync_proc; - end generate sync_loop; - end generate latency_gt_0; - end behav; - - - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/synth_reg_w_init.vhd b/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/synth_reg_w_init.vhd deleted file mode 100644 index 34bfa2e..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/synth_reg_w_init.vhd +++ /dev/null @@ -1,98 +0,0 @@ -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - ----------------------------------------------------------------------------- --- --- Filename : synth_reg_w_init.vhd --- --- Created : 6/10/2000 --- --- Description : Synthesizable VHDL description of parallel register with --- an initial value. The register has clr and ce pins and --- is implemented using flip-flops (i.e., not SRL16s). --- --- Mod. History : Delayed input .1 ns so that there isn't a setup --- violation in the fdse or fdre Unisim models. --- : Changed VHDL so that initial register is passed as a bit --- vector generic value, instead of the const_pkg. --- --- Mod. Dates : 8/10/2001 --- 3/19/2003 ----------------------------------------------------------------------------- - --- synthesis translate_off -library unisim; -use unisim.vcomponents.all; --- synthesis translate_on - -library IEEE; -use IEEE.std_logic_1164.all; - -entity synth_reg_w_init is - generic ( - width: integer := 8; - init_index: integer := 0; - init_value: bit_vector := b"0000"; - latency: integer := 1 - ); - port ( - i: in std_logic_vector(width - 1 downto 0); - ce: in std_logic; - clr: in std_logic; - clk: in std_logic; - o: out std_logic_vector(width - 1 downto 0) - ); -end synth_reg_w_init; - -architecture structural of synth_reg_w_init is - component single_reg_w_init - generic ( - width: integer := 8; - init_index: integer := 0; - init_value: bit_vector := b"0000" - ); - port ( - i: in std_logic_vector(width - 1 downto 0); - ce: in std_logic; - clr: in std_logic; - clk: in std_logic; - o: out std_logic_vector(width - 1 downto 0) - ); - end component; -- end single_reg_w_init - - -- 1D array used to connect all the register together - signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0); - signal dly_clr: std_logic; -begin - latency_eq_0: if (latency = 0) generate - o <= i; - end generate; -- end latency_eq_0 - - latency_gt_0: if (latency >= 1) generate - -- Delayed input 200 ps so that there isn't a setup violation in the - -- fdse or fdre Unisim models - dly_i((latency + 1) * width - 1 downto latency * width) <= i - after 200 ps; - dly_clr <= clr after 200 ps; - - fd_array: for index in latency downto 1 generate - reg_comp: single_reg_w_init - generic map ( - width => width, - init_index => init_index, - init_value => init_value - ) - port map ( - clk => clk, - i => dly_i((index + 1) * width - 1 downto index * width), - o => dly_i(index * width - 1 downto (index - 1) * width), - ce => ce, - clr => dly_clr - ); - end generate; -- end fd_array - - o <= dly_i(width - 1 downto 0); - end generate; -- end latency_gt_0 -end structural; - - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/xlclockdriver_rd.vhd b/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/xlclockdriver_rd.vhd deleted file mode 100644 index 92017d4..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/xlclockdriver_rd.vhd +++ /dev/null @@ -1,338 +0,0 @@ -library xil_defaultlib; -use xil_defaultlib.conv_pkg.all; - ---------------------------------------------------------------------- --- --- Filename : xlclockdriver.vhd --- --- Date : 10/1/99 --- --- Description : VHDL description of a clock enable generator block. --- This code is synthesizable. --- --- Assumptions : period >= 1 --- --- Mod. History : Removed one shot & OR gate --- If period is power of 2 a 1-bit smaller counter --- is used and no sync clear --- : Logic needed for use_bufg generic added --- : Initial ce output is now 0 instead of 1 --- Enable pulse now occurs at the end of the sample --- period, instead of at the start --- : Added pipeline registers --- : added OR gate for sysclr to work properly --- --- Mod. Dates : 7/26/2001 --- : 8/05/2001 --- : 1/02/2002 --- : 11/30/2004 --- : 4/11/2005 --- ---------------------------------------------------------------------- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; --- synthesis translate_off -library unisim; -use unisim.vcomponents.all; --- synthesis translate_on - -entity xlclockdriver is - generic ( - period: integer := 2; - log_2_period: integer := 0; - pipeline_regs: integer := 5; - use_bufg: integer := 0 - ); - port ( - sysclk: in std_logic; - sysclr: in std_logic; - sysce: in std_logic; - clk: out std_logic; - clr: out std_logic; - ce: out std_logic; - ce_logic: out std_logic - ); -end xlclockdriver; - -architecture behavior of xlclockdriver is - component bufg - port ( - i: in std_logic; - o: out std_logic - ); - end component; - - component synth_reg_w_init - generic ( - width: integer; - init_index: integer; - init_value: bit_vector; - latency: integer - ); - port ( - i: in std_logic_vector(width - 1 downto 0); - ce: in std_logic; - clr: in std_logic; - clk: in std_logic; - o: out std_logic_vector(width - 1 downto 0) - ); - end component; - - -- Returns the size of an unsigned integer - -- if power_of_2 is true return value is one less - function size_of_uint(inp: integer; power_of_2: boolean) - return integer - is - constant inp_vec: std_logic_vector(31 downto 0) := - integer_to_std_logic_vector(inp,32, xlUnsigned); - variable result: integer; - begin - result := 32; - for i in 0 to 31 loop - if inp_vec(i) = '1' then - result := i; - end if; - end loop; - if power_of_2 then - return result; - else - return result+1; - end if; - end; - - -- Returns boolean which says if 'inp' is a power of two - function is_power_of_2(inp: std_logic_vector) - return boolean - is - constant width: integer := inp'length; - variable vec: std_logic_vector(width - 1 downto 0); - variable single_bit_set: boolean; - variable more_than_one_bit_set: boolean; - variable result: boolean; - begin - vec := inp; - single_bit_set := false; - more_than_one_bit_set := false; - - -- synthesis translate_off - if (is_XorU(vec)) then - return false; - end if; - -- synthesis translate_on - if width > 0 then - for i in 0 to width - 1 loop - if vec(i) = '1' then - if single_bit_set then - more_than_one_bit_set := true; - end if; - single_bit_set := true; - end if; - end loop; - end if; - if (single_bit_set and not(more_than_one_bit_set)) then - result := true; - else - result := false; - end if; - return result; - end; - - -- Returns initial value for pipeline registers - function ce_reg_init_val(index, period : integer) - return integer - is - variable result: integer; - begin - result := 0; - if ((index mod period) = 0) then - result := 1; - end if; - return result; - end; - - -- Returns the remainder(num_pipeline_regs/period) + 1 - function remaining_pipe_regs(num_pipeline_regs, period : integer) - return integer - is - variable factor, result: integer; - begin - factor := (num_pipeline_regs / period); - result := num_pipeline_regs - (period * factor) + 1; - return result; - end; - - -- Calculate the min - function sg_min(L, R: INTEGER) return INTEGER is - begin - if L < R then - return L; - else - return R; - end if; - end; - - constant max_pipeline_regs : integer := 8; - constant pipe_regs : integer := 5; - - -- Check if requested pipeline regs are greater than the max amount - constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs); - constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period); - - constant period_floor: integer := max(2, period); - constant power_of_2_counter: boolean := - is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned)); - constant cnt_width: integer := - size_of_uint(period_floor, power_of_2_counter); - constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) := - integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned); - constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) := - integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned); - constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) := - integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned); - - signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0'); - signal ce_vec : std_logic_vector(num_pipeline_regs downto 0); - signal ce_vec_logic : std_logic_vector(num_pipeline_regs downto 0); - signal internal_ce: std_logic_vector(0 downto 0); - signal internal_ce_logic: std_logic_vector(0 downto 0); - signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0); -begin - -- Pass through the system clock and clear - clk <= sysclk; - clr <= sysclr; - - -- Clock Number Counter - cntr_gen: process(sysclk) - begin - if sysclk'event and sysclk = '1' then - if (sysce = '1') then - if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then - clk_num <= (others => '0'); - else - clk_num <= clk_num + 1; - end if; - end if; - end if; - end process; - - -- Clear logic for counter - clr_gen: process(clk_num, sysclr) - begin - if power_of_2_counter then - cnt_clr(0) <= sysclr; - else - -- Counter does not reset when clk_num = a power of 2 - if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1 - or sysclr = '1') then - cnt_clr(0) <= '1'; - else - cnt_clr(0) <= '0'; - end if; - end if; - end process; - - clr_reg: synth_reg_w_init - generic map ( - width => 1, - init_index => 0, - init_value => b"0000", - latency => 1 - ) - port map ( - i => cnt_clr, - ce => sysce, - clr => sysclr, - clk => sysclk, - o => cnt_clr_dly - ); - - -- Clock enable generation - pipelined_ce : if period > 1 generate - ce_gen: process(clk_num) - begin - if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then - ce_vec(num_pipeline_regs) <= '1'; - else - ce_vec(num_pipeline_regs) <= '0'; - end if; - end process; - ce_pipeline: for index in num_pipeline_regs downto 1 generate - ce_reg : synth_reg_w_init - generic map ( - width => 1, - init_index => ce_reg_init_val(index, period), - init_value => b"0000", -- not used - latency => 1 - ) - port map ( - i => ce_vec(index downto index), - ce => sysce, - clr => sysclr, - clk => sysclk, - o => ce_vec(index-1 downto index-1) - ); - end generate; -- i - internal_ce <= ce_vec(0 downto 0); - end generate; - - -- Clock enable generation - pipelined_ce_logic: if period > 1 generate - ce_gen_logic: process(clk_num) - begin - if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then - ce_vec_logic(num_pipeline_regs) <= '1'; - else - ce_vec_logic(num_pipeline_regs) <= '0'; - end if; - end process; - ce_logic_pipeline: for index in num_pipeline_regs downto 1 generate - ce_logic_reg : synth_reg_w_init - generic map ( - width => 1, - init_index => ce_reg_init_val(index, period), - init_value => b"0000", -- not used - latency => 1 - ) - port map ( - i => ce_vec_logic(index downto index), - ce => sysce, - clr => sysclr, - clk => sysclk, - o => ce_vec_logic(index-1 downto index-1) - ); - end generate; -- i - internal_ce_logic <= ce_vec_logic(0 downto 0); - end generate; - - - use_bufg_true: if period > 1 and use_bufg = 1 generate - -- Clock enable with bufg - ce_bufg_inst: bufg - port map ( - i => internal_ce(0), - o => ce - ); - ce_bufg_inst_logic: bufg - port map ( - i => internal_ce_logic(0), - o => ce_logic - ); - end generate; - - use_bufg_false: if period > 1 and (use_bufg = 0) generate - -- Clock enable without bufg - ce <= internal_ce(0) and sysce; - ce_logic <= internal_ce_logic(0) and sysce; - end generate; - - generate_system_clk: if period = 1 generate - ce <= sysce; - ce_logic <= sysce; - end generate; -end architecture behavior; - - - - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssrfft_8x8.vhd b/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssrfft_8x8.vhd deleted file mode 100644 index b788869..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssrfft_8x8.vhd +++ /dev/null @@ -1,196 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity ssrfft_8x8 is - Generic - ( - NFFT : Integer := 8; - SSR : Integer := 8; - B : Integer := 16 - ); - Port - ( - -- Reset and clock. - aresetn : in std_logic; - aclk : in std_logic; - - -- AXIS Slave. - s_axis_tdata : in std_logic_vector (SSR*2*B-1 downto 0); - s_axis_tvalid : in std_logic; - - -- AXIS Master. - m_axis_tdata : out std_logic_vector (SSR*2*B-1 downto 0); - m_axis_tvalid : out std_logic; - - -- Registers. - SCALE_REG : in std_logic_vector (31 downto 0); - QOUT_REG : in std_logic_vector (31 downto 0) - ); -end entity; - -architecture rtl of ssrfft_8x8 is - --- SSR FFT 8x8. -component ssr_8x8 is - port ( - -- Clock signal. - clk : in std_logic; - - -- Input data. - i_re_0 : in std_logic_vector( 16-1 downto 0 ); - i_re_1 : in std_logic_vector( 16-1 downto 0 ); - i_re_2 : in std_logic_vector( 16-1 downto 0 ); - i_re_3 : in std_logic_vector( 16-1 downto 0 ); - i_re_4 : in std_logic_vector( 16-1 downto 0 ); - i_re_5 : in std_logic_vector( 16-1 downto 0 ); - i_re_6 : in std_logic_vector( 16-1 downto 0 ); - i_re_7 : in std_logic_vector( 16-1 downto 0 ); - i_im_0 : in std_logic_vector( 16-1 downto 0 ); - i_im_1 : in std_logic_vector( 16-1 downto 0 ); - i_im_2 : in std_logic_vector( 16-1 downto 0 ); - i_im_3 : in std_logic_vector( 16-1 downto 0 ); - i_im_4 : in std_logic_vector( 16-1 downto 0 ); - i_im_5 : in std_logic_vector( 16-1 downto 0 ); - i_im_6 : in std_logic_vector( 16-1 downto 0 ); - i_im_7 : in std_logic_vector( 16-1 downto 0 ); - i_valid : in std_logic_vector( 1-1 downto 0 ); - i_scale : in std_logic_vector( 3-1 downto 0 ); - - -- Output data. - o_re_0 : out std_logic_vector( 27-1 downto 0 ); - o_re_1 : out std_logic_vector( 27-1 downto 0 ); - o_re_2 : out std_logic_vector( 27-1 downto 0 ); - o_re_3 : out std_logic_vector( 27-1 downto 0 ); - o_re_4 : out std_logic_vector( 27-1 downto 0 ); - o_re_5 : out std_logic_vector( 27-1 downto 0 ); - o_re_6 : out std_logic_vector( 27-1 downto 0 ); - o_re_7 : out std_logic_vector( 27-1 downto 0 ); - o_im_0 : out std_logic_vector( 27-1 downto 0 ); - o_im_1 : out std_logic_vector( 27-1 downto 0 ); - o_im_2 : out std_logic_vector( 27-1 downto 0 ); - o_im_3 : out std_logic_vector( 27-1 downto 0 ); - o_im_4 : out std_logic_vector( 27-1 downto 0 ); - o_im_5 : out std_logic_vector( 27-1 downto 0 ); - o_im_6 : out std_logic_vector( 27-1 downto 0 ); - o_im_7 : out std_logic_vector( 27-1 downto 0 ); - o_valid : out std_logic_vector( 1-1 downto 0); - o_scale : out std_logic_vector( 3-1 downto 0 ) - ); -end component; - --- Vectors with individual I,Q samples. -type data_v is array (SSR-1 downto 0) of std_logic_vector (B-1 downto 0); -signal din_iv : data_v; -signal din_qv : data_v; -signal dout_iv : data_v; -signal dout_qv : data_v; - --- Vector with individual I,Q samples (fft out full precision). -type data_vf is array (SSR-1 downto 0) of std_logic_vector (27-1 downto 0); -signal dout_ivf : data_vf; -signal dout_qvf : data_vf; - --- I,Q parts of input and output. -signal din_i : std_logic_vector (SSR*B-1 downto 0); -signal din_q : std_logic_vector (SSR*B-1 downto 0); -signal dout_i : std_logic_vector (SSR*B-1 downto 0); -signal dout_q : std_logic_vector (SSR*B-1 downto 0); - --- FFT scale. -signal o_scale : std_logic_vector (2 downto 0); - --- FFT output valid. -signal o_axis_tvalid : std_logic; - --- FFT data output. -signal o_axis_tdata : std_logic_vector (2*SSR*B-1 downto 0); - --- Registers. -signal scale_reg_i : std_logic_vector (2 downto 0); -signal qout_reg_i : unsigned (2 downto 0); - -begin - --- Registers. -scale_reg_i <= SCALE_REG (2 downto 0); - --- Full-precision output: 27 bits. Required output: 16 bits. --- Quantization selection from 0 to 11. -qout_reg_i <= (others => '0') when ( unsigned(QOUT_REG) > to_unsigned(11,QOUT_REG'length) ) else - unsigned(QOUT_REG(2 downto 0)); - --- Input/output data. -din_i <= s_axis_tdata (SSR*B-1 downto 0); -din_q <= s_axis_tdata (2*SSR*B-1 downto SSR*B); -o_axis_tdata(SSR*B-1 downto 0) <= dout_i; -o_axis_tdata(2*SSR*B-1 downto SSR*B) <= dout_q; - --- Input/output data to vector. -GEN: for I in 0 to SSR-1 generate - -- Input data to vector. - din_iv(I) <= din_i((I+1)*B-1 downto I*B); - din_qv(I) <= din_q((I+1)*B-1 downto I*B); - - -- Quantization selection. - dout_iv(I) <= dout_ivf(I)(to_integer(qout_reg_i)+B-1 downto to_integer(qout_reg_i)); - dout_qv(I) <= dout_qvf(I)(to_integer(qout_reg_i)+B-1 downto to_integer(qout_reg_i)); - - -- Output data to vector. - dout_i((I+1)*B-1 downto I*B) <= dout_iv(I); - dout_q((I+1)*B-1 downto I*B) <= dout_qv(I); -end generate GEN; - --- SSR FFT 8x8. -ssr_8x8_i : ssr_8x8 - port map ( - -- Clock signal. - clk => aclk , - - -- Input data. - i_re_0 => din_iv(0) , - i_re_1 => din_iv(1) , - i_re_2 => din_iv(2) , - i_re_3 => din_iv(3) , - i_re_4 => din_iv(4) , - i_re_5 => din_iv(5) , - i_re_6 => din_iv(6) , - i_re_7 => din_iv(7) , - i_im_0 => din_qv(0) , - i_im_1 => din_qv(1) , - i_im_2 => din_qv(2) , - i_im_3 => din_qv(3) , - i_im_4 => din_qv(4) , - i_im_5 => din_qv(5) , - i_im_6 => din_qv(6) , - i_im_7 => din_qv(7) , - i_valid(0) => s_axis_tvalid , - i_scale => scale_reg_i , - - -- Output data. - o_re_0 => dout_ivf(0) , - o_re_1 => dout_ivf(1) , - o_re_2 => dout_ivf(2) , - o_re_3 => dout_ivf(3) , - o_re_4 => dout_ivf(4) , - o_re_5 => dout_ivf(5) , - o_re_6 => dout_ivf(6) , - o_re_7 => dout_ivf(7) , - o_im_0 => dout_qvf(0) , - o_im_1 => dout_qvf(1) , - o_im_2 => dout_qvf(2) , - o_im_3 => dout_qvf(3) , - o_im_4 => dout_qvf(4) , - o_im_5 => dout_qvf(5) , - o_im_6 => dout_qvf(6) , - o_im_7 => dout_qvf(7) , - o_valid(0) => o_axis_tvalid , - o_scale => o_scale - ); - --- Assign outputs. -m_axis_tdata <= o_axis_tdata; -m_axis_tvalid <= o_axis_tvalid; - -end rtl; - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/tb.vhd b/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/tb.vhd deleted file mode 100644 index c2445f1..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/tb.vhd +++ /dev/null @@ -1,224 +0,0 @@ --- %%%%%%%%%%%%%%%%%%% Test Description %%%%%%%%%%%%%%%%%%%%% --- --- This test is for understanding if moving tvalid makes the --- block to generate incorrect tlast at the output. --- --- %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; -use IEEE.STD_LOGIC_TEXTIO.ALL; -use STD.TEXTIO.ALL; - -entity tb is -end tb; - -architecture rtl of tb is - --- DUT. -component ssrfft_8x8 is - Generic - ( - NFFT : Integer := 8; - SSR : Integer := 8; - B : Integer := 16 - ); - Port - ( - -- Reset and clock. - aresetn : in std_logic; - aclk : in std_logic; - - -- AXIS Slave. - s_axis_tdata : in std_logic_vector (SSR*2*B-1 downto 0); - s_axis_tvalid : in std_logic; - - -- AXIS Master. - m_axis_tdata : out std_logic_vector (SSR*2*B-1 downto 0); - m_axis_tvalid : out std_logic; - - -- Registers. - SCALE_REG : in std_logic_vector (31 downto 0); - QOUT_REG : in std_logic_vector (31 downto 0) - ); -end component; - -constant NFFT : Integer := 8; -constant SSR : Integer := 8; -constant B : Integer := 16; - -signal aresetn : std_logic; -signal aclk : std_logic; -signal s_axis_tdata : std_logic_vector (SSR*2*B-1 downto 0) := (others => '0'); -signal s_axis_tvalid : std_logic := '0'; - -signal m_axis_tdata : std_logic_vector (SSR*2*B-1 downto 0); -signal m_axis_tvalid : std_logic; - -signal SCALE_REG : std_logic_vector (31 downto 0) := (others => '0'); -signal QOUT_REG : std_logic_vector (31 downto 0) := std_logic_vector(to_unsigned(0,32)); - --- TB control. -signal rd_start : std_logic := '0'; - -signal i_re_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); -signal i_re_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); -signal i_re_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); -signal i_re_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); -signal i_re_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); -signal i_re_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); -signal i_re_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); -signal i_re_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); -signal i_im_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); -signal i_im_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); -signal i_im_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); -signal i_im_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); -signal i_im_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); -signal i_im_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); -signal i_im_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); -signal i_im_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); - -signal o_re_0 : std_logic_vector( 16-1 downto 0 ); -signal o_re_1 : std_logic_vector( 16-1 downto 0 ); -signal o_re_2 : std_logic_vector( 16-1 downto 0 ); -signal o_re_3 : std_logic_vector( 16-1 downto 0 ); -signal o_re_4 : std_logic_vector( 16-1 downto 0 ); -signal o_re_5 : std_logic_vector( 16-1 downto 0 ); -signal o_re_6 : std_logic_vector( 16-1 downto 0 ); -signal o_re_7 : std_logic_vector( 16-1 downto 0 ); -signal o_im_0 : std_logic_vector( 16-1 downto 0 ); -signal o_im_1 : std_logic_vector( 16-1 downto 0 ); -signal o_im_2 : std_logic_vector( 16-1 downto 0 ); -signal o_im_3 : std_logic_vector( 16-1 downto 0 ); -signal o_im_4 : std_logic_vector( 16-1 downto 0 ); -signal o_im_5 : std_logic_vector( 16-1 downto 0 ); -signal o_im_6 : std_logic_vector( 16-1 downto 0 ); -signal o_im_7 : std_logic_vector( 16-1 downto 0 ); - -begin - --- DUT. -DUT : ssrfft_8x8 - Generic map - ( - NFFT => NFFT , - SSR => SSR , - B => B - ) - Port map - ( - -- Reset and clock. - aresetn => aresetn , - aclk => aclk , - - -- AXIS Slave. - s_axis_tdata => s_axis_tdata , - s_axis_tvalid => s_axis_tvalid , - - -- AXIS Master. - m_axis_tdata => m_axis_tdata , - m_axis_tvalid => m_axis_tvalid , - - -- Registers. - SCALE_REG => SCALE_REG , - QOUT_REG => QOUT_REG - ); - --- Input data. -s_axis_tdata <= i_im_7 & i_im_6 & i_im_5 & i_im_4 & i_im_3 & i_im_2 & i_im_1 & i_im_0 & - i_re_7 & i_re_6 & i_re_5 & i_re_4 & i_re_3 & i_re_2 & i_re_1 & i_re_0; - --- Output data. -o_re_0 <= m_axis_tdata (1*B-1 downto 0*B); -o_re_1 <= m_axis_tdata (2*B-1 downto 1*B); -o_re_2 <= m_axis_tdata (3*B-1 downto 2*B); -o_re_3 <= m_axis_tdata (4*B-1 downto 3*B); -o_re_4 <= m_axis_tdata (5*B-1 downto 4*B); -o_re_5 <= m_axis_tdata (6*B-1 downto 5*B); -o_re_6 <= m_axis_tdata (7*B-1 downto 6*B); -o_re_7 <= m_axis_tdata (8*B-1 downto 7*B); -o_im_0 <= m_axis_tdata (9*B-1 downto 8*B); -o_im_1 <= m_axis_tdata (10*B-1 downto 9*B); -o_im_2 <= m_axis_tdata (11*B-1 downto 10*B); -o_im_3 <= m_axis_tdata (12*B-1 downto 11*B); -o_im_4 <= m_axis_tdata (13*B-1 downto 12*B); -o_im_5 <= m_axis_tdata (14*B-1 downto 13*B); -o_im_6 <= m_axis_tdata (15*B-1 downto 14*B); -o_im_7 <= m_axis_tdata (16*B-1 downto 15*B); - --- Main TB. -process -begin - aresetn <= '0'; - wait for 250 ns; - aresetn <= '1'; - - wait for 300 ns; - - rd_start <= '1'; - wait for 110 ns; - rd_start <= '0'; - wait for 220 ns; - rd_start <= '1'; - wait for 490 ns; - rd_start <= '0'; - wait for 100 ns; - rd_start <= '1'; - - wait for 20 us; - -end process; - --- Data process. -process - variable I : Integer := 0; - - begin - - for K in 0 to 200 loop - for J in 0 to 0 loop - while rd_start = '0' loop - wait until rising_edge(aclk); - s_axis_tvalid <= '0'; - end loop; - wait until rising_edge(aclk); - s_axis_tvalid <= '1'; - i_re_0 <= std_logic_vector(to_signed(0,i_re_0'length)); - i_re_1 <= std_logic_vector(to_signed(20000,i_re_0'length)); - i_re_2 <= std_logic_vector(to_signed(0,i_re_0'length)); - i_re_3 <= std_logic_vector(to_signed(0,i_re_0'length)); - i_re_4 <= std_logic_vector(to_signed(0,i_re_0'length)); - i_re_5 <= std_logic_vector(to_signed(0,i_re_0'length)); - i_re_6 <= std_logic_vector(to_signed(0,i_re_0'length)); - i_re_7 <= std_logic_vector(to_signed(0,i_re_0'length)); - i_im_0 <= std_logic_vector(to_signed(0,i_re_0'length)); - i_im_1 <= std_logic_vector(to_signed(20000,i_re_0'length)); - i_im_2 <= std_logic_vector(to_signed(0,i_re_0'length)); - i_im_3 <= std_logic_vector(to_signed(0,i_re_0'length)); - i_im_4 <= std_logic_vector(to_signed(0,i_re_0'length)); - i_im_5 <= std_logic_vector(to_signed(0,i_re_0'length)); - i_im_6 <= std_logic_vector(to_signed(0,i_re_0'length)); - i_im_7 <= std_logic_vector(to_signed(0,i_re_0'length)); - - I := I + 1; - end loop; - - while rd_start = '0' loop - wait until rising_edge(aclk); - s_axis_tvalid <= '0'; - end loop; - end loop; - -end process; - --- Clock. -process -begin - aclk <= '0'; - wait for 5 ns; - aclk <= '1'; - wait for 5 ns; -end process; - -end rtl; - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/src/tb/tb.sv b/qick/firmware/ip/axis_pfb_readout_v2/src/tb/tb.sv deleted file mode 100644 index 47777ab..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/src/tb/tb.sv +++ /dev/null @@ -1,361 +0,0 @@ -import axi_vip_pkg::*; -import axi_mst_0_pkg::*; - -module tb(); - -// s_axi interfase. -reg s_axi_aclk; -reg s_axi_aresetn; -wire [5:0] s_axi_araddr; -wire [2:0] s_axi_arprot; -wire s_axi_arready; -wire s_axi_arvalid; -wire [5:0] s_axi_awaddr; -wire [2:0] s_axi_awprot; -wire s_axi_awready; -wire s_axi_awvalid; -wire s_axi_bready; -wire [1:0] s_axi_bresp; -wire s_axi_bvalid; -wire [31:0] s_axi_rdata; -wire s_axi_rready; -wire [1:0] s_axi_rresp; -wire s_axi_rvalid; -wire [31:0] s_axi_wdata; -wire s_axi_wready; -wire [3:0] s_axi_wstrb; -wire s_axi_wvalid; - -reg aresetn; -reg aclk; - -wire s_axis_tready; -reg s_axis_tvalid; -reg [4*32-1:0] s_axis_tdata; - -wire m0_axis_tvalid; -reg [31:0] m0_axis_tdata; -wire m1_axis_tvalid; -reg [31:0] m1_axis_tdata; -wire m2_axis_tvalid; -reg [31:0] m2_axis_tdata; -wire m3_axis_tvalid; -reg [31:0] m3_axis_tdata; - - -xil_axi_prot_t prot = 0; -reg[31:0] data_wr = 32'h12345678; -reg[31:0] data; -xil_axi_resp_t resp; - -// Input data. -reg [31:0] din_ii [0:7]; - -// Test bench control. -reg tb_data = 0; -reg tb_data_done= 0; -reg tb_write_out= 0; - - -generate -genvar ii; -for (ii = 0; ii < 8; ii = ii + 1) begin - assign s_axis_tdata[32*ii +: 32] = din_ii[ii]; -end -endgenerate - -// axi_mst_0. -axi_mst_0 axi_mst_0_i - ( - .aclk (s_axi_aclk ), - .aresetn (s_axi_aresetn ), - .m_axi_araddr (s_axi_araddr ), - .m_axi_arprot (s_axi_arprot ), - .m_axi_arready (s_axi_arready ), - .m_axi_arvalid (s_axi_arvalid ), - .m_axi_awaddr (s_axi_awaddr ), - .m_axi_awprot (s_axi_awprot ), - .m_axi_awready (s_axi_awready ), - .m_axi_awvalid (s_axi_awvalid ), - .m_axi_bready (s_axi_bready ), - .m_axi_bresp (s_axi_bresp ), - .m_axi_bvalid (s_axi_bvalid ), - .m_axi_rdata (s_axi_rdata ), - .m_axi_rready (s_axi_rready ), - .m_axi_rresp (s_axi_rresp ), - .m_axi_rvalid (s_axi_rvalid ), - .m_axi_wdata (s_axi_wdata ), - .m_axi_wready (s_axi_wready ), - .m_axi_wstrb (s_axi_wstrb ), - .m_axi_wvalid (s_axi_wvalid ) - ); - -axis_pfb_readout_v2 - DUT - ( - // AXI Slave I/F for configuration. - .s_axi_aclk (s_axi_aclk ), - .s_axi_aresetn (s_axi_aresetn ), - .s_axi_araddr (s_axi_araddr ), - .s_axi_arprot (s_axi_arprot ), - .s_axi_arready (s_axi_arready ), - .s_axi_arvalid (s_axi_arvalid ), - .s_axi_awaddr (s_axi_awaddr ), - .s_axi_awprot (s_axi_awprot ), - .s_axi_awready (s_axi_awready ), - .s_axi_awvalid (s_axi_awvalid ), - .s_axi_bready (s_axi_bready ), - .s_axi_bresp (s_axi_bresp ), - .s_axi_bvalid (s_axi_bvalid ), - .s_axi_rdata (s_axi_rdata ), - .s_axi_rready (s_axi_rready ), - .s_axi_rresp (s_axi_rresp ), - .s_axi_rvalid (s_axi_rvalid ), - .s_axi_wdata (s_axi_wdata ), - .s_axi_wready (s_axi_wready ), - .s_axi_wstrb (s_axi_wstrb ), - .s_axi_wvalid (s_axi_wvalid ), - - // s_* and m_* reset/clock. - .aresetn (aresetn ), - .aclk (aclk ), - - // S_AXIS for input samples. - .s_axis_tvalid (s_axis_tvalid ), - .s_axis_tready (s_axis_tready ), - .s_axis_tdata (s_axis_tdata ), - - // M_AXIS for CH0 output. - .m0_axis_tvalid (m0_axis_tvalid ), - .m0_axis_tdata (m0_axis_tdata ), - - // M_AXIS for CH1 output. - .m1_axis_tvalid (m1_axis_tvalid ), - .m1_axis_tdata (m1_axis_tdata ), - - // M_AXIS for CH2 output. - .m2_axis_tvalid (m2_axis_tvalid ), - .m2_axis_tdata (m2_axis_tdata ), - - // M_AXIS for CH3 output. - .m3_axis_tvalid (m3_axis_tvalid ), - .m3_axis_tdata (m3_axis_tdata ) - ); - -// VIP Agents -axi_mst_0_mst_t axi_mst_0_agent; - -initial begin - // Create agents. - axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); - - // Set tag for agents. - axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); - - // Start agents. - axi_mst_0_agent.start_master(); - - // Reset sequence. - s_axi_aresetn <= 0; - aresetn <= 0; - #500; - s_axi_aresetn <= 1; - aresetn <= 1; - - #1000; - - $display("###################"); - $display("### Program DDS ###"); - $display("###################"); - $display("t = %0t", $time); - - // FREQ. - //for (int i=0; i<8; i = i+1) begin - // data_wr = freq_calc(100, i+10); - // axi_mst_0_agent.AXI4LITE_WRITE_BURST(i*4, prot, data_wr, resp); - // #10; - //end - - // FREQ0. - data_wr = freq_calc(100, 3.8); - axi_mst_0_agent.AXI4LITE_WRITE_BURST(0*4, prot, data_wr, resp); - #10; - - // FREQ1. - data_wr = freq_calc(100, 92); - axi_mst_0_agent.AXI4LITE_WRITE_BURST(1*4, prot, data_wr, resp); - #10; - - // FREQ2. - data_wr = freq_calc(100, 13.5); - axi_mst_0_agent.AXI4LITE_WRITE_BURST(2*4, prot, data_wr, resp); - #10; - - // FREQ3. - data_wr = freq_calc(100, 12.2); - axi_mst_0_agent.AXI4LITE_WRITE_BURST(3*4, prot, data_wr, resp); - #10; - - // FREQ4. - data_wr = freq_calc(100, 87); - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*4, prot, data_wr, resp); - #10; - - // FREQ5. - data_wr = freq_calc(100, 95); - axi_mst_0_agent.AXI4LITE_WRITE_BURST(5*4, prot, data_wr, resp); - #10; - - // FREQ6. - data_wr = freq_calc(100, 92); - axi_mst_0_agent.AXI4LITE_WRITE_BURST(6*4, prot, data_wr, resp); - #10; - - // FREQ7. - data_wr = freq_calc(100, 93); - axi_mst_0_agent.AXI4LITE_WRITE_BURST(7*4, prot, data_wr, resp); - #10; - - // OUTSEL. - data_wr = 1; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(8*4, prot, data_wr, resp); - #10; - - // CH0SEL. - data_wr = 0; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(9*4, prot, data_wr, resp); - #10; - - // CH1SEL. - data_wr = 1; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(10*4, prot, data_wr, resp); - #10; - - // CH2SEL. - data_wr = 4; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(11*4, prot, data_wr, resp); - #10; - - // CH3SEL. - data_wr = 7; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(12*4, prot, data_wr, resp); - #10; - - $display("###############################"); - $display("### Start Recording Outputs ###"); - $display("###############################"); - $display("t = %0t", $time); - - tb_data <= 1; - tb_write_out <= 1; - wait (tb_data_done); - tb_write_out <= 0; - -end - -// Input data. -initial begin - int fd; - int i; - bit signed [15:0] vali, valq; - s_axis_tvalid <= 0; - s_axis_tdata <= 0; - - // Open file with Coefficients. - fd = $fopen("../../../../../tb/data_iq.txt","r"); - - wait(tb_data); - @(posedge aclk); - - i = 0; - while ($fscanf(fd,"%d,%d", vali, valq) == 2) begin - //$display("T = %d, i = %d, I = %d, Q = %d", $time, i, vali, valq); - din_ii[i] <= {valq,vali}; - i = i + 1; - if (i == 4) begin - i = 0; - @(posedge aclk); - s_axis_tvalid <= 1; - end - end - - @(posedge aclk); - s_axis_tvalid <= 0; - tb_data_done <= 1; - -end - -// Write output into file. -initial begin - int fd0, fd1, fd2, fd3; - int i; - shortint real_d0, imag_d0; - shortint real_d1, imag_d1; - shortint real_d2, imag_d2; - shortint real_d3, imag_d3; - - // Output file. - fd0 = $fopen("../../../../../tb/dout_0.csv","w"); - fd1 = $fopen("../../../../../tb/dout_1.csv","w"); - fd2 = $fopen("../../../../../tb/dout_2.csv","w"); - fd3 = $fopen("../../../../../tb/dout_3.csv","w"); - - // Data format. - $fdisplay(fd0, "valid, real, imag"); - $fdisplay(fd1, "valid, real, imag"); - $fdisplay(fd2, "valid, real, imag"); - $fdisplay(fd3, "valid, real, imag"); - - wait (tb_write_out); - - while (tb_write_out) begin - @(posedge aclk); - real_d0 = m0_axis_tdata[15:0]; - imag_d0 = m0_axis_tdata[31:16]; - real_d1 = m1_axis_tdata[15:0]; - imag_d1 = m1_axis_tdata[31:16]; - real_d2 = m2_axis_tdata[15:0]; - imag_d2 = m2_axis_tdata[31:16]; - real_d3 = m3_axis_tdata[15:0]; - imag_d3 = m3_axis_tdata[31:16]; - $fdisplay(fd0,"%d,%d,%d",m0_axis_tvalid,real_d0,imag_d0); - $fdisplay(fd1,"%d,%d,%d",m1_axis_tvalid,real_d1,imag_d1); - $fdisplay(fd2,"%d,%d,%d",m2_axis_tvalid,real_d2,imag_d2); - $fdisplay(fd3,"%d,%d,%d",m3_axis_tvalid,real_d3,imag_d3); - end - - $display("Closing file, t = %0t", $time); - $fclose(fd0); - $fclose(fd1); - $fclose(fd2); - $fclose(fd3); -end - -always begin - s_axi_aclk <= 0; - #10; - s_axi_aclk <= 1; - #10; -end - -always begin - aclk <= 0; - #5; - aclk <= 1; - #5; -end - -// Function to compute frequency register. -function [31:0] freq_calc; - input int fclk; - input real f; - - // All input frequencies are in MHz. - real fs,temp; - fs = fclk; - temp = f/fs*2**30; - freq_calc = {int'(temp),2'b00}; -endfunction - -endmodule - diff --git a/qick/firmware/ip/axis_pfb_readout_v2/xgui/axis_pfb_readout_v2_v1_0.tcl b/qick/firmware/ip/axis_pfb_readout_v2/xgui/axis_pfb_readout_v2_v1_0.tcl deleted file mode 100644 index 9eea8a8..0000000 --- a/qick/firmware/ip/axis_pfb_readout_v2/xgui/axis_pfb_readout_v2_v1_0.tcl +++ /dev/null @@ -1,25 +0,0 @@ -# Definitional proc to organize widgets for parameters. -proc init_gui { IPINST } { - ipgui::add_param $IPINST -name "Component_Name" - #Adding Page - ipgui::add_page $IPINST -name "Page 0" - - ipgui::add_param $IPINST -name "INTERLEAVED_INPUT" - -} - -proc update_PARAM_VALUE.INTERLEAVED_INPUT { PARAM_VALUE.INTERLEAVED_INPUT } { - # Procedure called to update INTERLEAVED_INPUT when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.INTERLEAVED_INPUT { PARAM_VALUE.INTERLEAVED_INPUT } { - # Procedure called to validate INTERLEAVED_INPUT - return true -} - - -proc update_MODELPARAM_VALUE.INTERLEAVED_INPUT { MODELPARAM_VALUE.INTERLEAVED_INPUT PARAM_VALUE.INTERLEAVED_INPUT } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.INTERLEAVED_INPUT}] ${MODELPARAM_VALUE.INTERLEAVED_INPUT} -} - diff --git a/qick/firmware/ip/axis_readout_v1/component.xml b/qick/firmware/ip/axis_readout_v1/component.xml deleted file mode 100644 index 1fe2856..0000000 --- a/qick/firmware/ip/axis_readout_v1/component.xml +++ /dev/null @@ -1,1299 +0,0 @@ - - - user.org - user - axis_readout_v1 - 1.0 - - - m0_axis - - - - - - - TDATA - - - m0_axis_tdata - - - - - TVALID - - - m0_axis_tvalid - - - - - TREADY - - - m0_axis_tready - - - - - - m1_axis - - - - - - - TDATA - - - m1_axis_tdata - - - - - TVALID - - - m1_axis_tvalid - - - - - TREADY - - - m1_axis_tready - - - - - - s_axi - - - - - - - - - AWADDR - - - s_axi_awaddr - - - - - AWPROT - - - s_axi_awprot - - - - - AWVALID - - - s_axi_awvalid - - - - - AWREADY - - - s_axi_awready - - - - - WDATA - - - s_axi_wdata - - - - - WSTRB - - - s_axi_wstrb - - - - - WVALID - - - s_axi_wvalid - - - - - WREADY - - - s_axi_wready - - - - - BRESP - - - s_axi_bresp - - - - - BVALID - - - s_axi_bvalid - - - - - BREADY - - - s_axi_bready - - - - - ARADDR - - - s_axi_araddr - - - - - ARPROT - - - s_axi_arprot - - - - - ARVALID - - - s_axi_arvalid - - - - - ARREADY - - - s_axi_arready - - - - - RDATA - - - s_axi_rdata - - - - - RRESP - - - s_axi_rresp - - - - - RVALID - - - s_axi_rvalid - - - - - RREADY - - - s_axi_rready - - - - - - s_axi_aclk - - - - - - - CLK - - - s_axi_aclk - - - - - - ASSOCIATED_BUSIF - s_axi - - - ASSOCIATED_RESET - s_axi_aresetn - - - - - s_axi_aresetn - - - - - - - RST - - - s_axi_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - s_axis - - - - - - - TDATA - - - s_axis_tdata - - - - - TVALID - - - s_axis_tvalid - - - - - TREADY - - - s_axis_tready - - - - - - aclk - - - - - - - CLK - - - aclk - - - - - - ASSOCIATED_BUSIF - m0_axis:m1_axis:s_axis - - - ASSOCIATED_RESET - aresetn - - - - - aresetn - - - - - - - RST - - - aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - - - s_axi - - reg0 - 0 - 64 - 32 - register - - - - - - - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis - Verilog - axis_readout_v1 - - xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset - - - xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset - - - xilinx_anylanguagesynthesis_view_fileset - - - - viewChecksum - f74e8136 - - - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - Verilog - axis_readout_v1 - - xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset - - - xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - - - viewChecksum - f74e8136 - - - - - xilinx_xpgui - UI Layout - :vivado.xilinx.com:xgui.ui - - xilinx_xpgui_view_fileset - - - - viewChecksum - f92e9879 - - - - - - - s_axi_aclk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_aresetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_awaddr - - in - - 5 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_awprot - - in - - 2 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_awvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_awready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_wdata - - in - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_wstrb - - in - - 3 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 1 - - - - - s_axi_wvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_wready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_bresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_bvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_bready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_araddr - - in - - 5 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_arprot - - in - - 2 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_arvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_arready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_rdata - - out - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_rresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_rvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_rready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - aresetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - aclk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axis_tdata - - in - - 127 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axis_tvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axis_tready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m0_axis_tready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 1 - - - - - m0_axis_tvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m0_axis_tdata - - out - - 255 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m1_axis_tready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 1 - - - - - m1_axis_tvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m1_axis_tdata - - out - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - - - choice_list_9d8b0d81 - ACTIVE_HIGH - ACTIVE_LOW - - - - - xilinx_anylanguagesynthesis_view_fileset - - src/fir_compiler_0/fir_compiler_0.xci - xci - - - src/dds_compiler_0/dds_compiler_0.xci - xci - - - src/down_conversion.v - verilogSource - - - src/down_conversion_fir.v - verilogSource - - - src/readout_top.v - verilogSource - - - src/ctrl.sv - systemVerilogSource - - - src/axi_slv.vhd - vhdlSource - - - src/fir.coe - coe - - - src/axis_readout_v1.v - verilogSource - CHECKSUM_795757c0 - - - - xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset - - - - - - - - - - xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset - - - - - - - - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - src/fir_compiler_0/fir_compiler_0.xci - xci - - - src/dds_compiler_0/dds_compiler_0.xci - xci - - - src/down_conversion.v - verilogSource - - - src/down_conversion_fir.v - verilogSource - - - src/readout_top.v - verilogSource - - - src/ctrl.sv - systemVerilogSource - - - src/axi_slv.vhd - vhdlSource - - - src/fir.coe - coe - - - src/axis_readout_v1.v - verilogSource - - - - xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset - - - - - - - - - - xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset - - - - - - - - - - xilinx_xpgui_view_fileset - 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/home/lstefana/qsystem_2/ip/axis_readout_v1 - /home/lstefana/qsystem_2/ip/axis_readout_v1 - /home/lstefana/qsystem_2/ip/axis_readout_v1 - /home/lstefana/qsystem_2/ip/axis_readout_v1 - - - - 2019.1 - - - - - - - - diff --git a/qick/firmware/ip/axis_readout_v1/src/axi_mst_0/axi_mst_0.veo b/qick/firmware/ip/axis_readout_v1/src/axi_mst_0/axi_mst_0.veo deleted file mode 100644 index 5f33135..0000000 --- a/qick/firmware/ip/axis_readout_v1/src/axi_mst_0/axi_mst_0.veo +++ /dev/null @@ -1,85 +0,0 @@ -// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -// IP VLNV: xilinx.com:ip:axi_vip:1.1 -// IP Revision: 5 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -axi_mst_0 your_instance_name ( - .aclk(aclk), // input wire aclk - .aresetn(aresetn), // input wire aresetn - .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr - .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot - .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid - .m_axi_awready(m_axi_awready), // input wire m_axi_awready - .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata - .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb - .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid - .m_axi_wready(m_axi_wready), // input wire m_axi_wready - .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp - .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid - .m_axi_bready(m_axi_bready), // output wire m_axi_bready - .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr - .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot - .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid - .m_axi_arready(m_axi_arready), // input wire m_axi_arready - .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata - .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp - .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid - .m_axi_rready(m_axi_rready) // output wire m_axi_rready -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file axi_mst_0.v when simulating -// the core, axi_mst_0. When compiling the wrapper file, be sure to -// reference the Verilog simulation library. - diff --git a/qick/firmware/ip/axis_readout_v1/src/axi_mst_0/axi_mst_0.vho b/qick/firmware/ip/axis_readout_v1/src/axi_mst_0/axi_mst_0.vho deleted file mode 100644 index 5c4d9a9..0000000 --- a/qick/firmware/ip/axis_readout_v1/src/axi_mst_0/axi_mst_0.vho +++ /dev/null @@ -1,115 +0,0 @@ --- (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:axi_vip:1.1 --- IP Revision: 5 - --- The following code must appear in the VHDL architecture header. - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT axi_mst_0 - PORT ( - aclk : IN STD_LOGIC; - aresetn : IN STD_LOGIC; - m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - m_axi_awvalid : OUT STD_LOGIC; - m_axi_awready : IN STD_LOGIC; - m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - m_axi_wvalid : OUT STD_LOGIC; - m_axi_wready : IN STD_LOGIC; - m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - m_axi_bvalid : IN STD_LOGIC; - m_axi_bready : OUT STD_LOGIC; - m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - m_axi_arvalid : OUT STD_LOGIC; - m_axi_arready : IN STD_LOGIC; - m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - m_axi_rvalid : IN STD_LOGIC; - m_axi_rready : OUT STD_LOGIC - ); -END COMPONENT; --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : axi_mst_0 - PORT MAP ( - aclk => aclk, - aresetn => aresetn, - m_axi_awaddr => m_axi_awaddr, - m_axi_awprot => m_axi_awprot, - m_axi_awvalid => m_axi_awvalid, - m_axi_awready => m_axi_awready, - m_axi_wdata => m_axi_wdata, - m_axi_wstrb => m_axi_wstrb, - m_axi_wvalid => m_axi_wvalid, - m_axi_wready => m_axi_wready, - m_axi_bresp => m_axi_bresp, - m_axi_bvalid => m_axi_bvalid, - m_axi_bready => m_axi_bready, - m_axi_araddr => m_axi_araddr, - m_axi_arprot => m_axi_arprot, - m_axi_arvalid => m_axi_arvalid, - m_axi_arready => m_axi_arready, - m_axi_rdata => m_axi_rdata, - m_axi_rresp => m_axi_rresp, - m_axi_rvalid => m_axi_rvalid, - m_axi_rready => m_axi_rready - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file axi_mst_0.vhd when simulating --- the core, axi_mst_0. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/qick/firmware/ip/axis_readout_v1/src/axi_mst_0/axi_mst_0.xci b/qick/firmware/ip/axis_readout_v1/src/axi_mst_0/axi_mst_0.xci deleted file mode 100644 index 34f0b12..0000000 --- a/qick/firmware/ip/axis_readout_v1/src/axi_mst_0/axi_mst_0.xci +++ /dev/null @@ -1,187 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - axi_mst_0 - - - ACTIVE_LOW - - 100000000 - 0 - 0.000 - 32 - 0 - 0 - 0 - - 32 - 100000000 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 32 - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 0 - 2 - 32 - 0 - 0 - 0 - 32 - 0 - 0 - 32 - 0 - 0 - 0 - axi_mst_0 - 32 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 0 - 0 - 1 - 0 - MASTER - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - virtex7 - - - xc7vx485t - ffg1157 - VERILOG - - MIXED - -1 - - - TRUE - TRUE - IP_Flow - 5 - TRUE - . - - . - 2019.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/qick/firmware/ip/axis_readout_v1/src/axi_mst_0/axi_mst_0.xml b/qick/firmware/ip/axis_readout_v1/src/axi_mst_0/axi_mst_0.xml deleted file mode 100644 index 79a6b4d..0000000 --- a/qick/firmware/ip/axis_readout_v1/src/axi_mst_0/axi_mst_0.xml +++ /dev/null @@ -1,4751 +0,0 @@ - - - xilinx.com - customized_ip - axi_mst_0 - 1.0 - - - M_AXI - - - - - - - - - ARADDR - - - m_axi_araddr - - - - - ARBURST - - - m_axi_arburst - - - - - ARCACHE - - - m_axi_arcache - - - - - ARID - - - m_axi_arid - - - - - ARLEN - - - m_axi_arlen - - - - - ARLOCK - - - m_axi_arlock - - - - - ARPROT - - - m_axi_arprot - - - - - ARQOS - - - m_axi_arqos - - - - - ARREADY - - - m_axi_arready - - - - - ARREGION - - - m_axi_arregion - - - - - ARSIZE - - - m_axi_arsize - - - - - ARUSER - - - m_axi_aruser - - - - - ARVALID - - - m_axi_arvalid - - - - - AWADDR - - - m_axi_awaddr - - - - - AWBURST - - - m_axi_awburst - - - - - AWCACHE - - - m_axi_awcache - - - - - AWID - - - m_axi_awid - - - - - AWLEN - - - m_axi_awlen - - - - - AWLOCK - - - m_axi_awlock - - - - - AWPROT - - - m_axi_awprot - - - - - AWQOS - - - m_axi_awqos - - - - - AWREADY - - - m_axi_awready - - - - - AWREGION - - - m_axi_awregion - - - - - AWSIZE - - - m_axi_awsize - - - - - AWUSER - - - m_axi_awuser - - - - - AWVALID - - - m_axi_awvalid - - - - - BID - - - m_axi_bid - - - - - BREADY - - - m_axi_bready - - - - - BRESP - - - m_axi_bresp - - - - - BUSER - - - m_axi_buser - - - - - BVALID - - - m_axi_bvalid - - - - - RDATA - - - m_axi_rdata - - - - - RID - - - m_axi_rid - - - - - RLAST - - - m_axi_rlast - - - - - RREADY - - - m_axi_rready - - - - - RRESP - - - m_axi_rresp - - - - - RUSER - - - m_axi_ruser - - - - - RVALID - - - m_axi_rvalid - - - - - WDATA - - - m_axi_wdata - - - - - WID - - - m_axi_wid - - - - - WLAST - - - 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- - - - HAS_BRESP - 1 - - - simulation.tlm - - - - - HAS_RRESP - 1 - - - simulation.tlm - - - - - SUPPORTS_NARROW_BURST - 0 - - - simulation.tlm - - - - - NUM_READ_OUTSTANDING - 1 - - - simulation.tlm - - - - - NUM_WRITE_OUTSTANDING - 1 - - - simulation.tlm - - - - - MAX_BURST_LENGTH - 1 - - - simulation.tlm - - - - - PHASE - 0.000 - - - simulation.tlm - - - - - CLK_DOMAIN - - - - simulation.tlm - - - - - NUM_READ_THREADS - 1 - - - simulation.tlm - - - - - NUM_WRITE_THREADS - 1 - - - simulation.tlm - - - - - RUSER_BITS_PER_BYTE - 0 - - - simulation.tlm - - - - - WUSER_BITS_PER_BYTE - 0 - - - simulation.tlm - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - S_AXI - - - - - - - ARADDR - - - s_axi_araddr - - - - - ARBURST - - - s_axi_arburst - - - - - ARCACHE - - - s_axi_arcache - - - - - ARID - - - s_axi_arid - - - - - ARLEN - - - s_axi_arlen - - - - - ARLOCK - - - s_axi_arlock - - - - - ARPROT - - - s_axi_arprot - - - - - ARQOS - - - s_axi_arqos - - - - - ARREADY - - - s_axi_arready - - - - - ARREGION - - - s_axi_arregion - - - - - ARSIZE - - - s_axi_arsize - - - - - ARUSER - - - s_axi_aruser - - - - - ARVALID - - - s_axi_arvalid - - - - - AWADDR - - - s_axi_awaddr - - - - - AWBURST - - - s_axi_awburst - - - - - AWCACHE - - - s_axi_awcache - - - - - AWID - - - s_axi_awid - - - - - AWLEN - - - s_axi_awlen - - - - - AWLOCK - - - s_axi_awlock - - - - - AWPROT - - - s_axi_awprot - - - - - AWQOS - - - s_axi_awqos - - - - - AWREADY - - - s_axi_awready - - - - - AWREGION - - - s_axi_awregion - - - - - AWSIZE - - - s_axi_awsize - - - - - AWUSER - - - s_axi_awuser - - - - - AWVALID - - - s_axi_awvalid - - - - - BID - - - s_axi_bid - - - - - BREADY - - - s_axi_bready - - - - - BRESP - - - s_axi_bresp - - - - - BUSER - - - s_axi_buser - - - - - BVALID - - - s_axi_bvalid - - - - - RDATA - - - s_axi_rdata - - - - - RID - - - s_axi_rid - - - - - RLAST - - - s_axi_rlast - - - - - RREADY - - - s_axi_rready - - - - - RRESP - - - s_axi_rresp - - - - - RUSER - - - s_axi_ruser - - - - - RVALID - - - s_axi_rvalid - - - - - WDATA - - - s_axi_wdata - - - - - WID - - - s_axi_wid - - - - - WLAST - - - s_axi_wlast - - - - - WREADY - - - s_axi_wready - - - - - WSTRB - - - s_axi_wstrb - - - - - WUSER - - - s_axi_wuser - - - - - WVALID - - - s_axi_wvalid - - - - - - DATA_WIDTH - 1 - - - simulation.tlm - - - - - PROTOCOL - AXI4LITE - - - simulation.tlm - - - - - FREQ_HZ - 100000000 - - - simulation.tlm - - - - - ID_WIDTH - 0 - - - simulation.tlm - - - - - ADDR_WIDTH - 1 - - - simulation.tlm - - - - - AWUSER_WIDTH - 0 - - - simulation.tlm - - - - - ARUSER_WIDTH - 0 - - - simulation.tlm - - - - - WUSER_WIDTH - 0 - - - simulation.tlm - - - - - RUSER_WIDTH - 0 - - - simulation.tlm - - - - - BUSER_WIDTH - 0 - - - simulation.tlm - - - - - READ_WRITE_MODE - READ_WRITE - - - simulation.tlm - - - - - HAS_BURST - 0 - - - simulation.tlm - - - - - HAS_LOCK - 0 - - - simulation.tlm - - - - - HAS_PROT - 0 - - - simulation.tlm - - - - - HAS_CACHE - 0 - - - simulation.tlm - - - - - HAS_QOS - 0 - - - simulation.tlm - - - - - HAS_REGION - 0 - - - simulation.tlm - - - - - HAS_WSTRB - 0 - - - simulation.tlm - - - - - HAS_BRESP - 0 - - - simulation.tlm - - - - - HAS_RRESP - 0 - - - simulation.tlm - - - - - SUPPORTS_NARROW_BURST - 0 - - - simulation.tlm - - - - - NUM_READ_OUTSTANDING - 1 - - - simulation.tlm - - - - - NUM_WRITE_OUTSTANDING - 1 - - - simulation.tlm - - - - - MAX_BURST_LENGTH - 1 - - - simulation.tlm - - - - - PHASE - 0.000 - - - simulation.tlm - - - - - CLK_DOMAIN - - - - simulation.tlm - - - - - NUM_READ_THREADS - 1 - - - simulation.tlm - - - - - NUM_WRITE_THREADS - 1 - - - simulation.tlm - - - - - RUSER_BITS_PER_BYTE - 0 - - - simulation.tlm - - - - - WUSER_BITS_PER_BYTE - 0 - - - simulation.tlm - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - RESET - - - - - - - RST - - - aresetn - - - - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - ACLKEN - - - - - - - CE - - - aclken - - - - - - POLARITY - ACTIVE_LOW - - - none - - - - - - - - false - - - - - - CLOCK - - - - - - - CLK - - - aclk - - - - - - ASSOCIATED_BUSIF - M_AXI:S_AXI - - - ASSOCIATED_RESET - aresetn - - - FREQ_HZ - 100000000 - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - M_AXI_TLM - - - - - - - AXIMM_READ_SOCKET - - - M_INITIATOR_rd_socket - - - - - AXIMM_WRITE_SOCKET - - - M_INITIATOR_wr_socket - - - - - - S_AXI_TLM - - - - - - - AXIMM_READ_SOCKET - - - S_TARGET_rd_socket - - - - - AXIMM_WRITE_SOCKET - - - S_TARGET_wr_socket - - - - - - - - Master_AXI - 4294967296 - 32 - - - - true - - - - - - - - S_AXI - - Reg - 0 - 65536 - 32 - read-write - - - - false - - - - - - - - - - xilinx_veriloginstantiationtemplate - Verilog Instantiation Template - verilogSource:vivado.xilinx.com:synthesis.template - verilog - - xilinx_veriloginstantiationtemplate_view_fileset - - - - GENtimestamp - Thu Dec 17 22:05:33 UTC 2020 - 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- - sysc/axi_vip.h - systemCSource - true - axi_vip_v1_1_5 - - - - xilinx_verilogsimulationwrapper_view_fileset - - sim/axi_mst_0.sv - systemVerilogSource - xil_defaultlib - - - - xilinx_systemcsimulationwrapper_view_fileset - - sim/axi_mst_0_sc.h - systemCSource - true - - - sim/axi_mst_0_sc.cpp - systemCSource - - - sim/axi_mst_0.h - systemCSource - true - - - sim/axi_mst_0.cpp - systemCSource - - - sim/axi_mst_0_stub.sv - systemVerilogSource - - - - The AXI Verification IP. - - - Component_Name - Component Name - axi_mst_0 - - - PROTOCOL - PROTOCOL - AXI4LITE - - - READ_WRITE_MODE - READ_WRITE MODE - READ_WRITE - - - INTERFACE_MODE - INTERFACE MODE - MASTER - - - ADDR_WIDTH - ADDRESS WIDTH - 32 - - - DATA_WIDTH - DATA WIDTH - 32 - - - ID_WIDTH - ID WIDTH - 0 - - - - false - - - - - - AWUSER_WIDTH - AWUSER WIDTH - 0 - - - - false - - - - - - ARUSER_WIDTH - ARUSER WIDTH - 0 - - - - false - - - - - - RUSER_WIDTH - RUSER WIDTH - 0 - - - - false - - - - - - WUSER_WIDTH - WUSER WIDTH - 0 - - - - false - - - - - - BUSER_WIDTH - BUSER WIDTH - 0 - - - - false - - - - - - WUSER_BITS_PER_BYTE - WUSER BITS PER BYTE - 0 - - - - false - - - - - - RUSER_BITS_PER_BYTE - RUSER BITS PER BYTE - 0 - - - - false - - - - - - HAS_USER_BITS_PER_BYTE - HAS USER_BITS_PER_BYTE - 0 - - - - false - - - - - - SUPPORTS_NARROW - SUPPORTS NARROW - 0 - - - - false - - - - - - HAS_SIZE - HAS SIZE - 0 - - - - false - - - - - - HAS_BURST - HAS BURST - 0 - - - - false - - - - - - HAS_LOCK - HAS LOCK - 0 - - - - false - - - - - - HAS_CACHE - HAS CACHE - 0 - - - - false - - - - - - HAS_REGION - HAS REGION - 0 - - - - false - - - - - - HAS_QOS - HAS QOS - 0 - - - - false - - - - - - HAS_PROT - HAS PROT - 1 - - - HAS_WSTRB - HAS WSTRB - 1 - - - HAS_BRESP - HAS BRESP - 1 - - - HAS_RRESP - HAS RRESP - 1 - - - HAS_ACLKEN - HAS ACLKEN - 0 - - - HAS_ARESETN - HAS ARESETN - 1 - - - - - AXI Verification IP - - xtlm - - 5 - true - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2019.1 - - - - - - - - - - diff --git a/qick/firmware/ip/axis_readout_v1/src/axi_slv.vhd b/qick/firmware/ip/axis_readout_v1/src/axi_slv.vhd deleted file mode 100644 index e23890d..0000000 --- a/qick/firmware/ip/axis_readout_v1/src/axi_slv.vhd +++ /dev/null @@ -1,516 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity axi_slv is - Generic - ( - DATA_WIDTH : integer := 32; - ADDR_WIDTH : integer := 6 - ); - Port - ( - aclk : in std_logic; - aresetn : in std_logic; - - -- Write Address Channel. - awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); - awprot : in std_logic_vector(2 downto 0); - awvalid : in std_logic; - awready : out std_logic; - - -- Write Data Channel. - wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); - wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); - wvalid : in std_logic; - wready : out std_logic; - - -- Write Response Channel. - bresp : out std_logic_vector(1 downto 0); - bvalid : out std_logic; - bready : in std_logic; - - -- Read Address Channel. - araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); - arprot : in std_logic_vector(2 downto 0); - arvalid : in std_logic; - arready : out std_logic; - - -- Read Data Channel. - rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); - rresp : out std_logic_vector(1 downto 0); - rvalid : out std_logic; - rready : in std_logic; - - -- Registers. - OUTSEL_REG : out std_logic_vector (1 downto 0); - DDS_FREQ_REG : out std_logic_vector (15 downto 0) - ); -end axi_slv; - -architecture rtl of axi_slv is - - -- AXI4LITE signals - signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); - signal axi_awready : std_logic; - signal axi_wready : std_logic; - signal axi_bresp : std_logic_vector(1 downto 0); - signal axi_bvalid : std_logic; - signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); - signal axi_arready : std_logic; - signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); - signal axi_rresp : std_logic_vector(1 downto 0); - signal axi_rvalid : std_logic; - - -- Example-specific design signals - -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH - -- ADDR_LSB is used for addressing 32/64 bit registers/memories - -- ADDR_LSB = 2 for 32 bits (n downto 2) - -- ADDR_LSB = 3 for 64 bits (n downto 3) - constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; - constant OPT_MEM_ADDR_BITS : integer := 3; - ------------------------------------------------ - ---- Signals for user logic register space example - -------------------------------------------------- - ---- Number of Slave Registers 16 - signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg_rden : std_logic; - signal slv_reg_wren : std_logic; - signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); - signal byte_index : integer; - signal aw_en : std_logic; - -begin - -- I/O Connections assignments - - awreadY <= axi_awready; - wready <= axi_wready; - bresp <= axi_bresp; - bvalid <= axi_bvalid; - arreadY <= axi_arready; - rdata <= axi_rdata; - rresp <= axi_rresp; - rvalid <= axi_rvalid; - -- Implement axi_awready generation - -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is - -- de-asserted when reset is low. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_awready <= '0'; - aw_en <= '1'; - else - if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then - -- slave is ready to accept write address when - -- there is a valid write address and write data - -- on the write address and data bus. This design - -- expects no outstanding transactions. - axi_awready <= '1'; - aw_en <= '0'; - elsif (bready = '1' and axi_bvalid = '1') then - aw_en <= '1'; - axi_awready <= '0'; - else - axi_awready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement axi_awaddr latching - -- This process is used to latch the address when both - -- S_AXI_AWVALID and S_AXI_WVALID are valid. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_awaddr <= (others => '0'); - else - if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then - -- Write Address latching - axi_awaddr <= awaddr; - end if; - end if; - end if; - end process; - - -- Implement axi_wready generation - -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is - -- de-asserted when reset is low. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_wready <= '0'; - else - if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then - -- slave is ready to accept write data when - -- there is a valid write address and write data - -- on the write address and data bus. This design - -- expects no outstanding transactions. - axi_wready <= '1'; - else - axi_wready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement memory mapped register select and write logic generation - -- The write data is accepted and written to memory mapped registers when - -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to - -- select byte enables of slave registers while writing. - -- These registers are cleared when reset (active low) is applied. - -- Slave register write enable is asserted when valid address and data are available - -- and the slave is ready to accept the write address and write data. - slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; - - process (aclk) - variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); - begin - if rising_edge(aclk) then - if aresetn = '0' then - slv_reg0 <= (others => '0'); - slv_reg1 <= (others => '0'); - slv_reg2 <= (others => '0'); - slv_reg3 <= (others => '0'); - slv_reg4 <= (others => '0'); - slv_reg5 <= (others => '0'); - slv_reg6 <= (others => '0'); - slv_reg7 <= (others => '0'); - slv_reg8 <= (others => '0'); - slv_reg9 <= (others => '0'); - slv_reg10 <= (others => '0'); - slv_reg11 <= (others => '0'); - slv_reg12 <= (others => '0'); - slv_reg13 <= (others => '0'); - slv_reg14 <= (others => '0'); - slv_reg15 <= (others => '0'); - else - loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); - if (slv_reg_wren = '1') then - case loc_addr is - when b"0000" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 0 - slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0001" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 1 - slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0010" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 2 - slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0011" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 3 - slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0100" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 4 - slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0101" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 5 - slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0110" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 6 - slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0111" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 7 - slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1000" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 8 - slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1001" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 9 - slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1010" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 10 - slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1011" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 11 - slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1100" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 12 - slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1101" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 13 - slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1110" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 14 - slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1111" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 15 - slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when others => - slv_reg0 <= slv_reg0; - slv_reg1 <= slv_reg1; - slv_reg2 <= slv_reg2; - slv_reg3 <= slv_reg3; - slv_reg4 <= slv_reg4; - slv_reg5 <= slv_reg5; - slv_reg6 <= slv_reg6; - slv_reg7 <= slv_reg7; - slv_reg8 <= slv_reg8; - slv_reg9 <= slv_reg9; - slv_reg10 <= slv_reg10; - slv_reg11 <= slv_reg11; - slv_reg12 <= slv_reg12; - slv_reg13 <= slv_reg13; - slv_reg14 <= slv_reg14; - slv_reg15 <= slv_reg15; - end case; - end if; - end if; - end if; - end process; - - -- Implement write response logic generation - -- The write response and response valid signals are asserted by the slave - -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. - -- This marks the acceptance of address and indicates the status of - -- write transaction. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_bvalid <= '0'; - axi_bresp <= "00"; --need to work more on the responses - else - if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then - axi_bvalid <= '1'; - axi_bresp <= "00"; - elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) - axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) - end if; - end if; - end if; - end process; - - -- Implement axi_arready generation - -- axi_arready is asserted for one S_AXI_ACLK clock cycle when - -- S_AXI_ARVALID is asserted. axi_awready is - -- de-asserted when reset (active low) is asserted. - -- The read address is also latched when S_AXI_ARVALID is - -- asserted. axi_araddr is reset to zero on reset assertion. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_arready <= '0'; - axi_araddr <= (others => '1'); - else - if (axi_arready = '0' and arvalid = '1') then - -- indicates that the slave has acceped the valid read address - axi_arready <= '1'; - -- Read Address latching - axi_araddr <= araddr; - else - axi_arready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement axi_arvalid generation - -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_ARVALID and axi_arready are asserted. The slave registers - -- data are available on the axi_rdata bus at this instance. The - -- assertion of axi_rvalid marks the validity of read data on the - -- bus and axi_rresp indicates the status of read transaction.axi_rvalid - -- is deasserted on reset (active low). axi_rresp and axi_rdata are - -- cleared to zero on reset (active low). - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_rvalid <= '0'; - axi_rresp <= "00"; - else - if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then - -- Valid read data is available at the read data bus - axi_rvalid <= '1'; - axi_rresp <= "00"; -- 'OKAY' response - elsif (axi_rvalid = '1' and rready = '1') then - -- Read data is accepted by the master - axi_rvalid <= '0'; - end if; - end if; - end if; - end process; - - -- Implement memory mapped register select and read logic generation - -- Slave register read enable is asserted when valid address is available - -- and the slave is ready to accept the read address. - slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; - - process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) - variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); - begin - -- Address decoding for reading registers - loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); - case loc_addr is - when b"0000" => - reg_data_out <= slv_reg0; - when b"0001" => - reg_data_out <= slv_reg1; - when b"0010" => - reg_data_out <= slv_reg2; - when b"0011" => - reg_data_out <= slv_reg3; - when b"0100" => - reg_data_out <= slv_reg4; - when b"0101" => - reg_data_out <= slv_reg5; - when b"0110" => - reg_data_out <= slv_reg6; - when b"0111" => - reg_data_out <= slv_reg7; - when b"1000" => - reg_data_out <= slv_reg8; - when b"1001" => - reg_data_out <= slv_reg9; - when b"1010" => - reg_data_out <= slv_reg10; - when b"1011" => - reg_data_out <= slv_reg11; - when b"1100" => - reg_data_out <= slv_reg12; - when b"1101" => - reg_data_out <= slv_reg13; - when b"1110" => - reg_data_out <= slv_reg14; - when b"1111" => - reg_data_out <= slv_reg15; - when others => - reg_data_out <= (others => '0'); - end case; - end process; - - -- Output register or memory read data - process( aclk ) is - begin - if (rising_edge (aclk)) then - if ( aresetn = '0' ) then - axi_rdata <= (others => '0'); - else - if (slv_reg_rden = '1') then - -- When there is a valid read address (S_AXI_ARVALID) with - -- acceptance of read address by the slave (axi_arready), - -- output the read dada - -- Read address mux - axi_rdata <= reg_data_out; -- register read data - end if; - end if; - end if; - end process; - - -- Register Map. - -- 0 : OUTSEL_REG : 2-bit. Output selection of down-conversion Full Speed. - -- 1 : DDS_FREQ_REG : 16-bit. DDS frequency for down-conversion. - - -- Output Registers. - OUTSEL_REG <= slv_reg0(1 downto 0); - DDS_FREQ_REG <= slv_reg1(15 downto 0); - -end rtl; - diff --git a/qick/firmware/ip/axis_readout_v1/src/axis_readout_v1.v b/qick/firmware/ip/axis_readout_v1/src/axis_readout_v1.v deleted file mode 100644 index 93d7673..0000000 --- a/qick/firmware/ip/axis_readout_v1/src/axis_readout_v1.v +++ /dev/null @@ -1,187 +0,0 @@ -// Readout V1. -// s_axi_aclk : clock for s_axi_* -// aclk : clock for s0_axis_*, s1_axis_*, and m0_axis_* and m1_axis_* -// -module axis_readout_v1 - ( - // AXI Slave I/F for configuration. - s_axi_aclk , - s_axi_aresetn , - - s_axi_awaddr , - s_axi_awprot , - s_axi_awvalid , - s_axi_awready , - - s_axi_wdata , - s_axi_wstrb , - s_axi_wvalid , - s_axi_wready , - - s_axi_bresp , - s_axi_bvalid , - s_axi_bready , - - s_axi_araddr , - s_axi_arprot , - s_axi_arvalid , - s_axi_arready , - - s_axi_rdata , - s_axi_rresp , - s_axi_rvalid , - s_axi_rready , - - // Reset and clock (s_axis, m0_axis, m1_axis). - aresetn , - aclk , - - // S_AXIS: for input data (8x samples per clock). - s_axis_tdata , - s_axis_tvalid , - s_axis_tready , - - // M0_AXIS: for output data (before filter and decimation, 8x samples - // per clock). - m0_axis_tready , - m0_axis_tvalid , - m0_axis_tdata , - - // M1_AXIS: for output data. - m1_axis_tready , - m1_axis_tvalid , - m1_axis_tdata - ); - -/**************/ -/* Parameters */ -/**************/ -// Number of parallel dds blocks. -localparam [15:0] N_DDS = 8; - -/*********/ -/* Ports */ -/*********/ -input s_axi_aclk; -input s_axi_aresetn; - -input [5:0] s_axi_awaddr; -input [2:0] s_axi_awprot; -input s_axi_awvalid; -output s_axi_awready; - -input [31:0] s_axi_wdata; -input [3:0] s_axi_wstrb; -input s_axi_wvalid; -output s_axi_wready; - -output [1:0] s_axi_bresp; -output s_axi_bvalid; -input s_axi_bready; - -input [5:0] s_axi_araddr; -input [2:0] s_axi_arprot; -input s_axi_arvalid; -output s_axi_arready; - -output [31:0] s_axi_rdata; -output [1:0] s_axi_rresp; -output s_axi_rvalid; -input s_axi_rready; - -input aresetn; -input aclk; - -output s_axis_tready; -input s_axis_tvalid; -input [N_DDS*16-1:0] s_axis_tdata; - -input m0_axis_tready; -output m0_axis_tvalid; -output [N_DDS*32-1:0] m0_axis_tdata; - -input m1_axis_tready; -output m1_axis_tvalid; -output [32-1:0] m1_axis_tdata; - -/********************/ -/* Internal signals */ -/********************/ -// Registers. -wire [1:0] OUTSEL_REG; -wire [15:0] DDS_FREQ_REG; - - -/**********************/ -/* Begin Architecture */ -/**********************/ -// AXI Slave. -axi_slv axi_slv_i - ( - .aclk (s_axi_aclk ), - .aresetn (s_axi_aresetn ), - - // Write Address Channel. - .awaddr (s_axi_awaddr ), - .awprot (s_axi_awprot ), - .awvalid (s_axi_awvalid ), - .awready (s_axi_awready ), - - // Write Data Channel. - .wdata (s_axi_wdata ), - .wstrb (s_axi_wstrb ), - .wvalid (s_axi_wvalid ), - .wready (s_axi_wready ), - - // Write Response Channel. - .bresp (s_axi_bresp ), - .bvalid (s_axi_bvalid ), - .bready (s_axi_bready ), - - // Read Address Channel. - .araddr (s_axi_araddr ), - .arprot (s_axi_arprot ), - .arvalid (s_axi_arvalid ), - .arready (s_axi_arready ), - - // Read Data Channel. - .rdata (s_axi_rdata ), - .rresp (s_axi_rresp ), - .rvalid (s_axi_rvalid ), - .rready (s_axi_rready ), - - // Registers. - .OUTSEL_REG (OUTSEL_REG ), - .DDS_FREQ_REG (DDS_FREQ_REG ) - ); - -// Readout Top. -readout_top readout_top_i - ( - // Reset and clock (s0_axis, s1_axis, m0_axis, m1_axis). - .aresetn (aresetn ), - .aclk (aclk ), - - // S_AXIS: for input data (8x samples per clock). - .s_axis_tdata (s_axis_tdata ), - .s_axis_tvalid (s_axis_tvalid ), - .s_axis_tready (s_axis_tready ), - - // M0_AXIS: for output data (before filter and decimation, 8x samples - // per clock). - .m0_axis_tready (m0_axis_tready ), - .m0_axis_tvalid (m0_axis_tvalid ), - .m0_axis_tdata (m0_axis_tdata ), - - // M1_AXIS: for output data. - .m1_axis_tready (m1_axis_tready ), - .m1_axis_tvalid (m1_axis_tvalid ), - .m1_axis_tdata (m1_axis_tdata ), - - // Registers. - .OUTSEL_REG (OUTSEL_REG ), - .DDS_FREQ_REG (DDS_FREQ_REG ) - ); - -endmodule - diff --git a/qick/firmware/ip/axis_readout_v1/src/ctrl.sv b/qick/firmware/ip/axis_readout_v1/src/ctrl.sv deleted file mode 100644 index f46382b..0000000 --- a/qick/firmware/ip/axis_readout_v1/src/ctrl.sv +++ /dev/null @@ -1,85 +0,0 @@ -//Format of waveform interface: -module ctrl ( - // Reset and clock. - rstn , - clk , - - // dds control. - dds_ctrl_o , - - // Registers. - DDS_FREQ_REG - ); - -// Number of parallel dds blocks. -parameter [15:0] N_DDS = 16; - -// Ports. -input rstn; -input clk; -output [N_DDS*40-1:0] dds_ctrl_o; -input [15:0] DDS_FREQ_REG; - -// DDS_FREQ_REG register. -reg [15:0] DDS_FREQ_REG_r; - -// Pinc/phase. -wire [15:0] pinc_int; -reg [15:0] pinc_r1; -wire [15:0] pinc_N; -reg [15:0] pinc_N_r1; - -// Phase vectors. -wire [15:0] phase_v0 [0:N_DDS-1]; -reg [15:0] phase_v0_r1 [0:N_DDS-1]; - -// Registers. -always @(posedge clk) begin - if (~rstn) begin - // DDS_FREQ_REG register. - DDS_FREQ_REG_r <= 0; - - // Pinc. - pinc_r1 <= 0; - pinc_N_r1 <= 0; - end - else begin - // DDS_FREQ_REG regisrer. - DDS_FREQ_REG_r <= DDS_FREQ_REG; - - // Pinc. - pinc_r1 <= pinc_int; - pinc_N_r1 <= pinc_N; - end -end - -// Frequency. -assign pinc_int = DDS_FREQ_REG_r; - -// Frequency calculation. -assign pinc_N = pinc_r1*N_DDS; - -// Phase vectors. -generate -genvar i; - for (i=0; i < N_DDS; i = i + 1) begin : GEN_phase - // Registers. - always @(posedge clk) begin - if (~rstn) begin - phase_v0_r1[i] <= 0; - end - else begin - phase_v0_r1[i] <= phase_v0[i]; - end - end - - // v0. - assign phase_v0[i] = pinc_r1*i; - - // dds_ctrl_o output. - assign dds_ctrl_o[i*40 +: 40] = {8'h00,phase_v0_r1[i],pinc_N_r1}; - end -endgenerate - -endmodule - diff --git a/qick/firmware/ip/axis_readout_v1/src/dds_compiler_0/dds_compiler_0.veo b/qick/firmware/ip/axis_readout_v1/src/dds_compiler_0/dds_compiler_0.veo deleted file mode 100644 index 11a9d73..0000000 --- a/qick/firmware/ip/axis_readout_v1/src/dds_compiler_0/dds_compiler_0.veo +++ /dev/null @@ -1,69 +0,0 @@ -// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -// IP VLNV: xilinx.com:ip:dds_compiler:6.0 -// IP Revision: 18 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -dds_compiler_0 your_instance_name ( - .aclk(aclk), // input wire aclk - .s_axis_phase_tvalid(s_axis_phase_tvalid), // input wire s_axis_phase_tvalid - .s_axis_phase_tdata(s_axis_phase_tdata), // input wire [39 : 0] s_axis_phase_tdata - .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid - .m_axis_data_tdata(m_axis_data_tdata) // output wire [31 : 0] m_axis_data_tdata -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file dds_compiler_0.v when simulating -// the core, dds_compiler_0. When compiling the wrapper file, be sure to -// reference the Verilog simulation library. - diff --git a/qick/firmware/ip/axis_readout_v1/src/dds_compiler_0/dds_compiler_0.vho b/qick/firmware/ip/axis_readout_v1/src/dds_compiler_0/dds_compiler_0.vho deleted file mode 100644 index fca08e6..0000000 --- a/qick/firmware/ip/axis_readout_v1/src/dds_compiler_0/dds_compiler_0.vho +++ /dev/null @@ -1,83 +0,0 @@ --- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:dds_compiler:6.0 --- IP Revision: 18 - --- The following code must appear in the VHDL architecture header. - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT dds_compiler_0 - PORT ( - aclk : IN STD_LOGIC; - s_axis_phase_tvalid : IN STD_LOGIC; - s_axis_phase_tdata : IN STD_LOGIC_VECTOR(39 DOWNTO 0); - m_axis_data_tvalid : OUT STD_LOGIC; - m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) - ); -END COMPONENT; --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : dds_compiler_0 - PORT MAP ( - aclk => aclk, - s_axis_phase_tvalid => s_axis_phase_tvalid, - s_axis_phase_tdata => s_axis_phase_tdata, - m_axis_data_tvalid => m_axis_data_tvalid, - m_axis_data_tdata => m_axis_data_tdata - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file dds_compiler_0.vhd when simulating --- the core, dds_compiler_0. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/qick/firmware/ip/axis_readout_v1/src/dds_compiler_0/dds_compiler_0.xci b/qick/firmware/ip/axis_readout_v1/src/dds_compiler_0/dds_compiler_0.xci deleted file mode 100644 index 4ecd4c9..0000000 --- a/qick/firmware/ip/axis_readout_v1/src/dds_compiler_0/dds_compiler_0.xci +++ /dev/null @@ -1,307 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - dds_compiler_0 - - - ACTIVE_LOW - - 100000000 - 0 - 0.000 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 5 - 0 - 0 - 0 - 16 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 1 - 0 - 1 - 0 - 1 - 0 - 0 - 10 - 1 - 0 - 9 - 0 - 32 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 1 - 2 - 0 - 16 - 14 - 3 - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - 3 - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - 0 - 1 - 0 - 1 - 0 - 40 - 1 - 1 - zynquplus - Full_Range - 1 - dds_compiler_0 - Not_Required - 256 - Maximal - 3906.25 - Coregen - false - false - false - false - 10 - Auto - Not_Required - Not_Required - Auto - Standard - 9 - false - true - Phase_Dithering - Twos_Complement - Speed - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Sine_and_Cosine - 16 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - false - System_Parameters - Phase_Generator_and_SIN_COS_LUT - Streaming - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 16 - Streaming - true - On_Vector - Not_Required - 1 - 96 - false - 1 - zynquplusRFSOC - xilinx.com:zcu111:part0:1.1 - - xczu28dr - ffvg1517 - VERILOG - - MIXED - -2 - - E - TRUE - TRUE - IP_Flow - 18 - TRUE - . - - . - 2019.1 - GLOBAL - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/qick/firmware/ip/axis_readout_v1/src/dds_compiler_0/dds_compiler_0.xml b/qick/firmware/ip/axis_readout_v1/src/dds_compiler_0/dds_compiler_0.xml deleted file mode 100644 index 8d0fe6f..0000000 --- a/qick/firmware/ip/axis_readout_v1/src/dds_compiler_0/dds_compiler_0.xml +++ /dev/null @@ -1,3168 +0,0 @@ - - - xilinx.com - customized_ip - dds_compiler_0 - 1.0 - - - event_pinc_invalid_intf - - - - - - - INTERRUPT - - - event_pinc_invalid - - - - - - SENSITIVITY - EDGE_RISING - - - PortWidth - 1 - - - none - - - - - - - event_poff_invalid_intf - - - - - - - INTERRUPT - - - event_poff_invalid - - - - - - SENSITIVITY - EDGE_RISING - - - PortWidth - 1 - - - none - - - - - - - event_phase_in_invalid_intf - - - - - - - INTERRUPT - - - event_phase_in_invalid - - - - - - SENSITIVITY - EDGE_RISING - - - PortWidth - 1 - - - none - - - - - - - event_s_phase_tlast_missing_intf - - - - - - - INTERRUPT - - - event_s_phase_tlast_missing - - - - - - SENSITIVITY - EDGE_RISING - - - PortWidth - 1 - - - none - - - - - - - event_s_phase_tlast_unexpected_intf - - - - - - - INTERRUPT - - - event_s_phase_tlast_unexpected - - - - - - SENSITIVITY - EDGE_RISING - - - PortWidth - 1 - - - none - - - - - - - event_s_phase_chanid_incorrect_intf - - - - - - - INTERRUPT - - - event_s_phase_chanid_incorrect - - - - - - SENSITIVITY - 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zip - - - - xilinx_vhdltestbench_view_fileset - - demo_tb/tb_dds_compiler_0.vhd - vhdlSource - - - - xilinx_versioninformation_view_fileset - - doc/dds_compiler_v6_0_changelog.txt - text - - - - The Xilinx DDS Compiler LogiCORE provides Direct Digital Synthesizers (DDS) and optionally either Phase Generator or Sine/Cosine Lookup Table constituent parts as independent cores. The core features sine, cosine or quadrature outputs with 3 to 26-bit output sample precision. The core supports up to 16 channels by time-sharing the sine/cosine table which dramatically reduces the area requirement when multiple channels are needed. Phase Dithering and Taylor Series Correction options provide high dynamic range signals using minimal FPGA resources. In addition, the core has an optional phase offset capability, providing support for multiple synthesizers with precisely controlled phase differences. - - - Component_Name - Component Name - dds_compiler_0 - - - PartsPresent - Configuration Options - Phase_Generator_and_SIN_COS_LUT - - - DDS_Clock_Rate - System Clock - 256 - - - Channels - Number of Channels - 1 - - - Mode_of_Operation - Mode Of Operation - Standard - - - Modulus - Modulus - 9 - - - Parameter_Entry - Parameter Selection - System_Parameters - - - Spurious_Free_Dynamic_Range - Spurious Free Dynamic Range - 96 - - - Frequency_Resolution - Frequency Resolution - 3906.25 - - - Noise_Shaping - Noise Shaping - Phase_Dithering - - - Phase_Width - Phase Width - 16 - - - Output_Width - Output Width - 16 - - - Phase_Increment - Phase Increment - Streaming - - - Resync - Resync - true - - - Phase_offset - Phase Offset - Streaming - - - Output_Selection - Output Selection - Sine_and_Cosine - - - Negative_Sine - Negative Sine - true - - - Negative_Cosine - Negative Cosine - false - - - Amplitude_Mode - Amplitude Mode - Full_Range - - - Memory_Type - Memory Type - Auto - - - Optimization_Goal - Optimization Goal - Speed - - - DSP48_Use - DSP48 Use - Maximal - - - Has_Phase_Out - Has Phase Out - false - - - DATA_Has_TLAST - DATA Has TLAST - Not_Required - - - Has_TREADY - Output TREADY - false - - - S_PHASE_Has_TUSER - Input - Not_Required - - - S_PHASE_TUSER_Width - User Field Width - 1 - - - M_DATA_Has_TUSER - DATA Output - Not_Required - - - M_PHASE_Has_TUSER - PHASE Output - Not_Required - - - S_CONFIG_Sync_Mode - Synchronization Mode - On_Vector - - - OUTPUT_FORM - Output Form - Twos_Complement - - - Latency_Configuration - Auto - - - Latency - 10 - - - Has_ARESETn - ARESETn (active low) - false - - - Has_ACLKEN - ACLKEN - false - - - Output_Frequency1 - 0 - - - PINC1 - 0 - - - Phase_Offset_Angles1 - 0 - - - POFF1 - 0 - - - Output_Frequency2 - 0 - - - PINC2 - 0 - - - Phase_Offset_Angles2 - 0 - - - POFF2 - 0 - - - Output_Frequency3 - 0 - - - PINC3 - 0 - - - Phase_Offset_Angles3 - 0 - - - POFF3 - 0 - - - Output_Frequency4 - 0 - - - PINC4 - 0 - - - Phase_Offset_Angles4 - 0 - - - POFF4 - 0 - - - Output_Frequency5 - 0 - - - PINC5 - 0 - - - Phase_Offset_Angles5 - 0 - - - POFF5 - 0 - - - Output_Frequency6 - 0 - - - PINC6 - 0 - - - Phase_Offset_Angles6 - 0 - - - POFF6 - 0 - - - Output_Frequency7 - 0 - - - PINC7 - 0 - - - Phase_Offset_Angles7 - 0 - - - POFF7 - 0 - - - Output_Frequency8 - 0 - - - PINC8 - 0 - - - Phase_Offset_Angles8 - 0 - - - POFF8 - 0 - - - Output_Frequency9 - 0 - - - PINC9 - 0 - - - Phase_Offset_Angles9 - 0 - - - POFF9 - 0 - - - Output_Frequency10 - 0 - - - PINC10 - 0 - - - Phase_Offset_Angles10 - 0 - - - POFF10 - 0 - - - Output_Frequency11 - 0 - - - PINC11 - 0 - - - Phase_Offset_Angles11 - 0 - - - POFF11 - 0 - - - Output_Frequency12 - 0 - - - PINC12 - 0 - - - Phase_Offset_Angles12 - 0 - - - POFF12 - 0 - - - Output_Frequency13 - 0 - - - PINC13 - 0 - - - Phase_Offset_Angles13 - 0 - - - POFF13 - 0 - - - Output_Frequency14 - 0 - - - PINC14 - 0 - - - Phase_Offset_Angles14 - 0 - - - POFF14 - 0 - - - Output_Frequency15 - 0 - - - PINC15 - 0 - - - Phase_Offset_Angles15 - 0 - - - POFF15 - 0 - - - Output_Frequency16 - 0 - - - PINC16 - 0 - - - Phase_Offset_Angles16 - 0 - - - POFF16 - 0 - - - POR_mode - POR Mode - false - - - GUI_Behaviour - Coregen - - - explicit_period - false - - - period - 1 - - - - - DDS Compiler - 18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2019.1 - - - - - - - - diff --git a/qick/firmware/ip/axis_readout_v1/src/down_conversion.v b/qick/firmware/ip/axis_readout_v1/src/down_conversion.v deleted file mode 100644 index 592e92e..0000000 --- a/qick/firmware/ip/axis_readout_v1/src/down_conversion.v +++ /dev/null @@ -1,219 +0,0 @@ -module down_conversion ( - // Reset and clock. - rstn , - clk , - - // S_AXIS for input. - s_axis_tready_o , - s_axis_tvalid_i , - s_axis_tdata_i , - - // M_AXIS for output. - m_axis_tready_i , - m_axis_tvalid_o , - m_axis_tdata_o , - - // Registers. - OUTSEL_REG , - DDS_FREQ_REG - ); - -/**************/ -/* Parameters */ -/**************/ -// Number of parallel dds blocks. -parameter [15:0] N_DDS = 16; - -// 0.5 for rounding. -localparam [31:0] RND_0P5 = 2**15; - -/*********/ -/* Ports */ -/*********/ -input rstn; -input clk; - -output s_axis_tready_o; -input s_axis_tvalid_i; -input [N_DDS*16-1:0] s_axis_tdata_i; - -input m_axis_tready_i; -output m_axis_tvalid_o; -output [N_DDS*32-1:0] m_axis_tdata_o; - -input [1:0] OUTSEL_REG; -input [15:0] DDS_FREQ_REG; - -/********************/ -/* Internal signals */ -/********************/ -// DDS input control. -reg dds_tvalid_r; -wire [N_DDS*40-1:0] dds_ctrl_int; -reg [N_DDS*40-1:0] dds_ctrl_int_r; - -// DDS output. -wire [31:0] dds_dout [0:N_DDS-1]; -reg [31:0] dds_dout_r1 [0:N_DDS-1]; -reg [31:0] dds_dout_r2 [0:N_DDS-1]; -reg [31:0] dds_dout_r3 [0:N_DDS-1]; -reg [31:0] dds_dout_r4 [0:N_DDS-1]; - -// Input data. -reg [15:0] din_r1 [0:N_DDS-1]; -reg signed [15:0] din_r2 [0:N_DDS-1]; -reg [15:0] din_r3 [0:N_DDS-1]; -reg [15:0] din_r4 [0:N_DDS-1]; - -// Product. -wire signed [15:0] pa_real [0:N_DDS-1]; -wire signed [15:0] pa_imag [0:N_DDS-1]; -wire signed [31:0] py_full_real [0:N_DDS-1]; -wire signed [31:0] py_full_imag [0:N_DDS-1]; -reg signed [31:0] py_full_real_r [0:N_DDS-1]; -reg signed [31:0] py_full_imag_r [0:N_DDS-1]; -wire signed [31:0] py_round_real [0:N_DDS-1]; -wire signed [31:0] py_round_imag [0:N_DDS-1]; -wire [15:0] py_real [0:N_DDS-1]; -wire [15:0] py_imag [0:N_DDS-1]; -wire [31:0] py [0:N_DDS-1]; -reg [31:0] py_r [0:N_DDS-1]; - -// Muxed output. -wire [31:0] dout_mux [0:N_DDS-1]; -reg [31:0] dout_mux_r [0:N_DDS-1]; - -/**********************/ -/* Begin Architecture */ -/**********************/ -// Control block. -ctrl - #( - .N_DDS (N_DDS ) - ) - ctrl_i - ( - // Reset and clock. - .rstn (rstn ), - .clk (clk ), - - // dds control. - .dds_ctrl_o (dds_ctrl_int ), - - // Registers. - .DDS_FREQ_REG (DDS_FREQ_REG ) - ); - -generate -genvar i; - for (i=0; i aclk, - s_axis_data_tvalid => s_axis_data_tvalid, - s_axis_data_tready => s_axis_data_tready, - s_axis_data_tdata => s_axis_data_tdata, - m_axis_data_tvalid => m_axis_data_tvalid, - m_axis_data_tdata => m_axis_data_tdata - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file fir_compiler_0.vhd when simulating --- the core, fir_compiler_0. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/qick/firmware/ip/axis_readout_v1/src/fir_compiler_0/fir_compiler_0.xci b/qick/firmware/ip/axis_readout_v1/src/fir_compiler_0/fir_compiler_0.xci deleted file mode 100644 index af88717..0000000 --- a/qick/firmware/ip/axis_readout_v1/src/fir_compiler_0/fir_compiler_0.xci +++ /dev/null @@ -1,296 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - fir_compiler_0 - - - ACTIVE_LOW - - 100000000 - 0 - 0.000 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 1 - 0 - 0 - undef - 0.000 - 32 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - 35,35 - 35,35,35,35,35,35,35,35,35,35,35,35,35,35,35,35 - fixed - fir_compiler_0.mif - 120 - 2 - 0 - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16 - 0 - 16 - 120 - 1 - 4 - fir_compiler_0 - 0 - 0 - 1 - 2 - 0 - 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16 - 0 - 0 - -0,2,4,6,8,10,12,14;-1,3,5,7,9,11,13,15;0,-2,4,6,8,10,12,14;1,-3,5,7,9,11,13,15;0,2,-4,6,8,10,12,14;1,3,-5,7,9,11,13,15;0,2,4,-6,8,10,12,14;1,3,5,-7,9,11,13,15;0,2,4,6,-8,10,12,14;1,3,5,7,-9,11,13,15;0,2,4,6,8,-10,12,14;1,3,5,7,9,-11,13,15;0,2,4,6,8,10,-12,14;1,3,5,7,9,11,-13,15;0,2,4,6,8,10,12,-14;1,3,5,7,9,11,13,-15 - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 - 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16 - 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16 - 16 - 1 - ./ - none - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 2 - 126 - 2 - 0 - 0 - 32 - 1 - 1 - 1 - 120 - 1 - 120 - 0 - 0 - none - 0,2,4,6,8,10,12,-14;1,3,5,7,9,11,13,-15 - 16,16 - 1 - 16 - 1 - 14,15,14,15,14,15,14,15,14,15,14,15,14,15,14,15 - 1 - 2 - 0 - 0 - 0 - 256 - 1 - zynquplus - 1 - false - false - Basic - 300.0 - COE_File - 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 - Automatic - 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- - - GENtimestamp - Fri Mar 19 18:55:48 UTC 2021 - - - outputProductCRC - 9:9b138268 - - - - - - - aresetn - - in - - - std_logic - xilinx_veriloginstantiationtemplate - - - - 0x1 - - - - - - false - - - - - - aclk - - in - - - std_logic - xilinx_veriloginstantiationtemplate - - - - - - aclken - - in - - - std_logic - xilinx_veriloginstantiationtemplate - - - - 0x1 - - - - - - false - - - - - - s_axis_data_tvalid - - in - - - std_logic - xilinx_veriloginstantiationtemplate - - - - 0x0 - - - - - s_axis_data_tready - - out - - - std_logic - xilinx_veriloginstantiationtemplate - - - - 0x1 - - - - - s_axis_data_tlast - - in - - - std_logic - xilinx_veriloginstantiationtemplate - - - - 0x0 - - - - - - false - - - - - - s_axis_data_tuser - - in - - 0 - 0 - - - - std_logic_vector - xilinx_veriloginstantiationtemplate - - - - 0 - - - - - - false - - - - - - s_axis_data_tdata - - in - - 255 - 0 - - - - std_logic_vector - xilinx_veriloginstantiationtemplate - - - - 0 - - - - - s_axis_config_tvalid - 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- out - - - std_logic - xilinx_veriloginstantiationtemplate - - - - 0x0 - - - - - m_axis_data_tready - - in - - - std_logic - xilinx_veriloginstantiationtemplate - - - - 0x1 - - - - - - false - - - - - - m_axis_data_tlast - - out - - - std_logic - xilinx_veriloginstantiationtemplate - - - - 0x0 - - - - - - false - - - - - - m_axis_data_tuser - - out - - 0 - 0 - - - - std_logic_vector - xilinx_veriloginstantiationtemplate - - - - 0 - - - - - - false - - - - - - m_axis_data_tdata - - out - - 31 - 0 - - - - std_logic_vector - xilinx_veriloginstantiationtemplate - - - - 0 - - - - - event_s_data_tlast_missing - - out - - - std_logic - xilinx_veriloginstantiationtemplate - - - - 0x0 - - - - - - false - - - - - - event_s_data_tlast_unexpected - - out - - - std_logic - xilinx_veriloginstantiationtemplate - - - - 0x0 - - - - - - false - - - - - - event_s_data_chanid_incorrect - - out - - - std_logic - xilinx_veriloginstantiationtemplate - - - - 0x0 - - - - - - false - - - - - - event_s_config_tlast_missing - - out - - - std_logic - xilinx_veriloginstantiationtemplate - - - - 0x0 - - - - - - false - - - - - - event_s_config_tlast_unexpected - - out - - - std_logic - xilinx_veriloginstantiationtemplate - - - - 0x0 - - - - - - false - - - - - - event_s_reload_tlast_missing - - out - - - std_logic - xilinx_veriloginstantiationtemplate - - - - 0x0 - - - - - - false - - - - - - event_s_reload_tlast_unexpected - - out - - - std_logic - xilinx_veriloginstantiationtemplate - - - - 0x0 - - - - - - false - - - - - - - - C_XDEVICEFAMILY - zynquplus - - - C_ELABORATION_DIR - ./ - - - C_COMPONENT_NAME - fir_compiler_0 - - - C_COEF_FILE - fir_compiler_0.mif - - - C_COEF_FILE_LINES - 120 - - - C_FILTER_TYPE - 0 - - - C_INTERP_RATE - 1 - - - C_DECIM_RATE - 1 - - - C_ZERO_PACKING_FACTOR - 1 - - - C_SYMMETRY - 0 - - - C_NUM_FILTS - 1 - - - C_NUM_TAPS - 120 - - - C_NUM_CHANNELS - 1 - - - C_CHANNEL_PATTERN - fixed - - - C_ROUND_MODE - 2 - - - C_COEF_RELOAD - 0 - - - C_NUM_RELOAD_SLOTS - 1 - - - C_COL_MODE - 1 - - - C_COL_PIPE_LEN - 4 - - - C_COL_CONFIG - 120 - - - C_OPTIMIZATION - 0 - - - C_DATA_PATH_WIDTHS - 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16 - - - C_DATA_IP_PATH_WIDTHS - 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16 - - - C_DATA_PX_PATH_WIDTHS - 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16 - - - C_DATA_WIDTH - 16 - - - C_COEF_PATH_WIDTHS - 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16 - - - C_COEF_WIDTH - 16 - - - C_DATA_PATH_SRC - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 - - - C_COEF_PATH_SRC - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - - - C_PX_PATH_SRC - 14,15,14,15,14,15,14,15,14,15,14,15,14,15,14,15 - - - C_DATA_PATH_SIGN - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - - - C_COEF_PATH_SIGN - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - - - C_ACCUM_PATH_WIDTHS - 35,35,35,35,35,35,35,35,35,35,35,35,35,35,35,35 - - - C_OUTPUT_WIDTH - 16 - - - C_OUTPUT_PATH_WIDTHS - 16,16 - - - C_ACCUM_OP_PATH_WIDTHS - 35,35 - - - C_EXT_MULT_CNFG - none - - - C_DATA_PATH_PSAMP_SRC - -0,2,4,6,8,10,12,14;-1,3,5,7,9,11,13,15;0,-2,4,6,8,10,12,14;1,-3,5,7,9,11,13,15;0,2,-4,6,8,10,12,14;1,3,-5,7,9,11,13,15;0,2,4,-6,8,10,12,14;1,3,5,-7,9,11,13,15;0,2,4,6,-8,10,12,14;1,3,5,7,-9,11,13,15;0,2,4,6,8,-10,12,14;1,3,5,7,9,-11,13,15;0,2,4,6,8,10,-12,14;1,3,5,7,9,11,-13,15;0,2,4,6,8,10,12,-14;1,3,5,7,9,11,13,-15 - - - C_OP_PATH_PSAMP_SRC - 0,2,4,6,8,10,12,-14;1,3,5,7,9,11,13,-15 - - - C_NUM_MADDS - 120 - - - C_OPT_MADDS - none - - - C_OVERSAMPLING_RATE - 1 - - - C_INPUT_RATE - 1 - - - C_OUTPUT_RATE - 1 - - - C_DATA_MEMTYPE - 0 - - - C_COEF_MEMTYPE - 2 - - - C_IPBUFF_MEMTYPE - 2 - - - C_OPBUFF_MEMTYPE - 0 - - - C_DATAPATH_MEMTYPE - 2 - - - C_MEM_ARRANGEMENT - 2 - - - C_DATA_MEM_PACKING - 0 - - - C_COEF_MEM_PACKING - 0 - - - C_FILTS_PACKED - 0 - - - C_LATENCY - 126 - - - C_HAS_ARESETn - 0 - - - C_HAS_ACLKEN - 0 - - - C_DATA_HAS_TLAST - 0 - - - C_S_DATA_HAS_FIFO - 0 - - - C_S_DATA_HAS_TUSER - 0 - - - C_S_DATA_TDATA_WIDTH - 256 - - - C_S_DATA_TUSER_WIDTH - 1 - - - C_M_DATA_HAS_TREADY - 0 - - - C_M_DATA_HAS_TUSER - 0 - - - C_M_DATA_TDATA_WIDTH - 32 - - - C_M_DATA_TUSER_WIDTH - 1 - - - C_HAS_CONFIG_CHANNEL - 0 - - - C_CONFIG_SYNC_MODE - 0 - - - C_CONFIG_PACKET_SIZE - 0 - - - C_CONFIG_TDATA_WIDTH - 1 - - - C_RELOAD_TDATA_WIDTH - 1 - - - - - - choice_list_0dc4ca8f - Automatic - Custom - - - choice_list_24b724fb - Basic - Advanced - - - choice_list_3f660234 - All - - - choice_list_5e9d103c - Signed - - - choice_list_8506c89f - Signed - Unsigned - - - choice_list_a63914d2 - Area - Speed - Custom - - - choice_list_dd381b21 - Automatic - Block - Distributed - - - choice_pairs_18e22ec6 - Full_Precision - Truncate_LSBs - Non_Symmetric_Rounding_Down - Non_Symmetric_Rounding_Up - Symmetric_Rounding_to_Zero - Symmetric_Rounding_to_Infinity - Convergent_Rounding_to_Even - Convergent_Rounding_to_Odd - - - choice_pairs_2074757d - None - All - Data_Path_Fanout - Pre-Adder_Pipeline - Coefficient_Fanout - Control_Path_Fanout - Control_Column_Fanout - Control_Broadcast_Fanout - Control_LUT_Pipeline - No_BRAM_Read_First_Mode - Optimal_Column_Lengths - Data_Path_Broadcast - Disable_Half_Band_Centre_Tap - No_SRL_Attributes - Other - - - choice_pairs_2b265cc8 - Frequency_Specification - Input_Sample_Period - Output_Sample_Period - - - choice_pairs_3ab545a3 - Not_Required - Chan_ID_Field - - - choice_pairs_433eb1cb - Inferred - Non_Symmetric - - - choice_pairs_480f8ce0 - Not_Required - Packet_Framing - - - choice_pairs_74144f21 - COE_File - Vector - - - choice_pairs_789dfe7d - Single_Rate - Interpolation - Decimation - Hilbert - Interpolated - - - choice_pairs_8e2d2e35 - Not_Required - User_Field - - - choice_pairs_ab4ea833 - Systolic_Multiply_Accumulate - - - choice_pairs_b6c64168 - Single - By_Channel - - - choice_pairs_eb2746f0 - Integer - Fixed_Fractional - - - choice_pairs_f611af79 - On_Vector - On_Packet - - - choice_pairs_fd92e388 - Integer_Coefficients - Quantize_Only - Maximize_Dynamic_Range - - - - - xilinx_veriloginstantiationtemplate_view_fileset - - fir_compiler_0.vho - vhdlTemplate - - - fir_compiler_0.veo - verilogTemplate - - - - The Xilinx FIR Compiler LogiCORE is a module for generation of high speed, compact filter implementations that can be configured to implement many different filtering functions. The core is fully synchronous, using a single clock, and is highly parameterizable, allowing designers to control the filter type, data and coefficient widths, the number of filter taps, the number of channels, etc. Multi-rate operation is supported. The core is delivered through the Xilinx Vivado IP Catalog and integrates seamlessly with the Xilinx design flow. - - - Component_Name - fir_compiler_0 - - - GUI_Behaviour - Coregen - - - CoefficientSource - COE_File - - - CoefficientVector - 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 - - - Coefficient_File - ../fir.coe - - - Coefficient_Sets - 1 - - - Coefficient_Reload - false - - - Filter_Type - Decimation - - - Rate_Change_Type - Integer - - - Interpolation_Rate - 1 - - - Decimation_Rate - 8 - - - Zero_Pack_Factor - 1 - - - Channel_Sequence - Basic - - - Number_Channels - 1 - - - Select_Pattern - All - - - Pattern_List - P4-0,P4-1,P4-2,P4-3,P4-4 - - - Number_Paths - 2 - - - RateSpecification - Output_Sample_Period - - - HardwareOversamplingRate - 1 - - - SamplePeriod - 1 - - - Sample_Frequency - 0.001 - - - Clock_Frequency - 300.0 - - - Coefficient_Sign - Signed - - - Quantization - Integer_Coefficients - - - Coefficient_Width - 16 - - - BestPrecision - false - - - Coefficient_Fractional_Bits - 0 - - - Coefficient_Structure - Inferred - - - Data_Sign - Signed - - - Data_Width - 16 - - - Data_Fractional_Bits - 0 - - - Output_Rounding_Mode - Symmetric_Rounding_to_Zero - - - Output_Width - 16 - - - Filter_Architecture - Systolic_Multiply_Accumulate - - - Optimization_Goal - Area - - - Optimization_Selection - None - - - Optimization_List - None - - - Data_Buffer_Type - Automatic - - - Coefficient_Buffer_Type - Automatic - - - Input_Buffer_Type - Automatic - - - Output_Buffer_Type - Automatic - - - Preference_For_Other_Storage - Automatic - - - Multi_Column_Support - Automatic - - - Inter_Column_Pipe_Length - 4 - - - ColumnConfig - 120 - - - DATA_Has_TLAST - Not_Required - - - M_DATA_Has_TREADY - false - - - S_DATA_Has_FIFO - false - - - S_DATA_Has_TUSER - Not_Required - - - M_DATA_Has_TUSER - Not_Required - - - DATA_TUSER_Width - 1 - - - S_CONFIG_Sync_Mode - On_Vector - - - S_CONFIG_Method - Single - - - Num_Reload_Slots - 1 - - - Has_ACLKEN - false - - - Has_ARESETn - false - - - Reset_Data_Vector - true - - - Blank_Output - false - - - Gen_MIF_from_Spec - false - - - Gen_MIF_from_COE - false - - - Reload_File - no_coe_file_loaded - - - Gen_MIF_Files - false - - - DisplayReloadOrder - false - - - Passband_Min - 0.0 - - - Passband_Max - 0.5 - - - Stopband_Min - 0.5 - - - Stopband_Max - 1.0 - - - Filter_Selection - 1 - - - - - FIR Compiler - 12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2019.1 - - - - - - - - diff --git a/qick/firmware/ip/axis_readout_v1/src/readout_top.v b/qick/firmware/ip/axis_readout_v1/src/readout_top.v deleted file mode 100644 index df886fd..0000000 --- a/qick/firmware/ip/axis_readout_v1/src/readout_top.v +++ /dev/null @@ -1,92 +0,0 @@ -module readout_top - ( - // Reset and clock (s1_axis, m0_axis, m1_axis). - aresetn , - aclk , - - // S1_AXIS: for input data (8x samples per clock). - s_axis_tdata , - s_axis_tvalid , - s_axis_tready , - - // M0_AXIS: for output data (before filter and decimation, 8x samples - // per clock). - m0_axis_tready , - m0_axis_tvalid , - m0_axis_tdata , - - // M1_AXIS: for output data. - m1_axis_tready , - m1_axis_tvalid , - m1_axis_tdata , - - // Registers. - OUTSEL_REG , - DDS_FREQ_REG - ); - -/**************/ -/* Parameters */ -/**************/ -// Number of parallel dds blocks. -localparam [15:0] N_DDS = 8; - -/*********/ -/* Ports */ -/*********/ -input aresetn; -input aclk; - -output s_axis_tready; -input s_axis_tvalid; -input [N_DDS*16-1:0] s_axis_tdata; - -input m0_axis_tready; -output m0_axis_tvalid; -output [N_DDS*32-1:0] m0_axis_tdata; - -input m1_axis_tready; -output m1_axis_tvalid; -output [32-1:0] m1_axis_tdata; - -input [1:0] OUTSEL_REG; -input [15:0] DDS_FREQ_REG; - -/********************/ -/* Internal signals */ -/********************/ - -/**********************/ -/* Begin Architecture */ -/**********************/ - -// Down-conversion + Filter + Decimation. -down_conversion_fir - down_conversion_fir_i - ( - // Reset and clock. - .rstn (aresetn ), - .clk (aclk ), - - // S_AXIS for input. - .s_axis_tready_o (s_axis_tready ), - .s_axis_tvalid_i (s_axis_tvalid ), - .s_axis_tdata_i (s_axis_tdata ), - - // M0_AXIS for output data (before filter and decimation). - .m0_axis_tready_i (m0_axis_tready ), - .m0_axis_tvalid_o (m0_axis_tvalid ), - .m0_axis_tdata_o (m0_axis_tdata ), - - // M1_AXIS for output data. - .m1_axis_tready_i (m1_axis_tready ), - .m1_axis_tvalid_o (m1_axis_tvalid ), - .m1_axis_tdata_o (m1_axis_tdata ), - - // Registers. - .OUTSEL_REG (OUTSEL_REG ), - .DDS_FREQ_REG (DDS_FREQ_REG ) - ); - -endmodule - diff --git a/qick/firmware/ip/axis_readout_v1/src/tb/data_iq.txt b/qick/firmware/ip/axis_readout_v1/src/tb/data_iq.txt deleted file mode 100644 index 301691a..0000000 --- a/qick/firmware/ip/axis_readout_v1/src/tb/data_iq.txt +++ /dev/null @@ -1,10000 +0,0 @@ -16392,0 -3219,0 --15142,0 --9091,0 -11604,0 -13648,0 --6276,0 --16068,0 -11,0 -16054,0 -6273,0 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--16069,0 --6281,0 -13650,0 -11564,0 --9085,0 --15115,0 -3211,0 -16358,0 -3188,0 --15134,0 --9115,0 -11605,0 -13633,0 --6248,0 --16062,0 -11,0 -16064,0 -6253,0 --13608,0 --11604,0 -9089,0 -15130,0 --3169,0 diff --git a/qick/firmware/ip/axis_readout_v1/src/tb/tb.sv b/qick/firmware/ip/axis_readout_v1/src/tb/tb.sv deleted file mode 100644 index 2774dae..0000000 --- a/qick/firmware/ip/axis_readout_v1/src/tb/tb.sv +++ /dev/null @@ -1,358 +0,0 @@ -// VIP: axi_mst_0 -// DUT: axis_readout_v1 -// IF: s_axi -> axi_mst_0 - -import axi_vip_pkg::*; -import axi_mst_0_pkg::*; - -module tb(); - -// Define Behavioral or Post-Synthesis simulation. -//`define SYNTH_SIMU - -localparam N_DDS = 8; - -// s_axi interfase. -reg s_axi_aclk; -reg s_axi_aresetn; -wire [5:0] s_axi_araddr; -wire [2:0] s_axi_arprot; -wire s_axi_arready; -wire s_axi_arvalid; -wire [5:0] s_axi_awaddr; -wire [2:0] s_axi_awprot; -wire s_axi_awready; -wire s_axi_awvalid; -wire s_axi_bready; -wire [1:0] s_axi_bresp; -wire s_axi_bvalid; -wire [31:0] s_axi_rdata; -wire s_axi_rready; -wire [1:0] s_axi_rresp; -wire s_axi_rvalid; -wire [31:0] s_axi_wdata; -wire s_axi_wready; -wire [3:0] s_axi_wstrb; -wire s_axi_wvalid; - -reg aresetn; -reg aclk; - -// s_axis interfase. -wire s_axis_tready; -reg s_axis_tvalid; -reg [N_DDS*16-1:0] s_axis_tdata; - -// m0_axis interfase. -reg m0_axis_tready; -wire m0_axis_tvalid; -reg [N_DDS*32-1:0] m0_axis_tdata; - -// m1_axis interfase. -reg m1_axis_tready; -wire m1_axis_tvalid; -reg [32-1:0] m1_axis_tdata; - -// Assignment of data out for debugging. -wire [31:0] dout_ii [0:N_DDS-1]; - -xil_axi_prot_t prot = 0; -reg[31:0] data_wr = 32'h12345678; -reg[31:0] data; -xil_axi_resp_t resp; - -// Test bench control. -reg tb_data_in = 0; -reg tb_data_in_done = 0; -reg tb_write_out = 0; - -// Debug. -generate -genvar ii; -for (ii = 0; ii < N_DDS; ii = ii + 1) begin : GEN_debug - assign dout_ii[ii] = m0_axis_tdata[32*ii +: 32]; -end -endgenerate - -// axi_mst_0. -axi_mst_0 axi_mst_0_i - ( - .aclk (s_axi_aclk ), - .aresetn (s_axi_aresetn ), - .m_axi_araddr (s_axi_araddr ), - .m_axi_arprot (s_axi_arprot ), - .m_axi_arready (s_axi_arready ), - .m_axi_arvalid (s_axi_arvalid ), - .m_axi_awaddr (s_axi_awaddr ), - .m_axi_awprot (s_axi_awprot ), - .m_axi_awready (s_axi_awready ), - .m_axi_awvalid (s_axi_awvalid ), - .m_axi_bready (s_axi_bready ), - .m_axi_bresp (s_axi_bresp ), - .m_axi_bvalid (s_axi_bvalid ), - .m_axi_rdata (s_axi_rdata ), - .m_axi_rready (s_axi_rready ), - .m_axi_rresp (s_axi_rresp ), - .m_axi_rvalid (s_axi_rvalid ), - .m_axi_wdata (s_axi_wdata ), - .m_axi_wready (s_axi_wready ), - .m_axi_wstrb (s_axi_wstrb ), - .m_axi_wvalid (s_axi_wvalid ) - ); - -axis_readout_v1 - DUT - ( - // AXI Slave I/F for configuration. - .s_axi_aclk (s_axi_aclk ), - .s_axi_aresetn (s_axi_aresetn ), - .s_axi_araddr (s_axi_araddr ), - .s_axi_arprot (s_axi_arprot ), - .s_axi_arready (s_axi_arready ), - .s_axi_arvalid (s_axi_arvalid ), - .s_axi_awaddr (s_axi_awaddr ), - .s_axi_awprot (s_axi_awprot ), - .s_axi_awready (s_axi_awready ), - .s_axi_awvalid (s_axi_awvalid ), - .s_axi_bready (s_axi_bready ), - .s_axi_bresp (s_axi_bresp ), - .s_axi_bvalid (s_axi_bvalid ), - .s_axi_rdata (s_axi_rdata ), - .s_axi_rready (s_axi_rready ), - .s_axi_rresp (s_axi_rresp ), - .s_axi_rvalid (s_axi_rvalid ), - .s_axi_wdata (s_axi_wdata ), - .s_axi_wready (s_axi_wready ), - .s_axi_wstrb (s_axi_wstrb ), - .s_axi_wvalid (s_axi_wvalid ), - - // s_* and m_* reset/clock. - .aresetn (aresetn ), - .aclk (aclk ), - - // S_AXIS: for input data (8x samples per clock). - .s_axis_tdata (s_axis_tdata ), - .s_axis_tvalid (s_axis_tvalid ), - .s_axis_tready (s_axis_tready ), - - // M0_AXIS: for output data (before filter and decimation, 8x samples - // per clock). - .m0_axis_tready (m0_axis_tready ), - .m0_axis_tvalid (m0_axis_tvalid ), - .m0_axis_tdata (m0_axis_tdata ), - - // M1_AXIS: for output data. - .m1_axis_tready (m1_axis_tready ), - .m1_axis_tvalid (m1_axis_tvalid ), - .m1_axis_tdata (m1_axis_tdata ) - ); - -// VIP Agents -axi_mst_0_mst_t axi_mst_0_agent; - -initial begin - // Create agents. - axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); - - // Set tag for agents. - axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); - - // Start agents. - axi_mst_0_agent.start_master(); - - // Reset sequence. - s_axi_aresetn <= 0; - m0_axis_tready <= 1; - m1_axis_tready <= 1; - aresetn <= 0; - #500; - s_axi_aresetn <= 1; - aresetn <= 1; - - #1000; - - $display("###############################"); - $display("### Start Recording Outputs ###"); - $display("###############################"); - $display("t = %0t", $time); - - tb_write_out <= 1; - - - $display("#############################"); - $display("### Select M0_AXIS output ###"); - $display("#############################"); - $display("t = %0t", $time); - - data_wr = 2; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(0, prot, data_wr, resp); - #10; - - #1000; - - $display("###################"); - $display("### Program DDS ###"); - $display("###################"); - $display("t = %0t", $time); - - data_wr = freq_calc(100, N_DDS, 625); - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4, prot, data_wr, resp); - #10; - - #1000; - - #1000; - - $display("#######################"); - $display("### Send Input Data ###"); - $display("#######################"); - $display("t = %0t", $time); - tb_data_in <= 1; - - wait (tb_data_in_done); - - #1000; - - $display("##############################"); - $display("### Stop Recording Outputs ###"); - $display("##############################"); - $display("t = %0t", $time); - tb_write_out <= 0; - - #20000; - -end - -// Input data. -initial begin - int fd, i; - bit signed [15:0] vali, valq; - - tb_data_in_done <= 0; - s_axis_tvalid <= 1; - s_axis_tdata <= 0; - - wait (tb_data_in); - - #1000; - - // Open file with input data. - // Format: I, Q. - `ifdef SYNTH_SIMU - fd = $fopen("../../../../../../tb/data_iq.txt","r"); - `else - fd = $fopen("../../../../../tb/data_iq.txt","r"); - `endif - - //i = N_DDS; - i = 0; - while ($fscanf(fd,"%d,%d", vali, valq) == 2) begin - $display("Time %t: Line %d, I = %d, Q = %d", $time, i, vali, valq); - //s_axis_tdata_i[(i-1)*16 +: 16] <= vali; - s_axis_tdata[i*16 +: 16] <= vali; - //i = i - 1; - i = i + 1; - //if ( i == 0) begin - if ( i == N_DDS) begin - //i = N_DDS; - i = 0; - @(posedge aclk); - end - end - - #1000; - - @(posedge aclk); - tb_data_in_done <= 1; - -end - -// Write output into file. -initial begin - int fd; - int i; - shortint real_d, imag_d; - - // Output file. - `ifdef SYNTH_SIMU - fd = $fopen("../../../../../../tb/dout_fs.csv","w"); - `else - fd = $fopen("../../../../../tb/dout_fs.csv","w"); - `endif - - // Data format. - $fdisplay(fd, "valid, idx, real, imag"); - - wait (tb_write_out); - - while (tb_write_out) begin - @(posedge aclk); - for (i=0; i - - user.org - user - axis_readout_v2 - 1.0 - - - m0_axis - - - - - - - TDATA - - - m0_axis_tdata - - - - - TVALID - - - m0_axis_tvalid - - - - - TREADY - - - m0_axis_tready - - - - - - - true - - - - - - m1_axis - - - - - - - TDATA - - - m1_axis_tdata - - - - - TVALID - - - m1_axis_tvalid - - - - - TREADY - - - m1_axis_tready - - - - - - s_axis - - - - - - - TDATA - - - s_axis_tdata - - - - - TVALID - - - s_axis_tvalid - - - - - TREADY - - - s_axis_tready - - - - - - s_axi - - - - - - - - - AWADDR - - - s_axi_awaddr - - - - - AWPROT - - - s_axi_awprot - - - - - AWVALID - - - s_axi_awvalid - - - - - AWREADY - - - s_axi_awready - - - - - WDATA - - - s_axi_wdata - - - - - WSTRB - - - s_axi_wstrb - - - - - WVALID - - - s_axi_wvalid - - - - - WREADY - - - s_axi_wready - - - - - BRESP - - - s_axi_bresp - - - - - BVALID - - - s_axi_bvalid - - - - - BREADY - - - s_axi_bready - - - - - ARADDR - - - s_axi_araddr - - - - - ARPROT - - - s_axi_arprot - - - - - ARVALID - - - s_axi_arvalid - - - - - ARREADY - - - s_axi_arready - - - - - RDATA - - - s_axi_rdata - - - - - RRESP - - - s_axi_rresp - - - - - RVALID - - - s_axi_rvalid - - - - - RREADY - - - s_axi_rready - - - - - - s_axi_aclk - - - - - - - CLK - - - s_axi_aclk - - - - - - ASSOCIATED_BUSIF - s_axi - - - ASSOCIATED_RESET - s_axi_aresetn - - - - - s_axi_aresetn - - - - - - - RST - - - s_axi_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - aclk - - - - - - - CLK - - - aclk - - - - - - ASSOCIATED_BUSIF - m0_axis:m1_axis:s_axis - - - ASSOCIATED_RESET - aresetn - - - - - aresetn - - - - - - - RST - - - aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - - - s_axi - - reg0 - 0 - 64 - 32 - register - - - - - - - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis - Verilog - axis_readout_v2 - - xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset - - - xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset - - - xilinx_anylanguagesynthesis_view_fileset - - - - viewChecksum - 6e284896 - - - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - Verilog - axis_readout_v2 - - xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset - - - xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - - - viewChecksum - 6e284896 - - - - - xilinx_xpgui - UI Layout - :vivado.xilinx.com:xgui.ui - - xilinx_xpgui_view_fileset - - - - viewChecksum - f835ce2d - - - - - - - s_axi_aclk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_aresetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_awaddr - - in - - 5 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_awprot - - in - - 2 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_awvalid - - in - - - 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s_axi_rvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_rready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - aresetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - aclk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axis_tdata - - in - - 127 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axis_tvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axis_tready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m0_axis_tready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 1 - - - - - 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CELL_NAME_readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/dds_compiler_0 - - - src/fir.coe - coe - - - src/down_conversion.v - verilogSource - - - src/down_conversion_fir.v - verilogSource - - - src/readout_top.v - verilogSource - - - src/ctrl.sv - systemVerilogSource - - - src/axi_slv.vhd - vhdlSource - - - src/fifo/bram_simple_dp.vhd - vhdlSource - - - src/fifo/fifo.vhd - vhdlSource - - - src/synchronizer_n.vhd - vhdlSource - - - src/axis_readout_v2.v - verilogSource - - - - xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset - - - - - - - - - - xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset - - - - - - - - - - xilinx_xpgui_view_fileset - - xgui/axis_readout_v2_v1_0.tcl - tclSource - CHECKSUM_f835ce2d - XGUI_VERSION_2 - - - - AXIS Readout V2 block with digital down-conversion (32-bit, phase coherent), filtering and 8x decimation. - - - Component_Name - axis_readout_v2_v1_0 - - - FULLSPEED_OUTPUT - Fullspeed Output - true - - - - - - zynquplus - - - /UserIP - - AXIS Readout V2 - package_project - 8 - 2023-02-13T23:05:36Z - - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/qsystem_2/ip/axis_readout_v2 - /home/lstefana/v20.2/zcu216/q3diamond/ip/axis_readout_v2 - /home/lstefana/v20.2/zcu216/q3diamond/ip/axis_readout_v2 - /home/lstefana/v20.2/zcu216/q3diamond/ip/axis_readout_v2 - /home/lstefana/v20.2/zcu216/q3diamond/ip/axis_readout_v2 - /home/lstefana/v20.2/zcu216/q3diamond/ip/axis_readout_v2 - /home/lstefana/v20.2/zcu216/q3diamond/ip/axis_readout_v2 - /home/lstefana/v20.2/zcu216/q3diamond/ip/axis_readout_v2 - /home/lstefana/v20.2/zcu216/q3diamond/ip/axis_readout_v2 - /home/lstefana/v20.2/zcu216/q3diamond/ip/axis_readout_v2 - /home/lstefana/v20.2/zcu216/q3diamond/ip/axis_readout_v2 - /home/lstefana/v20.2/zcu216/q3diamond/ip/axis_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 - /home/lstefana/qick/firmware/ip/axis_readout_v2 - /home/lstefana/qick/firmware/ip/axis_readout_v2 - /home/lstefana/qick/firmware/ip/axis_readout_v2 - /home/lstefana/qick/firmware/ip/axis_readout_v2 - /home/lstefana/qick/firmware/ip/axis_readout_v2 - /home/lstefana/qick/firmware/ip/axis_readout_v2 - /home/lstefana/qick/firmware/ip/axis_readout_v2 - /home/lstefana/qick/firmware/ip/axis_readout_v2 - /home/lstefana/qick/firmware/ip/axis_readout_v2 - /home/lstefana/qick/firmware/ip/axis_readout_v2 - /home/lstefana/qick/firmware/ip/axis_readout_v2 - /home/lstefana/qick/firmware/ip/axis_readout_v2 - /home/lstefana/qick/firmware/ip/axis_readout_v2 - /home/lstefana/qick/firmware/ip/axis_readout_v2 - /home/lstefana/qick/firmware/ip/axis_readout_v2 - /home/lstefana/qick/firmware/ip/axis_readout_v2 - /home/lstefana/qick/firmware/ip/axis_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 - /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 - - - - 2020.2 - - - - - - - - diff --git a/qick/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.veo b/qick/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.veo deleted file mode 100644 index 7cfbd51..0000000 --- a/qick/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.veo +++ /dev/null @@ -1,85 +0,0 @@ -// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -// IP VLNV: xilinx.com:ip:axi_vip:1.1 -// IP Revision: 8 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -axi_mst_0 your_instance_name ( - .aclk(aclk), // input wire aclk - .aresetn(aresetn), // input wire aresetn - .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr - .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot - .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid - .m_axi_awready(m_axi_awready), // input wire m_axi_awready - .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata - .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb - .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid - .m_axi_wready(m_axi_wready), // input wire m_axi_wready - .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp - .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid - .m_axi_bready(m_axi_bready), // output wire m_axi_bready - .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr - .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot - .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid - .m_axi_arready(m_axi_arready), // input wire m_axi_arready - .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata - .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp - .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid - .m_axi_rready(m_axi_rready) // output wire m_axi_rready -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file axi_mst_0.v when simulating -// the core, axi_mst_0. When compiling the wrapper file, be sure to -// reference the Verilog simulation library. - diff --git a/qick/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.vho b/qick/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.vho deleted file mode 100644 index a53be60..0000000 --- a/qick/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.vho +++ /dev/null @@ -1,115 +0,0 @@ --- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:axi_vip:1.1 --- IP Revision: 8 - --- The following code must appear in the VHDL architecture header. - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT axi_mst_0 - PORT ( - aclk : IN STD_LOGIC; - aresetn : IN STD_LOGIC; - m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - m_axi_awvalid : OUT STD_LOGIC; - m_axi_awready : IN STD_LOGIC; - m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - m_axi_wvalid : OUT STD_LOGIC; - m_axi_wready : IN STD_LOGIC; - m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - m_axi_bvalid : IN STD_LOGIC; - m_axi_bready : OUT STD_LOGIC; - m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - m_axi_arvalid : OUT STD_LOGIC; - m_axi_arready : IN STD_LOGIC; - m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - m_axi_rvalid : IN STD_LOGIC; - m_axi_rready : OUT STD_LOGIC - ); -END COMPONENT; --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : axi_mst_0 - PORT MAP ( - aclk => aclk, - aresetn => aresetn, - m_axi_awaddr => m_axi_awaddr, - m_axi_awprot => m_axi_awprot, - m_axi_awvalid => m_axi_awvalid, - m_axi_awready => m_axi_awready, - m_axi_wdata => m_axi_wdata, - m_axi_wstrb => m_axi_wstrb, - m_axi_wvalid => m_axi_wvalid, - m_axi_wready => m_axi_wready, - m_axi_bresp => m_axi_bresp, - m_axi_bvalid => m_axi_bvalid, - m_axi_bready => m_axi_bready, - m_axi_araddr => m_axi_araddr, - m_axi_arprot => m_axi_arprot, - m_axi_arvalid => m_axi_arvalid, - m_axi_arready => m_axi_arready, - m_axi_rdata => m_axi_rdata, - m_axi_rresp => m_axi_rresp, - m_axi_rvalid => m_axi_rvalid, - m_axi_rready => m_axi_rready - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file axi_mst_0.vhd when simulating --- the core, axi_mst_0. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/qick/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.xci b/qick/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.xci deleted file mode 100644 index ac9cf04..0000000 --- a/qick/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.xci +++ /dev/null @@ -1,200 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - axi_mst_0 - - - ACTIVE_LOW - - 100000000 - 0 - 0 - 0.000 - 32 - 0 - 0 - 0 - - 32 - 100000000 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 32 - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 0 - 2 - 32 - 0 - 0 - 0 - 32 - 0 - 0 - 32 - 0 - 0 - 0 - axi_mst_0 - 32 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 0 - 0 - 1 - 0 - MASTER - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - zynquplusRFSOC - xilinx.com:zcu216:part0:2.0 - - xczu49dr - ffvf1760 - VERILOG - - MIXED - -2 - - E - TRUE - TRUE - IP_Flow - 8 - TRUE - . - - . - 2020.2 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/qick/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.xml b/qick/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.xml deleted file mode 100644 index 4b49cfe..0000000 --- a/qick/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.xml +++ /dev/null @@ -1,4760 +0,0 @@ - - - xilinx.com - customized_ip - axi_mst_0 - 1.0 - - - M_AXI - - - - - - - - - ARADDR - - - m_axi_araddr - - - - - ARBURST - - - m_axi_arburst - - - - - ARCACHE - - - m_axi_arcache - - - - - ARID - - - m_axi_arid - - - - - ARLEN - - - m_axi_arlen - - - - - ARLOCK - - - m_axi_arlock - - - - - ARPROT - - - m_axi_arprot - - - - - ARQOS - - - m_axi_arqos - - - - - ARREADY - - - m_axi_arready - - - - - ARREGION - - - m_axi_arregion - - - - - ARSIZE - - - m_axi_arsize - - - - - ARUSER - - - m_axi_aruser - - - - - ARVALID - - - m_axi_arvalid - - - - - AWADDR - - - m_axi_awaddr - - - - - AWBURST - - - m_axi_awburst - - - - - AWCACHE - - - m_axi_awcache - - - - - AWID - - - m_axi_awid - - - - - AWLEN - - - m_axi_awlen - - - - - AWLOCK - - - m_axi_awlock - - - - - AWPROT - - - m_axi_awprot - - - - - AWQOS - - - m_axi_awqos - - - - - AWREADY - - - m_axi_awready - - - - - AWREGION - - - m_axi_awregion - - - - - AWSIZE - - - m_axi_awsize - - - - - AWUSER - - - m_axi_awuser - - - - - AWVALID - - - m_axi_awvalid - - - - - BID - - - m_axi_bid - - - - - BREADY - - - m_axi_bready - - - - - BRESP - - - m_axi_bresp - - - - - BUSER - - - m_axi_buser - - - - - BVALID - - - m_axi_bvalid - - - - - RDATA - - - m_axi_rdata - - - - - RID - - - m_axi_rid - - - - - RLAST - - - m_axi_rlast - - - - - RREADY - - - m_axi_rready - - - - - RRESP - - - m_axi_rresp - - - - - RUSER - - - m_axi_ruser - - - - - RVALID - - - m_axi_rvalid - - - - - WDATA - - - m_axi_wdata - - - - - WID - - - m_axi_wid - - - - - WLAST - - - m_axi_wlast - - - - - WREADY - - - m_axi_wready - - - - - WSTRB - - - m_axi_wstrb - - - - - WUSER - - - m_axi_wuser - - - - - WVALID - - - m_axi_wvalid - - - - - - DATA_WIDTH - 32 - - - simulation.tlm - - - - - PROTOCOL - AXI4LITE - - - simulation.tlm - - - - - FREQ_HZ - 100000000 - - - simulation.tlm - - - - - ID_WIDTH - 0 - - - simulation.tlm - - - - - ADDR_WIDTH - 32 - - - simulation.tlm - - - - - AWUSER_WIDTH - 0 - - - simulation.tlm - - - - - ARUSER_WIDTH - 0 - - - simulation.tlm - - - - - WUSER_WIDTH - 0 - - - simulation.tlm - - - - - RUSER_WIDTH - 0 - - - simulation.tlm - - - - - BUSER_WIDTH - 0 - - - simulation.tlm - - - - - READ_WRITE_MODE - READ_WRITE - - - simulation.tlm - - - - - HAS_BURST - 0 - - - simulation.tlm - - - - - HAS_LOCK - 0 - - - simulation.tlm - - - - - HAS_PROT - 1 - - - simulation.tlm - - - - - HAS_CACHE - 0 - - - simulation.tlm - - - - - HAS_QOS - 0 - - - simulation.tlm - - - - - HAS_REGION - 0 - - - simulation.tlm - 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AXIMM Socket for Write - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - rd_socket - - - - - - - 1 - - - - - - - C_AXI_PROTOCOL - 2 - - - C_AXI_INTERFACE_MODE - 0 - - - C_AXI_ADDR_WIDTH - 32 - - - C_AXI_WDATA_WIDTH - 32 - - - C_AXI_RDATA_WIDTH - 32 - - - C_AXI_WID_WIDTH - 0 - - - C_AXI_RID_WIDTH - 0 - - - C_AXI_AWUSER_WIDTH - 0 - - - C_AXI_ARUSER_WIDTH - 0 - - - C_AXI_WUSER_WIDTH - 0 - - - C_AXI_RUSER_WIDTH - 0 - - - C_AXI_BUSER_WIDTH - 0 - - - C_AXI_SUPPORTS_NARROW - 0 - - - C_AXI_HAS_BURST - 0 - - - C_AXI_HAS_LOCK - 0 - - - C_AXI_HAS_CACHE - 0 - - - C_AXI_HAS_REGION - 0 - - - C_AXI_HAS_PROT - 1 - - - C_AXI_HAS_QOS - 0 - - - C_AXI_HAS_WSTRB - 1 - - - C_AXI_HAS_BRESP - 1 - - - C_AXI_HAS_RRESP - 1 - - - C_AXI_HAS_ARESETN - 1 - - - - - - choice_list_04fafd91 - AXI3 - AXI4 - AXI4LITE - - - choice_list_6240decd - READ_ONLY - READ_WRITE - WRITE_ONLY - - - choice_list_642e7122 - MASTER - PASS_THROUGH - SLAVE - - - choice_list_99ba8646 - 32 - 64 - - - choice_list_9d8b0d81 - ACTIVE_HIGH - ACTIVE_LOW - - - choice_pairs_0fc128e8 - 0 - 0 - - - - - xilinx_veriloginstantiationtemplate_view_fileset - - axi_mst_0.vho - vhdlTemplate - - - axi_mst_0.veo - verilogTemplate - - - - xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset - - hdl/axi_infrastructure_v1_1_0.vh - verilogSource - true - axi_infrastructure_v1_1_0 - - - hdl/axi_infrastructure_v1_1_vl_rfs.v - verilogSource - axi_infrastructure_v1_1_0 - - - - - - - - - - - xilinx_verilogsynthesis_view_fileset - - hdl/axi_vip_v1_1_vlsyn_rfs.sv - systemVerilogSource - axi_vip_v1_1_8 - - - - xilinx_synthesisconstraints_view_fileset - - axi_mst_0_ooc.xdc - xdc - USED_IN_implementation - USED_IN_out_of_context - USED_IN_synthesis - - - - xilinx_verilogsynthesiswrapper_view_fileset - - synth/axi_mst_0.sv - systemVerilogSource - xil_defaultlib - - - - xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset - - hdl/axi_infrastructure_v1_1_0.vh - verilogSource - USED_IN_ipstatic - true - axi_infrastructure_v1_1_0 - - - hdl/axi_infrastructure_v1_1_vl_rfs.v - verilogSource - USED_IN_ipstatic - axi_infrastructure_v1_1_0 - - - - - - - - - - - xilinx_verilogbehavioralsimulation_view_fileset - - sim/axi_mst_0_pkg.sv - systemVerilogSource - - - hdl/axi_vip_v1_1_vl_rfs.sv - systemVerilogSource - USED_IN_ipstatic - axi_vip_v1_1_8 - - - - xilinx_systemcsimulation_view_fileset - - sysc/axi_vip.cpp - systemCSource - axi_vip_v1_1_8 - - - sysc/axi_vip.h - systemCSource - true - axi_vip_v1_1_8 - - - - xilinx_verilogsimulationwrapper_view_fileset - - sim/axi_mst_0.sv - systemVerilogSource - xil_defaultlib - - - - xilinx_systemcsimulationwrapper_view_fileset - - sim/axi_mst_0_sc.h - systemCSource - true - - - sim/axi_mst_0_sc.cpp - systemCSource - - - sim/axi_mst_0.h - systemCSource - true - - - sim/axi_mst_0.cpp - systemCSource - - - sim/axi_mst_0_stub.sv - systemVerilogSource - - - - xilinx_versioninformation_view_fileset - - doc/axi_vip_v1_1_changelog.txt - text - axi_vip_v1_1_8 - - - - xilinx_externalfiles_view_fileset - - axi_mst_0.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - axi_mst_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - axi_mst_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - axi_mst_0_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - axi_mst_0_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - - The AXI Verification IP. - - - Component_Name - Component Name - axi_mst_0 - - - PROTOCOL - PROTOCOL - AXI4LITE - - - READ_WRITE_MODE - READ_WRITE MODE - READ_WRITE - - - INTERFACE_MODE - INTERFACE MODE - MASTER - - - ADDR_WIDTH - ADDRESS WIDTH - 32 - - - DATA_WIDTH - DATA WIDTH - 32 - - - ID_WIDTH - ID WIDTH - 0 - - - - false - - - - - - AWUSER_WIDTH - AWUSER WIDTH - 0 - - - - false - - - - - - ARUSER_WIDTH - ARUSER WIDTH - 0 - - - - false - - - - - - RUSER_WIDTH - RUSER WIDTH - 0 - - - - false - - - - - - WUSER_WIDTH - WUSER WIDTH - 0 - - - - false - - - - - - BUSER_WIDTH - BUSER WIDTH - 0 - - - - false - - - - - - WUSER_BITS_PER_BYTE - WUSER BITS PER BYTE - 0 - - - - false - - - - - - RUSER_BITS_PER_BYTE - RUSER BITS PER BYTE - 0 - - - - false - - - - - - HAS_USER_BITS_PER_BYTE - HAS USER_BITS_PER_BYTE - 0 - - - - false - - - - - - SUPPORTS_NARROW - SUPPORTS NARROW - 0 - - - - false - - - - - - HAS_SIZE - HAS SIZE - 0 - - - - false - - - - - - HAS_BURST - HAS BURST - 0 - - - - false - - - - - - HAS_LOCK - HAS LOCK - 0 - - - - false - - - - - - HAS_CACHE - HAS CACHE - 0 - - - - false - - - - - - HAS_REGION - HAS REGION - 0 - - - - false - - - - - - HAS_QOS - HAS QOS - 0 - - - - false - - - - - - HAS_PROT - HAS PROT - 1 - - - HAS_WSTRB - HAS WSTRB - 1 - - - HAS_BRESP - HAS BRESP - 1 - - - HAS_RRESP - HAS RRESP - 1 - - - HAS_ACLKEN - HAS ACLKEN - 0 - - - HAS_ARESETN - HAS ARESETN - 1 - - - - - AXI Verification IP - - xtlm - - 8 - true - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2020.2 - - - - - - - - - - diff --git a/qick/firmware/ip/axis_readout_v2/src/axi_slv.vhd b/qick/firmware/ip/axis_readout_v2/src/axi_slv.vhd deleted file mode 100644 index d8aa159..0000000 --- a/qick/firmware/ip/axis_readout_v2/src/axi_slv.vhd +++ /dev/null @@ -1,528 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity axi_slv is - Generic - ( - DATA_WIDTH : integer := 32; - ADDR_WIDTH : integer := 6 - ); - Port - ( - aclk : in std_logic; - aresetn : in std_logic; - - -- Write Address Channel. - awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); - awprot : in std_logic_vector(2 downto 0); - awvalid : in std_logic; - awready : out std_logic; - - -- Write Data Channel. - wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); - wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); - wvalid : in std_logic; - wready : out std_logic; - - -- Write Response Channel. - bresp : out std_logic_vector(1 downto 0); - bvalid : out std_logic; - bready : in std_logic; - - -- Read Address Channel. - araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); - arprot : in std_logic_vector(2 downto 0); - arvalid : in std_logic; - arready : out std_logic; - - -- Read Data Channel. - rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); - rresp : out std_logic_vector(1 downto 0); - rvalid : out std_logic; - rready : in std_logic; - - -- Registers. - FREQ_REG : out std_logic_vector (31 downto 0); - PHASE_REG : out std_logic_vector (31 downto 0); - NSAMP_REG : out std_logic_vector (15 downto 0); - OUTSEL_REG : out std_logic_vector (1 downto 0); - MODE_REG : out std_logic; - WE_REG : out std_logic - ); -end axi_slv; - -architecture rtl of axi_slv is - - -- AXI4LITE signals - signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); - signal axi_awready : std_logic; - signal axi_wready : std_logic; - signal axi_bresp : std_logic_vector(1 downto 0); - signal axi_bvalid : std_logic; - signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); - signal axi_arready : std_logic; - signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); - signal axi_rresp : std_logic_vector(1 downto 0); - signal axi_rvalid : std_logic; - - -- Example-specific design signals - -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH - -- ADDR_LSB is used for addressing 32/64 bit registers/memories - -- ADDR_LSB = 2 for 32 bits (n downto 2) - -- ADDR_LSB = 3 for 64 bits (n downto 3) - constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; - constant OPT_MEM_ADDR_BITS : integer := 3; - ------------------------------------------------ - ---- Signals for user logic register space example - -------------------------------------------------- - ---- Number of Slave Registers 16 - signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg_rden : std_logic; - signal slv_reg_wren : std_logic; - signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); - signal byte_index : integer; - signal aw_en : std_logic; - -begin - -- I/O Connections assignments - - awreadY <= axi_awready; - wready <= axi_wready; - bresp <= axi_bresp; - bvalid <= axi_bvalid; - arreadY <= axi_arready; - rdata <= axi_rdata; - rresp <= axi_rresp; - rvalid <= axi_rvalid; - -- Implement axi_awready generation - -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is - -- de-asserted when reset is low. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_awready <= '0'; - aw_en <= '1'; - else - if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then - -- slave is ready to accept write address when - -- there is a valid write address and write data - -- on the write address and data bus. This design - -- expects no outstanding transactions. - axi_awready <= '1'; - aw_en <= '0'; - elsif (bready = '1' and axi_bvalid = '1') then - aw_en <= '1'; - axi_awready <= '0'; - else - axi_awready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement axi_awaddr latching - -- This process is used to latch the address when both - -- S_AXI_AWVALID and S_AXI_WVALID are valid. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_awaddr <= (others => '0'); - else - if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then - -- Write Address latching - axi_awaddr <= awaddr; - end if; - end if; - end if; - end process; - - -- Implement axi_wready generation - -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is - -- de-asserted when reset is low. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_wready <= '0'; - else - if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then - -- slave is ready to accept write data when - -- there is a valid write address and write data - -- on the write address and data bus. This design - -- expects no outstanding transactions. - axi_wready <= '1'; - else - axi_wready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement memory mapped register select and write logic generation - -- The write data is accepted and written to memory mapped registers when - -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to - -- select byte enables of slave registers while writing. - -- These registers are cleared when reset (active low) is applied. - -- Slave register write enable is asserted when valid address and data are available - -- and the slave is ready to accept the write address and write data. - slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; - - process (aclk) - variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); - begin - if rising_edge(aclk) then - if aresetn = '0' then - slv_reg0 <= (others => '0'); - slv_reg1 <= (others => '0'); - slv_reg2 <= (others => '0'); - slv_reg3 <= (others => '0'); - slv_reg4 <= (others => '0'); - slv_reg5 <= (others => '0'); - slv_reg6 <= (others => '0'); - slv_reg7 <= (others => '0'); - slv_reg8 <= (others => '0'); - slv_reg9 <= (others => '0'); - slv_reg10 <= (others => '0'); - slv_reg11 <= (others => '0'); - slv_reg12 <= (others => '0'); - slv_reg13 <= (others => '0'); - slv_reg14 <= (others => '0'); - slv_reg15 <= (others => '0'); - else - loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); - if (slv_reg_wren = '1') then - case loc_addr is - when b"0000" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 0 - slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0001" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 1 - slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0010" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 2 - slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0011" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 3 - slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0100" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 4 - slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0101" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 5 - slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0110" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 6 - slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0111" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 7 - slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1000" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 8 - slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1001" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 9 - slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1010" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 10 - slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1011" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 11 - slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1100" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 12 - slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1101" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 13 - slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1110" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 14 - slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1111" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 15 - slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when others => - slv_reg0 <= slv_reg0; - slv_reg1 <= slv_reg1; - slv_reg2 <= slv_reg2; - slv_reg3 <= slv_reg3; - slv_reg4 <= slv_reg4; - slv_reg5 <= slv_reg5; - slv_reg6 <= slv_reg6; - slv_reg7 <= slv_reg7; - slv_reg8 <= slv_reg8; - slv_reg9 <= slv_reg9; - slv_reg10 <= slv_reg10; - slv_reg11 <= slv_reg11; - slv_reg12 <= slv_reg12; - slv_reg13 <= slv_reg13; - slv_reg14 <= slv_reg14; - slv_reg15 <= slv_reg15; - end case; - end if; - end if; - end if; - end process; - - -- Implement write response logic generation - -- The write response and response valid signals are asserted by the slave - -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. - -- This marks the acceptance of address and indicates the status of - -- write transaction. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_bvalid <= '0'; - axi_bresp <= "00"; --need to work more on the responses - else - if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then - axi_bvalid <= '1'; - axi_bresp <= "00"; - elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) - axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) - end if; - end if; - end if; - end process; - - -- Implement axi_arready generation - -- axi_arready is asserted for one S_AXI_ACLK clock cycle when - -- S_AXI_ARVALID is asserted. axi_awready is - -- de-asserted when reset (active low) is asserted. - -- The read address is also latched when S_AXI_ARVALID is - -- asserted. axi_araddr is reset to zero on reset assertion. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_arready <= '0'; - axi_araddr <= (others => '1'); - else - if (axi_arready = '0' and arvalid = '1') then - -- indicates that the slave has acceped the valid read address - axi_arready <= '1'; - -- Read Address latching - axi_araddr <= araddr; - else - axi_arready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement axi_arvalid generation - -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_ARVALID and axi_arready are asserted. The slave registers - -- data are available on the axi_rdata bus at this instance. The - -- assertion of axi_rvalid marks the validity of read data on the - -- bus and axi_rresp indicates the status of read transaction.axi_rvalid - -- is deasserted on reset (active low). axi_rresp and axi_rdata are - -- cleared to zero on reset (active low). - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_rvalid <= '0'; - axi_rresp <= "00"; - else - if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then - -- Valid read data is available at the read data bus - axi_rvalid <= '1'; - axi_rresp <= "00"; -- 'OKAY' response - elsif (axi_rvalid = '1' and rready = '1') then - -- Read data is accepted by the master - axi_rvalid <= '0'; - end if; - end if; - end if; - end process; - - -- Implement memory mapped register select and read logic generation - -- Slave register read enable is asserted when valid address is available - -- and the slave is ready to accept the read address. - slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; - - process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) - variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); - begin - -- Address decoding for reading registers - loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); - case loc_addr is - when b"0000" => - reg_data_out <= slv_reg0; - when b"0001" => - reg_data_out <= slv_reg1; - when b"0010" => - reg_data_out <= slv_reg2; - when b"0011" => - reg_data_out <= slv_reg3; - when b"0100" => - reg_data_out <= slv_reg4; - when b"0101" => - reg_data_out <= slv_reg5; - when b"0110" => - reg_data_out <= slv_reg6; - when b"0111" => - reg_data_out <= slv_reg7; - when b"1000" => - reg_data_out <= slv_reg8; - when b"1001" => - reg_data_out <= slv_reg9; - when b"1010" => - reg_data_out <= slv_reg10; - when b"1011" => - reg_data_out <= slv_reg11; - when b"1100" => - reg_data_out <= slv_reg12; - when b"1101" => - reg_data_out <= slv_reg13; - when b"1110" => - reg_data_out <= slv_reg14; - when b"1111" => - reg_data_out <= slv_reg15; - when others => - reg_data_out <= (others => '0'); - end case; - end process; - - -- Output register or memory read data - process( aclk ) is - begin - if (rising_edge (aclk)) then - if ( aresetn = '0' ) then - axi_rdata <= (others => '0'); - else - if (slv_reg_rden = '1') then - -- When there is a valid read address (S_AXI_ARVALID) with - -- acceptance of read address by the slave (axi_arready), - -- output the read dada - -- Read address mux - axi_rdata <= reg_data_out; -- register read data - end if; - end if; - end if; - end process; - - -- Register Map. - -- 0 : FREQ_REG : 32-bit. - -- 1 : PHASE_REG : 32-bit. - -- 2 : NSAMP_REG : 16-bit. - -- 3 : OUTSEL_REG : 2-bit. - -- 4 : MODE_REG : 1-bit. - -- 5 : WE_REG : 1-bit. - - -- Output Registers. - FREQ_REG <= slv_reg0; - PHASE_REG <= slv_reg1; - NSAMP_REG <= slv_reg2(15 downto 0); - OUTSEL_REG <= slv_reg3(1 downto 0); - MODE_REG <= slv_reg4(0); - WE_REG <= slv_reg5(0); - -end rtl; - diff --git a/qick/firmware/ip/axis_readout_v2/src/axis_readout_v2.v b/qick/firmware/ip/axis_readout_v2/src/axis_readout_v2.v deleted file mode 100644 index 692caf0..0000000 --- a/qick/firmware/ip/axis_readout_v2/src/axis_readout_v2.v +++ /dev/null @@ -1,195 +0,0 @@ -module axis_readout_v2 - ( - // AXI Slave I/F for configuration. - s_axi_aclk , - s_axi_aresetn , - - s_axi_awaddr , - s_axi_awprot , - s_axi_awvalid , - s_axi_awready , - - s_axi_wdata , - s_axi_wstrb , - s_axi_wvalid , - s_axi_wready , - - s_axi_bresp , - s_axi_bvalid , - s_axi_bready , - - s_axi_araddr , - s_axi_arprot , - s_axi_arvalid , - s_axi_arready , - - s_axi_rdata , - s_axi_rresp , - s_axi_rvalid , - s_axi_rready , - - // Reset and clock (s_axis, m0_axis, m1_axis). - aresetn , - aclk , - - // S_AXIS: for input data (8x samples per clock). - s_axis_tdata , - s_axis_tvalid , - s_axis_tready , - - // M0_AXIS: for output data (before filter and decimation, 8x samples - // per clock). - m0_axis_tready , - m0_axis_tvalid , - m0_axis_tdata , - - // M1_AXIS: for output data. - m1_axis_tready , - m1_axis_tvalid , - m1_axis_tdata - ); - -/**************/ -/* Parameters */ -/**************/ -// Number of parallel dds blocks. -localparam [15:0] N_DDS = 8; - -/*********/ -/* Ports */ -/*********/ -input s_axi_aclk; -input s_axi_aresetn; - -input [5:0] s_axi_awaddr; -input [2:0] s_axi_awprot; -input s_axi_awvalid; -output s_axi_awready; - -input [31:0] s_axi_wdata; -input [3:0] s_axi_wstrb; -input s_axi_wvalid; -output s_axi_wready; - -output [1:0] s_axi_bresp; -output s_axi_bvalid; -input s_axi_bready; - -input [5:0] s_axi_araddr; -input [2:0] s_axi_arprot; -input s_axi_arvalid; -output s_axi_arready; - -output [31:0] s_axi_rdata; -output [1:0] s_axi_rresp; -output s_axi_rvalid; -input s_axi_rready; - -input aresetn; -input aclk; - -output s_axis_tready; -input s_axis_tvalid; -input [N_DDS*16-1:0] s_axis_tdata; - -input m0_axis_tready; -output m0_axis_tvalid; -output [N_DDS*32-1:0] m0_axis_tdata; - -input m1_axis_tready; -output m1_axis_tvalid; -output [32-1:0] m1_axis_tdata; - -/********************/ -/* Internal signals */ -/********************/ -// Registers. -wire [31:0] FREQ_REG; -wire [31:0] PHASE_REG; -wire [15:0] NSAMP_REG; -wire [1:0] OUTSEL_REG; -wire MODE_REG; -wire WE_REG; - - -/**********************/ -/* Begin Architecture */ -/**********************/ -// AXI Slave. -axi_slv axi_slv_i - ( - .aclk (s_axi_aclk ), - .aresetn (s_axi_aresetn ), - - // Write Address Channel. - .awaddr (s_axi_awaddr ), - .awprot (s_axi_awprot ), - .awvalid (s_axi_awvalid ), - .awready (s_axi_awready ), - - // Write Data Channel. - .wdata (s_axi_wdata ), - .wstrb (s_axi_wstrb ), - .wvalid (s_axi_wvalid ), - .wready (s_axi_wready ), - - // Write Response Channel. - .bresp (s_axi_bresp ), - .bvalid (s_axi_bvalid ), - .bready (s_axi_bready ), - - // Read Address Channel. - .araddr (s_axi_araddr ), - .arprot (s_axi_arprot ), - .arvalid (s_axi_arvalid ), - .arready (s_axi_arready ), - - // Read Data Channel. - .rdata (s_axi_rdata ), - .rresp (s_axi_rresp ), - .rvalid (s_axi_rvalid ), - .rready (s_axi_rready ), - - // Registers. - .FREQ_REG (FREQ_REG ), - .PHASE_REG (PHASE_REG ), - .NSAMP_REG (NSAMP_REG ), - .OUTSEL_REG (OUTSEL_REG ), - .MODE_REG (MODE_REG ), - .WE_REG (WE_REG ) - ); - -// Readout Top. -readout_top readout_top_i - ( - // Reset and clock (s0_axis, s1_axis, m0_axis, m1_axis). - .aresetn (aresetn ), - .aclk (aclk ), - - // S_AXIS: for input data (8x samples per clock). - .s_axis_tdata (s_axis_tdata ), - .s_axis_tvalid (s_axis_tvalid ), - .s_axis_tready (s_axis_tready ), - - // M0_AXIS: for output data (before filter and decimation, 8x samples - // per clock). - .m0_axis_tready (m0_axis_tready ), - .m0_axis_tvalid (m0_axis_tvalid ), - .m0_axis_tdata (m0_axis_tdata ), - - // M1_AXIS: for output data. - .m1_axis_tready (m1_axis_tready ), - .m1_axis_tvalid (m1_axis_tvalid ), - .m1_axis_tdata (m1_axis_tdata ), - - // Registers. - .FREQ_REG (FREQ_REG ), - .PHASE_REG (PHASE_REG ), - .NSAMP_REG (NSAMP_REG ), - .OUTSEL_REG (OUTSEL_REG ), - .MODE_REG (MODE_REG ), - .WE_REG (WE_REG ) - ); - -endmodule - diff --git a/qick/firmware/ip/axis_readout_v2/src/ctrl.sv b/qick/firmware/ip/axis_readout_v2/src/ctrl.sv deleted file mode 100644 index a6932cf..0000000 --- a/qick/firmware/ip/axis_readout_v2/src/ctrl.sv +++ /dev/null @@ -1,318 +0,0 @@ -//Format of waveform interface: -// |------|----------|----------|----------|---------| -// | 82 | 81 .. 80 | 79 .. 64 | 63 .. 32 | 31 .. 0 | -// |------|----------|----------|----------|---------| -// | mode | outsel | nsamp | phase | freq | -// |------|----------|----------|----------|---------| -// freq : 32 bits -// phase : 32 bits -// nsamp : 16 bits -// outsel : 2 bits -// mode : 1 bit -// -// Fifo : 83 bits. -module ctrl ( - // Reset and clock. - rstn , - clk , - - // Fifo interface. - fifo_rd_en_o , - fifo_empty_i , - fifo_dout_i , - - // dds control. - dds_ctrl_o , - - // Output source selection. - outsel_o ); - -// Number of parallel dds blocks. -parameter [31:0] N_DDS = 16; - -// Ports. -input rstn; -input clk; -output fifo_rd_en_o; -input fifo_empty_i; -input [82:0] fifo_dout_i; -output [N_DDS*72-1:0] dds_ctrl_o; -output [1:0] outsel_o; - -// States. -typedef enum { READ_ST , - CNT_ST - } state_t; - -// State register. -(* fsm_encoding = "one_hot" *) state_t state; - -// Fifo dout register. -reg [82:0] fifo_dout_r; - -// Non-stop counter for time calculation (adds N_DDS samples each clock tick). -reg [31:0] cnt_n; -reg [31:0] cnt_n_reg; - -// Pinc/phase. -wire [31:0] pinc_int; -reg [31:0] pinc_r1; -reg [31:0] pinc_r2; -wire [31:0] pinc_N; -reg [31:0] pinc_N_r1; -reg [31:0] pinc_N_r2; -reg [31:0] pinc_N_r3; -reg [31:0] pinc_N_r4; -reg [31:0] pinc_N_r5; -wire [31:0] pinc_Nm; -reg [31:0] pinc_Nm_r1; -reg [31:0] pinc_Nm_r2; -reg [31:0] pinc_Nm_r3; - -wire [31:0] phase_int; -reg [31:0] phase_r1; -reg [31:0] phase_r2; -reg [31:0] phase_r3; -reg [31:0] phase_r4; -reg [31:0] phase_r5; -wire [31:0] phase_0; -reg [31:0] phase_0_r1; - -// Phase vectors. -wire [31:0] phase_v0 [0:N_DDS-1]; -reg [31:0] phase_v0_r1 [0:N_DDS-1]; -reg [31:0] phase_v0_r2 [0:N_DDS-1]; -reg [31:0] phase_v0_r3 [0:N_DDS-1]; -reg [31:0] phase_v0_r4 [0:N_DDS-1]; -wire [31:0] phase_v1 [0:N_DDS-1]; -reg [31:0] phase_v1_r1 [0:N_DDS-1]; - -// Number of samples. -wire [15:0] nsamp_int; - -// Output selection. -wire [1:0] outsel_int; -reg [1:0] outsel_r1; -reg [1:0] outsel_r2; -reg [1:0] outsel_r3; -reg [1:0] outsel_r4; -reg [1:0] outsel_r5; -reg [1:0] outsel_r6; -reg [1:0] outsel_r7; - -// Mode. -wire mode_int; - -// Load enable flag. -wire load_int; -reg load_r1; -reg load_r2; -reg load_r3; -reg load_r4; -reg load_r5; -reg load_r6; -reg load_r7; -reg load_r8; - -// Fifo Read Enable. -reg rd_en_int; - -// Counter. -reg [15:0] cnt; - -// Registers. -always @(posedge clk) begin - if (~rstn) begin - // State register. - state <= READ_ST; - - // Fifo dout register. - fifo_dout_r <= 0; - - // Non-stop counter for time calculation. - cnt_n <= 0; - cnt_n_reg <= 0; - - // Pinc/phase/sync. - pinc_r1 <= 0; - pinc_r2 <= 0; - pinc_N_r1 <= 0; - pinc_N_r2 <= 0; - pinc_N_r3 <= 0; - pinc_N_r4 <= 0; - pinc_N_r5 <= 0; - pinc_Nm_r1 <= 0; - pinc_Nm_r2 <= 0; - pinc_Nm_r3 <= 0; - - phase_r1 <= 0; - phase_r2 <= 0; - phase_r3 <= 0; - phase_r4 <= 0; - phase_r5 <= 0; - phase_0_r1 <= 0; - - // Output selection. - outsel_r1 <= 0; - outsel_r2 <= 0; - outsel_r3 <= 0; - outsel_r4 <= 0; - outsel_r5 <= 0; - outsel_r6 <= 0; - outsel_r7 <= 0; - - // Load enable flag. - load_r1 <= 0; - load_r2 <= 0; - load_r3 <= 0; - load_r4 <= 0; - load_r5 <= 0; - load_r6 <= 0; - load_r7 <= 0; - load_r8 <= 0; - - // Counter. - cnt <= 0; - end - else begin - // State register. - case (state) - READ_ST: - if (mode_int || ~fifo_empty_i) - state <= CNT_ST; - CNT_ST: - if ( cnt == nsamp_int-2 ) - state <= READ_ST; - endcase - - // Fifo dout register. - if (load_r1) - fifo_dout_r <= fifo_dout_i; - - // Non-stop counter for time calculation. - cnt_n <= cnt_n + N_DDS; - if (load_r2) - cnt_n_reg <= cnt_n; - - // Pinc/phase/sync. - pinc_r1 <= pinc_int; - pinc_r2 <= pinc_r1; - pinc_N_r1 <= pinc_N; - pinc_N_r2 <= pinc_N_r1; - pinc_N_r3 <= pinc_N_r2; - pinc_N_r4 <= pinc_N_r3; - pinc_N_r5 <= pinc_N_r4; - pinc_Nm_r1 <= pinc_Nm; - pinc_Nm_r2 <= pinc_Nm_r1; - pinc_Nm_r3 <= pinc_Nm_r2; - - phase_r1 <= phase_int; - phase_r2 <= phase_r1; - phase_r3 <= phase_r2; - phase_r4 <= phase_r3; - phase_r5 <= phase_r4; - phase_0_r1 <= phase_0; - - // Output selection. - outsel_r1 <= outsel_int; - outsel_r2 <= outsel_r1; - outsel_r3 <= outsel_r2; - outsel_r4 <= outsel_r3; - outsel_r5 <= outsel_r4; - outsel_r6 <= outsel_r5; - outsel_r7 <= outsel_r6; - - // Load enable flag. - load_r1 <= load_int; - load_r2 <= load_r1; - load_r3 <= load_r2; - load_r4 <= load_r3; - load_r5 <= load_r4; - load_r6 <= load_r5; - load_r7 <= load_r6; - load_r8 <= load_r7; - - // Counter. - if (rd_en_int) - cnt <= 0; - else - cnt <= cnt + 1; - end -end - -// FSM outputs. -always_comb begin - // Default. - rd_en_int = 0; - - case (state) - READ_ST: - rd_en_int = 1; - - CNT_ST: - rd_en_int = 0; - endcase -end - -// Fifo output fields. -assign pinc_int = fifo_dout_r[31:0]; -assign phase_int = fifo_dout_r[63:32]; -assign nsamp_int = fifo_dout_r[79:64]; -assign outsel_int = fifo_dout_r[81:80]; -assign mode_int = fifo_dout_r[82]; - -// Frequency calculation. -assign pinc_N = pinc_r2*N_DDS; - -// Phase calculation. -assign pinc_Nm = pinc_r2*cnt_n_reg; -assign phase_0 = pinc_Nm_r3 + phase_r5; - -// Phase vectors. -generate -genvar i; - for (i=0; i < N_DDS; i = i + 1) begin : GEN_phase - // Registers. - always @(posedge clk) begin - if (~rstn) begin - // v0. - phase_v0_r1[i] <= 0; - phase_v0_r2[i] <= 0; - phase_v0_r3[i] <= 0; - phase_v0_r4[i] <= 0; - - // v1. - phase_v1_r1[i] <= 0; - end - else begin - // v0. - phase_v0_r1[i] <= phase_v0[i]; - phase_v0_r2[i] <= phase_v0_r1[i]; - phase_v0_r3[i] <= phase_v0_r2[i]; - phase_v0_r4[i] <= phase_v0_r3[i]; - - // v1. - phase_v1_r1[i] <= phase_v1[i]; - end - end - - // v0. - assign phase_v0[i] = pinc_r2*i; - - // v1. - assign phase_v1[i] = phase_v0_r4[i] + phase_0_r1; - - // dds_ctrl_o output. - assign dds_ctrl_o[i*72 +: 72] = {7'h00,load_r8,phase_v1_r1[i],pinc_N_r5}; - end -endgenerate - -// load_int. -assign load_int = rd_en_int & ~fifo_empty_i; - -// Assign outputs. -assign fifo_rd_en_o = rd_en_int; -assign outsel_o = outsel_r7; - -endmodule - diff --git a/qick/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.veo b/qick/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.veo deleted file mode 100644 index 7bf3bc5..0000000 --- a/qick/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.veo +++ /dev/null @@ -1,69 +0,0 @@ -// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -// IP VLNV: xilinx.com:ip:dds_compiler:6.0 -// IP Revision: 20 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -dds_compiler_0 your_instance_name ( - .aclk(aclk), // input wire aclk - .s_axis_phase_tvalid(s_axis_phase_tvalid), // input wire s_axis_phase_tvalid - .s_axis_phase_tdata(s_axis_phase_tdata), // input wire [71 : 0] s_axis_phase_tdata - .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid - .m_axis_data_tdata(m_axis_data_tdata) // output wire [31 : 0] m_axis_data_tdata -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file dds_compiler_0.v when simulating -// the core, dds_compiler_0. When compiling the wrapper file, be sure to -// reference the Verilog simulation library. - diff --git a/qick/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.vho b/qick/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.vho deleted file mode 100644 index 8bdeb4a..0000000 --- a/qick/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.vho +++ /dev/null @@ -1,83 +0,0 @@ --- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:dds_compiler:6.0 --- IP Revision: 20 - --- The following code must appear in the VHDL architecture header. - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT dds_compiler_0 - PORT ( - aclk : IN STD_LOGIC; - s_axis_phase_tvalid : IN STD_LOGIC; - s_axis_phase_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0); - m_axis_data_tvalid : OUT STD_LOGIC; - m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) - ); -END COMPONENT; --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : dds_compiler_0 - PORT MAP ( - aclk => aclk, - s_axis_phase_tvalid => s_axis_phase_tvalid, - s_axis_phase_tdata => s_axis_phase_tdata, - m_axis_data_tvalid => m_axis_data_tvalid, - m_axis_data_tdata => m_axis_data_tdata - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file dds_compiler_0.vhd when simulating --- the core, dds_compiler_0. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/qick/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.xci b/qick/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.xci deleted file mode 100644 index 4b781ec..0000000 --- a/qick/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.xci +++ /dev/null @@ -1,318 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - dds_compiler_0 - - - - 100000000 - 0 - 0 - 0.000 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 9 - 0 - 0 - 0 - 32 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 1 - 0 - 1 - 0 - 1 - 0 - 0 - 8 - 1 - 0 - 9 - 0 - 32 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 2 - 0 - 16 - 14 - 3 - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - 3 - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - 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15 - 16 - - - choice_list_230272f2 - None - Fixed - Programmable - Streaming - - - choice_list_45db86b7 - Auto - Configurable - - - choice_list_4721e082 - Minimal - Maximal - - - choice_list_950bd3bd - Auto - Area - Speed - - - choice_list_ba6ede68 - Standard - Rasterized - - - choice_list_cd7e1d82 - Coregen - Sysgen - - - choice_list_de3e80a0 - Fixed - Programmable - Streaming - - - choice_list_faa329ca - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 16 - 17 - 18 - 19 - 20 - 21 - - - choice_pairs_0079eeec - Twos_Complement - Sign_and_Magnitude - - - choice_pairs_27d1d409 - Auto - Distributed_ROM - Block_ROM - - - choice_pairs_65a5252d - Full_Range - Unit_Circle - - - choice_pairs_6bdc34ae - System_Parameters - Hardware_Parameters - - - choice_pairs_75713637 - Packet_Framing - Not_Required - - - choice_pairs_8b9a47c2 - Auto - None - Phase_Dithering - Taylor_Series_Corrected - - - choice_pairs_944fe41d - Phase_Generator_and_SIN_COS_LUT - Phase_Generator_only - SIN_COS_LUT_only - - - choice_pairs_a54f933f - Sine - Cosine - Sine_and_Cosine - - - choice_pairs_d463c5cb - User_Field - Not_Required - - - choice_pairs_dac1efef - Not_Required - - - choice_pairs_f611af79 - On_Vector - On_Packet - - - - - xilinx_veriloginstantiationtemplate_view_fileset - - dds_compiler_0.vho - vhdlTemplate - - - dds_compiler_0.veo - verilogTemplate - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset - - hdl/xbip_utils_v3_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - xbip_utils_v3_0_10 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_utils_2_0__ref_view_fileset - - hdl/axi_utils_v2_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - axi_utils_v2_0_6 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_pipe_3_0__ref_view_fileset - - hdl/xbip_pipe_v3_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - xbip_pipe_v3_0_6 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset - - hdl/xbip_bram18k_v3_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - xbip_bram18k_v3_0_6 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_mult_gen_12_0__ref_view_fileset - - hdl/mult_gen_v12_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - mult_gen_v12_0_16 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_wrapper_3_0__ref_view_fileset - - hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - xbip_dsp48_wrapper_v3_0_4 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_addsub_3_0__ref_view_fileset - - hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - xbip_dsp48_addsub_v3_0_6 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_multadd_3_0__ref_view_fileset - - hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - xbip_dsp48_multadd_v3_0_6 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_view_fileset - - hdl/dds_compiler_v6_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - dds_compiler_v6_0_20 - - - - xilinx_vhdlsimulationwrapper_view_fileset - - sim/dds_compiler_0.vhd - vhdlSource - xil_defaultlib - - - - The Xilinx DDS Compiler LogiCORE provides Direct Digital Synthesizers (DDS) and optionally either Phase Generator or Sine/Cosine Lookup Table constituent parts as independent cores. The core features sine, cosine or quadrature outputs with 3 to 26-bit output sample precision. The core supports up to 16 channels by time-sharing the sine/cosine table which dramatically reduces the area requirement when multiple channels are needed. Phase Dithering and Taylor Series Correction options provide high dynamic range signals using minimal FPGA resources. In addition, the core has an optional phase offset capability, providing support for multiple synthesizers with precisely controlled phase differences. - - - Component_Name - Component Name - dds_compiler_0 - - - PartsPresent - Configuration Options - Phase_Generator_and_SIN_COS_LUT - - - DDS_Clock_Rate - System Clock - 256 - - - Channels - Number of Channels - 1 - - - Mode_of_Operation - Mode Of Operation - Standard - - - Modulus - Modulus - 9 - - - Parameter_Entry - Parameter Selection - System_Parameters - - - Spurious_Free_Dynamic_Range - Spurious Free Dynamic Range - 96 - - - Frequency_Resolution - Frequency Resolution - 0.06 - - - Noise_Shaping - Noise Shaping - Auto - - - Phase_Width - Phase Width - 32 - - - Output_Width - Output Width - 16 - - - Phase_Increment - Phase Increment - Streaming - - - Resync - Resync - true - - - Phase_offset - Phase Offset - Streaming - - - Output_Selection - Output Selection - Sine_and_Cosine - - - Negative_Sine - Negative Sine - false - - - Negative_Cosine - Negative Cosine - false - - - Amplitude_Mode - Amplitude Mode - Full_Range - - - Memory_Type - Memory Type - Auto - - - Optimization_Goal - Optimization Goal - Speed - - - DSP48_Use - DSP48 Use - Maximal - - - Has_Phase_Out - Has Phase Out - false - - - DATA_Has_TLAST - DATA Has TLAST - Not_Required - - - Has_TREADY - Output TREADY - false - - - S_PHASE_Has_TUSER - Input - Not_Required - - - S_PHASE_TUSER_Width - User Field Width - 1 - - - M_DATA_Has_TUSER - DATA Output - Not_Required - - - M_PHASE_Has_TUSER - PHASE Output - Not_Required - - - S_CONFIG_Sync_Mode - Synchronization Mode - On_Vector - - - OUTPUT_FORM - Output Form - Twos_Complement - - - Latency_Configuration - Configurable - - - Latency - 8 - - - Has_ARESETn - ARESETn (active low) - false - - - Has_ACLKEN - ACLKEN - false - - - Output_Frequency1 - 0 - - - PINC1 - 0 - - - Phase_Offset_Angles1 - 0 - - - POFF1 - 0 - - - Output_Frequency2 - 0 - - - PINC2 - 0 - - - Phase_Offset_Angles2 - 0 - - - POFF2 - 0 - - - Output_Frequency3 - 0 - - - PINC3 - 0 - - - Phase_Offset_Angles3 - 0 - - - POFF3 - 0 - - - Output_Frequency4 - 0 - - - PINC4 - 0 - - - Phase_Offset_Angles4 - 0 - - - POFF4 - 0 - - - Output_Frequency5 - 0 - - - PINC5 - 0 - - - Phase_Offset_Angles5 - 0 - - - POFF5 - 0 - - - Output_Frequency6 - 0 - - - PINC6 - 0 - - - Phase_Offset_Angles6 - 0 - - - POFF6 - 0 - - - Output_Frequency7 - 0 - - - PINC7 - 0 - - - Phase_Offset_Angles7 - 0 - - - POFF7 - 0 - - - Output_Frequency8 - 0 - - - PINC8 - 0 - - - Phase_Offset_Angles8 - 0 - - - POFF8 - 0 - - - Output_Frequency9 - 0 - - - PINC9 - 0 - - - Phase_Offset_Angles9 - 0 - - - POFF9 - 0 - - - Output_Frequency10 - 0 - - - PINC10 - 0 - - - Phase_Offset_Angles10 - 0 - - - POFF10 - 0 - - - Output_Frequency11 - 0 - - - PINC11 - 0 - - - Phase_Offset_Angles11 - 0 - - - POFF11 - 0 - - - Output_Frequency12 - 0 - - - PINC12 - 0 - - - Phase_Offset_Angles12 - 0 - - - POFF12 - 0 - - - Output_Frequency13 - 0 - - - PINC13 - 0 - - - Phase_Offset_Angles13 - 0 - - - POFF13 - 0 - - - Output_Frequency14 - 0 - - - PINC14 - 0 - - - Phase_Offset_Angles14 - 0 - - - POFF14 - 0 - - - Output_Frequency15 - 0 - - - PINC15 - 0 - - - Phase_Offset_Angles15 - 0 - - - POFF15 - 0 - - - Output_Frequency16 - 0 - - - PINC16 - 0 - - - Phase_Offset_Angles16 - 0 - - - POFF16 - 0 - - - POR_mode - POR Mode - false - - - GUI_Behaviour - Coregen - - - explicit_period - false - - - period - 1 - - - - - DDS Compiler - 20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2020.2 - - - - - - - - diff --git a/qick/firmware/ip/axis_readout_v2/src/down_conversion.v b/qick/firmware/ip/axis_readout_v2/src/down_conversion.v deleted file mode 100644 index ae8bd04..0000000 --- a/qick/firmware/ip/axis_readout_v2/src/down_conversion.v +++ /dev/null @@ -1,229 +0,0 @@ -module down_conversion ( - // Reset and clock. - rstn , - clk , - - // S_AXIS for input. - s_axis_tready_o , - s_axis_tvalid_i , - s_axis_tdata_i , - - // M_AXIS for output. - m_axis_tready_i , - m_axis_tvalid_o , - m_axis_tdata_o , - - // Fifo interface. - fifo_rd_en_o , - fifo_empty_i , - fifo_dout_i - ); - -/**************/ -/* Parameters */ -/**************/ -// Number of parallel dds blocks. -parameter [15:0] N_DDS = 16; - -// 0.5 for rounding. -localparam [31:0] RND_0P5 = 2**15; - -/*********/ -/* Ports */ -/*********/ -input rstn; -input clk; - -output s_axis_tready_o; -input s_axis_tvalid_i; -input [N_DDS*16-1:0] s_axis_tdata_i; - -input m_axis_tready_i; -output m_axis_tvalid_o; -output [N_DDS*32-1:0] m_axis_tdata_o; - -output fifo_rd_en_o; -input fifo_empty_i; -input [82:0] fifo_dout_i; - -/********************/ -/* Internal signals */ -/********************/ -// DDS input control. -reg dds_tvalid_r; -wire [N_DDS*72-1:0] dds_ctrl_int; -reg [N_DDS*72-1:0] dds_ctrl_int_r; - -// Output selection. -wire [1:0] outsel_int; - -// DDS output. -wire [31:0] dds_dout [0:N_DDS-1]; -reg [31:0] dds_dout_r1 [0:N_DDS-1]; -reg [31:0] dds_dout_r2 [0:N_DDS-1]; -reg [31:0] dds_dout_r3 [0:N_DDS-1]; -reg [31:0] dds_dout_r4 [0:N_DDS-1]; - -// Input data. -reg [15:0] din_r1 [0:N_DDS-1]; -reg signed [15:0] din_r2 [0:N_DDS-1]; -reg [15:0] din_r3 [0:N_DDS-1]; -reg [15:0] din_r4 [0:N_DDS-1]; - -// Product. -wire signed [15:0] pa_real [0:N_DDS-1]; -wire signed [15:0] pa_imag [0:N_DDS-1]; -wire signed [31:0] py_full_real [0:N_DDS-1]; -wire signed [31:0] py_full_imag [0:N_DDS-1]; -reg signed [31:0] py_full_real_r [0:N_DDS-1]; -reg signed [31:0] py_full_imag_r [0:N_DDS-1]; -wire signed [31:0] py_round_real [0:N_DDS-1]; -wire signed [31:0] py_round_imag [0:N_DDS-1]; -wire [15:0] py_real [0:N_DDS-1]; -wire [15:0] py_imag [0:N_DDS-1]; -wire [31:0] py [0:N_DDS-1]; -reg [31:0] py_r [0:N_DDS-1]; - -// Muxed output. -wire [31:0] dout_mux [0:N_DDS-1]; -reg [31:0] dout_mux_r [0:N_DDS-1]; - -/**********************/ -/* Begin Architecture */ -/**********************/ -// Control block. -ctrl - #( - .N_DDS (N_DDS ) - ) - ctrl_i - ( - // Reset and clock. - .rstn (rstn ), - .clk (clk ), - - // Fifo interface. - .fifo_rd_en_o (fifo_rd_en_o ), - .fifo_empty_i (fifo_empty_i ), - .fifo_dout_i (fifo_dout_i ), - - // dds control. - .dds_ctrl_o (dds_ctrl_int ), - - // Output source selection. - .outsel_o (outsel_int ) - ); - -generate -genvar i; - for (i=0; i N_LOG2, - -- Data width. - B => B - ) - Port map ( - clk => clk , - ena => '1' , - enb => rd_en , - wea => mem_wea , - addra => std_logic_vector(wptr) , - addrb => std_logic_vector(rptr) , - dia => din , - dob => mem_dob - ); - --- Memory connections. -mem_wea <= wr_en when full_i = '0' else - '0'; - --- Full/empty signals. -full_i <= '1' when wptr = rptr - 1 else - '0'; -empty_i <= '1' when wptr = rptr else - '0'; - --- wr_clk registers. -process (clk) -begin - if ( rising_edge(clk) ) then - if ( rstn = '0' ) then - wptr <= (others => '0'); - rptr <= (others => '0'); - else - -- Write. - if ( wr_en = '1' and full_i = '0' ) then - -- Write data. - - -- Increment pointer. - wptr <= wptr + 1; - end if; - - -- Read. - if ( rd_en = '1' and empty_i = '0' ) then - -- Read data. - - -- Increment pointer. - rptr <= rptr + 1; - end if; - end if; - end if; -end process; - --- Assign outputs. -dout <= mem_dob; -full <= full_i; -empty <= empty_i; - -end rtl; - diff --git a/qick/firmware/ip/axis_readout_v2/src/fifo/fifo_axi.vhd b/qick/firmware/ip/axis_readout_v2/src/fifo/fifo_axi.vhd deleted file mode 100644 index e1f76f7..0000000 --- a/qick/firmware/ip/axis_readout_v2/src/fifo/fifo_axi.vhd +++ /dev/null @@ -1,147 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo_axi is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo_axi; - -architecture rtl of fifo_axi is - --- FIFO. -component fifo is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end component; - --- FIFO read to AXI adapter. -component rd2axi is - Generic - ( - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- FIFO Read I/F. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (B-1 downto 0); - fifo_empty : in std_logic; - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - empty : out std_logic - ); -end component; - -signal rd_en_i : std_logic; -signal dout_i : std_logic_vector (B-1 downto 0); -signal empty_i : std_logic; - -begin - --- FIFO. -fifo_i : fifo - Generic map - ( - -- Data width. - B => B, - - -- Fifo depth. - N => N - ) - Port map - ( - rstn => rstn , - clk => clk , - - -- Write I/F. - wr_en => wr_en , - din => din , - - -- Read I/F. - rd_en => rd_en_i , - dout => dout_i , - - -- Flags. - full => full , - empty => empty_i - ); - --- FIFO read to AXI adapter. -rd2axi_i : rd2axi - Generic map - ( - -- Data width. - B => B - ) - Port map - ( - rstn => rstn , - clk => clk , - - -- FIFO Read I/F. - fifo_rd_en => rd_en_i , - fifo_dout => dout_i , - fifo_empty => empty_i , - - -- Read I/F. - rd_en => rd_en , - dout => dout , - empty => empty - ); - -end rtl; - diff --git a/qick/firmware/ip/axis_readout_v2/src/fifo/fifo_dc.vhd b/qick/firmware/ip/axis_readout_v2/src/fifo/fifo_dc.vhd deleted file mode 100644 index c214fae..0000000 --- a/qick/firmware/ip/axis_readout_v2/src/fifo/fifo_dc.vhd +++ /dev/null @@ -1,291 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo_dc is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - wr_rstn : in std_logic; - wr_clk : in std_logic; - - rd_rstn : in std_logic; - rd_clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo_dc; - -architecture rtl of fifo_dc is - --- Number of bits of depth. -constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); - --- Binary to gray converter. -component bin2gray is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end component; - --- Gray to binary converter. -component gray2bin is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end component; - --- Vector synchronizer (only for gray coded). -component synchronizer_vect is - generic ( - -- Sync stages. - N : Integer := 2; - - -- Data width. - B : Integer := 8 - ); - port ( - rstn : in std_logic; - clk : in std_logic; - data_in : in std_logic_vector (B-1 downto 0); - data_out : out std_logic_vector (B-1 downto 0) - ); -end component; - --- Dual port BRAM. -component bram_dp is - Generic ( - -- Memory address size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - ena : in STD_LOGIC; - enb : in STD_LOGIC; - wea : in STD_LOGIC; - web : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR (N-1 downto 0); - addrb : in STD_LOGIC_VECTOR (N-1 downto 0); - dia : in STD_LOGIC_VECTOR (B-1 downto 0); - dib : in STD_LOGIC_VECTOR (B-1 downto 0); - doa : out STD_LOGIC_VECTOR (B-1 downto 0); - dob : out STD_LOGIC_VECTOR (B-1 downto 0) - ); -end component; - --- Pointers. -signal wptr : unsigned (N_LOG2-1 downto 0); -signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); -signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); -signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); -signal rptr : unsigned (N_LOG2-1 downto 0); -signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); -signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); -signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); - --- Memory signals. -signal mem_wea : std_logic; -signal mem_dib : std_logic_vector (B-1 downto 0); -signal mem_doa : std_logic_vector (B-1 downto 0); -signal mem_dob : std_logic_vector (B-1 downto 0); - --- Flags. -signal full_i : std_logic; -signal empty_i : std_logic; - -begin - --- wptr_i: binary to gray. -wptr_i : bin2gray - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => std_logic_vector(wptr), - dout => wptr_g - ); - --- wptr_g: write to read domain. -wptr_g_i : synchronizer_vect - generic map ( - -- Sync stages. - N => 2, - - -- Data width. - B => N_LOG2 - ) - port map ( - rstn => rd_rstn, - clk => rd_clk, - data_in => wptr_g, - data_out => wptr_gc - ); - --- wptr_gc_i -wptr_gc_i : gray2bin - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => wptr_gc, - dout => wptr_c - ); - --- rptr_i: binary to gray. -rptr_i : bin2gray - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => std_logic_vector(rptr), - dout => rptr_g - ); - --- rptr_g: read to write domain. -rptr_g_i : synchronizer_vect - generic map ( - -- Sync stages. - N => 2, - - -- Data width. - B => N_LOG2 - ) - port map ( - rstn => wr_rstn, - clk => wr_clk, - data_in => rptr_g, - data_out => rptr_gc - ); - --- rptr_gc_i -rptr_gc_i : gray2bin - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => rptr_gc, - dout => rptr_c - ); - --- FIFO memory. -mem_i : bram_dp - Generic map ( - -- Memory address size. - N => N_LOG2, - -- Data width. - B => B - ) - Port map ( - clka => wr_clk, - clkb => rd_clk, - ena => '1', - enb => rd_en, - wea => mem_wea, - web => '0', - addra => std_logic_vector(wptr), - addrb => std_logic_vector(rptr), - dia => din, - dib => mem_dib, - doa => mem_doa, - dob => mem_dob - ); --- Memory connections. -mem_wea <= wr_en when full_i = '0' else - '0'; -mem_dib <= (others => '0'); - --- Full/empty signals. -full_i <= '1' when wptr = unsigned(rptr_c) - 1 else - '0'; -empty_i <= '1' when unsigned(wptr_c) = rptr else - '0'; - --- wr_clk registers. -process (wr_clk) -begin - if ( rising_edge(wr_clk) ) then - if ( wr_rstn = '0' ) then - wptr <= (others => '0'); - else - -- Write. - if ( wr_en = '1' and full_i = '0' ) then - -- Write data. - - -- Increment pointer. - wptr <= wptr + 1; - end if; - end if; - end if; -end process; - --- rd_clk registers. -process (rd_clk) -begin - if ( rising_edge(rd_clk) ) then - if ( rd_rstn = '0' ) then - rptr <= (others => '0'); - else - -- Read. - if ( rd_en = '1' and empty_i = '0' ) then - -- Read data. - - -- Increment pointer. - rptr <= rptr + 1; - end if; - end if; - end if; -end process; - --- Assign outputs. -dout <= mem_dob; -full <= full_i; -empty <= empty_i; - -end rtl; diff --git a/qick/firmware/ip/axis_readout_v2/src/fifo/fifo_dc_axi.vhd b/qick/firmware/ip/axis_readout_v2/src/fifo/fifo_dc_axi.vhd deleted file mode 100644 index eb83d1a..0000000 --- a/qick/firmware/ip/axis_readout_v2/src/fifo/fifo_dc_axi.vhd +++ /dev/null @@ -1,156 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo_dc_axi is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - wr_rstn : in std_logic; - wr_clk : in std_logic; - - rd_rstn : in std_logic; - rd_clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo_dc_axi; - -architecture rtl of fifo_dc_axi is - --- Dual-clock FIFO. -component fifo_dc is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - wr_rstn : in std_logic; - wr_clk : in std_logic; - - rd_rstn : in std_logic; - rd_clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end component; - --- FIFO read to AXI adapter. -component rd2axi is - Generic - ( - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- FIFO Read I/F. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (B-1 downto 0); - fifo_empty : in std_logic; - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - empty : out std_logic - ); -end component; - -signal rd_en_i : std_logic; -signal dout_i : std_logic_vector (B-1 downto 0); -signal empty_i : std_logic; - -begin - --- Dual-clock FIFO. -fifo_i : fifo_dc - Generic map - ( - -- Data width. - B => B, - - -- Fifo depth. - N => N - ) - Port map - ( - wr_rstn => wr_rstn , - wr_clk => wr_clk , - - rd_rstn => rd_rstn , - rd_clk => rd_clk , - - -- Write I/F. - wr_en => wr_en , - din => din , - - -- Read I/F. - rd_en => rd_en_i , - dout => dout_i , - - -- Flags. - full => full , - empty => empty_i - ); - --- FIFO read to AXI adapter. -rd2axi_i : rd2axi - Generic map - ( - -- Data width. - B => B - ) - Port map - ( - rstn => rd_rstn , - clk => rd_clk , - - -- FIFO Read I/F. - fifo_rd_en => rd_en_i , - fifo_dout => dout_i , - fifo_empty => empty_i , - - -- Read I/F. - rd_en => rd_en , - dout => dout , - empty => empty - ); - -end rtl; - diff --git a/qick/firmware/ip/axis_readout_v2/src/fifo/gray2bin.vhd b/qick/firmware/ip/axis_readout_v2/src/fifo/gray2bin.vhd deleted file mode 100644 index e23f8af..0000000 --- a/qick/firmware/ip/axis_readout_v2/src/fifo/gray2bin.vhd +++ /dev/null @@ -1,37 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity gray2bin is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end gray2bin; - -architecture rtl of gray2bin is - -signal bin : std_logic_vector (B-1 downto 0); - -begin - --- MSB always match. -bin(B-1) <= din(B-1); - -GEN: for I in 0 to B-2 generate -begin - bin(I) <= bin(I+1) xor din(I); -end generate GEN; - --- Assign output. -dout <= bin; - -end rtl; - diff --git a/qick/firmware/ip/axis_readout_v2/src/fifo/rd2axi.vhd b/qick/firmware/ip/axis_readout_v2/src/fifo/rd2axi.vhd deleted file mode 100644 index babadc6..0000000 --- a/qick/firmware/ip/axis_readout_v2/src/fifo/rd2axi.vhd +++ /dev/null @@ -1,138 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity rd2axi is - Generic - ( - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- FIFO Read I/F. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (B-1 downto 0); - fifo_empty : in std_logic; - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - empty : out std_logic - ); -end rd2axi; - -architecture rtl of rd2axi is - -type fsm_state is ( WAIT_EMPTY_ST, - READ_FIRST_ST, - READ_ST, - READ_LAST_ST); -signal current_state, next_state : fsm_state; - -signal wait_empty_state : std_logic; -signal read_first_state : std_logic; -signal read_state : std_logic; - -signal fifo_rd_en_i : std_logic; -signal empty_i : std_logic; - -begin - -process(clk) -begin - if (rising_edge(clk)) then - if (rstn = '0') then - current_state <= WAIT_EMPTY_ST; - else - current_state <= next_state; - end if; - end if; -end process; - --- Next state logic. -process(current_state, fifo_empty, rd_en) -begin - case current_state is - when WAIT_EMPTY_ST => - if (fifo_empty = '1') then - next_state <= WAIT_EMPTY_ST; - else - next_state <= READ_FIRST_ST; - end if; - - when READ_FIRST_ST => - next_state <= READ_ST; - - when READ_ST => - if (fifo_empty = '0') then - next_state <= READ_ST; - else - if (rd_en = '1') then - next_state <= WAIT_EMPTY_ST; - else - next_state <= READ_LAST_ST; - end if; - end if; - - when READ_LAST_ST => - if (rd_en = '0') then - next_state <= READ_LAST_ST; - else - next_state <= WAIT_EMPTY_ST; - end if; - - end case; -end process; - --- Output logic. -process(current_state) -begin -wait_empty_state <= '0'; -read_first_state <= '0'; -read_state <= '0'; -empty_i <= '0'; - case current_state is - when WAIT_EMPTY_ST => - wait_empty_state <= '1'; - read_first_state <= '0'; - read_state <= '0'; - empty_i <= '1'; - - when READ_FIRST_ST => - wait_empty_state <= '0'; - read_first_state <= '1'; - read_state <= '0'; - empty_i <= '1'; - - when READ_ST => - wait_empty_state <= '0'; - read_first_state <= '0'; - read_state <= '1'; - empty_i <= '0'; - - when READ_LAST_ST => - wait_empty_state <= '0'; - read_first_state <= '0'; - read_state <= '0'; - empty_i <= '0'; - - end case; -end process; - --- FIFO Read enable signal. -fifo_rd_en_i <= read_first_state or (read_state and rd_en); - --- Assign outputs. -fifo_rd_en <= fifo_rd_en_i; --- TODO: add register to freeze last value. -dout <= fifo_dout when empty_i = '0' else - (others => '0'); -empty <= empty_i; - -end rtl; - diff --git a/qick/firmware/ip/axis_readout_v2/src/fifo/synchronizer_vect.vhd b/qick/firmware/ip/axis_readout_v2/src/fifo/synchronizer_vect.vhd deleted file mode 100644 index 2fbb696..0000000 --- a/qick/firmware/ip/axis_readout_v2/src/fifo/synchronizer_vect.vhd +++ /dev/null @@ -1,49 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - --- This block is intended to use to sync gray coded vectors. - --- NOTE: Do not use with generic vector data, as it may result --- in corrupted re-sync data. - -entity synchronizer_vect is - generic ( - -- Sync stages. - N : Integer := 2; - - -- Data width. - B : Integer := 8 - ); - port ( - rstn : in std_logic; - clk : in std_logic; - data_in : in std_logic_vector (B-1 downto 0); - data_out : out std_logic_vector (B-1 downto 0) - ); -end synchronizer_vect; - -architecture rtl of synchronizer_vect is - --- Internal register. -type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); -signal data_int_reg : reg_t; - -begin - -process(clk) -begin - if (rising_edge(clk)) then - if (rstn = '0') then - data_int_reg <= (others => (others => '0')); -- 1 FF. - else - data_int_reg <= data_int_reg(N-2 downto 0) & data_in; - end if; - end if; -end process; - --- Assign output. -data_out <= data_int_reg(N-1); - -end rtl; - diff --git a/qick/firmware/ip/axis_readout_v2/src/fir.coe b/qick/firmware/ip/axis_readout_v2/src/fir.coe deleted file mode 100644 index 458482d..0000000 --- a/qick/firmware/ip/axis_readout_v2/src/fir.coe +++ /dev/null @@ -1,2 +0,0 @@ -Radix = 10; -CoefData = -56,-4,13,47,97,166,252,353,463,573,674,754,801,804,753,643,473,249,-20,-314,-611,-885,-1107,-1248,-1285,-1201,-989,-651,-206,318,878,1425,1903,2254,2428,2383,2094,1556,786,-172,-1251,-2364,-3408,-4271,-4839,-5010,-4696,-3838,-2410,-422,2076,4993,8205,11560,14889,18012,20758,22971,24523,25322,25322,24523,22971,20758,18012,14889,11560,8205,4993,2076,-422,-2410,-3838,-4696,-5010,-4839,-4271,-3408,-2364,-1251,-172,786,1556,2094,2383,2428,2254,1903,1425,878,318,-206,-651,-989,-1201,-1285,-1248,-1107,-885,-611,-314,-20,249,473,643,753,804,801,754,674,573,463,353,252,166,97,47,13,-4,-56 \ No newline at end of file diff --git a/qick/firmware/ip/axis_readout_v2/src/fir_compiler_0.v b/qick/firmware/ip/axis_readout_v2/src/fir_compiler_0.v deleted file mode 100644 index aab1311..0000000 --- a/qick/firmware/ip/axis_readout_v2/src/fir_compiler_0.v +++ /dev/null @@ -1,15 +0,0 @@ -module fir_compiler_0 - ( - input aclk , - input s_axis_data_tvalid , - output s_axis_data_tready , - input [255:0] s_axis_data_tdata , - output m_axis_data_tvalid , - output [31:0] m_axis_data_tdata -); - -assign s_axis_data_tready = 1'b1; -assign m_axis_data_tvalid = s_axis_data_tvalid; -assign m_axis_data_tdata = s_axis_data_tdata[31:0]; - -endmodule diff --git a/qick/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.veo b/qick/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.veo deleted file mode 100644 index e66a3e8..0000000 --- a/qick/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.veo +++ /dev/null @@ -1,70 +0,0 @@ -// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -// IP VLNV: xilinx.com:ip:fir_compiler:7.2 -// IP Revision: 15 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -fir_compiler_0 your_instance_name ( - .aclk(aclk), // input wire aclk - .s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid - .s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready - .s_axis_data_tdata(s_axis_data_tdata), // input wire [255 : 0] s_axis_data_tdata - .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid - .m_axis_data_tdata(m_axis_data_tdata) // output wire [31 : 0] m_axis_data_tdata -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file fir_compiler_0.v when simulating -// the core, fir_compiler_0. When compiling the wrapper file, be sure to -// reference the Verilog simulation library. - diff --git a/qick/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.vho b/qick/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.vho deleted file mode 100644 index a877167..0000000 --- a/qick/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.vho +++ /dev/null @@ -1,85 +0,0 @@ --- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:fir_compiler:7.2 --- IP Revision: 15 - --- The following code must appear in the VHDL architecture header. - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT fir_compiler_0 - PORT ( - aclk : IN STD_LOGIC; - s_axis_data_tvalid : IN STD_LOGIC; - s_axis_data_tready : OUT STD_LOGIC; - s_axis_data_tdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0); - m_axis_data_tvalid : OUT STD_LOGIC; - m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) - ); -END COMPONENT; --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : fir_compiler_0 - PORT MAP ( - aclk => aclk, - s_axis_data_tvalid => s_axis_data_tvalid, - s_axis_data_tready => s_axis_data_tready, - s_axis_data_tdata => s_axis_data_tdata, - m_axis_data_tvalid => m_axis_data_tvalid, - m_axis_data_tdata => m_axis_data_tdata - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file fir_compiler_0.vhd when simulating --- the core, fir_compiler_0. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/qick/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.xci b/qick/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.xci deleted file mode 100644 index 77b68ac..0000000 --- a/qick/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.xci +++ /dev/null @@ -1,321 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - fir_compiler_0 - - - - 100000000 - 0 - 0 - 0.000 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 1 - 0 - 0 - undef - 0.000 - 32 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - 35,35 - 35,35,35,35,35,35,35,35,35,35,35,35,35,35,35,35 - fixed - fir_compiler_0.mif - 60 - 2 - 0 - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16 - 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Basic - Advanced - - - choice_list_3f660234 - All - - - choice_list_5e9d103c - Signed - - - choice_list_8506c89f - Signed - Unsigned - - - choice_list_a63914d2 - Area - Speed - Custom - - - choice_list_dd381b21 - Automatic - Block - Distributed - - - choice_pairs_18e22ec6 - Full_Precision - Truncate_LSBs - Non_Symmetric_Rounding_Down - Non_Symmetric_Rounding_Up - Symmetric_Rounding_to_Zero - Symmetric_Rounding_to_Infinity - Convergent_Rounding_to_Even - Convergent_Rounding_to_Odd - - - choice_pairs_2074757d - None - All - Data_Path_Fanout - Pre-Adder_Pipeline - Coefficient_Fanout - Control_Path_Fanout - Control_Column_Fanout - Control_Broadcast_Fanout - Control_LUT_Pipeline - No_BRAM_Read_First_Mode - Optimal_Column_Lengths - Data_Path_Broadcast - Disable_Half_Band_Centre_Tap - No_SRL_Attributes - Other - - - choice_pairs_2b265cc8 - Frequency_Specification - Input_Sample_Period - Output_Sample_Period - - - choice_pairs_3ab545a3 - Not_Required - Chan_ID_Field - - - choice_pairs_480f8ce0 - Not_Required - Packet_Framing - - - choice_pairs_541959c1 - Inferred - Non_Symmetric - Symmetric - - - choice_pairs_74144f21 - COE_File - Vector - - - choice_pairs_789dfe7d - Single_Rate - Interpolation - Decimation - Hilbert - Interpolated - - - choice_pairs_8e2d2e35 - Not_Required - User_Field - - - choice_pairs_ab4ea833 - Systolic_Multiply_Accumulate - - - choice_pairs_b6c64168 - Single - By_Channel - - - choice_pairs_eb2746f0 - Integer - Fixed_Fractional - - - choice_pairs_f611af79 - On_Vector - On_Packet - - - choice_pairs_fd92e388 - Integer_Coefficients - Quantize_Only - Maximize_Dynamic_Range - - - - - xilinx_veriloginstantiationtemplate_view_fileset - - fir_compiler_0.vho - vhdlTemplate - - - fir_compiler_0.veo - verilogTemplate - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset - - hdl/xbip_utils_v3_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - xbip_utils_v3_0_10 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_utils_2_0__ref_view_fileset - - hdl/axi_utils_v2_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - axi_utils_v2_0_6 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_view_fileset - - constraints/fir_compiler_v7_2.xdc - xdc - fir_compiler_v7_2_15 - - - fir_compiler_0.mif - mif - - - hdl/fir_compiler_v7_2_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - fir_compiler_v7_2_15 - - - - xilinx_vhdlsimulationwrapper_view_fileset - - sim/fir_compiler_0.vhd - vhdlSource - xil_defaultlib - - - - The Xilinx FIR Compiler LogiCORE is a module for generation of high speed, compact filter implementations that can be configured to implement many different filtering functions. The core is fully synchronous, using a single clock, and is highly parameterizable, allowing designers to control the filter type, data and coefficient widths, the number of filter taps, the number of channels, etc. Multi-rate operation is supported. The core is delivered through the Xilinx Vivado IP Catalog and integrates seamlessly with the Xilinx design flow. - - - Component_Name - fir_compiler_0 - - - GUI_Behaviour - Coregen - - - CoefficientSource - COE_File - - - CoefficientVector - 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 - - - Coefficient_File - ../fir.coe - - - Coefficient_Sets - 1 - - - Coefficient_Reload - false - - - Filter_Type - Decimation - - - Rate_Change_Type - Integer - - - Interpolation_Rate - 1 - - - Decimation_Rate - 8 - - - Zero_Pack_Factor - 1 - - - Channel_Sequence - Basic - - - Number_Channels - 1 - - - Select_Pattern - All - - - Pattern_List - P4-0,P4-1,P4-2,P4-3,P4-4 - - - Number_Paths - 2 - - - RateSpecification - Output_Sample_Period - - - HardwareOversamplingRate - 1 - - - SamplePeriod - 1 - - - Sample_Frequency - 0.001 - - - Clock_Frequency - 300.0 - - - Coefficient_Sign - Signed - - - Quantization - Integer_Coefficients - - - Coefficient_Width - 16 - - - BestPrecision - false - - - Coefficient_Fractional_Bits - 0 - - - Coefficient_Structure - Inferred - - - Data_Sign - Signed - - - Data_Width - 16 - - - Data_Fractional_Bits - 0 - - - Output_Rounding_Mode - Symmetric_Rounding_to_Zero - - - Output_Width - 16 - - - Filter_Architecture - Systolic_Multiply_Accumulate - - - Optimization_Goal - Area - - - Optimization_Selection - None - - - Data_Path_Fanout - false - - - Pre_Adder_Pipeline - false - - - Coefficient_Fanout - false - - - Control_Path_Fanout - false - - - Control_Column_Fanout - false - - - Control_Broadcast_Fanout - false - - - Control_LUT_Pipeline - false - - - No_BRAM_Read_First_Mode - false - - - Optimal_Column_Lengths - false - - - Data_Path_Broadcast - false - - - Disable_Half_Band_Centre_Tap - false - - - No_SRL_Attributes - false - - - Other - false - - - Optimization_List - None - - - Data_Buffer_Type - Automatic - - - Coefficient_Buffer_Type - Automatic - - - Input_Buffer_Type - Automatic - - - Output_Buffer_Type - Automatic - - - Preference_For_Other_Storage - Automatic - - - Multi_Column_Support - Automatic - - - Inter_Column_Pipe_Length - 4 - - - ColumnConfig - 60 - - - DATA_Has_TLAST - Not_Required - - - M_DATA_Has_TREADY - false - - - S_DATA_Has_FIFO - false - - - S_DATA_Has_TUSER - Not_Required - - - M_DATA_Has_TUSER - Not_Required - - - DATA_TUSER_Width - 1 - - - S_CONFIG_Sync_Mode - On_Vector - - - S_CONFIG_Method - Single - - - Num_Reload_Slots - 1 - - - Has_ACLKEN - false - - - Has_ARESETn - false - - - Reset_Data_Vector - true - - - Blank_Output - false - - - Gen_MIF_from_Spec - false - - - Gen_MIF_from_COE - false - - - Reload_File - no_coe_file_loaded - - - Gen_MIF_Files - false - - - DisplayReloadOrder - false - - - Passband_Min - 0.0 - - - Passband_Max - 0.5 - - - Stopband_Min - 0.5 - - - Stopband_Max - 1.0 - - - Filter_Selection - 1 - - - - - FIR Compiler - 15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2020.2 - - - - - - - - diff --git a/qick/firmware/ip/axis_readout_v2/src/readout_top.v b/qick/firmware/ip/axis_readout_v2/src/readout_top.v deleted file mode 100644 index a9fc32e..0000000 --- a/qick/firmware/ip/axis_readout_v2/src/readout_top.v +++ /dev/null @@ -1,158 +0,0 @@ -module readout_top - ( - // Reset and clock. - aresetn , - aclk , - - // S1_AXIS: for input data (8x samples per clock). - s_axis_tdata , - s_axis_tvalid , - s_axis_tready , - - // M0_AXIS: for output data (before filter and decimation, 8x samples - // per clock). - m0_axis_tready , - m0_axis_tvalid , - m0_axis_tdata , - - // M1_AXIS: for output data. - m1_axis_tready , - m1_axis_tvalid , - m1_axis_tdata , - - // Registers. - FREQ_REG , - PHASE_REG , - NSAMP_REG , - OUTSEL_REG , - MODE_REG , - WE_REG - ); - -/**************/ -/* Parameters */ -/**************/ -// Number of parallel dds blocks. -localparam [15:0] N_DDS = 8; - -/*********/ -/* Ports */ -/*********/ -input aresetn; -input aclk; - -output s_axis_tready; -input s_axis_tvalid; -input [N_DDS*16-1:0] s_axis_tdata; - -input m0_axis_tready; -output m0_axis_tvalid; -output [N_DDS*32-1:0] m0_axis_tdata; - -input m1_axis_tready; -output m1_axis_tvalid; -output [32-1:0] m1_axis_tdata; - -input [31:0] FREQ_REG; -input [31:0] PHASE_REG; -input [15:0] NSAMP_REG; -input [1:0] OUTSEL_REG; -input MODE_REG; -input WE_REG; - -/********************/ -/* Internal signals */ -/********************/ -wire we; -reg we_r; - -wire fifo_wr_en; -wire [82:0] fifo_din; -wire fifo_rd_en; -wire [82:0] fifo_dout; -wire fifo_full; -wire fifo_empty; - -/**********************/ -/* Begin Architecture */ -/**********************/ - -// WE_REG sync. -synchronizer_n - WE_REG_resync_i - ( - .rstn (aresetn ), - .clk (aclk ), - .data_in (WE_REG ), - .data_out (we ) - ); - -// Down-conversion + Filter + Decimation. -down_conversion_fir - down_conversion_fir_i - ( - // Reset and clock. - .rstn (aresetn ), - .clk (aclk ), - - // S_AXIS for input. - .s_axis_tready_o (s_axis_tready ), - .s_axis_tvalid_i (s_axis_tvalid ), - .s_axis_tdata_i (s_axis_tdata ), - - // M0_AXIS for output data (before filter and decimation). - .m0_axis_tready_i (m0_axis_tready ), - .m0_axis_tvalid_o (m0_axis_tvalid ), - .m0_axis_tdata_o (m0_axis_tdata ), - - // M1_AXIS for output data. - .m1_axis_tready_i (m1_axis_tready ), - .m1_axis_tvalid_o (m1_axis_tvalid ), - .m1_axis_tdata_o (m1_axis_tdata ), - - // Fifo interface. - .fifo_rd_en_o (fifo_rd_en ), - .fifo_empty_i (fifo_empty ), - .fifo_dout_i (fifo_dout ) - ); - -// Fifo for queuing waveforms. -fifo - #( - // Data width. - .B (83), - - // Fifo depth. - .N (8) - ) - fifo_i - ( - .rstn (aresetn ), - .clk (aclk ), - - // Write I/F. - .wr_en (fifo_wr_en ), - .din (fifo_din ), - - // Read I/F. - .rd_en (fifo_rd_en ), - .dout (fifo_dout ), - - // Flags. - .full (fifo_full ), - .empty (fifo_empty ) - ); - -// Fifo connections. -assign fifo_wr_en = we & ~we_r; -assign fifo_din = {MODE_REG,OUTSEL_REG,NSAMP_REG,PHASE_REG,FREQ_REG}; - -always @(posedge aclk) begin - if (~aresetn) - we_r <= 0; - else - we_r <= we; -end - -endmodule - diff --git a/qick/firmware/ip/axis_readout_v2/src/synchronizer_n.vhd b/qick/firmware/ip/axis_readout_v2/src/synchronizer_n.vhd deleted file mode 100644 index 925425d..0000000 --- a/qick/firmware/ip/axis_readout_v2/src/synchronizer_n.vhd +++ /dev/null @@ -1,42 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library common_lib; -use common_lib.all; - -entity synchronizer_n is - generic ( - N : Integer := 2 - ); - port ( - rstn : in std_logic; - clk : in std_logic; - data_in : in std_logic; - data_out : out std_logic - ); -end synchronizer_n; - -architecture rtl of synchronizer_n is - --- Internal register. -signal data_int_reg : std_logic_vector (N-1 downto 0); - -begin - -process(clk) -begin - if (rising_edge(clk)) then - if (rstn = '0') then - data_int_reg <= (others => '0'); - else - data_int_reg <= data_int_reg(N-2 downto 0) & data_in; - end if; - end if; -end process; - --- Assign output. -data_out <= data_int_reg(N-1); - -end rtl; - diff --git a/qick/firmware/ip/axis_readout_v2/src/tb/data_iq.txt b/qick/firmware/ip/axis_readout_v2/src/tb/data_iq.txt deleted file mode 100644 index 301691a..0000000 --- a/qick/firmware/ip/axis_readout_v2/src/tb/data_iq.txt +++ /dev/null @@ -1,10000 +0,0 @@ -16392,0 -3219,0 --15142,0 --9091,0 -11604,0 -13648,0 --6276,0 --16068,0 -11,0 -16054,0 -6273,0 --13649,0 --11616,0 -9106,0 -15132,0 --3192,0 --16399,0 --3234,0 -15152,0 -9107,0 --11593,0 --13656,0 -6261,0 -16068,0 --33,0 --16070,0 --6267,0 -13617,0 -11569,0 --9125,0 --15134,0 -3218,0 -16370,0 -3175,0 --15157,0 --9123,0 -11589,0 -13654,0 --6280,0 --16043,0 --18,0 -16062,0 -6261,0 --13626,0 --11596,0 -9094,0 -15131,0 --3187,0 --16385,0 --3199,0 -15154,0 -9090,0 --11588,0 --13611,0 -6289,0 -16084,0 -14,0 --16091,0 --6292,0 -13607,0 -11584,0 --9127,0 --15153,0 -3189,0 -16375,0 -3200,0 --15147,0 --9130,0 -11565,0 -13630,0 --6269,0 --16083,0 --9,0 -16060,0 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-wire [2:0] s_axi_arprot; -wire s_axi_arready; -wire s_axi_arvalid; -wire [5:0] s_axi_awaddr; -wire [2:0] s_axi_awprot; -wire s_axi_awready; -wire s_axi_awvalid; -wire s_axi_bready; -wire [1:0] s_axi_bresp; -wire s_axi_bvalid; -wire [31:0] s_axi_rdata; -wire s_axi_rready; -wire [1:0] s_axi_rresp; -wire s_axi_rvalid; -wire [31:0] s_axi_wdata; -wire s_axi_wready; -wire [3:0] s_axi_wstrb; -wire s_axi_wvalid; - -reg aresetn; -reg aclk; - -// s_axis interfase. -wire s_axis_tready; -reg s_axis_tvalid; -reg [N_DDS*16-1:0] s_axis_tdata; - -// m0_axis interfase. -reg m0_axis_tready; -wire m0_axis_tvalid; -reg [N_DDS*32-1:0] m0_axis_tdata; - -// m1_axis interfase. -reg m1_axis_tready; -wire m1_axis_tvalid; -reg [32-1:0] m1_axis_tdata; - -// Assignment of data out for debugging. -wire [31:0] dout_ii [0:N_DDS-1]; - -xil_axi_prot_t prot = 0; -reg[31:0] data_wr = 32'h12345678; -reg[31:0] data; -xil_axi_resp_t resp; - -// Test bench control. -reg tb_data_in = 0; -reg tb_data_in_done = 0; -reg tb_write_out = 0; - -// Debug. -generate -genvar ii; -for (ii = 0; ii < N_DDS; ii = ii + 1) begin : GEN_debug - assign dout_ii[ii] = m0_axis_tdata[32*ii +: 32]; -end -endgenerate - -// axi_mst_0. -axi_mst_0 axi_mst_0_i - ( - .aclk (s_axi_aclk ), - .aresetn (s_axi_aresetn ), - .m_axi_araddr (s_axi_araddr ), - .m_axi_arprot (s_axi_arprot ), - .m_axi_arready (s_axi_arready ), - .m_axi_arvalid (s_axi_arvalid ), - .m_axi_awaddr (s_axi_awaddr ), - .m_axi_awprot (s_axi_awprot ), - .m_axi_awready (s_axi_awready ), - .m_axi_awvalid (s_axi_awvalid ), - .m_axi_bready (s_axi_bready ), - .m_axi_bresp (s_axi_bresp ), - .m_axi_bvalid (s_axi_bvalid ), - .m_axi_rdata (s_axi_rdata ), - .m_axi_rready (s_axi_rready ), - .m_axi_rresp (s_axi_rresp ), - .m_axi_rvalid (s_axi_rvalid ), - .m_axi_wdata (s_axi_wdata ), - .m_axi_wready (s_axi_wready ), - .m_axi_wstrb (s_axi_wstrb ), - .m_axi_wvalid (s_axi_wvalid ) - ); - -axis_readout_v2 - DUT - ( - // AXI Slave I/F for configuration. - .s_axi_aclk (s_axi_aclk ), - .s_axi_aresetn (s_axi_aresetn ), - .s_axi_araddr (s_axi_araddr ), - .s_axi_arprot (s_axi_arprot ), - .s_axi_arready (s_axi_arready ), - .s_axi_arvalid (s_axi_arvalid ), - .s_axi_awaddr (s_axi_awaddr ), - .s_axi_awprot (s_axi_awprot ), - .s_axi_awready (s_axi_awready ), - .s_axi_awvalid (s_axi_awvalid ), - .s_axi_bready (s_axi_bready ), - .s_axi_bresp (s_axi_bresp ), - .s_axi_bvalid (s_axi_bvalid ), - .s_axi_rdata (s_axi_rdata ), - .s_axi_rready (s_axi_rready ), - .s_axi_rresp (s_axi_rresp ), - .s_axi_rvalid (s_axi_rvalid ), - .s_axi_wdata (s_axi_wdata ), - .s_axi_wready (s_axi_wready ), - .s_axi_wstrb (s_axi_wstrb ), - .s_axi_wvalid (s_axi_wvalid ), - - // s_* and m_* reset/clock. - .aresetn (aresetn ), - .aclk (aclk ), - - // S_AXIS: for input data (8x samples per clock). - .s_axis_tdata (s_axis_tdata ), - .s_axis_tvalid (s_axis_tvalid ), - .s_axis_tready (s_axis_tready ), - - // M0_AXIS: for output data (before filter and decimation, 8x samples - // per clock). - .m0_axis_tready (m0_axis_tready ), - .m0_axis_tvalid (m0_axis_tvalid ), - .m0_axis_tdata (m0_axis_tdata ), - - // M1_AXIS: for output data. - .m1_axis_tready (m1_axis_tready ), - .m1_axis_tvalid (m1_axis_tvalid ), - .m1_axis_tdata (m1_axis_tdata ) - ); - -// VIP Agents -axi_mst_0_mst_t axi_mst_0_agent; - -initial begin - // Create agents. - axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); - - // Set tag for agents. - axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); - - // Start agents. - axi_mst_0_agent.start_master(); - - // Reset sequence. - s_axi_aresetn <= 0; - m0_axis_tready <= 1; - m1_axis_tready <= 1; - aresetn <= 0; - #500; - s_axi_aresetn <= 1; - aresetn <= 1; - - #1000; - - $display("###############################"); - $display("### Start Recording Outputs ###"); - $display("###############################"); - $display("t = %0t", $time); - - tb_write_out <= 1; - - - $display("###################"); - $display("### Program DDS ###"); - $display("###################"); - $display("t = %0t", $time); - - // FREQ. - data_wr = freq_calc(100, N_DDS, 5); - axi_mst_0_agent.AXI4LITE_WRITE_BURST(0*4, prot, data_wr, resp); - #10; - - // PHASE. - data_wr = 0; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(1*4, prot, data_wr, resp); - #10; - - // NSAMP. - data_wr = 10; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(2*4, prot, data_wr, resp); - #10; - - // OUTSEL : 0 (product), 1 (dds), 2 (input). - data_wr = 2; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(3*4, prot, data_wr, resp); - #10; - - // MODE : 1 (periodic). - data_wr = 1; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*4, prot, data_wr, resp); - #10; - - // WE. - data_wr = 1; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(5*4, prot, data_wr, resp); - #10; - - #100; - - // WE. - data_wr = 0; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(5*4, prot, data_wr, resp); - #10; - - #10000; - - //// FREQ. - //data_wr = freq_calc(100, N_DDS, 17); - //axi_mst_0_agent.AXI4LITE_WRITE_BURST(0*4, prot, data_wr, resp); - //#10; - - //// WE. - //data_wr = 1; - //axi_mst_0_agent.AXI4LITE_WRITE_BURST(5*4, prot, data_wr, resp); - //#10; - - //#100; - - //// WE. - //data_wr = 0; - //axi_mst_0_agent.AXI4LITE_WRITE_BURST(5*4, prot, data_wr, resp); - //#10; - - //#8484; - - //// FREQ. - //data_wr = freq_calc(100, N_DDS, 5); - //axi_mst_0_agent.AXI4LITE_WRITE_BURST(0*4, prot, data_wr, resp); - //#10; - - //// WE. - //data_wr = 1; - //axi_mst_0_agent.AXI4LITE_WRITE_BURST(5*4, prot, data_wr, resp); - //#10; - - #100; - - #888; - - $display("#######################"); - $display("### Send Input Data ###"); - $display("#######################"); - $display("t = %0t", $time); - tb_data_in <= 1; - - wait (tb_data_in_done); - - #1000; - - $display("##############################"); - $display("### Stop Recording Outputs ###"); - $display("##############################"); - $display("t = %0t", $time); - tb_write_out <= 0; - - #20000; - -end - -// Input data. -initial begin - int fd, i; - bit signed [15:0] vali, valq; - - tb_data_in_done <= 0; - s_axis_tvalid <= 1; - s_axis_tdata <= 0; - - wait (tb_data_in); - - #1000; - - // Open file with input data. - // Format: I, Q. - `ifdef SYNTH_SIMU - fd = $fopen("../../../../../../tb/data_iq.txt","r"); - `else - fd = $fopen("../../../../../tb/data_iq.txt","r"); - `endif - - //i = N_DDS; - i = 0; - while ($fscanf(fd,"%d,%d", vali, valq) == 2) begin - $display("Time %t: Line %d, I = %d, Q = %d", $time, i, vali, valq); - //s_axis_tdata_i[(i-1)*16 +: 16] <= vali; - s_axis_tdata[i*16 +: 16] <= vali; - //i = i - 1; - i = i + 1; - //if ( i == 0) begin - if ( i == N_DDS) begin - //i = N_DDS; - i = 0; - @(posedge aclk); - end - end - - #1000; - - @(posedge aclk); - tb_data_in_done <= 1; - -end - -// Write output into file. -initial begin - int fd; - int i; - shortint real_d, imag_d; - - // Output file. - `ifdef SYNTH_SIMU - fd = $fopen("../../../../../../tb/dout_fs.csv","w"); - `else - fd = $fopen("../../../../../tb/dout_fs.csv","w"); - `endif - - // Data format. - $fdisplay(fd, "valid, idx, real, imag"); - - wait (tb_write_out); - - while (tb_write_out) begin - @(posedge aclk); - for (i=0; i - - user.org - user - axis_readout_v3 - 1.0 - - - m_axis - - - - - - - TDATA - - - m_axis_tdata - - - - - TVALID - - - m_axis_tvalid - - - - - TREADY - - - m_axis_tready - - - - - - s0_axis - - - - - - - TDATA - - - s0_axis_tdata - - - - - TVALID - - - s0_axis_tvalid - - - - - TREADY - - - s0_axis_tready - - - - - - s1_axis - - - - - - - TDATA - - - s1_axis_tdata - - - - - TVALID - - - s1_axis_tvalid - - - - - TREADY - - - s1_axis_tready - - - - - - aresetn - - - - - - - RST - - - aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - aclk - - - - - - - CLK - - - aclk - - - - - - ASSOCIATED_BUSIF - m_axis:s0_axis:s1_axis - - - ASSOCIATED_RESET - aresetn - - - - - - - - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis - Verilog - axis_readout_v3 - - xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset - - - 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xilinx_anylanguagebehavioralsimulation - - - - - - - - - choice_list_9d8b0d81 - ACTIVE_HIGH - ACTIVE_LOW - - - - - xilinx_anylanguagesynthesis_view_fileset - - src/fir_0/fir.coe - coe - - - src/fir_0/fir_0/fir_0.xci - xci - CELL_NAME_down_conversion_fir_i/fir_0_i/fir_0 - - - src/dds_0/dds_0/dds_0.xci - xci - CELL_NAME_down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/dds_0 - - - src/latency_reg.v - verilogSource - - - src/ctrl.sv - systemVerilogSource - - - src/down_conversion.sv - systemVerilogSource - - - src/down_conversion_fir.sv - systemVerilogSource - - - src/fifo/bram_simple_dp.vhd - vhdlSource - - - src/fifo/fifo.vhd - vhdlSource - - - src/axis_readout_v3.v - verilogSource - CHECKSUM_ff9d9536 - - - - xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset - - - - - - - - - - xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset - - - - - - - - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - src/fir_0/fir.coe - coe - - - src/fir_0/fir_0/fir_0.xci - xci - CELL_NAME_down_conversion_fir_i/fir_0_i/fir_0 - - - src/dds_0/dds_0/dds_0.xci - xci - CELL_NAME_down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/dds_0 - - - src/latency_reg.v - verilogSource - - - src/ctrl.sv - systemVerilogSource - - - src/down_conversion.sv - systemVerilogSource - - - src/down_conversion_fir.sv - systemVerilogSource - - - src/fifo/bram_simple_dp.vhd - vhdlSource - - - src/fifo/fifo.vhd - vhdlSource - - - src/axis_readout_v3.v - verilogSource - - - - xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset - - - - - - - - - - xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset - - - - - - - - - - xilinx_xpgui_view_fileset - - xgui/axis_readout_v3_v1_0.tcl - tclSource - CHECKSUM_f92e9879 - XGUI_VERSION_2 - - - - AXIS Readout V3 block with DDC (32-bit, phase coherent), filtering and 4x decimation, tProc controlled. - - - Component_Name - axis_readout_v3_v1_0 - - - - - - zynquplus - - - /UserIP - - AXIS Readout V3 - package_project - 4 - 2022-09-30T20:19:36Z - - /home/lstefana/v20.2/ip/axis_readout_v3 - /home/lstefana/v20.2/ip/axis_readout_v3 - /home/lstefana/v20.2/ip/axis_readout_v3 - /home/lstefana/v20.2/ip/axis_readout_v3 - /home/lstefana/v20.2/ip/axis_readout_v3 - /home/lstefana/v20.2/ip/axis_readout_v3 - /home/lstefana/v20.2/ip/axis_readout_v3 - /home/lstefana/v20.2/ip/axis_readout_v3 - /home/lstefana/v20.2/ip/axis_readout_v3 - /home/lstefana/v20.2/ip/axis_readout_v3 - /home/lstefana/v20.2/ip/axis_readout_v3 - /home/lstefana/v20.2/ip/axis_readout_v3 - /home/lstefana/v20.2/ip/axis_readout_v3 - /home/lstefana/v20.2/ip/axis_readout_v3 - /home/lstefana/v20.2/ip/axis_readout_v3 - /home/lstefana/v20.2/ip/axis_readout_v3 - /home/lstefana/v20.2/ip/axis_readout_v3 - /home/lstefana/v20.2/ip/axis_readout_v3 - /home/lstefana/v20.2/ip/axis_readout_v3 - /home/lstefana/v20.2/ip/axis_readout_v3 - /home/lstefana/v20.2/ip/axis_readout_v3 - /home/lstefana/v20.2/ip/axis_readout_v3 - /home/lstefana/v20.2/ip/axis_readout_v3 - /home/lstefana/v20.2/ip/axis_readout_v3 - /home/lstefana/v20.2/ip/axis_readout_v3 - /home/lstefana/v20.2/ip/axis_readout_v3 - /home/lstefana/v20.2/ip/axis_readout_v3 - /home/lstefana/v20.2/ip/axis_readout_v3 - /home/lstefana/v20.2/ip/axis_readout_v3 - /home/lstefana/v20.2/ip/axis_readout_v3 - /home/lstefana/v20.2/ip/axis_readout_v3 - - - - 2020.2 - - - - - - - diff --git a/qick/firmware/ip/axis_readout_v3/src/axis_readout_v3.v b/qick/firmware/ip/axis_readout_v3/src/axis_readout_v3.v deleted file mode 100644 index 0f8f84a..0000000 --- a/qick/firmware/ip/axis_readout_v3/src/axis_readout_v3.v +++ /dev/null @@ -1,98 +0,0 @@ -module axis_readout_v3 - ( - // Reset and clock. - input wire aresetn , - input wire aclk , - - // s0_axis for pushing waveforms. - output wire s0_axis_tready , - input wire s0_axis_tvalid , - input wire [87:0] s0_axis_tdata , - - // s1_axis for input data (4 real samples per clock). - output wire s1_axis_tready , - input wire s1_axis_tvalid , - input wire [4*16-1:0] s1_axis_tdata , - - // m_axis for output data (1 complex sample per clock). - input wire m_axis_tready , - output wire m_axis_tvalid , - output wire [31:0] m_axis_tdata - ); - -/********************/ -/* Internal Signals */ -/********************/ - -// Fifo. -wire fifo_wr_en ; -wire [87:0] fifo_din ; -wire fifo_rd_en ; -wire [87:0] fifo_dout ; -wire fifo_full ; -wire fifo_empty ; - -/**********************/ -/* Begin Architecture */ -/**********************/ - -// Fifo for queuing waveforms. -fifo - #( - // Data width. - .B (88), - - // Fifo depth. - .N (8) - ) - fifo_i - ( - .rstn (aresetn ), - .clk (aclk ), - - // Write I/F. - .wr_en (fifo_wr_en ), - .din (fifo_din ), - - // Read I/F. - .rd_en (fifo_rd_en ), - .dout (fifo_dout ), - - // Flags. - .full (fifo_full ), - .empty (fifo_empty ) - ); - -// Fifo connections. -assign fifo_wr_en = s0_axis_tvalid; -assign fifo_din = s0_axis_tdata; - -// Down-conversion + Decimation FIR. -down_conversion_fir - down_conversion_fir_i - ( - // Reset and clock. - .aresetn (aresetn ), - .aclk (aclk ), - - // Fifo interface. - .fifo_rd_en (fifo_rd_en ), - .fifo_empty (fifo_empty ), - .fifo_dout (fifo_dout ), - - // s_axis for input data (N samples per clock). - .s_axis_tready (s1_axis_tready ), - .s_axis_tvalid (s1_axis_tvalid ), - .s_axis_tdata (s1_axis_tdata ), - - // m_axis for output data. - .m_axis_tready (m_axis_tready ), - .m_axis_tvalid (m_axis_tvalid ), - .m_axis_tdata (m_axis_tdata ) - ); - -// Assign outputs. -assign s0_axis_tready = ~fifo_full; - -endmodule - diff --git a/qick/firmware/ip/axis_readout_v3/src/ctrl.sv b/qick/firmware/ip/axis_readout_v3/src/ctrl.sv deleted file mode 100644 index 7bc0714..0000000 --- a/qick/firmware/ip/axis_readout_v3/src/ctrl.sv +++ /dev/null @@ -1,377 +0,0 @@ -//Format of waveform interface: -// |----------|-------|------|----------|----------|----------|---------| -// | 87 .. 84 | 83 | 82 | 81 .. 80 | 79 .. 64 | 63 .. 32 | 31 .. 0 | -// |----------|-------|------|----------|----------|----------|---------| -// | xxxx | phrst | mode | outsel | nsamp | phase | freq | -// |----------|-------|------|----------|----------|----------|---------| -// freq : 32 bits -// phase : 32 bits -// nsamp : 16 bits -// outsel : 2 bits -// mode : 1 bit -// phrst : 1 bit -module ctrl - #( - parameter N = 4 - ) - ( - // Reset and clock. - input wire aresetn , - input wire aclk , - - // Fifo interface. - output wire fifo_rd_en , - input wire fifo_empty , - input wire [87:0] fifo_dout , - - // dds control. - output wire [N*72-1:0] dds_ctrl , - - // Output source selection. - output wire [1:0] outsel , - - // Output enable. - output wire en - ); - -// States. -typedef enum { READ_ST , - CNT_ST - } state_t; - -// State register. -(* fsm_encoding = "one_hot" *) state_t state; - -// Fifo dout register. -reg [87:0] fifo_dout_r; - -// Non-stop counter for time calculation (adds N samples each clock tick). -reg [31:0] cnt_n; -reg [31:0] cnt_n_reg; - -// Pinc/phase. -wire [31:0] pinc_int; -reg [31:0] pinc_r1; -reg [31:0] pinc_r2; -wire [31:0] pinc_N; -reg [31:0] pinc_N_r1; -reg [31:0] pinc_N_r2; -reg [31:0] pinc_N_r3; -reg [31:0] pinc_N_r4; -reg [31:0] pinc_N_r5; -wire [31:0] pinc_Nm; -reg [31:0] pinc_Nm_r1; -reg [31:0] pinc_Nm_r2; -reg [31:0] pinc_Nm_r3; - -wire [31:0] phase_int; -reg [31:0] phase_r1; -reg [31:0] phase_r2; -reg [31:0] phase_r3; -reg [31:0] phase_r4; -reg [31:0] phase_r5; -wire [31:0] phase_0; -reg [31:0] phase_0_r1; - -// Phase vectors. -wire [31:0] phase_v0 [N]; -reg [31:0] phase_v0_r1 [N]; -reg [31:0] phase_v0_r2 [N]; -reg [31:0] phase_v0_r3 [N]; -reg [31:0] phase_v0_r4 [N]; -wire [31:0] phase_v1 [N]; -reg [31:0] phase_v1_r1 [N]; - -// sync. -reg sync_reg; -reg sync_reg_r1; -reg sync_reg_r2; -reg sync_reg_r3; -reg sync_reg_r4; -reg sync_reg_r5; -reg sync_reg_r6; -reg sync_reg_r7; - -// Number of samples. -wire [15:0] nsamp_int; - -// Output selection. -wire [1:0] outsel_int; -reg [1:0] outsel_r1; -reg [1:0] outsel_r2; -reg [1:0] outsel_r3; -reg [1:0] outsel_r4; -reg [1:0] outsel_r5; -reg [1:0] outsel_r6; -reg [1:0] outsel_r7; - -// Mode. -wire mode_int; - -// Phase reset. -wire phrst_int; - -// Load enable flag. -wire load_int; -reg load_r; - -// Fifo Read Enable. -reg rd_en_int; -reg rd_en_r1; -reg rd_en_r2; - -// Counter. -reg [31:0] cnt; - -// Output enable register. -reg en_reg; -reg en_reg_r1; -reg en_reg_r2; -reg en_reg_r3; -reg en_reg_r4; -reg en_reg_r5; -reg en_reg_r6; -reg en_reg_r7; -reg en_reg_r8; - -// Registers. -always @(posedge aclk) begin - if (~aresetn) begin - // State register. - state <= READ_ST; - - // Fifo dout register. - fifo_dout_r <= 0; - - // Non-stop counter for time calculation. - cnt_n <= 0; - cnt_n_reg <= 0; - - // Pinc/phase/sync. - pinc_r1 <= 0; - pinc_r2 <= 0; - pinc_N_r1 <= 0; - pinc_N_r2 <= 0; - pinc_N_r3 <= 0; - pinc_N_r4 <= 0; - pinc_N_r5 <= 0; - pinc_Nm_r1 <= 0; - pinc_Nm_r2 <= 0; - pinc_Nm_r3 <= 0; - - phase_r1 <= 0; - phase_r2 <= 0; - phase_r3 <= 0; - phase_r4 <= 0; - phase_r5 <= 0; - phase_0_r1 <= 0; - - sync_reg <= 0; - sync_reg_r1 <= 0; - sync_reg_r2 <= 0; - sync_reg_r3 <= 0; - sync_reg_r4 <= 0; - sync_reg_r5 <= 0; - sync_reg_r6 <= 0; - sync_reg_r7 <= 0; - - // Output selection. - outsel_r1 <= 0; - outsel_r2 <= 0; - outsel_r3 <= 0; - outsel_r4 <= 0; - outsel_r5 <= 0; - outsel_r6 <= 0; - outsel_r7 <= 0; - - // Load enable flag. - load_r <= 0; - - // Fifo Read Enable. - rd_en_r1 <= 0; - rd_en_r2 <= 0; - - // Counter. - cnt <= 0; - - // Output enable register. - en_reg <= 0; - en_reg_r1 <= 0; - en_reg_r2 <= 0; - en_reg_r3 <= 0; - en_reg_r4 <= 0; - en_reg_r5 <= 0; - en_reg_r6 <= 0; - en_reg_r7 <= 0; - en_reg_r8 <= 0; - end - else begin - // State register. - case (state) - READ_ST: - if (mode_int || ~fifo_empty) - state <= CNT_ST; - CNT_ST: - if ( cnt == nsamp_int-2 ) - state <= READ_ST; - endcase - - // Fifo dout register. - if (load_r) - fifo_dout_r <= fifo_dout; - - // Non-stop counter for time calculation. - if (sync_reg == 1'b1 && phrst_int == 1'b1) - cnt_n <= 0; - else - cnt_n <= cnt_n + N; - - if (sync_reg_r1 == 1'b1) - cnt_n_reg <= cnt_n; - - // Pinc/phase/sync. - pinc_r1 <= pinc_int; - pinc_r2 <= pinc_r1; - pinc_N_r1 <= pinc_N; - pinc_N_r2 <= pinc_N_r1; - pinc_N_r3 <= pinc_N_r2; - pinc_N_r4 <= pinc_N_r3; - pinc_N_r5 <= pinc_N_r4; - pinc_Nm_r1 <= pinc_Nm; - pinc_Nm_r2 <= pinc_Nm_r1; - pinc_Nm_r3 <= pinc_Nm_r2; - - phase_r1 <= phase_int; - phase_r2 <= phase_r1; - phase_r3 <= phase_r2; - phase_r4 <= phase_r3; - phase_r5 <= phase_r4; - phase_0_r1 <= phase_0; - - sync_reg <= load_r; - sync_reg_r1 <= sync_reg; - sync_reg_r2 <= sync_reg_r1; - sync_reg_r3 <= sync_reg_r2; - sync_reg_r4 <= sync_reg_r3; - sync_reg_r5 <= sync_reg_r4; - sync_reg_r6 <= sync_reg_r5; - sync_reg_r7 <= sync_reg_r6; - - // Output selection. - outsel_r1 <= outsel_int; - outsel_r2 <= outsel_r1; - outsel_r3 <= outsel_r2; - outsel_r4 <= outsel_r3; - outsel_r5 <= outsel_r4; - outsel_r6 <= outsel_r5; - outsel_r7 <= outsel_r6; - - // Load enable flag. - load_r <= load_int; - - // Fifo Read Enable. - rd_en_r1 <= rd_en_int; - rd_en_r2 <= rd_en_r1; - - // Counter. - if (rd_en_int) - cnt <= 0; - else - cnt <= cnt + 1; - - // Output enable register. - if (~mode_int && rd_en_int) - if (~fifo_empty) - en_reg <= 1; - else - en_reg <= 0; - - en_reg_r1 <= en_reg; - en_reg_r2 <= en_reg_r1; - en_reg_r3 <= en_reg_r2; - en_reg_r4 <= en_reg_r3; - en_reg_r5 <= en_reg_r4; - en_reg_r6 <= en_reg_r5; - en_reg_r7 <= en_reg_r6; - en_reg_r8 <= en_reg_r7; - end -end - -// FSM outputs. -always_comb begin - // Default. - rd_en_int = 0; - - case (state) - READ_ST: - rd_en_int = 1; - - CNT_ST: - rd_en_int = 0; - endcase -end - -// Fifo output fields. -assign pinc_int = fifo_dout_r[31:0]; -assign phase_int = fifo_dout_r[63:32]; -assign nsamp_int = fifo_dout_r[79:64]; -assign outsel_int = fifo_dout_r[81:80]; -assign mode_int = fifo_dout_r[82]; -assign phrst_int = fifo_dout_r[83]; - -// Frequency calculation. -assign pinc_N = pinc_r2*N; - -// Phase calculation. -assign pinc_Nm = pinc_r2*cnt_n_reg; -assign phase_0 = pinc_Nm_r3 + phase_r5; - -// Phase vectors. -generate -genvar i; - for (i=0; i < N; i = i + 1) begin : GEN_phase - // Registers. - always @(posedge aclk) begin - if (~aresetn) begin - // v0. - phase_v0_r1[i] <= 0; - phase_v0_r2[i] <= 0; - phase_v0_r3[i] <= 0; - phase_v0_r4[i] <= 0; - - // v1. - phase_v1_r1[i] <= 0; - end - else begin - // v0. - phase_v0_r1[i] <= phase_v0[i]; - phase_v0_r2[i] <= phase_v0_r1[i]; - phase_v0_r3[i] <= phase_v0_r2[i]; - phase_v0_r4[i] <= phase_v0_r3[i]; - - // v1. - phase_v1_r1[i] <= phase_v1[i]; - end - end - - // v0. - assign phase_v0[i] = pinc_r2*i; - - // v1. - assign phase_v1[i] = phase_v0_r4[i] + phase_0_r1; - - // dds_ctrl_o output. - assign dds_ctrl[i*72 +: 72] = {7'h00,sync_reg_r7,phase_v1_r1[i],pinc_N_r5}; - end -endgenerate - -// load_int. -assign load_int = rd_en_int & ~fifo_empty; - -// Assign outputs. -assign fifo_rd_en = rd_en_int; -assign outsel = outsel_r7; -assign en = en_reg_r8; - -endmodule - diff --git a/qick/firmware/ip/axis_readout_v3/src/dds_0/dds_0/dds_0.xci b/qick/firmware/ip/axis_readout_v3/src/dds_0/dds_0/dds_0.xci deleted file mode 100644 index a994dc7..0000000 --- a/qick/firmware/ip/axis_readout_v3/src/dds_0/dds_0/dds_0.xci +++ /dev/null @@ -1,312 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - dds_0 - - - - 100000000 - 0 - 0 - 0.000 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 9 - 0 - 0 - 0 - 32 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 1 - 0 - 1 - 0 - 1 - 0 - 0 - 10 - 1 - 0 - 9 - 0 - 32 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 0 - 2 - 0 - 16 - 14 - 3 - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - 3 - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - 0 - 1 - 0 - 1 - 0 - 72 - 1 - 0 - zynquplus - Full_Range - 1 - dds_0 - Not_Required - 256 - Minimal - 0.06 - Coregen - false - false - false - false - 10 - Configurable - Not_Required - Not_Required - Auto - Standard - 9 - false - false - Auto - Twos_Complement - Auto - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Sine_and_Cosine - 16 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - false - System_Parameters - Phase_Generator_and_SIN_COS_LUT - Streaming - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 32 - Streaming - true - On_Vector - Not_Required - 1 - 96 - false - 1 - zynquplusRFSOC - xilinx.com:zcu216:part0:2.0 - - xczu49dr - ffvf1760 - VERILOG - - MIXED - -2 - - E - TRUE - TRUE - IP_Flow - 20 - TRUE - ../../../../../test_phase/top/top.tmp/axis_readout_v3_v1_0_project/axis_readout_v3_v1_0_project.gen/sources_1/ip/dds_0 - - . - 2020.2 - GLOBAL - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/qick/firmware/ip/axis_readout_v3/src/down_conversion.sv b/qick/firmware/ip/axis_readout_v3/src/down_conversion.sv deleted file mode 100644 index cfd80fb..0000000 --- a/qick/firmware/ip/axis_readout_v3/src/down_conversion.sv +++ /dev/null @@ -1,290 +0,0 @@ -/* - * This block performs product between input data and dds. - * input tvalid is not taken into account. - * output tready is not taken into account. - */ -module down_conversion - #( - parameter N = 4 - ) - ( - // Reset and clock. - input wire aresetn , - input wire aclk , - - // Fifo interface. - output wire fifo_rd_en , - input wire fifo_empty , - input wire [87:0] fifo_dout , - - // s_axis for input data (N samples per clock). - output wire s_axis_tready , - input wire s_axis_tvalid , - input wire [N*16-1:0] s_axis_tdata , - - // m_axis for output data. - input wire m_axis_tready , - output wire m_axis_tvalid , - output wire [N*32-1:0] m_axis_tdata - ); - -/********************/ -/* Internal signals */ -/********************/ -// Input data. -reg [15:0] din_real_r1 [N] ; -wire [15:0] din_real_la [N] ; -wire [15:0] din_la_mux [N] ; - -// DDS input control. -reg dds_tvalid_r ; -wire [N*72-1:0] dds_ctrl_int ; -reg [N*72-1:0] dds_ctrl_int_r ; - -// DDS output. -wire [31:0] dds_dout [N] ; -reg [31:0] dds_dout_r1 [N] ; -wire [31:0] dds_dout_la [N] ; -wire [31:0] dds_la_mux [N] ; - -// Product. -wire signed [15:0] prod_a_real [N] ; -wire signed [15:0] prod_b_real [N] ; -wire signed [15:0] prod_b_imag [N] ; -wire signed [31:0] prod_y_real [N] ; -wire signed [31:0] prod_y_imag [N] ; -wire signed [15:0] prod_y_real_round [N] ; -wire signed [15:0] prod_y_imag_round [N] ; -wire [31:0] prod_y [N] ; -reg [31:0] prod_y_r1 [N] ; -reg [31:0] prod_y_r2 [N] ; - -// Muxed output. -wire [31:0] dout_mux [N] ; -reg [31:0] dout_mux_r1 [N] ; - -// Output source selection. -wire [1:0] outsel_int ; -wire [1:0] outsel_la ; - -// Output enable. -wire en_int ; -wire en_la ; - -/**********************/ -/* Begin Architecture */ -/**********************/ -// Control block. -ctrl - #( - .N(N) - ) - ctrl_i - ( - // Reset and clock. - .aresetn (aresetn ), - .aclk (aclk ), - - // Fifo interface. - .fifo_rd_en (fifo_rd_en ), - .fifo_empty (fifo_empty ), - .fifo_dout (fifo_dout ), - - // dds control. - .dds_ctrl (dds_ctrl_int ), - - // Output source selection. - .outsel (outsel_int ), - - // Output enable. - .en (en_int ) - ); - -generate -genvar i; - for (i=0; i N_LOG2, - -- Data width. - B => B - ) - Port map ( - clk => clk , - ena => '1' , - enb => rd_en , - wea => mem_wea , - addra => std_logic_vector(wptr) , - addrb => std_logic_vector(rptr) , - dia => din , - dob => mem_dob - ); - --- Memory connections. -mem_wea <= wr_en when full_i = '0' else - '0'; - --- Full/empty signals. -full_i <= '1' when wptr = rptr - 1 else - '0'; -empty_i <= '1' when wptr = rptr else - '0'; - --- wr_clk registers. -process (clk) -begin - if ( rising_edge(clk) ) then - if ( rstn = '0' ) then - wptr <= (others => '0'); - rptr <= (others => '0'); - else - -- Write. - if ( wr_en = '1' and full_i = '0' ) then - -- Write data. - - -- Increment pointer. - wptr <= wptr + 1; - end if; - - -- Read. - if ( rd_en = '1' and empty_i = '0' ) then - -- Read data. - - -- Increment pointer. - rptr <= rptr + 1; - end if; - end if; - end if; -end process; - --- Assign outputs. -dout <= mem_dob; -full <= full_i; -empty <= empty_i; - -end rtl; - diff --git a/qick/firmware/ip/axis_readout_v3/src/fifo/fifo_axi.vhd b/qick/firmware/ip/axis_readout_v3/src/fifo/fifo_axi.vhd deleted file mode 100644 index e1f76f7..0000000 --- a/qick/firmware/ip/axis_readout_v3/src/fifo/fifo_axi.vhd +++ /dev/null @@ -1,147 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo_axi is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo_axi; - -architecture rtl of fifo_axi is - --- FIFO. -component fifo is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end component; - --- FIFO read to AXI adapter. -component rd2axi is - Generic - ( - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- FIFO Read I/F. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (B-1 downto 0); - fifo_empty : in std_logic; - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - empty : out std_logic - ); -end component; - -signal rd_en_i : std_logic; -signal dout_i : std_logic_vector (B-1 downto 0); -signal empty_i : std_logic; - -begin - --- FIFO. -fifo_i : fifo - Generic map - ( - -- Data width. - B => B, - - -- Fifo depth. - N => N - ) - Port map - ( - rstn => rstn , - clk => clk , - - -- Write I/F. - wr_en => wr_en , - din => din , - - -- Read I/F. - rd_en => rd_en_i , - dout => dout_i , - - -- Flags. - full => full , - empty => empty_i - ); - --- FIFO read to AXI adapter. -rd2axi_i : rd2axi - Generic map - ( - -- Data width. - B => B - ) - Port map - ( - rstn => rstn , - clk => clk , - - -- FIFO Read I/F. - fifo_rd_en => rd_en_i , - fifo_dout => dout_i , - fifo_empty => empty_i , - - -- Read I/F. - rd_en => rd_en , - dout => dout , - empty => empty - ); - -end rtl; - diff --git a/qick/firmware/ip/axis_readout_v3/src/fifo/fifo_dc.vhd b/qick/firmware/ip/axis_readout_v3/src/fifo/fifo_dc.vhd deleted file mode 100644 index c214fae..0000000 --- a/qick/firmware/ip/axis_readout_v3/src/fifo/fifo_dc.vhd +++ /dev/null @@ -1,291 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo_dc is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - wr_rstn : in std_logic; - wr_clk : in std_logic; - - rd_rstn : in std_logic; - rd_clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo_dc; - -architecture rtl of fifo_dc is - --- Number of bits of depth. -constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); - --- Binary to gray converter. -component bin2gray is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end component; - --- Gray to binary converter. -component gray2bin is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end component; - --- Vector synchronizer (only for gray coded). -component synchronizer_vect is - generic ( - -- Sync stages. - N : Integer := 2; - - -- Data width. - B : Integer := 8 - ); - port ( - rstn : in std_logic; - clk : in std_logic; - data_in : in std_logic_vector (B-1 downto 0); - data_out : out std_logic_vector (B-1 downto 0) - ); -end component; - --- Dual port BRAM. -component bram_dp is - Generic ( - -- Memory address size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - ena : in STD_LOGIC; - enb : in STD_LOGIC; - wea : in STD_LOGIC; - web : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR (N-1 downto 0); - addrb : in STD_LOGIC_VECTOR (N-1 downto 0); - dia : in STD_LOGIC_VECTOR (B-1 downto 0); - dib : in STD_LOGIC_VECTOR (B-1 downto 0); - doa : out STD_LOGIC_VECTOR (B-1 downto 0); - dob : out STD_LOGIC_VECTOR (B-1 downto 0) - ); -end component; - --- Pointers. -signal wptr : unsigned (N_LOG2-1 downto 0); -signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); -signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); -signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); -signal rptr : unsigned (N_LOG2-1 downto 0); -signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); -signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); -signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); - --- Memory signals. -signal mem_wea : std_logic; -signal mem_dib : std_logic_vector (B-1 downto 0); -signal mem_doa : std_logic_vector (B-1 downto 0); -signal mem_dob : std_logic_vector (B-1 downto 0); - --- Flags. -signal full_i : std_logic; -signal empty_i : std_logic; - -begin - --- wptr_i: binary to gray. -wptr_i : bin2gray - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => std_logic_vector(wptr), - dout => wptr_g - ); - --- wptr_g: write to read domain. -wptr_g_i : synchronizer_vect - generic map ( - -- Sync stages. - N => 2, - - -- Data width. - B => N_LOG2 - ) - port map ( - rstn => rd_rstn, - clk => rd_clk, - data_in => wptr_g, - data_out => wptr_gc - ); - --- wptr_gc_i -wptr_gc_i : gray2bin - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => wptr_gc, - dout => wptr_c - ); - --- rptr_i: binary to gray. -rptr_i : bin2gray - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => std_logic_vector(rptr), - dout => rptr_g - ); - --- rptr_g: read to write domain. -rptr_g_i : synchronizer_vect - generic map ( - -- Sync stages. - N => 2, - - -- Data width. - B => N_LOG2 - ) - port map ( - rstn => wr_rstn, - clk => wr_clk, - data_in => rptr_g, - data_out => rptr_gc - ); - --- rptr_gc_i -rptr_gc_i : gray2bin - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => rptr_gc, - dout => rptr_c - ); - --- FIFO memory. -mem_i : bram_dp - Generic map ( - -- Memory address size. - N => N_LOG2, - -- Data width. - B => B - ) - Port map ( - clka => wr_clk, - clkb => rd_clk, - ena => '1', - enb => rd_en, - wea => mem_wea, - web => '0', - addra => std_logic_vector(wptr), - addrb => std_logic_vector(rptr), - dia => din, - dib => mem_dib, - doa => mem_doa, - dob => mem_dob - ); --- Memory connections. -mem_wea <= wr_en when full_i = '0' else - '0'; -mem_dib <= (others => '0'); - --- Full/empty signals. -full_i <= '1' when wptr = unsigned(rptr_c) - 1 else - '0'; -empty_i <= '1' when unsigned(wptr_c) = rptr else - '0'; - --- wr_clk registers. -process (wr_clk) -begin - if ( rising_edge(wr_clk) ) then - if ( wr_rstn = '0' ) then - wptr <= (others => '0'); - else - -- Write. - if ( wr_en = '1' and full_i = '0' ) then - -- Write data. - - -- Increment pointer. - wptr <= wptr + 1; - end if; - end if; - end if; -end process; - --- rd_clk registers. -process (rd_clk) -begin - if ( rising_edge(rd_clk) ) then - if ( rd_rstn = '0' ) then - rptr <= (others => '0'); - else - -- Read. - if ( rd_en = '1' and empty_i = '0' ) then - -- Read data. - - -- Increment pointer. - rptr <= rptr + 1; - end if; - end if; - end if; -end process; - --- Assign outputs. -dout <= mem_dob; -full <= full_i; -empty <= empty_i; - -end rtl; diff --git a/qick/firmware/ip/axis_readout_v3/src/fifo/fifo_dc_axi.vhd b/qick/firmware/ip/axis_readout_v3/src/fifo/fifo_dc_axi.vhd deleted file mode 100644 index eb83d1a..0000000 --- a/qick/firmware/ip/axis_readout_v3/src/fifo/fifo_dc_axi.vhd +++ /dev/null @@ -1,156 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo_dc_axi is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - wr_rstn : in std_logic; - wr_clk : in std_logic; - - rd_rstn : in std_logic; - rd_clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo_dc_axi; - -architecture rtl of fifo_dc_axi is - --- Dual-clock FIFO. -component fifo_dc is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - wr_rstn : in std_logic; - wr_clk : in std_logic; - - rd_rstn : in std_logic; - rd_clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end component; - --- FIFO read to AXI adapter. -component rd2axi is - Generic - ( - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- FIFO Read I/F. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (B-1 downto 0); - fifo_empty : in std_logic; - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - empty : out std_logic - ); -end component; - -signal rd_en_i : std_logic; -signal dout_i : std_logic_vector (B-1 downto 0); -signal empty_i : std_logic; - -begin - --- Dual-clock FIFO. -fifo_i : fifo_dc - Generic map - ( - -- Data width. - B => B, - - -- Fifo depth. - N => N - ) - Port map - ( - wr_rstn => wr_rstn , - wr_clk => wr_clk , - - rd_rstn => rd_rstn , - rd_clk => rd_clk , - - -- Write I/F. - wr_en => wr_en , - din => din , - - -- Read I/F. - rd_en => rd_en_i , - dout => dout_i , - - -- Flags. - full => full , - empty => empty_i - ); - --- FIFO read to AXI adapter. -rd2axi_i : rd2axi - Generic map - ( - -- Data width. - B => B - ) - Port map - ( - rstn => rd_rstn , - clk => rd_clk , - - -- FIFO Read I/F. - fifo_rd_en => rd_en_i , - fifo_dout => dout_i , - fifo_empty => empty_i , - - -- Read I/F. - rd_en => rd_en , - dout => dout , - empty => empty - ); - -end rtl; - diff --git a/qick/firmware/ip/axis_readout_v3/src/fifo/gray2bin.vhd b/qick/firmware/ip/axis_readout_v3/src/fifo/gray2bin.vhd deleted file mode 100644 index e23f8af..0000000 --- a/qick/firmware/ip/axis_readout_v3/src/fifo/gray2bin.vhd +++ /dev/null @@ -1,37 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity gray2bin is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end gray2bin; - -architecture rtl of gray2bin is - -signal bin : std_logic_vector (B-1 downto 0); - -begin - --- MSB always match. -bin(B-1) <= din(B-1); - -GEN: for I in 0 to B-2 generate -begin - bin(I) <= bin(I+1) xor din(I); -end generate GEN; - --- Assign output. -dout <= bin; - -end rtl; - diff --git a/qick/firmware/ip/axis_readout_v3/src/fifo/rd2axi.vhd b/qick/firmware/ip/axis_readout_v3/src/fifo/rd2axi.vhd deleted file mode 100644 index babadc6..0000000 --- a/qick/firmware/ip/axis_readout_v3/src/fifo/rd2axi.vhd +++ /dev/null @@ -1,138 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity rd2axi is - Generic - ( - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- FIFO Read I/F. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (B-1 downto 0); - fifo_empty : in std_logic; - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - empty : out std_logic - ); -end rd2axi; - -architecture rtl of rd2axi is - -type fsm_state is ( WAIT_EMPTY_ST, - READ_FIRST_ST, - READ_ST, - READ_LAST_ST); -signal current_state, next_state : fsm_state; - -signal wait_empty_state : std_logic; -signal read_first_state : std_logic; -signal read_state : std_logic; - -signal fifo_rd_en_i : std_logic; -signal empty_i : std_logic; - -begin - -process(clk) -begin - if (rising_edge(clk)) then - if (rstn = '0') then - current_state <= WAIT_EMPTY_ST; - else - current_state <= next_state; - end if; - end if; -end process; - --- Next state logic. -process(current_state, fifo_empty, rd_en) -begin - case current_state is - when WAIT_EMPTY_ST => - if (fifo_empty = '1') then - next_state <= WAIT_EMPTY_ST; - else - next_state <= READ_FIRST_ST; - end if; - - when READ_FIRST_ST => - next_state <= READ_ST; - - when READ_ST => - if (fifo_empty = '0') then - next_state <= READ_ST; - else - if (rd_en = '1') then - next_state <= WAIT_EMPTY_ST; - else - next_state <= READ_LAST_ST; - end if; - end if; - - when READ_LAST_ST => - if (rd_en = '0') then - next_state <= READ_LAST_ST; - else - next_state <= WAIT_EMPTY_ST; - end if; - - end case; -end process; - --- Output logic. -process(current_state) -begin -wait_empty_state <= '0'; -read_first_state <= '0'; -read_state <= '0'; -empty_i <= '0'; - case current_state is - when WAIT_EMPTY_ST => - wait_empty_state <= '1'; - read_first_state <= '0'; - read_state <= '0'; - empty_i <= '1'; - - when READ_FIRST_ST => - wait_empty_state <= '0'; - read_first_state <= '1'; - read_state <= '0'; - empty_i <= '1'; - - when READ_ST => - wait_empty_state <= '0'; - read_first_state <= '0'; - read_state <= '1'; - empty_i <= '0'; - - when READ_LAST_ST => - wait_empty_state <= '0'; - read_first_state <= '0'; - read_state <= '0'; - empty_i <= '0'; - - end case; -end process; - --- FIFO Read enable signal. -fifo_rd_en_i <= read_first_state or (read_state and rd_en); - --- Assign outputs. -fifo_rd_en <= fifo_rd_en_i; --- TODO: add register to freeze last value. -dout <= fifo_dout when empty_i = '0' else - (others => '0'); -empty <= empty_i; - -end rtl; - diff --git a/qick/firmware/ip/axis_readout_v3/src/fifo/synchronizer_vect.vhd b/qick/firmware/ip/axis_readout_v3/src/fifo/synchronizer_vect.vhd deleted file mode 100644 index 2fbb696..0000000 --- a/qick/firmware/ip/axis_readout_v3/src/fifo/synchronizer_vect.vhd +++ /dev/null @@ -1,49 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - --- This block is intended to use to sync gray coded vectors. - --- NOTE: Do not use with generic vector data, as it may result --- in corrupted re-sync data. - -entity synchronizer_vect is - generic ( - -- Sync stages. - N : Integer := 2; - - -- Data width. - B : Integer := 8 - ); - port ( - rstn : in std_logic; - clk : in std_logic; - data_in : in std_logic_vector (B-1 downto 0); - data_out : out std_logic_vector (B-1 downto 0) - ); -end synchronizer_vect; - -architecture rtl of synchronizer_vect is - --- Internal register. -type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); -signal data_int_reg : reg_t; - -begin - -process(clk) -begin - if (rising_edge(clk)) then - if (rstn = '0') then - data_int_reg <= (others => (others => '0')); -- 1 FF. - else - data_int_reg <= data_int_reg(N-2 downto 0) & data_in; - end if; - end if; -end process; - --- Assign output. -data_out <= data_int_reg(N-1); - -end rtl; - diff --git a/qick/firmware/ip/axis_readout_v3/src/fir_0/fir.coe b/qick/firmware/ip/axis_readout_v3/src/fir_0/fir.coe deleted file mode 100644 index 26bffb3..0000000 --- a/qick/firmware/ip/axis_readout_v3/src/fir_0/fir.coe +++ /dev/null @@ -1,2 +0,0 @@ -Radix = 10; -CoefData = -19,178,379,653,910,1053,997,719,273,-208,-558,-646,-438,-19,424,684,623,247,-287,-726,-844,-547,58,700,1059,922,301,-547,-1218,-1351,-811,213,1262,1803,1492,367,-1114,-2244,-2387,-1307,651,2636,3623,2887,414,-2944,-5678,-6144,-3225,3142,11784,20585,27137,29559,27137,20585,11784,3142,-3225,-6144,-5678,-2944,414,2887,3623,2636,651,-1307,-2387,-2244,-1114,367,1492,1803,1262,213,-811,-1351,-1218,-547,301,922,1059,700,58,-547,-844,-726,-287,247,623,684,424,-19,-438,-646,-558,-208,273,719,997,1053,910,653,379,178,-19 \ No newline at end of file diff --git a/qick/firmware/ip/axis_readout_v3/src/fir_0/fir_0.v b/qick/firmware/ip/axis_readout_v3/src/fir_0/fir_0.v deleted file mode 100644 index 9c50b5e..0000000 --- a/qick/firmware/ip/axis_readout_v3/src/fir_0/fir_0.v +++ /dev/null @@ -1,13 +0,0 @@ -module fir_0 - ( - input wire aclk , - input wire s_axis_data_tvalid , - output wire s_axis_data_tready , - input wire [127:0] s_axis_data_tdata , - output wire m_axis_data_tvalid , - output wire [31:0] m_axis_data_tdata - ); - -assign s_axis_data_tready = 1'b1; -assign m_axis_data_tvalid = 1'b1; -assign m_axis_data_tdata = s_axis_data_tdata[0 +: 16]; diff --git a/qick/firmware/ip/axis_readout_v3/src/fir_0/fir_0.veo b/qick/firmware/ip/axis_readout_v3/src/fir_0/fir_0.veo deleted file mode 100644 index 00695f6..0000000 --- a/qick/firmware/ip/axis_readout_v3/src/fir_0/fir_0.veo +++ /dev/null @@ -1,70 +0,0 @@ -// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -// IP VLNV: xilinx.com:ip:fir_compiler:7.2 -// IP Revision: 15 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -fir_0 your_instance_name ( - .aclk(aclk), // input wire aclk - .s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid - .s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready - .s_axis_data_tdata(s_axis_data_tdata), // input wire [127 : 0] s_axis_data_tdata - .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid - .m_axis_data_tdata(m_axis_data_tdata) // output wire [31 : 0] m_axis_data_tdata -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file fir_0.v when simulating -// the core, fir_0. When compiling the wrapper file, be sure to -// reference the Verilog simulation library. - diff --git a/qick/firmware/ip/axis_readout_v3/src/fir_0/fir_0/fir_0.xci b/qick/firmware/ip/axis_readout_v3/src/fir_0/fir_0/fir_0.xci deleted file mode 100644 index fc04e11..0000000 --- a/qick/firmware/ip/axis_readout_v3/src/fir_0/fir_0/fir_0.xci +++ /dev/null @@ -1,320 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - fir_0 - - - - 100000000 - 0 - 0 - 0.000 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 6 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 1 - 0 - 0 - undef - 0.000 - 16 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - 35,35 - 35,35,35,35,35,35,35,35 - fixed - fir_0.mif - 54 - 2 - 0 - 0,0,0,0,0,0,0,0 - 0,0,0,0,0,0,0,0 - 16,16,16,16,16,16,16,16 - 0 - 16 - 54 - 1 - 4 - fir_0 - 0 - 0 - 1 - 2 - 0 - 16,16,16,16,16,16,16,16 - 0 - 0 - -0,2,4,6;-1,3,5,7;0,-2,4,6;1,-3,5,7;0,2,-4,6;1,3,-5,7;0,2,4,-6;1,3,5,-7 - 0,0,0,0,0,0,0,0 - 0,1,2,3,4,5,6,7 - 16,16,16,16,16,16,16,16 - 16,16,16,16,16,16,16,16 - 16 - 1 - ./ - none - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 2 - 61 - 1 - 0 - 0 - 48 - 1 - 1 - 1 - 54 - 1 - 107 - 0 - 0 - none - 0,2,4,-6;1,3,5,-7 - 18,18 - 1 - 18 - 1 - 6,7,6,7,6,7,6,7 - 1 - 2 - 1 - 1 - 0 - 128 - 1 - zynquplus - 1 - false - false - Basic - 300.0 - COE_File - 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 - Automatic - false - ../fir.coe - 0 - false - 1 - Signed - Inferred - 16 - 54 - fir_0 - false - false - false - false - Not_Required - 1 - Automatic - 0 - false - false - Signed - 16 - 4 - false - false - Systolic_Multiply_Accumulate - 1 - Decimation - Coregen - false - false - false - 1 - false - false - Automatic - 4 - 1 - false - Not_Required - Automatic - false - false - 1 - 1 - 2 - false - Area - None - None - false - Automatic - Symmetric_Rounding_to_Zero - 18 - 0.5 - 0.0 - P4-0,P4-1,P4-2,P4-3,P4-4 - false - Automatic - Integer_Coefficients - Output_Sample_Period - Integer - no_coe_file_loaded - true - Single - On_Vector - true - Not_Required - 1 - 0.001 - All - 1.0 - 0.5 - 1 - zynquplusRFSOC - xilinx.com:zcu216:part0:2.0 - - xczu49dr - ffvf1760 - VERILOG - - MIXED - -2 - - E - TRUE - TRUE - IP_Flow - 15 - TRUE - ../../../../../test_phase/top/top.tmp/axis_readout_v3_v1_0_project/axis_readout_v3_v1_0_project.gen/sources_1/ip/fir_0 - - . - 2020.2 - GLOBAL - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/qick/firmware/ip/axis_readout_v3/src/latency_reg.v b/qick/firmware/ip/axis_readout_v3/src/latency_reg.v deleted file mode 100644 index 687a9f3..0000000 --- a/qick/firmware/ip/axis_readout_v3/src/latency_reg.v +++ /dev/null @@ -1,61 +0,0 @@ -module latency_reg - ( - rstn , - clk , - - din , - dout - ); - -// Parameters. -parameter N = 2; // Latency. -parameter B = 8; // Data width. - -// Ports. -input rstn; -input clk; -input [B-1:0] din; -output [B-1:0] dout; - -// Shift register. -reg [B-1:0] shift_r [0:N-1]; - -generate -genvar i; - for (i=1; i - - user.org - user - axis_register_slice_nb - 1.0 - - - m_axis - - - - - - - TDATA - - - m_axis_tdata - - - - - TVALID - - - m_axis_tvalid - - - - - TREADY - - - m_axis_tready - - - - - - s_axis - - - - - - - TDATA - - - s_axis_tdata - - - - - TVALID - - - s_axis_tvalid - - - - - TREADY - - - s_axis_tready - - - - - - aresetn - - - - - - - RST - - - aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - aclk - - - - - - - CLK - - - aclk - - - - - - ASSOCIATED_BUSIF - m_axis:s_axis - - - ASSOCIATED_RESET - aresetn - - - - - - - - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis - VHDL - axis_register_slice_nb - - xilinx_anylanguagesynthesis_view_fileset - - - - viewChecksum - 71ea944a - - - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - VHDL - axis_register_slice_nb - - xilinx_anylanguagebehavioralsimulation_view_fileset - - - - viewChecksum - 71ea944a - - - - - xilinx_xpgui - UI Layout - :vivado.xilinx.com:xgui.ui - - xilinx_xpgui_view_fileset - - - - viewChecksum - 2c3a0701 - - - - - - - aclk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - aresetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axis_tdata - - in - - 15 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axis_tvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axis_tready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m_axis_tdata - - out - - 15 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m_axis_tvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m_axis_tready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 1 - - - - - - - B - B - 16 - - - N - N - 4 - - - - - - choice_list_74b5137e - ACTIVE_HIGH - ACTIVE_LOW - - - - - xilinx_anylanguagesynthesis_view_fileset - - src/axis_register_slice_nb.vhd - vhdlSource - CHECKSUM_71ea944a - - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - src/axis_register_slice_nb.vhd - vhdlSource - - - - xilinx_xpgui_view_fileset - - xgui/axis_register_slice_nb_v1_0.tcl - tclSource - CHECKSUM_2c3a0701 - XGUI_VERSION_2 - - - - AXIS Register Slice Non-Blocking. - - - B - B - 16 - - - N - N - 4 - - - Component_Name - axis_register_slice_nb_v1_0 - - - - - - virtex7 - qvirtex7 - versal - kintex7 - kintex7l - qkintex7 - qkintex7l - akintex7 - artix7 - artix7l - aartix7 - qartix7 - zynq - qzynq - azynq - spartan7 - aspartan7 - virtexu - zynquplus - virtexuplus - virtexuplusHBM - virtexuplus58g - kintexuplus - kintexu - - - /UserIP - - AXIS Register Slice Non-Blocking - package_project - 2 - 2022-04-11T15:56:34Z - - /home/lstefana/v20.2/ip/axis_register_slice_nb - /home/lstefana/v20.2/ip/axis_register_slice_nb - /home/lstefana/v20.2/ip/axis_register_slice_nb - /home/lstefana/v20.2/ip/axis_register_slice_nb - /home/lstefana/v20.2/ip/axis_register_slice_nb - /home/lstefana/v20.2/ip/axis_register_slice_nb - /home/lstefana/v20.2/ip/axis_register_slice_nb - /home/lstefana/v20.2/ip/axis_register_slice_nb - /home/lstefana/v20.2/ip/axis_register_slice_nb - - - - 2020.2 - - - - - - - - diff --git a/qick/firmware/ip/axis_register_slice_nb/src/axis_register_slice_nb.vhd b/qick/firmware/ip/axis_register_slice_nb/src/axis_register_slice_nb.vhd deleted file mode 100644 index 14fdb50..0000000 --- a/qick/firmware/ip/axis_register_slice_nb/src/axis_register_slice_nb.vhd +++ /dev/null @@ -1,61 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; -use IEEE.MATH_REAL.ALL; - -entity axis_register_slice_nb is - Generic - ( - -- Number of bits. - B : Integer := 16; - - -- Delay. - N : Integer := 4 - ); - Port - ( - -- Reset and clock. - aclk : in std_logic; - aresetn : in std_logic; - - -- AXIS Slave I/F. - s_axis_tdata : in std_logic_vector(B-1 downto 0); - s_axis_tvalid : in std_logic; - s_axis_tready : out std_logic; - - -- AXIS Master I/F. - m_axis_tdata : out std_logic_vector(B-1 downto 0); - m_axis_tvalid : out std_logic; - m_axis_tready : in std_logic - ); -end axis_register_slice_nb; - -architecture rtl of axis_register_slice_nb is - --- Shift register for data. -type reg_v is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); -signal shift_reg_tdata : reg_v; - -begin - --- Registers. -process (aclk) -begin - if ( rising_edge(aclk) ) then - if ( aresetn = '0' ) then - -- Shift registers. - shift_reg_tdata <= (others => (others => '0')); - else - shift_reg_tdata <= shift_reg_tdata (N-2 downto 0) & s_axis_tdata; - end if; - end if; -end process; - --- Assign outputs. -s_axis_tready <= '1'; - -m_axis_tdata <= shift_reg_tdata (N-1); -m_axis_tvalid <= '1'; - -end rtl; - diff --git a/qick/firmware/ip/axis_register_slice_nb/src/tb.vhd b/qick/firmware/ip/axis_register_slice_nb/src/tb.vhd deleted file mode 100644 index cd3763f..0000000 --- a/qick/firmware/ip/axis_register_slice_nb/src/tb.vhd +++ /dev/null @@ -1,142 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity tb is -end tb; - -architecture rtl of tb is - -constant B : Integer := 8; -constant N : Integer := 3; - --- DUT. -component axis_register_slice_nb is - Generic - ( - -- Number of bits. - B : Integer := 16; - - -- Delay. - N : Integer := 4 - ); - Port - ( - -- Reset and clock. - aclk : in std_logic; - aresetn : in std_logic; - - -- AXIS Slave I/F. - s_axis_tdata : in std_logic_vector(B-1 downto 0); - s_axis_tvalid : in std_logic; - s_axis_tready : out std_logic; - - -- AXIS Master I/F. - m_axis_tdata : out std_logic_vector(B-1 downto 0); - m_axis_tvalid : out std_logic; - m_axis_tready : in std_logic - ); -end component; - --- Reset and clock. -signal aclk : std_logic; -signal aresetn : std_logic; - --- AXIS Slave I/F. -signal s_axis_tdata : std_logic_vector(B-1 downto 0); -signal s_axis_tvalid : std_logic; -signal s_axis_tready : std_logic; - --- AXIS Master I/F. -signal m_axis_tdata : std_logic_vector(B-1 downto 0); -signal m_axis_tvalid : std_logic; -signal m_axis_tready : std_logic; - -begin - --- DUT. -DUT: axis_register_slice_nb - Generic map - ( - -- Number of bits. - B => B , - - -- Delay. - N => N - ) - Port map - ( - -- Reset and clock. - aclk => aclk , - aresetn => aresetn , - - -- AXIS Slave I/F. - s_axis_tdata => s_axis_tdata , - s_axis_tvalid => s_axis_tvalid , - s_axis_tready => s_axis_tready , - - -- AXIS Master I/F. - m_axis_tdata => m_axis_tdata , - m_axis_tvalid => m_axis_tvalid , - m_axis_tready => m_axis_tready - ); - --- Main TB. -process -begin - aresetn <= '0'; - wait for 300 ns; - aresetn <= '1'; - - wait until rising_edge(aclk); - s_axis_tdata <= std_logic_vector(to_unsigned(23,s_axis_tdata'length)); - s_axis_tvalid <= '1'; - - wait until rising_edge(aclk); - s_axis_tdata <= std_logic_vector(to_unsigned(54,s_axis_tdata'length)); - s_axis_tvalid <= '1'; - - wait until rising_edge(aclk); - s_axis_tvalid <= '1'; - - wait until rising_edge(aclk); - s_axis_tdata <= std_logic_vector(to_unsigned(3,s_axis_tdata'length)); - s_axis_tvalid <= '1'; - - wait until rising_edge(aclk); - s_axis_tdata <= std_logic_vector(to_unsigned(99,s_axis_tdata'length)); - s_axis_tvalid <= '1'; - - wait until rising_edge(aclk); - s_axis_tdata <= std_logic_vector(to_unsigned(23,s_axis_tdata'length)); - s_axis_tvalid <= '0'; - - wait until rising_edge(aclk); - wait until rising_edge(aclk); - wait until rising_edge(aclk); - - wait until rising_edge(aclk); - s_axis_tdata <= std_logic_vector(to_unsigned(38,s_axis_tdata'length)); - s_axis_tvalid <= '1'; - - wait until rising_edge(aclk); - s_axis_tdata <= std_logic_vector(to_unsigned(3,s_axis_tdata'length)); - s_axis_tvalid <= '1'; - - wait until rising_edge(aclk); - s_axis_tdata <= std_logic_vector(to_unsigned(99,s_axis_tdata'length)); - s_axis_tvalid <= '1'; -end process; - --- Clock. -process -begin - aclk <= '0'; - wait for 5 ns; - aclk <= '1'; - wait for 5 ns; -end process; - - -end rtl; - diff --git a/qick/firmware/ip/axis_register_slice_nb/xgui/axis_register_slice_nb_v1_0.tcl b/qick/firmware/ip/axis_register_slice_nb/xgui/axis_register_slice_nb_v1_0.tcl deleted file mode 100644 index 1717489..0000000 --- a/qick/firmware/ip/axis_register_slice_nb/xgui/axis_register_slice_nb_v1_0.tcl +++ /dev/null @@ -1,40 +0,0 @@ -# Definitional proc to organize widgets for parameters. -proc init_gui { IPINST } { - ipgui::add_param $IPINST -name "Component_Name" - #Adding Page - set Page_0 [ipgui::add_page $IPINST -name "Page 0"] - ipgui::add_param $IPINST -name "B" -parent ${Page_0} - ipgui::add_param $IPINST -name "N" -parent ${Page_0} - - -} - -proc update_PARAM_VALUE.B { PARAM_VALUE.B } { - # Procedure called to update B when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.B { PARAM_VALUE.B } { - # Procedure called to validate B - return true -} - -proc update_PARAM_VALUE.N { PARAM_VALUE.N } { - # Procedure called to update N when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.N { PARAM_VALUE.N } { - # Procedure called to validate N - return true -} - - -proc update_MODELPARAM_VALUE.B { MODELPARAM_VALUE.B PARAM_VALUE.B } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.B}] ${MODELPARAM_VALUE.B} -} - -proc update_MODELPARAM_VALUE.N { MODELPARAM_VALUE.N PARAM_VALUE.N } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.N}] ${MODELPARAM_VALUE.N} -} - diff --git a/qick/firmware/ip/axis_resampler_2x1_v1/axis_resampler_2x1_v1_0.xcix b/qick/firmware/ip/axis_resampler_2x1_v1/axis_resampler_2x1_v1_0.xcix deleted file mode 100644 index 9f90510..0000000 Binary files a/qick/firmware/ip/axis_resampler_2x1_v1/axis_resampler_2x1_v1_0.xcix and /dev/null differ diff --git a/qick/firmware/ip/axis_resampler_2x1_v1/component.xml b/qick/firmware/ip/axis_resampler_2x1_v1/component.xml deleted file mode 100644 index 4aa9b43..0000000 --- a/qick/firmware/ip/axis_resampler_2x1_v1/component.xml +++ /dev/null @@ -1,424 +0,0 @@ - - - user.org - user - axis_resampler_2x1_v1 - 1.0 - - - m_axis - - - - - - - TDATA - - - m_axis_tdata - - - - - TVALID - - - m_axis_tvalid - - - - - TREADY - - - m_axis_tready - - - - - - s_axis - - - - - - - TDATA - - - s_axis_tdata - - - - - TVALID - - - s_axis_tvalid - - - - - TREADY - - - s_axis_tready - - - - - - aresetn - - - - - - - RST - - - aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - aclk - - - - - - - CLK - - - aclk - - - - - - ASSOCIATED_BUSIF - m_axis:s_axis - - - ASSOCIATED_RESET - aresetn - - - - - - - - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis - SystemVerilog - axis_resampler_2x1_v1 - - xilinx_anylanguagesynthesis_view_fileset - - - - viewChecksum - 2f191ebf - - - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - SystemVerilog - axis_resampler_2x1_v1 - - xilinx_anylanguagebehavioralsimulation_view_fileset - - - - viewChecksum - 2f191ebf - - - - - xilinx_xpgui - UI Layout - :vivado.xilinx.com:xgui.ui - - xilinx_xpgui_view_fileset - - - - viewChecksum - 2c3a0701 - - - - - - - aclk - - in - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - aresetn - - in - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axis_tready - - out - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axis_tvalid - - in - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axis_tdata - - in - - 127 - 0 - - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - m_axis_tready - - in - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 1 - - - - - m_axis_tvalid - - out - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m_axis_tdata - - out - - 63 - 0 - - - - wire - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - - B - B - 16 - - - N - N - 8 - - - - - - choice_list_9d8b0d81 - ACTIVE_HIGH - ACTIVE_LOW - - - - - xilinx_anylanguagesynthesis_view_fileset - - src/axis_resampler_2x1_v1.sv - systemVerilogSource - CHECKSUM_2f191ebf - - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - src/axis_resampler_2x1_v1.sv - systemVerilogSource - - - - xilinx_xpgui_view_fileset - - xgui/axis_resampler_2x1_v1_v1_0.tcl - tclSource - CHECKSUM_2c3a0701 - XGUI_VERSION_2 - - - - AXIS Resampler 2x1 V1 - - - B - B - 16 - - - N - N - 8 - - - Component_Name - axis_resampler_2x1_v1_v1_0 - - - - - - virtex7 - qvirtex7 - versal - kintex7 - kintex7l - qkintex7 - qkintex7l - akintex7 - artix7 - artix7l - aartix7 - qartix7 - zynq - qzynq - azynq - spartan7 - aspartan7 - virtexu - zynquplus - virtexuplus - virtexuplusHBM - virtexuplus58g - kintexuplus - kintexu - - - /UserIP - - AXIS Resampler 2x1 V1 - package_project - 3 - 2022-09-30T20:20:16Z - - /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 - /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 - /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 - /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 - /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 - /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 - /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 - /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 - /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 - /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 - /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 - /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 - /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 - /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 - /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 - /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 - /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 - /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 - /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 - /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 - /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 - /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 - /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 - /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 - - - - 2020.2 - - - - - - - - diff --git a/qick/firmware/ip/axis_resampler_2x1_v1/src/axis_resampler_2x1_v1.sv b/qick/firmware/ip/axis_resampler_2x1_v1/src/axis_resampler_2x1_v1.sv deleted file mode 100644 index 82a6aa4..0000000 --- a/qick/firmware/ip/axis_resampler_2x1_v1/src/axis_resampler_2x1_v1.sv +++ /dev/null @@ -1,103 +0,0 @@ -// This block resamples input data to reduce the number of lanes by 2. -// It is extremely important to be sure input data is valid only -// every other clock. Faster input data rate will make the block fail. -module axis_resampler_2x1_v1 - #( - // Number of bits. - parameter B = 16 , - - // Number of lanes (input). - parameter N = 8 - ) - ( - // Reset and clock. - input wire aclk , - input wire aresetn , - - // s_axis_* for input data. - output wire s_axis_tready , - input wire s_axis_tvalid , - input wire [N*B-1:0] s_axis_tdata , - - // m_axis_* for output data. - input wire m_axis_tready , - output wire m_axis_tvalid , - output wire [N/2*B-1:0] m_axis_tdata - ); - -/*************/ -/* Internals */ -/*************/ - -// Data registers. -reg [N*B-1:0] din_r1 ; -reg [N*B-1:0] din_r2 ; - -// Low/high part. -wire [N/2*B-1:0] din_low ; -wire [N/2*B-1:0] din_high ; - -// Muxed output. -wire [N/2*B-1:0] d_mux ; -reg [N/2*B-1:0] d_mux_r1 ; - -// Valid. -reg valid_r1 ; -reg valid_r2 ; -reg valid_r3 ; -reg valid_r4 ; -wire valid_i ; - -/****************/ -/* Architecture */ -/****************/ - -// Low/high part. -assign din_low = din_r2 [0 +: N/2*B]; -assign din_high = din_r2 [N/2*B +: N/2*B]; - -// Muxed output. -assign d_mux = (valid_r2)? din_low : din_high; - -// Valid. -assign valid_i = valid_r3 || valid_r4; - -// Registers. -always @(posedge aclk) begin - if (~aresetn) begin - // Data registers. - din_r1 <= 0; - din_r2 <= 0; - - d_mux_r1 <= 0; - - // Valid. - valid_r1 <= 0; - valid_r2 <= 0; - valid_r3 <= 0; - valid_r4 <= 0; - end - else begin - // Data registers. - din_r1 <= s_axis_tdata; - if (valid_r1) - din_r2 <= din_r1; - - // Muxed output. - d_mux_r1 <= d_mux; - - // Valid. - valid_r1 <= s_axis_tvalid; - valid_r2 <= valid_r1; - valid_r3 <= valid_r2; - valid_r4 <= valid_r3; - end -end - -// Assign outputs. -assign s_axis_tready = 1'b1 ; -assign m_axis_tvalid = valid_i ; -assign m_axis_tdata = d_mux_r1 ; - -endmodule - diff --git a/qick/firmware/ip/axis_resampler_2x1_v1/src/tb.sv b/qick/firmware/ip/axis_resampler_2x1_v1/src/tb.sv deleted file mode 100644 index bcbbdf2..0000000 --- a/qick/firmware/ip/axis_resampler_2x1_v1/src/tb.sv +++ /dev/null @@ -1,84 +0,0 @@ -module tb(); - -// Number of bits. -parameter B = 8; - -// Number of lanes (input). -parameter N = 4; - -// Reset and clock. -reg aresetn ; -reg aclk ; - -// s_axis_* for input data. -wire s_axis_tready ; -reg s_axis_tvalid ; -reg [N*B-1:0] s_axis_tdata ; - -// m_axis_* for output data. -reg m_axis_tready ; -wire m_axis_tvalid ; -wire [N/2*B-1:0] m_axis_tdata ; - -/**************/ -/* Test Bench */ -/**************/ - -// DUT. -axis_resampler_2x1_v1 - #( - // Number of bits. - .B(B), - - // Number of lanes (input). - .N(N) - ) - DUT - ( - // Reset and clock. - .aclk , - .aresetn , - - // s_axis_* for input data. - .s_axis_tready , - .s_axis_tvalid , - .s_axis_tdata , - - // m_axis_* for output data. - .m_axis_tready , - .m_axis_tvalid , - .m_axis_tdata - ); - -initial begin - // Reset sequence. - aresetn <= 0; - s_axis_tvalid <= 0; - m_axis_tready <= 1; - #500; - aresetn <= 1; - - #1000; - - for (int i=0; i<200; i=i+1) begin - @(posedge aclk); - s_axis_tvalid <= 0; - @(posedge aclk); - @(posedge aclk); - @(posedge aclk); - s_axis_tvalid <= 1; - for (int j=0; j - - user.org - user - axis_set_reg - 1.0 - - - s_axis - - - - - - - TDATA - - - s_axis_tdata - - - - - TSTRB - - - s_axis_tstrb - - - - - TLAST - - - s_axis_tlast - - - - - TVALID - - - s_axis_tvalid - - - - - TREADY - - - s_axis_tready - - - - - - s_axis_aresetn - - - - - - - RST - - - s_axis_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - s_axis_aclk - - - - - - - CLK - - - s_axis_aclk - - - - - - ASSOCIATED_BUSIF - s_axis - - - ASSOCIATED_RESET - s_axis_aresetn - - - - - - - - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis - VHDL - axis_set_reg - - xilinx_anylanguagesynthesis_view_fileset - - - - viewChecksum - 03ba7f93 - - - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - VHDL - axis_set_reg - - xilinx_anylanguagebehavioralsimulation_view_fileset - - - - viewChecksum - 03ba7f93 - - - - - xilinx_xpgui - UI Layout - :vivado.xilinx.com:xgui.ui - - xilinx_xpgui_view_fileset - - - - viewChecksum - 35ebc586 - - - - - - - s_axis_aclk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axis_aresetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axis_tready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axis_tdata - - in - - 15 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axis_tstrb - - in - - 1 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 1 - - - - - s_axis_tlast - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axis_tvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - dout - - out - - 15 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - - DATA_WIDTH - Data Width - 16 - - - - - - choice_list_9d8b0d81 - ACTIVE_HIGH - ACTIVE_LOW - - - - - xilinx_anylanguagesynthesis_view_fileset - - src/axis_set_reg.vhd - vhdlSource - CHECKSUM_03ba7f93 - - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - src/axis_set_reg.vhd - vhdlSource - - - - xilinx_xpgui_view_fileset - - xgui/axis_set_reg_v1_0.tcl - tclSource - CHECKSUM_35ebc586 - XGUI_VERSION_2 - - - - AXIS Set Register Block. - - - DATA_WIDTH - Data Width - 16 - - - Component_Name - axis_set_reg_v1_0 - - - - - - virtex7 - qvirtex7 - kintex7 - kintex7l - qkintex7 - qkintex7l - akintex7 - artix7 - artix7l - aartix7 - qartix7 - zynq - qzynq - azynq - spartan7 - aspartan7 - virtexu - zynquplus - virtexuplus - virtexuplusHBM - kintexuplus - kintexu - - - /UserIP - - AXIS Set Register - package_project - 3 - 2020-12-15T18:32:58Z - - /home/lstefana/v19.1/ip/axis_set_reg - /home/lstefana/v19.1/ip/axis_set_reg - /home/lstefana/v19.1/ip/axis_set_reg - /home/lstefana/v19.1/ip/axis_set_reg - /home/lstefana/v19.1/ip/axis_set_reg - /home/lstefana/v19.1/ip/axis_set_reg - /home/lstefana/v19.1/ip/axis_set_reg - /home/lstefana/v19.1/ip/axis_set_reg - /home/lstefana/v19.1/ip/axis_set_reg - /home/lstefana/v19.1/ip/axis_set_reg - /home/lstefana/v19.1/ip/axis_set_reg - /home/lstefana/v19.1/ip/axis_set_reg - /home/lstefana/v19.1/ip/axis_set_reg - - - - 2019.1 - - - - - - - - diff --git a/qick/firmware/ip/axis_set_reg/src/axis_set_reg.vhd b/qick/firmware/ip/axis_set_reg/src/axis_set_reg.vhd deleted file mode 100644 index cc2e0ea..0000000 --- a/qick/firmware/ip/axis_set_reg/src/axis_set_reg.vhd +++ /dev/null @@ -1,55 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity axis_set_reg is - generic - ( - -- Data width. - DATA_WIDTH : Integer := 16 - ); - port - ( - -- AXIS Slave I/F. - s_axis_aclk : in std_logic; - s_axis_aresetn : in std_logic; - s_axis_tready : out std_logic; - s_axis_tdata : in std_logic_vector(DATA_WIDTH-1 downto 0); - s_axis_tstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); - s_axis_tlast : in std_logic; - s_axis_tvalid : in std_logic; - - -- Output data. - dout : out std_logic_vector (DATA_WIDTH-1 downto 0) - ); -end axis_set_reg; - -architecture rtl of axis_set_reg is - --- Data register. -signal dout_r : std_logic_vector (DATA_WIDTH-1 downto 0); - -begin - --- Registers. -process (s_axis_aclk) -begin - if ( rising_edge(s_axis_aclk) ) then - if ( s_axis_aresetn = '0' ) then - -- Data register. - dout_r <= (others => '0'); - else - -- Data register. - if ( s_axis_tvalid = '1' ) then - dout_r <= s_axis_tdata; - end if; - end if; - end if; -end process; - --- Assign outputs. -s_axis_tready <= '1'; -dout <= dout_r; - -end rtl; - diff --git a/qick/firmware/ip/axis_set_reg/xgui/axis_set_reg_v1_0.tcl b/qick/firmware/ip/axis_set_reg/xgui/axis_set_reg_v1_0.tcl deleted file mode 100644 index 55a2622..0000000 --- a/qick/firmware/ip/axis_set_reg/xgui/axis_set_reg_v1_0.tcl +++ /dev/null @@ -1,25 +0,0 @@ -# Definitional proc to organize widgets for parameters. -proc init_gui { IPINST } { - ipgui::add_param $IPINST -name "Component_Name" - #Adding Page - set Page_0 [ipgui::add_page $IPINST -name "Page 0"] - ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${Page_0} - - -} - -proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { - # Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { - # Procedure called to validate DATA_WIDTH - return true -} - - -proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH} -} - diff --git a/qick/firmware/ip/axis_sg_int4_v1/component.xml b/qick/firmware/ip/axis_sg_int4_v1/component.xml deleted file mode 100644 index 3837c5a..0000000 --- a/qick/firmware/ip/axis_sg_int4_v1/component.xml +++ /dev/null @@ -1,1305 +0,0 @@ - - - user.org - user - axis_sg_int4_v1 - 1.0 - - - m_axis - - - - - - - TDATA - - - m_axis_tdata - - - - - TVALID - - - m_axis_tvalid - - - - - TREADY - - - m_axis_tready - - - - - - s0_axis - - - - - - - TDATA - - - s0_axis_tdata - - - - - TVALID - - - s0_axis_tvalid - - - - - TREADY - - - s0_axis_tready - - - - - - s1_axis - - - - - - - TDATA - - - s1_axis_tdata - - - - - TVALID - - - s1_axis_tvalid - - - - - TREADY - - - s1_axis_tready - - - - - - s_axi - - - - - - - - - AWADDR - - - s_axi_awaddr - - - - - AWPROT - - - s_axi_awprot - - - - - AWVALID - - - s_axi_awvalid - - - - - AWREADY - - - s_axi_awready - - - - - WDATA - - - s_axi_wdata - - - - - WSTRB - - - s_axi_wstrb - - - - - WVALID - - - s_axi_wvalid - - - - - WREADY - - - s_axi_wready - - - - - BRESP - - - s_axi_bresp - - - - - BVALID - - - s_axi_bvalid - - - - - BREADY - - - s_axi_bready - - - - - ARADDR - - - s_axi_araddr - - - - - ARPROT - - - s_axi_arprot - - - - - ARVALID - - - s_axi_arvalid - - - - - ARREADY - - - s_axi_arready - - - - - RDATA - - - s_axi_rdata - - - - - RRESP - - - s_axi_rresp - - - - - RVALID - - - s_axi_rvalid - - - - - RREADY - - - s_axi_rready - - - - - - s_axi_aclk - - - - - - - CLK - - - s_axi_aclk - - - - - - ASSOCIATED_BUSIF - s_axi - - - ASSOCIATED_RESET - s_axi_aresetn - - - - - s_axi_aresetn - - - - - - - RST - - - s_axi_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - s0_axis_aclk - - - - - - - CLK - - - s0_axis_aclk - - - - - - ASSOCIATED_BUSIF - s0_axis - - - ASSOCIATED_RESET - s0_axis_aresetn - - - - - s0_axis_aresetn - - - - - - - RST - - - s0_axis_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - aclk - - - - - - - CLK - - - aclk - - - - - - ASSOCIATED_BUSIF - m_axis:s1_axis - - - ASSOCIATED_RESET - aresetn - - - - - aresetn - - - - - - - RST - - - aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - - - s_axi - - reg0 - 0 - 64 - 32 - register - - - - - - - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis - Verilog - axis_sg_int4_v1 - - xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset - - - xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset - - - xilinx_anylanguagesynthesis_view_fileset - - - - viewChecksum - 95568600 - - - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - Verilog - axis_sg_int4_v1 - - xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset - - - xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - - - viewChecksum - 95568600 - - - - - xilinx_xpgui - UI Layout - :vivado.xilinx.com:xgui.ui - - xilinx_xpgui_view_fileset - - - - viewChecksum - 9465d594 - - - - - - - s_axi_aclk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_aresetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_awaddr - - in - - 5 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_awprot - - in - - 2 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_awvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_awready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_wdata - - in - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_wstrb - - in - - 3 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 1 - - - - - s_axi_wvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_wready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_bresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_bvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_bready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_araddr - - in - - 5 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_arprot - - in - - 2 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_arvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_arready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_rdata - - out - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_rresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_rvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_rready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s0_axis_aclk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s0_axis_aresetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s0_axis_tdata - - in - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s0_axis_tvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s0_axis_tready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - aclk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - aresetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s1_axis_tdata - - in - - 87 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s1_axis_tvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s1_axis_tready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m_axis_tready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 1 - - - - - m_axis_tvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m_axis_tdata - - out - - 127 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - - N - N - 12 - - - - - - choice_list_9d8b0d81 - ACTIVE_HIGH - ACTIVE_LOW - - - - - xilinx_anylanguagesynthesis_view_fileset - - src/fir_0/fir_0.coe - coe - - - src/dds_compiler_0/dds_compiler_0.xci - xci - CELL_NAME_signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/dds_compiler_0 - - - src/fir_0/fir_0.xci - xci - CELL_NAME_signal_gen_top_i/signal_gen_i/fir_i/fir_0 - - - src/latency_reg.v - verilogSource - - - src/signal_gen.v - verilogSource - - - src/signal_gen_top.v - verilogSource - - - src/ctrl.sv - systemVerilogSource - - - src/axi_slv.vhd - vhdlSource - - - src/fifo/bram_dp.vhd - vhdlSource - - - src/fifo/bram_simple_dp.vhd - vhdlSource - - - src/data_writer.vhd - vhdlSource - - - src/fifo/fifo.vhd - vhdlSource - - - src/synchronizer_n.vhd - vhdlSource - - - src/axis_sg_int4_v1.v - verilogSource - CHECKSUM_c287fed2 - - - - xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset - - - - - - - - - - xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset - - - - - - - - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - src/fir_0/fir_0.coe - coe - - - src/dds_compiler_0/dds_compiler_0.xci - xci - CELL_NAME_signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/dds_compiler_0 - - - src/fir_0/fir_0.xci - xci - CELL_NAME_signal_gen_top_i/signal_gen_i/fir_i/fir_0 - - - src/latency_reg.v - verilogSource - - - src/signal_gen.v - verilogSource - - - src/signal_gen_top.v - verilogSource - - - src/ctrl.sv - systemVerilogSource - - - src/axi_slv.vhd - vhdlSource - - - src/fifo/bram_dp.vhd - vhdlSource - - - src/fifo/bram_simple_dp.vhd - vhdlSource - - - src/data_writer.vhd - vhdlSource - - - src/fifo/fifo.vhd - vhdlSource - - - src/synchronizer_n.vhd - vhdlSource - - - src/axis_sg_int4_v1.v - verilogSource - - - - xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset - - - - - - - - - - xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset - - - - - - - - - - xilinx_xpgui_view_fileset - - xgui/axis_sg_int4_v1_v1_0.tcl - tclSource - CHECKSUM_9465d594 - XGUI_VERSION_2 - - - - AXIS Signal Generator with x4 Interpolated Envelope - - - N - N - 12 - - - Component_Name - axis_sg_int4_v1_v1_0 - - - - - - zynquplus - - - /UserIP - - AXIS SG x4 Interpolation - package_project - 6 - 2022-04-07T20:07:10Z - - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - /home/lstefana/v20.2/ip/axis_sg_int4_v1 - - - - 2020.2 - - - - - - - - - diff --git a/qick/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.veo b/qick/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.veo deleted file mode 100644 index 7cfbd51..0000000 --- a/qick/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.veo +++ /dev/null @@ -1,85 +0,0 @@ -// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -// IP VLNV: xilinx.com:ip:axi_vip:1.1 -// IP Revision: 8 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -axi_mst_0 your_instance_name ( - .aclk(aclk), // input wire aclk - .aresetn(aresetn), // input wire aresetn - .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr - .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot - .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid - .m_axi_awready(m_axi_awready), // input wire m_axi_awready - .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata - .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb - .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid - .m_axi_wready(m_axi_wready), // input wire m_axi_wready - .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp - .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid - .m_axi_bready(m_axi_bready), // output wire m_axi_bready - .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr - .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot - .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid - .m_axi_arready(m_axi_arready), // input wire m_axi_arready - .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata - .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp - .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid - .m_axi_rready(m_axi_rready) // output wire m_axi_rready -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file axi_mst_0.v when simulating -// the core, axi_mst_0. When compiling the wrapper file, be sure to -// reference the Verilog simulation library. - diff --git a/qick/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.vho b/qick/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.vho deleted file mode 100644 index a53be60..0000000 --- a/qick/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.vho +++ /dev/null @@ -1,115 +0,0 @@ --- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:axi_vip:1.1 --- IP Revision: 8 - --- The following code must appear in the VHDL architecture header. - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT axi_mst_0 - PORT ( - aclk : IN STD_LOGIC; - aresetn : IN STD_LOGIC; - m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - m_axi_awvalid : OUT STD_LOGIC; - m_axi_awready : IN STD_LOGIC; - m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - m_axi_wvalid : OUT STD_LOGIC; - m_axi_wready : IN STD_LOGIC; - m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - m_axi_bvalid : IN STD_LOGIC; - m_axi_bready : OUT STD_LOGIC; - m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - m_axi_arvalid : OUT STD_LOGIC; - m_axi_arready : IN STD_LOGIC; - m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - m_axi_rvalid : IN STD_LOGIC; - m_axi_rready : OUT STD_LOGIC - ); -END COMPONENT; --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : axi_mst_0 - PORT MAP ( - aclk => aclk, - aresetn => aresetn, - m_axi_awaddr => m_axi_awaddr, - m_axi_awprot => m_axi_awprot, - m_axi_awvalid => m_axi_awvalid, - m_axi_awready => m_axi_awready, - m_axi_wdata => m_axi_wdata, - m_axi_wstrb => m_axi_wstrb, - m_axi_wvalid => m_axi_wvalid, - m_axi_wready => m_axi_wready, - m_axi_bresp => m_axi_bresp, - m_axi_bvalid => m_axi_bvalid, - m_axi_bready => m_axi_bready, - m_axi_araddr => m_axi_araddr, - m_axi_arprot => m_axi_arprot, - m_axi_arvalid => m_axi_arvalid, - m_axi_arready => m_axi_arready, - m_axi_rdata => m_axi_rdata, - m_axi_rresp => m_axi_rresp, - m_axi_rvalid => m_axi_rvalid, - m_axi_rready => m_axi_rready - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file axi_mst_0.vhd when simulating --- the core, axi_mst_0. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/qick/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.xci b/qick/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.xci deleted file mode 100644 index ac9cf04..0000000 --- a/qick/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.xci +++ /dev/null @@ -1,200 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - axi_mst_0 - - - ACTIVE_LOW - - 100000000 - 0 - 0 - 0.000 - 32 - 0 - 0 - 0 - - 32 - 100000000 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 32 - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 0 - 2 - 32 - 0 - 0 - 0 - 32 - 0 - 0 - 32 - 0 - 0 - 0 - axi_mst_0 - 32 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 0 - 0 - 1 - 0 - MASTER - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - zynquplusRFSOC - xilinx.com:zcu216:part0:2.0 - - xczu49dr - ffvf1760 - VERILOG - - MIXED - -2 - - E - TRUE - TRUE - IP_Flow - 8 - TRUE - . - - . - 2020.2 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/qick/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.xml b/qick/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.xml deleted file mode 100644 index 7be1f50..0000000 --- a/qick/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.xml +++ /dev/null @@ -1,4760 +0,0 @@ - - - xilinx.com - customized_ip - axi_mst_0 - 1.0 - - - M_AXI - - - - - - - - - ARADDR - - - m_axi_araddr - - - - - ARBURST - - - m_axi_arburst - - - - - ARCACHE - - - m_axi_arcache - - - - - ARID - - - m_axi_arid - - - - - ARLEN - - - m_axi_arlen - - - - - ARLOCK - - - m_axi_arlock - - - - - ARPROT - - - m_axi_arprot - - - - - ARQOS - - - m_axi_arqos - - - - - ARREADY - - - m_axi_arready - - - - - ARREGION - - - m_axi_arregion - - - - - ARSIZE - - - m_axi_arsize - - - - - ARUSER - - - m_axi_aruser - - - - - ARVALID - - - m_axi_arvalid - - - - - AWADDR - - - m_axi_awaddr - - - - - AWBURST - - - m_axi_awburst - - - - - AWCACHE - - - m_axi_awcache - - - - - AWID - - - m_axi_awid - - - - - AWLEN - - - m_axi_awlen - - - - - AWLOCK - - - m_axi_awlock - - - - - AWPROT - - - m_axi_awprot - - - - - AWQOS - - - m_axi_awqos - - - - - AWREADY - - - m_axi_awready - - - - - AWREGION - - - m_axi_awregion - - - - - AWSIZE - - - m_axi_awsize - - - - - AWUSER - - - m_axi_awuser - - - - - AWVALID - - - m_axi_awvalid - - - - - BID - - - m_axi_bid - - - - - BREADY - - - m_axi_bready - - - - - BRESP - - - m_axi_bresp - - - - - BUSER - - - m_axi_buser - - - - - BVALID - - - m_axi_bvalid - - - - - RDATA - - - m_axi_rdata - - - - - RID - - - m_axi_rid - - - - - RLAST - - - m_axi_rlast - - - - - RREADY - - - m_axi_rready - - - - - RRESP - - - m_axi_rresp - - - - - RUSER - - - m_axi_ruser - - - - - RVALID - - - m_axi_rvalid - - - - - WDATA - - - m_axi_wdata - - - - - WID - - - m_axi_wid - - - - - WLAST - - - m_axi_wlast - - - - - WREADY - - - m_axi_wready - - - - - WSTRB - - - m_axi_wstrb - - - - - WUSER - - - m_axi_wuser - - - - - WVALID - - - m_axi_wvalid - - - - - - DATA_WIDTH - 32 - - - simulation.tlm - - - - - PROTOCOL - AXI4LITE - - - simulation.tlm - - - - - FREQ_HZ - 100000000 - - - simulation.tlm - - - - - ID_WIDTH - 0 - - - simulation.tlm - - - - - ADDR_WIDTH - 32 - - - simulation.tlm - - - - - AWUSER_WIDTH - 0 - - - simulation.tlm - - - - - ARUSER_WIDTH - 0 - - - simulation.tlm - - - - - WUSER_WIDTH - 0 - - - simulation.tlm - - - - - RUSER_WIDTH - 0 - - - simulation.tlm - - - - - BUSER_WIDTH - 0 - - - simulation.tlm - - - - - READ_WRITE_MODE - READ_WRITE - - - simulation.tlm - - - - - HAS_BURST - 0 - - - simulation.tlm - - - - - HAS_LOCK - 0 - - - simulation.tlm - - - - - HAS_PROT - 1 - - - simulation.tlm - - - - - HAS_CACHE - 0 - - - simulation.tlm - - - - - HAS_QOS - 0 - - - simulation.tlm - - - - - HAS_REGION - 0 - - - simulation.tlm - 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xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_arvalid - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - m_axi_arready - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - true - - - - - - m_axi_rid - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - m_axi_rdata - - in - - 31 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - true - - - - - - m_axi_rresp - - in - - 1 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - true - - - - - - m_axi_rlast - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - m_axi_ruser - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - m_axi_rvalid - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - true - - - - - - m_axi_rready - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - M_INITIATOR_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - M_INITIATOR_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - S_TARGET_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - wr_socket - - - - - - - 1 - - - - - S_TARGET_rd_socket - AXIMM Read Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - rd_socket - - - - - - - 1 - - - - - - - C_AXI_PROTOCOL - 2 - - - C_AXI_INTERFACE_MODE - 0 - - - C_AXI_ADDR_WIDTH - 32 - - - C_AXI_WDATA_WIDTH - 32 - - - C_AXI_RDATA_WIDTH - 32 - - - C_AXI_WID_WIDTH - 0 - - - C_AXI_RID_WIDTH - 0 - - - C_AXI_AWUSER_WIDTH - 0 - - - C_AXI_ARUSER_WIDTH - 0 - - - C_AXI_WUSER_WIDTH - 0 - - - C_AXI_RUSER_WIDTH - 0 - - - C_AXI_BUSER_WIDTH - 0 - - - C_AXI_SUPPORTS_NARROW - 0 - - - C_AXI_HAS_BURST - 0 - - - C_AXI_HAS_LOCK - 0 - - - C_AXI_HAS_CACHE - 0 - - - C_AXI_HAS_REGION - 0 - - - C_AXI_HAS_PROT - 1 - - - C_AXI_HAS_QOS - 0 - - - C_AXI_HAS_WSTRB - 1 - - - C_AXI_HAS_BRESP - 1 - - - C_AXI_HAS_RRESP - 1 - - - C_AXI_HAS_ARESETN - 1 - - - - - - choice_list_04fafd91 - AXI3 - AXI4 - AXI4LITE - - - choice_list_6240decd - READ_ONLY - READ_WRITE - WRITE_ONLY - - - choice_list_642e7122 - MASTER - PASS_THROUGH - SLAVE - - - choice_list_99ba8646 - 32 - 64 - - - choice_list_9d8b0d81 - ACTIVE_HIGH - ACTIVE_LOW - - - choice_pairs_0fc128e8 - 0 - 0 - - - - - xilinx_veriloginstantiationtemplate_view_fileset - - axi_mst_0.vho - vhdlTemplate - - - axi_mst_0.veo - verilogTemplate - - - - xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset - - hdl/axi_infrastructure_v1_1_0.vh - verilogSource - true - axi_infrastructure_v1_1_0 - - - hdl/axi_infrastructure_v1_1_vl_rfs.v - verilogSource - axi_infrastructure_v1_1_0 - - - - - - - - - - - xilinx_verilogsynthesis_view_fileset - - hdl/axi_vip_v1_1_vlsyn_rfs.sv - systemVerilogSource - axi_vip_v1_1_8 - - - - xilinx_synthesisconstraints_view_fileset - - axi_mst_0_ooc.xdc - xdc - USED_IN_implementation - USED_IN_out_of_context - USED_IN_synthesis - - - - xilinx_verilogsynthesiswrapper_view_fileset - - synth/axi_mst_0.sv - systemVerilogSource - xil_defaultlib - - - - xilinx_versioninformation_view_fileset - - doc/axi_vip_v1_1_changelog.txt - text - axi_vip_v1_1_8 - - - - xilinx_externalfiles_view_fileset - - axi_mst_0.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - axi_mst_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - axi_mst_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - axi_mst_0_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - axi_mst_0_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - - xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset - - hdl/axi_infrastructure_v1_1_0.vh - verilogSource - USED_IN_ipstatic - true - axi_infrastructure_v1_1_0 - - - hdl/axi_infrastructure_v1_1_vl_rfs.v - verilogSource - USED_IN_ipstatic - axi_infrastructure_v1_1_0 - - - - - - - - - - - xilinx_verilogbehavioralsimulation_view_fileset - - sim/axi_mst_0_pkg.sv - systemVerilogSource - - - hdl/axi_vip_v1_1_vl_rfs.sv - systemVerilogSource - USED_IN_ipstatic - axi_vip_v1_1_8 - - - - xilinx_systemcsimulation_view_fileset - - sysc/axi_vip.cpp - systemCSource - axi_vip_v1_1_8 - - - sysc/axi_vip.h - systemCSource - true - axi_vip_v1_1_8 - - - - xilinx_verilogsimulationwrapper_view_fileset - - sim/axi_mst_0.sv - systemVerilogSource - xil_defaultlib - - - - xilinx_systemcsimulationwrapper_view_fileset - - sim/axi_mst_0_sc.h - systemCSource - true - - - sim/axi_mst_0_sc.cpp - systemCSource - - - sim/axi_mst_0.h - systemCSource - true - - - sim/axi_mst_0.cpp - systemCSource - - - sim/axi_mst_0_stub.sv - systemVerilogSource - - - - The AXI Verification IP. - - - Component_Name - Component Name - axi_mst_0 - - - PROTOCOL - PROTOCOL - AXI4LITE - - - READ_WRITE_MODE - READ_WRITE MODE - READ_WRITE - - - INTERFACE_MODE - INTERFACE MODE - MASTER - - - ADDR_WIDTH - ADDRESS WIDTH - 32 - - - DATA_WIDTH - DATA WIDTH - 32 - - - ID_WIDTH - ID WIDTH - 0 - - - - false - - - - - - AWUSER_WIDTH - AWUSER WIDTH - 0 - - - - false - - - - - - ARUSER_WIDTH - ARUSER WIDTH - 0 - - - - false - - - - - - RUSER_WIDTH - RUSER WIDTH - 0 - - - - false - - - - - - WUSER_WIDTH - WUSER WIDTH - 0 - - - - false - - - - - - BUSER_WIDTH - BUSER WIDTH - 0 - - - - false - - - - - - WUSER_BITS_PER_BYTE - WUSER BITS PER BYTE - 0 - - - - false - - - - - - RUSER_BITS_PER_BYTE - RUSER BITS PER BYTE - 0 - - - - false - - - - - - HAS_USER_BITS_PER_BYTE - HAS USER_BITS_PER_BYTE - 0 - - - - false - - - - - - SUPPORTS_NARROW - SUPPORTS NARROW - 0 - - - - false - - - - - - HAS_SIZE - HAS SIZE - 0 - - - - false - - - - - - HAS_BURST - HAS BURST - 0 - - - - false - - - - - - HAS_LOCK - HAS LOCK - 0 - - - - false - - - - - - HAS_CACHE - HAS CACHE - 0 - - - - false - - - - - - HAS_REGION - HAS REGION - 0 - - - - false - - - - - - HAS_QOS - HAS QOS - 0 - - - - false - - - - - - HAS_PROT - HAS PROT - 1 - - - HAS_WSTRB - HAS WSTRB - 1 - - - HAS_BRESP - HAS BRESP - 1 - - - HAS_RRESP - HAS RRESP - 1 - - - HAS_ACLKEN - HAS ACLKEN - 0 - - - HAS_ARESETN - HAS ARESETN - 1 - - - - - AXI Verification IP - - xtlm - - 8 - true - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2020.2 - - - - - - - - - - diff --git a/qick/firmware/ip/axis_sg_int4_v1/src/axi_slv.vhd b/qick/firmware/ip/axis_sg_int4_v1/src/axi_slv.vhd deleted file mode 100644 index c60ea98..0000000 --- a/qick/firmware/ip/axis_sg_int4_v1/src/axi_slv.vhd +++ /dev/null @@ -1,516 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity axi_slv is - Generic - ( - DATA_WIDTH : integer := 32; - ADDR_WIDTH : integer := 6 - ); - Port - ( - aclk : in std_logic; - aresetn : in std_logic; - - -- Write Address Channel. - awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); - awprot : in std_logic_vector(2 downto 0); - awvalid : in std_logic; - awready : out std_logic; - - -- Write Data Channel. - wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); - wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); - wvalid : in std_logic; - wready : out std_logic; - - -- Write Response Channel. - bresp : out std_logic_vector(1 downto 0); - bvalid : out std_logic; - bready : in std_logic; - - -- Read Address Channel. - araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); - arprot : in std_logic_vector(2 downto 0); - arvalid : in std_logic; - arready : out std_logic; - - -- Read Data Channel. - rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); - rresp : out std_logic_vector(1 downto 0); - rvalid : out std_logic; - rready : in std_logic; - - -- Registers. - START_ADDR_REG : out std_logic_vector (31 downto 0); - WE_REG : out std_logic - ); -end axi_slv; - -architecture rtl of axi_slv is - - -- AXI4LITE signals - signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); - signal axi_awready : std_logic; - signal axi_wready : std_logic; - signal axi_bresp : std_logic_vector(1 downto 0); - signal axi_bvalid : std_logic; - signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); - signal axi_arready : std_logic; - signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); - signal axi_rresp : std_logic_vector(1 downto 0); - signal axi_rvalid : std_logic; - - -- Example-specific design signals - -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH - -- ADDR_LSB is used for addressing 32/64 bit registers/memories - -- ADDR_LSB = 2 for 32 bits (n downto 2) - -- ADDR_LSB = 3 for 64 bits (n downto 3) - constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; - constant OPT_MEM_ADDR_BITS : integer := 3; - ------------------------------------------------ - ---- Signals for user logic register space example - -------------------------------------------------- - ---- Number of Slave Registers 16 - signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg_rden : std_logic; - signal slv_reg_wren : std_logic; - signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); - signal byte_index : integer; - signal aw_en : std_logic; - -begin - -- I/O Connections assignments - - awreadY <= axi_awready; - wready <= axi_wready; - bresp <= axi_bresp; - bvalid <= axi_bvalid; - arreadY <= axi_arready; - rdata <= axi_rdata; - rresp <= axi_rresp; - rvalid <= axi_rvalid; - -- Implement axi_awready generation - -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is - -- de-asserted when reset is low. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_awready <= '0'; - aw_en <= '1'; - else - if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then - -- slave is ready to accept write address when - -- there is a valid write address and write data - -- on the write address and data bus. This design - -- expects no outstanding transactions. - axi_awready <= '1'; - aw_en <= '0'; - elsif (bready = '1' and axi_bvalid = '1') then - aw_en <= '1'; - axi_awready <= '0'; - else - axi_awready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement axi_awaddr latching - -- This process is used to latch the address when both - -- S_AXI_AWVALID and S_AXI_WVALID are valid. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_awaddr <= (others => '0'); - else - if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then - -- Write Address latching - axi_awaddr <= awaddr; - end if; - end if; - end if; - end process; - - -- Implement axi_wready generation - -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is - -- de-asserted when reset is low. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_wready <= '0'; - else - if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then - -- slave is ready to accept write data when - -- there is a valid write address and write data - -- on the write address and data bus. This design - -- expects no outstanding transactions. - axi_wready <= '1'; - else - axi_wready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement memory mapped register select and write logic generation - -- The write data is accepted and written to memory mapped registers when - -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to - -- select byte enables of slave registers while writing. - -- These registers are cleared when reset (active low) is applied. - -- Slave register write enable is asserted when valid address and data are available - -- and the slave is ready to accept the write address and write data. - slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; - - process (aclk) - variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); - begin - if rising_edge(aclk) then - if aresetn = '0' then - slv_reg0 <= (others => '0'); - slv_reg1 <= (others => '0'); - slv_reg2 <= (others => '0'); - slv_reg3 <= (others => '0'); - slv_reg4 <= (others => '0'); - slv_reg5 <= (others => '0'); - slv_reg6 <= (others => '0'); - slv_reg7 <= (others => '0'); - slv_reg8 <= (others => '0'); - slv_reg9 <= (others => '0'); - slv_reg10 <= (others => '0'); - slv_reg11 <= (others => '0'); - slv_reg12 <= (others => '0'); - slv_reg13 <= (others => '0'); - slv_reg14 <= (others => '0'); - slv_reg15 <= (others => '0'); - else - loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); - if (slv_reg_wren = '1') then - case loc_addr is - when b"0000" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 0 - slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0001" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 1 - slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0010" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 2 - slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0011" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 3 - slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0100" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 4 - slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0101" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 5 - slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0110" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 6 - slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0111" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 7 - slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1000" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 8 - slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1001" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 9 - slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1010" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 10 - slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1011" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 11 - slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1100" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 12 - slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1101" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 13 - slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1110" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 14 - slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1111" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 15 - slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when others => - slv_reg0 <= slv_reg0; - slv_reg1 <= slv_reg1; - slv_reg2 <= slv_reg2; - slv_reg3 <= slv_reg3; - slv_reg4 <= slv_reg4; - slv_reg5 <= slv_reg5; - slv_reg6 <= slv_reg6; - slv_reg7 <= slv_reg7; - slv_reg8 <= slv_reg8; - slv_reg9 <= slv_reg9; - slv_reg10 <= slv_reg10; - slv_reg11 <= slv_reg11; - slv_reg12 <= slv_reg12; - slv_reg13 <= slv_reg13; - slv_reg14 <= slv_reg14; - slv_reg15 <= slv_reg15; - end case; - end if; - end if; - end if; - end process; - - -- Implement write response logic generation - -- The write response and response valid signals are asserted by the slave - -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. - -- This marks the acceptance of address and indicates the status of - -- write transaction. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_bvalid <= '0'; - axi_bresp <= "00"; --need to work more on the responses - else - if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then - axi_bvalid <= '1'; - axi_bresp <= "00"; - elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) - axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) - end if; - end if; - end if; - end process; - - -- Implement axi_arready generation - -- axi_arready is asserted for one S_AXI_ACLK clock cycle when - -- S_AXI_ARVALID is asserted. axi_awready is - -- de-asserted when reset (active low) is asserted. - -- The read address is also latched when S_AXI_ARVALID is - -- asserted. axi_araddr is reset to zero on reset assertion. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_arready <= '0'; - axi_araddr <= (others => '1'); - else - if (axi_arready = '0' and arvalid = '1') then - -- indicates that the slave has acceped the valid read address - axi_arready <= '1'; - -- Read Address latching - axi_araddr <= araddr; - else - axi_arready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement axi_arvalid generation - -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_ARVALID and axi_arready are asserted. The slave registers - -- data are available on the axi_rdata bus at this instance. The - -- assertion of axi_rvalid marks the validity of read data on the - -- bus and axi_rresp indicates the status of read transaction.axi_rvalid - -- is deasserted on reset (active low). axi_rresp and axi_rdata are - -- cleared to zero on reset (active low). - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_rvalid <= '0'; - axi_rresp <= "00"; - else - if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then - -- Valid read data is available at the read data bus - axi_rvalid <= '1'; - axi_rresp <= "00"; -- 'OKAY' response - elsif (axi_rvalid = '1' and rready = '1') then - -- Read data is accepted by the master - axi_rvalid <= '0'; - end if; - end if; - end if; - end process; - - -- Implement memory mapped register select and read logic generation - -- Slave register read enable is asserted when valid address is available - -- and the slave is ready to accept the read address. - slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; - - process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) - variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); - begin - -- Address decoding for reading registers - loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); - case loc_addr is - when b"0000" => - reg_data_out <= slv_reg0; - when b"0001" => - reg_data_out <= slv_reg1; - when b"0010" => - reg_data_out <= slv_reg2; - when b"0011" => - reg_data_out <= slv_reg3; - when b"0100" => - reg_data_out <= slv_reg4; - when b"0101" => - reg_data_out <= slv_reg5; - when b"0110" => - reg_data_out <= slv_reg6; - when b"0111" => - reg_data_out <= slv_reg7; - when b"1000" => - reg_data_out <= slv_reg8; - when b"1001" => - reg_data_out <= slv_reg9; - when b"1010" => - reg_data_out <= slv_reg10; - when b"1011" => - reg_data_out <= slv_reg11; - when b"1100" => - reg_data_out <= slv_reg12; - when b"1101" => - reg_data_out <= slv_reg13; - when b"1110" => - reg_data_out <= slv_reg14; - when b"1111" => - reg_data_out <= slv_reg15; - when others => - reg_data_out <= (others => '0'); - end case; - end process; - - -- Output register or memory read data - process( aclk ) is - begin - if (rising_edge (aclk)) then - if ( aresetn = '0' ) then - axi_rdata <= (others => '0'); - else - if (slv_reg_rden = '1') then - -- When there is a valid read address (S_AXI_ARVALID) with - -- acceptance of read address by the slave (axi_arready), - -- output the read dada - -- Read address mux - axi_rdata <= reg_data_out; -- register read data - end if; - end if; - end if; - end process; - - -- Register Map. - -- 0 : START_ADDR_REG : 32-bit. Start address to write into memory. - -- 1 : WE_REG : 1-bit. Enable write into memory. - - -- Output Registers. - START_ADDR_REG <= slv_reg0; - WE_REG <= slv_reg1(0); - -end rtl; - diff --git a/qick/firmware/ip/axis_sg_int4_v1/src/axis_sg_int4_v1.v b/qick/firmware/ip/axis_sg_int4_v1/src/axis_sg_int4_v1.v deleted file mode 100644 index f913b85..0000000 --- a/qick/firmware/ip/axis_sg_int4_v1/src/axis_sg_int4_v1.v +++ /dev/null @@ -1,197 +0,0 @@ -// Signal Generator V4. -// s_axi_aclk : clock for s_axi_* -// s0_axis_aclk : clock for s0_axis_* -// aclk : clock for s1_axis_* and m_axis_* -// -module axis_sg_int4_v1 - ( - // AXI Slave I/F for configuration. - s_axi_aclk , - s_axi_aresetn , - - s_axi_awaddr , - s_axi_awprot , - s_axi_awvalid , - s_axi_awready , - - s_axi_wdata , - s_axi_wstrb , - s_axi_wvalid , - s_axi_wready , - - s_axi_bresp , - s_axi_bvalid , - s_axi_bready , - - s_axi_araddr , - s_axi_arprot , - s_axi_arvalid , - s_axi_arready , - - s_axi_rdata , - s_axi_rresp , - s_axi_rvalid , - s_axi_rready , - - // AXIS Slave to load memory samples. - s0_axis_aclk , - s0_axis_aresetn , - s0_axis_tdata , - s0_axis_tvalid , - s0_axis_tready , - - // s1_* and m_* reset/clock. - aclk , - aresetn , - - // AXIS Slave to queue waveforms. - s1_axis_tdata , - s1_axis_tvalid , - s1_axis_tready , - - // AXIS Master for output. - m_axis_tready , - m_axis_tvalid , - m_axis_tdata - ); - -/**************/ -/* Parameters */ -/**************/ -parameter N = 12; - -// Number of parallel dds blocks. -localparam [31:0] N_DDS = 4; - -/*********/ -/* Ports */ -/*********/ -input s_axi_aclk; -input s_axi_aresetn; - -input [5:0] s_axi_awaddr; -input [2:0] s_axi_awprot; -input s_axi_awvalid; -output s_axi_awready; - -input [31:0] s_axi_wdata; -input [3:0] s_axi_wstrb; -input s_axi_wvalid; -output s_axi_wready; - -output [1:0] s_axi_bresp; -output s_axi_bvalid; -input s_axi_bready; - -input [5:0] s_axi_araddr; -input [2:0] s_axi_arprot; -input s_axi_arvalid; -output s_axi_arready; - -output [31:0] s_axi_rdata; -output [1:0] s_axi_rresp; -output s_axi_rvalid; -input s_axi_rready; - -input s0_axis_aclk; -input s0_axis_aresetn; -input [31:0] s0_axis_tdata; -input s0_axis_tvalid; -output s0_axis_tready; - -input aresetn; -input aclk; - -input [87:0] s1_axis_tdata; -input s1_axis_tvalid; -output s1_axis_tready; - -input m_axis_tready; -output m_axis_tvalid; -output [4*32-1:0] m_axis_tdata; - -/********************/ -/* Internal signals */ -/********************/ -// Registers. -wire [31:0] START_ADDR_REG; -wire WE_REG; - -/**********************/ -/* Begin Architecture */ -/**********************/ -// AXI Slave. -axi_slv axi_slv_i - ( - .aclk (s_axi_aclk ), - .aresetn (s_axi_aresetn ), - - // Write Address Channel. - .awaddr (s_axi_awaddr ), - .awprot (s_axi_awprot ), - .awvalid (s_axi_awvalid ), - .awready (s_axi_awready ), - - // Write Data Channel. - .wdata (s_axi_wdata ), - .wstrb (s_axi_wstrb ), - .wvalid (s_axi_wvalid ), - .wready (s_axi_wready ), - - // Write Response Channel. - .bresp (s_axi_bresp ), - .bvalid (s_axi_bvalid ), - .bready (s_axi_bready ), - - // Read Address Channel. - .araddr (s_axi_araddr ), - .arprot (s_axi_arprot ), - .arvalid (s_axi_arvalid ), - .arready (s_axi_arready ), - - // Read Data Channel. - .rdata (s_axi_rdata ), - .rresp (s_axi_rresp ), - .rvalid (s_axi_rvalid ), - .rready (s_axi_rready ), - - // Registers. - .START_ADDR_REG (START_ADDR_REG ), - .WE_REG (WE_REG ) - ); - -signal_gen_top - #( - .N (N ), - .N_DDS (N_DDS ) - ) - signal_gen_top_i - ( - // Reset and clock. - .aresetn (aresetn ), - .aclk (aclk ), - - // AXIS Slave to load memory samples. - .s0_axis_aresetn (s0_axis_aresetn ), - .s0_axis_aclk (s0_axis_aclk ), - .s0_axis_tdata_i (s0_axis_tdata ), - .s0_axis_tvalid_i (s0_axis_tvalid ), - .s0_axis_tready_o (s0_axis_tready ), - - // AXIS Slave to queue waveforms. - .s1_axis_tdata_i (s1_axis_tdata ), - .s1_axis_tvalid_i (s1_axis_tvalid ), - .s1_axis_tready_o (s1_axis_tready ), - - // M_AXIS for output. - .m_axis_tready_i (m_axis_tready ), - .m_axis_tvalid_o (m_axis_tvalid ), - .m_axis_tdata_o (m_axis_tdata ), - - // Registers. - .START_ADDR_REG (START_ADDR_REG ), - .WE_REG (WE_REG ) - ); - -endmodule - diff --git a/qick/firmware/ip/axis_sg_int4_v1/src/bram.v b/qick/firmware/ip/axis_sg_int4_v1/src/bram.v deleted file mode 100644 index 018317e..0000000 --- a/qick/firmware/ip/axis_sg_int4_v1/src/bram.v +++ /dev/null @@ -1,33 +0,0 @@ -module bram (clk,ena,wea,addra,dia,doa); - -// Memory address size. -parameter N = 16; -// Data width. -parameter B = 16; - -input clk; -input ena; -input wea; -input [N-1:0] addra; -input [B-1:0] dia; -output [B-1:0] doa; - -// Ram type. -reg [B-1:0] RAM [0:2**N-1]; -reg [B-1:0] doa; - -always @(posedge clk) -begin - if (ena) - begin - if (wea) begin - RAM[addra] <= dia; - end - else begin - doa <= RAM[addra]; - end - end -end - -endmodule - diff --git a/qick/firmware/ip/axis_sg_int4_v1/src/ctrl.sv b/qick/firmware/ip/axis_sg_int4_v1/src/ctrl.sv deleted file mode 100644 index 0cfd01a..0000000 --- a/qick/firmware/ip/axis_sg_int4_v1/src/ctrl.sv +++ /dev/null @@ -1,499 +0,0 @@ -//Format of waveform interface: -// |-------|---------|------|----------|----------|----------|----------|----------|---------| -// | 84 | 83 | 82 | 81 .. 80 | 79 .. 64 | 63 .. 48 | 47 .. 32 | 31 .. 16 | 15 .. 0 | -// |-------|---------|------|----------|----------|----------|----------|----------|---------| -// | phrst | stdysel | mode | outsel | nsamp | gain | addr | phase | freq | -// |-------|---------|------|----------|----------|----------|----------|----------|---------| -// freq : 16 bits -// phase : 16 bits -// addr : 16 bits -// gain : 16 bits -// nsamp : 16 bits -// outsel : 2 bits -// mode : 1 bit -// stdysel : 1 bit -// phrst : 1 bit -// -// Total : 85. -module ctrl ( - // Reset and clock. - rstn , - clk , - - // Fifo interface. - fifo_rd_en_o , - fifo_empty_i , - fifo_dout_i , - - // dds control. - dds_ctrl_o , - - // memory control. - mem_addr_o , - - // gain. - gain_o , - - // Output source selection. - src_o , - - // Steady value selection. - stdy_o , - - // Output enable. - en_o ); - -// Memory address size. -parameter N = 16; - -// Number of parallel dds blocks. -parameter [31:0] N_DDS = 16; - -// Ports. -input rstn; -input clk; -output fifo_rd_en_o; -input fifo_empty_i; -input [84:0] fifo_dout_i; -output [N_DDS*40-1:0] dds_ctrl_o; -output [N-1:0] mem_addr_o; -output [15:0] gain_o; -output [1:0] src_o; -output stdy_o; -output en_o; - -// States. -typedef enum { READ_ST , - CNT_ST - } state_t; - -// State register. -(* fsm_encoding = "one_hot" *) state_t state; - -// Fifo dout register. -reg [84:0] fifo_dout_r; - -// Non-stop counter for time calculation (adds N_DDS samples each clock tick). -reg [15:0] cnt_n; -reg [15:0] cnt_n_reg; - -// Pinc/phase. -wire [15:0] pinc_int; -reg [15:0] pinc_r1; -reg [15:0] pinc_r2; -wire [15:0] pinc_N; -reg [15:0] pinc_N_r1; -reg [15:0] pinc_N_r2; -reg [15:0] pinc_N_r3; -reg [15:0] pinc_N_r4; -reg [15:0] pinc_N_r5; -wire [15:0] pinc_Nm; -reg [15:0] pinc_Nm_r1; -reg [15:0] pinc_Nm_r2; -reg [15:0] pinc_Nm_r3; - -wire [15:0] phase_int; -reg [15:0] phase_r1; -reg [15:0] phase_r2; -reg [15:0] phase_r3; -reg [15:0] phase_r4; -reg [15:0] phase_r5; -wire [15:0] phase_0; -reg [15:0] phase_0_r1; - -// Phase vectors. -wire [15:0] phase_v0 [0:N_DDS-1]; -reg [15:0] phase_v0_r1 [0:N_DDS-1]; -reg [15:0] phase_v0_r2 [0:N_DDS-1]; -reg [15:0] phase_v0_r3 [0:N_DDS-1]; -reg [15:0] phase_v0_r4 [0:N_DDS-1]; -wire [15:0] phase_v1 [0:N_DDS-1]; -reg [15:0] phase_v1_r1 [0:N_DDS-1]; - -// sync. -reg sync_reg; -reg sync_reg_r1; -reg sync_reg_r2; -reg sync_reg_r3; -reg sync_reg_r4; -reg sync_reg_r5; -reg sync_reg_r6; -reg sync_reg_r7; - -// Address. -wire [15:0] addr_int; -reg [15:0] addr_cnt; -reg [15:0] addr_cnt_r1; -reg [15:0] addr_cnt_r2; -reg [15:0] addr_cnt_r3; -reg [15:0] addr_cnt_r4; -reg [15:0] addr_cnt_r5; -reg [15:0] addr_cnt_r6; - -// Gain. -wire [15:0] gain_int; -reg [15:0] gain_r1; -reg [15:0] gain_r2; -reg [15:0] gain_r3; -reg [15:0] gain_r4; -reg [15:0] gain_r5; -reg [15:0] gain_r6; -reg [15:0] gain_r7; - -// Number of samples. -wire [15:0] nsamp_int; - -// Output selection. -wire [1:0] outsel_int; -reg [1:0] outsel_r1; -reg [1:0] outsel_r2; -reg [1:0] outsel_r3; -reg [1:0] outsel_r4; -reg [1:0] outsel_r5; -reg [1:0] outsel_r6; -reg [1:0] outsel_r7; - -// Mode. -wire mode_int; - -// Steady value selection. -wire stdysel_int; -reg stdysel_r1; -reg stdysel_r2; -reg stdysel_r3; -reg stdysel_r4; -reg stdysel_r5; -reg stdysel_r6; -reg stdysel_r7; - -// Phase reset. -wire phrst_int; - -// Load enable flag. -wire load_int; -reg load_r; - -// Fifo Read Enable. -reg rd_en_int; -reg rd_en_r1; -reg rd_en_r2; - -// Counter. -reg [31:0] cnt; - -// Output enable register. -reg en_reg; -reg en_reg_r1; -reg en_reg_r2; -reg en_reg_r3; -reg en_reg_r4; -reg en_reg_r5; -reg en_reg_r6; -reg en_reg_r7; -reg en_reg_r8; - -// Registers. -always @(posedge clk) begin - if (~rstn) begin - // State register. - state <= READ_ST; - - // Fifo dout register. - fifo_dout_r <= 0; - - // Non-stop counter for time calculation. - cnt_n <= 0; - cnt_n_reg <= 0; - - // Pinc/phase/sync. - pinc_r1 <= 0; - pinc_r2 <= 0; - pinc_N_r1 <= 0; - pinc_N_r2 <= 0; - pinc_N_r3 <= 0; - pinc_N_r4 <= 0; - pinc_N_r5 <= 0; - pinc_Nm_r1 <= 0; - pinc_Nm_r2 <= 0; - pinc_Nm_r3 <= 0; - - phase_r1 <= 0; - phase_r2 <= 0; - phase_r3 <= 0; - phase_r4 <= 0; - phase_r5 <= 0; - phase_0_r1 <= 0; - - sync_reg <= 0; - sync_reg_r1 <= 0; - sync_reg_r2 <= 0; - sync_reg_r3 <= 0; - sync_reg_r4 <= 0; - sync_reg_r5 <= 0; - sync_reg_r6 <= 0; - sync_reg_r7 <= 0; - - // Address. - addr_cnt <= 0; - addr_cnt_r1 <= 0; - addr_cnt_r2 <= 0; - addr_cnt_r3 <= 0; - addr_cnt_r4 <= 0; - addr_cnt_r5 <= 0; - addr_cnt_r6 <= 0; - - // Gain. - gain_r1 <= 0; - gain_r2 <= 0; - gain_r3 <= 0; - gain_r4 <= 0; - gain_r5 <= 0; - gain_r6 <= 0; - gain_r7 <= 0; - - // Output selection. - outsel_r1 <= 0; - outsel_r2 <= 0; - outsel_r3 <= 0; - outsel_r4 <= 0; - outsel_r5 <= 0; - outsel_r6 <= 0; - outsel_r7 <= 0; - - // Steady value selection. - stdysel_r1 <= 0; - stdysel_r2 <= 0; - stdysel_r3 <= 0; - stdysel_r4 <= 0; - stdysel_r5 <= 0; - stdysel_r6 <= 0; - stdysel_r7 <= 0; - - // Load enable flag. - load_r <= 0; - - // Fifo Read Enable. - rd_en_r1 <= 0; - rd_en_r2 <= 0; - - // Counter. - cnt <= 0; - - // Output enable register. - en_reg <= 0; - en_reg_r1 <= 0; - en_reg_r2 <= 0; - en_reg_r3 <= 0; - en_reg_r4 <= 0; - en_reg_r5 <= 0; - en_reg_r6 <= 0; - en_reg_r7 <= 0; - en_reg_r8 <= 0; - end - else begin - // State register. - case (state) - READ_ST: - if (mode_int || ~fifo_empty_i) - state <= CNT_ST; - CNT_ST: - if ( cnt == nsamp_int-2 ) - state <= READ_ST; - endcase - - // Fifo dout register. - if (load_r) - fifo_dout_r <= fifo_dout_i; - - // Non-stop counter for time calculation. - if (sync_reg == 1'b1 && phrst_int == 1'b1) - cnt_n <= 0; - else - cnt_n <= cnt_n + N_DDS; - - if (sync_reg_r1 == 1'b1) - cnt_n_reg <= cnt_n; - - // Pinc/phase/sync. - pinc_r1 <= pinc_int; - pinc_r2 <= pinc_r1; - pinc_N_r1 <= pinc_N; - pinc_N_r2 <= pinc_N_r1; - pinc_N_r3 <= pinc_N_r2; - pinc_N_r4 <= pinc_N_r3; - pinc_N_r5 <= pinc_N_r4; - pinc_Nm_r1 <= pinc_Nm; - pinc_Nm_r2 <= pinc_Nm_r1; - pinc_Nm_r3 <= pinc_Nm_r2; - - phase_r1 <= phase_int; - phase_r2 <= phase_r1; - phase_r3 <= phase_r2; - phase_r4 <= phase_r3; - phase_r5 <= phase_r4; - phase_0_r1 <= phase_0; - - sync_reg <= load_r; - sync_reg_r1 <= sync_reg; - sync_reg_r2 <= sync_reg_r1; - sync_reg_r3 <= sync_reg_r2; - sync_reg_r4 <= sync_reg_r3; - sync_reg_r5 <= sync_reg_r4; - sync_reg_r6 <= sync_reg_r5; - sync_reg_r7 <= sync_reg_r6; - - // Address. - if (rd_en_r2) - addr_cnt <= addr_int; - else - addr_cnt <= addr_cnt + 1; - - addr_cnt_r1 <= addr_cnt; - addr_cnt_r2 <= addr_cnt_r1; - addr_cnt_r3 <= addr_cnt_r2; - addr_cnt_r4 <= addr_cnt_r3; - addr_cnt_r5 <= addr_cnt_r4; - addr_cnt_r6 <= addr_cnt_r5; - - // Gain. - gain_r1 <= gain_int; - gain_r2 <= gain_r1; - gain_r3 <= gain_r2; - gain_r4 <= gain_r3; - gain_r5 <= gain_r4; - gain_r6 <= gain_r5; - gain_r7 <= gain_r6; - - // Output selection. - outsel_r1 <= outsel_int; - outsel_r2 <= outsel_r1; - outsel_r3 <= outsel_r2; - outsel_r4 <= outsel_r3; - outsel_r5 <= outsel_r4; - outsel_r6 <= outsel_r5; - outsel_r7 <= outsel_r6; - - // Steady value selection. - stdysel_r1 <= stdysel_int; - stdysel_r2 <= stdysel_r1; - stdysel_r3 <= stdysel_r2; - stdysel_r4 <= stdysel_r3; - stdysel_r5 <= stdysel_r4; - stdysel_r6 <= stdysel_r5; - stdysel_r7 <= stdysel_r6; - - // Load enable flag. - load_r <= load_int; - - // Fifo Read Enable. - rd_en_r1 <= rd_en_int; - rd_en_r2 <= rd_en_r1; - - // Counter. - if (rd_en_int) - cnt <= 0; - else - cnt <= cnt + 1; - - // Output enable register. - if (~mode_int && rd_en_int) - if (~fifo_empty_i) - en_reg <= 1; - else - en_reg <= 0; - - en_reg_r1 <= en_reg; - en_reg_r2 <= en_reg_r1; - en_reg_r3 <= en_reg_r2; - en_reg_r4 <= en_reg_r3; - en_reg_r5 <= en_reg_r4; - en_reg_r6 <= en_reg_r5; - en_reg_r7 <= en_reg_r6; - en_reg_r8 <= en_reg_r7; - end -end - -// FSM outputs. -always_comb begin - // Default. - rd_en_int = 0; - - case (state) - READ_ST: - rd_en_int = 1; - - CNT_ST: - rd_en_int = 0; - endcase -end - -// Fifo output fields. -assign pinc_int = fifo_dout_r[15:0]; -assign phase_int = fifo_dout_r[31:16]; -assign addr_int = fifo_dout_r[47:32]; -assign gain_int = fifo_dout_r[63:48]; -assign nsamp_int = fifo_dout_r[79:64]; -assign outsel_int = fifo_dout_r[81:80]; -assign mode_int = fifo_dout_r[82]; -assign stdysel_int = fifo_dout_r[83]; -assign phrst_int = fifo_dout_r[84]; - -// Frequency calculation. -assign pinc_N = pinc_r2*N_DDS; - -// Phase calculation. -assign pinc_Nm = pinc_r2*cnt_n_reg; -assign phase_0 = pinc_Nm_r3 + phase_r5; - -// Phase vectors. -generate -genvar i; - for (i=0; i < N_DDS; i = i + 1) begin : GEN_phase - // Registers. - always @(posedge clk) begin - if (~rstn) begin - // v0. - phase_v0_r1[i] <= 0; - phase_v0_r2[i] <= 0; - phase_v0_r3[i] <= 0; - phase_v0_r4[i] <= 0; - - // v1. - phase_v1_r1[i] <= 0; - end - else begin - // v0. - phase_v0_r1[i] <= phase_v0[i]; - phase_v0_r2[i] <= phase_v0_r1[i]; - phase_v0_r3[i] <= phase_v0_r2[i]; - phase_v0_r4[i] <= phase_v0_r3[i]; - - // v1. - phase_v1_r1[i] <= phase_v1[i]; - end - end - - // v0. - assign phase_v0[i] = pinc_r2*i; - - // v1. - assign phase_v1[i] = phase_v0_r4[i] + phase_0_r1; - - // dds_ctrl_o output. - assign dds_ctrl_o[i*40 +: 40] = {7'h00,sync_reg_r7,phase_v1_r1[i],pinc_N_r5}; - end -endgenerate - -// load_int. -assign load_int = rd_en_int & ~fifo_empty_i; - -// Assign outputs. -assign fifo_rd_en_o = rd_en_int; -assign mem_addr_o = addr_cnt_r6; -assign gain_o = gain_r7; -assign src_o = outsel_r7; -assign stdy_o = stdysel_r7; -assign en_o = en_reg_r8; - -endmodule - diff --git a/qick/firmware/ip/axis_sg_int4_v1/src/data_writer.vhd b/qick/firmware/ip/axis_sg_int4_v1/src/data_writer.vhd deleted file mode 100644 index 8fa76e3..0000000 --- a/qick/firmware/ip/axis_sg_int4_v1/src/data_writer.vhd +++ /dev/null @@ -1,200 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity data_writer is - Generic - ( - -- Memory size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in STD_LOGIC; - clk : in STD_LOGIC; - - -- AXI Stream I/F. - s_axis_tready : out std_logic; - s_axis_tdata : in std_logic_vector(B-1 downto 0); - s_axis_tvalid : in std_logic; - - -- Memory I/F. - mem_en : out std_logic; - mem_we : out std_logic; - mem_addr : out std_logic_vector (N-1 downto 0); - mem_di : out std_logic_vector (B-1 downto 0); - - -- Registers. - START_ADDR_REG : in std_logic_vector (31 downto 0); - WE_REG : in std_logic - ); -end data_writer; - -architecture rtl of data_writer is - --- Synchronizer. -component synchronizer_n is - generic ( - N : Integer := 2 - ); - port ( - rstn : in std_logic; - clk : in std_logic; - data_in : in std_logic; - data_out : out std_logic - ); -end component; - --- State machine. -type fsm_state is ( INIT_ST , - READ_START_ADDR_ST , - WAIT_TVALID_ST , - RW_TDATA_ST ); -signal state : fsm_state; - -signal read_start_addr_state : std_logic; -signal rw_tdata_state : std_logic; - --- WE_REG_resync. -signal WE_REG_resync : std_logic; - --- Axis registers. -signal tready_i : std_logic; -signal tready_r : std_logic; -signal tdata_r : std_logic_vector(B-1 downto 0); -signal tdata_rr : std_logic_vector(B-1 downto 0); -signal tdata_rrr : std_logic_vector(B-1 downto 0); -signal tvalid_r : std_logic; -signal tvalid_rr : std_logic; -signal tvalid_rrr : std_logic; - --- Memory address space. -signal mem_addr_full : unsigned (N-1 downto 0); -signal mem_addr_full_r : unsigned (N-1 downto 0); - -begin - --- WE_REG_resync -WE_REG_resync_i : synchronizer_n - generic map ( - N => 2 - ) - port map ( - rstn => rstn , - clk => clk , - data_in => WE_REG , - data_out => WE_REG_resync - ); - -process (clk) -begin - if ( rising_edge(clk) ) then - if (rstn = '0') then - -- Axis registers. - tready_r <= '0'; - tdata_r <= (others => '0'); - tdata_rr <= (others => '0'); - tdata_rrr <= (others => '0'); - tvalid_r <= '0'; - tvalid_rr <= '0'; - tvalid_rrr <= '0'; - - -- Memory address. - mem_addr_full <= (others => '0'); - mem_addr_full_r <= (others => '0'); - else - -- Axis registers. - tready_r <= tready_i; - tdata_r <= s_axis_tdata; - tvalid_r <= s_axis_tvalid; - - -- Extra registers to account pipe of state machine. - tdata_rr <= tdata_r; - tdata_rrr <= tdata_rr; - tvalid_rr <= tvalid_r; - tvalid_rrr <= tvalid_rr; - - -- Memory address. - if ( read_start_addr_state = '1') then - mem_addr_full <= to_unsigned(to_integer(unsigned(START_ADDR_REG)),mem_addr_full'length); - elsif ( rw_tdata_state = '1' ) then - mem_addr_full <= mem_addr_full + 1; - end if; - mem_addr_full_r <= mem_addr_full; - - end if; - end if; -end process; - --- Finite state machine. -process (clk) -begin - if ( rising_edge(clk) ) then - if ( rstn = '0' ) then - state <= INIT_ST; - else - case state is - when INIT_ST => - if ( WE_REG_resync = '1' ) then - state <= READ_START_ADDR_ST; - end if; - - when READ_START_ADDR_ST => - state <= WAIT_TVALID_ST; - - when WAIT_TVALID_ST => - if ( WE_REG_resync = '1') then - if ( tvalid_r = '0' ) then - state <= WAIT_TVALID_ST; - else - state <= RW_TDATA_ST; - end if; - else - state <= INIT_ST; - end if; - - when RW_TDATA_ST => - if ( tvalid_r = '0' ) then - state <= WAIT_TVALID_ST; - end if; - - end case; - end if; - end if; -end process; - --- Output logic. -process (state) -begin -read_start_addr_state <= '0'; -rw_tdata_state <= '0'; -tready_i <= '0'; - case state is - when INIT_ST => - - when READ_START_ADDR_ST => - read_start_addr_state <= '1'; - - when WAIT_TVALID_ST => - tready_i <= '1'; - - when RW_TDATA_ST => - rw_tdata_state <= '1'; - tready_i <= '1'; - - end case; -end process; - --- Assign output. -s_axis_tready <= tready_r; - -mem_en <= '1'; -mem_we <= tvalid_rrr; -mem_addr <= std_logic_vector(mem_addr_full_r); -mem_di <= tdata_rrr; - -end rtl; - diff --git a/qick/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.veo b/qick/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.veo deleted file mode 100644 index c3dea29..0000000 --- a/qick/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.veo +++ /dev/null @@ -1,69 +0,0 @@ -// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -// IP VLNV: xilinx.com:ip:dds_compiler:6.0 -// IP Revision: 20 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -dds_compiler_0 your_instance_name ( - .aclk(aclk), // input wire aclk - .s_axis_phase_tvalid(s_axis_phase_tvalid), // input wire s_axis_phase_tvalid - .s_axis_phase_tdata(s_axis_phase_tdata), // input wire [39 : 0] s_axis_phase_tdata - .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid - .m_axis_data_tdata(m_axis_data_tdata) // output wire [31 : 0] m_axis_data_tdata -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file dds_compiler_0.v when simulating -// the core, dds_compiler_0. When compiling the wrapper file, be sure to -// reference the Verilog simulation library. - diff --git a/qick/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.vho b/qick/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.vho deleted file mode 100644 index 4db3fc6..0000000 --- a/qick/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.vho +++ /dev/null @@ -1,83 +0,0 @@ --- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:dds_compiler:6.0 --- IP Revision: 20 - --- The following code must appear in the VHDL architecture header. - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT dds_compiler_0 - PORT ( - aclk : IN STD_LOGIC; - s_axis_phase_tvalid : IN STD_LOGIC; - s_axis_phase_tdata : IN STD_LOGIC_VECTOR(39 DOWNTO 0); - m_axis_data_tvalid : OUT STD_LOGIC; - m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) - ); -END COMPONENT; --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : dds_compiler_0 - PORT MAP ( - aclk => aclk, - s_axis_phase_tvalid => s_axis_phase_tvalid, - s_axis_phase_tdata => s_axis_phase_tdata, - m_axis_data_tvalid => m_axis_data_tvalid, - m_axis_data_tdata => m_axis_data_tdata - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file dds_compiler_0.vhd when simulating --- the core, dds_compiler_0. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/qick/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.xci b/qick/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.xci deleted file mode 100644 index 562a763..0000000 --- a/qick/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.xci +++ /dev/null @@ -1,315 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - dds_compiler_0 - - - - 100000000 - 0 - 0 - 0.000 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 5 - 0 - 0 - 0 - 16 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 1 - 0 - 1 - 0 - 1 - 0 - 0 - 10 - 1 - 0 - 9 - 0 - 32 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 2 - 0 - 16 - 14 - 3 - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - 3 - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - 0 - 1 - 0 - 1 - 0 - 40 - 1 - 1 - zynquplus - Full_Range - 1 - dds_compiler_0 - Not_Required - 256 - Maximal - 3906.25 - Coregen - false - false - false - false - 10 - Configurable - Not_Required - Not_Required - Auto - Standard - 9 - false - false - Auto - Twos_Complement - Speed - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Sine_and_Cosine - 16 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - false - System_Parameters - Phase_Generator_and_SIN_COS_LUT - Streaming - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 16 - Streaming - true - On_Vector - Not_Required - 1 - 96 - false - 1 - zynquplusRFSOC - xilinx.com:zcu216:part0:2.0 - - xczu49dr - ffvf1760 - VERILOG - - MIXED - -2 - - E - TRUE - TRUE - IP_Flow - 20 - TRUE - ../../../../top/top.tmp/axis_sg_int4_v1_v1_0_project/axis_sg_int4_v1_v1_0_project.gen/sources_1/ip/dds_compiler_0 - - . - 2020.2 - GLOBAL - - - - - - - - - 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- xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset - - hdl/xbip_utils_v3_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - xbip_utils_v3_0_10 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_utils_2_0__ref_view_fileset - - hdl/axi_utils_v2_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - axi_utils_v2_0_6 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_pipe_3_0__ref_view_fileset - - hdl/xbip_pipe_v3_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - xbip_pipe_v3_0_6 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset - - hdl/xbip_bram18k_v3_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - xbip_bram18k_v3_0_6 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_mult_gen_12_0__ref_view_fileset - - hdl/mult_gen_v12_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - mult_gen_v12_0_16 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_wrapper_3_0__ref_view_fileset - - hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - xbip_dsp48_wrapper_v3_0_4 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_addsub_3_0__ref_view_fileset - - hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - xbip_dsp48_addsub_v3_0_6 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_multadd_3_0__ref_view_fileset - - hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - xbip_dsp48_multadd_v3_0_6 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_view_fileset - - hdl/dds_compiler_v6_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - dds_compiler_v6_0_20 - - - - xilinx_vhdlsimulationwrapper_view_fileset - - sim/dds_compiler_0.vhd - vhdlSource - xil_defaultlib - - - - xilinx_cmodelsimulation_view_fileset - - cmodel/dds_compiler_v6_0_bitacc_cmodel_lin64.zip - zip - - - cmodel/dds_compiler_v6_0_bitacc_cmodel_nt64.zip - zip - - - - xilinx_vhdltestbench_view_fileset - - demo_tb/tb_dds_compiler_0.vhd - vhdlSource - - - - xilinx_versioninformation_view_fileset - - doc/dds_compiler_v6_0_changelog.txt - text - - - - xilinx_externalfiles_view_fileset - - dds_compiler_0.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - dds_compiler_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - dds_compiler_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - dds_compiler_0_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - dds_compiler_0_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - - The Xilinx DDS Compiler LogiCORE provides Direct Digital Synthesizers (DDS) and optionally either Phase Generator or Sine/Cosine Lookup Table constituent parts as independent cores. The core features sine, cosine or quadrature outputs with 3 to 26-bit output sample precision. The core supports up to 16 channels by time-sharing the sine/cosine table which dramatically reduces the area requirement when multiple channels are needed. Phase Dithering and Taylor Series Correction options provide high dynamic range signals using minimal FPGA resources. In addition, the core has an optional phase offset capability, providing support for multiple synthesizers with precisely controlled phase differences. - - - Component_Name - Component Name - dds_compiler_0 - - - PartsPresent - Configuration Options - Phase_Generator_and_SIN_COS_LUT - - - DDS_Clock_Rate - System Clock - 256 - - - Channels - Number of Channels - 1 - - - Mode_of_Operation - Mode Of Operation - Standard - - - Modulus - Modulus - 9 - - - Parameter_Entry - Parameter Selection - System_Parameters - - - Spurious_Free_Dynamic_Range - Spurious Free Dynamic Range - 96 - - - Frequency_Resolution - Frequency Resolution - 3906.25 - - - Noise_Shaping - Noise Shaping - Auto - - - Phase_Width - Phase Width - 16 - - - Output_Width - Output Width - 16 - - - Phase_Increment - Phase Increment - Streaming - - - Resync - Resync - true - - - Phase_offset - Phase Offset - Streaming - - - Output_Selection - Output Selection - Sine_and_Cosine - - - Negative_Sine - Negative Sine - false - - - Negative_Cosine - Negative Cosine - false - - - Amplitude_Mode - Amplitude Mode - Full_Range - - - Memory_Type - Memory Type - Auto - - - Optimization_Goal - Optimization Goal - Speed - - - DSP48_Use - DSP48 Use - Maximal - - - Has_Phase_Out - Has Phase Out - false - - - DATA_Has_TLAST - DATA Has TLAST - Not_Required - - - Has_TREADY - Output TREADY - false - - - S_PHASE_Has_TUSER - Input - Not_Required - - - S_PHASE_TUSER_Width - User Field Width - 1 - - - M_DATA_Has_TUSER - DATA Output - Not_Required - - - M_PHASE_Has_TUSER - PHASE Output - Not_Required - - - S_CONFIG_Sync_Mode - Synchronization Mode - On_Vector - - - OUTPUT_FORM - Output Form - Twos_Complement - - - Latency_Configuration - Configurable - - - Latency - 10 - - - Has_ARESETn - ARESETn (active low) - false - - - Has_ACLKEN - ACLKEN - false - - - Output_Frequency1 - 0 - - - PINC1 - 0 - - - Phase_Offset_Angles1 - 0 - - - POFF1 - 0 - - - Output_Frequency2 - 0 - - - PINC2 - 0 - - - Phase_Offset_Angles2 - 0 - - - POFF2 - 0 - - - Output_Frequency3 - 0 - - - PINC3 - 0 - - - Phase_Offset_Angles3 - 0 - - - POFF3 - 0 - - - Output_Frequency4 - 0 - - - PINC4 - 0 - - - Phase_Offset_Angles4 - 0 - - - POFF4 - 0 - - - Output_Frequency5 - 0 - - - PINC5 - 0 - - - Phase_Offset_Angles5 - 0 - - - POFF5 - 0 - - - Output_Frequency6 - 0 - - - PINC6 - 0 - - - Phase_Offset_Angles6 - 0 - - - POFF6 - 0 - - - Output_Frequency7 - 0 - - - PINC7 - 0 - - - Phase_Offset_Angles7 - 0 - - - POFF7 - 0 - - - Output_Frequency8 - 0 - - - PINC8 - 0 - - - Phase_Offset_Angles8 - 0 - - - POFF8 - 0 - - - Output_Frequency9 - 0 - - - PINC9 - 0 - - - Phase_Offset_Angles9 - 0 - - - POFF9 - 0 - - - Output_Frequency10 - 0 - - - PINC10 - 0 - - - Phase_Offset_Angles10 - 0 - - - POFF10 - 0 - - - Output_Frequency11 - 0 - - - PINC11 - 0 - - - Phase_Offset_Angles11 - 0 - - - POFF11 - 0 - - - Output_Frequency12 - 0 - - - PINC12 - 0 - - - Phase_Offset_Angles12 - 0 - - - POFF12 - 0 - - - Output_Frequency13 - 0 - - - PINC13 - 0 - - - Phase_Offset_Angles13 - 0 - - - POFF13 - 0 - - - Output_Frequency14 - 0 - - - PINC14 - 0 - - - Phase_Offset_Angles14 - 0 - - - POFF14 - 0 - - - Output_Frequency15 - 0 - - - PINC15 - 0 - - - Phase_Offset_Angles15 - 0 - - - POFF15 - 0 - - - Output_Frequency16 - 0 - - - PINC16 - 0 - - - Phase_Offset_Angles16 - 0 - - - POFF16 - 0 - - - POR_mode - POR Mode - false - - - GUI_Behaviour - Coregen - - - explicit_period - false - - - period - 1 - - - - - DDS Compiler - 20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2020.2 - - - - - - - - diff --git a/qick/firmware/ip/axis_sg_int4_v1/src/fifo/bin2gray.vhd b/qick/firmware/ip/axis_sg_int4_v1/src/fifo/bin2gray.vhd deleted file mode 100644 index 4ecc09b..0000000 --- a/qick/firmware/ip/axis_sg_int4_v1/src/fifo/bin2gray.vhd +++ /dev/null @@ -1,37 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity bin2gray is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end bin2gray; - -architecture rtl of bin2gray is - -signal gray : std_logic_vector (B-1 downto 0); - -begin - --- MSB always match. -gray(B-1) <= din(B-1); - -GEN: for I in 0 to B-2 generate -begin - gray(I) <= din(I+1) xor din(I); -end generate; - --- Assign output. -dout <= gray; - -end rtl; - diff --git a/qick/firmware/ip/axis_sg_int4_v1/src/fifo/bram_dp.vhd b/qick/firmware/ip/axis_sg_int4_v1/src/fifo/bram_dp.vhd deleted file mode 100644 index d57aad1..0000000 --- a/qick/firmware/ip/axis_sg_int4_v1/src/fifo/bram_dp.vhd +++ /dev/null @@ -1,63 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity bram_dp is - Generic ( - -- Memory address size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - ena : in STD_LOGIC; - enb : in STD_LOGIC; - wea : in STD_LOGIC; - web : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR (N-1 downto 0); - addrb : in STD_LOGIC_VECTOR (N-1 downto 0); - dia : in STD_LOGIC_VECTOR (B-1 downto 0); - dib : in STD_LOGIC_VECTOR (B-1 downto 0); - doa : out STD_LOGIC_VECTOR (B-1 downto 0); - dob : out STD_LOGIC_VECTOR (B-1 downto 0) - ); -end bram_dp; - -architecture rtl of bram_dp is - --- Ram type. -type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); -shared variable RAM : ram_type; - -begin - --- CLKA port. -process (clka) -begin - if (clka'event and clka = '1') then - if (ena = '1') then - doa <= RAM(conv_integer(addra)); - if (wea = '1') then - RAM(conv_integer(addra)) := dia; - end if; - end if; - end if; -end process; - --- CLKB port. -process (clkb) -begin - if (clkb'event and clkb = '1') then - if (enb = '1') then - dob <= RAM(conv_integer(addrb)); - if (web = '1') then - RAM(conv_integer(addrb)) := dib; - end if; - end if; - end if; -end process; - -end rtl; - diff --git a/qick/firmware/ip/axis_sg_int4_v1/src/fifo/bram_simple_dp.vhd b/qick/firmware/ip/axis_sg_int4_v1/src/fifo/bram_simple_dp.vhd deleted file mode 100644 index 1494332..0000000 --- a/qick/firmware/ip/axis_sg_int4_v1/src/fifo/bram_simple_dp.vhd +++ /dev/null @@ -1,53 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity bram_simple_dp is - Generic ( - -- Memory address size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port ( - clk : in STD_LOGIC; - ena : in STD_LOGIC; - enb : in STD_LOGIC; - wea : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR (N-1 downto 0); - addrb : in STD_LOGIC_VECTOR (N-1 downto 0); - dia : in STD_LOGIC_VECTOR (B-1 downto 0); - dob : out STD_LOGIC_VECTOR (B-1 downto 0) - ); -end bram_simple_dp; - -architecture rtl of bram_simple_dp is - --- Ram type. -type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); -shared variable RAM : ram_type; - -begin - -process (clk) -begin - if (clk'event and clk = '1') then - if (ena = '1') then - if (wea = '1') then - RAM(conv_integer(addra)) := dia; - end if; - end if; - end if; -end process; - -process (clk) -begin - if (clk'event and clk = '1') then - if (enb = '1') then - dob <= RAM(conv_integer(addrb)); - end if; - end if; -end process; - -end rtl; - diff --git a/qick/firmware/ip/axis_sg_int4_v1/src/fifo/fifo.vhd b/qick/firmware/ip/axis_sg_int4_v1/src/fifo/fifo.vhd deleted file mode 100644 index 957362b..0000000 --- a/qick/firmware/ip/axis_sg_int4_v1/src/fifo/fifo.vhd +++ /dev/null @@ -1,135 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo; - -architecture rtl of fifo is - --- Number of bits of depth. -constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); - --- Dual port, single clock BRAM. -component bram_simple_dp is - Generic ( - -- Memory address size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port ( - clk : in STD_LOGIC; - ena : in STD_LOGIC; - enb : in STD_LOGIC; - wea : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR (N-1 downto 0); - addrb : in STD_LOGIC_VECTOR (N-1 downto 0); - dia : in STD_LOGIC_VECTOR (B-1 downto 0); - dob : out STD_LOGIC_VECTOR (B-1 downto 0) - ); -end component; - --- Pointers. -signal wptr : unsigned (N_LOG2-1 downto 0); -signal rptr : unsigned (N_LOG2-1 downto 0); - --- Memory signals. -signal mem_wea : std_logic; -signal mem_dob : std_logic_vector (B-1 downto 0); - --- Flags. -signal full_i : std_logic; -signal empty_i : std_logic; - -begin - --- FIFO memory. -mem_i : bram_simple_dp - Generic map ( - -- Memory address size. - N => N_LOG2, - -- Data width. - B => B - ) - Port map ( - clk => clk , - ena => '1' , - enb => rd_en , - wea => mem_wea , - addra => std_logic_vector(wptr) , - addrb => std_logic_vector(rptr) , - dia => din , - dob => mem_dob - ); - --- Memory connections. -mem_wea <= wr_en when full_i = '0' else - '0'; - --- Full/empty signals. -full_i <= '1' when wptr = rptr - 1 else - '0'; -empty_i <= '1' when wptr = rptr else - '0'; - --- wr_clk registers. -process (clk) -begin - if ( rising_edge(clk) ) then - if ( rstn = '0' ) then - wptr <= (others => '0'); - rptr <= (others => '0'); - else - -- Write. - if ( wr_en = '1' and full_i = '0' ) then - -- Write data. - - -- Increment pointer. - wptr <= wptr + 1; - end if; - - -- Read. - if ( rd_en = '1' and empty_i = '0' ) then - -- Read data. - - -- Increment pointer. - rptr <= rptr + 1; - end if; - end if; - end if; -end process; - --- Assign outputs. -dout <= mem_dob; -full <= full_i; -empty <= empty_i; - -end rtl; - diff --git a/qick/firmware/ip/axis_sg_int4_v1/src/fifo/fifo_axi.vhd b/qick/firmware/ip/axis_sg_int4_v1/src/fifo/fifo_axi.vhd deleted file mode 100644 index e1f76f7..0000000 --- a/qick/firmware/ip/axis_sg_int4_v1/src/fifo/fifo_axi.vhd +++ /dev/null @@ -1,147 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo_axi is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo_axi; - -architecture rtl of fifo_axi is - --- FIFO. -component fifo is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end component; - --- FIFO read to AXI adapter. -component rd2axi is - Generic - ( - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- FIFO Read I/F. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (B-1 downto 0); - fifo_empty : in std_logic; - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - empty : out std_logic - ); -end component; - -signal rd_en_i : std_logic; -signal dout_i : std_logic_vector (B-1 downto 0); -signal empty_i : std_logic; - -begin - --- FIFO. -fifo_i : fifo - Generic map - ( - -- Data width. - B => B, - - -- Fifo depth. - N => N - ) - Port map - ( - rstn => rstn , - clk => clk , - - -- Write I/F. - wr_en => wr_en , - din => din , - - -- Read I/F. - rd_en => rd_en_i , - dout => dout_i , - - -- Flags. - full => full , - empty => empty_i - ); - --- FIFO read to AXI adapter. -rd2axi_i : rd2axi - Generic map - ( - -- Data width. - B => B - ) - Port map - ( - rstn => rstn , - clk => clk , - - -- FIFO Read I/F. - fifo_rd_en => rd_en_i , - fifo_dout => dout_i , - fifo_empty => empty_i , - - -- Read I/F. - rd_en => rd_en , - dout => dout , - empty => empty - ); - -end rtl; - diff --git a/qick/firmware/ip/axis_sg_int4_v1/src/fifo/fifo_dc.vhd b/qick/firmware/ip/axis_sg_int4_v1/src/fifo/fifo_dc.vhd deleted file mode 100644 index c214fae..0000000 --- a/qick/firmware/ip/axis_sg_int4_v1/src/fifo/fifo_dc.vhd +++ /dev/null @@ -1,291 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo_dc is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - wr_rstn : in std_logic; - wr_clk : in std_logic; - - rd_rstn : in std_logic; - rd_clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo_dc; - -architecture rtl of fifo_dc is - --- Number of bits of depth. -constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); - --- Binary to gray converter. -component bin2gray is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end component; - --- Gray to binary converter. -component gray2bin is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end component; - --- Vector synchronizer (only for gray coded). -component synchronizer_vect is - generic ( - -- Sync stages. - N : Integer := 2; - - -- Data width. - B : Integer := 8 - ); - port ( - rstn : in std_logic; - clk : in std_logic; - data_in : in std_logic_vector (B-1 downto 0); - data_out : out std_logic_vector (B-1 downto 0) - ); -end component; - --- Dual port BRAM. -component bram_dp is - Generic ( - -- Memory address size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - ena : in STD_LOGIC; - enb : in STD_LOGIC; - wea : in STD_LOGIC; - web : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR (N-1 downto 0); - addrb : in STD_LOGIC_VECTOR (N-1 downto 0); - dia : in STD_LOGIC_VECTOR (B-1 downto 0); - dib : in STD_LOGIC_VECTOR (B-1 downto 0); - doa : out STD_LOGIC_VECTOR (B-1 downto 0); - dob : out STD_LOGIC_VECTOR (B-1 downto 0) - ); -end component; - --- Pointers. -signal wptr : unsigned (N_LOG2-1 downto 0); -signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); -signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); -signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); -signal rptr : unsigned (N_LOG2-1 downto 0); -signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); -signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); -signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); - --- Memory signals. -signal mem_wea : std_logic; -signal mem_dib : std_logic_vector (B-1 downto 0); -signal mem_doa : std_logic_vector (B-1 downto 0); -signal mem_dob : std_logic_vector (B-1 downto 0); - --- Flags. -signal full_i : std_logic; -signal empty_i : std_logic; - -begin - --- wptr_i: binary to gray. -wptr_i : bin2gray - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => std_logic_vector(wptr), - dout => wptr_g - ); - --- wptr_g: write to read domain. -wptr_g_i : synchronizer_vect - generic map ( - -- Sync stages. - N => 2, - - -- Data width. - B => N_LOG2 - ) - port map ( - rstn => rd_rstn, - clk => rd_clk, - data_in => wptr_g, - data_out => wptr_gc - ); - --- wptr_gc_i -wptr_gc_i : gray2bin - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => wptr_gc, - dout => wptr_c - ); - --- rptr_i: binary to gray. -rptr_i : bin2gray - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => std_logic_vector(rptr), - dout => rptr_g - ); - --- rptr_g: read to write domain. -rptr_g_i : synchronizer_vect - generic map ( - -- Sync stages. - N => 2, - - -- Data width. - B => N_LOG2 - ) - port map ( - rstn => wr_rstn, - clk => wr_clk, - data_in => rptr_g, - data_out => rptr_gc - ); - --- rptr_gc_i -rptr_gc_i : gray2bin - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => rptr_gc, - dout => rptr_c - ); - --- FIFO memory. -mem_i : bram_dp - Generic map ( - -- Memory address size. - N => N_LOG2, - -- Data width. - B => B - ) - Port map ( - clka => wr_clk, - clkb => rd_clk, - ena => '1', - enb => rd_en, - wea => mem_wea, - web => '0', - addra => std_logic_vector(wptr), - addrb => std_logic_vector(rptr), - dia => din, - dib => mem_dib, - doa => mem_doa, - dob => mem_dob - ); --- Memory connections. -mem_wea <= wr_en when full_i = '0' else - '0'; -mem_dib <= (others => '0'); - --- Full/empty signals. -full_i <= '1' when wptr = unsigned(rptr_c) - 1 else - '0'; -empty_i <= '1' when unsigned(wptr_c) = rptr else - '0'; - --- wr_clk registers. -process (wr_clk) -begin - if ( rising_edge(wr_clk) ) then - if ( wr_rstn = '0' ) then - wptr <= (others => '0'); - else - -- Write. - if ( wr_en = '1' and full_i = '0' ) then - -- Write data. - - -- Increment pointer. - wptr <= wptr + 1; - end if; - end if; - end if; -end process; - --- rd_clk registers. -process (rd_clk) -begin - if ( rising_edge(rd_clk) ) then - if ( rd_rstn = '0' ) then - rptr <= (others => '0'); - else - -- Read. - if ( rd_en = '1' and empty_i = '0' ) then - -- Read data. - - -- Increment pointer. - rptr <= rptr + 1; - end if; - end if; - end if; -end process; - --- Assign outputs. -dout <= mem_dob; -full <= full_i; -empty <= empty_i; - -end rtl; diff --git a/qick/firmware/ip/axis_sg_int4_v1/src/fifo/fifo_dc_axi.vhd b/qick/firmware/ip/axis_sg_int4_v1/src/fifo/fifo_dc_axi.vhd deleted file mode 100644 index eb83d1a..0000000 --- a/qick/firmware/ip/axis_sg_int4_v1/src/fifo/fifo_dc_axi.vhd +++ /dev/null @@ -1,156 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo_dc_axi is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - wr_rstn : in std_logic; - wr_clk : in std_logic; - - rd_rstn : in std_logic; - rd_clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo_dc_axi; - -architecture rtl of fifo_dc_axi is - --- Dual-clock FIFO. -component fifo_dc is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - wr_rstn : in std_logic; - wr_clk : in std_logic; - - rd_rstn : in std_logic; - rd_clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end component; - --- FIFO read to AXI adapter. -component rd2axi is - Generic - ( - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- FIFO Read I/F. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (B-1 downto 0); - fifo_empty : in std_logic; - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - empty : out std_logic - ); -end component; - -signal rd_en_i : std_logic; -signal dout_i : std_logic_vector (B-1 downto 0); -signal empty_i : std_logic; - -begin - --- Dual-clock FIFO. -fifo_i : fifo_dc - Generic map - ( - -- Data width. - B => B, - - -- Fifo depth. - N => N - ) - Port map - ( - wr_rstn => wr_rstn , - wr_clk => wr_clk , - - rd_rstn => rd_rstn , - rd_clk => rd_clk , - - -- Write I/F. - wr_en => wr_en , - din => din , - - -- Read I/F. - rd_en => rd_en_i , - dout => dout_i , - - -- Flags. - full => full , - empty => empty_i - ); - --- FIFO read to AXI adapter. -rd2axi_i : rd2axi - Generic map - ( - -- Data width. - B => B - ) - Port map - ( - rstn => rd_rstn , - clk => rd_clk , - - -- FIFO Read I/F. - fifo_rd_en => rd_en_i , - fifo_dout => dout_i , - fifo_empty => empty_i , - - -- Read I/F. - rd_en => rd_en , - dout => dout , - empty => empty - ); - -end rtl; - diff --git a/qick/firmware/ip/axis_sg_int4_v1/src/fifo/gray2bin.vhd b/qick/firmware/ip/axis_sg_int4_v1/src/fifo/gray2bin.vhd deleted file mode 100644 index e23f8af..0000000 --- a/qick/firmware/ip/axis_sg_int4_v1/src/fifo/gray2bin.vhd +++ /dev/null @@ -1,37 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity gray2bin is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end gray2bin; - -architecture rtl of gray2bin is - -signal bin : std_logic_vector (B-1 downto 0); - -begin - --- MSB always match. -bin(B-1) <= din(B-1); - -GEN: for I in 0 to B-2 generate -begin - bin(I) <= bin(I+1) xor din(I); -end generate GEN; - --- Assign output. -dout <= bin; - -end rtl; - diff --git a/qick/firmware/ip/axis_sg_int4_v1/src/fifo/rd2axi.vhd b/qick/firmware/ip/axis_sg_int4_v1/src/fifo/rd2axi.vhd deleted file mode 100644 index babadc6..0000000 --- a/qick/firmware/ip/axis_sg_int4_v1/src/fifo/rd2axi.vhd +++ /dev/null @@ -1,138 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity rd2axi is - Generic - ( - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- FIFO Read I/F. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (B-1 downto 0); - fifo_empty : in std_logic; - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - empty : out std_logic - ); -end rd2axi; - -architecture rtl of rd2axi is - -type fsm_state is ( WAIT_EMPTY_ST, - READ_FIRST_ST, - READ_ST, - READ_LAST_ST); -signal current_state, next_state : fsm_state; - -signal wait_empty_state : std_logic; -signal read_first_state : std_logic; -signal read_state : std_logic; - -signal fifo_rd_en_i : std_logic; -signal empty_i : std_logic; - -begin - -process(clk) -begin - if (rising_edge(clk)) then - if (rstn = '0') then - current_state <= WAIT_EMPTY_ST; - else - current_state <= next_state; - end if; - end if; -end process; - --- Next state logic. -process(current_state, fifo_empty, rd_en) -begin - case current_state is - when WAIT_EMPTY_ST => - if (fifo_empty = '1') then - next_state <= WAIT_EMPTY_ST; - else - next_state <= READ_FIRST_ST; - end if; - - when READ_FIRST_ST => - next_state <= READ_ST; - - when READ_ST => - if (fifo_empty = '0') then - next_state <= READ_ST; - else - if (rd_en = '1') then - next_state <= WAIT_EMPTY_ST; - else - next_state <= READ_LAST_ST; - end if; - end if; - - when READ_LAST_ST => - if (rd_en = '0') then - next_state <= READ_LAST_ST; - else - next_state <= WAIT_EMPTY_ST; - end if; - - end case; -end process; - --- Output logic. -process(current_state) -begin -wait_empty_state <= '0'; -read_first_state <= '0'; -read_state <= '0'; -empty_i <= '0'; - case current_state is - when WAIT_EMPTY_ST => - wait_empty_state <= '1'; - read_first_state <= '0'; - read_state <= '0'; - empty_i <= '1'; - - when READ_FIRST_ST => - wait_empty_state <= '0'; - read_first_state <= '1'; - read_state <= '0'; - empty_i <= '1'; - - when READ_ST => - wait_empty_state <= '0'; - read_first_state <= '0'; - read_state <= '1'; - empty_i <= '0'; - - when READ_LAST_ST => - wait_empty_state <= '0'; - read_first_state <= '0'; - read_state <= '0'; - empty_i <= '0'; - - end case; -end process; - --- FIFO Read enable signal. -fifo_rd_en_i <= read_first_state or (read_state and rd_en); - --- Assign outputs. -fifo_rd_en <= fifo_rd_en_i; --- TODO: add register to freeze last value. -dout <= fifo_dout when empty_i = '0' else - (others => '0'); -empty <= empty_i; - -end rtl; - diff --git a/qick/firmware/ip/axis_sg_int4_v1/src/fifo/synchronizer_vect.vhd b/qick/firmware/ip/axis_sg_int4_v1/src/fifo/synchronizer_vect.vhd deleted file mode 100644 index 2fbb696..0000000 --- a/qick/firmware/ip/axis_sg_int4_v1/src/fifo/synchronizer_vect.vhd +++ /dev/null @@ -1,49 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - --- This block is intended to use to sync gray coded vectors. - --- NOTE: Do not use with generic vector data, as it may result --- in corrupted re-sync data. - -entity synchronizer_vect is - generic ( - -- Sync stages. - N : Integer := 2; - - -- Data width. - B : Integer := 8 - ); - port ( - rstn : in std_logic; - clk : in std_logic; - data_in : in std_logic_vector (B-1 downto 0); - data_out : out std_logic_vector (B-1 downto 0) - ); -end synchronizer_vect; - -architecture rtl of synchronizer_vect is - --- Internal register. -type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); -signal data_int_reg : reg_t; - -begin - -process(clk) -begin - if (rising_edge(clk)) then - if (rstn = '0') then - data_int_reg <= (others => (others => '0')); -- 1 FF. - else - data_int_reg <= data_int_reg(N-2 downto 0) & data_in; - end if; - end if; -end process; - --- Assign output. -data_out <= data_int_reg(N-1); - -end rtl; - diff --git a/qick/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.coe b/qick/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.coe deleted file mode 100644 index fd9c445..0000000 --- a/qick/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.coe +++ /dev/null @@ -1,2 +0,0 @@ -Radix = 10; -CoefData = 0.004708,0.005461,0.000000,-0.013987,-0.029332,-0.030123,0.000000,0.065216,0.149630,0.221652,0.250000,0.221652,0.149630,0.065216,0.000000,-0.030123,-0.029332,-0.013987,0.000000,0.005461,0.004708 \ No newline at end of file diff --git a/qick/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.veo b/qick/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.veo deleted file mode 100644 index 44cd847..0000000 --- a/qick/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.veo +++ /dev/null @@ -1,70 +0,0 @@ -// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -// IP VLNV: xilinx.com:ip:fir_compiler:7.2 -// IP Revision: 15 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -fir_0 your_instance_name ( - .aclk(aclk), // input wire aclk - .s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid - .s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready - .s_axis_data_tdata(s_axis_data_tdata), // input wire [31 : 0] s_axis_data_tdata - .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid - .m_axis_data_tdata(m_axis_data_tdata) // output wire [127 : 0] m_axis_data_tdata -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file fir_0.v when simulating -// the core, fir_0. When compiling the wrapper file, be sure to -// reference the Verilog simulation library. - diff --git a/qick/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.vho b/qick/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.vho deleted file mode 100644 index be451e1..0000000 --- a/qick/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.vho +++ /dev/null @@ -1,85 +0,0 @@ --- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:fir_compiler:7.2 --- IP Revision: 15 - --- The following code must appear in the VHDL architecture header. - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT fir_0 - PORT ( - aclk : IN STD_LOGIC; - s_axis_data_tvalid : IN STD_LOGIC; - s_axis_data_tready : OUT STD_LOGIC; - s_axis_data_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axis_data_tvalid : OUT STD_LOGIC; - m_axis_data_tdata : OUT STD_LOGIC_VECTOR(127 DOWNTO 0) - ); -END COMPONENT; --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : fir_0 - PORT MAP ( - aclk => aclk, - s_axis_data_tvalid => s_axis_data_tvalid, - s_axis_data_tready => s_axis_data_tready, - s_axis_data_tdata => s_axis_data_tdata, - m_axis_data_tvalid => m_axis_data_tvalid, - m_axis_data_tdata => m_axis_data_tdata - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file fir_0.vhd when simulating --- the core, fir_0. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/qick/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.xci b/qick/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.xci deleted file mode 100644 index e6289dd..0000000 --- a/qick/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.xci +++ /dev/null @@ -1,321 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - fir_0 - - - - 100000000 - 0 - 0 - 0.000 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 16 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 1 - 0 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - 31,31,31,31,31,31,31,31 - 31,31,31,31,31,31,31,31 - fixed - fir_0.mif - 24 - 2 - 0 - 0,0,0,0,0,0,0,0 - 0,0,2,2,4,4,6,6 - 16,16,16,16,16,16,16,16 - 0 - 16 - 6 - 1 - 4 - fir_0 - 0 - 0 - 1 - 0 - 0 - 16,16 - 0 - 0 - -0;-1;-0;-1;-0;-1;-0;-1 - 0,0,0,0,0,0,0,0 - 0,1,0,1,0,1,0,1 - 16,16,16,16,16,16,16,16 - 16,16 - 16 - 1 - ./ - none - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 12 - 2 - 0 - 0 - 128 - 1 - 1 - 1 - 6 - 1 - 21 - 0 - 0 - none;none;none;none - -0;-1;-0;-1;-0;-1;-0;-1 - 16,16,16,16,16,16,16,16 - 1 - 16 - 1 - 0,1,2,3,4,5,6,7 - 1 - 3 - 0 - 0 - 0 - 32 - 1 - zynquplus - 1 - true - false - Basic - 300.0 - COE_File - 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 - Automatic - false - fir_0.coe - 16 - false - 1 - Signed - Inferred - 16 - 6 - fir_0 - false - false - false - false - Not_Required - 1 - Automatic - 0 - false - false - Signed - 16 - 1 - false - false - Systolic_Multiply_Accumulate - 1 - Interpolation - Coregen - false - false - false - 1 - false - false - Automatic - 4 - 4 - false - Not_Required - Automatic - false - false - 1 - 1 - 2 - false - Area - None - None - false - Automatic - Symmetric_Rounding_to_Infinity - 16 - 0.5 - 0.0 - P4-0,P4-1,P4-2,P4-3,P4-4 - false - Automatic - Quantize_Only - Input_Sample_Period - Integer - no_coe_file_loaded - true - Single - On_Vector - false - Not_Required - 1 - 0.001 - All - 1.0 - 0.5 - 1 - zynquplusRFSOC - xilinx.com:zcu216:part0:2.0 - - xczu49dr - ffvf1760 - VERILOG - - MIXED - -2 - - E - TRUE - TRUE - IP_Flow - 15 - TRUE - ../../../../top/top.tmp/axis_sg_int4_v1_v1_0_project/axis_sg_int4_v1_v1_0_project.gen/sources_1/ip/fir_0 - - . - 2020.2 - GLOBAL - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/qick/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.xml b/qick/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.xml deleted file mode 100644 index 57879e2..0000000 --- a/qick/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.xml +++ /dev/null @@ -1,2875 +0,0 @@ - - - xilinx.com - customized_ip - fir_0 - 1.0 - - - event_s_data_tlast_missing_intf - - - - - - - INTERRUPT - - - event_s_data_tlast_missing - - - - - - SENSITIVITY - EDGE_RISING - - - PortWidth - 1 - - - none - - - - - - - event_s_data_tlast_unexpected_intf - - - - - - - INTERRUPT - - - event_s_data_tlast_unexpected - - - - - - SENSITIVITY - EDGE_RISING - - - PortWidth - 1 - - - none - - - - - - - event_s_data_chanid_incorrect_intf - - - - - - - INTERRUPT - - - event_s_data_chanid_incorrect - - - - - - SENSITIVITY - EDGE_RISING - - - PortWidth - 1 - - - none - - - - - - - event_s_config_tlast_missing_intf - - - - - - - INTERRUPT - - - event_s_config_tlast_missing - - - - - - SENSITIVITY - EDGE_RISING - - - PortWidth - 1 - - - none - - - - - - - event_s_config_tlast_unexpected_intf - - - - - - - INTERRUPT - - - event_s_config_tlast_unexpected - - - - - - SENSITIVITY - EDGE_RISING - - - PortWidth - 1 - - - none - - - - - - - event_s_reload_tlast_missing_intf - - - - - - - INTERRUPT - - - event_s_reload_tlast_missing - - - - - - SENSITIVITY - EDGE_RISING - - - PortWidth - 1 - - - none - - - - - - - event_s_reload_tlast_unexpected_intf - - - - - - - INTERRUPT - - - event_s_reload_tlast_unexpected - - - - - - SENSITIVITY - EDGE_RISING - - - PortWidth - 1 - - - none - - - - - - - S_AXIS_RELOAD - S_AXIS_RELOAD - - - - - - - TDATA - - - s_axis_reload_tdata - - - - - TLAST - - - s_axis_reload_tlast - - - - - TREADY - - - s_axis_reload_tready - - - - - TVALID - - - s_axis_reload_tvalid - - - - - - TDATA_NUM_BYTES - 0 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 0 - - - none - - - - - HAS_TREADY - 0 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 0 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - aclk_intf - - - - - - - CLK - - - aclk - - - - - - ASSOCIATED_BUSIF - S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD - - - ASSOCIATED_RESET - aresetn - - - ASSOCIATED_CLKEN - aclken - - - FREQ_HZ - aclk - 100000000 - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - aresetn_intf - - - - - - - RST - - - aresetn - - - - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - aclken_intf - - - - - - - CE - - - aclken - - - - - - POLARITY - ACTIVE_HIGH - - - - - S_AXIS_DATA - S_AXIS_DATA - - - - - - - TDATA - - - s_axis_data_tdata - - - - - TLAST - - - s_axis_data_tlast - - - - - TREADY - - - s_axis_data_tready - - - - - TUSER - - - s_axis_data_tuser - - - - - TVALID - - - s_axis_data_tvalid - - - - - - TDATA_NUM_BYTES - 4 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 0 - - - none - - - - - HAS_TREADY - 1 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 0 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - M_AXIS_DATA - M_AXIS_DATA - - - - - - - TDATA - - - m_axis_data_tdata - - - - - TLAST - - - m_axis_data_tlast - - - - - TREADY - - - m_axis_data_tready - - - - - TUSER - - - m_axis_data_tuser - - - - - TVALID - - - m_axis_data_tvalid - - - - - - TDATA_NUM_BYTES - 16 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 0 - - - none - - - - - HAS_TREADY - 0 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 0 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - S_AXIS_CONFIG - S_AXIS_CONFIG - - - - - - - TDATA - - - s_axis_config_tdata - - - - - TLAST - - - s_axis_config_tlast - - - - - TREADY - - - s_axis_config_tready - - - - - TVALID - - - s_axis_config_tvalid - - - - - - TDATA_NUM_BYTES - 0 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 0 - - - none - - - - - HAS_TREADY - 0 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 0 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - - - - xilinx_veriloginstantiationtemplate - Verilog Instantiation Template - verilogSource:vivado.xilinx.com:synthesis.template - verilog - - xilinx_veriloginstantiationtemplate_view_fileset - - - - GENtimestamp - Wed Feb 02 16:51:39 UTC 2022 - - - outputProductCRC - 9:ab919098 - - - - - xilinx_vhdlsynthesis - VHDL Synthesis - vhdlSource:vivado.xilinx.com:synthesis - vhdl - fir_compiler_v7_2_15 - - xilinx_vhdlsynthesis_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset - - - xilinx_vhdlsynthesis_xilinx_com_ip_axi_utils_2_0__ref_view_fileset - - - xilinx_vhdlsynthesis_view_fileset - - - - GENtimestamp - Wed Feb 02 16:51:39 UTC 2022 - - - outputProductCRC - 9:ab919098 - - - - - xilinx_synthesisconstraints - Synthesis Constraints - :vivado.xilinx.com:synthesis.constraints - - xilinx_synthesisconstraints_view_fileset - - - - GENtimestamp - Wed Feb 02 16:51:39 UTC 2022 - - - outputProductCRC - 9:ab919098 - - - - - xilinx_vhdlsynthesiswrapper - VHDL Synthesis Wrapper - vhdlSource:vivado.xilinx.com:synthesis.wrapper - vhdl - fir_0 - - xilinx_vhdlsynthesiswrapper_view_fileset - - - - GENtimestamp - Wed Feb 02 16:51:39 UTC 2022 - - - outputProductCRC - 9:ab919098 - - - - - xilinx_cmodelsimulation - C Simulation - cSource:vivado.xilinx.com:simulation.cmodel - c - - xilinx_cmodelsimulation_view_fileset - - - - GENtimestamp - Wed Feb 02 16:51:39 UTC 2022 - - - outputProductCRC - 9:ab919098 - - - - - xilinx_vhdltestbench - VHDL Test Bench - vhdlSource:vivado.xilinx.com:simulation.testbench - vhdl - testbench - - xilinx_vhdltestbench_view_fileset - - - - GENtimestamp - Wed Feb 02 16:51:40 UTC 2022 - - - outputProductCRC - 9:ab919098 - - - - - xilinx_project_archive - Miscellaneous - :vivado.xilinx.com:misc.files - - - outputProductCRC - 9:ab919098 - - - - - xilinx_versioninformation - Version Information - :vivado.xilinx.com:docs.versioninfo - - xilinx_versioninformation_view_fileset - - - - GENtimestamp - Wed Feb 02 16:51:40 UTC 2022 - - - outputProductCRC - 9:ab919098 - - - - - xilinx_externalfiles - External Files - :vivado.xilinx.com:external.files - - xilinx_externalfiles_view_fileset - - - - GENtimestamp - Wed Feb 02 16:53:29 UTC 2022 - - - outputProductCRC - 9:ab919098 - - - - - xilinx_vhdlbehavioralsimulation - VHDL Simulation - vhdlSource:vivado.xilinx.com:simulation - vhdl - fir_compiler_v7_2_15 - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_utils_2_0__ref_view_fileset - - - xilinx_vhdlbehavioralsimulation_view_fileset - - - - GENtimestamp - Thu Feb 10 19:39:33 UTC 2022 - - - outputProductCRC - 9:9729a5c6 - - - - - xilinx_vhdlsimulationwrapper - VHDL Simulation Wrapper - vhdlSource:vivado.xilinx.com:simulation.wrapper - vhdl - fir_0 - - xilinx_vhdlsimulationwrapper_view_fileset - - - - GENtimestamp - Thu Feb 10 19:39:33 UTC 2022 - - - outputProductCRC - 9:9729a5c6 - - - - - - - aresetn - - in - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0x1 - - - - - - false - - - - - - aclk - - in - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - aclken - - in - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0x1 - - - - - - false - - - - - - s_axis_data_tvalid - - in - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0x0 - - - - - s_axis_data_tready - - out - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0x1 - - - - - s_axis_data_tlast - - in - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0x0 - - - - - - false - - - - - - s_axis_data_tuser - - in - - 0 - 0 - - - - std_logic_vector - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axis_data_tdata - - in - - 31 - 0 - - - - std_logic_vector - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0 - - - - - s_axis_config_tvalid - - in - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0x0 - - - - - - false - - - - - - s_axis_config_tready - - out - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0x1 - - - - - - false - - - - - - s_axis_config_tlast - - in - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0x0 - - - - - - false - - - - - - s_axis_config_tdata - - in - - 0 - 0 - - - - std_logic_vector - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axis_reload_tvalid - - in - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0x0 - - - - - - false - - - - - - s_axis_reload_tready - - out - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0x1 - - - - - - false - - - - - - s_axis_reload_tlast - - in - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0x0 - - - - - - false - - - - - - s_axis_reload_tdata - - in - - 0 - 0 - - - - std_logic_vector - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0 - - - - - - false - - - - - - m_axis_data_tvalid - - out - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0x0 - - - - - m_axis_data_tready - - in - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0x1 - - - - - - false - - - - - - m_axis_data_tlast - - out - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0x0 - - - - - - false - - - - - - m_axis_data_tuser - - out - - 0 - 0 - - - - std_logic_vector - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0 - - - - - - false - - - - - - m_axis_data_tdata - - out - - 127 - 0 - - - - std_logic_vector - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0 - - - - - event_s_data_tlast_missing - - out - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0x0 - - - - - - false - - - - - - event_s_data_tlast_unexpected - - out - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0x0 - - - - - - false - - - - - - event_s_data_chanid_incorrect - - out - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0x0 - - - - - - false - - - - - - event_s_config_tlast_missing - - out - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0x0 - - - - - - false - - - - - - event_s_config_tlast_unexpected - - out - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0x0 - - - - - - false - - - - - - event_s_reload_tlast_missing - - out - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0x0 - - - - - - false - - - - - - event_s_reload_tlast_unexpected - - out - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0x0 - - - - - - false - - - - - - - - C_XDEVICEFAMILY - zynquplus - - - C_ELABORATION_DIR - ./ - - - C_COMPONENT_NAME - fir_0 - - - C_COEF_FILE - fir_0.mif - - - C_COEF_FILE_LINES - 24 - - - C_FILTER_TYPE - 0 - - - C_INTERP_RATE - 1 - - - C_DECIM_RATE - 1 - - - C_ZERO_PACKING_FACTOR - 1 - - - C_SYMMETRY - 0 - - - C_NUM_FILTS - 1 - - - C_NUM_TAPS - 21 - - - C_NUM_CHANNELS - 1 - - - C_CHANNEL_PATTERN - fixed - - - C_ROUND_MODE - 3 - - - C_COEF_RELOAD - 0 - - - C_NUM_RELOAD_SLOTS - 1 - - - C_COL_MODE - 1 - - - C_COL_PIPE_LEN - 4 - - - C_COL_CONFIG - 6 - - - C_OPTIMIZATION - 0 - - - C_DATA_PATH_WIDTHS - 16,16,16,16,16,16,16,16 - - - C_DATA_IP_PATH_WIDTHS - 16,16 - - - C_DATA_PX_PATH_WIDTHS - 16,16 - - - C_DATA_WIDTH - 16 - - - C_COEF_PATH_WIDTHS - 16,16,16,16,16,16,16,16 - - - C_COEF_WIDTH - 16 - - - C_DATA_PATH_SRC - 0,1,0,1,0,1,0,1 - - - C_COEF_PATH_SRC - 0,0,2,2,4,4,6,6 - - - C_PX_PATH_SRC - 0,1,2,3,4,5,6,7 - - - C_DATA_PATH_SIGN - 0,0,0,0,0,0,0,0 - - - C_COEF_PATH_SIGN - 0,0,0,0,0,0,0,0 - - - C_ACCUM_PATH_WIDTHS - 31,31,31,31,31,31,31,31 - - - C_OUTPUT_WIDTH - 16 - - - C_OUTPUT_PATH_WIDTHS - 16,16,16,16,16,16,16,16 - - - C_ACCUM_OP_PATH_WIDTHS - 31,31,31,31,31,31,31,31 - - - C_EXT_MULT_CNFG - none - - - C_DATA_PATH_PSAMP_SRC - -0;-1;-0;-1;-0;-1;-0;-1 - - - C_OP_PATH_PSAMP_SRC - -0;-1;-0;-1;-0;-1;-0;-1 - - - C_NUM_MADDS - 6 - - - C_OPT_MADDS - none;none;none;none - - - C_OVERSAMPLING_RATE - 1 - - - C_INPUT_RATE - 1 - - - C_OUTPUT_RATE - 1 - - - C_DATA_MEMTYPE - 0 - - - C_COEF_MEMTYPE - 2 - - - C_IPBUFF_MEMTYPE - 0 - - - C_OPBUFF_MEMTYPE - 0 - - - C_DATAPATH_MEMTYPE - 0 - - - C_MEM_ARRANGEMENT - 2 - - - C_DATA_MEM_PACKING - 0 - - - C_COEF_MEM_PACKING - 0 - - - C_FILTS_PACKED - 0 - - - C_LATENCY - 12 - - - C_HAS_ARESETn - 0 - - - C_HAS_ACLKEN - 0 - - - C_DATA_HAS_TLAST - 0 - - - C_S_DATA_HAS_FIFO - 0 - - - C_S_DATA_HAS_TUSER - 0 - - - C_S_DATA_TDATA_WIDTH - 32 - - - C_S_DATA_TUSER_WIDTH - 1 - - - C_M_DATA_HAS_TREADY - 0 - - - C_M_DATA_HAS_TUSER - 0 - - - C_M_DATA_TDATA_WIDTH - 128 - - - C_M_DATA_TUSER_WIDTH - 1 - - - C_HAS_CONFIG_CHANNEL - 0 - - - C_CONFIG_SYNC_MODE - 0 - - - C_CONFIG_PACKET_SIZE - 0 - - - C_CONFIG_TDATA_WIDTH - 1 - - - C_RELOAD_TDATA_WIDTH - 1 - - - - - - choice_list_0dc4ca8f - Automatic - Custom - - - choice_list_24b724fb - Basic - Advanced - - - choice_list_3f660234 - All - - - choice_list_5e9d103c - Signed - - - choice_list_8506c89f - Signed - Unsigned - - - choice_list_a63914d2 - Area - Speed - Custom - - - choice_list_dd381b21 - Automatic - Block - Distributed - - - choice_pairs_18e22ec6 - Full_Precision - Truncate_LSBs - Non_Symmetric_Rounding_Down - Non_Symmetric_Rounding_Up - Symmetric_Rounding_to_Zero - Symmetric_Rounding_to_Infinity - Convergent_Rounding_to_Even - Convergent_Rounding_to_Odd - - - choice_pairs_2074757d - None - All - Data_Path_Fanout - Pre-Adder_Pipeline - Coefficient_Fanout - Control_Path_Fanout - Control_Column_Fanout - Control_Broadcast_Fanout - Control_LUT_Pipeline - No_BRAM_Read_First_Mode - Optimal_Column_Lengths - Data_Path_Broadcast - Disable_Half_Band_Centre_Tap - No_SRL_Attributes - Other - - - choice_pairs_2b265cc8 - Frequency_Specification - Input_Sample_Period - Output_Sample_Period - - - choice_pairs_33abc840 - Quantize_Only - Maximize_Dynamic_Range - Normalize_to_Centre_Coefficient - - - choice_pairs_3ab545a3 - Not_Required - Chan_ID_Field - - - choice_pairs_433eb1cb - Inferred - Non_Symmetric - - - choice_pairs_480f8ce0 - Not_Required - Packet_Framing - - - choice_pairs_74144f21 - COE_File - Vector - - - choice_pairs_789dfe7d - Single_Rate - Interpolation - Decimation - Hilbert - Interpolated - - - choice_pairs_8e2d2e35 - Not_Required - User_Field - - - choice_pairs_ab4ea833 - Systolic_Multiply_Accumulate - - - choice_pairs_b6c64168 - Single - By_Channel - - - choice_pairs_eb2746f0 - Integer - Fixed_Fractional - - - choice_pairs_f611af79 - On_Vector - On_Packet - - - - - xilinx_veriloginstantiationtemplate_view_fileset - - fir_0.vho - vhdlTemplate - - - fir_0.veo - verilogTemplate - - - - xilinx_vhdlsynthesis_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset - - hdl/xbip_utils_v3_0_vh_rfs.vhd - vhdlSource - xbip_utils_v3_0_10 - - - - - - - - - - - xilinx_vhdlsynthesis_xilinx_com_ip_axi_utils_2_0__ref_view_fileset - - hdl/axi_utils_v2_0_vh_rfs.vhd - vhdlSource - axi_utils_v2_0_6 - - - - - - - - - - - xilinx_vhdlsynthesis_view_fileset - - constraints/fir_compiler_v7_2.xdc - xdc - fir_compiler_v7_2_15 - - - fir_0.mif - mif - - - hdl/fir_compiler_v7_2_vh_rfs.vhd - vhdlSource - fir_compiler_v7_2_15 - - - - xilinx_synthesisconstraints_view_fileset - - fir_0_ooc.xdc - xdc - USED_IN_implementation - USED_IN_out_of_context - USED_IN_synthesis - - - - xilinx_vhdlsynthesiswrapper_view_fileset - - synth/fir_0.vhd - vhdlSource - xil_defaultlib - - - - xilinx_cmodelsimulation_view_fileset - - cmodel/fir_0.h - cSource - - - cmodel/tb_fir_0.c - cSource - - - cmodel/fir_compiler_v7_2_bitacc_cmodel_lin64.zip - zip - - - cmodel/fir_compiler_v7_2_bitacc_cmodel_nt64.zip - zip - - - - xilinx_vhdltestbench_view_fileset - - demo_tb/tb_fir_0.vhd - vhdlSource - - - - xilinx_versioninformation_view_fileset - - doc/fir_compiler_v7_2_changelog.txt - text - - - - xilinx_externalfiles_view_fileset - - fir_0.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - fir_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - fir_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - fir_0_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - fir_0_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset - - hdl/xbip_utils_v3_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - xbip_utils_v3_0_10 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_utils_2_0__ref_view_fileset - - hdl/axi_utils_v2_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - axi_utils_v2_0_6 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_view_fileset - - constraints/fir_compiler_v7_2.xdc - xdc - fir_compiler_v7_2_15 - - - fir_0.mif - mif - - - hdl/fir_compiler_v7_2_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - fir_compiler_v7_2_15 - - - - xilinx_vhdlsimulationwrapper_view_fileset - - sim/fir_0.vhd - vhdlSource - xil_defaultlib - - - - The Xilinx FIR Compiler LogiCORE is a module for generation of high speed, compact filter implementations that can be configured to implement many different filtering functions. The core is fully synchronous, using a single clock, and is highly parameterizable, allowing designers to control the filter type, data and coefficient widths, the number of filter taps, the number of channels, etc. Multi-rate operation is supported. The core is delivered through the Xilinx Vivado IP Catalog and integrates seamlessly with the Xilinx design flow. - - - Component_Name - fir_0 - - - GUI_Behaviour - Coregen - - - CoefficientSource - COE_File - - - CoefficientVector - 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 - - - Coefficient_File - fir_0.coe - - - Coefficient_Sets - 1 - - - Coefficient_Reload - false - - - Filter_Type - Interpolation - - - Rate_Change_Type - Integer - - - Interpolation_Rate - 4 - - - Decimation_Rate - 1 - - - Zero_Pack_Factor - 1 - - - Channel_Sequence - Basic - - - Number_Channels - 1 - - - Select_Pattern - All - - - Pattern_List - P4-0,P4-1,P4-2,P4-3,P4-4 - - - Number_Paths - 2 - - - RateSpecification - Input_Sample_Period - - - HardwareOversamplingRate - 1 - - - SamplePeriod - 1 - - - Sample_Frequency - 0.001 - - - Clock_Frequency - 300.0 - - - Coefficient_Sign - Signed - - - Quantization - Quantize_Only - - - Coefficient_Width - 16 - - - BestPrecision - true - - - Coefficient_Fractional_Bits - 16 - - - Coefficient_Structure - Inferred - - - Data_Sign - Signed - - - Data_Width - 16 - - - Data_Fractional_Bits - 0 - - - Output_Rounding_Mode - Symmetric_Rounding_to_Infinity - - - Output_Width - 16 - - - Filter_Architecture - Systolic_Multiply_Accumulate - - - Optimization_Goal - Area - - - Optimization_Selection - None - - - Data_Path_Fanout - false - - - Pre_Adder_Pipeline - false - - - Coefficient_Fanout - false - - - Control_Path_Fanout - false - - - Control_Column_Fanout - false - - - Control_Broadcast_Fanout - false - - - Control_LUT_Pipeline - false - - - No_BRAM_Read_First_Mode - false - - - Optimal_Column_Lengths - false - - - Data_Path_Broadcast - false - - - Disable_Half_Band_Centre_Tap - false - - - No_SRL_Attributes - false - - - Other - false - - - Optimization_List - None - - - Data_Buffer_Type - Automatic - - - Coefficient_Buffer_Type - Automatic - - - Input_Buffer_Type - Automatic - - - Output_Buffer_Type - Automatic - - - Preference_For_Other_Storage - Automatic - - - Multi_Column_Support - Automatic - - - Inter_Column_Pipe_Length - 4 - - - ColumnConfig - 6 - - - DATA_Has_TLAST - Not_Required - - - M_DATA_Has_TREADY - false - - - S_DATA_Has_FIFO - false - - - S_DATA_Has_TUSER - Not_Required - - - M_DATA_Has_TUSER - Not_Required - - - DATA_TUSER_Width - 1 - - - S_CONFIG_Sync_Mode - On_Vector - - - S_CONFIG_Method - Single - - - Num_Reload_Slots - 1 - - - Has_ACLKEN - false - - - Has_ARESETn - false - - - Reset_Data_Vector - true - - - Blank_Output - false - - - Gen_MIF_from_Spec - false - - - Gen_MIF_from_COE - false - - - Reload_File - no_coe_file_loaded - - - Gen_MIF_Files - false - - - DisplayReloadOrder - false - - - Passband_Min - 0.0 - - - Passband_Max - 0.5 - - - Stopband_Min - 0.5 - - - Stopband_Max - 1.0 - - - Filter_Selection - 1 - - - - - FIR Compiler - 15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2020.2 - - - - - - - - diff --git a/qick/firmware/ip/axis_sg_int4_v1/src/latency_reg.v b/qick/firmware/ip/axis_sg_int4_v1/src/latency_reg.v deleted file mode 100644 index 687a9f3..0000000 --- a/qick/firmware/ip/axis_sg_int4_v1/src/latency_reg.v +++ /dev/null @@ -1,61 +0,0 @@ -module latency_reg - ( - rstn , - clk , - - din , - dout - ); - -// Parameters. -parameter N = 2; // Latency. -parameter B = 8; // Data width. - -// Ports. -input rstn; -input clk; -input [B-1:0] din; -output [B-1:0] dout; - -// Shift register. -reg [B-1:0] shift_r [0:N-1]; - -generate -genvar i; - for (i=1; i '0'); - else - data_int_reg <= data_int_reg(N-2 downto 0) & data_in; - end if; - end if; -end process; - --- Assign output. -data_out <= data_int_reg(N-1); - -end rtl; - diff --git a/qick/firmware/ip/axis_sg_int4_v1/src/tb/gen_gauss.py b/qick/firmware/ip/axis_sg_int4_v1/src/tb/gen_gauss.py deleted file mode 100644 index ea72942..0000000 --- a/qick/firmware/ip/axis_sg_int4_v1/src/tb/gen_gauss.py +++ /dev/null @@ -1,18 +0,0 @@ -import numpy as np -import matplotlib.pyplot as plt - -def gauss(mu=0, si=0, length=100, maxv=32000): - x = np.arange(0,length) - y = 1/(2*np.pi*si**2)*np.exp(-(x-mu)**2/si**2) - y = y/np.max(y)*maxv - return y - -yi = gauss(mu=300, si=120, length=600) -yq = np.zeros(len(yi)) - -yi = yi.astype(np.int16) -yq = yq.astype(np.int16) - -for ii in range(len(yi)): - print("%d,%d" %(yq[ii],yi[ii])) - diff --git a/qick/firmware/ip/axis_sg_int4_v1/src/tb/tb.sv b/qick/firmware/ip/axis_sg_int4_v1/src/tb/tb.sv deleted file mode 100644 index 8105bbf..0000000 --- a/qick/firmware/ip/axis_sg_int4_v1/src/tb/tb.sv +++ /dev/null @@ -1,513 +0,0 @@ -// VIP: axi_mst_0 -// DUT: axis_signal_gen_v2 -// IF: s_axi -> axi_mst_0 - -import axi_vip_pkg::*; -import axi_mst_0_pkg::*; - -module tb(); - -// DUT generics. -parameter N = 10; -parameter N_DDS = 4; - -// s_axi interfase. -reg s_axi_aclk; -reg s_axi_aresetn; -wire [5:0] s_axi_araddr; -wire [2:0] s_axi_arprot; -wire s_axi_arready; -wire s_axi_arvalid; -wire [5:0] s_axi_awaddr; -wire [2:0] s_axi_awprot; -wire s_axi_awready; -wire s_axi_awvalid; -wire s_axi_bready; -wire [1:0] s_axi_bresp; -wire s_axi_bvalid; -wire [31:0] s_axi_rdata; -wire s_axi_rready; -wire [1:0] s_axi_rresp; -wire s_axi_rvalid; -wire [31:0] s_axi_wdata; -wire s_axi_wready; -wire [3:0] s_axi_wstrb; -wire s_axi_wvalid; - -// s0_axis interfase. -reg s0_axis_aclk; -reg s0_axis_aresetn; -reg [31:0] s0_axis_tdata; -wire s0_axis_tready; -reg s0_axis_tvalid; - -reg aresetn; -reg aclk; - -// Dummy clock for debugging. -reg aclk4; - -// s1_axis interfase. -reg [87:0] s1_axis_tdata; -wire s1_axis_tready; -reg s1_axis_tvalid; - -// m_axis interfase. -wire [N_DDS*32-1:0] m_axis_tdata; -reg m_axis_tready = 1; -wire m_axis_tvalid; - -// Waveform Fields. -reg [15:0] freq_r; -reg [15:0] phase_r; -reg [15:0] addr_r; -reg [15:0] gain_r; -reg [15:0] nsamp_r; -reg [1:0] outsel_r; -reg mode_r; -reg stdysel_r; -reg phrst_r; - -// Assignment of data out for debugging. -wire [31:0] dout_ii [0:N_DDS-1]; -reg [31:0] dout_f; - -xil_axi_prot_t prot = 0; -reg[31:0] data_wr = 32'h12345678; -reg[31:0] data; -xil_axi_resp_t resp; - -// Test bench control. -reg tb_load_mem = 0; -reg tb_load_mem_done = 0; -reg tb_load_wave = 0; -reg tb_load_wave_done = 0; -reg tb_write_out = 0; - -// Debug. -generate -genvar ii; -for (ii = 0; ii < N_DDS; ii = ii + 1) begin : GEN_debug - assign dout_ii[ii] = m_axis_tdata[32*ii +: 32]; -end -endgenerate -axi_mst_0 axi_mst_0_i - ( - .aclk (s_axi_aclk ), - .aresetn (s_axi_aresetn ), - .m_axi_araddr (s_axi_araddr ), - .m_axi_arprot (s_axi_arprot ), - .m_axi_arready (s_axi_arready ), - .m_axi_arvalid (s_axi_arvalid ), - .m_axi_awaddr (s_axi_awaddr ), - .m_axi_awprot (s_axi_awprot ), - .m_axi_awready (s_axi_awready ), - .m_axi_awvalid (s_axi_awvalid ), - .m_axi_bready (s_axi_bready ), - .m_axi_bresp (s_axi_bresp ), - .m_axi_bvalid (s_axi_bvalid ), - .m_axi_rdata (s_axi_rdata ), - .m_axi_rready (s_axi_rready ), - .m_axi_rresp (s_axi_rresp ), - .m_axi_rvalid (s_axi_rvalid ), - .m_axi_wdata (s_axi_wdata ), - .m_axi_wready (s_axi_wready ), - .m_axi_wstrb (s_axi_wstrb ), - .m_axi_wvalid (s_axi_wvalid ) - ); - -axis_sg_int4_v1 - # - ( - .N(N) - ) - DUT - ( - // AXI Slave I/F for configuration. - .s_axi_aclk (s_axi_aclk ), - .s_axi_aresetn (s_axi_aresetn ), - .s_axi_araddr (s_axi_araddr ), - .s_axi_arprot (s_axi_arprot ), - .s_axi_arready (s_axi_arready ), - .s_axi_arvalid (s_axi_arvalid ), - .s_axi_awaddr (s_axi_awaddr ), - .s_axi_awprot (s_axi_awprot ), - .s_axi_awready (s_axi_awready ), - .s_axi_awvalid (s_axi_awvalid ), - .s_axi_bready (s_axi_bready ), - .s_axi_bresp (s_axi_bresp ), - .s_axi_bvalid (s_axi_bvalid ), - .s_axi_rdata (s_axi_rdata ), - .s_axi_rready (s_axi_rready ), - .s_axi_rresp (s_axi_rresp ), - .s_axi_rvalid (s_axi_rvalid ), - .s_axi_wdata (s_axi_wdata ), - .s_axi_wready (s_axi_wready ), - .s_axi_wstrb (s_axi_wstrb ), - .s_axi_wvalid (s_axi_wvalid ), - - // AXIS Slave to load data into memory. - .s0_axis_aclk (s0_axis_aclk ), - .s0_axis_aresetn(s0_axis_aresetn), - .s0_axis_tdata (s0_axis_tdata ), - .s0_axis_tvalid (s0_axis_tvalid ), - .s0_axis_tready (s0_axis_tready ), - - // s1_* and m_* reset/clock. - .aresetn (aresetn ), - .aclk (aclk ), - - // AXIS Slave to queue waveforms. - .s1_axis_tdata (s1_axis_tdata ), - .s1_axis_tvalid (s1_axis_tvalid ), - .s1_axis_tready (s1_axis_tready ), - - // AXIS Master for output data. - .m_axis_tready (m_axis_tready ), - .m_axis_tvalid (m_axis_tvalid ), - .m_axis_tdata (m_axis_tdata ) - ); - -// VIP Agents -axi_mst_0_mst_t axi_mst_0_agent; - -assign s1_axis_tdata = {phrst_r,stdysel_r,mode_r,outsel_r,nsamp_r,gain_r,addr_r,phase_r,freq_r}; - -initial begin - // Create agents. - axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); - - // Set tag for agents. - axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); - - // Start agents. - axi_mst_0_agent.start_master(); - - // Reset sequence. - s_axi_aresetn <= 0; - s0_axis_aresetn <= 0; - aresetn <= 0; - #500; - s_axi_aresetn <= 1; - s0_axis_aresetn <= 1; - aresetn <= 1; - - #1000; - - $display("############################"); - $display("### Load data into Table ###"); - $display("############################"); - $display("t = %0t", $time); - - /* - ADDR = 0 - */ - - // start_addr. - data_wr = 0; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*0, prot, data_wr, resp); - #10; - - // we. - data_wr = 1; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*1, prot, data_wr, resp); - #10; - - // Load Table. - tb_load_mem <= 1; - wait (tb_load_mem_done); - - #100; - - // we. - data_wr = 0; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*1, prot, data_wr, resp); - #10; - - $display("#######################"); - $display("### Queue Waveforms ###"); - $display("#######################"); - $display("t = %0t", $time); - - // Queue waveforms and write output while queuing. - tb_load_wave <= 1; - tb_write_out <= 1; - wait (tb_load_wave_done); - - #30000; - - // Stop writing output data. - tb_write_out <= 0; - - #20000; - -end - -// Load data into memroy. -initial begin - int fd,vali,valq; - bit signed [15:0] ii,qq; - - s0_axis_tvalid <= 0; - s0_axis_tdata <= 0; - - wait (tb_load_mem); - - fd = $fopen("../../../../../tb/gauss.txt","r"); - - wait (s0_axis_tready); - - while($fscanf(fd,"%d,%d", valq,vali) == 2) begin - $display("I,Q: %d, %d", vali,valq); - ii = vali; - qq = valq; - @(posedge s0_axis_aclk); - s0_axis_tvalid <= 1; - s0_axis_tdata <= {qq,ii}; - end - - @(posedge s0_axis_aclk); - s0_axis_tvalid <= 0; - - $fclose(fd); - tb_load_mem_done <= 1; - -end - -// Load waveforms. -initial begin - s1_axis_tvalid <= 0; - freq_r <= 0; - phase_r <= 0; - addr_r <= 0; - gain_r <= 0; - nsamp_r <= 0; - outsel_r <= 0; - mode_r <= 0; - stdysel_r <= 0; - phrst_r <= 0; - - wait (tb_load_wave); - wait (s1_axis_tready); - - /***************/ - /* Simple Test */ - /***************/ - @(posedge aclk); - $display("t = %0t", $time); - s1_axis_tvalid <= 1; - freq_r <= freq_calc(100, N_DDS, 15); - addr_r <= 0; - gain_r <= 22000; - nsamp_r <= 100; - outsel_r <= 1; // 0: prod, 1: dds, 2: mem - mode_r <= 0; // 0: nsamp, 1: periodic - stdysel_r <= 0; - phrst_r <= 0; - - @(posedge aclk); - s1_axis_tvalid <= 0; - - /************/ - /* Flat Top */ - /************/ - - //@(posedge aclk); - //$display("t = %0t", $time); - //s1_axis_tvalid <= 1; - //freq_r <= freq_calc(100, N_DDS, 15); - //addr_r <= 0; - //gain_r <= 22000; - //nsamp_r <= 300; - //outsel_r <= 0; // 0: prod, 1: dds, 2: mem - //mode_r <= 0; // 0: nsamp, 1: periodic - - //@(posedge aclk); - //$display("t = %0t", $time); - //s1_axis_tvalid <= 1; - //addr_r <= 300; - //gain_r <= 11000; - //nsamp_r <= 200; - //outsel_r <= 1; // 0: prod, 1: dds, 2: mem - //mode_r <= 0; // 0: nsamp, 1: periodic - - ////@(posedge aclk); - ////s1_axis_tvalid <= 0; - - ////#5000; - - //@(posedge aclk); - //$display("t = %0t", $time); - //s1_axis_tvalid <= 1; - //addr_r <= 300; - //gain_r <= 22000; - //nsamp_r <= 300; - //outsel_r <= 0; // 0: prod, 1: dds, 2: mem - //mode_r <= 0; // 0: nsamp, 1: periodic - //stdysel_r <= 1; - - /*****************/ - /* Latency Check */ - /*****************/ - - //@(posedge aclk); - //$display("t = %0t", $time); - //s1_axis_tvalid <= 1; - //freq_r <= freq_calc(100, N_DDS, 19); - //phase_r <= 100; - //addr_r <= 10; - //gain_r <= 30000; - //nsamp_r <= 17; - //outsel_r <= 0; // 0: prod, 1: dds, 2: mem - //mode_r <= 0; // 0: nsamp, 1: periodic - - //@(posedge aclk); - //$display("t = %0t", $time); - //s1_axis_tvalid <= 1; - //freq_r <= freq_calc(100, N_DDS, 1); - //phase_r <= 245; - //addr_r <= 300; - //gain_r <= 30000; - //nsamp_r <= 5; - //outsel_r <= 0; // 0: prod, 1: dds, 2: mem - //mode_r <= 0; // 0: nsamp, 1: periodic - - //@(posedge aclk); - //$display("t = %0t", $time); - //s1_axis_tvalid <= 1; - //freq_r <= freq_calc(100, N_DDS, 33); - //phase_r <= 0; - //addr_r <= 5; - //gain_r <= 30000; - //nsamp_r <= 670/N_DDS; - //outsel_r <= 1; // 0: prod, 1: dds, 2: mem - //mode_r <= 0; // 0: nsamp, 1: periodic - //stdysel_r <= 1; // 0: last, 1: zero. - - //@(posedge aclk); - //$display("t = %0t", $time); - //s1_axis_tvalid <= 1; - //freq_r <= freq_calc(100, N_DDS, 22); - //phase_r <= 7689; - //addr_r <= 0; - //gain_r <= 30000; - //nsamp_r <= 70/N_DDS; - //outsel_r <= 2; // 0: prod, 1: dds, 2: mem - //mode_r <= 1; // 0: nsamp, 1: periodic - //stdysel_r <= 1; // 0: last, 1: zero. - - //@(posedge aclk); - //s1_axis_tvalid <= 0; - - //#30000; - - //@(posedge aclk); - //$display("t = %0t", $time); - //s1_axis_tvalid <= 1; - //freq_r <= freq_calc(100, N_DDS, 3); - //phase_r <= 0; - //addr_r <= 5; - //gain_r <= 30000; - //nsamp_r <= 670/N_DDS; - //outsel_r <= 1; // 0: prod, 1: dds, 2: mem - //mode_r <= 0; // 0: nsamp, 1: periodic - //stdysel_r <= 1; // 0: last, 1: zero. - - @(posedge aclk); - s1_axis_tvalid <= 0; - tb_load_wave_done <= 1; -end - -// Write output into file. -initial begin - int fd; - int i; - shortint real_d, imag_d; - - // Output file. - fd = $fopen("../../../../../tb/dout.csv","w"); - - // Data format. - $fdisplay(fd, "valid, idx, real, imag"); - - wait (tb_write_out); - - while (tb_write_out) begin - @(posedge aclk); - for (i=0; i - - user.org - user - axis_sg_mux4_v1 - 1.0 - - - m_axis - - - - - - - TDATA - - - m_axis_tdata - - - - - TVALID - - - m_axis_tvalid - - - - - TREADY - - - m_axis_tready - - - - - - s_axis - - - - - - - TDATA - - - s_axis_tdata - - - - - TVALID - - - s_axis_tvalid - - - - - TREADY - - - s_axis_tready - - - - - - s_axi - - - - - - - - - AWADDR - - - s_axi_awaddr - - - - - AWPROT - - - s_axi_awprot - - - - - AWVALID - - - s_axi_awvalid - - - - - AWREADY - - - s_axi_awready - - - - - WDATA - - - s_axi_wdata - - - - - WSTRB - - - s_axi_wstrb - - - - - WVALID - - - s_axi_wvalid - - - - - WREADY - - - s_axi_wready - - - - - BRESP - - - s_axi_bresp - - - - - BVALID - - - s_axi_bvalid - - - - - BREADY - - - s_axi_bready - - - - - ARADDR - - - s_axi_araddr - - - - - ARPROT - - - s_axi_arprot - - - - - ARVALID - - - s_axi_arvalid - - - - - ARREADY - - - s_axi_arready - - - - - RDATA - - - s_axi_rdata - - - - - RRESP - - - s_axi_rresp - - - - - RVALID - - - s_axi_rvalid - - - - - RREADY - - - s_axi_rready - - - - - - s_axi_aclk - - - - - - - CLK - - - s_axi_aclk - - - - - - ASSOCIATED_BUSIF - s_axi - - - ASSOCIATED_RESET - s_axi_aresetn - - - - - s_axi_aresetn - - - - - - - RST - - - s_axi_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - aclk - - - - - - - CLK - - - aclk - - - - - - ASSOCIATED_BUSIF - m_axis:s_axis - - - ASSOCIATED_RESET - aresetn - - - - - aresetn - - - - - - - RST - - - aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - - - s_axi - - reg0 - 0 - 64 - 32 - register - - - - - - - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis - Verilog - axis_sg_mux4_v1 - - xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset - - - xilinx_anylanguagesynthesis_view_fileset - - - - viewChecksum - 8e4f9196 - - - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - Verilog - axis_sg_mux4_v1 - - xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - - - viewChecksum - 8e4f9196 - - - - - xilinx_xpgui - UI Layout - :vivado.xilinx.com:xgui.ui - - xilinx_xpgui_view_fileset - - - - viewChecksum - 429ef1d0 - - - - - - - s_axi_aclk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_aresetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_awaddr - - in - - 5 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_awprot - - in - - 2 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_awvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_awready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_wdata - - in - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_wstrb - - in - - 3 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 1 - - - - - s_axi_wvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_wready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_bresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_bvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_bready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_araddr - - in - - 5 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_arprot - - in - - 2 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_arvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_arready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_rdata - - out - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_rresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_rvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_rready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - aclk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - aresetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axis_tready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axis_tvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axis_tdata - - in - - 39 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - m_axis_tready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 1 - - - - - m_axis_tvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m_axis_tdata - - out - - 63 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - - N_DDS - N Dds - 2 - - - - - - choice_list_74b5137e - ACTIVE_HIGH - ACTIVE_LOW - - - - - xilinx_anylanguagesynthesis_view_fileset - - src/dds_compiler_0/dds_compiler_0.xci - xci - CELL_NAME_sg_mux4_i/GEN_out[0].dds_top_i/GEN_dds[0].dds_i/dds_compiler_0 - - - src/dds_top.v - verilogSource - - - src/latency_reg.v - verilogSource - - - src/sg_mux4.v - verilogSource - - - src/ctrl.sv - systemVerilogSource - - - src/phase_ctrl.sv - systemVerilogSource - - - src/axi_slv.vhd - vhdlSource - - - src/fifo/bram_simple_dp.vhd - vhdlSource - - - src/fifo/fifo.vhd - vhdlSource - - - src/synchronizer_n.vhd - vhdlSource - - - src/axis_sg_mux4.v - verilogSource - CHECKSUM_d597a72a - - - - xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset - - - - - - - - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - src/dds_compiler_0/dds_compiler_0.xci - xci - CELL_NAME_sg_mux4_i/GEN_out[0].dds_top_i/GEN_dds[0].dds_i/dds_compiler_0 - - - src/dds_top.v - verilogSource - - - src/latency_reg.v - verilogSource - - - src/sg_mux4.v - verilogSource - - - src/ctrl.sv - systemVerilogSource - - - src/phase_ctrl.sv - systemVerilogSource - - - src/axi_slv.vhd - vhdlSource - - - src/fifo/bram_simple_dp.vhd - vhdlSource - - - src/fifo/fifo.vhd - vhdlSource - - - src/synchronizer_n.vhd - vhdlSource - - - src/axis_sg_mux4.v - verilogSource - - - - xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset - - - - - - - - - - xilinx_xpgui_view_fileset - - xgui/axis_sg_mux4_v1_v1_0.tcl - tclSource - CHECKSUM_429ef1d0 - XGUI_VERSION_2 - - - - AXIS Signal Generator with 4 muxed outputs. - - - N_DDS - N Dds - 2 - - - Component_Name - axis_sg_mux4_v1_v1_0 - - - - - - zynquplus - - - /UserIP - - AXIS SG mux 4 - package_project - 3 - 2022-02-22T20:24:54Z - - /home/lstefana/v20.2/ip/axis_sg_mux4_v1 - /home/lstefana/v20.2/ip/axis_sg_mux4_v1 - /home/lstefana/v20.2/ip/axis_sg_mux4_v1 - /home/lstefana/v20.2/ip/axis_sg_mux4_v1 - /home/lstefana/v20.2/ip/axis_sg_mux4_v1 - /home/lstefana/v20.2/ip/axis_sg_mux4_v1 - /home/lstefana/v20.2/ip/axis_sg_mux4_v1 - /home/lstefana/v20.2/ip/axis_sg_mux4_v1 - /home/lstefana/v20.2/ip/axis_sg_mux4_v1 - /home/lstefana/v20.2/ip/axis_sg_mux4_v1 - /home/lstefana/v20.2/ip/axis_sg_mux4_v1 - /home/lstefana/v20.2/ip/axis_sg_mux4_v1 - /home/lstefana/v20.2/ip/axis_sg_mux4_v1 - /home/lstefana/v20.2/ip/axis_sg_mux4_v1 - /home/lstefana/v20.2/ip/axis_sg_mux4_v1 - /home/lstefana/v20.2/ip/axis_sg_mux4_v1 - /home/lstefana/v20.2/ip/axis_sg_mux4_v1 - /home/lstefana/v20.2/ip/axis_sg_mux4_v1 - /home/lstefana/v20.2/ip/axis_sg_mux4_v1 - /home/lstefana/v20.2/ip/axis_sg_mux4_v1 - /home/lstefana/v20.2/ip/axis_sg_mux4_v1 - /home/lstefana/v20.2/ip/axis_sg_mux4_v1 - /home/lstefana/v20.2/ip/axis_sg_mux4_v1 - /home/lstefana/v20.2/ip/axis_sg_mux4_v1 - - - - 2020.2 - - - - - - - - - diff --git a/qick/firmware/ip/axis_sg_mux4_v1/src/axi_mst_0/axi_mst_0.veo b/qick/firmware/ip/axis_sg_mux4_v1/src/axi_mst_0/axi_mst_0.veo deleted file mode 100644 index 7cfbd51..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v1/src/axi_mst_0/axi_mst_0.veo +++ /dev/null @@ -1,85 +0,0 @@ -// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -// IP VLNV: xilinx.com:ip:axi_vip:1.1 -// IP Revision: 8 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -axi_mst_0 your_instance_name ( - .aclk(aclk), // input wire aclk - .aresetn(aresetn), // input wire aresetn - .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr - .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot - .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid - .m_axi_awready(m_axi_awready), // input wire m_axi_awready - .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata - .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb - .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid - .m_axi_wready(m_axi_wready), // input wire m_axi_wready - .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp - .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid - .m_axi_bready(m_axi_bready), // output wire m_axi_bready - .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr - .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot - .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid - .m_axi_arready(m_axi_arready), // input wire m_axi_arready - .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata - .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp - .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid - .m_axi_rready(m_axi_rready) // output wire m_axi_rready -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file axi_mst_0.v when simulating -// the core, axi_mst_0. When compiling the wrapper file, be sure to -// reference the Verilog simulation library. - diff --git a/qick/firmware/ip/axis_sg_mux4_v1/src/axi_mst_0/axi_mst_0.vho b/qick/firmware/ip/axis_sg_mux4_v1/src/axi_mst_0/axi_mst_0.vho deleted file mode 100644 index a53be60..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v1/src/axi_mst_0/axi_mst_0.vho +++ /dev/null @@ -1,115 +0,0 @@ --- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:axi_vip:1.1 --- IP Revision: 8 - --- The following code must appear in the VHDL architecture header. - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT axi_mst_0 - PORT ( - aclk : IN STD_LOGIC; - aresetn : IN STD_LOGIC; - m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - m_axi_awvalid : OUT STD_LOGIC; - m_axi_awready : IN STD_LOGIC; - m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - m_axi_wvalid : OUT STD_LOGIC; - m_axi_wready : IN STD_LOGIC; - m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - m_axi_bvalid : IN STD_LOGIC; - m_axi_bready : OUT STD_LOGIC; - m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - m_axi_arvalid : OUT STD_LOGIC; - m_axi_arready : IN STD_LOGIC; - m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - m_axi_rvalid : IN STD_LOGIC; - m_axi_rready : OUT STD_LOGIC - ); -END COMPONENT; --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : axi_mst_0 - PORT MAP ( - aclk => aclk, - aresetn => aresetn, - m_axi_awaddr => m_axi_awaddr, - m_axi_awprot => m_axi_awprot, - m_axi_awvalid => m_axi_awvalid, - m_axi_awready => m_axi_awready, - m_axi_wdata => m_axi_wdata, - m_axi_wstrb => m_axi_wstrb, - m_axi_wvalid => m_axi_wvalid, - m_axi_wready => m_axi_wready, - m_axi_bresp => m_axi_bresp, - m_axi_bvalid => m_axi_bvalid, - m_axi_bready => m_axi_bready, - m_axi_araddr => m_axi_araddr, - m_axi_arprot => m_axi_arprot, - m_axi_arvalid => m_axi_arvalid, - m_axi_arready => m_axi_arready, - m_axi_rdata => m_axi_rdata, - m_axi_rresp => m_axi_rresp, - m_axi_rvalid => m_axi_rvalid, - m_axi_rready => m_axi_rready - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file axi_mst_0.vhd when simulating --- the core, axi_mst_0. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/qick/firmware/ip/axis_sg_mux4_v1/src/axi_mst_0/axi_mst_0.xci b/qick/firmware/ip/axis_sg_mux4_v1/src/axi_mst_0/axi_mst_0.xci deleted file mode 100644 index f5a8b15..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v1/src/axi_mst_0/axi_mst_0.xci +++ /dev/null @@ -1,200 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - axi_mst_0 - - - ACTIVE_LOW - - 100000000 - 0 - 0 - 0.000 - 32 - 0 - 0 - 0 - - 32 - 100000000 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 32 - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 0 - 2 - 32 - 0 - 0 - 0 - 32 - 0 - 0 - 32 - 0 - 0 - 0 - axi_mst_0 - 32 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 0 - 0 - 1 - 0 - MASTER - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - virtex7 - - - xc7vx485t - ffg1157 - VERILOG - - MIXED - -1 - - - TRUE - TRUE - IP_Flow - 8 - TRUE - . - - . - 2020.2 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/qick/firmware/ip/axis_sg_mux4_v1/src/axi_mst_0/axi_mst_0.xml b/qick/firmware/ip/axis_sg_mux4_v1/src/axi_mst_0/axi_mst_0.xml deleted file mode 100644 index 024a39d..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v1/src/axi_mst_0/axi_mst_0.xml +++ /dev/null @@ -1,4760 +0,0 @@ - - - xilinx.com - customized_ip - axi_mst_0 - 1.0 - - - M_AXI - - - - - - - - - ARADDR - - - m_axi_araddr - - - - - ARBURST - - - m_axi_arburst - - - - - ARCACHE - - - m_axi_arcache - - - - - ARID - - - m_axi_arid - - - - - ARLEN - - - m_axi_arlen - - - - - ARLOCK - - - m_axi_arlock - - - - - ARPROT - - - m_axi_arprot - - - - - ARQOS - - - m_axi_arqos - - - - - ARREADY - - - m_axi_arready - - - - - ARREGION - - - m_axi_arregion - - - - - ARSIZE - - - m_axi_arsize - - - - - ARUSER - - - m_axi_aruser - - - - - ARVALID - - - m_axi_arvalid - - - - - AWADDR - - - m_axi_awaddr - - - - - AWBURST - - - m_axi_awburst - - - - - AWCACHE - - - m_axi_awcache - - - - - AWID - - - m_axi_awid - - - - - AWLEN - - - m_axi_awlen - - - - - AWLOCK - - - m_axi_awlock - - - - - AWPROT - - - m_axi_awprot - - - - - AWQOS - - - m_axi_awqos - - - - - AWREADY - - - m_axi_awready - - - - - AWREGION - - - m_axi_awregion - - - - - AWSIZE - - - m_axi_awsize - - - - - AWUSER - - - m_axi_awuser - - - - - AWVALID - - - m_axi_awvalid - - - - - BID - - - m_axi_bid - - - - - BREADY - - - m_axi_bready - - - - - BRESP - - - m_axi_bresp - - - - - BUSER - - - m_axi_buser - - - - - BVALID - - - m_axi_bvalid - - - - - RDATA - - - m_axi_rdata - - - - - RID - - - m_axi_rid - - - - - RLAST - - - m_axi_rlast - - - - - RREADY - - - m_axi_rready - - - - - RRESP - - - m_axi_rresp - - - - - RUSER - - - m_axi_ruser - - - - - RVALID - - - m_axi_rvalid - - - - - WDATA - - - m_axi_wdata - - - - - WID - - - m_axi_wid - - - - - WLAST - - - m_axi_wlast - - - - - WREADY - - - m_axi_wready - - - - - WSTRB - - - m_axi_wstrb - - - - - WUSER - - - m_axi_wuser - - - - - WVALID - - - m_axi_wvalid - - - - - - DATA_WIDTH - 32 - - - simulation.tlm - - - - - PROTOCOL - AXI4LITE - - - simulation.tlm - - - - - FREQ_HZ - 100000000 - - - simulation.tlm - - - - - ID_WIDTH - 0 - - - simulation.tlm - - - - - ADDR_WIDTH - 32 - - - simulation.tlm - - - - - AWUSER_WIDTH - 0 - - - simulation.tlm - - - - - ARUSER_WIDTH - 0 - - - simulation.tlm - - - - - WUSER_WIDTH - 0 - - - simulation.tlm - - - - - RUSER_WIDTH - 0 - - - simulation.tlm - - - - - BUSER_WIDTH - 0 - - - simulation.tlm - - - - - READ_WRITE_MODE - READ_WRITE - - - simulation.tlm - - - - - HAS_BURST - 0 - - - simulation.tlm - - - - - HAS_LOCK - 0 - - - simulation.tlm - - - - - HAS_PROT - 1 - - - simulation.tlm - - - - - HAS_CACHE - 0 - - - simulation.tlm - - - - - HAS_QOS - 0 - - - simulation.tlm - - - - - HAS_REGION - 0 - - - simulation.tlm - - - - - HAS_WSTRB - 1 - - - simulation.tlm - - - - - HAS_BRESP - 1 - - - simulation.tlm - - - - - HAS_RRESP - 1 - - - simulation.tlm - - - - - SUPPORTS_NARROW_BURST - 0 - - - simulation.tlm - - - - - NUM_READ_OUTSTANDING - 1 - - - simulation.tlm - - - - - NUM_WRITE_OUTSTANDING - 1 - - - simulation.tlm - - - - - MAX_BURST_LENGTH - 1 - - - simulation.tlm - - - - - PHASE - 0.000 - - - simulation.tlm - - - - - CLK_DOMAIN - - - - simulation.tlm - - - - - NUM_READ_THREADS - 1 - - - simulation.tlm - - - - - NUM_WRITE_THREADS - 1 - - - simulation.tlm - - - - - RUSER_BITS_PER_BYTE - 0 - - - simulation.tlm - - - - - WUSER_BITS_PER_BYTE - 0 - - - simulation.tlm - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - S_AXI - - - - - - - ARADDR - - - s_axi_araddr - - - - - ARBURST - - - s_axi_arburst - - - - - ARCACHE - - - s_axi_arcache - - - - - ARID - - - s_axi_arid - - - - - ARLEN - - - s_axi_arlen - - - - - ARLOCK - - - s_axi_arlock - - - - - ARPROT - - - s_axi_arprot - - - - - ARQOS - - - s_axi_arqos - - - - - ARREADY - - - s_axi_arready - - - - - ARREGION - - - s_axi_arregion - - - - - ARSIZE - - - s_axi_arsize - - - - - ARUSER - - - s_axi_aruser - - - - - ARVALID - - - s_axi_arvalid - - - - - AWADDR - - - s_axi_awaddr - - - - - AWBURST - - - s_axi_awburst - - - - - AWCACHE - - - s_axi_awcache - - - - - AWID - - - s_axi_awid - - - - - AWLEN - - - s_axi_awlen - - - - - AWLOCK - - - s_axi_awlock - - - - - AWPROT - - - s_axi_awprot - - - - - AWQOS - - - s_axi_awqos - - - - - AWREADY - - - s_axi_awready - - - - - AWREGION - - - s_axi_awregion - - - - - AWSIZE - - - s_axi_awsize - - - - - AWUSER - - - s_axi_awuser - - - - - AWVALID - - - s_axi_awvalid - - - - - BID - - - s_axi_bid - - - - - BREADY - - - s_axi_bready - - - - - BRESP - - - s_axi_bresp - - - - - BUSER - - - s_axi_buser - - - - - BVALID - - - s_axi_bvalid - - - - - RDATA - - - s_axi_rdata - - - - - RID - - - s_axi_rid - - - - - RLAST - - - s_axi_rlast - - - - - RREADY - - - s_axi_rready - - - - - RRESP - - - s_axi_rresp - - - - - RUSER - - - s_axi_ruser - - - - - RVALID - - - s_axi_rvalid - - - - - WDATA - - - s_axi_wdata - - - - - WID - - - s_axi_wid - - - - - WLAST - - - s_axi_wlast - - - - - WREADY - - - s_axi_wready - - - - - WSTRB - - - s_axi_wstrb - - - - - WUSER - - - s_axi_wuser - - - - - WVALID - - - s_axi_wvalid - - - - - - DATA_WIDTH - 1 - - - simulation.tlm - - - - - PROTOCOL - AXI4LITE - - - simulation.tlm - - - - - FREQ_HZ - 100000000 - - - simulation.tlm - - - - - ID_WIDTH - 0 - - - simulation.tlm - - - - - ADDR_WIDTH - 1 - - - simulation.tlm - - - - - AWUSER_WIDTH - 0 - - - simulation.tlm - - - - - ARUSER_WIDTH - 0 - - - simulation.tlm - - - - - WUSER_WIDTH - 0 - - - simulation.tlm - - - - - RUSER_WIDTH - 0 - - - simulation.tlm - - - - - BUSER_WIDTH - 0 - - - simulation.tlm - - - - - READ_WRITE_MODE - READ_WRITE - - - simulation.tlm - - - - - HAS_BURST - 0 - - - simulation.tlm - - - - - HAS_LOCK - 0 - - - simulation.tlm - - - - - HAS_PROT - 0 - - - simulation.tlm - - - - - HAS_CACHE - 0 - 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- - - - - - CE - - - aclken - - - - - - POLARITY - ACTIVE_LOW - - - none - - - - - - - - false - - - - - - CLOCK - - - - - - - CLK - - - aclk - - - - - - ASSOCIATED_BUSIF - M_AXI:S_AXI - - - ASSOCIATED_RESET - aresetn - - - FREQ_HZ - 100000000 - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - M_AXI_TLM - - - - - - - AXIMM_READ_SOCKET - - - M_INITIATOR_rd_socket - - - - - AXIMM_WRITE_SOCKET - - - M_INITIATOR_wr_socket - - - - - - S_AXI_TLM - - - - - - - AXIMM_READ_SOCKET - - - S_TARGET_rd_socket - - - - - AXIMM_WRITE_SOCKET - - - S_TARGET_wr_socket - - - - - - - - Master_AXI - 4294967296 - 32 - - - - true - - - - - - - - S_AXI - - Reg - 0 - 65536 - 32 - read-write - - - - false - - - - - - - - - - xilinx_veriloginstantiationtemplate - Verilog Instantiation Template - verilogSource:vivado.xilinx.com:synthesis.template - verilog - - xilinx_veriloginstantiationtemplate_view_fileset - - - - GENtimestamp - Tue Feb 22 20:04:09 UTC 2022 - - - outputProductCRC - 9:0d30786a - - - - - xilinx_verilogsynthesis - Verilog Synthesis - verilogSource:vivado.xilinx.com:synthesis - verilog - axi_vip_v1_1_8_top - - xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset - - - xilinx_verilogsynthesis_view_fileset - - - - GENtimestamp - Tue Feb 22 20:04:13 UTC 2022 - - - outputProductCRC - 9:0d30786a - - - - - xilinx_synthesisconstraints - Synthesis Constraints - :vivado.xilinx.com:synthesis.constraints - - xilinx_synthesisconstraints_view_fileset - - - - GENtimestamp - Tue Feb 22 20:04:13 UTC 2022 - - - outputProductCRC - 9:0d30786a - - - - - xilinx_verilogsynthesiswrapper - Verilog Synthesis Wrapper - verilogSource:vivado.xilinx.com:synthesis.wrapper - verilog - axi_mst_0 - - xilinx_verilogsynthesiswrapper_view_fileset - - - - GENtimestamp - Tue Feb 22 20:04:13 UTC 2022 - - - outputProductCRC - 9:0d30786a - - - - - xilinx_verilogbehavioralsimulation - Verilog Simulation - verilogSource:vivado.xilinx.com:simulation - verilog - axi_vip_v1_1_8_top - - xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset - - - xilinx_verilogbehavioralsimulation_view_fileset - - - - GENtimestamp - Tue Feb 22 20:04:13 UTC 2022 - - - outputProductCRC - 9:b1d08ae7 - - - - - xilinx_systemcsimulation - SystemC Simulation - systemCSource:vivado.xilinx.com:simulation - systemc - axi_vip - - xilinx_systemcsimulation_view_fileset - - - - GENtimestamp - Tue Feb 22 20:04:13 UTC 2022 - - - outputProductCRC - 9:36f18ee7 - - - sim_type - tlm - - - use_subcore_outputs - false - - - - - xilinx_verilogsimulationwrapper - Verilog Simulation Wrapper - verilogSource:vivado.xilinx.com:simulation.wrapper - verilog - axi_mst_0 - - xilinx_verilogsimulationwrapper_view_fileset - - - - GENtimestamp - Tue Feb 22 20:04:13 UTC 2022 - - - outputProductCRC - 9:b1d08ae7 - - - - - xilinx_systemcsimulationwrapper - SystemC Simulation Wrapper - systemCSource:vivado.xilinx.com:simulation.wrapper - systemc - axi_mst_0 - - xilinx_systemcsimulationwrapper_view_fileset - - - - GENtimestamp - Tue Feb 22 20:04:13 UTC 2022 - - - outputProductCRC - 9:36f18ee7 - - - sim_type - tlm - - - - - xilinx_versioninformation - Version Information - :vivado.xilinx.com:docs.versioninfo - axi_vip_v1_1_8_top - - xilinx_versioninformation_view_fileset - - - - GENtimestamp - Tue Feb 22 20:04:13 UTC 2022 - - - outputProductCRC - 9:0d30786a - - - - - xilinx_externalfiles - External Files - :vivado.xilinx.com:external.files - - xilinx_externalfiles_view_fileset - - - - GENtimestamp - Tue Feb 22 20:04:54 UTC 2022 - - - outputProductCRC - 9:0d30786a - - - - - - - aclk - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - aclken - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 1 - - - - - - false - - - - - - aresetn - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 1 - 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- - - - - - false - - - - - - s_axi_wid - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_wdata - - in - - 31 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_wstrb - - in - - 3 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0xF - - - - - - false - - - - - - s_axi_wlast - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_wuser - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_wvalid - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_wready - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - s_axi_bid - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - s_axi_bresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - s_axi_buser - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - s_axi_bvalid - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - s_axi_bready - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arid - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_araddr - - in - - 31 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arlen - - in - - 7 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arsize - - in - - 2 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arburst - - in - - 1 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 1 - - - - - - false - - - - - - s_axi_arlock - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arcache - - in - - 3 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arprot - - in - - 2 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arregion - - in - - 3 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arqos - - in - - 3 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_aruser - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arvalid - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arready - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - s_axi_rid - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - s_axi_rdata - - out - - 31 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - 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xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - m_axi_awlen - - out - - 7 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_awsize - - out - - 2 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_awburst - - out - - 1 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_awlock - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_awcache - - out - - 3 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_awprot - - out - - 2 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - m_axi_awregion - - out - - 3 - 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- out - - 3 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - m_axi_wlast - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_wuser - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_wvalid - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - m_axi_wready - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - true - - - - - - m_axi_bid - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - m_axi_bresp - - in - - 1 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - true - - - - - - m_axi_buser - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - m_axi_bvalid - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - true - - - - - - m_axi_bready - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - m_axi_arid - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_araddr - - out - - 31 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - m_axi_arlen - - out - - 7 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_arsize - - out - - 2 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_arburst - - out - - 1 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_arlock - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_arcache - - out - - 3 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_arprot - - out - - 2 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - m_axi_arregion - - out - - 3 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_arqos - - out - - 3 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_aruser - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_arvalid - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - m_axi_arready - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - true - - - - - - m_axi_rid - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - m_axi_rdata - - in - - 31 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - true - - - - - - m_axi_rresp - - in - - 1 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - true - - - - - - m_axi_rlast - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - m_axi_ruser - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - m_axi_rvalid - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - true - - - - - - m_axi_rready - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - M_INITIATOR_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - M_INITIATOR_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - S_TARGET_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - wr_socket - - - - - - - 1 - - - - - S_TARGET_rd_socket - AXIMM Read Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - rd_socket - - - - - - - 1 - - - - - - - C_AXI_PROTOCOL - 2 - - - C_AXI_INTERFACE_MODE - 0 - - - C_AXI_ADDR_WIDTH - 32 - - - C_AXI_WDATA_WIDTH - 32 - - - C_AXI_RDATA_WIDTH - 32 - - - C_AXI_WID_WIDTH - 0 - - - C_AXI_RID_WIDTH - 0 - - - C_AXI_AWUSER_WIDTH - 0 - - - C_AXI_ARUSER_WIDTH - 0 - - - C_AXI_WUSER_WIDTH - 0 - - - C_AXI_RUSER_WIDTH - 0 - - - C_AXI_BUSER_WIDTH - 0 - - - C_AXI_SUPPORTS_NARROW - 0 - - - C_AXI_HAS_BURST - 0 - - - C_AXI_HAS_LOCK - 0 - - - C_AXI_HAS_CACHE - 0 - - - C_AXI_HAS_REGION - 0 - - - C_AXI_HAS_PROT - 1 - - - C_AXI_HAS_QOS - 0 - - - C_AXI_HAS_WSTRB - 1 - - - C_AXI_HAS_BRESP - 1 - - - C_AXI_HAS_RRESP - 1 - - - C_AXI_HAS_ARESETN - 1 - - - - - - choice_list_04fafd91 - AXI3 - AXI4 - AXI4LITE - - - choice_list_6240decd - READ_ONLY - READ_WRITE - WRITE_ONLY - - - choice_list_642e7122 - MASTER - PASS_THROUGH - SLAVE - - - choice_list_99ba8646 - 32 - 64 - - - choice_list_9d8b0d81 - ACTIVE_HIGH - ACTIVE_LOW - - - choice_pairs_0fc128e8 - 0 - 0 - - - - - xilinx_veriloginstantiationtemplate_view_fileset - - axi_mst_0.vho - vhdlTemplate - - - axi_mst_0.veo - verilogTemplate - - - - xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset - - hdl/axi_infrastructure_v1_1_0.vh - verilogSource - true - axi_infrastructure_v1_1_0 - - - hdl/axi_infrastructure_v1_1_vl_rfs.v - verilogSource - axi_infrastructure_v1_1_0 - - - - - - - - - - - xilinx_verilogsynthesis_view_fileset - - hdl/axi_vip_v1_1_vlsyn_rfs.sv - systemVerilogSource - axi_vip_v1_1_8 - - - - xilinx_synthesisconstraints_view_fileset - - axi_mst_0_ooc.xdc - xdc - USED_IN_implementation - USED_IN_out_of_context - USED_IN_synthesis - - - - xilinx_verilogsynthesiswrapper_view_fileset - - synth/axi_mst_0.sv - systemVerilogSource - xil_defaultlib - - - - xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset - - hdl/axi_infrastructure_v1_1_0.vh - verilogSource - USED_IN_ipstatic - true - axi_infrastructure_v1_1_0 - - - hdl/axi_infrastructure_v1_1_vl_rfs.v - verilogSource - USED_IN_ipstatic - axi_infrastructure_v1_1_0 - - - - - - - - - - - xilinx_verilogbehavioralsimulation_view_fileset - - sim/axi_mst_0_pkg.sv - systemVerilogSource - - - hdl/axi_vip_v1_1_vl_rfs.sv - systemVerilogSource - USED_IN_ipstatic - axi_vip_v1_1_8 - - - - xilinx_systemcsimulation_view_fileset - - sysc/axi_vip.cpp - systemCSource - axi_vip_v1_1_8 - - - sysc/axi_vip.h - systemCSource - true - axi_vip_v1_1_8 - - - - xilinx_verilogsimulationwrapper_view_fileset - - sim/axi_mst_0.sv - systemVerilogSource - xil_defaultlib - - - - xilinx_systemcsimulationwrapper_view_fileset - - sim/axi_mst_0_sc.h - systemCSource - true - - - sim/axi_mst_0_sc.cpp - systemCSource - - - sim/axi_mst_0.h - systemCSource - true - - - sim/axi_mst_0.cpp - systemCSource - - - sim/axi_mst_0_stub.sv - systemVerilogSource - - - - xilinx_versioninformation_view_fileset - - doc/axi_vip_v1_1_changelog.txt - text - axi_vip_v1_1_8 - - - - xilinx_externalfiles_view_fileset - - axi_mst_0.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - axi_mst_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - axi_mst_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - axi_mst_0_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - axi_mst_0_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - - The AXI Verification IP. - - - Component_Name - Component Name - axi_mst_0 - - - PROTOCOL - PROTOCOL - AXI4LITE - - - READ_WRITE_MODE - READ_WRITE MODE - READ_WRITE - - - INTERFACE_MODE - INTERFACE MODE - MASTER - - - ADDR_WIDTH - ADDRESS WIDTH - 32 - - - DATA_WIDTH - DATA WIDTH - 32 - - - ID_WIDTH - ID WIDTH - 0 - - - - false - - - - - - AWUSER_WIDTH - AWUSER WIDTH - 0 - - - - false - - - - - - ARUSER_WIDTH - ARUSER WIDTH - 0 - - - - false - - - - - - RUSER_WIDTH - RUSER WIDTH - 0 - - - - false - - - - - - WUSER_WIDTH - WUSER WIDTH - 0 - - - - false - - - - - - BUSER_WIDTH - BUSER WIDTH - 0 - - - - false - - - - - - WUSER_BITS_PER_BYTE - WUSER BITS PER BYTE - 0 - - - - false - - - - - - RUSER_BITS_PER_BYTE - RUSER BITS PER BYTE - 0 - - - - false - - - - - - HAS_USER_BITS_PER_BYTE - HAS USER_BITS_PER_BYTE - 0 - - - - false - - - - - - SUPPORTS_NARROW - SUPPORTS NARROW - 0 - - - - false - - - - - - HAS_SIZE - HAS SIZE - 0 - - - - false - - - - - - HAS_BURST - HAS BURST - 0 - - - - false - - - - - - HAS_LOCK - HAS LOCK - 0 - - - - false - - - - - - HAS_CACHE - HAS CACHE - 0 - - - - false - - - - - - HAS_REGION - HAS REGION - 0 - - - - false - - - - - - HAS_QOS - HAS QOS - 0 - - - - false - - - - - - HAS_PROT - HAS PROT - 1 - - - HAS_WSTRB - HAS WSTRB - 1 - - - HAS_BRESP - HAS BRESP - 1 - - - HAS_RRESP - HAS RRESP - 1 - - - HAS_ACLKEN - HAS ACLKEN - 0 - - - HAS_ARESETN - HAS ARESETN - 1 - - - - - AXI Verification IP - - xtlm - - 8 - true - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2020.2 - - - - - - - - - - diff --git a/qick/firmware/ip/axis_sg_mux4_v1/src/axi_slv.vhd b/qick/firmware/ip/axis_sg_mux4_v1/src/axi_slv.vhd deleted file mode 100644 index bcce170..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v1/src/axi_slv.vhd +++ /dev/null @@ -1,525 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity axi_slv is - Generic - ( - DATA_WIDTH : integer := 32; - ADDR_WIDTH : integer := 6 - ); - Port - ( - aclk : in std_logic; - aresetn : in std_logic; - - -- Write Address Channel. - awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); - awprot : in std_logic_vector(2 downto 0); - awvalid : in std_logic; - awready : out std_logic; - - -- Write Data Channel. - wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); - wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); - wvalid : in std_logic; - wready : out std_logic; - - -- Write Response Channel. - bresp : out std_logic_vector(1 downto 0); - bvalid : out std_logic; - bready : in std_logic; - - -- Read Address Channel. - araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); - arprot : in std_logic_vector(2 downto 0); - arvalid : in std_logic; - arready : out std_logic; - - -- Read Data Channel. - rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); - rresp : out std_logic_vector(1 downto 0); - rvalid : out std_logic; - rready : in std_logic; - - -- Registers. - PINC0_REG : out std_logic_vector (15 downto 0); - PINC1_REG : out std_logic_vector (15 downto 0); - PINC2_REG : out std_logic_vector (15 downto 0); - PINC3_REG : out std_logic_vector (15 downto 0); - WE_REG : out std_logic - ); -end axi_slv; - -architecture rtl of axi_slv is - - -- AXI4LITE signals - signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); - signal axi_awready : std_logic; - signal axi_wready : std_logic; - signal axi_bresp : std_logic_vector(1 downto 0); - signal axi_bvalid : std_logic; - signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); - signal axi_arready : std_logic; - signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); - signal axi_rresp : std_logic_vector(1 downto 0); - signal axi_rvalid : std_logic; - - -- Example-specific design signals - -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH - -- ADDR_LSB is used for addressing 32/64 bit registers/memories - -- ADDR_LSB = 2 for 32 bits (n downto 2) - -- ADDR_LSB = 3 for 64 bits (n downto 3) - constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; - constant OPT_MEM_ADDR_BITS : integer := 3; - ------------------------------------------------ - ---- Signals for user logic register space example - -------------------------------------------------- - ---- Number of Slave Registers 16 - signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg_rden : std_logic; - signal slv_reg_wren : std_logic; - signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); - signal byte_index : integer; - signal aw_en : std_logic; - -begin - -- I/O Connections assignments - - awreadY <= axi_awready; - wready <= axi_wready; - bresp <= axi_bresp; - bvalid <= axi_bvalid; - arreadY <= axi_arready; - rdata <= axi_rdata; - rresp <= axi_rresp; - rvalid <= axi_rvalid; - -- Implement axi_awready generation - -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is - -- de-asserted when reset is low. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_awready <= '0'; - aw_en <= '1'; - else - if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then - -- slave is ready to accept write address when - -- there is a valid write address and write data - -- on the write address and data bus. This design - -- expects no outstanding transactions. - axi_awready <= '1'; - aw_en <= '0'; - elsif (bready = '1' and axi_bvalid = '1') then - aw_en <= '1'; - axi_awready <= '0'; - else - axi_awready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement axi_awaddr latching - -- This process is used to latch the address when both - -- S_AXI_AWVALID and S_AXI_WVALID are valid. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_awaddr <= (others => '0'); - else - if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then - -- Write Address latching - axi_awaddr <= awaddr; - end if; - end if; - end if; - end process; - - -- Implement axi_wready generation - -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is - -- de-asserted when reset is low. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_wready <= '0'; - else - if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then - -- slave is ready to accept write data when - -- there is a valid write address and write data - -- on the write address and data bus. This design - -- expects no outstanding transactions. - axi_wready <= '1'; - else - axi_wready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement memory mapped register select and write logic generation - -- The write data is accepted and written to memory mapped registers when - -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to - -- select byte enables of slave registers while writing. - -- These registers are cleared when reset (active low) is applied. - -- Slave register write enable is asserted when valid address and data are available - -- and the slave is ready to accept the write address and write data. - slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; - - process (aclk) - variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); - begin - if rising_edge(aclk) then - if aresetn = '0' then - slv_reg0 <= (others => '0'); - slv_reg1 <= (others => '0'); - slv_reg2 <= (others => '0'); - slv_reg3 <= (others => '0'); - slv_reg4 <= (others => '0'); - slv_reg5 <= (others => '0'); - slv_reg6 <= (others => '0'); - slv_reg7 <= (others => '0'); - slv_reg8 <= (others => '0'); - slv_reg9 <= (others => '0'); - slv_reg10 <= (others => '0'); - slv_reg11 <= (others => '0'); - slv_reg12 <= (others => '0'); - slv_reg13 <= (others => '0'); - slv_reg14 <= (others => '0'); - slv_reg15 <= (others => '0'); - else - loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); - if (slv_reg_wren = '1') then - case loc_addr is - when b"0000" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 0 - slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0001" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 1 - slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0010" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 2 - slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0011" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 3 - slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0100" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 4 - slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0101" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 5 - slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0110" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 6 - slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0111" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 7 - slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1000" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 8 - slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1001" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 9 - slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1010" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 10 - slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1011" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 11 - slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1100" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 12 - slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1101" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 13 - slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1110" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 14 - slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1111" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 15 - slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when others => - slv_reg0 <= slv_reg0; - slv_reg1 <= slv_reg1; - slv_reg2 <= slv_reg2; - slv_reg3 <= slv_reg3; - slv_reg4 <= slv_reg4; - slv_reg5 <= slv_reg5; - slv_reg6 <= slv_reg6; - slv_reg7 <= slv_reg7; - slv_reg8 <= slv_reg8; - slv_reg9 <= slv_reg9; - slv_reg10 <= slv_reg10; - slv_reg11 <= slv_reg11; - slv_reg12 <= slv_reg12; - slv_reg13 <= slv_reg13; - slv_reg14 <= slv_reg14; - slv_reg15 <= slv_reg15; - end case; - end if; - end if; - end if; - end process; - - -- Implement write response logic generation - -- The write response and response valid signals are asserted by the slave - -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. - -- This marks the acceptance of address and indicates the status of - -- write transaction. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_bvalid <= '0'; - axi_bresp <= "00"; --need to work more on the responses - else - if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then - axi_bvalid <= '1'; - axi_bresp <= "00"; - elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) - axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) - end if; - end if; - end if; - end process; - - -- Implement axi_arready generation - -- axi_arready is asserted for one S_AXI_ACLK clock cycle when - -- S_AXI_ARVALID is asserted. axi_awready is - -- de-asserted when reset (active low) is asserted. - -- The read address is also latched when S_AXI_ARVALID is - -- asserted. axi_araddr is reset to zero on reset assertion. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_arready <= '0'; - axi_araddr <= (others => '1'); - else - if (axi_arready = '0' and arvalid = '1') then - -- indicates that the slave has acceped the valid read address - axi_arready <= '1'; - -- Read Address latching - axi_araddr <= araddr; - else - axi_arready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement axi_arvalid generation - -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_ARVALID and axi_arready are asserted. The slave registers - -- data are available on the axi_rdata bus at this instance. The - -- assertion of axi_rvalid marks the validity of read data on the - -- bus and axi_rresp indicates the status of read transaction.axi_rvalid - -- is deasserted on reset (active low). axi_rresp and axi_rdata are - -- cleared to zero on reset (active low). - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_rvalid <= '0'; - axi_rresp <= "00"; - else - if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then - -- Valid read data is available at the read data bus - axi_rvalid <= '1'; - axi_rresp <= "00"; -- 'OKAY' response - elsif (axi_rvalid = '1' and rready = '1') then - -- Read data is accepted by the master - axi_rvalid <= '0'; - end if; - end if; - end if; - end process; - - -- Implement memory mapped register select and read logic generation - -- Slave register read enable is asserted when valid address is available - -- and the slave is ready to accept the read address. - slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; - - process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) - variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); - begin - -- Address decoding for reading registers - loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); - case loc_addr is - when b"0000" => - reg_data_out <= slv_reg0; - when b"0001" => - reg_data_out <= slv_reg1; - when b"0010" => - reg_data_out <= slv_reg2; - when b"0011" => - reg_data_out <= slv_reg3; - when b"0100" => - reg_data_out <= slv_reg4; - when b"0101" => - reg_data_out <= slv_reg5; - when b"0110" => - reg_data_out <= slv_reg6; - when b"0111" => - reg_data_out <= slv_reg7; - when b"1000" => - reg_data_out <= slv_reg8; - when b"1001" => - reg_data_out <= slv_reg9; - when b"1010" => - reg_data_out <= slv_reg10; - when b"1011" => - reg_data_out <= slv_reg11; - when b"1100" => - reg_data_out <= slv_reg12; - when b"1101" => - reg_data_out <= slv_reg13; - when b"1110" => - reg_data_out <= slv_reg14; - when b"1111" => - reg_data_out <= slv_reg15; - when others => - reg_data_out <= (others => '0'); - end case; - end process; - - -- Output register or memory read data - process( aclk ) is - begin - if (rising_edge (aclk)) then - if ( aresetn = '0' ) then - axi_rdata <= (others => '0'); - else - if (slv_reg_rden = '1') then - -- When there is a valid read address (S_AXI_ARVALID) with - -- acceptance of read address by the slave (axi_arready), - -- output the read dada - -- Read address mux - axi_rdata <= reg_data_out; -- register read data - end if; - end if; - end if; - end process; - - -- Register Map. - -- 0 : PINC0_REG : 16-bit. Frequency of output 0. - -- 1 : PINC1_REG : 16-bit. Frequency of output 1. - -- 2 : PINC2_REG : 16-bit. Frequency of output 2. - -- 3 : PINC3_REG : 16-bit. Frequency of output 3. - -- 4 : WE_REG : 1-bit. Register write. - - -- Output Registers. - PINC0_REG <= slv_reg0(15 downto 0); - PINC1_REG <= slv_reg1(15 downto 0); - PINC2_REG <= slv_reg2(15 downto 0); - PINC3_REG <= slv_reg3(15 downto 0); - WE_REG <= slv_reg4(0); - -end rtl; - diff --git a/qick/firmware/ip/axis_sg_mux4_v1/src/axis_sg_mux4.v b/qick/firmware/ip/axis_sg_mux4_v1/src/axis_sg_mux4.v deleted file mode 100644 index 5b55552..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v1/src/axis_sg_mux4.v +++ /dev/null @@ -1,182 +0,0 @@ -// Signal Generator V4. -// s_axi_aclk : clock for s_axi_* -// aclk : clock for s_axis_* and m_axis_* -// -module axis_sg_mux4_v1 - ( - // AXI Slave I/F for configuration. - s_axi_aclk , - s_axi_aresetn , - - s_axi_awaddr , - s_axi_awprot , - s_axi_awvalid , - s_axi_awready , - - s_axi_wdata , - s_axi_wstrb , - s_axi_wvalid , - s_axi_wready , - - s_axi_bresp , - s_axi_bvalid , - s_axi_bready , - - s_axi_araddr , - s_axi_arprot , - s_axi_arvalid , - s_axi_arready , - - s_axi_rdata , - s_axi_rresp , - s_axi_rvalid , - s_axi_rready , - - // s_* and m_* reset/clock. - aclk , - aresetn , - - // S_AXIS to queue waveforms. - s_axis_tready , - s_axis_tvalid , - s_axis_tdata , - - // AXIS Master for output. - m_axis_tready , - m_axis_tvalid , - m_axis_tdata - ); - -/**************/ -/* Parameters */ -/**************/ -// Number of parallel dds blocks. -parameter [31:0] N_DDS = 2; - -/*********/ -/* Ports */ -/*********/ -input s_axi_aclk; -input s_axi_aresetn; - -input [5:0] s_axi_awaddr; -input [2:0] s_axi_awprot; -input s_axi_awvalid; -output s_axi_awready; - -input [31:0] s_axi_wdata; -input [3:0] s_axi_wstrb; -input s_axi_wvalid; -output s_axi_wready; - -output [1:0] s_axi_bresp; -output s_axi_bvalid; -input s_axi_bready; - -input [5:0] s_axi_araddr; -input [2:0] s_axi_arprot; -input s_axi_arvalid; -output s_axi_arready; - -output [31:0] s_axi_rdata; -output [1:0] s_axi_rresp; -output s_axi_rvalid; -input s_axi_rready; - -input aresetn; -input aclk; - -output s_axis_tready; -input s_axis_tvalid; -input [39:0] s_axis_tdata; - -input m_axis_tready; -output m_axis_tvalid; -output [N_DDS*32-1:0] m_axis_tdata; - -/********************/ -/* Internal signals */ -/********************/ -// Registers. -wire [15:0] PINC0_REG; -wire [15:0] PINC1_REG; -wire [15:0] PINC2_REG; -wire [15:0] PINC3_REG; -wire WE_REG; - -/**********************/ -/* Begin Architecture */ -/**********************/ -// AXI Slave. -axi_slv axi_slv_i - ( - .aclk (s_axi_aclk ), - .aresetn (s_axi_aresetn ), - - // Write Address Channel. - .awaddr (s_axi_awaddr ), - .awprot (s_axi_awprot ), - .awvalid (s_axi_awvalid ), - .awready (s_axi_awready ), - - // Write Data Channel. - .wdata (s_axi_wdata ), - .wstrb (s_axi_wstrb ), - .wvalid (s_axi_wvalid ), - .wready (s_axi_wready ), - - // Write Response Channel. - .bresp (s_axi_bresp ), - .bvalid (s_axi_bvalid ), - .bready (s_axi_bready ), - - // Read Address Channel. - .araddr (s_axi_araddr ), - .arprot (s_axi_arprot ), - .arvalid (s_axi_arvalid ), - .arready (s_axi_arready ), - - // Read Data Channel. - .rdata (s_axi_rdata ), - .rresp (s_axi_rresp ), - .rvalid (s_axi_rvalid ), - .rready (s_axi_rready ), - - // Registers. - .PINC0_REG (PINC0_REG ), - .PINC1_REG (PINC1_REG ), - .PINC2_REG (PINC2_REG ), - .PINC3_REG (PINC3_REG ), - .WE_REG (WE_REG ) - ); - -sg_mux4 - #( - .N_DDS (N_DDS ) - ) - sg_mux4_i - ( - // Reset and clock. - .aresetn (aresetn ), - .aclk (aclk ), - - // S_AXIS to queue waveforms. - .s_axis_tready_o (s_axis_tready ), - .s_axis_tvalid_i (s_axis_tvalid ), - .s_axis_tdata_i (s_axis_tdata ), - - // M_AXIS for output. - .m_axis_tready_i (m_axis_tready ), - .m_axis_tvalid_o (m_axis_tvalid ), - .m_axis_tdata_o (m_axis_tdata ), - - // Registers. - .PINC0_REG (PINC0_REG ), - .PINC1_REG (PINC1_REG ), - .PINC2_REG (PINC2_REG ), - .PINC3_REG (PINC3_REG ), - .WE_REG (WE_REG ) - ); - -endmodule - diff --git a/qick/firmware/ip/axis_sg_mux4_v1/src/ctrl.sv b/qick/firmware/ip/axis_sg_mux4_v1/src/ctrl.sv deleted file mode 100644 index e1ccea9..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v1/src/ctrl.sv +++ /dev/null @@ -1,175 +0,0 @@ -//Format of waveform interface: -// |----------|---------| -// | 39 .. 32 | 31 .. 0 | -// |----------|---------| -// | mask | nsamp | -// |----------|---------| -// nsamp : 32 bits -// mask : 8 bits -// -// Total : 40. -module ctrl ( - // Reset and clock. - rstn , - clk , - - // Fifo interface. - fifo_rd_en_o , - fifo_empty_i , - fifo_dout_i , - - // Mask output. - mask_o , - - // Output enable. - en_o ); - -// Ports. -input rstn; -input clk; -output fifo_rd_en_o; -input fifo_empty_i; -input [39:0] fifo_dout_i; -output [7:0] mask_o; -output en_o; - -// States. -typedef enum { READ_ST , - CNT_ST - } state_t; - -// State register. -(* fsm_encoding = "one_hot" *) state_t state; - -reg rd_en_int; - -// Fifo dout register. -reg [39:0] fifo_dout_r; - -// Number of samples. -wire [31:0] nsamp_int; - -// Mask. -wire [7:0] mask_int; -wire [7:0] mask_la; - -// Counter. -reg [31:0] cnt; - -// Output enable register. -reg en_reg; -wire en_reg_la; - -// Load register. -reg load_r; - -// Latency for mask. -latency_reg - #( - .N(2), - .B(8) - ) - mask_latency_reg_i - ( - .rstn (rstn ), - .clk (clk ), - - .din (mask_int ), - .dout (mask_la ) - ); - -// Latency for en_reg. -latency_reg - #( - .N(3), - .B(1) - ) - en_reg_latency_reg_i - ( - .rstn (rstn ), - .clk (clk ), - - .din (en_reg ), - .dout (en_reg_la ) - ); - - -// Registers. -always @(posedge clk) begin - if (~rstn) begin - // State register. - state <= READ_ST; - - // Fifo dout register. - fifo_dout_r <= 0; - - // Counter. - cnt <= 0; - - // Output enable register. - en_reg <= 0; - - // Load enable flag. - load_r <= 0; - end - else begin - // State register. - case (state) - READ_ST: - if (~fifo_empty_i) - state <= CNT_ST; - CNT_ST: - if ( cnt == nsamp_int-2 ) - state <= READ_ST; - endcase - - // Fifo dout register. - if (load_r) - fifo_dout_r <= fifo_dout_i; - - // Load enable flag. - load_r <= load_int; - - // Counter. - if (rd_en_int) - cnt <= 0; - else - cnt <= cnt + 1; - - // Output enable register. - if (rd_en_int) - if (!fifo_empty_i) - en_reg <= 1; - else - en_reg <= 0; - end -end - -// FSM outputs. -always_comb begin - // Default. - rd_en_int = 0; - - case (state) - READ_ST: - rd_en_int = 1; - - CNT_ST: - rd_en_int = 0; - endcase -end - -// Fifo output fields. -assign nsamp_int = fifo_dout_r[31:0]; -assign mask_int = fifo_dout_r[39:32]; - -// load_int. -assign load_int = rd_en_int & ~fifo_empty_i; - -// Assign outputs. -assign fifo_rd_en_o = rd_en_int; -assign mask_o = mask_la; -assign en_o = en_reg_la; - -endmodule - diff --git a/qick/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.veo b/qick/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.veo deleted file mode 100644 index c3dea29..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.veo +++ /dev/null @@ -1,69 +0,0 @@ -// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -// IP VLNV: xilinx.com:ip:dds_compiler:6.0 -// IP Revision: 20 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -dds_compiler_0 your_instance_name ( - .aclk(aclk), // input wire aclk - .s_axis_phase_tvalid(s_axis_phase_tvalid), // input wire s_axis_phase_tvalid - .s_axis_phase_tdata(s_axis_phase_tdata), // input wire [39 : 0] s_axis_phase_tdata - .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid - .m_axis_data_tdata(m_axis_data_tdata) // output wire [31 : 0] m_axis_data_tdata -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file dds_compiler_0.v when simulating -// the core, dds_compiler_0. When compiling the wrapper file, be sure to -// reference the Verilog simulation library. - diff --git a/qick/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.vho b/qick/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.vho deleted file mode 100644 index 4db3fc6..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.vho +++ /dev/null @@ -1,83 +0,0 @@ --- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:dds_compiler:6.0 --- IP Revision: 20 - --- The following code must appear in the VHDL architecture header. - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT dds_compiler_0 - PORT ( - aclk : IN STD_LOGIC; - s_axis_phase_tvalid : IN STD_LOGIC; - s_axis_phase_tdata : IN STD_LOGIC_VECTOR(39 DOWNTO 0); - m_axis_data_tvalid : OUT STD_LOGIC; - m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) - ); -END COMPONENT; --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : dds_compiler_0 - PORT MAP ( - aclk => aclk, - s_axis_phase_tvalid => s_axis_phase_tvalid, - s_axis_phase_tdata => s_axis_phase_tdata, - m_axis_data_tvalid => m_axis_data_tvalid, - m_axis_data_tdata => m_axis_data_tdata - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file dds_compiler_0.vhd when simulating --- the core, dds_compiler_0. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/qick/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.xci b/qick/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.xci deleted file mode 100644 index 274be99..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.xci +++ /dev/null @@ -1,315 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - dds_compiler_0 - - - - 100000000 - 0 - 0 - 0.000 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 5 - 0 - 0 - 0 - 16 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 1 - 0 - 1 - 0 - 1 - 0 - 0 - 10 - 1 - 0 - 9 - 0 - 32 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 2 - 0 - 16 - 14 - 3 - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - 3 - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - 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vhdlSource - - - - xilinx_versioninformation_view_fileset - - doc/dds_compiler_v6_0_changelog.txt - text - - - - xilinx_externalfiles_view_fileset - - dds_compiler_0.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - dds_compiler_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - dds_compiler_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - dds_compiler_0_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - dds_compiler_0_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - - The Xilinx DDS Compiler LogiCORE provides Direct Digital Synthesizers (DDS) and optionally either Phase Generator or Sine/Cosine Lookup Table constituent parts as independent cores. The core features sine, cosine or quadrature outputs with 3 to 26-bit output sample precision. The core supports up to 16 channels by time-sharing the sine/cosine table which dramatically reduces the area requirement when multiple channels are needed. Phase Dithering and Taylor Series Correction options provide high dynamic range signals using minimal FPGA resources. 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Negative_Cosine - Negative Cosine - false - - - Amplitude_Mode - Amplitude Mode - Full_Range - - - Memory_Type - Memory Type - Auto - - - Optimization_Goal - Optimization Goal - Speed - - - DSP48_Use - DSP48 Use - Maximal - - - Has_Phase_Out - Has Phase Out - false - - - DATA_Has_TLAST - DATA Has TLAST - Not_Required - - - Has_TREADY - Output TREADY - false - - - S_PHASE_Has_TUSER - Input - Not_Required - - - S_PHASE_TUSER_Width - User Field Width - 1 - - - M_DATA_Has_TUSER - DATA Output - Not_Required - - - M_PHASE_Has_TUSER - PHASE Output - Not_Required - - - S_CONFIG_Sync_Mode - Synchronization Mode - On_Vector - - - OUTPUT_FORM - Output Form - Twos_Complement - - - Latency_Configuration - Configurable - - - Latency - 10 - - - Has_ARESETn - ARESETn (active low) - false - - - Has_ACLKEN - ACLKEN - false - - - Output_Frequency1 - 0 - - - PINC1 - 0 - - - Phase_Offset_Angles1 - 0 - - - POFF1 - 0 - - - Output_Frequency2 - 0 - - - PINC2 - 0 - - - Phase_Offset_Angles2 - 0 - - - POFF2 - 0 - - - Output_Frequency3 - 0 - - - PINC3 - 0 - - - Phase_Offset_Angles3 - 0 - - - POFF3 - 0 - - - Output_Frequency4 - 0 - - - PINC4 - 0 - - - Phase_Offset_Angles4 - 0 - - - POFF4 - 0 - - - Output_Frequency5 - 0 - - - PINC5 - 0 - - - Phase_Offset_Angles5 - 0 - - - POFF5 - 0 - - - Output_Frequency6 - 0 - - - PINC6 - 0 - - - Phase_Offset_Angles6 - 0 - - - POFF6 - 0 - - - Output_Frequency7 - 0 - - - PINC7 - 0 - - - Phase_Offset_Angles7 - 0 - - - POFF7 - 0 - - - Output_Frequency8 - 0 - - - PINC8 - 0 - - - Phase_Offset_Angles8 - 0 - - - POFF8 - 0 - - - Output_Frequency9 - 0 - - - PINC9 - 0 - - - Phase_Offset_Angles9 - 0 - - - POFF9 - 0 - - - Output_Frequency10 - 0 - - - PINC10 - 0 - - - Phase_Offset_Angles10 - 0 - - - POFF10 - 0 - - - Output_Frequency11 - 0 - - - PINC11 - 0 - - - Phase_Offset_Angles11 - 0 - - - POFF11 - 0 - - - Output_Frequency12 - 0 - - - PINC12 - 0 - - - Phase_Offset_Angles12 - 0 - - - POFF12 - 0 - - - Output_Frequency13 - 0 - - - PINC13 - 0 - - - Phase_Offset_Angles13 - 0 - - - POFF13 - 0 - - - Output_Frequency14 - 0 - - - PINC14 - 0 - - - Phase_Offset_Angles14 - 0 - - - POFF14 - 0 - - - Output_Frequency15 - 0 - - - PINC15 - 0 - - - Phase_Offset_Angles15 - 0 - - - POFF15 - 0 - - - Output_Frequency16 - 0 - - - PINC16 - 0 - - - Phase_Offset_Angles16 - 0 - - - POFF16 - 0 - - - POR_mode - POR Mode - false - - - GUI_Behaviour - Coregen - - - explicit_period - false - - - period - 1 - - - - - DDS Compiler - 20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2020.2 - - - - - - - - diff --git a/qick/firmware/ip/axis_sg_mux4_v1/src/dds_top.v b/qick/firmware/ip/axis_sg_mux4_v1/src/dds_top.v deleted file mode 100644 index 587b63d..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v1/src/dds_top.v +++ /dev/null @@ -1,120 +0,0 @@ -module dds_top ( - // Reset and clock. - rstn , - clk , - - // DDS output. - dds_dout_o , - - // Registers. - PINC_REG , - WE_REG - ); - -/**************/ -/* Parameters */ -/**************/ -// Number of parallel dds blocks. -parameter [31:0] N_DDS = 2; - -/*********/ -/* Ports */ -/*********/ -input rstn; -input clk; - -output [N_DDS*32-1:0] dds_dout_o; - -input [15:0] PINC_REG; -input WE_REG; - -/********************/ -/* Internal signals */ -/********************/ -// DDS input control. -reg dds_tvalid_r; -wire [N_DDS*40-1:0] dds_ctrl_int; -reg [N_DDS*40-1:0] dds_ctrl_int_r; - -// DDS output. -wire [31:0] dds_dout [0:N_DDS-1]; -wire [31:0] dds_dout_la [0:N_DDS-1]; - -/**********************/ -/* Begin Architecture */ -/**********************/ -// Phase Control block. -phase_ctrl - #( - .N_DDS (N_DDS ) - ) - phase_ctrl_i - ( - // Reset and clock. - .rstn (rstn ), - .clk (clk ), - - // dds control. - .dds_ctrl_o (dds_ctrl_int ), - - // Registers. - .PINC_REG (PINC_REG ), - .WE_REG (WE_REG ) - ); - -generate -genvar i; - for (i=0; i N_LOG2, - -- Data width. - B => B - ) - Port map ( - clk => clk , - ena => '1' , - enb => rd_en , - wea => mem_wea , - addra => std_logic_vector(wptr) , - addrb => std_logic_vector(rptr) , - dia => din , - dob => mem_dob - ); - --- Memory connections. -mem_wea <= wr_en when full_i = '0' else - '0'; - --- Full/empty signals. -full_i <= '1' when wptr = rptr - 1 else - '0'; -empty_i <= '1' when wptr = rptr else - '0'; - --- wr_clk registers. -process (clk) -begin - if ( rising_edge(clk) ) then - if ( rstn = '0' ) then - wptr <= (others => '0'); - rptr <= (others => '0'); - else - -- Write. - if ( wr_en = '1' and full_i = '0' ) then - -- Write data. - - -- Increment pointer. - wptr <= wptr + 1; - end if; - - -- Read. - if ( rd_en = '1' and empty_i = '0' ) then - -- Read data. - - -- Increment pointer. - rptr <= rptr + 1; - end if; - end if; - end if; -end process; - --- Assign outputs. -dout <= mem_dob; -full <= full_i; -empty <= empty_i; - -end rtl; - diff --git a/qick/firmware/ip/axis_sg_mux4_v1/src/fifo/fifo_axi.vhd b/qick/firmware/ip/axis_sg_mux4_v1/src/fifo/fifo_axi.vhd deleted file mode 100644 index e1f76f7..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v1/src/fifo/fifo_axi.vhd +++ /dev/null @@ -1,147 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo_axi is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo_axi; - -architecture rtl of fifo_axi is - --- FIFO. -component fifo is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end component; - --- FIFO read to AXI adapter. -component rd2axi is - Generic - ( - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- FIFO Read I/F. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (B-1 downto 0); - fifo_empty : in std_logic; - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - empty : out std_logic - ); -end component; - -signal rd_en_i : std_logic; -signal dout_i : std_logic_vector (B-1 downto 0); -signal empty_i : std_logic; - -begin - --- FIFO. -fifo_i : fifo - Generic map - ( - -- Data width. - B => B, - - -- Fifo depth. - N => N - ) - Port map - ( - rstn => rstn , - clk => clk , - - -- Write I/F. - wr_en => wr_en , - din => din , - - -- Read I/F. - rd_en => rd_en_i , - dout => dout_i , - - -- Flags. - full => full , - empty => empty_i - ); - --- FIFO read to AXI adapter. -rd2axi_i : rd2axi - Generic map - ( - -- Data width. - B => B - ) - Port map - ( - rstn => rstn , - clk => clk , - - -- FIFO Read I/F. - fifo_rd_en => rd_en_i , - fifo_dout => dout_i , - fifo_empty => empty_i , - - -- Read I/F. - rd_en => rd_en , - dout => dout , - empty => empty - ); - -end rtl; - diff --git a/qick/firmware/ip/axis_sg_mux4_v1/src/fifo/fifo_dc.vhd b/qick/firmware/ip/axis_sg_mux4_v1/src/fifo/fifo_dc.vhd deleted file mode 100644 index c214fae..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v1/src/fifo/fifo_dc.vhd +++ /dev/null @@ -1,291 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo_dc is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - wr_rstn : in std_logic; - wr_clk : in std_logic; - - rd_rstn : in std_logic; - rd_clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo_dc; - -architecture rtl of fifo_dc is - --- Number of bits of depth. -constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); - --- Binary to gray converter. -component bin2gray is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end component; - --- Gray to binary converter. -component gray2bin is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end component; - --- Vector synchronizer (only for gray coded). -component synchronizer_vect is - generic ( - -- Sync stages. - N : Integer := 2; - - -- Data width. - B : Integer := 8 - ); - port ( - rstn : in std_logic; - clk : in std_logic; - data_in : in std_logic_vector (B-1 downto 0); - data_out : out std_logic_vector (B-1 downto 0) - ); -end component; - --- Dual port BRAM. -component bram_dp is - Generic ( - -- Memory address size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - ena : in STD_LOGIC; - enb : in STD_LOGIC; - wea : in STD_LOGIC; - web : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR (N-1 downto 0); - addrb : in STD_LOGIC_VECTOR (N-1 downto 0); - dia : in STD_LOGIC_VECTOR (B-1 downto 0); - dib : in STD_LOGIC_VECTOR (B-1 downto 0); - doa : out STD_LOGIC_VECTOR (B-1 downto 0); - dob : out STD_LOGIC_VECTOR (B-1 downto 0) - ); -end component; - --- Pointers. -signal wptr : unsigned (N_LOG2-1 downto 0); -signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); -signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); -signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); -signal rptr : unsigned (N_LOG2-1 downto 0); -signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); -signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); -signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); - --- Memory signals. -signal mem_wea : std_logic; -signal mem_dib : std_logic_vector (B-1 downto 0); -signal mem_doa : std_logic_vector (B-1 downto 0); -signal mem_dob : std_logic_vector (B-1 downto 0); - --- Flags. -signal full_i : std_logic; -signal empty_i : std_logic; - -begin - --- wptr_i: binary to gray. -wptr_i : bin2gray - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => std_logic_vector(wptr), - dout => wptr_g - ); - --- wptr_g: write to read domain. -wptr_g_i : synchronizer_vect - generic map ( - -- Sync stages. - N => 2, - - -- Data width. - B => N_LOG2 - ) - port map ( - rstn => rd_rstn, - clk => rd_clk, - data_in => wptr_g, - data_out => wptr_gc - ); - --- wptr_gc_i -wptr_gc_i : gray2bin - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => wptr_gc, - dout => wptr_c - ); - --- rptr_i: binary to gray. -rptr_i : bin2gray - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => std_logic_vector(rptr), - dout => rptr_g - ); - --- rptr_g: read to write domain. -rptr_g_i : synchronizer_vect - generic map ( - -- Sync stages. - N => 2, - - -- Data width. - B => N_LOG2 - ) - port map ( - rstn => wr_rstn, - clk => wr_clk, - data_in => rptr_g, - data_out => rptr_gc - ); - --- rptr_gc_i -rptr_gc_i : gray2bin - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => rptr_gc, - dout => rptr_c - ); - --- FIFO memory. -mem_i : bram_dp - Generic map ( - -- Memory address size. - N => N_LOG2, - -- Data width. - B => B - ) - Port map ( - clka => wr_clk, - clkb => rd_clk, - ena => '1', - enb => rd_en, - wea => mem_wea, - web => '0', - addra => std_logic_vector(wptr), - addrb => std_logic_vector(rptr), - dia => din, - dib => mem_dib, - doa => mem_doa, - dob => mem_dob - ); --- Memory connections. -mem_wea <= wr_en when full_i = '0' else - '0'; -mem_dib <= (others => '0'); - --- Full/empty signals. -full_i <= '1' when wptr = unsigned(rptr_c) - 1 else - '0'; -empty_i <= '1' when unsigned(wptr_c) = rptr else - '0'; - --- wr_clk registers. -process (wr_clk) -begin - if ( rising_edge(wr_clk) ) then - if ( wr_rstn = '0' ) then - wptr <= (others => '0'); - else - -- Write. - if ( wr_en = '1' and full_i = '0' ) then - -- Write data. - - -- Increment pointer. - wptr <= wptr + 1; - end if; - end if; - end if; -end process; - --- rd_clk registers. -process (rd_clk) -begin - if ( rising_edge(rd_clk) ) then - if ( rd_rstn = '0' ) then - rptr <= (others => '0'); - else - -- Read. - if ( rd_en = '1' and empty_i = '0' ) then - -- Read data. - - -- Increment pointer. - rptr <= rptr + 1; - end if; - end if; - end if; -end process; - --- Assign outputs. -dout <= mem_dob; -full <= full_i; -empty <= empty_i; - -end rtl; diff --git a/qick/firmware/ip/axis_sg_mux4_v1/src/fifo/fifo_dc_axi.vhd b/qick/firmware/ip/axis_sg_mux4_v1/src/fifo/fifo_dc_axi.vhd deleted file mode 100644 index eb83d1a..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v1/src/fifo/fifo_dc_axi.vhd +++ /dev/null @@ -1,156 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo_dc_axi is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - wr_rstn : in std_logic; - wr_clk : in std_logic; - - rd_rstn : in std_logic; - rd_clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo_dc_axi; - -architecture rtl of fifo_dc_axi is - --- Dual-clock FIFO. -component fifo_dc is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - wr_rstn : in std_logic; - wr_clk : in std_logic; - - rd_rstn : in std_logic; - rd_clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end component; - --- FIFO read to AXI adapter. -component rd2axi is - Generic - ( - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- FIFO Read I/F. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (B-1 downto 0); - fifo_empty : in std_logic; - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - empty : out std_logic - ); -end component; - -signal rd_en_i : std_logic; -signal dout_i : std_logic_vector (B-1 downto 0); -signal empty_i : std_logic; - -begin - --- Dual-clock FIFO. -fifo_i : fifo_dc - Generic map - ( - -- Data width. - B => B, - - -- Fifo depth. - N => N - ) - Port map - ( - wr_rstn => wr_rstn , - wr_clk => wr_clk , - - rd_rstn => rd_rstn , - rd_clk => rd_clk , - - -- Write I/F. - wr_en => wr_en , - din => din , - - -- Read I/F. - rd_en => rd_en_i , - dout => dout_i , - - -- Flags. - full => full , - empty => empty_i - ); - --- FIFO read to AXI adapter. -rd2axi_i : rd2axi - Generic map - ( - -- Data width. - B => B - ) - Port map - ( - rstn => rd_rstn , - clk => rd_clk , - - -- FIFO Read I/F. - fifo_rd_en => rd_en_i , - fifo_dout => dout_i , - fifo_empty => empty_i , - - -- Read I/F. - rd_en => rd_en , - dout => dout , - empty => empty - ); - -end rtl; - diff --git a/qick/firmware/ip/axis_sg_mux4_v1/src/fifo/gray2bin.vhd b/qick/firmware/ip/axis_sg_mux4_v1/src/fifo/gray2bin.vhd deleted file mode 100644 index e23f8af..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v1/src/fifo/gray2bin.vhd +++ /dev/null @@ -1,37 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity gray2bin is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end gray2bin; - -architecture rtl of gray2bin is - -signal bin : std_logic_vector (B-1 downto 0); - -begin - --- MSB always match. -bin(B-1) <= din(B-1); - -GEN: for I in 0 to B-2 generate -begin - bin(I) <= bin(I+1) xor din(I); -end generate GEN; - --- Assign output. -dout <= bin; - -end rtl; - diff --git a/qick/firmware/ip/axis_sg_mux4_v1/src/fifo/rd2axi.vhd b/qick/firmware/ip/axis_sg_mux4_v1/src/fifo/rd2axi.vhd deleted file mode 100644 index babadc6..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v1/src/fifo/rd2axi.vhd +++ /dev/null @@ -1,138 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity rd2axi is - Generic - ( - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- FIFO Read I/F. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (B-1 downto 0); - fifo_empty : in std_logic; - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - empty : out std_logic - ); -end rd2axi; - -architecture rtl of rd2axi is - -type fsm_state is ( WAIT_EMPTY_ST, - READ_FIRST_ST, - READ_ST, - READ_LAST_ST); -signal current_state, next_state : fsm_state; - -signal wait_empty_state : std_logic; -signal read_first_state : std_logic; -signal read_state : std_logic; - -signal fifo_rd_en_i : std_logic; -signal empty_i : std_logic; - -begin - -process(clk) -begin - if (rising_edge(clk)) then - if (rstn = '0') then - current_state <= WAIT_EMPTY_ST; - else - current_state <= next_state; - end if; - end if; -end process; - --- Next state logic. -process(current_state, fifo_empty, rd_en) -begin - case current_state is - when WAIT_EMPTY_ST => - if (fifo_empty = '1') then - next_state <= WAIT_EMPTY_ST; - else - next_state <= READ_FIRST_ST; - end if; - - when READ_FIRST_ST => - next_state <= READ_ST; - - when READ_ST => - if (fifo_empty = '0') then - next_state <= READ_ST; - else - if (rd_en = '1') then - next_state <= WAIT_EMPTY_ST; - else - next_state <= READ_LAST_ST; - end if; - end if; - - when READ_LAST_ST => - if (rd_en = '0') then - next_state <= READ_LAST_ST; - else - next_state <= WAIT_EMPTY_ST; - end if; - - end case; -end process; - --- Output logic. -process(current_state) -begin -wait_empty_state <= '0'; -read_first_state <= '0'; -read_state <= '0'; -empty_i <= '0'; - case current_state is - when WAIT_EMPTY_ST => - wait_empty_state <= '1'; - read_first_state <= '0'; - read_state <= '0'; - empty_i <= '1'; - - when READ_FIRST_ST => - wait_empty_state <= '0'; - read_first_state <= '1'; - read_state <= '0'; - empty_i <= '1'; - - when READ_ST => - wait_empty_state <= '0'; - read_first_state <= '0'; - read_state <= '1'; - empty_i <= '0'; - - when READ_LAST_ST => - wait_empty_state <= '0'; - read_first_state <= '0'; - read_state <= '0'; - empty_i <= '0'; - - end case; -end process; - --- FIFO Read enable signal. -fifo_rd_en_i <= read_first_state or (read_state and rd_en); - --- Assign outputs. -fifo_rd_en <= fifo_rd_en_i; --- TODO: add register to freeze last value. -dout <= fifo_dout when empty_i = '0' else - (others => '0'); -empty <= empty_i; - -end rtl; - diff --git a/qick/firmware/ip/axis_sg_mux4_v1/src/fifo/synchronizer_vect.vhd b/qick/firmware/ip/axis_sg_mux4_v1/src/fifo/synchronizer_vect.vhd deleted file mode 100644 index 2fbb696..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v1/src/fifo/synchronizer_vect.vhd +++ /dev/null @@ -1,49 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - --- This block is intended to use to sync gray coded vectors. - --- NOTE: Do not use with generic vector data, as it may result --- in corrupted re-sync data. - -entity synchronizer_vect is - generic ( - -- Sync stages. - N : Integer := 2; - - -- Data width. - B : Integer := 8 - ); - port ( - rstn : in std_logic; - clk : in std_logic; - data_in : in std_logic_vector (B-1 downto 0); - data_out : out std_logic_vector (B-1 downto 0) - ); -end synchronizer_vect; - -architecture rtl of synchronizer_vect is - --- Internal register. -type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); -signal data_int_reg : reg_t; - -begin - -process(clk) -begin - if (rising_edge(clk)) then - if (rstn = '0') then - data_int_reg <= (others => (others => '0')); -- 1 FF. - else - data_int_reg <= data_int_reg(N-2 downto 0) & data_in; - end if; - end if; -end process; - --- Assign output. -data_out <= data_int_reg(N-1); - -end rtl; - diff --git a/qick/firmware/ip/axis_sg_mux4_v1/src/latency_reg.v b/qick/firmware/ip/axis_sg_mux4_v1/src/latency_reg.v deleted file mode 100644 index 687a9f3..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v1/src/latency_reg.v +++ /dev/null @@ -1,61 +0,0 @@ -module latency_reg - ( - rstn , - clk , - - din , - dout - ); - -// Parameters. -parameter N = 2; // Latency. -parameter B = 8; // Data width. - -// Ports. -input rstn; -input clk; -input [B-1:0] din; -output [B-1:0] dout; - -// Shift register. -reg [B-1:0] shift_r [0:N-1]; - -generate -genvar i; - for (i=1; i '0'); - else - data_int_reg <= data_int_reg(N-2 downto 0) & data_in; - end if; - end if; -end process; - --- Assign output. -data_out <= data_int_reg(N-1); - -end rtl; - diff --git a/qick/firmware/ip/axis_sg_mux4_v1/src/tb/dout.csv b/qick/firmware/ip/axis_sg_mux4_v1/src/tb/dout.csv deleted file mode 100644 index 1a8273e..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v1/src/tb/dout.csv +++ /dev/null @@ -1,3685 +0,0 @@ -valid, idx, real, imag -0, 0, 0, 0 -0, 1, 0, 0 -0, 0, 0, 0 -0, 1, 0, 0 -0, 0, 0, 0 -0, 1, 0, 0 -0, 0, 0, 0 -0, 1, 0, 0 -0, 0, 0, 0 -0, 1, 0, 0 -0, 0, 0, 0 -0, 1, 0, 0 -0, 0, 0, 0 -0, 1, 0, 0 -0, 0, 0, 0 -0, 1, 0, 0 -0, 0, 0, 0 -0, 1, 0, 0 -1, 0, -805, 14828 -1, 1, 8879, -3717 -1, 0, -675, 3630 -1, 1, 17647, 5713 -1, 0, 870, 4187 -1, 1, 5189, 17839 -1, 0, -4817, -1555 -1, 1, -10640, 5836 -1, 0, 3871, -14318 -1, 1, -2114, -11642 -1, 0, 22534, -7325 -1, 1, 13309, -8091 -1, 0, 20072, 13037 -1, 1, 13562, 688 -1, 0, 2867, 13990 -1, 1, 14420, -86 -1, 0, 2527, 1842 -1, 1, 22542, 8458 -1, 0, 11583, 4990 -1, 1, 13141, 26682 -1, 0, 5539, 13409 -1, 1, -11572, 23188 -1, 0, -2194, 6430 -1, 1, -15861, -817 -1, 0, 5435, 1053 -1, 1, 1556, -9593 -1, 0, 7786, 10722 -1, 1, 9277, -873 -1, 0, -5221, 10978 -1, 1, 7630, 541 -1, 0, -5177, -5707 -1, 1, 15508, 1268 -1, 0, 14280, -7735 -1, 1, 18155, 17115 -1, 0, 20358, 11328 -1, 1, -252, 26055 -1, 0, 6642, 20396 -1, 1, -13263, 10569 -1, 0, -108, 15010 -1, 1, -2156, -1649 -1, 0, -563, 16775 -1, 1, 6273, 7303 -1, 0, -12772, 17081 -1, 1, -2799, 12058 -1, 0, -19490, -1897 -1, 1, -4976, 2374 -1, 0, -60, -16383 -1, 1, 4910, 2346 -1, 0, 19429, -1963 -1, 1, 2788, 12023 -1, 0, 12778, 17028 -1, 1, -6290, 7298 -1, 0, 560, 16758 -1, 1, 2116, -1673 -1, 0, 106, 14985 -1, 1, 13262, 10519 -1, 0, -6614, 20392 -1, 1, 297, 26050 -1, 0, -20349, 11383 -1, 1, -18150, 17175 -1, 0, -14345, -7695 -1, 1, -15565, 1296 -1, 0, 5107, -5729 -1, 1, -7682, 532 -1, 0, 5197, 10942 -1, 1, -9323, -876 -1, 0, -7805, 10718 -1, 1, -1630, -9621 -1, 0, -5484, 1017 -1, 1, 15821, -898 -1, 0, 2184, 6365 -1, 1, 11620, 23108 -1, 0, -5504, 13384 -1, 1, -13083, 26687 -1, 0, -11576, 5001 -1, 1, -22545, 8492 -1, 0, -2547, 1828 -1, 1, -14442, -77 -1, 0, -2857, 13977 -1, 1, -13578, 701 -1, 0, -20072, 13063 -1, 1, -13360, -8083 -1, 0, -22592, -7321 -1, 1, 2043, -11685 -1, 0, -3947, -14368 -1, 1, 10626, 5744 -1, 0, 4804, -1632 -1, 1, -5154, 17791 -1, 0, -859, 4140 -1, 1, -17637, 5695 -1, 0, 680, 3583 -1, 1, -8886, -3752 -1, 0, 841, 14778 -1, 1, -4240, 4304 -1, 0, -18212, 20501 -1, 1, -13987, 5475 -1, 0, -32766, 50 -1, 1, -14038, -5446 -1, 0, -18333, -20484 -1, 1, -4300, -4367 -1, 0, 762, -14879 -1, 1, -8882, 3683 -1, 0, 666, -3678 -1, 1, -17663, -5723 -1, 0, -882, -4236 -1, 1, -5219, -17890 -1, 0, 4828, 1480 -1, 1, 10656, -5922 -1, 0, -3808, 14264 -1, 1, 2181, 11596 -1, 0, -22473, 7343 -1, 1, -13258, 8101 -1, 0, -20074, -13013 -1, 1, -13546, -681 -1, 0, -2875, -14015 -1, 1, -14396, 83 -1, 0, -2509, -1856 -1, 1, -22546, -8425 -1, 0, -11581, -4985 -1, 1, -13190, -26683 -1, 0, -5565, -13440 -1, 1, 11540, -23260 -1, 0, 2200, -6494 -1, 1, 15900, 729 -1, 0, -5389, -1086 -1, 1, -1488, 9562 -1, 0, -7756, -10736 -1, 1, -9233, 863 -1, 0, 5241, -11016 -1, 1, -7580, -549 -1, 0, 5246, 5678 -1, 1, -15452, -1245 -1, 0, -14219, 7768 -1, 1, -18149, -17070 -1, 0, -20363, -11278 -1, 1, 215, -26054 -1, 0, -6663, -20402 -1, 1, 13266, -10614 -1, 0, 109, -15035 -1, 1, 2193, 1625 -1, 0, 564, -16792 -1, 1, -6255, -7303 -1, 0, 12767, -17131 -1, 1, 2817, -12094 -1, 0, 19549, 1822 -1, 1, 5039, -2405 -1, 0, 160, 16382 -1, 1, -4845, -2321 -1, 0, -19371, 2021 -1, 1, -2766, -11990 -1, 0, -12769, -16987 -1, 1, 6309, -7286 -1, 0, -552, -16743 -1, 1, -2073, 1694 -1, 0, -111, -14961 -1, 1, -13267, -10465 -1, 0, 6585, -20389 -1, 1, -335, -26051 -1, 0, 20344, -11439 -1, 1, 18149, -17228 -1, 0, 14408, 7654 -1, 1, 15621, -1326 -1, 0, -5038, 5753 -1, 1, 7732, -523 -1, 0, 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-1, 0, 2488, 1870 -1, 1, 22543, 8394 -1, 0, 11588, 4972 -1, 1, 13253, 26674 -1, 0, 5599, 13464 -1, 1, -11491, 23339 -1, 0, -2211, 6559 -1, 1, -15941, -643 -1, 0, 5341, 1122 -1, 1, 1421, -9533 -1, 0, 7730, 10746 -1, 1, 9187, -857 -1, 0, -5265, 11051 -1, 1, 7529, 557 -1, 0, -5316, -5653 -1, 1, 15395, 1216 -1, 0, 14154, -7809 -1, 1, 18148, 17017 -1, 0, 20366, 11225 -1, 1, -170, 26058 -1, 0, 6699, 20401 -1, 1, -13262, 10668 -1, 0, -110, 15058 -1, 1, -2226, -1602 -1, 0, -560, 16807 -1, 1, 6241, 7310 -1, 0, -12771, 17176 -1, 1, -2836, 12128 -1, 0, -19609, -1756 -1, 1, -5106, 2432 -1, 0, -261, -16383 -1, 1, 4777, 2294 -1, 0, 19310, -2088 -1, 1, 2743, 11952 -1, 0, 12778, 16931 -1, 1, -6325, 7288 -1, 0, 556, 16725 -1, 1, 2039, -1720 -1, 0, 109, 14935 -1, 1, 13266, 10414 -1, 0, -6549, 20388 -1, 1, 386, 26047 -1, 0, -20339, 11488 -1, 1, -18149, 17280 -1, 0, -14472, -7615 -1, 1, -15677, 1354 -1, 0, 4966, -5784 -1, 1, -7783, 513 -1, 0, 5149, 10870 -1, 1, -9413, -885 -1, 0, -7866, 10692 -1, 1, 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[2:0] s_axi_awprot; -wire s_axi_awready; -wire s_axi_awvalid; -wire s_axi_bready; -wire [1:0] s_axi_bresp; -wire s_axi_bvalid; -wire [31:0] s_axi_rdata; -wire s_axi_rready; -wire [1:0] s_axi_rresp; -wire s_axi_rvalid; -wire [31:0] s_axi_wdata; -wire s_axi_wready; -wire [3:0] s_axi_wstrb; -wire s_axi_wvalid; - -reg aresetn; -reg aclk; - -// s_axis interfase. -wire [39:0] s_axis_tdata; -wire s_axis_tready; -reg s_axis_tvalid; - -// m_axis interfase. -wire [N_DDS*32-1:0] m_axis_tdata; -reg m_axis_tready = 1; -wire m_axis_tvalid; - -// Waveform fields. -reg [31:0] nsamp_r; -reg [7:0] mask_r; - -// Assignment of data out for debugging. -wire [31:0] dout_ii [0:N_DDS-1]; - -xil_axi_prot_t prot = 0; -reg[31:0] data_wr = 32'h12345678; -reg[31:0] data; -xil_axi_resp_t resp; - -// TB control. -reg tb_load_wave = 0; -reg tb_load_wave_done = 0; -reg tb_write_out = 0; - -// Debug. -generate -genvar ii; -for (ii = 0; ii < N_DDS; ii = ii + 1) begin : GEN_debug - assign dout_ii[ii] = m_axis_tdata[32*ii +: 32]; -end -endgenerate - -// M_AXI. -axi_mst_0 axi_mst_0_i - ( - .aclk (s_axi_aclk ), - .aresetn (s_axi_aresetn ), - .m_axi_araddr (s_axi_araddr ), - .m_axi_arprot (s_axi_arprot ), - .m_axi_arready (s_axi_arready ), - .m_axi_arvalid (s_axi_arvalid ), - .m_axi_awaddr (s_axi_awaddr ), - .m_axi_awprot (s_axi_awprot ), - .m_axi_awready (s_axi_awready ), - .m_axi_awvalid (s_axi_awvalid ), - .m_axi_bready (s_axi_bready ), - .m_axi_bresp (s_axi_bresp ), - .m_axi_bvalid (s_axi_bvalid ), - .m_axi_rdata (s_axi_rdata ), - .m_axi_rready (s_axi_rready ), - .m_axi_rresp (s_axi_rresp ), - .m_axi_rvalid (s_axi_rvalid ), - .m_axi_wdata (s_axi_wdata ), - .m_axi_wready (s_axi_wready ), - .m_axi_wstrb (s_axi_wstrb ), - .m_axi_wvalid (s_axi_wvalid ) - ); - -axis_sg_mux4_v1 - # - ( - .N_DDS(N_DDS) - ) - DUT - ( - // AXI Slave I/F for configuration. - .s_axi_aclk (s_axi_aclk ), - .s_axi_aresetn (s_axi_aresetn ), - .s_axi_araddr (s_axi_araddr ), - .s_axi_arprot (s_axi_arprot ), - .s_axi_arready (s_axi_arready ), - .s_axi_arvalid (s_axi_arvalid ), - .s_axi_awaddr (s_axi_awaddr ), - .s_axi_awprot (s_axi_awprot ), - .s_axi_awready (s_axi_awready ), - .s_axi_awvalid (s_axi_awvalid ), - .s_axi_bready (s_axi_bready ), - .s_axi_bresp (s_axi_bresp ), - .s_axi_bvalid (s_axi_bvalid ), - .s_axi_rdata (s_axi_rdata ), - .s_axi_rready (s_axi_rready ), - .s_axi_rresp (s_axi_rresp ), - .s_axi_rvalid (s_axi_rvalid ), - .s_axi_wdata (s_axi_wdata ), - .s_axi_wready (s_axi_wready ), - .s_axi_wstrb (s_axi_wstrb ), - .s_axi_wvalid (s_axi_wvalid ), - - // s_* and m_* reset/clock. - .aresetn (aresetn ), - .aclk (aclk ), - - // S_AXIS to queue waveforms. - .s_axis_tready (s_axis_tready ), - .s_axis_tvalid (s_axis_tvalid ), - .s_axis_tdata (s_axis_tdata ), - - // AXIS Master for output data. - .m_axis_tready (m_axis_tready ), - .m_axis_tvalid (m_axis_tvalid ), - .m_axis_tdata (m_axis_tdata ) - ); - -// VIP Agents -axi_mst_0_mst_t axi_mst_0_agent; - -// Waveform fields. -assign s_axis_tdata = {mask_r,nsamp_r}; - - -initial begin - // Create agents. - axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); - - // Set tag for agents. - axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); - - // Start agents. - axi_mst_0_agent.start_master(); - - // Reset sequence. - s_axi_aresetn <= 0; - aresetn <= 0; - #500; - s_axi_aresetn <= 1; - aresetn <= 1; - - #1000; - - $display("###########################"); - $display("### Program Frequencies ###"); - $display("###########################"); - $display("t = %0t", $time); - - // PINC0_REG - data_wr = freq_calc(100, N_DDS, 1); - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*0, prot, data_wr, resp); - #10; - - // PINC1_REG - data_wr = freq_calc(100, N_DDS, 11); - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*1, prot, data_wr, resp); - #10; - - // PINC2_REG - data_wr = freq_calc(100, N_DDS, 27); - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*2, prot, data_wr, resp); - #10; - - // PINC3_REG - data_wr = freq_calc(100, N_DDS, 115); - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*3, prot, data_wr, resp); - #10; - - // we. - data_wr = 1; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*4, prot, data_wr, resp); - #10; - - // we. - data_wr = 0; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*4, prot, data_wr, resp); - #10; - - $display("#######################"); - $display("### Queue Waveforms ###"); - $display("#######################"); - $display("t = %0t", $time); - - // Queue waveforms and write output while queuing. - tb_load_wave <= 1; - tb_write_out <= 1; - wait (tb_load_wave_done); - - #30000; - - // Stop writing output data. - tb_write_out <= 0; - - #20000; - -end - -// Load waveforms. -initial begin - s_axis_tvalid <= 0; - nsamp_r <= 0; - mask_r <= 0; - - wait (tb_load_wave); - wait (s_axis_tready); - - @(posedge aclk); - $display("t = %0t", $time); - s_axis_tvalid <= 1; - nsamp_r <= 550; - mask_r <= 8'b0000_1111; - - @(posedge aclk); - $display("t = %0t", $time); - s_axis_tvalid <= 1; - nsamp_r <= 350; - mask_r <= 8'b0000_1111; - - //@(posedge aclk); - //$display("t = %0t", $time); - //s_axis_tvalid_i <= 1; - //nsamp_r <= 25; - //mask_r <= 8'b0000_0010; - - //@(posedge aclk); - //$display("t = %0t", $time); - //s_axis_tvalid_i <= 1; - //nsamp_r <= 35; - //mask_r <= 8'b0000_0100; - - //@(posedge aclk); - //$display("t = %0t", $time); - //s_axis_tvalid_i <= 1; - //nsamp_r <= 63; - //mask_r <= 8'b0000_1000; - - @(posedge aclk); - s_axis_tvalid <= 0; - tb_load_wave_done <= 1; -end - -// Write output into file. -initial begin - int fd; - int i; - shortint real_d, imag_d; - - // Output file. - fd = $fopen("../../../../../tb/dout.csv","w"); - - // Data format. - $fdisplay(fd, "valid, idx, real, imag"); - - wait (tb_write_out); - - while (tb_write_out) begin - @(posedge aclk); - for (i=0; i - - user.org - user - axis_sg_mux4_v2 - 1.0 - - - m_axis - - - - - - - TDATA - - - m_axis_tdata - - - - - TVALID - - - m_axis_tvalid - - - - - TREADY - - - m_axis_tready - - - - - - s_axis - - - - - - - TDATA - - - s_axis_tdata - - - - - TVALID - - - s_axis_tvalid - - - - - TREADY - - - s_axis_tready - - - - - - s_axi - - - - - - - - - AWADDR - - - s_axi_awaddr - - - - - AWPROT - - - s_axi_awprot - - - - - AWVALID - - - s_axi_awvalid - - - - - AWREADY - - - s_axi_awready - - - - - WDATA - - - s_axi_wdata - - - - - WSTRB - - - s_axi_wstrb - - - - - WVALID - - - s_axi_wvalid - - - - - WREADY - - - s_axi_wready - - - - - BRESP - - - s_axi_bresp - - - - - BVALID - - - s_axi_bvalid - - - - - BREADY - - - s_axi_bready - - - - - ARADDR - - - s_axi_araddr - - - - - ARPROT - - - s_axi_arprot - - - - - ARVALID - - - s_axi_arvalid - - - - - ARREADY - - - s_axi_arready - - - - - RDATA - - - s_axi_rdata - - - - - RRESP - - - s_axi_rresp - - - - - RVALID - - - s_axi_rvalid - - - - - RREADY - - - s_axi_rready - - - - - - s_axi_aclk - - - - - - - CLK - - - s_axi_aclk - - - - - - ASSOCIATED_BUSIF - s_axi - - - ASSOCIATED_RESET - s_axi_aresetn - - - - - s_axi_aresetn - - - - - - - RST - - - s_axi_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - aclk - - - - - - - CLK - - - aclk - - - - - - ASSOCIATED_BUSIF - m_axis:s_axis - - - ASSOCIATED_RESET - aresetn - - - - - aresetn - - - - - - - RST - - - aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - - - s_axi - - reg0 - 0 - 64 - 32 - register - - - - - - - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis - Verilog - axis_sg_mux4_v2 - - xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset - - - xilinx_anylanguagesynthesis_view_fileset - - - - viewChecksum - 5ea64aa6 - - - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - Verilog - axis_sg_mux4_v2 - - xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - - - viewChecksum - 5ea64aa6 - - - - - xilinx_xpgui - UI Layout - :vivado.xilinx.com:xgui.ui - - xilinx_xpgui_view_fileset - - - - viewChecksum - 429ef1d0 - - - - - - - s_axi_aclk - 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out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axis_tvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axis_tdata - - in - - 39 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - m_axis_tready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 1 - - - - - m_axis_tvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m_axis_tdata - - out - - 63 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - - N_DDS - N Dds - 2 - - - - - - choice_list_74b5137e - ACTIVE_HIGH - ACTIVE_LOW - - - - - xilinx_anylanguagesynthesis_view_fileset - - src/dds_compiler_0/dds_compiler_0.xci - xci - CELL_NAME_sg_mux4_i/GEN_out[0].dds_top_i/GEN_dds[0].dds_i/dds_compiler_0 - - - src/dds_top.v - verilogSource - - - src/latency_reg.v - verilogSource - - - src/sg_mux4.v - verilogSource - - - src/ctrl.sv - systemVerilogSource - - - src/phase_ctrl.sv - systemVerilogSource - - - src/axi_slv.vhd - vhdlSource - - - src/fifo/bram_simple_dp.vhd - vhdlSource - - - src/fifo/fifo.vhd - vhdlSource - - - src/synchronizer_n.vhd - vhdlSource - - - src/axis_sg_mux4.v - verilogSource - CHECKSUM_0b7ef357 - - - - xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset - - - - - - - - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - src/dds_compiler_0/dds_compiler_0.xci - xci - CELL_NAME_sg_mux4_i/GEN_out[0].dds_top_i/GEN_dds[0].dds_i/dds_compiler_0 - - - src/dds_top.v - verilogSource - - - src/latency_reg.v - verilogSource - - - src/sg_mux4.v - verilogSource - - - src/ctrl.sv - systemVerilogSource - - - src/phase_ctrl.sv - systemVerilogSource - - - src/axi_slv.vhd - vhdlSource - - - src/fifo/bram_simple_dp.vhd - vhdlSource - - - src/fifo/fifo.vhd - vhdlSource - - - src/synchronizer_n.vhd - vhdlSource - - - src/axis_sg_mux4.v - verilogSource - - - - xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset - - - - - - - - - - xilinx_xpgui_view_fileset - - xgui/axis_sg_mux4_v2_v1_0.tcl - tclSource - CHECKSUM_429ef1d0 - XGUI_VERSION_2 - - - - AXIS Signal Generator with 4 muxed outputs, 32-bit DDS and individual Gain. - - - N_DDS - N Dds - 2 - - - Component_Name - axis_sg_mux4_v1_v1_0 - - - - - - zynquplus - - - /UserIP - - AXIS SG mux 4 V2 - package_project - 2 - 2022-05-12T19:42:38Z - - /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 - /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 - /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 - /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 - /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 - /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 - /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 - /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 - /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 - /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 - /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 - /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 - /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 - /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 - /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 - /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 - /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 - /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 - /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 - /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 - /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 - /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 - /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 - /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 - /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 - /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 - /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 - /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 - - - - 2020.2 - - - - - - - - - diff --git a/qick/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.veo b/qick/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.veo deleted file mode 100644 index 7cfbd51..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.veo +++ /dev/null @@ -1,85 +0,0 @@ -// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -// IP VLNV: xilinx.com:ip:axi_vip:1.1 -// IP Revision: 8 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -axi_mst_0 your_instance_name ( - .aclk(aclk), // input wire aclk - .aresetn(aresetn), // input wire aresetn - .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr - .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot - .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid - .m_axi_awready(m_axi_awready), // input wire m_axi_awready - .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata - .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb - .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid - .m_axi_wready(m_axi_wready), // input wire m_axi_wready - .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp - .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid - .m_axi_bready(m_axi_bready), // output wire m_axi_bready - .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr - .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot - .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid - .m_axi_arready(m_axi_arready), // input wire m_axi_arready - .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata - .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp - .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid - .m_axi_rready(m_axi_rready) // output wire m_axi_rready -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file axi_mst_0.v when simulating -// the core, axi_mst_0. When compiling the wrapper file, be sure to -// reference the Verilog simulation library. - diff --git a/qick/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.vho b/qick/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.vho deleted file mode 100644 index a53be60..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.vho +++ /dev/null @@ -1,115 +0,0 @@ --- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:axi_vip:1.1 --- IP Revision: 8 - --- The following code must appear in the VHDL architecture header. - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT axi_mst_0 - PORT ( - aclk : IN STD_LOGIC; - aresetn : IN STD_LOGIC; - m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - m_axi_awvalid : OUT STD_LOGIC; - m_axi_awready : IN STD_LOGIC; - m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - m_axi_wvalid : OUT STD_LOGIC; - m_axi_wready : IN STD_LOGIC; - m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - m_axi_bvalid : IN STD_LOGIC; - m_axi_bready : OUT STD_LOGIC; - m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - m_axi_arvalid : OUT STD_LOGIC; - m_axi_arready : IN STD_LOGIC; - m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - m_axi_rvalid : IN STD_LOGIC; - m_axi_rready : OUT STD_LOGIC - ); -END COMPONENT; --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : axi_mst_0 - PORT MAP ( - aclk => aclk, - aresetn => aresetn, - m_axi_awaddr => m_axi_awaddr, - m_axi_awprot => m_axi_awprot, - m_axi_awvalid => m_axi_awvalid, - m_axi_awready => m_axi_awready, - m_axi_wdata => m_axi_wdata, - m_axi_wstrb => m_axi_wstrb, - m_axi_wvalid => m_axi_wvalid, - m_axi_wready => m_axi_wready, - m_axi_bresp => m_axi_bresp, - m_axi_bvalid => m_axi_bvalid, - m_axi_bready => m_axi_bready, - m_axi_araddr => m_axi_araddr, - m_axi_arprot => m_axi_arprot, - m_axi_arvalid => m_axi_arvalid, - m_axi_arready => m_axi_arready, - m_axi_rdata => m_axi_rdata, - m_axi_rresp => m_axi_rresp, - m_axi_rvalid => m_axi_rvalid, - m_axi_rready => m_axi_rready - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file axi_mst_0.vhd when simulating --- the core, axi_mst_0. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/qick/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.xci b/qick/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.xci deleted file mode 100644 index ac9cf04..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.xci +++ /dev/null @@ -1,200 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - axi_mst_0 - - - ACTIVE_LOW - - 100000000 - 0 - 0 - 0.000 - 32 - 0 - 0 - 0 - - 32 - 100000000 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 32 - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 0 - 2 - 32 - 0 - 0 - 0 - 32 - 0 - 0 - 32 - 0 - 0 - 0 - axi_mst_0 - 32 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 0 - 0 - 1 - 0 - MASTER - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - zynquplusRFSOC - xilinx.com:zcu216:part0:2.0 - - xczu49dr - ffvf1760 - VERILOG - - MIXED - -2 - - E - TRUE - TRUE - IP_Flow - 8 - TRUE - . - - . - 2020.2 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/qick/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.xml b/qick/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.xml deleted file mode 100644 index c2c5156..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.xml +++ /dev/null @@ -1,4760 +0,0 @@ - - - xilinx.com - customized_ip - axi_mst_0 - 1.0 - - - M_AXI - - - - - - - - - ARADDR - - - m_axi_araddr - - - - - ARBURST - - - m_axi_arburst - - - - - ARCACHE - - - m_axi_arcache - - - - - ARID - - - m_axi_arid - - - - - ARLEN - - - m_axi_arlen - - - - - ARLOCK - - - m_axi_arlock - - - - - ARPROT - - - m_axi_arprot - - - - - ARQOS - - - m_axi_arqos - - - - - ARREADY - - - m_axi_arready - - - - - ARREGION - - - m_axi_arregion - - - - - ARSIZE - - - m_axi_arsize - - - - - ARUSER - - - m_axi_aruser - - - - - ARVALID - - - m_axi_arvalid - - - - - AWADDR - - - m_axi_awaddr - - - - - AWBURST - - - m_axi_awburst - - - - - AWCACHE - - - m_axi_awcache - - - - - AWID - - - m_axi_awid - - - - - AWLEN - - - m_axi_awlen - - - - - AWLOCK - - - m_axi_awlock - - - - - AWPROT - - - m_axi_awprot - - - - - AWQOS - - - m_axi_awqos - - - - - AWREADY - - - m_axi_awready - - - - - AWREGION - - - m_axi_awregion - - - - - AWSIZE - - - m_axi_awsize - - - - - AWUSER - - - m_axi_awuser - - - - - AWVALID - - - m_axi_awvalid - - - - - BID - - - m_axi_bid - - - - - BREADY - - - m_axi_bready - - - - - BRESP - - - m_axi_bresp - - - - - BUSER - - - m_axi_buser - - - - - BVALID - - - m_axi_bvalid - - - - - RDATA - - - m_axi_rdata - - - - - RID - - - m_axi_rid - - - - - RLAST - - - m_axi_rlast - - - - - RREADY - - - m_axi_rready - - - - - RRESP - - - m_axi_rresp - - - - - RUSER - - - m_axi_ruser - - - - - RVALID - - - m_axi_rvalid - - - - - WDATA - - - m_axi_wdata - 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AXIMM Socket for Write - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - rd_socket - - - - - - - 1 - - - - - - - C_AXI_PROTOCOL - 2 - - - C_AXI_INTERFACE_MODE - 0 - - - C_AXI_ADDR_WIDTH - 32 - - - C_AXI_WDATA_WIDTH - 32 - - - C_AXI_RDATA_WIDTH - 32 - - - C_AXI_WID_WIDTH - 0 - - - C_AXI_RID_WIDTH - 0 - - - C_AXI_AWUSER_WIDTH - 0 - - - C_AXI_ARUSER_WIDTH - 0 - - - C_AXI_WUSER_WIDTH - 0 - - - C_AXI_RUSER_WIDTH - 0 - - - C_AXI_BUSER_WIDTH - 0 - - - C_AXI_SUPPORTS_NARROW - 0 - - - C_AXI_HAS_BURST - 0 - - - C_AXI_HAS_LOCK - 0 - - - C_AXI_HAS_CACHE - 0 - - - C_AXI_HAS_REGION - 0 - - - C_AXI_HAS_PROT - 1 - - - C_AXI_HAS_QOS - 0 - - - C_AXI_HAS_WSTRB - 1 - - - C_AXI_HAS_BRESP - 1 - - - C_AXI_HAS_RRESP - 1 - - - C_AXI_HAS_ARESETN - 1 - - - - - - choice_list_04fafd91 - AXI3 - AXI4 - AXI4LITE - - - choice_list_6240decd - READ_ONLY - READ_WRITE - WRITE_ONLY - - - choice_list_642e7122 - MASTER - PASS_THROUGH - SLAVE - - - choice_list_99ba8646 - 32 - 64 - - - choice_list_9d8b0d81 - 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true - axi_infrastructure_v1_1_0 - - - hdl/axi_infrastructure_v1_1_vl_rfs.v - verilogSource - USED_IN_ipstatic - axi_infrastructure_v1_1_0 - - - - - - - - - - - xilinx_verilogbehavioralsimulation_view_fileset - - sim/axi_mst_0_pkg.sv - systemVerilogSource - - - hdl/axi_vip_v1_1_vl_rfs.sv - systemVerilogSource - USED_IN_ipstatic - axi_vip_v1_1_8 - - - - xilinx_systemcsimulation_view_fileset - - sysc/axi_vip.cpp - systemCSource - axi_vip_v1_1_8 - - - sysc/axi_vip.h - systemCSource - true - axi_vip_v1_1_8 - - - - xilinx_verilogsimulationwrapper_view_fileset - - sim/axi_mst_0.sv - systemVerilogSource - xil_defaultlib - - - - xilinx_systemcsimulationwrapper_view_fileset - - sim/axi_mst_0_sc.h - systemCSource - true - - - sim/axi_mst_0_sc.cpp - systemCSource - - - sim/axi_mst_0.h - systemCSource - true - - - sim/axi_mst_0.cpp - systemCSource - - - sim/axi_mst_0_stub.sv - systemVerilogSource - - - - xilinx_versioninformation_view_fileset - - doc/axi_vip_v1_1_changelog.txt - text - axi_vip_v1_1_8 - - - - xilinx_externalfiles_view_fileset - - axi_mst_0.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - axi_mst_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - axi_mst_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - axi_mst_0_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - axi_mst_0_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - - The AXI Verification IP. - - - Component_Name - Component Name - axi_mst_0 - - - PROTOCOL - PROTOCOL - AXI4LITE - - - READ_WRITE_MODE - READ_WRITE MODE - READ_WRITE - - - INTERFACE_MODE - INTERFACE MODE - MASTER - - - ADDR_WIDTH - ADDRESS WIDTH - 32 - - - DATA_WIDTH - DATA WIDTH - 32 - - - ID_WIDTH - ID WIDTH - 0 - - - - false - - - - - - AWUSER_WIDTH - AWUSER WIDTH - 0 - - - - false - - - - - - ARUSER_WIDTH - ARUSER WIDTH - 0 - - - - false - - - - - - RUSER_WIDTH - RUSER WIDTH - 0 - - - - false - - - - - - WUSER_WIDTH - WUSER WIDTH - 0 - - - - false - - - - - - BUSER_WIDTH - BUSER WIDTH - 0 - - - - false - - - - - - WUSER_BITS_PER_BYTE - WUSER BITS PER BYTE - 0 - - - - false - - - - - - RUSER_BITS_PER_BYTE - RUSER BITS PER BYTE - 0 - - - - false - - - - - - HAS_USER_BITS_PER_BYTE - HAS USER_BITS_PER_BYTE - 0 - - - - false - - - - - - SUPPORTS_NARROW - SUPPORTS NARROW - 0 - - - - false - - - - - - HAS_SIZE - HAS SIZE - 0 - - - - false - - - - - - HAS_BURST - HAS BURST - 0 - - - - false - - - - - - HAS_LOCK - HAS LOCK - 0 - - - - false - - - - - - HAS_CACHE - HAS CACHE - 0 - - - - false - - - - - - HAS_REGION - HAS REGION - 0 - - - - false - - - - - - HAS_QOS - HAS QOS - 0 - - - - false - - - - - - HAS_PROT - HAS PROT - 1 - - - HAS_WSTRB - HAS WSTRB - 1 - - - HAS_BRESP - HAS BRESP - 1 - - - HAS_RRESP - HAS RRESP - 1 - - - HAS_ACLKEN - HAS ACLKEN - 0 - - - HAS_ARESETN - HAS ARESETN - 1 - - - - - AXI Verification IP - - xtlm - - 8 - true - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2020.2 - - - - - - - - - - diff --git a/qick/firmware/ip/axis_sg_mux4_v2/src/axi_slv.vhd b/qick/firmware/ip/axis_sg_mux4_v2/src/axi_slv.vhd deleted file mode 100644 index c92dcb1..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v2/src/axi_slv.vhd +++ /dev/null @@ -1,537 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity axi_slv is - Generic - ( - DATA_WIDTH : integer := 32; - ADDR_WIDTH : integer := 6 - ); - Port - ( - aclk : in std_logic; - aresetn : in std_logic; - - -- Write Address Channel. - awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); - awprot : in std_logic_vector(2 downto 0); - awvalid : in std_logic; - awready : out std_logic; - - -- Write Data Channel. - wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); - wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); - wvalid : in std_logic; - wready : out std_logic; - - -- Write Response Channel. - bresp : out std_logic_vector(1 downto 0); - bvalid : out std_logic; - bready : in std_logic; - - -- Read Address Channel. - araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); - arprot : in std_logic_vector(2 downto 0); - arvalid : in std_logic; - arready : out std_logic; - - -- Read Data Channel. - rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); - rresp : out std_logic_vector(1 downto 0); - rvalid : out std_logic; - rready : in std_logic; - - -- Registers. - PINC0_REG : out std_logic_vector (31 downto 0); - PINC1_REG : out std_logic_vector (31 downto 0); - PINC2_REG : out std_logic_vector (31 downto 0); - PINC3_REG : out std_logic_vector (31 downto 0); - GAIN0_REG : out std_logic_vector (15 downto 0); - GAIN1_REG : out std_logic_vector (15 downto 0); - GAIN2_REG : out std_logic_vector (15 downto 0); - GAIN3_REG : out std_logic_vector (15 downto 0); - WE_REG : out std_logic - ); -end axi_slv; - -architecture rtl of axi_slv is - - -- AXI4LITE signals - signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); - signal axi_awready : std_logic; - signal axi_wready : std_logic; - signal axi_bresp : std_logic_vector(1 downto 0); - signal axi_bvalid : std_logic; - signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); - signal axi_arready : std_logic; - signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); - signal axi_rresp : std_logic_vector(1 downto 0); - signal axi_rvalid : std_logic; - - -- Example-specific design signals - -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH - -- ADDR_LSB is used for addressing 32/64 bit registers/memories - -- ADDR_LSB = 2 for 32 bits (n downto 2) - -- ADDR_LSB = 3 for 64 bits (n downto 3) - constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; - constant OPT_MEM_ADDR_BITS : integer := 3; - ------------------------------------------------ - ---- Signals for user logic register space example - -------------------------------------------------- - ---- Number of Slave Registers 16 - signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg_rden : std_logic; - signal slv_reg_wren : std_logic; - signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); - signal byte_index : integer; - signal aw_en : std_logic; - -begin - -- I/O Connections assignments - - awreadY <= axi_awready; - wready <= axi_wready; - bresp <= axi_bresp; - bvalid <= axi_bvalid; - arreadY <= axi_arready; - rdata <= axi_rdata; - rresp <= axi_rresp; - rvalid <= axi_rvalid; - -- Implement axi_awready generation - -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is - -- de-asserted when reset is low. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_awready <= '0'; - aw_en <= '1'; - else - if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then - -- slave is ready to accept write address when - -- there is a valid write address and write data - -- on the write address and data bus. This design - -- expects no outstanding transactions. - axi_awready <= '1'; - aw_en <= '0'; - elsif (bready = '1' and axi_bvalid = '1') then - aw_en <= '1'; - axi_awready <= '0'; - else - axi_awready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement axi_awaddr latching - -- This process is used to latch the address when both - -- S_AXI_AWVALID and S_AXI_WVALID are valid. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_awaddr <= (others => '0'); - else - if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then - -- Write Address latching - axi_awaddr <= awaddr; - end if; - end if; - end if; - end process; - - -- Implement axi_wready generation - -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is - -- de-asserted when reset is low. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_wready <= '0'; - else - if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then - -- slave is ready to accept write data when - -- there is a valid write address and write data - -- on the write address and data bus. This design - -- expects no outstanding transactions. - axi_wready <= '1'; - else - axi_wready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement memory mapped register select and write logic generation - -- The write data is accepted and written to memory mapped registers when - -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to - -- select byte enables of slave registers while writing. - -- These registers are cleared when reset (active low) is applied. - -- Slave register write enable is asserted when valid address and data are available - -- and the slave is ready to accept the write address and write data. - slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; - - process (aclk) - variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); - begin - if rising_edge(aclk) then - if aresetn = '0' then - slv_reg0 <= (others => '0'); - slv_reg1 <= (others => '0'); - slv_reg2 <= (others => '0'); - slv_reg3 <= (others => '0'); - slv_reg4 <= (others => '0'); - slv_reg5 <= (others => '0'); - slv_reg6 <= (others => '0'); - slv_reg7 <= (others => '0'); - slv_reg8 <= (others => '0'); - slv_reg9 <= (others => '0'); - slv_reg10 <= (others => '0'); - slv_reg11 <= (others => '0'); - slv_reg12 <= (others => '0'); - slv_reg13 <= (others => '0'); - slv_reg14 <= (others => '0'); - slv_reg15 <= (others => '0'); - else - loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); - if (slv_reg_wren = '1') then - case loc_addr is - when b"0000" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 0 - slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0001" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 1 - slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0010" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 2 - slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0011" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 3 - slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0100" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 4 - slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0101" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 5 - slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0110" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 6 - slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0111" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 7 - slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1000" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 8 - slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1001" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 9 - slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1010" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 10 - slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1011" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 11 - slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1100" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 12 - slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1101" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 13 - slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1110" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 14 - slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1111" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 15 - slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when others => - slv_reg0 <= slv_reg0; - slv_reg1 <= slv_reg1; - slv_reg2 <= slv_reg2; - slv_reg3 <= slv_reg3; - slv_reg4 <= slv_reg4; - slv_reg5 <= slv_reg5; - slv_reg6 <= slv_reg6; - slv_reg7 <= slv_reg7; - slv_reg8 <= slv_reg8; - slv_reg9 <= slv_reg9; - slv_reg10 <= slv_reg10; - slv_reg11 <= slv_reg11; - slv_reg12 <= slv_reg12; - slv_reg13 <= slv_reg13; - slv_reg14 <= slv_reg14; - slv_reg15 <= slv_reg15; - end case; - end if; - end if; - end if; - end process; - - -- Implement write response logic generation - -- The write response and response valid signals are asserted by the slave - -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. - -- This marks the acceptance of address and indicates the status of - -- write transaction. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_bvalid <= '0'; - axi_bresp <= "00"; --need to work more on the responses - else - if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then - axi_bvalid <= '1'; - axi_bresp <= "00"; - elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) - axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) - end if; - end if; - end if; - end process; - - -- Implement axi_arready generation - -- axi_arready is asserted for one S_AXI_ACLK clock cycle when - -- S_AXI_ARVALID is asserted. axi_awready is - -- de-asserted when reset (active low) is asserted. - -- The read address is also latched when S_AXI_ARVALID is - -- asserted. axi_araddr is reset to zero on reset assertion. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_arready <= '0'; - axi_araddr <= (others => '1'); - else - if (axi_arready = '0' and arvalid = '1') then - -- indicates that the slave has acceped the valid read address - axi_arready <= '1'; - -- Read Address latching - axi_araddr <= araddr; - else - axi_arready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement axi_arvalid generation - -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_ARVALID and axi_arready are asserted. The slave registers - -- data are available on the axi_rdata bus at this instance. The - -- assertion of axi_rvalid marks the validity of read data on the - -- bus and axi_rresp indicates the status of read transaction.axi_rvalid - -- is deasserted on reset (active low). axi_rresp and axi_rdata are - -- cleared to zero on reset (active low). - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_rvalid <= '0'; - axi_rresp <= "00"; - else - if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then - -- Valid read data is available at the read data bus - axi_rvalid <= '1'; - axi_rresp <= "00"; -- 'OKAY' response - elsif (axi_rvalid = '1' and rready = '1') then - -- Read data is accepted by the master - axi_rvalid <= '0'; - end if; - end if; - end if; - end process; - - -- Implement memory mapped register select and read logic generation - -- Slave register read enable is asserted when valid address is available - -- and the slave is ready to accept the read address. - slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; - - process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) - variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); - begin - -- Address decoding for reading registers - loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); - case loc_addr is - when b"0000" => - reg_data_out <= slv_reg0; - when b"0001" => - reg_data_out <= slv_reg1; - when b"0010" => - reg_data_out <= slv_reg2; - when b"0011" => - reg_data_out <= slv_reg3; - when b"0100" => - reg_data_out <= slv_reg4; - when b"0101" => - reg_data_out <= slv_reg5; - when b"0110" => - reg_data_out <= slv_reg6; - when b"0111" => - reg_data_out <= slv_reg7; - when b"1000" => - reg_data_out <= slv_reg8; - when b"1001" => - reg_data_out <= slv_reg9; - when b"1010" => - reg_data_out <= slv_reg10; - when b"1011" => - reg_data_out <= slv_reg11; - when b"1100" => - reg_data_out <= slv_reg12; - when b"1101" => - reg_data_out <= slv_reg13; - when b"1110" => - reg_data_out <= slv_reg14; - when b"1111" => - reg_data_out <= slv_reg15; - when others => - reg_data_out <= (others => '0'); - end case; - end process; - - -- Output register or memory read data - process( aclk ) is - begin - if (rising_edge (aclk)) then - if ( aresetn = '0' ) then - axi_rdata <= (others => '0'); - else - if (slv_reg_rden = '1') then - -- When there is a valid read address (S_AXI_ARVALID) with - -- acceptance of read address by the slave (axi_arready), - -- output the read dada - -- Read address mux - axi_rdata <= reg_data_out; -- register read data - end if; - end if; - end if; - end process; - - -- Register Map. - -- 0 : PINC0_REG : 32-bit. Frequency of output 0. - -- 1 : PINC1_REG : 32-bit. Frequency of output 1. - -- 2 : PINC2_REG : 32-bit. Frequency of output 2. - -- 3 : PINC3_REG : 32-bit. Frequency of output 3. - -- 4 : GAIN0_REG : 16-bit. Frequency of output 0. - -- 5 : GAIN1_REG : 16-bit. Frequency of output 1. - -- 6 : GAIN2_REG : 16-bit. Frequency of output 2. - -- 7 : GAIN3_REG : 16-bit. Frequency of output 3. - -- 8 : WE_REG : 1-bit. Register write. - - -- Output Registers. - PINC0_REG <= slv_reg0(31 downto 0); - PINC1_REG <= slv_reg1(31 downto 0); - PINC2_REG <= slv_reg2(31 downto 0); - PINC3_REG <= slv_reg3(31 downto 0); - GAIN0_REG <= slv_reg4(15 downto 0); - GAIN1_REG <= slv_reg5(15 downto 0); - GAIN2_REG <= slv_reg6(15 downto 0); - GAIN3_REG <= slv_reg7(15 downto 0); - WE_REG <= slv_reg8(0); - -end rtl; - diff --git a/qick/firmware/ip/axis_sg_mux4_v2/src/axis_sg_mux4.v b/qick/firmware/ip/axis_sg_mux4_v2/src/axis_sg_mux4.v deleted file mode 100644 index b28a748..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v2/src/axis_sg_mux4.v +++ /dev/null @@ -1,194 +0,0 @@ -// Signal Generator V4. -// s_axi_aclk : clock for s_axi_* -// aclk : clock for s_axis_* and m_axis_* -// -module axis_sg_mux4_v2 - ( - // AXI Slave I/F for configuration. - s_axi_aclk , - s_axi_aresetn , - - s_axi_awaddr , - s_axi_awprot , - s_axi_awvalid , - s_axi_awready , - - s_axi_wdata , - s_axi_wstrb , - s_axi_wvalid , - s_axi_wready , - - s_axi_bresp , - s_axi_bvalid , - s_axi_bready , - - s_axi_araddr , - s_axi_arprot , - s_axi_arvalid , - s_axi_arready , - - s_axi_rdata , - s_axi_rresp , - s_axi_rvalid , - s_axi_rready , - - // s_* and m_* reset/clock. - aclk , - aresetn , - - // S_AXIS to queue waveforms. - s_axis_tready , - s_axis_tvalid , - s_axis_tdata , - - // AXIS Master for output. - m_axis_tready , - m_axis_tvalid , - m_axis_tdata - ); - -/**************/ -/* Parameters */ -/**************/ -// Number of parallel dds blocks. -parameter [31:0] N_DDS = 2; - -/*********/ -/* Ports */ -/*********/ -input s_axi_aclk; -input s_axi_aresetn; - -input [5:0] s_axi_awaddr; -input [2:0] s_axi_awprot; -input s_axi_awvalid; -output s_axi_awready; - -input [31:0] s_axi_wdata; -input [3:0] s_axi_wstrb; -input s_axi_wvalid; -output s_axi_wready; - -output [1:0] s_axi_bresp; -output s_axi_bvalid; -input s_axi_bready; - -input [5:0] s_axi_araddr; -input [2:0] s_axi_arprot; -input s_axi_arvalid; -output s_axi_arready; - -output [31:0] s_axi_rdata; -output [1:0] s_axi_rresp; -output s_axi_rvalid; -input s_axi_rready; - -input aresetn; -input aclk; - -output s_axis_tready; -input s_axis_tvalid; -input [39:0] s_axis_tdata; - -input m_axis_tready; -output m_axis_tvalid; -output [N_DDS*32-1:0] m_axis_tdata; - -/********************/ -/* Internal signals */ -/********************/ -// Registers. -wire [31:0] PINC0_REG; -wire [31:0] PINC1_REG; -wire [31:0] PINC2_REG; -wire [31:0] PINC3_REG; -wire [15:0] GAIN0_REG; -wire [15:0] GAIN1_REG; -wire [15:0] GAIN2_REG; -wire [15:0] GAIN3_REG; -wire WE_REG; - -/**********************/ -/* Begin Architecture */ -/**********************/ -// AXI Slave. -axi_slv axi_slv_i - ( - .aclk (s_axi_aclk ), - .aresetn (s_axi_aresetn ), - - // Write Address Channel. - .awaddr (s_axi_awaddr ), - .awprot (s_axi_awprot ), - .awvalid (s_axi_awvalid ), - .awready (s_axi_awready ), - - // Write Data Channel. - .wdata (s_axi_wdata ), - .wstrb (s_axi_wstrb ), - .wvalid (s_axi_wvalid ), - .wready (s_axi_wready ), - - // Write Response Channel. - .bresp (s_axi_bresp ), - .bvalid (s_axi_bvalid ), - .bready (s_axi_bready ), - - // Read Address Channel. - .araddr (s_axi_araddr ), - .arprot (s_axi_arprot ), - .arvalid (s_axi_arvalid ), - .arready (s_axi_arready ), - - // Read Data Channel. - .rdata (s_axi_rdata ), - .rresp (s_axi_rresp ), - .rvalid (s_axi_rvalid ), - .rready (s_axi_rready ), - - // Registers. - .PINC0_REG (PINC0_REG ), - .PINC1_REG (PINC1_REG ), - .PINC2_REG (PINC2_REG ), - .PINC3_REG (PINC3_REG ), - .GAIN0_REG (GAIN0_REG ), - .GAIN1_REG (GAIN1_REG ), - .GAIN2_REG (GAIN2_REG ), - .GAIN3_REG (GAIN3_REG ), - .WE_REG (WE_REG ) - ); - -sg_mux4 - #( - .N_DDS (N_DDS ) - ) - sg_mux4_i - ( - // Reset and clock. - .aresetn (aresetn ), - .aclk (aclk ), - - // S_AXIS to queue waveforms. - .s_axis_tready_o (s_axis_tready ), - .s_axis_tvalid_i (s_axis_tvalid ), - .s_axis_tdata_i (s_axis_tdata ), - - // M_AXIS for output. - .m_axis_tready_i (m_axis_tready ), - .m_axis_tvalid_o (m_axis_tvalid ), - .m_axis_tdata_o (m_axis_tdata ), - - // Registers. - .PINC0_REG (PINC0_REG ), - .PINC1_REG (PINC1_REG ), - .PINC2_REG (PINC2_REG ), - .PINC3_REG (PINC3_REG ), - .GAIN0_REG (GAIN0_REG ), - .GAIN1_REG (GAIN1_REG ), - .GAIN2_REG (GAIN2_REG ), - .GAIN3_REG (GAIN3_REG ), - .WE_REG (WE_REG ) - ); - -endmodule - diff --git a/qick/firmware/ip/axis_sg_mux4_v2/src/ctrl.sv b/qick/firmware/ip/axis_sg_mux4_v2/src/ctrl.sv deleted file mode 100644 index e1ccea9..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v2/src/ctrl.sv +++ /dev/null @@ -1,175 +0,0 @@ -//Format of waveform interface: -// |----------|---------| -// | 39 .. 32 | 31 .. 0 | -// |----------|---------| -// | mask | nsamp | -// |----------|---------| -// nsamp : 32 bits -// mask : 8 bits -// -// Total : 40. -module ctrl ( - // Reset and clock. - rstn , - clk , - - // Fifo interface. - fifo_rd_en_o , - fifo_empty_i , - fifo_dout_i , - - // Mask output. - mask_o , - - // Output enable. - en_o ); - -// Ports. -input rstn; -input clk; -output fifo_rd_en_o; -input fifo_empty_i; -input [39:0] fifo_dout_i; -output [7:0] mask_o; -output en_o; - -// States. -typedef enum { READ_ST , - CNT_ST - } state_t; - -// State register. -(* fsm_encoding = "one_hot" *) state_t state; - -reg rd_en_int; - -// Fifo dout register. -reg [39:0] fifo_dout_r; - -// Number of samples. -wire [31:0] nsamp_int; - -// Mask. -wire [7:0] mask_int; -wire [7:0] mask_la; - -// Counter. -reg [31:0] cnt; - -// Output enable register. -reg en_reg; -wire en_reg_la; - -// Load register. -reg load_r; - -// Latency for mask. -latency_reg - #( - .N(2), - .B(8) - ) - mask_latency_reg_i - ( - .rstn (rstn ), - .clk (clk ), - - .din (mask_int ), - .dout (mask_la ) - ); - -// Latency for en_reg. -latency_reg - #( - .N(3), - .B(1) - ) - en_reg_latency_reg_i - ( - .rstn (rstn ), - .clk (clk ), - - .din (en_reg ), - .dout (en_reg_la ) - ); - - -// Registers. -always @(posedge clk) begin - if (~rstn) begin - // State register. - state <= READ_ST; - - // Fifo dout register. - fifo_dout_r <= 0; - - // Counter. - cnt <= 0; - - // Output enable register. - en_reg <= 0; - - // Load enable flag. - load_r <= 0; - end - else begin - // State register. - case (state) - READ_ST: - if (~fifo_empty_i) - state <= CNT_ST; - CNT_ST: - if ( cnt == nsamp_int-2 ) - state <= READ_ST; - endcase - - // Fifo dout register. - if (load_r) - fifo_dout_r <= fifo_dout_i; - - // Load enable flag. - load_r <= load_int; - - // Counter. - if (rd_en_int) - cnt <= 0; - else - cnt <= cnt + 1; - - // Output enable register. - if (rd_en_int) - if (!fifo_empty_i) - en_reg <= 1; - else - en_reg <= 0; - end -end - -// FSM outputs. -always_comb begin - // Default. - rd_en_int = 0; - - case (state) - READ_ST: - rd_en_int = 1; - - CNT_ST: - rd_en_int = 0; - endcase -end - -// Fifo output fields. -assign nsamp_int = fifo_dout_r[31:0]; -assign mask_int = fifo_dout_r[39:32]; - -// load_int. -assign load_int = rd_en_int & ~fifo_empty_i; - -// Assign outputs. -assign fifo_rd_en_o = rd_en_int; -assign mask_o = mask_la; -assign en_o = en_reg_la; - -endmodule - diff --git a/qick/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.veo b/qick/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.veo deleted file mode 100644 index c3dea29..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.veo +++ /dev/null @@ -1,69 +0,0 @@ -// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -// IP VLNV: xilinx.com:ip:dds_compiler:6.0 -// IP Revision: 20 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -dds_compiler_0 your_instance_name ( - .aclk(aclk), // input wire aclk - .s_axis_phase_tvalid(s_axis_phase_tvalid), // input wire s_axis_phase_tvalid - .s_axis_phase_tdata(s_axis_phase_tdata), // input wire [39 : 0] s_axis_phase_tdata - .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid - .m_axis_data_tdata(m_axis_data_tdata) // output wire [31 : 0] m_axis_data_tdata -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file dds_compiler_0.v when simulating -// the core, dds_compiler_0. When compiling the wrapper file, be sure to -// reference the Verilog simulation library. - diff --git a/qick/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.vho b/qick/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.vho deleted file mode 100644 index 4db3fc6..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.vho +++ /dev/null @@ -1,83 +0,0 @@ --- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:dds_compiler:6.0 --- IP Revision: 20 - --- The following code must appear in the VHDL architecture header. - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT dds_compiler_0 - PORT ( - aclk : IN STD_LOGIC; - s_axis_phase_tvalid : IN STD_LOGIC; - s_axis_phase_tdata : IN STD_LOGIC_VECTOR(39 DOWNTO 0); - m_axis_data_tvalid : OUT STD_LOGIC; - m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) - ); -END COMPONENT; --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : dds_compiler_0 - PORT MAP ( - aclk => aclk, - s_axis_phase_tvalid => s_axis_phase_tvalid, - s_axis_phase_tdata => s_axis_phase_tdata, - m_axis_data_tvalid => m_axis_data_tvalid, - m_axis_data_tdata => m_axis_data_tdata - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file dds_compiler_0.vhd when simulating --- the core, dds_compiler_0. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/qick/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.xci b/qick/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.xci deleted file mode 100644 index 6ae4d16..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.xci +++ /dev/null @@ -1,315 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - dds_compiler_0 - - - - 100000000 - 0 - 0 - 0.000 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 9 - 0 - 0 - 0 - 32 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 1 - 0 - 1 - 0 - 1 - 0 - 0 - 10 - 1 - 0 - 9 - 0 - 32 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 2 - 0 - 16 - 14 - 3 - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - 3 - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - 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- - C_PHASE_INCREMENT - 3 - - - C_PHASE_INCREMENT_VALUE - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - - - C_RESYNC - 1 - - - C_PHASE_OFFSET - 3 - - - C_PHASE_OFFSET_VALUE - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - - - C_OPTIMISE_GOAL - 1 - - - C_USE_DSP48 - 1 - - - C_POR_MODE - 0 - - - C_AMPLITUDE - 0 - - - C_HAS_ACLKEN - 0 - - - C_HAS_ARESETN - 0 - - - C_HAS_TLAST - 0 - - - C_HAS_TREADY - 0 - - - C_HAS_S_PHASE - 1 - - - C_S_PHASE_TDATA_WIDTH - 40 - - - C_S_PHASE_HAS_TUSER - 0 - - - C_S_PHASE_TUSER_WIDTH - 1 - - - C_HAS_S_CONFIG - 0 - - - C_S_CONFIG_SYNC_MODE - 0 - - - C_S_CONFIG_TDATA_WIDTH - 1 - - - C_HAS_M_DATA - 1 - - - C_M_DATA_TDATA_WIDTH - 32 - - - C_M_DATA_HAS_TUSER - 0 - - - C_M_DATA_TUSER_WIDTH - 1 - - - C_HAS_M_PHASE - 0 - - - C_M_PHASE_TDATA_WIDTH - 1 - - - C_M_PHASE_HAS_TUSER - 0 - - - C_M_PHASE_TUSER_WIDTH - 1 - - - C_DEBUG_INTERFACE - 0 - - - C_CHAN_WIDTH - 1 - - - - - - choice_list_0be33969 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 16 - - - choice_list_230272f2 - None - Fixed - Programmable - Streaming - - - choice_list_45db86b7 - Auto - Configurable - - - choice_list_4721e082 - Minimal - Maximal - - - choice_list_950bd3bd - Auto - Area - Speed - - - choice_list_ba6ede68 - Standard - Rasterized - - - choice_list_cd7e1d82 - Coregen - Sysgen - - - choice_list_de3e80a0 - Fixed - Programmable - Streaming - - - choice_list_faa329ca - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 16 - 17 - 18 - 19 - 20 - 21 - - - choice_pairs_0079eeec - Twos_Complement - Sign_and_Magnitude - - - choice_pairs_27d1d409 - Auto - Distributed_ROM - Block_ROM - - - choice_pairs_65a5252d - Full_Range - Unit_Circle - - - choice_pairs_6bdc34ae - System_Parameters - Hardware_Parameters - - - choice_pairs_75713637 - Packet_Framing - Not_Required - - - choice_pairs_8b9a47c2 - Auto - None - Phase_Dithering - Taylor_Series_Corrected - - - choice_pairs_944fe41d - Phase_Generator_and_SIN_COS_LUT - Phase_Generator_only - SIN_COS_LUT_only - - - choice_pairs_a54f933f - Sine - Cosine - Sine_and_Cosine - - - choice_pairs_d463c5cb - User_Field - Not_Required - - - choice_pairs_dac1efef - Not_Required - - - choice_pairs_f611af79 - On_Vector - On_Packet - - - - - xilinx_veriloginstantiationtemplate_view_fileset - - dds_compiler_0.vho - vhdlTemplate - - - dds_compiler_0.veo - verilogTemplate - - - - xilinx_vhdlsynthesis_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset - - hdl/xbip_utils_v3_0_vh_rfs.vhd - vhdlSource - xbip_utils_v3_0_10 - - - - - - - - - - - xilinx_vhdlsynthesis_xilinx_com_ip_axi_utils_2_0__ref_view_fileset - - hdl/axi_utils_v2_0_vh_rfs.vhd - vhdlSource - axi_utils_v2_0_6 - - - - - - - - - - - xilinx_vhdlsynthesis_xilinx_com_ip_xbip_pipe_3_0__ref_view_fileset - - hdl/xbip_pipe_v3_0_vh_rfs.vhd - vhdlSource - xbip_pipe_v3_0_6 - - - - - - - - - - - xilinx_vhdlsynthesis_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset - - hdl/xbip_bram18k_v3_0_vh_rfs.vhd - vhdlSource - xbip_bram18k_v3_0_6 - - - - - - - - - - - xilinx_vhdlsynthesis_xilinx_com_ip_mult_gen_12_0__ref_view_fileset - - hdl/mult_gen_v12_0_vh_rfs.vhd - vhdlSource - mult_gen_v12_0_16 - - - - - - - - - - - xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_wrapper_3_0__ref_view_fileset - - hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd - vhdlSource - xbip_dsp48_wrapper_v3_0_4 - - - - - - - - - - - xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_addsub_3_0__ref_view_fileset - - hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd - vhdlSource - xbip_dsp48_addsub_v3_0_6 - - - - - - - - - - - xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_multadd_3_0__ref_view_fileset - - hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd - vhdlSource - xbip_dsp48_multadd_v3_0_6 - - - - - - - - - - - xilinx_vhdlsynthesis_view_fileset - - hdl/dds_compiler_v6_0_vh_rfs.vhd - vhdlSource - dds_compiler_v6_0_20 - - - - xilinx_synthesisconstraints_view_fileset - - dds_compiler_0_ooc.xdc - xdc - USED_IN_implementation - USED_IN_out_of_context - USED_IN_synthesis - - - - xilinx_vhdlsynthesiswrapper_view_fileset - - synth/dds_compiler_0.vhd - vhdlSource - xil_defaultlib - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset - - hdl/xbip_utils_v3_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - xbip_utils_v3_0_10 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_utils_2_0__ref_view_fileset - - hdl/axi_utils_v2_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - axi_utils_v2_0_6 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_pipe_3_0__ref_view_fileset - - hdl/xbip_pipe_v3_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - xbip_pipe_v3_0_6 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset - - hdl/xbip_bram18k_v3_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - xbip_bram18k_v3_0_6 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_mult_gen_12_0__ref_view_fileset - - hdl/mult_gen_v12_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - mult_gen_v12_0_16 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_wrapper_3_0__ref_view_fileset - - hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - xbip_dsp48_wrapper_v3_0_4 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_addsub_3_0__ref_view_fileset - - hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - xbip_dsp48_addsub_v3_0_6 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_multadd_3_0__ref_view_fileset - - hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - xbip_dsp48_multadd_v3_0_6 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_view_fileset - - hdl/dds_compiler_v6_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - dds_compiler_v6_0_20 - - - - xilinx_vhdlsimulationwrapper_view_fileset - - sim/dds_compiler_0.vhd - vhdlSource - xil_defaultlib - - - - xilinx_cmodelsimulation_view_fileset - - cmodel/dds_compiler_v6_0_bitacc_cmodel_lin64.zip - zip - - - cmodel/dds_compiler_v6_0_bitacc_cmodel_nt64.zip - zip - - - - xilinx_vhdltestbench_view_fileset - - demo_tb/tb_dds_compiler_0.vhd - vhdlSource - - - - xilinx_versioninformation_view_fileset - - doc/dds_compiler_v6_0_changelog.txt - text - - - - xilinx_externalfiles_view_fileset - - dds_compiler_0.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - dds_compiler_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - dds_compiler_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - dds_compiler_0_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - dds_compiler_0_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - - The Xilinx DDS Compiler LogiCORE provides Direct Digital Synthesizers (DDS) and optionally either Phase Generator or Sine/Cosine Lookup Table constituent parts as independent cores. The core features sine, cosine or quadrature outputs with 3 to 26-bit output sample precision. The core supports up to 16 channels by time-sharing the sine/cosine table which dramatically reduces the area requirement when multiple channels are needed. Phase Dithering and Taylor Series Correction options provide high dynamic range signals using minimal FPGA resources. In addition, the core has an optional phase offset capability, providing support for multiple synthesizers with precisely controlled phase differences. - - - Component_Name - Component Name - dds_compiler_0 - - - PartsPresent - Configuration Options - Phase_Generator_and_SIN_COS_LUT - - - DDS_Clock_Rate - System Clock - 256 - - - Channels - Number of Channels - 1 - - - Mode_of_Operation - Mode Of Operation - Standard - - - Modulus - Modulus - 9 - - - Parameter_Entry - Parameter Selection - System_Parameters - - - Spurious_Free_Dynamic_Range - Spurious Free Dynamic Range - 96 - - - Frequency_Resolution - Frequency Resolution - 3906.25 - - - Noise_Shaping - Noise Shaping - Auto - - - Phase_Width - Phase Width - 16 - - - Output_Width - Output Width - 16 - - - Phase_Increment - Phase Increment - Streaming - - - Resync - Resync - true - - - Phase_offset - Phase Offset - Streaming - - - Output_Selection - Output Selection - Sine_and_Cosine - - - Negative_Sine - Negative Sine - false - - - Negative_Cosine - Negative Cosine - false - - - Amplitude_Mode - Amplitude Mode - Full_Range - - - Memory_Type - Memory Type - Auto - - - Optimization_Goal - Optimization Goal - Speed - - - DSP48_Use - DSP48 Use - Maximal - - - Has_Phase_Out - Has Phase Out - false - - - DATA_Has_TLAST - DATA Has TLAST - Not_Required - - - Has_TREADY - Output TREADY - false - - - S_PHASE_Has_TUSER - Input - Not_Required - - - S_PHASE_TUSER_Width - User Field Width - 1 - - - M_DATA_Has_TUSER - DATA Output - Not_Required - - - M_PHASE_Has_TUSER - PHASE Output - Not_Required - - - S_CONFIG_Sync_Mode - Synchronization Mode - On_Vector - - - OUTPUT_FORM - Output Form - Twos_Complement - - - Latency_Configuration - Configurable - - - Latency - 10 - - - Has_ARESETn - ARESETn (active low) - false - - - Has_ACLKEN - ACLKEN - false - - - Output_Frequency1 - 0 - - - PINC1 - 0 - - - Phase_Offset_Angles1 - 0 - - - POFF1 - 0 - - - Output_Frequency2 - 0 - - - PINC2 - 0 - - - Phase_Offset_Angles2 - 0 - - - POFF2 - 0 - - - Output_Frequency3 - 0 - - - PINC3 - 0 - - - Phase_Offset_Angles3 - 0 - - - POFF3 - 0 - - - Output_Frequency4 - 0 - - - PINC4 - 0 - - - Phase_Offset_Angles4 - 0 - - - POFF4 - 0 - - - Output_Frequency5 - 0 - - - PINC5 - 0 - - - Phase_Offset_Angles5 - 0 - - - POFF5 - 0 - - - Output_Frequency6 - 0 - - - PINC6 - 0 - - - Phase_Offset_Angles6 - 0 - - - POFF6 - 0 - - - Output_Frequency7 - 0 - - - PINC7 - 0 - - - Phase_Offset_Angles7 - 0 - - - POFF7 - 0 - - - Output_Frequency8 - 0 - - - PINC8 - 0 - - - Phase_Offset_Angles8 - 0 - - - POFF8 - 0 - - - Output_Frequency9 - 0 - - - PINC9 - 0 - - - Phase_Offset_Angles9 - 0 - - - POFF9 - 0 - - - Output_Frequency10 - 0 - - - PINC10 - 0 - - - Phase_Offset_Angles10 - 0 - - - POFF10 - 0 - - - Output_Frequency11 - 0 - - - PINC11 - 0 - - - Phase_Offset_Angles11 - 0 - - - POFF11 - 0 - - - Output_Frequency12 - 0 - - - PINC12 - 0 - - - Phase_Offset_Angles12 - 0 - - - POFF12 - 0 - - - Output_Frequency13 - 0 - - - PINC13 - 0 - - - Phase_Offset_Angles13 - 0 - - - POFF13 - 0 - - - Output_Frequency14 - 0 - - - PINC14 - 0 - - - Phase_Offset_Angles14 - 0 - - - POFF14 - 0 - - - Output_Frequency15 - 0 - - - PINC15 - 0 - - - Phase_Offset_Angles15 - 0 - - - POFF15 - 0 - - - Output_Frequency16 - 0 - - - PINC16 - 0 - - - Phase_Offset_Angles16 - 0 - - - POFF16 - 0 - - - POR_mode - POR Mode - false - - - GUI_Behaviour - Coregen - - - explicit_period - false - - - period - 1 - - - - - DDS Compiler - 20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2020.2 - - - - - - - - diff --git a/qick/firmware/ip/axis_sg_mux4_v2/src/dds_top.v b/qick/firmware/ip/axis_sg_mux4_v2/src/dds_top.v deleted file mode 100644 index c940d26..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v2/src/dds_top.v +++ /dev/null @@ -1,163 +0,0 @@ -module dds_top ( - // Reset and clock. - rstn , - clk , - - // DDS output. - dds_dout_o , - - // Registers. - PINC_REG , - GAIN_REG , - WE_REG - ); - -/**************/ -/* Parameters */ -/**************/ -// Number of parallel dds blocks. -parameter [31:0] N_DDS = 2; - -/*********/ -/* Ports */ -/*********/ -input rstn; -input clk; - -output [N_DDS*32-1:0] dds_dout_o; - -input [31:0] PINC_REG; -input [15:0] GAIN_REG; -input WE_REG; - -/********************/ -/* Internal signals */ -/********************/ -// DDS input control. -reg dds_tvalid_r; -wire [N_DDS*72-1:0] dds_ctrl_int; -reg [N_DDS*72-1:0] dds_ctrl_int_r; - -// DDS output. -wire [31:0] dds_dout [0:N_DDS-1]; -wire [31:0] dds_dout_la [0:N_DDS-1]; - -// Product. -wire signed [15:0] gain; -wire signed [15:0] prod_a_real [0:N_DDS-1]; -wire signed [15:0] prod_a_imag [0:N_DDS-1]; -wire signed [31:0] prod_real [0:N_DDS-1]; -wire signed [31:0] prod_imag [0:N_DDS-1]; -reg [31:0] prod_real_r1[0:N_DDS-1]; -reg [31:0] prod_imag_r1[0:N_DDS-1]; -wire [15:0] prod_real_q [0:N_DDS-1]; -wire [15:0] prod_imag_q [0:N_DDS-1]; -wire [31:0] prod [0:N_DDS-1]; -reg [31:0] prod_r1 [0:N_DDS-1]; - -/**********************/ -/* Begin Architecture */ -/**********************/ -// Phase Control block. -phase_ctrl - #( - .N_DDS (N_DDS ) - ) - phase_ctrl_i - ( - // Reset and clock. - .rstn (rstn ), - .clk (clk ), - - // dds control. - .dds_ctrl_o (dds_ctrl_int ), - - // Registers. - .PINC_REG (PINC_REG ), - .WE_REG (WE_REG ) - ); - -generate -genvar i; - for (i=0; i N_LOG2, - -- Data width. - B => B - ) - Port map ( - clk => clk , - ena => '1' , - enb => rd_en , - wea => mem_wea , - addra => std_logic_vector(wptr) , - addrb => std_logic_vector(rptr) , - dia => din , - dob => mem_dob - ); - --- Memory connections. -mem_wea <= wr_en when full_i = '0' else - '0'; - --- Full/empty signals. -full_i <= '1' when wptr = rptr - 1 else - '0'; -empty_i <= '1' when wptr = rptr else - '0'; - --- wr_clk registers. -process (clk) -begin - if ( rising_edge(clk) ) then - if ( rstn = '0' ) then - wptr <= (others => '0'); - rptr <= (others => '0'); - else - -- Write. - if ( wr_en = '1' and full_i = '0' ) then - -- Write data. - - -- Increment pointer. - wptr <= wptr + 1; - end if; - - -- Read. - if ( rd_en = '1' and empty_i = '0' ) then - -- Read data. - - -- Increment pointer. - rptr <= rptr + 1; - end if; - end if; - end if; -end process; - --- Assign outputs. -dout <= mem_dob; -full <= full_i; -empty <= empty_i; - -end rtl; - diff --git a/qick/firmware/ip/axis_sg_mux4_v2/src/fifo/fifo_axi.vhd b/qick/firmware/ip/axis_sg_mux4_v2/src/fifo/fifo_axi.vhd deleted file mode 100644 index e1f76f7..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v2/src/fifo/fifo_axi.vhd +++ /dev/null @@ -1,147 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo_axi is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo_axi; - -architecture rtl of fifo_axi is - --- FIFO. -component fifo is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end component; - --- FIFO read to AXI adapter. -component rd2axi is - Generic - ( - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- FIFO Read I/F. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (B-1 downto 0); - fifo_empty : in std_logic; - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - empty : out std_logic - ); -end component; - -signal rd_en_i : std_logic; -signal dout_i : std_logic_vector (B-1 downto 0); -signal empty_i : std_logic; - -begin - --- FIFO. -fifo_i : fifo - Generic map - ( - -- Data width. - B => B, - - -- Fifo depth. - N => N - ) - Port map - ( - rstn => rstn , - clk => clk , - - -- Write I/F. - wr_en => wr_en , - din => din , - - -- Read I/F. - rd_en => rd_en_i , - dout => dout_i , - - -- Flags. - full => full , - empty => empty_i - ); - --- FIFO read to AXI adapter. -rd2axi_i : rd2axi - Generic map - ( - -- Data width. - B => B - ) - Port map - ( - rstn => rstn , - clk => clk , - - -- FIFO Read I/F. - fifo_rd_en => rd_en_i , - fifo_dout => dout_i , - fifo_empty => empty_i , - - -- Read I/F. - rd_en => rd_en , - dout => dout , - empty => empty - ); - -end rtl; - diff --git a/qick/firmware/ip/axis_sg_mux4_v2/src/fifo/fifo_dc.vhd b/qick/firmware/ip/axis_sg_mux4_v2/src/fifo/fifo_dc.vhd deleted file mode 100644 index c214fae..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v2/src/fifo/fifo_dc.vhd +++ /dev/null @@ -1,291 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo_dc is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - wr_rstn : in std_logic; - wr_clk : in std_logic; - - rd_rstn : in std_logic; - rd_clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo_dc; - -architecture rtl of fifo_dc is - --- Number of bits of depth. -constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); - --- Binary to gray converter. -component bin2gray is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end component; - --- Gray to binary converter. -component gray2bin is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end component; - --- Vector synchronizer (only for gray coded). -component synchronizer_vect is - generic ( - -- Sync stages. - N : Integer := 2; - - -- Data width. - B : Integer := 8 - ); - port ( - rstn : in std_logic; - clk : in std_logic; - data_in : in std_logic_vector (B-1 downto 0); - data_out : out std_logic_vector (B-1 downto 0) - ); -end component; - --- Dual port BRAM. -component bram_dp is - Generic ( - -- Memory address size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - ena : in STD_LOGIC; - enb : in STD_LOGIC; - wea : in STD_LOGIC; - web : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR (N-1 downto 0); - addrb : in STD_LOGIC_VECTOR (N-1 downto 0); - dia : in STD_LOGIC_VECTOR (B-1 downto 0); - dib : in STD_LOGIC_VECTOR (B-1 downto 0); - doa : out STD_LOGIC_VECTOR (B-1 downto 0); - dob : out STD_LOGIC_VECTOR (B-1 downto 0) - ); -end component; - --- Pointers. -signal wptr : unsigned (N_LOG2-1 downto 0); -signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); -signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); -signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); -signal rptr : unsigned (N_LOG2-1 downto 0); -signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); -signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); -signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); - --- Memory signals. -signal mem_wea : std_logic; -signal mem_dib : std_logic_vector (B-1 downto 0); -signal mem_doa : std_logic_vector (B-1 downto 0); -signal mem_dob : std_logic_vector (B-1 downto 0); - --- Flags. -signal full_i : std_logic; -signal empty_i : std_logic; - -begin - --- wptr_i: binary to gray. -wptr_i : bin2gray - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => std_logic_vector(wptr), - dout => wptr_g - ); - --- wptr_g: write to read domain. -wptr_g_i : synchronizer_vect - generic map ( - -- Sync stages. - N => 2, - - -- Data width. - B => N_LOG2 - ) - port map ( - rstn => rd_rstn, - clk => rd_clk, - data_in => wptr_g, - data_out => wptr_gc - ); - --- wptr_gc_i -wptr_gc_i : gray2bin - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => wptr_gc, - dout => wptr_c - ); - --- rptr_i: binary to gray. -rptr_i : bin2gray - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => std_logic_vector(rptr), - dout => rptr_g - ); - --- rptr_g: read to write domain. -rptr_g_i : synchronizer_vect - generic map ( - -- Sync stages. - N => 2, - - -- Data width. - B => N_LOG2 - ) - port map ( - rstn => wr_rstn, - clk => wr_clk, - data_in => rptr_g, - data_out => rptr_gc - ); - --- rptr_gc_i -rptr_gc_i : gray2bin - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => rptr_gc, - dout => rptr_c - ); - --- FIFO memory. -mem_i : bram_dp - Generic map ( - -- Memory address size. - N => N_LOG2, - -- Data width. - B => B - ) - Port map ( - clka => wr_clk, - clkb => rd_clk, - ena => '1', - enb => rd_en, - wea => mem_wea, - web => '0', - addra => std_logic_vector(wptr), - addrb => std_logic_vector(rptr), - dia => din, - dib => mem_dib, - doa => mem_doa, - dob => mem_dob - ); --- Memory connections. -mem_wea <= wr_en when full_i = '0' else - '0'; -mem_dib <= (others => '0'); - --- Full/empty signals. -full_i <= '1' when wptr = unsigned(rptr_c) - 1 else - '0'; -empty_i <= '1' when unsigned(wptr_c) = rptr else - '0'; - --- wr_clk registers. -process (wr_clk) -begin - if ( rising_edge(wr_clk) ) then - if ( wr_rstn = '0' ) then - wptr <= (others => '0'); - else - -- Write. - if ( wr_en = '1' and full_i = '0' ) then - -- Write data. - - -- Increment pointer. - wptr <= wptr + 1; - end if; - end if; - end if; -end process; - --- rd_clk registers. -process (rd_clk) -begin - if ( rising_edge(rd_clk) ) then - if ( rd_rstn = '0' ) then - rptr <= (others => '0'); - else - -- Read. - if ( rd_en = '1' and empty_i = '0' ) then - -- Read data. - - -- Increment pointer. - rptr <= rptr + 1; - end if; - end if; - end if; -end process; - --- Assign outputs. -dout <= mem_dob; -full <= full_i; -empty <= empty_i; - -end rtl; diff --git a/qick/firmware/ip/axis_sg_mux4_v2/src/fifo/fifo_dc_axi.vhd b/qick/firmware/ip/axis_sg_mux4_v2/src/fifo/fifo_dc_axi.vhd deleted file mode 100644 index eb83d1a..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v2/src/fifo/fifo_dc_axi.vhd +++ /dev/null @@ -1,156 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo_dc_axi is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - wr_rstn : in std_logic; - wr_clk : in std_logic; - - rd_rstn : in std_logic; - rd_clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo_dc_axi; - -architecture rtl of fifo_dc_axi is - --- Dual-clock FIFO. -component fifo_dc is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - wr_rstn : in std_logic; - wr_clk : in std_logic; - - rd_rstn : in std_logic; - rd_clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end component; - --- FIFO read to AXI adapter. -component rd2axi is - Generic - ( - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- FIFO Read I/F. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (B-1 downto 0); - fifo_empty : in std_logic; - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - empty : out std_logic - ); -end component; - -signal rd_en_i : std_logic; -signal dout_i : std_logic_vector (B-1 downto 0); -signal empty_i : std_logic; - -begin - --- Dual-clock FIFO. -fifo_i : fifo_dc - Generic map - ( - -- Data width. - B => B, - - -- Fifo depth. - N => N - ) - Port map - ( - wr_rstn => wr_rstn , - wr_clk => wr_clk , - - rd_rstn => rd_rstn , - rd_clk => rd_clk , - - -- Write I/F. - wr_en => wr_en , - din => din , - - -- Read I/F. - rd_en => rd_en_i , - dout => dout_i , - - -- Flags. - full => full , - empty => empty_i - ); - --- FIFO read to AXI adapter. -rd2axi_i : rd2axi - Generic map - ( - -- Data width. - B => B - ) - Port map - ( - rstn => rd_rstn , - clk => rd_clk , - - -- FIFO Read I/F. - fifo_rd_en => rd_en_i , - fifo_dout => dout_i , - fifo_empty => empty_i , - - -- Read I/F. - rd_en => rd_en , - dout => dout , - empty => empty - ); - -end rtl; - diff --git a/qick/firmware/ip/axis_sg_mux4_v2/src/fifo/gray2bin.vhd b/qick/firmware/ip/axis_sg_mux4_v2/src/fifo/gray2bin.vhd deleted file mode 100644 index e23f8af..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v2/src/fifo/gray2bin.vhd +++ /dev/null @@ -1,37 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity gray2bin is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end gray2bin; - -architecture rtl of gray2bin is - -signal bin : std_logic_vector (B-1 downto 0); - -begin - --- MSB always match. -bin(B-1) <= din(B-1); - -GEN: for I in 0 to B-2 generate -begin - bin(I) <= bin(I+1) xor din(I); -end generate GEN; - --- Assign output. -dout <= bin; - -end rtl; - diff --git a/qick/firmware/ip/axis_sg_mux4_v2/src/fifo/rd2axi.vhd b/qick/firmware/ip/axis_sg_mux4_v2/src/fifo/rd2axi.vhd deleted file mode 100644 index babadc6..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v2/src/fifo/rd2axi.vhd +++ /dev/null @@ -1,138 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity rd2axi is - Generic - ( - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- FIFO Read I/F. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (B-1 downto 0); - fifo_empty : in std_logic; - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - empty : out std_logic - ); -end rd2axi; - -architecture rtl of rd2axi is - -type fsm_state is ( WAIT_EMPTY_ST, - READ_FIRST_ST, - READ_ST, - READ_LAST_ST); -signal current_state, next_state : fsm_state; - -signal wait_empty_state : std_logic; -signal read_first_state : std_logic; -signal read_state : std_logic; - -signal fifo_rd_en_i : std_logic; -signal empty_i : std_logic; - -begin - -process(clk) -begin - if (rising_edge(clk)) then - if (rstn = '0') then - current_state <= WAIT_EMPTY_ST; - else - current_state <= next_state; - end if; - end if; -end process; - --- Next state logic. -process(current_state, fifo_empty, rd_en) -begin - case current_state is - when WAIT_EMPTY_ST => - if (fifo_empty = '1') then - next_state <= WAIT_EMPTY_ST; - else - next_state <= READ_FIRST_ST; - end if; - - when READ_FIRST_ST => - next_state <= READ_ST; - - when READ_ST => - if (fifo_empty = '0') then - next_state <= READ_ST; - else - if (rd_en = '1') then - next_state <= WAIT_EMPTY_ST; - else - next_state <= READ_LAST_ST; - end if; - end if; - - when READ_LAST_ST => - if (rd_en = '0') then - next_state <= READ_LAST_ST; - else - next_state <= WAIT_EMPTY_ST; - end if; - - end case; -end process; - --- Output logic. -process(current_state) -begin -wait_empty_state <= '0'; -read_first_state <= '0'; -read_state <= '0'; -empty_i <= '0'; - case current_state is - when WAIT_EMPTY_ST => - wait_empty_state <= '1'; - read_first_state <= '0'; - read_state <= '0'; - empty_i <= '1'; - - when READ_FIRST_ST => - wait_empty_state <= '0'; - read_first_state <= '1'; - read_state <= '0'; - empty_i <= '1'; - - when READ_ST => - wait_empty_state <= '0'; - read_first_state <= '0'; - read_state <= '1'; - empty_i <= '0'; - - when READ_LAST_ST => - wait_empty_state <= '0'; - read_first_state <= '0'; - read_state <= '0'; - empty_i <= '0'; - - end case; -end process; - --- FIFO Read enable signal. -fifo_rd_en_i <= read_first_state or (read_state and rd_en); - --- Assign outputs. -fifo_rd_en <= fifo_rd_en_i; --- TODO: add register to freeze last value. -dout <= fifo_dout when empty_i = '0' else - (others => '0'); -empty <= empty_i; - -end rtl; - diff --git a/qick/firmware/ip/axis_sg_mux4_v2/src/fifo/synchronizer_vect.vhd b/qick/firmware/ip/axis_sg_mux4_v2/src/fifo/synchronizer_vect.vhd deleted file mode 100644 index 2fbb696..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v2/src/fifo/synchronizer_vect.vhd +++ /dev/null @@ -1,49 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - --- This block is intended to use to sync gray coded vectors. - --- NOTE: Do not use with generic vector data, as it may result --- in corrupted re-sync data. - -entity synchronizer_vect is - generic ( - -- Sync stages. - N : Integer := 2; - - -- Data width. - B : Integer := 8 - ); - port ( - rstn : in std_logic; - clk : in std_logic; - data_in : in std_logic_vector (B-1 downto 0); - data_out : out std_logic_vector (B-1 downto 0) - ); -end synchronizer_vect; - -architecture rtl of synchronizer_vect is - --- Internal register. -type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); -signal data_int_reg : reg_t; - -begin - -process(clk) -begin - if (rising_edge(clk)) then - if (rstn = '0') then - data_int_reg <= (others => (others => '0')); -- 1 FF. - else - data_int_reg <= data_int_reg(N-2 downto 0) & data_in; - end if; - end if; -end process; - --- Assign output. -data_out <= data_int_reg(N-1); - -end rtl; - diff --git a/qick/firmware/ip/axis_sg_mux4_v2/src/latency_reg.v b/qick/firmware/ip/axis_sg_mux4_v2/src/latency_reg.v deleted file mode 100644 index 687a9f3..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v2/src/latency_reg.v +++ /dev/null @@ -1,61 +0,0 @@ -module latency_reg - ( - rstn , - clk , - - din , - dout - ); - -// Parameters. -parameter N = 2; // Latency. -parameter B = 8; // Data width. - -// Ports. -input rstn; -input clk; -input [B-1:0] din; -output [B-1:0] dout; - -// Shift register. -reg [B-1:0] shift_r [0:N-1]; - -generate -genvar i; - for (i=1; i '0'); - else - data_int_reg <= data_int_reg(N-2 downto 0) & data_in; - end if; - end if; -end process; - --- Assign output. -data_out <= data_int_reg(N-1); - -end rtl; - diff --git a/qick/firmware/ip/axis_sg_mux4_v2/src/tb/tb.sv b/qick/firmware/ip/axis_sg_mux4_v2/src/tb/tb.sv deleted file mode 100644 index 5dce62b..0000000 --- a/qick/firmware/ip/axis_sg_mux4_v2/src/tb/tb.sv +++ /dev/null @@ -1,340 +0,0 @@ -import axi_vip_pkg::*; -import axi_mst_0_pkg::*; - -module tb(); - -// DUT generics. -parameter N_DDS = 2; - -// s_axi interfase. -reg s_axi_aclk; -reg s_axi_aresetn; -wire [5:0] s_axi_araddr; -wire [2:0] s_axi_arprot; -wire s_axi_arready; -wire s_axi_arvalid; -wire [5:0] s_axi_awaddr; -wire [2:0] s_axi_awprot; -wire s_axi_awready; -wire s_axi_awvalid; -wire s_axi_bready; -wire [1:0] s_axi_bresp; -wire s_axi_bvalid; -wire [31:0] s_axi_rdata; -wire s_axi_rready; -wire [1:0] s_axi_rresp; -wire s_axi_rvalid; -wire [31:0] s_axi_wdata; -wire s_axi_wready; -wire [3:0] s_axi_wstrb; -wire s_axi_wvalid; - -reg aresetn; -reg aclk; - -// s_axis interfase. -wire [39:0] s_axis_tdata; -wire s_axis_tready; -reg s_axis_tvalid; - -// m_axis interfase. -wire [N_DDS*32-1:0] m_axis_tdata; -reg m_axis_tready = 1; -wire m_axis_tvalid; - -// Waveform fields. -reg [31:0] nsamp_r; -reg [7:0] mask_r; - -// Assignment of data out for debugging. -wire [31:0] dout_ii [0:N_DDS-1]; - -xil_axi_prot_t prot = 0; -reg[31:0] data_wr = 32'h12345678; -reg[31:0] data; -xil_axi_resp_t resp; - -// TB control. -reg tb_load_wave = 0; -reg tb_load_wave_done = 0; -reg tb_write_out = 0; - -// Debug. -generate -genvar ii; -for (ii = 0; ii < N_DDS; ii = ii + 1) begin : GEN_debug - assign dout_ii[ii] = m_axis_tdata[32*ii +: 32]; -end -endgenerate - -// M_AXI. -axi_mst_0 axi_mst_0_i - ( - .aclk (s_axi_aclk ), - .aresetn (s_axi_aresetn ), - .m_axi_araddr (s_axi_araddr ), - .m_axi_arprot (s_axi_arprot ), - .m_axi_arready (s_axi_arready ), - .m_axi_arvalid (s_axi_arvalid ), - .m_axi_awaddr (s_axi_awaddr ), - .m_axi_awprot (s_axi_awprot ), - .m_axi_awready (s_axi_awready ), - .m_axi_awvalid (s_axi_awvalid ), - .m_axi_bready (s_axi_bready ), - .m_axi_bresp (s_axi_bresp ), - .m_axi_bvalid (s_axi_bvalid ), - .m_axi_rdata (s_axi_rdata ), - .m_axi_rready (s_axi_rready ), - .m_axi_rresp (s_axi_rresp ), - .m_axi_rvalid (s_axi_rvalid ), - .m_axi_wdata (s_axi_wdata ), - .m_axi_wready (s_axi_wready ), - .m_axi_wstrb (s_axi_wstrb ), - .m_axi_wvalid (s_axi_wvalid ) - ); - -axis_sg_mux4_v1 - # - ( - .N_DDS(N_DDS) - ) - DUT - ( - // AXI Slave I/F for configuration. - .s_axi_aclk (s_axi_aclk ), - .s_axi_aresetn (s_axi_aresetn ), - .s_axi_araddr (s_axi_araddr ), - .s_axi_arprot (s_axi_arprot ), - .s_axi_arready (s_axi_arready ), - .s_axi_arvalid (s_axi_arvalid ), - .s_axi_awaddr (s_axi_awaddr ), - .s_axi_awprot (s_axi_awprot ), - .s_axi_awready (s_axi_awready ), - .s_axi_awvalid (s_axi_awvalid ), - .s_axi_bready (s_axi_bready ), - .s_axi_bresp (s_axi_bresp ), - .s_axi_bvalid (s_axi_bvalid ), - .s_axi_rdata (s_axi_rdata ), - .s_axi_rready (s_axi_rready ), - .s_axi_rresp (s_axi_rresp ), - .s_axi_rvalid (s_axi_rvalid ), - .s_axi_wdata (s_axi_wdata ), - .s_axi_wready (s_axi_wready ), - .s_axi_wstrb (s_axi_wstrb ), - .s_axi_wvalid (s_axi_wvalid ), - - // s_* and m_* reset/clock. - .aresetn (aresetn ), - .aclk (aclk ), - - // S_AXIS to queue waveforms. - .s_axis_tready (s_axis_tready ), - .s_axis_tvalid (s_axis_tvalid ), - .s_axis_tdata (s_axis_tdata ), - - // AXIS Master for output data. - .m_axis_tready (m_axis_tready ), - .m_axis_tvalid (m_axis_tvalid ), - .m_axis_tdata (m_axis_tdata ) - ); - -// VIP Agents -axi_mst_0_mst_t axi_mst_0_agent; - -// Waveform fields. -assign s_axis_tdata = {mask_r,nsamp_r}; - - -initial begin - // Create agents. - axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); - - // Set tag for agents. - axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); - - // Start agents. - axi_mst_0_agent.start_master(); - - // Reset sequence. - s_axi_aresetn <= 0; - aresetn <= 0; - #500; - s_axi_aresetn <= 1; - aresetn <= 1; - - #1000; - - $display("###########################"); - $display("### Program Frequencies ###"); - $display("###########################"); - $display("t = %0t", $time); - - // PINC0_REG - data_wr = freq_calc(100, N_DDS, 1); - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*0, prot, data_wr, resp); - #10; - - // PINC1_REG - data_wr = freq_calc(100, N_DDS, 11); - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*1, prot, data_wr, resp); - #10; - - // PINC2_REG - data_wr = freq_calc(100, N_DDS, 27); - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*2, prot, data_wr, resp); - #10; - - // PINC3_REG - data_wr = freq_calc(100, N_DDS, 115); - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*3, prot, data_wr, resp); - #10; - - // GAIN0_REG - data_wr = 32000; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*4, prot, data_wr, resp); - #10; - - // GAIN1_REG - data_wr = 25000; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*5, prot, data_wr, resp); - #10; - - // GAIN2_REG - data_wr = 10000; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*6, prot, data_wr, resp); - #10; - - // GAIN3_REG - data_wr = 1000; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*7, prot, data_wr, resp); - #10; - - // we. - data_wr = 1; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*8, prot, data_wr, resp); - #10; - - // we. - data_wr = 0; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*8, prot, data_wr, resp); - #10; - - $display("#######################"); - $display("### Queue Waveforms ###"); - $display("#######################"); - $display("t = %0t", $time); - - // Queue waveforms and write output while queuing. - tb_load_wave <= 1; - tb_write_out <= 1; - wait (tb_load_wave_done); - - #30000; - - // Stop writing output data. - tb_write_out <= 0; - - #20000; - -end - -// Load waveforms. -initial begin - s_axis_tvalid <= 0; - nsamp_r <= 0; - mask_r <= 0; - - wait (tb_load_wave); - wait (s_axis_tready); - - @(posedge aclk); - $display("t = %0t", $time); - s_axis_tvalid <= 1; - nsamp_r <= 550; - mask_r <= 8'b0000_1111; - - @(posedge aclk); - $display("t = %0t", $time); - s_axis_tvalid <= 1; - nsamp_r <= 350; - mask_r <= 8'b0000_1111; - - //@(posedge aclk); - //$display("t = %0t", $time); - //s_axis_tvalid_i <= 1; - //nsamp_r <= 25; - //mask_r <= 8'b0000_0010; - - //@(posedge aclk); - //$display("t = %0t", $time); - //s_axis_tvalid_i <= 1; - //nsamp_r <= 35; - //mask_r <= 8'b0000_0100; - - //@(posedge aclk); - //$display("t = %0t", $time); - //s_axis_tvalid_i <= 1; - //nsamp_r <= 63; - //mask_r <= 8'b0000_1000; - - @(posedge aclk); - s_axis_tvalid <= 0; - tb_load_wave_done <= 1; -end - -// Write output into file. -initial begin - int fd; - int i; - shortint real_d, imag_d; - - // Output file. - fd = $fopen("../../../../../tb/dout.csv","w"); - - // Data format. - $fdisplay(fd, "valid, idx, real, imag"); - - wait (tb_write_out); - - while (tb_write_out) begin - @(posedge aclk); - for (i=0; i - - user.org - user - axis_signal_gen_v4 - 1.0 - - - m_axis - - - - - - - TDATA - - - m_axis_tdata - - - - - TVALID - - - m_axis_tvalid - - - - - TREADY - - - m_axis_tready - - - - - - s0_axis - - - - - - - TDATA - - - s0_axis_tdata - - - - - TVALID - - - s0_axis_tvalid - - - - - TREADY - - - s0_axis_tready - - - - - - s1_axis - - - - - - - TDATA - - - s1_axis_tdata - - - - - TVALID - - - s1_axis_tvalid - - - - - TREADY - - - s1_axis_tready - - - - - - s_axi - - - - - - - - - AWADDR - - - s_axi_awaddr - - - - - AWPROT - - - s_axi_awprot - - - - - AWVALID - - - s_axi_awvalid - - - - - AWREADY - - - s_axi_awready - - - - - WDATA - - - s_axi_wdata - - - - - WSTRB - - - s_axi_wstrb - - - - - WVALID - - - s_axi_wvalid - - - - - WREADY - - - s_axi_wready - - - - - BRESP - - - s_axi_bresp - - - - - BVALID - - - s_axi_bvalid - - - - - BREADY - - - s_axi_bready - - - - - ARADDR - - - s_axi_araddr - - - - - ARPROT - - - s_axi_arprot - - - - - ARVALID - - - s_axi_arvalid - - - - - ARREADY - - - s_axi_arready - - - - - RDATA - - - s_axi_rdata - - - - - RRESP - - - s_axi_rresp - - - - - RVALID - - - s_axi_rvalid - - - - - RREADY - - - s_axi_rready - - - - - - s_axi_aclk - - - - - - - CLK - - - s_axi_aclk - - - - - - ASSOCIATED_BUSIF - s_axi - - - ASSOCIATED_RESET - s_axi_aresetn - - - - - s_axi_aresetn - - - - - - - RST - - - s_axi_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - s0_axis_aclk - - - - - - - CLK - - - s0_axis_aclk - - - - - - ASSOCIATED_BUSIF - s0_axis - - - ASSOCIATED_RESET - s0_axis_aresetn - - - - - s0_axis_aresetn - - - - - - - RST - - - s0_axis_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - aclk - - - - - - - CLK - - - aclk - - - - - - ASSOCIATED_BUSIF - m_axis:s1_axis - - - ASSOCIATED_RESET - aresetn - - - - - aresetn - - - - - - - RST - - - aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - - - s_axi - - reg0 - 0 - 64 - 32 - register - - - - - - - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis - Verilog - axis_signal_gen_v4 - - xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset - - - xilinx_anylanguagesynthesis_view_fileset - - - - viewChecksum - 203ec419 - - - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - Verilog - axis_signal_gen_v4 - - xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - - - viewChecksum - 203ec419 - - - - - xilinx_xpgui - UI Layout - :vivado.xilinx.com:xgui.ui - - xilinx_xpgui_view_fileset - - - - viewChecksum - e51fb623 - - - - - - - s_axi_aclk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_aresetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_awaddr - - in - - 5 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_awprot - - in - - 2 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_awvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_awready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_wdata - - in - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_wstrb - - in - - 3 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 1 - - - - - s_axi_wvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_wready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_bresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_bvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_bready - - in - - - std_logic - xilinx_anylanguagesynthesis - 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0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s1_axis_tvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s1_axis_tready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m_axis_tready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 1 - - - - - m_axis_tvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m_axis_tdata - - out - - 255 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - - N - N - 12 - - - N_DDS - N Dds - 16 - - - - - - choice_list_9d8b0d81 - ACTIVE_HIGH - ACTIVE_LOW - - - - - xilinx_anylanguagesynthesis_view_fileset - - src/dds_compiler_0/dds_compiler_0.xci - xci - - - src/signal_gen.v - verilogSource - - - src/signal_gen_top.v - verilogSource - - - src/ctrl.sv - systemVerilogSource - - - src/axi_slv.vhd - vhdlSource - - - src/fifo/bram_dp.vhd - vhdlSource - - - src/fifo/bram_simple_dp.vhd - vhdlSource - - - src/data_writer.vhd - vhdlSource - - - src/fifo/fifo.vhd - vhdlSource - - - src/synchronizer_n.vhd - vhdlSource - - - src/axis_signal_gen_v4.v - verilogSource - CHECKSUM_084788a4 - - - - xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset - - - - - - - - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - src/dds_compiler_0/dds_compiler_0.xci - xci - - - src/signal_gen.v - verilogSource - - - src/signal_gen_top.v - verilogSource - - - src/ctrl.sv - systemVerilogSource - - - src/axi_slv.vhd - vhdlSource - - - src/fifo/bram_dp.vhd - vhdlSource - - - src/fifo/bram_simple_dp.vhd - vhdlSource - - - src/data_writer.vhd - vhdlSource - - - src/fifo/fifo.vhd - vhdlSource - - - src/synchronizer_n.vhd - vhdlSource - - - src/axis_signal_gen_v4.v - verilogSource - - - - xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset - 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/home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 - - - - 2019.1 - - - - - - - - - diff --git a/qick/firmware/ip/axis_signal_gen_v4/src/axi_mst_0/axi_mst_0.veo b/qick/firmware/ip/axis_signal_gen_v4/src/axi_mst_0/axi_mst_0.veo deleted file mode 100644 index 5f33135..0000000 --- a/qick/firmware/ip/axis_signal_gen_v4/src/axi_mst_0/axi_mst_0.veo +++ /dev/null @@ -1,85 +0,0 @@ -// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -// IP VLNV: xilinx.com:ip:axi_vip:1.1 -// IP Revision: 5 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -axi_mst_0 your_instance_name ( - .aclk(aclk), // input wire aclk - .aresetn(aresetn), // input wire aresetn - .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr - .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot - .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid - .m_axi_awready(m_axi_awready), // input wire m_axi_awready - .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata - .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb - .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid - .m_axi_wready(m_axi_wready), // input wire m_axi_wready - .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp - .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid - .m_axi_bready(m_axi_bready), // output wire m_axi_bready - .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr - .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot - .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid - .m_axi_arready(m_axi_arready), // input wire m_axi_arready - .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata - .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp - .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid - .m_axi_rready(m_axi_rready) // output wire m_axi_rready -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file axi_mst_0.v when simulating -// the core, axi_mst_0. When compiling the wrapper file, be sure to -// reference the Verilog simulation library. - diff --git a/qick/firmware/ip/axis_signal_gen_v4/src/axi_mst_0/axi_mst_0.vho b/qick/firmware/ip/axis_signal_gen_v4/src/axi_mst_0/axi_mst_0.vho deleted file mode 100644 index 5c4d9a9..0000000 --- a/qick/firmware/ip/axis_signal_gen_v4/src/axi_mst_0/axi_mst_0.vho +++ /dev/null @@ -1,115 +0,0 @@ --- (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:axi_vip:1.1 --- IP Revision: 5 - --- The following code must appear in the VHDL architecture header. - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT axi_mst_0 - PORT ( - aclk : IN STD_LOGIC; - aresetn : IN STD_LOGIC; - m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - m_axi_awvalid : OUT STD_LOGIC; - m_axi_awready : IN STD_LOGIC; - m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - m_axi_wvalid : OUT STD_LOGIC; - m_axi_wready : IN STD_LOGIC; - m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - m_axi_bvalid : IN STD_LOGIC; - m_axi_bready : OUT STD_LOGIC; - m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - m_axi_arvalid : OUT STD_LOGIC; - m_axi_arready : IN STD_LOGIC; - m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - m_axi_rvalid : IN STD_LOGIC; - m_axi_rready : OUT STD_LOGIC - ); -END COMPONENT; --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : axi_mst_0 - PORT MAP ( - aclk => aclk, - aresetn => aresetn, - m_axi_awaddr => m_axi_awaddr, - m_axi_awprot => m_axi_awprot, - m_axi_awvalid => m_axi_awvalid, - m_axi_awready => m_axi_awready, - m_axi_wdata => m_axi_wdata, - m_axi_wstrb => m_axi_wstrb, - m_axi_wvalid => m_axi_wvalid, - m_axi_wready => m_axi_wready, - m_axi_bresp => m_axi_bresp, - m_axi_bvalid => m_axi_bvalid, - m_axi_bready => m_axi_bready, - m_axi_araddr => m_axi_araddr, - m_axi_arprot => m_axi_arprot, - m_axi_arvalid => m_axi_arvalid, - m_axi_arready => m_axi_arready, - m_axi_rdata => m_axi_rdata, - m_axi_rresp => m_axi_rresp, - m_axi_rvalid => m_axi_rvalid, - m_axi_rready => m_axi_rready - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file axi_mst_0.vhd when simulating --- the core, axi_mst_0. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/qick/firmware/ip/axis_signal_gen_v4/src/axi_mst_0/axi_mst_0.xci b/qick/firmware/ip/axis_signal_gen_v4/src/axi_mst_0/axi_mst_0.xci deleted file mode 100644 index 34f0b12..0000000 --- a/qick/firmware/ip/axis_signal_gen_v4/src/axi_mst_0/axi_mst_0.xci +++ /dev/null @@ -1,187 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - axi_mst_0 - - - ACTIVE_LOW - - 100000000 - 0 - 0.000 - 32 - 0 - 0 - 0 - - 32 - 100000000 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 32 - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 0 - 2 - 32 - 0 - 0 - 0 - 32 - 0 - 0 - 32 - 0 - 0 - 0 - axi_mst_0 - 32 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 0 - 0 - 1 - 0 - MASTER - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - virtex7 - - - xc7vx485t - ffg1157 - VERILOG - - MIXED - -1 - - - TRUE - TRUE - IP_Flow - 5 - TRUE - . - - . - 2019.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/qick/firmware/ip/axis_signal_gen_v4/src/axi_mst_0/axi_mst_0.xml b/qick/firmware/ip/axis_signal_gen_v4/src/axi_mst_0/axi_mst_0.xml deleted file mode 100644 index 0a20e0d..0000000 --- a/qick/firmware/ip/axis_signal_gen_v4/src/axi_mst_0/axi_mst_0.xml +++ /dev/null @@ -1,4751 +0,0 @@ - - - xilinx.com - customized_ip - axi_mst_0 - 1.0 - - - M_AXI - - - - - - - - - ARADDR - - - m_axi_araddr - - - - - ARBURST - - - m_axi_arburst - - - - - ARCACHE - - - m_axi_arcache - - - - - ARID - - - m_axi_arid - - - - - ARLEN - - - m_axi_arlen - - - - - ARLOCK - - - m_axi_arlock - - - - - ARPROT - - - m_axi_arprot - - - - - ARQOS - - - m_axi_arqos - - - - - ARREADY - - - m_axi_arready - - - - - ARREGION - - - m_axi_arregion - - - - - ARSIZE - - - m_axi_arsize - - - - - ARUSER - - - m_axi_aruser - - - - - ARVALID - - - m_axi_arvalid - - - - - AWADDR - - - m_axi_awaddr - - - - - AWBURST - - - m_axi_awburst - - - - - AWCACHE - - - m_axi_awcache - - - - - AWID - - - m_axi_awid - - - - - AWLEN - - - m_axi_awlen - - - - - AWLOCK - - - m_axi_awlock - - - - - AWPROT - - - m_axi_awprot - - - - - AWQOS - - - m_axi_awqos - - - - - AWREADY - - - m_axi_awready - - - - - AWREGION - - - m_axi_awregion - - - - - AWSIZE - - - m_axi_awsize - - - - - AWUSER - - - m_axi_awuser - - - - - AWVALID - - - m_axi_awvalid - - - - - BID - - - m_axi_bid - - - - - BREADY - - - m_axi_bready - - - - - BRESP - - - m_axi_bresp - - - - - BUSER - - - m_axi_buser - - - - - BVALID - - - m_axi_bvalid - - - - - RDATA - - - m_axi_rdata - - - - - RID - - - m_axi_rid - - - - - RLAST - - - m_axi_rlast - - - - - RREADY - - - m_axi_rready - - - - - RRESP - - - m_axi_rresp - - - - - RUSER - - - m_axi_ruser - - - - - RVALID - - - m_axi_rvalid - - - - - WDATA - - - m_axi_wdata - - - - - WID - - - m_axi_wid - - - - - WLAST - - - m_axi_wlast - - - - - WREADY - - - m_axi_wready - - - - - WSTRB - - - m_axi_wstrb - - - - - WUSER - - - m_axi_wuser - - - - - WVALID - - - m_axi_wvalid - - - - - - DATA_WIDTH - 32 - - - simulation.tlm - - - - - PROTOCOL - AXI4LITE - - - simulation.tlm - - - - - FREQ_HZ - 100000000 - - - simulation.tlm - - - - - ID_WIDTH - 0 - - - simulation.tlm - - - - - ADDR_WIDTH - 32 - - - simulation.tlm - - - - - AWUSER_WIDTH - 0 - - - simulation.tlm - - - - - ARUSER_WIDTH - 0 - - - simulation.tlm - - - - - WUSER_WIDTH - 0 - - - simulation.tlm - - - - - RUSER_WIDTH - 0 - - - simulation.tlm - - - - - BUSER_WIDTH - 0 - - - simulation.tlm - - - - - READ_WRITE_MODE - READ_WRITE - - - simulation.tlm - - - - - HAS_BURST - 0 - - - simulation.tlm - - - - - HAS_LOCK - 0 - - - simulation.tlm - - - - - HAS_PROT - 1 - - - simulation.tlm - - - - - HAS_CACHE - 0 - - - simulation.tlm - - - - - HAS_QOS - 0 - - - simulation.tlm - - - - - HAS_REGION - 0 - - - simulation.tlm - - - - - HAS_WSTRB - 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- - tlm - - - name - rd_socket - - - - - - - 1 - - - - - - - C_AXI_PROTOCOL - 2 - - - C_AXI_INTERFACE_MODE - 0 - - - C_AXI_ADDR_WIDTH - 32 - - - C_AXI_WDATA_WIDTH - 32 - - - C_AXI_RDATA_WIDTH - 32 - - - C_AXI_WID_WIDTH - 0 - - - C_AXI_RID_WIDTH - 0 - - - C_AXI_AWUSER_WIDTH - 0 - - - C_AXI_ARUSER_WIDTH - 0 - - - C_AXI_WUSER_WIDTH - 0 - - - C_AXI_RUSER_WIDTH - 0 - - - C_AXI_BUSER_WIDTH - 0 - - - C_AXI_SUPPORTS_NARROW - 0 - - - C_AXI_HAS_BURST - 0 - - - C_AXI_HAS_LOCK - 0 - - - C_AXI_HAS_CACHE - 0 - - - C_AXI_HAS_REGION - 0 - - - C_AXI_HAS_PROT - 1 - - - C_AXI_HAS_QOS - 0 - - - C_AXI_HAS_WSTRB - 1 - - - C_AXI_HAS_BRESP - 1 - - - C_AXI_HAS_RRESP - 1 - - - C_AXI_HAS_ARESETN - 1 - - - - - - choice_list_04fafd91 - AXI3 - AXI4 - AXI4LITE - - - choice_list_6240decd - READ_ONLY - READ_WRITE - WRITE_ONLY - - - choice_list_642e7122 - MASTER - PASS_THROUGH - SLAVE - - - choice_list_99ba8646 - 32 - 64 - - - choice_list_9d8b0d81 - ACTIVE_HIGH - ACTIVE_LOW - - - choice_pairs_0fc128e8 - 0 - 0 - - - - - xilinx_veriloginstantiationtemplate_view_fileset - - axi_mst_0.vho - vhdlTemplate - - - axi_mst_0.veo - verilogTemplate - - - - xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset - - hdl/axi_infrastructure_v1_1_0.vh - verilogSource - true - axi_infrastructure_v1_1_0 - - - hdl/axi_infrastructure_v1_1_vl_rfs.v - verilogSource - axi_infrastructure_v1_1_0 - - - - - - - - - - - xilinx_verilogsynthesis_view_fileset - - hdl/axi_vip_v1_1_vlsyn_rfs.sv - systemVerilogSource - axi_vip_v1_1_5 - - - - xilinx_synthesisconstraints_view_fileset - - axi_mst_0_ooc.xdc - xdc - USED_IN_implementation - USED_IN_out_of_context - USED_IN_synthesis - - - - xilinx_verilogsynthesiswrapper_view_fileset - - synth/axi_mst_0.sv - systemVerilogSource - xil_defaultlib - - - - xilinx_versioninformation_view_fileset - - doc/axi_vip_v1_1_changelog.txt - text - axi_vip_v1_1_5 - - - - xilinx_externalfiles_view_fileset - - axi_mst_0.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - axi_mst_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - axi_mst_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - axi_mst_0_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - axi_mst_0_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - - xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset - - hdl/axi_infrastructure_v1_1_0.vh - verilogSource - USED_IN_ipstatic - true - axi_infrastructure_v1_1_0 - - - hdl/axi_infrastructure_v1_1_vl_rfs.v - verilogSource - USED_IN_ipstatic - axi_infrastructure_v1_1_0 - - - - - - - - - - - xilinx_verilogbehavioralsimulation_view_fileset - - sim/axi_mst_0_pkg.sv - systemVerilogSource - - - hdl/axi_vip_v1_1_vl_rfs.sv - systemVerilogSource - USED_IN_ipstatic - axi_vip_v1_1_5 - - - - xilinx_systemcsimulation_view_fileset - - sysc/axi_vip.cpp - systemCSource - axi_vip_v1_1_5 - - - sysc/axi_vip.h - systemCSource - true - axi_vip_v1_1_5 - - - - xilinx_verilogsimulationwrapper_view_fileset - - sim/axi_mst_0.sv - systemVerilogSource - xil_defaultlib - - - - xilinx_systemcsimulationwrapper_view_fileset - - sim/axi_mst_0_sc.h - systemCSource - true - - - sim/axi_mst_0_sc.cpp - systemCSource - - - sim/axi_mst_0.h - systemCSource - true - - - sim/axi_mst_0.cpp - systemCSource - - - sim/axi_mst_0_stub.sv - systemVerilogSource - - - - The AXI Verification IP. - - - Component_Name - Component Name - axi_mst_0 - - - PROTOCOL - PROTOCOL - AXI4LITE - - - READ_WRITE_MODE - READ_WRITE MODE - READ_WRITE - - - INTERFACE_MODE - INTERFACE MODE - MASTER - - - ADDR_WIDTH - ADDRESS WIDTH - 32 - - - DATA_WIDTH - DATA WIDTH - 32 - - - ID_WIDTH - ID WIDTH - 0 - - - - false - - - - - - AWUSER_WIDTH - AWUSER WIDTH - 0 - - - - false - - - - - - ARUSER_WIDTH - ARUSER WIDTH - 0 - - - - false - - - - - - RUSER_WIDTH - RUSER WIDTH - 0 - - - - false - - - - - - WUSER_WIDTH - WUSER WIDTH - 0 - - - - false - - - - - - BUSER_WIDTH - BUSER WIDTH - 0 - - - - false - - - - - - WUSER_BITS_PER_BYTE - WUSER BITS PER BYTE - 0 - - - - false - - - - - - RUSER_BITS_PER_BYTE - RUSER BITS PER BYTE - 0 - - - - false - - - - - - HAS_USER_BITS_PER_BYTE - HAS USER_BITS_PER_BYTE - 0 - - - - false - - - - - - SUPPORTS_NARROW - SUPPORTS NARROW - 0 - - - - false - - - - - - HAS_SIZE - HAS SIZE - 0 - - - - false - - - - - - HAS_BURST - HAS BURST - 0 - - - - false - - - - - - HAS_LOCK - HAS LOCK - 0 - - - - false - - - - - - HAS_CACHE - HAS CACHE - 0 - - - - false - - - - - - HAS_REGION - HAS REGION - 0 - - - - false - - - - - - HAS_QOS - HAS QOS - 0 - - - - false - - - - - - HAS_PROT - HAS PROT - 1 - - - HAS_WSTRB - HAS WSTRB - 1 - - - HAS_BRESP - HAS BRESP - 1 - - - HAS_RRESP - HAS RRESP - 1 - - - HAS_ACLKEN - HAS ACLKEN - 0 - - - HAS_ARESETN - HAS ARESETN - 1 - - - - - AXI Verification IP - - xtlm - - 5 - true - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2019.1 - - - - - - - - - - diff --git a/qick/firmware/ip/axis_signal_gen_v4/src/axi_slv.vhd b/qick/firmware/ip/axis_signal_gen_v4/src/axi_slv.vhd deleted file mode 100644 index f1fb775..0000000 --- a/qick/firmware/ip/axis_signal_gen_v4/src/axi_slv.vhd +++ /dev/null @@ -1,522 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity axi_slv is - Generic - ( - DATA_WIDTH : integer := 32; - ADDR_WIDTH : integer := 6 - ); - Port - ( - aclk : in std_logic; - aresetn : in std_logic; - - -- Write Address Channel. - awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); - awprot : in std_logic_vector(2 downto 0); - awvalid : in std_logic; - awready : out std_logic; - - -- Write Data Channel. - wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); - wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); - wvalid : in std_logic; - wready : out std_logic; - - -- Write Response Channel. - bresp : out std_logic_vector(1 downto 0); - bvalid : out std_logic; - bready : in std_logic; - - -- Read Address Channel. - araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); - arprot : in std_logic_vector(2 downto 0); - arvalid : in std_logic; - arready : out std_logic; - - -- Read Data Channel. - rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); - rresp : out std_logic_vector(1 downto 0); - rvalid : out std_logic; - rready : in std_logic; - - -- Registers. - START_ADDR_REG : out std_logic_vector (31 downto 0); - WE_REG : out std_logic; - RNDQ_REG : out std_logic_vector (31 downto 0); - OUTSEL_REG : out std_logic - ); -end axi_slv; - -architecture rtl of axi_slv is - - -- AXI4LITE signals - signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); - signal axi_awready : std_logic; - signal axi_wready : std_logic; - signal axi_bresp : std_logic_vector(1 downto 0); - signal axi_bvalid : std_logic; - signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); - signal axi_arready : std_logic; - signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); - signal axi_rresp : std_logic_vector(1 downto 0); - signal axi_rvalid : std_logic; - - -- Example-specific design signals - -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH - -- ADDR_LSB is used for addressing 32/64 bit registers/memories - -- ADDR_LSB = 2 for 32 bits (n downto 2) - -- ADDR_LSB = 3 for 64 bits (n downto 3) - constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; - constant OPT_MEM_ADDR_BITS : integer := 3; - ------------------------------------------------ - ---- Signals for user logic register space example - -------------------------------------------------- - ---- Number of Slave Registers 16 - signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg_rden : std_logic; - signal slv_reg_wren : std_logic; - signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); - signal byte_index : integer; - signal aw_en : std_logic; - -begin - -- I/O Connections assignments - - awreadY <= axi_awready; - wready <= axi_wready; - bresp <= axi_bresp; - bvalid <= axi_bvalid; - arreadY <= axi_arready; - rdata <= axi_rdata; - rresp <= axi_rresp; - rvalid <= axi_rvalid; - -- Implement axi_awready generation - -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is - -- de-asserted when reset is low. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_awready <= '0'; - aw_en <= '1'; - else - if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then - -- slave is ready to accept write address when - -- there is a valid write address and write data - -- on the write address and data bus. This design - -- expects no outstanding transactions. - axi_awready <= '1'; - aw_en <= '0'; - elsif (bready = '1' and axi_bvalid = '1') then - aw_en <= '1'; - axi_awready <= '0'; - else - axi_awready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement axi_awaddr latching - -- This process is used to latch the address when both - -- S_AXI_AWVALID and S_AXI_WVALID are valid. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_awaddr <= (others => '0'); - else - if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then - -- Write Address latching - axi_awaddr <= awaddr; - end if; - end if; - end if; - end process; - - -- Implement axi_wready generation - -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is - -- de-asserted when reset is low. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_wready <= '0'; - else - if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then - -- slave is ready to accept write data when - -- there is a valid write address and write data - -- on the write address and data bus. This design - -- expects no outstanding transactions. - axi_wready <= '1'; - else - axi_wready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement memory mapped register select and write logic generation - -- The write data is accepted and written to memory mapped registers when - -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to - -- select byte enables of slave registers while writing. - -- These registers are cleared when reset (active low) is applied. - -- Slave register write enable is asserted when valid address and data are available - -- and the slave is ready to accept the write address and write data. - slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; - - process (aclk) - variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); - begin - if rising_edge(aclk) then - if aresetn = '0' then - slv_reg0 <= (others => '0'); - slv_reg1 <= (others => '0'); - slv_reg2 <= (others => '0'); - slv_reg3 <= (others => '0'); - slv_reg4 <= (others => '0'); - slv_reg5 <= (others => '0'); - slv_reg6 <= (others => '0'); - slv_reg7 <= (others => '0'); - slv_reg8 <= (others => '0'); - slv_reg9 <= (others => '0'); - slv_reg10 <= (others => '0'); - slv_reg11 <= (others => '0'); - slv_reg12 <= (others => '0'); - slv_reg13 <= (others => '0'); - slv_reg14 <= (others => '0'); - slv_reg15 <= (others => '0'); - else - loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); - if (slv_reg_wren = '1') then - case loc_addr is - when b"0000" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 0 - slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0001" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 1 - slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0010" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 2 - slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0011" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 3 - slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0100" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 4 - slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0101" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 5 - slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0110" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 6 - slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0111" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 7 - slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1000" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 8 - slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1001" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 9 - slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1010" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 10 - slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1011" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 11 - slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1100" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 12 - slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1101" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 13 - slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1110" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 14 - slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1111" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 15 - slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when others => - slv_reg0 <= slv_reg0; - slv_reg1 <= slv_reg1; - slv_reg2 <= slv_reg2; - slv_reg3 <= slv_reg3; - slv_reg4 <= slv_reg4; - slv_reg5 <= slv_reg5; - slv_reg6 <= slv_reg6; - slv_reg7 <= slv_reg7; - slv_reg8 <= slv_reg8; - slv_reg9 <= slv_reg9; - slv_reg10 <= slv_reg10; - slv_reg11 <= slv_reg11; - slv_reg12 <= slv_reg12; - slv_reg13 <= slv_reg13; - slv_reg14 <= slv_reg14; - slv_reg15 <= slv_reg15; - end case; - end if; - end if; - end if; - end process; - - -- Implement write response logic generation - -- The write response and response valid signals are asserted by the slave - -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. - -- This marks the acceptance of address and indicates the status of - -- write transaction. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_bvalid <= '0'; - axi_bresp <= "00"; --need to work more on the responses - else - if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then - axi_bvalid <= '1'; - axi_bresp <= "00"; - elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) - axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) - end if; - end if; - end if; - end process; - - -- Implement axi_arready generation - -- axi_arready is asserted for one S_AXI_ACLK clock cycle when - -- S_AXI_ARVALID is asserted. axi_awready is - -- de-asserted when reset (active low) is asserted. - -- The read address is also latched when S_AXI_ARVALID is - -- asserted. axi_araddr is reset to zero on reset assertion. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_arready <= '0'; - axi_araddr <= (others => '1'); - else - if (axi_arready = '0' and arvalid = '1') then - -- indicates that the slave has acceped the valid read address - axi_arready <= '1'; - -- Read Address latching - axi_araddr <= araddr; - else - axi_arready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement axi_arvalid generation - -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_ARVALID and axi_arready are asserted. The slave registers - -- data are available on the axi_rdata bus at this instance. The - -- assertion of axi_rvalid marks the validity of read data on the - -- bus and axi_rresp indicates the status of read transaction.axi_rvalid - -- is deasserted on reset (active low). axi_rresp and axi_rdata are - -- cleared to zero on reset (active low). - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_rvalid <= '0'; - axi_rresp <= "00"; - else - if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then - -- Valid read data is available at the read data bus - axi_rvalid <= '1'; - axi_rresp <= "00"; -- 'OKAY' response - elsif (axi_rvalid = '1' and rready = '1') then - -- Read data is accepted by the master - axi_rvalid <= '0'; - end if; - end if; - end if; - end process; - - -- Implement memory mapped register select and read logic generation - -- Slave register read enable is asserted when valid address is available - -- and the slave is ready to accept the read address. - slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; - - process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) - variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); - begin - -- Address decoding for reading registers - loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); - case loc_addr is - when b"0000" => - reg_data_out <= slv_reg0; - when b"0001" => - reg_data_out <= slv_reg1; - when b"0010" => - reg_data_out <= slv_reg2; - when b"0011" => - reg_data_out <= slv_reg3; - when b"0100" => - reg_data_out <= slv_reg4; - when b"0101" => - reg_data_out <= slv_reg5; - when b"0110" => - reg_data_out <= slv_reg6; - when b"0111" => - reg_data_out <= slv_reg7; - when b"1000" => - reg_data_out <= slv_reg8; - when b"1001" => - reg_data_out <= slv_reg9; - when b"1010" => - reg_data_out <= slv_reg10; - when b"1011" => - reg_data_out <= slv_reg11; - when b"1100" => - reg_data_out <= slv_reg12; - when b"1101" => - reg_data_out <= slv_reg13; - when b"1110" => - reg_data_out <= slv_reg14; - when b"1111" => - reg_data_out <= slv_reg15; - when others => - reg_data_out <= (others => '0'); - end case; - end process; - - -- Output register or memory read data - process( aclk ) is - begin - if (rising_edge (aclk)) then - if ( aresetn = '0' ) then - axi_rdata <= (others => '0'); - else - if (slv_reg_rden = '1') then - -- When there is a valid read address (S_AXI_ARVALID) with - -- acceptance of read address by the slave (axi_arready), - -- output the read dada - -- Read address mux - axi_rdata <= reg_data_out; -- register read data - end if; - end if; - end if; - end process; - - -- Register Map. - -- 0 : START_ADDR_REG : 32-bit. Start address to write into memory. - -- 1 : WE_REG : 1-bit. Enable write into memory. - -- 2 : RNDQ_REG : 32-bit. Noise amplitude for dithering. - -- 3 : OUTSEL_REG : 1-bit. Select real/imaginary output from block. - - -- Output Registers. - START_ADDR_REG <= slv_reg0; - WE_REG <= slv_reg1(0); - RNDQ_REG <= slv_reg2; - OUTSEL_REG <= slv_reg3(0); - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v4/src/axis_signal_gen_v4.v b/qick/firmware/ip/axis_signal_gen_v4/src/axis_signal_gen_v4.v deleted file mode 100644 index 080beb3..0000000 --- a/qick/firmware/ip/axis_signal_gen_v4/src/axis_signal_gen_v4.v +++ /dev/null @@ -1,204 +0,0 @@ -// Signal Generator V4. -// s_axi_aclk : clock for s_axi_* -// s0_axis_aclk : clock for s0_axis_* -// aclk : clock for s1_axis_* and m_axis_* -// -module axis_signal_gen_v4 - ( - // AXI Slave I/F for configuration. - s_axi_aclk , - s_axi_aresetn , - - s_axi_awaddr , - s_axi_awprot , - s_axi_awvalid , - s_axi_awready , - - s_axi_wdata , - s_axi_wstrb , - s_axi_wvalid , - s_axi_wready , - - s_axi_bresp , - s_axi_bvalid , - s_axi_bready , - - s_axi_araddr , - s_axi_arprot , - s_axi_arvalid , - s_axi_arready , - - s_axi_rdata , - s_axi_rresp , - s_axi_rvalid , - s_axi_rready , - - // AXIS Slave to load memory samples. - s0_axis_aclk , - s0_axis_aresetn , - s0_axis_tdata , - s0_axis_tvalid , - s0_axis_tready , - - // s1_* and m_* reset/clock. - aclk , - aresetn , - - // AXIS Slave to queue waveforms. - s1_axis_tdata , - s1_axis_tvalid , - s1_axis_tready , - - // AXIS Master for output. - m_axis_tready , - m_axis_tvalid , - m_axis_tdata - ); - -/**************/ -/* Parameters */ -/**************/ -parameter N = 12; - -// Number of parallel dds blocks. -parameter [31:0] N_DDS = 16; - -/*********/ -/* Ports */ -/*********/ -input s_axi_aclk; -input s_axi_aresetn; - -input [5:0] s_axi_awaddr; -input [2:0] s_axi_awprot; -input s_axi_awvalid; -output s_axi_awready; - -input [31:0] s_axi_wdata; -input [3:0] s_axi_wstrb; -input s_axi_wvalid; -output s_axi_wready; - -output [1:0] s_axi_bresp; -output s_axi_bvalid; -input s_axi_bready; - -input [5:0] s_axi_araddr; -input [2:0] s_axi_arprot; -input s_axi_arvalid; -output s_axi_arready; - -output [31:0] s_axi_rdata; -output [1:0] s_axi_rresp; -output s_axi_rvalid; -input s_axi_rready; - -input s0_axis_aclk; -input s0_axis_aresetn; -input [31:0] s0_axis_tdata; -input s0_axis_tvalid; -output s0_axis_tready; - -input aresetn; -input aclk; - -input [159:0] s1_axis_tdata; -input s1_axis_tvalid; -output s1_axis_tready; - -input m_axis_tready; -output m_axis_tvalid; -output [N_DDS*16-1:0] m_axis_tdata; - -/********************/ -/* Internal signals */ -/********************/ -// Registers. -wire [31:0] START_ADDR_REG; -wire WE_REG; -wire [31:0] RNDQ_REG; -wire OUTSEL_REG; - - -/**********************/ -/* Begin Architecture */ -/**********************/ -// AXI Slave. -axi_slv axi_slv_i - ( - .aclk (s_axi_aclk ), - .aresetn (s_axi_aresetn ), - - // Write Address Channel. - .awaddr (s_axi_awaddr ), - .awprot (s_axi_awprot ), - .awvalid (s_axi_awvalid ), - .awready (s_axi_awready ), - - // Write Data Channel. - .wdata (s_axi_wdata ), - .wstrb (s_axi_wstrb ), - .wvalid (s_axi_wvalid ), - .wready (s_axi_wready ), - - // Write Response Channel. - .bresp (s_axi_bresp ), - .bvalid (s_axi_bvalid ), - .bready (s_axi_bready ), - - // Read Address Channel. - .araddr (s_axi_araddr ), - .arprot (s_axi_arprot ), - .arvalid (s_axi_arvalid ), - .arready (s_axi_arready ), - - // Read Data Channel. - .rdata (s_axi_rdata ), - .rresp (s_axi_rresp ), - .rvalid (s_axi_rvalid ), - .rready (s_axi_rready ), - - // Registers. - .START_ADDR_REG (START_ADDR_REG ), - .WE_REG (WE_REG ), - .RNDQ_REG (RNDQ_REG ), - .OUTSEL_REG (OUTSEL_REG ) - ); - -signal_gen_top - #( - .N (N ), - .N_DDS (N_DDS ) - ) - signal_gen_top_i - ( - // Reset and clock. - .aresetn (aresetn ), - .aclk (aclk ), - - // AXIS Slave to load memory samples. - .s0_axis_aresetn (s0_axis_aresetn ), - .s0_axis_aclk (s0_axis_aclk ), - .s0_axis_tdata_i (s0_axis_tdata ), - .s0_axis_tvalid_i (s0_axis_tvalid ), - .s0_axis_tready_o (s0_axis_tready ), - - // AXIS Slave to queue waveforms. - .s1_axis_tdata_i (s1_axis_tdata ), - .s1_axis_tvalid_i (s1_axis_tvalid ), - .s1_axis_tready_o (s1_axis_tready ), - - // M_AXIS for output. - .m_axis_tready_i (m_axis_tready ), - .m_axis_tvalid_o (m_axis_tvalid ), - .m_axis_tdata_o (m_axis_tdata ), - - // Registers. - .START_ADDR_REG (START_ADDR_REG ), - .WE_REG (WE_REG ), - .RNDQ_REG (RNDQ_REG ), - .OUTSEL_REG (OUTSEL_REG ) - ); - -endmodule - diff --git a/qick/firmware/ip/axis_signal_gen_v4/src/bram.v b/qick/firmware/ip/axis_signal_gen_v4/src/bram.v deleted file mode 100644 index 018317e..0000000 --- a/qick/firmware/ip/axis_signal_gen_v4/src/bram.v +++ /dev/null @@ -1,33 +0,0 @@ -module bram (clk,ena,wea,addra,dia,doa); - -// Memory address size. -parameter N = 16; -// Data width. -parameter B = 16; - -input clk; -input ena; -input wea; -input [N-1:0] addra; -input [B-1:0] dia; -output [B-1:0] doa; - -// Ram type. -reg [B-1:0] RAM [0:2**N-1]; -reg [B-1:0] doa; - -always @(posedge clk) -begin - if (ena) - begin - if (wea) begin - RAM[addra] <= dia; - end - else begin - doa <= RAM[addra]; - end - end -end - -endmodule - diff --git a/qick/firmware/ip/axis_signal_gen_v4/src/ctrl.sv b/qick/firmware/ip/axis_signal_gen_v4/src/ctrl.sv deleted file mode 100644 index dbc81a3..0000000 --- a/qick/firmware/ip/axis_signal_gen_v4/src/ctrl.sv +++ /dev/null @@ -1,406 +0,0 @@ -//Format of waveform interface: -// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| -// | 159 .. 149 | 148 | 147 | 146 | 145 .. 144 | 143 .. 128 | 127 .. 112 | 111 .. 96 | 95 .. 80 | 79 .. 64 | 63 .. 32 | 31 .. 0 | -// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| -// | xxxx | phrst | stdysel | mode | outsel | nsamp | xxxx | gain | xxxx | addr | phase | freq | -// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| -// freq : 32 bits -// phase : 32 bits -// addr : 16 bits -// gain : 16 bits -// nsamp : 16 bits -// outsel : 2 bits -// mode : 1 bit -// stdysel : 1 bit -// phrst : 1 bit -module ctrl ( - // Reset and clock. - rstn , - clk , - - // Fifo interface. - fifo_rd_en_o , - fifo_empty_i , - fifo_dout_i , - - // dds control. - dds_ctrl_o , - - // memory control. - mem_addr_o , - - // gain. - gain_o , - - // Output source selection. - src_o , - - // Steady value selection. - stdy_o , - - // Output enable. - en_o ); - -// Memory address size. -parameter N = 16; - -// Number of parallel dds blocks. -parameter [31:0] N_DDS = 16; - -// Ports. -input rstn; -input clk; -output fifo_rd_en_o; -input fifo_empty_i; -input [159:0] fifo_dout_i; -output [N_DDS*72-1:0] dds_ctrl_o; -output [N-1:0] mem_addr_o; -output [15:0] gain_o; -output [1:0] src_o; -output stdy_o; -output en_o; - -// States. -typedef enum { READ_ST , - CNT_ST - } state_t; - -// State register. -(* fsm_encoding = "one_hot" *) state_t state; - -// Fifo dout register. -reg [159:0] fifo_dout_r; - -// Non-stop counter for time calculation (adds N_DDS samples each clock tick). -reg [31:0] cnt_n; -reg [31:0] cnt_n_reg; - -// Pinc/phase. -wire [31:0] pinc_int; -reg [31:0] pinc_r1; -wire [31:0] pinc_N; -reg [31:0] pinc_N_r1; -reg [31:0] pinc_N_r2; -reg [31:0] pinc_N_r3; -wire [31:0] pinc_Nm; -reg [31:0] pinc_Nm_r1; - -wire [31:0] phase_int; -reg [31:0] phase_r1; -reg [31:0] phase_r2; -wire [31:0] phase_0; -reg [31:0] phase_0_r1; - -// Phase vectors. -wire [31:0] phase_v0 [0:N_DDS-1]; -reg [31:0] phase_v0_r1 [0:N_DDS-1]; -reg [31:0] phase_v0_r2 [0:N_DDS-1]; -wire [31:0] phase_v1 [0:N_DDS-1]; -reg [31:0] phase_v1_r1 [0:N_DDS-1]; - -// sync. -reg sync_reg; -reg sync_reg_r1; -reg sync_reg_r2; -reg sync_reg_r3; -reg sync_reg_r4; - -// Address. -wire [15:0] addr_int; -reg [15:0] addr_cnt; -reg [15:0] addr_cnt_r1; -reg [15:0] addr_cnt_r2; -reg [15:0] addr_cnt_r3; - -// Gain. -wire [15:0] gain_int; -reg [15:0] gain_r1; -reg [15:0] gain_r2; -reg [15:0] gain_r3; -reg [15:0] gain_r4; - -// Number of samples. -wire [15:0] nsamp_int; - -// Output selection. -wire [1:0] outsel_int; -reg [1:0] outsel_r1; -reg [1:0] outsel_r2; -reg [1:0] outsel_r3; -reg [1:0] outsel_r4; - -// Mode. -wire mode_int; - -// Steady value selection. -wire stdysel_int; -reg stdysel_r1; -reg stdysel_r2; -reg stdysel_r3; -reg stdysel_r4; - -// Load enable flag. -wire load_int; -reg load_r; - -// Fifo Read Enable. -reg rd_en_int; -reg rd_en_r1; -reg rd_en_r2; - -// Counter. -reg [31:0] cnt; - -// Output enable register. -reg en_reg; -reg en_reg_r1; -reg en_reg_r2; -reg en_reg_r3; -reg en_reg_r4; -reg en_reg_r5; - -// Registers. -always @(posedge clk) begin - if (~rstn) begin - // State register. - state <= READ_ST; - - // Fifo dout register. - fifo_dout_r <= 0; - - // Non-stop counter for time calculation. - cnt_n <= 0; - cnt_n_reg <= 0; - - // Pinc/phase/sync. - pinc_r1 <= 0; - pinc_N_r1 <= 0; - pinc_N_r2 <= 0; - pinc_N_r3 <= 0; - pinc_Nm_r1 <= 0; - - phase_r1 <= 0; - phase_r2 <= 0; - phase_0_r1 <= 0; - - sync_reg <= 0; - sync_reg_r1 <= 0; - sync_reg_r2 <= 0; - sync_reg_r3 <= 0; - sync_reg_r4 <= 0; - - // Address. - addr_cnt <= 0; - addr_cnt_r1 <= 0; - addr_cnt_r2 <= 0; - addr_cnt_r3 <= 0; - - // Gain. - gain_r1 <= 0; - gain_r2 <= 0; - gain_r3 <= 0; - gain_r4 <= 0; - - // Output selection. - outsel_r1 <= 0; - outsel_r2 <= 0; - outsel_r3 <= 0; - outsel_r4 <= 0; - - // Steady value selection. - stdysel_r1 <= 0; - stdysel_r2 <= 0; - stdysel_r3 <= 0; - stdysel_r4 <= 0; - - // Load enable flag. - load_r <= 0; - - // Fifo Read Enable. - rd_en_r1 <= 0; - rd_en_r2 <= 0; - - // Counter. - cnt <= 0; - - // Output enable register. - en_reg <= 0; - en_reg_r1 <= 0; - en_reg_r2 <= 0; - en_reg_r3 <= 0; - en_reg_r4 <= 0; - en_reg_r5 <= 0; - end - else begin - // State register. - case (state) - READ_ST: - if (mode_int || ~fifo_empty_i) - state <= CNT_ST; - CNT_ST: - if ( cnt == nsamp_int-2 ) - state <= READ_ST; - endcase - - // Fifo dout register. - if (load_r) - fifo_dout_r <= fifo_dout_i; - - // Non-stop counter for time calculation. - cnt_n <= cnt_n + N_DDS; - if (sync_reg) - cnt_n_reg <= cnt_n; - - // Pinc/phase/sync. - pinc_r1 <= pinc_int; - pinc_N_r1 <= pinc_N; - pinc_N_r2 <= pinc_N_r1; - pinc_N_r3 <= pinc_N_r2; - pinc_Nm_r1 <= pinc_Nm; - - phase_r1 <= phase_int; - phase_r2 <= phase_r1; - phase_0_r1 <= phase_0; - - sync_reg <= load_r; - sync_reg_r1 <= sync_reg; - sync_reg_r2 <= sync_reg_r1; - sync_reg_r3 <= sync_reg_r2; - sync_reg_r4 <= sync_reg_r3; - - // Address. - if (rd_en_r2) - addr_cnt <= addr_int; - else - addr_cnt <= addr_cnt + 1; - - addr_cnt_r1 <= addr_cnt; - addr_cnt_r2 <= addr_cnt_r1; - addr_cnt_r3 <= addr_cnt_r2; - - // Gain. - gain_r1 <= gain_int; - gain_r2 <= gain_r1; - gain_r3 <= gain_r2; - gain_r4 <= gain_r3; - - // Output selection. - outsel_r1 <= outsel_int; - outsel_r2 <= outsel_r1; - outsel_r3 <= outsel_r2; - outsel_r4 <= outsel_r3; - - // Steady value selection. - stdysel_r1 <= stdysel_int; - stdysel_r2 <= stdysel_r1; - stdysel_r3 <= stdysel_r2; - stdysel_r4 <= stdysel_r3; - - // Load enable flag. - load_r <= load_int; - - // Fifo Read Enable. - rd_en_r1 <= rd_en_int; - rd_en_r2 <= rd_en_r1; - - // Counter. - if (rd_en_int) - cnt <= 0; - else - cnt <= cnt + 1; - - // Output enable register. - if (~mode_int && rd_en_int) - if (~fifo_empty_i) - en_reg <= 1; - else - en_reg <= 0; - - en_reg_r1 <= en_reg; - en_reg_r2 <= en_reg_r1; - en_reg_r3 <= en_reg_r2; - en_reg_r4 <= en_reg_r3; - en_reg_r5 <= en_reg_r4; - - end -end - -// FSM outputs. -always_comb begin - // Default. - rd_en_int = 0; - - case (state) - READ_ST: - rd_en_int = 1; - - CNT_ST: - rd_en_int = 0; - endcase -end - -// Fifo output fields. -assign pinc_int = fifo_dout_r[31:0]; -assign phase_int = fifo_dout_r[63:32]; -assign addr_int = fifo_dout_r[79:64]; -assign gain_int = fifo_dout_r[111:96]; -assign nsamp_int = fifo_dout_r[143:128]; -assign outsel_int = fifo_dout_r[145:144]; -assign mode_int = fifo_dout_r[146]; -assign stdysel_int = fifo_dout_r[147]; - -// Frequency calculation. -assign pinc_N = pinc_r1*N_DDS; - -// Phase calculation. -assign pinc_Nm = pinc_r1*cnt_n_reg; -assign phase_0 = pinc_Nm_r1 + phase_r2; - -// Phase vectors. -generate -genvar i; - for (i=0; i < N_DDS; i = i + 1) begin : GEN_phase - // Registers. - always @(posedge clk) begin - if (~rstn) begin - // v0. - phase_v0_r1[i] <= 0; - phase_v0_r2[i] <= 0; - - // v1. - phase_v1_r1[i] <= 0; - end - else begin - // v0. - phase_v0_r1[i] <= phase_v0[i]; - phase_v0_r2[i] <= phase_v0_r1[i]; - - // v1. - phase_v1_r1[i] <= phase_v1[i]; - end - end - - // v0. - assign phase_v0[i] = pinc_r1*i; - - // v1. - assign phase_v1[i] = phase_v0_r2[i] + phase_0_r1; - - // dds_ctrl_o output. - assign dds_ctrl_o[i*72 +: 72] = {7'h00,sync_reg_r4,phase_v1_r1[i],pinc_N_r3}; - end -endgenerate - -// load_int. -assign load_int = rd_en_int & ~fifo_empty_i; - -// Assign outputs. -assign fifo_rd_en_o = rd_en_int; -assign mem_addr_o = addr_cnt_r3; -assign gain_o = gain_r4; -assign src_o = outsel_r4; -assign stdy_o = stdysel_r4; -assign en_o = en_reg_r5; - -endmodule - diff --git a/qick/firmware/ip/axis_signal_gen_v4/src/data_writer.vhd b/qick/firmware/ip/axis_signal_gen_v4/src/data_writer.vhd deleted file mode 100644 index cbf1912..0000000 --- a/qick/firmware/ip/axis_signal_gen_v4/src/data_writer.vhd +++ /dev/null @@ -1,226 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity data_writer is - Generic - ( - -- Number of tables. - NT : Integer := 16; - -- Address map of each table. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in STD_LOGIC; - clk : in STD_LOGIC; - - -- AXI Stream I/F. - s_axis_tready : out std_logic; - s_axis_tdata : in std_logic_vector(B-1 downto 0); - s_axis_tvalid : in std_logic; - - -- Memory I/F. - mem_en : out std_logic_vector (NT-1 downto 0); - mem_we : out std_logic; - mem_addr : out std_logic_vector (N-1 downto 0); - mem_di : out std_logic_vector (B-1 downto 0); - - -- Registers. - START_ADDR_REG : in std_logic_vector (31 downto 0); - WE_REG : in std_logic - ); -end data_writer; - -architecture rtl of data_writer is - --- Log2 of number of tables. -constant NT_LOG2 : Integer := Integer(ceil(log2(real(NT)))); - --- Synchronizer. -component synchronizer_n is - generic ( - N : Integer := 2 - ); - port ( - rstn : in std_logic; - clk : in std_logic; - data_in : in std_logic; - data_out : out std_logic - ); -end component; - --- State machine. -type fsm_state is ( INIT_ST , - READ_START_ADDR_ST , - WAIT_TVALID_ST , - RW_TDATA_ST ); -signal state : fsm_state; - -signal read_start_addr_state : std_logic; -signal rw_tdata_state : std_logic; - --- WE_REG_resync. -signal WE_REG_resync : std_logic; - --- Axis registers. -signal tready_i : std_logic; -signal tready_r : std_logic; -signal tdata_r : std_logic_vector(B-1 downto 0); -signal tdata_rr : std_logic_vector(B-1 downto 0); -signal tdata_rrr : std_logic_vector(B-1 downto 0); -signal tvalid_r : std_logic; -signal tvalid_rr : std_logic; -signal tvalid_rrr : std_logic; - --- Memory Enable. -signal mem_en_i : std_logic_vector (NT-1 downto 0); -signal mem_en_r : std_logic_vector (NT-1 downto 0); - --- Memory address space. -signal mem_addr_full : unsigned (NT_LOG2+N-1 downto 0); -signal mem_addr_low : unsigned (NT_LOG2-1 downto 0); -signal mem_addr_high : unsigned (N-1 downto 0); -signal mem_addr_high_r : unsigned (N-1 downto 0); - -begin - --- WE_REG_resync -WE_REG_resync_i : synchronizer_n - generic map ( - N => 2 - ) - port map ( - rstn => rstn , - clk => clk , - data_in => WE_REG , - data_out => WE_REG_resync - ); - --- Enable logic generation. -GEN: for I in 0 to NT-1 generate - - mem_en_i(I) <= '1' when mem_addr_low = to_unsigned(I,mem_addr_low'length) else - '0'; - -end generate GEN; - -process (clk) -begin - if ( rising_edge(clk) ) then - if (rstn = '0') then - -- Axis registers. - tready_r <= '0'; - tdata_r <= (others => '0'); - tdata_rr <= (others => '0'); - tdata_rrr <= (others => '0'); - tvalid_r <= '0'; - tvalid_rr <= '0'; - tvalid_rrr <= '0'; - - -- Memory address. - mem_addr_full <= (others => '0'); - mem_addr_high_r <= (others => '0'); - mem_en_r <= (others => '0'); - - else - -- Axis registers. - tready_r <= tready_i; - tdata_r <= s_axis_tdata; - tvalid_r <= s_axis_tvalid; - - -- Extra registers to account pipe of state machine. - tdata_rr <= tdata_r; - tdata_rrr <= tdata_rr; - tvalid_rr <= tvalid_r; - tvalid_rrr <= tvalid_rr; - - -- Memory address. - if ( read_start_addr_state = '1') then - mem_addr_full <= to_unsigned(to_integer(unsigned(START_ADDR_REG)),mem_addr_full'length); - elsif ( rw_tdata_state = '1' ) then - mem_addr_full <= mem_addr_full + 1; - end if; - mem_addr_high_r <= mem_addr_high; - mem_en_r <= mem_en_i; - - end if; - end if; -end process; - --- Address computation. -mem_addr_low <= mem_addr_full(NT_LOG2-1 downto 0); -mem_addr_high <= mem_addr_full(NT_LOG2+N-1 downto NT_LOG2); - --- Finite state machine. -process (clk) -begin - if ( rising_edge(clk) ) then - if ( rstn = '0' ) then - state <= INIT_ST; - else - case state is - when INIT_ST => - if ( WE_REG_resync = '1' ) then - state <= READ_START_ADDR_ST; - end if; - - when READ_START_ADDR_ST => - state <= WAIT_TVALID_ST; - - when WAIT_TVALID_ST => - if ( WE_REG_resync = '1') then - if ( tvalid_r = '0' ) then - state <= WAIT_TVALID_ST; - else - state <= RW_TDATA_ST; - end if; - else - state <= INIT_ST; - end if; - - when RW_TDATA_ST => - if ( tvalid_r = '0' ) then - state <= WAIT_TVALID_ST; - end if; - - end case; - end if; - end if; -end process; - --- Output logic. -process (state) -begin -read_start_addr_state <= '0'; -rw_tdata_state <= '0'; -tready_i <= '0'; - case state is - when INIT_ST => - - when READ_START_ADDR_ST => - read_start_addr_state <= '1'; - - when WAIT_TVALID_ST => - tready_i <= '1'; - - when RW_TDATA_ST => - rw_tdata_state <= '1'; - tready_i <= '1'; - - end case; -end process; - --- Assign output. -s_axis_tready <= tready_r; - -mem_en <= mem_en_r; -mem_we <= tvalid_rrr; -mem_addr <= std_logic_vector(mem_addr_high_r); -mem_di <= tdata_rrr; - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v4/src/dds_compiler_0/dds_compiler_0.veo b/qick/firmware/ip/axis_signal_gen_v4/src/dds_compiler_0/dds_compiler_0.veo deleted file mode 100644 index 894ecd6..0000000 --- a/qick/firmware/ip/axis_signal_gen_v4/src/dds_compiler_0/dds_compiler_0.veo +++ /dev/null @@ -1,69 +0,0 @@ -// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -// IP VLNV: xilinx.com:ip:dds_compiler:6.0 -// IP Revision: 18 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -dds_compiler_0 your_instance_name ( - .aclk(aclk), // input wire aclk - .s_axis_phase_tvalid(s_axis_phase_tvalid), // input wire s_axis_phase_tvalid - .s_axis_phase_tdata(s_axis_phase_tdata), // input wire [71 : 0] s_axis_phase_tdata - .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid - .m_axis_data_tdata(m_axis_data_tdata) // output wire [31 : 0] m_axis_data_tdata -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file dds_compiler_0.v when simulating -// the core, dds_compiler_0. When compiling the wrapper file, be sure to -// reference the Verilog simulation library. - diff --git a/qick/firmware/ip/axis_signal_gen_v4/src/dds_compiler_0/dds_compiler_0.vho b/qick/firmware/ip/axis_signal_gen_v4/src/dds_compiler_0/dds_compiler_0.vho deleted file mode 100644 index e65044c..0000000 --- a/qick/firmware/ip/axis_signal_gen_v4/src/dds_compiler_0/dds_compiler_0.vho +++ /dev/null @@ -1,83 +0,0 @@ --- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:dds_compiler:6.0 --- IP Revision: 18 - --- The following code must appear in the VHDL architecture header. - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT dds_compiler_0 - PORT ( - aclk : IN STD_LOGIC; - s_axis_phase_tvalid : IN STD_LOGIC; - s_axis_phase_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0); - m_axis_data_tvalid : OUT STD_LOGIC; - m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) - ); -END COMPONENT; --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : dds_compiler_0 - PORT MAP ( - aclk => aclk, - s_axis_phase_tvalid => s_axis_phase_tvalid, - s_axis_phase_tdata => s_axis_phase_tdata, - m_axis_data_tvalid => m_axis_data_tvalid, - m_axis_data_tdata => m_axis_data_tdata - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file dds_compiler_0.vhd when simulating --- the core, dds_compiler_0. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/qick/firmware/ip/axis_signal_gen_v4/src/dds_compiler_0/dds_compiler_0.xci b/qick/firmware/ip/axis_signal_gen_v4/src/dds_compiler_0/dds_compiler_0.xci deleted file mode 100644 index 47bc665..0000000 --- a/qick/firmware/ip/axis_signal_gen_v4/src/dds_compiler_0/dds_compiler_0.xci +++ /dev/null @@ -1,306 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - dds_compiler_0 - - - ACTIVE_LOW - - 100000000 - 0 - 0.000 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 9 - 0 - 0 - 0 - 32 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 1 - 0 - 1 - 0 - 1 - 0 - 0 - 8 - 1 - 0 - 9 - 0 - 32 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 2 - 0 - 16 - 14 - 3 - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - 3 - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - 0 - 1 - 0 - 1 - 0 - 72 - 1 - 1 - zynquplus - Full_Range - 1 - dds_compiler_0 - Not_Required - 256 - Maximal - 0.06 - Coregen - false - false - false - false - 8 - Configurable - Not_Required - Not_Required - Auto - Standard - 9 - false - false - Auto - Twos_Complement - Speed - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Sine_and_Cosine - 16 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - false - System_Parameters - Phase_Generator_and_SIN_COS_LUT - Streaming - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 32 - Streaming - true - On_Vector - Not_Required - 1 - 96 - false - 1 - zynquplusRFSOC - xilinx.com:zcu111:part0:1.1 - - xczu28dr - ffvg1517 - VERILOG - - MIXED - -2 - - E - TRUE - TRUE - IP_Flow - 18 - TRUE - . - - . - 2019.1 - GLOBAL - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/qick/firmware/ip/axis_signal_gen_v4/src/dds_compiler_0/dds_compiler_0.xml b/qick/firmware/ip/axis_signal_gen_v4/src/dds_compiler_0/dds_compiler_0.xml deleted file mode 100644 index 9395e93..0000000 --- a/qick/firmware/ip/axis_signal_gen_v4/src/dds_compiler_0/dds_compiler_0.xml +++ /dev/null @@ -1,3165 +0,0 @@ - - - xilinx.com - customized_ip - dds_compiler_0 - 1.0 - - - event_pinc_invalid_intf - - - - - - - INTERRUPT - - - event_pinc_invalid - - - - - - SENSITIVITY - EDGE_RISING - - - PortWidth - 1 - - - none - - - - - - - event_poff_invalid_intf - - - - - - - INTERRUPT - - - event_poff_invalid - - - - - - SENSITIVITY - EDGE_RISING - - - PortWidth - 1 - - - none - - - - - - - event_phase_in_invalid_intf - - - - - - - INTERRUPT - - - event_phase_in_invalid - - - - - - SENSITIVITY - EDGE_RISING - - - PortWidth - 1 - - - none - - - - - - - event_s_phase_tlast_missing_intf - - - - - - - INTERRUPT - - - event_s_phase_tlast_missing - - - - - - SENSITIVITY - EDGE_RISING - - - PortWidth - 1 - - - none - - - - - - - event_s_phase_tlast_unexpected_intf - - - - - - - INTERRUPT - - - event_s_phase_tlast_unexpected - - - - - - SENSITIVITY - EDGE_RISING - - - PortWidth - 1 - - - none - - - - - - - event_s_phase_chanid_incorrect_intf - - - - - - - INTERRUPT - - - event_s_phase_chanid_incorrect - - - - - - SENSITIVITY - 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zip - - - - xilinx_vhdltestbench_view_fileset - - demo_tb/tb_dds_compiler_0.vhd - vhdlSource - - - - xilinx_versioninformation_view_fileset - - doc/dds_compiler_v6_0_changelog.txt - text - - - - The Xilinx DDS Compiler LogiCORE provides Direct Digital Synthesizers (DDS) and optionally either Phase Generator or Sine/Cosine Lookup Table constituent parts as independent cores. The core features sine, cosine or quadrature outputs with 3 to 26-bit output sample precision. The core supports up to 16 channels by time-sharing the sine/cosine table which dramatically reduces the area requirement when multiple channels are needed. Phase Dithering and Taylor Series Correction options provide high dynamic range signals using minimal FPGA resources. In addition, the core has an optional phase offset capability, providing support for multiple synthesizers with precisely controlled phase differences. - - - Component_Name - Component Name - dds_compiler_0 - - - PartsPresent - Configuration Options - Phase_Generator_and_SIN_COS_LUT - - - DDS_Clock_Rate - System Clock - 256 - - - Channels - Number of Channels - 1 - - - Mode_of_Operation - Mode Of Operation - Standard - - - Modulus - Modulus - 9 - - - Parameter_Entry - Parameter Selection - System_Parameters - - - Spurious_Free_Dynamic_Range - Spurious Free Dynamic Range - 96 - - - Frequency_Resolution - Frequency Resolution - 0.06 - - - Noise_Shaping - Noise Shaping - Auto - - - Phase_Width - Phase Width - 32 - - - Output_Width - Output Width - 16 - - - Phase_Increment - Phase Increment - Streaming - - - Resync - Resync - true - - - Phase_offset - Phase Offset - Streaming - - - Output_Selection - Output Selection - Sine_and_Cosine - - - Negative_Sine - Negative Sine - false - - - Negative_Cosine - Negative Cosine - false - - - Amplitude_Mode - Amplitude Mode - Full_Range - - - Memory_Type - Memory Type - Auto - - - Optimization_Goal - Optimization Goal - Speed - - - DSP48_Use - DSP48 Use - Maximal - - - Has_Phase_Out - Has Phase Out - false - - - DATA_Has_TLAST - DATA Has TLAST - Not_Required - - - Has_TREADY - Output TREADY - false - - - S_PHASE_Has_TUSER - Input - Not_Required - - - S_PHASE_TUSER_Width - User Field Width - 1 - - - M_DATA_Has_TUSER - DATA Output - Not_Required - - - M_PHASE_Has_TUSER - PHASE Output - Not_Required - - - S_CONFIG_Sync_Mode - Synchronization Mode - On_Vector - - - OUTPUT_FORM - Output Form - Twos_Complement - - - Latency_Configuration - Configurable - - - Latency - 8 - - - Has_ARESETn - ARESETn (active low) - false - - - Has_ACLKEN - ACLKEN - false - - - Output_Frequency1 - 0 - - - PINC1 - 0 - - - Phase_Offset_Angles1 - 0 - - - POFF1 - 0 - - - Output_Frequency2 - 0 - - - PINC2 - 0 - - - Phase_Offset_Angles2 - 0 - - - POFF2 - 0 - - - Output_Frequency3 - 0 - - - PINC3 - 0 - - - Phase_Offset_Angles3 - 0 - - - POFF3 - 0 - - - Output_Frequency4 - 0 - - - PINC4 - 0 - - - Phase_Offset_Angles4 - 0 - - - POFF4 - 0 - - - Output_Frequency5 - 0 - - - PINC5 - 0 - - - Phase_Offset_Angles5 - 0 - - - POFF5 - 0 - - - Output_Frequency6 - 0 - - - PINC6 - 0 - - - Phase_Offset_Angles6 - 0 - - - POFF6 - 0 - - - Output_Frequency7 - 0 - - - PINC7 - 0 - - - Phase_Offset_Angles7 - 0 - - - POFF7 - 0 - - - Output_Frequency8 - 0 - - - PINC8 - 0 - - - Phase_Offset_Angles8 - 0 - - - POFF8 - 0 - - - Output_Frequency9 - 0 - - - PINC9 - 0 - - - Phase_Offset_Angles9 - 0 - - - POFF9 - 0 - - - Output_Frequency10 - 0 - - - PINC10 - 0 - - - Phase_Offset_Angles10 - 0 - - - POFF10 - 0 - - - Output_Frequency11 - 0 - - - PINC11 - 0 - - - Phase_Offset_Angles11 - 0 - - - POFF11 - 0 - - - Output_Frequency12 - 0 - - - PINC12 - 0 - - - Phase_Offset_Angles12 - 0 - - - POFF12 - 0 - - - Output_Frequency13 - 0 - - - PINC13 - 0 - - - Phase_Offset_Angles13 - 0 - - - POFF13 - 0 - - - Output_Frequency14 - 0 - - - PINC14 - 0 - - - Phase_Offset_Angles14 - 0 - - - POFF14 - 0 - - - Output_Frequency15 - 0 - - - PINC15 - 0 - - - Phase_Offset_Angles15 - 0 - - - POFF15 - 0 - - - Output_Frequency16 - 0 - - - PINC16 - 0 - - - Phase_Offset_Angles16 - 0 - - - POFF16 - 0 - - - POR_mode - POR Mode - false - - - GUI_Behaviour - Coregen - - - explicit_period - false - - - period - 1 - - - - - DDS Compiler - 18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2019.1 - - - - - - - - diff --git a/qick/firmware/ip/axis_signal_gen_v4/src/dither.v b/qick/firmware/ip/axis_signal_gen_v4/src/dither.v deleted file mode 100644 index fabedf4..0000000 --- a/qick/firmware/ip/axis_signal_gen_v4/src/dither.v +++ /dev/null @@ -1,80 +0,0 @@ -module dither - #( - parameter N = 8, // Bits of input. - parameter M = 6, // Bits of output. - parameter SEED = 0 // Random Number Generator. - ) - ( - input rstn , - input clk , - input [N-1:0] din , - output [M-1:0] dout , - - // Registers. - input [N-1:0] RNDQ_REG - ); - -// Random number. -wire signed [N-1:0] rnd_int; -wire signed [N-1:0] rnd_q; -reg signed [N:0] rnd_r1; -reg signed [N:0] rnd_r2; -reg signed [N:0] rnd_r3; -reg signed [N:0] rnd_r4; - -// Signal + Noise. -wire signed [N:0] x; -wire signed [N:0] y; -wire signed [N:0] q; -reg signed [M-1:0] q_r; - -// Random Number Generator. -random_gen - #( - .W (N ), - .SEED (SEED ) - ) - random_gen_i - ( - .rstn (rstn ), - .clk (clk ), - .dout (rnd_int ) - ); - -// Noise (divide to lower amplitude). -assign rnd_q = rnd_int >>> RNDQ_REG; - -// Signal + Noise. -assign x = {din[N-1],din}; -assign y = x + rnd_r4; -assign q = y >>> (N+1-M); - -// Registes. -always @(posedge clk) begin - if (~rstn) begin - // Random number. - rnd_r1 <= 0; - rnd_r2 <= 0; - rnd_r3 <= 0; - rnd_r4 <= 0; - - // Signal + Noise. - q_r <= 0; - end - else begin - // Random number. - rnd_r1 <= {rnd_q[N-1],rnd_q}; - rnd_r2 <= rnd_r1; - rnd_r3 <= rnd_r2; - rnd_r4 <= rnd_r3; - - // Signal + Noise. - q_r <= q[0 +: M]; - end -end - -// Assign outputs. -assign dout = q_r; - -endmodule - diff --git a/qick/firmware/ip/axis_signal_gen_v4/src/fifo/bin2gray.vhd b/qick/firmware/ip/axis_signal_gen_v4/src/fifo/bin2gray.vhd deleted file mode 100644 index 4ecc09b..0000000 --- a/qick/firmware/ip/axis_signal_gen_v4/src/fifo/bin2gray.vhd +++ /dev/null @@ -1,37 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity bin2gray is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end bin2gray; - -architecture rtl of bin2gray is - -signal gray : std_logic_vector (B-1 downto 0); - -begin - --- MSB always match. -gray(B-1) <= din(B-1); - -GEN: for I in 0 to B-2 generate -begin - gray(I) <= din(I+1) xor din(I); -end generate; - --- Assign output. -dout <= gray; - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v4/src/fifo/bram_dp.vhd b/qick/firmware/ip/axis_signal_gen_v4/src/fifo/bram_dp.vhd deleted file mode 100644 index d57aad1..0000000 --- a/qick/firmware/ip/axis_signal_gen_v4/src/fifo/bram_dp.vhd +++ /dev/null @@ -1,63 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity bram_dp is - Generic ( - -- Memory address size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - ena : in STD_LOGIC; - enb : in STD_LOGIC; - wea : in STD_LOGIC; - web : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR (N-1 downto 0); - addrb : in STD_LOGIC_VECTOR (N-1 downto 0); - dia : in STD_LOGIC_VECTOR (B-1 downto 0); - dib : in STD_LOGIC_VECTOR (B-1 downto 0); - doa : out STD_LOGIC_VECTOR (B-1 downto 0); - dob : out STD_LOGIC_VECTOR (B-1 downto 0) - ); -end bram_dp; - -architecture rtl of bram_dp is - --- Ram type. -type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); -shared variable RAM : ram_type; - -begin - --- CLKA port. -process (clka) -begin - if (clka'event and clka = '1') then - if (ena = '1') then - doa <= RAM(conv_integer(addra)); - if (wea = '1') then - RAM(conv_integer(addra)) := dia; - end if; - end if; - end if; -end process; - --- CLKB port. -process (clkb) -begin - if (clkb'event and clkb = '1') then - if (enb = '1') then - dob <= RAM(conv_integer(addrb)); - if (web = '1') then - RAM(conv_integer(addrb)) := dib; - end if; - end if; - end if; -end process; - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v4/src/fifo/bram_simple_dp.vhd b/qick/firmware/ip/axis_signal_gen_v4/src/fifo/bram_simple_dp.vhd deleted file mode 100644 index 1494332..0000000 --- a/qick/firmware/ip/axis_signal_gen_v4/src/fifo/bram_simple_dp.vhd +++ /dev/null @@ -1,53 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity bram_simple_dp is - Generic ( - -- Memory address size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port ( - clk : in STD_LOGIC; - ena : in STD_LOGIC; - enb : in STD_LOGIC; - wea : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR (N-1 downto 0); - addrb : in STD_LOGIC_VECTOR (N-1 downto 0); - dia : in STD_LOGIC_VECTOR (B-1 downto 0); - dob : out STD_LOGIC_VECTOR (B-1 downto 0) - ); -end bram_simple_dp; - -architecture rtl of bram_simple_dp is - --- Ram type. -type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); -shared variable RAM : ram_type; - -begin - -process (clk) -begin - if (clk'event and clk = '1') then - if (ena = '1') then - if (wea = '1') then - RAM(conv_integer(addra)) := dia; - end if; - end if; - end if; -end process; - -process (clk) -begin - if (clk'event and clk = '1') then - if (enb = '1') then - dob <= RAM(conv_integer(addrb)); - end if; - end if; -end process; - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v4/src/fifo/fifo.vhd b/qick/firmware/ip/axis_signal_gen_v4/src/fifo/fifo.vhd deleted file mode 100644 index 957362b..0000000 --- a/qick/firmware/ip/axis_signal_gen_v4/src/fifo/fifo.vhd +++ /dev/null @@ -1,135 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo; - -architecture rtl of fifo is - --- Number of bits of depth. -constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); - --- Dual port, single clock BRAM. -component bram_simple_dp is - Generic ( - -- Memory address size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port ( - clk : in STD_LOGIC; - ena : in STD_LOGIC; - enb : in STD_LOGIC; - wea : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR (N-1 downto 0); - addrb : in STD_LOGIC_VECTOR (N-1 downto 0); - dia : in STD_LOGIC_VECTOR (B-1 downto 0); - dob : out STD_LOGIC_VECTOR (B-1 downto 0) - ); -end component; - --- Pointers. -signal wptr : unsigned (N_LOG2-1 downto 0); -signal rptr : unsigned (N_LOG2-1 downto 0); - --- Memory signals. -signal mem_wea : std_logic; -signal mem_dob : std_logic_vector (B-1 downto 0); - --- Flags. -signal full_i : std_logic; -signal empty_i : std_logic; - -begin - --- FIFO memory. -mem_i : bram_simple_dp - Generic map ( - -- Memory address size. - N => N_LOG2, - -- Data width. - B => B - ) - Port map ( - clk => clk , - ena => '1' , - enb => rd_en , - wea => mem_wea , - addra => std_logic_vector(wptr) , - addrb => std_logic_vector(rptr) , - dia => din , - dob => mem_dob - ); - --- Memory connections. -mem_wea <= wr_en when full_i = '0' else - '0'; - --- Full/empty signals. -full_i <= '1' when wptr = rptr - 1 else - '0'; -empty_i <= '1' when wptr = rptr else - '0'; - --- wr_clk registers. -process (clk) -begin - if ( rising_edge(clk) ) then - if ( rstn = '0' ) then - wptr <= (others => '0'); - rptr <= (others => '0'); - else - -- Write. - if ( wr_en = '1' and full_i = '0' ) then - -- Write data. - - -- Increment pointer. - wptr <= wptr + 1; - end if; - - -- Read. - if ( rd_en = '1' and empty_i = '0' ) then - -- Read data. - - -- Increment pointer. - rptr <= rptr + 1; - end if; - end if; - end if; -end process; - --- Assign outputs. -dout <= mem_dob; -full <= full_i; -empty <= empty_i; - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v4/src/fifo/fifo_axi.vhd b/qick/firmware/ip/axis_signal_gen_v4/src/fifo/fifo_axi.vhd deleted file mode 100644 index e1f76f7..0000000 --- a/qick/firmware/ip/axis_signal_gen_v4/src/fifo/fifo_axi.vhd +++ /dev/null @@ -1,147 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo_axi is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo_axi; - -architecture rtl of fifo_axi is - --- FIFO. -component fifo is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end component; - --- FIFO read to AXI adapter. -component rd2axi is - Generic - ( - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- FIFO Read I/F. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (B-1 downto 0); - fifo_empty : in std_logic; - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - empty : out std_logic - ); -end component; - -signal rd_en_i : std_logic; -signal dout_i : std_logic_vector (B-1 downto 0); -signal empty_i : std_logic; - -begin - --- FIFO. -fifo_i : fifo - Generic map - ( - -- Data width. - B => B, - - -- Fifo depth. - N => N - ) - Port map - ( - rstn => rstn , - clk => clk , - - -- Write I/F. - wr_en => wr_en , - din => din , - - -- Read I/F. - rd_en => rd_en_i , - dout => dout_i , - - -- Flags. - full => full , - empty => empty_i - ); - --- FIFO read to AXI adapter. -rd2axi_i : rd2axi - Generic map - ( - -- Data width. - B => B - ) - Port map - ( - rstn => rstn , - clk => clk , - - -- FIFO Read I/F. - fifo_rd_en => rd_en_i , - fifo_dout => dout_i , - fifo_empty => empty_i , - - -- Read I/F. - rd_en => rd_en , - dout => dout , - empty => empty - ); - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v4/src/fifo/fifo_dc.vhd b/qick/firmware/ip/axis_signal_gen_v4/src/fifo/fifo_dc.vhd deleted file mode 100644 index c214fae..0000000 --- a/qick/firmware/ip/axis_signal_gen_v4/src/fifo/fifo_dc.vhd +++ /dev/null @@ -1,291 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo_dc is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - wr_rstn : in std_logic; - wr_clk : in std_logic; - - rd_rstn : in std_logic; - rd_clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo_dc; - -architecture rtl of fifo_dc is - --- Number of bits of depth. -constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); - --- Binary to gray converter. -component bin2gray is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end component; - --- Gray to binary converter. -component gray2bin is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end component; - --- Vector synchronizer (only for gray coded). -component synchronizer_vect is - generic ( - -- Sync stages. - N : Integer := 2; - - -- Data width. - B : Integer := 8 - ); - port ( - rstn : in std_logic; - clk : in std_logic; - data_in : in std_logic_vector (B-1 downto 0); - data_out : out std_logic_vector (B-1 downto 0) - ); -end component; - --- Dual port BRAM. -component bram_dp is - Generic ( - -- Memory address size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - ena : in STD_LOGIC; - enb : in STD_LOGIC; - wea : in STD_LOGIC; - web : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR (N-1 downto 0); - addrb : in STD_LOGIC_VECTOR (N-1 downto 0); - dia : in STD_LOGIC_VECTOR (B-1 downto 0); - dib : in STD_LOGIC_VECTOR (B-1 downto 0); - doa : out STD_LOGIC_VECTOR (B-1 downto 0); - dob : out STD_LOGIC_VECTOR (B-1 downto 0) - ); -end component; - --- Pointers. -signal wptr : unsigned (N_LOG2-1 downto 0); -signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); -signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); -signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); -signal rptr : unsigned (N_LOG2-1 downto 0); -signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); -signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); -signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); - --- Memory signals. -signal mem_wea : std_logic; -signal mem_dib : std_logic_vector (B-1 downto 0); -signal mem_doa : std_logic_vector (B-1 downto 0); -signal mem_dob : std_logic_vector (B-1 downto 0); - --- Flags. -signal full_i : std_logic; -signal empty_i : std_logic; - -begin - --- wptr_i: binary to gray. -wptr_i : bin2gray - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => std_logic_vector(wptr), - dout => wptr_g - ); - --- wptr_g: write to read domain. -wptr_g_i : synchronizer_vect - generic map ( - -- Sync stages. - N => 2, - - -- Data width. - B => N_LOG2 - ) - port map ( - rstn => rd_rstn, - clk => rd_clk, - data_in => wptr_g, - data_out => wptr_gc - ); - --- wptr_gc_i -wptr_gc_i : gray2bin - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => wptr_gc, - dout => wptr_c - ); - --- rptr_i: binary to gray. -rptr_i : bin2gray - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => std_logic_vector(rptr), - dout => rptr_g - ); - --- rptr_g: read to write domain. -rptr_g_i : synchronizer_vect - generic map ( - -- Sync stages. - N => 2, - - -- Data width. - B => N_LOG2 - ) - port map ( - rstn => wr_rstn, - clk => wr_clk, - data_in => rptr_g, - data_out => rptr_gc - ); - --- rptr_gc_i -rptr_gc_i : gray2bin - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => rptr_gc, - dout => rptr_c - ); - --- FIFO memory. -mem_i : bram_dp - Generic map ( - -- Memory address size. - N => N_LOG2, - -- Data width. - B => B - ) - Port map ( - clka => wr_clk, - clkb => rd_clk, - ena => '1', - enb => rd_en, - wea => mem_wea, - web => '0', - addra => std_logic_vector(wptr), - addrb => std_logic_vector(rptr), - dia => din, - dib => mem_dib, - doa => mem_doa, - dob => mem_dob - ); --- Memory connections. -mem_wea <= wr_en when full_i = '0' else - '0'; -mem_dib <= (others => '0'); - --- Full/empty signals. -full_i <= '1' when wptr = unsigned(rptr_c) - 1 else - '0'; -empty_i <= '1' when unsigned(wptr_c) = rptr else - '0'; - --- wr_clk registers. -process (wr_clk) -begin - if ( rising_edge(wr_clk) ) then - if ( wr_rstn = '0' ) then - wptr <= (others => '0'); - else - -- Write. - if ( wr_en = '1' and full_i = '0' ) then - -- Write data. - - -- Increment pointer. - wptr <= wptr + 1; - end if; - end if; - end if; -end process; - --- rd_clk registers. -process (rd_clk) -begin - if ( rising_edge(rd_clk) ) then - if ( rd_rstn = '0' ) then - rptr <= (others => '0'); - else - -- Read. - if ( rd_en = '1' and empty_i = '0' ) then - -- Read data. - - -- Increment pointer. - rptr <= rptr + 1; - end if; - end if; - end if; -end process; - --- Assign outputs. -dout <= mem_dob; -full <= full_i; -empty <= empty_i; - -end rtl; diff --git a/qick/firmware/ip/axis_signal_gen_v4/src/fifo/fifo_dc_axi.vhd b/qick/firmware/ip/axis_signal_gen_v4/src/fifo/fifo_dc_axi.vhd deleted file mode 100644 index eb83d1a..0000000 --- a/qick/firmware/ip/axis_signal_gen_v4/src/fifo/fifo_dc_axi.vhd +++ /dev/null @@ -1,156 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo_dc_axi is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - wr_rstn : in std_logic; - wr_clk : in std_logic; - - rd_rstn : in std_logic; - rd_clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo_dc_axi; - -architecture rtl of fifo_dc_axi is - --- Dual-clock FIFO. -component fifo_dc is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - wr_rstn : in std_logic; - wr_clk : in std_logic; - - rd_rstn : in std_logic; - rd_clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end component; - --- FIFO read to AXI adapter. -component rd2axi is - Generic - ( - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- FIFO Read I/F. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (B-1 downto 0); - fifo_empty : in std_logic; - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - empty : out std_logic - ); -end component; - -signal rd_en_i : std_logic; -signal dout_i : std_logic_vector (B-1 downto 0); -signal empty_i : std_logic; - -begin - --- Dual-clock FIFO. -fifo_i : fifo_dc - Generic map - ( - -- Data width. - B => B, - - -- Fifo depth. - N => N - ) - Port map - ( - wr_rstn => wr_rstn , - wr_clk => wr_clk , - - rd_rstn => rd_rstn , - rd_clk => rd_clk , - - -- Write I/F. - wr_en => wr_en , - din => din , - - -- Read I/F. - rd_en => rd_en_i , - dout => dout_i , - - -- Flags. - full => full , - empty => empty_i - ); - --- FIFO read to AXI adapter. -rd2axi_i : rd2axi - Generic map - ( - -- Data width. - B => B - ) - Port map - ( - rstn => rd_rstn , - clk => rd_clk , - - -- FIFO Read I/F. - fifo_rd_en => rd_en_i , - fifo_dout => dout_i , - fifo_empty => empty_i , - - -- Read I/F. - rd_en => rd_en , - dout => dout , - empty => empty - ); - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v4/src/fifo/gray2bin.vhd b/qick/firmware/ip/axis_signal_gen_v4/src/fifo/gray2bin.vhd deleted file mode 100644 index e23f8af..0000000 --- a/qick/firmware/ip/axis_signal_gen_v4/src/fifo/gray2bin.vhd +++ /dev/null @@ -1,37 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity gray2bin is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end gray2bin; - -architecture rtl of gray2bin is - -signal bin : std_logic_vector (B-1 downto 0); - -begin - --- MSB always match. -bin(B-1) <= din(B-1); - -GEN: for I in 0 to B-2 generate -begin - bin(I) <= bin(I+1) xor din(I); -end generate GEN; - --- Assign output. -dout <= bin; - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v4/src/fifo/rd2axi.vhd b/qick/firmware/ip/axis_signal_gen_v4/src/fifo/rd2axi.vhd deleted file mode 100644 index babadc6..0000000 --- a/qick/firmware/ip/axis_signal_gen_v4/src/fifo/rd2axi.vhd +++ /dev/null @@ -1,138 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity rd2axi is - Generic - ( - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- FIFO Read I/F. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (B-1 downto 0); - fifo_empty : in std_logic; - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - empty : out std_logic - ); -end rd2axi; - -architecture rtl of rd2axi is - -type fsm_state is ( WAIT_EMPTY_ST, - READ_FIRST_ST, - READ_ST, - READ_LAST_ST); -signal current_state, next_state : fsm_state; - -signal wait_empty_state : std_logic; -signal read_first_state : std_logic; -signal read_state : std_logic; - -signal fifo_rd_en_i : std_logic; -signal empty_i : std_logic; - -begin - -process(clk) -begin - if (rising_edge(clk)) then - if (rstn = '0') then - current_state <= WAIT_EMPTY_ST; - else - current_state <= next_state; - end if; - end if; -end process; - --- Next state logic. -process(current_state, fifo_empty, rd_en) -begin - case current_state is - when WAIT_EMPTY_ST => - if (fifo_empty = '1') then - next_state <= WAIT_EMPTY_ST; - else - next_state <= READ_FIRST_ST; - end if; - - when READ_FIRST_ST => - next_state <= READ_ST; - - when READ_ST => - if (fifo_empty = '0') then - next_state <= READ_ST; - else - if (rd_en = '1') then - next_state <= WAIT_EMPTY_ST; - else - next_state <= READ_LAST_ST; - end if; - end if; - - when READ_LAST_ST => - if (rd_en = '0') then - next_state <= READ_LAST_ST; - else - next_state <= WAIT_EMPTY_ST; - end if; - - end case; -end process; - --- Output logic. -process(current_state) -begin -wait_empty_state <= '0'; -read_first_state <= '0'; -read_state <= '0'; -empty_i <= '0'; - case current_state is - when WAIT_EMPTY_ST => - wait_empty_state <= '1'; - read_first_state <= '0'; - read_state <= '0'; - empty_i <= '1'; - - when READ_FIRST_ST => - wait_empty_state <= '0'; - read_first_state <= '1'; - read_state <= '0'; - empty_i <= '1'; - - when READ_ST => - wait_empty_state <= '0'; - read_first_state <= '0'; - read_state <= '1'; - empty_i <= '0'; - - when READ_LAST_ST => - wait_empty_state <= '0'; - read_first_state <= '0'; - read_state <= '0'; - empty_i <= '0'; - - end case; -end process; - --- FIFO Read enable signal. -fifo_rd_en_i <= read_first_state or (read_state and rd_en); - --- Assign outputs. -fifo_rd_en <= fifo_rd_en_i; --- TODO: add register to freeze last value. -dout <= fifo_dout when empty_i = '0' else - (others => '0'); -empty <= empty_i; - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v4/src/fifo/synchronizer_vect.vhd b/qick/firmware/ip/axis_signal_gen_v4/src/fifo/synchronizer_vect.vhd deleted file mode 100644 index 2fbb696..0000000 --- a/qick/firmware/ip/axis_signal_gen_v4/src/fifo/synchronizer_vect.vhd +++ /dev/null @@ -1,49 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - --- This block is intended to use to sync gray coded vectors. - --- NOTE: Do not use with generic vector data, as it may result --- in corrupted re-sync data. - -entity synchronizer_vect is - generic ( - -- Sync stages. - N : Integer := 2; - - -- Data width. - B : Integer := 8 - ); - port ( - rstn : in std_logic; - clk : in std_logic; - data_in : in std_logic_vector (B-1 downto 0); - data_out : out std_logic_vector (B-1 downto 0) - ); -end synchronizer_vect; - -architecture rtl of synchronizer_vect is - --- Internal register. -type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); -signal data_int_reg : reg_t; - -begin - -process(clk) -begin - if (rising_edge(clk)) then - if (rstn = '0') then - data_int_reg <= (others => (others => '0')); -- 1 FF. - else - data_int_reg <= data_int_reg(N-2 downto 0) & data_in; - end if; - end if; -end process; - --- Assign output. -data_out <= data_int_reg(N-1); - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v4/src/random_gen.v b/qick/firmware/ip/axis_signal_gen_v4/src/random_gen.v deleted file mode 100644 index e67cd42..0000000 --- a/qick/firmware/ip/axis_signal_gen_v4/src/random_gen.v +++ /dev/null @@ -1,137 +0,0 @@ -module random_gen - #( - parameter W = 16 , - parameter SEED = 0 - ) - ( - input rstn , - input clk , - output [W-1 : 0] dout - ); - -reg [W-1 : 0] rand_out; -reg [W-1 : 0] rand_ff; - -reg [W-1 : 0] dout_r1; -reg [W-1 : 0] dout_r2; -reg [W-1 : 0] dout_r3; -reg [W-1 : 0] dout_r4; - -localparam seed_int = 24'b 0110_0011_0111_0110_1001_1101 + SEED; - -// LFSR. -always @(posedge clk) begin - if(rstn == 1'b 0) begin - rand_ff[W-1 :0] <= seed_int; // seed for pseudo random number sequencer - rand_out <= {W-1{1'b 0}}; - end - else begin - case (W) - 24 : begin - rand_ff[W-1 : 0] <= { ( rand_ff[7] ^ rand_ff[2] ^ rand_ff[1] ^ rand_ff[0]) , rand_ff[W-1 : 1] }; // x^24 + x^23 + x^22 + x^17 + - rand_out <= rand_ff; - end - 23 : begin - rand_ff[W-1 : 0] <= { ( rand_ff[5] ^ rand_ff[0] ) , rand_ff[W-1 : 1] }; // x^23+ x^18 + - rand_out <= rand_ff; - end - 22 : begin - rand_ff[W-1 : 0] <= { ( rand_ff[1] ^ rand_ff[0] ) , rand_ff[W-1 : 1] }; // x^22+ x^21 + - rand_out <= rand_ff; - end - 21 : begin - rand_ff[W-1 : 0] <= { ( rand_ff[2] ^ rand_ff[0] ), rand_ff[W-1 : 1] }; // x^21+ x^19 + - rand_out <= rand_ff; - end - 20 : begin - rand_ff[W-1 : 0] <= { ( rand_ff[3] ^ rand_ff[0] ), rand_ff[W-1 : 1] }; // x^20+ x^17 + - rand_out <= rand_ff; - end - 19 : begin - rand_ff[W-1 : 0] <= { ( rand_ff[15] ^ rand_ff[13] ^ rand_ff[0] ), rand_ff[W-1 : 1] }; // x^19 + x^5 + x^2 + 1 - rand_out <= rand_ff; - end - 18 : begin - rand_ff[W-1 : 0] <= { ( rand_ff[7] ^ rand_ff[0] ) , rand_ff[W-1 : 1] }; // x^18 + x^11 + - rand_out <= rand_ff; - end - 17 : begin - rand_ff[W-1 : 0] <= { ( rand_ff[3] ^ rand_ff[0] ) , rand_ff[W-1 : 1] }; // x^17 + x^14 + - rand_out <= rand_ff; - end - 16 : begin - rand_ff[W-1 : 0] <= { ( rand_ff[5] ^ rand_ff[3] ^ rand_ff[2] ^ rand_ff[0]) , rand_ff[W-1 : 1] }; // x^16 + x^14 + x^13 + x^11 + - rand_out <= rand_ff; - end - 15 : begin - rand_ff[W-1 : 0] <= { ( rand_ff[1] ^ rand_ff[0] ), rand_ff[W-1 : 1] }; // x^15 + x^14 + - rand_out <= rand_ff; - end - 14 : begin - rand_ff[W-1 : 0] <= { ( rand_ff[12] ^ rand_ff[2] ^ rand_ff[1] ^ rand_ff[0]), rand_ff[W-1 : 1] }; // x^14 + x^13 + x^12 + x^2 + - rand_out <= rand_ff; - end - 13 : begin - rand_ff[W-1 : 0] <= { ( rand_ff[5] ^ rand_ff[2] ^ rand_ff[1] ^ rand_ff[0] ), rand_ff[W-1 : 1] }; // x^13 + x^12 + x^11 + x^8 + - rand_out <= rand_ff; - end - 12 : begin - rand_ff[W-1 : 0] <= { ( rand_ff[8] ^ rand_ff[2] ^ rand_ff[1] ^ rand_ff[0] ), rand_ff[W-1 : 1] }; // x^12 + x^11 + x^10 + x^4 + - rand_out <= rand_ff; - end - 11 : begin - rand_ff[W-1 : 0] <= { ( rand_ff[1] ^ rand_ff[0] ), rand_ff[W-1 : 1] }; // x^11 + x^9 + - rand_out <= rand_ff; - end - 10 : begin - rand_ff[W-1 : 0] <= { ( rand_ff[3] ^ rand_ff[0] ), rand_ff[W-1 : 1] }; // x^10 + x^7 + - rand_out <= rand_ff; - end - 9 : begin - rand_ff[W-1 : 0] <= { ( rand_ff[4] ^ rand_ff[0] ), rand_ff[W-1 : 1] }; // x^9 + x^5 + - rand_out <= rand_ff; - end - 8 : begin - rand_ff[W-1 : 0] <= { ( rand_ff[4] ^ rand_ff[3] ^ rand_ff[2] ^ rand_ff[0]), rand_ff[W-1 : 1] }; // x^8 + x^6 + x^5 + x^4 + - rand_out <= rand_ff; - end - 7 : begin - rand_ff[W-1 : 0] <= { ( rand_ff[1] ^ rand_ff[0] ) , rand_ff[W-1 : 1] }; // x^7 + x^6 + - rand_out <= rand_ff; - end - 6 : begin - rand_ff[W-1 : 0] <= { ( rand_ff[1] ^ rand_ff[0] ) , rand_ff[W-1 : 1] }; // x^6 + x^5 + - rand_out <= rand_ff; - end - 5 : begin - rand_ff[W-1 : 0] <= { ( rand_ff[2] ^ rand_ff[0] ), rand_ff[W-1 : 1] }; // x^5 + x^3 + - rand_out <= rand_ff; - end - default : begin - rand_ff[W-1 : 0] <= { (rand_ff[1] ^ rand_ff[0]) , rand_ff[W-1 : 0]}; // x^4 + x^3 + - rand_out <= rand_ff; - end - endcase - end -end - -// Output register. -always @(posedge clk) begin - if (rstn == 1'b0) begin - dout_r1 <= 0; - dout_r2 <= 0; - dout_r3 <= 0; - dout_r4 <= 0; - end - else begin - dout_r1 <= rand_out; - dout_r2 <= dout_r1; - dout_r3 <= dout_r2; - dout_r4 <= dout_r3; - end -end - -assign dout = dout_r4; - -endmodule - diff --git a/qick/firmware/ip/axis_signal_gen_v4/src/signal_gen.v b/qick/firmware/ip/axis_signal_gen_v4/src/signal_gen.v deleted file mode 100644 index 6fc6f42..0000000 --- a/qick/firmware/ip/axis_signal_gen_v4/src/signal_gen.v +++ /dev/null @@ -1,639 +0,0 @@ -module signal_gen ( - // Reset and clock. - rstn , - clk , - - // Fifo interface. - fifo_rd_en_o , - fifo_empty_i , - fifo_dout_i , - - // Memory interface. - mem_addr_o , - mem_dout_real_i , - mem_dout_imag_i , - - // M_AXIS for output. - m_axis_tready_i , - m_axis_tvalid_o , - m_axis_tdata_o , - - // Registers. - RNDQ_REG , - OUTSEL_REG - ); - -/**************/ -/* Parameters */ -/**************/ -// Memory address size. -parameter N = 16; - -// Number of parallel dds blocks. -parameter [31:0] N_DDS = 16; - -/*********/ -/* Ports */ -/*********/ -input rstn; -input clk; - -output fifo_rd_en_o; -input fifo_empty_i; -input [159:0] fifo_dout_i; - -output [N-1:0] mem_addr_o; -input [N_DDS*16-1:0] mem_dout_real_i; -input [N_DDS*16-1:0] mem_dout_imag_i; - -input m_axis_tready_i; -output m_axis_tvalid_o; -output [N_DDS*16-1:0] m_axis_tdata_o; - -input [31:0] RNDQ_REG; -input OUTSEL_REG; - -/********************/ -/* Internal signals */ -/********************/ -// Memory address. -wire [N-1:0] mem_addr_int; -reg [N-1:0] mem_addr_int_r; - -// DDS input control. -reg dds_tvalid_r; -wire [N_DDS*72-1:0] dds_ctrl_int; -reg [N_DDS*72-1:0] dds_ctrl_int_r; - -// DDS output. -wire [31:0] dds_dout [0:N_DDS-1]; -reg [31:0] dds_dout_r1 [0:N_DDS-1]; -reg [31:0] dds_dout_r2 [0:N_DDS-1]; -reg [31:0] dds_dout_r3 [0:N_DDS-1]; -reg [31:0] dds_dout_r4 [0:N_DDS-1]; -reg [31:0] dds_dout_r5 [0:N_DDS-1]; -reg [31:0] dds_dout_r6 [0:N_DDS-1]; - -// Memory data. -reg [15:0] mem_dout_real_r1 [0:N_DDS-1]; -reg [15:0] mem_dout_real_r2 [0:N_DDS-1]; -reg [15:0] mem_dout_real_r3 [0:N_DDS-1]; -reg [15:0] mem_dout_real_r4 [0:N_DDS-1]; -reg [15:0] mem_dout_real_r5 [0:N_DDS-1]; -reg [15:0] mem_dout_real_r6 [0:N_DDS-1]; -reg [15:0] mem_dout_real_r7 [0:N_DDS-1]; -reg [15:0] mem_dout_real_r8 [0:N_DDS-1]; -reg [15:0] mem_dout_real_r9 [0:N_DDS-1]; -reg signed [15:0] mem_dout_real_r10_a [0:N_DDS-1]; -reg [15:0] mem_dout_real_r10_b [0:N_DDS-1]; -reg [15:0] mem_dout_real_r11 [0:N_DDS-1]; -reg [15:0] mem_dout_real_r12 [0:N_DDS-1]; -reg [15:0] mem_dout_real_r13 [0:N_DDS-1]; -reg [15:0] mem_dout_imag_r1 [0:N_DDS-1]; -reg [15:0] mem_dout_imag_r2 [0:N_DDS-1]; -reg [15:0] mem_dout_imag_r3 [0:N_DDS-1]; -reg [15:0] mem_dout_imag_r4 [0:N_DDS-1]; -reg [15:0] mem_dout_imag_r5 [0:N_DDS-1]; -reg [15:0] mem_dout_imag_r6 [0:N_DDS-1]; -reg [15:0] mem_dout_imag_r7 [0:N_DDS-1]; -reg [15:0] mem_dout_imag_r8 [0:N_DDS-1]; -reg [15:0] mem_dout_imag_r9 [0:N_DDS-1]; -reg signed [15:0] mem_dout_imag_r10_a [0:N_DDS-1]; -reg [15:0] mem_dout_imag_r10_b [0:N_DDS-1]; -reg [15:0] mem_dout_imag_r11 [0:N_DDS-1]; -reg [15:0] mem_dout_imag_r12 [0:N_DDS-1]; -reg [15:0] mem_dout_imag_r13 [0:N_DDS-1]; - -// Product. -wire signed [15:0] prod_a_real [0:N_DDS-1]; -wire signed [15:0] prod_a_imag [0:N_DDS-1]; -wire signed [15:0] prod_b_real [0:N_DDS-1]; -wire signed [15:0] prod_b_imag [0:N_DDS-1]; -wire signed [31:0] prod_y_full_real_a [0:N_DDS-1]; -wire signed [31:0] prod_y_full_real_b [0:N_DDS-1]; -reg signed [31:0] prod_y_full_real_a_r[0:N_DDS-1]; -reg signed [31:0] prod_y_full_real_b_r[0:N_DDS-1]; -wire signed [31:0] prod_y_full_imag_a [0:N_DDS-1]; -wire signed [31:0] prod_y_full_imag_b [0:N_DDS-1]; -reg signed [31:0] prod_y_full_imag_a_r[0:N_DDS-1]; -reg signed [31:0] prod_y_full_imag_b_r[0:N_DDS-1]; -wire signed [31:0] prod_y_full_real [0:N_DDS-1]; -wire signed [31:0] prod_y_full_imag [0:N_DDS-1]; -wire [15:0] prod_y_real [0:N_DDS-1]; -wire [15:0] prod_y_imag [0:N_DDS-1]; -wire [31:0] prod_y [0:N_DDS-1]; -reg [31:0] prod_y_r1 [0:N_DDS-1]; -reg [31:0] prod_y_r2 [0:N_DDS-1]; - -// Muxed output. -wire [31:0] dout_mux [0:N_DDS-1]; -reg [31:0] dout_mux_r1 [0:N_DDS-1]; -reg [31:0] dout_mux_r2 [0:N_DDS-1]; - -// Product with Gain. -wire [15:0] gain_int; -reg [15:0] gain_int_r1; -reg [15:0] gain_int_r2; -reg [15:0] gain_int_r3; -reg [15:0] gain_int_r4; -reg [15:0] gain_int_r5; -reg [15:0] gain_int_r6; -reg [15:0] gain_int_r7; -reg [15:0] gain_int_r8; -reg [15:0] gain_int_r9; -reg [15:0] gain_int_r10; -reg [15:0] gain_int_r11; -reg [15:0] gain_int_r12; -reg [15:0] gain_int_r13; -reg [15:0] gain_int_r14; -reg [15:0] gain_int_r15; -reg [15:0] gain_int_r16; -reg signed [15:0] gain_int_r17; -wire signed [15:0] prodg_a_real [0:N_DDS-1]; -wire signed [15:0] prodg_a_imag [0:N_DDS-1]; -wire signed [31:0] prodg_y_full_real [0:N_DDS-1]; -wire signed [31:0] prodg_y_full_imag [0:N_DDS-1]; -reg [31:0] prodg_y_full_real_r [0:N_DDS-1]; -reg [31:0] prodg_y_full_imag_r [0:N_DDS-1]; -reg [15:0] round_r_real [0:N_DDS-1]; -reg [15:0] round_r_imag [0:N_DDS-1]; - -// Mux for real/imaginary part selection. -wire [15:0] round_r_mux [0:N_DDS-1]; - -// Output source selection. -wire [1:0] src_int; -reg [1:0] src_int_r1; -reg [1:0] src_int_r2; -reg [1:0] src_int_r3; -reg [1:0] src_int_r4; -reg [1:0] src_int_r5; -reg [1:0] src_int_r6; -reg [1:0] src_int_r7; -reg [1:0] src_int_r8; -reg [1:0] src_int_r9; -reg [1:0] src_int_r10; -reg [1:0] src_int_r11; -reg [1:0] src_int_r12; -reg [1:0] src_int_r13; -reg [1:0] src_int_r14; -reg [1:0] src_int_r15; - -// Steady value selection. -wire stdy_int; -reg stdy_int_r1; -reg stdy_int_r2; -reg stdy_int_r3; -reg stdy_int_r4; -reg stdy_int_r5; -reg stdy_int_r6; -reg stdy_int_r7; -reg stdy_int_r8; -reg stdy_int_r9; -reg stdy_int_r10; -reg stdy_int_r11; -reg stdy_int_r12; -reg stdy_int_r13; -reg stdy_int_r14; -reg stdy_int_r15; -reg stdy_int_r16; -reg stdy_int_r17; -reg stdy_int_r18; -reg stdy_int_r19; - -// Output enable. -wire en_int; -reg en_int_r1; -reg en_int_r2; -reg en_int_r3; -reg en_int_r4; -reg en_int_r5; -reg en_int_r6; -reg en_int_r7; -reg en_int_r8; -reg en_int_r9; -reg en_int_r10; -reg en_int_r11; -reg en_int_r12; -reg en_int_r13; -reg en_int_r14; -reg en_int_r15; -reg en_int_r16; -reg en_int_r17; -reg en_int_r18; -reg en_int_r19; - -// Output selection mux. -wire outmux_sel; - -/**********************/ -/* Begin Architecture */ -/**********************/ -// Control block. -ctrl - #( - .N (N ), - .N_DDS (N_DDS ) - ) - ctrl_i - ( - // Reset and clock. - .rstn (rstn ), - .clk (clk ), - - // Fifo interface. - .fifo_rd_en_o (fifo_rd_en_o ), - .fifo_empty_i (fifo_empty_i ), - .fifo_dout_i (fifo_dout_i ), - - // dds control. - .dds_ctrl_o (dds_ctrl_int ), - - // memory control. - .mem_addr_o (mem_addr_int ), - - // gain. - .gain_o (gain_int ), - - // Output source selection. - .src_o (src_int ), - - // Steady value selection. - .stdy_o (stdy_int ), - - // Output enable. - .en_o (en_int ) - ); - - - -generate -genvar i; - for (i=0; i '0'); - else - data_int_reg <= data_int_reg(N-2 downto 0) & data_in; - end if; - end if; -end process; - --- Assign output. -data_out <= data_int_reg(N-1); - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v4/src/tb/gauss.txt b/qick/firmware/ip/axis_signal_gen_v4/src/tb/gauss.txt deleted file mode 100644 index 68d9265..0000000 --- a/qick/firmware/ip/axis_signal_gen_v4/src/tb/gauss.txt +++ /dev/null @@ -1,512 +0,0 @@ -57,0 -60,0 -62,0 -65,0 -68,0 -71,0 -74,0 -77,0 -80,0 -83,0 -87,0 -90,0 -94,0 -98,0 -102,0 -106,0 -110,0 -115,0 -119,0 -124,0 -129,0 -134,0 -140,0 -145,0 -151,0 -157,0 -163,0 -169,0 -176,0 -182,0 -189,0 -197,0 -204,0 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-1574,0 -1530,0 -1486,0 -1444,0 -1403,0 -1362,0 diff --git a/qick/firmware/ip/axis_signal_gen_v4/src/tb/gen_gauss.py b/qick/firmware/ip/axis_signal_gen_v4/src/tb/gen_gauss.py deleted file mode 100644 index 88ba683..0000000 --- a/qick/firmware/ip/axis_signal_gen_v4/src/tb/gen_gauss.py +++ /dev/null @@ -1,18 +0,0 @@ -import numpy as np -import matplotlib.pyplot as plt - -def gauss(mu=0, si=0, length=100, maxv=30000): - x = np.arange(0,length) - y = 1/(2*np.pi*si**2)*np.exp(-(x-mu)**2/si**2) - y = y/np.max(y)*maxv - return y - -yq = gauss(mu=300, si=120, length=512) -yi = np.zeros(len(yq)) - -yi = yi.astype(np.int16) -yq = yq.astype(np.int16) - -for ii in range(len(yi)): - print("%d,%d" %(yq[ii],yi[ii])) - diff --git a/qick/firmware/ip/axis_signal_gen_v4/src/tb/gen_ramp.py b/qick/firmware/ip/axis_signal_gen_v4/src/tb/gen_ramp.py deleted file mode 100644 index 71d11e7..0000000 --- a/qick/firmware/ip/axis_signal_gen_v4/src/tb/gen_ramp.py +++ /dev/null @@ -1,19 +0,0 @@ -import numpy as np -import matplotlib.pyplot as plt - -def triang(length=100, maxv=30000): - y1 = np.arange(0,length/2) - y2 = np.flip(y1,0) - y = np.concatenate((y1,y2)) - y = y/np.max(y)*maxv - return y - -yq = triang(length=512) -yi = yq - -yi = yi.astype(np.int16) -yq = yq.astype(np.int16) - -for ii in range(len(yi)): - print("%d,%d" %(yq[ii],yi[ii])) - diff --git a/qick/firmware/ip/axis_signal_gen_v4/src/tb/ramp.txt b/qick/firmware/ip/axis_signal_gen_v4/src/tb/ramp.txt deleted file mode 100644 index 32bfe92..0000000 --- a/qick/firmware/ip/axis_signal_gen_v4/src/tb/ramp.txt +++ /dev/null @@ -1,512 +0,0 @@ -0,0 -117,117 -235,235 -352,352 -470,470 -588,588 -705,705 -823,823 -941,941 -1058,1058 -1176,1176 -1294,1294 -1411,1411 -1529,1529 -1647,1647 -1764,1764 -1882,1882 -2000,2000 -2117,2117 -2235,2235 -2352,2352 -2470,2470 -2588,2588 -2705,2705 -2823,2823 -2941,2941 -3058,3058 -3176,3176 -3294,3294 -3411,3411 -3529,3529 -3647,3647 -3764,3764 -3882,3882 -4000,4000 -4117,4117 -4235,4235 -4352,4352 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file mode 100644 index da66249..0000000 --- a/qick/firmware/ip/axis_signal_gen_v4/src/tb/tb.sv +++ /dev/null @@ -1,412 +0,0 @@ -// VIP: axi_mst_0 -// DUT: axis_signal_gen_v2 -// IF: s_axi -> axi_mst_0 - -import axi_vip_pkg::*; -import axi_mst_0_pkg::*; - -module tb(); - -// DUT generics. -parameter N = 10; -parameter N_DDS = 16; - -// s_axi interfase. -reg s_axi_aclk; -reg s_axi_aresetn; -wire [5:0] s_axi_araddr; -wire [2:0] s_axi_arprot; -wire s_axi_arready; -wire s_axi_arvalid; -wire [5:0] s_axi_awaddr; -wire [2:0] s_axi_awprot; -wire s_axi_awready; -wire s_axi_awvalid; -wire s_axi_bready; -wire [1:0] s_axi_bresp; -wire s_axi_bvalid; -wire [31:0] s_axi_rdata; -wire s_axi_rready; -wire [1:0] s_axi_rresp; -wire s_axi_rvalid; -wire [31:0] s_axi_wdata; -wire s_axi_wready; -wire [3:0] s_axi_wstrb; -wire s_axi_wvalid; - -// s0_axis interfase. -reg s0_axis_aclk; -reg s0_axis_aresetn; -reg [31:0] s0_axis_tdata; -wire s0_axis_tready; -reg s0_axis_tvalid; - -reg aresetn; -reg aclk; - -// s1_axis interfase. -reg [159:0] s1_axis_tdata; -wire s1_axis_tready; -reg s1_axis_tvalid; - -// m_axis interfase. -wire [N_DDS*16-1:0] m_axis_tdata; -reg m_axis_tready = 1; -wire m_axis_tvalid; - -// Waveform Fields. -reg [31:0] freq_r; -reg [31:0] phase_r; -reg [15:0] addr_r; -reg [15:0] gain_r; -reg [15:0] nsamp_r; -reg [1:0] outsel_r; -reg mode_r; -reg stdysel_r; -reg phrst_r; - -// Assignment of data out for debugging. -wire [15:0] dout_ii [0:N_DDS-1]; - -// AXI VIP master address. -xil_axi_ulong addr_start_addr = 32'h40000000; // 0 -xil_axi_ulong addr_we = 32'h40000004; // 1 -xil_axi_ulong addr_rndq = 32'h40000008; // 2 -xil_axi_ulong addr_outsel = 32'h4000000c; // 3 - -xil_axi_prot_t prot = 0; -reg[31:0] data_wr = 32'h12345678; -reg[31:0] data; -xil_axi_resp_t resp; - -// Test bench control. -reg tb_load_mem = 0; -reg tb_load_mem_done = 0; -reg tb_load_wave = 0; -reg tb_load_wave_done = 0; -reg tb_write_out = 0; - -// Debug. -generate -genvar ii; -for (ii = 0; ii < N_DDS; ii = ii + 1) begin : GEN_debug - assign dout_ii[ii] = m_axis_tdata[16*ii +: 16]; -end -endgenerate -axi_mst_0 axi_mst_0_i - ( - .aclk (s_axi_aclk ), - .aresetn (s_axi_aresetn ), - .m_axi_araddr (s_axi_araddr ), - .m_axi_arprot (s_axi_arprot ), - .m_axi_arready (s_axi_arready ), - .m_axi_arvalid (s_axi_arvalid ), - .m_axi_awaddr (s_axi_awaddr ), - .m_axi_awprot (s_axi_awprot ), - .m_axi_awready (s_axi_awready ), - .m_axi_awvalid (s_axi_awvalid ), - .m_axi_bready (s_axi_bready ), - .m_axi_bresp (s_axi_bresp ), - .m_axi_bvalid (s_axi_bvalid ), - .m_axi_rdata (s_axi_rdata ), - .m_axi_rready (s_axi_rready ), - .m_axi_rresp (s_axi_rresp ), - .m_axi_rvalid (s_axi_rvalid ), - .m_axi_wdata (s_axi_wdata ), - .m_axi_wready (s_axi_wready ), - .m_axi_wstrb (s_axi_wstrb ), - .m_axi_wvalid (s_axi_wvalid ) - ); - -axis_signal_gen_v4 - # - ( - .N (N ), - .N_DDS (N_DDS ) - ) - DUT - ( - // AXI Slave I/F for configuration. - .s_axi_aclk (s_axi_aclk ), - .s_axi_aresetn (s_axi_aresetn ), - .s_axi_araddr (s_axi_araddr ), - .s_axi_arprot (s_axi_arprot ), - .s_axi_arready (s_axi_arready ), - .s_axi_arvalid (s_axi_arvalid ), - .s_axi_awaddr (s_axi_awaddr ), - .s_axi_awprot (s_axi_awprot ), - .s_axi_awready (s_axi_awready ), - .s_axi_awvalid (s_axi_awvalid ), - .s_axi_bready (s_axi_bready ), - .s_axi_bresp (s_axi_bresp ), - .s_axi_bvalid (s_axi_bvalid ), - .s_axi_rdata (s_axi_rdata ), - .s_axi_rready (s_axi_rready ), - .s_axi_rresp (s_axi_rresp ), - .s_axi_rvalid (s_axi_rvalid ), - .s_axi_wdata (s_axi_wdata ), - .s_axi_wready (s_axi_wready ), - .s_axi_wstrb (s_axi_wstrb ), - .s_axi_wvalid (s_axi_wvalid ), - - // AXIS Slave to load data into memory. - .s0_axis_aclk (s0_axis_aclk ), - .s0_axis_aresetn(s0_axis_aresetn), - .s0_axis_tdata (s0_axis_tdata ), - .s0_axis_tvalid (s0_axis_tvalid ), - .s0_axis_tready (s0_axis_tready ), - - // s1_* and m_* reset/clock. - .aresetn (aresetn ), - .aclk (aclk ), - - // AXIS Slave to queue waveforms. - .s1_axis_tdata (s1_axis_tdata ), - .s1_axis_tvalid (s1_axis_tvalid ), - .s1_axis_tready (s1_axis_tready ), - - // AXIS Master for output data. - .m_axis_tready (m_axis_tready ), - .m_axis_tvalid (m_axis_tvalid ), - .m_axis_tdata (m_axis_tdata ) - ); - -// VIP Agents -axi_mst_0_mst_t axi_mst_0_agent; - -assign s1_axis_tdata = {{10{1'b0}},phrst_r,stdysel_r,mode_r,outsel_r,nsamp_r,{16{1'b0}},gain_r,{16{1'b0}},addr_r,phase_r,freq_r}; - -initial begin - // Create agents. - axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); - - // Set tag for agents. - axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); - - // Start agents. - axi_mst_0_agent.start_master(); - - // Reset sequence. - s_axi_aresetn <= 0; - s0_axis_aresetn <= 0; - aresetn <= 0; - #500; - s_axi_aresetn <= 1; - s0_axis_aresetn <= 1; - aresetn <= 1; - - #1000; - - $display("############################"); - $display("### Load data into Table ###"); - $display("############################"); - $display("t = %0t", $time); - - /* - ADDR = 0 - */ - - // start_addr. - data_wr = 0; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(addr_start_addr, prot, data_wr, resp); - #10; - - // we. - data_wr = 1; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(addr_we, prot, data_wr, resp); - #10; - - // Load Table. - tb_load_mem <= 1; - wait (tb_load_mem_done); - - #100; - - // we. - data_wr = 0; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(addr_we, prot, data_wr, resp); - #10; - - $display("############################"); - $display("### Output selection reg ###"); - $display("############################"); - $display("t = %0t", $time); - - /* - OUTSEL = 0 (real part). - */ - - data_wr = 1; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(addr_outsel, prot, data_wr, resp); - #10; - - #1000; - - $display("#######################"); - $display("### Queue Waveforms ###"); - $display("#######################"); - $display("t = %0t", $time); - - // Queue waveforms and write output while queuing. - tb_load_wave <= 1; - tb_write_out <= 1; - wait (tb_load_wave_done); - - #3000; - - // Stop writing output data. - tb_write_out <= 0; - - #20000; - -end - -// Load data into memroy. -initial begin - int fd,vali,valq; - bit signed [15:0] ii,qq; - - s0_axis_tvalid <= 0; - s0_axis_tdata <= 0; - - wait (tb_load_mem); - - //fd = $fopen("../../../../../tb/gauss.txt","r"); - fd = $fopen("../../../../../tb/ramp.txt","r"); - - wait (s0_axis_tready); - - while($fscanf(fd,"%d,%d", valq,vali) == 2) begin - $display("I,Q: %d, %d", vali,valq); - ii = vali; - qq = valq; - @(posedge s0_axis_aclk); - s0_axis_tvalid <= 1; - s0_axis_tdata <= {qq,ii}; - end - - @(posedge s0_axis_aclk); - s0_axis_tvalid <= 0; - - $fclose(fd); - tb_load_mem_done <= 1; - -end - -// Load waveforms. -initial begin - s1_axis_tvalid <= 0; - freq_r <= 0; - phase_r <= 0; - addr_r <= 0; - gain_r <= 0; - nsamp_r <= 0; - outsel_r <= 0; - mode_r <= 0; - stdysel_r <= 0; - phrst_r <= 0; - - wait (tb_load_wave); - wait (s1_axis_tready); - - @(posedge aclk); - $display("t = %0t", $time); - s1_axis_tvalid <= 1; - freq_r <= freq_calc(100, N_DDS, 34); - phase_r <= 0; - addr_r <= 0; - gain_r <= 30000; - nsamp_r <= 128/N_DDS; - outsel_r <= 2; // 0: prod, 1: dds, 2: mem - mode_r <= 0; // 0: nsamp, 1: periodic - stdysel_r <= 1; // 0: last, 1: zero. - - @(posedge aclk); - s1_axis_tvalid <= 0; - - #200; - - @(posedge aclk); - $display("t = %0t", $time); - s1_axis_tvalid <= 1; - gain_r <= 10000; - nsamp_r <= 620/N_DDS; - - //@(posedge aclk); - //s1_axis_tvalid <= 0; - - //#10000; - - //@(posedge aclk); - //$display("t = %0t", $time); - //s1_axis_tvalid <= 1; - //nsamp_r <= 920/N_DDS; - - @(posedge aclk); - s1_axis_tvalid <= 0; - tb_load_wave_done <= 1; -end - -// Write output into file. -initial begin - int fd; - int i; - shortint real_d, imag_d; - - // Output file. - fd = $fopen("../../../../../tb/dout.csv","w"); - - // Data format. - $fdisplay(fd, "valid, idx, real, imag"); - - wait (tb_write_out); - - while (tb_write_out) begin - @(posedge aclk); - for (i=0; i - - user.org - user - axis_signal_gen_v5 - 1.0 - - - m_axis - - - - - - - TDATA - - - m_axis_tdata - - - - - TVALID - - - m_axis_tvalid - - - - - TREADY - - - m_axis_tready - - - - - - s0_axis - - - - - - - TDATA - - - s0_axis_tdata - - - - - TVALID - - - s0_axis_tvalid - - - - - TREADY - - - s0_axis_tready - - - - - - s1_axis - - - - - - - TDATA - - - s1_axis_tdata - - - - - TVALID - - - s1_axis_tvalid - - - - - TREADY - - - s1_axis_tready - - - - - - s_axi - - - - - - - - - AWADDR - - - s_axi_awaddr - - - - - AWPROT - - - s_axi_awprot - - - - - AWVALID - - - s_axi_awvalid - - - - - AWREADY - - - s_axi_awready - - - - - WDATA - - - s_axi_wdata - - - - - WSTRB - - - s_axi_wstrb - - - - - WVALID - - - s_axi_wvalid - - - - - WREADY - - - s_axi_wready - - - - - BRESP - - - s_axi_bresp - - - - - BVALID - - - s_axi_bvalid - - - - - BREADY - - - s_axi_bready - - - - - ARADDR - - - s_axi_araddr - - - - - ARPROT - - - s_axi_arprot - - - - - ARVALID - - - s_axi_arvalid - - - - - ARREADY - - - s_axi_arready - - - - - RDATA - - - s_axi_rdata - - - - - RRESP - - - s_axi_rresp - - - - - RVALID - - - s_axi_rvalid - - - - - RREADY - - - s_axi_rready - - - - - - s_axi_aclk - - - - - - - CLK - - - s_axi_aclk - - - - - - ASSOCIATED_BUSIF - s_axi - - - ASSOCIATED_RESET - s_axi_aresetn - - - - - s_axi_aresetn - - - - - - - RST - - - s_axi_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - s0_axis_aclk - - - - - - - CLK - - - s0_axis_aclk - - - - - - ASSOCIATED_BUSIF - s0_axis - - - ASSOCIATED_RESET - s0_axis_aresetn - - - - - s0_axis_aresetn - - - - - - - RST - - - s0_axis_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - aclk - - - - - - - CLK - - - aclk - - - - - - ASSOCIATED_BUSIF - m_axis:s1_axis - - - ASSOCIATED_RESET - aresetn - - - - - aresetn - - - - - - - RST - - - aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - - - s_axi - - reg0 - 0 - 64 - 32 - register - - - - - - - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis - Verilog - axis_signal_gen_v5 - - xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset - - - xilinx_anylanguagesynthesis_view_fileset - - - - viewChecksum - 6b2d8ce5 - - - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - Verilog - axis_signal_gen_v5 - - xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - - - viewChecksum - 6b2d8ce5 - - - - - xilinx_xpgui - UI Layout - :vivado.xilinx.com:xgui.ui - - xilinx_xpgui_view_fileset - - - - viewChecksum - e51fb623 - - - - - - - s_axi_aclk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_aresetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axi_awaddr - - in - - 5 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axi_awprot - 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xilinx_anylanguagebehavioralsimulation - - - - - - aclk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - aresetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s1_axis_tdata - - in - - 159 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s1_axis_tvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s1_axis_tready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m_axis_tready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 1 - - - - - m_axis_tvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m_axis_tdata - - out - - 255 - 0 - - - - std_logic_vector - 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/home/lstefana/v20.2/ip/axis_signal_gen_v5 - /home/lstefana/v20.2/ip/axis_signal_gen_v5 - /home/lstefana/v20.2/ip/axis_signal_gen_v5 - /home/lstefana/v20.2/ip/axis_signal_gen_v5 - /home/lstefana/v20.2/ip/axis_signal_gen_v5 - /home/lstefana/v20.2/ip/axis_signal_gen_v5 - /home/lstefana/v20.2/ip/axis_signal_gen_v5 - /home/lstefana/v20.2/ip/axis_signal_gen_v5 - /home/lstefana/v20.2/ip/axis_signal_gen_v5 - /home/lstefana/v20.2/ip/axis_signal_gen_v5 - /home/lstefana/v20.2/ip/axis_signal_gen_v5 - /home/lstefana/v20.2/ip/axis_signal_gen_v5 - /home/lstefana/v20.2/ip/axis_signal_gen_v5 - /home/lstefana/v20.2/ip/axis_signal_gen_v5 - /home/lstefana/v20.2/ip/axis_signal_gen_v5 - /home/lstefana/v20.2/ip/axis_signal_gen_v5 - /home/lstefana/v20.2/ip/axis_signal_gen_v5 - - - - 2020.2 - - - - - - - - - diff --git a/qick/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.veo b/qick/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.veo deleted file mode 100644 index 7cfbd51..0000000 --- a/qick/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.veo +++ /dev/null @@ -1,85 +0,0 @@ -// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -// IP VLNV: xilinx.com:ip:axi_vip:1.1 -// IP Revision: 8 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -axi_mst_0 your_instance_name ( - .aclk(aclk), // input wire aclk - .aresetn(aresetn), // input wire aresetn - .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr - .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot - .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid - .m_axi_awready(m_axi_awready), // input wire m_axi_awready - .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata - .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb - .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid - .m_axi_wready(m_axi_wready), // input wire m_axi_wready - .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp - .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid - .m_axi_bready(m_axi_bready), // output wire m_axi_bready - .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr - .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot - .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid - .m_axi_arready(m_axi_arready), // input wire m_axi_arready - .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata - .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp - .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid - .m_axi_rready(m_axi_rready) // output wire m_axi_rready -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file axi_mst_0.v when simulating -// the core, axi_mst_0. When compiling the wrapper file, be sure to -// reference the Verilog simulation library. - diff --git a/qick/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.vho b/qick/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.vho deleted file mode 100644 index a53be60..0000000 --- a/qick/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.vho +++ /dev/null @@ -1,115 +0,0 @@ --- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:axi_vip:1.1 --- IP Revision: 8 - --- The following code must appear in the VHDL architecture header. - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT axi_mst_0 - PORT ( - aclk : IN STD_LOGIC; - aresetn : IN STD_LOGIC; - m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - m_axi_awvalid : OUT STD_LOGIC; - m_axi_awready : IN STD_LOGIC; - m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - m_axi_wvalid : OUT STD_LOGIC; - m_axi_wready : IN STD_LOGIC; - m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - m_axi_bvalid : IN STD_LOGIC; - m_axi_bready : OUT STD_LOGIC; - m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - m_axi_arvalid : OUT STD_LOGIC; - m_axi_arready : IN STD_LOGIC; - m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - m_axi_rvalid : IN STD_LOGIC; - m_axi_rready : OUT STD_LOGIC - ); -END COMPONENT; --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : axi_mst_0 - PORT MAP ( - aclk => aclk, - aresetn => aresetn, - m_axi_awaddr => m_axi_awaddr, - m_axi_awprot => m_axi_awprot, - m_axi_awvalid => m_axi_awvalid, - m_axi_awready => m_axi_awready, - m_axi_wdata => m_axi_wdata, - m_axi_wstrb => m_axi_wstrb, - m_axi_wvalid => m_axi_wvalid, - m_axi_wready => m_axi_wready, - m_axi_bresp => m_axi_bresp, - m_axi_bvalid => m_axi_bvalid, - m_axi_bready => m_axi_bready, - m_axi_araddr => m_axi_araddr, - m_axi_arprot => m_axi_arprot, - m_axi_arvalid => m_axi_arvalid, - m_axi_arready => m_axi_arready, - m_axi_rdata => m_axi_rdata, - m_axi_rresp => m_axi_rresp, - m_axi_rvalid => m_axi_rvalid, - m_axi_rready => m_axi_rready - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file axi_mst_0.vhd when simulating --- the core, axi_mst_0. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/qick/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.xci b/qick/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.xci deleted file mode 100644 index ac9cf04..0000000 --- a/qick/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.xci +++ /dev/null @@ -1,200 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - axi_mst_0 - - - ACTIVE_LOW - - 100000000 - 0 - 0 - 0.000 - 32 - 0 - 0 - 0 - - 32 - 100000000 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 32 - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 0 - 2 - 32 - 0 - 0 - 0 - 32 - 0 - 0 - 32 - 0 - 0 - 0 - axi_mst_0 - 32 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 0 - 0 - 1 - 0 - MASTER - AXI4LITE - READ_WRITE - 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- in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - m_axi_bvalid - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - true - - - - - - m_axi_bready - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - m_axi_arid - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_araddr - - out - - 31 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - m_axi_arlen - - out - - 7 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_arsize - - out - - 2 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - 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xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_arvalid - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - m_axi_arready - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - true - - - - - - m_axi_rid - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - m_axi_rdata - - in - - 31 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - true - - - - - - m_axi_rresp - - in - - 1 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - true - - - - - - m_axi_rlast - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - m_axi_ruser - - in - - 0 - 0 - - - - std_logic_vector - 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AXIMM Socket for Write - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - rd_socket - - - - - - - 1 - - - - - - - C_AXI_PROTOCOL - 2 - - - C_AXI_INTERFACE_MODE - 0 - - - C_AXI_ADDR_WIDTH - 32 - - - C_AXI_WDATA_WIDTH - 32 - - - C_AXI_RDATA_WIDTH - 32 - - - C_AXI_WID_WIDTH - 0 - - - C_AXI_RID_WIDTH - 0 - - - C_AXI_AWUSER_WIDTH - 0 - - - C_AXI_ARUSER_WIDTH - 0 - - - C_AXI_WUSER_WIDTH - 0 - - - C_AXI_RUSER_WIDTH - 0 - - - C_AXI_BUSER_WIDTH - 0 - - - C_AXI_SUPPORTS_NARROW - 0 - - - C_AXI_HAS_BURST - 0 - - - C_AXI_HAS_LOCK - 0 - - - C_AXI_HAS_CACHE - 0 - - - C_AXI_HAS_REGION - 0 - - - C_AXI_HAS_PROT - 1 - - - C_AXI_HAS_QOS - 0 - - - C_AXI_HAS_WSTRB - 1 - - - C_AXI_HAS_BRESP - 1 - - - C_AXI_HAS_RRESP - 1 - - - C_AXI_HAS_ARESETN - 1 - - - - - - choice_list_04fafd91 - AXI3 - AXI4 - AXI4LITE - - - choice_list_6240decd - READ_ONLY - READ_WRITE - WRITE_ONLY - - - choice_list_642e7122 - MASTER - PASS_THROUGH - SLAVE - - - choice_list_99ba8646 - 32 - 64 - - - choice_list_9d8b0d81 - ACTIVE_HIGH - ACTIVE_LOW - - - choice_pairs_0fc128e8 - 0 - 0 - - - - - xilinx_veriloginstantiationtemplate_view_fileset - - axi_mst_0.vho - vhdlTemplate - - - axi_mst_0.veo - verilogTemplate - - - - xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset - - hdl/axi_infrastructure_v1_1_0.vh - verilogSource - true - axi_infrastructure_v1_1_0 - - - hdl/axi_infrastructure_v1_1_vl_rfs.v - verilogSource - axi_infrastructure_v1_1_0 - - - - - - - - - - - xilinx_verilogsynthesis_view_fileset - - hdl/axi_vip_v1_1_vlsyn_rfs.sv - systemVerilogSource - axi_vip_v1_1_8 - - - - xilinx_synthesisconstraints_view_fileset - - axi_mst_0_ooc.xdc - xdc - USED_IN_implementation - USED_IN_out_of_context - USED_IN_synthesis - - - - xilinx_verilogsynthesiswrapper_view_fileset - - synth/axi_mst_0.sv - systemVerilogSource - xil_defaultlib - - - - xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset - - hdl/axi_infrastructure_v1_1_0.vh - verilogSource - USED_IN_ipstatic - true - axi_infrastructure_v1_1_0 - - - hdl/axi_infrastructure_v1_1_vl_rfs.v - verilogSource - USED_IN_ipstatic - axi_infrastructure_v1_1_0 - - - - - - - - - - - xilinx_verilogbehavioralsimulation_view_fileset - - sim/axi_mst_0_pkg.sv - systemVerilogSource - - - hdl/axi_vip_v1_1_vl_rfs.sv - systemVerilogSource - USED_IN_ipstatic - axi_vip_v1_1_8 - - - - xilinx_systemcsimulation_view_fileset - - sysc/axi_vip.cpp - systemCSource - axi_vip_v1_1_8 - - - sysc/axi_vip.h - systemCSource - true - axi_vip_v1_1_8 - - - - xilinx_verilogsimulationwrapper_view_fileset - - sim/axi_mst_0.sv - systemVerilogSource - xil_defaultlib - - - - xilinx_systemcsimulationwrapper_view_fileset - - sim/axi_mst_0_sc.h - systemCSource - true - - - sim/axi_mst_0_sc.cpp - systemCSource - - - sim/axi_mst_0.h - systemCSource - true - - - sim/axi_mst_0.cpp - systemCSource - - - sim/axi_mst_0_stub.sv - systemVerilogSource - - - - xilinx_versioninformation_view_fileset - - doc/axi_vip_v1_1_changelog.txt - text - axi_vip_v1_1_8 - - - - xilinx_externalfiles_view_fileset - - axi_mst_0.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - axi_mst_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - axi_mst_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - axi_mst_0_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - axi_mst_0_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - - The AXI Verification IP. - - - Component_Name - Component Name - axi_mst_0 - - - PROTOCOL - PROTOCOL - AXI4LITE - - - READ_WRITE_MODE - READ_WRITE MODE - READ_WRITE - - - INTERFACE_MODE - INTERFACE MODE - MASTER - - - ADDR_WIDTH - ADDRESS WIDTH - 32 - - - DATA_WIDTH - DATA WIDTH - 32 - - - ID_WIDTH - ID WIDTH - 0 - - - - false - - - - - - AWUSER_WIDTH - AWUSER WIDTH - 0 - - - - false - - - - - - ARUSER_WIDTH - ARUSER WIDTH - 0 - - - - false - - - - - - RUSER_WIDTH - RUSER WIDTH - 0 - - - - false - - - - - - WUSER_WIDTH - WUSER WIDTH - 0 - - - - false - - - - - - BUSER_WIDTH - BUSER WIDTH - 0 - - - - false - - - - - - WUSER_BITS_PER_BYTE - WUSER BITS PER BYTE - 0 - - - - false - - - - - - RUSER_BITS_PER_BYTE - RUSER BITS PER BYTE - 0 - - - - false - - - - - - HAS_USER_BITS_PER_BYTE - HAS USER_BITS_PER_BYTE - 0 - - - - false - - - - - - SUPPORTS_NARROW - SUPPORTS NARROW - 0 - - - - false - - - - - - HAS_SIZE - HAS SIZE - 0 - - - - false - - - - - - HAS_BURST - HAS BURST - 0 - - - - false - - - - - - HAS_LOCK - HAS LOCK - 0 - - - - false - - - - - - HAS_CACHE - HAS CACHE - 0 - - - - false - - - - - - HAS_REGION - HAS REGION - 0 - - - - false - - - - - - HAS_QOS - HAS QOS - 0 - - - - false - - - - - - HAS_PROT - HAS PROT - 1 - - - HAS_WSTRB - HAS WSTRB - 1 - - - HAS_BRESP - HAS BRESP - 1 - - - HAS_RRESP - HAS RRESP - 1 - - - HAS_ACLKEN - HAS ACLKEN - 0 - - - HAS_ARESETN - HAS ARESETN - 1 - - - - - AXI Verification IP - - xtlm - - 8 - true - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2020.2 - - - - - - - - - - diff --git a/qick/firmware/ip/axis_signal_gen_v5/src/axi_slv.vhd b/qick/firmware/ip/axis_signal_gen_v5/src/axi_slv.vhd deleted file mode 100644 index c60ea98..0000000 --- a/qick/firmware/ip/axis_signal_gen_v5/src/axi_slv.vhd +++ /dev/null @@ -1,516 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity axi_slv is - Generic - ( - DATA_WIDTH : integer := 32; - ADDR_WIDTH : integer := 6 - ); - Port - ( - aclk : in std_logic; - aresetn : in std_logic; - - -- Write Address Channel. - awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); - awprot : in std_logic_vector(2 downto 0); - awvalid : in std_logic; - awready : out std_logic; - - -- Write Data Channel. - wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); - wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); - wvalid : in std_logic; - wready : out std_logic; - - -- Write Response Channel. - bresp : out std_logic_vector(1 downto 0); - bvalid : out std_logic; - bready : in std_logic; - - -- Read Address Channel. - araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); - arprot : in std_logic_vector(2 downto 0); - arvalid : in std_logic; - arready : out std_logic; - - -- Read Data Channel. - rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); - rresp : out std_logic_vector(1 downto 0); - rvalid : out std_logic; - rready : in std_logic; - - -- Registers. - START_ADDR_REG : out std_logic_vector (31 downto 0); - WE_REG : out std_logic - ); -end axi_slv; - -architecture rtl of axi_slv is - - -- AXI4LITE signals - signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); - signal axi_awready : std_logic; - signal axi_wready : std_logic; - signal axi_bresp : std_logic_vector(1 downto 0); - signal axi_bvalid : std_logic; - signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); - signal axi_arready : std_logic; - signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); - signal axi_rresp : std_logic_vector(1 downto 0); - signal axi_rvalid : std_logic; - - -- Example-specific design signals - -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH - -- ADDR_LSB is used for addressing 32/64 bit registers/memories - -- ADDR_LSB = 2 for 32 bits (n downto 2) - -- ADDR_LSB = 3 for 64 bits (n downto 3) - constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; - constant OPT_MEM_ADDR_BITS : integer := 3; - ------------------------------------------------ - ---- Signals for user logic register space example - -------------------------------------------------- - ---- Number of Slave Registers 16 - signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg_rden : std_logic; - signal slv_reg_wren : std_logic; - signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); - signal byte_index : integer; - signal aw_en : std_logic; - -begin - -- I/O Connections assignments - - awreadY <= axi_awready; - wready <= axi_wready; - bresp <= axi_bresp; - bvalid <= axi_bvalid; - arreadY <= axi_arready; - rdata <= axi_rdata; - rresp <= axi_rresp; - rvalid <= axi_rvalid; - -- Implement axi_awready generation - -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is - -- de-asserted when reset is low. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_awready <= '0'; - aw_en <= '1'; - else - if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then - -- slave is ready to accept write address when - -- there is a valid write address and write data - -- on the write address and data bus. This design - -- expects no outstanding transactions. - axi_awready <= '1'; - aw_en <= '0'; - elsif (bready = '1' and axi_bvalid = '1') then - aw_en <= '1'; - axi_awready <= '0'; - else - axi_awready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement axi_awaddr latching - -- This process is used to latch the address when both - -- S_AXI_AWVALID and S_AXI_WVALID are valid. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_awaddr <= (others => '0'); - else - if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then - -- Write Address latching - axi_awaddr <= awaddr; - end if; - end if; - end if; - end process; - - -- Implement axi_wready generation - -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is - -- de-asserted when reset is low. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_wready <= '0'; - else - if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then - -- slave is ready to accept write data when - -- there is a valid write address and write data - -- on the write address and data bus. This design - -- expects no outstanding transactions. - axi_wready <= '1'; - else - axi_wready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement memory mapped register select and write logic generation - -- The write data is accepted and written to memory mapped registers when - -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to - -- select byte enables of slave registers while writing. - -- These registers are cleared when reset (active low) is applied. - -- Slave register write enable is asserted when valid address and data are available - -- and the slave is ready to accept the write address and write data. - slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; - - process (aclk) - variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); - begin - if rising_edge(aclk) then - if aresetn = '0' then - slv_reg0 <= (others => '0'); - slv_reg1 <= (others => '0'); - slv_reg2 <= (others => '0'); - slv_reg3 <= (others => '0'); - slv_reg4 <= (others => '0'); - slv_reg5 <= (others => '0'); - slv_reg6 <= (others => '0'); - slv_reg7 <= (others => '0'); - slv_reg8 <= (others => '0'); - slv_reg9 <= (others => '0'); - slv_reg10 <= (others => '0'); - slv_reg11 <= (others => '0'); - slv_reg12 <= (others => '0'); - slv_reg13 <= (others => '0'); - slv_reg14 <= (others => '0'); - slv_reg15 <= (others => '0'); - else - loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); - if (slv_reg_wren = '1') then - case loc_addr is - when b"0000" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 0 - slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0001" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 1 - slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0010" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 2 - slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0011" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 3 - slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0100" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 4 - slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0101" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 5 - slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0110" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 6 - slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0111" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 7 - slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1000" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 8 - slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1001" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 9 - slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1010" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 10 - slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1011" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 11 - slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1100" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 12 - slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1101" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 13 - slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1110" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 14 - slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1111" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 15 - slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when others => - slv_reg0 <= slv_reg0; - slv_reg1 <= slv_reg1; - slv_reg2 <= slv_reg2; - slv_reg3 <= slv_reg3; - slv_reg4 <= slv_reg4; - slv_reg5 <= slv_reg5; - slv_reg6 <= slv_reg6; - slv_reg7 <= slv_reg7; - slv_reg8 <= slv_reg8; - slv_reg9 <= slv_reg9; - slv_reg10 <= slv_reg10; - slv_reg11 <= slv_reg11; - slv_reg12 <= slv_reg12; - slv_reg13 <= slv_reg13; - slv_reg14 <= slv_reg14; - slv_reg15 <= slv_reg15; - end case; - end if; - end if; - end if; - end process; - - -- Implement write response logic generation - -- The write response and response valid signals are asserted by the slave - -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. - -- This marks the acceptance of address and indicates the status of - -- write transaction. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_bvalid <= '0'; - axi_bresp <= "00"; --need to work more on the responses - else - if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then - axi_bvalid <= '1'; - axi_bresp <= "00"; - elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) - axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) - end if; - end if; - end if; - end process; - - -- Implement axi_arready generation - -- axi_arready is asserted for one S_AXI_ACLK clock cycle when - -- S_AXI_ARVALID is asserted. axi_awready is - -- de-asserted when reset (active low) is asserted. - -- The read address is also latched when S_AXI_ARVALID is - -- asserted. axi_araddr is reset to zero on reset assertion. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_arready <= '0'; - axi_araddr <= (others => '1'); - else - if (axi_arready = '0' and arvalid = '1') then - -- indicates that the slave has acceped the valid read address - axi_arready <= '1'; - -- Read Address latching - axi_araddr <= araddr; - else - axi_arready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement axi_arvalid generation - -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_ARVALID and axi_arready are asserted. The slave registers - -- data are available on the axi_rdata bus at this instance. The - -- assertion of axi_rvalid marks the validity of read data on the - -- bus and axi_rresp indicates the status of read transaction.axi_rvalid - -- is deasserted on reset (active low). axi_rresp and axi_rdata are - -- cleared to zero on reset (active low). - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_rvalid <= '0'; - axi_rresp <= "00"; - else - if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then - -- Valid read data is available at the read data bus - axi_rvalid <= '1'; - axi_rresp <= "00"; -- 'OKAY' response - elsif (axi_rvalid = '1' and rready = '1') then - -- Read data is accepted by the master - axi_rvalid <= '0'; - end if; - end if; - end if; - end process; - - -- Implement memory mapped register select and read logic generation - -- Slave register read enable is asserted when valid address is available - -- and the slave is ready to accept the read address. - slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; - - process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) - variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); - begin - -- Address decoding for reading registers - loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); - case loc_addr is - when b"0000" => - reg_data_out <= slv_reg0; - when b"0001" => - reg_data_out <= slv_reg1; - when b"0010" => - reg_data_out <= slv_reg2; - when b"0011" => - reg_data_out <= slv_reg3; - when b"0100" => - reg_data_out <= slv_reg4; - when b"0101" => - reg_data_out <= slv_reg5; - when b"0110" => - reg_data_out <= slv_reg6; - when b"0111" => - reg_data_out <= slv_reg7; - when b"1000" => - reg_data_out <= slv_reg8; - when b"1001" => - reg_data_out <= slv_reg9; - when b"1010" => - reg_data_out <= slv_reg10; - when b"1011" => - reg_data_out <= slv_reg11; - when b"1100" => - reg_data_out <= slv_reg12; - when b"1101" => - reg_data_out <= slv_reg13; - when b"1110" => - reg_data_out <= slv_reg14; - when b"1111" => - reg_data_out <= slv_reg15; - when others => - reg_data_out <= (others => '0'); - end case; - end process; - - -- Output register or memory read data - process( aclk ) is - begin - if (rising_edge (aclk)) then - if ( aresetn = '0' ) then - axi_rdata <= (others => '0'); - else - if (slv_reg_rden = '1') then - -- When there is a valid read address (S_AXI_ARVALID) with - -- acceptance of read address by the slave (axi_arready), - -- output the read dada - -- Read address mux - axi_rdata <= reg_data_out; -- register read data - end if; - end if; - end if; - end process; - - -- Register Map. - -- 0 : START_ADDR_REG : 32-bit. Start address to write into memory. - -- 1 : WE_REG : 1-bit. Enable write into memory. - - -- Output Registers. - START_ADDR_REG <= slv_reg0; - WE_REG <= slv_reg1(0); - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v5/src/axis_signal_gen_v5.v b/qick/firmware/ip/axis_signal_gen_v5/src/axis_signal_gen_v5.v deleted file mode 100644 index 240bff6..0000000 --- a/qick/firmware/ip/axis_signal_gen_v5/src/axis_signal_gen_v5.v +++ /dev/null @@ -1,198 +0,0 @@ -// Signal Generator V4. -// s_axi_aclk : clock for s_axi_* -// s0_axis_aclk : clock for s0_axis_* -// aclk : clock for s1_axis_* and m_axis_* -// -module axis_signal_gen_v5 - ( - // AXI Slave I/F for configuration. - s_axi_aclk , - s_axi_aresetn , - - s_axi_awaddr , - s_axi_awprot , - s_axi_awvalid , - s_axi_awready , - - s_axi_wdata , - s_axi_wstrb , - s_axi_wvalid , - s_axi_wready , - - s_axi_bresp , - s_axi_bvalid , - s_axi_bready , - - s_axi_araddr , - s_axi_arprot , - s_axi_arvalid , - s_axi_arready , - - s_axi_rdata , - s_axi_rresp , - s_axi_rvalid , - s_axi_rready , - - // AXIS Slave to load memory samples. - s0_axis_aclk , - s0_axis_aresetn , - s0_axis_tdata , - s0_axis_tvalid , - s0_axis_tready , - - // s1_* and m_* reset/clock. - aclk , - aresetn , - - // AXIS Slave to queue waveforms. - s1_axis_tdata , - s1_axis_tvalid , - s1_axis_tready , - - // AXIS Master for output. - m_axis_tready , - m_axis_tvalid , - m_axis_tdata - ); - -/**************/ -/* Parameters */ -/**************/ -parameter N = 12; - -// Number of parallel dds blocks. -parameter [31:0] N_DDS = 16; - -/*********/ -/* Ports */ -/*********/ -input s_axi_aclk; -input s_axi_aresetn; - -input [5:0] s_axi_awaddr; -input [2:0] s_axi_awprot; -input s_axi_awvalid; -output s_axi_awready; - -input [31:0] s_axi_wdata; -input [3:0] s_axi_wstrb; -input s_axi_wvalid; -output s_axi_wready; - -output [1:0] s_axi_bresp; -output s_axi_bvalid; -input s_axi_bready; - -input [5:0] s_axi_araddr; -input [2:0] s_axi_arprot; -input s_axi_arvalid; -output s_axi_arready; - -output [31:0] s_axi_rdata; -output [1:0] s_axi_rresp; -output s_axi_rvalid; -input s_axi_rready; - -input s0_axis_aclk; -input s0_axis_aresetn; -input [31:0] s0_axis_tdata; -input s0_axis_tvalid; -output s0_axis_tready; - -input aresetn; -input aclk; - -input [159:0] s1_axis_tdata; -input s1_axis_tvalid; -output s1_axis_tready; - -input m_axis_tready; -output m_axis_tvalid; -output [N_DDS*16-1:0] m_axis_tdata; - -/********************/ -/* Internal signals */ -/********************/ -// Registers. -wire [31:0] START_ADDR_REG; -wire WE_REG; - - -/**********************/ -/* Begin Architecture */ -/**********************/ -// AXI Slave. -axi_slv axi_slv_i - ( - .aclk (s_axi_aclk ), - .aresetn (s_axi_aresetn ), - - // Write Address Channel. - .awaddr (s_axi_awaddr ), - .awprot (s_axi_awprot ), - .awvalid (s_axi_awvalid ), - .awready (s_axi_awready ), - - // Write Data Channel. - .wdata (s_axi_wdata ), - .wstrb (s_axi_wstrb ), - .wvalid (s_axi_wvalid ), - .wready (s_axi_wready ), - - // Write Response Channel. - .bresp (s_axi_bresp ), - .bvalid (s_axi_bvalid ), - .bready (s_axi_bready ), - - // Read Address Channel. - .araddr (s_axi_araddr ), - .arprot (s_axi_arprot ), - .arvalid (s_axi_arvalid ), - .arready (s_axi_arready ), - - // Read Data Channel. - .rdata (s_axi_rdata ), - .rresp (s_axi_rresp ), - .rvalid (s_axi_rvalid ), - .rready (s_axi_rready ), - - // Registers. - .START_ADDR_REG (START_ADDR_REG ), - .WE_REG (WE_REG ) - ); - -signal_gen_top - #( - .N (N ), - .N_DDS (N_DDS ) - ) - signal_gen_top_i - ( - // Reset and clock. - .aresetn (aresetn ), - .aclk (aclk ), - - // AXIS Slave to load memory samples. - .s0_axis_aresetn (s0_axis_aresetn ), - .s0_axis_aclk (s0_axis_aclk ), - .s0_axis_tdata_i (s0_axis_tdata ), - .s0_axis_tvalid_i (s0_axis_tvalid ), - .s0_axis_tready_o (s0_axis_tready ), - - // AXIS Slave to queue waveforms. - .s1_axis_tdata_i (s1_axis_tdata ), - .s1_axis_tvalid_i (s1_axis_tvalid ), - .s1_axis_tready_o (s1_axis_tready ), - - // M_AXIS for output. - .m_axis_tready_i (m_axis_tready ), - .m_axis_tvalid_o (m_axis_tvalid ), - .m_axis_tdata_o (m_axis_tdata ), - - // Registers. - .START_ADDR_REG (START_ADDR_REG ), - .WE_REG (WE_REG ) - ); - -endmodule - diff --git a/qick/firmware/ip/axis_signal_gen_v5/src/bram.v b/qick/firmware/ip/axis_signal_gen_v5/src/bram.v deleted file mode 100644 index 018317e..0000000 --- a/qick/firmware/ip/axis_signal_gen_v5/src/bram.v +++ /dev/null @@ -1,33 +0,0 @@ -module bram (clk,ena,wea,addra,dia,doa); - -// Memory address size. -parameter N = 16; -// Data width. -parameter B = 16; - -input clk; -input ena; -input wea; -input [N-1:0] addra; -input [B-1:0] dia; -output [B-1:0] doa; - -// Ram type. -reg [B-1:0] RAM [0:2**N-1]; -reg [B-1:0] doa; - -always @(posedge clk) -begin - if (ena) - begin - if (wea) begin - RAM[addra] <= dia; - end - else begin - doa <= RAM[addra]; - end - end -end - -endmodule - diff --git a/qick/firmware/ip/axis_signal_gen_v5/src/ctrl.sv b/qick/firmware/ip/axis_signal_gen_v5/src/ctrl.sv deleted file mode 100644 index 7cc6a09..0000000 --- a/qick/firmware/ip/axis_signal_gen_v5/src/ctrl.sv +++ /dev/null @@ -1,466 +0,0 @@ -//Format of waveform interface: -// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| -// | 159 .. 149 | 148 | 147 | 146 | 145 .. 144 | 143 .. 128 | 127 .. 112 | 111 .. 96 | 95 .. 80 | 79 .. 64 | 63 .. 32 | 31 .. 0 | -// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| -// | xxxx | phrst | stdysel | mode | outsel | nsamp | xxxx | gain | xxxx | addr | phase | freq | -// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| -// freq : 32 bits -// phase : 32 bits -// addr : 16 bits -// gain : 16 bits -// nsamp : 16 bits -// outsel : 2 bits -// mode : 1 bit -// stdysel : 1 bit -// phrst : 1 bit -module ctrl ( - // Reset and clock. - rstn , - clk , - - // Fifo interface. - fifo_rd_en_o , - fifo_empty_i , - fifo_dout_i , - - // dds control. - dds_ctrl_o , - - // memory control. - mem_addr_o , - - // gain. - gain_o , - - // Output source selection. - src_o , - - // Steady value selection. - stdy_o , - - // Output enable. - en_o ); - -// Memory address size. -parameter N = 16; - -// Number of parallel dds blocks. -parameter [31:0] N_DDS = 16; - -// Ports. -input rstn; -input clk; -output fifo_rd_en_o; -input fifo_empty_i; -input [159:0] fifo_dout_i; -output [N_DDS*72-1:0] dds_ctrl_o; -output [N-1:0] mem_addr_o; -output [15:0] gain_o; -output [1:0] src_o; -output stdy_o; -output en_o; - -// States. -typedef enum { READ_ST , - CNT_ST - } state_t; - -// State register. -(* fsm_encoding = "one_hot" *) state_t state; - -// Fifo dout register. -reg [159:0] fifo_dout_r; - -// Non-stop counter for time calculation (adds N_DDS samples each clock tick). -reg [15:0] cnt_n; -reg [15:0] cnt_n_reg; - -// Pinc/phase. -wire [31:0] pinc_int; -reg [31:0] pinc_r1; -wire [31:0] pinc_N; -reg [31:0] pinc_N_r1; -reg [31:0] pinc_N_r2; -reg [31:0] pinc_N_r3; -reg [31:0] pinc_N_r4; -reg [31:0] pinc_N_r5; -wire [31:0] pinc_Nm; -reg [31:0] pinc_Nm_r1; -reg [31:0] pinc_Nm_r2; -reg [31:0] pinc_Nm_r3; - -wire [31:0] phase_int; -reg [31:0] phase_r1; -reg [31:0] phase_r2; -reg [31:0] phase_r3; -reg [31:0] phase_r4; -wire [31:0] phase_0; -reg [31:0] phase_0_r1; - -// Phase vectors. -wire [31:0] phase_v0 [0:N_DDS-1]; -reg [31:0] phase_v0_r1 [0:N_DDS-1]; -reg [31:0] phase_v0_r2 [0:N_DDS-1]; -reg [31:0] phase_v0_r3 [0:N_DDS-1]; -reg [31:0] phase_v0_r4 [0:N_DDS-1]; -wire [31:0] phase_v1 [0:N_DDS-1]; -reg [31:0] phase_v1_r1 [0:N_DDS-1]; - -// sync. -reg sync_reg; -reg sync_reg_r1; -reg sync_reg_r2; -reg sync_reg_r3; -reg sync_reg_r4; -reg sync_reg_r5; -reg sync_reg_r6; - -// Address. -wire [15:0] addr_int; -reg [15:0] addr_cnt; -reg [15:0] addr_cnt_r1; -reg [15:0] addr_cnt_r2; -reg [15:0] addr_cnt_r3; -reg [15:0] addr_cnt_r4; -reg [15:0] addr_cnt_r5; - -// Gain. -wire [15:0] gain_int; -reg [15:0] gain_r1; -reg [15:0] gain_r2; -reg [15:0] gain_r3; -reg [15:0] gain_r4; -reg [15:0] gain_r5; -reg [15:0] gain_r6; - -// Number of samples. -wire [15:0] nsamp_int; - -// Output selection. -wire [1:0] outsel_int; -reg [1:0] outsel_r1; -reg [1:0] outsel_r2; -reg [1:0] outsel_r3; -reg [1:0] outsel_r4; -reg [1:0] outsel_r5; -reg [1:0] outsel_r6; - -// Mode. -wire mode_int; - -// Steady value selection. -wire stdysel_int; -reg stdysel_r1; -reg stdysel_r2; -reg stdysel_r3; -reg stdysel_r4; -reg stdysel_r5; -reg stdysel_r6; - -// Load enable flag. -wire load_int; -reg load_r; - -// Fifo Read Enable. -reg rd_en_int; -reg rd_en_r1; -reg rd_en_r2; - -// Counter. -reg [31:0] cnt; - -// Output enable register. -reg en_reg; -reg en_reg_r1; -reg en_reg_r2; -reg en_reg_r3; -reg en_reg_r4; -reg en_reg_r5; -reg en_reg_r6; -reg en_reg_r7; - -// Registers. -always @(posedge clk) begin - if (~rstn) begin - // State register. - state <= READ_ST; - - // Fifo dout register. - fifo_dout_r <= 0; - - // Non-stop counter for time calculation. - cnt_n <= 0; - cnt_n_reg <= 0; - - // Pinc/phase/sync. - pinc_r1 <= 0; - pinc_N_r1 <= 0; - pinc_N_r2 <= 0; - pinc_N_r3 <= 0; - pinc_N_r4 <= 0; - pinc_N_r5 <= 0; - pinc_Nm_r1 <= 0; - pinc_Nm_r2 <= 0; - pinc_Nm_r3 <= 0; - - phase_r1 <= 0; - phase_r2 <= 0; - phase_r3 <= 0; - phase_r4 <= 0; - phase_0_r1 <= 0; - - sync_reg <= 0; - sync_reg_r1 <= 0; - sync_reg_r2 <= 0; - sync_reg_r3 <= 0; - sync_reg_r4 <= 0; - sync_reg_r5 <= 0; - sync_reg_r6 <= 0; - - // Address. - addr_cnt <= 0; - addr_cnt_r1 <= 0; - addr_cnt_r2 <= 0; - addr_cnt_r3 <= 0; - addr_cnt_r4 <= 0; - addr_cnt_r5 <= 0; - - // Gain. - gain_r1 <= 0; - gain_r2 <= 0; - gain_r3 <= 0; - gain_r4 <= 0; - gain_r5 <= 0; - gain_r6 <= 0; - - // Output selection. - outsel_r1 <= 0; - outsel_r2 <= 0; - outsel_r3 <= 0; - outsel_r4 <= 0; - outsel_r5 <= 0; - outsel_r6 <= 0; - - // Steady value selection. - stdysel_r1 <= 0; - stdysel_r2 <= 0; - stdysel_r3 <= 0; - stdysel_r4 <= 0; - stdysel_r5 <= 0; - stdysel_r6 <= 0; - - // Load enable flag. - load_r <= 0; - - // Fifo Read Enable. - rd_en_r1 <= 0; - rd_en_r2 <= 0; - - // Counter. - cnt <= 0; - - // Output enable register. - en_reg <= 0; - en_reg_r1 <= 0; - en_reg_r2 <= 0; - en_reg_r3 <= 0; - en_reg_r4 <= 0; - en_reg_r5 <= 0; - en_reg_r6 <= 0; - en_reg_r7 <= 0; - end - else begin - // State register. - case (state) - READ_ST: - if (mode_int || ~fifo_empty_i) - state <= CNT_ST; - CNT_ST: - if ( cnt == nsamp_int-2 ) - state <= READ_ST; - endcase - - // Fifo dout register. - if (load_r) - fifo_dout_r <= fifo_dout_i; - - // Non-stop counter for time calculation. - cnt_n <= cnt_n + N_DDS; - if (sync_reg) - cnt_n_reg <= cnt_n; - - // Pinc/phase/sync. - pinc_r1 <= pinc_int; - pinc_N_r1 <= pinc_N; - pinc_N_r2 <= pinc_N_r1; - pinc_N_r3 <= pinc_N_r2; - pinc_N_r4 <= pinc_N_r3; - pinc_N_r5 <= pinc_N_r4; - pinc_Nm_r1 <= pinc_Nm; - pinc_Nm_r2 <= pinc_Nm_r1; - pinc_Nm_r3 <= pinc_Nm_r2; - - phase_r1 <= phase_int; - phase_r2 <= phase_r1; - phase_r3 <= phase_r2; - phase_r4 <= phase_r3; - phase_0_r1 <= phase_0; - - sync_reg <= load_r; - sync_reg_r1 <= sync_reg; - sync_reg_r2 <= sync_reg_r1; - sync_reg_r3 <= sync_reg_r2; - sync_reg_r4 <= sync_reg_r3; - sync_reg_r5 <= sync_reg_r4; - sync_reg_r6 <= sync_reg_r5; - - // Address. - if (rd_en_r2) - addr_cnt <= addr_int; - else - addr_cnt <= addr_cnt + 1; - - addr_cnt_r1 <= addr_cnt; - addr_cnt_r2 <= addr_cnt_r1; - addr_cnt_r3 <= addr_cnt_r2; - addr_cnt_r4 <= addr_cnt_r3; - addr_cnt_r5 <= addr_cnt_r4; - - // Gain. - gain_r1 <= gain_int; - gain_r2 <= gain_r1; - gain_r3 <= gain_r2; - gain_r4 <= gain_r3; - gain_r5 <= gain_r4; - gain_r6 <= gain_r5; - - // Output selection. - outsel_r1 <= outsel_int; - outsel_r2 <= outsel_r1; - outsel_r3 <= outsel_r2; - outsel_r4 <= outsel_r3; - outsel_r5 <= outsel_r4; - outsel_r6 <= outsel_r5; - - // Steady value selection. - stdysel_r1 <= stdysel_int; - stdysel_r2 <= stdysel_r1; - stdysel_r3 <= stdysel_r2; - stdysel_r4 <= stdysel_r3; - stdysel_r5 <= stdysel_r3; - stdysel_r6 <= stdysel_r3; - - // Load enable flag. - load_r <= load_int; - - // Fifo Read Enable. - rd_en_r1 <= rd_en_int; - rd_en_r2 <= rd_en_r1; - - // Counter. - if (rd_en_int) - cnt <= 0; - else - cnt <= cnt + 1; - - // Output enable register. - if (~mode_int && rd_en_int) - if (~fifo_empty_i) - en_reg <= 1; - else - en_reg <= 0; - - en_reg_r1 <= en_reg; - en_reg_r2 <= en_reg_r1; - en_reg_r3 <= en_reg_r2; - en_reg_r4 <= en_reg_r3; - en_reg_r5 <= en_reg_r4; - en_reg_r6 <= en_reg_r5; - en_reg_r7 <= en_reg_r6; - - end -end - -// FSM outputs. -always_comb begin - // Default. - rd_en_int = 0; - - case (state) - READ_ST: - rd_en_int = 1; - - CNT_ST: - rd_en_int = 0; - endcase -end - -// Fifo output fields. -assign pinc_int = fifo_dout_r[31:0]; -assign phase_int = fifo_dout_r[63:32]; -assign addr_int = fifo_dout_r[79:64]; -assign gain_int = fifo_dout_r[111:96]; -assign nsamp_int = fifo_dout_r[143:128]; -assign outsel_int = fifo_dout_r[145:144]; -assign mode_int = fifo_dout_r[146]; -assign stdysel_int = fifo_dout_r[147]; - -// Frequency calculation. -assign pinc_N = pinc_r1*N_DDS; - -// Phase calculation. -assign pinc_Nm = pinc_r1*cnt_n_reg; -assign phase_0 = pinc_Nm_r3 + phase_r4; - -// Phase vectors. -generate -genvar i; - for (i=0; i < N_DDS; i = i + 1) begin : GEN_phase - // Registers. - always @(posedge clk) begin - if (~rstn) begin - // v0. - phase_v0_r1[i] <= 0; - phase_v0_r2[i] <= 0; - phase_v0_r3[i] <= 0; - phase_v0_r4[i] <= 0; - - // v1. - phase_v1_r1[i] <= 0; - end - else begin - // v0. - phase_v0_r1[i] <= phase_v0[i]; - phase_v0_r2[i] <= phase_v0_r1[i]; - phase_v0_r3[i] <= phase_v0_r2[i]; - phase_v0_r4[i] <= phase_v0_r3[i]; - - // v1. - phase_v1_r1[i] <= phase_v1[i]; - end - end - - // v0. - assign phase_v0[i] = pinc_r1*i; - - // v1. - assign phase_v1[i] = phase_v0_r4[i] + phase_0_r1; - - // dds_ctrl_o output. - assign dds_ctrl_o[i*72 +: 72] = {7'h00,sync_reg_r6,phase_v1_r1[i],pinc_N_r5}; - end -endgenerate - -// load_int. -assign load_int = rd_en_int & ~fifo_empty_i; - -// Assign outputs. -assign fifo_rd_en_o = rd_en_int; -assign mem_addr_o = addr_cnt_r5; -assign gain_o = gain_r6; -assign src_o = outsel_r6; -assign stdy_o = stdysel_r6; -assign en_o = en_reg_r7; - -endmodule - diff --git a/qick/firmware/ip/axis_signal_gen_v5/src/data_writer.vhd b/qick/firmware/ip/axis_signal_gen_v5/src/data_writer.vhd deleted file mode 100644 index cbf1912..0000000 --- a/qick/firmware/ip/axis_signal_gen_v5/src/data_writer.vhd +++ /dev/null @@ -1,226 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity data_writer is - Generic - ( - -- Number of tables. - NT : Integer := 16; - -- Address map of each table. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in STD_LOGIC; - clk : in STD_LOGIC; - - -- AXI Stream I/F. - s_axis_tready : out std_logic; - s_axis_tdata : in std_logic_vector(B-1 downto 0); - s_axis_tvalid : in std_logic; - - -- Memory I/F. - mem_en : out std_logic_vector (NT-1 downto 0); - mem_we : out std_logic; - mem_addr : out std_logic_vector (N-1 downto 0); - mem_di : out std_logic_vector (B-1 downto 0); - - -- Registers. - START_ADDR_REG : in std_logic_vector (31 downto 0); - WE_REG : in std_logic - ); -end data_writer; - -architecture rtl of data_writer is - --- Log2 of number of tables. -constant NT_LOG2 : Integer := Integer(ceil(log2(real(NT)))); - --- Synchronizer. -component synchronizer_n is - generic ( - N : Integer := 2 - ); - port ( - rstn : in std_logic; - clk : in std_logic; - data_in : in std_logic; - data_out : out std_logic - ); -end component; - --- State machine. -type fsm_state is ( INIT_ST , - READ_START_ADDR_ST , - WAIT_TVALID_ST , - RW_TDATA_ST ); -signal state : fsm_state; - -signal read_start_addr_state : std_logic; -signal rw_tdata_state : std_logic; - --- WE_REG_resync. -signal WE_REG_resync : std_logic; - --- Axis registers. -signal tready_i : std_logic; -signal tready_r : std_logic; -signal tdata_r : std_logic_vector(B-1 downto 0); -signal tdata_rr : std_logic_vector(B-1 downto 0); -signal tdata_rrr : std_logic_vector(B-1 downto 0); -signal tvalid_r : std_logic; -signal tvalid_rr : std_logic; -signal tvalid_rrr : std_logic; - --- Memory Enable. -signal mem_en_i : std_logic_vector (NT-1 downto 0); -signal mem_en_r : std_logic_vector (NT-1 downto 0); - --- Memory address space. -signal mem_addr_full : unsigned (NT_LOG2+N-1 downto 0); -signal mem_addr_low : unsigned (NT_LOG2-1 downto 0); -signal mem_addr_high : unsigned (N-1 downto 0); -signal mem_addr_high_r : unsigned (N-1 downto 0); - -begin - --- WE_REG_resync -WE_REG_resync_i : synchronizer_n - generic map ( - N => 2 - ) - port map ( - rstn => rstn , - clk => clk , - data_in => WE_REG , - data_out => WE_REG_resync - ); - --- Enable logic generation. -GEN: for I in 0 to NT-1 generate - - mem_en_i(I) <= '1' when mem_addr_low = to_unsigned(I,mem_addr_low'length) else - '0'; - -end generate GEN; - -process (clk) -begin - if ( rising_edge(clk) ) then - if (rstn = '0') then - -- Axis registers. - tready_r <= '0'; - tdata_r <= (others => '0'); - tdata_rr <= (others => '0'); - tdata_rrr <= (others => '0'); - tvalid_r <= '0'; - tvalid_rr <= '0'; - tvalid_rrr <= '0'; - - -- Memory address. - mem_addr_full <= (others => '0'); - mem_addr_high_r <= (others => '0'); - mem_en_r <= (others => '0'); - - else - -- Axis registers. - tready_r <= tready_i; - tdata_r <= s_axis_tdata; - tvalid_r <= s_axis_tvalid; - - -- Extra registers to account pipe of state machine. - tdata_rr <= tdata_r; - tdata_rrr <= tdata_rr; - tvalid_rr <= tvalid_r; - tvalid_rrr <= tvalid_rr; - - -- Memory address. - if ( read_start_addr_state = '1') then - mem_addr_full <= to_unsigned(to_integer(unsigned(START_ADDR_REG)),mem_addr_full'length); - elsif ( rw_tdata_state = '1' ) then - mem_addr_full <= mem_addr_full + 1; - end if; - mem_addr_high_r <= mem_addr_high; - mem_en_r <= mem_en_i; - - end if; - end if; -end process; - --- Address computation. -mem_addr_low <= mem_addr_full(NT_LOG2-1 downto 0); -mem_addr_high <= mem_addr_full(NT_LOG2+N-1 downto NT_LOG2); - --- Finite state machine. -process (clk) -begin - if ( rising_edge(clk) ) then - if ( rstn = '0' ) then - state <= INIT_ST; - else - case state is - when INIT_ST => - if ( WE_REG_resync = '1' ) then - state <= READ_START_ADDR_ST; - end if; - - when READ_START_ADDR_ST => - state <= WAIT_TVALID_ST; - - when WAIT_TVALID_ST => - if ( WE_REG_resync = '1') then - if ( tvalid_r = '0' ) then - state <= WAIT_TVALID_ST; - else - state <= RW_TDATA_ST; - end if; - else - state <= INIT_ST; - end if; - - when RW_TDATA_ST => - if ( tvalid_r = '0' ) then - state <= WAIT_TVALID_ST; - end if; - - end case; - end if; - end if; -end process; - --- Output logic. -process (state) -begin -read_start_addr_state <= '0'; -rw_tdata_state <= '0'; -tready_i <= '0'; - case state is - when INIT_ST => - - when READ_START_ADDR_ST => - read_start_addr_state <= '1'; - - when WAIT_TVALID_ST => - tready_i <= '1'; - - when RW_TDATA_ST => - rw_tdata_state <= '1'; - tready_i <= '1'; - - end case; -end process; - --- Assign output. -s_axis_tready <= tready_r; - -mem_en <= mem_en_r; -mem_we <= tvalid_rrr; -mem_addr <= std_logic_vector(mem_addr_high_r); -mem_di <= tdata_rrr; - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v5/src/dds_compiler_0/dds_compiler_0.veo b/qick/firmware/ip/axis_signal_gen_v5/src/dds_compiler_0/dds_compiler_0.veo deleted file mode 100644 index 894ecd6..0000000 --- a/qick/firmware/ip/axis_signal_gen_v5/src/dds_compiler_0/dds_compiler_0.veo +++ /dev/null @@ -1,69 +0,0 @@ -// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -// IP VLNV: xilinx.com:ip:dds_compiler:6.0 -// IP Revision: 18 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -dds_compiler_0 your_instance_name ( - .aclk(aclk), // input wire aclk - .s_axis_phase_tvalid(s_axis_phase_tvalid), // input wire s_axis_phase_tvalid - .s_axis_phase_tdata(s_axis_phase_tdata), // input wire [71 : 0] s_axis_phase_tdata - .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid - .m_axis_data_tdata(m_axis_data_tdata) // output wire [31 : 0] m_axis_data_tdata -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file dds_compiler_0.v when simulating -// the core, dds_compiler_0. When compiling the wrapper file, be sure to -// reference the Verilog simulation library. - diff --git a/qick/firmware/ip/axis_signal_gen_v5/src/dds_compiler_0/dds_compiler_0.vho b/qick/firmware/ip/axis_signal_gen_v5/src/dds_compiler_0/dds_compiler_0.vho deleted file mode 100644 index e65044c..0000000 --- a/qick/firmware/ip/axis_signal_gen_v5/src/dds_compiler_0/dds_compiler_0.vho +++ /dev/null @@ -1,83 +0,0 @@ --- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:dds_compiler:6.0 --- IP Revision: 18 - --- The following code must appear in the VHDL architecture header. - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT dds_compiler_0 - PORT ( - aclk : IN STD_LOGIC; - s_axis_phase_tvalid : IN STD_LOGIC; - s_axis_phase_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0); - m_axis_data_tvalid : OUT STD_LOGIC; - m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) - ); -END COMPONENT; --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : dds_compiler_0 - PORT MAP ( - aclk => aclk, - s_axis_phase_tvalid => s_axis_phase_tvalid, - s_axis_phase_tdata => s_axis_phase_tdata, - m_axis_data_tvalid => m_axis_data_tvalid, - m_axis_data_tdata => m_axis_data_tdata - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file dds_compiler_0.vhd when simulating --- the core, dds_compiler_0. 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- hdl/xbip_utils_v3_0_vh_rfs.vhd - vhdlSource - xbip_utils_v3_0_10 - - - - - - - - - - - xilinx_vhdlsynthesis_xilinx_com_ip_axi_utils_2_0__ref_view_fileset - - hdl/axi_utils_v2_0_vh_rfs.vhd - vhdlSource - axi_utils_v2_0_6 - - - - - - - - - - - xilinx_vhdlsynthesis_xilinx_com_ip_xbip_pipe_3_0__ref_view_fileset - - hdl/xbip_pipe_v3_0_vh_rfs.vhd - vhdlSource - xbip_pipe_v3_0_6 - - - - - - - - - - - xilinx_vhdlsynthesis_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset - - hdl/xbip_bram18k_v3_0_vh_rfs.vhd - vhdlSource - xbip_bram18k_v3_0_6 - - - - - - - - - - - xilinx_vhdlsynthesis_xilinx_com_ip_mult_gen_12_0__ref_view_fileset - - hdl/mult_gen_v12_0_vh_rfs.vhd - vhdlSource - mult_gen_v12_0_15 - - - - - - - - - - - xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_wrapper_3_0__ref_view_fileset - - hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd - vhdlSource - xbip_dsp48_wrapper_v3_0_4 - - - - - - - - - - - xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_addsub_3_0__ref_view_fileset - - hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd - vhdlSource - xbip_dsp48_addsub_v3_0_6 - - - - - - - - - - - xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_multadd_3_0__ref_view_fileset - - hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd - vhdlSource - xbip_dsp48_multadd_v3_0_6 - - - - - - - - - - - xilinx_vhdlsynthesis_view_fileset - - hdl/dds_compiler_v6_0_vh_rfs.vhd - vhdlSource - dds_compiler_v6_0_18 - - - - xilinx_vhdlsynthesiswrapper_view_fileset - - synth/dds_compiler_0.vhd - vhdlSource - xil_defaultlib - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset - - hdl/xbip_utils_v3_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - xbip_utils_v3_0_10 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_utils_2_0__ref_view_fileset - - hdl/axi_utils_v2_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - axi_utils_v2_0_6 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_pipe_3_0__ref_view_fileset - - hdl/xbip_pipe_v3_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - xbip_pipe_v3_0_6 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset - - hdl/xbip_bram18k_v3_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - xbip_bram18k_v3_0_6 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_mult_gen_12_0__ref_view_fileset - - hdl/mult_gen_v12_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - mult_gen_v12_0_15 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_wrapper_3_0__ref_view_fileset - - hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - xbip_dsp48_wrapper_v3_0_4 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_addsub_3_0__ref_view_fileset - - hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - xbip_dsp48_addsub_v3_0_6 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_multadd_3_0__ref_view_fileset - - hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - xbip_dsp48_multadd_v3_0_6 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_view_fileset - - hdl/dds_compiler_v6_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - dds_compiler_v6_0_18 - - - - xilinx_vhdlsimulationwrapper_view_fileset - - sim/dds_compiler_0.vhd - vhdlSource - xil_defaultlib - - - - xilinx_cmodelsimulation_view_fileset - - cmodel/dds_compiler_v6_0_bitacc_cmodel_lin64.zip - zip - - - cmodel/dds_compiler_v6_0_bitacc_cmodel_nt64.zip - zip - - - - xilinx_vhdltestbench_view_fileset - - demo_tb/tb_dds_compiler_0.vhd - vhdlSource - - - - xilinx_versioninformation_view_fileset - - doc/dds_compiler_v6_0_changelog.txt - text - - - - The Xilinx DDS Compiler LogiCORE provides Direct Digital Synthesizers (DDS) and optionally either Phase Generator or Sine/Cosine Lookup Table constituent parts as independent cores. The core features sine, cosine or quadrature outputs with 3 to 26-bit output sample precision. The core supports up to 16 channels by time-sharing the sine/cosine table which dramatically reduces the area requirement when multiple channels are needed. Phase Dithering and Taylor Series Correction options provide high dynamic range signals using minimal FPGA resources. In addition, the core has an optional phase offset capability, providing support for multiple synthesizers with precisely controlled phase differences. - - - Component_Name - Component Name - dds_compiler_0 - - - PartsPresent - Configuration Options - Phase_Generator_and_SIN_COS_LUT - - - DDS_Clock_Rate - System Clock - 256 - - - Channels - Number of Channels - 1 - - - Mode_of_Operation - Mode Of Operation - Standard - - - Modulus - Modulus - 9 - - - Parameter_Entry - Parameter Selection - System_Parameters - - - Spurious_Free_Dynamic_Range - Spurious Free Dynamic Range - 96 - - - Frequency_Resolution - Frequency Resolution - 0.06 - - - Noise_Shaping - Noise Shaping - Auto - - - Phase_Width - Phase Width - 32 - - - Output_Width - Output Width - 16 - - - Phase_Increment - Phase Increment - Streaming - - - Resync - Resync - true - - - Phase_offset - Phase Offset - Streaming - - - Output_Selection - Output Selection - Sine_and_Cosine - - - Negative_Sine - Negative Sine - false - - - Negative_Cosine - Negative Cosine - false - - - Amplitude_Mode - Amplitude Mode - Full_Range - - - Memory_Type - Memory Type - Auto - - - Optimization_Goal - Optimization Goal - Speed - - - DSP48_Use - DSP48 Use - Maximal - - - Has_Phase_Out - Has Phase Out - false - - - DATA_Has_TLAST - DATA Has TLAST - Not_Required - - - Has_TREADY - Output TREADY - false - - - S_PHASE_Has_TUSER - Input - Not_Required - - - S_PHASE_TUSER_Width - User Field Width - 1 - - - M_DATA_Has_TUSER - DATA Output - Not_Required - - - M_PHASE_Has_TUSER - PHASE Output - Not_Required - - - S_CONFIG_Sync_Mode - Synchronization Mode - On_Vector - - - OUTPUT_FORM - Output Form - Twos_Complement - - - Latency_Configuration - Configurable - - - Latency - 2 - - - Has_ARESETn - ARESETn (active low) - false - - - Has_ACLKEN - ACLKEN - false - - - Output_Frequency1 - 0 - - - PINC1 - 0 - - - Phase_Offset_Angles1 - 0 - - - POFF1 - 0 - - - Output_Frequency2 - 0 - - - PINC2 - 0 - - - Phase_Offset_Angles2 - 0 - - - POFF2 - 0 - - - Output_Frequency3 - 0 - - - PINC3 - 0 - - - Phase_Offset_Angles3 - 0 - - - POFF3 - 0 - - - Output_Frequency4 - 0 - - - PINC4 - 0 - - - Phase_Offset_Angles4 - 0 - - - POFF4 - 0 - - - Output_Frequency5 - 0 - - - PINC5 - 0 - - - Phase_Offset_Angles5 - 0 - - - POFF5 - 0 - - - Output_Frequency6 - 0 - - - PINC6 - 0 - - - Phase_Offset_Angles6 - 0 - - - POFF6 - 0 - - - Output_Frequency7 - 0 - - - PINC7 - 0 - - - Phase_Offset_Angles7 - 0 - - - POFF7 - 0 - - - Output_Frequency8 - 0 - - - PINC8 - 0 - - - Phase_Offset_Angles8 - 0 - - - POFF8 - 0 - - - Output_Frequency9 - 0 - - - PINC9 - 0 - - - Phase_Offset_Angles9 - 0 - - - POFF9 - 0 - - - Output_Frequency10 - 0 - - - PINC10 - 0 - - - Phase_Offset_Angles10 - 0 - - - POFF10 - 0 - - - Output_Frequency11 - 0 - - - PINC11 - 0 - - - Phase_Offset_Angles11 - 0 - - - POFF11 - 0 - - - Output_Frequency12 - 0 - - - PINC12 - 0 - - - Phase_Offset_Angles12 - 0 - - - POFF12 - 0 - - - Output_Frequency13 - 0 - - - PINC13 - 0 - - - Phase_Offset_Angles13 - 0 - - - POFF13 - 0 - - - Output_Frequency14 - 0 - - - PINC14 - 0 - - - Phase_Offset_Angles14 - 0 - - - POFF14 - 0 - - - Output_Frequency15 - 0 - - - PINC15 - 0 - - - Phase_Offset_Angles15 - 0 - - - POFF15 - 0 - - - Output_Frequency16 - 0 - - - PINC16 - 0 - - - Phase_Offset_Angles16 - 0 - - - POFF16 - 0 - - - POR_mode - POR Mode - false - - - GUI_Behaviour - Coregen - - - explicit_period - false - - - period - 1 - - - - - DDS Compiler - 18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2019.1 - - - - - - - - diff --git a/qick/firmware/ip/axis_signal_gen_v5/src/fifo/bin2gray.vhd b/qick/firmware/ip/axis_signal_gen_v5/src/fifo/bin2gray.vhd deleted file mode 100644 index 4ecc09b..0000000 --- a/qick/firmware/ip/axis_signal_gen_v5/src/fifo/bin2gray.vhd +++ /dev/null @@ -1,37 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity bin2gray is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end bin2gray; - -architecture rtl of bin2gray is - -signal gray : std_logic_vector (B-1 downto 0); - -begin - --- MSB always match. -gray(B-1) <= din(B-1); - -GEN: for I in 0 to B-2 generate -begin - gray(I) <= din(I+1) xor din(I); -end generate; - --- Assign output. -dout <= gray; - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v5/src/fifo/bram_dp.vhd b/qick/firmware/ip/axis_signal_gen_v5/src/fifo/bram_dp.vhd deleted file mode 100644 index d57aad1..0000000 --- a/qick/firmware/ip/axis_signal_gen_v5/src/fifo/bram_dp.vhd +++ /dev/null @@ -1,63 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity bram_dp is - Generic ( - -- Memory address size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - ena : in STD_LOGIC; - enb : in STD_LOGIC; - wea : in STD_LOGIC; - web : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR (N-1 downto 0); - addrb : in STD_LOGIC_VECTOR (N-1 downto 0); - dia : in STD_LOGIC_VECTOR (B-1 downto 0); - dib : in STD_LOGIC_VECTOR (B-1 downto 0); - doa : out STD_LOGIC_VECTOR (B-1 downto 0); - dob : out STD_LOGIC_VECTOR (B-1 downto 0) - ); -end bram_dp; - -architecture rtl of bram_dp is - --- Ram type. -type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); -shared variable RAM : ram_type; - -begin - --- CLKA port. -process (clka) -begin - if (clka'event and clka = '1') then - if (ena = '1') then - doa <= RAM(conv_integer(addra)); - if (wea = '1') then - RAM(conv_integer(addra)) := dia; - end if; - end if; - end if; -end process; - --- CLKB port. -process (clkb) -begin - if (clkb'event and clkb = '1') then - if (enb = '1') then - dob <= RAM(conv_integer(addrb)); - if (web = '1') then - RAM(conv_integer(addrb)) := dib; - end if; - end if; - end if; -end process; - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v5/src/fifo/bram_simple_dp.vhd b/qick/firmware/ip/axis_signal_gen_v5/src/fifo/bram_simple_dp.vhd deleted file mode 100644 index 1494332..0000000 --- a/qick/firmware/ip/axis_signal_gen_v5/src/fifo/bram_simple_dp.vhd +++ /dev/null @@ -1,53 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity bram_simple_dp is - Generic ( - -- Memory address size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port ( - clk : in STD_LOGIC; - ena : in STD_LOGIC; - enb : in STD_LOGIC; - wea : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR (N-1 downto 0); - addrb : in STD_LOGIC_VECTOR (N-1 downto 0); - dia : in STD_LOGIC_VECTOR (B-1 downto 0); - dob : out STD_LOGIC_VECTOR (B-1 downto 0) - ); -end bram_simple_dp; - -architecture rtl of bram_simple_dp is - --- Ram type. -type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); -shared variable RAM : ram_type; - -begin - -process (clk) -begin - if (clk'event and clk = '1') then - if (ena = '1') then - if (wea = '1') then - RAM(conv_integer(addra)) := dia; - end if; - end if; - end if; -end process; - -process (clk) -begin - if (clk'event and clk = '1') then - if (enb = '1') then - dob <= RAM(conv_integer(addrb)); - end if; - end if; -end process; - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v5/src/fifo/fifo.vhd b/qick/firmware/ip/axis_signal_gen_v5/src/fifo/fifo.vhd deleted file mode 100644 index 957362b..0000000 --- a/qick/firmware/ip/axis_signal_gen_v5/src/fifo/fifo.vhd +++ /dev/null @@ -1,135 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo; - -architecture rtl of fifo is - --- Number of bits of depth. -constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); - --- Dual port, single clock BRAM. -component bram_simple_dp is - Generic ( - -- Memory address size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port ( - clk : in STD_LOGIC; - ena : in STD_LOGIC; - enb : in STD_LOGIC; - wea : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR (N-1 downto 0); - addrb : in STD_LOGIC_VECTOR (N-1 downto 0); - dia : in STD_LOGIC_VECTOR (B-1 downto 0); - dob : out STD_LOGIC_VECTOR (B-1 downto 0) - ); -end component; - --- Pointers. -signal wptr : unsigned (N_LOG2-1 downto 0); -signal rptr : unsigned (N_LOG2-1 downto 0); - --- Memory signals. -signal mem_wea : std_logic; -signal mem_dob : std_logic_vector (B-1 downto 0); - --- Flags. -signal full_i : std_logic; -signal empty_i : std_logic; - -begin - --- FIFO memory. -mem_i : bram_simple_dp - Generic map ( - -- Memory address size. - N => N_LOG2, - -- Data width. - B => B - ) - Port map ( - clk => clk , - ena => '1' , - enb => rd_en , - wea => mem_wea , - addra => std_logic_vector(wptr) , - addrb => std_logic_vector(rptr) , - dia => din , - dob => mem_dob - ); - --- Memory connections. -mem_wea <= wr_en when full_i = '0' else - '0'; - --- Full/empty signals. -full_i <= '1' when wptr = rptr - 1 else - '0'; -empty_i <= '1' when wptr = rptr else - '0'; - --- wr_clk registers. -process (clk) -begin - if ( rising_edge(clk) ) then - if ( rstn = '0' ) then - wptr <= (others => '0'); - rptr <= (others => '0'); - else - -- Write. - if ( wr_en = '1' and full_i = '0' ) then - -- Write data. - - -- Increment pointer. - wptr <= wptr + 1; - end if; - - -- Read. - if ( rd_en = '1' and empty_i = '0' ) then - -- Read data. - - -- Increment pointer. - rptr <= rptr + 1; - end if; - end if; - end if; -end process; - --- Assign outputs. -dout <= mem_dob; -full <= full_i; -empty <= empty_i; - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v5/src/fifo/fifo_axi.vhd b/qick/firmware/ip/axis_signal_gen_v5/src/fifo/fifo_axi.vhd deleted file mode 100644 index e1f76f7..0000000 --- a/qick/firmware/ip/axis_signal_gen_v5/src/fifo/fifo_axi.vhd +++ /dev/null @@ -1,147 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo_axi is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo_axi; - -architecture rtl of fifo_axi is - --- FIFO. -component fifo is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end component; - --- FIFO read to AXI adapter. -component rd2axi is - Generic - ( - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- FIFO Read I/F. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (B-1 downto 0); - fifo_empty : in std_logic; - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - empty : out std_logic - ); -end component; - -signal rd_en_i : std_logic; -signal dout_i : std_logic_vector (B-1 downto 0); -signal empty_i : std_logic; - -begin - --- FIFO. -fifo_i : fifo - Generic map - ( - -- Data width. - B => B, - - -- Fifo depth. - N => N - ) - Port map - ( - rstn => rstn , - clk => clk , - - -- Write I/F. - wr_en => wr_en , - din => din , - - -- Read I/F. - rd_en => rd_en_i , - dout => dout_i , - - -- Flags. - full => full , - empty => empty_i - ); - --- FIFO read to AXI adapter. -rd2axi_i : rd2axi - Generic map - ( - -- Data width. - B => B - ) - Port map - ( - rstn => rstn , - clk => clk , - - -- FIFO Read I/F. - fifo_rd_en => rd_en_i , - fifo_dout => dout_i , - fifo_empty => empty_i , - - -- Read I/F. - rd_en => rd_en , - dout => dout , - empty => empty - ); - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v5/src/fifo/fifo_dc.vhd b/qick/firmware/ip/axis_signal_gen_v5/src/fifo/fifo_dc.vhd deleted file mode 100644 index c214fae..0000000 --- a/qick/firmware/ip/axis_signal_gen_v5/src/fifo/fifo_dc.vhd +++ /dev/null @@ -1,291 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo_dc is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - wr_rstn : in std_logic; - wr_clk : in std_logic; - - rd_rstn : in std_logic; - rd_clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo_dc; - -architecture rtl of fifo_dc is - --- Number of bits of depth. -constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); - --- Binary to gray converter. -component bin2gray is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end component; - --- Gray to binary converter. -component gray2bin is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end component; - --- Vector synchronizer (only for gray coded). -component synchronizer_vect is - generic ( - -- Sync stages. - N : Integer := 2; - - -- Data width. - B : Integer := 8 - ); - port ( - rstn : in std_logic; - clk : in std_logic; - data_in : in std_logic_vector (B-1 downto 0); - data_out : out std_logic_vector (B-1 downto 0) - ); -end component; - --- Dual port BRAM. -component bram_dp is - Generic ( - -- Memory address size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - ena : in STD_LOGIC; - enb : in STD_LOGIC; - wea : in STD_LOGIC; - web : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR (N-1 downto 0); - addrb : in STD_LOGIC_VECTOR (N-1 downto 0); - dia : in STD_LOGIC_VECTOR (B-1 downto 0); - dib : in STD_LOGIC_VECTOR (B-1 downto 0); - doa : out STD_LOGIC_VECTOR (B-1 downto 0); - dob : out STD_LOGIC_VECTOR (B-1 downto 0) - ); -end component; - --- Pointers. -signal wptr : unsigned (N_LOG2-1 downto 0); -signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); -signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); -signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); -signal rptr : unsigned (N_LOG2-1 downto 0); -signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); -signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); -signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); - --- Memory signals. -signal mem_wea : std_logic; -signal mem_dib : std_logic_vector (B-1 downto 0); -signal mem_doa : std_logic_vector (B-1 downto 0); -signal mem_dob : std_logic_vector (B-1 downto 0); - --- Flags. -signal full_i : std_logic; -signal empty_i : std_logic; - -begin - --- wptr_i: binary to gray. -wptr_i : bin2gray - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => std_logic_vector(wptr), - dout => wptr_g - ); - --- wptr_g: write to read domain. -wptr_g_i : synchronizer_vect - generic map ( - -- Sync stages. - N => 2, - - -- Data width. - B => N_LOG2 - ) - port map ( - rstn => rd_rstn, - clk => rd_clk, - data_in => wptr_g, - data_out => wptr_gc - ); - --- wptr_gc_i -wptr_gc_i : gray2bin - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => wptr_gc, - dout => wptr_c - ); - --- rptr_i: binary to gray. -rptr_i : bin2gray - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => std_logic_vector(rptr), - dout => rptr_g - ); - --- rptr_g: read to write domain. -rptr_g_i : synchronizer_vect - generic map ( - -- Sync stages. - N => 2, - - -- Data width. - B => N_LOG2 - ) - port map ( - rstn => wr_rstn, - clk => wr_clk, - data_in => rptr_g, - data_out => rptr_gc - ); - --- rptr_gc_i -rptr_gc_i : gray2bin - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => rptr_gc, - dout => rptr_c - ); - --- FIFO memory. -mem_i : bram_dp - Generic map ( - -- Memory address size. - N => N_LOG2, - -- Data width. - B => B - ) - Port map ( - clka => wr_clk, - clkb => rd_clk, - ena => '1', - enb => rd_en, - wea => mem_wea, - web => '0', - addra => std_logic_vector(wptr), - addrb => std_logic_vector(rptr), - dia => din, - dib => mem_dib, - doa => mem_doa, - dob => mem_dob - ); --- Memory connections. -mem_wea <= wr_en when full_i = '0' else - '0'; -mem_dib <= (others => '0'); - --- Full/empty signals. -full_i <= '1' when wptr = unsigned(rptr_c) - 1 else - '0'; -empty_i <= '1' when unsigned(wptr_c) = rptr else - '0'; - --- wr_clk registers. -process (wr_clk) -begin - if ( rising_edge(wr_clk) ) then - if ( wr_rstn = '0' ) then - wptr <= (others => '0'); - else - -- Write. - if ( wr_en = '1' and full_i = '0' ) then - -- Write data. - - -- Increment pointer. - wptr <= wptr + 1; - end if; - end if; - end if; -end process; - --- rd_clk registers. -process (rd_clk) -begin - if ( rising_edge(rd_clk) ) then - if ( rd_rstn = '0' ) then - rptr <= (others => '0'); - else - -- Read. - if ( rd_en = '1' and empty_i = '0' ) then - -- Read data. - - -- Increment pointer. - rptr <= rptr + 1; - end if; - end if; - end if; -end process; - --- Assign outputs. -dout <= mem_dob; -full <= full_i; -empty <= empty_i; - -end rtl; diff --git a/qick/firmware/ip/axis_signal_gen_v5/src/fifo/fifo_dc_axi.vhd b/qick/firmware/ip/axis_signal_gen_v5/src/fifo/fifo_dc_axi.vhd deleted file mode 100644 index eb83d1a..0000000 --- a/qick/firmware/ip/axis_signal_gen_v5/src/fifo/fifo_dc_axi.vhd +++ /dev/null @@ -1,156 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo_dc_axi is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - wr_rstn : in std_logic; - wr_clk : in std_logic; - - rd_rstn : in std_logic; - rd_clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo_dc_axi; - -architecture rtl of fifo_dc_axi is - --- Dual-clock FIFO. -component fifo_dc is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - wr_rstn : in std_logic; - wr_clk : in std_logic; - - rd_rstn : in std_logic; - rd_clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end component; - --- FIFO read to AXI adapter. -component rd2axi is - Generic - ( - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- FIFO Read I/F. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (B-1 downto 0); - fifo_empty : in std_logic; - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - empty : out std_logic - ); -end component; - -signal rd_en_i : std_logic; -signal dout_i : std_logic_vector (B-1 downto 0); -signal empty_i : std_logic; - -begin - --- Dual-clock FIFO. -fifo_i : fifo_dc - Generic map - ( - -- Data width. - B => B, - - -- Fifo depth. - N => N - ) - Port map - ( - wr_rstn => wr_rstn , - wr_clk => wr_clk , - - rd_rstn => rd_rstn , - rd_clk => rd_clk , - - -- Write I/F. - wr_en => wr_en , - din => din , - - -- Read I/F. - rd_en => rd_en_i , - dout => dout_i , - - -- Flags. - full => full , - empty => empty_i - ); - --- FIFO read to AXI adapter. -rd2axi_i : rd2axi - Generic map - ( - -- Data width. - B => B - ) - Port map - ( - rstn => rd_rstn , - clk => rd_clk , - - -- FIFO Read I/F. - fifo_rd_en => rd_en_i , - fifo_dout => dout_i , - fifo_empty => empty_i , - - -- Read I/F. - rd_en => rd_en , - dout => dout , - empty => empty - ); - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v5/src/fifo/gray2bin.vhd b/qick/firmware/ip/axis_signal_gen_v5/src/fifo/gray2bin.vhd deleted file mode 100644 index e23f8af..0000000 --- a/qick/firmware/ip/axis_signal_gen_v5/src/fifo/gray2bin.vhd +++ /dev/null @@ -1,37 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity gray2bin is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end gray2bin; - -architecture rtl of gray2bin is - -signal bin : std_logic_vector (B-1 downto 0); - -begin - --- MSB always match. -bin(B-1) <= din(B-1); - -GEN: for I in 0 to B-2 generate -begin - bin(I) <= bin(I+1) xor din(I); -end generate GEN; - --- Assign output. -dout <= bin; - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v5/src/fifo/rd2axi.vhd b/qick/firmware/ip/axis_signal_gen_v5/src/fifo/rd2axi.vhd deleted file mode 100644 index babadc6..0000000 --- a/qick/firmware/ip/axis_signal_gen_v5/src/fifo/rd2axi.vhd +++ /dev/null @@ -1,138 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity rd2axi is - Generic - ( - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- FIFO Read I/F. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (B-1 downto 0); - fifo_empty : in std_logic; - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - empty : out std_logic - ); -end rd2axi; - -architecture rtl of rd2axi is - -type fsm_state is ( WAIT_EMPTY_ST, - READ_FIRST_ST, - READ_ST, - READ_LAST_ST); -signal current_state, next_state : fsm_state; - -signal wait_empty_state : std_logic; -signal read_first_state : std_logic; -signal read_state : std_logic; - -signal fifo_rd_en_i : std_logic; -signal empty_i : std_logic; - -begin - -process(clk) -begin - if (rising_edge(clk)) then - if (rstn = '0') then - current_state <= WAIT_EMPTY_ST; - else - current_state <= next_state; - end if; - end if; -end process; - --- Next state logic. -process(current_state, fifo_empty, rd_en) -begin - case current_state is - when WAIT_EMPTY_ST => - if (fifo_empty = '1') then - next_state <= WAIT_EMPTY_ST; - else - next_state <= READ_FIRST_ST; - end if; - - when READ_FIRST_ST => - next_state <= READ_ST; - - when READ_ST => - if (fifo_empty = '0') then - next_state <= READ_ST; - else - if (rd_en = '1') then - next_state <= WAIT_EMPTY_ST; - else - next_state <= READ_LAST_ST; - end if; - end if; - - when READ_LAST_ST => - if (rd_en = '0') then - next_state <= READ_LAST_ST; - else - next_state <= WAIT_EMPTY_ST; - end if; - - end case; -end process; - --- Output logic. -process(current_state) -begin -wait_empty_state <= '0'; -read_first_state <= '0'; -read_state <= '0'; -empty_i <= '0'; - case current_state is - when WAIT_EMPTY_ST => - wait_empty_state <= '1'; - read_first_state <= '0'; - read_state <= '0'; - empty_i <= '1'; - - when READ_FIRST_ST => - wait_empty_state <= '0'; - read_first_state <= '1'; - read_state <= '0'; - empty_i <= '1'; - - when READ_ST => - wait_empty_state <= '0'; - read_first_state <= '0'; - read_state <= '1'; - empty_i <= '0'; - - when READ_LAST_ST => - wait_empty_state <= '0'; - read_first_state <= '0'; - read_state <= '0'; - empty_i <= '0'; - - end case; -end process; - --- FIFO Read enable signal. -fifo_rd_en_i <= read_first_state or (read_state and rd_en); - --- Assign outputs. -fifo_rd_en <= fifo_rd_en_i; --- TODO: add register to freeze last value. -dout <= fifo_dout when empty_i = '0' else - (others => '0'); -empty <= empty_i; - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v5/src/fifo/synchronizer_vect.vhd b/qick/firmware/ip/axis_signal_gen_v5/src/fifo/synchronizer_vect.vhd deleted file mode 100644 index 2fbb696..0000000 --- a/qick/firmware/ip/axis_signal_gen_v5/src/fifo/synchronizer_vect.vhd +++ /dev/null @@ -1,49 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - --- This block is intended to use to sync gray coded vectors. - --- NOTE: Do not use with generic vector data, as it may result --- in corrupted re-sync data. - -entity synchronizer_vect is - generic ( - -- Sync stages. - N : Integer := 2; - - -- Data width. - B : Integer := 8 - ); - port ( - rstn : in std_logic; - clk : in std_logic; - data_in : in std_logic_vector (B-1 downto 0); - data_out : out std_logic_vector (B-1 downto 0) - ); -end synchronizer_vect; - -architecture rtl of synchronizer_vect is - --- Internal register. -type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); -signal data_int_reg : reg_t; - -begin - -process(clk) -begin - if (rising_edge(clk)) then - if (rstn = '0') then - data_int_reg <= (others => (others => '0')); -- 1 FF. - else - data_int_reg <= data_int_reg(N-2 downto 0) & data_in; - end if; - end if; -end process; - --- Assign output. -data_out <= data_int_reg(N-1); - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v5/src/latency_reg.v b/qick/firmware/ip/axis_signal_gen_v5/src/latency_reg.v deleted file mode 100644 index 687a9f3..0000000 --- a/qick/firmware/ip/axis_signal_gen_v5/src/latency_reg.v +++ /dev/null @@ -1,61 +0,0 @@ -module latency_reg - ( - rstn , - clk , - - din , - dout - ); - -// Parameters. -parameter N = 2; // Latency. -parameter B = 8; // Data width. - -// Ports. -input rstn; -input clk; -input [B-1:0] din; -output [B-1:0] dout; - -// Shift register. -reg [B-1:0] shift_r [0:N-1]; - -generate -genvar i; - for (i=1; i '0'); - else - data_int_reg <= data_int_reg(N-2 downto 0) & data_in; - end if; - end if; -end process; - --- Assign output. -data_out <= data_int_reg(N-1); - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v5/src/tb/dout.csv b/qick/firmware/ip/axis_signal_gen_v5/src/tb/dout.csv deleted file mode 100644 index 0ecffa5..0000000 --- a/qick/firmware/ip/axis_signal_gen_v5/src/tb/dout.csv +++ /dev/null @@ -1,20013 +0,0 @@ -valid, idx, real, imag -0, 0, 0 -0, 1, 0 -0, 2, 0 -0, 3, 0 -0, 0, 0 -0, 1, 0 -0, 2, 0 -0, 3, 0 -0, 0, 0 -0, 1, 0 -0, 2, 0 -0, 3, 0 -0, 0, 0 -0, 1, 0 -0, 2, 0 -0, 3, 0 -0, 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-1865,0 -1814,0 -1764,0 -1715,0 -1667,0 -1620,0 -1574,0 -1530,0 -1486,0 -1444,0 -1403,0 -1362,0 diff --git a/qick/firmware/ip/axis_signal_gen_v5/src/tb/gen_gauss.py b/qick/firmware/ip/axis_signal_gen_v5/src/tb/gen_gauss.py deleted file mode 100644 index 88ba683..0000000 --- a/qick/firmware/ip/axis_signal_gen_v5/src/tb/gen_gauss.py +++ /dev/null @@ -1,18 +0,0 @@ -import numpy as np -import matplotlib.pyplot as plt - -def gauss(mu=0, si=0, length=100, maxv=30000): - x = np.arange(0,length) - y = 1/(2*np.pi*si**2)*np.exp(-(x-mu)**2/si**2) - y = y/np.max(y)*maxv - return y - -yq = gauss(mu=300, si=120, length=512) -yi = np.zeros(len(yq)) - -yi = yi.astype(np.int16) -yq = yq.astype(np.int16) - -for ii in range(len(yi)): - print("%d,%d" %(yq[ii],yi[ii])) - diff --git a/qick/firmware/ip/axis_signal_gen_v5/src/tb/tb.sv b/qick/firmware/ip/axis_signal_gen_v5/src/tb/tb.sv deleted file mode 100644 index 929571d..0000000 --- a/qick/firmware/ip/axis_signal_gen_v5/src/tb/tb.sv +++ /dev/null @@ -1,427 +0,0 @@ -// VIP: axi_mst_0 -// DUT: axis_signal_gen_v2 -// IF: s_axi -> axi_mst_0 - -import axi_vip_pkg::*; -import axi_mst_0_pkg::*; - -module tb(); - -// DUT generics. -parameter N = 10; -parameter N_DDS = 4; - -// s_axi interfase. -reg s_axi_aclk; -reg s_axi_aresetn; -wire [5:0] s_axi_araddr; -wire [2:0] s_axi_arprot; -wire s_axi_arready; -wire s_axi_arvalid; -wire [5:0] s_axi_awaddr; -wire [2:0] s_axi_awprot; -wire s_axi_awready; -wire s_axi_awvalid; -wire s_axi_bready; -wire [1:0] s_axi_bresp; -wire s_axi_bvalid; -wire [31:0] s_axi_rdata; -wire s_axi_rready; -wire [1:0] s_axi_rresp; -wire s_axi_rvalid; -wire [31:0] s_axi_wdata; -wire s_axi_wready; -wire [3:0] s_axi_wstrb; -wire s_axi_wvalid; - -// s0_axis interfase. -reg s0_axis_aclk; -reg s0_axis_aresetn; -reg [31:0] s0_axis_tdata; -wire s0_axis_tready; -reg s0_axis_tvalid; - -reg aresetn; -reg aclk; - -// s1_axis interfase. -reg [159:0] s1_axis_tdata; -wire s1_axis_tready; -reg s1_axis_tvalid; - -// m_axis interfase. -wire [N_DDS*16-1:0] m_axis_tdata; -reg m_axis_tready = 1; -wire m_axis_tvalid; - -// Waveform Fields. -reg [31:0] freq_r; -reg [31:0] phase_r; -reg [15:0] addr_r; -reg [15:0] gain_r; -reg [15:0] nsamp_r; -reg [1:0] outsel_r; -reg mode_r; -reg stdysel_r; -reg phrst_r; - -// Assignment of data out for debugging. -wire [15:0] dout_ii [0:N_DDS-1]; - -// AXI VIP master address. -xil_axi_ulong addr_start_addr = 32'h40000000; // 0 -xil_axi_ulong addr_we = 32'h40000004; // 1 - -xil_axi_prot_t prot = 0; -reg[31:0] data_wr = 32'h12345678; -reg[31:0] data; -xil_axi_resp_t resp; - -// Test bench control. -reg tb_load_mem = 0; -reg tb_load_mem_done = 0; -reg tb_load_wave = 0; -reg tb_load_wave_done = 0; -reg tb_write_out = 0; - -// Debug. -generate -genvar ii; -for (ii = 0; ii < N_DDS; ii = ii + 1) begin : GEN_debug - assign dout_ii[ii] = m_axis_tdata[16*ii +: 16]; -end -endgenerate -axi_mst_0 axi_mst_0_i - ( - .aclk (s_axi_aclk ), - .aresetn (s_axi_aresetn ), - .m_axi_araddr (s_axi_araddr ), - .m_axi_arprot (s_axi_arprot ), - .m_axi_arready (s_axi_arready ), - .m_axi_arvalid (s_axi_arvalid ), - .m_axi_awaddr (s_axi_awaddr ), - .m_axi_awprot (s_axi_awprot ), - .m_axi_awready (s_axi_awready ), - .m_axi_awvalid (s_axi_awvalid ), - .m_axi_bready (s_axi_bready ), - .m_axi_bresp (s_axi_bresp ), - .m_axi_bvalid (s_axi_bvalid ), - .m_axi_rdata (s_axi_rdata ), - .m_axi_rready (s_axi_rready ), - .m_axi_rresp (s_axi_rresp ), - .m_axi_rvalid (s_axi_rvalid ), - .m_axi_wdata (s_axi_wdata ), - .m_axi_wready (s_axi_wready ), - .m_axi_wstrb (s_axi_wstrb ), - .m_axi_wvalid (s_axi_wvalid ) - ); - -axis_signal_gen_v5 - # - ( - .N (N ), - .N_DDS (N_DDS ) - ) - DUT - ( - // AXI Slave I/F for configuration. - .s_axi_aclk (s_axi_aclk ), - .s_axi_aresetn (s_axi_aresetn ), - .s_axi_araddr (s_axi_araddr ), - .s_axi_arprot (s_axi_arprot ), - .s_axi_arready (s_axi_arready ), - .s_axi_arvalid (s_axi_arvalid ), - .s_axi_awaddr (s_axi_awaddr ), - .s_axi_awprot (s_axi_awprot ), - .s_axi_awready (s_axi_awready ), - .s_axi_awvalid (s_axi_awvalid ), - .s_axi_bready (s_axi_bready ), - .s_axi_bresp (s_axi_bresp ), - .s_axi_bvalid (s_axi_bvalid ), - .s_axi_rdata (s_axi_rdata ), - .s_axi_rready (s_axi_rready ), - .s_axi_rresp (s_axi_rresp ), - .s_axi_rvalid (s_axi_rvalid ), - .s_axi_wdata (s_axi_wdata ), - .s_axi_wready (s_axi_wready ), - .s_axi_wstrb (s_axi_wstrb ), - .s_axi_wvalid (s_axi_wvalid ), - - // AXIS Slave to load data into memory. - .s0_axis_aclk (s0_axis_aclk ), - .s0_axis_aresetn(s0_axis_aresetn), - .s0_axis_tdata (s0_axis_tdata ), - .s0_axis_tvalid (s0_axis_tvalid ), - .s0_axis_tready (s0_axis_tready ), - - // s1_* and m_* reset/clock. - .aresetn (aresetn ), - .aclk (aclk ), - - // AXIS Slave to queue waveforms. - .s1_axis_tdata (s1_axis_tdata ), - .s1_axis_tvalid (s1_axis_tvalid ), - .s1_axis_tready (s1_axis_tready ), - - // AXIS Master for output data. - .m_axis_tready (m_axis_tready ), - .m_axis_tvalid (m_axis_tvalid ), - .m_axis_tdata (m_axis_tdata ) - ); - -// VIP Agents -axi_mst_0_mst_t axi_mst_0_agent; - -assign s1_axis_tdata = {{10{1'b0}},phrst_r,stdysel_r,mode_r,outsel_r,nsamp_r,{16{1'b0}},gain_r,{16{1'b0}},addr_r,phase_r,freq_r}; - -initial begin - // Create agents. - axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); - - // Set tag for agents. - axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); - - // Start agents. - axi_mst_0_agent.start_master(); - - // Reset sequence. - s_axi_aresetn <= 0; - s0_axis_aresetn <= 0; - aresetn <= 0; - #500; - s_axi_aresetn <= 1; - s0_axis_aresetn <= 1; - aresetn <= 1; - - #1000; - - $display("############################"); - $display("### Load data into Table ###"); - $display("############################"); - $display("t = %0t", $time); - - /* - ADDR = 0 - */ - - // start_addr. - data_wr = 0; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(addr_start_addr, prot, data_wr, resp); - #10; - - // we. - data_wr = 1; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(addr_we, prot, data_wr, resp); - #10; - - // Load Table. - tb_load_mem <= 1; - wait (tb_load_mem_done); - - #100; - - // we. - data_wr = 0; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(addr_we, prot, data_wr, resp); - #10; - - #1000; - - $display("#######################"); - $display("### Queue Waveforms ###"); - $display("#######################"); - $display("t = %0t", $time); - - // Queue waveforms and write output while queuing. - tb_load_wave <= 1; - tb_write_out <= 1; - wait (tb_load_wave_done); - - #30000; - - // Stop writing output data. - tb_write_out <= 0; - - #20000; - -end - -// Load data into memroy. -initial begin - int fd,vali,valq; - bit signed [15:0] ii,qq; - - s0_axis_tvalid <= 0; - s0_axis_tdata <= 0; - - wait (tb_load_mem); - - fd = $fopen("../../../../../tb/gauss.txt","r"); - - wait (s0_axis_tready); - - while($fscanf(fd,"%d,%d", valq,vali) == 2) begin - $display("I,Q: %d, %d", vali,valq); - ii = vali; - qq = valq; - @(posedge s0_axis_aclk); - s0_axis_tvalid <= 1; - s0_axis_tdata <= {qq,ii}; - end - - @(posedge s0_axis_aclk); - s0_axis_tvalid <= 0; - - $fclose(fd); - tb_load_mem_done <= 1; - -end - -// Load waveforms. -initial begin - s1_axis_tvalid <= 0; - freq_r <= 0; - phase_r <= 0; - addr_r <= 0; - gain_r <= 0; - nsamp_r <= 0; - outsel_r <= 0; - mode_r <= 0; - stdysel_r <= 0; - phrst_r <= 0; - - wait (tb_load_wave); - wait (s1_axis_tready); - - @(posedge aclk); - $display("t = %0t", $time); - s1_axis_tvalid <= 1; - freq_r <= freq_calc(100, N_DDS, 4); // 120 MHz. - phase_r <= 0; - addr_r <= 22; - gain_r <= 12000; - nsamp_r <= 123; - outsel_r <= 1; // 0: prod, 1: dds, 2: mem - mode_r <= 0; // 0: nsamp, 1: periodic - stdysel_r <= 0; // 0: last, 1: zero. - - @(posedge aclk); - $display("t = %0t", $time); - s1_axis_tvalid <= 1; - freq_r <= freq_calc(100, N_DDS, 13); - phase_r <= 0; - addr_r <= 0; - gain_r <= 30000; - nsamp_r <= 512/N_DDS; - outsel_r <= 0; // 0: prod, 1: dds, 2: mem - mode_r <= 0; // 0: nsamp, 1: periodic - stdysel_r <= 0; // 0: last, 1: zero. - - //@(posedge aclk); - //$display("t = %0t", $time); - //s1_axis_tvalid <= 1; - //freq_r <= freq_calc(100, N_DDS, 33); - //phase_r <= 0; - //addr_r <= 5; - //gain_r <= 30000; - //nsamp_r <= 670/N_DDS; - //outsel_r <= 1; // 0: prod, 1: dds, 2: mem - //mode_r <= 0; // 0: nsamp, 1: periodic - //stdysel_r <= 1; // 0: last, 1: zero. - - //@(posedge aclk); - //$display("t = %0t", $time); - //s1_axis_tvalid <= 1; - //freq_r <= freq_calc(100, N_DDS, 22); - //phase_r <= 7689; - //addr_r <= 0; - //gain_r <= 30000; - //nsamp_r <= 70/N_DDS; - //outsel_r <= 2; // 0: prod, 1: dds, 2: mem - //mode_r <= 1; // 0: nsamp, 1: periodic - //stdysel_r <= 1; // 0: last, 1: zero. - - //@(posedge aclk); - //s1_axis_tvalid <= 0; - - //#30000; - - //@(posedge aclk); - //$display("t = %0t", $time); - //s1_axis_tvalid <= 1; - //freq_r <= freq_calc(100, N_DDS, 3); - //phase_r <= 0; - //addr_r <= 5; - //gain_r <= 30000; - //nsamp_r <= 670/N_DDS; - //outsel_r <= 1; // 0: prod, 1: dds, 2: mem - //mode_r <= 0; // 0: nsamp, 1: periodic - //stdysel_r <= 1; // 0: last, 1: zero. - - @(posedge aclk); - s1_axis_tvalid <= 0; - tb_load_wave_done <= 1; -end - -// Write output into file. -initial begin - int fd; - int i; - shortint real_d; - - // Output file. - fd = $fopen("../../../../../tb/dout.csv","w"); - - // Data format. - $fdisplay(fd, "valid, idx, real"); - - wait (tb_write_out); - - while (tb_write_out) begin - @(posedge aclk); - for (i=0; i - - user.org - user - axis_signal_gen_v6 - 1.0 - - - m_axis - - - - - - - TDATA - - - m_axis_tdata - - - - - TVALID - - - m_axis_tvalid - - - - - TREADY - - - m_axis_tready - - - - - - s0_axis - - - - - - - TDATA - - - s0_axis_tdata - - - - - TVALID - - - s0_axis_tvalid - - - - - TREADY - - - s0_axis_tready - - - - - - s1_axis - - - - - - - TDATA - - - s1_axis_tdata - - - - - TVALID - - - s1_axis_tvalid - - - - - TREADY - - - s1_axis_tready - - - - - - s_axi - - - - - - - - - AWADDR - - - s_axi_awaddr - - - - - AWPROT - - - s_axi_awprot - - - - - AWVALID - - - s_axi_awvalid - - - - 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xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset - - - - - - - - - - xilinx_xpgui_view_fileset - - xgui/axis_signal_gen_v6_v1_0.tcl - tclSource - CHECKSUM_e51fb623 - XGUI_VERSION_2 - - - - AXIS Signal Generator V6, Phase coherent with Phase reset. - - - N - N - 12 - - - N_DDS - N Dds - 16 - - - Component_Name - axis_signal_gen_v6_v1_0 - - - - - - zynquplus - - - /UserIP - - AXIS Signal Generator V6 - package_project - 4 - 2022-04-08T14:14:02Z - - /home/lstefana/v20.2/ip/axis_signal_gen_v6 - /home/lstefana/v20.2/ip/axis_signal_gen_v6 - /home/lstefana/v20.2/ip/axis_signal_gen_v6 - /home/lstefana/v20.2/ip/axis_signal_gen_v6 - /home/lstefana/v20.2/ip/axis_signal_gen_v6 - /home/lstefana/v20.2/ip/axis_signal_gen_v6 - /home/lstefana/v20.2/ip/axis_signal_gen_v6 - /home/lstefana/v20.2/ip/axis_signal_gen_v6 - /home/lstefana/v20.2/ip/axis_signal_gen_v6 - /home/lstefana/v20.2/ip/axis_signal_gen_v6 - /home/lstefana/v20.2/ip/axis_signal_gen_v6 - /home/lstefana/v20.2/ip/axis_signal_gen_v6 - /home/lstefana/v20.2/ip/axis_signal_gen_v6 - /home/lstefana/v20.2/ip/axis_signal_gen_v6 - /home/lstefana/v20.2/ip/axis_signal_gen_v6 - /home/lstefana/v20.2/ip/axis_signal_gen_v6 - /home/lstefana/v20.2/ip/axis_signal_gen_v6 - /home/lstefana/v20.2/ip/axis_signal_gen_v6 - /home/lstefana/v20.2/ip/axis_signal_gen_v6 - /home/lstefana/v20.2/ip/axis_signal_gen_v6 - /home/lstefana/v20.2/ip/axis_signal_gen_v6 - /home/lstefana/v20.2/ip/axis_signal_gen_v6 - /home/lstefana/v20.2/ip/axis_signal_gen_v6 - /home/lstefana/v20.2/ip/axis_signal_gen_v6 - /home/lstefana/v20.2/ip/axis_signal_gen_v6 - /home/lstefana/v20.2/ip/axis_signal_gen_v6 - /home/lstefana/v20.2/ip/axis_signal_gen_v6 - /home/lstefana/v20.2/ip/axis_signal_gen_v6 - /home/lstefana/v20.2/ip/axis_signal_gen_v6 - /home/lstefana/v20.2/ip/axis_signal_gen_v6 - /home/lstefana/v20.2/ip/axis_signal_gen_v6 - /home/lstefana/v20.2/ip/axis_signal_gen_v6 - - - - 2020.2 - - - - - - - - - diff --git a/qick/firmware/ip/axis_signal_gen_v6/src/axi_mst_0/axi_mst_0.veo b/qick/firmware/ip/axis_signal_gen_v6/src/axi_mst_0/axi_mst_0.veo deleted file mode 100644 index 7cfbd51..0000000 --- a/qick/firmware/ip/axis_signal_gen_v6/src/axi_mst_0/axi_mst_0.veo +++ /dev/null @@ -1,85 +0,0 @@ -// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -// IP VLNV: xilinx.com:ip:axi_vip:1.1 -// IP Revision: 8 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -axi_mst_0 your_instance_name ( - .aclk(aclk), // input wire aclk - .aresetn(aresetn), // input wire aresetn - .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr - .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot - .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid - .m_axi_awready(m_axi_awready), // input wire m_axi_awready - .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata - .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb - .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid - .m_axi_wready(m_axi_wready), // input wire m_axi_wready - .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp - .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid - .m_axi_bready(m_axi_bready), // output wire m_axi_bready - .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr - .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot - .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid - .m_axi_arready(m_axi_arready), // input wire m_axi_arready - .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata - .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp - .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid - .m_axi_rready(m_axi_rready) // output wire m_axi_rready -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file axi_mst_0.v when simulating -// the core, axi_mst_0. When compiling the wrapper file, be sure to -// reference the Verilog simulation library. - diff --git a/qick/firmware/ip/axis_signal_gen_v6/src/axi_mst_0/axi_mst_0.vho b/qick/firmware/ip/axis_signal_gen_v6/src/axi_mst_0/axi_mst_0.vho deleted file mode 100644 index a53be60..0000000 --- a/qick/firmware/ip/axis_signal_gen_v6/src/axi_mst_0/axi_mst_0.vho +++ /dev/null @@ -1,115 +0,0 @@ --- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:axi_vip:1.1 --- IP Revision: 8 - --- The following code must appear in the VHDL architecture header. - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT axi_mst_0 - PORT ( - aclk : IN STD_LOGIC; - aresetn : IN STD_LOGIC; - m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - m_axi_awvalid : OUT STD_LOGIC; - m_axi_awready : IN STD_LOGIC; - m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - m_axi_wvalid : OUT STD_LOGIC; - m_axi_wready : IN STD_LOGIC; - m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - m_axi_bvalid : IN STD_LOGIC; - m_axi_bready : OUT STD_LOGIC; - m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - m_axi_arvalid : OUT STD_LOGIC; - m_axi_arready : IN STD_LOGIC; - m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - m_axi_rvalid : IN STD_LOGIC; - m_axi_rready : OUT STD_LOGIC - ); -END COMPONENT; --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : axi_mst_0 - PORT MAP ( - aclk => aclk, - aresetn => aresetn, - m_axi_awaddr => m_axi_awaddr, - m_axi_awprot => m_axi_awprot, - m_axi_awvalid => m_axi_awvalid, - m_axi_awready => m_axi_awready, - m_axi_wdata => m_axi_wdata, - m_axi_wstrb => m_axi_wstrb, - m_axi_wvalid => m_axi_wvalid, - m_axi_wready => m_axi_wready, - m_axi_bresp => m_axi_bresp, - m_axi_bvalid => m_axi_bvalid, - m_axi_bready => m_axi_bready, - m_axi_araddr => m_axi_araddr, - m_axi_arprot => m_axi_arprot, - m_axi_arvalid => m_axi_arvalid, - m_axi_arready => m_axi_arready, - m_axi_rdata => m_axi_rdata, - m_axi_rresp => m_axi_rresp, - m_axi_rvalid => m_axi_rvalid, - m_axi_rready => m_axi_rready - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file axi_mst_0.vhd when simulating --- the core, axi_mst_0. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/qick/firmware/ip/axis_signal_gen_v6/src/axi_mst_0/axi_mst_0.xci b/qick/firmware/ip/axis_signal_gen_v6/src/axi_mst_0/axi_mst_0.xci deleted file mode 100644 index ac9cf04..0000000 --- a/qick/firmware/ip/axis_signal_gen_v6/src/axi_mst_0/axi_mst_0.xci +++ /dev/null @@ -1,200 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - axi_mst_0 - - - ACTIVE_LOW - - 100000000 - 0 - 0 - 0.000 - 32 - 0 - 0 - 0 - - 32 - 100000000 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 32 - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 0 - 2 - 32 - 0 - 0 - 0 - 32 - 0 - 0 - 32 - 0 - 0 - 0 - axi_mst_0 - 32 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 0 - 0 - 1 - 0 - MASTER - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - zynquplusRFSOC - xilinx.com:zcu216:part0:2.0 - - xczu49dr - ffvf1760 - VERILOG - - MIXED - -2 - - E - TRUE - TRUE - IP_Flow - 8 - TRUE - . - - . - 2020.2 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/qick/firmware/ip/axis_signal_gen_v6/src/axi_mst_0/axi_mst_0.xml b/qick/firmware/ip/axis_signal_gen_v6/src/axi_mst_0/axi_mst_0.xml deleted file mode 100644 index d201dca..0000000 --- a/qick/firmware/ip/axis_signal_gen_v6/src/axi_mst_0/axi_mst_0.xml +++ /dev/null @@ -1,4760 +0,0 @@ - - - xilinx.com - customized_ip - axi_mst_0 - 1.0 - - - M_AXI - - - - - - - - - ARADDR - - - m_axi_araddr - - - - - ARBURST - - - m_axi_arburst - - - - - ARCACHE - - - m_axi_arcache - - - - - ARID - - - m_axi_arid - - - - - ARLEN - - - m_axi_arlen - - - - - ARLOCK - - - m_axi_arlock - - - - - ARPROT - - - m_axi_arprot - - - - - ARQOS - - - m_axi_arqos - - - - - ARREADY - - - m_axi_arready - - - - - ARREGION - - - m_axi_arregion - - - - - ARSIZE - - - m_axi_arsize - - - - - ARUSER - - - m_axi_aruser - - - - - ARVALID - - - m_axi_arvalid - - - - - AWADDR - - - m_axi_awaddr - - - - - AWBURST - - - m_axi_awburst - - - - - AWCACHE - - - m_axi_awcache - - - - - AWID - - - m_axi_awid - - - - - AWLEN - - - m_axi_awlen - - - - - AWLOCK - - - m_axi_awlock - - - - - AWPROT - - - m_axi_awprot - - - - - AWQOS - - - m_axi_awqos - - - - - AWREADY - - - m_axi_awready - - - - - AWREGION - - - m_axi_awregion - - - - - AWSIZE - - - m_axi_awsize - - - - - AWUSER - - - m_axi_awuser - - - - - AWVALID - - - m_axi_awvalid - - - - - BID - - - m_axi_bid - - - - - BREADY - - - m_axi_bready - - - - - BRESP - - - m_axi_bresp - - - - - BUSER - - - m_axi_buser - - - - - BVALID - - - m_axi_bvalid - - - - - RDATA - - - m_axi_rdata - - - - - RID - - - m_axi_rid - - - - - RLAST - - - m_axi_rlast - - - - - RREADY - - - m_axi_rready - - - - - RRESP - - - m_axi_rresp - - - - - RUSER - - - m_axi_ruser - - - - - RVALID - - - m_axi_rvalid - - - - - WDATA - - - m_axi_wdata - - - - - WID - - - m_axi_wid - - - - - WLAST - - - m_axi_wlast - - - - - WREADY - - - m_axi_wready - - - - - WSTRB - - - m_axi_wstrb - - - - - WUSER - - - m_axi_wuser - - - - - WVALID - - - m_axi_wvalid - - - - - - DATA_WIDTH - 32 - - - simulation.tlm - - - - - PROTOCOL - AXI4LITE - - - simulation.tlm - - - - - FREQ_HZ - 100000000 - - - simulation.tlm - - - - - ID_WIDTH - 0 - - - simulation.tlm - - - - - ADDR_WIDTH - 32 - - - simulation.tlm - - - - - AWUSER_WIDTH - 0 - - - simulation.tlm - - - - - ARUSER_WIDTH - 0 - - - simulation.tlm - - - - - WUSER_WIDTH - 0 - - - simulation.tlm - - - - - RUSER_WIDTH - 0 - - - simulation.tlm - - - - - BUSER_WIDTH - 0 - - - simulation.tlm - - - - - READ_WRITE_MODE - READ_WRITE - - - simulation.tlm - - - - - HAS_BURST - 0 - - - simulation.tlm - - - - - HAS_LOCK - 0 - - - simulation.tlm - - - - - HAS_PROT - 1 - - - simulation.tlm - - - - - HAS_CACHE - 0 - - - simulation.tlm - - - - - HAS_QOS - 0 - - - simulation.tlm - - - - - HAS_REGION - 0 - - - simulation.tlm - - - - - HAS_WSTRB - 1 - - - simulation.tlm - - - - - HAS_BRESP - 1 - - - simulation.tlm - - - - - HAS_RRESP - 1 - - - simulation.tlm - - - - - SUPPORTS_NARROW_BURST - 0 - - - simulation.tlm - - - - - NUM_READ_OUTSTANDING - 1 - - - simulation.tlm - - - - - NUM_WRITE_OUTSTANDING - 1 - - - simulation.tlm - - - - - MAX_BURST_LENGTH - 1 - - - simulation.tlm - - - - - PHASE - 0.000 - - - simulation.tlm - - - - - CLK_DOMAIN - - - - simulation.tlm - - - - - NUM_READ_THREADS - 1 - - - simulation.tlm - - - - - NUM_WRITE_THREADS - 1 - - - simulation.tlm - - - - - RUSER_BITS_PER_BYTE - 0 - - - simulation.tlm - - - - - WUSER_BITS_PER_BYTE - 0 - - - simulation.tlm - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - S_AXI - - - - - - - ARADDR - - - s_axi_araddr - - - - - ARBURST - - - s_axi_arburst - - - - - ARCACHE - - - s_axi_arcache - - - - - ARID - - - s_axi_arid - - - - - ARLEN - - - s_axi_arlen - - - - - ARLOCK - - - s_axi_arlock - - - - - ARPROT - - - s_axi_arprot - - - - - ARQOS - - - s_axi_arqos - - - - - ARREADY - - - s_axi_arready - - - - - ARREGION - - - s_axi_arregion - - - - - ARSIZE - - - s_axi_arsize - - - - - ARUSER - - - s_axi_aruser - - - - - ARVALID - - - s_axi_arvalid - - - - - AWADDR - - - s_axi_awaddr - - - - - AWBURST - - - s_axi_awburst - - - - - AWCACHE - - - s_axi_awcache - - - - - AWID - - - s_axi_awid - - - - - AWLEN - - - s_axi_awlen - - - - - AWLOCK - - - s_axi_awlock - - - - - AWPROT - - - s_axi_awprot - - - - - AWQOS - - - s_axi_awqos - - - - - AWREADY - - - s_axi_awready - - - - - AWREGION - - - s_axi_awregion - - - - - AWSIZE - - - s_axi_awsize - - - - - AWUSER - - - s_axi_awuser - - - - - AWVALID - - - s_axi_awvalid - - - - - BID - - - s_axi_bid - - - - - BREADY - - - s_axi_bready - - - - - BRESP - - - s_axi_bresp - - - - - BUSER - - - s_axi_buser - - - - - BVALID - - - s_axi_bvalid - - - - - RDATA - - - s_axi_rdata - - - - - RID - - - s_axi_rid - - - - - RLAST - - - s_axi_rlast - - - - - RREADY - - - s_axi_rready - - - - - RRESP - - - s_axi_rresp - - - - - RUSER - - - s_axi_ruser - - - - - RVALID - - - s_axi_rvalid - - - - - WDATA - - - s_axi_wdata - - - - - WID - - - s_axi_wid - - - - - WLAST - - - s_axi_wlast - - - - - WREADY - - - s_axi_wready - - - - - WSTRB - - - s_axi_wstrb - - - - - WUSER - - - s_axi_wuser - - - - - WVALID - - - s_axi_wvalid - - - - - - DATA_WIDTH - 1 - - - simulation.tlm - - - - - PROTOCOL - AXI4LITE - - - simulation.tlm - - - - - FREQ_HZ - 100000000 - - - simulation.tlm - - - - - ID_WIDTH - 0 - - - simulation.tlm - - - - - ADDR_WIDTH - 1 - - - simulation.tlm - - - - - AWUSER_WIDTH - 0 - - - simulation.tlm - - - - - ARUSER_WIDTH - 0 - - - simulation.tlm - - - - - WUSER_WIDTH - 0 - - - simulation.tlm - - - - - RUSER_WIDTH - 0 - - - simulation.tlm - - - - - BUSER_WIDTH - 0 - - - simulation.tlm - - - - - READ_WRITE_MODE - READ_WRITE - - - simulation.tlm - - - - - HAS_BURST - 0 - - - simulation.tlm - - - - - HAS_LOCK - 0 - - - simulation.tlm - - - - - HAS_PROT - 0 - - - simulation.tlm - - - - - HAS_CACHE - 0 - - - simulation.tlm - - - - - HAS_QOS - 0 - - - simulation.tlm - - - - - HAS_REGION - 0 - - - simulation.tlm - - - - - HAS_WSTRB - 0 - - - simulation.tlm - - - - - HAS_BRESP - 0 - - - simulation.tlm - - - - - HAS_RRESP - 0 - - - simulation.tlm - - - - - SUPPORTS_NARROW_BURST - 0 - - - simulation.tlm - - - - - NUM_READ_OUTSTANDING - 1 - - - simulation.tlm - - - - - NUM_WRITE_OUTSTANDING - 1 - - - simulation.tlm - - - - - MAX_BURST_LENGTH - 1 - - - simulation.tlm - - - - - PHASE - 0.000 - - - simulation.tlm - - - - - CLK_DOMAIN - - - - simulation.tlm - - - - - NUM_READ_THREADS - 1 - - - simulation.tlm - - - - - NUM_WRITE_THREADS - 1 - - - simulation.tlm - - - - - RUSER_BITS_PER_BYTE - 0 - - - simulation.tlm - - - - - WUSER_BITS_PER_BYTE - 0 - - - simulation.tlm - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - RESET - - - - - - - RST - - - aresetn - - - - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - ACLKEN - - - - - - - CE - - - aclken - - - - - - POLARITY - ACTIVE_LOW - - - none - - - - - - - - false - - - - - - CLOCK - - - - - - - CLK - - - aclk - - - - - - ASSOCIATED_BUSIF - M_AXI:S_AXI - - - ASSOCIATED_RESET - aresetn - - - FREQ_HZ - 100000000 - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - M_AXI_TLM - - - - - - - AXIMM_READ_SOCKET - - - M_INITIATOR_rd_socket - - - - - AXIMM_WRITE_SOCKET - - - M_INITIATOR_wr_socket - - - - - - S_AXI_TLM - - - - - - - AXIMM_READ_SOCKET - - - S_TARGET_rd_socket - - - - - AXIMM_WRITE_SOCKET - - - S_TARGET_wr_socket - - - - - - - - Master_AXI - 4294967296 - 32 - - - - true - - - - - - - - S_AXI - - Reg - 0 - 65536 - 32 - read-write - - - - false - - - - - - - - - - xilinx_veriloginstantiationtemplate - Verilog Instantiation Template - verilogSource:vivado.xilinx.com:synthesis.template - verilog - - xilinx_veriloginstantiationtemplate_view_fileset - - - - GENtimestamp - Mon Feb 14 15:48:27 UTC 2022 - - - outputProductCRC - 9:b40c5c85 - - - - - xilinx_verilogsynthesis - Verilog Synthesis - verilogSource:vivado.xilinx.com:synthesis - verilog - axi_vip_v1_1_8_top - - xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset - - - xilinx_verilogsynthesis_view_fileset - - - - GENtimestamp - Mon Feb 14 15:49:50 UTC 2022 - - - outputProductCRC - 9:b40c5c85 - - - - - xilinx_synthesisconstraints - Synthesis Constraints - :vivado.xilinx.com:synthesis.constraints - - xilinx_synthesisconstraints_view_fileset - - - - GENtimestamp - Mon Feb 14 15:49:50 UTC 2022 - - - outputProductCRC - 9:b40c5c85 - - - - - xilinx_verilogsynthesiswrapper - Verilog Synthesis Wrapper - verilogSource:vivado.xilinx.com:synthesis.wrapper - verilog - axi_mst_0 - - xilinx_verilogsynthesiswrapper_view_fileset - - - - GENtimestamp - Mon Feb 14 15:49:50 UTC 2022 - - - outputProductCRC - 9:b40c5c85 - - - - - xilinx_versioninformation - Version Information - :vivado.xilinx.com:docs.versioninfo - axi_vip_v1_1_8_top - - xilinx_versioninformation_view_fileset - - - - GENtimestamp - Mon Feb 14 15:49:50 UTC 2022 - - - outputProductCRC - 9:b40c5c85 - - - - - xilinx_externalfiles - External Files - :vivado.xilinx.com:external.files - - xilinx_externalfiles_view_fileset - - - - GENtimestamp - Mon Feb 14 15:51:07 UTC 2022 - - - outputProductCRC - 9:b40c5c85 - - - - - xilinx_verilogbehavioralsimulation - Verilog Simulation - verilogSource:vivado.xilinx.com:simulation - verilog - axi_vip_v1_1_8_top - - xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset - - - xilinx_verilogbehavioralsimulation_view_fileset - - - - GENtimestamp - Fri Apr 08 13:54:03 UTC 2022 - - - outputProductCRC - 9:a9f86b20 - - - - - xilinx_systemcsimulation - SystemC Simulation - systemCSource:vivado.xilinx.com:simulation - systemc - axi_vip - - xilinx_systemcsimulation_view_fileset - - - - GENtimestamp - Fri Apr 08 13:54:03 UTC 2022 - - - outputProductCRC - 9:81fdbefd - - - sim_type - tlm - - - use_subcore_outputs - false - - - - - xilinx_verilogsimulationwrapper - Verilog Simulation Wrapper - verilogSource:vivado.xilinx.com:simulation.wrapper - verilog - axi_mst_0 - - xilinx_verilogsimulationwrapper_view_fileset - - - - GENtimestamp - Fri Apr 08 13:54:03 UTC 2022 - - - outputProductCRC - 9:a9f86b20 - - - - - xilinx_systemcsimulationwrapper - SystemC Simulation Wrapper - systemCSource:vivado.xilinx.com:simulation.wrapper - systemc - axi_mst_0 - - xilinx_systemcsimulationwrapper_view_fileset - - - - GENtimestamp - Fri Apr 08 13:54:03 UTC 2022 - - - outputProductCRC - 9:81fdbefd - - - sim_type - tlm - - - - - - - aclk - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - aclken - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 1 - - - - - - false - - - - - - aresetn - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 1 - - - - - - true - - - - - - s_axi_awid - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_awaddr - - in - - 31 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_awlen - - in - - 7 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_awsize - - in - - 2 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_awburst - - in - - 1 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 1 - - - - - - false - - - - - - s_axi_awlock - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_awcache - 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- - - - - - false - - - - - - s_axi_wid - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_wdata - - in - - 31 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_wstrb - - in - - 3 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0xF - - - - - - false - - - - - - s_axi_wlast - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_wuser - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_wvalid - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_wready - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - s_axi_bid - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - s_axi_bresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - s_axi_buser - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - s_axi_bvalid - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - s_axi_bready - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arid - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_araddr - - in - - 31 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arlen - - in - - 7 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arsize - - in - - 2 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arburst - - in - - 1 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 1 - - - - - - false - - - - - - s_axi_arlock - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arcache - - in - - 3 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arprot - - in - - 2 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arregion - - in - - 3 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arqos - - in - - 3 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_aruser - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arvalid - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arready - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - s_axi_rid - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - s_axi_rdata - - out - - 31 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - s_axi_rresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - s_axi_rlast - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - s_axi_ruser - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - s_axi_rvalid - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - s_axi_rready - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - m_axi_awid - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_awaddr - - out - - 31 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - m_axi_awlen - - out - - 7 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_awsize - - out - - 2 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_awburst - - out - - 1 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_awlock - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_awcache - - out - - 3 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_awprot - - out - - 2 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - m_axi_awregion - - out - - 3 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_awqos - - out - - 3 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_awuser - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_awvalid - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - m_axi_awready - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - true - - - - - - m_axi_wid - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_wdata - - out - - 31 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - m_axi_wstrb - - out - - 3 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - m_axi_wlast - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_wuser - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_wvalid - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - m_axi_wready - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - true - - - - - - m_axi_bid - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - m_axi_bresp - - in - - 1 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - true - - - - - - m_axi_buser - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - m_axi_bvalid - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - true - - - - - - m_axi_bready - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - m_axi_arid - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_araddr - - out - - 31 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - m_axi_arlen - - out - - 7 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_arsize - - out - - 2 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_arburst - - out - - 1 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_arlock - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_arcache - - out - - 3 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_arprot - - out - - 2 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - m_axi_arregion - - out - - 3 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_arqos - - out - - 3 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_aruser - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_arvalid - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - m_axi_arready - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - true - - - - - - m_axi_rid - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - m_axi_rdata - - in - - 31 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - true - - - - - - m_axi_rresp - - in - - 1 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - true - - - - - - m_axi_rlast - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - m_axi_ruser - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - m_axi_rvalid - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - true - - - - - - m_axi_rready - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - M_INITIATOR_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - M_INITIATOR_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - S_TARGET_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - wr_socket - - - - - - - 1 - - - - - S_TARGET_rd_socket - AXIMM Read Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - rd_socket - - - - - - - 1 - - - - - - - C_AXI_PROTOCOL - 2 - - - C_AXI_INTERFACE_MODE - 0 - - - C_AXI_ADDR_WIDTH - 32 - - - C_AXI_WDATA_WIDTH - 32 - - - C_AXI_RDATA_WIDTH - 32 - - - C_AXI_WID_WIDTH - 0 - - - C_AXI_RID_WIDTH - 0 - - - C_AXI_AWUSER_WIDTH - 0 - - - C_AXI_ARUSER_WIDTH - 0 - - - C_AXI_WUSER_WIDTH - 0 - - - C_AXI_RUSER_WIDTH - 0 - - - C_AXI_BUSER_WIDTH - 0 - - - C_AXI_SUPPORTS_NARROW - 0 - - - C_AXI_HAS_BURST - 0 - - - C_AXI_HAS_LOCK - 0 - - - C_AXI_HAS_CACHE - 0 - - - C_AXI_HAS_REGION - 0 - - - C_AXI_HAS_PROT - 1 - - - C_AXI_HAS_QOS - 0 - - - C_AXI_HAS_WSTRB - 1 - - - C_AXI_HAS_BRESP - 1 - - - C_AXI_HAS_RRESP - 1 - - - C_AXI_HAS_ARESETN - 1 - - - - - - choice_list_04fafd91 - AXI3 - AXI4 - AXI4LITE - - - choice_list_6240decd - READ_ONLY - READ_WRITE - WRITE_ONLY - - - choice_list_642e7122 - MASTER - PASS_THROUGH - SLAVE - - - choice_list_99ba8646 - 32 - 64 - - - choice_list_9d8b0d81 - ACTIVE_HIGH - ACTIVE_LOW - - - choice_pairs_0fc128e8 - 0 - 0 - - - - - xilinx_veriloginstantiationtemplate_view_fileset - - axi_mst_0.vho - vhdlTemplate - - - axi_mst_0.veo - verilogTemplate - - - - xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset - - hdl/axi_infrastructure_v1_1_0.vh - verilogSource - true - axi_infrastructure_v1_1_0 - - - hdl/axi_infrastructure_v1_1_vl_rfs.v - verilogSource - axi_infrastructure_v1_1_0 - - - - - - - - - - - xilinx_verilogsynthesis_view_fileset - - hdl/axi_vip_v1_1_vlsyn_rfs.sv - systemVerilogSource - axi_vip_v1_1_8 - - - - xilinx_synthesisconstraints_view_fileset - - axi_mst_0_ooc.xdc - xdc - USED_IN_implementation - USED_IN_out_of_context - USED_IN_synthesis - - - - xilinx_verilogsynthesiswrapper_view_fileset - - synth/axi_mst_0.sv - systemVerilogSource - xil_defaultlib - - - - xilinx_versioninformation_view_fileset - - doc/axi_vip_v1_1_changelog.txt - text - axi_vip_v1_1_8 - - - - xilinx_externalfiles_view_fileset - - axi_mst_0.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - axi_mst_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - axi_mst_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - axi_mst_0_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - axi_mst_0_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - - xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset - - hdl/axi_infrastructure_v1_1_0.vh - verilogSource - USED_IN_ipstatic - true - axi_infrastructure_v1_1_0 - - - hdl/axi_infrastructure_v1_1_vl_rfs.v - verilogSource - USED_IN_ipstatic - axi_infrastructure_v1_1_0 - - - - - - - - - - - xilinx_verilogbehavioralsimulation_view_fileset - - sim/axi_mst_0_pkg.sv - systemVerilogSource - - - hdl/axi_vip_v1_1_vl_rfs.sv - systemVerilogSource - USED_IN_ipstatic - axi_vip_v1_1_8 - - - - xilinx_systemcsimulation_view_fileset - - sysc/axi_vip.cpp - systemCSource - axi_vip_v1_1_8 - - - sysc/axi_vip.h - systemCSource - true - axi_vip_v1_1_8 - - - - xilinx_verilogsimulationwrapper_view_fileset - - sim/axi_mst_0.sv - systemVerilogSource - xil_defaultlib - - - - xilinx_systemcsimulationwrapper_view_fileset - - sim/axi_mst_0_sc.h - systemCSource - true - - - sim/axi_mst_0_sc.cpp - systemCSource - - - sim/axi_mst_0.h - systemCSource - true - - - sim/axi_mst_0.cpp - systemCSource - - - sim/axi_mst_0_stub.sv - systemVerilogSource - - - - The AXI Verification IP. - - - Component_Name - Component Name - axi_mst_0 - - - PROTOCOL - PROTOCOL - AXI4LITE - - - READ_WRITE_MODE - READ_WRITE MODE - READ_WRITE - - - INTERFACE_MODE - INTERFACE MODE - MASTER - - - ADDR_WIDTH - ADDRESS WIDTH - 32 - - - DATA_WIDTH - DATA WIDTH - 32 - - - ID_WIDTH - ID WIDTH - 0 - - - - false - - - - - - AWUSER_WIDTH - AWUSER WIDTH - 0 - - - - false - - - - - - ARUSER_WIDTH - ARUSER WIDTH - 0 - - - - false - - - - - - RUSER_WIDTH - RUSER WIDTH - 0 - - - - false - - - - - - WUSER_WIDTH - WUSER WIDTH - 0 - - - - false - - - - - - BUSER_WIDTH - BUSER WIDTH - 0 - - - - false - - - - - - WUSER_BITS_PER_BYTE - WUSER BITS PER BYTE - 0 - - - - false - - - - - - RUSER_BITS_PER_BYTE - RUSER BITS PER BYTE - 0 - - - - false - - - - - - HAS_USER_BITS_PER_BYTE - HAS USER_BITS_PER_BYTE - 0 - - - - false - - - - - - SUPPORTS_NARROW - SUPPORTS NARROW - 0 - - - - false - - - - - - HAS_SIZE - HAS SIZE - 0 - - - - false - - - - - - HAS_BURST - HAS BURST - 0 - - - - false - - - - - - HAS_LOCK - HAS LOCK - 0 - - - - false - - - - - - HAS_CACHE - HAS CACHE - 0 - - - - false - - - - - - HAS_REGION - HAS REGION - 0 - - - - false - - - - - - HAS_QOS - HAS QOS - 0 - - - - false - - - - - - HAS_PROT - HAS PROT - 1 - - - HAS_WSTRB - HAS WSTRB - 1 - - - HAS_BRESP - HAS BRESP - 1 - - - HAS_RRESP - HAS RRESP - 1 - - - HAS_ACLKEN - HAS ACLKEN - 0 - - - HAS_ARESETN - HAS ARESETN - 1 - - - - - AXI Verification IP - - xtlm - - 8 - true - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2020.2 - - - - - - - - - - diff --git a/qick/firmware/ip/axis_signal_gen_v6/src/axi_slv.vhd b/qick/firmware/ip/axis_signal_gen_v6/src/axi_slv.vhd deleted file mode 100644 index c60ea98..0000000 --- a/qick/firmware/ip/axis_signal_gen_v6/src/axi_slv.vhd +++ /dev/null @@ -1,516 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity axi_slv is - Generic - ( - DATA_WIDTH : integer := 32; - ADDR_WIDTH : integer := 6 - ); - Port - ( - aclk : in std_logic; - aresetn : in std_logic; - - -- Write Address Channel. - awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); - awprot : in std_logic_vector(2 downto 0); - awvalid : in std_logic; - awready : out std_logic; - - -- Write Data Channel. - wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); - wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); - wvalid : in std_logic; - wready : out std_logic; - - -- Write Response Channel. - bresp : out std_logic_vector(1 downto 0); - bvalid : out std_logic; - bready : in std_logic; - - -- Read Address Channel. - araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); - arprot : in std_logic_vector(2 downto 0); - arvalid : in std_logic; - arready : out std_logic; - - -- Read Data Channel. - rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); - rresp : out std_logic_vector(1 downto 0); - rvalid : out std_logic; - rready : in std_logic; - - -- Registers. - START_ADDR_REG : out std_logic_vector (31 downto 0); - WE_REG : out std_logic - ); -end axi_slv; - -architecture rtl of axi_slv is - - -- AXI4LITE signals - signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); - signal axi_awready : std_logic; - signal axi_wready : std_logic; - signal axi_bresp : std_logic_vector(1 downto 0); - signal axi_bvalid : std_logic; - signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); - signal axi_arready : std_logic; - signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); - signal axi_rresp : std_logic_vector(1 downto 0); - signal axi_rvalid : std_logic; - - -- Example-specific design signals - -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH - -- ADDR_LSB is used for addressing 32/64 bit registers/memories - -- ADDR_LSB = 2 for 32 bits (n downto 2) - -- ADDR_LSB = 3 for 64 bits (n downto 3) - constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; - constant OPT_MEM_ADDR_BITS : integer := 3; - ------------------------------------------------ - ---- Signals for user logic register space example - -------------------------------------------------- - ---- Number of Slave Registers 16 - signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); - signal slv_reg_rden : std_logic; - signal slv_reg_wren : std_logic; - signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); - signal byte_index : integer; - signal aw_en : std_logic; - -begin - -- I/O Connections assignments - - awreadY <= axi_awready; - wready <= axi_wready; - bresp <= axi_bresp; - bvalid <= axi_bvalid; - arreadY <= axi_arready; - rdata <= axi_rdata; - rresp <= axi_rresp; - rvalid <= axi_rvalid; - -- Implement axi_awready generation - -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is - -- de-asserted when reset is low. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_awready <= '0'; - aw_en <= '1'; - else - if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then - -- slave is ready to accept write address when - -- there is a valid write address and write data - -- on the write address and data bus. This design - -- expects no outstanding transactions. - axi_awready <= '1'; - aw_en <= '0'; - elsif (bready = '1' and axi_bvalid = '1') then - aw_en <= '1'; - axi_awready <= '0'; - else - axi_awready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement axi_awaddr latching - -- This process is used to latch the address when both - -- S_AXI_AWVALID and S_AXI_WVALID are valid. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_awaddr <= (others => '0'); - else - if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then - -- Write Address latching - axi_awaddr <= awaddr; - end if; - end if; - end if; - end process; - - -- Implement axi_wready generation - -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is - -- de-asserted when reset is low. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_wready <= '0'; - else - if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then - -- slave is ready to accept write data when - -- there is a valid write address and write data - -- on the write address and data bus. This design - -- expects no outstanding transactions. - axi_wready <= '1'; - else - axi_wready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement memory mapped register select and write logic generation - -- The write data is accepted and written to memory mapped registers when - -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to - -- select byte enables of slave registers while writing. - -- These registers are cleared when reset (active low) is applied. - -- Slave register write enable is asserted when valid address and data are available - -- and the slave is ready to accept the write address and write data. - slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; - - process (aclk) - variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); - begin - if rising_edge(aclk) then - if aresetn = '0' then - slv_reg0 <= (others => '0'); - slv_reg1 <= (others => '0'); - slv_reg2 <= (others => '0'); - slv_reg3 <= (others => '0'); - slv_reg4 <= (others => '0'); - slv_reg5 <= (others => '0'); - slv_reg6 <= (others => '0'); - slv_reg7 <= (others => '0'); - slv_reg8 <= (others => '0'); - slv_reg9 <= (others => '0'); - slv_reg10 <= (others => '0'); - slv_reg11 <= (others => '0'); - slv_reg12 <= (others => '0'); - slv_reg13 <= (others => '0'); - slv_reg14 <= (others => '0'); - slv_reg15 <= (others => '0'); - else - loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); - if (slv_reg_wren = '1') then - case loc_addr is - when b"0000" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 0 - slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0001" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 1 - slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0010" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 2 - slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0011" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 3 - slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0100" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 4 - slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0101" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 5 - slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0110" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 6 - slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0111" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 7 - slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1000" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 8 - slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1001" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 9 - slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1010" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 10 - slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1011" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 11 - slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1100" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 12 - slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1101" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 13 - slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1110" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 14 - slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1111" => - for byte_index in 0 to (DATA_WIDTH/8-1) loop - if ( wstrb(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 15 - slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when others => - slv_reg0 <= slv_reg0; - slv_reg1 <= slv_reg1; - slv_reg2 <= slv_reg2; - slv_reg3 <= slv_reg3; - slv_reg4 <= slv_reg4; - slv_reg5 <= slv_reg5; - slv_reg6 <= slv_reg6; - slv_reg7 <= slv_reg7; - slv_reg8 <= slv_reg8; - slv_reg9 <= slv_reg9; - slv_reg10 <= slv_reg10; - slv_reg11 <= slv_reg11; - slv_reg12 <= slv_reg12; - slv_reg13 <= slv_reg13; - slv_reg14 <= slv_reg14; - slv_reg15 <= slv_reg15; - end case; - end if; - end if; - end if; - end process; - - -- Implement write response logic generation - -- The write response and response valid signals are asserted by the slave - -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. - -- This marks the acceptance of address and indicates the status of - -- write transaction. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_bvalid <= '0'; - axi_bresp <= "00"; --need to work more on the responses - else - if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then - axi_bvalid <= '1'; - axi_bresp <= "00"; - elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) - axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) - end if; - end if; - end if; - end process; - - -- Implement axi_arready generation - -- axi_arready is asserted for one S_AXI_ACLK clock cycle when - -- S_AXI_ARVALID is asserted. axi_awready is - -- de-asserted when reset (active low) is asserted. - -- The read address is also latched when S_AXI_ARVALID is - -- asserted. axi_araddr is reset to zero on reset assertion. - - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_arready <= '0'; - axi_araddr <= (others => '1'); - else - if (axi_arready = '0' and arvalid = '1') then - -- indicates that the slave has acceped the valid read address - axi_arready <= '1'; - -- Read Address latching - axi_araddr <= araddr; - else - axi_arready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement axi_arvalid generation - -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_ARVALID and axi_arready are asserted. The slave registers - -- data are available on the axi_rdata bus at this instance. The - -- assertion of axi_rvalid marks the validity of read data on the - -- bus and axi_rresp indicates the status of read transaction.axi_rvalid - -- is deasserted on reset (active low). axi_rresp and axi_rdata are - -- cleared to zero on reset (active low). - process (aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then - axi_rvalid <= '0'; - axi_rresp <= "00"; - else - if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then - -- Valid read data is available at the read data bus - axi_rvalid <= '1'; - axi_rresp <= "00"; -- 'OKAY' response - elsif (axi_rvalid = '1' and rready = '1') then - -- Read data is accepted by the master - axi_rvalid <= '0'; - end if; - end if; - end if; - end process; - - -- Implement memory mapped register select and read logic generation - -- Slave register read enable is asserted when valid address is available - -- and the slave is ready to accept the read address. - slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; - - process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) - variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); - begin - -- Address decoding for reading registers - loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); - case loc_addr is - when b"0000" => - reg_data_out <= slv_reg0; - when b"0001" => - reg_data_out <= slv_reg1; - when b"0010" => - reg_data_out <= slv_reg2; - when b"0011" => - reg_data_out <= slv_reg3; - when b"0100" => - reg_data_out <= slv_reg4; - when b"0101" => - reg_data_out <= slv_reg5; - when b"0110" => - reg_data_out <= slv_reg6; - when b"0111" => - reg_data_out <= slv_reg7; - when b"1000" => - reg_data_out <= slv_reg8; - when b"1001" => - reg_data_out <= slv_reg9; - when b"1010" => - reg_data_out <= slv_reg10; - when b"1011" => - reg_data_out <= slv_reg11; - when b"1100" => - reg_data_out <= slv_reg12; - when b"1101" => - reg_data_out <= slv_reg13; - when b"1110" => - reg_data_out <= slv_reg14; - when b"1111" => - reg_data_out <= slv_reg15; - when others => - reg_data_out <= (others => '0'); - end case; - end process; - - -- Output register or memory read data - process( aclk ) is - begin - if (rising_edge (aclk)) then - if ( aresetn = '0' ) then - axi_rdata <= (others => '0'); - else - if (slv_reg_rden = '1') then - -- When there is a valid read address (S_AXI_ARVALID) with - -- acceptance of read address by the slave (axi_arready), - -- output the read dada - -- Read address mux - axi_rdata <= reg_data_out; -- register read data - end if; - end if; - end if; - end process; - - -- Register Map. - -- 0 : START_ADDR_REG : 32-bit. Start address to write into memory. - -- 1 : WE_REG : 1-bit. Enable write into memory. - - -- Output Registers. - START_ADDR_REG <= slv_reg0; - WE_REG <= slv_reg1(0); - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v6/src/axis_signal_gen_v6.v b/qick/firmware/ip/axis_signal_gen_v6/src/axis_signal_gen_v6.v deleted file mode 100644 index 3d27102..0000000 --- a/qick/firmware/ip/axis_signal_gen_v6/src/axis_signal_gen_v6.v +++ /dev/null @@ -1,198 +0,0 @@ -// Signal Generator V4. -// s_axi_aclk : clock for s_axi_* -// s0_axis_aclk : clock for s0_axis_* -// aclk : clock for s1_axis_* and m_axis_* -// -module axis_signal_gen_v6 - ( - // AXI Slave I/F for configuration. - s_axi_aclk , - s_axi_aresetn , - - s_axi_awaddr , - s_axi_awprot , - s_axi_awvalid , - s_axi_awready , - - s_axi_wdata , - s_axi_wstrb , - s_axi_wvalid , - s_axi_wready , - - s_axi_bresp , - s_axi_bvalid , - s_axi_bready , - - s_axi_araddr , - s_axi_arprot , - s_axi_arvalid , - s_axi_arready , - - s_axi_rdata , - s_axi_rresp , - s_axi_rvalid , - s_axi_rready , - - // AXIS Slave to load memory samples. - s0_axis_aclk , - s0_axis_aresetn , - s0_axis_tdata , - s0_axis_tvalid , - s0_axis_tready , - - // s1_* and m_* reset/clock. - aclk , - aresetn , - - // AXIS Slave to queue waveforms. - s1_axis_tdata , - s1_axis_tvalid , - s1_axis_tready , - - // AXIS Master for output. - m_axis_tready , - m_axis_tvalid , - m_axis_tdata - ); - -/**************/ -/* Parameters */ -/**************/ -parameter N = 12; - -// Number of parallel dds blocks. -parameter [31:0] N_DDS = 16; - -/*********/ -/* Ports */ -/*********/ -input s_axi_aclk; -input s_axi_aresetn; - -input [5:0] s_axi_awaddr; -input [2:0] s_axi_awprot; -input s_axi_awvalid; -output s_axi_awready; - -input [31:0] s_axi_wdata; -input [3:0] s_axi_wstrb; -input s_axi_wvalid; -output s_axi_wready; - -output [1:0] s_axi_bresp; -output s_axi_bvalid; -input s_axi_bready; - -input [5:0] s_axi_araddr; -input [2:0] s_axi_arprot; -input s_axi_arvalid; -output s_axi_arready; - -output [31:0] s_axi_rdata; -output [1:0] s_axi_rresp; -output s_axi_rvalid; -input s_axi_rready; - -input s0_axis_aclk; -input s0_axis_aresetn; -input [31:0] s0_axis_tdata; -input s0_axis_tvalid; -output s0_axis_tready; - -input aresetn; -input aclk; - -input [159:0] s1_axis_tdata; -input s1_axis_tvalid; -output s1_axis_tready; - -input m_axis_tready; -output m_axis_tvalid; -output [N_DDS*16-1:0] m_axis_tdata; - -/********************/ -/* Internal signals */ -/********************/ -// Registers. -wire [31:0] START_ADDR_REG; -wire WE_REG; - - -/**********************/ -/* Begin Architecture */ -/**********************/ -// AXI Slave. -axi_slv axi_slv_i - ( - .aclk (s_axi_aclk ), - .aresetn (s_axi_aresetn ), - - // Write Address Channel. - .awaddr (s_axi_awaddr ), - .awprot (s_axi_awprot ), - .awvalid (s_axi_awvalid ), - .awready (s_axi_awready ), - - // Write Data Channel. - .wdata (s_axi_wdata ), - .wstrb (s_axi_wstrb ), - .wvalid (s_axi_wvalid ), - .wready (s_axi_wready ), - - // Write Response Channel. - .bresp (s_axi_bresp ), - .bvalid (s_axi_bvalid ), - .bready (s_axi_bready ), - - // Read Address Channel. - .araddr (s_axi_araddr ), - .arprot (s_axi_arprot ), - .arvalid (s_axi_arvalid ), - .arready (s_axi_arready ), - - // Read Data Channel. - .rdata (s_axi_rdata ), - .rresp (s_axi_rresp ), - .rvalid (s_axi_rvalid ), - .rready (s_axi_rready ), - - // Registers. - .START_ADDR_REG (START_ADDR_REG ), - .WE_REG (WE_REG ) - ); - -signal_gen_top - #( - .N (N ), - .N_DDS (N_DDS ) - ) - signal_gen_top_i - ( - // Reset and clock. - .aresetn (aresetn ), - .aclk (aclk ), - - // AXIS Slave to load memory samples. - .s0_axis_aresetn (s0_axis_aresetn ), - .s0_axis_aclk (s0_axis_aclk ), - .s0_axis_tdata_i (s0_axis_tdata ), - .s0_axis_tvalid_i (s0_axis_tvalid ), - .s0_axis_tready_o (s0_axis_tready ), - - // AXIS Slave to queue waveforms. - .s1_axis_tdata_i (s1_axis_tdata ), - .s1_axis_tvalid_i (s1_axis_tvalid ), - .s1_axis_tready_o (s1_axis_tready ), - - // M_AXIS for output. - .m_axis_tready_i (m_axis_tready ), - .m_axis_tvalid_o (m_axis_tvalid ), - .m_axis_tdata_o (m_axis_tdata ), - - // Registers. - .START_ADDR_REG (START_ADDR_REG ), - .WE_REG (WE_REG ) - ); - -endmodule - diff --git a/qick/firmware/ip/axis_signal_gen_v6/src/ctrl.sv b/qick/firmware/ip/axis_signal_gen_v6/src/ctrl.sv deleted file mode 100644 index 76767e5..0000000 --- a/qick/firmware/ip/axis_signal_gen_v6/src/ctrl.sv +++ /dev/null @@ -1,497 +0,0 @@ -//Format of waveform interface: -// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| -// | 159 .. 149 | 148 | 147 | 146 | 145 .. 144 | 143 .. 128 | 127 .. 112 | 111 .. 96 | 95 .. 80 | 79 .. 64 | 63 .. 32 | 31 .. 0 | -// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| -// | xxxx | phrst | stdysel | mode | outsel | nsamp | xxxx | gain | xxxx | addr | phase | freq | -// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| -// freq : 32 bits -// phase : 32 bits -// addr : 16 bits -// gain : 16 bits -// nsamp : 16 bits -// outsel : 2 bits -// mode : 1 bit -// stdysel : 1 bit -// phrst : 1 bit -module ctrl ( - // Reset and clock. - rstn , - clk , - - // Fifo interface. - fifo_rd_en_o , - fifo_empty_i , - fifo_dout_i , - - // dds control. - dds_ctrl_o , - - // memory control. - mem_addr_o , - - // gain. - gain_o , - - // Output source selection. - src_o , - - // Steady value selection. - stdy_o , - - // Output enable. - en_o ); - -// Memory address size. -parameter N = 16; - -// Number of parallel dds blocks. -parameter [31:0] N_DDS = 16; - -// Ports. -input rstn; -input clk; -output fifo_rd_en_o; -input fifo_empty_i; -input [159:0] fifo_dout_i; -output [N_DDS*72-1:0] dds_ctrl_o; -output [N-1:0] mem_addr_o; -output [15:0] gain_o; -output [1:0] src_o; -output stdy_o; -output en_o; - -// States. -typedef enum { READ_ST , - CNT_ST - } state_t; - -// State register. -(* fsm_encoding = "one_hot" *) state_t state; - -// Fifo dout register. -reg [159:0] fifo_dout_r; - -// Non-stop counter for time calculation (adds N_DDS samples each clock tick). -reg [31:0] cnt_n; -reg [31:0] cnt_n_reg; - -// Pinc/phase. -wire [31:0] pinc_int; -reg [31:0] pinc_r1; -reg [31:0] pinc_r2; -wire [31:0] pinc_N; -reg [31:0] pinc_N_r1; -reg [31:0] pinc_N_r2; -reg [31:0] pinc_N_r3; -reg [31:0] pinc_N_r4; -reg [31:0] pinc_N_r5; -wire [31:0] pinc_Nm; -reg [31:0] pinc_Nm_r1; -reg [31:0] pinc_Nm_r2; -reg [31:0] pinc_Nm_r3; - -wire [31:0] phase_int; -reg [31:0] phase_r1; -reg [31:0] phase_r2; -reg [31:0] phase_r3; -reg [31:0] phase_r4; -reg [31:0] phase_r5; -wire [31:0] phase_0; -reg [31:0] phase_0_r1; - -// Phase vectors. -wire [31:0] phase_v0 [0:N_DDS-1]; -reg [31:0] phase_v0_r1 [0:N_DDS-1]; -reg [31:0] phase_v0_r2 [0:N_DDS-1]; -reg [31:0] phase_v0_r3 [0:N_DDS-1]; -reg [31:0] phase_v0_r4 [0:N_DDS-1]; -wire [31:0] phase_v1 [0:N_DDS-1]; -reg [31:0] phase_v1_r1 [0:N_DDS-1]; - -// sync. -reg sync_reg; -reg sync_reg_r1; -reg sync_reg_r2; -reg sync_reg_r3; -reg sync_reg_r4; -reg sync_reg_r5; -reg sync_reg_r6; -reg sync_reg_r7; - -// Address. -wire [15:0] addr_int; -reg [15:0] addr_cnt; -reg [15:0] addr_cnt_r1; -reg [15:0] addr_cnt_r2; -reg [15:0] addr_cnt_r3; -reg [15:0] addr_cnt_r4; -reg [15:0] addr_cnt_r5; -reg [15:0] addr_cnt_r6; - -// Gain. -wire [15:0] gain_int; -reg [15:0] gain_r1; -reg [15:0] gain_r2; -reg [15:0] gain_r3; -reg [15:0] gain_r4; -reg [15:0] gain_r5; -reg [15:0] gain_r6; -reg [15:0] gain_r7; - -// Number of samples. -wire [15:0] nsamp_int; - -// Output selection. -wire [1:0] outsel_int; -reg [1:0] outsel_r1; -reg [1:0] outsel_r2; -reg [1:0] outsel_r3; -reg [1:0] outsel_r4; -reg [1:0] outsel_r5; -reg [1:0] outsel_r6; -reg [1:0] outsel_r7; - -// Mode. -wire mode_int; - -// Steady value selection. -wire stdysel_int; -reg stdysel_r1; -reg stdysel_r2; -reg stdysel_r3; -reg stdysel_r4; -reg stdysel_r5; -reg stdysel_r6; -reg stdysel_r7; - -// Phase reset. -wire phrst_int; - -// Load enable flag. -wire load_int; -reg load_r; - -// Fifo Read Enable. -reg rd_en_int; -reg rd_en_r1; -reg rd_en_r2; - -// Counter. -reg [31:0] cnt; - -// Output enable register. -reg en_reg; -reg en_reg_r1; -reg en_reg_r2; -reg en_reg_r3; -reg en_reg_r4; -reg en_reg_r5; -reg en_reg_r6; -reg en_reg_r7; -reg en_reg_r8; - -// Registers. -always @(posedge clk) begin - if (~rstn) begin - // State register. - state <= READ_ST; - - // Fifo dout register. - fifo_dout_r <= 0; - - // Non-stop counter for time calculation. - cnt_n <= 0; - cnt_n_reg <= 0; - - // Pinc/phase/sync. - pinc_r1 <= 0; - pinc_r2 <= 0; - pinc_N_r1 <= 0; - pinc_N_r2 <= 0; - pinc_N_r3 <= 0; - pinc_N_r4 <= 0; - pinc_N_r5 <= 0; - pinc_Nm_r1 <= 0; - pinc_Nm_r2 <= 0; - pinc_Nm_r3 <= 0; - - phase_r1 <= 0; - phase_r2 <= 0; - phase_r3 <= 0; - phase_r4 <= 0; - phase_r5 <= 0; - phase_0_r1 <= 0; - - sync_reg <= 0; - sync_reg_r1 <= 0; - sync_reg_r2 <= 0; - sync_reg_r3 <= 0; - sync_reg_r4 <= 0; - sync_reg_r5 <= 0; - sync_reg_r6 <= 0; - sync_reg_r7 <= 0; - - // Address. - addr_cnt <= 0; - addr_cnt_r1 <= 0; - addr_cnt_r2 <= 0; - addr_cnt_r3 <= 0; - addr_cnt_r4 <= 0; - addr_cnt_r5 <= 0; - addr_cnt_r6 <= 0; - - // Gain. - gain_r1 <= 0; - gain_r2 <= 0; - gain_r3 <= 0; - gain_r4 <= 0; - gain_r5 <= 0; - gain_r6 <= 0; - gain_r7 <= 0; - - // Output selection. - outsel_r1 <= 0; - outsel_r2 <= 0; - outsel_r3 <= 0; - outsel_r4 <= 0; - outsel_r5 <= 0; - outsel_r6 <= 0; - outsel_r7 <= 0; - - // Steady value selection. - stdysel_r1 <= 0; - stdysel_r2 <= 0; - stdysel_r3 <= 0; - stdysel_r4 <= 0; - stdysel_r5 <= 0; - stdysel_r6 <= 0; - stdysel_r7 <= 0; - - // Load enable flag. - load_r <= 0; - - // Fifo Read Enable. - rd_en_r1 <= 0; - rd_en_r2 <= 0; - - // Counter. - cnt <= 0; - - // Output enable register. - en_reg <= 0; - en_reg_r1 <= 0; - en_reg_r2 <= 0; - en_reg_r3 <= 0; - en_reg_r4 <= 0; - en_reg_r5 <= 0; - en_reg_r6 <= 0; - en_reg_r7 <= 0; - en_reg_r8 <= 0; - end - else begin - // State register. - case (state) - READ_ST: - if (mode_int || ~fifo_empty_i) - state <= CNT_ST; - CNT_ST: - if ( cnt == nsamp_int-2 ) - state <= READ_ST; - endcase - - // Fifo dout register. - if (load_r) - fifo_dout_r <= fifo_dout_i; - - // Non-stop counter for time calculation. - if (sync_reg == 1'b1 && phrst_int == 1'b1) - cnt_n <= 0; - else - cnt_n <= cnt_n + N_DDS; - - if (sync_reg_r1 == 1'b1) - cnt_n_reg <= cnt_n; - - // Pinc/phase/sync. - pinc_r1 <= pinc_int; - pinc_r2 <= pinc_r1; - pinc_N_r1 <= pinc_N; - pinc_N_r2 <= pinc_N_r1; - pinc_N_r3 <= pinc_N_r2; - pinc_N_r4 <= pinc_N_r3; - pinc_N_r5 <= pinc_N_r4; - pinc_Nm_r1 <= pinc_Nm; - pinc_Nm_r2 <= pinc_Nm_r1; - pinc_Nm_r3 <= pinc_Nm_r2; - - phase_r1 <= phase_int; - phase_r2 <= phase_r1; - phase_r3 <= phase_r2; - phase_r4 <= phase_r3; - phase_r5 <= phase_r4; - phase_0_r1 <= phase_0; - - sync_reg <= load_r; - sync_reg_r1 <= sync_reg; - sync_reg_r2 <= sync_reg_r1; - sync_reg_r3 <= sync_reg_r2; - sync_reg_r4 <= sync_reg_r3; - sync_reg_r5 <= sync_reg_r4; - sync_reg_r6 <= sync_reg_r5; - sync_reg_r7 <= sync_reg_r6; - - // Address. - if (rd_en_r2) - addr_cnt <= addr_int; - else - addr_cnt <= addr_cnt + 1; - - addr_cnt_r1 <= addr_cnt; - addr_cnt_r2 <= addr_cnt_r1; - addr_cnt_r3 <= addr_cnt_r2; - addr_cnt_r4 <= addr_cnt_r3; - addr_cnt_r5 <= addr_cnt_r4; - addr_cnt_r6 <= addr_cnt_r5; - - // Gain. - gain_r1 <= gain_int; - gain_r2 <= gain_r1; - gain_r3 <= gain_r2; - gain_r4 <= gain_r3; - gain_r5 <= gain_r4; - gain_r6 <= gain_r5; - gain_r7 <= gain_r6; - - // Output selection. - outsel_r1 <= outsel_int; - outsel_r2 <= outsel_r1; - outsel_r3 <= outsel_r2; - outsel_r4 <= outsel_r3; - outsel_r5 <= outsel_r4; - outsel_r6 <= outsel_r5; - outsel_r7 <= outsel_r6; - - // Steady value selection. - stdysel_r1 <= stdysel_int; - stdysel_r2 <= stdysel_r1; - stdysel_r3 <= stdysel_r2; - stdysel_r4 <= stdysel_r3; - stdysel_r5 <= stdysel_r4; - stdysel_r6 <= stdysel_r5; - stdysel_r7 <= stdysel_r6; - - // Load enable flag. - load_r <= load_int; - - // Fifo Read Enable. - rd_en_r1 <= rd_en_int; - rd_en_r2 <= rd_en_r1; - - // Counter. - if (rd_en_int) - cnt <= 0; - else - cnt <= cnt + 1; - - // Output enable register. - if (~mode_int && rd_en_int) - if (~fifo_empty_i) - en_reg <= 1; - else - en_reg <= 0; - - en_reg_r1 <= en_reg; - en_reg_r2 <= en_reg_r1; - en_reg_r3 <= en_reg_r2; - en_reg_r4 <= en_reg_r3; - en_reg_r5 <= en_reg_r4; - en_reg_r6 <= en_reg_r5; - en_reg_r7 <= en_reg_r6; - en_reg_r8 <= en_reg_r7; - end -end - -// FSM outputs. -always_comb begin - // Default. - rd_en_int = 0; - - case (state) - READ_ST: - rd_en_int = 1; - - CNT_ST: - rd_en_int = 0; - endcase -end - -// Fifo output fields. -assign pinc_int = fifo_dout_r[31:0]; -assign phase_int = fifo_dout_r[63:32]; -assign addr_int = fifo_dout_r[79:64]; -assign gain_int = fifo_dout_r[111:96]; -assign nsamp_int = fifo_dout_r[143:128]; -assign outsel_int = fifo_dout_r[145:144]; -assign mode_int = fifo_dout_r[146]; -assign stdysel_int = fifo_dout_r[147]; -assign phrst_int = fifo_dout_r[148]; - -// Frequency calculation. -assign pinc_N = pinc_r2*N_DDS; - -// Phase calculation. -assign pinc_Nm = pinc_r2*cnt_n_reg; -assign phase_0 = pinc_Nm_r3 + phase_r5; - -// Phase vectors. -generate -genvar i; - for (i=0; i < N_DDS; i = i + 1) begin : GEN_phase - // Registers. - always @(posedge clk) begin - if (~rstn) begin - // v0. - phase_v0_r1[i] <= 0; - phase_v0_r2[i] <= 0; - phase_v0_r3[i] <= 0; - phase_v0_r4[i] <= 0; - - // v1. - phase_v1_r1[i] <= 0; - end - else begin - // v0. - phase_v0_r1[i] <= phase_v0[i]; - phase_v0_r2[i] <= phase_v0_r1[i]; - phase_v0_r3[i] <= phase_v0_r2[i]; - phase_v0_r4[i] <= phase_v0_r3[i]; - - // v1. - phase_v1_r1[i] <= phase_v1[i]; - end - end - - // v0. - assign phase_v0[i] = pinc_r2*i; - - // v1. - assign phase_v1[i] = phase_v0_r4[i] + phase_0_r1; - - // dds_ctrl_o output. - assign dds_ctrl_o[i*72 +: 72] = {7'h00,sync_reg_r7,phase_v1_r1[i],pinc_N_r5}; - end -endgenerate - -// load_int. -assign load_int = rd_en_int & ~fifo_empty_i; - -// Assign outputs. -assign fifo_rd_en_o = rd_en_int; -assign mem_addr_o = addr_cnt_r6; -assign gain_o = gain_r7; -assign src_o = outsel_r7; -assign stdy_o = stdysel_r7; -assign en_o = en_reg_r8; - -endmodule - diff --git a/qick/firmware/ip/axis_signal_gen_v6/src/data_writer.vhd b/qick/firmware/ip/axis_signal_gen_v6/src/data_writer.vhd deleted file mode 100644 index cbf1912..0000000 --- a/qick/firmware/ip/axis_signal_gen_v6/src/data_writer.vhd +++ /dev/null @@ -1,226 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity data_writer is - Generic - ( - -- Number of tables. - NT : Integer := 16; - -- Address map of each table. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in STD_LOGIC; - clk : in STD_LOGIC; - - -- AXI Stream I/F. - s_axis_tready : out std_logic; - s_axis_tdata : in std_logic_vector(B-1 downto 0); - s_axis_tvalid : in std_logic; - - -- Memory I/F. - mem_en : out std_logic_vector (NT-1 downto 0); - mem_we : out std_logic; - mem_addr : out std_logic_vector (N-1 downto 0); - mem_di : out std_logic_vector (B-1 downto 0); - - -- Registers. - START_ADDR_REG : in std_logic_vector (31 downto 0); - WE_REG : in std_logic - ); -end data_writer; - -architecture rtl of data_writer is - --- Log2 of number of tables. -constant NT_LOG2 : Integer := Integer(ceil(log2(real(NT)))); - --- Synchronizer. -component synchronizer_n is - generic ( - N : Integer := 2 - ); - port ( - rstn : in std_logic; - clk : in std_logic; - data_in : in std_logic; - data_out : out std_logic - ); -end component; - --- State machine. -type fsm_state is ( INIT_ST , - READ_START_ADDR_ST , - WAIT_TVALID_ST , - RW_TDATA_ST ); -signal state : fsm_state; - -signal read_start_addr_state : std_logic; -signal rw_tdata_state : std_logic; - --- WE_REG_resync. -signal WE_REG_resync : std_logic; - --- Axis registers. -signal tready_i : std_logic; -signal tready_r : std_logic; -signal tdata_r : std_logic_vector(B-1 downto 0); -signal tdata_rr : std_logic_vector(B-1 downto 0); -signal tdata_rrr : std_logic_vector(B-1 downto 0); -signal tvalid_r : std_logic; -signal tvalid_rr : std_logic; -signal tvalid_rrr : std_logic; - --- Memory Enable. -signal mem_en_i : std_logic_vector (NT-1 downto 0); -signal mem_en_r : std_logic_vector (NT-1 downto 0); - --- Memory address space. -signal mem_addr_full : unsigned (NT_LOG2+N-1 downto 0); -signal mem_addr_low : unsigned (NT_LOG2-1 downto 0); -signal mem_addr_high : unsigned (N-1 downto 0); -signal mem_addr_high_r : unsigned (N-1 downto 0); - -begin - --- WE_REG_resync -WE_REG_resync_i : synchronizer_n - generic map ( - N => 2 - ) - port map ( - rstn => rstn , - clk => clk , - data_in => WE_REG , - data_out => WE_REG_resync - ); - --- Enable logic generation. -GEN: for I in 0 to NT-1 generate - - mem_en_i(I) <= '1' when mem_addr_low = to_unsigned(I,mem_addr_low'length) else - '0'; - -end generate GEN; - -process (clk) -begin - if ( rising_edge(clk) ) then - if (rstn = '0') then - -- Axis registers. - tready_r <= '0'; - tdata_r <= (others => '0'); - tdata_rr <= (others => '0'); - tdata_rrr <= (others => '0'); - tvalid_r <= '0'; - tvalid_rr <= '0'; - tvalid_rrr <= '0'; - - -- Memory address. - mem_addr_full <= (others => '0'); - mem_addr_high_r <= (others => '0'); - mem_en_r <= (others => '0'); - - else - -- Axis registers. - tready_r <= tready_i; - tdata_r <= s_axis_tdata; - tvalid_r <= s_axis_tvalid; - - -- Extra registers to account pipe of state machine. - tdata_rr <= tdata_r; - tdata_rrr <= tdata_rr; - tvalid_rr <= tvalid_r; - tvalid_rrr <= tvalid_rr; - - -- Memory address. - if ( read_start_addr_state = '1') then - mem_addr_full <= to_unsigned(to_integer(unsigned(START_ADDR_REG)),mem_addr_full'length); - elsif ( rw_tdata_state = '1' ) then - mem_addr_full <= mem_addr_full + 1; - end if; - mem_addr_high_r <= mem_addr_high; - mem_en_r <= mem_en_i; - - end if; - end if; -end process; - --- Address computation. -mem_addr_low <= mem_addr_full(NT_LOG2-1 downto 0); -mem_addr_high <= mem_addr_full(NT_LOG2+N-1 downto NT_LOG2); - --- Finite state machine. -process (clk) -begin - if ( rising_edge(clk) ) then - if ( rstn = '0' ) then - state <= INIT_ST; - else - case state is - when INIT_ST => - if ( WE_REG_resync = '1' ) then - state <= READ_START_ADDR_ST; - end if; - - when READ_START_ADDR_ST => - state <= WAIT_TVALID_ST; - - when WAIT_TVALID_ST => - if ( WE_REG_resync = '1') then - if ( tvalid_r = '0' ) then - state <= WAIT_TVALID_ST; - else - state <= RW_TDATA_ST; - end if; - else - state <= INIT_ST; - end if; - - when RW_TDATA_ST => - if ( tvalid_r = '0' ) then - state <= WAIT_TVALID_ST; - end if; - - end case; - end if; - end if; -end process; - --- Output logic. -process (state) -begin -read_start_addr_state <= '0'; -rw_tdata_state <= '0'; -tready_i <= '0'; - case state is - when INIT_ST => - - when READ_START_ADDR_ST => - read_start_addr_state <= '1'; - - when WAIT_TVALID_ST => - tready_i <= '1'; - - when RW_TDATA_ST => - rw_tdata_state <= '1'; - tready_i <= '1'; - - end case; -end process; - --- Assign output. -s_axis_tready <= tready_r; - -mem_en <= mem_en_r; -mem_we <= tvalid_rrr; -mem_addr <= std_logic_vector(mem_addr_high_r); -mem_di <= tdata_rrr; - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v6/src/dds_compiler_0/dds_compiler_0.veo b/qick/firmware/ip/axis_signal_gen_v6/src/dds_compiler_0/dds_compiler_0.veo deleted file mode 100644 index 894ecd6..0000000 --- a/qick/firmware/ip/axis_signal_gen_v6/src/dds_compiler_0/dds_compiler_0.veo +++ /dev/null @@ -1,69 +0,0 @@ -// (c) Copyright 1995-2021 Xilinx, Inc. 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Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -// IP VLNV: xilinx.com:ip:dds_compiler:6.0 -// IP Revision: 18 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -dds_compiler_0 your_instance_name ( - .aclk(aclk), // input wire aclk - .s_axis_phase_tvalid(s_axis_phase_tvalid), // input wire s_axis_phase_tvalid - .s_axis_phase_tdata(s_axis_phase_tdata), // input wire [71 : 0] s_axis_phase_tdata - .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid - .m_axis_data_tdata(m_axis_data_tdata) // output wire [31 : 0] m_axis_data_tdata -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file dds_compiler_0.v when simulating -// the core, dds_compiler_0. When compiling the wrapper file, be sure to -// reference the Verilog simulation library. - diff --git a/qick/firmware/ip/axis_signal_gen_v6/src/dds_compiler_0/dds_compiler_0.vho b/qick/firmware/ip/axis_signal_gen_v6/src/dds_compiler_0/dds_compiler_0.vho deleted file mode 100644 index e65044c..0000000 --- a/qick/firmware/ip/axis_signal_gen_v6/src/dds_compiler_0/dds_compiler_0.vho +++ /dev/null @@ -1,83 +0,0 @@ --- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:dds_compiler:6.0 --- IP Revision: 18 - --- The following code must appear in the VHDL architecture header. - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT dds_compiler_0 - PORT ( - aclk : IN STD_LOGIC; - s_axis_phase_tvalid : IN STD_LOGIC; - s_axis_phase_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0); - m_axis_data_tvalid : OUT STD_LOGIC; - m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) - ); -END COMPONENT; --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : dds_compiler_0 - PORT MAP ( - aclk => aclk, - s_axis_phase_tvalid => s_axis_phase_tvalid, - s_axis_phase_tdata => s_axis_phase_tdata, - m_axis_data_tvalid => m_axis_data_tvalid, - m_axis_data_tdata => m_axis_data_tdata - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file dds_compiler_0.vhd when simulating --- the core, dds_compiler_0. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/qick/firmware/ip/axis_signal_gen_v6/src/dds_compiler_0/dds_compiler_0.xci b/qick/firmware/ip/axis_signal_gen_v6/src/dds_compiler_0/dds_compiler_0.xci deleted file mode 100644 index 9516423..0000000 --- a/qick/firmware/ip/axis_signal_gen_v6/src/dds_compiler_0/dds_compiler_0.xci +++ /dev/null @@ -1,318 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - dds_compiler_0 - - - - 100000000 - 0 - 0 - 0.000 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 9 - 0 - 0 - 0 - 32 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 1 - 0 - 1 - 0 - 1 - 0 - 0 - 10 - 1 - 0 - 9 - 0 - 32 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 2 - 0 - 16 - 14 - 3 - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - 3 - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - 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- false - - - - - - event_s_config_tlast_unexpected - - out - - - std_logic - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - 0x0 - - - - - - false - - - - - - - - C_XDEVICEFAMILY - zynquplus - - - C_MODE_OF_OPERATION - 0 - - - C_MODULUS - 9 - - - C_ACCUMULATOR_WIDTH - 32 - - - C_CHANNELS - 1 - - - C_HAS_PHASE_OUT - 0 - - - C_HAS_PHASEGEN - 1 - - - C_HAS_SINCOS - 1 - - - C_LATENCY - 2 - - - C_MEM_TYPE - 1 - - - C_NEGATIVE_COSINE - 0 - - - C_NEGATIVE_SINE - 0 - - - C_NOISE_SHAPING - 1 - - - C_OUTPUTS_REQUIRED - 2 - - - C_OUTPUT_FORM - 0 - - - C_OUTPUT_WIDTH - 16 - - - C_PHASE_ANGLE_WIDTH - 14 - - - C_PHASE_INCREMENT - 3 - - - C_PHASE_INCREMENT_VALUE - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - - - C_RESYNC - 1 - - - C_PHASE_OFFSET - 3 - - - C_PHASE_OFFSET_VALUE - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - - - C_OPTIMISE_GOAL - 1 - - - C_USE_DSP48 - 1 - - - C_POR_MODE - 0 - - - C_AMPLITUDE - 0 - - - C_HAS_ACLKEN - 0 - - - C_HAS_ARESETN - 0 - - - C_HAS_TLAST - 0 - - - C_HAS_TREADY - 0 - - - C_HAS_S_PHASE - 1 - - - C_S_PHASE_TDATA_WIDTH - 72 - - - C_S_PHASE_HAS_TUSER - 0 - - - C_S_PHASE_TUSER_WIDTH - 1 - - - C_HAS_S_CONFIG - 0 - - - C_S_CONFIG_SYNC_MODE - 0 - - - C_S_CONFIG_TDATA_WIDTH - 1 - - - C_HAS_M_DATA - 1 - - - C_M_DATA_TDATA_WIDTH - 32 - - - C_M_DATA_HAS_TUSER - 0 - - - C_M_DATA_TUSER_WIDTH - 1 - - - C_HAS_M_PHASE - 0 - - - C_M_PHASE_TDATA_WIDTH - 1 - - - C_M_PHASE_HAS_TUSER - 0 - - - C_M_PHASE_TUSER_WIDTH - 1 - - - C_DEBUG_INTERFACE - 0 - - - C_CHAN_WIDTH - 1 - - - - - - choice_list_0be33969 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 16 - - - choice_list_230272f2 - None - Fixed - Programmable - Streaming - - - choice_list_45db86b7 - Auto - Configurable - - - choice_list_4721e082 - Minimal - Maximal - - - choice_list_950bd3bd - Auto - Area - Speed - - - choice_list_ba6ede68 - Standard - Rasterized - - - choice_list_cd7e1d82 - Coregen - Sysgen - - - choice_list_de3e80a0 - Fixed - Programmable - Streaming - - - choice_list_faa329ca - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 16 - 17 - 18 - 19 - 20 - 21 - - - choice_pairs_0079eeec - Twos_Complement - Sign_and_Magnitude - - - choice_pairs_27d1d409 - Auto - Distributed_ROM - Block_ROM - - - choice_pairs_65a5252d - Full_Range - Unit_Circle - - - choice_pairs_6bdc34ae - System_Parameters - Hardware_Parameters - - - choice_pairs_75713637 - Packet_Framing - Not_Required - - - choice_pairs_8b9a47c2 - Auto - None - Phase_Dithering - Taylor_Series_Corrected - - - choice_pairs_944fe41d - Phase_Generator_and_SIN_COS_LUT - Phase_Generator_only - SIN_COS_LUT_only - - - choice_pairs_a54f933f - Sine - Cosine - Sine_and_Cosine - - - choice_pairs_d463c5cb - User_Field - Not_Required - - - choice_pairs_dac1efef - Not_Required - - - choice_pairs_f611af79 - On_Vector - On_Packet - - - - - xilinx_veriloginstantiationtemplate_view_fileset - - dds_compiler_0.vho - vhdlTemplate - - - dds_compiler_0.veo - verilogTemplate - - - - xilinx_vhdlsynthesis_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset - - hdl/xbip_utils_v3_0_vh_rfs.vhd - vhdlSource - xbip_utils_v3_0_10 - - - - - - - - - - - xilinx_vhdlsynthesis_xilinx_com_ip_axi_utils_2_0__ref_view_fileset - - hdl/axi_utils_v2_0_vh_rfs.vhd - vhdlSource - axi_utils_v2_0_6 - - - - - - - - - - - xilinx_vhdlsynthesis_xilinx_com_ip_xbip_pipe_3_0__ref_view_fileset - - hdl/xbip_pipe_v3_0_vh_rfs.vhd - vhdlSource - xbip_pipe_v3_0_6 - - - - - - - - - - - xilinx_vhdlsynthesis_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset - - hdl/xbip_bram18k_v3_0_vh_rfs.vhd - vhdlSource - xbip_bram18k_v3_0_6 - - - - - - - - - - - xilinx_vhdlsynthesis_xilinx_com_ip_mult_gen_12_0__ref_view_fileset - - hdl/mult_gen_v12_0_vh_rfs.vhd - vhdlSource - mult_gen_v12_0_15 - - - - - - - - - - - xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_wrapper_3_0__ref_view_fileset - - hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd - vhdlSource - xbip_dsp48_wrapper_v3_0_4 - - - - - - - - - - - xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_addsub_3_0__ref_view_fileset - - hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd - vhdlSource - xbip_dsp48_addsub_v3_0_6 - - - - - - - - - - - xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_multadd_3_0__ref_view_fileset - - hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd - vhdlSource - xbip_dsp48_multadd_v3_0_6 - - - - - - - - - - - xilinx_vhdlsynthesis_view_fileset - - hdl/dds_compiler_v6_0_vh_rfs.vhd - vhdlSource - dds_compiler_v6_0_18 - - - - xilinx_vhdlsynthesiswrapper_view_fileset - - synth/dds_compiler_0.vhd - vhdlSource - xil_defaultlib - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset - - hdl/xbip_utils_v3_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - xbip_utils_v3_0_10 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_utils_2_0__ref_view_fileset - - hdl/axi_utils_v2_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - axi_utils_v2_0_6 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_pipe_3_0__ref_view_fileset - - hdl/xbip_pipe_v3_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - xbip_pipe_v3_0_6 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset - - hdl/xbip_bram18k_v3_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - xbip_bram18k_v3_0_6 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_mult_gen_12_0__ref_view_fileset - - hdl/mult_gen_v12_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - mult_gen_v12_0_15 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_wrapper_3_0__ref_view_fileset - - hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - xbip_dsp48_wrapper_v3_0_4 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_addsub_3_0__ref_view_fileset - - hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - xbip_dsp48_addsub_v3_0_6 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_multadd_3_0__ref_view_fileset - - hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - xbip_dsp48_multadd_v3_0_6 - - - - - - - - - - - xilinx_vhdlbehavioralsimulation_view_fileset - - hdl/dds_compiler_v6_0_vh_rfs.vhd - vhdlSource - USED_IN_ipstatic - dds_compiler_v6_0_18 - - - - xilinx_vhdlsimulationwrapper_view_fileset - - sim/dds_compiler_0.vhd - vhdlSource - xil_defaultlib - - - - xilinx_cmodelsimulation_view_fileset - - cmodel/dds_compiler_v6_0_bitacc_cmodel_lin64.zip - zip - - - cmodel/dds_compiler_v6_0_bitacc_cmodel_nt64.zip - zip - - - - xilinx_vhdltestbench_view_fileset - - demo_tb/tb_dds_compiler_0.vhd - vhdlSource - - - - xilinx_versioninformation_view_fileset - - doc/dds_compiler_v6_0_changelog.txt - text - - - - The Xilinx DDS Compiler LogiCORE provides Direct Digital Synthesizers (DDS) and optionally either Phase Generator or Sine/Cosine Lookup Table constituent parts as independent cores. The core features sine, cosine or quadrature outputs with 3 to 26-bit output sample precision. The core supports up to 16 channels by time-sharing the sine/cosine table which dramatically reduces the area requirement when multiple channels are needed. Phase Dithering and Taylor Series Correction options provide high dynamic range signals using minimal FPGA resources. In addition, the core has an optional phase offset capability, providing support for multiple synthesizers with precisely controlled phase differences. - - - Component_Name - Component Name - dds_compiler_0 - - - PartsPresent - Configuration Options - Phase_Generator_and_SIN_COS_LUT - - - DDS_Clock_Rate - System Clock - 256 - - - Channels - Number of Channels - 1 - - - Mode_of_Operation - Mode Of Operation - Standard - - - Modulus - Modulus - 9 - - - Parameter_Entry - Parameter Selection - System_Parameters - - - Spurious_Free_Dynamic_Range - Spurious Free Dynamic Range - 96 - - - Frequency_Resolution - Frequency Resolution - 0.06 - - - Noise_Shaping - Noise Shaping - Auto - - - Phase_Width - Phase Width - 32 - - - Output_Width - Output Width - 16 - - - Phase_Increment - Phase Increment - Streaming - - - Resync - Resync - true - - - Phase_offset - Phase Offset - Streaming - - - Output_Selection - Output Selection - Sine_and_Cosine - - - Negative_Sine - Negative Sine - false - - - Negative_Cosine - Negative Cosine - false - - - Amplitude_Mode - Amplitude Mode - Full_Range - - - Memory_Type - Memory Type - Auto - - - Optimization_Goal - Optimization Goal - Speed - - - DSP48_Use - DSP48 Use - Maximal - - - Has_Phase_Out - Has Phase Out - false - - - DATA_Has_TLAST - DATA Has TLAST - Not_Required - - - Has_TREADY - Output TREADY - false - - - S_PHASE_Has_TUSER - Input - Not_Required - - - S_PHASE_TUSER_Width - User Field Width - 1 - - - M_DATA_Has_TUSER - DATA Output - Not_Required - - - M_PHASE_Has_TUSER - PHASE Output - Not_Required - - - S_CONFIG_Sync_Mode - Synchronization Mode - On_Vector - - - OUTPUT_FORM - Output Form - Twos_Complement - - - Latency_Configuration - Configurable - - - Latency - 2 - - - Has_ARESETn - ARESETn (active low) - false - - - Has_ACLKEN - ACLKEN - false - - - Output_Frequency1 - 0 - - - PINC1 - 0 - - - Phase_Offset_Angles1 - 0 - - - POFF1 - 0 - - - Output_Frequency2 - 0 - - - PINC2 - 0 - - - Phase_Offset_Angles2 - 0 - - - POFF2 - 0 - - - Output_Frequency3 - 0 - - - PINC3 - 0 - - - Phase_Offset_Angles3 - 0 - - - POFF3 - 0 - - - Output_Frequency4 - 0 - - - PINC4 - 0 - - - Phase_Offset_Angles4 - 0 - - - POFF4 - 0 - - - Output_Frequency5 - 0 - - - PINC5 - 0 - - - Phase_Offset_Angles5 - 0 - - - POFF5 - 0 - - - Output_Frequency6 - 0 - - - PINC6 - 0 - - - Phase_Offset_Angles6 - 0 - - - POFF6 - 0 - - - Output_Frequency7 - 0 - - - PINC7 - 0 - - - Phase_Offset_Angles7 - 0 - - - POFF7 - 0 - - - Output_Frequency8 - 0 - - - PINC8 - 0 - - - Phase_Offset_Angles8 - 0 - - - POFF8 - 0 - - - Output_Frequency9 - 0 - - - PINC9 - 0 - - - Phase_Offset_Angles9 - 0 - - - POFF9 - 0 - - - Output_Frequency10 - 0 - - - PINC10 - 0 - - - Phase_Offset_Angles10 - 0 - - - POFF10 - 0 - - - Output_Frequency11 - 0 - - - PINC11 - 0 - - - Phase_Offset_Angles11 - 0 - - - POFF11 - 0 - - - Output_Frequency12 - 0 - - - PINC12 - 0 - - - Phase_Offset_Angles12 - 0 - - - POFF12 - 0 - - - Output_Frequency13 - 0 - - - PINC13 - 0 - - - Phase_Offset_Angles13 - 0 - - - POFF13 - 0 - - - Output_Frequency14 - 0 - - - PINC14 - 0 - - - Phase_Offset_Angles14 - 0 - - - POFF14 - 0 - - - Output_Frequency15 - 0 - - - PINC15 - 0 - - - Phase_Offset_Angles15 - 0 - - - POFF15 - 0 - - - Output_Frequency16 - 0 - - - PINC16 - 0 - - - Phase_Offset_Angles16 - 0 - - - POFF16 - 0 - - - POR_mode - POR Mode - false - - - GUI_Behaviour - Coregen - - - explicit_period - false - - - period - 1 - - - - - DDS Compiler - 18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2019.1 - - - - - - - - diff --git a/qick/firmware/ip/axis_signal_gen_v6/src/fifo/bin2gray.vhd b/qick/firmware/ip/axis_signal_gen_v6/src/fifo/bin2gray.vhd deleted file mode 100644 index 4ecc09b..0000000 --- a/qick/firmware/ip/axis_signal_gen_v6/src/fifo/bin2gray.vhd +++ /dev/null @@ -1,37 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity bin2gray is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end bin2gray; - -architecture rtl of bin2gray is - -signal gray : std_logic_vector (B-1 downto 0); - -begin - --- MSB always match. -gray(B-1) <= din(B-1); - -GEN: for I in 0 to B-2 generate -begin - gray(I) <= din(I+1) xor din(I); -end generate; - --- Assign output. -dout <= gray; - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v6/src/fifo/bram_dp.vhd b/qick/firmware/ip/axis_signal_gen_v6/src/fifo/bram_dp.vhd deleted file mode 100644 index d57aad1..0000000 --- a/qick/firmware/ip/axis_signal_gen_v6/src/fifo/bram_dp.vhd +++ /dev/null @@ -1,63 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity bram_dp is - Generic ( - -- Memory address size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - ena : in STD_LOGIC; - enb : in STD_LOGIC; - wea : in STD_LOGIC; - web : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR (N-1 downto 0); - addrb : in STD_LOGIC_VECTOR (N-1 downto 0); - dia : in STD_LOGIC_VECTOR (B-1 downto 0); - dib : in STD_LOGIC_VECTOR (B-1 downto 0); - doa : out STD_LOGIC_VECTOR (B-1 downto 0); - dob : out STD_LOGIC_VECTOR (B-1 downto 0) - ); -end bram_dp; - -architecture rtl of bram_dp is - --- Ram type. -type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); -shared variable RAM : ram_type; - -begin - --- CLKA port. -process (clka) -begin - if (clka'event and clka = '1') then - if (ena = '1') then - doa <= RAM(conv_integer(addra)); - if (wea = '1') then - RAM(conv_integer(addra)) := dia; - end if; - end if; - end if; -end process; - --- CLKB port. -process (clkb) -begin - if (clkb'event and clkb = '1') then - if (enb = '1') then - dob <= RAM(conv_integer(addrb)); - if (web = '1') then - RAM(conv_integer(addrb)) := dib; - end if; - end if; - end if; -end process; - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v6/src/fifo/bram_simple_dp.vhd b/qick/firmware/ip/axis_signal_gen_v6/src/fifo/bram_simple_dp.vhd deleted file mode 100644 index 1494332..0000000 --- a/qick/firmware/ip/axis_signal_gen_v6/src/fifo/bram_simple_dp.vhd +++ /dev/null @@ -1,53 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity bram_simple_dp is - Generic ( - -- Memory address size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port ( - clk : in STD_LOGIC; - ena : in STD_LOGIC; - enb : in STD_LOGIC; - wea : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR (N-1 downto 0); - addrb : in STD_LOGIC_VECTOR (N-1 downto 0); - dia : in STD_LOGIC_VECTOR (B-1 downto 0); - dob : out STD_LOGIC_VECTOR (B-1 downto 0) - ); -end bram_simple_dp; - -architecture rtl of bram_simple_dp is - --- Ram type. -type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); -shared variable RAM : ram_type; - -begin - -process (clk) -begin - if (clk'event and clk = '1') then - if (ena = '1') then - if (wea = '1') then - RAM(conv_integer(addra)) := dia; - end if; - end if; - end if; -end process; - -process (clk) -begin - if (clk'event and clk = '1') then - if (enb = '1') then - dob <= RAM(conv_integer(addrb)); - end if; - end if; -end process; - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v6/src/fifo/fifo.vhd b/qick/firmware/ip/axis_signal_gen_v6/src/fifo/fifo.vhd deleted file mode 100644 index 957362b..0000000 --- a/qick/firmware/ip/axis_signal_gen_v6/src/fifo/fifo.vhd +++ /dev/null @@ -1,135 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo; - -architecture rtl of fifo is - --- Number of bits of depth. -constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); - --- Dual port, single clock BRAM. -component bram_simple_dp is - Generic ( - -- Memory address size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port ( - clk : in STD_LOGIC; - ena : in STD_LOGIC; - enb : in STD_LOGIC; - wea : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR (N-1 downto 0); - addrb : in STD_LOGIC_VECTOR (N-1 downto 0); - dia : in STD_LOGIC_VECTOR (B-1 downto 0); - dob : out STD_LOGIC_VECTOR (B-1 downto 0) - ); -end component; - --- Pointers. -signal wptr : unsigned (N_LOG2-1 downto 0); -signal rptr : unsigned (N_LOG2-1 downto 0); - --- Memory signals. -signal mem_wea : std_logic; -signal mem_dob : std_logic_vector (B-1 downto 0); - --- Flags. -signal full_i : std_logic; -signal empty_i : std_logic; - -begin - --- FIFO memory. -mem_i : bram_simple_dp - Generic map ( - -- Memory address size. - N => N_LOG2, - -- Data width. - B => B - ) - Port map ( - clk => clk , - ena => '1' , - enb => rd_en , - wea => mem_wea , - addra => std_logic_vector(wptr) , - addrb => std_logic_vector(rptr) , - dia => din , - dob => mem_dob - ); - --- Memory connections. -mem_wea <= wr_en when full_i = '0' else - '0'; - --- Full/empty signals. -full_i <= '1' when wptr = rptr - 1 else - '0'; -empty_i <= '1' when wptr = rptr else - '0'; - --- wr_clk registers. -process (clk) -begin - if ( rising_edge(clk) ) then - if ( rstn = '0' ) then - wptr <= (others => '0'); - rptr <= (others => '0'); - else - -- Write. - if ( wr_en = '1' and full_i = '0' ) then - -- Write data. - - -- Increment pointer. - wptr <= wptr + 1; - end if; - - -- Read. - if ( rd_en = '1' and empty_i = '0' ) then - -- Read data. - - -- Increment pointer. - rptr <= rptr + 1; - end if; - end if; - end if; -end process; - --- Assign outputs. -dout <= mem_dob; -full <= full_i; -empty <= empty_i; - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v6/src/fifo/fifo_axi.vhd b/qick/firmware/ip/axis_signal_gen_v6/src/fifo/fifo_axi.vhd deleted file mode 100644 index e1f76f7..0000000 --- a/qick/firmware/ip/axis_signal_gen_v6/src/fifo/fifo_axi.vhd +++ /dev/null @@ -1,147 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo_axi is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo_axi; - -architecture rtl of fifo_axi is - --- FIFO. -component fifo is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end component; - --- FIFO read to AXI adapter. -component rd2axi is - Generic - ( - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- FIFO Read I/F. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (B-1 downto 0); - fifo_empty : in std_logic; - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - empty : out std_logic - ); -end component; - -signal rd_en_i : std_logic; -signal dout_i : std_logic_vector (B-1 downto 0); -signal empty_i : std_logic; - -begin - --- FIFO. -fifo_i : fifo - Generic map - ( - -- Data width. - B => B, - - -- Fifo depth. - N => N - ) - Port map - ( - rstn => rstn , - clk => clk , - - -- Write I/F. - wr_en => wr_en , - din => din , - - -- Read I/F. - rd_en => rd_en_i , - dout => dout_i , - - -- Flags. - full => full , - empty => empty_i - ); - --- FIFO read to AXI adapter. -rd2axi_i : rd2axi - Generic map - ( - -- Data width. - B => B - ) - Port map - ( - rstn => rstn , - clk => clk , - - -- FIFO Read I/F. - fifo_rd_en => rd_en_i , - fifo_dout => dout_i , - fifo_empty => empty_i , - - -- Read I/F. - rd_en => rd_en , - dout => dout , - empty => empty - ); - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v6/src/fifo/fifo_dc.vhd b/qick/firmware/ip/axis_signal_gen_v6/src/fifo/fifo_dc.vhd deleted file mode 100644 index c214fae..0000000 --- a/qick/firmware/ip/axis_signal_gen_v6/src/fifo/fifo_dc.vhd +++ /dev/null @@ -1,291 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo_dc is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - wr_rstn : in std_logic; - wr_clk : in std_logic; - - rd_rstn : in std_logic; - rd_clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo_dc; - -architecture rtl of fifo_dc is - --- Number of bits of depth. -constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); - --- Binary to gray converter. -component bin2gray is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end component; - --- Gray to binary converter. -component gray2bin is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end component; - --- Vector synchronizer (only for gray coded). -component synchronizer_vect is - generic ( - -- Sync stages. - N : Integer := 2; - - -- Data width. - B : Integer := 8 - ); - port ( - rstn : in std_logic; - clk : in std_logic; - data_in : in std_logic_vector (B-1 downto 0); - data_out : out std_logic_vector (B-1 downto 0) - ); -end component; - --- Dual port BRAM. -component bram_dp is - Generic ( - -- Memory address size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - ena : in STD_LOGIC; - enb : in STD_LOGIC; - wea : in STD_LOGIC; - web : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR (N-1 downto 0); - addrb : in STD_LOGIC_VECTOR (N-1 downto 0); - dia : in STD_LOGIC_VECTOR (B-1 downto 0); - dib : in STD_LOGIC_VECTOR (B-1 downto 0); - doa : out STD_LOGIC_VECTOR (B-1 downto 0); - dob : out STD_LOGIC_VECTOR (B-1 downto 0) - ); -end component; - --- Pointers. -signal wptr : unsigned (N_LOG2-1 downto 0); -signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); -signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); -signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); -signal rptr : unsigned (N_LOG2-1 downto 0); -signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); -signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); -signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); - --- Memory signals. -signal mem_wea : std_logic; -signal mem_dib : std_logic_vector (B-1 downto 0); -signal mem_doa : std_logic_vector (B-1 downto 0); -signal mem_dob : std_logic_vector (B-1 downto 0); - --- Flags. -signal full_i : std_logic; -signal empty_i : std_logic; - -begin - --- wptr_i: binary to gray. -wptr_i : bin2gray - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => std_logic_vector(wptr), - dout => wptr_g - ); - --- wptr_g: write to read domain. -wptr_g_i : synchronizer_vect - generic map ( - -- Sync stages. - N => 2, - - -- Data width. - B => N_LOG2 - ) - port map ( - rstn => rd_rstn, - clk => rd_clk, - data_in => wptr_g, - data_out => wptr_gc - ); - --- wptr_gc_i -wptr_gc_i : gray2bin - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => wptr_gc, - dout => wptr_c - ); - --- rptr_i: binary to gray. -rptr_i : bin2gray - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => std_logic_vector(rptr), - dout => rptr_g - ); - --- rptr_g: read to write domain. -rptr_g_i : synchronizer_vect - generic map ( - -- Sync stages. - N => 2, - - -- Data width. - B => N_LOG2 - ) - port map ( - rstn => wr_rstn, - clk => wr_clk, - data_in => rptr_g, - data_out => rptr_gc - ); - --- rptr_gc_i -rptr_gc_i : gray2bin - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => rptr_gc, - dout => rptr_c - ); - --- FIFO memory. -mem_i : bram_dp - Generic map ( - -- Memory address size. - N => N_LOG2, - -- Data width. - B => B - ) - Port map ( - clka => wr_clk, - clkb => rd_clk, - ena => '1', - enb => rd_en, - wea => mem_wea, - web => '0', - addra => std_logic_vector(wptr), - addrb => std_logic_vector(rptr), - dia => din, - dib => mem_dib, - doa => mem_doa, - dob => mem_dob - ); --- Memory connections. -mem_wea <= wr_en when full_i = '0' else - '0'; -mem_dib <= (others => '0'); - --- Full/empty signals. -full_i <= '1' when wptr = unsigned(rptr_c) - 1 else - '0'; -empty_i <= '1' when unsigned(wptr_c) = rptr else - '0'; - --- wr_clk registers. -process (wr_clk) -begin - if ( rising_edge(wr_clk) ) then - if ( wr_rstn = '0' ) then - wptr <= (others => '0'); - else - -- Write. - if ( wr_en = '1' and full_i = '0' ) then - -- Write data. - - -- Increment pointer. - wptr <= wptr + 1; - end if; - end if; - end if; -end process; - --- rd_clk registers. -process (rd_clk) -begin - if ( rising_edge(rd_clk) ) then - if ( rd_rstn = '0' ) then - rptr <= (others => '0'); - else - -- Read. - if ( rd_en = '1' and empty_i = '0' ) then - -- Read data. - - -- Increment pointer. - rptr <= rptr + 1; - end if; - end if; - end if; -end process; - --- Assign outputs. -dout <= mem_dob; -full <= full_i; -empty <= empty_i; - -end rtl; diff --git a/qick/firmware/ip/axis_signal_gen_v6/src/fifo/fifo_dc_axi.vhd b/qick/firmware/ip/axis_signal_gen_v6/src/fifo/fifo_dc_axi.vhd deleted file mode 100644 index eb83d1a..0000000 --- a/qick/firmware/ip/axis_signal_gen_v6/src/fifo/fifo_dc_axi.vhd +++ /dev/null @@ -1,156 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo_dc_axi is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - wr_rstn : in std_logic; - wr_clk : in std_logic; - - rd_rstn : in std_logic; - rd_clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo_dc_axi; - -architecture rtl of fifo_dc_axi is - --- Dual-clock FIFO. -component fifo_dc is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - wr_rstn : in std_logic; - wr_clk : in std_logic; - - rd_rstn : in std_logic; - rd_clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end component; - --- FIFO read to AXI adapter. -component rd2axi is - Generic - ( - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- FIFO Read I/F. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (B-1 downto 0); - fifo_empty : in std_logic; - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - empty : out std_logic - ); -end component; - -signal rd_en_i : std_logic; -signal dout_i : std_logic_vector (B-1 downto 0); -signal empty_i : std_logic; - -begin - --- Dual-clock FIFO. -fifo_i : fifo_dc - Generic map - ( - -- Data width. - B => B, - - -- Fifo depth. - N => N - ) - Port map - ( - wr_rstn => wr_rstn , - wr_clk => wr_clk , - - rd_rstn => rd_rstn , - rd_clk => rd_clk , - - -- Write I/F. - wr_en => wr_en , - din => din , - - -- Read I/F. - rd_en => rd_en_i , - dout => dout_i , - - -- Flags. - full => full , - empty => empty_i - ); - --- FIFO read to AXI adapter. -rd2axi_i : rd2axi - Generic map - ( - -- Data width. - B => B - ) - Port map - ( - rstn => rd_rstn , - clk => rd_clk , - - -- FIFO Read I/F. - fifo_rd_en => rd_en_i , - fifo_dout => dout_i , - fifo_empty => empty_i , - - -- Read I/F. - rd_en => rd_en , - dout => dout , - empty => empty - ); - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v6/src/fifo/gray2bin.vhd b/qick/firmware/ip/axis_signal_gen_v6/src/fifo/gray2bin.vhd deleted file mode 100644 index e23f8af..0000000 --- a/qick/firmware/ip/axis_signal_gen_v6/src/fifo/gray2bin.vhd +++ /dev/null @@ -1,37 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity gray2bin is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end gray2bin; - -architecture rtl of gray2bin is - -signal bin : std_logic_vector (B-1 downto 0); - -begin - --- MSB always match. -bin(B-1) <= din(B-1); - -GEN: for I in 0 to B-2 generate -begin - bin(I) <= bin(I+1) xor din(I); -end generate GEN; - --- Assign output. -dout <= bin; - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v6/src/fifo/rd2axi.vhd b/qick/firmware/ip/axis_signal_gen_v6/src/fifo/rd2axi.vhd deleted file mode 100644 index babadc6..0000000 --- a/qick/firmware/ip/axis_signal_gen_v6/src/fifo/rd2axi.vhd +++ /dev/null @@ -1,138 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity rd2axi is - Generic - ( - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- FIFO Read I/F. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (B-1 downto 0); - fifo_empty : in std_logic; - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - empty : out std_logic - ); -end rd2axi; - -architecture rtl of rd2axi is - -type fsm_state is ( WAIT_EMPTY_ST, - READ_FIRST_ST, - READ_ST, - READ_LAST_ST); -signal current_state, next_state : fsm_state; - -signal wait_empty_state : std_logic; -signal read_first_state : std_logic; -signal read_state : std_logic; - -signal fifo_rd_en_i : std_logic; -signal empty_i : std_logic; - -begin - -process(clk) -begin - if (rising_edge(clk)) then - if (rstn = '0') then - current_state <= WAIT_EMPTY_ST; - else - current_state <= next_state; - end if; - end if; -end process; - --- Next state logic. -process(current_state, fifo_empty, rd_en) -begin - case current_state is - when WAIT_EMPTY_ST => - if (fifo_empty = '1') then - next_state <= WAIT_EMPTY_ST; - else - next_state <= READ_FIRST_ST; - end if; - - when READ_FIRST_ST => - next_state <= READ_ST; - - when READ_ST => - if (fifo_empty = '0') then - next_state <= READ_ST; - else - if (rd_en = '1') then - next_state <= WAIT_EMPTY_ST; - else - next_state <= READ_LAST_ST; - end if; - end if; - - when READ_LAST_ST => - if (rd_en = '0') then - next_state <= READ_LAST_ST; - else - next_state <= WAIT_EMPTY_ST; - end if; - - end case; -end process; - --- Output logic. -process(current_state) -begin -wait_empty_state <= '0'; -read_first_state <= '0'; -read_state <= '0'; -empty_i <= '0'; - case current_state is - when WAIT_EMPTY_ST => - wait_empty_state <= '1'; - read_first_state <= '0'; - read_state <= '0'; - empty_i <= '1'; - - when READ_FIRST_ST => - wait_empty_state <= '0'; - read_first_state <= '1'; - read_state <= '0'; - empty_i <= '1'; - - when READ_ST => - wait_empty_state <= '0'; - read_first_state <= '0'; - read_state <= '1'; - empty_i <= '0'; - - when READ_LAST_ST => - wait_empty_state <= '0'; - read_first_state <= '0'; - read_state <= '0'; - empty_i <= '0'; - - end case; -end process; - --- FIFO Read enable signal. -fifo_rd_en_i <= read_first_state or (read_state and rd_en); - --- Assign outputs. -fifo_rd_en <= fifo_rd_en_i; --- TODO: add register to freeze last value. -dout <= fifo_dout when empty_i = '0' else - (others => '0'); -empty <= empty_i; - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v6/src/fifo/synchronizer_vect.vhd b/qick/firmware/ip/axis_signal_gen_v6/src/fifo/synchronizer_vect.vhd deleted file mode 100644 index 2fbb696..0000000 --- a/qick/firmware/ip/axis_signal_gen_v6/src/fifo/synchronizer_vect.vhd +++ /dev/null @@ -1,49 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - --- This block is intended to use to sync gray coded vectors. - --- NOTE: Do not use with generic vector data, as it may result --- in corrupted re-sync data. - -entity synchronizer_vect is - generic ( - -- Sync stages. - N : Integer := 2; - - -- Data width. - B : Integer := 8 - ); - port ( - rstn : in std_logic; - clk : in std_logic; - data_in : in std_logic_vector (B-1 downto 0); - data_out : out std_logic_vector (B-1 downto 0) - ); -end synchronizer_vect; - -architecture rtl of synchronizer_vect is - --- Internal register. -type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); -signal data_int_reg : reg_t; - -begin - -process(clk) -begin - if (rising_edge(clk)) then - if (rstn = '0') then - data_int_reg <= (others => (others => '0')); -- 1 FF. - else - data_int_reg <= data_int_reg(N-2 downto 0) & data_in; - end if; - end if; -end process; - --- Assign output. -data_out <= data_int_reg(N-1); - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v6/src/latency_reg.v b/qick/firmware/ip/axis_signal_gen_v6/src/latency_reg.v deleted file mode 100644 index 687a9f3..0000000 --- a/qick/firmware/ip/axis_signal_gen_v6/src/latency_reg.v +++ /dev/null @@ -1,61 +0,0 @@ -module latency_reg - ( - rstn , - clk , - - din , - dout - ); - -// Parameters. -parameter N = 2; // Latency. -parameter B = 8; // Data width. - -// Ports. -input rstn; -input clk; -input [B-1:0] din; -output [B-1:0] dout; - -// Shift register. -reg [B-1:0] shift_r [0:N-1]; - -generate -genvar i; - for (i=1; i '0'); - else - data_int_reg <= data_int_reg(N-2 downto 0) & data_in; - end if; - end if; -end process; - --- Assign output. -data_out <= data_int_reg(N-1); - -end rtl; - diff --git a/qick/firmware/ip/axis_signal_gen_v6/src/tb/gen_gauss.py b/qick/firmware/ip/axis_signal_gen_v6/src/tb/gen_gauss.py deleted file mode 100644 index 88ba683..0000000 --- a/qick/firmware/ip/axis_signal_gen_v6/src/tb/gen_gauss.py +++ /dev/null @@ -1,18 +0,0 @@ -import numpy as np -import matplotlib.pyplot as plt - -def gauss(mu=0, si=0, length=100, maxv=30000): - x = np.arange(0,length) - y = 1/(2*np.pi*si**2)*np.exp(-(x-mu)**2/si**2) - y = y/np.max(y)*maxv - return y - -yq = gauss(mu=300, si=120, length=512) -yi = np.zeros(len(yq)) - -yi = yi.astype(np.int16) -yq = yq.astype(np.int16) - -for ii in range(len(yi)): - print("%d,%d" %(yq[ii],yi[ii])) - diff --git a/qick/firmware/ip/axis_signal_gen_v6/src/tb/tb.sv b/qick/firmware/ip/axis_signal_gen_v6/src/tb/tb.sv deleted file mode 100644 index 23c4c78..0000000 --- a/qick/firmware/ip/axis_signal_gen_v6/src/tb/tb.sv +++ /dev/null @@ -1,481 +0,0 @@ -// VIP: axi_mst_0 -// DUT: axis_signal_gen_v2 -// IF: s_axi -> axi_mst_0 - -import axi_vip_pkg::*; -import axi_mst_0_pkg::*; - -module tb(); - -// DUT generics. -parameter N = 10; -parameter N_DDS = 4; - -// s_axi interfase. -reg s_axi_aclk; -reg s_axi_aresetn; -wire [5:0] s_axi_araddr; -wire [2:0] s_axi_arprot; -wire s_axi_arready; -wire s_axi_arvalid; -wire [5:0] s_axi_awaddr; -wire [2:0] s_axi_awprot; -wire s_axi_awready; -wire s_axi_awvalid; -wire s_axi_bready; -wire [1:0] s_axi_bresp; -wire s_axi_bvalid; -wire [31:0] s_axi_rdata; -wire s_axi_rready; -wire [1:0] s_axi_rresp; -wire s_axi_rvalid; -wire [31:0] s_axi_wdata; -wire s_axi_wready; -wire [3:0] s_axi_wstrb; -wire s_axi_wvalid; - -// s0_axis interfase. -reg s0_axis_aclk; -reg s0_axis_aresetn; -reg [31:0] s0_axis_tdata; -wire s0_axis_tready; -reg s0_axis_tvalid; - -reg aresetn; -reg aclk; - -// Dummy clock for debugging. -reg aclk4; - -// s1_axis interfase. -reg [159:0] s1_axis_tdata; -wire s1_axis_tready; -reg s1_axis_tvalid; - -// m_axis interfase. -wire [N_DDS*16-1:0] m_axis_tdata; -reg m_axis_tready = 1; -wire m_axis_tvalid; - -// Waveform Fields. -reg [31:0] freq_r; -reg [31:0] phase_r; -reg [15:0] addr_r; -reg [15:0] gain_r; -reg [15:0] nsamp_r; -reg [1:0] outsel_r; -reg mode_r; -reg stdysel_r; -reg phrst_r; - -// Assignment of data out for debugging. -wire [15:0] dout_ii [0:N_DDS-1]; -reg [15:0] dout_f; - -// AXI VIP master address. -xil_axi_ulong addr_start_addr = 32'h40000000; // 0 -xil_axi_ulong addr_we = 32'h40000004; // 1 - -xil_axi_prot_t prot = 0; -reg[31:0] data_wr = 32'h12345678; -reg[31:0] data; -xil_axi_resp_t resp; - -// Test bench control. -reg tb_load_mem = 0; -reg tb_load_mem_done = 0; -reg tb_load_wave = 0; -reg tb_load_wave_done = 0; -reg tb_write_out = 0; - -// Debug. -generate -genvar ii; -for (ii = 0; ii < N_DDS; ii = ii + 1) begin : GEN_debug - assign dout_ii[ii] = m_axis_tdata[16*ii +: 16]; -end -endgenerate -axi_mst_0 axi_mst_0_i - ( - .aclk (s_axi_aclk ), - .aresetn (s_axi_aresetn ), - .m_axi_araddr (s_axi_araddr ), - .m_axi_arprot (s_axi_arprot ), - .m_axi_arready (s_axi_arready ), - .m_axi_arvalid (s_axi_arvalid ), - .m_axi_awaddr (s_axi_awaddr ), - .m_axi_awprot (s_axi_awprot ), - .m_axi_awready (s_axi_awready ), - .m_axi_awvalid (s_axi_awvalid ), - .m_axi_bready (s_axi_bready ), - .m_axi_bresp (s_axi_bresp ), - .m_axi_bvalid (s_axi_bvalid ), - .m_axi_rdata (s_axi_rdata ), - .m_axi_rready (s_axi_rready ), - .m_axi_rresp (s_axi_rresp ), - .m_axi_rvalid (s_axi_rvalid ), - .m_axi_wdata (s_axi_wdata ), - .m_axi_wready (s_axi_wready ), - .m_axi_wstrb (s_axi_wstrb ), - .m_axi_wvalid (s_axi_wvalid ) - ); - -axis_signal_gen_v6 - # - ( - .N (N ), - .N_DDS (N_DDS ) - ) - DUT - ( - // AXI Slave I/F for configuration. - .s_axi_aclk (s_axi_aclk ), - .s_axi_aresetn (s_axi_aresetn ), - .s_axi_araddr (s_axi_araddr ), - .s_axi_arprot (s_axi_arprot ), - .s_axi_arready (s_axi_arready ), - .s_axi_arvalid (s_axi_arvalid ), - .s_axi_awaddr (s_axi_awaddr ), - .s_axi_awprot (s_axi_awprot ), - .s_axi_awready (s_axi_awready ), - .s_axi_awvalid (s_axi_awvalid ), - .s_axi_bready (s_axi_bready ), - .s_axi_bresp (s_axi_bresp ), - .s_axi_bvalid (s_axi_bvalid ), - .s_axi_rdata (s_axi_rdata ), - .s_axi_rready (s_axi_rready ), - .s_axi_rresp (s_axi_rresp ), - .s_axi_rvalid (s_axi_rvalid ), - .s_axi_wdata (s_axi_wdata ), - .s_axi_wready (s_axi_wready ), - .s_axi_wstrb (s_axi_wstrb ), - .s_axi_wvalid (s_axi_wvalid ), - - // AXIS Slave to load data into memory. - .s0_axis_aclk (s0_axis_aclk ), - .s0_axis_aresetn(s0_axis_aresetn), - .s0_axis_tdata (s0_axis_tdata ), - .s0_axis_tvalid (s0_axis_tvalid ), - .s0_axis_tready (s0_axis_tready ), - - // s1_* and m_* reset/clock. - .aresetn (aresetn ), - .aclk (aclk ), - - // AXIS Slave to queue waveforms. - .s1_axis_tdata (s1_axis_tdata ), - .s1_axis_tvalid (s1_axis_tvalid ), - .s1_axis_tready (s1_axis_tready ), - - // AXIS Master for output data. - .m_axis_tready (m_axis_tready ), - .m_axis_tvalid (m_axis_tvalid ), - .m_axis_tdata (m_axis_tdata ) - ); - -// VIP Agents -axi_mst_0_mst_t axi_mst_0_agent; - -assign s1_axis_tdata = {{10{1'b0}},phrst_r,stdysel_r,mode_r,outsel_r,nsamp_r,{16{1'b0}},gain_r,{16{1'b0}},addr_r,phase_r,freq_r}; - -initial begin - // Create agents. - axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); - - // Set tag for agents. - axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); - - // Start agents. - axi_mst_0_agent.start_master(); - - // Reset sequence. - s_axi_aresetn <= 0; - s0_axis_aresetn <= 0; - aresetn <= 0; - #500; - s_axi_aresetn <= 1; - s0_axis_aresetn <= 1; - aresetn <= 1; - - #1000; - - $display("############################"); - $display("### Load data into Table ###"); - $display("############################"); - $display("t = %0t", $time); - - /* - ADDR = 0 - */ - - // start_addr. - data_wr = 0; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(addr_start_addr, prot, data_wr, resp); - #10; - - // we. - data_wr = 1; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(addr_we, prot, data_wr, resp); - #10; - - // Load Table. - tb_load_mem <= 1; - wait (tb_load_mem_done); - - #100; - - // we. - data_wr = 0; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(addr_we, prot, data_wr, resp); - #10; - - #1000; - - $display("#######################"); - $display("### Queue Waveforms ###"); - $display("#######################"); - $display("t = %0t", $time); - - // Queue waveforms and write output while queuing. - tb_load_wave <= 1; - tb_write_out <= 1; - wait (tb_load_wave_done); - - #30000; - - // Stop writing output data. - tb_write_out <= 0; - - #20000; - -end - -// Load data into memroy. -initial begin - int fd,vali,valq; - bit signed [15:0] ii,qq; - - s0_axis_tvalid <= 0; - s0_axis_tdata <= 0; - - wait (tb_load_mem); - - fd = $fopen("../../../../../tb/gauss.txt","r"); - - wait (s0_axis_tready); - - while($fscanf(fd,"%d,%d", valq,vali) == 2) begin - $display("I,Q: %d, %d", vali,valq); - ii = vali; - qq = valq; - @(posedge s0_axis_aclk); - s0_axis_tvalid <= 1; - s0_axis_tdata <= {qq,ii}; - end - - @(posedge s0_axis_aclk); - s0_axis_tvalid <= 0; - - $fclose(fd); - tb_load_mem_done <= 1; - -end - -// Load waveforms. -initial begin - s1_axis_tvalid <= 0; - freq_r <= 0; - phase_r <= 0; - addr_r <= 0; - gain_r <= 0; - nsamp_r <= 0; - outsel_r <= 0; - mode_r <= 0; - stdysel_r <= 0; - phrst_r <= 0; - - wait (tb_load_wave); - wait (s1_axis_tready); - - @(posedge aclk); - $display("t = %0t", $time); - s1_axis_tvalid <= 1; - freq_r <= freq_calc(100, N_DDS, 4); // 120 MHz. - phase_r <= 0; - addr_r <= 22; - gain_r <= 12000; - nsamp_r <= 80; - outsel_r <= 1; // 0: prod, 1: dds, 2: mem - mode_r <= 0; // 0: nsamp, 1: periodic - stdysel_r <= 0; // 0: last, 1: zero. - phrst_r <= 0; - - @(posedge aclk); - $display("t = %0t", $time); - s1_axis_tvalid <= 1; - freq_r <= freq_calc(100, N_DDS, 4); // 120 MHz. - phase_r <= 0; - addr_r <= 22; - gain_r <= 12000; - nsamp_r <= 123; - outsel_r <= 1; // 0: prod, 1: dds, 2: mem - mode_r <= 0; // 0: nsamp, 1: periodic - stdysel_r <= 0; // 0: last, 1: zero. - phrst_r <= 1; - - @(posedge aclk); - s1_axis_tvalid <= 0; - - #5000; - - @(posedge aclk); - $display("t = %0t", $time); - s1_axis_tvalid <= 1; - freq_r <= freq_calc(100, N_DDS, 13); - phase_r <= 0; - addr_r <= 0; - gain_r <= 30000; - nsamp_r <= 400/N_DDS; - outsel_r <= 0; // 0: prod, 1: dds, 2: mem - mode_r <= 0; // 0: nsamp, 1: periodic - stdysel_r <= 1; // 0: last, 1: zero. - phrst_r <= 0; - - //@(posedge aclk); - //$display("t = %0t", $time); - //s1_axis_tvalid <= 1; - //freq_r <= freq_calc(100, N_DDS, 33); - //phase_r <= 0; - //addr_r <= 5; - //gain_r <= 30000; - //nsamp_r <= 670/N_DDS; - //outsel_r <= 1; // 0: prod, 1: dds, 2: mem - //mode_r <= 0; // 0: nsamp, 1: periodic - //stdysel_r <= 1; // 0: last, 1: zero. - - //@(posedge aclk); - //$display("t = %0t", $time); - //s1_axis_tvalid <= 1; - //freq_r <= freq_calc(100, N_DDS, 22); - //phase_r <= 7689; - //addr_r <= 0; - //gain_r <= 30000; - //nsamp_r <= 70/N_DDS; - //outsel_r <= 2; // 0: prod, 1: dds, 2: mem - //mode_r <= 1; // 0: nsamp, 1: periodic - //stdysel_r <= 1; // 0: last, 1: zero. - - //@(posedge aclk); - //s1_axis_tvalid <= 0; - - //#30000; - - //@(posedge aclk); - //$display("t = %0t", $time); - //s1_axis_tvalid <= 1; - //freq_r <= freq_calc(100, N_DDS, 3); - //phase_r <= 0; - //addr_r <= 5; - //gain_r <= 30000; - //nsamp_r <= 670/N_DDS; - //outsel_r <= 1; // 0: prod, 1: dds, 2: mem - //mode_r <= 0; // 0: nsamp, 1: periodic - //stdysel_r <= 1; // 0: last, 1: zero. - - @(posedge aclk); - s1_axis_tvalid <= 0; - tb_load_wave_done <= 1; -end - -// Write output into file. -initial begin - int fd; - int i; - shortint real_d; - - // Output file. - fd = $fopen("../../../../../tb/dout.csv","w"); - - // Data format. - $fdisplay(fd, "valid, idx, real"); - - wait (tb_write_out); - - while (tb_write_out) begin - @(posedge aclk); - for (i=0; i - - user.org - user - axis_terminator - 1.0 - - - s_axis - - - - - - - TDATA - - - s_axis_tdata - - - - - TSTRB - - - s_axis_tstrb - - - - - TLAST - - - s_axis_tlast - - - - - TVALID - - - s_axis_tvalid - - - - - TREADY - - - s_axis_tready - - - - - - s_axis_aresetn - - - - - - - RST - - - s_axis_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - s_axis_aclk - - - - - - - CLK - - - s_axis_aclk - - - - - - ASSOCIATED_BUSIF - s_axis - - - ASSOCIATED_RESET - s_axis_aresetn - - - - - - - - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis - VHDL - axis_terminator - - xilinx_anylanguagesynthesis_view_fileset - - - - viewChecksum - d2deb9f7 - - - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - VHDL - axis_terminator - - xilinx_anylanguagebehavioralsimulation_view_fileset - - - - viewChecksum - d2deb9f7 - - - - - xilinx_xpgui - UI Layout - :vivado.xilinx.com:xgui.ui - - xilinx_xpgui_view_fileset - - - - viewChecksum - 35ebc586 - - - - - - - s_axis_aclk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axis_aresetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axis_tready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axis_tdata - - in - - 15 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axis_tstrb - - in - - 1 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 1 - - - - - s_axis_tlast - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axis_tvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - - DATA_WIDTH - Data Width - 16 - - - - - - choice_list_74b5137e - ACTIVE_HIGH - ACTIVE_LOW - - - - - xilinx_anylanguagesynthesis_view_fileset - - src/axis_terminator.vhd - vhdlSource - CHECKSUM_d2deb9f7 - - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - src/axis_terminator.vhd - vhdlSource - - - - xilinx_xpgui_view_fileset - - xgui/axis_terminator_v1_0.tcl - tclSource - CHECKSUM_35ebc586 - XGUI_VERSION_2 - - - - AXIS Terminator block. - - - DATA_WIDTH - Data Width - 16 - - - Component_Name - axis_terminator_v1_0 - - - - - - virtex7 - qvirtex7 - kintex7 - kintex7l - qkintex7 - qkintex7l - artix7 - artix7l - aartix7 - qartix7 - zynq - qzynq - azynq - spartan7 - aspartan7 - virtexu - zynquplus - virtexuplus - virtexuplusHBM - kintexuplus - kintexu - - - /UserIP - - AXIS Terminator - package_project - 2 - 2019-08-16T18:41:23Z - - /home/lstefana/v18.3/ip/axis_terminator - /home/lstefana/v18.3/ip/axis_terminator - /home/lstefana/v18.3/ip/axis_terminator - /home/lstefana/v18.3/ip/axis_terminator - /home/lstefana/v18.3/ip/axis_terminator - /home/lstefana/v18.3/ip/axis_terminator - /home/lstefana/v18.3/ip/axis_terminator - - - - 2018.3 - - - - - - - - diff --git a/qick/firmware/ip/axis_terminator/src/axis_terminator.vhd b/qick/firmware/ip/axis_terminator/src/axis_terminator.vhd deleted file mode 100644 index 90824d6..0000000 --- a/qick/firmware/ip/axis_terminator/src/axis_terminator.vhd +++ /dev/null @@ -1,31 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity axis_terminator is - generic - ( - -- Data width. - DATA_WIDTH : Integer := 16 - ); - port - ( - -- AXIS Slave I/F. - s_axis_aclk : in std_logic; - s_axis_aresetn : in std_logic; - s_axis_tready : out std_logic; - s_axis_tdata : in std_logic_vector(DATA_WIDTH-1 downto 0); - s_axis_tstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); - s_axis_tlast : in std_logic; - s_axis_tvalid : in std_logic - ); -end axis_terminator; - -architecture rtl of axis_terminator is - -begin - -s_axis_tready <= '1'; - -end rtl; - diff --git a/qick/firmware/ip/axis_terminator/xgui/axis_terminator_v1_0.tcl b/qick/firmware/ip/axis_terminator/xgui/axis_terminator_v1_0.tcl deleted file mode 100644 index 55a2622..0000000 --- a/qick/firmware/ip/axis_terminator/xgui/axis_terminator_v1_0.tcl +++ /dev/null @@ -1,25 +0,0 @@ -# Definitional proc to organize widgets for parameters. -proc init_gui { IPINST } { - ipgui::add_param $IPINST -name "Component_Name" - #Adding Page - set Page_0 [ipgui::add_page $IPINST -name "Page 0"] - ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${Page_0} - - -} - -proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { - # Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { - # Procedure called to validate DATA_WIDTH - return true -} - - -proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH} -} - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/component.xml b/qick/firmware/ip/axis_tproc64x32_x8_v1/component.xml deleted file mode 100644 index 0a6501b..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/component.xml +++ /dev/null @@ -1,2338 +0,0 @@ - - - user.org - user - axis_tproc64x32_x8 - 1.0 - - - m0_axis - - - - - - - TDATA - - - m0_axis_tdata - - - - - TLAST - - - m0_axis_tlast - - - - - TVALID - - - m0_axis_tvalid - - - - - TREADY - - - m0_axis_tready - - - - - - m1_axis - - - - - - - TDATA - - - m1_axis_tdata - - - - - TVALID - - - m1_axis_tvalid - - - - - TREADY - - - m1_axis_tready - - - - - - m2_axis - - - - - - - TDATA - - - m2_axis_tdata - - - - - TVALID - - - m2_axis_tvalid - - - - - TREADY - - - m2_axis_tready - - - - - - m3_axis - - - - - - - TDATA - - - m3_axis_tdata - - - - - TVALID - - - m3_axis_tvalid - - - - - TREADY - - - m3_axis_tready - - - - - - m4_axis - - - - - - - TDATA - - - m4_axis_tdata - - - - - TVALID - - - m4_axis_tvalid - - - - - TREADY - - - m4_axis_tready - - - - - - m5_axis - - - - - - - TDATA - - - m5_axis_tdata - - - - - TVALID - - - m5_axis_tvalid - - - - - TREADY - - - m5_axis_tready - - - - - - m6_axis - - - - - - - TDATA - - - m6_axis_tdata - - - - - TVALID - - - m6_axis_tvalid - - - - - TREADY - - - m6_axis_tready - - - - - - m7_axis - - - - - - - TDATA - - - m7_axis_tdata - - - - - TVALID - - - m7_axis_tvalid - - - - - TREADY - - - m7_axis_tready - - - - - - m8_axis - - - - - - - TDATA - - - m8_axis_tdata - - - - - TVALID - - - m8_axis_tvalid - - - - - TREADY - - - m8_axis_tready - - - - - - s0_axis - - - - - - - TDATA - - - s0_axis_tdata - - - - - TLAST - - - s0_axis_tlast - - - - - TVALID - - - s0_axis_tvalid - - - - - TREADY - - - s0_axis_tready - - - - - - s1_axis - - - - - - - TDATA - - - s1_axis_tdata - - - - - TVALID - - - s1_axis_tvalid - - - - - TREADY - - - s1_axis_tready - - - - - - s2_axis - - - - - - - TDATA - - - s2_axis_tdata - - - - - TVALID - - - s2_axis_tvalid - - - - - TREADY - - - s2_axis_tready - - - - - - s3_axis - - - - - - - TDATA - - - s3_axis_tdata - - - - - TVALID - - - s3_axis_tvalid - - - - - TREADY - - - s3_axis_tready - - - - - - s4_axis - - - - - - - TDATA - - - s4_axis_tdata - - - - - TVALID - - - s4_axis_tvalid - - - - - TREADY - - - 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tclSource - CHECKSUM_9f9e4535 - XGUI_VERSION_2 - - - - AXIS tProcessor, 64-bit Instructions, 32-bit registers, 4 input channels, 8 output channels. - - - PMEM_N - Pmem N - 16 - - - DMEM_N - Dmem N - 10 - - - Component_Name - axis_tproc64x32_x8_v1_0 - - - - - - virtex7 - qvirtex7 - kintex7 - kintex7l - qkintex7 - qkintex7l - akintex7 - artix7 - artix7l - aartix7 - qartix7 - zynq - qzynq - azynq - spartan7 - aspartan7 - virtexu - zynquplus - virtexuplus - virtexuplusHBM - kintexuplus - kintexu - - - /UserIP - - AXIS tProcessor 64x32, 8 channels V1. - package_project - 3 - 2021-06-11T18:17:59Z - - /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 - /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 - /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 - /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 - /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 - /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 - /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 - /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 - /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 - /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 - /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 - /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 - /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 - /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 - /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 - /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 - /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 - /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 - /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 - /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 - /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 - /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 - /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 - - - - 2019.1 - - - - - - - - - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/alu/alu.v b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/alu/alu.v deleted file mode 100644 index 490dced..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/alu/alu.v +++ /dev/null @@ -1,140 +0,0 @@ -// ALU block integrating math and bitw. -// -// 0000 : din_a and din_b -// 0001 : din_a or din_b -// 0010 : din_a xor din_b -// 0011 : not(din_a) -// 0100 : din_a << din_b -// 0101 : din_a >> din_b -// 1000 : din_a + din_b -// 1001 : din_a - din_b -// 1010 : din_a * din_b - -module alu - ( - // Clock and reset. - clk , - rstn , - - // Input operands. - din_a , - din_b , - - // Operation. - op , - - // Zero detection. - zero_a , - zero_b , - - // Output. - dout - ); - -// Data width. -parameter B = 16; - -// Ports. -input clk; -input rstn; - -input [B-1:0] din_a; -input [B-1:0] din_b; - -input [3:0] op; - -output zero_a; -output zero_b; - -output [B-1:0] dout; - -// Registers to account latency. -reg [3:0] op_r; -reg [3:0] op_rr; -reg [3:0] op_rrr; - -// Operation. -wire [3:0] oper_i; -wire sel; - -// Outputs. -wire [B-1:0] math_dout; -wire [B-1:0] bitw_dout; - -// Math block. -math - #( - // Data width. - .B(B) - ) - math_i - ( - // Clock and reset. - .clk (clk ), - .rstn (rstn ), - - // Input operands. - .din_a (din_a ), - .din_b (din_b ), - - // Operation. - .op (oper_i ), - - // Zero detection. - .zero_a (zero_a ), - .zero_b (zero_b ), - - // Output. - .dout (math_dout ) - ); - -// Bitw block. -bitw - #( - // Data width. - .B(B) - ) - bitw_i - ( - // Clock and reset. - .clk (clk ), - .rstn (rstn ), - - // Input operands. - .din_a (din_a ), - .din_b (din_b ), - - // Operation. - .op (oper_i ), - - // Output. - .dout (bitw_dout ) - ); - -// Registers. -always @(posedge clk) begin - if (~rstn) begin - // Registers to account latency. - op_r <= 0; - op_rr <= 0; - op_rrr <= 0; - - end else - // Registers to account latency. - op_r <= op; - op_rr <= op_r; - op_rrr <= op_rr; - begin - - end -end - -// Operation. -assign oper_i = {1'b0,op[2:0]}; -assign sel = op_rrr[3]; - -// Output mux. -assign dout = (sel == 0)? bitw_dout : math_dout; - -endmodule - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/alu/bitw.vhd b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/alu/bitw.vhd deleted file mode 100644 index 2487155..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/alu/bitw.vhd +++ /dev/null @@ -1,135 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use ieee.math_real.all; - --- Bit-wise operations block. - --- It operates on two inputs. --- Operations are: --- 0000 : din_a and din_b --- 0001 : din_a or din_b --- 0010 : din_a xor din_b --- 0011 : not(din_b) --- 0100 : din_a << din_b --- 0101 : din_a >> din_b --- --- Latency is 3 clocks. - -entity bitw is - Generic ( - -- Data width. - B : Integer := 16 - ); - Port ( - -- Clock and reset. - clk : in std_logic; - rstn : in std_logic; - - -- Input operands. - din_a : in std_logic_vector (B-1 downto 0); - din_b : in std_logic_vector (B-1 downto 0); - - -- Operation. - op : in std_logic_vector (3 downto 0); - - -- Output. - dout : out std_logic_vector (B-1 downto 0) - ); -end bitw; - -architecture rtl of bitw is - --- Number of bits of B. -constant B_LOG2 : Integer := Integer(ceil(log2(real(B)))); - --- Input registers. -signal din_a_r : std_logic_vector (B-1 downto 0); -signal din_b_r : std_logic_vector (B-1 downto 0); -signal op_r : std_logic_vector (3 downto 0); - --- Operations. -signal and_i : std_logic_vector (B-1 downto 0); -signal or_i : std_logic_vector (B-1 downto 0); -signal xor_i : std_logic_vector (B-1 downto 0); -signal not_i : std_logic_vector (B-1 downto 0); - --- Shift. -type vect_t is array (B-1 downto 0) of std_logic_vector (B-1 downto 0); -signal ls_i : vect_t; -signal rs_i : vect_t; -signal ls_mux : std_logic_vector (B-1 downto 0); -signal rs_mux : std_logic_vector (B-1 downto 0); -signal shift_n : unsigned(B_LOG2-1 downto 0); - --- Output mux. -signal dout_mux : std_logic_vector (B-1 downto 0); -signal dout_r : std_logic_vector (B-1 downto 0); -signal dout_rr : std_logic_vector (B-1 downto 0); - -begin - --- Registers. -process (clk) -begin - if ( rising_edge(clk) ) then - if ( rstn = '0' ) then - -- Input registers. - din_a_r <= (others => '0'); - din_b_r <= (others => '0'); - op_r <= (others => '0'); - - -- Output mux. - dout_r <= (others => '0'); - dout_rr <= (others => '0'); - else - -- Input registers. - din_a_r <= din_a; - din_b_r <= din_b; - op_r <= op; - - -- Output mux. - dout_r <= dout_mux; - dout_rr <= dout_r; - end if; - end if; -end process; - --- Operations. -and_i <= din_a_r and din_b_r; -or_i <= din_a_r or din_b_r; -xor_i <= din_a_r xor din_b_r; -not_i <= not(din_b_r); - --- Shift. -GEN_shift: for I in 0 to B-1 generate - -- Zeros for padding before/after. - signal zeros_tmp : std_logic_vector (I-1 downto 0) := (others => '0'); -begin - ls_i(I) <= din_a_r(B-I-1 downto 0) & zeros_tmp; - rs_i(I) <= zeros_tmp & din_a_r(B-1 downto I); -end generate GEN_shift; - --- Left shift selection mux. -ls_mux <= ls_i(to_integer(shift_n)); - --- Right shift selection mux. -rs_mux <= rs_i(to_integer(shift_n)); - --- Shift amount. -shift_n <= unsigned(din_b(B_LOG2-1 downto 0)); - --- Output mux. -dout_mux <= and_i when op_r = "0000" else - or_i when op_r = "0001" else - xor_i when op_r = "0010" else - not_i when op_r = "0011" else - ls_mux when op_r = "0100" else - rs_mux when op_r = "0101" else - (others => '0'); - --- Assign outputs. -dout <= dout_rr; - -end rtl; - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/alu/math.vhd b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/alu/math.vhd deleted file mode 100644 index eeab7f8..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/alu/math.vhd +++ /dev/null @@ -1,108 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - --- Mathematical block. - --- It operates on two inputs. --- Operations are: --- 0000 : din_a + din_b --- 0001 : din_a - din_b --- 0010 : din_a * din_b - --- Product: takes B/2 lower bits from din_a and din_b. - --- Zero detection does not have any latency. --- Output latency is 3 clocks. - -entity math is - Generic ( - -- Data width. - B : Integer := 16 - ); - Port ( - -- Clock and reset. - clk : in std_logic; - rstn : in std_logic; - - -- Input operands. - din_a : in std_logic_vector (B-1 downto 0); - din_b : in std_logic_vector (B-1 downto 0); - - -- Operation. - op : in std_logic_vector (3 downto 0); - - -- Zero detection. - zero_a : out std_logic; - zero_b : out std_logic; - - -- Output. - dout : out std_logic_vector (B-1 downto 0) - ); -end math; - -architecture rtl of math is - --- Input registers. -signal din_a_r : signed (B-1 downto 0); -signal din_b_r : signed (B-1 downto 0); -signal op_r : std_logic_vector (3 downto 0); - --- Operations. -signal add_i : signed (B-1 downto 0); -signal sub_i : signed (B-1 downto 0); -signal prod_i : signed (B-1 downto 0); - --- Muxed output. -signal dout_mux : std_logic_vector (B-1 downto 0); - --- Output registers. -signal dout_r : std_logic_vector (B-1 downto 0); -signal dout_rr : std_logic_vector (B-1 downto 0); - -begin - --- Registers. -process (clk) -begin - if ( rising_edge(clk) ) then - if ( rstn = '0' ) then - -- Input registers. - din_a_r <= (others => '0'); - din_b_r <= (others => '0'); - op_r <= (others => '0'); - - -- Output registers. - dout_r <= (others => '0'); - dout_rr <= (others => '0'); - else - -- Input registers. - din_a_r <= signed(din_a); - din_b_r <= signed(din_b); - op_r <= op; - - -- Output registers. - dout_r <= dout_mux; - dout_rr <= dout_r; - end if; - end if; -end process; - --- Operations. -add_i <= din_a_r + din_b_r; -sub_i <= din_a_r - din_b_r; -prod_i <= din_a_r(B/2-1 downto 0)*din_b_r(B/2-1 downto 0); - --- Muxed output. -dout_mux <= std_logic_vector(add_i) when op_r = "0000" else - std_logic_vector(sub_i) when op_r = "0001" else - std_logic_vector(prod_i)when op_r = "0010" else - (others => '0'); - --- Assign outputs. -zero_a <= '1' when signed(din_a) = 0 else '0'; -zero_b <= '1' when signed(din_b) = 0 else '0'; -dout <= dout_rr; - -end rtl; - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axi_mst_0/axi_mst_0.veo b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axi_mst_0/axi_mst_0.veo deleted file mode 100644 index 5f33135..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axi_mst_0/axi_mst_0.veo +++ /dev/null @@ -1,85 +0,0 @@ -// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -// IP VLNV: xilinx.com:ip:axi_vip:1.1 -// IP Revision: 5 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -axi_mst_0 your_instance_name ( - .aclk(aclk), // input wire aclk - .aresetn(aresetn), // input wire aresetn - .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr - .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot - .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid - .m_axi_awready(m_axi_awready), // input wire m_axi_awready - .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata - .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb - .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid - .m_axi_wready(m_axi_wready), // input wire m_axi_wready - .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp - .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid - .m_axi_bready(m_axi_bready), // output wire m_axi_bready - .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr - .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot - .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid - .m_axi_arready(m_axi_arready), // input wire m_axi_arready - .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata - .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp - .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid - .m_axi_rready(m_axi_rready) // output wire m_axi_rready -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file axi_mst_0.v when simulating -// the core, axi_mst_0. When compiling the wrapper file, be sure to -// reference the Verilog simulation library. - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axi_mst_0/axi_mst_0.vho b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axi_mst_0/axi_mst_0.vho deleted file mode 100644 index 5c4d9a9..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axi_mst_0/axi_mst_0.vho +++ /dev/null @@ -1,115 +0,0 @@ --- (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:axi_vip:1.1 --- IP Revision: 5 - --- The following code must appear in the VHDL architecture header. - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT axi_mst_0 - PORT ( - aclk : IN STD_LOGIC; - aresetn : IN STD_LOGIC; - m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - m_axi_awvalid : OUT STD_LOGIC; - m_axi_awready : IN STD_LOGIC; - m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - m_axi_wvalid : OUT STD_LOGIC; - m_axi_wready : IN STD_LOGIC; - m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - m_axi_bvalid : IN STD_LOGIC; - m_axi_bready : OUT STD_LOGIC; - m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - m_axi_arvalid : OUT STD_LOGIC; - m_axi_arready : IN STD_LOGIC; - m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - m_axi_rvalid : IN STD_LOGIC; - m_axi_rready : OUT STD_LOGIC - ); -END COMPONENT; --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : axi_mst_0 - PORT MAP ( - aclk => aclk, - aresetn => aresetn, - m_axi_awaddr => m_axi_awaddr, - m_axi_awprot => m_axi_awprot, - m_axi_awvalid => m_axi_awvalid, - m_axi_awready => m_axi_awready, - m_axi_wdata => m_axi_wdata, - m_axi_wstrb => m_axi_wstrb, - m_axi_wvalid => m_axi_wvalid, - m_axi_wready => m_axi_wready, - m_axi_bresp => m_axi_bresp, - m_axi_bvalid => m_axi_bvalid, - m_axi_bready => m_axi_bready, - m_axi_araddr => m_axi_araddr, - m_axi_arprot => m_axi_arprot, - m_axi_arvalid => m_axi_arvalid, - m_axi_arready => m_axi_arready, - m_axi_rdata => m_axi_rdata, - m_axi_rresp => m_axi_rresp, - m_axi_rvalid => m_axi_rvalid, - m_axi_rready => m_axi_rready - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file axi_mst_0.vhd when simulating --- the core, axi_mst_0. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axi_mst_0/axi_mst_0.xci b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axi_mst_0/axi_mst_0.xci deleted file mode 100644 index 34f0b12..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axi_mst_0/axi_mst_0.xci +++ /dev/null @@ -1,187 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - axi_mst_0 - - - ACTIVE_LOW - - 100000000 - 0 - 0.000 - 32 - 0 - 0 - 0 - - 32 - 100000000 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 32 - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 0 - 2 - 32 - 0 - 0 - 0 - 32 - 0 - 0 - 32 - 0 - 0 - 0 - axi_mst_0 - 32 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 0 - 0 - 1 - 0 - MASTER - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - virtex7 - - - xc7vx485t - ffg1157 - VERILOG - - MIXED - -1 - - - TRUE - TRUE - IP_Flow - 5 - TRUE - . - - . - 2019.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axi_mst_0/axi_mst_0.xml b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axi_mst_0/axi_mst_0.xml deleted file mode 100644 index f2fccc7..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axi_mst_0/axi_mst_0.xml +++ /dev/null @@ -1,4751 +0,0 @@ - - - xilinx.com - customized_ip - axi_mst_0 - 1.0 - - - M_AXI - - - - - - - - - ARADDR - - - m_axi_araddr - - - - - ARBURST - - - m_axi_arburst - - - - - ARCACHE - - - m_axi_arcache - - - - - ARID - - - m_axi_arid - - - - - ARLEN - - - m_axi_arlen - - - - - ARLOCK - - - m_axi_arlock - - - - - ARPROT - - - m_axi_arprot - - - - - ARQOS - - - m_axi_arqos - - - - - ARREADY - - - m_axi_arready - - - - - ARREGION - - - m_axi_arregion - - - - - ARSIZE - - - m_axi_arsize - - - - - ARUSER - - - m_axi_aruser - - - - - ARVALID - - - m_axi_arvalid - - - - - AWADDR - - - m_axi_awaddr - - - - - AWBURST - - - m_axi_awburst - - - - - AWCACHE - - - m_axi_awcache - - - - - AWID - - - m_axi_awid - - - - - AWLEN - - - m_axi_awlen - - - - - AWLOCK - - - m_axi_awlock - - - - - AWPROT - - - m_axi_awprot - - - - - AWQOS - - - m_axi_awqos - - - - - AWREADY - - - m_axi_awready - - - - - AWREGION - - - m_axi_awregion - - - - - AWSIZE - - - m_axi_awsize - - - - - AWUSER - - - m_axi_awuser - - - - - AWVALID - - - m_axi_awvalid - - - - - BID - - - m_axi_bid - - - - - BREADY - - - m_axi_bready - - - - - BRESP - - - m_axi_bresp - - - - - BUSER - - - m_axi_buser - - - - - BVALID - - - m_axi_bvalid - - - - - RDATA - - - m_axi_rdata - - - - - RID - - - m_axi_rid - - - - - RLAST - - - m_axi_rlast - - - - - RREADY - - - m_axi_rready - - - - - RRESP - - - m_axi_rresp - - - - - RUSER - - - m_axi_ruser - - - - - RVALID - - - m_axi_rvalid - - - - - WDATA - - - m_axi_wdata - - - - - WID - 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- - ARQOS - - - s_axi_arqos - - - - - ARREADY - - - s_axi_arready - - - - - ARREGION - - - s_axi_arregion - - - - - ARSIZE - - - s_axi_arsize - - - - - ARUSER - - - s_axi_aruser - - - - - ARVALID - - - s_axi_arvalid - - - - - AWADDR - - - s_axi_awaddr - - - - - AWBURST - - - s_axi_awburst - - - - - AWCACHE - - - s_axi_awcache - - - - - AWID - - - s_axi_awid - - - - - AWLEN - - - s_axi_awlen - - - - - AWLOCK - - - s_axi_awlock - - - - - AWPROT - - - s_axi_awprot - - - - - AWQOS - - - s_axi_awqos - - - - - AWREADY - - - s_axi_awready - - - - - AWREGION - - - s_axi_awregion - - - - - AWSIZE - - - s_axi_awsize - - - - - AWUSER - - - s_axi_awuser - - - - - AWVALID - - - s_axi_awvalid - - - - - BID - - - s_axi_bid - - - - - BREADY - - - s_axi_bready - - - - - BRESP - - - s_axi_bresp - - - - - BUSER - - - s_axi_buser - - - - - BVALID - - - s_axi_bvalid - - - - - RDATA - - - s_axi_rdata - - - - - RID - - - s_axi_rid - - - - - RLAST - - - s_axi_rlast - - - - - RREADY - - - s_axi_rready - - - - - RRESP - - - s_axi_rresp - - - - - RUSER - - - s_axi_ruser - - - - - RVALID - - - s_axi_rvalid - - - - - WDATA - - - s_axi_wdata - - - - - WID - - - s_axi_wid - - - - - WLAST - - - s_axi_wlast - - - - - WREADY - - - s_axi_wready - - - - - WSTRB - - - s_axi_wstrb - - - - - WUSER - - - s_axi_wuser - - - - - WVALID - - - s_axi_wvalid - - - - - - DATA_WIDTH - 1 - - - simulation.tlm - - - - - PROTOCOL - AXI4LITE - - - simulation.tlm - - - - - FREQ_HZ - 100000000 - - - simulation.tlm - - - - - ID_WIDTH - 0 - - - simulation.tlm - - - - - ADDR_WIDTH - 1 - - - simulation.tlm - - - - - AWUSER_WIDTH - 0 - - - simulation.tlm - - - - - ARUSER_WIDTH - 0 - - - simulation.tlm - - - - - WUSER_WIDTH - 0 - - - simulation.tlm - - - - - RUSER_WIDTH - 0 - - - simulation.tlm - - - - - BUSER_WIDTH - 0 - - - simulation.tlm - - - - - READ_WRITE_MODE - READ_WRITE - - - simulation.tlm - - - - - HAS_BURST - 0 - - - simulation.tlm - - - - - HAS_LOCK - 0 - - - simulation.tlm - - - - - HAS_PROT - 0 - - - simulation.tlm - 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- true - - - - - - ACLKEN - - - - - - - CE - - - aclken - - - - - - POLARITY - ACTIVE_LOW - - - none - - - - - - - - false - - - - - - CLOCK - - - - - - - CLK - - - aclk - - - - - - ASSOCIATED_BUSIF - M_AXI:S_AXI - - - ASSOCIATED_RESET - aresetn - - - FREQ_HZ - 100000000 - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - M_AXI_TLM - - - - - - - AXIMM_READ_SOCKET - - - M_INITIATOR_rd_socket - - - - - AXIMM_WRITE_SOCKET - - - M_INITIATOR_wr_socket - - - - - - S_AXI_TLM - - - - - - - AXIMM_READ_SOCKET - - - S_TARGET_rd_socket - - - - - AXIMM_WRITE_SOCKET - - - S_TARGET_wr_socket - - - - - - - - Master_AXI - 4294967296 - 32 - - - - true - - - - - - - - S_AXI - - Reg - 0 - 65536 - 32 - read-write - - - - false - - - - - - - - - - xilinx_veriloginstantiationtemplate - Verilog Instantiation Template - verilogSource:vivado.xilinx.com:synthesis.template - verilog - - xilinx_veriloginstantiationtemplate_view_fileset - - - - GENtimestamp - Thu Dec 17 22:05:33 UTC 2020 - - - outputProductCRC - 9:564fbf77 - - - - - xilinx_verilogsynthesis - Verilog Synthesis - verilogSource:vivado.xilinx.com:synthesis - verilog - axi_vip_v1_1_5_top - - xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset - - - xilinx_verilogsynthesis_view_fileset - - - - GENtimestamp - Thu Dec 17 22:05:37 UTC 2020 - - - outputProductCRC - 9:564fbf77 - - - - - xilinx_synthesisconstraints - Synthesis Constraints - :vivado.xilinx.com:synthesis.constraints - - xilinx_synthesisconstraints_view_fileset - - - - GENtimestamp - Thu Dec 17 22:05:37 UTC 2020 - - - outputProductCRC - 9:564fbf77 - - - - - xilinx_verilogsynthesiswrapper - Verilog Synthesis Wrapper - verilogSource:vivado.xilinx.com:synthesis.wrapper - verilog - axi_mst_0 - - xilinx_verilogsynthesiswrapper_view_fileset - - - - GENtimestamp - Thu Dec 17 22:05:37 UTC 2020 - - - outputProductCRC - 9:564fbf77 - - - - - xilinx_versioninformation - Version Information - :vivado.xilinx.com:docs.versioninfo - axi_vip_v1_1_5_top - - xilinx_versioninformation_view_fileset - - - - GENtimestamp - Thu Dec 17 22:05:37 UTC 2020 - - - outputProductCRC - 9:564fbf77 - - - - - xilinx_externalfiles - External Files - :vivado.xilinx.com:external.files - - xilinx_externalfiles_view_fileset - - - - GENtimestamp - Thu Dec 17 22:06:13 UTC 2020 - - - outputProductCRC - 9:564fbf77 - - - - - xilinx_verilogbehavioralsimulation - Verilog Simulation - verilogSource:vivado.xilinx.com:simulation - verilog - axi_vip_v1_1_5_top - - xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset - - - xilinx_verilogbehavioralsimulation_view_fileset - - - - GENtimestamp - Thu May 20 20:20:28 UTC 2021 - - - outputProductCRC - 9:eaaf4dfa - - - - - xilinx_systemcsimulation - SystemC Simulation - systemCSource:vivado.xilinx.com:simulation - systemc - axi_vip - - xilinx_systemcsimulation_view_fileset - - - - GENtimestamp - Thu May 20 20:20:28 UTC 2021 - - - outputProductCRC - 9:6d8e49fa - - - sim_type - tlm - - - use_subcore_outputs - false - - - - - xilinx_verilogsimulationwrapper - Verilog Simulation Wrapper - verilogSource:vivado.xilinx.com:simulation.wrapper - verilog - axi_mst_0 - - xilinx_verilogsimulationwrapper_view_fileset - - - - GENtimestamp - Thu May 20 20:20:28 UTC 2021 - - - outputProductCRC - 9:eaaf4dfa - - - - - xilinx_systemcsimulationwrapper - SystemC Simulation Wrapper - systemCSource:vivado.xilinx.com:simulation.wrapper - systemc - axi_mst_0 - - xilinx_systemcsimulationwrapper_view_fileset - - - - GENtimestamp - Thu May 20 20:20:28 UTC 2021 - - - outputProductCRC - 9:6d8e49fa - - - sim_type - tlm - - - - - - - aclk - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - aclken - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 1 - - - - - - false - - - - - - aresetn - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 1 - - - - - - true - - - - - - s_axi_awid - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_awaddr - - in - - 31 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_awlen - - in - - 7 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_awsize - - in - - 2 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_awburst - - in - - 1 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 1 - - - - - - false - - - - - - s_axi_awlock - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_awcache - 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- - - - - - false - - - - - - s_axi_wid - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_wdata - - in - - 31 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_wstrb - - in - - 3 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0xF - - - - - - false - - - - - - s_axi_wlast - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_wuser - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_wvalid - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_wready - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - s_axi_bid - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - s_axi_bresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - s_axi_buser - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - s_axi_bvalid - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - s_axi_bready - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arid - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_araddr - - in - - 31 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arlen - - in - - 7 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arsize - - in - - 2 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arburst - - in - - 1 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 1 - - - - - - false - - - - - - s_axi_arlock - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arcache - - in - - 3 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arprot - - in - - 2 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arregion - - in - - 3 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arqos - - in - - 3 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_aruser - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arvalid - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arready - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - s_axi_rid - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - s_axi_rdata - - out - - 31 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - s_axi_rresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - s_axi_rlast - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - s_axi_ruser - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - s_axi_rvalid - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - s_axi_rready - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - m_axi_awid - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_awaddr - - out - - 31 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - m_axi_awlen - - out - - 7 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_awsize - - out - - 2 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_awburst - - out - - 1 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_awlock - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_awcache - - out - - 3 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_awprot - - out - - 2 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - m_axi_awregion - - out - - 3 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_awqos - - out - - 3 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_awuser - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_awvalid - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - m_axi_awready - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - true - - - - - - m_axi_wid - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_wdata - - out - - 31 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - m_axi_wstrb - - out - - 3 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - m_axi_wlast - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_wuser - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_wvalid - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - m_axi_wready - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - true - - - - - - m_axi_bid - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - m_axi_bresp - - in - - 1 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - true - - - - - - m_axi_buser - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - m_axi_bvalid - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - true - - - - - - m_axi_bready - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - m_axi_arid - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_araddr - - out - - 31 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - m_axi_arlen - - out - - 7 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_arsize - - out - - 2 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_arburst - - out - - 1 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_arlock - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_arcache - - out - - 3 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_arprot - - out - - 2 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - m_axi_arregion - - out - - 3 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_arqos - - out - - 3 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_aruser - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axi_arvalid - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - m_axi_arready - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - true - - - - - - m_axi_rid - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - m_axi_rdata - - in - - 31 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - true - - - - - - m_axi_rresp - - in - - 1 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - true - - - - - - m_axi_rlast - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - m_axi_ruser - - in - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - false - - - - - - m_axi_rvalid - - in - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0 - - - - - - true - - - - - - m_axi_rready - - out - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - M_INITIATOR_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - M_INITIATOR_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - S_TARGET_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - wr_socket - - - - - - - 1 - - - - - S_TARGET_rd_socket - AXIMM Read Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - rd_socket - - - - - - - 1 - - - - - - - C_AXI_PROTOCOL - 2 - - - C_AXI_INTERFACE_MODE - 0 - - - C_AXI_ADDR_WIDTH - 32 - - - C_AXI_WDATA_WIDTH - 32 - - - C_AXI_RDATA_WIDTH - 32 - - - C_AXI_WID_WIDTH - 0 - - - C_AXI_RID_WIDTH - 0 - - - C_AXI_AWUSER_WIDTH - 0 - - - C_AXI_ARUSER_WIDTH - 0 - - - C_AXI_WUSER_WIDTH - 0 - - - C_AXI_RUSER_WIDTH - 0 - - - C_AXI_BUSER_WIDTH - 0 - - - C_AXI_SUPPORTS_NARROW - 0 - - - C_AXI_HAS_BURST - 0 - - - C_AXI_HAS_LOCK - 0 - - - C_AXI_HAS_CACHE - 0 - - - C_AXI_HAS_REGION - 0 - - - C_AXI_HAS_PROT - 1 - - - C_AXI_HAS_QOS - 0 - - - C_AXI_HAS_WSTRB - 1 - - - C_AXI_HAS_BRESP - 1 - - - C_AXI_HAS_RRESP - 1 - - - C_AXI_HAS_ARESETN - 1 - - - - - - choice_list_04fafd91 - AXI3 - AXI4 - AXI4LITE - - - choice_list_6240decd - READ_ONLY - READ_WRITE - WRITE_ONLY - - - choice_list_642e7122 - MASTER - PASS_THROUGH - SLAVE - - - choice_list_99ba8646 - 32 - 64 - - - choice_list_9d8b0d81 - ACTIVE_HIGH - ACTIVE_LOW - - - choice_pairs_0fc128e8 - 0 - 0 - - - - - xilinx_veriloginstantiationtemplate_view_fileset - - axi_mst_0.vho - vhdlTemplate - - - axi_mst_0.veo - verilogTemplate - - - - xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset - - hdl/axi_infrastructure_v1_1_0.vh - verilogSource - true - axi_infrastructure_v1_1_0 - - - hdl/axi_infrastructure_v1_1_vl_rfs.v - verilogSource - axi_infrastructure_v1_1_0 - - - - - - - - - - - xilinx_verilogsynthesis_view_fileset - - hdl/axi_vip_v1_1_vlsyn_rfs.sv - systemVerilogSource - axi_vip_v1_1_5 - - - - xilinx_synthesisconstraints_view_fileset - - axi_mst_0_ooc.xdc - xdc - USED_IN_implementation - USED_IN_out_of_context - USED_IN_synthesis - - - - xilinx_verilogsynthesiswrapper_view_fileset - - synth/axi_mst_0.sv - systemVerilogSource - xil_defaultlib - - - - xilinx_versioninformation_view_fileset - - doc/axi_vip_v1_1_changelog.txt - text - axi_vip_v1_1_5 - - - - xilinx_externalfiles_view_fileset - - axi_mst_0.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - axi_mst_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - axi_mst_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - axi_mst_0_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - axi_mst_0_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - - xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset - - hdl/axi_infrastructure_v1_1_0.vh - verilogSource - USED_IN_ipstatic - true - axi_infrastructure_v1_1_0 - - - hdl/axi_infrastructure_v1_1_vl_rfs.v - verilogSource - USED_IN_ipstatic - axi_infrastructure_v1_1_0 - - - - - - - - - - - xilinx_verilogbehavioralsimulation_view_fileset - - sim/axi_mst_0_pkg.sv - systemVerilogSource - - - hdl/axi_vip_v1_1_vl_rfs.sv - systemVerilogSource - USED_IN_ipstatic - axi_vip_v1_1_5 - - - - xilinx_systemcsimulation_view_fileset - - sysc/axi_vip.cpp - systemCSource - axi_vip_v1_1_5 - - - sysc/axi_vip.h - systemCSource - true - axi_vip_v1_1_5 - - - - xilinx_verilogsimulationwrapper_view_fileset - - sim/axi_mst_0.sv - systemVerilogSource - xil_defaultlib - - - - xilinx_systemcsimulationwrapper_view_fileset - - sim/axi_mst_0_sc.h - systemCSource - true - - - sim/axi_mst_0_sc.cpp - systemCSource - - - sim/axi_mst_0.h - systemCSource - true - - - sim/axi_mst_0.cpp - systemCSource - - - sim/axi_mst_0_stub.sv - systemVerilogSource - - - - The AXI Verification IP. - - - Component_Name - Component Name - axi_mst_0 - - - PROTOCOL - PROTOCOL - AXI4LITE - - - READ_WRITE_MODE - READ_WRITE MODE - READ_WRITE - - - INTERFACE_MODE - INTERFACE MODE - MASTER - - - ADDR_WIDTH - ADDRESS WIDTH - 32 - - - DATA_WIDTH - DATA WIDTH - 32 - - - ID_WIDTH - ID WIDTH - 0 - - - - false - - - - - - AWUSER_WIDTH - AWUSER WIDTH - 0 - - - - false - - - - - - ARUSER_WIDTH - ARUSER WIDTH - 0 - - - - false - - - - - - RUSER_WIDTH - RUSER WIDTH - 0 - - - - false - - - - - - WUSER_WIDTH - WUSER WIDTH - 0 - - - - false - - - - - - BUSER_WIDTH - BUSER WIDTH - 0 - - - - false - - - - - - WUSER_BITS_PER_BYTE - WUSER BITS PER BYTE - 0 - - - - false - - - - - - RUSER_BITS_PER_BYTE - RUSER BITS PER BYTE - 0 - - - - false - - - - - - HAS_USER_BITS_PER_BYTE - HAS USER_BITS_PER_BYTE - 0 - - - - false - - - - - - SUPPORTS_NARROW - SUPPORTS NARROW - 0 - - - - false - - - - - - HAS_SIZE - HAS SIZE - 0 - - - - false - - - - - - HAS_BURST - HAS BURST - 0 - - - - false - - - - - - HAS_LOCK - HAS LOCK - 0 - - - - false - - - - - - HAS_CACHE - HAS CACHE - 0 - - - - false - - - - - - HAS_REGION - HAS REGION - 0 - - - - false - - - - - - HAS_QOS - HAS QOS - 0 - - - - false - - - - - - HAS_PROT - HAS PROT - 1 - - - HAS_WSTRB - HAS WSTRB - 1 - - - HAS_BRESP - HAS BRESP - 1 - - - HAS_RRESP - HAS RRESP - 1 - - - HAS_ACLKEN - HAS ACLKEN - 0 - - - HAS_ARESETN - HAS ARESETN - 1 - - - - - AXI Verification IP - - xtlm - - 5 - true - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2019.1 - - - - - - - - - - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axi_slv_custom.sv b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axi_slv_custom.sv deleted file mode 100644 index 9369730..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axi_slv_custom.sv +++ /dev/null @@ -1,434 +0,0 @@ -// Custom axi-lite slave block with limited functionality: -// -// * Address map is DATA_WIDTH based, not byte based. -// * Strobe not implemented. Always full access. -// -// The slave supports a maximum of 16-bit address space. The lower portion -// is reserved for registers, the upper portion for external memory. -// Registers: 64 registers, 32-bit each (4 bytes), gives 256 bytes. -// -// AXI RRESP/BRESP: when the external memory arbiter is executing a stream -// operation, memory is busy and cannot be accesses with single read/write -// modes. In this case, the axi slave will return with an error code: -// RRESP/BRESP = 2'b10 (SLVERR, see AXI specification). -// -// In any other access, if the operation is executed properly, the axi slave -// block will return a OKAY standard code: -// RRESP/BRESP = 2'b00 (OKAY, see AXI specification). -// -// This allows to avoid dead-locks due to the bus already taken. -// -module axi_slv_custom ( - // Reset and clock. - aclk_i , - aresetn_i , - - // Write Address Channel. - awaddr_i , - awprot_i , - awvalid_i , - awready_o , - - // Write Data Channel. - wdata_i , - wstrb_i , - wvalid_i , - wready_o , - - // Write Response Channel. - bresp_o , - bvalid_o , - bready_i , - - // Read Address Channel. - araddr_i , - arprot_i , - arvalid_i , - arready_o , - - // Read Data Channel. - rdata_o , - rresp_o , - rvalid_o , - rready_i , - - // Single Access Handshake. - busy_i , - oper_o , - addr_o , - dwrite_o , - dread_i , - exec_o , - exec_ack_i , - - // Registers. - START_SRC_REG , - START_REG , - MEM_MODE_REG , - MEM_START_REG , - MEM_ADDR_REG , - MEM_LEN_REG -); - -// Parameters. -localparam DATA_WIDTH = 32; -localparam DATA_WIDTH_BYTE = DATA_WIDTH/8; -localparam DATA_WIDTH_BYTE_LOG2 = $clog2(DATA_WIDTH_BYTE); -localparam NREG = 64; -localparam NREG_BYTE = NREG*DATA_WIDTH_BYTE; - -// Ports. -input aclk_i; -input aresetn_i; - -input [31:0] awaddr_i; -input [2:0] awprot_i; -input awvalid_i; -output reg awready_o; - -input [DATA_WIDTH-1:0] wdata_i; -input [DATA_WIDTH/8-1:0] wstrb_i; -input wvalid_i; -output reg wready_o; - -output [1:0] bresp_o; -output reg bvalid_o; -input bready_i; - -input [31:0] araddr_i; -input [2:0] arprot_i; -input arvalid_i; -output reg arready_o; - -output [DATA_WIDTH-1:0] rdata_o; -output [1:0] rresp_o; -output reg rvalid_o; -input rready_i; - -input busy_i; -output reg oper_o; -output [31:0] addr_o; -output [DATA_WIDTH-1:0] dwrite_o; -input [DATA_WIDTH-1:0] dread_i; -output reg exec_o; -input exec_ack_i; - -output START_SRC_REG; -output START_REG; -output MEM_MODE_REG; -output MEM_START_REG; -output [31:0] MEM_ADDR_REG; -output [31:0] MEM_LEN_REG; - -// States. -typedef enum { INIT_ST , - AWADDR_ST , // Address Write State. - WDATA_ST , // Write Data State. - BRESP_ST , // Write Response State. - ARADDR_ST , // Address Read State. - RDATA_ST , // Read Data State. - REG_WR_ST , // Lower address, write internal register map. - MEM_WR_ST , // Higher address, write external memory. - REG_RD_ST , // Lower address, read internal register map. - MEM_RD_ST , // Higher address, read external memory. - WR_ACK_ST , // Wait acknowledge from single write access interface. - RD_ACK_ST , // Wait acknowledge from single read access interface. - BRESP_OK_ST , // Set BRESP OKAY response register. - BRESP_ERR_ST , // Set BRESP SLVERR response register. - RRESP_OK_ST , // Set RRESP OKAY response register. - RRESP_ERR_ST // Set RRESP SLVERR response register. - } state_t; - -(* fsm_encoding = "one_hot" *) state_t state; - -// Flags. -reg reg_rw; // 0: register read, 1: register write. -reg sel_int; // 0: register, 1: external memory. -reg data_en; // Enable data register. -reg addr_sel; // 0: awaddr, 1: araddr. - -// Address register. -reg [31:0] addr_r; -wire [31:0] addr_mux; - -// Output memory address computation. -wire [31:0] addr_out; - -// Data registers. -reg [DATA_WIDTH-1:0] wdata_r; -reg [DATA_WIDTH-1:0] data_r; -wire [DATA_WIDTH-1:0] data_mux; - -// Resp register. -reg [1:0] resp_r; -reg resp_en; -reg [1:0] resp_int; // 2'b00: OKAY, 2'b10: SLVERR. - -// Register map. -reg [DATA_WIDTH-1:0] reg0; -reg [DATA_WIDTH-1:0] reg1; -reg [DATA_WIDTH-1:0] reg2; -reg [DATA_WIDTH-1:0] reg3; -reg [DATA_WIDTH-1:0] reg4; -reg [DATA_WIDTH-1:0] reg5; -reg [DATA_WIDTH-1:0] reg6; -reg [DATA_WIDTH-1:0] reg7; -wire [DATA_WIDTH-1:0] reg_int; // Selected register. - -// Registers. -always @(posedge aclk_i) begin - if (~aresetn_i) begin - // State register. - state <= INIT_ST; - - // Address register. - addr_r <= 0; - - // Data registers. - wdata_r <= 0; - data_r <= 0; - - // Resp register. - resp_r <= 0; - - // Register map. - reg0 <= 0; - reg1 <= 0; - reg2 <= 0; - reg3 <= 0; - reg4 <= 0; - reg5 <= 0; - reg6 <= 0; - reg7 <= 0; - end - else begin - // State register. - case (state) - INIT_ST: - if (awvalid_i) - state <= AWADDR_ST; - else if (arvalid_i) - state <= ARADDR_ST; - - AWADDR_ST: - state <= WDATA_ST; - - WDATA_ST: - if (wvalid_i) - if (addr_r < NREG_BYTE) - // Lower address map, register write. - state <= REG_WR_ST; - else - // Higher address map, memory write. - if (busy_i) - state <= BRESP_ERR_ST; - else - state <= MEM_WR_ST; - - BRESP_ST: - if (bready_i) - state <= INIT_ST; - - ARADDR_ST: - if (araddr_i < NREG_BYTE) - // Lower address map, register read. - state <= REG_RD_ST; - else - // Higher address map, memory read. - if (busy_i) - state <= RRESP_ERR_ST; - else - state <= MEM_RD_ST; - - RDATA_ST: - if (rready_i) - state <= INIT_ST; - - REG_WR_ST: - state <= BRESP_OK_ST; - - MEM_WR_ST: - if (exec_ack_i) - state <= WR_ACK_ST; - - REG_RD_ST: - state <= RRESP_OK_ST; - - MEM_RD_ST: - if (exec_ack_i) - state <= RD_ACK_ST; - - WR_ACK_ST: - if (~exec_ack_i) - state <= BRESP_OK_ST; - - RD_ACK_ST: - if (~exec_ack_i) - state <= RRESP_OK_ST; - - BRESP_OK_ST: - state <= BRESP_ST; - - BRESP_ERR_ST: - state <= BRESP_ST; - - RRESP_OK_ST: - state <= RDATA_ST; - - RRESP_ERR_ST: - state <= RDATA_ST; - - endcase - - // Address register. - if ((awvalid_i && awready_o) || (arvalid_i && arready_o)) - addr_r <= addr_mux; - - // Data registers. - if (wvalid_i && wready_o) - wdata_r <= wdata_i; - - if (data_en) - data_r <= data_mux; - - // Resp register. - if (resp_en) - resp_r <= resp_int; - - // Register write. - if (reg_rw) - case (addr_r) - 0: reg0 <= wdata_r; - 4: reg1 <= wdata_r; - 8: reg2 <= wdata_r; - 12: reg3 <= wdata_r; - 16: reg4 <= wdata_r; - 20: reg5 <= wdata_r; - 24: reg6 <= wdata_r; - 28: reg7 <= wdata_r; - endcase - end -end - -// FSM outputs. -always_comb begin - // Default value. - awready_o = 0; - wready_o = 0; - bvalid_o = 0; - arready_o = 0; - rvalid_o = 0; - oper_o = 0; // 0: read, 1: write. - exec_o = 0; - reg_rw = 0; - sel_int = 0; - data_en = 0; - addr_sel = 0; - resp_en = 0; - resp_int = 0; - - case (state) - //INIT_ST: - - AWADDR_ST: begin - awready_o = 1; - addr_sel = 0; - end - - WDATA_ST: - wready_o = 1; - - BRESP_ST: - bvalid_o = 1; - - ARADDR_ST: begin - arready_o = 1; - addr_sel = 1; - end - - RDATA_ST: - rvalid_o = 1; - - REG_WR_ST: - reg_rw = 1; - - MEM_WR_ST: begin - oper_o = 1; - exec_o = 1; - end - - REG_RD_ST: begin - reg_rw = 0; - sel_int = 0; - data_en = 1; - end - - MEM_RD_ST: begin - oper_o = 0; - exec_o = 1; - sel_int = 1; - data_en = 1; - end - - //WR_ACK_ST: - - //RD_ACK_ST: - - BRESP_OK_ST: begin - resp_en = 1; - resp_int = 2'b00; - end - - BRESP_ERR_ST: begin - resp_en = 1; - resp_int = 2'b10; - end - - RRESP_OK_ST: begin - resp_en = 1; - resp_int = 2'b00; - end - - RRESP_ERR_ST: begin - resp_en = 1; - resp_int = 2'b10; - end - - endcase -end - -// Output memory address computation. -assign addr_out = addr_r - NREG_BYTE; - -// Address mux. -assign addr_mux = (addr_sel == 0)? awaddr_i : araddr_i; - -// Data mux. -assign data_mux = (sel_int == 0)? reg_int : dread_i; - -// Mux for register. -assign reg_int = (addr_r == 0)? reg0 : - (addr_r == 4)? reg1 : - (addr_r == 8)? reg2 : - (addr_r == 12)? reg3 : - (addr_r == 16)? reg4 : - (addr_r == 20)? reg5 : - (addr_r == 24)? reg6 : - (addr_r == 28)? reg7 : - 0; - -// Assign outputs. -assign bresp_o = resp_r; -assign rresp_o = resp_r; -assign rdata_o = data_r; -assign addr_o = addr_out[31:DATA_WIDTH_BYTE_LOG2]; // Byte to Sample-based. -assign dwrite_o = wdata_r; -assign START_SRC_REG = reg0[0]; -assign START_REG = reg1[0]; -assign MEM_MODE_REG = reg2[0]; -assign MEM_START_REG = reg3[0]; -assign MEM_ADDR_REG = reg4; -assign MEM_LEN_REG = reg5; - -endmodule - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axis_mst_0/axis_mst_0.veo b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axis_mst_0/axis_mst_0.veo deleted file mode 100644 index 40fe937..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axis_mst_0/axis_mst_0.veo +++ /dev/null @@ -1,71 +0,0 @@ -// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -// IP VLNV: xilinx.com:ip:axi4stream_vip:1.1 -// IP Revision: 5 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -axis_mst_0 your_instance_name ( - .aclk(aclk), // input wire aclk - .aresetn(aresetn), // input wire aresetn - .m_axis_tvalid(m_axis_tvalid), // output wire [0 : 0] m_axis_tvalid - .m_axis_tready(m_axis_tready), // input wire [0 : 0] m_axis_tready - .m_axis_tdata(m_axis_tdata), // output wire [31 : 0] m_axis_tdata - .m_axis_tstrb(m_axis_tstrb), // output wire [3 : 0] m_axis_tstrb - .m_axis_tlast(m_axis_tlast) // output wire [0 : 0] m_axis_tlast -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file axis_mst_0.v when simulating -// the core, axis_mst_0. When compiling the wrapper file, be sure to -// reference the Verilog simulation library. - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axis_mst_0/axis_mst_0.vho b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axis_mst_0/axis_mst_0.vho deleted file mode 100644 index a9ea647..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axis_mst_0/axis_mst_0.vho +++ /dev/null @@ -1,87 +0,0 @@ --- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:axi4stream_vip:1.1 --- IP Revision: 5 - --- The following code must appear in the VHDL architecture header. - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT axis_mst_0 - PORT ( - aclk : IN STD_LOGIC; - aresetn : IN STD_LOGIC; - m_axis_tvalid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - m_axis_tready : IN STD_LOGIC_VECTOR(0 DOWNTO 0); - m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axis_tstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - m_axis_tlast : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) - ); -END COMPONENT; --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : axis_mst_0 - PORT MAP ( - aclk => aclk, - aresetn => aresetn, - m_axis_tvalid => m_axis_tvalid, - m_axis_tready => m_axis_tready, - m_axis_tdata => m_axis_tdata, - m_axis_tstrb => m_axis_tstrb, - m_axis_tlast => m_axis_tlast - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file axis_mst_0.vhd when simulating --- the core, axis_mst_0. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axis_mst_0/axis_mst_0.xci b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axis_mst_0/axis_mst_0.xci deleted file mode 100644 index 4d57aef..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axis_mst_0/axis_mst_0.xci +++ /dev/null @@ -1,105 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - axis_mst_0 - - - ACTIVE_LOW - - 100000000 - 0 - 0.000 - - 100000000 - 0 - 1 - 1 - 1 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - 32 - 0 - 1 - 0 - 0 - 0b00000000000000000000000000010111 - 0 - 0 - axis_mst_0 - 0 - 1 - 0 - 1 - 1 - 1 - 0 - MASTER - 4 - 0 - 0 - 0 - 0 - virtex7 - - - xc7vx485t - ffg1157 - VERILOG - - MIXED - -1 - - - TRUE - TRUE - IP_Flow - 5 - TRUE - . - - . - 2019.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axis_mst_0/axis_mst_0.xml b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axis_mst_0/axis_mst_0.xml deleted file mode 100644 index 6fbde64..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axis_mst_0/axis_mst_0.xml +++ /dev/null @@ -1,1548 +0,0 @@ - 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- - choice_list_9d8b0d81 - ACTIVE_HIGH - ACTIVE_LOW - - - choice_pairs_2d96f706 - 0 - 1 - - - - - xilinx_veriloginstantiationtemplate_view_fileset - - axis_mst_0.vho - vhdlTemplate - - - axis_mst_0.veo - verilogTemplate - - - - xilinx_verilogsynthesis_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset - - hdl/axis_infrastructure_v1_1_0.vh - verilogSource - true - axis_infrastructure_v1_1_0 - - - hdl/axis_infrastructure_v1_1_vl_rfs.v - verilogSource - axis_infrastructure_v1_1_0 - - - - - - - - - - - xilinx_verilogsynthesis_view_fileset - - hdl/axi4stream_vip_v1_1_vlsyn_rfs.sv - systemVerilogSource - axi4stream_vip_v1_1_5 - - - - xilinx_synthesisconstraints_view_fileset - - axis_mst_0_ooc.xdc - xdc - USED_IN_implementation - USED_IN_out_of_context - USED_IN_synthesis - - - - xilinx_verilogsynthesiswrapper_view_fileset - - synth/axis_mst_0.sv - systemVerilogSource - xil_defaultlib - - - - xilinx_versioninformation_view_fileset - - doc/axi4stream_vip_v1_1_changelog.txt - text - axi4stream_vip_v1_1_5 - - - - xilinx_externalfiles_view_fileset - - axis_mst_0.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - axis_mst_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - axis_mst_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - axis_mst_0_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - axis_mst_0_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - - xilinx_verilogbehavioralsimulation_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset - - hdl/axis_infrastructure_v1_1_0.vh - verilogSource - USED_IN_ipstatic - true - axis_infrastructure_v1_1_0 - - - hdl/axis_infrastructure_v1_1_vl_rfs.v - verilogSource - USED_IN_ipstatic - axis_infrastructure_v1_1_0 - - - - - - - - - - - xilinx_verilogbehavioralsimulation_view_fileset - - sim/axis_mst_0_pkg.sv - systemVerilogSource - - - hdl/axi4stream_vip_v1_1_vl_rfs.sv - systemVerilogSource - USED_IN_ipstatic - axi4stream_vip_v1_1_5 - - - - xilinx_verilogsimulationwrapper_view_fileset - - sim/axis_mst_0.sv - systemVerilogSource - xil_defaultlib - - - - The AXI4-Stream Verification IP. - - - INTERFACE_MODE - INTERFACE MODE - MASTER - - - TDATA_NUM_BYTES - TDATA WIDTH(BYTES) - 4 - - - USER_BITS_PER_BYTE - TUSER BITS PER BYTE - 0 - - - - false - - - - - - HAS_TUSER_BITS_PER_BYTE - HAS TUSER_BITS_PER_BYTE - 0 - - - TID_WIDTH - TID WIDTH(BITS) - 0 - - - TDEST_WIDTH - TDEST WIDTH(BITS) - 0 - - - TUSER_WIDTH - TUSER WIDTH(BITS) - 0 - - - HAS_TREADY - ENABLE TREADY - 1 - - - HAS_TSTRB - ENABLE TSTRB - 1 - - - HAS_TKEEP - ENABLE TKEEP - 0 - - - HAS_TLAST - ENABLE TLAST - 1 - - - HAS_ACLKEN - HAS ACLKEN - 0 - - - HAS_ARESETN - HAS ARESETN - 1 - - - Component_Name - axis_mst_0 - - - - - AXI4-Stream Verification IP - - XPM_CDC - - 5 - true - - - - - - - - - - - - - - 2019.1 - - - - - - - - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axis_slv_0/axis_slv_0.veo b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axis_slv_0/axis_slv_0.veo deleted file mode 100644 index 5072ea6..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axis_slv_0/axis_slv_0.veo +++ /dev/null @@ -1,71 +0,0 @@ -// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -// IP VLNV: xilinx.com:ip:axi4stream_vip:1.1 -// IP Revision: 5 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -axis_slv_0 your_instance_name ( - .aclk(aclk), // input wire aclk - .aresetn(aresetn), // input wire aresetn - .s_axis_tvalid(s_axis_tvalid), // input wire [0 : 0] s_axis_tvalid - .s_axis_tready(s_axis_tready), // output wire [0 : 0] s_axis_tready - .s_axis_tdata(s_axis_tdata), // input wire [31 : 0] s_axis_tdata - .s_axis_tstrb(s_axis_tstrb), // input wire [3 : 0] s_axis_tstrb - .s_axis_tlast(s_axis_tlast) // input wire [0 : 0] s_axis_tlast -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file axis_slv_0.v when simulating -// the core, axis_slv_0. When compiling the wrapper file, be sure to -// reference the Verilog simulation library. - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axis_slv_0/axis_slv_0.vho b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axis_slv_0/axis_slv_0.vho deleted file mode 100644 index b633a5a..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axis_slv_0/axis_slv_0.vho +++ /dev/null @@ -1,87 +0,0 @@ --- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:axi4stream_vip:1.1 --- IP Revision: 5 - --- The following code must appear in the VHDL architecture header. - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT axis_slv_0 - PORT ( - aclk : IN STD_LOGIC; - aresetn : IN STD_LOGIC; - s_axis_tvalid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); - s_axis_tready : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - s_axis_tstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - s_axis_tlast : IN STD_LOGIC_VECTOR(0 DOWNTO 0) - ); -END COMPONENT; --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : axis_slv_0 - PORT MAP ( - aclk => aclk, - aresetn => aresetn, - s_axis_tvalid => s_axis_tvalid, - s_axis_tready => s_axis_tready, - s_axis_tdata => s_axis_tdata, - s_axis_tstrb => s_axis_tstrb, - s_axis_tlast => s_axis_tlast - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file axis_slv_0.vhd when simulating --- the core, axis_slv_0. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axis_slv_0/axis_slv_0.xci b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axis_slv_0/axis_slv_0.xci deleted file mode 100644 index 6c4cc2c..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axis_slv_0/axis_slv_0.xci +++ /dev/null @@ -1,105 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - axis_slv_0 - - - ACTIVE_LOW - - 100000000 - 0 - 0.000 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 1 - 1 - 1 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - 32 - 0 - 1 - 0 - 2 - 0b00000000000000000000000000010111 - 0 - 0 - axis_slv_0 - 0 - 1 - 0 - 1 - 1 - 1 - 0 - SLAVE - 4 - 0 - 0 - 0 - 0 - virtex7 - - - xc7vx485t - ffg1157 - VERILOG - - MIXED - -1 - - - TRUE - TRUE - IP_Flow - 5 - TRUE - . - - . - 2019.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axis_slv_0/axis_slv_0.xml b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axis_slv_0/axis_slv_0.xml deleted file mode 100644 index 323d46d..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axis_slv_0/axis_slv_0.xml +++ /dev/null @@ -1,1548 +0,0 @@ - - - xilinx.com - customized_ip - axis_slv_0 - 1.0 - - - M_AXIS - - - - - - - TDATA - - - m_axis_tdata - - - - - TDEST - - - m_axis_tdest - - - - - TID - - - m_axis_tid - - - - - TKEEP - - - m_axis_tkeep - - - - - TLAST - - - m_axis_tlast - - - - - TREADY - - - m_axis_tready - - - - - TSTRB - - - m_axis_tstrb - - - - - TUSER - - - m_axis_tuser - - - - - TVALID - - - m_axis_tvalid - - - - - - TDATA_NUM_BYTES - 0 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 0 - - - none - - - - - HAS_TREADY - 0 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 0 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - S_AXIS - - - - - - - TDATA - - - s_axis_tdata - - - - - TDEST - - - s_axis_tdest - - - - - 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- - - false - - - - - - CLOCK - - - - - - - CLK - - - aclk - - - - - - ASSOCIATED_BUSIF - M_AXIS:S_AXIS - - - ASSOCIATED_RESET - aresetn - - - FREQ_HZ - 100000000 - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - - - xilinx_veriloginstantiationtemplate - Verilog Instantiation Template - verilogSource:vivado.xilinx.com:synthesis.template - verilog - - xilinx_veriloginstantiationtemplate_view_fileset - - - - GENtimestamp - Mon May 17 17:06:36 UTC 2021 - - - outputProductCRC - 9:85eb7414 - - - - - xilinx_verilogsynthesis - Verilog Synthesis - verilogSource:vivado.xilinx.com:synthesis - verilog - axi4stream_vip_v1_1_5_top - - xilinx_verilogsynthesis_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset - - - xilinx_verilogsynthesis_view_fileset - - - - GENtimestamp - Mon May 17 17:06:36 UTC 2021 - - - outputProductCRC - 9:85eb7414 - - - - - xilinx_synthesisconstraints - Synthesis Constraints - :vivado.xilinx.com:synthesis.constraints - - xilinx_synthesisconstraints_view_fileset - - - - GENtimestamp - Mon May 17 17:06:36 UTC 2021 - - - outputProductCRC - 9:85eb7414 - - - - - xilinx_verilogsynthesiswrapper - Verilog Synthesis Wrapper - verilogSource:vivado.xilinx.com:synthesis.wrapper - verilog - axis_slv_0 - - xilinx_verilogsynthesiswrapper_view_fileset - - - - GENtimestamp - Mon May 17 17:06:36 UTC 2021 - - - outputProductCRC - 9:85eb7414 - - - - - xilinx_versioninformation - Version Information - :vivado.xilinx.com:docs.versioninfo - axi4stream_vip_v1_1_5_top - - xilinx_versioninformation_view_fileset - - - - GENtimestamp - Mon May 17 17:06:36 UTC 2021 - - - outputProductCRC - 9:85eb7414 - - - - - xilinx_externalfiles - External Files - :vivado.xilinx.com:external.files - - xilinx_externalfiles_view_fileset - - - - GENtimestamp - Mon May 17 17:07:13 UTC 2021 - - - outputProductCRC - 9:85eb7414 - - - - - xilinx_verilogbehavioralsimulation - Verilog Simulation - verilogSource:vivado.xilinx.com:simulation - verilog - axi4stream_vip_v1_1_5_top - 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ACTIVE_HIGH - ACTIVE_LOW - - - choice_pairs_2d96f706 - 0 - 1 - - - - - xilinx_veriloginstantiationtemplate_view_fileset - - axis_slv_0.vho - vhdlTemplate - - - axis_slv_0.veo - verilogTemplate - - - - xilinx_verilogsynthesis_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset - - hdl/axis_infrastructure_v1_1_0.vh - verilogSource - true - axis_infrastructure_v1_1_0 - - - hdl/axis_infrastructure_v1_1_vl_rfs.v - verilogSource - axis_infrastructure_v1_1_0 - - - - - - - - - - - xilinx_verilogsynthesis_view_fileset - - hdl/axi4stream_vip_v1_1_vlsyn_rfs.sv - systemVerilogSource - axi4stream_vip_v1_1_5 - - - - xilinx_synthesisconstraints_view_fileset - - axis_slv_0_ooc.xdc - xdc - USED_IN_implementation - USED_IN_out_of_context - USED_IN_synthesis - - - - xilinx_verilogsynthesiswrapper_view_fileset - - synth/axis_slv_0.sv - systemVerilogSource - xil_defaultlib - - - - xilinx_versioninformation_view_fileset - - doc/axi4stream_vip_v1_1_changelog.txt - text - axi4stream_vip_v1_1_5 - - - - xilinx_externalfiles_view_fileset - - axis_slv_0.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - axis_slv_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - axis_slv_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - axis_slv_0_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - axis_slv_0_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - - xilinx_verilogbehavioralsimulation_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset - - hdl/axis_infrastructure_v1_1_0.vh - verilogSource - USED_IN_ipstatic - true - axis_infrastructure_v1_1_0 - - - hdl/axis_infrastructure_v1_1_vl_rfs.v - verilogSource - USED_IN_ipstatic - axis_infrastructure_v1_1_0 - - - - - - - - - - - xilinx_verilogbehavioralsimulation_view_fileset - - sim/axis_slv_0_pkg.sv - systemVerilogSource - - - hdl/axi4stream_vip_v1_1_vl_rfs.sv - systemVerilogSource - USED_IN_ipstatic - axi4stream_vip_v1_1_5 - - - - xilinx_verilogsimulationwrapper_view_fileset - - sim/axis_slv_0.sv - systemVerilogSource - xil_defaultlib - - - - The AXI4-Stream Verification IP. - - - INTERFACE_MODE - INTERFACE MODE - SLAVE - - - TDATA_NUM_BYTES - TDATA WIDTH(BYTES) - 4 - - - USER_BITS_PER_BYTE - TUSER BITS PER BYTE - 0 - - - - false - - - - - - HAS_TUSER_BITS_PER_BYTE - HAS TUSER_BITS_PER_BYTE - 0 - - - TID_WIDTH - TID WIDTH(BITS) - 0 - - - TDEST_WIDTH - TDEST WIDTH(BITS) - 0 - - - TUSER_WIDTH - TUSER WIDTH(BITS) - 0 - - - HAS_TREADY - ENABLE TREADY - 1 - - - HAS_TSTRB - ENABLE TSTRB - 1 - - - HAS_TKEEP - ENABLE TKEEP - 0 - - - HAS_TLAST - ENABLE TLAST - 1 - - - HAS_ACLKEN - HAS ACLKEN - 0 - - - HAS_ARESETN - HAS ARESETN - 1 - - - Component_Name - axis_slv_0 - - - - - AXI4-Stream Verification IP - - XPM_CDC - - 5 - true - - - - - - - - - - - - - - 2019.1 - - - - - - - - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axis_tproc64x32_x8.v b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axis_tproc64x32_x8.v deleted file mode 100644 index d6e10e6..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/axis_tproc64x32_x8.v +++ /dev/null @@ -1,482 +0,0 @@ -module axis_tproc64x32_x8 -( - /////////////////////// - // s_axi_aclk domain // - /////////////////////// - s_axi_aclk , - s_axi_aresetn , - - // AXI Slave I/F for configuration. - s_axi_awaddr , - s_axi_awprot , - s_axi_awvalid , - s_axi_awready , - - s_axi_wdata , - s_axi_wstrb , - s_axi_wvalid , - s_axi_wready , - - s_axi_bresp , - s_axi_bvalid , - s_axi_bready , - - s_axi_araddr , - s_axi_arprot , - s_axi_arvalid , - s_axi_arready , - - s_axi_rdata , - s_axi_rresp , - s_axi_rvalid , - s_axi_rready , - - // Slave AXIS for writing into Data Memory. - s0_axis_aclk , // For IF only, not connected. - s0_axis_aresetn , // For IF only, not connected. - s0_axis_tdata , - s0_axis_tlast , - s0_axis_tvalid , - s0_axis_tready , - - // Master AXIS 0 to read from Data Memory. - m0_axis_aclk , // For IF only, not connected. - m0_axis_aresetn , // For IF only, not connected. - m0_axis_tdata , - m0_axis_tlast , - m0_axis_tvalid , - m0_axis_tready , - - ///////////////// - // aclk domain // - ///////////////// - aclk , - aresetn , - - // Start/stop. - start , - - // Program Memory Interface. - pmem_addr , - pmem_do , - - // Slave AXIS 0: "read" on tProcessor. - s1_axis_tdata , - s1_axis_tvalid , - s1_axis_tready , - - // Slave AXIS 1: "read" on tProcessor. - s2_axis_tdata , - s2_axis_tvalid , - s2_axis_tready , - - // Slave AXIS 2: "read" on tProcessor. - s3_axis_tdata , - s3_axis_tvalid , - s3_axis_tready , - - // Slave AXIS 3: "read" on tProcessor. - s4_axis_tdata , - s4_axis_tvalid , - s4_axis_tready , - - // Master AXIS 1 for Channel 0. - m1_axis_tdata , - m1_axis_tvalid , - m1_axis_tready , - - // Master AXIS 2 for Channel 1. - m2_axis_tdata , - m2_axis_tvalid , - m2_axis_tready , - - // Master AXIS 3 for Channel 2. - m3_axis_tdata , - m3_axis_tvalid , - m3_axis_tready , - - // Master AXIS 4 for Channel 3. - m4_axis_tdata , - m4_axis_tvalid , - m4_axis_tready , - - // Master AXIS 5 for Channel 4. - m5_axis_tdata , - m5_axis_tvalid , - m5_axis_tready , - - // Master AXIS 6 for Channel 5. - m6_axis_tdata , - m6_axis_tvalid , - m6_axis_tready , - - // Master AXIS 7 for Channel 6. - m7_axis_tdata , - m7_axis_tvalid , - m7_axis_tready , - - // Master AXIS 8 for Channel 7. - m8_axis_tdata , - m8_axis_tvalid , - m8_axis_tready - -); - -// Parameters. -parameter PMEM_N = 16; // Program Memory Depth. -parameter DMEM_N = 10; // Data Memory Depth. - -// Ports. -input s_axi_aclk; -input s_axi_aresetn; -input s0_axis_aclk; -input s0_axis_aresetn; -input m0_axis_aclk; -input m0_axis_aresetn; - -input [31:0] s_axi_awaddr; -input [2:0] s_axi_awprot; -input s_axi_awvalid; -output s_axi_awready; - -input [31:0] s_axi_wdata; -input [3:0] s_axi_wstrb; -input s_axi_wvalid; -output s_axi_wready; - -output [1:0] s_axi_bresp; -output s_axi_bvalid; -input s_axi_bready; - -input [31:0] s_axi_araddr; -input [2:0] s_axi_arprot; -input s_axi_arvalid; -output s_axi_arready; - -output [31:0] s_axi_rdata; -output [1:0] s_axi_rresp; -output s_axi_rvalid; -input s_axi_rready; - -input [31:0] s0_axis_tdata; -input s0_axis_tlast; -input s0_axis_tvalid; -output s0_axis_tready; - -output [31:0] m0_axis_tdata; -output m0_axis_tlast; -output m0_axis_tvalid; -input m0_axis_tready; - -input aclk; -input aresetn; - -input start; - -output [PMEM_N-1:0] pmem_addr; -input [63:0] pmem_do; - -input [63:0] s1_axis_tdata; -input s1_axis_tvalid; -output s1_axis_tready; - -input [63:0] s2_axis_tdata; -input s2_axis_tvalid; -output s2_axis_tready; - -input [63:0] s3_axis_tdata; -input s3_axis_tvalid; -output s3_axis_tready; - -input [63:0] s4_axis_tdata; -input s4_axis_tvalid; -output s4_axis_tready; - -output [159:0] m1_axis_tdata; -output m1_axis_tvalid; -input m1_axis_tready; - -output [159:0] m2_axis_tdata; -output m2_axis_tvalid; -input m2_axis_tready; - -output [159:0] m3_axis_tdata; -output m3_axis_tvalid; -input m3_axis_tready; - -output [159:0] m4_axis_tdata; -output m4_axis_tvalid; -input m4_axis_tready; - -output [159:0] m5_axis_tdata; -output m5_axis_tvalid; -input m5_axis_tready; - -output [159:0] m6_axis_tdata; -output m6_axis_tvalid; -input m6_axis_tready; - -output [159:0] m7_axis_tdata; -output m7_axis_tvalid; -input m7_axis_tready; - -output [159:0] m8_axis_tdata; -output m8_axis_tvalid; -input m8_axis_tready; - -// Internal connections. -// Program memory address. -wire [PMEM_N-1:0] pmem_addr_int; - -// axi_slv_custom -> data_mem -wire busy_int; -wire oper_int; -wire [DMEM_N-1:0] addr_int; -wire [31:0] dwrite_int; -wire [31:0] dread_int; -wire exec_int; -wire exec_ack_int; - -// data_mem -> dmem (port a). -wire dmem_wea; -wire [DMEM_N-1:0] dmem_addra; -wire [31:0] dmem_dia; -wire [31:0] dmem_doa; - -// tProc -> dmem (port b). -wire dmem_web; -wire [DMEM_N-1:0] dmem_addrb; -wire [31:0] dmem_dib; -wire [31:0] dmem_dob; - -// Registers. -wire START_SRC_REG; -wire START_REG; -wire MEM_MODE_REG; -wire MEM_START_REG; -wire [DMEM_N-1:0] MEM_ADDR_REG; -wire [DMEM_N-1:0] MEM_LEN_REG; - -// AXI Slave. -axi_slv_custom - axi_slv_i - ( - // Reset and clock. - .aclk_i (s_axi_aclk ), - .aresetn_i (s_axi_aresetn ), - - // Write Address Channel. - .awaddr_i (s_axi_awaddr ), - .awprot_i (s_axi_awprot ), - .awvalid_i (s_axi_awvalid ), - .awready_o (s_axi_awready ), - - // Write Data Channel. - .wdata_i (s_axi_wdata ), - .wstrb_i (s_axi_wstrb ), - .wvalid_i (s_axi_wvalid ), - .wready_o (s_axi_wready ), - - // Write Response Channel. - .bresp_o (s_axi_bresp ), - .bvalid_o (s_axi_bvalid ), - .bready_i (s_axi_bready ), - - // Read Address Channel. - .araddr_i (s_axi_araddr ), - .arprot_i (s_axi_arprot ), - .arvalid_i (s_axi_arvalid ), - .arready_o (s_axi_arready ), - - // Read Data Channel. - .rdata_o (s_axi_rdata ), - .rresp_o (s_axi_rresp ), - .rvalid_o (s_axi_rvalid ), - .rready_i (s_axi_rready ), - - // Single Access Handshake. - .busy_i (busy_int ), - .oper_o (oper_int ), - .addr_o (addr_int ), - .dwrite_o (dwrite_int ), - .dread_i (dread_int ), - .exec_o (exec_int ), - .exec_ack_i (exec_ack_int ), - - // Registers. - .START_SRC_REG (START_SRC_REG ), - .START_REG (START_REG ), - .MEM_MODE_REG (MEM_MODE_REG ), - .MEM_START_REG (MEM_START_REG ), - .MEM_ADDR_REG (MEM_ADDR_REG ), - .MEM_LEN_REG (MEM_LEN_REG ) -); - -// Data Memory arbiter. -data_mem - #( - .N (DMEM_N ), - .B (32 ) - ) - data_mem_i - ( - // Reset and clock. - .aclk_i (s_axi_aclk ), - .aresetn_i (s_axi_aresetn ), - - // Single Access Handshake. - .busy_o (busy_int ), - .oper_i (oper_int ), - .addr_i (addr_int ), - .din_i (dwrite_int ), - .dout_o (dread_int ), - .exec_i (exec_int ), - .exec_ack_o (exec_ack_int ), - - // Memory interface. - .mem_we_o (dmem_wea ), - .mem_di_o (dmem_dia ), - .mem_do_i (dmem_doa ), - .mem_addr_o (dmem_addra ), - - // AXIS Slave for receiving data. - .s_axis_tdata_i (s0_axis_tdata ), - .s_axis_tlast_i (s0_axis_tlast ), - .s_axis_tvalid_i (s0_axis_tvalid ), - .s_axis_tready_o (s0_axis_tready ), - - // AXIS Master for sending data. - .m_axis_tdata_o (m0_axis_tdata ), - .m_axis_tlast_o (m0_axis_tlast ), - .m_axis_tvalid_o (m0_axis_tvalid ), - .m_axis_tready_i (m0_axis_tready ), - - // Registers. - .MODE_REG (MEM_MODE_REG ), - .START_REG (MEM_START_REG ), - .ADDR_REG (MEM_ADDR_REG ), - .LEN_REG (MEM_LEN_REG ) -); - -// Data memory. -bram_dp - #( - // Memory address size. - .N (DMEM_N ), - // Data width. - .B (32 ) - ) - dmem_i - ( - .clka (s_axi_aclk ), - .clkb (aclk ), - .ena (1'b1 ), - .enb (1'b1 ), - .wea (dmem_wea ), - .web (dmem_web ), - .addra (dmem_addra ), - .addrb (dmem_addrb ), - .dia (dmem_dia ), - .dib (dmem_dib ), - .doa (dmem_doa ), - .dob (dmem_dob ) - ); - -// tProcessor: 64-bit, 32-bit registers, 8 channels. -tproc64x32_x8 - #( - // Program memory depth. - .N (PMEM_N ), - - // Data memory depth. - .M (DMEM_N ) - ) - tproc_i - ( - // Clock and reset. - .clk (aclk ), - .rstn (aresetn ), - - // Start/stop. - .start (start ), - - // Program Memory Interface. - .pmem_addr (pmem_addr_int ), - .pmem_do (pmem_do ), - - // Data Memory Interface. - .dmem_we (dmem_web ), - .dmem_addr (dmem_addrb ), - .dmem_di (dmem_dib ), - .dmem_do (dmem_dob ), - - // Slave AXIS 0 for Input data. - .s0_axis_tdata (s1_axis_tdata ), - .s0_axis_tvalid (s1_axis_tvalid ), - .s0_axis_tready (s1_axis_tready ), - - // Slave AXIS 1 for Input data. - .s1_axis_tdata (s2_axis_tdata ), - .s1_axis_tvalid (s2_axis_tvalid ), - .s1_axis_tready (s2_axis_tready ), - - // Slave AXIS 2 for Input data. - .s2_axis_tdata (s3_axis_tdata ), - .s2_axis_tvalid (s3_axis_tvalid ), - .s2_axis_tready (s3_axis_tready ), - - // Slave AXIS 3 for Input data. - .s3_axis_tdata (s4_axis_tdata ), - .s3_axis_tvalid (s4_axis_tvalid ), - .s3_axis_tready (s4_axis_tready ), - - // Master AXIS 0 for Output data. - .m0_axis_tdata (m1_axis_tdata ), - .m0_axis_tvalid (m1_axis_tvalid ), - .m0_axis_tready (m1_axis_tready ), - - // Master AXIS 1 for Output data. - .m1_axis_tdata (m2_axis_tdata ), - .m1_axis_tvalid (m2_axis_tvalid ), - .m1_axis_tready (m2_axis_tready ), - - // Master AXIS 2 for Output data. - .m2_axis_tdata (m3_axis_tdata ), - .m2_axis_tvalid (m3_axis_tvalid ), - .m2_axis_tready (m3_axis_tready ), - - // Master AXIS 3 for Output data. - .m3_axis_tdata (m4_axis_tdata ), - .m3_axis_tvalid (m4_axis_tvalid ), - .m3_axis_tready (m4_axis_tready ), - - // Master AXIS 4 for Output data. - .m4_axis_tdata (m5_axis_tdata ), - .m4_axis_tvalid (m5_axis_tvalid ), - .m4_axis_tready (m5_axis_tready ), - - // Master AXIS 5 for Output data. - .m5_axis_tdata (m6_axis_tdata ), - .m5_axis_tvalid (m6_axis_tvalid ), - .m5_axis_tready (m6_axis_tready ), - - // Master AXIS 6 for Output data. - .m6_axis_tdata (m7_axis_tdata ), - .m6_axis_tvalid (m7_axis_tvalid ), - .m6_axis_tready (m7_axis_tready ), - - // Master AXIS 7 for Output data. - .m7_axis_tdata (m8_axis_tdata ), - .m7_axis_tvalid (m8_axis_tvalid ), - .m7_axis_tready (m8_axis_tready ), - - // Registers. - .START_SRC_REG (START_SRC_REG ), - .START_REG (START_REG ) -); - -// Assign outputs. -assign pmem_addr = {pmem_addr_int[PMEM_N-4:0],3'b000}; // Multiply address by 8 to convert 64-bit address to 8-bit address. - -endmodule - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/bram.v b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/bram.v deleted file mode 100644 index 018317e..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/bram.v +++ /dev/null @@ -1,33 +0,0 @@ -module bram (clk,ena,wea,addra,dia,doa); - -// Memory address size. -parameter N = 16; -// Data width. -parameter B = 16; - -input clk; -input ena; -input wea; -input [N-1:0] addra; -input [B-1:0] dia; -output [B-1:0] doa; - -// Ram type. -reg [B-1:0] RAM [0:2**N-1]; -reg [B-1:0] doa; - -always @(posedge clk) -begin - if (ena) - begin - if (wea) begin - RAM[addra] <= dia; - end - else begin - doa <= RAM[addra]; - end - end -end - -endmodule - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/bram.vhd b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/bram.vhd deleted file mode 100644 index c03c6c3..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/bram.vhd +++ /dev/null @@ -1,51 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -entity bram is - Generic ( - -- Memory address size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port ( - clk : in std_logic; - ena : in std_logic; - wea : in std_logic; - addra : in std_logic_vector (N-1 downto 0); - dia : in std_logic_vector (B-1 downto 0); - doa : out std_logic_vector (B-1 downto 0) - ); -end bram; - -architecture rtl of bram is - --- Ram type. -type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); -shared variable RAM : ram_type; - -begin - -process (clk) -begin - if (clk'event and clk = '1') then - if (ena = '1') then - if (wea = '1') then - RAM(conv_integer(addra)) := dia; - end if; - end if; - end if; -end process; - -process (clk) -begin - if (clk'event and clk = '1') then - if (ena = '1') then - doa <= RAM(conv_integer(addra)); - end if; - end if; -end process; - -end rtl; - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/cond.vhd b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/cond.vhd deleted file mode 100644 index 5804663..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/cond.vhd +++ /dev/null @@ -1,94 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - --- Conditional block. - --- It operates on two inputs. --- Operations are: --- 0000 : din_a > din_b --- 0001 : din_a >= din_b --- 0010 : din_a < din_b --- 0011 : din_a <= din_b --- 0100 : din_a == din_b --- 0101 : din_a != din_b - --- Output flag is 1 when condition is true. Otherwise is 0. --- Latency is 1 clock. - -entity cond is - Generic ( - -- Data width. - B : Integer := 16 - ); - Port ( - -- Clock and reset. - clk : in std_logic; - rstn : in std_logic; - - -- Input operands. - din_a : in std_logic_vector (B-1 downto 0); - din_b : in std_logic_vector (B-1 downto 0); - - -- Operation. - op : in std_logic_vector (3 downto 0); - - -- Flag. - flag : out std_logic - ); -end cond; - -architecture rtl of cond is - --- Input registers. -signal din_a_r : signed (B-1 downto 0); -signal din_b_r : signed (B-1 downto 0); -signal op_r : std_logic_vector (3 downto 0); - --- Flags for conditions. -signal cond_0_i : std_logic; -- > -signal cond_1_i : std_logic; -- >= -signal cond_2_i : std_logic; -- < -signal cond_3_i : std_logic; -- <= -signal cond_4_i : std_logic; -- == -signal cond_5_i : std_logic; -- != - -begin - --- Registers. -process (clk) -begin - if ( rising_edge(clk) ) then - if ( rstn = '0' ) then - -- Input registers. - din_a_r <= (others => '0'); - din_b_r <= (others => '0'); - op_r <= (others => '0'); - else - -- Input registers. - din_a_r <= signed(din_a); - din_b_r <= signed(din_b); - op_r <= op; - end if; - end if; -end process; - --- Flags for conditions. -cond_0_i <= '1' when din_a_r > din_b_r else '0' ; -- > -cond_1_i <= cond_0_i or cond_4_i ; -- >= -cond_2_i <= '1' when din_a_r < din_b_r else '0' ; -- < -cond_3_i <= cond_2_i or cond_4_i ; -- <= -cond_4_i <= '1' when din_a_r = din_b_r else '0' ; -- == -cond_5_i <= not(cond_4_i) ; -- != - --- Mux for output. -flag <= cond_0_i when op_r = "0000" else - cond_1_i when op_r = "0001" else - cond_2_i when op_r = "0010" else - cond_3_i when op_r = "0011" else - cond_4_i when op_r = "0100" else - cond_5_i when op_r = "0101" else - '0'; - -end rtl; - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/ctrl.sv b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/ctrl.sv deleted file mode 100644 index b07dee5..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/ctrl.sv +++ /dev/null @@ -1,1093 +0,0 @@ -/* tProcessor control state machine. -This version works with 32-bit registers. To avoid modifying the whole instruction structure, -immediate value from instruction is 31 bits. It's sign-extended to get the 32-bit register -value before operating with it. It applies to I-Type instructions only. -*/ -// -// Instructions: -// -// ############## -// ### I-Type ### -// ############## -// -// I-Type: immediate type. Three registers and an immediate value. -// -// |----------|----------|----------|----------|----------|----------|----------|---------| -// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 0 | -// |----------|----------|----------|----------|----------|----------|----------|---------| -// | opcode | page | channel | oper | ra | rb | rc | imm | -// |----------|----------|----------|----------|----------|----------|----------|---------| -// -// pushi p, $ra, $rb, imm : push the content of register $ra into the stack. Load register -// $rb with imm value. Registers $ra and $rb can be the same. $p indicates the page of the -// regfile. -// |----------|----------|----------|----------|----------|----------|----------|---------| -// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 0 | -// |----------|----------|----------|----------|----------|----------|----------|---------| -// | 00010000 | page | xxxxxxx | xxxx | rb | ra | xx | imm | -// |----------|----------|----------|----------|----------|----------|----------|---------| -// -// popi $p, $r : pop the content of the stack into register $r. -// |----------|----------|----------|----------|----------|----------|----------|---------| -// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 0 | -// |----------|----------|----------|----------|----------|----------|----------|---------| -// | 00010001 | page | xxxxxxx | xxxx | r | xx | xx | xxx | -// |----------|----------|----------|----------|----------|----------|----------|---------| -// -// mathi $p, $ra, $rb oper imm : operation as $ra = $rb oper imm. -// oper : -// 1000 : $rb + imm -// 1001 : $rb - imm -// 1010 : $rb * imm -// |----------|----------|----------|----------|----------|----------|----------|---------| -// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 0 | -// |----------|----------|----------|----------|----------|----------|----------|---------| -// | 00010010 | page | xxxxxxx | oper | ra | rb | xx | imm | -// |----------|----------|----------|----------|----------|----------|----------|---------| -// -// seti ch, p, $r, t : set value on register $r at time t for channel ch. -// |----------|----------|----------|----------|----------|----------|----------|---------| -// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 0 | -// |----------|----------|----------|----------|----------|----------|----------|---------| -// | 00010011 | page | channel | xxxx | xx | r | xx | t | -// |----------|----------|----------|----------|----------|----------|----------|---------| -// -// synci t : sync master clock to t for upcoming instructions. -// |----------|----------|----------|----------|----------|----------|----------|---------| -// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 0 | -// |----------|----------|----------|----------|----------|----------|----------|---------| -// | 00010100 | xxxx | xxxxxxx | xxxx | xx | xx | xx | t | -// |----------|----------|----------|----------|----------|----------|----------|---------| -// -// waiti ch, t : wait until master clock = t on channel ch. -// |----------|----------|----------|----------|----------|----------|----------|---------| -// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 0 | -// |----------|----------|----------|----------|----------|----------|----------|---------| -// | 00010101 | xxxx | channel | xxxx | xx | xx | xx | t | -// |----------|----------|----------|----------|----------|----------|----------|---------| -// -// bitwi p, $ra, $rb oper imm : perform the bit-wise operation $rb oper imm and write the result -// into register $ra. -// oper : -// 0000 : $rb & imm (and) -// 0001 : $rb | imm (or) -// 0010 : $rb ^ imm (xor) -// 0011 : ~imm (not) -// 0100 : $rb << imm (left shift) -// 0101 : $rb >> imm (right shift) -// |----------|----------|----------|----------|----------|----------|----------|---------| -// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 0 | -// |----------|----------|----------|----------|----------|----------|----------|---------| -// | 00010110 | page | xxxxxxx | oper | ra | rb | xx | imm | -// |----------|----------|----------|----------|----------|----------|----------|---------| -// -// NOTE: the not operation operates on a single operand. The syntax is slightly different: -// bitwi p, $ra, ~imm -// -// memri p, $r, imm : read memory at address imm and write value into register: $r = mem[imm]. -// |----------|----------|----------|----------|----------|----------|----------|---------| -// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 0 | -// |----------|----------|----------|----------|----------|----------|----------|---------| -// | 00010111 | page | xxxxxxx | xxxx | r | xx | xx | imm | -// |----------|----------|----------|----------|----------|----------|----------|---------| -// -// memwi p, $r, imm : write register contents into address imm of memory: mem[imm] = $r. -// |----------|----------|----------|----------|----------|----------|----------|---------| -// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 0 | -// |----------|----------|----------|----------|----------|----------|----------|---------| -// | 00011000 | page | xxxxxxx | xxxx | xx | xx | r | imm | -// |----------|----------|----------|----------|----------|----------|----------|---------| -// -// regwi p, $r, imm : write imm value into register. -// |----------|----------|----------|----------|----------|----------|----------|---------| -// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 0 | -// |----------|----------|----------|----------|----------|----------|----------|---------| -// | 00011001 | page | xxxxxxx | xxxx | r | xx | xx | imm | -// |----------|----------|----------|----------|----------|----------|----------|---------| -// -// setbi ch, p, $r, t : set value on register $r at time t for channel ch (blocking). -// |----------|----------|----------|----------|----------|----------|----------|---------| -// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 0 | -// |----------|----------|----------|----------|----------|----------|----------|---------| -// | 00011010 | page | channel | xxxx | xx | r | xx | t | -// |----------|----------|----------|----------|----------|----------|----------|---------| -// -// ############## -// ### J-Type ### -// ############## -// -// J-Type: jump type. Three registers and an address for jump. -// -// |----------|----------|----------|----------|----------|----------|----------|----------|---------| -// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 16 | 15 .. 0 | -// |----------|----------|----------|----------|----------|----------|----------|----------|---------| -// | opcode | page | xxxxxxx | oper | ra | rb | rc | xxx | addr | -// |----------|----------|----------|----------|----------|----------|----------|----------|---------| -// -// loopnz $p, $r, addr : jump to address addr if $r is not equal to zero and decrement register. -// If $r is equal to zero, continue with next instruction. -// |----------|----------|----------|----------|----------|----------|----------|----------|---------| -// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 16 | 15 .. 0 | -// |----------|----------|----------|----------|----------|----------|----------|----------|---------| -// | 00110000 | page | xxxxxxx | 1000 | r | r | xx | xxx | addr | -// |----------|----------|----------|----------|----------|----------|----------|----------|---------| -// -// condj p, $ra oper $rb, @label : jump to address @label if condition is true. Operation is defined as: -// oper : -// 0000 : $ra > $rb -// 0001 : $ra >= $rb -// 0010 : $ra < $rb -// 0011 : $ra <= $rb -// 0100 : $ra == $rb -// 0101 : $ra != $rb -// |----------|----------|----------|----------|----------|----------|----------|----------|---------| -// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 16 | 15 .. 0 | -// |----------|----------|----------|----------|----------|----------|----------|----------|---------| -// | 00110001 | page | xxxxxxx | oper | xx | ra | rb | xxx | addr | -// |----------|----------|----------|----------|----------|----------|----------|----------|---------| -// -// end : jump to END_ST to finish the execution of the program. -// |----------|----------|----------|----------|----------|----------|----------|----------|---------| -// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 16 | 15 .. 0 | -// |----------|----------|----------|----------|----------|----------|----------|----------|---------| -// | 00111111 | xxxx | xxxxxxx | xxxx | xx | xx | xx | xxx | xxxx | -// |----------|----------|----------|----------|----------|----------|----------|----------|---------| -// - -// ############## -// ### R-Type ### -// ############## -// -// R-Type: register type. 8 registers: 1 for writing, 7 for reading. -// -// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| -// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 26 | 25 .. 21 | 20 .. 16 | 15 .. 11 | 10 .. 6 | 5 .. 0 | -// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| -// | opcode | page | channel | oper | ra | rb | rc | rd | re | rf | rg | rh | xxx | -// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| -// -// add $p, $ra, $rb oper $rc : apply operation on registers $rb and $rc and store the result into register $ra. Registers are on page $p. -// oper : -// 1000 : $rb + $rc -// 1001 : $rb - $rc -// 1010 : $rb * $rc -// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| -// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 26 | 25 .. 21 | 20 .. 16 | 15 .. 11 | 10 .. 6 | 5 .. 0 | -// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| -// | 01010000 | page | xxxxxxx | oper | ra | rb | rc | xx | xx | xx | xx | xx | xxx | -// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| -// -// set ch, p, $ra, $rb, $rc, $rd, $re, $rt : set value on {$re,$rd,$rc,$rb,$ra} at time $rt for chhanel ch. -// $ra is the lower 32 bits and $re are the 32 most significant bits. -// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| -// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 26 | 25 .. 21 | 20 .. 16 | 15 .. 11 | 10 .. 6 | 5 .. 0 | -// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| -// | 01010001 | page | channel | xxxx | xx | ra | rt | rb | rc | rd | re | xx | xxx | -// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| -// -// sync $p, $r : sync master clock to $r for upcoming instructions. -// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| -// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 26 | 25 .. 21 | 20 .. 16 | 15 .. 11 | 10 .. 6 | 5 .. 0 | -// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| -// | 01010010 | page | xxxxxxx | xxxx | xx | xx | r | xx | xx | xx | xx | xx | xxx | -// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| -// -// read ch, $p, oper $r : read input data port "channel" (s?_axis) into register $r. -// oper: -// 1010 : upper 32 bits. -// else : lower 32 bits. -// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| -// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 26 | 25 .. 21 | 20 .. 16 | 15 .. 11 | 10 .. 6 | 5 .. 0 | -// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| -// | 01010011 | page | channel | oper | r | xx | xx | xx | xx | xx | xx | xx | xxx | -// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| -// Example: -// read 0, 2, upper $3: read upper 32 bits of channel 0 into register 3 on page 2. -// -// wait ch, p, $r : wait until master clock reaches time specified by register $r on channel ch. -// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| -// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 26 | 25 .. 21 | 20 .. 16 | 15 .. 11 | 10 .. 6 | 5 .. 0 | -// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| -// | 01010100 | page | channel | xxxx | xx | xx | r | xx | xx | xx | xx | xx | xxx | -// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| -// -// bitw p, $ra, $rb oper $rc : perform the bit-wise operation $rb oper $rc and write the result into register $ra. -// oper : -// 0000 : $rb & $rc (and) -// 0001 : $rb | $rc (or) -// 0010 : $rb ^ $rc (xor) -// 0011 : ~$rc (not) -// 0100 : $rb << $rc (left shift) -// 0101 : $rb >> $rc (right shift) -// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| -// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 26 | 25 .. 21 | 20 .. 16 | 15 .. 11 | 10 .. 6 | 5 .. 0 | -// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| -// | 01010101 | page | xxxxxxx | oper | ra | rb | rc | xx | xx | xx | xx | xx | xxx | -// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| -// -// NOTE: the not operation operates on a single operand. The syntax is slightly different: -// bitw p, $ra, ~$rc -// -// memr p, $ra, $rb : read memory at address $rb and write value into register $ra: $ra = mem[$rb]. -// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| -// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 26 | 25 .. 21 | 20 .. 16 | 15 .. 11 | 10 .. 6 | 5 .. 0 | -// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| -// | 01010110 | page | xxxxxxx | xxxx | ra | rb | xx | xx | xx | xx | xx | xx | xxx | -// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| -// -// memw p, $ra, $rb : write value of register $ra into memory at address $rb: $mem[$rb] = $ra. -// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| -// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 26 | 25 .. 21 | 20 .. 16 | 15 .. 11 | 10 .. 6 | 5 .. 0 | -// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| -// | 01010111 | page | xxxxxxx | xxxx | xx | rb | ra | xx | xx | xx | xx | xx | xxx | -// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| -// -// setb ch, p, $ra, $rb, $rc, $rd, $re, $rt : set value on {$re,$rd,$rc,$rb,$ra} at time $rt for chhanel ch. -// $ra is the lower 32 bits and $re are the 32 most significant bits (blocking). -// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| -// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 26 | 25 .. 21 | 20 .. 16 | 15 .. 11 | 10 .. 6 | 5 .. 0 | -// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| -// | 01011000 | page | channel | xxxx | xx | ra | rt | rb | rc | rd | re | xx | xxx | -// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| -// - -module ctrl - ( - // Clock and reset. - clk , - rstn , - - // Start/stop. - start , - - // Opcode. - opcode , - - // IR control. - ir_en , - - // Pogram counter out (jump instructions). - pc_src , - pc_en , - pc_rst , - - // Alu control. - alu_src_b , - alu_zero , - - // Alu Time control. - alut_src_b , - - // Register write control. - reg_src , - reg_wen , - - // Conditional control. - cond_flag , - - // Stack control. - stack_en , - stack_op , - stack_full , - stack_empty , - - // Fifo time control. - fifo_wr_en , - fifo_full , - - // Data Memory control. - dmem_we , - addr_src , - - // Master clock control. - t_en , - t_sync_en , - - // Wait handshake. - waitt , - waitt_ack - ); - -// Ports. -input clk; -input rstn; - -input start; - -input [7:0] opcode; - -output ir_en; - -output pc_src; -output pc_en; -output pc_rst; - -output [1:0] alu_src_b; -input alu_zero; - -output alut_src_b; - -output [2:0] reg_src; -output reg_wen; - -input cond_flag; - -output stack_en; -output stack_op; -input stack_full; -input stack_empty; - -output fifo_wr_en; -input fifo_full; - -output dmem_we; -output addr_src; - -output t_en; -output t_sync_en; - -input waitt; -output waitt_ack; - -// States. -typedef enum { INIT_ST , - PC_RST_ST , - START_MC_ST , - FETCH_ST , - DECODE_ST , - MATHI0_ST , - MATHI1_ST , - MATHI2_ST , - MATHI3_ST , - BITWI0_ST , - BITWI1_ST , - BITWI2_ST , - BITWI3_ST , - MATH0_ST , - MATH1_ST , - MATH2_ST , - MATH3_ST , - BITW0_ST , - BITW1_ST , - BITW2_ST , - BITW3_ST , - PUSHI0_ST , - POPI0_ST , - POPI1_ST , - POPI2_ST , - LOOPNZ0_ST , - LOOPNZ1_ST , - LOOPNZ2_ST , - LOOPNZ3_ST , - SETI0_ST , - SETI1_ST , - SET0_ST , - SET1_ST , - SYNCI0_ST , - SYNCI1_ST , - SYNC0_ST , - SYNC1_ST , - CONDJ0_ST , - CONDJ1_ST , - CONDJ2_ST , - READ0_ST , - MEMRI0_ST , - MEMRI1_ST , - MEMRI2_ST , - MEMR0_ST , - MEMR1_ST , - MEMR2_ST , - MEMWI0_ST , - MEMW0_ST , - REGWI0_ST , - WAITI0_ST , - WAITI1_ST , - WAIT0_ST , - WAIT1_ST , - WAIT_ACK_ST , - ERR_INSTR_ST, - ERR_STACK_ST, - END_ST - } state_t; - -(* fsm_encoding = "one_hot" *) state_t state; - -reg state_loopnz; -reg state_condj; - -// IR control. -reg ir_en_i; - -// Pogram counter out (jump instructions). -reg pc_src_i; // 0: pc + 1, 1: jump. -reg pc_en_i; -reg pc_rst_i; - -// Alu control. -reg [1:0] alu_src_b_i; // 00: imm, 01: D1, 10: -1. - -// ALU Time control. -reg alut_src_b_i; // 0: D1, 1: imm. - -// Register write control. -reg [2:0] reg_src_i; // 000: imm, 001: Alu out, 010: Stack Out, 011: Input Port (s_axis), 100: memory. -reg reg_wen_i; - -// Stack control. -reg stack_en_i; -reg stack_op_i; // 0: pop, 1: push. - -// Fifo Time control. -reg fifo_wr_en_i; - -// Data memory control. -reg dmem_we_i; -reg addr_src_i; // 0: imm, 1: reg. - -// Master clock control. -reg t_en_i; -reg t_sync_en_i; - -// Wait handshake. -reg waitt_ack_i; - -// Registers. -always @(posedge clk) begin - if (~rstn) begin - // State register. - state <= INIT_ST; - end - else begin - // State register. - case (state) - INIT_ST: - if (start) - state <= PC_RST_ST; - - PC_RST_ST: - state <= START_MC_ST; - - START_MC_ST: - state <= FETCH_ST; - - FETCH_ST: - state <= DECODE_ST; - - DECODE_ST: - // pushi - if ( opcode == 8'b00010000 ) - state <= PUSHI0_ST; - - // popi - else if ( opcode == 8'b00010001 ) - state <= POPI0_ST; - - // mathi - else if ( opcode == 8'b00010010 ) - state <= MATHI0_ST; - - // seti/setbi - else if ( opcode == 8'b00010011 || opcode == 8'b00011010 ) - state <= SETI0_ST; - - // synci - else if ( opcode == 8'b00010100 ) - state <= SYNCI0_ST; - - // waiti - else if ( opcode == 8'b00010101 ) - state <= WAITI0_ST; - - // bitwi - else if ( opcode == 8'b00010110 ) - state <= BITWI0_ST; - - // memri - else if ( opcode == 8'b00010111 ) - state <= MEMRI0_ST; - - // memwi - else if ( opcode == 8'b00011000 ) - state <= MEMWI0_ST; - - // regwi - else if ( opcode == 8'b00011001 ) - state <= REGWI0_ST; - - // loopnz - else if ( opcode == 8'b00110000 ) - state <= LOOPNZ0_ST; - - // condj - else if ( opcode == 8'b00110001 ) - state <= CONDJ0_ST; - - // end - else if ( opcode == 8'b00111111 ) - state <= END_ST; - - // math - else if ( opcode == 8'b01010000 ) - state <= MATH0_ST; - - // set/setb - else if ( opcode == 8'b01010001 || opcode == 8'b01011000 ) - state <= SET0_ST; - - // sync - else if ( opcode == 8'b01010010 ) - state <= SYNC0_ST; - - // read - else if ( opcode == 8'b01010011 ) - state <= READ0_ST; - - // wait - else if ( opcode == 8'b01010100 ) - state <= WAIT0_ST; - - // bitw - else if ( opcode == 8'b01010101 ) - state <= BITW0_ST; - - // memr - else if ( opcode == 8'b01010110 ) - state <= MEMR0_ST; - - // memw - else if ( opcode == 8'b01010111 ) - state <= MEMW0_ST; - - // Instruction not recognized. - else - state <= ERR_INSTR_ST; - - MATHI0_ST: - state <= MATHI1_ST; - - MATHI1_ST: - state <= MATHI2_ST; - - MATHI2_ST: - state <= MATHI3_ST; - - MATHI3_ST: - state <= DECODE_ST; - - BITWI0_ST: - state <= BITWI1_ST; - - BITWI1_ST: - state <= BITWI2_ST; - - BITWI2_ST: - state <= BITWI3_ST; - - BITWI3_ST: - state <= DECODE_ST; - - MATH0_ST: - state <= MATH1_ST; - - MATH1_ST: - state <= MATH2_ST; - - MATH2_ST: - state <= MATH3_ST; - - MATH3_ST: - state <= DECODE_ST; - - BITW0_ST: - state <= BITW1_ST; - - BITW1_ST: - state <= BITW2_ST; - - BITW2_ST: - state <= BITW3_ST; - - BITW3_ST: - state <= DECODE_ST; - - PUSHI0_ST: - if (stack_full) - state <= ERR_STACK_ST; - else - state <= DECODE_ST; - - POPI0_ST: - if (stack_empty) - state <= ERR_STACK_ST; - else - state <= POPI1_ST; - - POPI1_ST: - state <= POPI2_ST; - - POPI2_ST: - state <= DECODE_ST; - - LOOPNZ0_ST: - if (alu_zero) - // If zero, skip to next instruction. - state <= FETCH_ST; - else - // If not zero, jump to address. - state <= LOOPNZ1_ST; - - LOOPNZ1_ST: - state <= LOOPNZ2_ST; - - LOOPNZ2_ST: - state <= LOOPNZ3_ST; - - LOOPNZ3_ST: - state <= FETCH_ST; - - SETI0_ST: - state <= SETI1_ST; - - SETI1_ST: - if (~fifo_full) - state <= FETCH_ST; - - SET0_ST: - state <= SET1_ST; - - SET1_ST: - if (~fifo_full) - state <= FETCH_ST; - - SYNCI0_ST: - state <= SYNCI1_ST; - - SYNCI1_ST: - state <= DECODE_ST; - - SYNC0_ST: - state <= SYNC1_ST; - - SYNC1_ST: - state <= DECODE_ST; - - CONDJ0_ST: - state <= CONDJ1_ST; - - CONDJ1_ST: - if (cond_flag) - // Jump. - state <= CONDJ2_ST; - else - // Continue without jump. - state <= FETCH_ST; - - CONDJ2_ST: - state <= FETCH_ST; - - READ0_ST: - state <= DECODE_ST; - - MEMRI0_ST: - state <= MEMRI1_ST; - - MEMRI1_ST: - state <= MEMRI2_ST; - - MEMRI2_ST: - state <= DECODE_ST; - - MEMR0_ST: - state <= MEMR1_ST; - - MEMR1_ST: - state <= MEMR2_ST; - - MEMR2_ST: - state <= DECODE_ST; - - MEMWI0_ST: - state <= DECODE_ST; - - MEMW0_ST: - state <= DECODE_ST; - - REGWI0_ST: - state <= DECODE_ST; - - WAITI0_ST: - state <= WAITI1_ST; - - WAITI1_ST: - if (~fifo_full) - state <= WAIT_ACK_ST; - - WAIT0_ST: - state <= WAIT1_ST; - - WAIT1_ST: - if (~fifo_full) - state <= WAIT_ACK_ST; - - WAIT_ACK_ST: - if (waitt) - state <= FETCH_ST; - - ERR_INSTR_ST: - state <= END_ST; - - ERR_STACK_ST: - state <= END_ST; - - END_ST: - if (~start) - state <= INIT_ST; - endcase - end -end - -// FSM outputs. -always_comb begin - // Default. - state_loopnz = 1'b0; - state_condj = 1'b0; - ir_en_i = 1'b0; - pc_src_i = 1'b0; - pc_en_i = 1'b0; - pc_rst_i = 1'b0; - alu_src_b_i = 2'b00; - alut_src_b_i = 1'b0; - reg_src_i = 3'b000; - reg_wen_i = 1'b0; - stack_en_i = 1'b0; - stack_op_i = 1'b0; - fifo_wr_en_i = 1'b0; - dmem_we_i = 1'b0; - addr_src_i = 1'b0; - t_en_i = 1'b1; - t_sync_en_i = 1'b0; - waitt_ack_i = 1'b0; - - case (state) - //INIT_ST: - - PC_RST_ST: - pc_rst_i = 1'b1; - - START_MC_ST: - t_en_i = 1'b0; - - FETCH_ST: begin - ir_en_i = 1'b1; - pc_src_i = 1'b0; // pc + 1. - pc_en_i = 1'b1; - end - - //DECODE_ST: - - MATHI0_ST: - alu_src_b_i = 2'b00; // imm. - - MATHI1_ST: - alu_src_b_i = 2'b00; // imm. - - MATHI2_ST: - alu_src_b_i = 2'b00; // imm. - - MATHI3_ST: begin - ir_en_i = 1'b1; - pc_src_i = 1'b0; // pc + 1. - pc_en_i = 1'b1; - reg_src_i = 3'b001; // Alu out. - reg_wen_i = 1'b1; - end - - BITWI0_ST: - alu_src_b_i = 2'b00; // imm. - - BITWI1_ST: - alu_src_b_i = 2'b00; // imm. - - BITWI2_ST: - alu_src_b_i = 2'b00; // imm. - - BITWI3_ST: begin - ir_en_i = 1'b1; - pc_src_i = 1'b0; // pc + 1. - pc_en_i = 1'b1; - reg_src_i = 3'b001; // Alu out. - reg_wen_i = 1'b1; - end - - MATH0_ST: - alu_src_b_i = 2'b01; // D1. - - MATH1_ST: - alu_src_b_i = 2'b01; // D1. - - MATH2_ST: - alu_src_b_i = 2'b01; // D1. - - MATH3_ST: begin - ir_en_i = 1'b1; - pc_src_i = 1'b0; // pc + 1. - pc_en_i = 1'b1; - reg_src_i = 3'b001; // Alu out. - reg_wen_i = 1'b1; - end - - BITW0_ST: - alu_src_b_i = 2'b01; // D1. - - BITW1_ST: - alu_src_b_i = 2'b01; // D1. - - BITW2_ST: - alu_src_b_i = 2'b01; // D1. - - BITW3_ST: begin - ir_en_i = 1'b1; - pc_src_i = 1'b0; // pc + 1. - pc_en_i = 1'b1; - reg_src_i = 3'b001; // Alu out. - reg_wen_i = 1'b1; - end - - PUSHI0_ST: begin - ir_en_i = 1'b1; - pc_src_i = 1'b0; // pc + 1. - pc_en_i = 1'b1; - reg_src_i = 3'b000; // imm. - reg_wen_i = 1'b1; - stack_en_i = 1'b1; - stack_op_i = 1'b1; // push. - end - - POPI0_ST: begin - stack_en_i = 1'b1; - stack_op_i = 1'b0; // pop. - end - - POPI1_ST: begin - reg_src_i = 3'b010; // Stack Out. - end - - POPI2_ST: begin - ir_en_i = 1'b1; - pc_src_i = 1'b0; // pc + 1. - pc_en_i = 1'b1; - reg_src_i = 3'b010; // Stack Out. - reg_wen_i = 1'b1; - end - - LOOPNZ0_ST: begin - state_loopnz = 1'b1; - pc_src_i = 1'b1; // jump. - pc_en_i = 1'b1; - alu_src_b_i = 2'b10; // -1. - end - - LOOPNZ1_ST: begin - state_loopnz = 1'b1; - pc_src_i = 1'b1; // jump. - pc_en_i = 1'b1; - alu_src_b_i = 2'b10; // -1. - end - - LOOPNZ2_ST: begin - state_loopnz = 1'b1; - pc_src_i = 1'b1; // jump. - pc_en_i = 1'b1; - alu_src_b_i = 2'b10; // -1. - end - - LOOPNZ3_ST: begin - reg_src_i = 3'b001; // ALU out reg. - reg_wen_i = 1'b1; - end - - SETI0_ST: - alut_src_b_i = 1'b1; - - SETI1_ST: begin - alut_src_b_i = 1'b1; - fifo_wr_en_i = 1'b1; - end - - SET0_ST: - alut_src_b_i = 1'b0; - - SET1_ST: begin - alut_src_b_i = 1'b0; - fifo_wr_en_i = 1'b1; - end - - SYNCI0_ST: - alut_src_b_i = 1'b1; - - SYNCI1_ST: begin - ir_en_i = 1'b1; - pc_src_i = 1'b0; // pc + 1. - pc_en_i = 1'b1; - alut_src_b_i = 1'b1; - t_sync_en_i = 1'b1; - end - - SYNC0_ST: - alut_src_b_i = 1'b0; - - SYNC1_ST: begin - ir_en_i = 1'b1; - pc_src_i = 1'b0; // pc + 1. - pc_en_i = 1'b1; - alut_src_b_i = 1'b0; - t_sync_en_i = 1'b1; - end - - CONDJ0_ST: - state_condj = 1'b1; - - CONDJ1_ST: begin - state_condj = 1'b1; - pc_src_i = 1'b1; // jump. - pc_en_i = 1'b1; - end - - CONDJ2_ST: - state_condj = 1'b1; - - READ0_ST: begin - ir_en_i = 1'b1; - pc_src_i = 1'b0; // pc + 1. - pc_en_i = 1'b1; - reg_src_i = 3'b011; // Input Port (s_axis). - reg_wen_i = 1'b1; - end - - MEMRI0_ST: begin - reg_src_i = 3'b100; // Memory. - dmem_we_i = 1'b0; // Read. - addr_src_i = 1'b0; // imm. - end - - MEMRI1_ST: begin - reg_src_i = 3'b100; // Memory. - dmem_we_i = 1'b0; // Read. - addr_src_i = 1'b0; // imm. - end - - MEMRI2_ST: begin - ir_en_i = 1'b1; - pc_src_i = 1'b0; // pc + 1. - pc_en_i = 1'b1; - reg_src_i = 3'b100; // Memory. - reg_wen_i = 1'b1; - dmem_we_i = 1'b0; // Read. - addr_src_i = 1'b0; // imm. - end - - MEMR0_ST: begin - reg_src_i = 3'b100; // Memory. - dmem_we_i = 1'b0; // Read. - addr_src_i = 1'b1; // reg. - end - - MEMR1_ST: begin - reg_src_i = 3'b100; // Memory. - dmem_we_i = 1'b0; // Read. - addr_src_i = 1'b1; // reg. - end - - MEMR2_ST: begin - ir_en_i = 1'b1; - pc_src_i = 1'b0; // pc + 1. - pc_en_i = 1'b1; - reg_src_i = 3'b100; // Memory. - reg_wen_i = 1'b1; - dmem_we_i = 1'b0; // Read. - addr_src_i = 1'b1; // reg. - end - - MEMWI0_ST: begin - ir_en_i = 1'b1; - pc_src_i = 1'b0; // pc + 1. - pc_en_i = 1'b1; - dmem_we_i = 1'b1; // Write. - addr_src_i = 1'b0; // imm. - end - - MEMW0_ST: begin - ir_en_i = 1'b1; - pc_src_i = 1'b0; // pc + 1. - pc_en_i = 1'b1; - dmem_we_i = 1'b1; // Write. - addr_src_i = 1'b1; // reg. - end - - REGWI0_ST: begin - ir_en_i = 1'b1; - pc_src_i = 1'b0; // pc + 1. - pc_en_i = 1'b1; - reg_src_i = 3'b000; // imm. - reg_wen_i = 1'b1; - end - - WAITI0_ST: - alut_src_b_i = 1'b1; - - WAITI1_ST: begin - alut_src_b_i = 1'b1; - fifo_wr_en_i = 1'b1; - end - - WAIT0_ST: - alut_src_b_i = 1'b0; - - WAIT1_ST: begin - alut_src_b_i = 1'b0; - fifo_wr_en_i = 1'b1; - end - - WAIT_ACK_ST: - waitt_ack_i = 1'b1; - - //ERR_INSTR_ST: - - //ERR_STACK_ST: - - //END_ST: - - endcase -end - -// Assign outputs. -assign ir_en = ir_en_i; - -assign pc_src = (state_condj == 1'b1)? pc_src_i & cond_flag : pc_src_i; -assign pc_en = (state_loopnz == 1'b1 && state_condj == 1'b0)? pc_en_i & ~alu_zero : - (state_loopnz == 1'b0 && state_condj == 1'b1)? pc_en_i & cond_flag : - pc_en_i; - -assign pc_rst = pc_rst_i; - -assign alu_src_b = alu_src_b_i; -assign alut_src_b = alut_src_b_i; - -assign reg_src = reg_src_i; -assign reg_wen = reg_wen_i; - -assign stack_en = stack_en_i; -assign stack_op = stack_op_i; - -assign fifo_wr_en = fifo_wr_en_i; - -assign dmem_we = dmem_we_i; -assign addr_src = addr_src_i; - -assign t_en = t_en_i; -assign t_sync_en = t_sync_en_i; - -assign waitt_ack = waitt_ack_i; - -endmodule - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/data_mem/axis_read.v b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/data_mem/axis_read.v deleted file mode 100644 index 810cfa4..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/data_mem/axis_read.v +++ /dev/null @@ -1,188 +0,0 @@ -module axis_read ( - // Reset and clock. - aclk_i , - aresetn_i , - - // AXIS Master for sending data. - m_axis_tdata_o , - m_axis_tlast_o , - m_axis_tvalid_o , - m_axis_tready_i , - - // Memory interface. - mem_we_o , - mem_do_i , - mem_addr_o , - - // Handshake. - exec_i , - exec_ack_o , - - // Start address. - addr_i , - - // Length. - len_i -); - -// Parameters. -parameter N = 10; // Memory depth (2**N). -parameter B = 16; // Memory width. - -// Ports. -input aclk_i; -input aresetn_i; -output [B-1:0] m_axis_tdata_o; -output m_axis_tlast_o; -output m_axis_tvalid_o; -input m_axis_tready_i; -output mem_we_o; -input [B-1:0] mem_do_i; -output [N-1:0] mem_addr_o; -input exec_i; -output exec_ack_o; -input [N-1:0] addr_i; -input [N-1:0] len_i; - -// States. -localparam INIT_ST = 0; -localparam LOAD0_ST = 1; -localparam LOAD1_ST = 2; -localparam SEND_ST = 3; -localparam ACK_ST = 4; -localparam END_ST = 5; - -// State register. -reg [2:0] state; - -// State flags. -reg load0_state; -reg load1_state; -reg send_state; -reg ack_int; - -// Start address and length. -reg [N-1:0] addr_r; -reg [N-1:0] len_r; - -// Counter. -reg [N-1:0] cnt; - -// Selection (0: mem, 1: reg). -reg sel_r; - -// Data register. -reg [B-1:0] data_r; -wire data_en; - -// Registers. -always @(posedge aclk_i) begin - if (~aresetn_i) begin - // State register. - state <= INIT_ST; - - // Start address and length. - addr_r <= 0; - len_r <= 0; - - // Counter. - cnt <= 0; - - // Selection (0: mem, 1: reg). - sel_r <= 0; - - // Data register. - data_r <= 0; - - end - else begin - // State register. - case(state) - INIT_ST: - if (exec_i == 1'b1) - state <= LOAD0_ST; - - LOAD0_ST: - state <= LOAD1_ST; - - LOAD1_ST: - state <= SEND_ST; - - SEND_ST: - if (cnt == len_r-1 && m_axis_tready_i) - state <= ACK_ST; - - ACK_ST: - state <= END_ST; - - END_ST: - if (exec_i == 1'b0) - state <= INIT_ST; - endcase - - // Start address and length. - if (load0_state) - addr_r <= addr_i; - else if (load1_state || (send_state && m_axis_tready_i)) - addr_r <= addr_r + 1; - - if (load0_state) - len_r <= len_i; - - // Counter. - if (load0_state) - cnt <= 0; - else if (send_state && m_axis_tready_i) - cnt <= cnt + 1; - - // Selection (0: mem, 1: reg). - if (send_state && ~m_axis_tready_i) - sel_r <= 1; - else - sel_r <= 0; - - // Data register. - if (data_en) - data_r <= mem_do_i; - end -end - -// FSM outputs. -always @(state) begin - // Default. - load0_state = 0; - load1_state = 0; - send_state = 0; - ack_int = 0; - - case (state) - //INIT_ST: - - LOAD0_ST: - load0_state = 1; - - LOAD1_ST: - load1_state = 1; - - SEND_ST: - send_state = 1; - - ACK_ST: - ack_int = 1; - //END_ST: - endcase -end - -// Data enable. -assign data_en = m_axis_tready_i | ~sel_r; - -// Assign outputs. -assign m_axis_tdata_o = (sel_r == 1)? data_r : mem_do_i; -assign m_axis_tlast_o = (cnt == len_r-1) & send_state; -assign m_axis_tvalid_o = send_state; -assign mem_we_o = 1'b0; -assign mem_addr_o = addr_r; -assign exec_ack_o = ack_int; - -endmodule - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/data_mem/axis_write.v b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/data_mem/axis_write.v deleted file mode 100644 index fad6053..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/data_mem/axis_write.v +++ /dev/null @@ -1,151 +0,0 @@ -module axis_write ( - // Reset and clock. - aclk_i , - aresetn_i , - - // AXIS Slave for receiving data. - s_axis_tdata_i , - s_axis_tlast_i , - s_axis_tvalid_i , - s_axis_tready_o , - - // Memory interface. - mem_we_o , - mem_di_o , - mem_addr_o , - - // Handshake. - exec_i , - exec_ack_o , - - // Start address. - addr_i -); - -// Parameters. -parameter N = 10; // Memory depth (2**N). -parameter B = 16; // Memory width. - -// Ports. -input aclk_i; -input aresetn_i; -input [B-1:0] s_axis_tdata_i; -input s_axis_tlast_i; -input s_axis_tvalid_i; -output s_axis_tready_o; -output mem_we_o; -output [B-1:0] mem_di_o; -output [N-1:0] mem_addr_o; -input exec_i; -output exec_ack_o; -input [N-1:0] addr_i; - -// States. -localparam INIT_ST = 0; -localparam WRITE_ST = 1; -localparam ACK_ST = 2; -localparam END_ST = 3; - -// State register. -reg [1:0] state; - -// State flags. -reg init_state; -reg write_state; -reg ack_int; - -// Address generation. -reg [N-1:0] addr_cnt; -reg [N-1:0] addr_cnt_r; - -// Data. -reg [B-1:0] data_r; - -// we generation. -wire we_int; -reg we_int_r; - -// Registers. -always @(posedge aclk_i) begin - if (~aresetn_i) begin - // State register. - state <= INIT_ST; - - // Address generation. - addr_cnt <= 0; - addr_cnt_r <= 0; - - // Data. - data_r <= 0; - - // we generation. - we_int_r <= 0; - end - else begin - // State register. - case(state) - INIT_ST: - if (exec_i == 1'b1) - state <= WRITE_ST; - - WRITE_ST: - if (s_axis_tlast_i && s_axis_tvalid_i) - state <= ACK_ST; - - ACK_ST: - state <= END_ST; - - END_ST: - if (exec_i == 1'b0) - state <= INIT_ST; - endcase - // Address generation. - if (init_state) - addr_cnt <= addr_i; - else if (s_axis_tvalid_i) - addr_cnt <= addr_cnt + 1; - - addr_cnt_r <= addr_cnt; - - // Data. - data_r <= s_axis_tdata_i; - - // we generation. - we_int_r <= we_int; - - end -end - -// FSM outputs. -always @(state) begin - // Default. - init_state = 0; - write_state = 0; - ack_int = 0; - - case (state) - INIT_ST: - init_state = 1; - - WRITE_ST: - write_state = 1; - - ACK_ST: - ack_int = 1; - - //END_ST: - endcase -end - -// we generation. -assign we_int = s_axis_tvalid_i & write_state; - -// Assign outputs. -assign s_axis_tready_o = write_state; -assign mem_we_o = we_int_r; -assign mem_di_o = data_r; -assign mem_addr_o = addr_cnt_r; -assign exec_ack_o = ack_int; - -endmodule - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/data_mem/data_mem.v b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/data_mem/data_mem.v deleted file mode 100644 index 39beef2..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/data_mem/data_mem.v +++ /dev/null @@ -1,276 +0,0 @@ -// Assembled memory access module. Three modes of accessing the memory: -// -// * Single access using the in/out ports. It's only available when busy_o = 0. -// -// * AXIS read: this mode allows to send data using m_axis_* interface, using -// ADDR_REG as the starting address and LEN_REG to indicate the number of -// samples to be transferred. The last sample will assert m_axis_tlast_o to -// indicate the external block transaction is done. Similar to AXIS write -// mode, the user needs to set START_REG = 1 to start the process. -// -// * AXIS write: this mode receives data from s_axis_* interface and writes -// into the memory using ADDR_REG as the starting address. The user must also -// provide the START_REG = 1 to allow starting receiving data. The block will -// rely on s_axis_tlast_i = 1 to finish the writing process. -// -// When not performing any AXIS transaction, the block will grant access to -// the memory using the single access interface. This is a very basic -// handshake interface to allow external blocks to easily communicate and -// perform single-access transaction. -// -// Once a AXIS transaction is done, the user must set START_REG = 0 and back -// to 1 if a new AXIS transaction needs to be executed. START_REG = 1 steady -// will not allow further AXIS transactions, and will only allow -// single-access. -// -// Registers: -// -// MODE_REG : indicates the type of the next AXIS transaction. -// * 0 : AXIS Read (from memory to m_axis). -// * 1 : AXIS Write (from s_axis to memory). -// -// START_REG : starts execution of indicated AXIS transaction. -// * 0 : Stop. -// * 1 : Execute Operation. -// -// ADDR_REG : starting memory address for either AXIS read or write. -// -// LEN_REG : number of samples to be transferred in AXIS read mode. -// -module data_mem ( - // Reset and clock. - aclk_i , - aresetn_i , - - // Single Access Handshake. - busy_o , - oper_i , - addr_i , - din_i , - dout_o , - exec_i , - exec_ack_o , - - // Memory interface. - mem_we_o , - mem_di_o , - mem_do_i , - mem_addr_o , - - // AXIS Slave for receiving data. - s_axis_tdata_i , - s_axis_tlast_i , - s_axis_tvalid_i , - s_axis_tready_o , - - // AXIS Master for sending data. - m_axis_tdata_o , - m_axis_tlast_o , - m_axis_tvalid_o , - m_axis_tready_i , - - // Registers. - MODE_REG , - START_REG , - ADDR_REG , - LEN_REG -); - -// Parameters. -parameter N = 16; -parameter B = 32; - -// Ports. -input aclk_i; -input aresetn_i; - -output busy_o; -input oper_i; -input [N-1:0] addr_i; -input [B-1:0] din_i; -output [B-1:0] dout_o; -input exec_i; -output exec_ack_o; - -output mem_we_o; -output [B-1:0] mem_di_o; -input [B-1:0] mem_do_i; -output [N-1:0] mem_addr_o; - -// AXIS Slave for receiving data. -input [B-1:0] s_axis_tdata_i; -input s_axis_tlast_i; -input s_axis_tvalid_i; -output s_axis_tready_o; - -// AXIS Master for sending data. -output [B-1:0] m_axis_tdata_o; -output m_axis_tlast_o; -output m_axis_tvalid_o; -input m_axis_tready_i; - -input MODE_REG; -input START_REG; -input [N-1:0] ADDR_REG; -input [N-1:0] LEN_REG; - -// Internals. -wire [1:0] sel; -wire ar_exec; -wire ar_exec_ack; -wire aw_exec; -wire aw_exec_ack; - -// Memory Single. -wire mem_we_single; -wire [B-1:0] mem_di_single; -wire [N-1:0] mem_addr_single; - -// Memory AXIS Read. -wire mem_we_aread; -wire [N-1:0] mem_addr_aread; - -// Memory AXIS Write. -wire mem_we_awrite; -wire [B-1:0] mem_di_awrite; -wire [N-1:0] mem_addr_awrite; - -data_mem_ctrl - #( - .N(N) - ) - data_mem_ctrl_i - ( - // Reset and clock. - .aclk_i (aclk_i ), - .aresetn_i (aresetn_i ), - - // Selector. - .sel_o (sel ), - - // axis_read handshake. - .ar_exec_o (ar_exec ), - .ar_exec_ack_i (ar_exec_ack ), - - // axis_write handshake. - .aw_exec_o (aw_exec ), - .aw_exec_ack_i (aw_exec_ack ), - - // Busy flag. - .busy_o (busy_o ), - - // Registers. - .MODE_REG (MODE_REG ), - .START_REG (START_REG ) - ); - -mem_rw - #( - .N(N), - .B(B) - ) - mem_rw_i - ( - // Reset and clock. - .aclk_i (aclk_i ), - .aresetn_i (aresetn_i ), - - // Operation. - .rw_i (oper_i ), - - // Handshake. - .exec_i (exec_i ), - .exec_ack_o (exec_ack_o ), - - // Address. - .addr_i (addr_i ), - - // Input/Output data. - .di_i (din_i ), - .do_o (dout_o ), - - // Memory interface. - .mem_we_o (mem_we_single ), - .mem_di_o (mem_di_single ), - .mem_do_i (mem_do_i ), - .mem_addr_o (mem_addr_single ) - ); - -axis_read - #( - .N(N), - .B(B) - ) - axis_read_i - ( - // Reset and clock. - .aclk_i (aclk_i ), - .aresetn_i (aresetn_i ), - - // AXIS Master for sending data. - .m_axis_tdata_o (m_axis_tdata_o ), - .m_axis_tlast_o (m_axis_tlast_o ), - .m_axis_tvalid_o (m_axis_tvalid_o ), - .m_axis_tready_i (m_axis_tready_i ), - - // Memory interface. - .mem_we_o (mem_we_aread ), - .mem_do_i (mem_do_i ), - .mem_addr_o (mem_addr_aread ), - - // Handshake. - .exec_i (ar_exec ), - .exec_ack_o (ar_exec_ack ), - - // Start address. - .addr_i (ADDR_REG ), - - // Length. - .len_i (LEN_REG ) - ); - -axis_write - #( - .N(N), - .B(B) - ) - axis_write_i - ( - // Reset and clock. - .aclk_i (aclk_i ), - .aresetn_i (aresetn_i ), - - // AXIS Slave for receiving data. - .s_axis_tdata_i (s_axis_tdata_i ), - .s_axis_tlast_i (s_axis_tlast_i ), - .s_axis_tvalid_i (s_axis_tvalid_i ), - .s_axis_tready_o (s_axis_tready_o ), - - // Memory interface. - .mem_we_o (mem_we_awrite ), - .mem_di_o (mem_di_awrite ), - .mem_addr_o (mem_addr_awrite ), - - // Start. - .exec_i (aw_exec ), - .exec_ack_o (aw_exec_ack ), - - // Start address. - .addr_i (ADDR_REG ) - ); - -// Assign outputs. -assign mem_we_o = (sel == 0)? mem_we_single : - (sel == 1)? mem_we_aread : - (sel == 2)? mem_we_awrite : - 1'b0; -assign mem_di_o = (sel == 0)? mem_di_single : - (sel == 2)? mem_di_awrite : - {B{1'b0}}; -assign mem_addr_o = (sel == 0)? mem_addr_single : - (sel == 1)? mem_addr_aread : - (sel == 2)? mem_addr_awrite : - {N{1'b0}}; - -endmodule - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/data_mem/data_mem_ctrl.v b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/data_mem/data_mem_ctrl.v deleted file mode 100644 index 30f5804..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/data_mem/data_mem_ctrl.v +++ /dev/null @@ -1,156 +0,0 @@ -// Control arbiter for memory access operations. -// -// The block arbitrates access to the memory. While executing -// either AXIS Read or Write, busy flag is asserted. If the -// busy flag is not asserted, memory can be accessed using -// single mode (external block). -// -// MODE_REG: -// * 0 : AXIS Read (from memory to m_axis). -// * 1 : AXIS Write (from s_axis to memory). -// -// START_REG: -// * 0 : Stop. -// * 1 : Execute Operation. -module data_mem_ctrl ( - // Reset and clock. - aclk_i , - aresetn_i , - - // Selector. - sel_o , - - // axis_read handshake. - ar_exec_o , - ar_exec_ack_i , - - // axis_write handshake. - aw_exec_o , - aw_exec_ack_i , - - // Busy flag. - busy_o , - - // Registers. - MODE_REG , - START_REG -); - -// Parameters. -parameter N = 16; - -// Ports. -input aclk_i; -input aresetn_i; -output [1:0] sel_o; -output ar_exec_o; -input ar_exec_ack_i; -output aw_exec_o; -input aw_exec_ack_i; -output busy_o; -input MODE_REG; -input START_REG; - -// States. -localparam INIT_ST = 0; -localparam AXIS_READ_ST = 1; -localparam AXIS_READ_ACK_ST = 2; -localparam AXIS_WRITE_ST = 3; -localparam AXIS_WRITE_ACK_ST = 4; -localparam END_ST = 6; - -// State register. -reg [2:0] state; - -// State flags. -reg busy_int; -reg ar_exec_int; -reg aw_exec_int; -reg [1:0] sel_int; // 0: single, 1: axis_read, 2: axis_write. - -// Registers. -always @(posedge aclk_i) begin - if (~aresetn_i) begin - // State register. - state <= INIT_ST; - end - else begin - // State register. - case(state) - INIT_ST: - if (START_REG == 1'b1) - if (MODE_REG == 1'b0) - // AXIS read (from memory to m_axis). - state <= AXIS_READ_ST; - else - // AXIS write (from s_axis to memory). - state <= AXIS_WRITE_ST; - - AXIS_READ_ST: - state <= AXIS_READ_ACK_ST; - - AXIS_READ_ACK_ST: - if (ar_exec_ack_i == 1'b1) - state <= END_ST; - - AXIS_WRITE_ST: - state <= AXIS_WRITE_ACK_ST; - - AXIS_WRITE_ACK_ST: - if (aw_exec_ack_i == 1'b1) - state <= END_ST; - - END_ST: - if (START_REG == 1'b0) - state <= INIT_ST; - endcase - - end -end - -// FSM outputs. -always @(state) begin - // Default. - busy_int = 0; - ar_exec_int = 0; - aw_exec_int = 0; - sel_int = 0; - - case (state) - //INIT_ST: - - AXIS_READ_ST: begin - busy_int = 1; - sel_int = 1; - end - - AXIS_READ_ACK_ST: begin - ar_exec_int = 1; - busy_int = 1; - sel_int = 1; - end - - AXIS_WRITE_ST: begin - busy_int = 1; - sel_int = 2; - end - - AXIS_WRITE_ACK_ST: begin - aw_exec_int = 1; - busy_int = 1; - sel_int = 2; - end - - //END_ST: - - endcase -end - -// Assign outputs. -assign sel_o = sel_int; -assign ar_exec_o = ar_exec_int; -assign aw_exec_o = aw_exec_int; -assign busy_o = busy_int; - -endmodule - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/data_mem/mem_rw.v b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/data_mem/mem_rw.v deleted file mode 100644 index a1a1c76..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/data_mem/mem_rw.v +++ /dev/null @@ -1,148 +0,0 @@ -// Block to execute single read/write operation over a memory. -module mem_rw ( - // Reset and clock. - aclk_i , - aresetn_i , - - // Operation. - rw_i , - - // Handshake. - exec_i , - exec_ack_o , - - // Address. - addr_i , - - // Input/Output data. - di_i , - do_o , - - // Memory interface. - mem_we_o , - mem_di_o , - mem_do_i , - mem_addr_o -); - -// Parameters. -parameter N = 10; // Memory depth (2**N). -parameter B = 16; // Memory width. - -// Ports. -input aclk_i; -input aresetn_i; -input rw_i; -input exec_i; -output exec_ack_o; -input [N-1:0] addr_i; -input [B-1:0] di_i; -output [B-1:0] do_o; -output mem_we_o; -output [B-1:0] mem_di_o; -input [B-1:0] mem_do_i; -output [N-1:0] mem_addr_o; - -// States. -localparam INIT_ST = 0; -localparam READ0_ST = 1; -localparam READ1_ST = 2; -localparam WRITE_ST = 3; -localparam ACK_ST = 4; - -// State register. -reg [2:0] state; - -// Flags. -reg init_state; -reg re_int; -reg we_int; -reg ack_int; - -// Address/data register. -reg [N-1:0] addr_r; -reg [B-1:0] din_r; -reg [B-1:0] dout_r; - -// Registers. -always @(posedge aclk_i) begin - if (~aresetn_i) begin - // State register. - state <= INIT_ST; - - // Address/data register. - addr_r <= 0; - din_r <= 0; - dout_r <= 0; - end - else begin - // State register. - case(state) - INIT_ST: - if (exec_i == 1'b1) - if (rw_i == 1'b0) - state <= READ0_ST; - else - state <= WRITE_ST; - - READ0_ST: - state <= READ1_ST; - - READ1_ST: - state <= ACK_ST; - - WRITE_ST: - state <= ACK_ST; - - ACK_ST: - if (exec_i == 1'b0) - state <= INIT_ST; - endcase - - // Address/data register. - if (init_state) begin - addr_r <= addr_i; - din_r <= di_i; - end - - if (re_int) - dout_r <= mem_do_i; - - end -end - -// FSM outputs. -always @(state) begin - // Default. - init_state = 0; - re_int = 0; - we_int = 0; - ack_int = 0; - - case (state) - INIT_ST: - init_state = 1; - - //READ0_ST: - - READ1_ST: - re_int = 1; - - WRITE_ST: - we_int = 1; - - ACK_ST: - ack_int = 1; - - endcase -end - -// Assign outputs. -assign exec_ack_o = ack_int; -assign do_o = dout_r; -assign mem_we_o = we_int; -assign mem_di_o = din_r; -assign mem_addr_o = addr_r; - -endmodule - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/bin2gray.vhd b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/bin2gray.vhd deleted file mode 100644 index 4ecc09b..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/bin2gray.vhd +++ /dev/null @@ -1,37 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity bin2gray is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end bin2gray; - -architecture rtl of bin2gray is - -signal gray : std_logic_vector (B-1 downto 0); - -begin - --- MSB always match. -gray(B-1) <= din(B-1); - -GEN: for I in 0 to B-2 generate -begin - gray(I) <= din(I+1) xor din(I); -end generate; - --- Assign output. -dout <= gray; - -end rtl; - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/bram_dp.vhd b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/bram_dp.vhd deleted file mode 100644 index d57aad1..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/bram_dp.vhd +++ /dev/null @@ -1,63 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity bram_dp is - Generic ( - -- Memory address size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - ena : in STD_LOGIC; - enb : in STD_LOGIC; - wea : in STD_LOGIC; - web : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR (N-1 downto 0); - addrb : in STD_LOGIC_VECTOR (N-1 downto 0); - dia : in STD_LOGIC_VECTOR (B-1 downto 0); - dib : in STD_LOGIC_VECTOR (B-1 downto 0); - doa : out STD_LOGIC_VECTOR (B-1 downto 0); - dob : out STD_LOGIC_VECTOR (B-1 downto 0) - ); -end bram_dp; - -architecture rtl of bram_dp is - --- Ram type. -type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); -shared variable RAM : ram_type; - -begin - --- CLKA port. -process (clka) -begin - if (clka'event and clka = '1') then - if (ena = '1') then - doa <= RAM(conv_integer(addra)); - if (wea = '1') then - RAM(conv_integer(addra)) := dia; - end if; - end if; - end if; -end process; - --- CLKB port. -process (clkb) -begin - if (clkb'event and clkb = '1') then - if (enb = '1') then - dob <= RAM(conv_integer(addrb)); - if (web = '1') then - RAM(conv_integer(addrb)) := dib; - end if; - end if; - end if; -end process; - -end rtl; - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/bram_simple_dp.vhd b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/bram_simple_dp.vhd deleted file mode 100644 index 1494332..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/bram_simple_dp.vhd +++ /dev/null @@ -1,53 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity bram_simple_dp is - Generic ( - -- Memory address size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port ( - clk : in STD_LOGIC; - ena : in STD_LOGIC; - enb : in STD_LOGIC; - wea : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR (N-1 downto 0); - addrb : in STD_LOGIC_VECTOR (N-1 downto 0); - dia : in STD_LOGIC_VECTOR (B-1 downto 0); - dob : out STD_LOGIC_VECTOR (B-1 downto 0) - ); -end bram_simple_dp; - -architecture rtl of bram_simple_dp is - --- Ram type. -type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); -shared variable RAM : ram_type; - -begin - -process (clk) -begin - if (clk'event and clk = '1') then - if (ena = '1') then - if (wea = '1') then - RAM(conv_integer(addra)) := dia; - end if; - end if; - end if; -end process; - -process (clk) -begin - if (clk'event and clk = '1') then - if (enb = '1') then - dob <= RAM(conv_integer(addrb)); - end if; - end if; -end process; - -end rtl; - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/fifo.vhd b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/fifo.vhd deleted file mode 100644 index 957362b..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/fifo.vhd +++ /dev/null @@ -1,135 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo; - -architecture rtl of fifo is - --- Number of bits of depth. -constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); - --- Dual port, single clock BRAM. -component bram_simple_dp is - Generic ( - -- Memory address size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port ( - clk : in STD_LOGIC; - ena : in STD_LOGIC; - enb : in STD_LOGIC; - wea : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR (N-1 downto 0); - addrb : in STD_LOGIC_VECTOR (N-1 downto 0); - dia : in STD_LOGIC_VECTOR (B-1 downto 0); - dob : out STD_LOGIC_VECTOR (B-1 downto 0) - ); -end component; - --- Pointers. -signal wptr : unsigned (N_LOG2-1 downto 0); -signal rptr : unsigned (N_LOG2-1 downto 0); - --- Memory signals. -signal mem_wea : std_logic; -signal mem_dob : std_logic_vector (B-1 downto 0); - --- Flags. -signal full_i : std_logic; -signal empty_i : std_logic; - -begin - --- FIFO memory. -mem_i : bram_simple_dp - Generic map ( - -- Memory address size. - N => N_LOG2, - -- Data width. - B => B - ) - Port map ( - clk => clk , - ena => '1' , - enb => rd_en , - wea => mem_wea , - addra => std_logic_vector(wptr) , - addrb => std_logic_vector(rptr) , - dia => din , - dob => mem_dob - ); - --- Memory connections. -mem_wea <= wr_en when full_i = '0' else - '0'; - --- Full/empty signals. -full_i <= '1' when wptr = rptr - 1 else - '0'; -empty_i <= '1' when wptr = rptr else - '0'; - --- wr_clk registers. -process (clk) -begin - if ( rising_edge(clk) ) then - if ( rstn = '0' ) then - wptr <= (others => '0'); - rptr <= (others => '0'); - else - -- Write. - if ( wr_en = '1' and full_i = '0' ) then - -- Write data. - - -- Increment pointer. - wptr <= wptr + 1; - end if; - - -- Read. - if ( rd_en = '1' and empty_i = '0' ) then - -- Read data. - - -- Increment pointer. - rptr <= rptr + 1; - end if; - end if; - end if; -end process; - --- Assign outputs. -dout <= mem_dob; -full <= full_i; -empty <= empty_i; - -end rtl; - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/fifo_axi.vhd b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/fifo_axi.vhd deleted file mode 100644 index e1f76f7..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/fifo_axi.vhd +++ /dev/null @@ -1,147 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo_axi is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo_axi; - -architecture rtl of fifo_axi is - --- FIFO. -component fifo is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end component; - --- FIFO read to AXI adapter. -component rd2axi is - Generic - ( - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- FIFO Read I/F. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (B-1 downto 0); - fifo_empty : in std_logic; - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - empty : out std_logic - ); -end component; - -signal rd_en_i : std_logic; -signal dout_i : std_logic_vector (B-1 downto 0); -signal empty_i : std_logic; - -begin - --- FIFO. -fifo_i : fifo - Generic map - ( - -- Data width. - B => B, - - -- Fifo depth. - N => N - ) - Port map - ( - rstn => rstn , - clk => clk , - - -- Write I/F. - wr_en => wr_en , - din => din , - - -- Read I/F. - rd_en => rd_en_i , - dout => dout_i , - - -- Flags. - full => full , - empty => empty_i - ); - --- FIFO read to AXI adapter. -rd2axi_i : rd2axi - Generic map - ( - -- Data width. - B => B - ) - Port map - ( - rstn => rstn , - clk => clk , - - -- FIFO Read I/F. - fifo_rd_en => rd_en_i , - fifo_dout => dout_i , - fifo_empty => empty_i , - - -- Read I/F. - rd_en => rd_en , - dout => dout , - empty => empty - ); - -end rtl; - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/fifo_dc.vhd b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/fifo_dc.vhd deleted file mode 100644 index c214fae..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/fifo_dc.vhd +++ /dev/null @@ -1,291 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo_dc is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - wr_rstn : in std_logic; - wr_clk : in std_logic; - - rd_rstn : in std_logic; - rd_clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo_dc; - -architecture rtl of fifo_dc is - --- Number of bits of depth. -constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); - --- Binary to gray converter. -component bin2gray is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end component; - --- Gray to binary converter. -component gray2bin is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end component; - --- Vector synchronizer (only for gray coded). -component synchronizer_vect is - generic ( - -- Sync stages. - N : Integer := 2; - - -- Data width. - B : Integer := 8 - ); - port ( - rstn : in std_logic; - clk : in std_logic; - data_in : in std_logic_vector (B-1 downto 0); - data_out : out std_logic_vector (B-1 downto 0) - ); -end component; - --- Dual port BRAM. -component bram_dp is - Generic ( - -- Memory address size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - ena : in STD_LOGIC; - enb : in STD_LOGIC; - wea : in STD_LOGIC; - web : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR (N-1 downto 0); - addrb : in STD_LOGIC_VECTOR (N-1 downto 0); - dia : in STD_LOGIC_VECTOR (B-1 downto 0); - dib : in STD_LOGIC_VECTOR (B-1 downto 0); - doa : out STD_LOGIC_VECTOR (B-1 downto 0); - dob : out STD_LOGIC_VECTOR (B-1 downto 0) - ); -end component; - --- Pointers. -signal wptr : unsigned (N_LOG2-1 downto 0); -signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); -signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); -signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); -signal rptr : unsigned (N_LOG2-1 downto 0); -signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); -signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); -signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); - --- Memory signals. -signal mem_wea : std_logic; -signal mem_dib : std_logic_vector (B-1 downto 0); -signal mem_doa : std_logic_vector (B-1 downto 0); -signal mem_dob : std_logic_vector (B-1 downto 0); - --- Flags. -signal full_i : std_logic; -signal empty_i : std_logic; - -begin - --- wptr_i: binary to gray. -wptr_i : bin2gray - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => std_logic_vector(wptr), - dout => wptr_g - ); - --- wptr_g: write to read domain. -wptr_g_i : synchronizer_vect - generic map ( - -- Sync stages. - N => 2, - - -- Data width. - B => N_LOG2 - ) - port map ( - rstn => rd_rstn, - clk => rd_clk, - data_in => wptr_g, - data_out => wptr_gc - ); - --- wptr_gc_i -wptr_gc_i : gray2bin - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => wptr_gc, - dout => wptr_c - ); - --- rptr_i: binary to gray. -rptr_i : bin2gray - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => std_logic_vector(rptr), - dout => rptr_g - ); - --- rptr_g: read to write domain. -rptr_g_i : synchronizer_vect - generic map ( - -- Sync stages. - N => 2, - - -- Data width. - B => N_LOG2 - ) - port map ( - rstn => wr_rstn, - clk => wr_clk, - data_in => rptr_g, - data_out => rptr_gc - ); - --- rptr_gc_i -rptr_gc_i : gray2bin - Generic map - ( - -- Data width. - B => N_LOG2 - ) - Port map - ( - din => rptr_gc, - dout => rptr_c - ); - --- FIFO memory. -mem_i : bram_dp - Generic map ( - -- Memory address size. - N => N_LOG2, - -- Data width. - B => B - ) - Port map ( - clka => wr_clk, - clkb => rd_clk, - ena => '1', - enb => rd_en, - wea => mem_wea, - web => '0', - addra => std_logic_vector(wptr), - addrb => std_logic_vector(rptr), - dia => din, - dib => mem_dib, - doa => mem_doa, - dob => mem_dob - ); --- Memory connections. -mem_wea <= wr_en when full_i = '0' else - '0'; -mem_dib <= (others => '0'); - --- Full/empty signals. -full_i <= '1' when wptr = unsigned(rptr_c) - 1 else - '0'; -empty_i <= '1' when unsigned(wptr_c) = rptr else - '0'; - --- wr_clk registers. -process (wr_clk) -begin - if ( rising_edge(wr_clk) ) then - if ( wr_rstn = '0' ) then - wptr <= (others => '0'); - else - -- Write. - if ( wr_en = '1' and full_i = '0' ) then - -- Write data. - - -- Increment pointer. - wptr <= wptr + 1; - end if; - end if; - end if; -end process; - --- rd_clk registers. -process (rd_clk) -begin - if ( rising_edge(rd_clk) ) then - if ( rd_rstn = '0' ) then - rptr <= (others => '0'); - else - -- Read. - if ( rd_en = '1' and empty_i = '0' ) then - -- Read data. - - -- Increment pointer. - rptr <= rptr + 1; - end if; - end if; - end if; -end process; - --- Assign outputs. -dout <= mem_dob; -full <= full_i; -empty <= empty_i; - -end rtl; diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/fifo_dc_axi.vhd b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/fifo_dc_axi.vhd deleted file mode 100644 index eb83d1a..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/fifo_dc_axi.vhd +++ /dev/null @@ -1,156 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity fifo_dc_axi is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - wr_rstn : in std_logic; - wr_clk : in std_logic; - - rd_rstn : in std_logic; - rd_clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo_dc_axi; - -architecture rtl of fifo_dc_axi is - --- Dual-clock FIFO. -component fifo_dc is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - wr_rstn : in std_logic; - wr_clk : in std_logic; - - rd_rstn : in std_logic; - rd_clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end component; - --- FIFO read to AXI adapter. -component rd2axi is - Generic - ( - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- FIFO Read I/F. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (B-1 downto 0); - fifo_empty : in std_logic; - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - empty : out std_logic - ); -end component; - -signal rd_en_i : std_logic; -signal dout_i : std_logic_vector (B-1 downto 0); -signal empty_i : std_logic; - -begin - --- Dual-clock FIFO. -fifo_i : fifo_dc - Generic map - ( - -- Data width. - B => B, - - -- Fifo depth. - N => N - ) - Port map - ( - wr_rstn => wr_rstn , - wr_clk => wr_clk , - - rd_rstn => rd_rstn , - rd_clk => rd_clk , - - -- Write I/F. - wr_en => wr_en , - din => din , - - -- Read I/F. - rd_en => rd_en_i , - dout => dout_i , - - -- Flags. - full => full , - empty => empty_i - ); - --- FIFO read to AXI adapter. -rd2axi_i : rd2axi - Generic map - ( - -- Data width. - B => B - ) - Port map - ( - rstn => rd_rstn , - clk => rd_clk , - - -- FIFO Read I/F. - fifo_rd_en => rd_en_i , - fifo_dout => dout_i , - fifo_empty => empty_i , - - -- Read I/F. - rd_en => rd_en , - dout => dout , - empty => empty - ); - -end rtl; - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/gray2bin.vhd b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/gray2bin.vhd deleted file mode 100644 index e23f8af..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/gray2bin.vhd +++ /dev/null @@ -1,37 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity gray2bin is - Generic - ( - -- Data width. - B : Integer := 8 - ); - Port - ( - din : in std_logic_vector (B-1 downto 0); - dout: out std_logic_vector (B-1 downto 0) - ); -end gray2bin; - -architecture rtl of gray2bin is - -signal bin : std_logic_vector (B-1 downto 0); - -begin - --- MSB always match. -bin(B-1) <= din(B-1); - -GEN: for I in 0 to B-2 generate -begin - bin(I) <= bin(I+1) xor din(I); -end generate GEN; - --- Assign output. -dout <= bin; - -end rtl; - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/rd2axi.vhd b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/rd2axi.vhd deleted file mode 100644 index babadc6..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/rd2axi.vhd +++ /dev/null @@ -1,138 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity rd2axi is - Generic - ( - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- FIFO Read I/F. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (B-1 downto 0); - fifo_empty : in std_logic; - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - empty : out std_logic - ); -end rd2axi; - -architecture rtl of rd2axi is - -type fsm_state is ( WAIT_EMPTY_ST, - READ_FIRST_ST, - READ_ST, - READ_LAST_ST); -signal current_state, next_state : fsm_state; - -signal wait_empty_state : std_logic; -signal read_first_state : std_logic; -signal read_state : std_logic; - -signal fifo_rd_en_i : std_logic; -signal empty_i : std_logic; - -begin - -process(clk) -begin - if (rising_edge(clk)) then - if (rstn = '0') then - current_state <= WAIT_EMPTY_ST; - else - current_state <= next_state; - end if; - end if; -end process; - --- Next state logic. -process(current_state, fifo_empty, rd_en) -begin - case current_state is - when WAIT_EMPTY_ST => - if (fifo_empty = '1') then - next_state <= WAIT_EMPTY_ST; - else - next_state <= READ_FIRST_ST; - end if; - - when READ_FIRST_ST => - next_state <= READ_ST; - - when READ_ST => - if (fifo_empty = '0') then - next_state <= READ_ST; - else - if (rd_en = '1') then - next_state <= WAIT_EMPTY_ST; - else - next_state <= READ_LAST_ST; - end if; - end if; - - when READ_LAST_ST => - if (rd_en = '0') then - next_state <= READ_LAST_ST; - else - next_state <= WAIT_EMPTY_ST; - end if; - - end case; -end process; - --- Output logic. -process(current_state) -begin -wait_empty_state <= '0'; -read_first_state <= '0'; -read_state <= '0'; -empty_i <= '0'; - case current_state is - when WAIT_EMPTY_ST => - wait_empty_state <= '1'; - read_first_state <= '0'; - read_state <= '0'; - empty_i <= '1'; - - when READ_FIRST_ST => - wait_empty_state <= '0'; - read_first_state <= '1'; - read_state <= '0'; - empty_i <= '1'; - - when READ_ST => - wait_empty_state <= '0'; - read_first_state <= '0'; - read_state <= '1'; - empty_i <= '0'; - - when READ_LAST_ST => - wait_empty_state <= '0'; - read_first_state <= '0'; - read_state <= '0'; - empty_i <= '0'; - - end case; -end process; - --- FIFO Read enable signal. -fifo_rd_en_i <= read_first_state or (read_state and rd_en); - --- Assign outputs. -fifo_rd_en <= fifo_rd_en_i; --- TODO: add register to freeze last value. -dout <= fifo_dout when empty_i = '0' else - (others => '0'); -empty <= empty_i; - -end rtl; - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/synchronizer_vect.vhd b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/synchronizer_vect.vhd deleted file mode 100644 index 2fbb696..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/synchronizer_vect.vhd +++ /dev/null @@ -1,49 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - --- This block is intended to use to sync gray coded vectors. - --- NOTE: Do not use with generic vector data, as it may result --- in corrupted re-sync data. - -entity synchronizer_vect is - generic ( - -- Sync stages. - N : Integer := 2; - - -- Data width. - B : Integer := 8 - ); - port ( - rstn : in std_logic; - clk : in std_logic; - data_in : in std_logic_vector (B-1 downto 0); - data_out : out std_logic_vector (B-1 downto 0) - ); -end synchronizer_vect; - -architecture rtl of synchronizer_vect is - --- Internal register. -type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); -signal data_int_reg : reg_t; - -begin - -process(clk) -begin - if (rising_edge(clk)) then - if (rstn = '0') then - data_int_reg <= (others => (others => '0')); -- 1 FF. - else - data_int_reg <= data_int_reg(N-2 downto 0) & data_in; - end if; - end if; -end process; - --- Assign output. -data_out <= data_int_reg(N-1); - -end rtl; - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/gen_sim/gen_sim.sv b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/gen_sim/gen_sim.sv deleted file mode 100644 index deace3c..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/gen_sim/gen_sim.sv +++ /dev/null @@ -1,142 +0,0 @@ -// Simplified Signal Generator Simulator. -// The block reads from the queue and implements the periodic -// and non-periodic mode, using the lower 16 bits for the number -// of samples and the next bit for mode. -module gen_sim - ( - clk , - rstn , - s_axis_tdata , - s_axis_tvalid , - s_axis_tready - ); - -input clk; -input rstn; - -input [159:0] s_axis_tdata; -input s_axis_tvalid; -output s_axis_tready; - -// States. -typedef enum { READ_ST , - CNT_ST - } state_t; - -(* fsm_encoding = "one_hot" *) state_t state; - -reg fifo_rd_en; -wire [159:0] fifo_dout; -wire fifo_full; -wire fifo_empty; - -// Fifo fields. -wire [15:0] nsamp_int; -reg [15:0] nsamp_r; -wire mode_int; -reg mode_r; - -// Counter. -reg [15:0] cnt; - -// Register enable. -wire en; -reg en_r; - -// Fifo. -fifo - #( - // Data width. - .B (160 ), - - // Fifo depth. - .N (16 ) - ) - fifo_i - ( - .rstn (rstn ), - .clk (clk ), - - // Write I/F. - .wr_en (s_axis_tvalid ), - .din (s_axis_tdata ), - - // Read I/F. - .rd_en (fifo_rd_en ), - .dout (fifo_dout ), - - // Flags. - .full (fifo_full ), - .empty (fifo_empty ) - ); - -// Fifo fields. -assign nsamp_int = fifo_dout[15:0]; -assign mode_int = fifo_dout[16]; - -// Register enable. -assign en = fifo_rd_en & ~fifo_empty; - -// Registers. -always @(posedge clk) begin - if (~rstn) begin - // State register. - state <= READ_ST; - - // Fifo fields. - nsamp_r <= 0; - mode_r <= 0; - - // Counter. - cnt <= 0; - - // Register enable. - en_r <= 0; - end - else begin - // State register. - case (state) - READ_ST: - if (mode_r == 1'b1 || fifo_empty == 1'b0) - state <= CNT_ST; - - CNT_ST: - if (cnt == nsamp_r-2) - state <= READ_ST; - endcase - - // Counter. - if (fifo_rd_en == 1'b0) - cnt <= cnt + 1; - else - cnt <= 0; - - // Fifo fields. - if (en_r == 1'b1) begin - nsamp_r <= nsamp_int; - mode_r <= mode_int; - end - - // Register enable. - en_r <= en; - end -end - -// FSM outputs. -always_comb begin - // Default. - fifo_rd_en = 1'b0; - - case (state) - READ_ST: begin - fifo_rd_en = 1'b1; - end - - //CNT_ST: - endcase -end - -assign s_axis_tready = ~fifo_full; - -endmodule - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/regfile/regfile.vhd b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/regfile/regfile.vhd deleted file mode 100644 index 6b6ce9c..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/regfile/regfile.vhd +++ /dev/null @@ -1,104 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity regfile is - Generic ( - -- Data width. - B : Integer := 16; - -- Map size. - N : Integer := 4 - ); - Port ( - -- Clock. - clk : in std_logic; - - -- Read address. - addr0 : in std_logic_vector (N-1 downto 0); - addr1 : in std_logic_vector (N-1 downto 0); - addr2 : in std_logic_vector (N-1 downto 0); - addr3 : in std_logic_vector (N-1 downto 0); - addr4 : in std_logic_vector (N-1 downto 0); - addr5 : in std_logic_vector (N-1 downto 0); - addr6 : in std_logic_vector (N-1 downto 0); - - -- Write address. - addr7 : in std_logic_vector (N-1 downto 0); - - -- Write data. - din7 : in std_logic_vector (B-1 downto 0); - wen7 : in std_logic; - - -- Output registers. - dout0 : out std_logic_vector (B-1 downto 0); - dout1 : out std_logic_vector (B-1 downto 0); - dout2 : out std_logic_vector (B-1 downto 0); - dout3 : out std_logic_vector (B-1 downto 0); - dout4 : out std_logic_vector (B-1 downto 0); - dout5 : out std_logic_vector (B-1 downto 0); - dout6 : out std_logic_vector (B-1 downto 0) - ); -end regfile; - -architecture rtl of regfile is - -type mem_array_t is array ((2**N-1) downto 0) of std_logic_vector (B-1 downto 0); -signal mem_array : mem_array_t; - -begin - -process (clk) -begin - if ( rising_edge(clk) ) then - -- Write. - if ( wen7 = '1' ) then - mem_array(to_integer(unsigned(addr7))) <= din7; - end if; - - -- Read. - if ( unsigned(addr0) = 0 ) then - dout0 <= (others => '0'); - else - dout0 <= mem_array(to_integer(unsigned(addr0))); - end if; - - if ( unsigned(addr1) = 0 ) then - dout1 <= (others => '0'); - else - dout1 <= mem_array(to_integer(unsigned(addr1))); - end if; - - if ( unsigned(addr2) = 0 ) then - dout2 <= (others => '0'); - else - dout2 <= mem_array(to_integer(unsigned(addr2))); - end if; - - if ( unsigned(addr3) = 0 ) then - dout3 <= (others => '0'); - else - dout3 <= mem_array(to_integer(unsigned(addr3))); - end if; - - if ( unsigned(addr4) = 0 ) then - dout4 <= (others => '0'); - else - dout4 <= mem_array(to_integer(unsigned(addr4))); - end if; - - if ( unsigned(addr5) = 0 ) then - dout5 <= (others => '0'); - else - dout5 <= mem_array(to_integer(unsigned(addr5))); - end if; - - if ( unsigned(addr6) = 0 ) then - dout6 <= (others => '0'); - else - dout6 <= mem_array(to_integer(unsigned(addr6))); - end if; - end if; -end process; - -end rtl; - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/regfile/regfile_8p.vhd b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/regfile/regfile_8p.vhd deleted file mode 100644 index 6407924..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/regfile/regfile_8p.vhd +++ /dev/null @@ -1,592 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - --- Regfile block. --- --- 7 registers can be read in parallel. One clock cycle latency. --- 1 register can be written. --- 8 pages allow 32x8 = 256 total registers. --- In any page, reading register 0 gives 0. - -entity regfile_8p is - Generic ( - -- Data width. - B : Integer := 16 - ); - Port ( - -- Clock and reset. - clk : in std_logic; - rstn : in std_logic; - - -- Read address. - addr0 : in std_logic_vector (4 downto 0); - addr1 : in std_logic_vector (4 downto 0); - addr2 : in std_logic_vector (4 downto 0); - addr3 : in std_logic_vector (4 downto 0); - addr4 : in std_logic_vector (4 downto 0); - addr5 : in std_logic_vector (4 downto 0); - addr6 : in std_logic_vector (4 downto 0); - - -- Write address. - addr7 : in std_logic_vector (4 downto 0); - - -- Write data. - din7 : in std_logic_vector (B-1 downto 0); - wen7 : in std_logic; - - -- Page number. - pnum : in std_logic_vector (2 downto 0); - - -- Output registers. - dout0 : out std_logic_vector (B-1 downto 0); - dout1 : out std_logic_vector (B-1 downto 0); - dout2 : out std_logic_vector (B-1 downto 0); - dout3 : out std_logic_vector (B-1 downto 0); - dout4 : out std_logic_vector (B-1 downto 0); - dout5 : out std_logic_vector (B-1 downto 0); - dout6 : out std_logic_vector (B-1 downto 0) - ); -end regfile_8p; - -architecture rtl of regfile_8p is - -constant N : Integer := 5; - --- Register file. -component regfile is - Generic ( - -- Data width. - B : Integer := 16; - -- Map size. - N : Integer := 4 - ); - Port ( - -- Clock. - clk : in std_logic; - - -- Read address. - addr0 : in std_logic_vector (N-1 downto 0); - addr1 : in std_logic_vector (N-1 downto 0); - addr2 : in std_logic_vector (N-1 downto 0); - addr3 : in std_logic_vector (N-1 downto 0); - addr4 : in std_logic_vector (N-1 downto 0); - addr5 : in std_logic_vector (N-1 downto 0); - addr6 : in std_logic_vector (N-1 downto 0); - - -- Write address. - addr7 : in std_logic_vector (N-1 downto 0); - - -- Write data. - din7 : in std_logic_vector (B-1 downto 0); - wen7 : in std_logic; - - -- Output registers. - dout0 : out std_logic_vector (B-1 downto 0); - dout1 : out std_logic_vector (B-1 downto 0); - dout2 : out std_logic_vector (B-1 downto 0); - dout3 : out std_logic_vector (B-1 downto 0); - dout4 : out std_logic_vector (B-1 downto 0); - dout5 : out std_logic_vector (B-1 downto 0); - dout6 : out std_logic_vector (B-1 downto 0) - ); -end component; - --- Regfile 0. -signal wen7_0 : std_logic; -signal dout0_0 : std_logic_vector (B-1 downto 0); -signal dout1_0 : std_logic_vector (B-1 downto 0); -signal dout2_0 : std_logic_vector (B-1 downto 0); -signal dout3_0 : std_logic_vector (B-1 downto 0); -signal dout4_0 : std_logic_vector (B-1 downto 0); -signal dout5_0 : std_logic_vector (B-1 downto 0); -signal dout6_0 : std_logic_vector (B-1 downto 0); - --- Regfile 1. -signal wen7_1 : std_logic; -signal dout0_1 : std_logic_vector (B-1 downto 0); -signal dout1_1 : std_logic_vector (B-1 downto 0); -signal dout2_1 : std_logic_vector (B-1 downto 0); -signal dout3_1 : std_logic_vector (B-1 downto 0); -signal dout4_1 : std_logic_vector (B-1 downto 0); -signal dout5_1 : std_logic_vector (B-1 downto 0); -signal dout6_1 : std_logic_vector (B-1 downto 0); - --- Regfile 2. -signal wen7_2 : std_logic; -signal dout0_2 : std_logic_vector (B-1 downto 0); -signal dout1_2 : std_logic_vector (B-1 downto 0); -signal dout2_2 : std_logic_vector (B-1 downto 0); -signal dout3_2 : std_logic_vector (B-1 downto 0); -signal dout4_2 : std_logic_vector (B-1 downto 0); -signal dout5_2 : std_logic_vector (B-1 downto 0); -signal dout6_2 : std_logic_vector (B-1 downto 0); - --- Regfile 3. -signal wen7_3 : std_logic; -signal dout0_3 : std_logic_vector (B-1 downto 0); -signal dout1_3 : std_logic_vector (B-1 downto 0); -signal dout2_3 : std_logic_vector (B-1 downto 0); -signal dout3_3 : std_logic_vector (B-1 downto 0); -signal dout4_3 : std_logic_vector (B-1 downto 0); -signal dout5_3 : std_logic_vector (B-1 downto 0); -signal dout6_3 : std_logic_vector (B-1 downto 0); - --- Regfile 4. -signal wen7_4 : std_logic; -signal dout0_4 : std_logic_vector (B-1 downto 0); -signal dout1_4 : std_logic_vector (B-1 downto 0); -signal dout2_4 : std_logic_vector (B-1 downto 0); -signal dout3_4 : std_logic_vector (B-1 downto 0); -signal dout4_4 : std_logic_vector (B-1 downto 0); -signal dout5_4 : std_logic_vector (B-1 downto 0); -signal dout6_4 : std_logic_vector (B-1 downto 0); - --- Regfile 5. -signal wen7_5 : std_logic; -signal dout0_5 : std_logic_vector (B-1 downto 0); -signal dout1_5 : std_logic_vector (B-1 downto 0); -signal dout2_5 : std_logic_vector (B-1 downto 0); -signal dout3_5 : std_logic_vector (B-1 downto 0); -signal dout4_5 : std_logic_vector (B-1 downto 0); -signal dout5_5 : std_logic_vector (B-1 downto 0); -signal dout6_5 : std_logic_vector (B-1 downto 0); - --- Regfile 6. -signal wen7_6 : std_logic; -signal dout0_6 : std_logic_vector (B-1 downto 0); -signal dout1_6 : std_logic_vector (B-1 downto 0); -signal dout2_6 : std_logic_vector (B-1 downto 0); -signal dout3_6 : std_logic_vector (B-1 downto 0); -signal dout4_6 : std_logic_vector (B-1 downto 0); -signal dout5_6 : std_logic_vector (B-1 downto 0); -signal dout6_6 : std_logic_vector (B-1 downto 0); - --- Regfile 7. -signal wen7_7 : std_logic; -signal dout0_7 : std_logic_vector (B-1 downto 0); -signal dout1_7 : std_logic_vector (B-1 downto 0); -signal dout2_7 : std_logic_vector (B-1 downto 0); -signal dout3_7 : std_logic_vector (B-1 downto 0); -signal dout4_7 : std_logic_vector (B-1 downto 0); -signal dout5_7 : std_logic_vector (B-1 downto 0); -signal dout6_7 : std_logic_vector (B-1 downto 0); - --- Muxed output data. -signal dout0_i : std_logic_vector (B-1 downto 0); -signal dout1_i : std_logic_vector (B-1 downto 0); -signal dout2_i : std_logic_vector (B-1 downto 0); -signal dout3_i : std_logic_vector (B-1 downto 0); -signal dout4_i : std_logic_vector (B-1 downto 0); -signal dout5_i : std_logic_vector (B-1 downto 0); -signal dout6_i : std_logic_vector (B-1 downto 0); - --- Pipe on page selection. -signal pnum_r : std_logic_vector (2 downto 0); - -begin - --- Register file 0. -regfile_0_i : regfile - Generic map ( - -- Data width. - B => B , - -- Map size. - N => N - ) - Port map ( - -- Clock. - clk => clk , - - -- Read address. - addr0 => addr0 , - addr1 => addr1 , - addr2 => addr2 , - addr3 => addr3 , - addr4 => addr4 , - addr5 => addr5 , - addr6 => addr6 , - - -- Write address. - addr7 => addr7 , - - -- Write data. - din7 => din7 , - wen7 => wen7_0 , - - -- Output registers. - dout0 => dout0_0 , - dout1 => dout1_0 , - dout2 => dout2_0 , - dout3 => dout3_0 , - dout4 => dout4_0 , - dout5 => dout5_0 , - dout6 => dout6_0 - ); - --- Register file 1. -regfile_1_i : regfile - Generic map ( - -- Data width. - B => B , - -- Map size. - N => N - ) - Port map ( - -- Clock. - clk => clk , - - -- Read address. - addr0 => addr0 , - addr1 => addr1 , - addr2 => addr2 , - addr3 => addr3 , - addr4 => addr4 , - addr5 => addr5 , - addr6 => addr6 , - - -- Write address. - addr7 => addr7 , - - -- Write data. - din7 => din7 , - wen7 => wen7_1 , - - -- Output registers. - dout0 => dout0_1 , - dout1 => dout1_1 , - dout2 => dout2_1 , - dout3 => dout3_1 , - dout4 => dout4_1 , - dout5 => dout5_1 , - dout6 => dout6_1 - ); - --- Register file 2. -regfile_2_i : regfile - Generic map ( - -- Data width. - B => B , - -- Map size. - N => N - ) - Port map ( - -- Clock. - clk => clk , - - -- Read address. - addr0 => addr0 , - addr1 => addr1 , - addr2 => addr2 , - addr3 => addr3 , - addr4 => addr4 , - addr5 => addr5 , - addr6 => addr6 , - - -- Write address. - addr7 => addr7 , - - -- Write data. - din7 => din7 , - wen7 => wen7_2 , - - -- Output registers. - dout0 => dout0_2 , - dout1 => dout1_2 , - dout2 => dout2_2 , - dout3 => dout3_2 , - dout4 => dout4_2 , - dout5 => dout5_2 , - dout6 => dout6_2 - ); - --- Register file 3. -regfile_3_i : regfile - Generic map ( - -- Data width. - B => B , - -- Map size. - N => N - ) - Port map ( - -- Clock. - clk => clk , - - -- Read address. - addr0 => addr0 , - addr1 => addr1 , - addr2 => addr2 , - addr3 => addr3 , - addr4 => addr4 , - addr5 => addr5 , - addr6 => addr6 , - - -- Write address. - addr7 => addr7 , - - -- Write data. - din7 => din7 , - wen7 => wen7_3 , - - -- Output registers. - dout0 => dout0_3 , - dout1 => dout1_3 , - dout2 => dout2_3 , - dout3 => dout3_3 , - dout4 => dout4_3 , - dout5 => dout5_3 , - dout6 => dout6_3 - ); - --- Register file 4. -regfile_4_i : regfile - Generic map ( - -- Data width. - B => B , - -- Map size. - N => N - ) - Port map ( - -- Clock. - clk => clk , - - -- Read address. - addr0 => addr0 , - addr1 => addr1 , - addr2 => addr2 , - addr3 => addr3 , - addr4 => addr4 , - addr5 => addr5 , - addr6 => addr6 , - - -- Write address. - addr7 => addr7 , - - -- Write data. - din7 => din7 , - wen7 => wen7_4 , - - -- Output registers. - dout0 => dout0_4 , - dout1 => dout1_4 , - dout2 => dout2_4 , - dout3 => dout3_4 , - dout4 => dout4_4 , - dout5 => dout5_4 , - dout6 => dout6_4 - ); - --- Register file 5. -regfile_5_i : regfile - Generic map ( - -- Data width. - B => B , - -- Map size. - N => N - ) - Port map ( - -- Clock. - clk => clk , - - -- Read address. - addr0 => addr0 , - addr1 => addr1 , - addr2 => addr2 , - addr3 => addr3 , - addr4 => addr4 , - addr5 => addr5 , - addr6 => addr6 , - - -- Write address. - addr7 => addr7 , - - -- Write data. - din7 => din7 , - wen7 => wen7_5 , - - -- Output registers. - dout0 => dout0_5 , - dout1 => dout1_5 , - dout2 => dout2_5 , - dout3 => dout3_5 , - dout4 => dout4_5 , - dout5 => dout5_5 , - dout6 => dout6_5 - ); - --- Register file 6. -regfile_6_i : regfile - Generic map ( - -- Data width. - B => B , - -- Map size. - N => N - ) - Port map ( - -- Clock. - clk => clk , - - -- Read address. - addr0 => addr0 , - addr1 => addr1 , - addr2 => addr2 , - addr3 => addr3 , - addr4 => addr4 , - addr5 => addr5 , - addr6 => addr6 , - - -- Write address. - addr7 => addr7 , - - -- Write data. - din7 => din7 , - wen7 => wen7_6 , - - -- Output registers. - dout0 => dout0_6 , - dout1 => dout1_6 , - dout2 => dout2_6 , - dout3 => dout3_6 , - dout4 => dout4_6 , - dout5 => dout5_6 , - dout6 => dout6_6 - ); - --- Register file 7. -regfile_7_i : regfile - Generic map ( - -- Data width. - B => B , - -- Map size. - N => N - ) - Port map ( - -- Clock. - clk => clk , - - -- Read address. - addr0 => addr0 , - addr1 => addr1 , - addr2 => addr2 , - addr3 => addr3 , - addr4 => addr4 , - addr5 => addr5 , - addr6 => addr6 , - - -- Write address. - addr7 => addr7 , - - -- Write data. - din7 => din7 , - wen7 => wen7_7 , - - -- Output registers. - dout0 => dout0_7 , - dout1 => dout1_7 , - dout2 => dout2_7 , - dout3 => dout3_7 , - dout4 => dout4_7 , - dout5 => dout5_7 , - dout6 => dout6_7 - ); - - --- Registers. -process (clk) -begin - if ( rising_edge(clk) ) then - if ( rstn = '0' ) then - -- Pipe on page selection. - pnum_r <= (others => '0'); - else - -- Pipe on page selection. - pnum_r <= pnum; - end if; - end if; -end process; - --- Muxed write enable signals. -wen7_0 <= wen7 when pnum = "000" else '0'; -wen7_1 <= wen7 when pnum = "001" else '0'; -wen7_2 <= wen7 when pnum = "010" else '0'; -wen7_3 <= wen7 when pnum = "011" else '0'; -wen7_4 <= wen7 when pnum = "100" else '0'; -wen7_5 <= wen7 when pnum = "101" else '0'; -wen7_6 <= wen7 when pnum = "110" else '0'; -wen7_7 <= wen7 when pnum = "111" else '0'; - --- Muxed output data. -dout0_i <= dout0_0 when pnum_r = "000" else - dout0_1 when pnum_r = "001" else - dout0_2 when pnum_r = "010" else - dout0_3 when pnum_r = "011" else - dout0_4 when pnum_r = "100" else - dout0_5 when pnum_r = "101" else - dout0_6 when pnum_r = "110" else - dout0_7; - -dout1_i <= dout1_0 when pnum_r = "000" else - dout1_1 when pnum_r = "001" else - dout1_2 when pnum_r = "010" else - dout1_3 when pnum_r = "011" else - dout1_4 when pnum_r = "100" else - dout1_5 when pnum_r = "101" else - dout1_6 when pnum_r = "110" else - dout1_7; - -dout2_i <= dout2_0 when pnum_r = "000" else - dout2_1 when pnum_r = "001" else - dout2_2 when pnum_r = "010" else - dout2_3 when pnum_r = "011" else - dout2_4 when pnum_r = "100" else - dout2_5 when pnum_r = "101" else - dout2_6 when pnum_r = "110" else - dout2_7; - -dout3_i <= dout3_0 when pnum_r = "000" else - dout3_1 when pnum_r = "001" else - dout3_2 when pnum_r = "010" else - dout3_3 when pnum_r = "011" else - dout3_4 when pnum_r = "100" else - dout3_5 when pnum_r = "101" else - dout3_6 when pnum_r = "110" else - dout3_7; - -dout4_i <= dout4_0 when pnum_r = "000" else - dout4_1 when pnum_r = "001" else - dout4_2 when pnum_r = "010" else - dout4_3 when pnum_r = "011" else - dout4_4 when pnum_r = "100" else - dout4_5 when pnum_r = "101" else - dout4_6 when pnum_r = "110" else - dout4_7; - -dout5_i <= dout5_0 when pnum_r = "000" else - dout5_1 when pnum_r = "001" else - dout5_2 when pnum_r = "010" else - dout5_3 when pnum_r = "011" else - dout5_4 when pnum_r = "100" else - dout5_5 when pnum_r = "101" else - dout5_6 when pnum_r = "110" else - dout5_7; - -dout6_i <= dout6_0 when pnum_r = "000" else - dout6_1 when pnum_r = "001" else - dout6_2 when pnum_r = "010" else - dout6_3 when pnum_r = "011" else - dout6_4 when pnum_r = "100" else - dout6_5 when pnum_r = "101" else - dout6_6 when pnum_r = "110" else - dout6_7; - --- Assign outputs. -dout0 <= dout0_i; -dout1 <= dout1_i; -dout2 <= dout2_i; -dout3 <= dout3_i; -dout4 <= dout4_i; -dout5 <= dout5_i; -dout6 <= dout6_i; - -end rtl; - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/s_axis_read.vhd b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/s_axis_read.vhd deleted file mode 100644 index 74d52b1..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/s_axis_read.vhd +++ /dev/null @@ -1,53 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity s_axis_read is - Generic ( - -- Data width. - B : Integer := 16 - ); - Port ( - -- Clock and reset. - clk : in std_logic; - rstn : in std_logic; - - -- AXIS Slave. - s_axis_tdata : in std_logic_vector (B-1 downto 0); - s_axis_tvalid : in std_logic; - s_axis_tready : out std_logic; - - -- Output data. - dout : out std_logic_vector (B-1 downto 0) - ); -end s_axis_read; - -architecture rtl of s_axis_read is - --- Data register. -signal data_r : std_logic_vector (B-1 downto 0); - -begin - --- Registers. -process (clk) -begin - if ( rising_edge(clk) ) then - if ( rstn = '0' ) then - -- Data register. - data_r <= (others => '0'); - else - -- Data register. - if ( s_axis_tvalid = '1' ) then - data_r <= s_axis_tdata; - end if; - end if; - end if; -end process; - --- Assign outputs. -s_axis_tready <= '1'; -dout <= data_r; - -end rtl; - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/soft/compile.pl b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/soft/compile.pl deleted file mode 100644 index 6c417c6..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/soft/compile.pl +++ /dev/null @@ -1,824 +0,0 @@ -#!/usr/bin/perl - -# Input program file. -open(FD,"<","$ARGV[0]"); -@lines = ; - -# Output binary file. -$out_file = $ARGV[0]; -$out_file =~ s/.asm/.bin/; -open(FD_OUT,">","$out_file"); - -# Output dump file. -$out_file_dump = $out_file . "-dump"; -open(FD_OUT_DUMP,">","$out_file_dump"); - -# Hash for data structures. -my @hash = (); - -# Instruction coding. -# I-type. -$hash{instructions}{pushi}{bin} = "00010000"; -$hash{instructions}{popi}{bin} = "00010001"; -$hash{instructions}{mathi}{bin} = "00010010"; -$hash{instructions}{seti}{bin} = "00010011"; -$hash{instructions}{synci}{bin} = "00010100"; -$hash{instructions}{waiti}{bin} = "00010101"; -$hash{instructions}{bitwi}{bin} = "00010110"; -$hash{instructions}{memri}{bin} = "00010111"; -$hash{instructions}{memwi}{bin} = "00011000"; -$hash{instructions}{regwi}{bin} = "00011001"; -$hash{instructions}{setbi}{bin} = "00011010"; - -# J-type. -$hash{instructions}{loopnz}{bin} = "00110000"; -$hash{instructions}{condj}{bin} = "00110001"; -$hash{instructions}{end}{bin} = "00111111"; - -# R-type. -$hash{instructions}{math}{bin} = "01010000"; -$hash{instructions}{set}{bin} = "01010001"; -$hash{instructions}{sync}{bin} = "01010010"; -$hash{instructions}{read}{bin} = "01010011"; -$hash{instructions}{wait}{bin} = "01010100"; -$hash{instructions}{bitw}{bin} = "01010101"; -$hash{instructions}{memr}{bin} = "01010110"; -$hash{instructions}{memw}{bin} = "01010111"; -$hash{instructions}{setb}{bin} = "01011000"; - -###################################### -### First pass: parse instructions ### -###################################### -my $addr = 0; -foreach $line (@lines) -{ - chomp ($line); - - # Empty lines. - if ( $line =~ m/^\s*$/ ) - { - - } - - # Comments. - elsif ( $line =~ m/^\s*\/\// ) - { - #print "$line\n"; - } - - # Tagged instruction (for Jump). - elsif ( $line =~ m/\s*(.+)\s*:(.+);/ ) - { - my $ref = $1; - my $inst = $2; - - # Add reference entry into hash. - $hash{refs}{$ref} = $addr; - - # Parse instruction. - &parse_inst(\%hash, $inst, $addr); - - # Increment memory address. - $addr++; - } - else - { - my $inst = $line; - - # Parse instruction. - &parse_inst(\%hash, $inst, $addr); - - # Increment memory address. - $addr++; - } -} - -####################################### -### Second Pass: resolve references ### -####################################### -&resolve_refs(\%hash); - -############################### -### Convert to machine code ### -############################### -&convert(\%hash); - -############################ -### Generate output file ### -############################ -@mems = (sort {$a <=> $b} keys %{$hash{memory}}); -foreach $mem (@mems) -{ - $inst = $hash{memory}{$mem}{orig}; - $bin = $hash{memory}{$mem}{bin}; - print FD_OUT "$bin\n"; -} - -########################## -### Generate DUMP file ### -########################## -print FD_OUT_DUMP "#######################\n"; -print FD_OUT_DUMP "### Memory Contents ###\n"; -print FD_OUT_DUMP "#######################\n"; -@mems = (sort {$a <=> $b} keys %{$hash{memory}}); -foreach $mem (@mems) -{ - $inst = $hash{memory}{$mem}{orig}; - $bin = $hash{memory}{$mem}{bin}; - $hex = $hash{memory}{$mem}{hex}; - print FD_OUT_DUMP "$mem\t: $hex -> $inst\n"; -} -print FD_OUT_DUMP "\n"; - -print FD_OUT_DUMP "###############\n"; -print FD_OUT_DUMP "### Symbols ###\n"; -print FD_OUT_DUMP "###############\n"; -@refs = keys %{$hash{refs}}; -foreach $ref (@refs) -{ - $addr = $hash{refs}{$ref}; - print FD_OUT_DUMP "$ref\t: $addr\n"; -} -print FD_OUT_DUMP "\n"; - -#################### -### Sub Routines ### -#################### -sub parse_inst -{ - my ($hash_ref, $inst, $addr) = @_; - - # Remove leading spaces from instruction. - $inst =~ s/^\s+//; - - # Remove trailing comments from instruction. - $inst =~ s/\s*\/\/.+$//; - - # Remove trailing ; - $inst =~ s/;//; - - ############## - ### I-Type ### - ############## - - # pushi p, $ra, $rb, imm - if ( $inst =~ m/pushi\s+(\d+)\s*,\s*\$(\d+)\s*,\s*\$(\d+)\s*,\s*(\-{0,1}\d+)/ ) - { - my $page = $1; - my $ra = $2; - my $rb = $3; - my $imm = $4; - - # Push instruction into hash. - $$hash_ref{memory}{$addr}{inst} = "I-type:pushi:$page:0:0:$rb:$ra:0:$imm"; - $$hash_ref{memory}{$addr}{orig} = $inst; - } - - # popi p, $r - if ( $inst =~ m/popi\s+(\d+)\s*,\s*\$(\d+)/ ) - { - my $page = $1; - my $r = $2; - - # Push instruction into hash. - $$hash_ref{memory}{$addr}{inst} = "I-type:popi:$page:0:0:$r:0:0:0"; - $$hash_ref{memory}{$addr}{orig} = $inst; - } - - # mathi p, $ra, $rb oper imm. - if ( $inst =~ m/mathi\s+(\d+)\s*,\s*\$(\d+)\s*,\s*\$(\d+)\s*([\+\-\*])\s*(0?x?\-?[0-9a-fA-F]+)/) - { - my $page = $1; - my $ra = $2; - my $rb = $3; - my $oper = $4; - my $imm = $5; - - # Push instruction into hash. - $$hash_ref{memory}{$addr}{inst} = "I-type:mathi:$page:0:$oper:$ra:$rb:0:$imm"; - $$hash_ref{memory}{$addr}{orig} = $inst; - } - - # seti ch, p, $r, t - if ( $inst =~ m/seti\s+(\d+)\s*,\s*(\d+)\s*,\s*\$(\d+)\s*,\s*(0?x?[0-9a-fA-F]+)/) - { - my $ch = $1; - my $page = $2; - my $ra = $3; - my $t = $4; - - # Push instruction into hash. - $$hash_ref{memory}{$addr}{inst} = "I-type:seti:$page:$ch:0:0:$ra:0:$t"; - $$hash_ref{memory}{$addr}{orig} = $inst; - } - - # synci t - if ( $inst =~ m/synci\s+(\d+)/) - { - my $t = $1; - - # Push instruction into hash. - $$hash_ref{memory}{$addr}{inst} = "I-type:synci:0:0:0:0:0:0:$t"; - $$hash_ref{memory}{$addr}{orig} = $inst; - } - - # waiti ch, t - if ( $inst =~ m/waiti\s+(\d+),\s*(\d+)/) - { - my $ch = $1; - my $t = $2; - - # Push instruction into hash. - $$hash_ref{memory}{$addr}{inst} = "I-type:waiti:0:$ch:0:0:0:0:$t"; - $$hash_ref{memory}{$addr}{orig} = $inst; - } - - # bitwi p, $ra, $rb oper imm. - if ( $inst =~ m/bitwi\s+(\d+)\s*,\s*\$(\d+),\s*\$(\d+)\s*([&|<>^]+)\s*(0?x?\-?[0-9a-fA-F]+)/) - { - - my $page = $1; - my $ra = $2; - my $rb = $3; - my $oper = $4; - my $imm = $5; - - # Push instruction into hash. - $$hash_ref{memory}{$addr}{inst} = "I-type:bitwi:$page:0:$oper:$ra:$rb:0:$imm"; - $$hash_ref{memory}{$addr}{orig} = $inst; - } - - # bitwi p, $ra, ~imm. - if ( $inst =~ m/bitwi\s+(\d+)\s*,\s*\$(\d+),\s*~\s*(0?x?\-?[0-9a-fA-F]+)/) - { - - my $page = $1; - my $ra = $2; - my $oper = "~"; - my $imm = $3; - - # Push instruction into hash. - $$hash_ref{memory}{$addr}{inst} = "I-type:bitwi:$page:0:$oper:$ra:0:0:$imm"; - $$hash_ref{memory}{$addr}{orig} = $inst; - } - - # memri p, $r, imm. - if ( $inst =~ m/memri\s+(\d+)\s*,\s*\$(\d+),\s*(0?x?\-?[0-9a-fA-F]+)/) - { - - my $page = $1; - my $r = $2; - my $imm = $3; - - # Push instruction into hash. - $$hash_ref{memory}{$addr}{inst} = "I-type:memri:$page:0:0:$r:0:0:$imm"; - $$hash_ref{memory}{$addr}{orig} = $inst; - } - - # memwi p, $r, imm. - if ( $inst =~ m/memwi\s+(\d+)\s*,\s*\$(\d+),\s*(0?x?\-?[0-9a-fA-F]+)/) - { - - my $page = $1; - my $r = $2; - my $imm = $3; - - # Push instruction into hash. - $$hash_ref{memory}{$addr}{inst} = "I-type:memwi:$page:0:0:0:0:$r:$imm"; - $$hash_ref{memory}{$addr}{orig} = $inst; - } - - # regwi p, $r, imm. - if ( $inst =~ m/regwi\s+(\d+)\s*,\s*\$(\d+),\s*(0?x?\-?[0-9a-fA-F]+)/) - { - - my $page = $1; - my $r = $2; - my $imm = $3; - - # Push instruction into hash. - $$hash_ref{memory}{$addr}{inst} = "I-type:regwi:$page:0:0:$r:0:0:$imm"; - $$hash_ref{memory}{$addr}{orig} = $inst; - } - - # setbi ch, p, $r, t - if ( $inst =~ m/setbi\s+(\d+)\s*,\s*(\d+)\s*,\s*\$(\d+)\s*,\s*(0?x?[0-9a-fA-F]+)/) - { - my $ch = $1; - my $page = $2; - my $ra = $3; - my $t = $4; - - # Push instruction into hash. - $$hash_ref{memory}{$addr}{inst} = "I-type:setbi:$page:$ch:0:0:$ra:0:$t"; - $$hash_ref{memory}{$addr}{orig} = $inst; - } - - ############## - ### J-Type ### - ############## - - # loopnz p, $r, @label - if ( $inst =~ m/loopnz\s+(\d+)\s*,\s*\$(\d+)\s*,\s*\@(.+)/) - { - my $page = $1; - my $oper = "+"; - my $r = $2; - my $label = $3; - - # Push instruction into hash. - $$hash_ref{memory}{$addr}{inst} = "J-type:loopnz:$page:$oper:$r:$r:0:\@$label"; - $$hash_ref{memory}{$addr}{orig} = $inst; - } - - # condj p, $ra op $rb, @label - if ( $inst =~ m/condj\s+(\d+)\s*,\s*\$(\d+)\s*([<>=!]+)\s*\$(\d+)\s*,\s*\@(.+)/) - { - my $page = $1; - my $ra = $2; - my $op = $3; - my $rb = $4; - my $label = $5; - - # Push instruction into hash. - $$hash_ref{memory}{$addr}{inst} = "J-type:condj:$page:$op:0:$ra:$rb:\@$label"; - $$hash_ref{memory}{$addr}{orig} = $inst; - } - - # end - if ( $inst =~ m/end/ ) - { - # Push instruction into hash. - $$hash_ref{memory}{$addr}{inst} = "J-type:end:0:0:0:0:0:0"; - $$hash_ref{memory}{$addr}{orig} = $inst; - } - - ############## - ### R-Type ### - ############## - - # math p, $ra, $rb oper $rc - if ( $inst =~ m/math\s+(\d+)\s*,\s*\$(\d+)\s*,\s*\$(\d+)\s*([\+\-\*]+)\s*\$(\d+)/) - { - my $page = $1; - my $ra = $2; - my $rb = $3; - my $oper = $4; - my $rc = $5; - - # Push instruction into hash. - $$hash_ref{memory}{$addr}{inst} = "R-type:math:$page:0:$oper:$ra:$rb:$rc:0:0:0:0:0"; - $$hash_ref{memory}{$addr}{orig} = $inst; - } - - # set ch, p, $ra, $rb, $rc, $rd, $re, $rt - if ( $inst =~ m/set\s+(\d+)\s*,\s*(\d+)\s*,\s*\$(\d+)\s*,\s*\$(\d+),\s*\$(\d+),\s*\$(\d+),\s*\$(\d+),\s*\$(\d+)/) - { - my $ch = $1; - my $page = $2; - my $ra = $3; - my $rb = $4; - my $rc = $5; - my $rd = $6; - my $re = $7; - my $rt = $8; - - # Push instruction into hash. - $$hash_ref{memory}{$addr}{inst} = "R-type:set:$page:$ch:0:0:$ra:$rt:$rb:$rc:$rd:$re:0"; - $$hash_ref{memory}{$addr}{orig} = $inst; - } - - # sync p, $r - if ( $inst =~ m/sync\s+(\d+)\s*,\s*\$(\d+)/) - { - my $page = $1; - my $r = $2; - - # Push instruction into hash. - $$hash_ref{memory}{$addr}{inst} = "R-type:sync:$page:0:0:0:0:$r:0:0:0:0:0"; - $$hash_ref{memory}{$addr}{orig} = $inst; - } - - # read ch, p, oper $r - if ( $inst =~ m/read\s+(\d+)\s*,\s*(\d+)\s*,\s*(upper|lower)\s+\$(\d+)/) - { - my $ch = $1; - my $page = $2; - my $oper = $3; - my $ra = $4; - - # Push instruction into hash. - $$hash_ref{memory}{$addr}{inst} = "R-type:read:$page:$ch:$oper:$ra:0:0:0:0:0:0:0"; - $$hash_ref{memory}{$addr}{orig} = $inst; - } - - # wait ch, p, $r - if ( $inst =~ m/wait\s+(\d+)\s*,\s*(\d+)\s*,\s*\$(\d+)/) - { - my $ch = $1; - my $page = $2; - my $r = $3; - - # Push instruction into hash. - $$hash_ref{memory}{$addr}{inst} = "R-type:wait:$page:$ch:0:0:0:$r:0:0:0:0:0"; - $$hash_ref{memory}{$addr}{orig} = $inst; - } - - # bitw p, $ra, $rb oper $rc - if ( $inst =~ m/bitw\s+(\d+)\s*,\s*\$(\d+),\s*\$(\d+)\s*([&|<>^]+)\s*\$(\d+)/) - { - - my $page = $1; - my $ra = $2; - my $rb = $3; - my $oper = $4; - my $rc = $5; - - - # Push instruction into hash. - $$hash_ref{memory}{$addr}{inst} = "R-type:bitw:$page:0:$oper:$ra:$rb:$rc:0:0:0:0:0"; - $$hash_ref{memory}{$addr}{orig} = $inst; - } - - # bitw p, $ra, ~$rb. - if ( $inst =~ m/bitw\s+(\d+)\s*,\s*\$(\d+),\s*~\s*\$(\d+)/) - { - - my $page = $1; - my $ra = $2; - my $oper = "~"; - my $rb = $3; - - # Push instruction into hash. - $$hash_ref{memory}{$addr}{inst} = "R-type:bitw:$page:0:$oper:$ra:0:$rb:0:0:0:0:0"; - $$hash_ref{memory}{$addr}{orig} = $inst; - } - - # memr p, $ra, $rb - if ( $inst =~ m/memr\s+(\d+)\s*,\s*\$(\d+),\s*\$(\d+)\s*/) - { - - my $page = $1; - my $ra = $2; - my $rb = $3; - - # Push instruction into hash. - $$hash_ref{memory}{$addr}{inst} = "R-type:memr:$page:0:0:$ra:$rb:0:0:0:0:0:0"; - $$hash_ref{memory}{$addr}{orig} = $inst; - } - - # memr p, $ra, $rb - if ( $inst =~ m/memw\s+(\d+)\s*,\s*\$(\d+),\s*\$(\d+)\s*/) - { - - my $page = $1; - my $ra = $2; - my $rb = $3; - - # Push instruction into hash. - $$hash_ref{memory}{$addr}{inst} = "R-type:memw:$page:0:0:0:$rb:$ra:0:0:0:0:0"; - $$hash_ref{memory}{$addr}{orig} = $inst; - } - - # setb ch, p, $ra, $rb, $rc, $rd, $re, $rt - if ( $inst =~ m/setb\s+(\d+)\s*,\s*(\d+)\s*,\s*\$(\d+)\s*,\s*\$(\d+),\s*\$(\d+),\s*\$(\d+),\s*\$(\d+),\s*\$(\d+)/) - { - my $ch = $1; - my $page = $2; - my $ra = $3; - my $rb = $4; - my $rc = $5; - my $rd = $6; - my $re = $7; - my $rt = $8; - - # Push instruction into hash. - $$hash_ref{memory}{$addr}{inst} = "R-type:setb:$page:$ch:0:0:$ra:$rt:$rb:$rc:$rd:$re:0"; - $$hash_ref{memory}{$addr}{orig} = $inst; - } -} - -sub resolve_refs -{ - my ($hash_ref) = @_; - - my @mems = (sort {$a <=> $b} keys %{$$hash_ref{memory}}); - foreach $mem (@mems) - { - my $inst = $hash{memory}{$mem}{inst}; - - if ( $inst =~ m/\@(.+)$/ ) - { - my $ref = $1; - - # Get symbol from table. - if ( exists $$hash_ref{refs}{$ref} ) - { - # Get symbol address. - my $addr = $$hash_ref{refs}{$ref}; - - # Replace symbol with actual address. - $inst =~ s/\@(.+)$/$addr/; - - # Write value back into hash. - $$hash_ref{memory}{$mem}{inst} = $inst; - } - else - { - print "ERROR: Could not resolve $ref symbol. Aborting.\n"; - exit(0); - } - } - } -} - -sub convert -{ - my ($hash_ref) = @_; - - my @mems = (sort {$a <=> $b} keys %{$$hash_ref{memory}}); - foreach $mem (@mems) - { - # Get instructions. - my $inst = $$hash_ref{memory}{$mem}{inst}; - - # Split parameters. - my @params = split(/:/,$inst); - - # I-type instruction. - # I-type:opcode:page:channel:oper:ra:rb:imm. - if ( $params[0] eq "I-type" ) - { - # Translate instruction to machine code. - if ( exists $$hash_ref{instructions}{$params[1]} ) - { - my $i = $$hash_ref{instructions}{$params[1]}{bin}; - my $page = &unsigned2bin($params[2],3); - my $ch = &unsigned2bin($params[3],3); - my $oper = &oper2bin($params[4]); - my $ra = &unsigned2bin($params[5],5); - my $rb = &unsigned2bin($params[6],5); - my $rc = &unsigned2bin($params[7],5); - my $imm = &integer2bin($params[8],31); - - my $code = $i . $page . $ch . $oper . $ra . $rb . $rc . $imm; - my $code_h = sprintf("%x", oct("0b$code")); - - # Write binary value back into hash. - $$hash_ref{memory}{$mem}{bin} = $code; - $$hash_ref{memory}{$mem}{hex} = $code_h; - } - else - { - print "ERROR: Instruction $params[1] not found in catalog. Aborting.\n"; - exit(1); - } - } - - # J-type instruction. - # J-type:opcode:page:oper:ra:rb:rc:addr. - if ( $params[0] eq "J-type" ) - { - # Translate instruction to machine code. - if ( exists $$hash_ref{instructions}{$params[1]} ) - { - my $i = $$hash_ref{instructions}{$params[1]}{bin}; - my $page = &unsigned2bin($params[2],3); - my $z3 = &unsigned2bin(0,3); - my $oper = &oper2bin($params[3]); - my $ra = &unsigned2bin($params[4],5); - my $rb = &unsigned2bin($params[5],5); - my $rc = &unsigned2bin($params[6],5); - my $z15 = &unsigned2bin(0,15); - my $addr = &unsigned2bin($params[7],16); - - my $code = $i . $page . $z3 . $oper . $ra . $rb . $rc . $z15 . $addr; - my $code_h = sprintf("%x", oct("0b$code")); - - # Write binary value back into hash. - $$hash_ref{memory}{$mem}{bin} = $code; - $$hash_ref{memory}{$mem}{hex} = $code_h; - } - else - { - print "ERROR: Instruction $params[1] not found in catalog. Aborting.\n"; - exit(1); - } - - } - - # R-type instruction. - # R-type:opcode:page:channel:oper:ra:rb:rc:rd:re:rf:rg:rh. - if ( $params[0] eq "R-type" ) - { - # Translate instruction to machine code. - if ( exists $$hash_ref{instructions}{$params[1]} ) - { - my $i = $$hash_ref{instructions}{$params[1]}{bin}; - my $page = &unsigned2bin($params[2],3); - my $ch = &unsigned2bin($params[3],3); - my $oper = &oper2bin($params[4]); - my $ra = &unsigned2bin($params[5],5); - my $rb = &unsigned2bin($params[6],5); - my $rc = &unsigned2bin($params[7],5); - my $rd = &unsigned2bin($params[8],5); - my $re = &unsigned2bin($params[9],5); - my $rf = &unsigned2bin($params[10],5); - my $rg = &unsigned2bin($params[11],5); - my $rh = &unsigned2bin($params[12],5); - my $z6 = &unsigned2bin(0,6); - - my $code = $i . $page . $ch . $oper . $ra . $rb . $rc . $rd . $re . $rf . $rg . $rh . $z6; - my $code_h = sprintf("%x", oct("0b$code")); - - # Write binary value back into hash. - $$hash_ref{memory}{$mem}{bin} = $code; - $$hash_ref{memory}{$mem}{hex} = $code_h; - } - else - { - print "ERROR: Instruction $params[1] not found in catalog. Aborting.\n"; - exit(1); - } - } - - } -} - -sub integer2bin -{ - my $dec = shift; - my $bits = shift; - - # Number goes from -2^(bits-1) to 2^(bits-1) - 1 - $min = -2**($bits-1); - $max = 2**($bits-1) - 1; - - # Check if number is 0x form. - if ( $dec =~ m/0x/ ) - { - my $mmax = 2**$bits - 1; - - $dec = hex($dec); - - if ( $dec > $mmax ) - { - print "ERROR: number $dec bigger than $mmax\n"; - exit(1); - } - - # Perform conversion. - $f = "." . $bits . "b"; - return sprintf("%$f", $dec); - } - - # Check maximum and minimum. - if ( $dec < $min ) - { - print "ERROR: number $dec smaller than $min\n"; - exit(1); - } - - if ( $dec > $max ) - { - print "ERROR: number $dec bigger than $max\n"; - exit(1); - } - - # Check if number is negative. - if ( $dec < 0 ) - { - $dec = $dec + 2**$bits; - } - - # Perform conversion. - $f = "." . $bits . "b"; - return sprintf("%$f", $dec); -} - -sub unsigned2bin -{ - my $dec = shift; - my $bits = shift; - - # Number goes from 0 to 2^(bits-1) - 1 - $max = 2**$bits - 1; - - # Check if number is 0x form. - if ( $dec =~ m/0x/ ) - { - $dec = hex($dec); - } - - if ( $dec > $max ) - { - print "ERROR: number $dec bigger than $max\n"; - exit(1); - } - - # Perform conversion. - $f = "." . $bits . "b"; - return sprintf("%$f", $dec); -} - -sub oper2bin -{ - my $op = shift; - - if ( $op eq "0" ) - { - return "0000"; - } - - # Conditional block. - elsif ( $op eq ">" ) - { - return "0000"; - } - elsif ( $op eq ">=" ) - { - return "0001"; - } - elsif ( $op eq "<" ) - { - return "0010"; - } - elsif ( $op eq "<=" ) - { - return "0011"; - } - elsif ( $op eq "==" ) - { - return "0100"; - } - elsif ( $op eq "!=" ) - { - return "0101"; - } - - # Alu (math). - elsif ( $op eq "+" ) - { - return "1000"; - } - - elsif ( $op eq "-" ) - { - return "1001"; - } - - elsif ( $op eq "*" ) - { - return "1010"; - } - - # Alu (bitw). - elsif ( $op eq "&" ) - { - return "0000"; - } - - elsif ( $op eq "|" ) - { - return "0001"; - } - - elsif ( $op eq "^" ) - { - return "0010"; - } - - elsif ( $op eq "~" ) - { - return "0011"; - } - - elsif ( $op eq "<<" ) - { - return "0100"; - } - - elsif ( $op eq ">>" ) - { - return "0101"; - } - - # Read (upper/lower bits). - elsif ( $op eq "upper" ) - { - return "1010"; - } - - elsif ( $op eq "lower" ) - { - return "0101"; - } - - # Not recognized. - else - { - print "ERROR: operation $op not recognized. Aborting\n"; - } - -} - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/soft/prog.asm b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/soft/prog.asm deleted file mode 100644 index 04e24b2..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/soft/prog.asm +++ /dev/null @@ -1,15 +0,0 @@ - // $1: periodic mode. - regwi 0, $1, 33; - regwi 0, $2, 1; - bitwi 0, $2, $2 << 16; - bitw 0, $1, $1 | $2; - - // $4: non-periodic mode. - regwi 0, $4, 500; - - regwi 1, $1, 100; // i -LOOP: setbi 7, 0, $4, 0; - loopnz 1, $1, @LOOP; - - end; - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/soft/prog.asm.old b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/soft/prog.asm.old deleted file mode 100644 index bf00ba5..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/soft/prog.asm.old +++ /dev/null @@ -1,84 +0,0 @@ -// Read input ports. - read 0, 2, upper $3; - read 0, 2, lower $4; - read 1, 0, upper $3; - read 1, 0, lower $4; - read 2, 0, upper $5; - read 2, 0, lower $6; - read 3, 1, upper $1; - read 3, 1, lower $2; - -// Basic math. - regwi 0, $1, 0x1234; - regwi 0, $2, -1234; - regwi 0, $3, 7; - -LOOP: math 0, $1, $1 + $2; - loopnz 0, $3, @LOOP; - - // Some time offset to start. - synci 1000; - -// Nested loops and stack. - regwi 0, $9, 0; // memory address. - regwi 0, $1, -5000; // df - regwi 0, $3, 34; // dg - regwi 0, $5, 100; // dn - regwi 0, $8, 50; // t - - regwi 0, $2, 120000; // freq - regwi 0, $7, 5; // i = 5 - -// Loop freq. -FREQ: math 0, $2, $2 + $1; // freq = freq + df - regwi 0, $4, 120; // gain = 120 - pushi 0, $7, $7, 3; // i -> stack, j = 3 - - // Loop gain. - GAIN: math 0, $4, $4 + $3; // gain = gain + dg - regwi 0, $6, 25; // nsamples = 25 - pushi 0, $7, $7, 6; // j -> stack, k = 6 - - // Loop nsamp. - NSAMP: math 0, $6, $6 + $5; // nsamp = nsamp + dn - // Output value on port. - set 0, 0, $2, $0, $4, $0, $6, $7; - synci 150; - loopnz 0, $7, @NSAMP; // loop k - - popi 0, $7; // stack -> j - loopnz 0, $7, @GAIN; // loop j - - popi 0, $7; // stack -> i - memw 0, $2, $9; // freq -> mem[$9] - mathi 0, $9, $9 + 1; - loopnz 0, $7, @FREQ; // loop i - -// Signal end of first pass. - regwi 0, $1, 0x0ABCD; - regwi 0, $2, 0x01234; - memwi 0, $1, 100; // mem[100] = 0x0ABCD - memwi 0, $0, 101; // mem[101] = 0 -WAITF0: memri 0, $1, 101; // $1 = mem[101] - condj 0, $1 != $2, @WAITF0; - -// Wait memory upload. - regwi 0, $1, 0x0ABCD; - regwi 0, $2, 0x01234; - memwi 0, $1, 100; // mem[100] = 0x0ABCD - memwi 0, $0, 101; // mem[101] = 0 -WAITF1: memri 0, $1, 101; // $1 = mem[101] - condj 0, $1 != $2, @WAITF1; - -// Read/modify/write. - regwi 0, $1, 0; // Address. - regwi 0, $2, 54; // i. -LOOP0: memr 0, $3, $1; // $3 = mem[$1] - mathi 0, $3, $3*2; - memw 0, $3, $1; // mem[$1] = $3. - mathi 0, $1, $1 + 1; // Address = address + 1. - loopnz 0, $2, @LOOP0; - - // End of program. - end; - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/soft/prog.bin b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/soft/prog.bin deleted file mode 100644 index 135ef80..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/soft/prog.bin +++ /dev/null @@ -1,9 +0,0 @@ -0001100100000000000000100000000000000000000000000000000000100001 -0001100100000000000001000000000000000000000000000000000000000001 -0001011000000001000001000010000000000000000000000000000000010000 -0101010100000000010000100001000100000000000000000000000000000000 -0001100100000000000010000000000000000000000000000000000111110100 -0001100100100000000000100000000000000000000000000000000001100100 -0001101000011100000000000100000000000000000000000000000000000000 -0011000000100010000000100001000000000000000000000000000000000110 -0011111100000000000000000000000000000000000000000000000000000000 diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/soft/prog.bin-dump b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/soft/prog.bin-dump deleted file mode 100644 index 9c46e20..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/soft/prog.bin-dump +++ /dev/null @@ -1,18 +0,0 @@ -####################### -### Memory Contents ### -####################### -0 : 1900020000000021 -> regwi 0, $1, 33 -1 : 1900040000000001 -> regwi 0, $2, 1 -2 : 1601042000000010 -> bitwi 0, $2, $2 << 16 -3 : 5500421100000000 -> bitw 0, $1, $1 | $2 -4 : 19000800000001f4 -> regwi 0, $4, 500 -5 : 1920020000000064 -> regwi 1, $1, 100 -6 : 1a1c004000000000 -> setbi 7, 0, $4, 0 -7 : 3022021000000006 -> loopnz 1, $1, @LOOP -8 : 3f00000000000000 -> end - -############### -### Symbols ### -############### -LOOP : 6 - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/stack.vhd b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/stack.vhd deleted file mode 100644 index fe2f5b6..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/stack.vhd +++ /dev/null @@ -1,131 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - --- Stack block. --- --- Number of words: 256 (8 bits). --- op: --- * 0 : pop operation. --- * 1 : push operation. - -entity stack is - Generic ( - -- Data width. - B : Integer := 16 - ); - Port ( - -- Clock and reset. - clk : in std_logic; - rstn : in std_logic; - - -- Enable and operation. - en : in std_logic; - op : in std_logic; - - -- Input/Output data. - din : in std_logic_vector (B-1 downto 0); - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - empty : out std_logic; - full : out std_logic - ); -end stack; - -architecture rtl of stack is - --- Bram. -component bram is - Generic ( - -- Memory address size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port ( - clk : in std_logic; - ena : in std_logic; - wea : in std_logic; - addra : in std_logic_vector (N-1 downto 0); - dia : in std_logic_vector (B-1 downto 0); - doa : out std_logic_vector (B-1 downto 0) - ); -end component; - --- Memory signals. -signal mem_addr : std_logic_vector (7 downto 0); - --- Stack pointer (points to the address where the next data is written). -signal sp : unsigned (7 downto 0); -signal sp_1 : unsigned (7 downto 0); - --- Empty/full. -signal empty_i : std_logic; -signal full_i : std_logic; - -begin - --- Bram. -bram_i : bram - Generic map ( - -- Memory address size. - N => 8 , - -- Data width. - B => B - ) - Port map ( - clk => clk , - ena => en , - wea => op , - addra => mem_addr , - dia => din , - doa => dout - ); - --- Registers. -process (clk) -begin - if ( rising_edge(clk) ) then - if ( rstn = '0' ) then - -- Stack pointer. - sp <= (others => '1'); - else - -- Stack pointer. - if ( en = '1' ) then - if ( op = '1' ) then - -- Push. - if ( full_i = '0' ) then - -- If not full. - sp <= sp - 1; - end if; - else - -- Pop. - if ( empty_i = '0' ) then - -- If not empty. - sp <= sp + 1; - end if; - end if; - end if; - - end if; - end if; -end process; - --- Stack pointer + 1 (read address). -sp_1 <= sp + 1; - --- Mux for memory address. -mem_addr <= std_logic_vector (sp) when op = '1' else - std_logic_vector (sp_1); - --- Empty/full flags. -empty_i <= '1' when sp = 255 else '0'; -full_i <= '1' when sp = 0 else '0'; - --- Assign outputs. -empty <= empty_i; -full <= full_i; - -end rtl; - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/synchronizer_n.vhd b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/synchronizer_n.vhd deleted file mode 100644 index 925425d..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/synchronizer_n.vhd +++ /dev/null @@ -1,42 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library common_lib; -use common_lib.all; - -entity synchronizer_n is - generic ( - N : Integer := 2 - ); - port ( - rstn : in std_logic; - clk : in std_logic; - data_in : in std_logic; - data_out : out std_logic - ); -end synchronizer_n; - -architecture rtl of synchronizer_n is - --- Internal register. -signal data_int_reg : std_logic_vector (N-1 downto 0); - -begin - -process(clk) -begin - if (rising_edge(clk)) then - if (rstn = '0') then - data_int_reg <= (others => '0'); - else - data_int_reg <= data_int_reg(N-2 downto 0) & data_in; - end if; - end if; -end process; - --- Assign output. -data_out <= data_int_reg(N-1); - -end rtl; - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/tb/tb.sv b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/tb/tb.sv deleted file mode 100644 index 7a50b85..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/tb/tb.sv +++ /dev/null @@ -1,708 +0,0 @@ -// VIP: axi_mst_0 -// VIP: axis_mst_0 -// VIP: axis_slv_0 -// DUT: axis_tproc6664_x8 -// IF: s_axi -> axi_mst_0 -// IF: m0_axis -> axis_slv_0 -// IF: s0_axis -> axis_mst_0 - -import axi_vip_pkg::*; -import axi4stream_vip_pkg::*; -import axi_mst_0_pkg::*; -import axis_mst_0_pkg::*; -import axis_slv_0_pkg::*; - -module tb(); - -localparam PMEM_N = 16; // Program Memory Depth. -localparam DMEM_N = 10; // Data Memory Depth. -localparam DMEM_OFFSET = 256; - -/////////////////////// -// s_axi_aclk domain // -/////////////////////// -reg s_axi_aclk; -reg s_axi_aresetn; - -wire [31:0] s_axi_awaddr; -wire [2:0] s_axi_awprot; -wire s_axi_awvalid; -wire s_axi_awready; - -wire [31:0] s_axi_wdata; -wire [3:0] s_axi_wstrb; -wire s_axi_wvalid; -wire s_axi_wready; - -wire [1:0] s_axi_bresp; -wire s_axi_bvalid; -wire s_axi_bready; - -wire [31:0] s_axi_araddr; -wire [2:0] s_axi_arprot; -wire s_axi_arvalid; -wire s_axi_arready; - -wire [31:0] s_axi_rdata; -wire [1:0] s_axi_rresp; -wire s_axi_rvalid; -wire s_axi_rready; - -wire [31:0] s0_axis_tdata; -wire s0_axis_tlast; -wire s0_axis_tvalid; -wire s0_axis_tready; - -wire [31:0] m0_axis_tdata; -wire m0_axis_tlast; -wire m0_axis_tvalid; -wire m0_axis_tready; - -///////////////// -// aclk domain // -///////////////// -reg aclk; -reg aresetn; - -reg start; - -wire [PMEM_N-1:0] pmem_addr; -wire [63:0] pmem_do; - -reg [63:0] s1_axis_tdata; -reg s1_axis_tvalid; -wire s1_axis_tready; - -reg [63:0] s2_axis_tdata; -reg s2_axis_tvalid; -wire s2_axis_tready; - -reg [63:0] s3_axis_tdata; -reg s3_axis_tvalid; -wire s3_axis_tready; - -reg [63:0] s4_axis_tdata; -reg s4_axis_tvalid; -wire s4_axis_tready; - -wire [159:0] m1_axis_tdata; -wire m1_axis_tvalid; -reg m1_axis_tready; - -wire [159:0] m2_axis_tdata; -wire m2_axis_tvalid; -reg m2_axis_tready; - -wire [159:0] m3_axis_tdata; -wire m3_axis_tvalid; -reg m3_axis_tready; - -wire [159:0] m4_axis_tdata; -wire m4_axis_tvalid; -reg m4_axis_tready; - -wire [159:0] m5_axis_tdata; -wire m5_axis_tvalid; -reg m5_axis_tready; - -wire [159:0] m6_axis_tdata; -wire m6_axis_tvalid; -reg m6_axis_tready; - -wire [159:0] m7_axis_tdata; -wire m7_axis_tvalid; -reg m7_axis_tready; - -wire [159:0] m8_axis_tdata; -wire m8_axis_tvalid; -wire m8_axis_tready; - -xil_axi_prot_t prot = 0; -reg[31:0] data_wr = 32'h12345678; -reg[31:0] data; -xil_axi_resp_t resp; - -// Ready generator for axis slave. -axi4stream_ready_gen ready_gen_0; -// Program memory. -bram - #( - // Memory address size. - .N (PMEM_N ), - // Data width. - .B (64 ) - ) - pmem_i ( - .clk (aclk ), - .ena (1'b1 ), - .wea (1'b0 ), - .addra ({3'b000,pmem_addr[PMEM_N-1:3]} ), - .dia ({64{1'b0}} ), - .doa (pmem_do ) - ); - -// AXIS master. -axis_mst_0 axis_mst_0_i - ( - .aclk (s_axi_aclk ), - .aresetn (s_axi_aresetn ), - .m_axis_tdata (s0_axis_tdata ), - .m_axis_tlast (s0_axis_tlast ), - .m_axis_tready (s0_axis_tready ), - .m_axis_tstrb ( ), - .m_axis_tvalid (s0_axis_tvalid ) - ); - -// AXIS slave. -axis_slv_0 axis_slv_0_i - ( - .aclk (s_axi_aclk ), - .aresetn (s_axi_aresetn ), - .s_axis_tdata (m0_axis_tdata ), - .s_axis_tlast (m0_axis_tlast ), - .s_axis_tready (m0_axis_tready ), - .s_axis_tstrb ( ), - .s_axis_tvalid (m0_axis_tvalid ) - ); - -// AXI master. -axi_mst_0 axi_mst_0_i - ( - .aclk (s_axi_aclk ), - .aresetn (s_axi_aresetn ), - .m_axi_araddr (s_axi_araddr ), - .m_axi_arprot (s_axi_arprot ), - .m_axi_arready (s_axi_arready ), - .m_axi_arvalid (s_axi_arvalid ), - .m_axi_awaddr (s_axi_awaddr ), - .m_axi_awprot (s_axi_awprot ), - .m_axi_awready (s_axi_awready ), - .m_axi_awvalid (s_axi_awvalid ), - .m_axi_bready (s_axi_bready ), - .m_axi_bresp (s_axi_bresp ), - .m_axi_bvalid (s_axi_bvalid ), - .m_axi_rdata (s_axi_rdata ), - .m_axi_rready (s_axi_rready ), - .m_axi_rresp (s_axi_rresp ), - .m_axi_rvalid (s_axi_rvalid ), - .m_axi_wdata (s_axi_wdata ), - .m_axi_wready (s_axi_wready ), - .m_axi_wstrb (s_axi_wstrb ), - .m_axi_wvalid (s_axi_wvalid ) - ); - -// DUT. -axis_tproc64x32_x8 - DUT - ( - /////////////////////// - // s_axi_aclk domain // - /////////////////////// - .s_axi_aclk (s_axi_aclk ), - .s_axi_aresetn (s_axi_aresetn ), - - // AXI Slave I/F for configuration. - .s_axi_awaddr (s_axi_awaddr ), - .s_axi_awprot (s_axi_awprot ), - .s_axi_awvalid (s_axi_awvalid ), - .s_axi_awready (s_axi_awready ), - - .s_axi_wdata (s_axi_wdata ), - .s_axi_wstrb (s_axi_wstrb ), - .s_axi_wvalid (s_axi_wvalid ), - .s_axi_wready (s_axi_wready ), - - .s_axi_bresp (s_axi_bresp ), - .s_axi_bvalid (s_axi_bvalid ), - .s_axi_bready (s_axi_bready ), - - .s_axi_araddr (s_axi_araddr ), - .s_axi_arprot (s_axi_arprot ), - .s_axi_arvalid (s_axi_arvalid ), - .s_axi_arready (s_axi_arready ), - - .s_axi_rdata (s_axi_rdata ), - .s_axi_rresp (s_axi_rresp ), - .s_axi_rvalid (s_axi_rvalid ), - .s_axi_rready (s_axi_rready ), - - // Slave AXIS for writing into Data Memory. - .s0_axis_tdata (s0_axis_tdata ), - .s0_axis_tlast (s0_axis_tlast ), - .s0_axis_tvalid (s0_axis_tvalid ), - .s0_axis_tready (s0_axis_tready ), - - // Master AXIS 0 to read from Data Memory. - .m0_axis_tdata (m0_axis_tdata ), - .m0_axis_tlast (m0_axis_tlast ), - .m0_axis_tvalid (m0_axis_tvalid ), - .m0_axis_tready (m0_axis_tready ), - - ///////////////// - // aclk domain // - ///////////////// - .aclk (aclk ), - .aresetn (aresetn ), - - // Start/stop. - .start (start ), - - // Program Memory Interface. - .pmem_addr (pmem_addr ), - .pmem_do (pmem_do ), - - // Slave AXIS 0: "read" on tProcessor. - .s1_axis_tdata (s1_axis_tdata ), - .s1_axis_tvalid (s1_axis_tvalid ), - .s1_axis_tready (s1_axis_tready ), - - // Slave AXIS 1: "read" on tProcessor. - .s2_axis_tdata (s2_axis_tdata ), - .s2_axis_tvalid (s2_axis_tvalid ), - .s2_axis_tready (s2_axis_tready ), - - // Slave AXIS 2: "read" on tProcessor. - .s3_axis_tdata (s3_axis_tdata ), - .s3_axis_tvalid (s3_axis_tvalid ), - .s3_axis_tready (s3_axis_tready ), - - // Slave AXIS 3: "read" on tProcessor. - .s4_axis_tdata (s4_axis_tdata ), - .s4_axis_tvalid (s4_axis_tvalid ), - .s4_axis_tready (s4_axis_tready ), - - // Master AXIS 1 for Channel 0. - .m1_axis_tdata (m1_axis_tdata ), - .m1_axis_tvalid (m1_axis_tvalid ), - .m1_axis_tready (m1_axis_tready ), - - // Master AXIS 2 for Channel 1. - .m2_axis_tdata (m2_axis_tdata ), - .m2_axis_tvalid (m2_axis_tvalid ), - .m2_axis_tready (m2_axis_tready ), - - // Master AXIS 3 for Channel 2. - .m3_axis_tdata (m3_axis_tdata ), - .m3_axis_tvalid (m3_axis_tvalid ), - .m3_axis_tready (m3_axis_tready ), - - // Master AXIS 4 for Channel 3. - .m4_axis_tdata (m4_axis_tdata ), - .m4_axis_tvalid (m4_axis_tvalid ), - .m4_axis_tready (m4_axis_tready ), - - // Master AXIS 5 for Channel 4. - .m5_axis_tdata (m5_axis_tdata ), - .m5_axis_tvalid (m5_axis_tvalid ), - .m5_axis_tready (m5_axis_tready ), - - // Master AXIS 6 for Channel 5. - .m6_axis_tdata (m6_axis_tdata ), - .m6_axis_tvalid (m6_axis_tvalid ), - .m6_axis_tready (m6_axis_tready ), - - // Master AXIS 7 for Channel 6. - .m7_axis_tdata (m7_axis_tdata ), - .m7_axis_tvalid (m7_axis_tvalid ), - .m7_axis_tready (m7_axis_tready ), - - // Master AXIS 8 for Channel 7. - .m8_axis_tdata (m8_axis_tdata ), - .m8_axis_tvalid (m8_axis_tvalid ), - .m8_axis_tready (m8_axis_tready ) -); - -// Simple Signal Generator Simulator. -gen_sim - gen_sim_i - ( - .clk (aclk ), - .rstn (aresetn ), - .s_axis_tdata (m8_axis_tdata ), - .s_axis_tvalid (m8_axis_tvalid ), - .s_axis_tready (m8_axis_tready ) - ); - - -// VIP Agents -axi_mst_0_mst_t axi_mst_0_agent; -axis_mst_0_mst_t axis_mst_0_agent; -axis_slv_0_slv_t axis_slv_0_agent; - -initial begin - // Create agents. - axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); - axis_mst_0_agent = new("axis_mst_0 VIP Agent",tb.axis_mst_0_i.inst.IF); - axis_slv_0_agent = new("axis_slv_0 VIP Agent",tb.axis_slv_0_i.inst.IF); - - // Set tag for agents. - axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); - axis_mst_0_agent.set_agent_tag ("axis_mst_0 VIP"); - axis_slv_0_agent.set_agent_tag ("axis_slv_0 VIP"); - - // Drive everything to 0 to avoid assertion from axi_protocol_checker. - axis_mst_0_agent.vif_proxy.set_dummy_drive_type(XIL_AXI4STREAM_VIF_DRIVE_NONE); - axis_slv_0_agent.vif_proxy.set_dummy_drive_type(XIL_AXI4STREAM_VIF_DRIVE_NONE); - - // Ready generator. - ready_gen_0 = axis_slv_0_agent.driver.create_ready("ready gen 0"); - ready_gen_0.set_ready_policy(XIL_AXI4STREAM_READY_GEN_EVENTS); - ready_gen_0.set_low_time(5); - ready_gen_0.set_event_count(6); - - // Start agents. - axi_mst_0_agent.start_master(); - axis_mst_0_agent.start_master(); - axis_slv_0_agent.start_slave(); - - // Reset sequence. - s_axi_aresetn <= 0; - aresetn <= 0; - start <= 0; - s1_axis_tdata <= 0; - s1_axis_tvalid <= 0; - s2_axis_tdata <= 0; - s2_axis_tvalid <= 0; - s3_axis_tdata <= 0; - s3_axis_tvalid <= 0; - s4_axis_tdata <= 0; - s4_axis_tvalid <= 0; - m1_axis_tready <= 1; - m2_axis_tready <= 1; - m3_axis_tready <= 1; - m4_axis_tready <= 1; - m5_axis_tready <= 1; - m6_axis_tready <= 1; - m7_axis_tready <= 1; - #1000; - s_axi_aresetn <= 1; - aresetn <= 1; - - // Load program memory. - $readmemb("../../../../../soft/prog.bin", pmem_i.RAM); - - // Change ready policy for AXIS slave. - axis_slv_0_agent.driver.send_tready(ready_gen_0); - - #300; - - // Write input ports. - @(posedge aclk) - s1_axis_tdata <= 64'h12345678_87654321; - s1_axis_tvalid <= 1; - s2_axis_tdata <= 64'h55555555_aaaaaaaa; - s2_axis_tvalid <= 1; - s3_axis_tdata <= 64'habcdef00_01234567; - s3_axis_tvalid <= 1; - s4_axis_tdata <= 64'h01012323_ababcdcd; - s4_axis_tvalid <= 1; - - @(posedge aclk) - s1_axis_tvalid <= 0; - s2_axis_tvalid <= 0; - s3_axis_tvalid <= 0; - s4_axis_tvalid <= 0; - - - // Register Map: - // - // 0 : START_SRC_REG - // 1 : START_REG - // 2 : MEM_MODE_REG - // 3 : MEM_START_REG - // 4 : MEM_ADDR_REG - // 5 : MEM_LEN_REG - - // START_SRC_REG - // * 0 : Internal Start. - // * 1 : External Start. - data_wr = 0; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*0, prot, data_wr, resp); - #10; - - // START_REG - data_wr = 1; - axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*1, prot, data_wr, resp); - #10; - - #50000; - - //// Read back flag to signal start of next step. - //$display("#####################"); - //$display("### Wait for flag ###"); - //$display("#####################"); - //$display("t = %0t", $time); - - //// Flag: tProcessor data memory @100. - //// Memory is accessed using the upper part of the memory map. - //// Addresses are byte-based. - //// address = DMEM_OFFSET + 4*100 - //while (1) begin - // axi_mst_0_agent.AXI4LITE_READ_BURST(DMEM_OFFSET + 4*100, prot, data, resp); - // #200; - // - // if (data == 32'h0abcd) - // break; - //end - - //// Flag: tProcessor data memory @101. - //// Memory is accessed using the upper half of the memory map. - //// address = DMEM_OFFSET + 4*101 - //data_wr = 32'h01234; - //axi_mst_0_agent.AXI4LITE_WRITE_BURST(DMEM_OFFSET + 4*101, prot, data_wr, resp); - //#200; - // - - //// Single write. - //$display("##############################"); - //$display("### Single read/write mode ###"); - //$display("##############################"); - //$display("t = %0t", $time); - // - //// Write memory (upper address map). - //for (int i=0;i<55;i++) begin - // data_wr = i; - // axi_mst_0_agent.AXI4LITE_WRITE_BURST(DMEM_OFFSET + 4*i, prot, data_wr, resp); - // #10; - //end - - //#500; - - //// Read back flag to signal start of next step. - //$display("#####################"); - //$display("### Wait for flag ###"); - //$display("#####################"); - //$display("t = %0t", $time); - - //// Flag: tProcessor data memory @100. - //// Memory is accessed using the upper part of the memory map. - //// Addresses are byte-based. - //// address = DMEM_OFFSET + 4*100 - //while (1) begin - // axi_mst_0_agent.AXI4LITE_READ_BURST(DMEM_OFFSET + 4*100, prot, data, resp); - // #200; - // - // if (data == 32'h0abcd) - // break; - //end - - //// Flag: tProcessor data memory @101. - //// Memory is accessed using the upper half of the memory map. - //// address = DMEM_OFFSET + 4*101 - //data_wr = 32'h01234; - //axi_mst_0_agent.AXI4LITE_WRITE_BURST(DMEM_OFFSET + 4*101, prot, data_wr, resp); - //#200; - - //// Read back flag to signal end of transfer. - //$display("#####################################"); - //$display("### Wait for end-of-transfer flag ###"); - //$display("#####################################"); - //$display("t = %0t", $time); - - //// Flag: tProcessor data memory @200. - //// Memory is accessed using the upper half of the memory map. - //// address = 200 + 2^DMEM_N - //while (1) begin - // axi_mst_0_agent.AXI4LITE_READ_BURST(2**DMEM_N + 4*200, prot, data, resp); - // #200; - // - // if (data == 16'h5a5a) - // break; - //end - - //// AXIS read (from memory to m0_axis). - //$display("##########################################"); - //$display("### AXIS read (from memory to m0_axis) ###"); - //$display("##########################################"); - //$display("t = %0t", $time); - - ///* - // MEM_MODE_REG = 0; - // MEM_START_REG = 1; - // MEM_ADDR_REG = 0; - // MEM_LEN_REG = 100; - //*/ - - //// MEM_MODE_REG - //data_wr = 0; - //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*2, prot, data_wr, resp); - //#10; - - //// MEM_ADDR_REG - //data_wr = 0; - //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*4, prot, data_wr, resp); - //#10; - - //// MEM_LEN_REG - //data_wr = 100; - //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*5, prot, data_wr, resp); - //#10; - - //// MEM_START_REG - //data_wr = 1; - //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*3, prot, data_wr, resp); - //#10; - - //// Wait until transaction is done. - //while (1) begin - // @(posedge aclk); - // if (m0_axis_tlast == 1'b1 && m0_axis_tvalid == 1'b1 && m0_axis_tready == 1'b1) - // break; - //end - - //// MEM_START_REG - //data_wr = 0; - //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*3, prot, data_wr, resp); - //#10; - - //// AXIS write (from s0_axis to memory). - //$display("###########################################"); - //$display("### AXIS write (from s0_axis to memory) ###"); - //$display("###########################################"); - //$display("t = %0t", $time); - - ///* - // MEM_MODE_REG = 1; - // MEM_START_REG = 1; - // MEM_ADDR_REG = 50; - //*/ - - //// MEM_MODE_REG - //data_wr = 1; - //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*2, prot, data_wr, resp); - //#10; - - //// MEM_ADDR_REG - //data_wr = 50; - //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*4, prot, data_wr, resp); - //#10; - - //// MEM_START_REG - //data_wr = 1; - //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*3, prot, data_wr, resp); - //#10; - - //// Send data. - //fork - // gen_0(44,0); - //join - - //// MEM_START_REG - //data_wr = 0; - //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*3, prot, data_wr, resp); - //#10; - - //// Flag to signal data has been transferred. - //data_wr = 32'h0000cdef; - //axi_mst_0_agent.AXI4LITE_WRITE_BURST(2**DMEM_N + 4*200, prot, data_wr, resp); - //#10; - - //// Read back flag to signal end of memory operation. - //$display("######################################"); - //$display("### Wait for end-of-operation flag ###"); - //$display("######################################"); - //$display("t = %0t", $time); - - //// Flag: tProcessor data memory @200. - //// Memory is accessed using the upper half of the memory map. - //// address = 200 + 2^DMEM_N - //while (1) begin - // axi_mst_0_agent.AXI4LITE_READ_BURST(2**DMEM_N + 4*200, prot, data, resp); - // #200; - // - // if (data == 16'h5a5a) - // break; - //end - - //// AXIS read (from memory to m0_axis). - //$display("##########################################"); - //$display("### AXIS read (from memory to m0_axis) ###"); - //$display("##########################################"); - //$display("t = %0t", $time); - - ///* - // MEM_MODE_REG = 0; - // MEM_START_REG = 1; - // MEM_ADDR_REG = 50; - // MEM_LEN_REG = 44; - //*/ - - //// MEM_MODE_REG - //data_wr = 0; - //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*2, prot, data_wr, resp); - //#10; - - //// MEM_ADDR_REG - //data_wr = 50; - //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*4, prot, data_wr, resp); - //#10; - - //// MEM_LEN_REG - //data_wr = 44; - //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*5, prot, data_wr, resp); - //#10; - - //// MEM_START_REG - //data_wr = 1; - //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*3, prot, data_wr, resp); - //#10; - - //// Wait until transaction is done. - //while (1) begin - // @(posedge aclk); - // if (m0_axis_tlast == 1'b1 && m0_axis_tvalid == 1'b1 && m0_axis_tready == 1'b1) - // break; - //end - - //// MEM_START_REG - //data_wr = 0; - //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*3, prot, data_wr, resp); - //#10; - - #1000; - -end - -always -begin - s_axi_aclk <= 0; - #5; - s_axi_aclk <= 1; - #5; -end - -always -begin - aclk <= 0; - #1; - aclk <= 1; - #1; -end - -task gen_0(input int cnt, input int delay); - // Create transaction. - axi4stream_transaction wr_transaction; - wr_transaction = axis_mst_0_agent.driver.create_transaction("Master 0 VIP write transaction"); - - // Set transaction parameters. - wr_transaction.set_xfer_alignment(XIL_AXI4STREAM_XFER_RANDOM); - - // Send transactions. - for (int i=0; i < cnt-1; i++) - begin - WR_TRANSACTION_FAIL: assert(wr_transaction.randomize()); - wr_transaction.set_last(0); - wr_transaction.set_delay(delay); - axis_mst_0_agent.driver.send(wr_transaction); - end - - // Last. - WR_TRANSACTION_FAIL: assert(wr_transaction.randomize()); - wr_transaction.set_last(1); - wr_transaction.set_delay(delay); - axis_mst_0_agent.driver.send(wr_transaction); - -endtask - -endmodule - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/tb/tb_alu.sv b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/tb/tb_alu.sv deleted file mode 100644 index 20620cc..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/tb/tb_alu.sv +++ /dev/null @@ -1,82 +0,0 @@ -module tb(); - -// Data width. -localparam B = 32; - -reg clk; -reg rstn; -reg signed [B-1:0] din_a; -reg signed [B-1:0] din_b; -reg [3:0] op; -wire zero_a; -wire zero_b; -wire signed [B-1:0] dout; - -// DUT. -alu - #( - // Data width. - .B(32) - ) - DUT - ( - // Clock and reset. - .clk (clk ), - .rstn (rstn ), - - // Input operands. - .din_a (din_a ), - .din_b (din_b ), - - // Operation. - .op (op ), - - // Zero detection. - .zero_a (zero_a ), - .zero_b (zero_b ), - - // Output. - .dout (dout ) - ); - -initial begin - // Reset sequence. - rstn <= 0; - #1000; - rstn <= 1; - - // Addition. - @(posedge clk); - op <= 4'b1000; - din_a <= 53; - din_b <= -38; - - @(posedge clk); - din_a <= 530; - din_b <= -3000; - - // Substraction. - @(posedge clk); - op <= 4'b1001; - din_a <= 5830; - din_b <= 5830; - - // Product. - @(posedge clk); - op <= 4'b1010; - din_a <= 5830; - din_b <= 8; - - #1000; -end - -always -begin - clk <= 0; - #5; - clk <= 1; - #5; -end - -endmodule - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/timed_ictrl.vhd b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/timed_ictrl.vhd deleted file mode 100644 index c09ae5c..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/timed_ictrl.vhd +++ /dev/null @@ -1,204 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - --- Timed-instructions dispatcher control. --- --- 31 .. 0 : r0 --- 63 .. 32 : r1 --- 95 .. 64 : r2 --- 127 .. 96 : r3 --- 159 .. 128 : r4 --- 207 .. 160 : t --- 215 .. 208 : opcode -entity timed_ictrl is - Port ( - -- Clock and reset. - clk : in std_logic; - rstn : in std_logic; - - -- Master clock. - t_cnt : in unsigned (47 downto 0); - - -- Fifo Time control. - fifo_rd_en : out std_logic; - fifo_dout : in std_logic_vector (215 downto 0); - fifo_empty : in std_logic; - - -- Wait handshake. - waitt : out std_logic; - waitt_ack : in std_logic; - - -- Output AXIS. - m_axis_tdata : out std_logic_vector (159 downto 0); - m_axis_tvalid : out std_logic; - m_axis_tready : in std_logic - ); -end timed_ictrl; - -architecture rtl of timed_ictrl is - -type fsm_type is ( READ_ST , - WAIT_ST , - WAIT_ACK_ST , - SETI_ST , - SETBI_ST , - SET_ST , - SETB_ST ); - -signal state : fsm_type; - --- Time of actual instruction. -signal t_inst : unsigned (47 downto 0); - --- Parameters. -signal p0_i : std_logic_vector (31 downto 0); -signal p1_i : std_logic_vector (31 downto 0); -signal p2_i : std_logic_vector (31 downto 0); -signal p3_i : std_logic_vector (31 downto 0); -signal p4_i : std_logic_vector (31 downto 0); - --- Opcode. -signal opcode_i : std_logic_vector (7 downto 0); - -signal rd_en_i : std_logic; -signal tvalid_i : std_logic; - --- Wait handshake. -signal waitt_i : std_logic; - --- Output source. -signal src_i : std_logic; -- 0: 32 bits, 1: 128 bits. - --- Zeros. -signal zeros_128: std_logic_vector (127 downto 0) := (others => '0'); - -begin - --- Time of actual instruction. -t_inst <= unsigned (fifo_dout(207 downto 160)); - --- Parameters. -p0_i <= fifo_dout(31 downto 0); -p1_i <= fifo_dout(63 downto 32); -p2_i <= fifo_dout(95 downto 64); -p3_i <= fifo_dout(127 downto 96); -p4_i <= fifo_dout(159 downto 128); - --- Opcode. -opcode_i <= fifo_dout(215 downto 208); - --- Finite State Machine. -process (clk) -begin - if ( rising_edge(clk) ) then - if ( rstn = '0' ) then - state <= READ_ST; - else - case (state) is - when READ_ST => - if ( fifo_empty = '0' ) then - state <= WAIT_ST; - end if; - - when WAIT_ST => - if ( t_inst <= t_cnt ) then - -- waiti/wait - if ( opcode_i = "00010101" or opcode_i = "01010100") then - state <= WAIT_ACK_ST; - - -- seti - elsif ( opcode_i = "00010011" ) then - state <= SETI_ST; - - -- setbi - elsif ( opcode_i = "00011010" ) then - state <= SETBI_ST; - - -- set - elsif ( opcode_i = "01010001" ) then - state <= SET_ST; - - -- setb - elsif ( opcode_i = "01011000" ) then - state <= SETB_ST; - - -- Read next word. - else - state <= READ_ST; - - end if; - end if; - - when WAIT_ACK_ST => - if ( waitt_ack = '1' ) then - state <= READ_ST; - end if; - - when SETI_ST => - state <= READ_ST; - - when SETBI_ST => - if ( m_axis_tready = '1' ) then - state <= READ_ST; - end if; - - when SET_ST => - state <= READ_ST; - - when SETB_ST => - if ( m_axis_tready = '1' ) then - state <= READ_ST; - end if; - - end case; - end if; - end if; -end process; - --- Output logic. -process (state) -begin -rd_en_i <= '0'; -tvalid_i <= '0'; -waitt_i <= '0'; -src_i <= '0'; - case (state) is - when READ_ST => - rd_en_i <= '1'; - - when WAIT_ST => - - when WAIT_ACK_ST => - waitt_i <= '1'; - - when SETI_ST => - tvalid_i <= '1'; - src_i <= '0'; - - when SETBI_ST => - tvalid_i <= '1'; - src_i <= '0'; - - when SET_ST => - tvalid_i <= '1'; - src_i <= '1'; - - when SETB_ST => - tvalid_i <= '1'; - src_i <= '1'; - end case; -end process; - --- Assign outputs. -fifo_rd_en <= rd_en_i; - -waitt <= waitt_i; - -m_axis_tdata <= zeros_128 & p0_i when src_i = '0' else - p4_i & p3_i & p2_i & p1_i & p0_i; - -m_axis_tvalid <= tvalid_i; - -end rtl; - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/tproc64x32_x8.v b/qick/firmware/ip/axis_tproc64x32_x8_v1/src/tproc64x32_x8.v deleted file mode 100644 index d6a338a..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/src/tproc64x32_x8.v +++ /dev/null @@ -1,833 +0,0 @@ -module tproc64x32_x8 -( - // Clock and reset. - clk , - rstn , - - // Start/stop. - start , - - // Program Memory Interface. - pmem_addr , - pmem_do , - - // Data Memory Interface. - dmem_we , - dmem_addr , - dmem_di , - dmem_do , - - // Slave AXIS 0 for Input data. - s0_axis_tdata , - s0_axis_tvalid , - s0_axis_tready , - - // Slave AXIS 1 for Input data. - s1_axis_tdata , - s1_axis_tvalid , - s1_axis_tready , - - // Slave AXIS 2 for Input data. - s2_axis_tdata , - s2_axis_tvalid , - s2_axis_tready , - - // Slave AXIS 3 for Input data. - s3_axis_tdata , - s3_axis_tvalid , - s3_axis_tready , - - // Master AXIS 0 for Output data. - m0_axis_tdata , - m0_axis_tvalid , - m0_axis_tready , - - // Master AXIS 1 for Output data. - m1_axis_tdata , - m1_axis_tvalid , - m1_axis_tready , - - // Master AXIS 2 for Output data. - m2_axis_tdata , - m2_axis_tvalid , - m2_axis_tready , - - // Master AXIS 3 for Output data. - m3_axis_tdata , - m3_axis_tvalid , - m3_axis_tready , - - // Master AXIS 4 for Output data. - m4_axis_tdata , - m4_axis_tvalid , - m4_axis_tready , - - // Master AXIS 5 for Output data. - m5_axis_tdata , - m5_axis_tvalid , - m5_axis_tready , - - // Master AXIS 6 for Output data. - m6_axis_tdata , - m6_axis_tvalid , - m6_axis_tready , - - // Master AXIS 7 for Output data. - m7_axis_tdata , - m7_axis_tvalid , - m7_axis_tready , - - // Registers. - START_SRC_REG , - START_REG -); - -// Parameters. -parameter N = 16; // Program memory depth. -parameter M = 10; // Data memory depth. - -// Ports. -input clk; -input rstn; - -input start; - -output [N-1:0] pmem_addr; -input [63:0] pmem_do; - -output dmem_we; -output [M-1:0] dmem_addr; -output [31:0] dmem_di; -input [31:0] dmem_do; - -input [63:0] s0_axis_tdata; -input s0_axis_tvalid; -output s0_axis_tready; - -input [63:0] s1_axis_tdata; -input s1_axis_tvalid; -output s1_axis_tready; - -input [63:0] s2_axis_tdata; -input s2_axis_tvalid; -output s2_axis_tready; - -input [63:0] s3_axis_tdata; -input s3_axis_tvalid; -output s3_axis_tready; - -output [159:0] m0_axis_tdata; -output m0_axis_tvalid; -input m0_axis_tready; - -output [159:0] m1_axis_tdata; -output m1_axis_tvalid; -input m1_axis_tready; - -output [159:0] m2_axis_tdata; -output m2_axis_tvalid; -input m2_axis_tready; - -output [159:0] m3_axis_tdata; -output m3_axis_tvalid; -input m3_axis_tready; - -output [159:0] m4_axis_tdata; -output m4_axis_tvalid; -input m4_axis_tready; - -output [159:0] m5_axis_tdata; -output m5_axis_tvalid; -input m5_axis_tready; - -output [159:0] m6_axis_tdata; -output m6_axis_tvalid; -input m6_axis_tready; - -output [159:0] m7_axis_tdata; -output m7_axis_tvalid; -input m7_axis_tready; - -input START_SRC_REG; -input START_REG; - -// Number of channels. -localparam NCH = 8; - -// Bit-width. -localparam B = 32; - -// Master Clock Width. -localparam TW = 48; - -// Fifo-width: 5*B (registers) + TW (Master Clock) + 8 (opcode) -localparam FW = 5*B + TW + 8; - -// Synced regs. -wire START_SRC_REG_resync; -wire START_REG_resync; - -// Muxed start. -wire start_i; - -// Instruction fields. -wire [7:0] opcode_i; -wire [2:0] page_i; -wire [2:0] channel_i; -wire [3:0] oper_i; -wire [31:0] imm_i; - -// IR enable. -wire ir_en_i; - -// Pogram counter out (jump instructions). -wire pc_src_i; -wire pc_en_i; -wire pc_rst_i; - -// Alu control. -wire [B-1:0] alu_a; -wire [B-1:0] alu_b; -wire [1:0] alu_src_b_i; -wire alu_zero_i; -wire [B-1:0] alu_out; - -// Alu Time control -wire alut_src_b_i; - -// Register write control. -wire [2:0] reg_src_i; -wire reg_wen_i; - -// Conditional control. -wire cond_flag_i; - -// Stack control. -wire stack_en_i; -wire stack_op_i; -wire [B-1:0] stack_din_i; -wire [B-1:0] stack_dout_i; -wire stack_full_i; -wire stack_empty_i; - -// Read address. -wire [4:0] reg_addr0_i; -wire [4:0] reg_addr1_i; -wire [4:0] reg_addr2_i; -wire [4:0] reg_addr3_i; -wire [4:0] reg_addr4_i; -wire [4:0] reg_addr5_i; -wire [4:0] reg_addr6_i; - -// Write address. -wire [4:0] reg_addr7_i; - -// Write data. -wire [B-1:0] reg_din7_i; - - -// Output registers. -wire [B-1:0] reg_dout0_i; -wire [B-1:0] reg_dout1_i; -wire [B-1:0] reg_dout2_i; -wire [B-1:0] reg_dout3_i; -wire [B-1:0] reg_dout4_i; -wire [B-1:0] reg_dout5_i; -wire [B-1:0] reg_dout6_i; - -// Program Counter. -wire [15:0] pc_i; -wire [15:0] pc_mux; -reg [15:0] pc_r; - -// Instruction register. -reg [63:0] ir_r; - -// Fifo for timed-instructions. -wire [NCH-1:0] fifo_time_wr_en; -wire [FW-1:0] fifo_time_din; -wire [NCH-1:0] fifo_time_rd_en; -wire [FW-1:0] fifo_time_dout [NCH-1:0]; -wire [NCH-1:0] fifo_time_full; -wire [NCH-1:0] fifo_time_empty; - -// Muxed fifo signals for control. -wire fifo_wr_en_mux; -wire fifo_full_mux; - -// Data memory control. -wire [M-1:0] dmem_addr_mux; -wire dmem_addr_src; - -// Alu for time computation. -wire [TW-1:0] alut_a; -wire [TW-1:0] alut_b; -wire [TW-1:0] alut_out; -reg [TW-1:0] alut_out_r; - -// Master clock. -reg [TW-1:0] t_cnt; -wire t_cnt_en; -reg [TW-1:0] t_cnt_sync; -wire t_cnt_sync_en; - -// Data memory output data register. -reg [B-1:0] dmem_do_r; - -// Stack output register. -reg [B-1:0] stack_dout_r; - -// Data input from external AXIS ports. -wire [63:0] din0_i; -wire [63:0] din1_i; -wire [63:0] din2_i; -wire [63:0] din3_i; -wire [63:0] din_mux; -wire [31:0] din_i; - -// Wait handshake. -wire [NCH-1:0] waitt_i; -wire [NCH-1:0] waitt_ack_i; -wire waitt_mux; -wire waitt_ack_mux; - -// Output AXIS. -wire [159:0] m_axis_tdata_i [NCH-1:0]; -wire [NCH-1:0] m_axis_tvalid_i; -wire [NCH-1:0] m_axis_tready_i; - -// START_SRC_REG_resync -synchronizer_n - #( - .N(2) - ) - START_SRC_REG_resync_i - ( - .rstn (rstn ), - .clk (clk ), - .data_in (START_SRC_REG ), - .data_out (START_SRC_REG_resync ) - ); - -// START_REG_resync -synchronizer_n - #( - .N(2) - ) - START_REG_resync_i - ( - .rstn (rstn ), - .clk (clk ), - .data_in (START_REG ), - .data_out (START_REG_resync ) - ); - -// Control block. -ctrl - ctrl_i - ( - // Clock and reset. - .clk (clk ), - .rstn (rstn ), - - // Start/stop. - .start (start_i ), - - // Opcode. - .opcode (opcode_i ), - - // IR control. - .ir_en (ir_en_i ), - - // Pogram counter out (jump instructions). - .pc_src (pc_src_i ), - .pc_en (pc_en_i ), - .pc_rst (pc_rst_i ), - - // Alu control. - .alu_src_b (alu_src_b_i ), - .alu_zero (alu_zero_i ), - - // Alu time control. - .alut_src_b (alut_src_b_i ), - - // Register write control. - .reg_src (reg_src_i ), - .reg_wen (reg_wen_i ), - - // Conditional control. - .cond_flag (cond_flag_i ), - - // Stack control. - .stack_en (stack_en_i ), - .stack_op (stack_op_i ), - .stack_full (stack_full_i ), - .stack_empty (stack_empty_i ), - - // Fifo Time control. - .fifo_wr_en (fifo_wr_en_mux ), - .fifo_full (fifo_full_mux ), - - // Data Memory control. - .dmem_we (dmem_we ), - .addr_src (dmem_addr_src ), - - // Master clock control. - .t_en (t_cnt_en ), - .t_sync_en (t_cnt_sync_en ), - - // Wait handshake. - .waitt (waitt_mux ), - .waitt_ack (waitt_ack_mux ) - ); - -// Muxed start. -assign start_i = (START_SRC_REG_resync == 1)? start : START_REG_resync; - -// Instruction fields. -assign opcode_i = ir_r[63:56]; -assign page_i = ir_r[55:53]; -assign channel_i = ir_r[52:50]; -assign oper_i = ir_r[49:46]; -assign imm_i = {ir_r[30],ir_r[30:0]}; // Sign-extend immediate to be 32-bit. - -// Stack block. -stack - #( - // Data width. - .B(B) - ) - stack_i - ( - // Clock and reset. - .clk (clk ), - .rstn (rstn ), - - // Enable and operation. - .en (stack_en_i ), - .op (stack_op_i ), - - // Input/Output data. - .din (stack_din_i ), - .dout (stack_dout_i ), - - // Flags. - .empty (stack_empty_i ), - .full (stack_full_i ) - ); - -// Stack input data. -assign stack_din_i = reg_dout0_i; - -// Regfile block. -regfile_8p - #( - // Data width. - .B(B) - ) - regfile_i - ( - // Clock and reset. - .clk (clk ), - .rstn (rstn ), - - // Read address. - .addr0 (reg_addr0_i ), - .addr1 (reg_addr1_i ), - .addr2 (reg_addr2_i ), - .addr3 (reg_addr3_i ), - .addr4 (reg_addr4_i ), - .addr5 (reg_addr5_i ), - .addr6 (reg_addr6_i ), - - // Write address. - .addr7 (reg_addr7_i ), - - // Write data. - .din7 (reg_din7_i ), - .wen7 (reg_wen_i ), - - // Page number. - .pnum (page_i ), - - // Output registers. - .dout0 (reg_dout0_i ), - .dout1 (reg_dout1_i ), - .dout2 (reg_dout2_i ), - .dout3 (reg_dout3_i ), - .dout4 (reg_dout4_i ), - .dout5 (reg_dout5_i ), - .dout6 (reg_dout6_i ) - ); - -// Register address. -assign reg_addr0_i = ir_r[40:36]; -assign reg_addr1_i = ir_r[35:31]; -assign reg_addr2_i = ir_r[30:26]; -assign reg_addr3_i = ir_r[25:21]; -assign reg_addr4_i = ir_r[20:16]; -assign reg_addr5_i = ir_r[15:11]; -assign reg_addr6_i = ir_r[10:6]; -assign reg_addr7_i = ir_r[45:41]; - -// Mux for register data input. -assign reg_din7_i = (reg_src_i == 3'b000)? imm_i : - (reg_src_i == 3'b001)? alu_out : - (reg_src_i == 3'b010)? stack_dout_r : - (reg_src_i == 3'b011)? din_i : - (reg_src_i == 3'b100)? dmem_do_r : - imm_i; - - -// Instantiate fifo and timed_ictrl. -generate -genvar i; - for (i = 0; i < NCH; i = i + 1 ) begin : GEN_channel - // Fifo for dispatching timed-instructions. - fifo - #( - // Data width. - .B (FW ), - - // Fifo depth. - .N (16 ) - ) - fifo_time_i - ( - .rstn (rstn ), - .clk (clk ), - - // Write I/F. - .wr_en (fifo_time_wr_en[i] ), - .din (fifo_time_din ), - - // Read I/F. - .rd_en (fifo_time_rd_en[i] ), - .dout (fifo_time_dout[i] ), - - // Flags. - .full (fifo_time_full[i] ), - .empty (fifo_time_empty[i] ) - ); - - // Write enable mux. - assign fifo_time_wr_en[i] = (channel_i == i)? fifo_wr_en_mux : 1'b0; - - // Timed-instructions dispatcher control. - timed_ictrl - timed_ictrl_i - ( - // Clock and reset. - .clk (clk ), - .rstn (rstn ), - - // Master clock. - .t_cnt (t_cnt ), - - // Fifo Time control. - .fifo_rd_en (fifo_time_rd_en[i] ), - .fifo_dout (fifo_time_dout[i] ), - .fifo_empty (fifo_time_empty[i] ), - - // Wait handshake. - .waitt (waitt_i[i] ), - .waitt_ack (waitt_ack_i[i] ), - - // Output AXIS. - .m_axis_tdata (m_axis_tdata_i[i] ), - .m_axis_tvalid (m_axis_tvalid_i[i] ), - .m_axis_tready (m_axis_tready_i[i] ) - ); - - // Wait handshake. - assign waitt_ack_i[i] = (channel_i == i)? waitt_ack_mux : 1'b0; - - end -endgenerate - -// Fifo Time input data (shared among channels). -// reg1 is reserved for time specification. reg0, reg2, reg3, reg4, reg5. -assign fifo_time_din = { opcode_i , - alut_out_r , - reg_dout5_i , - reg_dout4_i , - reg_dout3_i , - reg_dout2_i , - reg_dout0_i }; - -// Muxed fifo signals for control. -assign fifo_full_mux = fifo_time_full[channel_i[2:0]]; - -// Wait handshake. -assign waitt_mux = waitt_i[channel_i[2:0]]; - -// m_axis_tready signals. -assign m_axis_tready_i[0] = m0_axis_tready; -assign m_axis_tready_i[1] = m1_axis_tready; -assign m_axis_tready_i[2] = m2_axis_tready; -assign m_axis_tready_i[3] = m3_axis_tready; -assign m_axis_tready_i[4] = m4_axis_tready; -assign m_axis_tready_i[5] = m5_axis_tready; -assign m_axis_tready_i[6] = m6_axis_tready; -assign m_axis_tready_i[7] = m7_axis_tready; - -// Data memory address mux. -assign dmem_addr_mux = (dmem_addr_src == 1'b0)? imm_i : reg_dout0_i; - -// Conditional logic. -cond - #( - // Data width. - .B(B) - ) - cond_i - ( - // Clock and reset. - .clk (clk ), - .rstn (rstn ), - - // Input operands. - .din_a (reg_dout0_i ), - .din_b (reg_dout1_i ), - - // Operation. - .op (oper_i ), - - // Flag. - .flag (cond_flag_i ) - ); - -// Alu for math and bit-wise operations. -alu - #( - // Data width. - .B(B) - ) - alu_i - ( - // Clock and reset. - .clk (clk ), - .rstn (rstn ), - - // Input operands. - .din_a (alu_a ), - .din_b (alu_b ), - - // Operation. - .op (oper_i ), - - // Zero detection. - .zero_a (alu_zero_i ), - .zero_b ( ), - - // Output. - .dout (alu_out ) - ); - -// Alu inputs. -assign alu_a = reg_dout0_i; -assign alu_b = (alu_src_b_i == 2'b00)? imm_i : - (alu_src_b_i == 2'b01)? reg_dout1_i : - (alu_src_b_i == 2'b10)? -1 : - 0; - -// Slave AXIS 0 read block. -s_axis_read - #( - // Data width. - .B(64) - ) - s0_axis_read_i - ( - // Clock and reset. - .clk (clk ), - .rstn (rstn ), - - // AXIS Slave. - .s_axis_tdata (s0_axis_tdata ), - .s_axis_tvalid (s0_axis_tvalid ), - .s_axis_tready (s0_axis_tready ), - - // Output data. - .dout (din0_i ) - ); - -// Slave AXIS 1 read block. -s_axis_read - #( - // Data width. - .B(64) - ) - s1_axis_read_i - ( - // Clock and reset. - .clk (clk ), - .rstn (rstn ), - - // AXIS Slave. - .s_axis_tdata (s1_axis_tdata ), - .s_axis_tvalid (s1_axis_tvalid ), - .s_axis_tready (s1_axis_tready ), - - // Output data. - .dout (din1_i ) - ); - -// Slave AXIS 2 read block. -s_axis_read - #( - // Data width. - .B(64) - ) - s2_axis_read_i - ( - // Clock and reset. - .clk (clk ), - .rstn (rstn ), - - // AXIS Slave. - .s_axis_tdata (s2_axis_tdata ), - .s_axis_tvalid (s2_axis_tvalid ), - .s_axis_tready (s2_axis_tready ), - - // Output data. - .dout (din2_i ) - ); - -// Slave AXIS 3 read block. -s_axis_read - #( - // Data width. - .B(64) - ) - s3_axis_read_i - ( - // Clock and reset. - .clk (clk ), - .rstn (rstn ), - - // AXIS Slave. - .s_axis_tdata (s3_axis_tdata ), - .s_axis_tvalid (s3_axis_tvalid ), - .s_axis_tready (s3_axis_tready ), - - // Output data. - .dout (din3_i ) - ); - -// Data input mux. -assign din_mux = (channel_i == 0)? din0_i : - (channel_i == 1)? din1_i : - (channel_i == 2)? din2_i : - (channel_i == 3)? din3_i : - 0; - -// Low/high part selection. -assign din_i = (oper_i == 4'b1010)? din_mux[32 +:32] : - din_mux[0 +: 32]; - -// Alu for time inputs. -assign alut_a = t_cnt_sync; -assign alut_b = (alut_src_b_i == 0)? reg_dout1_i : imm_i; -assign alut_out = alut_a + alut_b; - -// Registers. -always @(posedge clk) begin - if (~rstn) begin - // Program counter. - pc_r <= 0; - - // Instruction counter. - ir_r <= 0; - - // ALU t output register. - alut_out_r <= 0; - - // Master clock. - t_cnt <= 0; - t_cnt_sync <= 0; - - // Data memory output data register. - dmem_do_r <= 0; - - // Stack output register. - stack_dout_r <= 0; - end - else begin - // Program counter. - if (pc_rst_i) - pc_r <= 0; - else if (pc_en_i) - pc_r <= pc_mux; - - // Instruction counter. - if (ir_en_i) - ir_r <= pmem_do; - - // ALU t output register. - alut_out_r <= alut_out; - - // Master clock. - if (pc_rst_i) - t_cnt <= 0; - else if (t_cnt_en) - t_cnt <= t_cnt + 1; - - if (pc_rst_i) - t_cnt_sync <= 0; - else if (t_cnt_sync_en) - t_cnt_sync <= alut_out_r; - - // Data memory output data register. - dmem_do_r <= dmem_do; - - // Stack output register. - stack_dout_r <= stack_dout_i; - end -end - -// Program counter. -assign pc_i = pc_r + 1; -assign pc_mux = (pc_src_i == 1)? imm_i : pc_i; - -// Assign outputs. -assign pmem_addr = pc_r; - -// Data memory interface. -assign dmem_addr = dmem_addr_mux; -assign dmem_di = reg_dout1_i; - -// Master AXIS 0 for Output data. -assign m0_axis_tdata = m_axis_tdata_i[0]; -assign m0_axis_tvalid = m_axis_tvalid_i[0]; - -// Master AXIS 1 for Output data. -assign m1_axis_tdata = m_axis_tdata_i[1]; -assign m1_axis_tvalid = m_axis_tvalid_i[1]; - -// Master AXIS 2 for Output data. -assign m2_axis_tdata = m_axis_tdata_i[2]; -assign m2_axis_tvalid = m_axis_tvalid_i[2]; - -// Master AXIS 3 for Output data. -assign m3_axis_tdata = m_axis_tdata_i[3]; -assign m3_axis_tvalid = m_axis_tvalid_i[3]; - -// Master AXIS 4 for Output data. -assign m4_axis_tdata = m_axis_tdata_i[4]; -assign m4_axis_tvalid = m_axis_tvalid_i[4]; - -// Master AXIS 5 for Output data. -assign m5_axis_tdata = m_axis_tdata_i[5]; -assign m5_axis_tvalid = m_axis_tvalid_i[5]; - -// Master AXIS 6 for Output data. -assign m6_axis_tdata = m_axis_tdata_i[6]; -assign m6_axis_tvalid = m_axis_tvalid_i[6]; - -// Master AXIS 7 for Output data. -assign m7_axis_tdata = m_axis_tdata_i[7]; -assign m7_axis_tvalid = m_axis_tvalid_i[7]; - -endmodule - diff --git a/qick/firmware/ip/axis_tproc64x32_x8_v1/xgui/axis_tproc64x32_x8_v1_0.tcl b/qick/firmware/ip/axis_tproc64x32_x8_v1/xgui/axis_tproc64x32_x8_v1_0.tcl deleted file mode 100644 index f4042d5..0000000 --- a/qick/firmware/ip/axis_tproc64x32_x8_v1/xgui/axis_tproc64x32_x8_v1_0.tcl +++ /dev/null @@ -1,40 +0,0 @@ -# Definitional proc to organize widgets for parameters. -proc init_gui { IPINST } { - ipgui::add_param $IPINST -name "Component_Name" - #Adding Page - set Page_0 [ipgui::add_page $IPINST -name "Page 0"] - ipgui::add_param $IPINST -name "DMEM_N" -parent ${Page_0} - ipgui::add_param $IPINST -name "PMEM_N" -parent ${Page_0} - - -} - -proc update_PARAM_VALUE.DMEM_N { PARAM_VALUE.DMEM_N } { - # Procedure called to update DMEM_N when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.DMEM_N { PARAM_VALUE.DMEM_N } { - # Procedure called to validate DMEM_N - return true -} - -proc update_PARAM_VALUE.PMEM_N { PARAM_VALUE.PMEM_N } { - # Procedure called to update PMEM_N when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.PMEM_N { PARAM_VALUE.PMEM_N } { - # Procedure called to validate PMEM_N - return true -} - - -proc update_MODELPARAM_VALUE.PMEM_N { MODELPARAM_VALUE.PMEM_N PARAM_VALUE.PMEM_N } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.PMEM_N}] ${MODELPARAM_VALUE.PMEM_N} -} - -proc update_MODELPARAM_VALUE.DMEM_N { MODELPARAM_VALUE.DMEM_N PARAM_VALUE.DMEM_N } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.DMEM_N}] ${MODELPARAM_VALUE.DMEM_N} -} - diff --git a/qick/firmware/ip/mr_buffer_et/component.xml b/qick/firmware/ip/mr_buffer_et/component.xml deleted file mode 100644 index 1133e53..0000000 --- a/qick/firmware/ip/mr_buffer_et/component.xml +++ /dev/null @@ -1,1258 +0,0 @@ - - - user.org - user - mr_buffer_et - 1.0 - - - m00_axis - - - - - - - TDATA - - - m00_axis_tdata - - - - - TSTRB - - - m00_axis_tstrb - - - - - TLAST - - - m00_axis_tlast - - - - - TVALID - - - m00_axis_tvalid - - - - - TREADY - - - m00_axis_tready - - - - - - s00_axis - - - - - - - TDATA - - - s00_axis_tdata - - - - - TSTRB - - - s00_axis_tstrb - - - - - TLAST - - - s00_axis_tlast - - - - - TVALID - - - s00_axis_tvalid - - - - - TREADY - - - s00_axis_tready - - - - - - s00_axi - - - - - - - - - AWADDR - - - s00_axi_awaddr - - - - - AWPROT - - - s00_axi_awprot - - - - - AWVALID - - - s00_axi_awvalid - - - - - AWREADY - - - s00_axi_awready - - - - - WDATA - - - s00_axi_wdata - - - - - WSTRB - - - s00_axi_wstrb - - - - - WVALID - - - s00_axi_wvalid - - - - - WREADY - - - s00_axi_wready - - - - - BRESP - - - s00_axi_bresp - - - - - BVALID - - - s00_axi_bvalid - - - - - BREADY - - - s00_axi_bready - - - - - ARADDR - - - s00_axi_araddr - - - - - ARPROT - - - s00_axi_arprot - - - - - ARVALID - - - s00_axi_arvalid - - - - - ARREADY - - - s00_axi_arready - - - - - RDATA - - - s00_axi_rdata - - - - - RRESP - - - s00_axi_rresp - - - - - RVALID - - - s00_axi_rvalid - - - - - RREADY - - - s00_axi_rready - - - - - - m00_axis_aresetn - - - - - - - RST - - - m00_axis_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - s00_axi_aresetn - - - - - - - RST - - - s00_axi_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - s00_axis_aresetn - - - - - - - RST - - - s00_axis_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - m00_axis_aclk - - - - - - - CLK - - - m00_axis_aclk - - - - - - ASSOCIATED_BUSIF - m00_axis - - - ASSOCIATED_RESET - m00_axis_aresetn - - - - - s00_axi_aclk - - - - - - - CLK - - - s00_axi_aclk - - - - - - ASSOCIATED_BUSIF - s00_axi - - - ASSOCIATED_RESET - s00_axi_aresetn - - - - - s00_axis_aclk - - - - - - - CLK - - - s00_axis_aclk - - - - - - ASSOCIATED_BUSIF - s00_axis - - - ASSOCIATED_RESET - s00_axis_aresetn - - - - - - - s00_axi - - reg0 - 0 - 4096 - 32 - register - - - - - - - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis - VHDL - mr_buffer_v1_0 - - xilinx_anylanguagesynthesis_view_fileset - - - - viewChecksum - 65cf1a34 - - - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - VHDL - mr_buffer_v1_0 - - xilinx_anylanguagebehavioralsimulation_view_fileset - - - - viewChecksum - 65cf1a34 - - - - - xilinx_testbench - Test Bench - :vivado.xilinx.com:simulation.testbench - tb - - xilinx_testbench_view_fileset - - - - viewChecksum - 90a7182e - - - - - xilinx_xpgui - UI Layout - :vivado.xilinx.com:xgui.ui - - xilinx_xpgui_view_fileset - - - - viewChecksum - 03a1763f - - - - - - - trigger - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s00_axi_aclk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s00_axi_aresetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s00_axi_awaddr - - in - - 5 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s00_axi_awprot - - in - - 2 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s00_axi_awvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s00_axi_awready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s00_axi_wdata - - in - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s00_axi_wstrb - - in - - 3 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 1 - - - - - s00_axi_wvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s00_axi_wready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s00_axi_bresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s00_axi_bvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s00_axi_bready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s00_axi_araddr - - in - - 5 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s00_axi_arprot - - in - - 2 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s00_axi_arvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s00_axi_arready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s00_axi_rdata - - out - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s00_axi_rresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s00_axi_rvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s00_axi_rready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s00_axis_aclk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s00_axis_aresetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s00_axis_tready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s00_axis_tdata - - in - - 127 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s00_axis_tstrb - - in - - 15 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 1 - - - - - s00_axis_tlast - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s00_axis_tvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m00_axis_aclk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m00_axis_aresetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m00_axis_tvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m00_axis_tdata - - out - - 15 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m00_axis_tstrb - - out - - 1 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m00_axis_tlast - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m00_axis_tready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 1 - - - - - - - NM - Nm - 8 - - - N - N - 8 - - - B - B - 16 - - - C_S00_AXI_DATA_WIDTH - C S00 Axi Data Width - 32 - - - C_S00_AXI_ADDR_WIDTH - C S00 Axi Addr Width - 6 - - - - - - choice_list_74b5137e - ACTIVE_HIGH - ACTIVE_LOW - - - - - xilinx_anylanguagesynthesis_view_fileset - - src/bram_dp.vhd - vhdlSource - - - src/data_reader.vhd - vhdlSource - - - src/data_writer.vhd - vhdlSource - - - src/fifo.vhd - vhdlSource - - - src/mr_buffer.vhd - vhdlSource - - - src/mr_buffer_v1_0_S00_AXI.vhd - vhdlSource - - - src/synchronizer.vhd - vhdlSource - - - src/mr_buffer_v1_0.vhd - vhdlSource - CHECKSUM_103c4483 - - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - src/bram_dp.vhd - vhdlSource - - - src/data_reader.vhd - vhdlSource - - - src/data_writer.vhd - vhdlSource - - - src/fifo.vhd - vhdlSource - - - src/mr_buffer.vhd - vhdlSource - - - src/mr_buffer_v1_0_S00_AXI.vhd - vhdlSource - - - src/synchronizer.vhd - vhdlSource - - - src/mr_buffer_v1_0.vhd - vhdlSource - - - - xilinx_testbench_view_fileset - - src/tb.sv - systemVerilogSource - USED_IN_implementation - USED_IN_simulation - USED_IN_synthesis - - - - xilinx_xpgui_view_fileset - - xgui/mr_buffer_et_v1_0.tcl - tclSource - CHECKSUM_03a1763f - XGUI_VERSION_2 - - - - Multi-Rate Buffer with External Trigger. - - - NM - Nm - 8 - - - N - N - 8 - - - B - B - 16 - - - C_S00_AXI_DATA_WIDTH - C S00 Axi Data Width - 32 - - - C_S00_AXI_ADDR_WIDTH - C S00 Axi Addr Width - 6 - - - Component_Name - mr_buffer_v1_0_v1_0 - - - - - - zynquplus - - - /UserIP - - Multi-Rate Buffer ET - package_project - 3 - 2019-10-15T15:31:13Z - - /home/lstefana/v18.3/ip-git/mr_buffer_et - /home/lstefana/v18.3/ip-git/mr_buffer_et - /home/lstefana/v18.3/ip-git/mr_buffer_et - /home/lstefana/v18.3/ip-git/mr_buffer_et - /home/lstefana/v18.3/ip-git/mr_buffer_et - /home/lstefana/v18.3/ip-git/mr_buffer_et - /home/lstefana/v18.3/ip-git/mr_buffer_et - /home/lstefana/v18.3/ip-git/mr_buffer_et - /home/lstefana/v18.3/ip-git/mr_buffer_et - /home/lstefana/v18.3/ip-git/mr_buffer_et - /home/lstefana/v18.3/ip-git/mr_buffer_et - /home/lstefana/v18.3/ip-git/mr_buffer_et - /home/lstefana/v18.3/ip-git/mr_buffer_et - /home/lstefana/v18.3/ip-git/mr_buffer_et - /home/lstefana/v18.3/ip-git/mr_buffer_et - /home/lstefana/v18.3/ip-git/mr_buffer_et - /home/lstefana/v18.3/ip-git/mr_buffer_et - /home/lstefana/v18.3/ip-git/mr_buffer_et - /home/lstefana/v18.3/ip-git/mr_buffer_et - /home/lstefana/v18.3/ip-git/mr_buffer_et - - - - 2018.3 - - - - - - - - - diff --git a/qick/firmware/ip/mr_buffer_et/src/axi4stream_vip_0/axi4stream_vip_0.vho b/qick/firmware/ip/mr_buffer_et/src/axi4stream_vip_0/axi4stream_vip_0.vho deleted file mode 100644 index 1c7056e..0000000 --- a/qick/firmware/ip/mr_buffer_et/src/axi4stream_vip_0/axi4stream_vip_0.vho +++ /dev/null @@ -1,83 +0,0 @@ --- (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:axi4stream_vip:1.1 --- IP Revision: 4 - --- The following code must appear in the VHDL architecture header. - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT axi4stream_vip_0 - PORT ( - aclk : IN STD_LOGIC; - aresetn : IN STD_LOGIC; - s_axis_tvalid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); - s_axis_tready : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0) - ); -END COMPONENT; --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : axi4stream_vip_0 - PORT MAP ( - aclk => aclk, - aresetn => aresetn, - s_axis_tvalid => s_axis_tvalid, - s_axis_tready => s_axis_tready, - s_axis_tdata => s_axis_tdata - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file axi4stream_vip_0.vhd when simulating --- the core, axi4stream_vip_0. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/qick/firmware/ip/mr_buffer_et/src/axi4stream_vip_0/axi4stream_vip_0.xci b/qick/firmware/ip/mr_buffer_et/src/axi4stream_vip_0/axi4stream_vip_0.xci deleted file mode 100644 index 5042c51..0000000 --- a/qick/firmware/ip/mr_buffer_et/src/axi4stream_vip_0/axi4stream_vip_0.xci +++ /dev/null @@ -1,99 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - axi4stream_vip_0 - - - ACTIVE_LOW - - 100000000 - 0 - 0.000 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 1 - 0 - 0 - undef - 0.000 - 1 - 0 - 0 - 0 - 8 - 0 - 1 - 0 - 2 - 0x00000003 - 0 - 0 - axi4stream_vip_0 - 0 - 1 - 0 - 0 - 1 - 0 - 0 - SLAVE - 1 - 0 - 0 - 0 - 0 - zynquplusRFSOC - xilinx.com:zcu111:part0:1.1 - - xczu28dr - ffvg1517 - VERILOG - - MIXED - -2 - E - TRUE - TRUE - IP_Flow - 4 - TRUE - . - - . - 2018.3 - OUT_OF_CONTEXT - - - - - - - - - - - - - - diff --git a/qick/firmware/ip/mr_buffer_et/src/axi4stream_vip_0/axi4stream_vip_0.xml b/qick/firmware/ip/mr_buffer_et/src/axi4stream_vip_0/axi4stream_vip_0.xml deleted file mode 100644 index 4b46f26..0000000 --- a/qick/firmware/ip/mr_buffer_et/src/axi4stream_vip_0/axi4stream_vip_0.xml +++ /dev/null @@ -1,1536 +0,0 @@ - - - xilinx.com - customized_ip - axi4stream_vip_0 - 1.0 - - - M_AXIS - - - - - - - TDATA - - - m_axis_tdata - - - - - TDEST - - - m_axis_tdest - - - - - TID - - - m_axis_tid - - - - - TKEEP - - - m_axis_tkeep - - - - - TLAST - - - m_axis_tlast - - - - - TREADY - - - m_axis_tready - - - - - TSTRB - - - m_axis_tstrb - - - - - TUSER - - - m_axis_tuser - - - - - TVALID - - - m_axis_tvalid - - - - - - TDATA_NUM_BYTES - 0 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 0 - - - none - - - - - HAS_TREADY - 0 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 0 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - S_AXIS - - - - - - - TDATA - - - s_axis_tdata - - - - - TDEST - - - s_axis_tdest - - - - - TID - - - s_axis_tid - - - - - TKEEP - - - s_axis_tkeep - - - - - TLAST - - - s_axis_tlast - - - - - TREADY - - - s_axis_tready - - - - - TSTRB - - - s_axis_tstrb - - - - - TUSER - - - s_axis_tuser - - - - - TVALID - - - s_axis_tvalid - - - - - - TDATA_NUM_BYTES - 1 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 0 - - - none - - - - - HAS_TREADY - 1 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 0 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - RESET - - - - - - - RST - - - aresetn - - - - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - ACLKEN - - - - - - - CE - - - aclken - - - - - - POLARITY - ACTIVE_LOW - - - none - - - - - - - - false - - - - - - CLOCK - - - - - - - CLK - - - aclk - - - - - - ASSOCIATED_BUSIF - M_AXIS:S_AXIS - - - ASSOCIATED_RESET - aresetn - - - FREQ_HZ - 100000000 - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - - - xilinx_veriloginstantiationtemplate - Verilog Instantiation Template - verilogSource:vivado.xilinx.com:synthesis.template - verilog - - xilinx_veriloginstantiationtemplate_view_fileset - - - - GENtimestamp - Wed Jul 31 19:44:44 UTC 2019 - - - outputProductCRC - 9:d7246b49 - - - - - xilinx_verilogsynthesis - Verilog Synthesis - verilogSource:vivado.xilinx.com:synthesis - verilog - axi4stream_vip_v1_1_4_top - - xilinx_verilogsynthesis_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset - - - xilinx_verilogsynthesis_view_fileset - - - - GENtimestamp - Wed Jul 31 19:48:50 UTC 2019 - - - outputProductCRC - 9:d7246b49 - - - - - xilinx_synthesisconstraints - Synthesis Constraints - :vivado.xilinx.com:synthesis.constraints - - xilinx_synthesisconstraints_view_fileset - - - - GENtimestamp - Wed Jul 31 19:48:50 UTC 2019 - - - outputProductCRC - 9:d7246b49 - - - - - xilinx_verilogsynthesiswrapper - Verilog Synthesis Wrapper - verilogSource:vivado.xilinx.com:synthesis.wrapper - verilog - axi4stream_vip_0 - - xilinx_verilogsynthesiswrapper_view_fileset - - - - GENtimestamp - Wed Jul 31 19:48:50 UTC 2019 - - - outputProductCRC - 9:d7246b49 - - - - - xilinx_versioninformation - Version Information - :vivado.xilinx.com:docs.versioninfo - axi4stream_vip_v1_1_4_top - - xilinx_versioninformation_view_fileset - - - - GENtimestamp - Wed Jul 31 19:48:50 UTC 2019 - - - outputProductCRC - 9:d7246b49 - - - - - xilinx_externalfiles - External Files - :vivado.xilinx.com:external.files - - xilinx_externalfiles_view_fileset - - - - GENtimestamp - Wed Jul 31 19:50:52 UTC 2019 - - - outputProductCRC - 9:d7246b49 - - - - - xilinx_verilogbehavioralsimulation - Verilog Simulation - verilogSource:vivado.xilinx.com:simulation - verilog - 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- - - xilinx_externalfiles_view_fileset - - axi4stream_vip_0.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - axi4stream_vip_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - axi4stream_vip_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - axi4stream_vip_0_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - axi4stream_vip_0_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - - xilinx_verilogbehavioralsimulation_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset - - hdl/axis_infrastructure_v1_1_0.vh - verilogSource - USED_IN_ipstatic - true - axis_infrastructure_v1_1_0 - - - hdl/axis_infrastructure_v1_1_vl_rfs.v - verilogSource - USED_IN_ipstatic - axis_infrastructure_v1_1_0 - - - - - - - - - - - xilinx_verilogbehavioralsimulation_view_fileset - - sim/axi4stream_vip_0_pkg.sv - systemVerilogSource - - - hdl/axi4stream_vip_v1_1_vl_rfs.sv - systemVerilogSource - USED_IN_ipstatic - axi4stream_vip_v1_1_4 - - - - xilinx_verilogsimulationwrapper_view_fileset - - sim/axi4stream_vip_0.sv - systemVerilogSource - xil_defaultlib - - - - The AXI4-Stream Verification IP. - - - INTERFACE_MODE - INTERFACE MODE - SLAVE - - - TDATA_NUM_BYTES - TDATA WIDTH(BYTES) - 1 - - - USER_BITS_PER_BYTE - TUSER BITS PER BYTE - 0 - - - HAS_TUSER_BITS_PER_BYTE - HAS TUSER_BITS_PER_BYTE - 0 - - - TID_WIDTH - TID WIDTH(BITS) - 0 - - - TDEST_WIDTH - TDEST WIDTH(BITS) - 0 - - - TUSER_WIDTH - TUSER WIDTH(BITS) - 0 - - - HAS_TREADY - ENABLE TREADY - 1 - - - HAS_TSTRB - ENABLE TSTRB - 0 - - - HAS_TKEEP - ENABLE TKEEP - 0 - - - HAS_TLAST - ENABLE TLAST - 0 - - - HAS_ACLKEN - HAS ACLKEN - 0 - - - HAS_ARESETN - HAS ARESETN - 1 - - - Component_Name - axi4stream_vip_0 - - - - - AXI4-Stream Verification IP - - XPM_CDC - - 4 - true - - - - - - - - - 2018.3 - - - - - - - - diff --git a/qick/firmware/ip/mr_buffer_et/src/axi4stream_vip_1/axi4stream_vip_1.vho b/qick/firmware/ip/mr_buffer_et/src/axi4stream_vip_1/axi4stream_vip_1.vho deleted file mode 100644 index 00c7841..0000000 --- a/qick/firmware/ip/mr_buffer_et/src/axi4stream_vip_1/axi4stream_vip_1.vho +++ /dev/null @@ -1,83 +0,0 @@ --- (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:axi4stream_vip:1.1 --- IP Revision: 4 - --- The following code must appear in the VHDL architecture header. - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT axi4stream_vip_1 - PORT ( - aclk : IN STD_LOGIC; - aresetn : IN STD_LOGIC; - m_axis_tvalid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - m_axis_tready : IN STD_LOGIC_VECTOR(0 DOWNTO 0); - m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) - ); -END COMPONENT; --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : axi4stream_vip_1 - PORT MAP ( - aclk => aclk, - aresetn => aresetn, - m_axis_tvalid => m_axis_tvalid, - m_axis_tready => m_axis_tready, - m_axis_tdata => m_axis_tdata - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file axi4stream_vip_1.vhd when simulating --- the core, axi4stream_vip_1. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/qick/firmware/ip/mr_buffer_et/src/axi4stream_vip_1/axi4stream_vip_1.xci b/qick/firmware/ip/mr_buffer_et/src/axi4stream_vip_1/axi4stream_vip_1.xci deleted file mode 100644 index c3847db..0000000 --- a/qick/firmware/ip/mr_buffer_et/src/axi4stream_vip_1/axi4stream_vip_1.xci +++ /dev/null @@ -1,100 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - axi4stream_vip_1 - - - ACTIVE_LOW - - 100000000 - 0 - 0.000 - - 100000000 - 0 - 0 - 1 - 0 - 0 - undef - 0.000 - 4 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - 32 - 0 - 1 - 0 - 0 - 0b00000000000000000000000000000011 - 0 - 0 - axi4stream_vip_1 - 0 - 1 - 0 - 0 - 1 - 0 - 0 - MASTER - 4 - 0 - 0 - 0 - 0 - zynquplusRFSOC - xilinx.com:zcu111:part0:1.1 - - xczu28dr - ffvg1517 - VERILOG - - MIXED - -2 - E - TRUE - TRUE - IP_Flow - 4 - TRUE - . - - . - 2018.3 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - diff --git a/qick/firmware/ip/mr_buffer_et/src/axi4stream_vip_1/axi4stream_vip_1.xml b/qick/firmware/ip/mr_buffer_et/src/axi4stream_vip_1/axi4stream_vip_1.xml deleted file mode 100644 index eda7a8f..0000000 --- a/qick/firmware/ip/mr_buffer_et/src/axi4stream_vip_1/axi4stream_vip_1.xml +++ /dev/null @@ -1,1544 +0,0 @@ - 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- - - - - false - - - - - - CLOCK - - - - - - - CLK - - - aclk - - - - - - ASSOCIATED_BUSIF - M_AXIS:S_AXIS - - - ASSOCIATED_RESET - aresetn - - - FREQ_HZ - 100000000 - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - - - xilinx_veriloginstantiationtemplate - Verilog Instantiation Template - verilogSource:vivado.xilinx.com:synthesis.template - verilog - - xilinx_veriloginstantiationtemplate_view_fileset - - - - GENtimestamp - Wed Jul 31 19:45:34 UTC 2019 - - - outputProductCRC - 9:99973ee0 - - - - - xilinx_verilogsynthesis - Verilog Synthesis - verilogSource:vivado.xilinx.com:synthesis - verilog - axi4stream_vip_v1_1_4_top - - xilinx_verilogsynthesis_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset - - - xilinx_verilogsynthesis_view_fileset - - - - GENtimestamp - Wed Jul 31 19:48:53 UTC 2019 - - - outputProductCRC - 9:99973ee0 - - - - - xilinx_synthesisconstraints - Synthesis Constraints - :vivado.xilinx.com:synthesis.constraints - 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xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axis_tlast - - out - - 0 - 0 - - - - std_logic - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axis_tid - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axis_tdest - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axis_tuser - - out - - 0 - 0 - - - - std_logic_vector - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - - - C_AXI4STREAM_SIGNAL_SET - 0b00000000000000000000000000000011 - - - C_AXI4STREAM_INTERFACE_MODE - 0 - - - C_AXI4STREAM_DATA_WIDTH - 32 - - - C_AXI4STREAM_USER_BITS_PER_BYTE - 0 - - - C_AXI4STREAM_ID_WIDTH - 0 - - - C_AXI4STREAM_DEST_WIDTH - 0 - - - C_AXI4STREAM_USER_WIDTH - 0 - - - C_AXI4STREAM_HAS_ARESETN - 1 - - - - - - choice_list_642e7122 - MASTER - PASS_THROUGH - SLAVE - - - choice_list_9d8b0d81 - ACTIVE_HIGH - ACTIVE_LOW - - - choice_pairs_2d96f706 - 0 - 1 - - - - - xilinx_veriloginstantiationtemplate_view_fileset - - axi4stream_vip_1.vho - vhdlTemplate - - - axi4stream_vip_1.veo - verilogTemplate - - - - xilinx_verilogsynthesis_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset - - hdl/axis_infrastructure_v1_1_0.vh - verilogSource - true - axis_infrastructure_v1_1_0 - - - hdl/axis_infrastructure_v1_1_vl_rfs.v - verilogSource - axis_infrastructure_v1_1_0 - - - - - - - - - - - xilinx_verilogsynthesis_view_fileset - - hdl/axi4stream_vip_v1_1_vlsyn_rfs.sv - systemVerilogSource - axi4stream_vip_v1_1_4 - - - - xilinx_synthesisconstraints_view_fileset - - axi4stream_vip_1_ooc.xdc - xdc - USED_IN_implementation - USED_IN_out_of_context - USED_IN_synthesis - - - - xilinx_verilogsynthesiswrapper_view_fileset - - synth/axi4stream_vip_1.sv - systemVerilogSource - xil_defaultlib - - - - xilinx_versioninformation_view_fileset - - doc/axi4stream_vip_v1_1_changelog.txt - text - axi4stream_vip_v1_1_4 - - - - xilinx_externalfiles_view_fileset - - axi4stream_vip_1.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - axi4stream_vip_1_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - axi4stream_vip_1_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - axi4stream_vip_1_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - axi4stream_vip_1_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - - xilinx_verilogbehavioralsimulation_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset - - hdl/axis_infrastructure_v1_1_0.vh - verilogSource - USED_IN_ipstatic - true - axis_infrastructure_v1_1_0 - - - hdl/axis_infrastructure_v1_1_vl_rfs.v - verilogSource - USED_IN_ipstatic - axis_infrastructure_v1_1_0 - - - - - - - - - - - xilinx_verilogbehavioralsimulation_view_fileset - - sim/axi4stream_vip_1_pkg.sv - systemVerilogSource - - - hdl/axi4stream_vip_v1_1_vl_rfs.sv - systemVerilogSource - USED_IN_ipstatic - axi4stream_vip_v1_1_4 - - - - xilinx_verilogsimulationwrapper_view_fileset - - sim/axi4stream_vip_1.sv - systemVerilogSource - xil_defaultlib - - - - The AXI4-Stream Verification IP. - - - INTERFACE_MODE - INTERFACE MODE - MASTER - - - TDATA_NUM_BYTES - TDATA WIDTH(BYTES) - 4 - - - USER_BITS_PER_BYTE - TUSER BITS PER BYTE - 0 - - - - false - - - - - - HAS_TUSER_BITS_PER_BYTE - HAS TUSER_BITS_PER_BYTE - 0 - - - TID_WIDTH - TID WIDTH(BITS) - 0 - - - TDEST_WIDTH - TDEST WIDTH(BITS) - 0 - - - TUSER_WIDTH - TUSER WIDTH(BITS) - 0 - - - HAS_TREADY - ENABLE TREADY - 1 - - - HAS_TSTRB - ENABLE TSTRB - 0 - - - HAS_TKEEP - ENABLE TKEEP - 0 - - - HAS_TLAST - ENABLE TLAST - 0 - - - HAS_ACLKEN - HAS ACLKEN - 0 - - - HAS_ARESETN - HAS ARESETN - 1 - - - Component_Name - axi4stream_vip_1 - - - - - AXI4-Stream Verification IP - - XPM_CDC - - 4 - true - - - - - - - - - - 2018.3 - - - - - - - - diff --git a/qick/firmware/ip/mr_buffer_et/src/axi_vip_0/axi_vip_0.vho b/qick/firmware/ip/mr_buffer_et/src/axi_vip_0/axi_vip_0.vho deleted file mode 100644 index 5c34574..0000000 --- a/qick/firmware/ip/mr_buffer_et/src/axi_vip_0/axi_vip_0.vho +++ /dev/null @@ -1,115 +0,0 @@ --- (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:axi_vip:1.1 --- IP Revision: 4 - --- The following code must appear in the VHDL architecture header. - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT axi_vip_0 - PORT ( - aclk : IN STD_LOGIC; - aresetn : IN STD_LOGIC; - m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - m_axi_awvalid : OUT STD_LOGIC; - m_axi_awready : IN STD_LOGIC; - m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - m_axi_wvalid : OUT STD_LOGIC; - m_axi_wready : IN STD_LOGIC; - m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - m_axi_bvalid : IN STD_LOGIC; - m_axi_bready : OUT STD_LOGIC; - m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - m_axi_arvalid : OUT STD_LOGIC; - m_axi_arready : IN STD_LOGIC; - m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - m_axi_rvalid : IN STD_LOGIC; - m_axi_rready : OUT STD_LOGIC - ); -END COMPONENT; --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : axi_vip_0 - PORT MAP ( - aclk => aclk, - aresetn => aresetn, - m_axi_awaddr => m_axi_awaddr, - m_axi_awprot => m_axi_awprot, - m_axi_awvalid => m_axi_awvalid, - m_axi_awready => m_axi_awready, - m_axi_wdata => m_axi_wdata, - m_axi_wstrb => m_axi_wstrb, - m_axi_wvalid => m_axi_wvalid, - m_axi_wready => m_axi_wready, - m_axi_bresp => m_axi_bresp, - m_axi_bvalid => m_axi_bvalid, - m_axi_bready => m_axi_bready, - m_axi_araddr => m_axi_araddr, - m_axi_arprot => m_axi_arprot, - m_axi_arvalid => m_axi_arvalid, - m_axi_arready => m_axi_arready, - m_axi_rdata => m_axi_rdata, - m_axi_rresp => m_axi_rresp, - m_axi_rvalid => m_axi_rvalid, - m_axi_rready => m_axi_rready - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file axi_vip_0.vhd when simulating --- the core, axi_vip_0. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/qick/firmware/ip/mr_buffer_et/src/axi_vip_0/axi_vip_0.xci b/qick/firmware/ip/mr_buffer_et/src/axi_vip_0/axi_vip_0.xci deleted file mode 100644 index 7be9f09..0000000 --- a/qick/firmware/ip/mr_buffer_et/src/axi_vip_0/axi_vip_0.xci +++ /dev/null @@ -1,185 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - axi_vip_0 - - - ACTIVE_LOW - - 100000000 - 0 - 0.000 - 32 - 0 - 0 - 0 - - 32 - 100000000 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 32 - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 0 - 2 - 32 - 0 - 0 - 0 - 32 - 0 - 0 - 32 - 0 - 0 - 0 - axi_vip_0 - 32 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 0 - 1 - 0 - MASTER - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - zynquplusRFSOC - xilinx.com:zcu111:part0:1.1 - - xczu28dr - ffvg1517 - VERILOG - - MIXED - -2 - E - TRUE - TRUE - IP_Flow - 4 - TRUE - . - - . - 2018.3 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/qick/firmware/ip/mr_buffer_et/src/axi_vip_0/axi_vip_0.xml b/qick/firmware/ip/mr_buffer_et/src/axi_vip_0/axi_vip_0.xml deleted file mode 100644 index f372b50..0000000 --- a/qick/firmware/ip/mr_buffer_et/src/axi_vip_0/axi_vip_0.xml +++ /dev/null @@ -1,4477 +0,0 @@ - - - xilinx.com - customized_ip - axi_vip_0 - 1.0 - - - M_AXI - - - - - - - - - ARADDR - - - m_axi_araddr - - - - - ARBURST - - - m_axi_arburst - - - - - ARCACHE - - - m_axi_arcache - - - - - ARID - - - m_axi_arid - - - - - ARLEN - - - m_axi_arlen - - - - - ARLOCK - - - m_axi_arlock - - - - - ARPROT - - - m_axi_arprot - - - - - ARQOS - - - m_axi_arqos - - - - - ARREADY - - - m_axi_arready - - - - - ARREGION - - - m_axi_arregion - - - - - ARSIZE - - - m_axi_arsize - - - - - ARUSER - - - m_axi_aruser - - - - - ARVALID - - - m_axi_arvalid - - - - - AWADDR - - - m_axi_awaddr - - - - - AWBURST - - - m_axi_awburst - - - - - AWCACHE - - - m_axi_awcache - - - - - AWID - - - m_axi_awid - - - - - AWLEN - - - m_axi_awlen - - - - - AWLOCK - - - m_axi_awlock - - - - - AWPROT - - - m_axi_awprot - - - - - AWQOS - - - m_axi_awqos - - - - - AWREADY - - - m_axi_awready - - - - - AWREGION - - - m_axi_awregion - - - - - AWSIZE - - - m_axi_awsize - - - - - AWUSER - - - m_axi_awuser - - - - - AWVALID - - - m_axi_awvalid - - - - - BID - - - m_axi_bid - - - - - BREADY - - - m_axi_bready - - - - - BRESP - - - m_axi_bresp - - - - - BUSER - - - m_axi_buser - - - - - BVALID - - - m_axi_bvalid - - - - - RDATA - - - m_axi_rdata - - - - - RID - - - m_axi_rid - - - - - RLAST - - - m_axi_rlast - - - - - RREADY - - - m_axi_rready - - - - - RRESP - - - m_axi_rresp - - - - - RUSER - - - m_axi_ruser - - - - - RVALID - - - m_axi_rvalid - - - - - WDATA - - - m_axi_wdata - - - - - WID - - - m_axi_wid - - - - - WLAST - - - m_axi_wlast - - - - - WREADY - - - m_axi_wready - - - - - WSTRB - - - m_axi_wstrb - - - - - WUSER - - - m_axi_wuser - - - - - WVALID - - - m_axi_wvalid - - - - - - DATA_WIDTH - 32 - - - none - - - - - PROTOCOL - AXI4LITE - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - ID_WIDTH - 0 - - - none - - - - - ADDR_WIDTH - 32 - - - none - - - - - AWUSER_WIDTH - 0 - - - none - - - - - ARUSER_WIDTH - 0 - - - none - - - - - WUSER_WIDTH - 0 - - - none - - - - - RUSER_WIDTH - 0 - - - none - - - - - BUSER_WIDTH - 0 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - HAS_BURST - 0 - - - none - - - - - HAS_LOCK - 0 - - - none - - - - - HAS_PROT - 1 - - - none - - - - - HAS_CACHE - 0 - - - none - - - - - HAS_QOS - 0 - - - none - - - - - HAS_REGION - 0 - - - none - - - - - HAS_WSTRB - 1 - - - none - - - - - HAS_BRESP - 1 - - - none - - - - - HAS_RRESP - 1 - - - none - - - - - SUPPORTS_NARROW_BURST - 0 - - - none - - - - - NUM_READ_OUTSTANDING - 1 - - - none - - - - - NUM_WRITE_OUTSTANDING - 1 - - - none - - - - - MAX_BURST_LENGTH - 1 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - NUM_READ_THREADS - 1 - - - none - - - - - NUM_WRITE_THREADS - 1 - - - none - - - - - RUSER_BITS_PER_BYTE - 0 - - - none - - - - - WUSER_BITS_PER_BYTE - 0 - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - S_AXI - - - - - - - ARADDR - - - s_axi_araddr - - - - - ARBURST - - - s_axi_arburst - - - - - ARCACHE - - - s_axi_arcache - - - - - ARID - - - s_axi_arid - - - - - ARLEN - - - s_axi_arlen - - - - - ARLOCK - - - s_axi_arlock - - - - - ARPROT - - - s_axi_arprot - - - - - ARQOS - - - s_axi_arqos - - - - - ARREADY - - - s_axi_arready - - - - - ARREGION - - - s_axi_arregion - - - - - ARSIZE - - - s_axi_arsize - - - - - ARUSER - - - s_axi_aruser - - - - - ARVALID - - - s_axi_arvalid - - - - - AWADDR - - - s_axi_awaddr - - - - - AWBURST - - - s_axi_awburst - - - - - AWCACHE - - - s_axi_awcache - - - - - AWID - - - s_axi_awid - - - - - AWLEN - - - s_axi_awlen - - - - - AWLOCK - - - s_axi_awlock - - - - - AWPROT - - - s_axi_awprot - - - - - AWQOS - - - s_axi_awqos - - - - - AWREADY - - - s_axi_awready - - - - - AWREGION - - - s_axi_awregion - - - - - AWSIZE - - - s_axi_awsize - - - - - AWUSER - - - s_axi_awuser - - - - - AWVALID - - - s_axi_awvalid - - - - - BID - - - s_axi_bid - - - - - BREADY - - - s_axi_bready - - - - - BRESP - - - s_axi_bresp - - - - - BUSER - - - s_axi_buser - - - - - BVALID - - - s_axi_bvalid - - - - - RDATA - - - s_axi_rdata - - - - - RID - - - s_axi_rid - - - - - RLAST - - - s_axi_rlast - - - - - RREADY - - - s_axi_rready - - - - - RRESP - - - s_axi_rresp - - - - - RUSER - - - s_axi_ruser - - - - - RVALID - - - s_axi_rvalid - - - - - WDATA - - - s_axi_wdata - - - - - WID - - - s_axi_wid - - - - - WLAST - - - s_axi_wlast - - - - - WREADY - - - s_axi_wready - - - - - WSTRB - - - s_axi_wstrb - - - - - WUSER - - - s_axi_wuser - - - - - WVALID - - - s_axi_wvalid - - - - - - DATA_WIDTH - 1 - - - none - - - - - PROTOCOL - AXI4LITE - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - ID_WIDTH - 0 - - - none - - - - - ADDR_WIDTH - 1 - - - none - - - - - AWUSER_WIDTH - 0 - - - none - - - - - ARUSER_WIDTH - 0 - - - none - - - - - WUSER_WIDTH - 0 - - - none - - - - - RUSER_WIDTH - 0 - - - none - - - - - BUSER_WIDTH - 0 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - HAS_BURST - 0 - - - none - - - - - HAS_LOCK - 0 - - - none - - - - - HAS_PROT - 0 - - - none - - - - - HAS_CACHE - 0 - - - none - - - - - HAS_QOS - 0 - - - none - - - - - HAS_REGION - 0 - - - none - - - - - HAS_WSTRB - 0 - - - none - - - - - HAS_BRESP - 0 - - - none - - - - - HAS_RRESP - 0 - - - none - - - - - SUPPORTS_NARROW_BURST - 0 - - - none - - - - - NUM_READ_OUTSTANDING - 1 - - - none - - - - - NUM_WRITE_OUTSTANDING - 1 - - - none - - - - - MAX_BURST_LENGTH - 1 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - NUM_READ_THREADS - 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USED_IN_single_language - xil_defaultlib - - - - xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset - - hdl/axi_infrastructure_v1_1_0.vh - verilogSource - USED_IN_ipstatic - true - axi_infrastructure_v1_1_0 - - - hdl/axi_infrastructure_v1_1_vl_rfs.v - verilogSource - USED_IN_ipstatic - axi_infrastructure_v1_1_0 - - - - - - - - - - - xilinx_verilogbehavioralsimulation_view_fileset - - sim/axi_vip_0_pkg.sv - systemVerilogSource - - - hdl/axi_vip_v1_1_vl_rfs.sv - systemVerilogSource - USED_IN_ipstatic - axi_vip_v1_1_4 - - - - xilinx_verilogsimulationwrapper_view_fileset - - sim/axi_vip_0.sv - systemVerilogSource - xil_defaultlib - - - - The AXI Verification IP. - - - Component_Name - Component Name - axi_vip_0 - - - PROTOCOL - PROTOCOL - AXI4LITE - - - READ_WRITE_MODE - READ_WRITE MODE - READ_WRITE - - - INTERFACE_MODE - INTERFACE MODE - MASTER - - - ADDR_WIDTH - ADDRESS WIDTH - 32 - - - DATA_WIDTH - DATA WIDTH - 32 - - - ID_WIDTH - ID WIDTH - 0 - - - - false - - - - - - AWUSER_WIDTH - AWUSER WIDTH - 0 - - - - false - - - - - - ARUSER_WIDTH - ARUSER WIDTH - 0 - - - - false - - - - - - RUSER_WIDTH - RUSER WIDTH - 0 - - - - false - - - - - - WUSER_WIDTH - WUSER WIDTH - 0 - - - - false - - - - - - BUSER_WIDTH - BUSER WIDTH - 0 - - - - false - - - - - - WUSER_BITS_PER_BYTE - WUSER BITS PER BYTE - 0 - - - - false - - - - - - RUSER_BITS_PER_BYTE - RUSER BITS PER BYTE - 0 - - - - false - - - - - - HAS_USER_BITS_PER_BYTE - HAS USER_BITS_PER_BYTE - 0 - - - - false - - - - - - SUPPORTS_NARROW - SUPPORTS NARROW - 0 - - - - false - - - - - - HAS_BURST - HAS BURST - 0 - - - - false - - - - - - HAS_LOCK - HAS LOCK - 0 - - - - false - - - - - - HAS_CACHE - HAS CACHE - 0 - - - - false - - - - - - HAS_REGION - HAS REGION - 0 - - - - false - - - - - - HAS_QOS - HAS QOS - 0 - - - - false - - - - - - HAS_PROT - HAS PROT - 1 - - - HAS_WSTRB - HAS WSTRB - 1 - - - HAS_BRESP - HAS BRESP - 1 - - - HAS_RRESP - HAS RRESP - 1 - - - HAS_ACLKEN - HAS ACLKEN - 0 - - - HAS_ARESETN - HAS ARESETN - 1 - - - - - AXI Verification IP - 4 - true - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2018.3 - - - - - - - - - - diff --git a/qick/firmware/ip/mr_buffer_et/src/bram_dp.vhd b/qick/firmware/ip/mr_buffer_et/src/bram_dp.vhd deleted file mode 100644 index 86df6ac..0000000 --- a/qick/firmware/ip/mr_buffer_et/src/bram_dp.vhd +++ /dev/null @@ -1,88 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 04/02/2019 09:12:29 AM --- Design Name: --- Module Name: bram_dp - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity bram_dp is - Generic ( - -- Memory address size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - ena : in STD_LOGIC; - enb : in STD_LOGIC; - wea : in STD_LOGIC; - web : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR (N-1 downto 0); - addrb : in STD_LOGIC_VECTOR (N-1 downto 0); - dia : in STD_LOGIC_VECTOR (B-1 downto 0); - dib : in STD_LOGIC_VECTOR (B-1 downto 0); - doa : out STD_LOGIC_VECTOR (B-1 downto 0); - dob : out STD_LOGIC_VECTOR (B-1 downto 0) - ); -end bram_dp; - -architecture Behavioral of bram_dp is - --- Ram type. -type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); -shared variable RAM : ram_type; - -begin - --- CLKA port. -process (clka) -begin - if (clka'event and clka = '1') then - if (ena = '1') then - doa <= RAM(conv_integer(addra)); - if (wea = '1') then - RAM(conv_integer(addra)) := dia; - end if; - end if; - end if; -end process; - --- CLKB port. -process (clkb) -begin - if (clkb'event and clkb = '1') then - if (enb = '1') then - dob <= RAM(conv_integer(addrb)); - if (web = '1') then - RAM(conv_integer(addrb)) := dib; - end if; - end if; - end if; -end process; - -end Behavioral; diff --git a/qick/firmware/ip/mr_buffer_et/src/data_reader.vhd b/qick/firmware/ip/mr_buffer_et/src/data_reader.vhd deleted file mode 100644 index f5708da..0000000 --- a/qick/firmware/ip/mr_buffer_et/src/data_reader.vhd +++ /dev/null @@ -1,338 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 07/26/2019 12:08:45 PM --- Design Name: --- Module Name: data_reader - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity data_reader is - Generic - ( - -- Number of memories. - NM : Integer := 8; - -- Address map of each memory. - N : Integer := 8; - -- Data width. - B : Integer := 16 - ); - Port - ( - -- Reset and clock. - rstn : in std_logic; - clk : in std_logic; - - -- Memory I/F. - mem_en : out std_logic; - mem_we : out std_logic; - mem_addr : out std_logic_vector (N-1 downto 0); - mem_dout : in std_logic_vector (NM*B-1 downto 0); - - -- Data out. - dout : out std_logic_vector (B-1 downto 0); - dready : in std_logic; - dvalid : out std_logic; - dlast : out std_logic; - - -- Registers. - START_REG : in std_logic - ); -end entity; - -architecture Behavioral of data_reader is - -constant NM_LOG2 : Integer := Integer(ceil(log2(real(NM)))); -constant NPOW : Integer := 2**N; - --- Fifo to drive AXI Stream Master I/F. -component fifo is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end component; - -type fsm_state is ( INIT_ST, - READ_ST, - WRITE_ST, - READ_LAST_ST, - WRITE_LAST_ST, - FIFO_ST, - END_ST); -signal current_state, next_state : fsm_state; - -signal init_state : std_logic; -signal read_state : std_logic; -signal write_state : std_logic; -signal fifo_state : std_logic; -signal read_en : std_logic; - --- Counter for memory address. -signal addr_cnt : unsigned(N-1 downto 0); - --- Counter for memory selection. -signal sel_cnt : unsigned(NM_LOG2-1 downto 0); - --- Counter for read data. -signal read_cnt : unsigned(NM_LOG2-1 downto 0); - --- Fifo signals. -signal fifo_wr_en : std_logic; -signal fifo_rd_en : std_logic; -signal fifo_din : std_logic_vector (B-1 downto 0); -signal fifo_dout : std_logic_vector (B-1 downto 0); -signal fifo_full : std_logic; -signal fifo_empty : std_logic; - -signal mem_dout_r : std_logic_vector (NM*B-1 downto 0); - -signal dlast_i : std_logic; - -begin - --- Fifo to drive AXI Stream Master I/F. -fifo_i : fifo - Generic map - ( - -- Data width. - B => B, - - -- Fifo depth. - N => 4 - ) - Port map - ( - rstn => rstn, - clk => clk, - - -- Write I/F. - wr_en => fifo_wr_en, - din => fifo_din, - - -- Read I/F. - rd_en => fifo_rd_en, - dout => fifo_dout, - - -- Flags. - full => fifo_full, - empty => fifo_empty - ); - --- Fifo connections. -fifo_wr_en <= write_state; - -fifo_rd_en <= dready when read_en = '1' else - '0'; - --- Mux for fifo_din. -process(sel_cnt,mem_dout_r) -begin - fifo_din <= (others => '0'); - for I in 0 to NM-1 loop - if ( sel_cnt = to_unsigned(I,sel_cnt'length) ) then - fifo_din <= mem_dout_r((I+1)*B-1 downto I*B); - end if; - end loop; -end process; - --- dlast generation. -dlast_i <= '1' when (read_cnt = to_unsigned(NM-1,read_cnt'length)) and (fifo_state = '1') else - '0'; - -process(clk) -begin - if ( rising_edge(clk) ) then - if ( rstn = '0' ) then - current_state <= INIT_ST; - - addr_cnt <= (others => '0'); - sel_cnt <= (others => '0'); - read_cnt <= (others => '0'); - - mem_dout_r <= (others => '0'); - else - current_state <= next_state; - - if ( init_state = '1' ) then - mem_dout_r <= (others => '0'); - addr_cnt <= (others => '0'); - sel_cnt <= (others => '0'); - elsif ( read_state = '1' ) then - mem_dout_r <= mem_dout; - addr_cnt <= addr_cnt + 1; - elsif ( write_state = '1' ) then - if ( fifo_full = '0' ) then - sel_cnt <= sel_cnt + 1; - end if; - end if; - - if ( init_state = '1' ) then - read_cnt <= (others => '0'); - else - if ( dready = '1' and fifo_empty = '0' ) then - read_cnt <= read_cnt + 1; - end if; - end if; - end if; - end if; -end process; - --- Next state logic. -process (current_state, START_REG, addr_cnt, sel_cnt, fifo_full, fifo_empty) -begin - case current_state is - when INIT_ST => - if (START_REG = '0') then - next_state <= INIT_ST; - else - next_state <= READ_ST; - end if; - - when READ_ST => - next_state <= WRITE_ST; - - when WRITE_ST => - if ( (sel_cnt < to_unsigned(NM-1,sel_cnt'length)) or (fifo_full = '1') ) then - next_state <= WRITE_ST; - elsif ( addr_cnt < to_unsigned(NPOW-1,addr_cnt'length) ) then - next_state <= READ_ST; - else - next_state <= READ_LAST_ST; - end if; - - when READ_LAST_ST => - next_state <= WRITE_LAST_ST; - - when WRITE_LAST_ST => - if ( (sel_cnt < to_unsigned(NM-1,sel_cnt'length)) or (fifo_full = '1') ) then - next_state <= WRITE_LAST_ST; - else - next_state <= FIFO_ST; - end if; - - when FIFO_ST => - if ( fifo_empty = '0' ) then - next_state <= FIFO_ST; - else - next_state <= END_ST; - end if; - - when END_ST => - if ( START_REG = '1' ) then - next_state <= END_ST; - else - next_state <= INIT_ST; - end if; - end case; -end process; - --- Output logic. -process (current_state) -begin -init_state <= '0'; -read_state <= '0'; -write_state <= '0'; -fifo_state <= '0'; -read_en <= '0'; - case current_state is - when INIT_ST => - init_state <= '1'; - read_state <= '0'; - write_state <= '0'; - fifo_state <= '0'; - read_en <= '0'; - - when READ_ST => - init_state <= '0'; - read_state <= '1'; - write_state <= '0'; - fifo_state <= '0'; - read_en <= '1'; - - when WRITE_ST => - init_state <= '0'; - read_state <= '0'; - write_state <= '1'; - fifo_state <= '0'; - read_en <= '1'; - - when READ_LAST_ST => - init_state <= '0'; - read_state <= '1'; - write_state <= '0'; - fifo_state <= '0'; - read_en <= '1'; - - when WRITE_LAST_ST => - init_state <= '0'; - read_state <= '0'; - write_state <= '1'; - fifo_state <= '0'; - read_en <= '1'; - - when FIFO_ST => - init_state <= '0'; - read_state <= '0'; - write_state <= '0'; - fifo_state <= '1'; - read_en <= '1'; - - when END_ST => - init_state <= '0'; - read_state <= '0'; - write_state <= '0'; - fifo_state <= '0'; - read_en <= '0'; - - end case; -end process; - --- Assign outputs. -mem_en <= '1'; -mem_we <= '0'; -mem_addr <= std_logic_vector(addr_cnt); - -dout <= fifo_dout; -dvalid <= not(fifo_empty); -dlast <= dlast_i; - -end Behavioral; diff --git a/qick/firmware/ip/mr_buffer_et/src/data_writer.vhd b/qick/firmware/ip/mr_buffer_et/src/data_writer.vhd deleted file mode 100644 index 0ffe3b6..0000000 --- a/qick/firmware/ip/mr_buffer_et/src/data_writer.vhd +++ /dev/null @@ -1,211 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity data_writer is - Generic - ( - -- Number of memories. - NM : Integer := 8; - -- Address map of each memory. - N : Integer := 8; - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Trigger. - trigger : in std_logic; - - -- AXI Stream I/F. - s_axis_tready : out std_logic; - s_axis_tdata : in std_logic_vector(B-1 downto 0); - s_axis_tvalid : in std_logic; - - -- Memory I/F. - mem_en : out std_logic; - mem_we : out std_logic; - mem_addr : out std_logic_vector (N-1 downto 0); - mem_di : out std_logic_vector (B-1 downto 0); - - -- Registers. - CAPTURE_REG : in std_logic - ); -end entity; - -architecture Behavioral of data_writer is - -constant NPOW : Integer := 2**N; - --- Fifo to interfase with AXI Stream. -component fifo is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end component; - --- State machine. -type fsm_state is ( INIT_ST, - TRIGGER_ST, - CAPTURE_ST, - END_ST); -signal current_state, next_state : fsm_state; - -signal init_state : std_logic; - -signal write_en : std_logic; - -signal fifo_wr_en : std_logic; -signal fifo_rd_en : std_logic; -signal fifo_dout : std_logic_vector (B-1 downto 0); -signal fifo_full : std_logic; -signal fifo_empty : std_logic; - -signal addr_cnt : unsigned (N-1 downto 0); - -begin - --- Fifo to interfase with AXI stream. -fifo_i : fifo - Generic map - ( - -- Data width. - B => B, - - -- Fifo depth. - N => 4 - ) - Port map - ( - rstn => rstn, - clk => clk, - - -- Write I/F. - wr_en => fifo_wr_en, - din => s_axis_tdata, - - -- Read I/F. - rd_en => fifo_rd_en, - dout => fifo_dout, - - -- Flags. - full => fifo_full, - empty => fifo_empty - ); - --- Mux for fifo_wr_en. -fifo_wr_en <= s_axis_tvalid when write_en = '1' else - '0'; - --- fifo_rd_en. -fifo_rd_en <= write_en; - --- Registers. -process (clk) -begin - if (rising_edge(clk)) then - if ( rstn = '0' ) then - current_state <= INIT_ST; - else - current_state <= next_state; - - -- Address counter. - if ( init_state = '1' ) then - addr_cnt <= (others => '0'); - else - if ( write_en = '1' and fifo_empty = '0' ) then - addr_cnt <= addr_cnt + 1; - end if; - end if; - end if; - end if; -end process; - --- Next state logic. -process (current_state, CAPTURE_REG, trigger, addr_cnt) -begin - case current_state is - when INIT_ST => - if (CAPTURE_REG = '0') then - next_state <= INIT_ST; - else - next_state <= TRIGGER_ST; - end if; - - when TRIGGER_ST => - if (trigger = '0') then - next_state <= TRIGGER_ST; - else - next_state <= CAPTURE_ST; - end if; - - when CAPTURE_ST => - if ( addr_cnt < to_unsigned(NPOW-1,addr_cnt'length) ) then - next_state <= CAPTURE_ST; - else - next_state <= END_ST; - end if; - - when END_ST => - if ( CAPTURE_REG = '1' ) then - next_state <= END_ST; - else - next_state <= INIT_ST; - end if; - end case; -end process; - --- Output logic. -process (current_state) -begin -init_state <= '0'; -write_en <= '0'; - case current_state is - when INIT_ST => - init_state <= '1'; - - when TRIGGER_ST => - - when CAPTURE_ST => - write_en <= '1'; - - when END_ST => - - end case; -end process; - --- Assign outputs. -s_axis_tready <= not(fifo_full) when write_en = '1' else - '0'; - -mem_en <= '1'; -mem_we <= write_en; -mem_addr <= std_logic_vector(addr_cnt); -mem_di <= fifo_dout; - -end Behavioral; diff --git a/qick/firmware/ip/mr_buffer_et/src/fifo.vhd b/qick/firmware/ip/mr_buffer_et/src/fifo.vhd deleted file mode 100644 index 2795bb6..0000000 --- a/qick/firmware/ip/mr_buffer_et/src/fifo.vhd +++ /dev/null @@ -1,115 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 07/18/2019 08:35:37 AM --- Design Name: --- Module Name: fifo - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use IEEE.NUMERIC_STD.ALL; - - -entity fifo is - Generic - ( - -- Data width. - B : Integer := 16; - - -- Fifo depth. - N : Integer := 4; - - -- Almost full. - AF : Integer := 3 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Write I/F. - wr_en : in std_logic; - din : in std_logic_vector (B-1 downto 0); - - -- Read I/F. - rd_en : in std_logic; - dout : out std_logic_vector (B-1 downto 0); - - -- Flags. - full : out std_logic; - empty : out std_logic - ); -end fifo; - -architecture Behavioral of fifo is - --- Number of bits of depth. -constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); - --- Registers. -type array_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); -signal regs : array_t; - --- Pointers. -signal wr_ptr : unsigned (N_LOG2-1 downto 0); -signal rd_ptr : unsigned (N_LOG2-1 downto 0); - --- Flags. -signal full_i : std_logic; -signal empty_i : std_logic; - -begin - --- Full/empty signals. -full_i <= '1' when wr_ptr = rd_ptr - 1 else - '0'; -empty_i <= '1' when wr_ptr = rd_ptr else - '0'; - -process (clk) -begin - if ( rising_edge(clk) ) then - if ( rstn = '0' ) then - wr_ptr <= (others => '0'); - rd_ptr <= (others => '0'); - else - -- Write. - if ( wr_en = '1' and full_i = '0' ) then - -- Write data. - regs(to_integer(wr_ptr)) <= din; - - -- Increment pointer. - wr_ptr <= wr_ptr + 1; - end if; - - -- Read. - if ( rd_en = '1' and empty_i = '0' ) then - -- Increment pointer. - rd_ptr <= rd_ptr + 1; - end if; - - end if; - end if; -end process; - --- Assign outputs. -dout <= regs(to_integer(rd_ptr)); -full <= full_i; -empty <= empty_i; - -end Behavioral; diff --git a/qick/firmware/ip/mr_buffer_et/src/mr_buffer.vhd b/qick/firmware/ip/mr_buffer_et/src/mr_buffer.vhd deleted file mode 100644 index a095d8b..0000000 --- a/qick/firmware/ip/mr_buffer_et/src/mr_buffer.vhd +++ /dev/null @@ -1,334 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity mr_buffer is - Generic - ( - -- Number of memories. - NM : Integer := 8; - -- Address map of each memory. - N : Integer := 8; - -- Data width. - B : Integer := 16 - ); - Port - ( - -- Trigger. - trigger : in std_logic; - - -- AXI Stream Slave I/F. - s_axis_aclk : in std_logic; - s_axis_aresetn : in std_logic; - s_axis_tready : out std_logic; - s_axis_tdata : in std_logic_vector(NM*B-1 downto 0); - s_axis_tstrb : in std_logic_vector((NM*B/8)-1 downto 0); - s_axis_tlast : in std_logic; - s_axis_tvalid : in std_logic; - - -- AXI Stream Master I/F. - m_axis_aclk : in std_logic; - m_axis_aresetn : in std_logic; - m_axis_tvalid : out std_logic; - m_axis_tdata : out std_logic_vector(B-1 downto 0); - m_axis_tstrobe : out std_logic_vector((B/8)-1 downto 0); - m_axis_tlast : out std_logic; - m_axis_tready : in std_logic; - - -- Registers. - DW_CAPTURE_REG : in std_logic; - DR_START_REG : in std_logic - - ); -end mr_buffer; - -architecture Behavioral of mr_buffer is - --- Synchronizer. -component synchronizer is - generic ( - N : Integer := 2 - ); - port ( - rstn : in std_logic; - clk : in std_logic; - data_in : in std_logic; - data_out : out std_logic - ); -end component; - --- Memory. -component bram_dp is - Generic ( - -- Memory address size. - N : Integer := 16; - -- Data width. - B : Integer := 16 - ); - Port ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - ena : in STD_LOGIC; - enb : in STD_LOGIC; - wea : in STD_LOGIC; - web : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR (N-1 downto 0); - addrb : in STD_LOGIC_VECTOR (N-1 downto 0); - dia : in STD_LOGIC_VECTOR (B-1 downto 0); - dib : in STD_LOGIC_VECTOR (B-1 downto 0); - doa : out STD_LOGIC_VECTOR (B-1 downto 0); - dob : out STD_LOGIC_VECTOR (B-1 downto 0) - ); -end component; - --- Data writer. -component data_writer is - Generic - ( - -- Number of memories. - NM : Integer := 8; - -- Address map of each memory. - N : Integer := 8; - -- Data width. - B : Integer := 16 - ); - Port - ( - rstn : in std_logic; - clk : in std_logic; - - -- Trigger. - trigger : in std_logic; - - -- AXI Stream I/F. - s_axis_tready : out std_logic; - s_axis_tdata : in std_logic_vector(B-1 downto 0); - s_axis_tvalid : in std_logic; - - -- Memory I/F. - mem_en : out std_logic; - mem_we : out std_logic; - mem_addr : out std_logic_vector (N-1 downto 0); - mem_di : out std_logic_vector (B-1 downto 0); - - -- Registers. - CAPTURE_REG : in std_logic - ); -end component; - --- Data reader. -component data_reader is - Generic - ( - -- Number of memories. - NM : Integer := 8; - -- Address map of each memory. - N : Integer := 8; - -- Data width. - B : Integer := 16 - ); - Port - ( - -- Reset and clock. - rstn : in std_logic; - clk : in std_logic; - - -- Memory I/F. - mem_en : out std_logic; - mem_we : out std_logic; - mem_addr : out std_logic_vector (N-1 downto 0); - mem_dout : in std_logic_vector (NM*B-1 downto 0); - - -- Data out. - dout : out std_logic_vector (B-1 downto 0); - dready : in std_logic; - dvalid : out std_logic; - dlast : out std_logic; - - -- Registers. - START_REG : in std_logic - ); -end component; - --- Re-sync trigger and registers. -signal DW_CAPTURE_REG_resync: std_logic; -signal DR_START_REG_resync : std_logic; -signal trigger_resync : std_logic; - --- ena/enb/wea/web. -signal ena : std_logic_vector (NM-1 downto 0); -signal enb : std_logic; -signal wea : std_logic_vector (NM-1 downto 0); -signal web : std_logic; - --- addra/addrb. -type addr_array_t is array (NM-1 downto 0) of std_logic_vector (N-1 downto 0); -signal addra : addr_array_t; -signal addrb : std_logic_vector (N-1 downto 0); - --- dia/dib/doa/dob/dout. -type di_do_array_t is array (NM-1 downto 0) of std_logic_vector (B-1 downto 0); -signal dia : di_do_array_t; -signal dib : std_logic_vector (B-1 downto 0); -signal doa : di_do_array_t; -signal dob : di_do_array_t; -signal dout : std_logic_vector (B-1 downto 0); - --- Concatenated data for reader. -signal dob_c: std_logic_vector (NM*B-1 downto 0); - --- s_axis_tdata. -type tdata_array_t is array (NM-1 downto 0) of std_logic_vector (B-1 downto 0); -signal s_axis_tdata_i : tdata_array_t; - --- s_axis_tvalid/tready. -signal s_axis_tvalid_i : std_logic_vector (NM-1 downto 0); -signal s_axis_tready_i : std_logic_vector (NM-1 downto 0); - -begin - --- DW_CAPTURE_REG_resync. -DW_CAPTURE_REG_resync_i : synchronizer - generic map ( - N => 2 - ) - port map ( - rstn => s_axis_aresetn, - clk => s_axis_aclk, - data_in => DW_CAPTURE_REG, - data_out => DW_CAPTURE_REG_resync - ); - --- DR_START_REG_resync. -DR_START_REG_resync_i : synchronizer - generic map ( - N => 2 - ) - port map ( - rstn => m_axis_aresetn, - clk => m_axis_aclk, - data_in => DR_START_REG, - data_out => DR_START_REG_resync - ); - --- trigger_resync. -trigger_resync_i : synchronizer - generic map ( - N => 2 - ) - port map ( - rstn => s_axis_aresetn, - clk => s_axis_aclk, - data_in => trigger, - data_out => trigger_resync - ); - -GEN: for I in 0 to NM-1 generate - - -- Memory instantiation. - bram_dp_i : bram_dp - Generic map - ( - -- Memory address size. - N => N, - -- Data width. - B => B - ) - Port map - ( - clka => s_axis_aclk, - clkb => m_axis_aclk, - ena => ena(I), - enb => enb, - wea => wea(I), - web => web, - addra => addra(I), - addrb => addrb, - dia => dia(I), - dib => dib, - doa => doa(I), - dob => dob(I) - ); - - -- Data writer. - data_writer_i : data_writer - Generic map - ( - -- Number of memories. - NM => NM, - -- Address map of each memory. - N => N, - -- Data width. - B => B - ) - Port map - ( - rstn => s_axis_aresetn , - clk => s_axis_aclk , - - -- Trigger. - trigger => trigger_resync , - - -- AXI Stream I/F. - s_axis_tready => s_axis_tready_i(I) , - s_axis_tdata => s_axis_tdata_i(I) , - s_axis_tvalid => s_axis_tvalid_i(I) , - - -- Memory I/F. - mem_en => ena(I) , - mem_we => wea(I) , - mem_addr => addra(I) , - mem_di => dia(I) , - - -- Registers. - CAPTURE_REG => DW_CAPTURE_REG_resync - ); - - -- Input tdata. - s_axis_tdata_i(I) <= s_axis_tdata((I+1)*B-1 downto I*B); - s_axis_tvalid_i(I) <= s_axis_tvalid; - - -- Concatenate output data for port b. - dob_c((I+1)*B-1 downto I*B) <= dob(I); - -end generate GEN; - --- Data reader instantiation. -data_reader_i : data_reader -Generic map -( - -- Number of memories. - NM => NM, - -- Memory address size. - N => N, - -- Data width. - B => B -) -Port map -( - -- Reset and clock. - rstn => m_axis_aresetn, - clk => m_axis_aclk, - - -- Memory I/F. - mem_en => enb, - mem_we => web, - mem_addr => addrb, - mem_dout => dob_c, - - -- Data out. - dout => m_axis_tdata, - dready => m_axis_tready, - dvalid => m_axis_tvalid, - dlast => m_axis_tlast, - - -- Registers. - START_REG => DR_START_REG_resync -); - --- Output assignment. -s_axis_tready <= s_axis_tready_i(0); -m_axis_tstrobe <= (others => '1'); - -end Behavioral; - diff --git a/qick/firmware/ip/mr_buffer_et/src/mr_buffer_v1_0.vhd b/qick/firmware/ip/mr_buffer_et/src/mr_buffer_v1_0.vhd deleted file mode 100644 index 4c5f51b..0000000 --- a/qick/firmware/ip/mr_buffer_et/src/mr_buffer_v1_0.vhd +++ /dev/null @@ -1,186 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity mr_buffer_v1_0 is - generic ( - -- Number of memories. - NM : Integer := 8; - -- Address map of each memory. - N : Integer := 8; - -- Data width. - B : Integer := 16; - - -- Parameters of Axi Slave Bus Interface S00_AXI - C_S00_AXI_DATA_WIDTH : integer := 32; - C_S00_AXI_ADDR_WIDTH : integer := 6 - ); - port ( - -- Trigger. - trigger : in std_logic; - - -- Ports of Axi Slave Bus Interface S00_AXI - s00_axi_aclk : in std_logic; - s00_axi_aresetn : in std_logic; - s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0); - s00_axi_awprot : in std_logic_vector(2 downto 0); - s00_axi_awvalid : in std_logic; - s00_axi_awready : out std_logic; - s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); - s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0); - s00_axi_wvalid : in std_logic; - s00_axi_wready : out std_logic; - s00_axi_bresp : out std_logic_vector(1 downto 0); - s00_axi_bvalid : out std_logic; - s00_axi_bready : in std_logic; - s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0); - s00_axi_arprot : in std_logic_vector(2 downto 0); - s00_axi_arvalid : in std_logic; - s00_axi_arready : out std_logic; - s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); - s00_axi_rresp : out std_logic_vector(1 downto 0); - s00_axi_rvalid : out std_logic; - s00_axi_rready : in std_logic; - - -- Ports of Axi Slave Bus Interface S00_AXIS - s00_axis_aclk : in std_logic; - s00_axis_aresetn: in std_logic; - s00_axis_tready : out std_logic; - s00_axis_tdata : in std_logic_vector(NM*B-1 downto 0); - s00_axis_tstrb : in std_logic_vector((NM*B/8)-1 downto 0); - s00_axis_tlast : in std_logic; - s00_axis_tvalid : in std_logic; - - -- Ports of Axi Master Bus Interface M00_AXIS - m00_axis_aclk : in std_logic; - m00_axis_aresetn : in std_logic; - m00_axis_tvalid : out std_logic; - m00_axis_tdata : out std_logic_vector(B-1 downto 0); - m00_axis_tstrb : out std_logic_vector((B/8)-1 downto 0); - m00_axis_tlast : out std_logic; - m00_axis_tready : in std_logic - ); -end mr_buffer_v1_0; - -architecture arch_imp of mr_buffer_v1_0 is - - -- component declaration - component mr_buffer_v1_0_S00_AXI is - generic ( - -- Number of memories. - NM : Integer := 8; - -- Address map of each memory. - N : Integer := 8; - -- Data width. - B : Integer := 16; - - -- Parameters of Axi Slave Bus Interface S00_AXI - C_S_AXI_DATA_WIDTH : integer := 32; - C_S_AXI_ADDR_WIDTH : integer := 6 - ); - port ( - -- Trigger. - trigger : in std_logic; - - -- Ports of Axi Slave Bus Interface S00_AXI - S_AXI_ACLK : in std_logic; - S_AXI_ARESETN : in std_logic; - S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); - S_AXI_AWPROT : in std_logic_vector(2 downto 0); - S_AXI_AWVALID : in std_logic; - S_AXI_AWREADY : out std_logic; - S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); - S_AXI_WVALID : in std_logic; - S_AXI_WREADY : out std_logic; - S_AXI_BRESP : out std_logic_vector(1 downto 0); - S_AXI_BVALID : out std_logic; - S_AXI_BREADY : in std_logic; - S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); - S_AXI_ARPROT : in std_logic_vector(2 downto 0); - S_AXI_ARVALID : in std_logic; - S_AXI_ARREADY : out std_logic; - S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - S_AXI_RRESP : out std_logic_vector(1 downto 0); - S_AXI_RVALID : out std_logic; - S_AXI_RREADY : in std_logic; - - -- Ports of Axi Slave Bus Interface S00_AXIS - S_AXIS_ACLK : in std_logic; - S_AXIS_ARESETN : in std_logic; - S_AXIS_TREADY : out std_logic; - S_AXIS_TDATA : in std_logic_vector(NM*B-1 downto 0); - S_AXIS_TSTRB : in std_logic_vector((NM*B/8)-1 downto 0); - S_AXIS_TLAST : in std_logic; - S_AXIS_TVALID : in std_logic; - - -- Ports of Axi Master Bus Interface M00_AXIS - M_AXIS_ACLK : in std_logic; - M_AXIS_ARESETN : in std_logic; - M_AXIS_TVALID : out std_logic; - M_AXIS_TDATA : out std_logic_vector(B-1 downto 0); - M_AXIS_TSTRB : out std_logic_vector((B/8)-1 downto 0); - M_AXIS_TLAST : out std_logic; - M_AXIS_TREADY : in std_logic - ); - end component mr_buffer_v1_0_S00_AXI; - -begin - --- Instantiation of Axi Bus Interface S00_AXI -mr_buffer_v1_0_S00_AXI_inst : mr_buffer_v1_0_S00_AXI - generic map ( - NM => NM, - N => N, - B => B, - C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH, - C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH - ) - port map ( - -- Trigger. - trigger => trigger, - - -- Ports of Axi Slave Bus Interface S00_AXI - S_AXI_ACLK => s00_axi_aclk, - S_AXI_ARESETN => s00_axi_aresetn, - S_AXI_AWADDR => s00_axi_awaddr, - S_AXI_AWPROT => s00_axi_awprot, - S_AXI_AWVALID => s00_axi_awvalid, - S_AXI_AWREADY => s00_axi_awready, - S_AXI_WDATA => s00_axi_wdata, - S_AXI_WSTRB => s00_axi_wstrb, - S_AXI_WVALID => s00_axi_wvalid, - S_AXI_WREADY => s00_axi_wready, - S_AXI_BRESP => s00_axi_bresp, - S_AXI_BVALID => s00_axi_bvalid, - S_AXI_BREADY => s00_axi_bready, - S_AXI_ARADDR => s00_axi_araddr, - S_AXI_ARPROT => s00_axi_arprot, - S_AXI_ARVALID => s00_axi_arvalid, - S_AXI_ARREADY => s00_axi_arready, - S_AXI_RDATA => s00_axi_rdata, - S_AXI_RRESP => s00_axi_rresp, - S_AXI_RVALID => s00_axi_rvalid, - S_AXI_RREADY => s00_axi_rready, - - -- Ports of Axi Slave Bus Interface S00_AXIS - S_AXIS_ACLK => s00_axis_aclk, - S_AXIS_ARESETN => s00_axis_aresetn, - S_AXIS_TREADY => s00_axis_tready, - S_AXIS_TDATA => s00_axis_tdata, - S_AXIS_TSTRB => s00_axis_tstrb, - S_AXIS_TLAST => s00_axis_tlast, - S_AXIS_TVALID => s00_axis_tvalid, - - -- Ports of Axi Master Bus Interface M00_AXIS - M_AXIS_ACLK => m00_axis_aclk, - M_AXIS_ARESETN => m00_axis_aresetn, - M_AXIS_TVALID => m00_axis_tvalid, - M_AXIS_TDATA => m00_axis_tdata, - M_AXIS_TSTRB => m00_axis_tstrb, - M_AXIS_TLAST => m00_axis_tlast, - M_AXIS_TREADY => m00_axis_tready - ); - -end arch_imp; - diff --git a/qick/firmware/ip/mr_buffer_et/src/mr_buffer_v1_0_S00_AXI.vhd b/qick/firmware/ip/mr_buffer_et/src/mr_buffer_v1_0_S00_AXI.vhd deleted file mode 100644 index 64e46c0..0000000 --- a/qick/firmware/ip/mr_buffer_et/src/mr_buffer_v1_0_S00_AXI.vhd +++ /dev/null @@ -1,602 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity mr_buffer_v1_0_S00_AXI is - generic ( - -- Number of memories. - NM : Integer := 8; - -- Address map of each memory. - N : Integer := 8; - -- Data width. - B : Integer := 16; - - -- Width of S_AXI data bus - C_S_AXI_DATA_WIDTH : integer := 32; - -- Width of S_AXI address bus - C_S_AXI_ADDR_WIDTH : integer := 6 - ); - port ( - -- Trigger. - trigger : in std_logic; - - -- Ports of Axi Slave Bus Interface S00_AXI - S_AXI_ACLK : in std_logic; - S_AXI_ARESETN : in std_logic; - S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); - S_AXI_AWPROT : in std_logic_vector(2 downto 0); - S_AXI_AWVALID : in std_logic; - S_AXI_AWREADY : out std_logic; - S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); - S_AXI_WVALID : in std_logic; - S_AXI_WREADY : out std_logic; - S_AXI_BRESP : out std_logic_vector(1 downto 0); - S_AXI_BVALID : out std_logic; - S_AXI_BREADY : in std_logic; - S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); - S_AXI_ARPROT : in std_logic_vector(2 downto 0); - S_AXI_ARVALID : in std_logic; - S_AXI_ARREADY : out std_logic; - S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - S_AXI_RRESP : out std_logic_vector(1 downto 0); - S_AXI_RVALID : out std_logic; - S_AXI_RREADY : in std_logic; - - -- Ports of Axi Slave Bus Interface S00_AXIS - S_AXIS_ACLK : in std_logic; - S_AXIS_ARESETN : in std_logic; - S_AXIS_TREADY : out std_logic; - S_AXIS_TDATA : in std_logic_vector(NM*B-1 downto 0); - S_AXIS_TSTRB : in std_logic_vector((NM*B/8)-1 downto 0); - S_AXIS_TLAST : in std_logic; - S_AXIS_TVALID : in std_logic; - - -- Ports of Axi Master Bus Interface M00_AXIS - M_AXIS_ACLK : in std_logic; - M_AXIS_ARESETN : in std_logic; - M_AXIS_TVALID : out std_logic; - M_AXIS_TDATA : out std_logic_vector(B-1 downto 0); - M_AXIS_TSTRB : out std_logic_vector((B/8)-1 downto 0); - M_AXIS_TLAST : out std_logic; - M_AXIS_TREADY : in std_logic - ); -end mr_buffer_v1_0_S00_AXI; - -architecture arch_imp of mr_buffer_v1_0_S00_AXI is - - -- AXI4LITE signals - signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); - signal axi_awready : std_logic; - signal axi_wready : std_logic; - signal axi_bresp : std_logic_vector(1 downto 0); - signal axi_bvalid : std_logic; - signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); - signal axi_arready : std_logic; - signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - signal axi_rresp : std_logic_vector(1 downto 0); - signal axi_rvalid : std_logic; - - -- Example-specific design signals - -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH - -- ADDR_LSB is used for addressing 32/64 bit registers/memories - -- ADDR_LSB = 2 for 32 bits (n downto 2) - -- ADDR_LSB = 3 for 64 bits (n downto 3) - constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1; - constant OPT_MEM_ADDR_BITS : integer := 3; - ------------------------------------------------ - ---- Signals for user logic register space example - -------------------------------------------------- - ---- Number of Slave Registers 16 - signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - signal slv_reg_rden : std_logic; - signal slv_reg_wren : std_logic; - signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - signal byte_index : integer; - signal aw_en : std_logic; - - component mr_buffer is - Generic - ( - -- Number of memories. - NM : Integer := 8; - -- Address map of each memory. - N : Integer := 8; - -- Data width. - B : Integer := 16 - ); - Port - ( - -- Trigger. - trigger : in std_logic; - - -- AXI Stream Slave I/F. - s_axis_aclk : in std_logic; - s_axis_aresetn : in std_logic; - s_axis_tready : out std_logic; - s_axis_tdata : in std_logic_vector(NM*B-1 downto 0); - s_axis_tstrb : in std_logic_vector((NM*B/8)-1 downto 0); - s_axis_tlast : in std_logic; - s_axis_tvalid : in std_logic; - - -- AXI Stream Master I/F. - m_axis_aclk : in std_logic; - m_axis_aresetn : in std_logic; - m_axis_tvalid : out std_logic; - m_axis_tdata : out std_logic_vector(B-1 downto 0); - m_axis_tstrobe : out std_logic_vector((B/8)-1 downto 0); - m_axis_tlast : out std_logic; - m_axis_tready : in std_logic; - - -- Registers. - DW_CAPTURE_REG : in std_logic; - DR_START_REG : in std_logic - - ); - end component; - -begin - -- I/O Connections assignments - - S_AXI_AWREADY <= axi_awready; - S_AXI_WREADY <= axi_wready; - S_AXI_BRESP <= axi_bresp; - S_AXI_BVALID <= axi_bvalid; - S_AXI_ARREADY <= axi_arready; - S_AXI_RDATA <= axi_rdata; - S_AXI_RRESP <= axi_rresp; - S_AXI_RVALID <= axi_rvalid; - -- Implement axi_awready generation - -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is - -- de-asserted when reset is low. - - process (S_AXI_ACLK) - begin - if rising_edge(S_AXI_ACLK) then - if S_AXI_ARESETN = '0' then - axi_awready <= '0'; - aw_en <= '1'; - else - if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then - -- slave is ready to accept write address when - -- there is a valid write address and write data - -- on the write address and data bus. This design - -- expects no outstanding transactions. - axi_awready <= '1'; - aw_en <= '0'; - elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then - aw_en <= '1'; - axi_awready <= '0'; - else - axi_awready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement axi_awaddr latching - -- This process is used to latch the address when both - -- S_AXI_AWVALID and S_AXI_WVALID are valid. - - process (S_AXI_ACLK) - begin - if rising_edge(S_AXI_ACLK) then - if S_AXI_ARESETN = '0' then - axi_awaddr <= (others => '0'); - else - if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then - -- Write Address latching - axi_awaddr <= S_AXI_AWADDR; - end if; - end if; - end if; - end process; - - -- Implement axi_wready generation - -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is - -- de-asserted when reset is low. - - process (S_AXI_ACLK) - begin - if rising_edge(S_AXI_ACLK) then - if S_AXI_ARESETN = '0' then - axi_wready <= '0'; - else - if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then - -- slave is ready to accept write data when - -- there is a valid write address and write data - -- on the write address and data bus. This design - -- expects no outstanding transactions. - axi_wready <= '1'; - else - axi_wready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement memory mapped register select and write logic generation - -- The write data is accepted and written to memory mapped registers when - -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to - -- select byte enables of slave registers while writing. - -- These registers are cleared when reset (active low) is applied. - -- Slave register write enable is asserted when valid address and data are available - -- and the slave is ready to accept the write address and write data. - slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ; - - process (S_AXI_ACLK) - variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); - begin - if rising_edge(S_AXI_ACLK) then - if S_AXI_ARESETN = '0' then - slv_reg0 <= (others => '0'); - slv_reg1 <= (others => '0'); - slv_reg2 <= (others => '0'); - slv_reg3 <= (others => '0'); - slv_reg4 <= (others => '0'); - slv_reg5 <= (others => '0'); - slv_reg6 <= (others => '0'); - slv_reg7 <= (others => '0'); - slv_reg8 <= (others => '0'); - slv_reg9 <= (others => '0'); - slv_reg10 <= (others => '0'); - slv_reg11 <= (others => '0'); - slv_reg12 <= (others => '0'); - slv_reg13 <= (others => '0'); - slv_reg14 <= (others => '0'); - slv_reg15 <= (others => '0'); - else - loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); - if (slv_reg_wren = '1') then - case loc_addr is - when b"0000" => - for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop - if ( S_AXI_WSTRB(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 0 - slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0001" => - for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop - if ( S_AXI_WSTRB(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 1 - slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0010" => - for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop - if ( S_AXI_WSTRB(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 2 - slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0011" => - for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop - if ( S_AXI_WSTRB(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 3 - slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0100" => - for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop - if ( S_AXI_WSTRB(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 4 - slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0101" => - for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop - if ( S_AXI_WSTRB(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 5 - slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0110" => - for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop - if ( S_AXI_WSTRB(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 6 - slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"0111" => - for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop - if ( S_AXI_WSTRB(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 7 - slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1000" => - for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop - if ( S_AXI_WSTRB(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 8 - slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1001" => - for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop - if ( S_AXI_WSTRB(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 9 - slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1010" => - for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop - if ( S_AXI_WSTRB(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 10 - slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1011" => - for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop - if ( S_AXI_WSTRB(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 11 - slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1100" => - for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop - if ( S_AXI_WSTRB(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 12 - slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1101" => - for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop - if ( S_AXI_WSTRB(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 13 - slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1110" => - for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop - if ( S_AXI_WSTRB(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 14 - slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when b"1111" => - for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop - if ( S_AXI_WSTRB(byte_index) = '1' ) then - -- Respective byte enables are asserted as per write strobes - -- slave registor 15 - slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); - end if; - end loop; - when others => - slv_reg0 <= slv_reg0; - slv_reg1 <= slv_reg1; - slv_reg2 <= slv_reg2; - slv_reg3 <= slv_reg3; - slv_reg4 <= slv_reg4; - slv_reg5 <= slv_reg5; - slv_reg6 <= slv_reg6; - slv_reg7 <= slv_reg7; - slv_reg8 <= slv_reg8; - slv_reg9 <= slv_reg9; - slv_reg10 <= slv_reg10; - slv_reg11 <= slv_reg11; - slv_reg12 <= slv_reg12; - slv_reg13 <= slv_reg13; - slv_reg14 <= slv_reg14; - slv_reg15 <= slv_reg15; - end case; - end if; - end if; - end if; - end process; - - -- Implement write response logic generation - -- The write response and response valid signals are asserted by the slave - -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. - -- This marks the acceptance of address and indicates the status of - -- write transaction. - - process (S_AXI_ACLK) - begin - if rising_edge(S_AXI_ACLK) then - if S_AXI_ARESETN = '0' then - axi_bvalid <= '0'; - axi_bresp <= "00"; --need to work more on the responses - else - if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then - axi_bvalid <= '1'; - axi_bresp <= "00"; - elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) - axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) - end if; - end if; - end if; - end process; - - -- Implement axi_arready generation - -- axi_arready is asserted for one S_AXI_ACLK clock cycle when - -- S_AXI_ARVALID is asserted. axi_awready is - -- de-asserted when reset (active low) is asserted. - -- The read address is also latched when S_AXI_ARVALID is - -- asserted. axi_araddr is reset to zero on reset assertion. - - process (S_AXI_ACLK) - begin - if rising_edge(S_AXI_ACLK) then - if S_AXI_ARESETN = '0' then - axi_arready <= '0'; - axi_araddr <= (others => '1'); - else - if (axi_arready = '0' and S_AXI_ARVALID = '1') then - -- indicates that the slave has acceped the valid read address - axi_arready <= '1'; - -- Read Address latching - axi_araddr <= S_AXI_ARADDR; - else - axi_arready <= '0'; - end if; - end if; - end if; - end process; - - -- Implement axi_arvalid generation - -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both - -- S_AXI_ARVALID and axi_arready are asserted. The slave registers - -- data are available on the axi_rdata bus at this instance. The - -- assertion of axi_rvalid marks the validity of read data on the - -- bus and axi_rresp indicates the status of read transaction.axi_rvalid - -- is deasserted on reset (active low). axi_rresp and axi_rdata are - -- cleared to zero on reset (active low). - process (S_AXI_ACLK) - begin - if rising_edge(S_AXI_ACLK) then - if S_AXI_ARESETN = '0' then - axi_rvalid <= '0'; - axi_rresp <= "00"; - else - if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then - -- Valid read data is available at the read data bus - axi_rvalid <= '1'; - axi_rresp <= "00"; -- 'OKAY' response - elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then - -- Read data is accepted by the master - axi_rvalid <= '0'; - end if; - end if; - end if; - end process; - - -- Implement memory mapped register select and read logic generation - -- Slave register read enable is asserted when valid address is available - -- and the slave is ready to accept the read address. - slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ; - - process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, S_AXI_ARESETN, slv_reg_rden) - variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); - begin - -- Address decoding for reading registers - loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); - case loc_addr is - when b"0000" => - reg_data_out <= slv_reg0; - when b"0001" => - reg_data_out <= slv_reg1; - when b"0010" => - reg_data_out <= slv_reg2; - when b"0011" => - reg_data_out <= slv_reg3; - when b"0100" => - reg_data_out <= slv_reg4; - when b"0101" => - reg_data_out <= slv_reg5; - when b"0110" => - reg_data_out <= slv_reg6; - when b"0111" => - reg_data_out <= slv_reg7; - when b"1000" => - reg_data_out <= slv_reg8; - when b"1001" => - reg_data_out <= slv_reg9; - when b"1010" => - reg_data_out <= slv_reg10; - when b"1011" => - reg_data_out <= slv_reg11; - when b"1100" => - reg_data_out <= slv_reg12; - when b"1101" => - reg_data_out <= slv_reg13; - when b"1110" => - reg_data_out <= slv_reg14; - when b"1111" => - reg_data_out <= slv_reg15; - when others => - reg_data_out <= (others => '0'); - end case; - end process; - - -- Output register or memory read data - process( S_AXI_ACLK ) is - begin - if (rising_edge (S_AXI_ACLK)) then - if ( S_AXI_ARESETN = '0' ) then - axi_rdata <= (others => '0'); - else - if (slv_reg_rden = '1') then - -- When there is a valid read address (S_AXI_ARVALID) with - -- acceptance of read address by the slave (axi_arready), - -- output the read dada - -- Read address mux - axi_rdata <= reg_data_out; -- register read data - end if; - end if; - end if; - end process; - - mr_buffer_i : mr_buffer - Generic map - ( - -- Number of memories. - NM => NM, - -- Address map of each memory. - N => N, - -- Data width. - B => B - ) - Port map - ( - -- Trigger. - trigger => trigger, - - -- AXI Stream Slave I/F. - s_axis_aclk => S_AXIS_ACLK, - s_axis_aresetn => S_AXIS_ARESETN, - s_axis_tready => S_AXIS_TREADY, - s_axis_tdata => S_AXIS_TDATA, - s_axis_tstrb => S_AXIS_TSTRB, - s_axis_tlast => S_AXIS_TLAST, - s_axis_tvalid => S_AXIS_TVALID, - - -- AXI Stream Master I/F. - m_axis_aclk => M_AXIS_ACLK, - m_axis_aresetn => M_AXIS_ARESETN, - m_axis_tvalid => M_AXIS_TVALID, - m_axis_tdata => M_AXIS_TDATA, - m_axis_tstrobe => M_AXIS_TSTRB, - m_axis_tlast => M_AXIS_TLAST, - m_axis_tready => M_AXIS_TREADY, - - -- Registers. - DW_CAPTURE_REG => slv_reg0(0), - DR_START_REG => slv_reg1(0) - - ); - -end arch_imp; - diff --git a/qick/firmware/ip/mr_buffer_et/src/synchronizer.vhd b/qick/firmware/ip/mr_buffer_et/src/synchronizer.vhd deleted file mode 100644 index 3a3ed27..0000000 --- a/qick/firmware/ip/mr_buffer_et/src/synchronizer.vhd +++ /dev/null @@ -1,40 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library common_lib; -use common_lib.all; - -entity synchronizer is - generic ( - N : Integer := 2 - ); - port ( - rstn : in std_logic; - clk : in std_logic; - data_in : in std_logic; - data_out : out std_logic - ); -end synchronizer; - -architecture rtl of synchronizer is - --- Internal register. -signal data_int_reg : std_logic_vector (N-1 downto 0); - -begin - -process(clk,rstn) -begin - if (rstn = '0') then - data_int_reg <= (others => '0'); -- 1 FF. - elsif (clk'event and clk='1') then - data_int_reg <= data_int_reg(N-2 downto 0) & data_in; - end if; -end process; - --- Assign output. -data_out <= data_int_reg(N-1); - -end rtl; - diff --git a/qick/firmware/ip/mr_buffer_et/src/tb.sv b/qick/firmware/ip/mr_buffer_et/src/tb.sv deleted file mode 100644 index 95991bd..0000000 --- a/qick/firmware/ip/mr_buffer_et/src/tb.sv +++ /dev/null @@ -1,345 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 02/19/2019 01:38:28 PM -// Design Name: -// Module Name: tb -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - -import axi_vip_pkg::*; -import axi_vip_0_pkg::*; -import axi4stream_vip_pkg::*; -import axi4stream_vip_0_pkg::*; -import axi4stream_vip_1_pkg::*; - -module tb( - ); - -// AXI signals. -reg aclk = 0; -reg aresetn; -reg trigger; -wire [31:0] m_axi_awaddr; -wire [2:0] m_axi_awprot; -wire m_axi_awvalid; -wire m_axi_awready; -wire [31:0] m_axi_wdata; -wire [3:0] m_axi_wstrb; -wire m_axi_wvalid; -wire m_axi_wready; -wire [1:0] m_axi_bresp; -wire m_axi_bvalid; -wire m_axi_bready; -wire [31:0] m_axi_araddr; -wire [2:0] m_axi_arprot; -wire m_axi_arvalid; -wire m_axi_arready; -wire [31:0] m_axi_rdata; -wire [1:0] m_axi_rresp; -wire m_axi_rvalid; -wire m_axi_rready; - -// AXIS Master signals. -reg m_axis_aclk = 0; -reg m_axis_aresetn; -wire m_axis_tvalid; -wire m_axis_tready; -wire [7:0] m_axis_tdata; - -// AXIS Slave signals. -reg s_axis_aclk = 0; -reg s_axis_aresetn; -wire s_axis_tready; -wire [31:0] s_axis_tdata; -wire s_axis_tvalid; - -axi4stream_transaction wr_transaction; -axi4stream_ready_gen ready_gen; - -xil_axi_ulong addr_DW_CAPTURE_REG = 32'h44A00000; // 0 -xil_axi_ulong addr_DR_START_REG = 32'h44A00004; // 1 - -xil_axi_prot_t prot = 0; -reg[31:0] data_wr=32'h01234567; -reg[31:0] data_rd=32'h01234567; -xil_axi_resp_t resp; - -// AXI Master VIP. -axi_vip_0 axi_vip_i ( - .aclk(aclk), // input wire aclk - .aresetn(aresetn), // input wire aresetn - .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr - .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot - .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid - .m_axi_awready(m_axi_awready), // input wire m_axi_awready - .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata - .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb - .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid - .m_axi_wready(m_axi_wready), // input wire m_axi_wready - .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp - .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid - .m_axi_bready(m_axi_bready), // output wire m_axi_bready - .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr - .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot - .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid - .m_axi_arready(m_axi_arready), // input wire m_axi_arready - .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata - .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp - .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid - .m_axi_rready(m_axi_rready) // output wire m_axi_rready -); - -// AXIS Master VIP. -axi4stream_vip_1 axis_mst_vip_i ( - .aclk(s_axis_aclk), // input wire aclk - .aresetn(s_axis_aresetn), // input wire aresetn - .m_axis_tvalid(s_axis_tvalid), // output wire [0 : 0] m_axis_tvalid - .m_axis_tready(s_axis_tready), // input wire [0 : 0] m_axis_tready - .m_axis_tdata(s_axis_tdata) // output wire [7 : 0] m_axis_tdata -); - -// AXIS Slave VIP. -axi4stream_vip_0 axis_slv_vip_i ( - .aclk(m_axis_aclk), // input wire aclk - .aresetn(m_axis_aresetn), // input wire aresetn - .s_axis_tvalid(m_axis_tvalid), // input wire [0 : 0] s_axis_tvalid - .s_axis_tready(m_axis_tready), // output wire [0 : 0] s_axis_tready - .s_axis_tdata(m_axis_tdata) // input wire [31 : 0] s_axis_tdata -); - -// Instantiate DUT. -mr_buffer_v1_0 - #(.NM(4), .N(4), .B(8)) - DUT ( - .trigger(trigger), - .s00_axi_aclk(aclk), - .s00_axi_aresetn(aresetn), - .s00_axi_awaddr(m_axi_awaddr), - .s00_axi_awprot(m_axi_awprot), - .s00_axi_awvalid(m_axi_awvalid), - .s00_axi_awready(m_axi_awready), - .s00_axi_wdata(m_axi_wdata), - .s00_axi_wstrb(m_axi_wstrb), - .s00_axi_wvalid(m_axi_wvalid), - .s00_axi_wready(m_axi_wready), - .s00_axi_bresp(m_axi_bresp), - .s00_axi_bvalid(m_axi_bvalid), - .s00_axi_bready(m_axi_bready), - .s00_axi_araddr(m_axi_araddr), - .s00_axi_arprot(m_axi_arprot), - .s00_axi_arvalid(m_axi_arvalid), - .s00_axi_arready(m_axi_arready), - .s00_axi_rdata(m_axi_rdata), - .s00_axi_rresp(m_axi_rresp), - .s00_axi_rvalid(m_axi_rvalid), - .s00_axi_rready(m_axi_rready), - .s00_axis_aclk(s_axis_aclk), - .s00_axis_aresetn(s_axis_aresetn), - .s00_axis_tready(s_axis_tready), - .s00_axis_tdata(s_axis_tdata), - .s00_axis_tstrb(), - .s00_axis_tlast(), - .s00_axis_tvalid(s_axis_tvalid), - .m00_axis_aclk(m_axis_aclk), - .m00_axis_aresetn(m_axis_aresetn), - .m00_axis_tvalid(m_axis_tvalid), - .m00_axis_tdata(m_axis_tdata), - .m00_axis_tstrb(), - .m00_axis_tlast(), - .m00_axis_tready(m_axis_tready)); - -// Declare AXI master VIP agent. -axi_vip_0_mst_t mst_agent; - -// Declare AXIS master VIP agent. -axi4stream_vip_1_mst_t axis_mst_agent; - -// Declare AXIS slave VIP agent. -axi4stream_vip_0_slv_t axis_slv_agent; - -initial begin - // Create agentt. - mst_agent = new("axi master vip agent", axi_vip_i.inst.IF); - axis_mst_agent = new("axis master vip agent", axis_mst_vip_i.inst.IF); - axis_slv_agent = new("axis slave vip agent", axis_slv_vip_i.inst.IF); - - // Set tag for agent to ease debug. - mst_agent.set_agent_tag("AXI Master VIP"); - axis_mst_agent.set_agent_tag("AXIS Master VIP"); - axis_slv_agent.set_agent_tag("AXIS Slave VIP"); - - // Set print verbosity level. - mst_agent.set_verbosity(400); - axis_mst_agent.set_verbosity(400); - axis_slv_agent.set_verbosity(400); - - /*************************************************************************************************** - * When bus is in idle, it must drive everything to 0.otherwise it will - * trigger false assertion failure from axi_protocol_chekcer - ***************************************************************************************************/ - - axis_mst_agent.vif_proxy.set_dummy_drive_type(XIL_AXI4STREAM_VIF_DRIVE_NONE); - axis_slv_agent.vif_proxy.set_dummy_drive_type(XIL_AXI4STREAM_VIF_DRIVE_NONE); - - /* - DW_CAPTURE_REG : 1 bit. - -> 0 : disable capture. - -> 1 : enable capture. - - DR_START_REG : 1 bit. - -> 0 : stop. - -> 1 : start. - - trigger : 1 bit. - -> 0 : wait. - -> 1 : start capture. - */ - - // Start the agent. - mst_agent.start_master(); - axis_mst_agent.start_master(); - axis_slv_agent.start_slave(); - - // dready generator. - ready_gen = axis_slv_agent.driver.create_ready("ready_gen"); - ready_gen.set_ready_policy(XIL_AXI4STREAM_READY_GEN_EVENTS); - ready_gen.set_low_time(4); - ready_gen.set_event_count(25); - - trigger <= 0; - - // Reset sequence. - aresetn = 0; - m_axis_aresetn = 0; - s_axis_aresetn = 0; - #200; - aresetn = 1; - m_axis_aresetn = 1; - s_axis_aresetn = 1; - #200; - - // Write DW_CAPTURE_REG. - data_wr = 1; - mst_agent.AXI4LITE_WRITE_BURST(addr_DW_CAPTURE_REG,prot,data_wr,resp); - #200; - - // Send data. - fork - gen_0(8,10); - join_none - - #1000; - - // Trigger. - trigger <= 1; - - // Send data. - fork - gen_0(8,0); - join - - #1000 - trigger <= 0; - - // Write DW_CAPTURE_REG. - data_wr = 0; - mst_agent.AXI4LITE_WRITE_BURST(addr_DW_CAPTURE_REG,prot,data_wr,resp); - #200; - - #1000; - - // Write DW_CAPTURE_REG. - data_wr = 1; - mst_agent.AXI4LITE_WRITE_BURST(addr_DW_CAPTURE_REG,prot,data_wr,resp); - #200; - - #200; - - // Write DW_CAPTURE_REG. - data_wr = 0; - mst_agent.AXI4LITE_WRITE_BURST(addr_DW_CAPTURE_REG,prot,data_wr,resp); - #200; - - // Send data. - fork - gen_0(16,10); - join_none - - #100; - trigger <= 1; - - #1000; - - // Write DR_START_REG. - data_wr = 1; - mst_agent.AXI4LITE_WRITE_BURST(addr_DR_START_REG,prot,data_wr,resp); - #200; - - // Write DR_START_REG. - data_wr = 0; - mst_agent.AXI4LITE_WRITE_BURST(addr_DR_START_REG,prot,data_wr,resp); - #200; - - #2000; - - axis_slv_agent.driver.send_tready(ready_gen); - - // Write DR_START_REG. - data_wr = 1; - mst_agent.AXI4LITE_WRITE_BURST(addr_DR_START_REG,prot,data_wr,resp); - #200; - - // Write DR_START_REG. - data_wr = 0; - mst_agent.AXI4LITE_WRITE_BURST(addr_DR_START_REG,prot,data_wr,resp); - #200; - - #1000; -end - -// aclk. -always begin - #10; aclk = ~aclk; -end - -//m_axis_aclk -always begin - #4; m_axis_aclk = ~m_axis_aclk; -end - -//s_axis_aclk -always begin - #3; s_axis_aclk = ~s_axis_aclk; -end - -task gen_0(input bit [31:0] cnt, input bit [31:0] delay); - // Create transaction. - axi4stream_transaction wr_transaction; - wr_transaction = axis_mst_agent.driver.create_transaction("Master 0 VIP write transaction"); - - // Set transaction parameters. - wr_transaction.set_xfer_alignment(XIL_AXI4STREAM_XFER_RANDOM); - wr_transaction.set_delay(0); - - // Send transactions. - for (int i=0; i < cnt; i++) - begin - WR_TRANSACTION_FAIL: assert(wr_transaction.randomize()); - axis_mst_agent.driver.send(wr_transaction); - end -endtask - -endmodule diff --git a/qick/firmware/ip/mr_buffer_et/xgui/mr_buffer_et_v1_0.tcl b/qick/firmware/ip/mr_buffer_et/xgui/mr_buffer_et_v1_0.tcl deleted file mode 100644 index 4c44d73..0000000 --- a/qick/firmware/ip/mr_buffer_et/xgui/mr_buffer_et_v1_0.tcl +++ /dev/null @@ -1,85 +0,0 @@ -# Definitional proc to organize widgets for parameters. -proc init_gui { IPINST } { - ipgui::add_param $IPINST -name "Component_Name" - #Adding Page - set Page_0 [ipgui::add_page $IPINST -name "Page 0"] - ipgui::add_param $IPINST -name "B" -parent ${Page_0} - ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0} - ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} - ipgui::add_param $IPINST -name "N" -parent ${Page_0} - ipgui::add_param $IPINST -name "NM" -parent ${Page_0} - - -} - -proc update_PARAM_VALUE.B { PARAM_VALUE.B } { - # Procedure called to update B when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.B { PARAM_VALUE.B } { - # Procedure called to validate B - return true -} - -proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { - # Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { - # Procedure called to validate C_S00_AXI_ADDR_WIDTH - return true -} - -proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { - # Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { - # Procedure called to validate C_S00_AXI_DATA_WIDTH - return true -} - -proc update_PARAM_VALUE.N { PARAM_VALUE.N } { - # Procedure called to update N when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.N { PARAM_VALUE.N } { - # Procedure called to validate N - return true -} - -proc update_PARAM_VALUE.NM { PARAM_VALUE.NM } { - # Procedure called to update NM when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.NM { PARAM_VALUE.NM } { - # Procedure called to validate NM - return true -} - - -proc update_MODELPARAM_VALUE.NM { MODELPARAM_VALUE.NM PARAM_VALUE.NM } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.NM}] ${MODELPARAM_VALUE.NM} -} - -proc update_MODELPARAM_VALUE.N { MODELPARAM_VALUE.N PARAM_VALUE.N } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.N}] ${MODELPARAM_VALUE.N} -} - -proc update_MODELPARAM_VALUE.B { MODELPARAM_VALUE.B PARAM_VALUE.B } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.B}] ${MODELPARAM_VALUE.B} -} - -proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH} -} - -proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH} -} - diff --git a/qick/firmware/out/qick_111.bit b/qick/firmware/out/qick_111.bit deleted file mode 100644 index 1010330..0000000 --- a/qick/firmware/out/qick_111.bit +++ /dev/null @@ -1 +0,0 @@ -../top_111/top_111.runs/impl_1/d_1_wrapper.bit \ No newline at end of file diff --git a/qick/firmware/out/qick_111.hwh b/qick/firmware/out/qick_111.hwh deleted file mode 100644 index 79c7c05..0000000 --- a/qick/firmware/out/qick_111.hwh +++ /dev/null @@ -1 +0,0 @@ -../top_111/top_111.gen/sources_1/bd/d_1/hw_handoff/d_1.hwh \ No newline at end of file diff --git a/qick/firmware/out/qick_111.ltx b/qick/firmware/out/qick_111.ltx deleted file mode 100644 index edf5ecf..0000000 --- a/qick/firmware/out/qick_111.ltx +++ /dev/null @@ -1 +0,0 @@ -../top_111/top_111.runs/impl_1/d_1_wrapper.ltx \ No newline at end of file diff --git a/qick/firmware/out/qick_111_rfbv1.bit b/qick/firmware/out/qick_111_rfbv1.bit deleted file mode 100644 index 7417f05..0000000 --- a/qick/firmware/out/qick_111_rfbv1.bit +++ /dev/null @@ -1 +0,0 @@ -../top_111_rfbv1/top_111_rfbv1.runs/impl_1/d_1_wrapper.bit \ No newline at end of file diff --git a/qick/firmware/out/qick_111_rfbv1.hwh b/qick/firmware/out/qick_111_rfbv1.hwh deleted file mode 100644 index b2f3cd5..0000000 --- a/qick/firmware/out/qick_111_rfbv1.hwh +++ /dev/null @@ -1 +0,0 @@ -../top_111_rfbv1/top_111_rfbv1.gen/sources_1/bd/d_1/hw_handoff/d_1.hwh \ No newline at end of file diff --git a/qick/firmware/out/qick_111_rfbv1.ltx b/qick/firmware/out/qick_111_rfbv1.ltx deleted file mode 100644 index 3e85172..0000000 --- a/qick/firmware/out/qick_111_rfbv1.ltx +++ /dev/null @@ -1 +0,0 @@ -../top_111_rfbv1/top_111_rfbv1.runs/impl_1/d_1_wrapper.ltx \ No newline at end of file diff --git a/qick/firmware/out/qick_111_rfbv2.bit b/qick/firmware/out/qick_111_rfbv2.bit deleted file mode 100644 index 6cb598b..0000000 --- a/qick/firmware/out/qick_111_rfbv2.bit +++ /dev/null @@ -1 +0,0 @@ -../top_111_rfbv2/top_111_rfbv2.runs/impl_1/d_1_wrapper.bit \ No newline at end of file diff --git a/qick/firmware/out/qick_111_rfbv2.hwh b/qick/firmware/out/qick_111_rfbv2.hwh deleted file mode 100644 index 98df3f9..0000000 --- a/qick/firmware/out/qick_111_rfbv2.hwh +++ /dev/null @@ -1 +0,0 @@ -../top_111_rfbv2/top_111_rfbv2.gen/sources_1/bd/d_1/hw_handoff/d_1.hwh \ No newline at end of file diff --git a/qick/firmware/out/qick_111_rfbv2.ltx b/qick/firmware/out/qick_111_rfbv2.ltx deleted file mode 100644 index ca455ce..0000000 --- a/qick/firmware/out/qick_111_rfbv2.ltx +++ /dev/null @@ -1 +0,0 @@ -../top_111_rfbv2/top_111_rfbv2.runs/impl_1/d_1_wrapper.ltx \ No newline at end of file diff --git a/qick/firmware/out/qick_216.bit b/qick/firmware/out/qick_216.bit deleted file mode 100644 index 5600f66..0000000 --- a/qick/firmware/out/qick_216.bit +++ /dev/null @@ -1 +0,0 @@ -../top_216/top_216.runs/impl_1/d_1_wrapper.bit \ No newline at end of file diff --git a/qick/firmware/out/qick_216.hwh b/qick/firmware/out/qick_216.hwh deleted file mode 100644 index 2ad1539..0000000 --- a/qick/firmware/out/qick_216.hwh +++ /dev/null @@ -1 +0,0 @@ -../top_216/top_216.gen/sources_1/bd/d_1/hw_handoff/d_1.hwh \ No newline at end of file diff --git a/qick/firmware/out/qick_4x2.bit b/qick/firmware/out/qick_4x2.bit deleted file mode 100644 index afdac17..0000000 --- a/qick/firmware/out/qick_4x2.bit +++ /dev/null @@ -1 +0,0 @@ -../top_4x2/top_4x2.runs/impl_1/d_1_wrapper.bit \ No newline at end of file diff --git a/qick/firmware/out/qick_4x2.hwh b/qick/firmware/out/qick_4x2.hwh deleted file mode 100644 index 7d2bb3c..0000000 --- a/qick/firmware/out/qick_4x2.hwh +++ /dev/null @@ -1 +0,0 @@ -../top_4x2/top_4x2.gen/sources_1/bd/d_1/hw_handoff/d_1.hwh \ No newline at end of file diff --git a/qick/firmware/proj_111.tcl b/qick/firmware/proj_111.tcl deleted file mode 100644 index 6fe6eae..0000000 --- a/qick/firmware/proj_111.tcl +++ /dev/null @@ -1,92 +0,0 @@ -# Set the reference directory for source file relative paths (by default the value is script directory path) -set origin_dir "." - -# Use origin directory path location variable, if specified in the tcl shell -if { [info exists ::origin_dir_loc] } { - set origin_dir $::origin_dir_loc -} - -# Set the project name -set _xil_proj_name_ "top_111" - -# Set the directory path for the original project from where this script was exported -set orig_proj_dir "[file normalize "$origin_dir/"]" - -# Create project -create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xczu28dr-ffvg1517-2-e - -# Set the directory path for the new project -set proj_dir [get_property directory [current_project]] - -# Set project properties -set obj [current_project] -set_property -name "board_part" -value "xilinx.com:zcu111:part0:1.4" -objects $obj -set_property -name "default_lib" -value "xil_defaultlib" -objects $obj -set_property -name "dsa.accelerator_binary_content" -value "bitstream" -objects $obj -set_property -name "dsa.accelerator_binary_format" -value "xclbin2" -objects $obj -set_property -name "dsa.board_id" -value "zcu111" -objects $obj -set_property -name "dsa.description" -value "Vivado generated DSA" -objects $obj -set_property -name "dsa.dr_bd_base_address" -value "0" -objects $obj -set_property -name "dsa.emu_dir" -value "emu" -objects $obj -set_property -name "dsa.flash_interface_type" -value "bpix16" -objects $obj -set_property -name "dsa.flash_offset_address" -value "0" -objects $obj -set_property -name "dsa.flash_size" -value "1024" -objects $obj -set_property -name "dsa.host_architecture" -value "x86_64" -objects $obj -set_property -name "dsa.host_interface" -value "pcie" -objects $obj -set_property -name "dsa.num_compute_units" -value "60" -objects $obj -set_property -name "dsa.platform_state" -value "pre_synth" -objects $obj -set_property -name "dsa.vendor" -value "xilinx" -objects $obj -set_property -name "dsa.version" -value "0.0" -objects $obj -set_property -name "enable_vhdl_2008" -value "1" -objects $obj -set_property -name "ip_cache_permissions" -value "read write" -objects $obj -set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj -set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj -set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj -set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj -set_property -name "simulator_language" -value "Mixed" -objects $obj -set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj - -# Set IP repository paths -set obj [get_filesets sources_1] -set_property "ip_repo_paths" "[file normalize "$origin_dir/ip"]" $obj - -# Rebuild user ip_repo's index before adding any source files -update_ip_catalog -rebuild - -# Set 'sources_1' fileset object -set obj [get_filesets sources_1] -set files [list \ - [ file normalize "$origin_dir/hdl/vect2bits_16.v"] \ -] -add_files -norecurse -fileset $obj $files - -# Set 'constrs_1' fileset object -set obj [get_filesets constrs_1] - -# Add/Import constrs file and set constrs file properties -set files [list \ - [ file normalize "$origin_dir/xdc/timing_111.xdc"] \ - [ file normalize "$origin_dir/xdc/ios_111.xdc"] \ -] -add_files -fileset $obj $files - -# Source Block Design. -#set file "[file normalize "$origin_dir/bd/bd-2019-1.tcl"]" -set file "[file normalize "$origin_dir/bd/bd_111_2020-2.tcl"]" -source $file - -# Update compile order. -#update_compile_order -fileset sources_1 - -# Set sources_1 fileset object -set obj [get_filesets sources_1] - -# Create HDL Wrapper. -make_wrapper -files [get_files d_1.bd] -top - -# Add files to sources_1 fileset -set files [list \ - [file normalize "${origin_dir}/top_111/top_111.srcs/sources_1/bd/d_1/hdl/d_1_wrapper.v" ]\ -] -add_files -fileset $obj $files - diff --git a/qick/firmware/proj_111_rfbv1.tcl b/qick/firmware/proj_111_rfbv1.tcl deleted file mode 100644 index 3e69667..0000000 --- a/qick/firmware/proj_111_rfbv1.tcl +++ /dev/null @@ -1,92 +0,0 @@ -# Set the reference directory for source file relative paths (by default the value is script directory path) -set origin_dir "." - -# Use origin directory path location variable, if specified in the tcl shell -if { [info exists ::origin_dir_loc] } { - set origin_dir $::origin_dir_loc -} - -# Set the project name -set _xil_proj_name_ "top_111_rfbv1" - -# Set the directory path for the original project from where this script was exported -set orig_proj_dir "[file normalize "$origin_dir/"]" - -# Create project -create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xczu28dr-ffvg1517-2-e - -# Set the directory path for the new project -set proj_dir [get_property directory [current_project]] - -# Set project properties -set obj [current_project] -set_property -name "board_part" -value "xilinx.com:zcu111:part0:1.4" -objects $obj -set_property -name "default_lib" -value "xil_defaultlib" -objects $obj -set_property -name "dsa.accelerator_binary_content" -value "bitstream" -objects $obj -set_property -name "dsa.accelerator_binary_format" -value "xclbin2" -objects $obj -set_property -name "dsa.board_id" -value "zcu111" -objects $obj -set_property -name "dsa.description" -value "Vivado generated DSA" -objects $obj -set_property -name "dsa.dr_bd_base_address" -value "0" -objects $obj -set_property -name "dsa.emu_dir" -value "emu" -objects $obj -set_property -name "dsa.flash_interface_type" -value "bpix16" -objects $obj -set_property -name "dsa.flash_offset_address" -value "0" -objects $obj -set_property -name "dsa.flash_size" -value "1024" -objects $obj -set_property -name "dsa.host_architecture" -value "x86_64" -objects $obj -set_property -name "dsa.host_interface" -value "pcie" -objects $obj -set_property -name "dsa.num_compute_units" -value "60" -objects $obj -set_property -name "dsa.platform_state" -value "pre_synth" -objects $obj -set_property -name "dsa.vendor" -value "xilinx" -objects $obj -set_property -name "dsa.version" -value "0.0" -objects $obj -set_property -name "enable_vhdl_2008" -value "1" -objects $obj -set_property -name "ip_cache_permissions" -value "read write" -objects $obj -set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj -set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj -set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj -set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj -set_property -name "simulator_language" -value "Mixed" -objects $obj -set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj - -# Set IP repository paths -set obj [get_filesets sources_1] -set_property "ip_repo_paths" "[file normalize "$origin_dir/ip"]" $obj - -# Rebuild user ip_repo's index before adding any source files -update_ip_catalog -rebuild - -# Set 'sources_1' fileset object -set obj [get_filesets sources_1] -set files [list \ - [ file normalize "$origin_dir/hdl/vect2bits_16.v"] \ - [ file normalize "$origin_dir/hdl/lo_spi_mux.vhd"] \ -] -add_files -norecurse -fileset $obj $files - -# Set 'constrs_1' fileset object -set obj [get_filesets constrs_1] - -# Add/Import constrs file and set constrs file properties -set files [list \ - [ file normalize "$origin_dir/xdc/timing_111_rfbv1.xdc"] \ - [ file normalize "$origin_dir/xdc/ios_111_rfbv1.xdc"] \ -] -add_files -fileset $obj $files - -# Source Block Design. -set file "[file normalize "$origin_dir/bd/bd_111_rfbv1_2020-2.tcl"]" -source $file - -# Update compile order. -#update_compile_order -fileset sources_1 - -# Set sources_1 fileset object -set obj [get_filesets sources_1] - -# Create HDL Wrapper. -make_wrapper -files [get_files d_1.bd] -top - -# Add files to sources_1 fileset -set files [list \ - [file normalize "${origin_dir}/top_111_rfbv1/top_111_rfbv1.srcs/sources_1/bd/d_1/hdl/d_1_wrapper.v" ]\ -] -add_files -fileset $obj $files - diff --git a/qick/firmware/proj_111_rfbv2.tcl b/qick/firmware/proj_111_rfbv2.tcl deleted file mode 100644 index 4683c0c..0000000 --- a/qick/firmware/proj_111_rfbv2.tcl +++ /dev/null @@ -1,91 +0,0 @@ -# Set the reference directory for source file relative paths (by default the value is script directory path) -set origin_dir "." - -# Use origin directory path location variable, if specified in the tcl shell -if { [info exists ::origin_dir_loc] } { - set origin_dir $::origin_dir_loc -} - -# Set the project name -set _xil_proj_name_ "top_111_rfbv2" - -# Set the directory path for the original project from where this script was exported -set orig_proj_dir "[file normalize "$origin_dir/"]" - -# Create project -create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xczu28dr-ffvg1517-2-e - -# Set the directory path for the new project -set proj_dir [get_property directory [current_project]] - -# Set project properties -set obj [current_project] -set_property -name "board_part" -value "xilinx.com:zcu111:part0:1.4" -objects $obj -set_property -name "default_lib" -value "xil_defaultlib" -objects $obj -set_property -name "dsa.accelerator_binary_content" -value "bitstream" -objects $obj -set_property -name "dsa.accelerator_binary_format" -value "xclbin2" -objects $obj -set_property -name "dsa.board_id" -value "zcu111" -objects $obj -set_property -name "dsa.description" -value "Vivado generated DSA" -objects $obj -set_property -name "dsa.dr_bd_base_address" -value "0" -objects $obj -set_property -name "dsa.emu_dir" -value "emu" -objects $obj -set_property -name "dsa.flash_interface_type" -value "bpix16" -objects $obj -set_property -name "dsa.flash_offset_address" -value "0" -objects $obj -set_property -name "dsa.flash_size" -value "1024" -objects $obj -set_property -name "dsa.host_architecture" -value "x86_64" -objects $obj -set_property -name "dsa.host_interface" -value "pcie" -objects $obj -set_property -name "dsa.num_compute_units" -value "60" -objects $obj -set_property -name "dsa.platform_state" -value "pre_synth" -objects $obj -set_property -name "dsa.vendor" -value "xilinx" -objects $obj -set_property -name "dsa.version" -value "0.0" -objects $obj -set_property -name "enable_vhdl_2008" -value "1" -objects $obj -set_property -name "ip_cache_permissions" -value "read write" -objects $obj -set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj -set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj -set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj -set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj -set_property -name "simulator_language" -value "Mixed" -objects $obj -set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj - -# Set IP repository paths -set obj [get_filesets sources_1] -set_property "ip_repo_paths" "[file normalize "$origin_dir/ip"]" $obj - -# Rebuild user ip_repo's index before adding any source files -update_ip_catalog -rebuild - -# Set 'sources_1' fileset object -set obj [get_filesets sources_1] -set files [list \ - [ file normalize "$origin_dir/hdl/vect2bits_16.v"] \ - [ file normalize "$origin_dir/hdl/lo_spi_mux_v2.vhd"] \ -] -add_files -norecurse -fileset $obj $files - -# Set 'constrs_1' fileset object -set obj [get_filesets constrs_1] - -# Add/Import constrs file and set constrs file properties -set files [list \ - [ file normalize "$origin_dir/xdc/timing_111.xdc"] \ - [ file normalize "$origin_dir/xdc/ios_111_rfbv2.xdc"] \ -] -add_files -fileset $obj $files - -# Source Block Design. -set file "[file normalize "$origin_dir/bd/bd_111_rfbv2_2020-2.tcl"]" -source $file - -# Update compile order. -#update_compile_order -fileset sources_1 - -# Set sources_1 fileset object -set obj [get_filesets sources_1] - -# Create HDL Wrapper. -make_wrapper -files [get_files d_1.bd] -top - -# Add files to sources_1 fileset -set files [list \ - [file normalize "${origin_dir}/top_111_rfbv2/top_111_rfbv2.srcs/sources_1/bd/d_1/hdl/d_1_wrapper.v" ]\ -] -add_files -fileset $obj $files diff --git a/qick/firmware/proj_216.tcl b/qick/firmware/proj_216.tcl deleted file mode 100644 index d5437a4..0000000 --- a/qick/firmware/proj_216.tcl +++ /dev/null @@ -1,76 +0,0 @@ -# Set the reference directory for source file relative paths (by default the value is script directory path) -set origin_dir "." - -# Use origin directory path location variable, if specified in the tcl shell -if { [info exists ::origin_dir_loc] } { - set origin_dir $::origin_dir_loc -} - -# Set the project name -set _xil_proj_name_ "top_216" - -# Set the directory path for the original project from where this script was exported -set orig_proj_dir "[file normalize "$origin_dir/"]" - -# Create project -create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xczu49dr-ffvf1760-2-e - -# Set the directory path for the new project -set proj_dir [get_property directory [current_project]] - -# Set project properties -set obj [current_project] -set_property -name "board_part" -value "xilinx.com:zcu216:part0:2.0" -objects $obj -set_property -name "default_lib" -value "xil_defaultlib" -objects $obj -set_property -name "enable_vhdl_2008" -value "1" -objects $obj -set_property -name "ip_cache_permissions" -value "read write" -objects $obj -set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj -set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj -set_property -name "platform.board_id" -value "zcu216" -objects $obj -set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj -set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj -set_property -name "simulator_language" -value "Mixed" -objects $obj - -# Set IP repository paths -set obj [get_filesets sources_1] -set_property "ip_repo_paths" "[file normalize "$origin_dir/ip"]" $obj - -# Rebuild user ip_repo's index before adding any source files -update_ip_catalog -rebuild - -# Set 'sources_1' fileset object -set obj [get_filesets sources_1] -set files [list \ - [ file normalize "$origin_dir/hdl/vect2bits_16.v"] \ -] -add_files -norecurse -fileset $obj $files - -# Set 'constrs_1' fileset object -set obj [get_filesets constrs_1] - -# Add/Import constrs file and set constrs file properties -set files [list \ - [ file normalize "$origin_dir/xdc/timing_216.xdc"] \ - [ file normalize "$origin_dir/xdc/ios_216.xdc"] \ -] -add_files -fileset $obj $files - -# Source Block Design. -set file "[file normalize "$origin_dir/bd/bd_216_2020-2.tcl"]" -source $file - -# Update compile order. -#update_compile_order -fileset sources_1 - -# Set sources_1 fileset object -set obj [get_filesets sources_1] - -# Create HDL Wrapper. -make_wrapper -files [get_files d_1.bd] -top - -# Add files to sources_1 fileset -set files [list \ - [file normalize "${origin_dir}/top_216/top_216.srcs/sources_1/bd/d_1/hdl/d_1_wrapper.v" ]\ -] -add_files -fileset $obj $files - diff --git a/qick/firmware/proj_4x2.tcl b/qick/firmware/proj_4x2.tcl deleted file mode 100644 index 04d827f..0000000 --- a/qick/firmware/proj_4x2.tcl +++ /dev/null @@ -1,77 +0,0 @@ -# Set the reference directory for source file relative paths (by default the value is script directory path) -set origin_dir "." - -# Use origin directory path location variable, if specified in the tcl shell -if { [info exists ::origin_dir_loc] } { - set origin_dir $::origin_dir_loc -} - -# Set the project name -set _xil_proj_name_ "top_4x2" - -# Set the directory path for the original project from where this script was exported -set orig_proj_dir "[file normalize "$origin_dir/"]" - -# Create project -create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xczu48dr-ffvg1517-2-e - -# Set the directory path for the new project -set proj_dir [get_property directory [current_project]] - -# Set project properties -set obj [current_project] -set_property -name "board_part_repo_paths" -value "[file normalize "$origin_dir/board_files"]" -objects $obj -set_property -name "board_part" -value "realdigital.org:rfsoc4x2:part0:1.0" -objects $obj -set_property -name "default_lib" -value "xil_defaultlib" -objects $obj -set_property -name "enable_vhdl_2008" -value "1" -objects $obj -set_property -name "ip_cache_permissions" -value "read write" -objects $obj -set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj -set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj -set_property -name "platform.board_id" -value "rfsoc4x2" -objects $obj -set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj -set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj -set_property -name "simulator_language" -value "Mixed" -objects $obj -set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj - -# Set IP repository paths -set obj [get_filesets sources_1] -set_property "ip_repo_paths" "[file normalize "$origin_dir/ip"]" $obj - -# Rebuild user ip_repo's index before adding any source files -update_ip_catalog -rebuild - -# Set 'sources_1' fileset object -set obj [get_filesets sources_1] -set files [list \ - [ file normalize "$origin_dir/hdl/vect2bits_16.v"] \ -] -add_files -norecurse -fileset $obj $files - -# Set 'constrs_1' fileset object -set obj [get_filesets constrs_1] - -# Add/Import constrs file and set constrs file properties -set files [list \ - [ file normalize "$origin_dir/xdc/timing_4x2.xdc"] \ - [ file normalize "$origin_dir/xdc/ios_4x2.xdc"] \ -] -add_files -fileset $obj $files - -# Source Block Design. -set file "[file normalize "$origin_dir/bd/bd_4x2_2020-2.tcl"]" -source $file - -# Update compile order. -#update_compile_order -fileset sources_1 - -# Set sources_1 fileset object -set obj [get_filesets sources_1] -# Create HDL Wrapper. -make_wrapper -files [get_files d_1.bd] -top - -# Add files to sources_1 fileset -set files [list \ - [file normalize "${origin_dir}/top_4x2/top_4x2.srcs/sources_1/bd/d_1/hdl/d_1_wrapper.v" ]\ -] -add_files -fileset $obj $files - diff --git a/qick/firmware/tProcessor_64_and_Signal_Generator_V4.pdf b/qick/firmware/tProcessor_64_and_Signal_Generator_V4.pdf deleted file mode 100644 index 049fff2..0000000 Binary files a/qick/firmware/tProcessor_64_and_Signal_Generator_V4.pdf and /dev/null differ diff --git a/qick/firmware/xdc/ios_111.xdc b/qick/firmware/xdc/ios_111.xdc deleted file mode 100644 index ec19659..0000000 --- a/qick/firmware/xdc/ios_111.xdc +++ /dev/null @@ -1,33 +0,0 @@ -set_property PACKAGE_PIN C17 [get_ports "PMOD0_0_LS"]; -set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_0_LS"]; -set_property PACKAGE_PIN M18 [get_ports "PMOD0_1_LS"]; -set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_1_LS"]; -set_property PACKAGE_PIN H16 [get_ports "PMOD0_2_LS"]; -set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_2_LS"]; -set_property PACKAGE_PIN H17 [get_ports "PMOD0_3_LS"]; -set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_3_LS"]; -set_property PACKAGE_PIN J16 [get_ports "PMOD0_4_LS"]; -set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_4_LS"]; -set_property PACKAGE_PIN K16 [get_ports "PMOD0_5_LS"]; -set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_5_LS"]; -set_property PACKAGE_PIN H15 [get_ports "PMOD0_6_LS"]; -set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_6_LS"]; -set_property PACKAGE_PIN J15 [get_ports "PMOD0_7_LS"]; -set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_7_LS"]; - -set_property PACKAGE_PIN L14 [get_ports "PMOD1_0_LS"]; -set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_0_LS"]; -#set_property PACKAGE_PIN L15 [get_ports "PMOD1_1_LS"]; -#set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_1_LS"]; -#set_property PACKAGE_PIN M13 [get_ports "PMOD1_2_LS"]; -#set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_2_LS"]; -#set_property PACKAGE_PIN N13 [get_ports "PMOD1_3_LS"]; -#set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_3_LS"]; -#set_property PACKAGE_PIN M15 [get_ports "PMOD1_4_LS"]; -#set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_4_LS"]; -#set_property PACKAGE_PIN N15 [get_ports "PMOD1_5_LS"]; -#set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_5_LS"]; -#set_property PACKAGE_PIN M14 [get_ports "PMOD1_6_LS"]; -#set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_6_LS"]; -#set_property PACKAGE_PIN N14 [get_ports "PMOD1_7_LS"]; -#set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_7_LS"]; diff --git a/qick/firmware/xdc/ios_111_rfbv1.xdc b/qick/firmware/xdc/ios_111_rfbv1.xdc deleted file mode 100644 index 8f4836b..0000000 --- a/qick/firmware/xdc/ios_111_rfbv1.xdc +++ /dev/null @@ -1,104 +0,0 @@ -set_property PACKAGE_PIN C17 [get_ports "PMOD0_0_LS"]; -set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_0_LS"]; -set_property PACKAGE_PIN M18 [get_ports "PMOD0_1_LS"]; -set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_1_LS"]; -set_property PACKAGE_PIN H16 [get_ports "PMOD0_2_LS"]; -set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_2_LS"]; -set_property PACKAGE_PIN H17 [get_ports "PMOD0_3_LS"]; -set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_3_LS"]; -set_property PACKAGE_PIN J16 [get_ports "PMOD0_4_LS"]; -set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_4_LS"]; -set_property PACKAGE_PIN K16 [get_ports "PMOD0_5_LS"]; -set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_5_LS"]; -set_property PACKAGE_PIN H15 [get_ports "PMOD0_6_LS"]; -set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_6_LS"]; -set_property PACKAGE_PIN J15 [get_ports "PMOD0_7_LS"]; -set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_7_LS"]; - -set_property PACKAGE_PIN L14 [get_ports "PMOD1_0_LS"]; -set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_0_LS"]; -#set_property PACKAGE_PIN L15 [get_ports "PMOD1_1_LS"]; -#set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_1_LS"]; -#set_property PACKAGE_PIN M13 [get_ports "PMOD1_2_LS"]; -#set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_2_LS"]; -#set_property PACKAGE_PIN N13 [get_ports "PMOD1_3_LS"]; -#set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_3_LS"]; -#set_property PACKAGE_PIN M15 [get_ports "PMOD1_4_LS"]; -#set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_4_LS"]; -#set_property PACKAGE_PIN N15 [get_ports "PMOD1_5_LS"]; -#set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_5_LS"]; -#set_property PACKAGE_PIN M14 [get_ports "PMOD1_6_LS"]; -#set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_6_LS"]; -#set_property PACKAGE_PIN N14 [get_ports "PMOD1_7_LS"]; -#set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_7_LS"]; - - -# ATTN_SPI -set_property PACKAGE_PIN A9 [get_ports "ATTN_CLK"] ; # Bank 87 VCCO - VCC1V8 - DACIO_00 - IO_L12N_AD8N_87 -set_property IOSTANDARD LVCMOS18 [get_ports "ATTN_CLK"] ; # Bank 87 VCCO - VCC1V8 - DACIO_00 - IO_L12N_AD8N_87 -set_property PACKAGE_PIN A10 [get_ports "ATTN_SI"] ; # Bank 87 VCCO - VCC1V8 - DACIO_01 - IO_L12P_AD8P_87 -set_property IOSTANDARD LVCMOS18 [get_ports "ATTN_SI"] ; # Bank 87 VCCO - VCC1V8 - DACIO_01 - IO_L12P_AD8P_87 -set_property PACKAGE_PIN A6 [get_ports "ATTN_LE[0]"] ; # Bank 87 VCCO - VCC1V8 - DACIO_02 - IO_L11N_AD9N_87 -set_property IOSTANDARD LVCMOS18 [get_ports "ATTN_LE[0]"] ; # Bank 87 VCCO - VCC1V8 - DACIO_02 - IO_L11N_AD9N_87 -set_property PACKAGE_PIN A7 [get_ports "ATTN_LE[1]"] ; # Bank 87 VCCO - VCC1V8 - DACIO_03 - IO_L11P_AD9P_87 -set_property IOSTANDARD LVCMOS18 [get_ports "ATTN_LE[1]"] ; # Bank 87 VCCO - VCC1V8 - DACIO_03 - IO_L11P_AD9P_87 -set_property PACKAGE_PIN A5 [get_ports "ATTN_LE[2]"] ; # Bank 87 VCCO - VCC1V8 - DACIO_04 - IO_L10N_AD10N_87 -set_property IOSTANDARD LVCMOS18 [get_ports "ATTN_LE[2]"] ; # Bank 87 VCCO - VCC1V8 - DACIO_04 - IO_L10N_AD10N_87 - -# PSF_SPI -set_property PACKAGE_PIN B5 [get_ports "SCLK"] ; # Bank 87 VCCO - VCC1V8 - DACIO_05 - IO_L10P_AD10P_87 -set_property IOSTANDARD LVCMOS18 [get_ports "SCLK"] ; # Bank 87 VCCO - VCC1V8 - DACIO_05 - IO_L10P_AD10P_87 -set_property PACKAGE_PIN C6 [get_ports "SDI"] ; # Bank 87 VCCO - VCC1V8 - DACIO_07 - IO_L9P_AD11P_87 -set_property IOSTANDARD LVCMOS18 [get_ports "SDI"] ; # Bank 87 VCCO - VCC1V8 - DACIO_07 - IO_L9P_AD11P_87 -set_property PACKAGE_PIN B9 [get_ports "SDO"] ; # Bank 87 VCCO - VCC1V8 - DACIO_08 - IO_L8N_HDGC_87 -set_property IOSTANDARD LVCMOS18 [get_ports "SDO"] ; # Bank 87 VCCO - VCC1V8 - DACIO_08 - IO_L8N_HDGC_87 -set_property PACKAGE_PIN D10 [get_ports "S[0]"] ; # Bank 87 VCCO - VCC1V8 - DACIO_17 - IO_L4P_AD12P_87 -set_property IOSTANDARD LVCMOS18 [get_ports "S[0]"] ; # Bank 87 VCCO - VCC1V8 - DACIO_17 - IO_L4P_AD12P_87 -set_property PACKAGE_PIN D6 [get_ports "S[1]"] ; # Bank 87 VCCO - VCC1V8 - DACIO_18 - IO_L3N_AD13N_87 -set_property IOSTANDARD LVCMOS18 [get_ports "S[1]"] ; # Bank 87 VCCO - VCC1V8 - DACIO_18 - IO_L3N_AD13N_87 -set_property PACKAGE_PIN E7 [get_ports "S[2]"] ; # Bank 87 VCCO - VCC1V8 - DACIO_19- IO_L3P_AD13P_87 -set_property IOSTANDARD LVCMOS18 [get_ports "S[2]"] ; # Bank 87 VCCO - VCC1V8 - DACIO_19 - IO_L3P_AD13P_87 -set_property PACKAGE_PIN C5 [get_ports "S[3]"] ; # Bank 87 VCCO - VCC1V8 - DACIO_06 - IO_L9N_AD11N_87 -set_property IOSTANDARD LVCMOS18 [get_ports "S[3]"] ; # Bank 87 VCCO - VCC1V8 - DACIO_06 - IO_L9N_AD11N_87 -set_property PACKAGE_PIN B10 [get_ports "RST_5VEN"] ; # Bank 87 VCCO - VCC1V8 - DACIO_09 - IO_L8P_HDGC_87 -set_property IOSTANDARD LVCMOS18 [get_ports "RST_5VEN"] ; # Bank 87 VCCO - VCC1V8 - DACIO_09 - IO_L8P_HDGC_87 - -# LO_SPI -set_property PACKAGE_PIN B7 [get_ports "LO_SCLK"] ; # Bank 87 VCCO - VCC1V8 - DACIO_10 - IO_L7N_HDGC_87 -set_property IOSTANDARD LVCMOS18 [get_ports "LO_SCLK"] ; # Bank 87 VCCO - VCC1V8 - DACIO_10 - IO_L7N_HDGC_87 -set_property PACKAGE_PIN D9 [get_ports "LO_MISO0"] ; # Bank 87 VCCO - VCC1V8 - DACIO_13 - IO_L6P_HDGC_87 -set_property IOSTANDARD LVCMOS18 [get_ports "LO_MISO0"] ; # Bank 87 VCCO - VCC1V8 - DACIO_13 - IO_L6P_HDGC_87 -set_property PACKAGE_PIN C7 [get_ports "LO_MISO1"] ; # Bank 87 VCCO - VCC1V8 - DACIO_14 - IO_L5N_HDGC_87 -set_property IOSTANDARD LVCMOS18 [get_ports "LO_MISO1"] ; # Bank 87 VCCO - VCC1V8 - DACIO_14 - IO_L5N_HDGC_87 -set_property PACKAGE_PIN D8 [get_ports "LO_MOSI"] ; # Bank 87 VCCO - VCC1V8 - DACIO_12 - IO_L6N_HDGC_87 -set_property IOSTANDARD LVCMOS18 [get_ports "LO_MOSI"] ; # Bank 87 VCCO - VCC1V8 - DACIO_12 - IO_L6N_HDGC_87 -set_property PACKAGE_PIN B8 [get_ports "LO_CS0"] ; # Bank 87 VCCO - VCC1V8 - DACIO_11 - IO_L7P_HDGC_87 -set_property IOSTANDARD LVCMOS18 [get_ports "LO_CS0"] ; # Bank 87 VCCO - VCC1V8 - DACIO_11 - IO_L7P_HDGC_87 -set_property PACKAGE_PIN C8 [get_ports "LO_CS1"] ; # Bank 87 VCCO - VCC1V8 - DACIO_15 - IO_L5P_HDGC_87 -set_property IOSTANDARD LVCMOS18 [get_ports "LO_CS1"] ; # Bank 87 VCCO - VCC1V8 - DACIO_15 - IO_L5P_HDGC_87 - -# BIAS_SPI -set_property PACKAGE_PIN AU2 [get_ports "BIAS_SCLK"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_17 - IO_L4P_AD8P_84 -set_property IOSTANDARD LVCMOS18 [get_ports "BIAS_SCLK"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_17 - IO_L4P_AD8P_84 -set_property PACKAGE_PIN AU8 [get_ports "BIAS_SDI"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_07 - IO_L9P_AD3P_84 -set_property IOSTANDARD LVCMOS18 [get_ports "BIAS_SDI"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_07 - IO_L9P_AD3P_84 -set_property PACKAGE_PIN AP5 [get_ports "BIAS_SDO"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_00 - IO_L12N_AD0N_84 -set_property IOSTANDARD LVCMOS18 [get_ports "BIAS_SDO"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_00 - IO_L12N_AD0N_84 -set_property PACKAGE_PIN AU5 [get_ports "BIAS_S[0]"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_10 - IO_L7N_HDGC_AD5N_84 -set_property IOSTANDARD LVCMOS18 [get_ports "BIAS_S[0]"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_10 - IO_L7N_HDGC_AD5N_84 -set_property PACKAGE_PIN AU3 [get_ports "BIAS_S[1]"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_12 - IO_L6N_HDGC_AD6N_84 -set_property IOSTANDARD LVCMOS18 [get_ports "BIAS_S[1]"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_12 - IO_L6N_HDGC_AD6N_84 -set_property PACKAGE_PIN AV2 [get_ports "BIAS_S[2]"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_18 - IO_L3N_AD9N_84 -set_property IOSTANDARD LVCMOS18 [get_ports "BIAS_S[2]"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_18 - IO_L3N_AD9N_84 -set_property PACKAGE_PIN AV6 [get_ports "BIAS_S[3]"] ; # BIAS_SYNC Bank 84 VCCO - VCC1V8 - ADCIO_15 - IO_L5P_HDGC_AD7P_84 -set_property IOSTANDARD LVCMOS18 [get_ports "BIAS_S[3]"] ; # BIAS_SYNC Bank 84 VCCO - VCC1V8 - ADCIO_15 - IO_L5P_HDGC_AD7P_84 -set_property PACKAGE_PIN AR6 [get_ports "BIAS_CLR"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_02 - IO_L11N_AD1N_84 -set_property IOSTANDARD LVCMOS18 [get_ports "BIAS_CLR"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_02 - IO_L11N_AD1N_84 -set_property PACKAGE_PIN AU7 [get_ports "BIAS_RESET"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_05 - IO_L10P_AD2P_84 -set_property IOSTANDARD LVCMOS18 [get_ports "BIAS_RESET"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_05 - IO_L10P_AD2P_84 -set_property PACKAGE_PIN AT6 [get_ports "BIAS_CE"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_08 - IO_L8N_HDGC_AD4N_84 -set_property IOSTANDARD LVCMOS18 [get_ports "BIAS_CE"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_08 - IO_L8N_HDGC_AD4N_84 - -# PWR_SYNC -set_property PACKAGE_PIN C10 [get_ports "PWR_SYNC[0]"] ; # Bank 87 VCCO - VCC1V8 - DACIO_16 - IO_L4N_AD12N_87 -set_property IOSTANDARD LVCMOS18 [get_ports "PWR_SYNC[0]"] ; # Bank 87 VCCO - VCC1V8 - DACIO_16 - IO_L4N_AD12N_87 \ No newline at end of file diff --git a/qick/firmware/xdc/ios_111_rfbv2.xdc b/qick/firmware/xdc/ios_111_rfbv2.xdc deleted file mode 100644 index 9e0e6fe..0000000 --- a/qick/firmware/xdc/ios_111_rfbv2.xdc +++ /dev/null @@ -1,128 +0,0 @@ -set_property PACKAGE_PIN C17 [get_ports "PMOD0_0_LS"]; -set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_0_LS"]; -set_property PACKAGE_PIN M18 [get_ports "PMOD0_1_LS"]; -set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_1_LS"]; -set_property PACKAGE_PIN H16 [get_ports "PMOD0_2_LS"]; -set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_2_LS"]; -set_property PACKAGE_PIN H17 [get_ports "PMOD0_3_LS"]; -set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_3_LS"]; -set_property PACKAGE_PIN J16 [get_ports "PMOD0_4_LS"]; -set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_4_LS"]; -set_property PACKAGE_PIN K16 [get_ports "PMOD0_5_LS"]; -set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_5_LS"]; -set_property PACKAGE_PIN H15 [get_ports "PMOD0_6_LS"]; -set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_6_LS"]; -set_property PACKAGE_PIN J15 [get_ports "PMOD0_7_LS"]; -set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_7_LS"]; - -set_property PACKAGE_PIN L14 [get_ports "PMOD1_0_LS"]; -set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_0_LS"]; -#set_property PACKAGE_PIN L15 [get_ports "PMOD1_1_LS"]; -#set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_1_LS"]; -#set_property PACKAGE_PIN M13 [get_ports "PMOD1_2_LS"]; -#set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_2_LS"]; -#set_property PACKAGE_PIN N13 [get_ports "PMOD1_3_LS"]; -#set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_3_LS"]; -#set_property PACKAGE_PIN M15 [get_ports "PMOD1_4_LS"]; -#set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_4_LS"]; -#set_property PACKAGE_PIN N15 [get_ports "PMOD1_5_LS"]; -#set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_5_LS"]; -#set_property PACKAGE_PIN M14 [get_ports "PMOD1_6_LS"]; -#set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_6_LS"]; -#set_property PACKAGE_PIN N14 [get_ports "PMOD1_7_LS"]; -#set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_7_LS"]; - -# ATTN_SPI -set_property PACKAGE_PIN A9 [get_ports "ATTN_CLK"] ; # Bank 87 VCCO - VCC1V8 - DACIO_00 - IO_L12N_AD8N_87 -set_property IOSTANDARD LVCMOS18 [get_ports "ATTN_CLK"] ; # Bank 87 VCCO - VCC1V8 - DACIO_00 - IO_L12N_AD8N_87 -set_property PACKAGE_PIN A10 [get_ports "ATTN_SI"] ; # Bank 87 VCCO - VCC1V8 - DACIO_01 - IO_L12P_AD8P_87 -set_property IOSTANDARD LVCMOS18 [get_ports "ATTN_SI"] ; # Bank 87 VCCO - VCC1V8 - DACIO_01 - IO_L12P_AD8P_87 -set_property PACKAGE_PIN A6 [get_ports "ATTN_LE[0]"] ; # Bank 87 VCCO - VCC1V8 - DACIO_02 - IO_L11N_AD9N_87 -set_property IOSTANDARD LVCMOS18 [get_ports "ATTN_LE[0]"] ; # Bank 87 VCCO - VCC1V8 - DACIO_02 - IO_L11N_AD9N_87 -set_property PACKAGE_PIN A7 [get_ports "ATTN_LE[1]"] ; # Bank 87 VCCO - VCC1V8 - DACIO_03 - IO_L11P_AD9P_87 -set_property IOSTANDARD LVCMOS18 [get_ports "ATTN_LE[1]"] ; # Bank 87 VCCO - VCC1V8 - DACIO_03 - IO_L11P_AD9P_87 -set_property PACKAGE_PIN A5 [get_ports "ATTN_LE[2]"] ; # Bank 87 VCCO - VCC1V8 - DACIO_04 - IO_L10N_AD10N_87 -set_property IOSTANDARD LVCMOS18 [get_ports "ATTN_LE[2]"] ; # Bank 87 VCCO - VCC1V8 - DACIO_04 - IO_L10N_AD10N_87 - -# PSF_SPI -set_property PACKAGE_PIN B5 [get_ports "SCLK"] ; # Bank 87 VCCO - VCC1V8 - DACIO_05 - IO_L10P_AD10P_87 -set_property IOSTANDARD LVCMOS18 [get_ports "SCLK"] ; # Bank 87 VCCO - VCC1V8 - DACIO_05 - IO_L10P_AD10P_87 -set_property PACKAGE_PIN C6 [get_ports "SDI"] ; # Bank 87 VCCO - VCC1V8 - DACIO_07 - IO_L9P_AD11P_87 -set_property IOSTANDARD LVCMOS18 [get_ports "SDI"] ; # Bank 87 VCCO - VCC1V8 - DACIO_07 - IO_L9P_AD11P_87 -set_property PACKAGE_PIN B9 [get_ports "SDO"] ; # Bank 87 VCCO - VCC1V8 - DACIO_08 - IO_L8N_HDGC_87 -set_property IOSTANDARD LVCMOS18 [get_ports "SDO"] ; # Bank 87 VCCO - VCC1V8 - DACIO_08 - IO_L8N_HDGC_87 -set_property PACKAGE_PIN D10 [get_ports "S[0]"] ; # Bank 87 VCCO - VCC1V8 - DACIO_17 - IO_L4P_AD12P_87 -set_property IOSTANDARD LVCMOS18 [get_ports "S[0]"] ; # Bank 87 VCCO - VCC1V8 - DACIO_17 - IO_L4P_AD12P_87 -set_property PACKAGE_PIN D6 [get_ports "S[1]"] ; # Bank 87 VCCO - VCC1V8 - DACIO_18 - IO_L3N_AD13N_87 -set_property IOSTANDARD LVCMOS18 [get_ports "S[1]"] ; # Bank 87 VCCO - VCC1V8 - DACIO_18 - IO_L3N_AD13N_87 -set_property PACKAGE_PIN E7 [get_ports "S[2]"] ; # Bank 87 VCCO - VCC1V8 - DACIO_19- IO_L3P_AD13P_87 -set_property IOSTANDARD LVCMOS18 [get_ports "S[2]"] ; # Bank 87 VCCO - VCC1V8 - DACIO_19 - IO_L3P_AD13P_87 -set_property PACKAGE_PIN C5 [get_ports "S[3]"] ; # Bank 87 VCCO - VCC1V8 - DACIO_06 - IO_L9N_AD11N_87 -set_property IOSTANDARD LVCMOS18 [get_ports "S[3]"] ; # Bank 87 VCCO - VCC1V8 - DACIO_06 - IO_L9N_AD11N_87 - -# LO_SPI -set_property PACKAGE_PIN B7 [get_ports "LO_SCLK"] ; # Bank 87 VCCO - VCC1V8 - DACIO_10 - IO_L7N_HDGC_87 -set_property IOSTANDARD LVCMOS18 [get_ports "LO_SCLK"] ; # Bank 87 VCCO - VCC1V8 - DACIO_10 - IO_L7N_HDGC_87 -set_property PACKAGE_PIN D9 [get_ports "LO_MISO0"] ; # Bank 87 VCCO - VCC1V8 - DACIO_13 - IO_L6P_HDGC_87 -set_property IOSTANDARD LVCMOS18 [get_ports "LO_MISO0"] ; # Bank 87 VCCO - VCC1V8 - DACIO_13 - IO_L6P_HDGC_87 -set_property PACKAGE_PIN C7 [get_ports "LO_MISO1"] ; # Bank 87 VCCO - VCC1V8 - DACIO_14 - IO_L5N_HDGC_87 -set_property IOSTANDARD LVCMOS18 [get_ports "LO_MISO1"] ; # Bank 87 VCCO - VCC1V8 - DACIO_14 - IO_L5N_HDGC_87 -set_property PACKAGE_PIN AV7 [get_ports "LO_MISO2"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_04 - IO_L10N_AD2N_84 -set_property IOSTANDARD LVCMOS18 [get_ports "LO_MISO2"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_04 - IO_L10N_AD2N_84 -set_property PACKAGE_PIN D8 [get_ports "LO_MOSI"] ; # Bank 87 VCCO - VCC1V8 - DACIO_12 - IO_L6N_HDGC_87 -set_property IOSTANDARD LVCMOS18 [get_ports "LO_MOSI"] ; # Bank 87 VCCO - VCC1V8 - DACIO_12 - IO_L6N_HDGC_87 -set_property PACKAGE_PIN B8 [get_ports "LO_CS0"] ; # Bank 87 VCCO - VCC1V8 - DACIO_11 - IO_L7P_HDGC_87 -set_property IOSTANDARD LVCMOS18 [get_ports "LO_CS0"] ; # Bank 87 VCCO - VCC1V8 - DACIO_11 - IO_L7P_HDGC_87 -set_property PACKAGE_PIN C8 [get_ports "LO_CS1"] ; # Bank 87 VCCO - VCC1V8 - DACIO_15 - IO_L5P_HDGC_87 -set_property IOSTANDARD LVCMOS18 [get_ports "LO_CS1"] ; # Bank 87 VCCO - VCC1V8 - DACIO_15 - IO_L5P_HDGC_87 -set_property PACKAGE_PIN AV3 [get_ports "LO_CS2"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_19 - IO_L3P_AD9P_84 -set_property IOSTANDARD LVCMOS18 [get_ports "LO_CS2"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_19 - IO_L3P_AD9P_84 -set_property PACKAGE_PIN AU7 [get_ports "LO_SYNC"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_05 - IO_L10P_AD2P_84 -set_property IOSTANDARD LVCMOS18 [get_ports "LO_SYNC"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_05 - IO_L10P_AD2P_84 - -# BIAS_SPI -set_property PACKAGE_PIN AU2 [get_ports "BIAS_SCLK"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_17 - IO_L4P_AD8P_84 -set_property IOSTANDARD LVCMOS18 [get_ports "BIAS_SCLK"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_17 - IO_L4P_AD8P_84 -set_property PACKAGE_PIN AU8 [get_ports "BIAS_SDI"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_07 - IO_L9P_AD3P_84 -set_property IOSTANDARD LVCMOS18 [get_ports "BIAS_SDI"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_07 - IO_L9P_AD3P_84 -set_property PACKAGE_PIN AP5 [get_ports "BIAS_SDO"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_00 - IO_L12N_AD0N_84 -set_property IOSTANDARD LVCMOS18 [get_ports "BIAS_SDO"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_00 - IO_L12N_AD0N_84 -set_property PACKAGE_PIN AU5 [get_ports "BIAS_S[0]"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_10 - IO_L7N_HDGC_AD5N_84 -set_property IOSTANDARD LVCMOS18 [get_ports "BIAS_S[0]"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_10 - IO_L7N_HDGC_AD5N_84 -set_property PACKAGE_PIN AU3 [get_ports "BIAS_S[1]"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_12 - IO_L6N_HDGC_AD6N_84 -set_property IOSTANDARD LVCMOS18 [get_ports "BIAS_S[1]"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_12 - IO_L6N_HDGC_AD6N_84 -set_property PACKAGE_PIN AV2 [get_ports "BIAS_S[2]"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_18 - IO_L3N_AD9N_84 -set_property IOSTANDARD LVCMOS18 [get_ports "BIAS_S[2]"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_18 - IO_L3N_AD9N_84 -set_property PACKAGE_PIN AV6 [get_ports "BIAS_S[3]"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_15 - IO_L5P_HDGC_AD7P_84 -set_property IOSTANDARD LVCMOS18 [get_ports "BIAS_S[3]"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_15 - IO_L5P_HDGC_AD7P_84 -set_property PACKAGE_PIN AR6 [get_ports "BIAS_CLR"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_02 - IO_L11N_AD1N_84 -set_property IOSTANDARD LVCMOS18 [get_ports "BIAS_CLR"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_02 - IO_L11N_AD1N_84 - -# PWR_SYNC -set_property PACKAGE_PIN C10 [get_ports "PWR_SYNC[0]"] ;# Bank 87 VCCO - VCC1V8 - DACIO_16 - IO_L4N_AD12N_87 -set_property IOSTANDARD LVCMOS18 [get_ports "PWR_SYNC[0]"] ;# Bank 87 VCCO - VCC1V8 - DACIO_16 - IO_L4N_AD12N_87 - -# SPARE IO -#set_property PACKAGE_PIN B10 [get_ports "SPARE0"] ; # Bank 87 VCCO - VCC1V8 - DACIO_09 - IO_L8P_HDGC_87 -#set_property IOSTANDARD LVCMOS18 [get_ports "SPARE0"] ; # Bank 87 VCCO - VCC1V8 - DACIO_09 - IO_L8P_HDGC_87 -#set_property PACKAGE_PIN AT6 [get_ports "SPARE1"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_08 - IO_L8N_HDGC_AD4N_84 -#set_property IOSTANDARD LVCMOS18 [get_ports "SPARE1"] ; # Bank 84 VCCO - VCC1V8 - ADCIO_08 - IO_L8N_HDGC_AD4N_84 - -# -# RF Output Switches -#set_property PACKAGE_PIN AP6 [get_ports "OSW_CTL_CH[0]"] ;# Bank 84 VCCO - VCC1V8 - ADCIO_01 - IO_L12P_AD0P_84 -#set_property IOSTANDARD LVCMOS18 [get_ports "OSW_CTL_CH[0]"] ;# Bank 84 VCCO - VCC1V8 - ADCIO_01 - IO_L12P_AD0P_84 -#set_property PACKAGE_PIN AR7 [get_ports "OSW_CTL_CH[1]"] ;# Bank 84 VCCO - VCC1V8 - ADCIO_03 - IO_L11P_AD1P_84 -#set_property IOSTANDARD LVCMOS18 [get_ports "OSW_CTL_CH[1]"] ;# Bank 84 VCCO - VCC1V8 - ADCIO_03 - IO_L11P_AD1P_84 -#set_property PACKAGE_PIN AV8 [get_ports "OSW_CTL_CH[2]"] ;# Bank 84 VCCO - VCC1V8 - ADCIO_06 - IO_L9N_AD3N_84 -#set_property IOSTANDARD LVCMOS18 [get_ports "OSW_CTL_CH[2]"] ;# Bank 84 VCCO - VCC1V8 - ADCIO_06 - IO_L9N_AD3N_84 -#set_property PACKAGE_PIN AT7 [get_ports "OSW_CTL_CH[3]"] ;# Bank 84 VCCO - VCC1V8 - ADCIO_09 - IO_L8P_HDGC_AD4P_84 -#set_property IOSTANDARD LVCMOS18 [get_ports "OSW_CTL_CH[3]"] ;# Bank 84 VCCO - VCC1V8 - ADCIO_09 - IO_L8P_HDGC_AD4P_84 -#set_property PACKAGE_PIN AT5 [get_ports "OSW_CTL_CH[4]"] ;# Bank 84 VCCO - VCC1V8 - ADCIO_11 - IO_L7P_HDGC_AD5P_84 -#set_property IOSTANDARD LVCMOS18 [get_ports "OSW_CTL_CH[4]"] ;# Bank 84 VCCO - VCC1V8 - ADCIO_11 - IO_L7P_HDGC_AD5P_84 -#set_property PACKAGE_PIN AU4 [get_ports "OSW_CTL_CH[5]"] ;# Bank 84 VCCO - VCC1V8 - ADCIO_13 - IO_L6P_HDGC_AD6P_84 -#set_property IOSTANDARD LVCMOS18 [get_ports "OSW_CTL_CH[5]"] ;# Bank 84 VCCO - VCC1V8 - ADCIO_13 - IO_L6P_HDGC_AD6P_84 -#set_property PACKAGE_PIN AV5 [get_ports "OSW_CTL_CH[6]"] ;# Bank 84 VCCO - VCC1V8 - ADCIO_14 - IO_L5N_HDGC_AD7N_84 -#set_property IOSTANDARD LVCMOS18 [get_ports "OSW_CTL_CH[6]"] ;# Bank 84 VCCO - VCC1V8 - ADCIO_14 - IO_L5N_HDGC_AD7N_84 -#set_property PACKAGE_PIN AU1 [get_ports "OSW_CTL_CH[7]"] ;# Bank 84 VCCO - VCC1V8 - ADCIO_16 - IO_L4N_AD8N_84 -#set_property IOSTANDARD LVCMOS18 [get_ports "OSW_CTL_CH[7]"] ;# Bank 84 VCCO - VCC1V8 - ADCIO_16 - IO_L4N_AD8N_84 diff --git a/qick/firmware/xdc/ios_216.xdc b/qick/firmware/xdc/ios_216.xdc deleted file mode 100644 index 1caabd8..0000000 --- a/qick/firmware/xdc/ios_216.xdc +++ /dev/null @@ -1,33 +0,0 @@ -set_property PACKAGE_PIN G15 [get_ports "PMOD0_0_LS"] ;# Bank 88 VCCO - VCC1V8 - IO_L12N_AD8N_88 -set_property IOSTANDARD LVCMOS18 [get_ports "PMOD0_0_LS"] ;# Bank 88 VCCO - VCC1V8 - IO_L12N_AD8N_88 -set_property PACKAGE_PIN G16 [get_ports "PMOD0_1_LS"] ;# Bank 88 VCCO - VCC1V8 - IO_L12P_AD8P_88 -set_property IOSTANDARD LVCMOS18 [get_ports "PMOD0_1_LS"] ;# Bank 88 VCCO - VCC1V8 - IO_L12P_AD8P_88 -set_property PACKAGE_PIN H14 [get_ports "PMOD0_2_LS"] ;# Bank 88 VCCO - VCC1V8 - IO_L11N_AD9N_88 -set_property IOSTANDARD LVCMOS18 [get_ports "PMOD0_2_LS"] ;# Bank 88 VCCO - VCC1V8 - IO_L11N_AD9N_88 -set_property PACKAGE_PIN H15 [get_ports "PMOD0_3_LS"] ;# Bank 88 VCCO - VCC1V8 - IO_L11P_AD9P_88 -set_property IOSTANDARD LVCMOS18 [get_ports "PMOD0_3_LS"] ;# Bank 88 VCCO - VCC1V8 - IO_L11P_AD9P_88 -set_property PACKAGE_PIN G13 [get_ports "PMOD0_4_LS"] ;# Bank 88 VCCO - VCC1V8 - IO_L10N_AD10N_88 -set_property IOSTANDARD LVCMOS18 [get_ports "PMOD0_4_LS"] ;# Bank 88 VCCO - VCC1V8 - IO_L10N_AD10N_88 -set_property PACKAGE_PIN H13 [get_ports "PMOD0_5_LS"] ;# Bank 88 VCCO - VCC1V8 - IO_L10P_AD10P_88 -set_property IOSTANDARD LVCMOS18 [get_ports "PMOD0_5_LS"] ;# Bank 88 VCCO - VCC1V8 - IO_L10P_AD10P_88 -set_property PACKAGE_PIN J13 [get_ports "PMOD0_6_LS"] ;# Bank 88 VCCO - VCC1V8 - IO_L9N_AD11N_88 -set_property IOSTANDARD LVCMOS18 [get_ports "PMOD0_6_LS"] ;# Bank 88 VCCO - VCC1V8 - IO_L9N_AD11N_88 -set_property PACKAGE_PIN J14 [get_ports "PMOD0_7_LS"] ;# Bank 88 VCCO - VCC1V8 - IO_L9P_AD11P_88 -set_property IOSTANDARD LVCMOS18 [get_ports "PMOD0_7_LS"] ;# Bank 88 VCCO - VCC1V8 - IO_L9P_AD11P_88 - -set_property PACKAGE_PIN L17 [get_ports "PMOD1_0_LS"] ;# Bank 88 VCCO - VCC1V8 - IO_L4N_AD12N_88 -set_property IOSTANDARD LVCMOS18 [get_ports "PMOD1_0_LS"] ;# Bank 88 VCCO - VCC1V8 - IO_L4N_AD12N_88 -#set_property PACKAGE_PIN M17 [get_ports "PMOD1_1_LS"] ;# Bank 88 VCCO - VCC1V8 - IO_L4P_AD12P_88 -#set_property IOSTANDARD LVCMOS18 [get_ports "PMOD1_1_LS"] ;# Bank 88 VCCO - VCC1V8 - IO_L4P_AD12P_88 -#set_property PACKAGE_PIN M14 [get_ports "PMOD1_2_LS"] ;# Bank 88 VCCO - VCC1V8 - IO_L3N_AD13N_88 -#set_property IOSTANDARD LVCMOS18 [get_ports "PMOD1_2_LS"] ;# Bank 88 VCCO - VCC1V8 - IO_L3N_AD13N_88 -#set_property PACKAGE_PIN N14 [get_ports "PMOD1_3_LS"] ;# Bank 88 VCCO - VCC1V8 - IO_L3P_AD13P_88 -#set_property IOSTANDARD LVCMOS18 [get_ports "PMOD1_3_LS"] ;# Bank 88 VCCO - VCC1V8 - IO_L3P_AD13P_88 -#set_property PACKAGE_PIN M15 [get_ports "PMOD1_4_LS"] ;# Bank 88 VCCO - VCC1V8 - IO_L2N_AD14N_88 -#set_property IOSTANDARD LVCMOS18 [get_ports "PMOD1_4_LS"] ;# Bank 88 VCCO - VCC1V8 - IO_L2N_AD14N_88 -#set_property PACKAGE_PIN N15 [get_ports "PMOD1_5_LS"] ;# Bank 88 VCCO - VCC1V8 - IO_L2P_AD14P_88 -#set_property IOSTANDARD LVCMOS18 [get_ports "PMOD1_5_LS"] ;# Bank 88 VCCO - VCC1V8 - IO_L2P_AD14P_88 -#set_property PACKAGE_PIN M16 [get_ports "PMOD1_6_LS"] ;# Bank 88 VCCO - VCC1V8 - IO_L1N_AD15N_88 -#set_property IOSTANDARD LVCMOS18 [get_ports "PMOD1_6_LS"] ;# Bank 88 VCCO - VCC1V8 - IO_L1N_AD15N_88 -#set_property PACKAGE_PIN N16 [get_ports "PMOD1_7_LS"] ;# Bank 88 VCCO - VCC1V8 - IO_L1P_AD15P_88 -#set_property IOSTANDARD LVCMOS18 [get_ports "PMOD1_7_LS"] ;# Bank 88 VCCO - VCC1V8 - IO_L1P_AD15P_88 diff --git a/qick/firmware/xdc/ios_4x2.xdc b/qick/firmware/xdc/ios_4x2.xdc deleted file mode 100644 index 5a79376..0000000 --- a/qick/firmware/xdc/ios_4x2.xdc +++ /dev/null @@ -1,28 +0,0 @@ -set_property PACKAGE_PIN AF16 [ get_ports "PMOD0_0" ] -set_property PACKAGE_PIN AG17 [ get_ports "PMOD0_1" ] -set_property PACKAGE_PIN AJ16 [ get_ports "PMOD0_2" ] -set_property PACKAGE_PIN AK17 [ get_ports "PMOD0_3" ] -#set_property PACKAGE_PIN AF15 [ get_ports "PMOD0_4" ] -#set_property PACKAGE_PIN AF17 [ get_ports "PMOD0_5" ] -#set_property PACKAGE_PIN AH17 [ get_ports "PMOD0_6" ] -#set_property PACKAGE_PIN AK16 [ get_ports "PMOD0_7" ] -set_property IOSTANDARD LVCMOS18 [ get_ports "PMOD0*"] - -#set_property PACKAGE_PIN AW13 [ get_ports "PMOD1_0" ] -#set_property PACKAGE_PIN AR13 [ get_ports "PMOD1_1" ] -#set_property PACKAGE_PIN AU13 [ get_ports "PMOD1_2" ] -#set_property PACKAGE_PIN AV13 [ get_ports "PMOD1_3" ] -#set_property PACKAGE_PIN AU15 [ get_ports "PMOD1_4" ] -#set_property PACKAGE_PIN AP14 [ get_ports "PMOD1_5" ] -#set_property PACKAGE_PIN AT15 [ get_ports "PMOD1_6" ] -#set_property PACKAGE_PIN AU14 [ get_ports "PMOD1_7" ] -#set_property IOSTANDARD LVCMOS18 [ get_ports "PMOD1*"] - -#set_property PACKAGE_PIN AW16 [ get_ports "PMOD01_0" ] -#set_property PACKAGE_PIN AW15 [ get_ports "PMOD01_1" ] -#set_property PACKAGE_PIN AW14 [ get_ports "PMOD01_2" ] -#set_property PACKAGE_PIN AR16 [ get_ports "PMOD01_3" ] -#set_property PACKAGE_PIN AV16 [ get_ports "PMOD01_4" ] -#set_property PACKAGE_PIN AT16 [ get_ports "PMOD01_5" ] -#set_property IOSTANDARD LVCMOS18 [ get_ports "PMOD01*"] - diff --git a/qick/firmware/xdc/timing_111.xdc b/qick/firmware/xdc/timing_111.xdc deleted file mode 100644 index 5b2c2fd..0000000 --- a/qick/firmware/xdc/timing_111.xdc +++ /dev/null @@ -1,39 +0,0 @@ -set clk_axi [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/usp_rf_data_converter_0/s_axi_aclk]]] - -# ADC/DAC -#set clk_adc0 [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/usp_rf_data_converter_0/clk_adc0]]] -set clk_adc0_x2 [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/clk_adc0_x2/clk_out1]]] -set clk_dac0 [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/usp_rf_data_converter_0/clk_dac0]]] -set clk_dac1 [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/usp_rf_data_converter_0/clk_dac1]]] - -#set_clock_group -name clk_axi_to_fabric -asynchronous \ -# -group [get_clocks $clk_axi] \ -# -group [get_clocks $clk_dac0] \ -# -group [get_clocks $clk_dac1] \ -# -group [get_clocks $clk_adc0_x2] - -#set_clock_group -name clk_adc_to_adc_x2 -asynchronous \ -# -group [get_clocks $clk_adc0] \ -# -group [get_clocks $clk_adc0_x2] - - - -set_clock_group -name clk_axi_to_adc0_x2 -asynchronous \ - -group [get_clocks $clk_axi] \ - -group [get_clocks $clk_adc0_x2] - -set_clock_group -name clk_axi_to_dac0 -asynchronous \ - -group [get_clocks $clk_axi] \ - -group [get_clocks $clk_dac0] - -set_clock_group -name clk_axi_to_dac1 -asynchronous \ - -group [get_clocks $clk_axi] \ - -group [get_clocks $clk_dac1] - -set_clock_group -name clk_tproc_to_dac1 -asynchronous \ - -group [get_clocks $clk_dac0] \ - -group [get_clocks $clk_dac1] - -set_clock_group -name clk_tproc_to_adc0_x2 -asynchronous \ - -group [get_clocks $clk_dac0] \ - -group [get_clocks $clk_adc0_x2] diff --git a/qick/firmware/xdc/timing_111_rfbv1.xdc b/qick/firmware/xdc/timing_111_rfbv1.xdc deleted file mode 100644 index aa32e7a..0000000 --- a/qick/firmware/xdc/timing_111_rfbv1.xdc +++ /dev/null @@ -1,21 +0,0 @@ -set clk_axi [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/usp_rf_data_converter_0/s_axi_aclk]]] - -# ADC/DAC -set clk_adc0 [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/usp_rf_data_converter_0/clk_adc0]]] -set clk_adc0_x2 [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/clk_adc0_x2/clk_out1]]] -set clk_dac0 [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/usp_rf_data_converter_0/clk_dac0]]] -set clk_dac1 [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/usp_rf_data_converter_0/clk_dac1]]] - -set_clock_group -name clk_axi_to_fabric -asynchronous \ - -group [get_clocks $clk_axi] \ - -group [get_clocks $clk_dac0] \ - -group [get_clocks $clk_dac1] \ - -group [get_clocks $clk_adc0_x2] - -set_clock_group -name clk_adc_to_adc_x2 -asynchronous \ - -group [get_clocks $clk_adc0] \ - -group [get_clocks $clk_adc0_x2] - -# Fix io critical warning on lo input mux to spi ip -set_property IOB FALSE [get_cells d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG] -# diff --git a/qick/firmware/xdc/timing_216.xdc b/qick/firmware/xdc/timing_216.xdc deleted file mode 100644 index 3ebe5c1..0000000 --- a/qick/firmware/xdc/timing_216.xdc +++ /dev/null @@ -1,13 +0,0 @@ -set clk_axi [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/usp_rf_data_converter_0/s_axi_aclk]]] - -# ADC/DAC -set clk_adc2 [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/usp_rf_data_converter_0/clk_adc2]]] -set clk_dac2 [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/usp_rf_data_converter_0/clk_dac2]]] -set clk_dac3 [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/usp_rf_data_converter_0/clk_dac3]]] - -set_clock_group -name clk_axi_to_fabric -asynchronous \ - -group [get_clocks $clk_axi] \ - -group [get_clocks $clk_dac2] \ - -group [get_clocks $clk_dac3] \ - -group [get_clocks $clk_adc2] - diff --git a/qick/firmware/xdc/timing_4x2.xdc b/qick/firmware/xdc/timing_4x2.xdc deleted file mode 100644 index 9c0f722..0000000 --- a/qick/firmware/xdc/timing_4x2.xdc +++ /dev/null @@ -1,34 +0,0 @@ -set clk_axi [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/zynq_ultra_ps_e_0/pl_clk0]]] -set clk_adc0 [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/usp_rf_data_converter_0/clk_adc0]]] -set clk_dac0 [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/usp_rf_data_converter_0/clk_dac0]]] -set clk_dac2 [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/usp_rf_data_converter_0/clk_dac2]]] -set clk_adc0_x2 [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/clk_adc0_x2/clk_out1]]] -set clk_tproc [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/clk_tproc/clk_out1]]] - -set_clock_group -name clk_axi_to_adc0_x2 -asynchronous \ - -group [get_clocks $clk_axi] \ - -group [get_clocks $clk_adc0_x2] - -set_clock_group -name clk_axi_to_dac0 -asynchronous \ - -group [get_clocks $clk_axi] \ - -group [get_clocks $clk_dac0] - -set_clock_group -name clk_axi_to_dac2 -asynchronous \ - -group [get_clocks $clk_axi] \ - -group [get_clocks $clk_dac2] - -set_clock_group -name clk_axi_to_tproc -asynchronous \ - -group [get_clocks $clk_axi] \ - -group [get_clocks $clk_tproc] - -set_clock_group -name clk_tproc_to_dac0 -asynchronous \ - -group [get_clocks $clk_tproc] \ - -group [get_clocks $clk_dac0] - -set_clock_group -name clk_tproc_to_dac2 -asynchronous \ - -group [get_clocks $clk_tproc] \ - -group [get_clocks $clk_dac2] - -set_clock_group -name clk_tproc_to_adc0_x2 -asynchronous \ - -group [get_clocks $clk_tproc] \ - -group [get_clocks $clk_adc0_x2] \ No newline at end of file diff --git a/qick/graphics/QICK.jpg b/qick/graphics/QICK.jpg deleted file mode 100644 index 7ce1dab..0000000 Binary files a/qick/graphics/QICK.jpg and /dev/null differ diff --git a/qick/graphics/logoQICK.svg b/qick/graphics/logoQICK.svg deleted file mode 100644 index 9127ea0..0000000 --- a/qick/graphics/logoQICK.svg +++ /dev/null @@ -1,173 +0,0 @@ - - - - diff --git a/qick/graphics/qsystem-readout.png b/qick/graphics/qsystem-readout.png deleted file mode 100644 index 01a853a..0000000 Binary files a/qick/graphics/qsystem-readout.png and /dev/null differ diff --git a/qick/graphics/qsystem-readout.svg b/qick/graphics/qsystem-readout.svg deleted file mode 100644 index 56d1242..0000000 --- a/qick/graphics/qsystem-readout.svg +++ /dev/null @@ -1 +0,0 @@ - \ No newline at end of file diff --git a/qick/hardware/README.md b/qick/hardware/README.md deleted file mode 100644 index 901c2b5..0000000 --- a/qick/hardware/README.md +++ /dev/null @@ -1,13 +0,0 @@ -# RF board hardware README - -Last updated on 9/25/2022. - -Please download the linked zip file to see the gerbers, BOM and spec file for the ZCU111 RF board V4: https://drive.google.com/drive/folders/1Fn6O4_VWpmnVYbzh4Vd3sZ7TfodG5d2U?usp=sharing. -As of 9/25/2022, there are some modifications that the assembler will need to make: - -* C518 should not be installed. -* R84 value should be changed from 18.2K to 9.76K -* There are oscillations on some RF ADC inputs. -* Added 0.4"x0.65" strip of 3M AB5010S EMI Absorber under the first RF covers of the RF ADC channels. -* Note that AB5010S is obsolete and replaced with AB5010SHF (Halogen Free). - diff --git a/qick/hardware/RF Board Schematic V1.pdf b/qick/hardware/RF Board Schematic V1.pdf deleted file mode 100644 index 16fe2d3..0000000 Binary files a/qick/hardware/RF Board Schematic V1.pdf and /dev/null differ diff --git a/qick/hardware/RF Board Schematic V2.pdf b/qick/hardware/RF Board Schematic V2.pdf deleted file mode 100644 index 915de87..0000000 Binary files a/qick/hardware/RF Board Schematic V2.pdf and /dev/null differ diff --git a/qick/pyro4/00_nameserver.ipynb b/qick/pyro4/00_nameserver.ipynb deleted file mode 100644 index 1a2b09f..0000000 --- a/qick/pyro4/00_nameserver.ipynb +++ /dev/null @@ -1,225 +0,0 @@ -{ - "cells": [ - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "#
Running remotely using Pyro4\n", - "###
In this demo you will learn how to run the low-level software on the QICK as a server, and \"proxy\" it over the network to a separate client computer that runs the high-level software." - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "Pyro4 is a software package that lets you \"proxy\" a Python object so it can be accessed from another computer.\n", - "\n", - "https://pyro4.readthedocs.io/en/stable/intro.html\n", - "\n", - "we can use Pyro4 to proxy the QickSoc object. This allows you to take any of the demo notebooks and run it on a different computer, and all you need to do is replace the `QickSoc()` initialization with some Pyro4 initialization.\n", - "\n", - "## Pros and cons\n", - "There are advantages to using Pyro4:\n", - "* The QickSoc doesn't get reinitialized every time you restart your notebook. If your experiment cares about the readout phase, which gets reset and must be recalibrated every time the FPGA gets reprogrammed, this is a big deal.\n", - "* You can write and run your QickProgram (or AveragerProgram/RAveragerProgram) on any computer. If you're used to using a graphical IDE, or you want to run your programs in an environment other than what's available on the QICK (i.e. Jupyter notebooks and command-line scripts over SSH), this is a big deal. Your PC is probably also more responsive than the QICK (which has approximately the CPU/RAM/storage performance of a Raspberry Pi).\n", - "\n", - "But there are disadvantages that you should be aware of:\n", - "* There's some overhead: you need to start a nameserver and server in addition to what you would normally do.\n", - "* Debugging is harder, because exceptions on the server don't get printed on the client (you just get a generic Pyro4 error) without some extra work: https://pyro4.readthedocs.io/en/stable/errors.html\n", - "* Any messages printed by QickSoc code only show up on the server.\n", - "* Pyro4 only proxies methods and specially registered properties of the QickSoc. This means that you can't access all the members of the QickSoc (e.g. the readout and generator objects). The demos are written to avoid Pyro4-incompatible operations, but you may have code that needs to be rewritten.\n", - "* It's easy to lose track of which version of the QICK library you have installed in which place.\n", - "\n", - "## Overview, requirements\n", - "There are three components to a Pyro4 setup: the nameserver, the server (also known as the daemon), and the client. Start them in this order.\n", - "\n", - "The server must run on the QICK, but the nameserver and client can be anywhere. To keep things self-contained, this demo is structured to put everything on the QICK, but we note what you would do differently if running the nameserver and/or client elsewhere.\n", - "\n", - "The nameserver, server, and client must all be on the same network - a lab LAN is fine. Tailscale (http://tailscale.com/) works well in the case where everything has Internet access, but not everything is on the same LAN.\n", - "\n", - "You need to install pyro4, both on the QICK and the computer(s) running the nameserver and client - it's a Python module, available through pip (`sudo pip3 install Pyro4`) or apt (`sudo apt install python3-pyro4`).\n", - "\n", - "The nameserver and server run continuously, so if you want to run them in Jupyter notebooks you need to use separate notebooks for the nameserver, server, and client. Alternatively, you could run the nameserver and server as command-line scripts (also provided here) which you would run over SSH, perhaps using a tool such as `screen` which provides persistent terminal sessions that survive loss of an SSH connection." - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "## Nameserver\n", - "The nameserver is how the client finds the server. You should only run one nameserver on a network.\n", - "\n", - "##### Hostname\n", - "The hostname defines how clients and servers can connect to the nameserver. Specify the hostname or IP address that both the client and server will use to connect to the nameserver (if you're running everything on the QICK you could specify \"localhost\" or \"127.0.0.1\" to restrict access to programs running locally). \"0.0.0.0\" means that the nameserver listens on all available network interfaces, which is usually what you want (but might not work in all cases?).\n", - "\n", - "##### Port\n", - "Because the default nameserver port (9090) conflicts with the port PYNQ uses for the Jupyter notebook server, we use port 8888 in this demo. If you put the nameserver elsewhere, you might prefer to use the default port and save a few lines of code. In this case you would not define the ns_port variable and omit that parameter in the `pyro4-ns` and `locateNS()` commands.\n", - "\n", - "### Running the nameserver\n", - "To run the nameserver, run the following shell command (either in an SSH session or a separate notebook):\n", - "```\n", - "PYRO_SERIALIZERS_ACCEPTED=pickle PYRO_PICKLE_PROTOCOL_VERSION=4 pyro4-ns -n 0.0.0.0 -p 8888\n", - "```\n", - "\n", - "There's also a script in this directory, which takes the same options (again, this could run over SSH or in a notebook):\n", - "```\n", - "./nameserver.sh -n 0.0.0.0 -p 8888\n", - "```\n", - "\n", - "Typical output looks like this:\n", - "\n", - "```\n", - "xilinx@pynq216:~$ export PYRO_SERIALIZERS_ACCEPTED=pickle PYRO_PICKLE_PROTOCOL_VERSION=4 pyro4-ns -n 0.0.0.0 -p 8888\n", - "Broadcast server running on 0.0.0.0:9091\n", - "NS running on 0.0.0.0:8888 (0.0.0.0)\n", - "Warning: HMAC key not set. Anyone can connect to this server!\n", - "URI = PYRO:Pyro.NameServer@0.0.0.0:8888\n", - "```\n", - "\n", - "The nameserver doesn't print anything when servers and clients connect to it - don't worry! Leave it running. \n", - "\n", - "Now start the server and client, in that order (see the other two notebooks in this directory).\n", - "\n", - "**If you stop the nameserver for any reason, you need to restart the server, then any clients.**" - ] - }, - { - "cell_type": "code", - "execution_count": 1, - "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "Broadcast server running on 0.0.0.0:9091\n", - "NS running on 0.0.0.0:8888 (0.0.0.0)\n", - "Warning: HMAC key not set. Anyone can connect to this server!\n", - "URI = PYRO:Pyro.NameServer@0.0.0.0:8888\n", - "^C\n" - ] - } - ], - "source": [ - "!./nameserver.sh -n 0.0.0.0 -p 8888" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "If you just want some Python code that starts a nameserver, this does the same thing as the script:" - ] - }, - { - "cell_type": "code", - "execution_count": 2, - "metadata": {}, - "outputs": [ - { - "data": { - "application/javascript": [ - "\n", - "try {\n", - "require(['notebook/js/codecell'], function(codecell) {\n", - " codecell.CodeCell.options_default.highlight_modes[\n", - " 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n", - " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", - " Jupyter.notebook.get_cells().map(function(cell){\n", - " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", - " });\n", - "});\n", - "} catch (e) {};\n" - ] - }, - "metadata": {}, - "output_type": "display_data" - }, - { - "data": { - "application/javascript": [ - "\n", - "try {\n", - "require(['notebook/js/codecell'], function(codecell) {\n", - " codecell.CodeCell.options_default.highlight_modes[\n", - " 'magic_text/x-csrc'] = {'reg':[/^%%pybind11/]};\n", - " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", - " Jupyter.notebook.get_cells().map(function(cell){\n", - " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", - " });\n", - "});\n", - "} catch (e) {};\n" - ] - }, - "metadata": {}, - "output_type": "display_data" - }, - { - "name": "stdout", - "output_type": "stream", - "text": [ - "Broadcast server running on 0.0.0.0:9091\n", - "NS running on 0.0.0.0:8888 (0.0.0.0)\n", - "Warning: HMAC key not set. Anyone can connect to this server!\n", - "URI = PYRO:Pyro.NameServer@0.0.0.0:8888\n", - "NS shut down.\n" - ] - } - ], - "source": [ - "from qick.pyro import start_nameserver\n", - "start_nameserver(ns_port=8888)" - ] - }, - { - "cell_type": "code", - "execution_count": 3, - "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "Help on function start_nameserver in module qick_pyro:\n", - "\n", - "start_nameserver(ns_port=8888)\n", - " Starts a Pyro4 nameserver that listens on all network interfaces.\n", - " \n", - " Parameters\n", - " ----------\n", - " ns_port : int\n", - " the port number for the nameserver to listen on\n", - " \n", - " Returns\n", - " -------\n", - "\n" - ] - } - ], - "source": [ - "help(start_nameserver)" - ] - } - ], - "metadata": { - "kernelspec": { - "display_name": "Python 3 (ipykernel)", - "language": "python", - "name": "python3" - }, - "language_info": { - "codemirror_mode": { - "name": "ipython", - "version": 3 - }, - "file_extension": ".py", - "mimetype": "text/x-python", - "name": "python", - "nbconvert_exporter": "python", - "pygments_lexer": "ipython3", - "version": "3.11.3" - } - }, - "nbformat": 4, - "nbformat_minor": 2 -} diff --git a/qick/pyro4/01_server.ipynb b/qick/pyro4/01_server.ipynb deleted file mode 100644 index 5294b20..0000000 --- a/qick/pyro4/01_server.ipynb +++ /dev/null @@ -1,154 +0,0 @@ -{ - "cells": [ - { - "cell_type": "markdown", - "id": "8eb4502d", - "metadata": {}, - "source": [ - "## Server\n", - "The server runs the QickSoc code and exposes it to the network.\n", - "\n", - "The nameserver must already be running (see the previous notebook in this directory).\n", - "\n", - "You can choose whatever proxy name you want, as long as you use the same one on the client. You could run multiple QICKs, each with a Pyro4 server, using different server names.\n", - "\n", - "You can use the notebook cells below, or the script in this directory (use `-h` for help), which must run as root with the PYNQ environment initialized:\n", - "\n", - "```\n", - "sudo -s\n", - "source /etc/profile\n", - "python -m qick.pyro_cli myqick -n localhost -p 8888\n", - "```\n", - "\n", - "Either way, leave the server running.\n", - "\n", - "Now you can start a client (see the next notebook in this directory).\n", - "\n", - "**\"localhost\" is only correct if you are running the nameserver on the QICK board. If the nameserver is elsewhere, you need to use its IP or a hostname that resolves to it.**" - ] - }, - { - "cell_type": "code", - "execution_count": 1, - "id": "5976d31a", - "metadata": {}, - "outputs": [ - { - "data": { - "application/javascript": [ - "\n", - "try {\n", - "require(['notebook/js/codecell'], function(codecell) {\n", - " codecell.CodeCell.options_default.highlight_modes[\n", - " 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n", - " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", - " Jupyter.notebook.get_cells().map(function(cell){\n", - " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", - " });\n", - "});\n", - "} catch (e) {};\n" - ] - }, - "metadata": {}, - "output_type": "display_data" - }, - { - "data": { - "application/javascript": [ - "\n", - "try {\n", - "require(['notebook/js/codecell'], function(codecell) {\n", - " codecell.CodeCell.options_default.highlight_modes[\n", - " 'magic_text/x-csrc'] = {'reg':[/^%%pybind11/]};\n", - " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", - " Jupyter.notebook.get_cells().map(function(cell){\n", - " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", - " });\n", - "});\n", - "} catch (e) {};\n" - ] - }, - "metadata": {}, - "output_type": "display_data" - }, - { - "name": "stdout", - "output_type": "stream", - "text": [ - "looking for nameserver . . .\n", - "found nameserver\n", - "initialized QICK\n", - "registered QICK\n", - "registered member \n", - "registered member \n", - "starting daemon\n" - ] - } - ], - "source": [ - "from qick.pyro import start_server\n", - "start_server(ns_host=\"localhost\", ns_port=8888, proxy_name=\"myqick\")" - ] - }, - { - "cell_type": "code", - "execution_count": 2, - "id": "e6b32867", - "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "Help on function start_server in module qick_pyro:\n", - "\n", - "start_server(ns_host, ns_port=8888, proxy_name='myqick', **kwargs)\n", - " Initializes the QickSoc and starts a Pyro4 proxy server.\n", - " \n", - " Parameters\n", - " ----------\n", - " ns_host : str\n", - " hostname or IP address of the nameserver\n", - " if the nameserver is running on the QICK board, \"localhost\" is fine\n", - " ns_port : int\n", - " the port number you used when starting the nameserver\n", - " proxy_name : str\n", - " name for the QickSoc proxy\n", - " multiple boards can use the same nameserver, but must have different names\n", - " kwargs : optional named arguments\n", - " any other options will be passed to the QickSoc constructor;\n", - " see QickSoc documentation for details\n", - " \n", - " Returns\n", - " -------\n", - "\n" - ] - } - ], - "source": [ - "help(start_server)" - ] - } - ], - "metadata": { - "kernelspec": { - "display_name": "Python 3 (ipykernel)", - "language": "python", - "name": "python3" - }, - "language_info": { - "codemirror_mode": { - "name": "ipython", - "version": 3 - }, - "file_extension": ".py", - "mimetype": "text/x-python", - "name": "python", - "nbconvert_exporter": "python", - "pygments_lexer": "ipython3", - "version": "3.11.3" - } - }, - "nbformat": 4, - "nbformat_minor": 5 -} diff --git a/qick/pyro4/02_client.ipynb b/qick/pyro4/02_client.ipynb deleted file mode 100644 index 904a4dc..0000000 --- a/qick/pyro4/02_client.ipynb +++ /dev/null @@ -1,341 +0,0 @@ -{ - "cells": [ - { - "cell_type": "markdown", - "id": "73b66a2b", - "metadata": {}, - "source": [ - "## Client\n", - "The client controls the experiment. The client doesn't need the PYNQ device drivers, so it can be a Linux or Windows PC (you should be able to install the QICK libraries as usual, the PYNQ library will be skipped on systems that don't support it).\n", - "\n", - "The nameserver and server must already be running (see the previous notebooks in this directory).\n", - "\n", - "The cells below contain the initialization code that replace the typical initialization steps of:\n", - "```\n", - "from qick import QickSoc\n", - "soc = QickSoc()\n", - "soccfg = soc\n", - "```\n", - "\n", - "**\"localhost\" is only correct for this proof of concept, where the nameserver is running in the same place as the client. In actual use, your client will be some PC, and the nameserver might be running on the QICK board or a third PC. Either way, you need to use the nameserver's IP or a hostname that resolves to it.**" - ] - }, - { - "cell_type": "code", - "execution_count": 1, - "id": "b565f064", - "metadata": {}, - "outputs": [ - { - "data": { - "application/javascript": [ - "\n", - "try {\n", - "require(['notebook/js/codecell'], function(codecell) {\n", - " codecell.CodeCell.options_default.highlight_modes[\n", - " 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n", - " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", - " Jupyter.notebook.get_cells().map(function(cell){\n", - " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", - " });\n", - "});\n", - "} catch (e) {};\n" - ] - }, - "metadata": {}, - "output_type": "display_data" - }, - { - "data": { - "application/javascript": [ - "\n", - "try {\n", - "require(['notebook/js/codecell'], function(codecell) {\n", - " codecell.CodeCell.options_default.highlight_modes[\n", - " 'magic_text/x-csrc'] = {'reg':[/^%%pybind11/]};\n", - " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", - " Jupyter.notebook.get_cells().map(function(cell){\n", - " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", - " });\n", - "});\n", - "} catch (e) {};\n" - ] - }, - "metadata": {}, - "output_type": "display_data" - } - ], - "source": [ - "import Pyro4\n", - "from qick import QickConfig\n", - "Pyro4.config.SERIALIZER = \"pickle\"\n", - "Pyro4.config.PICKLE_PROTOCOL_VERSION=4\n", - "\n", - "ns_host = \"localhost\"\n", - "ns_port = 8888\n", - "proxy_name = \"myqick\"\n", - "\n", - "ns = Pyro4.locateNS(host=ns_host, port=ns_port)" - ] - }, - { - "cell_type": "markdown", - "id": "b623eb10", - "metadata": {}, - "source": [ - "Let's see what is registered on the nameserver:" - ] - }, - { - "cell_type": "code", - "execution_count": 2, - "id": "10238eff", - "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "Pyro.NameServer PYRO:Pyro.NameServer@0.0.0.0:8888\n", - "myqick PYRO:obj_2d0d1ae01ad847229027ddb66b3e0181@131.225.82.122:39409\n" - ] - } - ], - "source": [ - "# print the nameserver entries: you should see the QickSoc proxy\n", - "for k,v in ns.list().items():\n", - " print(k,v)" - ] - }, - { - "cell_type": "markdown", - "id": "0d8c046a", - "metadata": {}, - "source": [ - "Now, connect to the server. The Proxy object replaces the QickSoc in your code. There's one additional step: you need to create a QickConfig object that contains all the information necessary to compile programs.\n", - "\n", - "In the demo notebooks both `soc` and `soccfg` point to the same QickSoc object; when using Pyro, `soc` is a Proxy object and `soccfg` is a QickConfig object." - ] - }, - { - "cell_type": "code", - "execution_count": 3, - "id": "516d5b4c", - "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "\n", - "QICK configuration:\n", - "\n", - "\tBoard: ZCU216\n", - "\n", - "\tGlobal clocks (MHz): tProcessor 430.080, RF reference 245.760\n", - "\n", - "\t7 signal generator channels:\n", - "\t0:\taxis_signal_gen_v6 - tProc output 1, envelope memory 65536 samples\n", - "\t\tDAC tile 2, ch 0, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\t1:\taxis_signal_gen_v6 - tProc output 2, envelope memory 65536 samples\n", - "\t\tDAC tile 2, ch 1, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\t2:\taxis_signal_gen_v6 - tProc output 3, envelope memory 65536 samples\n", - "\t\tDAC tile 2, ch 2, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\t3:\taxis_signal_gen_v6 - tProc output 4, envelope memory 65536 samples\n", - "\t\tDAC tile 2, ch 3, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\t4:\taxis_signal_gen_v6 - tProc output 5, envelope memory 65536 samples\n", - "\t\tDAC tile 3, ch 0, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\t5:\taxis_signal_gen_v6 - tProc output 6, envelope memory 65536 samples\n", - "\t\tDAC tile 3, ch 1, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\t6:\taxis_signal_gen_v6 - tProc output 7, envelope memory 65536 samples\n", - "\t\tDAC tile 3, ch 2, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\n", - "\t2 readout channels:\n", - "\t0:\taxis_readout_v2 - controlled by PYNQ\n", - "\t\tADC tile 2, ch 0, 32-bit DDS, fabric=307.200 MHz, fs=2457.600 MHz\n", - "\t\tmaxlen 16384 (avg) 1024 (decimated), trigger bit 14, tProc input 0\n", - "\t1:\taxis_readout_v2 - controlled by PYNQ\n", - "\t\tADC tile 2, ch 2, 32-bit DDS, fabric=307.200 MHz, fs=2457.600 MHz\n", - "\t\tmaxlen 16384 (avg) 1024 (decimated), trigger bit 15, tProc input 1\n", - "\n", - "\t7 DACs:\n", - "\t\tDAC tile 2, ch 0 is 0_230, on JHC3\n", - "\t\tDAC tile 2, ch 1 is 1_230, on JHC4\n", - "\t\tDAC tile 2, ch 2 is 2_230, on JHC3\n", - "\t\tDAC tile 2, ch 3 is 3_230, on JHC4\n", - "\t\tDAC tile 3, ch 0 is 0_231, on JHC3\n", - "\t\tDAC tile 3, ch 1 is 1_231, on JHC4\n", - "\t\tDAC tile 3, ch 2 is 2_231, on JHC3\n", - "\n", - "\t2 ADCs:\n", - "\t\tADC tile 2, ch 0 is 0_226, on JHC7\n", - "\t\tADC tile 2, ch 2 is 2_226, on JHC7\n", - "\n", - "\t8 digital output pins (tProc output 0):\n", - "\t0:\tPMOD0_0_LS\n", - "\t1:\tPMOD0_1_LS\n", - "\t2:\tPMOD0_2_LS\n", - "\t3:\tPMOD0_3_LS\n", - "\t4:\tPMOD0_4_LS\n", - "\t5:\tPMOD0_5_LS\n", - "\t6:\tPMOD0_6_LS\n", - "\t7:\tPMOD0_7_LS\n", - "\n", - "\ttProc: program memory 8192 words, data memory 4096 words\n", - "\t\texternal start pin: PMOD1_0_LS\n" - ] - } - ], - "source": [ - "soc = Pyro4.Proxy(ns.lookup(proxy_name))\n", - "soccfg = QickConfig(soc.get_cfg())\n", - "print(soccfg)" - ] - }, - { - "cell_type": "markdown", - "id": "695d7d15", - "metadata": {}, - "source": [ - "For your convenience, there's a function that encapsulates the code above. You could just put this in your code." - ] - }, - { - "cell_type": "code", - "execution_count": 4, - "id": "bb0b9371", - "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "Pyro.NameServer PYRO:Pyro.NameServer@0.0.0.0:8888\n", - "myqick PYRO:obj_2d0d1ae01ad847229027ddb66b3e0181@131.225.82.122:39409\n", - "\n", - "QICK configuration:\n", - "\n", - "\tBoard: ZCU216\n", - "\n", - "\tGlobal clocks (MHz): tProcessor 430.080, RF reference 245.760\n", - "\n", - "\t7 signal generator channels:\n", - "\t0:\taxis_signal_gen_v6 - tProc output 1, envelope memory 65536 samples\n", - "\t\tDAC tile 2, ch 0, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\t1:\taxis_signal_gen_v6 - tProc output 2, envelope memory 65536 samples\n", - "\t\tDAC tile 2, ch 1, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\t2:\taxis_signal_gen_v6 - tProc output 3, envelope memory 65536 samples\n", - "\t\tDAC tile 2, ch 2, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\t3:\taxis_signal_gen_v6 - tProc output 4, envelope memory 65536 samples\n", - "\t\tDAC tile 2, ch 3, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\t4:\taxis_signal_gen_v6 - tProc output 5, envelope memory 65536 samples\n", - "\t\tDAC tile 3, ch 0, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\t5:\taxis_signal_gen_v6 - tProc output 6, envelope memory 65536 samples\n", - "\t\tDAC tile 3, ch 1, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\t6:\taxis_signal_gen_v6 - tProc output 7, envelope memory 65536 samples\n", - "\t\tDAC tile 3, ch 2, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\n", - "\t2 readout channels:\n", - "\t0:\taxis_readout_v2 - controlled by PYNQ\n", - "\t\tADC tile 2, ch 0, 32-bit DDS, fabric=307.200 MHz, fs=2457.600 MHz\n", - "\t\tmaxlen 16384 (avg) 1024 (decimated), trigger bit 14, tProc input 0\n", - "\t1:\taxis_readout_v2 - controlled by PYNQ\n", - "\t\tADC tile 2, ch 2, 32-bit DDS, fabric=307.200 MHz, fs=2457.600 MHz\n", - "\t\tmaxlen 16384 (avg) 1024 (decimated), trigger bit 15, tProc input 1\n", - "\n", - "\t7 DACs:\n", - "\t\tDAC tile 2, ch 0 is 0_230, on JHC3\n", - "\t\tDAC tile 2, ch 1 is 1_230, on JHC4\n", - "\t\tDAC tile 2, ch 2 is 2_230, on JHC3\n", - "\t\tDAC tile 2, ch 3 is 3_230, on JHC4\n", - "\t\tDAC tile 3, ch 0 is 0_231, on JHC3\n", - "\t\tDAC tile 3, ch 1 is 1_231, on JHC4\n", - "\t\tDAC tile 3, ch 2 is 2_231, on JHC3\n", - "\n", - "\t2 ADCs:\n", - "\t\tADC tile 2, ch 0 is 0_226, on JHC7\n", - "\t\tADC tile 2, ch 2 is 2_226, on JHC7\n", - "\n", - "\t8 digital output pins (tProc output 0):\n", - "\t0:\tPMOD0_0_LS\n", - "\t1:\tPMOD0_1_LS\n", - "\t2:\tPMOD0_2_LS\n", - "\t3:\tPMOD0_3_LS\n", - "\t4:\tPMOD0_4_LS\n", - "\t5:\tPMOD0_5_LS\n", - "\t6:\tPMOD0_6_LS\n", - "\t7:\tPMOD0_7_LS\n", - "\n", - "\ttProc: program memory 8192 words, data memory 4096 words\n", - "\t\texternal start pin: PMOD1_0_LS\n" - ] - } - ], - "source": [ - "from qick.pyro import make_proxy\n", - "soc, soccfg = make_proxy(ns_host=\"localhost\", ns_port=8888, proxy_name=\"myqick\")\n", - "print(soccfg)" - ] - }, - { - "cell_type": "code", - "execution_count": 5, - "id": "b8bf4dcc", - "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "Help on function make_proxy in module qick_pyro:\n", - "\n", - "make_proxy(ns_host, ns_port='8888', proxy_name='myqick')\n", - " Connects to a QickSoc proxy server.\n", - " \n", - " Parameters\n", - " ----------\n", - " ns_host : str\n", - " hostname or IP address of the nameserver\n", - " if the nameserver is running on the same PC you are running make_proxy() on, \"localhost\" is fine\n", - " ns_port : int\n", - " the port number you used when starting the nameserver\n", - " proxy_name : str\n", - " name for the QickSoc proxy you used when running start_server()\n", - " \n", - " Returns\n", - " -------\n", - " Proxy\n", - " proxy to QickSoc - this is usually called \"soc\" in demos\n", - " QickConfig\n", - " config object - this is usually called \"soccfg\" in demos\n", - "\n" - ] - } - ], - "source": [ - "help(make_proxy)" - ] - } - ], - "metadata": { - "kernelspec": { - "display_name": "Python 3 (ipykernel)", - "language": "python", - "name": "python3" - }, - "language_info": { - "codemirror_mode": { - "name": "ipython", - "version": 3 - }, - "file_extension": ".py", - "mimetype": "text/x-python", - "name": "python", - "nbconvert_exporter": "python", - "pygments_lexer": "ipython3", - "version": "3.11.3" - } - }, - "nbformat": 4, - "nbformat_minor": 5 -} diff --git a/qick/pyro4/nameserver.sh b/qick/pyro4/nameserver.sh deleted file mode 100644 index ee1f9b5..0000000 --- a/qick/pyro4/nameserver.sh +++ /dev/null @@ -1,8 +0,0 @@ -#!/bin/bash -# Start a Pyro4 nameserver. -# Typically: -# ./nameserver.sh -n 0.0.0.0 -p 8888 -export PYRO_SERIALIZERS_ACCEPTED=pickle PYRO_PICKLE_PROTOCOL_VERSION=4 - -# pass all arguments to pyro4-ns -pyro4-ns $@ diff --git a/qick/pyro4/pyro_service.py b/qick/pyro4/pyro_service.py deleted file mode 100644 index 7082ae8..0000000 --- a/qick/pyro4/pyro_service.py +++ /dev/null @@ -1,37 +0,0 @@ -#!/usr/bin/env python3 -"""This file starts a pyro nameserver and the proxying server.""" -from pathlib import Path -import subprocess -import time -from qick.pyro import start_server - -HERE = Path(__file__).parent - -############ -# parameters -############ - -bitfile = '../qick_lib/qick/qick_4x2.bit' -proxy_name ='rfsoc' -ns_port = 8000 -# set to 0.0.0.0 to allow access from outside systems -ns_host = 'localhost' - -############ - -# start the nameserver process -ns_proc = subprocess.Popen( - [f'PYRO_SERIALIZERS_ACCEPTED=pickle PYRO_PICKLE_PROTOCOL_VERSION=4 pyro4-ns -n {ns_host} -p {ns_port}'], - shell=True -) - -# wait for the nameserver to start up -time.sleep(5) - -# start the qick proxy server -start_server( - bitfile=str(HERE / bitfile), - proxy_name=proxy_name, - ns_host='localhost', - ns_port=ns_port -) diff --git a/qick/pyro4/qick_pyro.service b/qick/pyro4/qick_pyro.service deleted file mode 100644 index 61a5f0b..0000000 --- a/qick/pyro4/qick_pyro.service +++ /dev/null @@ -1,16 +0,0 @@ -# copy to /etc/systemd/system -# reload services "sudo systemctl daemon-reload" -# enable "sudo systemctl enable qick_pyro.service" - -[Unit] -Description=RFSoC QICK pyro server -After=network.target - -[Service] -Type=idle -Restart=always -User=root -ExecStart=/bin/bash -c 'source /etc/profile && python /home/xilinx/jupyter_notebooks/qick/pyro4/pyro_service.py' - -[Install] -WantedBy=multi-user.target diff --git a/qick/qick_demos/000_Install_qick_package.ipynb b/qick/qick_demos/000_Install_qick_package.ipynb deleted file mode 100644 index ec7d125..0000000 --- a/qick/qick_demos/000_Install_qick_package.ipynb +++ /dev/null @@ -1,478 +0,0 @@ -{ - "cells": [ - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "#
Installing and testing the qick package
\n", - "\n", - "This notebook will explain how to install the qick library and use it to program the FPGA.\n", - "\n", - "There are multiple ways to do any given thing, and this notebook gives several options.\n", - "The recommended option is always uncommented and ready for you to execute; alternatives are commented out, and you need to uncomment them (and comment out the recommended option) if you choose to go that route. So it should be safe to just run the whole notebook, and you will end up with a working system.\n", - "\n", - "*However we strongly recommend (not only for this notebook, but for all of the demo notebooks) that you read carefully through the notebook and run one cell at a time.*" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "## pynq library\n", - "Let's check that the Xilinx pynq library is installed: you should see (among things) a version number, which should match the version of the PYNQ Linux image you installed.\n", - "\n", - "The QICK software supports pynq versions 2.6.0 and above." - ] - }, - { - "cell_type": "code", - "execution_count": 1, - "metadata": {}, - "outputs": [ - { - "data": { - "application/javascript": [ - "\n", - "try {\n", - "require(['notebook/js/codecell'], function(codecell) {\n", - " codecell.CodeCell.options_default.highlight_modes[\n", - " 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n", - " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", - " Jupyter.notebook.get_cells().map(function(cell){\n", - " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", - " });\n", - "});\n", - "} catch (e) {};\n" - ] - }, - "metadata": {}, - "output_type": "display_data" - }, - { - "data": { - "application/javascript": [ - "\n", - "try {\n", - "require(['notebook/js/codecell'], function(codecell) {\n", - " codecell.CodeCell.options_default.highlight_modes[\n", - " 'magic_text/x-csrc'] = {'reg':[/^%%pybind11/]};\n", - " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", - " Jupyter.notebook.get_cells().map(function(cell){\n", - " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", - " });\n", - "});\n", - "} catch (e) {};\n" - ] - }, - "metadata": {}, - "output_type": "display_data" - }, - { - "name": "stdout", - "output_type": "stream", - "text": [ - "Help on package pynq:\n", - "\n", - "NAME\n", - " pynq\n", - "\n", - "DESCRIPTION\n", - " # Copyright (c) 2016, Xilinx, Inc.\n", - " # All rights reserved.\n", - " # \n", - " # Redistribution and use in source and binary forms, with or without \n", - " # modification, are permitted provided that the following conditions are met:\n", - " #\n", - " # 1. Redistributions of source code must retain the above copyright notice, \n", - " # this list of conditions and the following disclaimer.\n", - " #\n", - " # 2. Redistributions in binary form must reproduce the above copyright \n", - " # notice, this list of conditions and the following disclaimer in the \n", - " # documentation and/or other materials provided with the distribution.\n", - " #\n", - " # 3. Neither the name of the copyright holder nor the names of its \n", - " # contributors may be used to endorse or promote products derived from \n", - " # this software without specific prior written permission.\n", - " #\n", - " # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n", - " # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, \n", - " # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR \n", - " # PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n", - " # CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, \n", - " # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, \n", - " # PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n", - " # OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, \n", - " # WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR \n", - " # OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n", - " # ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n", - "\n", - "PACKAGE CONTENTS\n", - " _3rdparty (package)\n", - " _cli (package)\n", - " bitstream\n", - " buffer\n", - " devicetree\n", - " gpio\n", - " interrupt\n", - " lib (package)\n", - " mmio\n", - " overlay\n", - " overlays (package)\n", - " pl\n", - " pl_server (package)\n", - " pmbus\n", - " ps\n", - " registers\n", - " uio\n", - " utils\n", - "\n", - "DATA\n", - " __all__ = ['lib', 'tests']\n", - " __copyright__ = 'Copyright 2016, Xilinx'\n", - " __email__ = 'pynq_support@xilinx.com'\n", - " __git_id__ = '$Id: 285d1457e64c076bbb39844afd54b38f075ad2c7 $'\n", - "\n", - "VERSION\n", - " 2.7.0\n", - "\n", - "AUTHOR\n", - " Yun Rock Qu\n", - "\n", - "FILE\n", - " /usr/local/share/pynq-venv/lib/python3.8/site-packages/pynq/__init__.py\n", - "\n", - "\n" - ] - } - ], - "source": [ - "import pynq\n", - "help(pynq)" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "## qick library\n", - "\n", - "Now let's install the qick library. The qick library has three dependencies: `pynq`, `numpy`, and `tqdm`. All should already be installed as part of the PYNQ Linux image." - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### Installing using pip (recommended option)\n", - "\n", - "You could run these `pip3` commands from the shell over SSH - they need to be run as root (using `sudo`), and on pynq 2.7 you must additionally enable the pynq `venv`. Running the commands inside a notebook, as we do here, conveniently ensures that the commands run in (and install to) the same environment that the notebook runs in." - ] - }, - { - "cell_type": "code", - "execution_count": 2, - "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "Obtaining file:///home/xilinx/jupyter_notebooks/qick\n", - " Installing build dependencies ... \u001b[?25ldone\n", - "\u001b[?25h Getting requirements to build wheel ... \u001b[?25ldone\n", - "\u001b[?25h Installing backend dependencies ... \u001b[?25ldone\n", - "\u001b[?25h Preparing wheel metadata ... \u001b[?25ldone\n", - "\u001b[?25hRequirement already satisfied: numpy in /usr/local/share/pynq-venv/lib/python3.8/site-packages (from qick==1.0.0) (1.20.3)\n", - "Requirement already satisfied: tqdm in /usr/local/share/pynq-venv/lib/python3.8/site-packages (from qick==1.0.0) (4.62.3)\n", - "Requirement already satisfied: pynq in /usr/local/share/pynq-venv/lib/python3.8/site-packages (from qick==1.0.0) (2.7.0)\n", - "Requirement already satisfied: setuptools>=24.2.0 in /usr/local/share/pynq-venv/lib/python3.8/site-packages (from pynq->qick==1.0.0) (44.0.0)\n", - "Requirement already satisfied: pandas in /usr/local/share/pynq-venv/lib/python3.8/site-packages (from pynq->qick==1.0.0) (1.3.3)\n", - "Requirement already satisfied: cffi in /usr/local/share/pynq-venv/lib/python3.8/site-packages (from pynq->qick==1.0.0) (1.14.5)\n", - "Requirement already satisfied: pycparser in /usr/lib/python3/dist-packages (from cffi->pynq->qick==1.0.0) (2.19)\n", - "Requirement already satisfied: python-dateutil>=2.7.3 in /usr/lib/python3/dist-packages (from pandas->pynq->qick==1.0.0) (2.7.3)\n", - "Requirement already satisfied: pytz>=2017.3 in /usr/lib/python3/dist-packages (from pandas->pynq->qick==1.0.0) (2019.3)\n", - "Installing collected packages: qick\n", - " Running setup.py develop for qick\n", - "Successfully installed qick\n", - "\u001b[33mWARNING: You are using pip version 21.2.1; however, version 22.0.4 is available.\n", - "You should consider upgrading via the '/usr/local/share/pynq-venv/bin/python3 -m pip install --upgrade pip' command.\u001b[0m\n" - ] - } - ], - "source": [ - "# Use the line below for an \"editable mode\" install.\n", - "# This installs a link telling Python to look for the library files in their current location.\n", - "# It is recommended if you expect to update the git repo, or you want to test changes to the QICK library, \n", - "# and don't want to reinstall the library every time.\n", - "\n", - "!pip3 install -e ../\n", - "\n", - "# If your board doesn't have Internet access, you may need to add some extra options:\n", - "\n", - "# !pip3 install --no-index --no-build-isolation -e ../\n", - "\n", - "# Use the line below instead for a normal pip install, which copies the library files to a central location.\n", - "# In contrast to an editable install, you will need to re-install whenever you modify or update the qick library;\n", - "# a normal install is somewhat slower for the initial install and infinitely slower for updates.\n", - "# This is only recommended if for some reason you want to delete the git repo after installing,\n", - "# or the git repo is on a temporarily available filesystem (e.g. flash drive).\n", - "\n", - "# !pip3 install ../\n" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "Let's see that the package is installed." - ] - }, - { - "cell_type": "code", - "execution_count": 3, - "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "Name: qick\r\n", - "Version: 1.0.0\r\n", - "Summary: Quantum Instrumentation Controller Kit software library\r\n", - "Home-page: https://github.com/openquantumhardware/qick\r\n", - "Author: Open Quantum Hardware\r\n", - "Author-email: openquantumhardware@gmail.com\r\n", - "License: UNKNOWN\r\n", - "Location: /home/xilinx/jupyter_notebooks/qick/qick_lib\r\n", - "Requires: numpy, tqdm, pynq\r\n", - "Required-by: \r\n" - ] - } - ], - "source": [ - "!pip3 show qick" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "Now you need to restart the Jupyter kernel so it picks up the newly installed library: click the Kernel menu, then Restart." - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "#### How to uninstall" - ] - }, - { - "cell_type": "code", - "execution_count": 4, - "metadata": {}, - "outputs": [], - "source": [ - "# !pip3 uninstall -y qick" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### Using the qick library without installing it (alternative)\n", - "\n", - "If for whatever reason you don't want to install the library (maybe you don't want to risk changing the Python environment for other code that you run on the board?), you can tell Python the path to the library.\n", - "\n", - "You would need to take the two lines below and copy them into the beginning of every notebook." - ] - }, - { - "cell_type": "code", - "execution_count": 5, - "metadata": {}, - "outputs": [], - "source": [ - "# import sys\n", - "# sys.path.append('../qick_lib/')" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### Testing the qick library and programming the FPGA" - ] - }, - { - "cell_type": "code", - "execution_count": 1, - "metadata": {}, - "outputs": [ - { - "data": { - "application/javascript": [ - "\n", - "try {\n", - "require(['notebook/js/codecell'], function(codecell) {\n", - " codecell.CodeCell.options_default.highlight_modes[\n", - " 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n", - " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", - " Jupyter.notebook.get_cells().map(function(cell){\n", - " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", - " });\n", - "});\n", - "} catch (e) {};\n" - ] - }, - "metadata": {}, - "output_type": "display_data" - }, - { - "data": { - "application/javascript": [ - "\n", - "try {\n", - "require(['notebook/js/codecell'], function(codecell) {\n", - " codecell.CodeCell.options_default.highlight_modes[\n", - " 'magic_text/x-csrc'] = {'reg':[/^%%pybind11/]};\n", - " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", - " Jupyter.notebook.get_cells().map(function(cell){\n", - " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", - " });\n", - "});\n", - "} catch (e) {};\n" - ] - }, - "metadata": {}, - "output_type": "display_data" - }, - { - "name": "stdout", - "output_type": "stream", - "text": [ - "Help on package qick:\n", - "\n", - "NAME\n", - " qick\n", - "\n", - "PACKAGE CONTENTS\n", - " averager_program\n", - " envelop_pulse\n", - " helpers\n", - " parser\n", - " qick\n", - " qick_asm\n", - " rfboard\n", - " streamer\n", - "\n", - "FUNCTIONS\n", - " bitfile_path()\n", - "\n", - "FILE\n", - " /home/xilinx/jupyter_notebooks/qick/qick_lib/qick/__init__.py\n", - "\n", - "\n" - ] - } - ], - "source": [ - "import qick\n", - "help(qick)" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "Normally we import all the Python classes defined by the package - you will see this initialization at the beginning of all the demo notebooks." - ] - }, - { - "cell_type": "code", - "execution_count": 2, - "metadata": {}, - "outputs": [], - "source": [ - "from qick import *" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "Initializing the QickSoc class programs the FPGA.\n", - "Printing the class gives a description of the generator and readout channels in the programmed firmware. You're ready to run the other demo notebooks." - ] - }, - { - "cell_type": "code", - "execution_count": 3, - "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "\n", - "QICK configuration:\n", - "\n", - "\tBoard: ZCU216\n", - "\n", - "\tGlobal clocks (MHz): tProcessor 430.080, RF reference 245.760\n", - "\n", - "\t7 signal generator channels:\n", - "\t0:\taxis_signal_gen_v4 - tProc output 1, switch ch 0, maxlen 65536\n", - "\t\tDAC tile 2, ch 0, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\t1:\taxis_signal_gen_v4 - tProc output 2, switch ch 1, maxlen 65536\n", - "\t\tDAC tile 2, ch 1, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\t2:\taxis_signal_gen_v4 - tProc output 3, switch ch 2, maxlen 65536\n", - "\t\tDAC tile 2, ch 2, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\t3:\taxis_signal_gen_v4 - tProc output 4, switch ch 3, maxlen 65536\n", - "\t\tDAC tile 2, ch 3, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\t4:\taxis_signal_gen_v4 - tProc output 5, switch ch 4, maxlen 65536\n", - "\t\tDAC tile 3, ch 0, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\t5:\taxis_signal_gen_v4 - tProc output 6, switch ch 5, maxlen 65536\n", - "\t\tDAC tile 3, ch 1, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\t6:\taxis_signal_gen_v4 - tProc output 7, switch ch 6, maxlen 65536\n", - "\t\tDAC tile 3, ch 2, 32-bit DDS, fabric=430.080 MHz, fs=6881.280 MHz\n", - "\n", - "\t2 readout channels:\n", - "\t0:\tADC tile 2, ch 0, 32-bit DDS, fabric=307.200 MHz, fs=2457.600 MHz\n", - "\t\tmaxlen 16384 (avg) 1024 (decimated), trigger 14, tProc input 0\n", - "\t1:\tADC tile 2, ch 2, 32-bit DDS, fabric=307.200 MHz, fs=2457.600 MHz\n", - "\t\tmaxlen 16384 (avg) 1024 (decimated), trigger 15, tProc input 1\n", - "\n", - "\ttProc: 1048576 words program memory, 4096 words data memory\n", - "\t\tprogram RAM: 65536 bytes\n" - ] - } - ], - "source": [ - "soc = QickSoc()\n", - "print(soc)" - ] - } - ], - "metadata": { - "kernelspec": { - "display_name": "Python 3", - "language": "python", - "name": "python3" - }, - "language_info": { - "codemirror_mode": { - "name": "ipython", - "version": 3 - }, - "file_extension": ".py", - "mimetype": "text/x-python", - "name": "python", - "nbconvert_exporter": "python", - "pygments_lexer": "ipython3", - "version": "3.8.2" - } - }, - "nbformat": 4, - "nbformat_minor": 2 -} diff --git a/qick/qick_demos/00_Send_receive_pulse.ipynb b/qick/qick_demos/00_Send_receive_pulse.ipynb deleted file mode 100644 index 1fc36c2..0000000 --- a/qick/qick_demos/00_Send_receive_pulse.ipynb +++ /dev/null @@ -1,1138 +0,0 @@ -{ - "cells": [ - { - "cell_type": "code", - "execution_count": 1, - "metadata": {}, - "outputs": [ - { - "data": { - "application/javascript": [ - "\n", - "try {\n", - "require(['notebook/js/codecell'], function(codecell) {\n", - " codecell.CodeCell.options_default.highlight_modes[\n", - " 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n", - " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", - " Jupyter.notebook.get_cells().map(function(cell){\n", - " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", - " });\n", - "});\n", - "} catch (e) {};\n" - ] - }, - "metadata": {}, - "output_type": "display_data" - }, - { - "data": { - "application/javascript": [ - "\n", - "try {\n", - "require(['notebook/js/codecell'], function(codecell) {\n", - " codecell.CodeCell.options_default.highlight_modes[\n", - " 'magic_text/x-csrc'] = {'reg':[/^%%pybind11/]};\n", - " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", - " Jupyter.notebook.get_cells().map(function(cell){\n", - " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", - " });\n", - "});\n", - "} catch (e) {};\n" - ] - }, - "metadata": {}, - "output_type": "display_data" - }, - { - "name": "stdout", - "output_type": "stream", - "text": [ - "Populating the interactive namespace from numpy and matplotlib\n" - ] - } - ], - "source": [ - "# Import the QICK drivers and auxiliary libraries\n", - "from qick import *\n", - "%pylab inline" - ] - }, - { - "cell_type": "code", - "execution_count": 2, - "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "\n", - "QICK configuration:\n", - "\n", - "\tBoard: ZCU111\n", - "\n", - "\tGlobal clocks (MHz): tProcessor 384.000, RF reference 204.800\n", - "\n", - "\t7 signal generator channels:\n", - "\t0:\taxis_signal_gen_v4 - tProc output 1, switch ch 0, maxlen 65536\n", - "\t\tDAC tile 0, ch 0, 32-bit DDS, fabric=384.000 MHz, fs=6144.000 MHz\n", - "\t1:\taxis_signal_gen_v4 - tProc output 2, switch ch 1, maxlen 65536\n", - "\t\tDAC tile 0, ch 1, 32-bit DDS, fabric=384.000 MHz, fs=6144.000 MHz\n", - "\t2:\taxis_signal_gen_v4 - tProc output 3, switch ch 2, maxlen 65536\n", - "\t\tDAC tile 0, ch 2, 32-bit DDS, fabric=384.000 MHz, fs=6144.000 MHz\n", - "\t3:\taxis_signal_gen_v4 - tProc output 4, switch ch 3, maxlen 65536\n", - "\t\tDAC tile 1, ch 0, 32-bit DDS, fabric=384.000 MHz, fs=6144.000 MHz\n", - "\t4:\taxis_signal_gen_v4 - tProc output 5, switch ch 4, maxlen 65536\n", - "\t\tDAC tile 1, ch 1, 32-bit DDS, fabric=384.000 MHz, fs=6144.000 MHz\n", - "\t5:\taxis_signal_gen_v4 - tProc output 6, switch ch 5, maxlen 65536\n", - "\t\tDAC tile 1, ch 2, 32-bit DDS, fabric=384.000 MHz, fs=6144.000 MHz\n", - "\t6:\taxis_signal_gen_v4 - tProc output 7, switch ch 6, maxlen 65536\n", - "\t\tDAC tile 1, ch 3, 32-bit DDS, fabric=384.000 MHz, fs=6144.000 MHz\n", - "\n", - "\t2 readout channels:\n", - "\t0:\tADC tile 0, ch 0, 32-bit DDS, fabric=384.000 MHz, fs=3072.000 MHz\n", - "\t\tmaxlen 16384 (avg) 1024 (decimated), trigger bit 14, tProc input 0\n", - "\t1:\tADC tile 0, ch 1, 32-bit DDS, fabric=384.000 MHz, fs=3072.000 MHz\n", - "\t\tmaxlen 16384 (avg) 1024 (decimated), trigger bit 15, tProc input 1\n", - "\n", - "\t7 DACs:\n", - "\t\tDAC tile 0, ch 0 is DAC228_T0_CH0 or RF board output 0\n", - "\t\tDAC tile 0, ch 1 is DAC228_T0_CH1 or RF board output 1\n", - "\t\tDAC tile 0, ch 2 is DAC228_T0_CH2 or RF board output 2\n", - "\t\tDAC tile 1, ch 0 is DAC229_T1_CH0 or RF board output 4\n", - "\t\tDAC tile 1, ch 1 is DAC229_T1_CH1 or RF board output 5\n", - "\t\tDAC tile 1, ch 2 is DAC229_T1_CH2 or RF board output 6\n", - "\t\tDAC tile 1, ch 3 is DAC229_T1_CH3 or RF board output 7\n", - "\n", - "\t2 ADCs:\n", - "\t\tADC tile 0, ch 0 is ADC224_T0_CH0 or RF board AC input 0\n", - "\t\tADC tile 0, ch 1 is ADC224_T0_CH1 or RF board AC input 1\n", - "\n", - "\t4 digital output pins:\n", - "\t0:\tPMOD0_0_LS\n", - "\t1:\tPMOD0_1_LS\n", - "\t2:\tPMOD0_2_LS\n", - "\t3:\tPMOD0_3_LS\n", - "\n", - "\ttProc: 8192 words program memory, 4096 words data memory\n", - "\t\texternal start pin: None\n" - ] - } - ], - "source": [ - "# Load bitstream with custom overlay\n", - "soc = QickSoc()\n", - "# Since we're running locally on the QICK, we don't need a separate QickConfig object.\n", - "# If running remotely, you could generate a QickConfig from the QickSoc:\n", - "# soccfg = QickConfig(soc.get_cfg())\n", - "# or save the config to file, and load it later:\n", - "# with open(\"qick_config.json\", \"w\") as f:\n", - "# f.write(soc.dump_cfg())\n", - "# soccfg = QickConfig(\"qick_config.json\")\n", - "soccfg = soc\n", - "print(soccfg)" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### Hardware Configuration\n", - "\n", - "generator channel 6 : DAC 229 CH3 <-> Readout channel 0 : ADC 224 CH0" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "## Things to know when writing programs\n", - "\n", - "### How to avoid timing problems\n", - "Timed instructions are executed in two steps: first when the control core of the tProcessor pushes the instruction into the timed queue, and second when the instruction pops off the timed queue.\n", - "* The control core executes all instructions in order and (except wait/waiti) as quickly as possible. If you have a non-timed instruction with external effects, it will generally execute before the timed instructions before and after it. Specifically, programs typically use memwi to update a data counter, and then read that counter to know how many data samples to get from the buffers - if the memwi happens before the readout is triggered or completed, you will read invalid data.\n", - "* If the instruction is pushed later than the specified time, it will execute later than specified - this can lead to variations in the relative timing of pulses and readout windows. You are responsible for keeping the control core running ahead of the instruction times.\n", - "\n", - "Things you should do in your programs:\n", - "* Your initialization should contain a synci instruction which gives the tProcessor time to get ahead of the clock.\n", - "* Put a `sync_all()` somewhere in your loop body, probably at the end. This ensures that you don't have pulses or readouts that exceed the loop length.\n", - "* Put a waiti instruction after the last readout in your loop body, to make sure the tProcessor doesn't prematurely update the data counter.\n", - "* Follow the waiti with a sync that exceeds the waiti, to allow the tProcessor to get ahead of the clock.\n", - "\n", - "The last three points are automatically addressed if the last timed instruction in your loop body is a `measure()` instruction that specifies `wait=True` and a nonzero `syncdelay`.\n", - "\n", - "### How to ensure frequency matching\n", - "DACs and ADCs have different frequency units, and the frequencies used in the two systems must be exactly equal. If they are not, there will be a small difference between the upconversion and downconversion frequencies - this will manifest as a sliding phase, and so you will not see a consistent phase between acquisitions.\n", - "\n", - "There are two ways to ensure frequency matching:\n", - "* When converting a frequency to an integer value (often with `freq2reg()` or `declare_readout()`), specify not only the channel you are configuring, but the channel you want to be frequency-matched to.\n", - "* Before doing any conversion, round the frequency to the closest frequency that is valid on both channels using `soccfg.adcfreq(f, gen_ch, ro_ch)`.\n", - "\n", - "Frequency-matching makes your frequency resolution worse, since the smallest possible frequency step is now the LCM of the two channels' frequency steps. Usually this doesn't matter - O(10 Hz) resolution is ample for most applications - but you can disable frequency-matching by specifying None as the other channel.\n", - "\n", - "You may have a DAC channel that does not itself drive any ADC channels, but needs to be phase-locked to a DAC channel that does. In this case you will want to frequency-match both DAC channels to that ADC, otherwise you will have a sliding phase between the two DAC channels.\n", - "\n", - "Since all DAC and ADC channels are the same in the standard QICK firmware, it's OK to just use ch 0 for the matched channel. But it's a good habit to do this consistently correctly, and that is the approach here.\n", - "\n", - "### Clocks and durations\n", - "Time durations are generally specified in units of clock cycles. The relevant clocks are the tProcessor clock and the fabric clocks of the DACs and ADCs. In general these can all be different (and can even vary among DACs), though the standard ZCU111 firmware uses the same clock in all three places.\n", - "\n", - "For convenience, the `us2cycles()` and `cycles2us()` methods will convert between floating-point times and integer cycles. You should be careful to specify which clock you are using, and set the appropriate parameter in `us2cycles()`:\n", - "* Pulse parameters (the `length` parameter to `set_pulse_registers()`, the `length` and `sigma` parameters to `add_gauss`) use the DAC clock and you should specify `gen_ch`.\n", - "* Readout parameters (the `length` parameter to `declare_readout()`) use the ADC clock and you should specify `ro_ch`.\n", - "* All other values will use the tProc clock. This includes sync and wait commands, and any sort of delay (`t`, `adc_trig_offset`). No special parameter needed.\n", - "\n", - "### How to play pulses\n", - "There are three steps to playing a pulse:\n", - "\n", - "#### Loading a waveform\n", - "(You skip this step for rectangular \"const\" pulses, which have no envelope.)\n", - "\n", - "Each signal generator has an internal waveform memory, which stores the I/Q data for the pulse envelope. Multiple waveforms can be stored in the same signal generator, and a single waveform can be used for different pulses (e.g. a Gaussian waveform can be used for Gaussian pulses and the ramp-up/ramp-down of flat-top pulses with different flat-top duration, each with its own gain and carrier frequency).\n", - "\n", - "`add_pulse(ch, name, idata, qdata)` writes an arbitrary waveform to the specified channel's waveform memory. \n", - "`add_gauss(ch, name, length, sigma)`, `add_triangle(ch, name, length)`, and `add_DRAG(ch, name, length, sigma, delta, alpha)` write commonly-used standard pulse waveforms, with duration units of fabric clock cycles. The name is used in the next step.\n", - "\n", - "#### Setting registers\n", - "There are a lot of parameters that need to be specified when playing a pulse - more than can be specified inline in a tProcessor instruction. So all the parameters must be written to registers first, and when we fire the pulse we just tell the tProcessor which registers to read.\n", - "\n", - "`set_pulse_registers()` writes the settings for a pulse to registers. All arguments to this method must be integers in the native units of the signal generator. This can happen immediately before you fire the pulse, but if a signal generator is only used for one type of pulse you will save time for the tProcessor by setting registers in initialization, before the program loop.\n", - "\n", - "If you want to modify pulse parameters on the fly (for example, you might want to sweep the frequency of the qubit drive pulse), you will set the registers in two steps (you can see an example in the demo 02_Sweeping_variables):\n", - "* First, use set_pulse_registers() to write initial values for all parameters. You could do this in initialization, or right before the following step.\n", - "* Second, overwrite the register(s) you want to update. You need to get the page and address of the register using ch_page(ch) and sreg(ch, name). Then you can use assembly instructions to change the value of that register.\n", - "\n", - "#### Firing the pulse\n", - "`pulse(ch, t)` fires a pulse on the specified channel at the specified time, using whatever values are loaded in the registers.\n", - "\n", - "Often you will want to trigger the readout at the same time: `measure()` is a wrapper around `trigger()` and `pulse()`, and that's what is used in this demo." - ] - }, - { - "cell_type": "code", - "execution_count": 3, - "metadata": {}, - "outputs": [], - "source": [ - "class LoopbackProgram(AveragerProgram):\n", - " def initialize(self):\n", - " cfg=self.cfg \n", - " res_ch = cfg[\"res_ch\"]\n", - "\n", - " # set the nyquist zone\n", - " self.declare_gen(ch=cfg[\"res_ch\"], nqz=1)\n", - " \n", - " # configure the readout lengths and downconversion frequencies (ensuring it is an available DAC frequency)\n", - " for ch in cfg[\"ro_chs\"]:\n", - " self.declare_readout(ch=ch, length=self.cfg[\"readout_length\"],\n", - " freq=self.cfg[\"pulse_freq\"], gen_ch=cfg[\"res_ch\"])\n", - "\n", - " # convert frequency to DAC frequency (ensuring it is an available ADC frequency)\n", - " freq = self.freq2reg(cfg[\"pulse_freq\"],gen_ch=res_ch, ro_ch=cfg[\"ro_chs\"][0])\n", - " phase = self.deg2reg(cfg[\"res_phase\"], gen_ch=res_ch)\n", - " gain = cfg[\"pulse_gain\"]\n", - " self.default_pulse_registers(ch=res_ch, freq=freq, phase=phase, gain=gain)\n", - "\n", - " style=self.cfg[\"pulse_style\"]\n", - "\n", - " if style in [\"flat_top\",\"arb\"]:\n", - " sigma = cfg[\"sigma\"]\n", - " self.add_gauss(ch=res_ch, name=\"measure\", sigma=sigma, length=sigma*5)\n", - " \n", - " if style == \"const\":\n", - " self.set_pulse_registers(ch=res_ch, style=style, length=cfg[\"length\"])\n", - " elif style == \"flat_top\":\n", - " # The first half of the waveform ramps up the pulse, the second half ramps down the pulse\n", - " self.set_pulse_registers(ch=res_ch, style=style, waveform=\"measure\", length=cfg[\"length\"])\n", - " elif style == \"arb\":\n", - " self.set_pulse_registers(ch=res_ch, style=style, waveform=\"measure\")\n", - " \n", - " self.synci(200) # give processor some time to configure pulses\n", - " \n", - " def body(self):\n", - " # fire the pulse\n", - " # trigger all declared ADCs\n", - " # pulse PMOD0_0 for a scope trigger\n", - " # pause the tProc until readout is done\n", - " # increment the time counter to give some time before the next measurement\n", - " # (the syncdelay also lets the tProc get back ahead of the clock)\n", - " self.measure(pulse_ch=self.cfg[\"res_ch\"], \n", - " adcs=self.ro_chs,\n", - " pins=[0], \n", - " adc_trig_offset=self.cfg[\"adc_trig_offset\"],\n", - " wait=True,\n", - " syncdelay=self.us2cycles(self.cfg[\"relax_delay\"]))\n", - " \n", - " # equivalent to the following:\n", - "# self.trigger(adcs=self.ro_chs,\n", - "# pins=[0], \n", - "# adc_trig_offset=self.cfg[\"adc_trig_offset\"])\n", - "# self.pulse(ch=self.cfg[\"res_ch\"])\n", - "# self.wait_all()\n", - "# self.sync_all(self.us2cycles(self.cfg[\"relax_delay\"]))" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### Send/receive a pulse with pulse_style = const " - ] - }, - { - "cell_type": "code", - "execution_count": 4, - "metadata": {}, - "outputs": [ - { - "data": { - "application/vnd.jupyter.widget-view+json": { - "model_id": "1d55be1a95aa40bc827a9d3ac264c87d", - "version_major": 2, - "version_minor": 0 - }, - "text/plain": [ - " 0%| | 0/100 [00:00" - ] - }, - "metadata": { - "needs_background": "light" - }, - "output_type": "display_data" - } - ], - "source": [ - "# Plot results.\n", - "plt.figure(1)\n", - "for ii, iq in enumerate(iq_list):\n", - " plt.plot(iq[0], label=\"I value, ADC %d\"%(config['ro_chs'][ii]))\n", - " plt.plot(iq[1], label=\"Q value, ADC %d\"%(config['ro_chs'][ii]))\n", - " plt.plot(np.abs(iq[0]+1j*iq[1]), label=\"mag, ADC %d\"%(config['ro_chs'][ii]))\n", - "plt.ylabel(\"a.u.\")\n", - "plt.xlabel(\"Clock ticks\")\n", - "plt.title(\"Averages = \" + str(config[\"soft_avgs\"]))\n", - "plt.legend()\n", - "plt.savefig(\"images/Send_recieve_pulse_const.pdf\", dpi=350)" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### Rep-to-rep consistency\n", - "In this notebook we mostly use decimated readout (we acquire a full waveform, not just a single accumulated value). To avoid exhausting the waveform buffer, we usually run with reps=1 (the tProcessor program only fires+reads one pulse, and we run the program `soft_avgs` times).\n", - "\n", - "However, it's important to check that if you run a tProcessor loop with reps>1, the pulse looks the same in each iteration of the loop. So let's do a decimated readout with multiple reps; the 1024-sample buffer will allow for 10 reps of 100 samples each.\n", - "\n", - "Try changing the relax_delay to 0. You will see that the first rep appears in the same place, but the others are delayed by a bit because the tProcessor didn't have enough time between waiting for the measurement in one rep and firing the pulse in the next rep." - ] - }, - { - "cell_type": "code", - "execution_count": 6, - "metadata": {}, - "outputs": [ - { - "data": { - "application/vnd.jupyter.widget-view+json": { - "model_id": "0950f116db4649cd8c6a3fe19bf6f8e0", - "version_major": 2, - "version_minor": 0 - }, - "text/plain": [ - " 0%| | 0/100 [00:00" - ] - }, - "execution_count": 6, - "metadata": {}, - "output_type": "execute_result" - }, - { - "data": { - "image/png": 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LkkIPJAJeUogilO1shKHwt2cfY94hnwfgib8u4U8zDmWUvs/RyWe4f9C5XPer2/nepV/i1z//P/zy0HNxMhm+uWML3zi/pSVwMprJkHznHZwRIwj61z23N65iHHMPHsen/OfvvPcKJUVljBpxOG46zZV3/JE/TzyUH02bxKrH/ov5m9OcdvZlfPfFpVQNO4rF6+/lL+OPY9Wo4QC4zc2sGzSEg3Udh82/gKGNS1mxw7ufcFdjbdaOoTGm+z73uc/x4IMPMmLECFavXt0r72lVUnsgGfS6iSKBEOMSIYKaYn3Iu2jq9XWr+H16PduCIzl74yrOTIxljG7iL4dMYumfb+PWQxbg4nB1TQPfOP/U3d5XAgEikybtNSF05KADZzFqxEEAOMEgN33+U9zSCJOaq1lavpBrJ5/EF1+8j0eHzuWo5hf40imLmFH/NmvCk1j31ms8/OclVDmjObj+fUSCHHD8qZSnvRvzNu/Y2huHyxjTRk9LZwN85jOf4ZFHHumFaD5gSaEHUn5SKA0XMeXw46lkEy8Nn8QX77uVe167ncfKFzCzYS3f+czVnLTwi5y14Vl2BIfyH4OnsE1G8sU3X+HiTy7MWnxnnnEUyz56Kv/n3TVMbtzI00VHU671fEkDjD3gUKZvqsWVEHc8s4znm3agEmBSrZfUJFKEujEAGpoasxajMbky0EtnAxx77LEMGTKkF4+KdR/1SMrxcmpZcQVT5x7DR/7+TR4r+ShLhx0NHI2TSfH1A49q3f6K877F8/9ewgvRI1i04Qm+eenXsx5jUTTMfy6+gG9kMtxzx82EIkFOucgbQ7jo5LO5s2obr40aRWk8RUiTfPKEi1tfq2nvTCaRiGU9TlPgHr4Ktr62/+26YtRhcOq+ZyMbyKWzs8WSQg8k/aQwZNhIQuEwE16LsrjiPrRxEnUlk6iYcTinzvxg0DlaWsL/TY3kubeWc+kXLu3TWAOBABcu/o/dlh14yKEc9sazvFQ+hSGhnRyU2sCB445sXe/490Mk7V4Fk6cGcunsbLGk0AOpYBCAA0Z4E12MKzqI5m0TOOmiU6k4pOMJd+adcTrzOL3Ddbkwc1M9z0wv5n0p5vCdT++2LuSXxUr2/5vLzUC3nzP6bBnIpbOzxcYUesD1xxRGjBwJwGlf/RznXvuFvSaE/uiUOR8monEAJu3c/RzBSXu/9Cmbf9oUsP5aOjtbLCn0QNJvKQwrKwVAnAAS7Jts3luOPGoWs2reJ5JJ8tGjF+y2zhHv1yM1sHbJmF7VX0tnA1xwwQV86EMfYu3atVRWVnL77R2Wl+sS6z7qgZQTxNEUISeY61C6TUT40Ns1HFK7lsNvuGq3dSF/mou0nTqYPDR+/Pjdru1v2wpou+5DH/oQb731Vuu67373uwBEo1Huvvvu3UpnH3jggdTX1zNp0qTd5k9u8cQTT+z2fNiwYfzxj3/sML5DDjmE2267bZ/7cM89vV/N2JJCDyQDQcIkcx1Gj11x5WISbmaPPsuweMnODVhTwZj2mpubOe6440ilUqhqa+nscDhspbMLlRsIEtaBnxScYAAnuGdzIOJ45TgsKRizJyudbfaQDDqESeU6jKwp9mdes6RgTOGwpNADKQkS0vxNCkVFXhG9dMB+TYwpFPbX3gOpgEM4k79JoaJsEACuJQVjCob9tfdAUkKENH/v9h06yLu8zloKxhQO+2vvgZQ4hPO4BERFhTeTj7UUjOl/Nm3axHHHHceUKVOYNm0at9xyS6+8b9b+2kXkNyKyXURWt1n2XyLypoi8KiIPiMigNuuuFpG3RWStiJycrbh6U0rChPI5KQwdiqNJ3ODAvQ/DmP6qp6WzHcfhxz/+MWvWrOG5557jZz/72W51lLorm6eAdwKntFv2GDBdVWcAbwFXA4jIVOB8YJr/mltFpF9/E8UTca/7KI+TQklpOQ5p0n1Uc8WYvjTQS2ePHj2aww8/HPAuj50yZQqbN2/u8XHJ2n0KqvqkiIxvt+zRNk+fA871Hy8ElqhqAlgvIm8DRwLPZiu+nqqrrSZJmHA6f4vFBYpKcEjhBvp1fjZ54MYVN/Lmzjd79T0nD5nMN4/85j63yZfS2Rs2bODll19m3rx5XThCHcvlzWufA1ru7x6DlyRaVPnL9iAilwCXAIwbNy6b8e1T/dYqUoRxMvmbFMRxCKlLWmxMweSnfCid3djYyDnnnMPNN99MeXl51w9COzlJCiLyLcAFft+yqIPNOizNqaq3AbcBzJkzJ2flOxuqq0gExhN28zcpAARJW0vBZN3+zuizZaCXzk6lUpxzzjlceOGFnH322d2Kp70+PwUUkUXA6cCF+sFRrQLaVo+qBN7v69i6YueObaQlRCidyXUoWeWoi9u/h3eMyar+WjpbVVm8eDFTpkzhP/5j9wm0eqJPk4KInAJ8EzhDVZvbrFoGnC8iERGZAEwC9n9Ec6iu0WvihfJ4TAHA0bRdkmoKWn8tnf3000/zu9/9jn/84x/MmjWLWbNm8dBDD/V4f7PWfSQi9wALgGEiUgVci3e1UQR4zG8KPaeqX1LV10XkXuANvG6ly1T793RfjUmvEF4ond8T0HhXH1ndRJN/Bnrp7Pnz53e7C2tfsnn10QUdLN7rDBCq+n3g+9mKp7fF/fIW4XxPCpq27iNjOmCls81uEv7PUH4PKeBkXLt5zZgOWOlss5tkwGshRPP8EAY1g2vdR8YUjPz+RsuipD8pTSQQznEk2eV1H1lSMKZQWFLoplTQu2a4JFqc40iyK6gZXKz7yJhCYUmhm1KOd+jKigbtZ8uBzclY95ExhcSSQje1JIWKIcNyHEl2hTRN2q5HMKbficfjHHnkkcycOZNp06Zx7bXX9sr72l97N7WMKQwaPCLHkWRXMKOk7NfEmF7nui6O0/2/rUgkwj/+8Q9KS0tJpVLMnz+fU089laOOOqpHcVlLoZtcPykMr+h5Aar+zMlkcAmRdhP739iYAWSgl84WEUpLSwGvBlIqleqwPlJX2SlgN6Ucb/B1xODSHEeSXU4mjYtDOtZAsCyy/xcY0w1bf/ADEmt6t3R2ZMpkRl1zzT63Geils9PpNEcccQRvv/02l1122YAvnT2gpfzKoUNLozmOJLuCacWVELH6WsJl+T1+YgrPQC+dHQwGeeWVV6itreWss85i9erVTJ8+vXsHw2dJoZuSwSCOpnDyvFico94t23WN9VTkOBaTv/Z3Rp8tA710dotBgwaxYMECHnnkkR4nhfz+RsuiVCBIiFSuw8g6xy8NXtuwK8eRGJMb/bV0dnV1NbW1tQDEYjEef/xxJk+e3PUdbMeSQjelAg5hTeY6jKwL+gX/djXU5jgSY3Kjv5bO3rJlC8cddxwzZsxg7ty5nHjiiZx++uk93l/rPuqmVCBIWN1ch5F1TqalpVCX40iM6V0DvXT2jBkzePnll/e7n11lSaGbUhIinMn/7qOWlkJTrCnHkRjTv1jpbLOblDiEMoXQUvCSQjwRz3EkxvQvVjrbtEq5KZKBcEG0FBy/pRBL5/++GmMsKXRLQ3MDKRxCmX49Y2ivcPxJhJJ5Phe1McaTtaQgIr8Rke0isrrNsiEi8piIrPN/Dm6z7moReVtE1orIydmKqzfUNewkJWHChdB95N+nkCTPp5gzxgDZbSncCZzSbtlVwHJVnQQs958jIlOB84Fp/mtuFem/EwM3bttGkjChAjh7DmW8G2ZSlhSMKQhZSwqq+iSws93ihcBd/uO7gDPbLF+iqglVXQ+8DRyZrdh6qql2S+EkBf8uSrcXCm0ZY3pfOp1m9uzZvXKPAvT9mMJIVd0C4P9sqTs9BtjUZrsqf9keROQSEVkpIiurq6uzGuzexOu3kyRSGEnBn3XNDVpSMKY3tZTR6KlbbrmFKVOm9Mp7Qf8ZaO7oG6fDwiKqepuqzlHVOcOHD89yWB1LNNT6LYX871KJBL2kkLaWgskzA710NkBVVRV/+9vf+PznP99rx6Wv71PYJiKjVXWLiIwGtvvLq4C2t/9VAu/3cWyd1tzUhCshwm7+txQiIa9AmLUUTDb9+9632LGpsVffc9jYUj583iH73Gagl87++te/zo9+9KPWyqq9oa+TwjJgEXCD/3Npm+V/EJGbgAOAScD+q0nlSHPaq3nkFEBLoTjiVW9M53k1WFOYBnLp7AcffJARI0ZwxBFH7FE+oyeylhRE5B5gATBMRKqAa/GSwb0ishjYCHwCQFVfF5F7gTcAF7hMVfvtaXjMv0wznO5e6dyBpLTYK/PrBqylYLJnf2f02TKQS2c//fTTLFu2jIceeoh4PE59fT0XXXQRd999d7fiapHNq48uUNXRqhpS1UpVvV1Va1T1BFWd5P/c2Wb776vqQap6qKo+nK24ekPCH+4IZfL/7Lm8zJtu1A302yuEjcmq/lo6+4c//CFVVVVs2LCBJUuWcPzxx/c4IUD/GWgeUFJ+/3pU8v/wDSn3phu17iNTqPpr6exssYJ43ZD0k0JE8n/O4vKKcoglcS0pmDwz0Etnt7VgwYLWbq2esqTQDa7jtxSie/YD5pvisjICW7ZbUjCmHSudbVql/Gv3i4tKcxxJ9kXLy3F437qPjGnHSmebVinHO2wlxeU5jiT7oiWlOLik+28pKmNML7Kk0A0tSaHlypx8FggGcdS1q4+MKRCWFLohFfQO26Cykv1smR8cXBtTMKZA2F96N7SMKQwtL85xJH3D0bR1HxlTIGyguRtazpqHDyrLcSR9w1EX15KCMf3O+PHjKSsrIxgM4jhOrwx8W1LohlTQO2xDS6I5jqRvBDVjScGYXua6Lo7T86/gf/7znwwbNqwXIvJY91E3pAJBgupSFCqMnGotBZOP8qF0djYUxrdaL0sFHMKaynUYfcaxloLJsn/eeRvb33u3V99zxIETOe4zl+xzm4FeOltEOOmkkxARvvjFL3LJJfve386wpNANKQkWWFJIkxT7VTH5ZyCXzgavUuoBBxzA9u3bOfHEE5k8eTLHHnts9w6Gz/7SuyEZCBEqsKTQTGGMn5jc2N8ZfbYM5NLZQGvLYcSIEZx11lmsWLGix0nBxhS6wZUQYe2d+VUHAieTIWXnD6ZA9dfS2U1NTa2tiqamJh599FGmT5/e9R1sx5JCF2UyGZISJpwpnJZCUDN2n4IpWP21dPa2bduYP38+M2fObN32lFNO6fH+2ulfFyXdJClChDKF01IIZdK4OKhqh01YYwaigV46e+LEiaxatWq/+9lVlhS6qDneRFLCFBVQUghmMl5SSCWQsI0tGANWOtv44rEmkoQoz8RyHUqf8cYUQqSa64lYUjAGsNLZvUpEviEir4vIahG5R0SiIjJERB4TkXX+z8G5iG1/mhtqSRHGyaT3v3Ge8FoKIZqbduU6FGNMlvV5UhCRMcDXgDmqOh0IAucDVwHLVXUSsNx/3u/EG3bi4hDKZHIdSp9xMoqLQ2PjzlyHYozJslxdfeQARSLiAMXA+8BC4C5//V3AmXt5bU4lGr2WQrCAWgpOJkNGgjTU1+Y6FGNMlvV5UlDVzcB/AxuBLUCdqj4KjFTVLf42W4ARHb1eRC4RkZUisrK6urqvwm6VbKolVWgthbS3rw1N9TmOxBiTbbnoPhqM1yqYABwAlIjIRZ19varepqpzVHXO8OHDsxXmXqWaG3AJtX5RFoJgxrtzs6GpMceRGGPaqq2t5dxzz2Xy5MlMmTKFZ599tsfvmYurjz4KrFfVagARuR84GtgmIqNVdYuIjAa25yC2/UrEm0lJmGC6gLqPWloKzU05jsSY/NEbpbMvv/xyTjnlFP70pz+RTCZpbm7ucVy5GFPYCBwlIsXi3Ql1ArAGWAYs8rdZBCzNQWz7FY97B93JdK/uyUDkpL19jSUL5zJck/8Geuns+vp6nnzySRYvXgxAOBxm0KBBPT4u3U5TIvKgqp7e1dep6vMi8ifgJcAFXgZuA0qBe0VkMV7i+ER3Y8um5pR305pTSGMKfgKMpRI5jsTkq9q/vkPy/d5tiYYPKGHQxw/a5zYDuXT2u+++y/Dhw/nsZz/LqlWrOOKII7jlllt2K7jXHT1pu3yhuy9U1WuBa9stTuC1Gvq1uH/VUSG1FFrGFBIF1GVmCsNALp3tuobW5FkAAB+6SURBVC4vvfQSP/nJT5g3bx6XX345N9xwQ2sZju7qdlJouVKo0CTVayEUUlIItSQFLZzWkelb+zujz5aBXDq7srKSyspK5s2bB8C5557LDTfc0K2Y2urUmIKIrBeRd9v/6/GnD0AttVELKSk4fi5wLSmYAtRfS2ePGjWKsWPHto5xLF++nKlTp3Z9B9vpbEthTpvHUbz+/iE9/vQBqCUphAqo6rij3hlKKmAVUk3hufLKK1m0aBE33XQTxx9/fOvySy+9lEWLFjFjxgxmz57d7dLZl112GTNmzMB1XY499tjW8tkt5bA3btzYYelsgJ/85CdceOGFJJNJJk6cyB133NHj/e1UUlDVmnaLbhaRp4Dv9DiCASYV9L4YCyopiLevacsJJo8M9NLZALNmzer1onydSgoicnibpwG8lkNZr0YyQLgB7wsyEiicSWci/vzM1lIw5gOFXjr7x20eu8B64LzeD6f/c/1cEAmEcxtIH4oEQwCkA4XTOjJmf/K1dHZnu4+Oy3YgA4XrXwEQjRTOvAJRfw4F13KCMXmv23/m7bqUCkY66B2yoqKe3SAykBRHvcvlWvbdGJO/evJX/uVei2IAaRlTiEZLcxxJ3ykrLgbALaBxFGMKVadvXvOrm07CuyQV4HdZiaifc4PeF2NxD28lH0hK/X11xQaajcl3nb157fPAk8Dfgev9n9dlL6z+y/WvwCkvK5yLr0pKrfvImP5m7dq1zJo1q/VfeXk5N998c4/ft7MthcuBucBzqnqciEzGSw4Fp6ULpaK0gLqPSosh7rZ2nRljeq6npbMPPfTQ1jug0+k0Y8aM4ayzzupxXJ39K4+rahxARCKq+iZwaI8/fQBy/ZvXKkoL5+qjkjIvAaZtTMHkkYFeOrut5cuXc9BBB3HggQf2+Lh0Nk1Vicgg4C/AYyKyC29e5YLTcq1+RUnhJIVoaRmOVuOKtRRMdjz88MNs3bq1V99z1KhRnHrqqfvcZiCXzm5ryZIlXHDBBV04OnvX2fsUWtok14nIP4EK4JFeiWCAcQPeIasoKpykUFxaQpC03bxm8s5ALp3dIplMsmzZMn74wx92/QB0oMsdWqr6r1755AHKlQCOpoiEQ7kOpc+Ew2FC6tolqSZr9ndGny0DuXR2i4cffpjDDz+ckSNHdiue9uzUr4vcQBAHN9dh9KlAIICDiyuWFEzh6a+ls1vcc889vdZ1BJYUusyVII4WVlIACGqatI0pmAJ05ZVXcvXVV3PMMceQbjP74KWXXkp1dTUzZszgxhtv7Hbp7JUrVzJjxgymTp3aWjYbPiidfdRRR+21dHZzczOPPfYYZ599di/sqacn03F2mz9o/WtgOqDA54C1wB+B8cAG4DxV3ZWL+PYlHQgQKrCWAoCjLq7k5NfFmKzIh9LZxcXF1NS0n9mgZ3L1V34L8IiqnisiYaAYuAZYrqo3iMhVwFXAN3MU316lxMHRwpurOKRp6z4ypo1CL53da0SkHDgW+AyAqiaBpIgsBBb4m90FPEE/TAoF3X1kA83GtMrX0tm56CSeCFQDd4jIyyLyaxEpAUaq6hYA/+eIjl4sIpeIyEoRWVldXd13UfsKNSk41lIwpiDkIik4wOHAz1V1NtCE11XUKap6m6rOUdU5w4cPz1aMe+UWaPeRlxRsTMGYfJeLpFAFVKnq8/7zP+EliW0iMhrA/7k9B7Htl4tDqCCTQgYXaykYk+/6PCmo6lZgk4i01E46AXgDWAYs8pctApb2dWyd4YqDkynApJDJ4Erh3LBnTKHK1YXnXwV+LyKvArOAHwA3ACeKyDrgRP95v6KqflLI5DqUPudk0rg43b6L0xjT+/7nf/6HadOmMX36dC644ALi8XiP3zMnSUFVX/HHBWao6pmquktVa1T1BFWd5P/cmYvY9iWRTJDCKciB5qBmcHFIJ2K5DsWYvNBSRqO7Nm/e3Hrz2+rVq0mn0yxZsqTHcdktql3Q3FyPS6hAWwpeUmhq6He52phuyYfS2a7rEovFcF2X5ubmvVZR7Qq7nKQLYs31uBTwmAIOzY01VAyvzHU4Js+89dZ3aWhc06vvWVY6hUMO+fY+txnIpbPHjBnDFVdcwbhx4ygqKuKkk07ipJNO6ubR+oAlhS5ort9FqmBbCkqKEPHm2lyHYkyvGcils3ft2sXSpUtZv349gwYN4hOf+AR33303F110UfcPCJYUuiTRWEOKigJNChlcQsSa+/6GQZP/9ndGny0DuXT2448/zoQJE2i5X+vss8/mmWee6XFSsDGFLkg07PLGFNKF130UTHuXpDY39LsahcZkVX8tnT1u3Diee+45mpubUVWWL1/OlClTurWPbVlS6IKmhjrS4uBkCu+yTMf19rm+wbqPTGHpr6Wz582bx7nnnsvhhx/OYYcdRiaT4ZJLLunx/lr3URc0NTVDOTjpAuw+8v8WGpvrchuIMb0kH0pnX3/99Vx//fX73KarLCl0QXPSu0Y/WIhjCq7XqGxONOY4EmP6ByudbWhOeQNPhdhSCPkthbjb8zsmjckHVjrbkEj7SaEAxxRCae9XJV6As84ZU0gsKXRBQr0WQqgAk4LjJ4WUFN6+G1NILCl0getfJlyItUJL/FwQd6x8tjH5zJJCF6TwvhmdjOxny/xT7P+Mh2wYyph8ZkmhC9yAlwxCUniHrdjPBXGnENtJxvRPt9xyC9OnT2fatGncfPPNvfKehfft1gOpoHe4wsHCO1suLfaSQSJkScGY3tDT0tmrV6/mV7/6FStWrGDVqlU8+OCDrFu3rsdxWVLoAjfgHa5ooPC+GAcNLgMg7oRzHIkxvWOgl85es2YNRx11FMXFxTiOw0c+8hEeeOCBHh+Xwjvl7QHXL0hVHNmzeFW+Gzp0KLgQD1pSML3v2+uqWN3YuxM4TS8t4ruT9l3mfSCXzp4+fTrf+ta3qKmpoaioiIceeog5c+Z082h9wJJCF7h+91FRUWmOI+l7Q0aOIrqpmnjAkoLJHwO5dPaUKVP45je/yYknnkhpaSkzZ87EcXr+lZ6zpCAiQWAlsFlVTxeRIcAfgfHABuA8Ve1XJTnTflIoLa3IcSR9b8iwoRRtrCIejOx/Y2O6aH9n9NkykEtnAyxevJjFixcDcM0111BZ2fPjmMsxhcuBtlMtXQUsV9VJwHL/eb+S8scUysoLLykMrigjmk4QD0RzHYoxfaq/ls4G2L59OwAbN27k/vvv54ILLujaznUgJ0lBRCqBjwG/brN4IXCX//gu4Mz2r8u1dNDL1BXlhdd9FAgGKcokiUmUTAHOJ2EKV38tnQ1wzjnnMHXqVD7+8Y/zs5/9jMGDB/d4f3PVfXQzcCVQ1mbZSFXdAqCqW0RkREcvFJFLgEvAm2SiL7kB727eivKy/WyZn4rcFLFIMW5jLeGKobkOx5geyYfS2f/+97/3ub47+jwpiMjpwHZVfVFEFnT19ap6G3AbwJw5c/q0EE/LJakVZSX72TI/FaVT1FBK3c6NDLekYAqclc7uPccAZ4jIaUAUKBeRu4FtIjLabyWMBrbnILZ9ciWAaIayaGEOtkZTKZoppq5mE8MnzM51OMbklJXO7iWqerWqVqrqeOB84B+qehGwDFjkb7YIWNrXse2PGwzi4BIJF97NawBFKZcYRdTuej/XoZg80d0reEzndOf49qc7mm8AThSRdcCJ/vN+xZUAIVIdXhpWCKKpNCmJUFu/I9ehmDwQjUapqamxxJAlqkpNTQ3RaNeuGMzpzWuq+gTwhP+4Bjghl/HsTzoQxNHCnWQmmvT2fWesd+88NYWpsrKSqqoqqqurcx1K3opGo12+d8HuaO6ClHjdR4WqKOVdjlfnpnIcickHoVCICRMm5DoM005/6j7q99ISxNHCvUY/mvJmnmsswJnnjCkUlhS6wJUgoQLuPirOeL8uzcHCHFMxphBYUuiClDgF3VIo9+sexYM2Jacx+cqSQhe44hT0QPOgYj8p2EQ7xuQtSwpd4Bb4mMLw1ol2LCkYk68sKXSBKw5OpnCTwohhXrEtSwrG5C9LCl3gUthjCkPHjCasSZuS05g8ZkmhC1ISwslkch1GzgwePZqoxojZ7GvG5C1LCp2kqrg4hDKFO9BcUlJCUSZhs68Zk8csKXRSMpnwu48Kt6UAEM0kiAcsKRiTrywpdFJz0y5ShHDShZ0UitJJYrLnfLLGmPxgSaGTmupqcAkRLOCrj8CSgjH5zpJCJzXt2kmKEKECHmgGiLopYhThxhtzHYoxJgssKXRSU0MNKgHrPnJdmikmttMm2jEmH1lS6KS6hjqAgr4kFSDquiSkiC1bNuQ4EmNMNlhS6KS6xgaAgm8pRFPeJblbdm7NcSTGmGywpNBJsUQcgGCBzyVQ5CeFrbt25jgSY0w2WFLopGZ/trGC7z5Keldf1TTbQLMx+ajPk4KIjBWRf4rIGhF5XUQu95cPEZHHRGSd/3NwX8e2L4m0d4bsFHpLwfWSYn3GpuQ0Jh/loqXgAv+pqlOAo4DLRGQqcBWwXFUnAcv95/1G0r+TOVTgSaFYvV+ZmLUxjclLff6nrapbVPUl/3EDsAYYAywE7vI3uws4s69j25cUXjIIZQp7KsqyoFcML2azrxmTl3J6vici44HZwPPASFXdAl7iAEbs5TWXiMhKEVlZXV3dV6GS8nOB02ef2D8NKfMm2kmECv1IGJOfcpYURKQU+DPwdVWt7+zrVPU2VZ2jqnOGDx+evQDbccXLCiEKu6UwdpR3zGM2p4IxeSknSUFEQngJ4feqer+/eJuIjPbXjwa25yK2vUkFvWQQDhb2GfLYMeMIqmuzrxmTp3Jx9ZEAtwNrVPWmNquWAYv8x4uApX0d2764AS8pRAv8y3D4uLEUESMetJaCMfkoF6e9xwAXA6+JyCv+smuAG4B7RWQxsBH4RA5i26t0wBtYLY4UdoXQYEkpRRqzKTmNyVN9nhRU9SnYa8f8CX0ZS1e4fvdRaXFZjiPJLQkEiGYSNiWnMXnKrjbvJDfgHaqyin51T11OFGUSxAPRXIdhjMkCSwqd5PrdR0MqhuU4ktwryiSIWVIwJi9ZUugkN+gdqorBFTmOJPeirs2+Zky+sqTQSS3dR4MrynMcSe5F097sa8aY/GNJoZPSgQBBdSkpLc51KDlX5LrEKCJulVKNyTuWFDrJDQRwcAmHCvs+BYCI66ISYPs2m5LTmHxjSaGTUhLEwSUQsENWlPLKZq+vei/HkRhjept9w3VSOhDEUTfXYfQL0ZQ30c57WzflOBJjTG+zpNBJbiBICJtYBqAk5iXH1YmGHEdijOltlhQ6yRVrKbQYX6+MT6/ngdGz2VRticGYfGJJoQ1V5ekVT1Nfv2clby8ppHMQVf8zsnIIJ65/hmYp5mtP/zPX4RhjepElhTZWv/YC77z5A5b86po91llL4QNHHXMyB2wazUmpR3i2YhwPrN2S65CMMb3EkkIbz//rTm6u/DKbJqd54cUndluXEoeQtRQAKJ84kUPHDWLWO+8yUrfwrXffpjmdyXVYxpheYEnBl06nWTVuKO9LJcuKzuDV535JJvPBF50rjrUU2ljw2c9Qsv1QLk7cxa5ICecsf5W0aq7DMsb0kCUF3z8fvovnyo6gKB1nm4zmvUklLHvol63rXRwbU2gjEAwwf9EpDFof4ULu4uUQfOEfL+x1+7/+/nrefvbRPozQGNMdBZsU4qufgzZnti9sf51NMp7T3n6Z0fU1/M1ZSGP1g8RSMWq3b/fGFDLWRdLW5AkzSYUnMu299zgp8zceCoT58v03sLV695vafvfb7/KV0SdzadP7bH79+RxFa4zpjIJMCg/e9UsWVq3n3p/8CICGpnpWVE4konH+zxnnMqdqM5tlLJvGVnD/kjP413OnkZYgIUsKe/j0oivYOmgWH36ynlmx1/nLoJP432duIploBmDHW6v55ZhDSRPk1eAsvrPpMZprbWDamP6qIJPCeomxLjyW70+byT0//T5//t2PWOnMYe6ONxl/wHD+7zkfY2hDHcvkXIaP3ISbGEk8XUFxrc2l0F5JqISrz7qOL1x/I59dt52Dm7ZyV9nF/PAv15BJpfjOa0t5O3AIn1n3Kh/e/i5/i5zOjf/6LqlULNehG2M60O+SgoicIiJrReRtEbkqG5/x1U9/nUvffYFdMoibphzGvyvLSEmEMyPel/6Bo4Yy+70NrA9M5Dux3/G1Id+jzilmUCyRjXDyxicv/waffvNNKhPV/Hr4p7hi2XX8dfCJzGx6i8/Omcd358xhQtN27iy7mBse/Sp/W/IfpBJ1uQ7bGNOGaD+6YkREgsBbwIlAFfACcIGqvtHR9nPmzNGVK1d2+/NuvP1WfjJhLq6EmJDcyLMnn9G67uV1VXz+hRcRVcZt38CELe8zPt3AV3/8825/XqG4/brv8dOj57IlNJJSbeD6517mwmu+BsCDK17mil3N1IZLABih2xiV3EGFW09ZqpGwJkk7AdKO0BwoZheD2RUYRFJClNJIqTTg4NKQHky9VpAixKBMHUPYQUVgF0mNEKeYlEaIZJJEMwkimQQhSeJIgqB4c0HEKCFOMRHilEktZVJHKJ2GVBDcIJoOQSaIqgMiaCCDBjNkHEUdJe1ARgNI3CETc5CUEiVOscQgmKEuVExdqJRYIIqkA4gbQNMB3JCQdoRMUIhkkkQyScKZNK4TJBkMkQyGyWRCZNwwmg6TdjK4TgYNpimmicHUMEhqcFJCOl5GJl6Gk8lQFKwlEtpJRoREpoyYlpOSMAEBAgGCpIlojKjGkEyapnQRMTdETMNkIiEyoSCZYABxFXHTBDJpQpE0wUgKcTLE0mU0pUuJaRFF6WZKtYFSrSeccQm6aSQtkHFwNEyQKI3BMLtCIepCUSSToSiZJJJMEZQ0mUiGTFgJ4BJNNxNJxyhyE5QmXcoSGRyFZNQhEQ6QCISQdARJFQMB4kVxEkUJMo6LkwrixIME42EaMxXUazmNUkQZtQwPbGNEcAe1boQd6XLqtJyAhommI0TSIQglyISbyEQaSQUipAJluJQQIEDETRHOJAlpHIcmRGMkAg67woOpiQxGA8rY1GbGpTcwWGtp0uE06gjiWkwwHUfSCUSTOKE0TlhxwkFIVkBzGYGmEMVSQ3G4iqLwNhrTFdSkR1MnQwiGExRF64lG6kDDpDLlJAKl1ATK2B4oZatTQUW6mUmJ9zkovpUDwiWc9snvdutvVEReVNU5Ha1zuvWO2XMk8LaqvgsgIkuAhUCHSaGnvrn4UlK/vo1fTDycEzdW7bZu9qRKvlfTwKpnniGxaQvhHRsZevwZe3kn09Znv3MNwWtv5K4PHcKJ7+7g/Cu+3Lru9CNnM7mmltv+tJQdoSSbR0WpCVfwbngcjVLWul1QXYo0xqBMLYPYRViTNGkZOxhBShzKAnVUBt/BIcVOhvKujqNBphPWBFHiOKRIEiEmRcQoQmX3RnFUYxRpM3EpIiY9mCOjZN+rIxojQwCXECoBQpokRBKHNAnCJPwZ7EQzRIkT0QQBSRMgg6A4uARJI6psYjT1cjhpcSAKlO37s7tCNIODi4uzx7EC//+DGCGSNFPcGvf+RDRGGgdX8qPkfERjgPC8zOzxe4lmOjzWHQlrggPYzAbG8lTZdADmxl7mtB5H0VFc/aulcC5wiqp+3n9+MTBPVb/SZptLgEsAxo0bd8R77/W8fHNzYyPFpaU9fh/zATeZ5Kn/+ikHnXYcY2fP3ut2WzeuZ+s7bxEmgdsch3CYwUOHIpSQDBRRVDqUTCpALJGiLrGZnRvfINGwk+Dg0bjhYjLpGEVDJhItKyXkhAmkkiS315CobaB02GAqhlRQ5Agk6snsfJvMrvdxiitIBAdTl4qQSAh1dUmq42nCZcUMGTGYikFlSDRMXTJBzY4agkGH4cVlVIQCBDIpUvU7aNq1BddVguVjCNJMQlwaAkOopZSkG6IiDkPrGyiKN1BUFCMSriUYaEDqM6TrXDJNGRhcjjtmLLFR43DTjTQ3vU+8eRuDBo+irLycjNtAIh3kvV3vs3PHVoYkyhicHIqbipIMpnGDu4hH3sPVELHESBrdcoIilAXSlDkpgmElHighEQuS0ACpoiDxIiAYZBhhBmXiFKdihJKKxFK46RRFFSVopAQ3FKaREuJN1UjtTkodpbxIKClLUjpiIrGysdTEM7h1NTTv2klDUzOJcIZYNESSFKWpJCOaGxjSUE/IgVRpiKbiItKE0cYA6TohECimZPAgwtEodWHhPXHZkEwQy6Qoy6QpSSQIJROkIykIJglomkhDCKfeJZhyyUSKSUQhXZSkItzEkPAuigON1LnD2ZUeQUN6MCUkqQjGGBJqJhNsplmaiGkCSRURTAwiECvFybiEtI4gO8lImmSgmFigmEwgQjpQTEwHEXJdRrnVRNmFmwlQI2PYHBlNQzhCsdtEMTuJaBMaiOAGikhqGEkJmgZFCRbXEiraRTDaTG16FLXuaJpkMGVujMFSR4XuIpEM0RBzSGbSRJIBwgjhSJLyeDPFTTES4qDArtIS3hsylOFp5Qdf/fJe/7b2ZV8thf6WFD4BnNwuKRypql/taPuedh8ZY0wh2ldS6G8DzVXA2DbPKwGb3ssYY/pIf0sKLwCTRGSCiISB84FlOY7JGGMKRr8aaFZVV0S+AvwdCAK/UdXXcxyWMcYUjH6VFABU9SHgoVzHYYwxhai/dR8ZY4zJIUsKxhhjWllSMMYY08qSgjHGmFb96ua1rhKRaqAntzQPA3b0UjgDRSHuMxTmfts+F46u7veBqjq8oxUDOin0lIis3NtdffmqEPcZCnO/bZ8LR2/ut3UfGWOMaWVJwRhjTKtCTwq35TqAHCjEfYbC3G/b58LRa/td0GMKxhhjdlfoLQVjjDFtWFIwxhjTqiCTgoicIiJrReRtEbkq1/Fkg4iMFZF/isgaEXldRC73lw8RkcdEZJ3/c3CuY80GEQmKyMsi8qD/PK/3W0QGicifRORN///8Q/m+zwAi8g3/93u1iNwjItF83G8R+Y2IbBeR1W2W7XU/ReRq//ttrYic3JXPKrikICJB4GfAqcBU4AIRmZrbqLLCBf5TVacARwGX+ft5FbBcVScBy/3n+ehyYE2b5/m+37cAj6jqZGAm3r7n9T6LyBjga8AcVZ2OV27/fPJzv+8ETmm3rMP99P/Ozwem+a+51f/e65SCSwrAkcDbqvquqiaBJcDCHMfU61R1i6q+5D9uwPuSGIO3r3f5m90FnJmbCLNHRCqBjwG/brM4b/dbRMqBY4HbAVQ1qaq15PE+t+EARSLiAMV4MzXm3X6r6pPAznaL97afC4ElqppQ1fXA23jfe51SiElhDLCpzfMqf1neEpHxwGzgeWCkqm4BL3EAI3IXWdbcDFwJZNosy+f9nghUA3f4XWa/FpES8nufUdXNwH8DG4EtQJ2qPkqe73cbe9vPHn3HFWJSkA6W5e11uSJSCvwZ+Lqq1uc6nmwTkdOB7ar6Yq5j6UMOcDjwc1WdDTSRH10m++T3oS8EJgAHACUiclFuo+oXevQdV4hJoQoY2+Z5JV6TM++ISAgvIfxeVe/3F28TkdH++tHA9lzFlyXHAGeIyAa8rsHjReRu8nu/q4AqVX3ef/4nvCSRz/sM8FFgvapWq2oKuB84mvzf7xZ7288efccVYlJ4AZgkIhNEJIw3ILMsxzH1OhERvD7mNap6U5tVy4BF/uNFwNK+ji2bVPVqVa1U1fF4/7f/UNWLyOP9VtWtwCYROdRfdALwBnm8z76NwFEiUuz/vp+AN3aW7/vdYm/7uQw4X0QiIjIBmASs6PS7qmrB/QNOA94C3gG+let4srSP8/GajK8Cr/j/TgOG4l2psM7/OSTXsWbxGCwAHvQf5/V+A7OAlf7/91+Awfm+z/5+Xw+8CawGfgdE8nG/gXvwxk1SeC2BxfvaT+Bb/vfbWuDUrnyWlbkwxhjTqhC7j4wxxuyFJQVjjDGtLCkYY4xpZUnBGGNMK0sKxhhjWllSMAVHREaJyBIReUdE3hCRh0TkEBEZ37YKZRffc4OIDNvPNte0e/7MfrZ/QkQKbhJ6k1uWFExB8W9yegB4QlUPUtWpwDXAyD74+N2Sgqoe3QefaUyXWFIwheY4IKWqv2hZoKqvqOq/227k1+W/Q0Re84vMHecvD4rIf/vLXxWRr7Z7XZGIPCIiX2i3/Aa8ap6viMjv/WWNbdZf6b/nKn/btq8NiMhdIvI9//Pv9OcPeE1EvtFbB8YY8AppGVNIpgOdKZZ3GYCqHiYik4FHReQQ4LN4Bdhmq6orIkPavKYUr97Sb1X1t23fTFWvEpGvqOqs9h8kIqfilT2ep6rN7d7TAX4PrFbV74vIEcAY9eYPQEQGdXK/jekUaykY07H5eGUTUNU3gfeAQ/CKsP1CVV1/Xdsa90uBO9onhE74qP+65g7e85f4CcF//i4wUUR+IiKnAHlf+db0LUsKptC8DhzRie06Kj/csnxvtWGeBk71xy26Yl/v+QxwnIhEAVR1F97Mak/gtWZ+vZfXGdMtlhRMofkHEGnb5y8ic0XkI+22exK40F9/CDAOr7jYo8CX/Jm+aNfV8x2gBrh1L5+d8suZt/co8DkRKe7gPW8HHgLuExHHv8IpoKp/Br6NVyLbmF5jScEUFPUqQJ4FnOhfkvo6cB171pu/FQiKyGvAH4HPqGoC78x8I/CqiKwCPtXudV8HoiLyow4+/jb/db9vF9MjeOWOV4rIK8AV7dbfBLyE1501BnjC3+5O4Oou7L4x+2VVUo0xxrSyloIxxphWlhSMMca0sqRgjDGmlSUFY4wxrSwpGGOMaWVJwRhjTCtLCsYYY1r9f7OIgUj65W0RAAAAAElFTkSuQmCC\n", - "text/plain": [ - "
" - ] - }, - "metadata": { - "needs_background": "light" - }, - "output_type": "display_data" - } - ], - "source": [ - "config={\"res_ch\":6, # --Fixed\n", - " \"ro_chs\":[0], # --Fixed\n", - " \"reps\":10, # --Fixed\n", - " \"relax_delay\":1.0, # --us\n", - " \"res_phase\":0, # --degrees\n", - " \"pulse_style\": \"const\", # --Fixed\n", - " \n", - " \"length\":20, # [Clock ticks]\n", - " # Try varying length from 10-100 clock ticks\n", - " \n", - " \"readout_length\":100, # [Clock ticks]\n", - " # Try varying readout_length from 50-1000 clock ticks\n", - "\n", - " \"pulse_gain\":3000, # [DAC units]\n", - " # Try varying pulse_gain from 500 to 30000 DAC units\n", - "\n", - " \"pulse_freq\": 100, # [MHz]\n", - " # In this program the signal is up and downconverted digitally so you won't see any frequency\n", - " # components in the I/Q traces below. But since the signal gain depends on frequency, \n", - " # if you lower pulse_freq you will see an increased gain.\n", - "\n", - " \"adc_trig_offset\": 100, # [Clock ticks]\n", - " # Try varying adc_trig_offset from 100 to 220 clock ticks\n", - "\n", - " \"soft_avgs\":100\n", - " # Try varying soft_avgs from 1 to 200 averages\n", - "\n", - " }\n", - "\n", - "###################\n", - "# Try it yourself !\n", - "###################\n", - "\n", - "prog =LoopbackProgram(soccfg, config)\n", - "iq_list = prog.acquire_decimated(soc, load_pulses=True, progress=True, debug=False)\n", - "\n", - "plt.figure(1)\n", - "for ii, iq in enumerate(iq_list[0]):\n", - "# plt.plot(iq[0], label=\"I value, rep %d\"%(ii))\n", - "# plt.plot(iq[1], label=\"Q value, rep %d\"%(ii))\n", - " plt.plot(np.abs(iq[0]+1j*iq[1]), label=\"mag, rep %d\"%(ii))\n", - "plt.ylabel(\"a.u.\")\n", - "plt.xlabel(\"Clock ticks\")\n", - "plt.title(\"Averages = \" + str(config[\"soft_avgs\"]))\n", - "plt.legend()\n" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### Multiple triggers\n", - "You can send multiple triggers inside a loop. The `acquire()` and `acquire_decimated()` methods take a `readouts_per_experiment` parameter which must equal the number of triggers.\n", - "\n", - "Let's check the rep-to-rep consistency as well as the consistency between the first and second trigger." - ] - }, - { - "cell_type": "code", - "execution_count": 7, - "metadata": {}, - "outputs": [ - { - "data": { - "application/vnd.jupyter.widget-view+json": { - "model_id": "a87f38cf51e34a3197e0175a5698081d", - "version_major": 2, - "version_minor": 0 - }, - "text/plain": [ - " 0%| | 0/100 [00:00" - ] - }, - "execution_count": 7, - "metadata": {}, - "output_type": "execute_result" - }, - { - "data": { - "image/png": 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rbuJzH7udkkjva7EbY4Y3q8swAFE3DkA4qYxP7GR7pOsBrQse+RWvlx3G8o1vcPbsuR3Lk9Eoz37rG/z6iJGsPH0xMYkA8Jt4Pcet/AkxQjQEyngvWEF9cBKcOImguiTl/T/bGN3BpNpHGfd2Pa1aTG1kNDvCYzjy1cf5emEhp8y/8IB47v/DGu4oqyRRNoYvb9vO4YemB87WbN5EauphnL/lzzx0yJn8dtwcyn/xWT7zz3dYFU1j8oRdcTUAbZIepA+lYPzeRnYFRrNjR80+29z0k+/yXMXxNAdG8KNdmzuWqyo/+eZNfOXMWTw88Ryq3Y0s3fo0l9Ssoiq6nZfC09gUmkgqoBzp/oPFDU/w9Xcf4ImSrTw1dgtfTz3LeXV/YnxTA5ukmkfLz+UP5bNpKihhAlt5ofw4/q+T4lf//VVSqVTH627bvYefxHYRpQBXwvz08V91rHtzXAkBTfLRE8/jnzZvZrMcwbYjlG07d2T3jTTGDBnWUhiAuHfwHEEY27QXrQjw4Mrf8blPXgPAc398hgeOPJ5xqe0cEavhz2Un8d8//DZf/PxXefzb3+TnH5zNe4FRXF63lm+dfzWhcLqbJh6N8u7//i8lpWVUjj8Gp7yCYOm+ZwJN61RTK5VK8vz/Pkt5QQmHT51DUzLAt3/z39x3+Af5j6ml7H34UqpbZjJ78TV8/4n/4bVDz+X8XWt4cvTJvD5+FJBOUm+PGM3k5LuccvzHOHT8KJ5Z9yb3RS5hwaY3qRrX82l9xpjhz1oKA5AIpLNCJBBiYiwIwCZNX6vgJlz+q3ED9VLJZRuf50sFYwkR57HDx/P3VU+wfPoYtgYncuXuv3HbRV/uSAgA4UiE6nPOYfzJJ1MwYcIBCWF/gUCQ0874IFNmzaCgqIgxpRG++5nr+Gqylb3JEdxY/lVuObSCbz35Ve4/5AMcEd/ELWdfwfS2t3it6Cjeeettnr3/12x2JnFEc7p2StWYiZyyewP1MortO4b/WVXGZJNfpbPnz59PeXk5CxYs6NPjumNJYQDiwXRSKApH+NDs+YQ0Tm1ZKU/99ndcf893eaZ0Fh9ofp5rr1rGB+YsYn7dOv5WMJ0bU5t5vvBkPrL7OZYt/lzW4vvC3LN4dvZMFu7ayDtuNT8uuQIXh69Eg1SMGc302jpapZgVa+5jbd1mkuJwxJ7Wjsc7yXRtmT2tmS2QZsxQ0l5Go7/aS2c/8cQTrF+/nnvuuafLL//ukkJ76ewrrriiT6993XXXcffdd/cr7oOxpDAAcSfdOigvLuWo405gfKqWZ8pncHnFZH45YR6jtY5vHnNix1lEt8y/nMpUPX+JnMa0trf5yceuynqM44oKWP7xC3n9Q7P54s53+GrddhYtShfzuvzMjxDWGOurKtk0vhTRFJ/40MUdj3W8K5ujsVjW4zT5y0pn9690NsCcOXMoLS3t2xveAxtTGAA3mM6po0aOBeCUXW/z+sgWJjbXc2RTPZ8760OMPOLUju0ryiq4unUHDwUa+MVpc3ACg5eTw4EAX7/4o/ssO/Lo45i66Vf8vfgoRiV3MzG5laOrTupYH2xPCqnEoMVpfPbE9bDj7z1v1xfjjoNzu+5SaWels/teOjtbLCkMQNxJf6kfMvFwAD4/Yx47d2zngx++5KCncF79T5dw9aBF2LPj63by8sSpNDgj+VD9c/usc7yzlhI6sOa1MT2x0tnv623p7GyxpDAAiaCDaIpDxqePEqYcfRxTjj7O56j65lNnfIRfvNtCSoIcs3ffgn5OKv2PnchifSwzxPRwRJ8tVjr7fdmsR9cbNqYwAIlggBBxioqG71wKRx9xNEdH30U0xWUfumCfdSGvUK0rlhSM/6x09uCwpDAA8UCQMMO/v/3zxZVcsXsjkw/ZtwxHyPv3SNjVzGYIsNLZBzrzzDNZvHgxa9asoaqqilWrMjCLsaoO258ZM2aonxY9eodOWfOkrzFk0/d+8h0d+/TL+m8//Xe/QzFZtH79er9DGBDXdbWtrU1VVTdu3KiTJk3SWCymTU1NeuGFFw7ouW+66Sa97bbbMhFmnzQ3N3fcvuWWW/Saa67p93N19fcF1ulBvldtTGEAEgGHsA7/lsLBRILpfw83YC0FM3S1trZy9tlnk0gkUNWO0tnhcHhYl86+5ZZbcF2XSZMm7dNdlm2WFAYgEXAI5XJSCKcH+ywpmKHMSmdnlo0pDEBccrulUBxJV21NBe3fxJh8YZ/2AYgHQoRSuXsO/4iS9JWS7iBeZGeM8Zd92gcgkeMthfLy9CTgrrUUjMkb9mkfgLiEc7qlUDlqDGAtBWPySdY+7SLyMxHZJSKvdVp2m4i8ISKvisiDIlLead3XRGSjiLwpIvOyFVcmJQgRzuGkMNJLCklLCsZ069Of/jRjxow5aOE6yE7p7BUrVlBdXU11dTUrVqzo02MPJpuf9ruA+fstexKYpqrTgbeArwGIyLHAxcBU7zE/FJFgFmPLiLiECXW6iCbXFBeNQDRlLQWT0wZaOhvgk5/8JCtXrux2m0yXzq6vr+fmm2/m+eef54UXXuDmm2+moaGhT3F3JWufdlV9Bqjfb9lq1Y7qas8BVd7tRcC9qhpT1XeAjcDJ2YotExKxOHFChFK5mxTCBQUEcS0pmKwa7qWzAT7wgQ9QWVl50NfLRunsVatWMXfuXCorK6moqGDu3Lk9Jqbe8PM6hU8Dv/FuH0o6SbSr8ZYdQESuAq4CmDhxYjbj61bDjlriEiGcwy0FgBCudR/lkW+/8G3eqH8jo895TOUxfPXkr3a7zXAund0b2Sid3VXJ7m3btvUprq74khRE5OuAC7TPGt/V1VFdVmFT1eXAcoCZM2f6VqmtZutmoCynu48AHFzcod+TZ4a54Vw6eyAGUjpbB1CyuzuDnhRE5EpgATBH39+rGqBzNbYqYPtgx9YXO+tqobyMkJvjSUGtpZBPejqiz5bhXDp7IAZSOruqqoq1a9d23K+pqel4TwZiUD/tIjIf+CqwUFVbO616BLhYRApE5DCgGui53q2P6pvSAzqhZMrnSLLLwSUhVg3F+G+ols7urUyXzp43bx6rV6+moaGBhoYGVq9ezbx5Az9xM5unpN4D/AU4WkRqRGQJ8AOgFHhSRF4RkR8DqOrrwH3AemAlcLWqDulD8L2xdE7L9TEFR5PWUjBDwlAtnQ3wiU98gtNOO40333yTqqoq7rzzzgO2yXTp7MrKSpYuXdoxOH7jjTd2O9jdW9LfptdQMHPmTM1WIayefP9H3+Zbx8xjyT9W8s0lgzuH6mCa9eSjVKQaWT3vcr9DMVmyYcMGpkyZ4ncY/ZZMJkkkEkQiETZt2sScOXN46623iEajLFmyZECVUpctW0ZJSQnXXnttBiPuWUtLCyUlJQDceuut1NbWcvvtt/frubr6+4rIS6o6s6vtrV+gn6LembUFqeGbVHsjqEkbaDZDmpXOzixLCv0U88aawrmdE7zuI0sKZuiy0tmZZZ3F/RQPprNCJBjyOZLsCllLwZi8YkmhnxJOOikUhwt62HJ4czSJaw1KY/KGJYV+SnjlpMuKR/gcSXalxxQsKRiTLywp9FP7HAOjK0f5HEl2OakULtZ9ZEy+sKTQT3En/UU5vsq/+kuDwbGWgjE98qt09vz58ykvL2fBggV9elx3LCn0U3v3UdWYCT1sObwFUylccnsw3eS34Vo6G+C6667j7rvv7tNjemJJoZ/iwSABTVJckttjCu3dR8P5IkcztFnp7P6VzgaYM2cOpaWl3b/BfWT9Av2UCAYJE0dyvASE47UUYtEYkcKI3+GYLNvxrW8R25DZ0tkFU45h3A03dLuNlc7ue+nsbLGk0E+JQDop5DonlSRBiD1NDUQKe64hY0x/WOns9/W2dHa2WFLop0TAIay5nxSCKSUlQRrq6hgzzpJCruvpiD5brHT2+/zuqs3tvo8sSgSChDThdxhZ56TSpcHr36v1ORKT76x09uCwpNBP8UCIcD4kBW++iMY99T1saUx2WensA5155pksXryYNWvWUFVVxapVq3rc155Y6ex++uDq35DE4dkPX+DL6w+WL/7ie9w/4Sz+u/YFFl9yld/hmCyw0tkHZ6WzTa/FJURhMvfHFNq7j6KxNp8jMaZrVjo7sywp9FM8EKIs0drzhsNce/dRNJH7CdAMT1Y6O7NsTKGfEoQIpXJ7Kk4Ax+tejKVyf/zEGJPdOZp/JiK7ROS1TssqReRJEXnb+13Rad3XRGSjiLwpIgOffTqLUqkUcQkTSg388vihLujNLJcg5XMkxpjBkM2Wwl3A/P2WXQ+sUdVqYI13HxE5FrgYmOo95ociQ3dml1hzCwnChJO531IIeechxDX399UYk8WkoKrPAPufx7gIWOHdXgGc32n5vaoaU9V3gI3AydmKbaCa6nYRJ0womfsthRDpC3XcDF6wY4wZugZ7TGGsqtYCeL/HeMsPBbZ22q7GWzYk7di2hYSECaVyv0sl5CUD10afjOnS1q1bOfvss5kyZQpTp0496Kmj2SidvWLFCqqrq6murmbFihU9P6AXhsrZR10dhnZ5AYWIXAVcBTBxoj9zGeysq4WRlYTd3O9SKfB68SwpmFzlui6O0/+vQsdx+O53v8tJJ51Ec3MzM2bMYO7cuRx77LH7bPfQQw+xYMGCA5a3x/DZz362T69bX1/PzTffzLp16xARZsyYwcKFC6moqOj5wd0Y7I/6ThEZD+D93uUtrwE6T0xQBWzv6glUdbmqzlTVmaNHj85qsAfTsKcJgFAejCkUOOm5FJI5Xg3W+Ge4l84eP348J510EpA+PXbKlCls27Ztn22yUTp71apVzJ07l8rKSioqKpg7d26Pczr0xmC3FB4BrgRu9X4/3Gn5r0XkP4FDgGqg54IlPmmLp69PCCVzv/uoqCAMgBu0MYV88Kf73uK9rS0Zfc5RE0o486Kjut0mV0pnb968mZdffplTTjlln+XZKJ29bds2Jkx4/1i6qqrqgGTUH1lLCiJyD3AWMEpEaoCbSCeD+0RkCbAFWAygqq+LyH3AesAFrlYduqe77E3GAAjnQVIoLkxXcbSWgsmmXCid3dLSwgUXXMD3vvc9Rozo3eRbAymd3VWJokxUcM1aUlDVTxxk1ZyDbP9N4JvZiieTYppOBqFhXDeqt8pK0//cbsBaCvmgpyP6bBnupbMTiQQXXHABl156KR/72Mf6FUO73u5PVVUVa9eu7bhfU1PT8Z4MhB3+9UM8kP6jRfLg7ausHAmAG8z9fTVD21Atna2qLFmyhClTpvCv//qvB32NTJfOnjdvHqtXr6ahoYGGhgZWr17NvHkDv+7XPun9kPD61yOBIXt9XcZUjBwFWPeR8d9QLZ395z//mbvvvpunn36aE044gRNOOIHHH3/8gNfIdOnsyspKli5d2jE4fuONN3Y7T3Svqeqw/ZkxY4b64es//YaOffpl/dHd/+3L6w+mxobdOvbpl/Uz93/X71BMlqxfv97vEAbEdV1ta2tTVdWNGzfqpEmTNBaLaVNTk1544YUDeu6bbrpJb7vttkyE2SfNzc0dt2+55Ra95ppr+v1cXf19gXV6kO/VoXKdwrCScNJHzeVevfNcVlxcCoBrLQUzRFnp7MyypNAP7UlhZMUonyPJPicUwtG4JQUzZFnp7MyyT3o/xL1B1/Fj8mMie4ckbh6MnxhjLCn0S/uZOONGjfU5ksHhkCAp9q9iTD6wT3o/JJz0UXNZWe53HwGE1LWWgjF5wpJCP8QDQRxNEApH/A5lUARJ2piCMXnCPun9kAgGCZE/cxY76pLEWgrGdMXP0tnz58+nvLycBQsW9Olx3bGzj/ohEXAIa/7MWeyoDTSb3DVcS2cDXHfddbS2tvKTn/yk3/Hvz1oK/ZAIBPMsKbi4Q3d2VDPMWens/pXOBpgzZw6lpaV9eLd7Zi2FfohLiHA+dR+RwhX7V8kHf7hrObve/UdGn3PMpMM5+5NXdbuNlc7ue+nsbLFPej8kAg6hVO7Pz9zOSbkdZ1wZkw1WOvt9vS2dnS2WFPohIQ7hVD51HyVpI+R3GGYQ9HREny1WOvt9/d2fTLExhX6IS4hwHrUUgmrdR8Z/Vjp7cFhS6IeEhPOq+yiUSpG0Ruer/EcAACAASURBVKXxmZXOPtCZZ57J4sWLWbNmDVVVVaxatarHfe2J+N1UGYiZM2dqtgphdWf6mlVMatvBowuuHPTX9sOiR+9iU/GhvHbOXL9DMVmwYcMGpkyZ4ncY/ZZMJkkkEkQiETZt2sScOXN46623iEajLFmyZECVUpctW0ZJSQnXXnttBiPuWUtLCyVeFeZbb72V2trag17/0JOu/r4i8pKqzuxqezv86yNVxRUHJzVkp5DOuFAqScL+VcwQZaWzM8uXT7qI/AvwGUCBvwOfAoqA3wCTgc3ARara4Ed83UkmEiRwcFIpv0MZNMFUChcHN5HACdmAsxlarHR2Zg36mIKIHApcA8xU1WlAELgYuB5Yo6rVwBrv/pAT37sXl/xqKTheUmhtbvE7FGNMlvk10OwAhSLikG4hbAcWASu89SuAA08EHgKadtfj4hDU/GkppJNCiOaGIddwM8Zk2KAnBVXdBnwH2ALUAk2quhoYq6q13ja1wJiuHi8iV4nIOhFZV1dXN1hhd2jc/R4uIULJ/EkKwVSKpDg07h7899sYM7j86D6qIN0qOAw4BCgWkct6+3hVXa6qM1V15ujRo7MV5kE1Nr6HSoBgHo0ptI+f7G7c5XMkxphs86P76EPAO6pap6oJ4HfA6cBOERkP4P0ekt9ATXsaAfJqoNnxWkXN3r4bY94XjUY5+eSTOf7445k6dSo33XRTl9tlo3T2ihUrqK6uprq6mhUrVvT8gF7w4+yjLcCpIlIEtAFzgHXAXuBK4Fbv98M+xNajltb0FYn5lBSCqfS1LHtbbaDZ5J6Bls4uKCjg6aefpqSkhEQiwRlnnMG5557Lqaeeus92mS6dXV9fz80338y6desQEWbMmMHChQupqKjo976AP2MKzwMPAH8lfTpqAFhOOhnMFZG3gbne/SGnLR4FIJhHYwrtCbB9343JpOFeOltEOi40SyQSJBKJA+ojZaN09qpVq5g7dy6VlZVUVFQwd+5cVq5c2cd3/0D9To8i8piq9mu6H1W9Cdi/jRUj3WoY0qJuDAAnNXyvBO+r9pZCLJk/5cLzVeOjm4hv35vR5wwfUkz5Px3R7TbDvXR2MplkxowZbNy4kauvvnpQSmdv27aNCRMmdNyvqqo6YB6H/hhI99E/D/jVh6G4V/Mon7qPQu1JIY8qw5rBNdxLZweDQV555RUaGxv56Ec/ymuvvXbQiXEOFkO73pbO7qpEUVcVXPuq30mh/fTRfJMg/YfIp5ZC+74myJ9EmK96OqLPluFeOrtdeXk5Z511FitXruxVUhhI6eyqqirWrl3bcb+mpqbjPRmIXo0piMg7IvKP/X8G/OrDUPsXYz4Ve2g/cnDz6II9M/QM1dLZdXV1NDamz8xra2vjqaee4phjjjngNTJdOnvevHmsXr2ahoYGGhoaWL16NfPmzevx+XvS24HmmcAs7+dM4PvALwf86sNQwnvH8ikphL3ficDAm6bG9NdQLZ1dW1vL2WefzfTp05k1axZz585lwYIDh1szXTq7srKSpUuXdgyO33jjjVRWVva4rz1S1X79AM/297GZ+pkxY4YOtpt/dLOOffpl/Y+f3jbor+2X7yz/jo59+mVd9pNlfodismD9+vV+hzAgrutqW1ubqqpu3LhRJ02apLFYTJuamvTCCy8c0HPfdNNNetttg/9Zb25u7rh9yy236DXXXNPv5+rq7wus04N8r/ZqTEFETup0N0C65VA68JQ0/LjBdFOhIJg/cxaHAul9da2lYIYgK52dWb0daP5up9su8A5wUebDGfpcr/soEsyfDqSicLoDKRm0pGCGHiudnVm9Sgqqena2Axkukl5LoShy4FkKuaownD4TJBmw2VuNyXX9/pTv16WUN5JeF0pxcYnPkQyeUu+0OddaCsbkvIEc+n0uY1EMI+1jCpXl5T5HMnhGeGc+JG1MwZic1+uL17yS19VAxFt0d1YiGuJcrwtlZPkonyMZPCPLR8N74AbyZ3DdmHzV24vXPgM8A6wCbvZ+L8teWENXexfKyMr8SQoV5emqi3b2kTEH8rN09vz58ykvL+/yuoj+6m330ZdIX7j2rjfofCKQl9NwtQ+2lo3IwEUiw0RpaXtSsJaCyT3tZTT6q7109t/+9jdeeeUVVq5c2XE1cmfdJYX20tlXXHFFn177uuuu4+67M9tp09ukEFXVKICIFKjqG8DRGY1kmGj/YowU5M/ZR6XF6UtS7Owjkw1WOrt/pbMB5syZQ2lpZi8Z6+2YQo2IlAMPAU+KSAOwPaORDBNuIICjCQIDmJRjuAmEQjiasKSQB5544gl27NiR0eccN24c5557brfbWOnsvpfOzpbeXqfwUe/mMhH5A1AGDHw2h2EoGRAcBtbcHI4c3I5BdmMyzUpnv6+3pbOzpc+Hu6r6x2wEMly4ErSkYHJWT0f02WKls9/X3/3JFPuU95EbCOJoHiYFdXHFBpqNf6x09uDwJSmISLmIPCAib4jIBhE5TUQqReRJEXnb+z2w2aezxJVA3rYUknb2kfGRlc4+0JlnnsnixYtZs2YNVVVVrFq1qsd97Yn40VQRkRXAn1T1DhEJA0XADUC9qt4qItcDFar61e6eZ+bMmZqtQlgHc94TP2d7aByvfMifZrZfTnhqJYe6tfx+/qf8DsVk2IYNG5gyZYrfYfRbMpkkkUgQiUTYtGkTc+bM4a233iIajbJkyZIBVUpdtmwZJSUlXHvttRmMuGctLS0dZzTdeuut1NbWcvvtt/frubr6+4rIS6o6s6vtB/0UGhEZAXwA+CSAqsaBuIgsAs7yNlsBrAW6TQp+SAaChPK2+8h6G83QY6WzM8uP8yoPJ33h289F5HjgJdIXx41Vb95nVa0VkTE+xNYjV4I4mux5wxzjaBJX8uc0XDN8WOnszPLj0M8BTgJ+pKonAnuBXp+IKyJXicg6EVlXVzf4F1UnxMnjpGBjCsbkOj+SQg1Qo6rPe/cfIJ0kdorIeADv966uHqyqy1V1pqrOHD169KAE3FlSggTzMCkENUnSkoIxOW/Qk4Kq7gC2ikh7mYw5wHrgEeBKb9mVwMODHVtvuORnSyGkSVwsKRiT6/zqJP4i8CvvzKN/AJ8inaDuE5ElwBZgsU+xdStfxxSCmrIxBWPygC+nk6jqK14X0HRVPV9VG1R1t6rOUdVq73e9H7H1xMXBSeVfUnBSSVzfjiGMGfqSySQnnnjiQctYZ6N09ooVK6iurqa6upoVK1b06bEHY5/yPnLFwdGU32EMOidlLQWTm1zXxclAgcvbb7+dKVOmsGfPni7XP/TQQyxYsIBjjz22yxg++9nP9un16uvrufnmm1m3bh0iwowZM1i4cCEVFQO77tdOPO+DVCqFSyg/WwqabimkUvmXEE12DffS2QA1NTX8/ve/5zOf+UyX67NROnvVqlXMnTuXyspKKioqmDt3LitXDrxOqR369UEyFiOBg5OHX4yOlxBjLa0UjijxOxyTJW+99Q2aWzZk9DlLS6Zw1FFLu91muJfO/vKXv8x//Md/HLS2UTZKZ2/bto0JEyZ03K+qqmLbtm292vfuWFLog72Ne/K2pRBMpXBxaGlqsqRgMm44l85+7LHHGDNmDDNmzGDt2rV92u+BlM7uqkRRdxVce8uSQh/s3r0TF4dgyt/Stn5wUikSODQ1NjB6wqF+h2OypKcj+mwZzqWz//znP/PII4/w+OOPE41G2bNnD5dddhm//OUv+xRDu97uT1VV1T5JqKampuM9GQgbU+iDhvfqSEkwb7uPkhKiuWG336GYPDVUS2ffcsst1NTUsHnzZu69917OOeecLhNCpktnz5s3j9WrV9PQ0EBDQwOrV69m3rx5PT5/Tywp9EFj03sAOMn8SwpBb58bmywpGH8M1dLZvZXp0tmVlZUsXbq0Y3D8xhtvpLKysl+x7UNVh+3PjBkzdDA9+Kuf6tinX9bP3/2fg/q6Q8Fn775dxz79sj78qzv8DsVk2Pr16/0OYUBc19W2tjZVVd24caNOmjRJY7GYNjU16YUXXjig577pppv0tttuy0SYfdLc3Nxx+5ZbbtFrrrmm38/V1d8XWKcH+V61MYU+aIu2AeDk4ZhCyNvnlr1dn4NtjF+sdHZmWVLogzY3BqTPxMk3TjKdFPbGW32OxJh9WenszLIxhT6IuelT4Nq/IPOJk0qfcRFLRX2OxBiTTZYU+iDuzc3s+DCFqd8KvF2OB/Jv1jlj8oklhT5IkP5mDOVfTqDUm4oz5gz84hhjzNBlSaEP3Pak4HMcfqgoSV9kEw3bv4wxucw+4X3gBtJHySHy72h5fGW68mI0ZOcmGNMVP0pnz58/n/Ly8oO+Zn9YUugDN5hOBgWB/Hvbxo8cA0AsZLOvmdzSXkZjoNpLZx9Md0mhvXT2FVdc0afXvO6667j77rv79Jie5N+32wC0txQKnPzrQBo/Nl1ewFoKJtOsdHb/SmcDzJkzh9LS0p7f5D6wT3gftCeFonBBD1vmnjFjxiNv1hPLw4SYT5a+XcNrLW0Zfc5pJYV8o7qq222sdHbfS2dniyWFPnCD6YZVceGBlQ1znRMqIEKMaDDsdygmB1np7Pf1tnR2tviWFEQkCKwDtqnqAhGpBH4DTAY2AxepaoNf8XUl6bUUykaU+xyJPwpTbUSD1lLIZT0d0WeLlc5+X3/3J1P8HFP4EtB5iqfrgTWqWg2s8e4PKe0thcrygc2BOlxFNEYskH9dZ2ZosNLZg8OXpCAiVcBHgDs6LV4ErPBurwDO3/9xfmtvKYweM87nSPxRmIrRZknB+MRKZx/ozDPPZPHixaxZs4aqqipWrVrVr9j2cbDyqdn8AR4AZgBnAY95yxr326bhII+9inS307qJEyf2u5xsf/zzfd/VsU+/rE176gf1dYeKc35/n5761AN+h2EyzEpnH5yVzh4EIrIA2KWqL4nIWX19vKouB5YDzJw5c1A739xA+0Bzfs5RHEkm2C3lJKJRQpGI3+EYA1jp7EzzY6B5NrBQRM4DIsAIEfklsFNExqtqrYiMB3b5EFu33ECAoLoE8/S0zEI3TpRCdm3fxqGHH+F3OMYAVjo70wZ9TEFVv6aqVao6GbgYeFpVLwMeAa70NrsSeHiwY+tJMhDAIX+rhEYSLq0U8V7NFr9DMRmmeVj5Nx/05+86lK5ovhWYKyJvA3O9+0OKGwjmeVJIEJcCduzc6ncoJoMikQi7d++2xJBjVJXdu3cT6WNXr68Xr6nqWmCtd3s3MMfPeHqSDARwNOF3GL6JuOkzPuoah1zPnhmAqqoqampqqKur8zsUk2GRSISqqr5de2JXNPdBQgI4JHveMEdFEulWUnOixedITCaFQiEOO+wwv8MwQ8RQ6j4a8pISxNH87T4qTKW7F1olf1tLxuQ6Swp94AaCOJq/LYUSb/a1aDD/5pMwJl9YUugDV5y8HmguL0gPWEVD9m9jTK6yT3cfuJLfLYVxIysBm1PBmFxmSaEPXIKE8nhMYeKh6bMYbPY1Y3KXJYU+yPeWQtUhEwGIhfLzim5j8oElhT5wxSGYSvkdhm9GjhxHUF2iQes+MiZXWVLoAxcnr1sKgWCQCFGijs2+ZkyusqTQB644OHncUgAoTEVtSk5jcpglhT7I95YCpGdfiwYsKRiTqywp9FIqlcIlhJPM85ZCMkY0YHMpGJOrLCn0UrS5hQQOTirPWwqpBFGxKTmNyVWWFHqpoX4XLqG8PvsIIOLGaZNCv8MwxmSJJYVeathVR9IGmom4CdoopKV5j9+hGGOywJJCL9U3pOcQsJZCeva1nVve8TsUY0wWWFLopT3NjQB5P9AcSbgkJcTWLRv9DsUYkwWWFHqptXUvAI5aUgCordvmcyTGmGwY9KQgIhNE5A8iskFEXheRL3nLK0XkSRF52/tdMdixdac1HgXAcfN7HttCLyk0RW1MwZhc5EdLwQX+r6pOAU4FrhaRY4HrgTWqWg2s8e4PGbFUHLCWQiSZTooteTxXtTG5bNCTgqrWqupfvdvNwAbgUGARsMLbbAVw/mDH1p24d31CKL9zAsWkZ12LWvVsY3KSr2MKIjIZOBF4HhirqrWQThzAmIM85ioRWSci6+rq6gYrVOJeeQtH87v7qCyUvnAt6thwlDG5yLdPtoiUAL8Fvqyqve6gVtXlqjpTVWeOHj06ewHux5V0MnDyOycwuqwcgKhjTQVjcpEvSUFEQqQTwq9U9Xfe4p0iMt5bPx7Y5UdsB+N6c9WHNL8nrZ88cRJgU3Iak6v8OPtIgDuBDar6n51WPQJc6d2+Enh4sGPrjhtIJ4OCQH53m0w+vBqAqM2+ZkxO8uMbbjZwOXCOiLzi/ZwH3ArMFZG3gbne/SGjIyk4+X2EXFE5mpDGieX5+2BMrhr0T7aqPgscrA9mzmDG0hftSaEwz2cdCwQCRDRKNGgtBWNyUX73hfSBG0y/VUWFNpdAobYRDVr5bGNykSWFXkp6LYWS4lKfI/FfJGWzrxmTqywp9FLSaylUllf6HIn/ClNx2mz2NWNykiWFXnK9s45Gjh7rcyT+iyTjNvuaMTnKkkIvtY8pjKocvAvmhqpIMmGzrxmToywp9FLSaymMGDGkirf6on32NdeN+x2KMSbDLCn0khsIIJoi5NipmO1J4b26HX6HYozJMEsKveRKkBBWLhrSE+2oBHnn7df8DsUYk2GWFHrJDQRwcP0OY0iIJNIVY2tqt/ociTEm0ywp9JIbCFpS8ERi6VKx9fEtPkdijMk0Swq9lJQAjlpSAChuTV+jsLuyFvXmmTDG5AZLCr3kBgKELCkAMG9WNZXxPTxQ+DEeX/0jv8MxxmSQJYVOttW8y+fv+3e+/4OlB6xzxSGIHRUDnDx7Dh9/fSPbpYrHkrtwXUuWxuQKSwqd3PHwz/jd6IU8deQEWtui+6xzJWjdRx4R4f988lymN23kscgC7rzz3/wOyRiTIZYUOnlx8mQAXgqfxPI7btpnXTopWEuh3bjK8VzS0kSQJPcddhw7N7/jd0jGmAywpOB5+Dd38UrhNE5oW48ivFQ9kqaWvR3rLSkc6MpLP82Ha5/n9dBUvvbyIzx5168Puu199z/AxvUbBjE6Y0x/5G1SaHhp3T73H00040qIC+pqmdmwiT+Fz+CeFV/vWO+KY0lhPyLCF086i5ObX+Tx8g/yg0Ob+MU3rqahZt8rne/4+Y+5ZtSRfLzmXba98YZP0RpjeiMvk8Kqn36DSxte5YHv3ADA3sZ6nh93NEcl3+TTl32JT4eEqBTx+hGFvNfQBHhJIWVJYX/HTTmBn3/gY8zf+RLPO6dx5+zZ/PbR64m3tgFQv2M7P6yaSKk2sd0ZzT+//RKt773nc9TGmIPJy6TwavFhvBE4iq+dNI+ffvsWvvuLFdQFxzB75waCQYdF/3QhR+/ZxprwHJ568nzu/MlF3nUKlhS6MrJ8JHddvIQbgrvZxFEsP/p87rrjy6gq1//hN2x3DuGid59hUeNT/LVkKl9e/Wvctja/wzbGdGHIJQURmS8ib4rIRhG5Phuvcd0ll/HFmteIEOXfZ83hwaOnUqJ7+OjRs9tj4MKm7dTLKH5fcR5l1ZtwcSiwnNCtaz4wh+8Wt7KD8fxw2kK+ueJfeWLsbE6MvspXLvgiN5/5CU6K/o1Hx83mXx7+Ho/+vy+x98W1aCqV0ThUlURi8JJOsqWFeM02UvGhXzVWVVFVv8MwQ5gMpX8QEQkCbwFzgRrgReATqrq+q+1nzpyp69at62pVr6y4//v8dOQ4NspRzG97krvOu65jXWxvCwt/8yh/O2wKwVQKFeEDtVu499JF/X69fHHP07/nBippk0Ii2sZ/7H6DixZ/CoC/vvEsn9taz7vORAq0jZm6jrJoK7Ucys7AGOISojAVpUhbKUy1ESZGgUZBlCgltEoxSUIUp9ooTrUS0jjRYIjWQAHRYJikEyAZoKNl56RSBFOKiKKiCCmKNEppci+FyRgNOpIdwbHsCo3EUZcRqRbKtIkCN4XEC5BYBFA0FINQHAeXSEwpjKVIpWBvGNrCAZJBwQm4BMUlSIpQFMJtAskgLSOE5qIwMSdEmdtMRXQvpdE4IiE0EAYJ4aRcQskETjJJUh1ShEjiEAtCPKjEHdCAQkBBlIJkgkgiTkEsQSAh4AaRuJCSIIlQCDfk0OaEaXYKaQkVIgqj2/YwJrqHklicPVJKi5TQ5jgkC6JoOAaOCwkH4kECbhBxQIKgwRQBTRDUGMFUnHDKJZJKEtYksXCQloIQzaEIATdAOBqgcG+QMElCThvh4F7iEmEv5bTICMKpOKPcnYyiFlLC7tQhNMgY4oEQBU4LkeAe3JCyO1zO7nAZbYEwpW6U0mQrkWSCBEICB0UojbVSGm2lwI3SGimkqbCE5oIIYY0R1lYKUi2IKmgAVSERDOE6IRKOQ2EsQXlzjMr6BKFkAA05EHKIOwHawg7RUBAhSVGyhaJkK5oMsCc5gj1aRjwQIhBIEgy6BAOKI4IDBAOKSAyCMQi6BANCUNLrg0khkAggruCKEpcUiUCKIFHCgVaCEqUtUURLooyWZBkpDRAICkFxcAJKOOASDLhEAw7NRGgORjh8bxO3//M/9+szKiIvqerMrtY5/f3gZ8nJwEZV/QeAiNwLLAK6TAoDdeXiayh96Bu8OGItxzWX7bOuoLiExy79KK9veJFfbtnKYwUTOf3QbESRez5xzkeIPfBL/rNsHB/e8gYXLflCx7qTjjmDpyY18V9PPshL8RB/rZhJvDDEaN3FeNlChCitFNFKMbsoI0ohUQpJEaCUPZRoCyGJUkspzRxKjAIKaaVIW4lolGAqRTCu6UQeCBAPBEkF0l8KKKgG2BkYy95wMa2BYsq0kfFsYwZvoARoSFXSRAXxAge3OESCdKn0IBECpHBxaKWYmKRLfTiaIEIbIRIIiiIkCdJWUkjCm52uWJsp10YiyQQbCw6nIVKBSu8b6QFNEibuPT8ogY7X70mRtlBGE0mCvMIEUhLscrugugjpA0RFUIQAKYR0Ky7Rw0x7YY2hCAk5+Nzdoilvv6f1GHeBRhnNLgppYTul7GEsrRThkCSI2+V7IJqkjCZcQrRS1OW+hjWGQ4I2itAxATiix1B8EfC6qhXQ/fajSFsopZny1u1Zee2h1lK4EJivqp/x7l8OnKKqX+i0zVXAVQATJ06c8e677w74daPRXUQiYwb8PGZfGo8i4e6/vHbV76GuYQ8jyopINq4n5DYjI44iySg0CRIKIE766zDlwns7d9Dc1EjZyAoqR1VSVlJCSThIqi1BIhqDgiAtrsvuPXtJxuPE2/bS2txINAltcaEtCSMryjhkTAWVZYW0xpvZUr+duoZ/IE4xBeFKwskwxZEiSgreI5lYT1KTNFLCtsZW4rEoI4qCFARThJwCimQUGqsg1VZKMZUUJAPgRgkUtJIs2EJK9oJW0RhziKfiTBw/ntEjx7KXFCGU+vp66nbtximOIOEUe+MttMX30hJtIdrWTCAJgbiDtgYJhB2kOIAUpAgUOiSDQsyNkdQQtEWhsREn4BIuKaCgNEJQUiRborTWNyOpFJHicmKFI9BAikqppzy1g8JUM5HiYwgEjyHRUkRj2zZaYltJJHcTTTm0JgO0uSmKC8ZTGh5LQMLsUeU9t5kmt5URgQhVOpJRbjFJdzexVA2twd0kwkUki8ciRUUUR5RS9hBJvEdbymFHqoJadwSJVILSVC0j4pspSLYS1XKirWVIW4jiAiUQckhJEIkncPbGCLpKSUmC8mKhKBQmESqg3g2xJxWkMhCiKBmkLR4CdwRJLSaeckiiKDFSgTiFEiASDEKyDQlG2VPUSl04TlSUaCJBLBpDSFFYWMroogpCoRB72mI0t8QJiTKmMsSokjbC2kpbPETjnlba4nEIhXDCYUTCtCULaI1GSOxRCmK7cZobSMZitBUVsbe4mFhBhIJgmDIJUewGiSdCROMOqVSAQolT6jRQGqqHYIIUCTQZp1VD1BOh0XUpVGWk4zAiqBQXjeNjl3+lX5/N7loKQy0pLAbm7ZcUTlbVL3a1/UC7j4wxJh91lxSG2kBzDTCh0/0qIDttJGOMMQcYaknhRaBaRA4TkTBwMfCIzzEZY0zeGFIDzarqisgXgFVAEPiZqr7uc1jGGJM3hlRSAFDVx4HH/Y7DGGPy0VDrPjLGGOMjSwrGGGM6WFIwxhjTwZKCMcaYDkPq4rW+EpE6YCCXNI8C8q2Ocz7uM+Tnfts+54++7vckVR3d1YphnRQGSkTWHeyqvlyVj/sM+bnfts/5I5P7bd1HxhhjOlhSMMYY0yHfk8JyvwPwQT7uM+Tnfts+54+M7XdejykYY4zZV763FIwxxnRiScEYY0yHvEwKIjJfRN4UkY0icr3f8WSDiEwQkT+IyAYReV1EvuQtrxSRJ0Xkbe93hd+xZoOIBEXkZRF5zLuf0/stIuUi8oCIvOH9zU/L9X0GEJF/8f6/XxORe0Qkkov7LSI/E5FdIvJap2UH3U8R+Zr3/famiMzry2vlXVIQkSDwP8C5wLHAJ0TkWH+jygoX+L+qOgU4Fbja28/rgTWqWg2s8e7noi8BGzrdz/X9vh1YqarHAMeT3vec3mcRORS4BpipqtNIl9u/mNzc77uA+fst63I/vc/5xcBU7zE/9L73eiXvkgJwMrBRVf+hqnHgXmCRzzFlnKrWqupfvdvNpL8kDiW9ryu8zVYA5/sTYfaISBXwEeCOTotzdr9FZATwAeBOAFWNq2ojObzPnThAoYg4QBHpmRpzbr9V9Rmgfr/FB9vPRcC9qhpT1XeAjaS/93olH5PCocDWTvdrvGU5S0QmAycCzwNjVbUW0okDGONfZFnzPeArQKrTslze78OBOuDnXpfZHSJSTG7vM6q6DfgOsAWoBZpUdTU5vt+dHGw/B/Qdl49JQbpYlrPn5YpICfBb4MuqusfveLJNtaM8agAABBxJREFURBYAu1T1Jb9jGUQOcBLwI1U9EdhLbnSZdMvrQ18EHAYcAhSLyGX+RjUkDOg7Lh+TQg0wodP9KtJNzpwjIiHSCeFXqvo7b/FOERnvrR8P7PIrviyZDSwUkc2kuwbPEZFfktv7XQPUqOrz3v0HSCeJXN5ngA8B76hqnaomgN8Bp5P7+93uYPs5oO+4fEwKLwLVInKYiIRJD8g84nNMGSciQrqPeYOq/menVY8AV3q3rwQeHuzYsklVv6aqVao6mfTf9mlVvYwc3m9V3QFsFZGjvUVzgPXk8D57tgCnikiR9/8+h/TYWa7vd7uD7ecjwMUiUiAihwHVwAu9flZVzbsf4DzgLWAT8HW/48nSPp5Busn4KvCK93MeMJL0mQpve78r/Y41i+/BWcBj3u2c3m/gBGCd9/d+CKjI9X329vtm4A3gNeBuoCAX9xu4h/S4SYJ0S2BJd/sJfN37fnsTOPf/t3d/oTXGcRzH359tZeRCUtRKopZE0ZKS0oqyS7fcoJRCURIrckFJcqPWiDarFUlys9YudCK7kvbH5IZwLzdaaauvi+e3p+NxZudoTXk+r7vze35/znNuvud5znM+v0bWcsyFmZnlynj7yMzM5uGiYGZmORcFMzPLuSiYmVnORcHMzHIuClY6ktZJeijpg6R3koYktUvaUJ1C2eCcnyStWaBPd+H16AL9K5JKtwm9/VsuClYq6U9OT4FKRGyKiC1AN7B2CZb/pShExO4lWNOsIS4KVjadwExE9M41RMRYRLys7pRy+fskTaaQuc7U3izpZmqfkHS6MG65pGFJxwvt18nSPMckDaa271XHz6c5x1Pf6rFNkh5IuprW70/7B0xKOrtYH4wZZEFaZmWyFagnLO8kQERsk7QZGJHUDhwlC2DbERGzklZXjVlJlrc0EBED1ZNFxAVJpyJie3EhSV1ksce7ImK6MGcLMAi8jYhrkjqAtsj2D0DSqjrP26wuvlIwq20PWWwCEfEe+Ay0k4Ww9UbEbDpWnXH/DOgrFoQ67EvjpmvMeYdUENLrj8BGSbclHQD+++RbW1ouClY2U0BHHf1qxQ/Ptc+XDfMK6Eq/WzTiT3OOAp2SWgEi4hvZzmoVsquZe/OMM/srLgpWNs+BZdX3/CXtlLS30O8FcDgdbwfWk4WLjQAn0k5fFG71XAa+Aj3zrD2T4syLRoBjklbUmPM+MAQ8ltSSnnBqiognwCWyiGyzReOiYKUSWQLkQWB/eiR1CrjC73nzPUCzpEngEXAkIn6QfTP/AkxIGgcOFcadAVol3aix/N00brDwnobJ4o5fSxoDzhWO3wLekN3OagMqqV8/cLGB0zdbkFNSzcws5ysFMzPLuSiYmVnORcHMzHIuCmZmlnNRMDOznIuCmZnlXBTMzCz3E5g5OPjnUbIHAAAAAElFTkSuQmCC\n", - "text/plain": [ - "
" - ] - }, - "metadata": { - "needs_background": "light" - }, - "output_type": "display_data" - } - ], - "source": [ - "class DoubleTriggerProgram(AveragerProgram):\n", - " def initialize(self):\n", - " cfg=self.cfg \n", - " res_ch = cfg[\"res_ch\"]\n", - "\n", - " # set the nyquist zone\n", - " self.declare_gen(ch=cfg[\"res_ch\"], nqz=1)\n", - " \n", - " # configure the readout lengths and downconversion frequencies (ensuring it is an available DAC frequency)\n", - " for ch in cfg[\"ro_chs\"]:\n", - " self.declare_readout(ch=ch, length=self.cfg[\"readout_length\"],\n", - " freq=self.cfg[\"pulse_freq\"], gen_ch=cfg[\"res_ch\"])\n", - "\n", - " # convert frequency to DAC frequency (ensuring it is an available ADC frequency)\n", - " freq = self.freq2reg(cfg[\"pulse_freq\"],gen_ch=res_ch, ro_ch=cfg[\"ro_chs\"][0])\n", - " phase = self.deg2reg(cfg[\"res_phase\"], gen_ch=res_ch)\n", - " gain = cfg[\"pulse_gain\"]\n", - " self.default_pulse_registers(ch=res_ch, freq=freq, phase=phase, gain=gain)\n", - "\n", - " style=self.cfg[\"pulse_style\"]\n", - "\n", - " if style in [\"flat_top\",\"arb\"]:\n", - " sigma = cfg[\"sigma\"]\n", - " self.add_gauss(ch=res_ch, name=\"measure\", sigma=sigma, length=sigma*5)\n", - " \n", - " if style == \"const\":\n", - " self.set_pulse_registers(ch=res_ch, style=style, length=cfg[\"length\"])\n", - " elif style == \"flat_top\":\n", - " # The first half of the waveform ramps up the pulse, the second half ramps down the pulse\n", - " self.set_pulse_registers(ch=res_ch, style=style, waveform=\"measure\", length=cfg[\"length\"])\n", - " elif style == \"arb\":\n", - " self.set_pulse_registers(ch=res_ch, style=style, waveform=\"measure\")\n", - " \n", - " self.synci(200) # give processor some time to configure pulses\n", - " \n", - " def body(self):\n", - " # fire the same pulse+trigger twice, with 100 tProc clock ticks in between\n", - " # with the first ADC trigger, pulse PMOD0_0 for a scope trigger\n", - " # after the second pulse, pause the tProc until readout is done\n", - " # and increment the time counter to give some time before the next measurement\n", - " # (the syncdelay also lets the tProc get back ahead of the clock)\n", - " self.measure(pulse_ch=self.cfg[\"res_ch\"], \n", - " adcs=self.ro_chs,\n", - " pins=[0], \n", - " adc_trig_offset=self.cfg[\"adc_trig_offset\"],\n", - " syncdelay=100)\n", - " self.measure(pulse_ch=self.cfg[\"res_ch\"], \n", - " adcs=self.ro_chs,\n", - " adc_trig_offset=self.cfg[\"adc_trig_offset\"],\n", - " wait=True,\n", - " syncdelay=self.us2cycles(self.cfg[\"relax_delay\"]))\n", - "\n", - "config={\"res_ch\":6, # --Fixed\n", - " \"ro_chs\":[0], # --Fixed\n", - " \"reps\":5, # --Fixed\n", - " \"relax_delay\":1.0, # --us\n", - " \"res_phase\":0, # --degrees\n", - " \"pulse_style\": \"const\", # --Fixed\n", - " \n", - " \"length\":20, # [Clock ticks]\n", - " # Try varying length from 10-100 clock ticks\n", - " \n", - " \"readout_length\":100, # [Clock ticks]\n", - " # Try varying readout_length from 50-1000 clock ticks\n", - "\n", - " \"pulse_gain\":3000, # [DAC units]\n", - " # Try varying pulse_gain from 500 to 30000 DAC units\n", - "\n", - " \"pulse_freq\": 100, # [MHz]\n", - " # In this program the signal is up and downconverted digitally so you won't see any frequency\n", - " # components in the I/Q traces below. But since the signal gain depends on frequency, \n", - " # if you lower pulse_freq you will see an increased gain.\n", - "\n", - " \"adc_trig_offset\": 100, # [Clock ticks]\n", - " # Try varying adc_trig_offset from 100 to 220 clock ticks\n", - "\n", - " \"soft_avgs\":100\n", - " # Try varying soft_avgs from 1 to 200 averages\n", - " }\n", - "\n", - "prog = DoubleTriggerProgram(soccfg, config)\n", - "# print(prog.acquire(soc, readouts_per_experiment=1))\n", - "# print(prog.di_buf)\n", - "iq_list = prog.acquire_decimated(soc, readouts_per_experiment=2)\n", - "\n", - "plt.figure(1)\n", - "for rep in range(config['reps']):\n", - " for trig in range(2):\n", - " plt.plot(np.abs(iq_list[0][rep][trig][0]+1j*iq_list[0][rep][trig][1]), label=\"mag, rep %d trig %d\"%(rep, trig))\n", - "plt.ylabel(\"a.u.\")\n", - "plt.xlabel(\"Clock ticks\")\n", - "plt.title(\"Averages = \" + str(config[\"soft_avgs\"]))\n", - "plt.legend()" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### Multiple pulses\n", - "\n", - "Here's an example of playing multiple pulses from the same generator, with a 90-degree shift in the carrier phase between the two pulses." - ] - }, - { - "cell_type": "code", - "execution_count": 8, - "metadata": {}, - "outputs": [ - { - "data": { - "application/vnd.jupyter.widget-view+json": { - "model_id": "57c8892245b14d7c9dfe32e1608d4a18", - "version_major": 2, - "version_minor": 0 - }, - "text/plain": [ - " 0%| | 0/100 [00:00" - ] - }, - "execution_count": 8, - "metadata": {}, - "output_type": "execute_result" - }, - { - "data": { - "image/png": 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/feD7/RdR7vF8j1DYztMw/SPVp4FC+Vy49qnEKKq2CSMpXATn/ztUbYDNL6WaMTz1CBM+fEGbfjUQm6dML8T8mM1ya/pNqk9jxDHw949BqACGTuh6o0/8B8y4FHfwaMDeY/nGkkaOS/s8DREEsUrDdCk191TRUCgs7dlGw4+Gyx/EcQva/Q2THyxp5Lh0zwgHO2PXdC9ZaYScdPrNbLBFPrKkkePimt71NMCmrjbdS00j4va+T8IJ3pf2HssvljRyXNyPE3bS62R0HdfmnjJdOnA9Das0TIIljRznqZcaCdVbVmmY7iSH3DrpVBpBs6nNP5VfLGnkON/30+7TsKmrTXdSQ27tXCATsKSR4zKpNOwiOaY7yQN+Wn0adi5QXrKkkeN89TNqnrJvgaYryQN+cvhsbyQ7wu09ll8saeQ4T23Irek/fvLkvjSap5zgpFN7j+UXSxo5LpNKQ8RO7jNd870YAJJG85RrlUZesqSR46zSMP3J96JAupWGnaeRjyxp5LhM+zTsA2264gWVhuMW9npbqzTykyWNHJdJ0rBKw3TH95OVRjqjpxJ9GvbFJL9Y0shxNnrK9CcvaJ5yQr0fPWWVRn6ypJHjPPXSnnvKKg3TnWRHuJvBkFurNPKLJY0cljzgp11pOI5N8WC65AXNU05aZ4TbkNt8ZEkjh6VmILXRU6afpCqNcO87wp3gOi/2xSS/WNLIYRlXGjZ6ynTD85Ojp9Lp0wgqjeAEQZMfLGnksNRkclZpmH6SqjTS6Ag/UGlY0sgnljRymFUapr8lqwRJq9IIRk8FI7BMfrCkkcOsT8P0N99Pv9IQa57KS5Y0cljygC8iaW1vlYbpTrJpKb0+jcQJgcnEY/KDJY0cZpWG6W++7+GqQlrXCE/2aVjSyCeWNHKY9WmY/uaplzhIBAmgN1KjpzxLGvnEkkYOS11VLd3LvToOvm+VhulcqtJIY9YBGz2Vnyxp5LBMKw273Kvpjqfx9CuN4Cxy69PIL5Y0cliqTyPNuaccbMJC0zVfPVwF0qhmnaAj3POs0sgnljRyWF/0afhY0jCd83wfB02z0kgOubVKI59Y0shhGY+eclzr0zBd8tXDhbSSRqrSsD6NvGJJI4clD/g2esr0F199REmrI9zO08hPvf/6cJiIyFagAfCAuKpWiMhwYAkwCdgKXKGqNdmKMdsyrTTsIkymO4lKI73mKce1SiMfDfRK4yxVnaOqFcH9bwEvquo04MXg/hHLRk+Z/ub56Z+n4aQqDUsa+WSgJ42DzQMeCm4/BFySxViyzpKG6W+++onRU2l1hFulkY8GctJQ4DkRWSEiNwTLRqvqToDg96iONhSRG0RkuYgsr6qqOkzhHn7JA366SSPkhIjbB9p0IXFGeLon9yWShtoXk7wyYPs0gNNUdYeIjAKeF5ENPd1QVe8H7geoqKjQ/gow2zI9IzzshC1pmC756idGT6UxKWYomOQwbtOI5JUBW2mo6o7g9x7gcWAusFtExgIEv/dkL8Lsy7TSCLthYjayxXTBUx+H9GZRDgfTqcftPZZXBmTSEJFBIlKSvA2cC6wBngSuCVa7BngiOxEODH1RacTsW6Dpgq9+2geJUDCNiH0xyS8DtXlqNPB4cJ2IEPCIqj4jIm8BS0XkeuAD4PIsxph1mXaEh5wQMT+GqqZ9TQ6T3zx83DQrDceNEFK1LyZ5ZkAmDVX9GzC7g+XVwDmHP6KBKdO5p8JOGEXx1CMkA/KtYLIsk0oDJ0RY1SqNPDMgm6dMz2RaaYSD0S3WGW46k2nSCKk1T+UbSxo5LNM+jVAw9t4+1KYzidFTaTZdOi5hlJh9KckrljRymOdnOHoqqDQsaZjOeKppj56y5qn8ZEkjh2XcPBWcsWsdlaYzPukPuT2QNKzSyCeWNHJYxudpJPs01D7UpmOeKm66I+ucEGGFmL2/8ooljRzWZ30aVmmYTvRNpWHTiOQTSxo5rK8qDWtzNp3xVfugI9zeX/nEkkYO64szwsGShumch+Kk2zzlRoLmKas08okljRzWZ30a1lFpOpHRkFs3Yh3heciSRg5TTUzga+dpmP6SqDTSPEw4LmGs0sg3ljRymPVpmP7mZ9I8BYQRqzTyjCWNHJbq00h37ik7T8N0w1fFyeAwEUaI2XXo80ra7wYReaovAzG9Z30apr/5ZHCeBhAWhzjWPJVPMqk0Pt9nUZi0pM4IT/NltD4N0x2P9L+UAIRxrNLIM2m/G5LX6jbZk5p7yrE+DdM/EudpZJA0xJJGvunRRRREZAtwyLW2VfXoPo/I9Jidp2H6W0ajp4CQOMQtaeSVnl55p6LN7UISV8wb3vfhmN6wPg3T33zIsE/DJWZ9GnmlR0cbVa1u87NdVf8TOLufYzPdsOtpmP6WaaURFofYoY0UJof1tHnqpDZ3HRKVR0m/RGR6LONKw4bcmm74gEt6X0oAQhIiRmvfBWSyrqfNU//R5nYc2AJc0ffhmN6wPg3T3zIePSUuHolBG+meT2QGlh4lDVU9q78DMb3nqYcgSJptztanYbqjmZ4RHjSBxjWeUcViBo5MTu47qfu1TH9S1bSrDDhQoVilYTqTqDTSf4+F7ZoteSeTk/u+2GdRmLR46mXUdCAihJ2wJQ3TKV/ATfM8IGiTNOw9ljd62qeBiAwDppEYcgvwq36JyPSYr35GSQOwpGG61GeVhr3H8kZPR099DvgyUA6sBE4FXseG3WZVppUGJIbdWp+G6UziPI1MkoYNtsg3PT3ifBk4BXg/6BQ/Eajqt6hMj/jqZ/SBBqs0TNc8kcxGTzk2rDvf9PTd0KKqLQAiUqCqG4Dp/ReW6QnP99Kedyop7IbtA206lOnU+2CVRj7qaZ9GpYgMBX4LPC8iNcCO/gvL9ERfVBrFoWLqWuv6KCKTT1Inj2YwVDbsRgCIetE+iclkX0/P07g0uHmbiLwMDAGe6beoTJdqWmq46vdXMTg8OOM+jYa6MbzR8Daqmvb5Hib/PLf1OZbvegvIrNKYEC4FYGPtRmaMnNEnsZns6vHoqSRVfaU/AjE999aut9jWsA2AUcWjMvpbZbvqqRpTz/v17zNpyKQ+iM7kg6+98rXU7UxGT00IDafU81m+awWXTL2kL0IzWWaXe81BVc0HxiBk2jz17/HnAHh267N87/Xvce/KezP6eyb/OBlUGqt2NHFSSwt/+OB1Wr1WXt/xeqqvxOSmXlca2SYi5wP/D3CBn6nqD7Mc0mFT11rHw+sfZum7S1PLMm2emhyL87HGJu5ZeU9q2XUzr6MoVJTR3zW5aU/THu5feV+7ZZlUGr4T5hONTfxh0G4+/PCpxDTOwjk385nZduHPXJVTlYaIuMC9wAXA8cACETk+u1EdPne+dSf3rbqP6pbq1LJRhZk1TwmwsLqm3bKl7y4l7sdT3whjfozmeDOqStyP0xxtpa5xN02xpkP+nqqiqt0uO+LkwP8f9aJc/ZuLWbJxWbvlmkFfV1FhIec3NnFlfQMxTZwP9NyaX2YUp8muXKs05gKbVPVvACKyGJgHrOvTZ1Hln391NXtaN+AhEBpCRKK0+EKR47FfQwwlhHoNNBEm7BYxCGU/+xEvRsQppNnxceMFeBImEo6guIgqRbF6RJW4FBIJhwGHJvWIyn7ceDOuHyHqhIg7YXxH8LwWHOLEELa4DZwy6iTe2vM2o2M+j+3Ywd/K/injf3eU53GUH+EDJ8oxxVO5a/ld3LX8LkLq4KhH1EkcNAp8iAmA4EviIOiog4OPT+JEMARcheHeYErVpykUpsGvx0Xx3ALifpQQoBLB9WM4okSdAsTzGCMFbJcYozxoceJEKMXz6lHHp14KKPZhpBRQDZT4LRCOoB7EaKTVjYDnE9IooxnKXhUiNFLgFFGpTYxAcNxBNMc9whIjHClkSLSVOqLUhIop8ZQwLag7BIn5FEucunABGm1iKB71oVK8eAMFDjhuERJrRkSpdQsYFotS5IZp0mIK/DiDCguIew5+vIbqsI/4JTT6uwiJS4lfSiFxGgqKkWgM0Ua8UBF7vWbG4tLohtmjjQz3fUplEL4folSi1IcGI3FlmLbSEiml0ItSgE8VITReR8R1cJzBhGIxWkKFeOITie9DBWLOMNSvIySgTiloAzgFhDSCxmsJh4bQ4sXYIbXUtikqfrRnL8tKBjMkPj7t95YfDLk9r7GJJaWJqymsiNfyyZ+dSLETok4G4WiMllCUuIYYHYXGsEeJX0id1lEqEWJaCv5+HCfGfgoY4hTT6npEfZeJPtSJw16vgSJakFARsZjDUGlFIkPRWJyIxGhyXZriIYZJmHpRmr29DAEGy2BavSglTgEthIjqfoqdQtQZRNxvxXViRHxht9ZS6BQQc4pRr54WN0SjU8DUuEsLPvvVodSvJSrFtFDAYG0iFC7Ek0I0Wo/vCK1OASVeC36oGD/eQkyaKJFiBvkFKA4hoogfpVEifFDgUhIPUeL7uNpCNT6FoWKGaZSYOLSIEvXCNPpxSokzTAYj6uEIRN1BiNdIo9bxv9e8TkGkbw/zuZY0xgPb2tyvBD508EoicgNwA8BRRx3V+2cRYUfzKlrFI6JKLF5HTIUwPvtxKVCPba5LSF2KNMZ+FXaJUOpDTEM00czQmNLi+KDgRcFHUCAugi8CKL6XmKahWJWhnk8LYeLSSMT3CHuKi1KggDoMwuejvsdnV63jnMg+ZrdEGeL7DNr4VPJf7TVVJfkd8pFtm6l2XbxoMytLm9jthGl1oIlChvutFOCx041Q4CthiRP1hjOUGhpdaNQihtCEA1RqGcVOPXsizexzQoyPxRnmKXUSZojup8B3aCZCsdTTQgTwKaKeBsdhpxtiVjzGxnABR8eVmLMfV8OEfZ9BNFDrhKhzhRmeR4MTpijqJZKYX8Bo3UtcHKqllO2RvYzy4qBhGp39nB6Ls1cKcJ06HAXFQWM+lW4BJb4yPdZAvTgUeSEcp4FmEVrFYXw0jicO+8VhmFdLkS+04hKSGloIISjTozVUO2EaFJC91CPUtkIcIaTCuKY4jU4NpeoQ0jitzm4axWVY416iIjh+mHC8nkm+ssONMDka5SPxOJVOCVG3Gk9gPyFK4vtoEYcqcQi1Jp6nVRyG+h4RFXxfaJYaWsQhEvcRYB9hBnmKyDZEBR8HR+oI+y4ONTS4Dq4fotXfTxgYRpipTUXM2jOVCUNe4bzGJs5vbGLRtPPTen8BRINDzJCm4Xy4McbwuimMjWxmVXErUXEZQy0qMLTFJ6LKB6EII1ug2q1nXCxCi9uAK3WEfAfiIcqoZ5/rMrrVI4rwXjjMEM9jatyjRYsIx/YSF9gvEZyWeqI47MehOOZRJLDNdRkV95gYV3Y7BVS5VYRw2C31FKpPkbps13rUgwJVxBP2hRzGR0M4sp/BUoP4YY7yoyDK+kiEUt+nVJUWwoSpZjBKq4SIRuvwREEdCuI+RSj1EiIU3YeP4HoF7A4lErWjAIK6QogGJjZFqXMd/ua4hBBGeh6tsX2854QApcRXfPEp8ZV9TogtTm3qUleiiuPA8FiI/fu3UzB8YtqvX0dyLWl0VCd3dO3y+4H7ASoqKtJqF1j0meeRwaPA92iur2ZXfBBjB8GuJmEk+3AKBiMFpRRpM4qy3y9gX2OUkSWFtMQ8dtW3MGXkIAq0mdbmRsJ+Ky4+DJsEIqjvUdfYQoGjOMTZ1RBnaOkQSotCiX+ytYF4ayOhQSOISWLZi3dfy9yWJ5jbciDO0rp30/n3APB8Tb0BhvjKED8OUkVk0pfZNXkeR/vbCE87k52b32F6/F2qJpzLm5v28LGJQl3p8by+/E0+cZTHytAsanZv4+ypJfyldijbqvbx9WkFOEPG0fzBXxlWPp290RD+ltcom3YKVbECQrtXMXzSbNbu3M/w2ncYM2U2m2s9Ru9bjjNuNmtrQkyN1DBs3NFU1jQxpHYdJeOOYW9jjJH+XlqGHct7lbuZPiJMlQ5h364PmFk+DLd0NPHWJkKxRmJFI2hsbGRoAdT5hfhV7zFs6DCqZTjbd25n/NhxDI4IsukFwqOnU+mMp7DhfcrKRlOnxTRXvsPo8sl44RK0ehPhYRNooIi62lrGlw2jvqEet+59Bk+YTW1TK0O0Dr9oJJt31RUZ9HIAACAASURBVDBukKJFw9iwrYoTCvegZcexoz7KxOIYze5garetY+yYcdTIEJprdnLU6JHsjYXxaz5g1JBBtBSNJt64j8GFEer8YnTf3xhaMggdPIZoTSXRyFCihCls3cugEeVU1jRRHK9j+OhyqNsO8RbiQybRGvcobtxGXbiMqIYYFt/DDh1JQUsVIwZH8AePoaVuL6UlJdTEQnzyv1/j5WgT5XvP5bKCrwCwPzwy7fdYTBOly3YdxXMf3ALArFFhll09l90tIca2/o2oO5jXtntMYidTT/gQyysbmToiwpDBg9hT10gZNYSGjKcx5lMcq6GuFZqrtzGm2Cc2ahbavI+CSCHVXhH1e3cyuWwwjaGhNOytZPTQEnbHB7GnroGZQ2I4kSK0YTcypJx98QiuCEOKw8Q9nxA+uCGi0Rhhbz+Iy95YAaVFiU/J9n1NjJNqWovHUb1rC+Nb/4ZOOBXROAWxehh+NDTuBa8Vr2Q8u+uaGOLXMGjoGOKtjRBtREvGUF9fx4iSQdTFhKZonFElhTgCMU8JuwJejH2b3mTY+GNwSoLm53iUmob9tDrFADRF40waFMcRoGjogc+050NLLW5hKbj9c3iXXGprFpEPA7ep6nnB/YUAqvrvnW1TUVGhy5cvP0wR9q+dNQ2se+FXTNiyjGOaVgCwS8oYc+umtP5eSzRG4Q8SB4RmjVAkiROw9Ns7kUhx3wRtckpDS4yX363i5kV/ZYH7Irt1GBXnLuDGM6em9fdeWfxj/m7Dv/KYdzpr5/6IdTvruP2SE5g6anAfR276moisUNWKg5fnWqXxFjBNRCYD24H5wGeyG9LhM3ZYCWMvv5E3fiuwMpE0XE1/ssFotJVC4P74Jzjlc/9JvGEvRUXFzLSEccQqKQxz8exx3PbkWhY1ngPAiV76XyzDrYlBFvM+MotPX3DEjFnJazmVNFQ1LiI3Ac+SGHL7C1Vdm+WwDrtjz/oMz6x/meHUMbU1/TEAsWji2s0nzZjOiZNGAZmNxDL54/c3f5Q9DS1cfM+fiPvpJ41IdB8AzqCyvgrNZFlODbkFUNXfq+oxqjpFVb+f7XiyYeiQIZy/cCleSXminyRN8SBpEMwPZEzSmCGFzCofiusIcT/999jbZZewWcfhzFnQh9GZbMq5pGHacFxcvLQ3j8cSSUPccF9FZPJMImmkX2lUhcdzkX83lI7tw6hMNlnSyGHqhHE1g6QRVBpOyCoN07GwI3gZ9GnEPCUSssNMPrFXM4epuIQyqDS8eGK0lIQK+iokk2cyrTSink/YtcNMPrFXM5c5IcLipT1FhRezSsN0LeQ6GfVpxOI+Edem3M8nljRymRMMfktz1tBkn4ZjfRqmEyFH8DKtNKx5Kq/Yq5nLgnl9/Hh6l9L0YonmKdeap0wnQo4Qz6hPw5qn8o29mrnMTUzREI+ndynNZNKQsDVPmY65boZ9GnElYkkjr9irmcuC5ikvnt5Z4X48WWlY0jAdCztORkkjZs1TecdezRwmqaSRZqURD/o0rNIwnXAdwcukI9yzjvB8Y0kjl6WSRnp9Ghokm1DY+jRMx1xHiGXQpxGNW59GvrFXM4dJMPWx56XbPJVINq4lDdOJsOtkNHrKOsLzj72auSwYPZVu85QfNE+FrHnKdCLzk/vsjPB8Y69mDktVGml2hKtnzVOma4kht5n2adhhJp/Yq5nDkh3h6Z6noTFLGqZrmVYaieYp6wjPJ5Y0cpiEguYpL82kEWwXiljzlOlYpn0a1hGef+zVzGES9Gloms1T+MlKo7CvQjJ5xu2D5ik7TyO/2KuZww6MnkqvI1yDZq1wxJqnTMdCmXaEx61PI9/Yq5nDnCBp+GkOucWzM8JN10JuZhMW2vU08o+9mjksWWn4aTZPSbIvxGa5NZ0I9cU0ItYRnlcsaeQwJ+gI13Q7wv0YMXVB7ENtOpZJn4bvK3FfrSM8z9irmcMkw+Yp8aLExKoM07lQBrPcRoNkY0kjv9irmcNcNzl6Kr1KQ/wYcdy+DMnkmUwuwhQLkoZ1hOcXezVzWKrS8DNJGqG+DMnkGddx0p6wMHnxppD1aeQVSxo5LFVppNk85fhx4mJJw3Qu7KY/NXqyWStklUZesVczhyXPCE+7T8MqDdONTKYRSTZrhRyrNPKJJY0c5oYSB3z106w0NI4v1qdhOpfJNcLjQYXiWtLIK5Y0ctiB5ql0+zQ8PKs0TBdcJ/25p1J9GpY08ooljRx24DwNqzRM/wi7kqoYesv6NPKTvZo5LDn9R/pJw7OkYbrkOoKviRP1esv6NPKTJY0clpx7ijT7NETjeJY0TBeSB/x0OsOtTyM/WdLIYaGMm6c8fDu5z3Qh2bSUTr+G9WnkpwGXNETkNhHZLiIrg58L2zy2UEQ2ici7InJeNuMcCA5UGul1hDsax3esI9x07kCl0ft+DevTyE8D9Yhxt6re1XaBiBwPzAdmAOOAF0TkGFX1shHgQBBK9mmkPeTWwxObFt10Ltm0lM6wW+vTyE+59BVgHrBYVVtVdQuwCZib5Ziyyk1epjXNpOGqh1qfhulCskqwPg2TNFArjZtE5GpgOfA1Va0BxgNvtFmnMlh2CBG5AbgB4KijjurnULMn5Lr4KmknDQcPz6YRMV1IVgnd9WnEYjEqKytpaWlJLSuKefz04rEUNu5i/fo9/RqnSV9hYSHl5eWEwz2b8TorRwwReQEY08FD3wHuA/4N0OD3fwDXAR19Xenwnayq9wP3A1RUVKR/BZkBznWEOA746bXQuRq3SsN0KVklxLq5pkZlZSUlJSVMmjQJCa7PUt8cw61uZOqowRRH7MvJQKSqVFdXU1lZyeTJk3u0TVZeSVX9WE/WE5GfAk8FdyuBCW0eLgd29HFoOcUVoRUX0jwj3MGap0zXklfd667SaGlpaZcw2rLGqYFLRBgxYgRVVVU93mbA9WmIyNg2dy8F1gS3nwTmi0iBiEwGpgFvHu74BhLHEeK4SAZ9Gr5jF2EynXOdnvdpHJwwNNUQYGljIOso0XdlINaMd4rIHBJNT1uBLwCo6loRWQqsA+LAl47kkVNJcVxIczdY85TpTiZDbjXIGXY14fwy4CoNVf2sqp6gqrNU9WJV3dnmse+r6hRVna6qT2czzoHCy6TSwEPtPA3ThVAGQ24Pd50xePDgAfV3OjJv3jw+/OEPt1t22223MX78eObMmcO0adP41Kc+xbp161KPx2IxvvWtbzFt2jRmzpzJ3LlzefrpQw9/W7Zs4UMf+hDTpk3jyiuvJBqN9sv/MOCShukdDyeD0VO+JQ3TpXAocYjoriO8I1ZptFdbW8vbb79NbW0tW7ZsaffYV7/6VVauXMnGjRu58sorOfvss1P9DN/97nfZuXMna9asYc2aNfzud7+joaHhkL9/yy238NWvfpWNGzcybNgwfv7zn/fL/2FHjBznSQgnzaQRIg7WPGW6EHaSSaPnlca//m4t63bUE/d9WmM+xZFQxonj+HGl3PrJGb3e7pZbbmHixInceOONQOJbfUlJCV/4wheYN28eNTU1xGIxbr/9dubNm9du2z/84Q/cddddPPVUYizOTTfdREVFBddeey0rVqzgn//5n9m/fz8jR47kwQcfZOzYsYc8f1uPPfYYn/zkJxk9ejSLFy9m4cKFHa535ZVX8n//93888sgjfP7zn+enP/0pW7ZsoaCgAIDRo0dzxRVXtNtGVXnppZd45JFHALjmmmu47bbb+OIXv9jrfdYdqzRyXIwQoumNnko0T1lHuOlccvRUOpXGQOgHnz9/PkuWLEndX7p0KZdffjmFhYU8/vjjvP3227z88st87WtfQ7VniTEWi/FP//RPLFu2jBUrVnDdddfxne98p9vtFi1axIIFC1iwYAGLFi3qct2TTjqJDRs2sGnTJo466ihKS0u7XL+6upqhQ4cSCi7MVl5ezvbt23v0//SWVRo5Li4hnDTnngrZGeGmG+k0TyUrgr37W9lR28zxY0uzNv/UiSeeyJ49e9ixYwdVVVUMGzaMo446ilgsxre//W1effVVHMdh+/bt7N69mzFjOjp9rL13332XNWvW8PGPfxwAz/O6rTJ2797Npk2bOP300xERQqEQa9asYebMmR2u39ME1tX6vR0V1VOWNHJcnDCOn16Hl3WEm+6k0zyVpAOg0gC47LLLWLZsGbt27WL+/PkAPPzww1RVVbFixQrC4TCTJk1qdzY7QCgUwm8zaiz5uKoyY8YMXn/99R7HsGTJEmpqalIn0NXX17N48WJuv/32Dtf/61//SkVFBVOnTuWDDz6goaGBkpKSTv/+yJEjqa2tJR6PEwqFqKysZNy4cT2OrzeseSrHZVRp4IMlDdOFcCiD5qmgfUqynDXmz5/P4sWLWbZsGZdddhkAdXV1jBo1inA4zMsvv8z7779/yHYTJ05k3bp1tLa2UldXx4svvgjA9OnTqaqqSiWNWCzG2rVrAbjnnnu45557DvlbixYt4plnnmHr1q1s3bqVFStWsHjx4g7jfeyxx3juuedYsGABxcXFXH/99dx8882p0VA7d+7k17/+dbttRISzzjqLZcuWAfDQQw8d0kfTVyxp5Li4hNPqCFcvjiNqScN0KexmMHoq+J3twVMzZsygoaGB8ePHp5qRrrrqKpYvX05FRQUPP/wwxx577CHbTZgwgSuuuIJZs2Zx1VVXceKJJwIQiURYtmwZt9xyC7Nnz2bOnDn8+c9/BmDDhg2MGDGi3d/ZunUrH3zwAaeeempq2eTJkyktLeUvf/kLAHfffXdqyO2vf/1rXnrpJcrKygC4/fbbKSsr4/jjj2fmzJlccsklqcfauuOOO/jxj3/M1KlTqa6u5vrrr++DvXco6W3bWa6pqKjQ5cuXZzuMfvP27X9HiRtn2sI/9Wq7eGszoX8fw58nfYmPXPuDforO5Lpt+5r46J0vc9fls7ns5PJO11u/fj3HHXdcu2W761vYXd/CCeOH9Fv7+kBz0UUX8Zvf/IZIJLcuOdDR6yciK1S14uB17WtmjvMlhKtNvd4uHo8lXnyrNEwXQhmMnsrvr6MdSw7PzWfWPJXjPCeMm8aQWy8ebOPY6CnTuWTzVDytIbeKIEdMlXGksKSR43wngptGn8aBpGHnaZjOJZNGNM1pRCxf5B9LGjnOlzChtCqNxEgMseYp04VMTu7L8+7SI5YljRznO+kmjWAb15KG6Vxq9FQ8nSG3VmnkI0saOU7dcGIOqV7ygws3iWvNU6ZzyVluY2lcI1yDPg2TXyxp5DjfiRDSNJJGqk/DKg3TOREh7Erao6cOZ6VRWVnJvHnzmDZtGkcffTQ33XQTra2tGf/drVu3djrdR1+YPXs2CxYsaLfs2muvZfLkycyePZtjjjmGq6++ut1cUvv37+cLX/gCU6ZMYcaMGZxxxhmpcz7aWrFiBSeccAJTp07l5ptv7vX0JB2xpJHj1AkTpvfNU76XSDRizVOmG2HXSat56nD2aagqn/rUp7jkkkvYuHEjGzdupLm5mW9+85uHL4g0rF+/Ht/3efXVV2lsbGz32I9+9CNWrVrFu+++y4knnshZZ52VOiv8c5/7HMOHD2fjxo2sXbuWBx98kL179x7y97/4xS9y//33p/bJM888k3HMdsTIcepG0mqeSvZpWPOU6U7YdXp0udeUp78Fu96hLO4xwleI9MFhZswJcMEPO334pZdeorCwkH/4h38AwHVd7r77biZOnMj3v//9dhdWuvLKK7nmmmu48MILgcS3+k9+8pOcfPLJfPazn00dvO+55x4+8pGPtHueBx98kOXLl6emCrnooov4+te/zplnnslzzz3HrbfeSmtrK1OmTOGBBx7o9oJOjzzyCJ/97GdZv349Tz755CEVBySqva9+9as8/vjjPP3008ycOZO//OUvPPzwwzjB3GBHH300Rx99dLvtdu7cSX19feqiT1dffTW//e1vueCCC7qMqTtWaeQ6N4yLD37vLvma6tOwIbemG2HXIZrW3FOHz9q1azn55JPbLSstLWXSpEls2rSp3fK206VHo1FefPFFLrzwQkaNGsXzzz/P22+/zZIlS7j55pt7/Px79+7l9ttv54UXXuDtt9+moqKCH//4x91ut2TJEq688speTZe+du1a5syZg+t2fY7V9u3bKS8/cBZ/X02XbpVGjlMncWEW4q0QKe7xdn7cmqdMz4Rd6V3zVFAR7K5upDXmc8yYzmdn7Suq2uFJhB214V9wwQXcfPPNtLa28swzz3DGGWdQVFREXV0dN910EytXrsR1Xd57770eP/8bb7zBunXrOO2004BEMjr4sq4He+uttygrK2PixImUl5dz3XXXUVNTw7Bhwzr9H3ujv6ZLtyNGrgsFlYIXBXqTNBJto441T5lu9Lp5KqDKYZutcMaMGTz22GPtltXX17N7926mT5/ebnlhYSFnnnkmzz77LEuWLEk1Cd19992MHj2aVatW4fs+hYWFhzxPV9Olf/zjH++2Wmhr0aJFbNiwgUmTJqXifeyxx/jc5z7X4fp//etfOeecc5gxY0YqxmTzVEfKy8uprKxM3e+r6dKteSrXuYmJ0dTr3TU1Us1TIfveYLoWdiXt5qnDNXjqnHPOoampiV/+8pdA4sJIX/va17jpppsoKio6ZP358+fzwAMP8Mc//pHzzjsPSEyXPnbsWBzH4Ve/+hWed2iT76RJk1i5ciW+77Nt2zbefPNNAE499VT+9Kc/pZrCmpqaUpXKwoULefzxx9v9Hd/3efTRR1m9enVquvQnnniiw6SjqvzXf/0XO3fu5Pzzz2fKlClUVFRw6623pqqJjRs38sQTT7TbbuzYsZSUlPDGG2+gqvzyl7/sk+nSLWnkOAmSRjzWu6GFydFTVmmY7qQ9eor+u3rcwUSExx9/nGXLljFt2jRGjBiB4zidXob13HPP5dVXX+VjH/tYakbaG2+8kYceeohTTz2V9957j0GDBh2y3WmnncbkyZM54YQT+PrXv85JJ50EQFlZGQ8++CALFixg1qxZnHrqqWzYsAGAd95555ArAr766quMHz+e8ePHp5adccYZrFu3jp07dwLwjW98IzXk9q233uLll19Oxfqzn/2MXbt2MXXqVE444QQ+//nPd1hF3HfffXzuc59j6tSpTJkyJeNOcCCRxfL55+STT9Z89uLi/1S9tVSbdr3Xq+3Wv7pM9dZSXfX6c/0UmckXF/3XH/XaX/yly3XWrVt3yLLNexp00+6G/gqrS3/605/0qKOO0uXLl2fl+ds699xzsx1Ctzp6/YDl2sEx1domcpy4iY7weLS3zVOJSsO1SsN0I+xKen0akLUrMH3kIx/p8Gp82fDss89mO4Q+ZUkjx0k4Ua7Goi3drNnG+t9RtC9ROlufhulOyHWI9qJ5qiXmsbOuBc/X1DQkJn9Yn0aOc4I+jcjaJYlzNeq2g9/FBzwehSV/z+TVP263vTGdibgOdc0xtu1rwveVlljX5wTtqG2moSVGS8yza2nkIfuameOcUOKgP/jt/4W6TbD5RZh7A1z4o0NXjkdh66vtt7fmKdONsCts2NXAR+98mWmjBvO3vY28sfAcykoK2q0XjftBsjjwpcVSRv6xSiPHSbjNB3fzi4nfb94P+7bAG/8D21dAawO89p/woynw60+3296x5inTjeT06AAb9+zH85V///166ltivLRhN+9XN+L7yt+q9rO9tpl4m0rXCo38Y0eMHOeECg5dGCqC/5oT3BEoGgbN+6D8FKh8q92qUlDa/0GavDBycIS9+6OMKS3kN3/dzm/+mpiSQgR+dvFYRg1RSgvD1LccmECzOGKXE843VmnkODd8oE/idxUP8MsTF7P7Y/8PjvskXLUMPvwlGDEFrnuWus88zZ9PuYe7YpcD8NP4hcigEdkK3eSIfY2JkXk3nTWVf7noeP7wjTP5xnnTuebDE3ng2lO49iOTKIq4TB01iKOGFzN80IH35JCi/O4zi8fjjBw5koULF7ZbfuaZZzJ9+nRmzZrFsccey0033URtbW3q8V27djF//nymTJnC8ccfz4UXXtjhtCXPPPMM06dPZ+rUqfzwh51P2Hg4WaWR40JB81RcHf7ptQLA54GRo3n5679OrDDt40BiRMvH73yZPQ3DgUt5yDuPBoo5r4tpCIwBqA6SxuSywfzdMWUAfOmsqanHzzp2FOvXr6comM22fFgxw4sjNMc8IqH8fn8999xzTJ8+naVLl/KDH/ygXcf/ww8/TEVFBdFolIULFzJv3jxeeeUVVJVLL72Ua665hsWLFwOwcuVKdu/ezTHHHJPa3vM8vvSlL/H8889TXl7OKaecwsUXX8zxxx9/2P/PtrKSNETkcuA24Dhgrqoub/PYQuB6wANuVtVng+UnAw8CRcDvgS8HJ6Ac0dygI7yKoallW/Y2ctoPX2LSyGLOmzGGZSsqWV1Z1267hmCeqoJwfn+oTeb2NiRmGxg75NC5mDpyx5t3sCEY0t1Xjh1+LLfMvaXTx7du3cr555/P6aefzhtvvMHs2bP5h3/4B2699Vb27NnDww8/zNy5c3nzzTf5yle+QnNzM0VFRTzwwANMnz6dpqYmrr32WjZs2MBxxx3H1q1buffee6moqOgyrkWLFvHlL3+Z++67jzfeeKPDSQojkQh33nknU6dOZdWqVVRXVxMOh/nHf/zH1Dpz5sw5ZLs333yTqVOnpqY8nz9/Pk888cSRmTSANcCngP9tu1BEjgfmAzOAccALInKMqnrAfcANwBskksb5wNOHM+iBKBR8k1vhT+Ouy2dTWhhi5bZaVlXWsmFnA3/aVM2E4UWUFIZYMPcoGlpiLFtRScxL5NvRpT07EJgjV0Nr4kTQniaNbNm0aROPPvoo999/P6eccgqPPPIIr732Gk8++SQ/+MEP+O1vf8uxxx7Lq6++SigU4oUXXuDb3/42jz32GD/5yU8YNmwYq1evZs2aNR0exA/W3NzMiy++yP/+7/9SW1vLokWLOp3Z1nVdZs+ezYYNG9i9e/ch07h3ZPv27UyYMCF1v7y8vMOr8x1uWUkaqroeOpyXZh6wWFVbgS0isgmYKyJbgVJVfT3Y7pfAJVjSQIdP5QvRr/CqP4v1Jyfmzj93RmKem8bWOH/cWMWZ00cRcR2c4ESrr507nYrbX+C/FpyYtbhN7rhkzjh+u3IHJYU9G57dVUXQn5JzQkFi1ttzzjkHEeGEE05g69atQGJSwmuuuYaNGzciIsRiiU771157jS9/+csAzJw5k1mzZnX7fE899RRnnXUWxcXFfPrTn+bf/u3fuPvuuzu9zkVvG0Y6Wn8gnPcy0NomxgPb2tyvDJaND24fvLxDInKDiCwXkeVVVVX9EuhAEXYdnvXnEncPnclzUEGI82eOpTDsphIGwMjBBWz59wu5eHbm0ySb/PcfV8xh3ffOy3YY3SooODCS0HGc1H3HcYgH14/57ne/y1lnncWaNWv43e9+125q895atGgRL7zwApMmTeLkk0+murqal19+ucN1Pc/jnXfe4bjjjmPGjBmsWLGi279fXl7Otm0HDod9NbV5pvotaYjICyKypoOfrubm7SiNdjYrf6evsqrer6oVqlpRVlbW29BzSshN7Jq2I1Z6YiB8YzG5wXWE4r64ZOsAUFdXl5pZ9sEHH0wtP/3001m6dCkA69at45133kk9dvXVV6emQE+qr6/ntdde44MPPkhNbX7vvfd2OLV5LBZj4cKFTJgwgVmzZnH22WfT2trKT3/609Q6b731Fq+88kq77U455RQ2btzIli1biEajLF68mIsvvjjjfZCpfksaqvoxVZ3Zwc8TXWxWCUxoc78c2BEsL+9g+REvOSdQ+bCeX4DJmCPVN7/5TRYuXMhpp53W7noZN954I1VVVcyaNYs77riDWbNmMWTIEABWr17N2LFj2/2d3/zmN5x99tntqpt58+bx5JNP0tqaGDhw1VVXMWvWLGbOnEljY2PqehfJadyff/55pkyZwowZM7jtttsOqSJCoRD33HMP5513HscddxxXXHEFM2bM6Jf90isdTX17uH6APwAVbe7PAFYBBcBk4G+AGzz2FnAqiarjaeDCnjxHvk+N7nm+3vnMet1Z25ztUMwRrKOptXNJPB7X5ubEZ2jTpk06ceJEbW1t1bq6Or3sssuyHF3/G/BTo4vIpcB/A2XA/4nISlU9T1XXishSYB0QB76kiZFTAF/kwJDbp7FOcAAcR/jGecdmOwxjclpTUxNnnXUWsVgMVeW+++4jEokQiUR49NFHsx3egJKt0VOPA4938tj3ge93sHw5MLOfQzPGHIFKSkpYvnx59yuaATd6yhiTo9TOtc1JvX3dLGkYYzJWWFhIdXW1JY4co6pUV1dTWNjzEzfzYxydMSarysvLqaysJN/Pi8pHhYWFlJeXd79iwJKGMSZj4XCYyZMnZzsMcxhY85Qxxpges6RhjDGmxyxpGGOM6THJ99EOIlIFvJ/m5iOBvX0YTl+xuHrH4uq9gRqbxdU7mcQ1UVUPmbwv75NGJkRkuap2fRWWLLC4esfi6r2BGpvF1Tv9EZc1TxljjOkxSxrGGGN6zJJG1+7PdgCdsLh6x+LqvYEam8XVO30el/VpGGOM6TGrNIwxxvSYJQ1jjDE9ZkmjAyJyvoi8KyKbRORbWY5lq4i8IyIrRWR5sGy4iDwvIhuD38MOUyy/EJE9IrKmzbJOYxGRhcE+fFdEzjvMcd0mItuD/bZSRC7MQlwTRORlEVkvImtF5MvB8qzusy7iyuo+E5FCEXlTRFYFcf1rsDzb+6uzuLL+HgueyxWRv4rIU8H9/t1fHV3O70j+AVxgM3A0ECFx+dnjsxjPVmDkQcvuBL4V3P4WcMdhiuUM4CRgTXexAMfT/tK9mwku3XuY4roN+HoH6x7OuMYCJwW3S4D3gufP6j7rIq6s7jMSl3IeHNwOA38hjRURWQAABW1JREFUcYnnbO+vzuLK+nsseL5/Bh4Bngru9+v+skrjUHOBTar6N1WNAouBeVmO6WDzgIeC2w8BlxyOJ1XVV4F9PYxlHrBYVVtVdQuwicS+PVxxdeZwxrVTVd8ObjcA64HxZHmfdRFXZw5XXKqq+4O74eBHyf7+6iyuzhy295iIlAOfAH520PP32/6ypHGo8cC2Nvcr6foD1d8UeE5EVojIDcGy0aq6ExIHAGBU1qLrPJaBsB9vEpHVQfNVskTPSlwiMgk4kcS31AGzzw6KC7K8z4KmlpXAHuB5VR0Q+6uTuCD777H/BL4J+G2W9ev+sqRxKOlgWTbHJZ+mqicBFwBfEpEzshhLb2R7P94HTAHmADuB/wiWH/a4RGQw8BjwFVWt72rVDpb1W2wdxJX1faaqnqrOAcqBuSIys4vVsx1XVveXiFwE7FHVFT3dpINlvY7LksahKoEJbe6XAzuyFAuquiP4vQd4nEQ5uVtExgIEv/dkK74uYsnqflTV3cEH3Qd+yoEy/LDGJSJhEgfmh1X1N8HirO+zjuIaKPssiKUW+ANwPgNgf3UU1wDYX6cBF4vIVhLN6GeLyK/p5/1lSeNQbwHTRGSyiESA+cCT2QhERAaJSEnyNnAusCaI55pgtWuAJ7IRX6CzWJ4E5otIgYhMBqYBbx6uoJIfmsClJPbbYY1LRAT4ObBeVX/c5qGs7rPO4sr2PhORMhEZGtwuAj4GbCD7+6vDuLK9v1R1oaqWq+okEsepl1T17+nv/dVfPfq5/ANcSGJEyWbgO1mM42gSox1WAWuTsQAjgBeBjcHv4YcpnkUkyvAYiW8t13cVC/CdYB++C1xwmOP6FfAOsDr4sIzNQlynkyj/VwMrg58Ls73Puogrq/sM/n979xNiUxjGcfz7M1NmZCEpSknUJPmTkJJiimJpywalFIqSUKwoSTZKQ2nG1BRJspmmWWgis5Ix/mVD2MtGStRj8b5y7mnGvHcwY/H77O7795zTrefec899HlYBI3n/F8CZid7v03xc0/4eq+y3hV9PT/3T6+U0ImZmVsy3p8zMrJiDhpmZFXPQMDOzYg4aZmZWzEHDzMyKOWiY1UhaIOmmpDeSXknql9QhabEqmXSbXPOdpHkTjDlVez08wfghSesmczxmk+WgYVaR//h2FxiKiKURsRw4Bcyfgu0bgkZEbJyCPc2a4qBh1qgT+BYRXT8bIuJpRDysDso1FrqVap2MSOrM7S2SLub2Z5IO1+a1SxqQtL/Wfh5oz3UZ+nLb50r/8bzmaB5bnTtD0g1JZ/P+PZJe5PFH/9aFMQNone4DMPvPrABKEsAdBIiIlZKWkTIRdwB7SbUK1kTEd0lzK3Nmk3IE9UZEb3WxiDgh6VCkpHgNJO0gpbfeEBFfamu2An2kWiLnJK0FFkbEijx3TuF5mxXxNw2zydlESiNBRLwG3gMdpLxEXRHxPfdV63zcA7rrAaPA1jzvyxhrXiUHjPz6LbBE0mVJ24HfZdU1a5qDhlmjl8DagnFjpZn+2T5ebp5HwI78u0kzfrfmMNApqQ0gIj4Bq0mZWA/SWJzH7I85aJg1ug/MrP7mIGm9pM21cQ+A3bm/A1hESgI3CByQ1Jr7qreSzgAfgSvj7P0tpyyvGwT2SZo1xprXgX7gtqTW/ITWjIi4A5wmlcE1+2scNMwqImXw3Alsy4/cviTVgq7XHbgCtEh6DtwC9kTEV9In+w/AM0mjwK7avCNAm6QLY2x/Lc/rqx3TACmL6mOl6nHHav2XgCek22ULgaE8rgc42cTpm03IWW7NzKyYv2mYmVkxBw0zMyvmoGFmZsUcNMzMrJiDhpmZFXPQMDOzYg4aZmZW7Ad/sYLscAozBgAAAABJRU5ErkJggg==\n", - "text/plain": [ - "
" - ] - }, - "metadata": { - "needs_background": "light" - }, - "output_type": "display_data" - } - ], - "source": [ - "class DoublePulseProgram(AveragerProgram):\n", - " def initialize(self):\n", - " cfg=self.cfg \n", - " res_ch = cfg[\"res_ch\"]\n", - "\n", - " # set the nyquist zone\n", - " self.declare_gen(ch=cfg[\"res_ch\"], nqz=1)\n", - " \n", - " # configure the readout lengths and downconversion frequencies (ensuring it is an available DAC frequency)\n", - " for ch in cfg[\"ro_chs\"]:\n", - " self.declare_readout(ch=ch, length=self.cfg[\"readout_length\"],\n", - " freq=self.cfg[\"pulse_freq\"], gen_ch=cfg[\"res_ch\"])\n", - "\n", - " # convert frequency to DAC frequency (ensuring it is an available ADC frequency)\n", - " freq = self.freq2reg(cfg[\"pulse_freq\"],gen_ch=res_ch, ro_ch=cfg[\"ro_chs\"][0])\n", - " gain = cfg[\"pulse_gain\"]\n", - "\n", - " style=self.cfg[\"pulse_style\"]\n", - "\n", - " if style in [\"flat_top\",\"arb\"]:\n", - " sigma = cfg[\"sigma\"]\n", - " self.add_gauss(ch=res_ch, name=\"measure\", sigma=sigma, length=sigma*5)\n", - " \n", - " if style == \"const\":\n", - " self.default_pulse_registers(ch=res_ch, style=style, freq=freq, gain=gain, \n", - " length=cfg[\"length\"])\n", - " elif style == \"flat_top\":\n", - " # The first half of the waveform ramps up the pulse, the second half ramps down the pulse\n", - " self.default_pulse_registers(ch=res_ch, style=style, freq=freq, gain=gain, \n", - " waveform=\"measure\", length=cfg[\"length\"])\n", - " elif style == \"arb\":\n", - " self.default_pulse_registers(ch=res_ch, style=style, freq=freq, gain=gain, \n", - " waveform=\"measure\")\n", - " \n", - " self.synci(200) # give processor some time to configure pulses\n", - " \n", - " def body(self):\n", - " phase1 = self.deg2reg(self.cfg[\"res_phase\"], gen_ch=self.cfg[\"res_ch\"])\n", - " phase2 = self.deg2reg(self.cfg[\"res_phase\"]+90, gen_ch=self.cfg[\"res_ch\"])\n", - " # fire a single trigger, but two pulses offset by 200 tProc clock ticks\n", - " # with the first ADC trigger, pulse PMOD0_0 for a scope trigger\n", - " # after the full sequence is set up, pause the tProc until readout is done\n", - " # and increment the time counter to give some time before the next measurement\n", - " # (the syncdelay also lets the tProc get back ahead of the clock)\n", - " self.trigger(adcs=self.ro_chs,\n", - " pins=[0], \n", - " adc_trig_offset=self.cfg[\"adc_trig_offset\"])\n", - " self.set_pulse_registers(ch=self.cfg[\"res_ch\"], phase=phase1)\n", - " self.pulse(ch=self.cfg[\"res_ch\"], t=0)\n", - " self.set_pulse_registers(ch=self.cfg[\"res_ch\"], phase=phase2)\n", - " self.pulse(ch=self.cfg[\"res_ch\"], t=200)\n", - " self.wait_all()\n", - " self.sync_all(self.us2cycles(self.cfg[\"relax_delay\"]))\n", - "\n", - "config={\"res_ch\":6, # --Fixed\n", - " \"ro_chs\":[0], # --Fixed\n", - " \"reps\":1, # --Fixed\n", - " \"relax_delay\":1.0, # --us\n", - " \"res_phase\":0, # --degrees\n", - " \"pulse_style\": \"const\", # --Fixed\n", - " \n", - " \"length\":20, # [Clock ticks]\n", - " # Try varying length from 10-100 clock ticks\n", - " \n", - " \"readout_length\":400, # [Clock ticks]\n", - " # Try varying readout_length from 50-1000 clock ticks\n", - "\n", - " \"pulse_gain\":3000, # [DAC units]\n", - " # Try varying pulse_gain from 500 to 30000 DAC units\n", - "\n", - " \"pulse_freq\": 100, # [MHz]\n", - " # In this program the signal is up and downconverted digitally so you won't see any frequency\n", - " # components in the I/Q traces below. But since the signal gain depends on frequency, \n", - " # if you lower pulse_freq you will see an increased gain.\n", - "\n", - " \"adc_trig_offset\": 100, # [Clock ticks]\n", - " # Try varying adc_trig_offset from 100 to 220 clock ticks\n", - "\n", - " \"soft_avgs\":100\n", - " # Try varying soft_avgs from 1 to 200 averages\n", - " }\n", - "\n", - "prog = DoublePulseProgram(soccfg, config)\n", - "# print(prog.acquire(soc))\n", - "# print(prog.di_buf)\n", - "iq_list = prog.acquire_decimated(soc)\n", - "\n", - "plt.figure(1)\n", - "for ii, iq in enumerate(iq_list):\n", - " plt.plot(iq[0], label=\"I value, ADC %d\"%(config['ro_chs'][ii]))\n", - " plt.plot(iq[1], label=\"Q value, ADC %d\"%(config['ro_chs'][ii]))\n", - " plt.plot(np.abs(iq[0]+1j*iq[1]), label=\"mag, ADC %d\"%(config['ro_chs'][ii]))\n", - "plt.ylabel(\"a.u.\")\n", - "plt.xlabel(\"Clock ticks\")\n", - "plt.title(\"Averages = \" + str(config[\"soft_avgs\"]))\n", - "plt.legend()" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### Send/receive a pulse with pulse_style = flat_top " - ] - }, - { - "cell_type": "code", - "execution_count": 9, - "metadata": {}, - "outputs": [ - { - "data": { - "application/vnd.jupyter.widget-view+json": { - "model_id": "2802d646121247aebd5fa8c1ecd3d879", - "version_major": 2, - "version_minor": 0 - }, - "text/plain": [ - " 0%| | 0/100 [00:00" - ] - }, - "metadata": { - "needs_background": "light" - }, - "output_type": "display_data" - } - ], - "source": [ - "# Plot results.\n", - "plt.figure(1)\n", - "for ii, iq in enumerate(iq_list):\n", - " plt.plot(iq[0], label=\"I value, ADC %d\"%(config['ro_chs'][ii]))\n", - " plt.plot(iq[1], label=\"Q value, ADC %d\"%(config['ro_chs'][ii]))\n", - " plt.plot(np.abs(iq[0]+1j*iq[1]), label=\"mag, ADC %d\"%(config['ro_chs'][ii]))\n", - "plt.ylabel(\"a.u.\")\n", - "plt.xlabel(\"Clock ticks\")\n", - "plt.title(\"Averages = \" + str(config[\"soft_avgs\"]))\n", - "plt.legend()\n", - "plt.savefig(\"images/Send_recieve_pulse_flattop.pdf\", dpi=350)" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### Send/receive a pulse with pulse_style = arb " - ] - }, - { - "cell_type": "code", - "execution_count": 11, - "metadata": {}, - "outputs": [ - { - "data": { - "application/vnd.jupyter.widget-view+json": { - "model_id": "23da85fd5ef4402b907d17fdb44b583e", - "version_major": 2, - "version_minor": 0 - }, - "text/plain": [ - " 0%| | 0/100 [00:00" - ] - }, - "metadata": { - "needs_background": "light" - }, - "output_type": "display_data" - } - ], - "source": [ - "# Plot results.\n", - "plt.figure(1)\n", - "for ii, iq in enumerate(iq_list):\n", - " plt.plot(iq[0], label=\"I value, ADC %d\"%(config['ro_chs'][ii]))\n", - " plt.plot(iq[1], label=\"Q value, ADC %d\"%(config['ro_chs'][ii]))\n", - " plt.plot(np.abs(iq[0]+1j*iq[1]), label=\"mag, ADC %d\"%(config['ro_chs'][ii]))\n", - "plt.ylabel(\"a.u.\")\n", - "plt.xlabel(\"Clock ticks\")\n", - "plt.title(\"Averages = \" + str(config[\"soft_avgs\"]))\n", - "plt.legend()\n", - "plt.savefig(\"images/Send_recieve_pulse_arb.pdf\", dpi=350)" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### Compare the two main ways of acquiring data: prog.acquire_decimated and prog.acquire\n", - "\n", - "In the previous two demonstrations we used prog.acquire_decimated which uses the QICK decimated buffer (acquiring a whole time trace of data for every measurement shot. The QICK accumulated buffer is used in prog.acquire, which acquires a single I/Q data point per measurement shot- the average of the I/Q values in the decimated buffer. In qubit experiments we will be mainly using prog.acquire since for every shot we only need one I/Q value to assess the state of the qubit. So let's verify that prog.acquire_decimated and prog.acquire produce similar results (to within +/- 1 DAC units)." - ] - }, - { - "cell_type": "code", - "execution_count": 13, - "metadata": {}, - "outputs": [ - { - "data": { - "application/vnd.jupyter.widget-view+json": { - "model_id": "091bcf482155467baee0b2ee923d7c09", - "version_major": 2, - "version_minor": 0 - }, - "text/plain": [ - " 0%| | 0/100 [00:00 Calibrating the QICK for phase coherent readout\n", - "\n", - "###
In this demo you will calibrate the QICK clocks to have the same phase.\n", - "\n", - "Before you measure a resonance with your QICK this is the first calibration you should do. It is a calibration for the two synthesizers which belong to the QICK signal generator and the QICK readout, respectively. The two synthesizers are running at the same frequency, but there is initially a constant phase difference $\\phi$ between these two synthesizers. Doing this calibration results in you finding that phase difference $\\phi$. In your subsequent measurements, you can specify this initial phase difference $\\phi$ to compensate for it. From then on, the signal generator can synthesize any frequency and then if you read in data (doing a digital down conversion in the process), the readout will still be phase coherent with respect to the signal generator. \n", - "\n", - "
The angular frequency $\\omega = 2 \\pi f$ .\n", - "\n", - "
Also, $\\phi = (\\omega t) + \\phi_0$. \n", - "\n", - "
So, $\\phi = (2 \\pi f)*t + \\phi_0 $. \n", - "\n", - "If $f$ goes up linearly, the phase difference will also change linearly (it will either increase or decrease, depending on whether the readout is ahead or behind of the signal generator- this is randomly determined each time the board clocks are initialized). Once the phase hits 360 degrees it cycles back to 0 again. For a readout frequency of interest $f_i$ there is a corresponding phase difference $\\phi_i$. In this demonstration we assume $f_i \\approx 180$ MHz. You can plot $\\phi(f)$ and evaluate $\\phi(f_i)=\\phi_i$." - ] - }, - { - "cell_type": "code", - "execution_count": 1, - "metadata": {}, - "outputs": [ - { - "data": { - "application/javascript": [ - "\n", - "try {\n", - "require(['notebook/js/codecell'], function(codecell) {\n", - " codecell.CodeCell.options_default.highlight_modes[\n", - " 'magic_text/x-csrc'] = {'reg':[/^%%pybind11/]};\n", - " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", - " Jupyter.notebook.get_cells().map(function(cell){\n", - " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", - " });\n", - "});\n", - "} catch (e) {};\n" - ] - }, - "metadata": {}, - "output_type": "display_data" - }, - { - "name": "stdout", - "output_type": "stream", - "text": [ - "Populating the interactive namespace from numpy and matplotlib\n" - ] - } - ], - "source": [ - "# Import the QICK drivers and auxiliary libraries\n", - "from qick import *\n", - "from qick.parser import load_program\n", - "%pylab inline" - ] - }, - { - "cell_type": "code", - "execution_count": 2, - "metadata": { - "scrolled": false - }, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "\n", - "QICK configuration:\n", - "\n", - "\tBoard: ZCU111\n", - "\n", - "\tGlobal clocks (MHz): DAC fabric 384.000, ADC fabric 384.000, reference 204.800\n", - "\n", - "\tSampling freqs (MHz): DAC 6144.000, ADC 3072.000\n", - "\n", - "\tRefclk multiplier factors: 30 (DAC), 15 (ADC)\n", - "\tFrequency resolution step: 1.431 Hz\n", - "\n", - "\t7 signal generator channels:\n", - "\t0:\ttProc output 1, maxlen 65536\n", - "\t\tDAC tile 0, ch 0, 32-bit DDS, fabric=384.000 MHz, fs=6144.000 MHz\n", - "\t1:\ttProc output 2, maxlen 65536\n", - "\t\tDAC tile 0, ch 1, 32-bit DDS, fabric=384.000 MHz, fs=6144.000 MHz\n", - "\t2:\ttProc output 3, maxlen 65536\n", - "\t\tDAC tile 0, ch 2, 32-bit DDS, fabric=384.000 MHz, fs=6144.000 MHz\n", - "\t3:\ttProc output 4, maxlen 65536\n", - "\t\tDAC tile 1, ch 0, 32-bit DDS, fabric=384.000 MHz, fs=6144.000 MHz\n", - "\t4:\ttProc output 5, maxlen 65536\n", - "\t\tDAC tile 1, ch 1, 32-bit DDS, fabric=384.000 MHz, fs=6144.000 MHz\n", - "\t5:\ttProc output 6, maxlen 65536\n", - "\t\tDAC tile 1, ch 2, 32-bit DDS, fabric=384.000 MHz, fs=6144.000 MHz\n", - "\t6:\ttProc output 7, maxlen 65536\n", - "\t\tDAC tile 1, ch 3, 32-bit DDS, fabric=384.000 MHz, fs=6144.000 MHz\n", - "\n", - "\t2 readout channels:\n", - "\t0:\tADC tile 0, ch 0, 32-bit DDS, fabric=384.000 MHz, fs=3072.000 MHz\n", - "\t\tmaxlen 1024 (avg) 1024 (decimated), trigger 14, tproc input 0\n", - "\t1:\tADC tile 0, ch 1, 32-bit DDS, fabric=384.000 MHz, fs=3072.000 MHz\n", - "\t\tmaxlen 1024 (avg) 1024 (decimated), trigger 15, tproc input 1\n", - "\n", - "\ttProc: 1048576 words program memory, 4096 words data memory\n", - "\t\tprogram RAM: 65536 bytes\n" - ] - } - ], - "source": [ - "# Load bitstream with custom overlay\n", - "soc = QickSoc()\n", - "# Since we're running locally on the QICK, we don't need a separate QickConfig object.\n", - "# If running remotely, you could generate a QickConfig from the QickSoc:\n", - "# soccfg = QickConfig(soc.get_cfg())\n", - "# or save the config to file, and load it later:\n", - "# with open(\"qick_config.json\", \"w\") as f:\n", - "# f.write(soc.dump_cfg())\n", - "# soccfg = QickConfig(\"qick_config.json\")\n", - "soccfg = soc\n", - "# print(soccfg)\n", - "\n", - "# Print the QICK configuration\n", - "print(soc)\n", - "\n", - "# loopback and monitor channels\n", - "out_chs = [0,5,6]" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "\n", - "### Hardware Configuration\n", - "\n", - "tProc channel 7 : DAC 229 CH3 <-> Readout channel 0 : ADC 224 CH0\n", - "\n", - "The following are optional:\n", - "\n", - "* tProc channel 6 : DAC 229 CH2 <-> Readout channel 1 : ADC 224 CH1\n", - "* tProc channel 1 : DAC 228 CH0(P) <-> oscilloscope, through a DC-block\n", - "* PMOD 0_0 (pin 1 on J48 on the ZCU111) <-> oscilloscope\n", - "\n" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "We are going to drive the DAC outputs in periodic mode, so we only need to specify a short constant waveform and they will continue to run forever. This is useful for the phase measurement, but it's good practice to stop the DACs afterwards using soc.reset_gens()." - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "We define the frequency range to be tested, and some helper functions that will process and print the results. For each frequency we will print the measured phase (what we care about), and also the mean magnitude and RMS of the waveform (for debugging - the magnitude should always be much larger than the RMS)." - ] - }, - { - "cell_type": "code", - "execution_count": 4, - "metadata": {}, - "outputs": [], - "source": [ - "# Output frequency f0_v.\n", - "###################\n", - "# Try it yourself ! Change the output frequency.\n", - "###################\n", - "\n", - "f0_start=100\n", - "f0_step=0.000250\n", - "expts=40\n", - "# expts=1\n", - "\n", - "f0_v = np.arange(0,expts)*f0_step+f0_start\n", - "\n", - "f0_v = soccfg.adcfreq(f0_v, gen_ch=6, ro_ch=0)\n", - "\n", - "def calculate_phase(d):\n", - " [xi,xq] = d\n", - " x = xi +1j*xq\n", - "\n", - " # Average to improve calibration.\n", - " xavg = np.mean(x)\n", - "\n", - " # Calculate calibration phase.\n", - " fi = np.remainder(np.angle(xavg,deg=True)+360,360)\n", - " return [fi, np.abs(xavg), np.std(x)]\n", - "\n", - "def print_results(res):\n", - " print(\"freq_i = %f MHz, \"%(f0) +\n", - " \"phi_i = (%.2f, %.2f) deg, \" % tuple([res[i][0] for i in range(2)]) +\n", - " \"mag = (%.2f, %.2f), \" % tuple([res[i][1] for i in range(2)]) +\n", - " \"RMS = (%.2f, %.2f) ADU\" % tuple([res[i][2] for i in range(2)]))\n", - "# print(\"freq_i = %f MHz, phi_i = (%.2f, %.2f) deg, mag = (%.2f, %.2f), RMS = (%.2f, %.2f) ADU\" %(f0,*out_array,*A,*xrms))" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### Measurement methods\n", - "We are going to make the same measurement in several ways, to demonstrate different ways of running the QICK (and hopefully gain some understanding of what's going on under the hood). You can jump to the analysis at the end at any point to plot the data - all methods write the results to the same array.\n", - "\n", - "For the first two methods, we will have a common Python method - below - that acquires the data, but doesn't load the tProc program." - ] - }, - { - "cell_type": "code", - "execution_count": 5, - "metadata": {}, - "outputs": [], - "source": [ - "def measure_phase_decimated(soc, f0, fi0, out_array):\n", - " \"\"\"\n", - " Measure the phase shift for a given frequency using decimated readout, and write it into the provided array.\n", - " Assumes that the tProc is already loaded with a program that reads the frequency and phase from memory locations 123 and 124.\n", - " \"\"\"\n", - " readout_length = 1000\n", - "\n", - " f0_dac_int = soccfg.freq2reg(f=f0) # Frequency of signal generator\n", - " \n", - " soc.tproc.single_write(addr=123, data=f0_dac_int)\n", - "\n", - " fi0_int = soccfg.deg2reg(fi0, gen_ch=6)\n", - " soc.tproc.single_write(addr=124, data=fi0_int)\n", - "\n", - " # Configure readout.\n", - " for ch in range(2):\n", - " soc.configure_readout(ch=ch, output=\"product\", frequency=f0)\n", - "# soc.config_avg(ch=ch, address=0, length=readout_length, enable=True)\n", - " soc.config_buf(ch=ch, address=0, length=readout_length, enable=True)\n", - " \n", - " # Start tProc.\n", - " soc.tproc.start()\n", - "\n", - " time.sleep(0.1)\n", - " \n", - " # Get data.\n", - " data = [soc.get_decimated(ch=ch, length=readout_length).T for ch in range(2)]\n", - "# print(data)\n", - "\n", - " # Process data.\n", - " res = [calculate_phase(d) for d in data]\n", - "\n", - " # Save results.\n", - " out_array[:] = [a[0] for a in res]\n", - " print_results(res)" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### Load ASM from text file\n", - "\n", - "First, let's program the tProc from an assembly language file, which needs to be located in the same directory when you run it: `01_phase_calibration.asm`" - ] - }, - { - "cell_type": "code", - "execution_count": 6, - "metadata": { - "scrolled": false - }, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "freq_i = 100.000000 MHz, phi_i = (323.42, 217.77) deg, mag = (637.06, 635.08), RMS = (1.87, 1.79) ADU\n", - "freq_i = 100.000249 MHz, phi_i = (302.88, 197.21) deg, mag = (637.77, 634.55), RMS = (1.84, 1.91) ADU\n", - "freq_i = 100.000500 MHz, phi_i = (282.22, 176.56) deg, mag = (637.85, 634.81), RMS = (1.84, 1.63) ADU\n", - "freq_i = 100.000750 MHz, phi_i = (261.56, 155.90) deg, mag = (637.85, 634.85), RMS = (1.77, 1.75) ADU\n", - "freq_i = 100.001000 MHz, phi_i = (240.89, 135.23) deg, mag = (637.83, 634.69), RMS = (1.84, 1.70) ADU\n", - "freq_i = 100.001249 MHz, phi_i = (220.34, 114.69) deg, mag = (637.97, 634.82), RMS = (1.84, 1.71) ADU\n", - "freq_i = 100.001500 MHz, phi_i = (199.68, 94.02) deg, mag = (637.68, 634.96), RMS = (1.89, 1.67) ADU\n", - "freq_i = 100.001750 MHz, phi_i = (179.02, 73.36) deg, mag = (637.74, 635.02), RMS = (1.93, 1.70) ADU\n", - "freq_i = 100.002000 MHz, phi_i = (158.35, 52.69) deg, mag = (637.95, 635.06), RMS = (1.82, 1.79) ADU\n", - "freq_i = 100.002251 MHz, phi_i = (137.70, 32.03) deg, mag = (637.94, 634.95), RMS = (1.84, 1.65) ADU\n", - "freq_i = 100.002500 MHz, phi_i = (117.14, 11.48) deg, mag = (637.89, 634.72), RMS = (1.80, 1.68) ADU\n", - "freq_i = 100.002750 MHz, phi_i = (96.48, 350.81) deg, mag = (637.74, 634.90), RMS = (1.79, 1.71) ADU\n", - "freq_i = 100.003000 MHz, phi_i = (75.81, 330.15) deg, mag = (637.78, 634.51), RMS = (1.90, 1.69) ADU\n", - "freq_i = 100.003251 MHz, phi_i = (55.16, 309.49) deg, mag = (637.60, 634.80), RMS = (2.11, 1.71) ADU\n", - "freq_i = 100.003500 MHz, phi_i = (34.61, 288.94) deg, mag = (637.84, 635.00), RMS = (1.91, 1.78) ADU\n", - "freq_i = 100.003750 MHz, phi_i = (13.95, 268.28) deg, mag = (637.56, 634.95), RMS = (1.96, 1.67) ADU\n", - "freq_i = 100.004000 MHz, phi_i = (353.27, 247.61) deg, mag = (637.69, 634.96), RMS = (1.80, 1.72) ADU\n", - "freq_i = 100.004251 MHz, phi_i = (332.62, 226.95) deg, mag = (637.83, 634.87), RMS = (1.94, 1.73) ADU\n", - "freq_i = 100.004499 MHz, phi_i = (312.08, 206.40) deg, mag = (637.81, 634.75), RMS = (1.87, 1.70) ADU\n", - "freq_i = 100.004750 MHz, phi_i = (291.41, 185.75) deg, mag = (637.74, 634.55), RMS = (2.02, 1.66) ADU\n", - "freq_i = 100.005000 MHz, phi_i = (270.73, 165.08) deg, mag = (637.96, 635.02), RMS = (1.77, 1.58) ADU\n", - "freq_i = 100.005250 MHz, phi_i = (250.08, 144.42) deg, mag = (637.77, 634.60), RMS = (1.96, 1.70) ADU\n", - "freq_i = 100.005499 MHz, phi_i = (229.54, 123.87) deg, mag = (637.60, 635.15), RMS = (1.93, 1.83) ADU\n", - "freq_i = 100.005750 MHz, phi_i = (208.87, 103.21) deg, mag = (637.83, 634.97), RMS = (2.08, 1.85) ADU\n", - "freq_i = 100.006000 MHz, phi_i = (188.19, 82.54) deg, mag = (637.74, 634.82), RMS = (2.19, 1.71) ADU\n", - "freq_i = 100.006250 MHz, phi_i = (167.53, 61.86) deg, mag = (638.14, 635.18), RMS = (2.22, 1.78) ADU\n", - "freq_i = 100.006499 MHz, phi_i = (146.99, 41.32) deg, mag = (637.77, 635.07), RMS = (2.11, 1.76) ADU\n", - "freq_i = 100.006750 MHz, phi_i = (126.33, 20.67) deg, mag = (638.16, 634.90), RMS = (1.83, 1.68) ADU\n", - "freq_i = 100.007000 MHz, phi_i = (105.66, 359.99) deg, mag = (637.95, 634.95), RMS = (1.99, 1.69) ADU\n", - "freq_i = 100.007250 MHz, phi_i = (85.00, 339.32) deg, mag = (638.05, 634.89), RMS = (1.93, 1.71) ADU\n", - "freq_i = 100.007501 MHz, phi_i = (64.34, 318.67) deg, mag = (638.02, 635.13), RMS = (2.20, 1.65) ADU\n", - "freq_i = 100.007750 MHz, phi_i = (43.80, 298.14) deg, mag = (637.97, 635.01), RMS = (2.07, 1.76) ADU\n", - "freq_i = 100.008000 MHz, phi_i = (23.13, 277.46) deg, mag = (638.15, 635.51), RMS = (2.02, 1.73) ADU\n", - "freq_i = 100.008250 MHz, phi_i = (2.47, 256.80) deg, mag = (637.93, 635.11), RMS = (1.94, 1.78) ADU\n", - "freq_i = 100.008501 MHz, phi_i = (341.80, 236.14) deg, mag = (637.57, 634.87), RMS = (1.93, 1.85) ADU\n", - "freq_i = 100.008749 MHz, phi_i = (321.26, 215.59) deg, mag = (637.83, 635.21), RMS = (1.94, 1.79) ADU\n", - "freq_i = 100.009000 MHz, phi_i = (300.59, 194.92) deg, mag = (638.07, 635.14), RMS = (1.82, 1.69) ADU\n", - "freq_i = 100.009250 MHz, phi_i = (279.92, 174.26) deg, mag = (638.02, 635.14), RMS = (2.15, 1.71) ADU\n", - "freq_i = 100.009501 MHz, phi_i = (259.26, 153.60) deg, mag = (638.08, 635.00), RMS = (1.91, 1.73) ADU\n", - "freq_i = 100.009749 MHz, phi_i = (238.72, 133.06) deg, mag = (638.15, 635.30), RMS = (2.09, 1.73) ADU\n" - ] - } - ], - "source": [ - "# Constant, real envelope.\n", - "# The length must be at least 16 times the nsamp parameter passed to the signal generators.\n", - "xg = np.zeros((160,2), dtype=np.int16)\n", - "xg[:,0] = 30000\n", - "\n", - "# Upload waveform.\n", - "for ch in out_chs:\n", - " # Set the DAC channels to be in 1st Nyquist zone mode\n", - " soc.set_nyquist(ch=ch,nqz=1)\n", - " soc.load_pulse_data(ch=ch, data=xg, addr=0)\n", - "\n", - "# Load program.\n", - "load_program(soc, prog=\"01_phase_calibration.asm\")\n", - "\n", - "# Output phase.\n", - "fi0 = 0\n", - "fi_v = np.zeros((2,len(f0_v)))\n", - "for ii, f0 in enumerate(f0_v):\n", - " measure_phase_decimated(soc, f0, fi0, fi_v[:,ii])\n", - "\n", - "soc.reset_gens()" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### QickProgram\n", - "\n", - "It's usually easier to define the tProc program dynamically in Python, rather than loading it from a separate file. The low-level tool for this is QickProgram.\n", - "\n", - "If you compare `01_phase_calibration.asm` to the commands below, you can see the resemblance; if you convert the QickProgram to .asm format with print(prog) it is very clear." - ] - }, - { - "cell_type": "code", - "execution_count": 7, - "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "\n", - "// Program\n", - "\n", - " memri 1, $1, 123; //freq\n", - " memri 1, $2, 124; //phase\n", - " regwi 1, $3, 32000; //gain\n", - " regwi 1, $4, 10; //nsamp: generator will consume 16*nsamp DAC values.\n", - " regwi 1, $5, 4; //b00100 -> phrst = 0, stdysel = 0, mode = 1, outsel = 00\n", - " bitwi 1, $5, $5 << 16;\n", - " bitw 1, $4, $4 | $5;\n", - " regwi 1, $6, 0; //start time\n", - " synci 1000;\n", - " regwi 0, $1, 1; //Send a pulse on pmod 0_0 (pin 1 on J48 on the ZCU111).\n", - " seti 0, 0, $1, 0; //Start the pulse.\n", - " seti 0, 0, $0, 100; //End the pulse after 100 ticks (260 ns).\n", - " set 1, 1, $1, $2, $0, $3, $4, $6;\n", - " set 6, 1, $1, $2, $0, $3, $4, $6;\n", - " set 7, 1, $1, $2, $0, $3, $4, $6;\n", - " synci 1000;\n", - " regwi 0, $1, 49152; //Trigger both buffers.\n", - " seti 0, 0, $1, 0; //Start the pulse.\n", - " seti 0, 0, $0, 100; //End the pulse after 100 ticks (260 ns).\n", - " end ;\n", - "freq_i = 100.000000 MHz, phi_i = (323.43, 217.77) deg, mag = (637.87, 634.92), RMS = (1.88, 1.66) ADU\n", - "freq_i = 100.000249 MHz, phi_i = (302.89, 197.23) deg, mag = (638.03, 635.09), RMS = (2.21, 1.64) ADU\n", - "freq_i = 100.000500 MHz, phi_i = (282.21, 176.56) deg, mag = (638.04, 635.01), RMS = (1.86, 1.75) ADU\n", - "freq_i = 100.000750 MHz, phi_i = (261.55, 155.89) deg, mag = (638.13, 635.17), RMS = (1.81, 1.68) ADU\n", - "freq_i = 100.001000 MHz, phi_i = (240.89, 135.23) deg, mag = (637.75, 635.00), RMS = (2.14, 1.69) ADU\n", - "freq_i = 100.001249 MHz, phi_i = (220.34, 114.69) deg, mag = (638.08, 635.03), RMS = (2.01, 1.72) ADU\n", - "freq_i = 100.001500 MHz, phi_i = (199.67, 94.02) deg, mag = (638.02, 635.14), RMS = (2.16, 1.81) ADU\n", - "freq_i = 100.001750 MHz, phi_i = (179.01, 73.36) deg, mag = (638.09, 635.15), RMS = (1.92, 1.73) ADU\n", - "freq_i = 100.002000 MHz, phi_i = (158.35, 52.69) deg, mag = (637.91, 635.10), RMS = (1.91, 1.76) ADU\n", - "freq_i = 100.002251 MHz, phi_i = (137.68, 32.03) deg, mag = (638.00, 635.13), RMS = (1.90, 1.70) ADU\n", - "freq_i = 100.002500 MHz, phi_i = (117.14, 11.48) deg, mag = (637.91, 634.97), RMS = (2.03, 1.71) ADU\n", - "freq_i = 100.002750 MHz, phi_i = (96.48, 350.82) deg, mag = (638.06, 635.07), RMS = (2.01, 1.79) ADU\n", - "freq_i = 100.003000 MHz, phi_i = (75.81, 330.15) deg, mag = (638.04, 635.02), RMS = (2.28, 1.69) ADU\n", - "freq_i = 100.003251 MHz, phi_i = (55.14, 309.49) deg, mag = (638.21, 635.15), RMS = (2.00, 1.66) ADU\n", - "freq_i = 100.003500 MHz, phi_i = (34.61, 288.94) deg, mag = (637.89, 634.84), RMS = (1.97, 1.69) ADU\n", - "freq_i = 100.003750 MHz, phi_i = (13.94, 268.27) deg, mag = (637.83, 635.05), RMS = (1.94, 1.78) ADU\n", - "freq_i = 100.004000 MHz, phi_i = (353.26, 247.61) deg, mag = (637.74, 634.97), RMS = (2.11, 1.67) ADU\n", - "freq_i = 100.004251 MHz, phi_i = (332.61, 226.94) deg, mag = (637.83, 635.41), RMS = (2.02, 1.76) ADU\n", - "freq_i = 100.004499 MHz, phi_i = (312.07, 206.42) deg, mag = (637.69, 634.95), RMS = (2.00, 1.70) ADU\n", - "freq_i = 100.004750 MHz, phi_i = (291.39, 185.74) deg, mag = (637.72, 635.27), RMS = (1.80, 1.76) ADU\n", - "freq_i = 100.005000 MHz, phi_i = (270.73, 165.08) deg, mag = (638.04, 635.13), RMS = (1.85, 1.67) ADU\n", - "freq_i = 100.005250 MHz, phi_i = (250.08, 144.42) deg, mag = (637.90, 635.25), RMS = (2.01, 1.78) ADU\n", - "freq_i = 100.005499 MHz, phi_i = (229.53, 123.87) deg, mag = (637.97, 634.75), RMS = (1.89, 1.72) ADU\n", - "freq_i = 100.005750 MHz, phi_i = (208.87, 103.21) deg, mag = (638.02, 635.05), RMS = (2.13, 1.83) ADU\n", - "freq_i = 100.006000 MHz, phi_i = (188.20, 82.54) deg, mag = (637.81, 634.85), RMS = (2.00, 1.76) ADU\n", - "freq_i = 100.006250 MHz, phi_i = (167.54, 61.88) deg, mag = (637.85, 634.97), RMS = (1.89, 1.86) ADU\n", - "freq_i = 100.006499 MHz, phi_i = (147.00, 41.33) deg, mag = (638.26, 635.28), RMS = (2.20, 1.70) ADU\n", - "freq_i = 100.006750 MHz, phi_i = (126.34, 20.66) deg, mag = (638.03, 635.21), RMS = (2.34, 1.75) ADU\n", - "freq_i = 100.007000 MHz, phi_i = (105.66, 0.00) deg, mag = (638.02, 635.01), RMS = (1.87, 1.81) ADU\n", - "freq_i = 100.007250 MHz, phi_i = (84.99, 339.34) deg, mag = (637.83, 635.05), RMS = (2.06, 1.68) ADU\n", - "freq_i = 100.007501 MHz, phi_i = (64.34, 318.68) deg, mag = (637.92, 634.90), RMS = (2.02, 1.70) ADU\n", - "freq_i = 100.007750 MHz, phi_i = (43.80, 298.13) deg, mag = (637.85, 635.15), RMS = (2.12, 1.68) ADU\n", - "freq_i = 100.008000 MHz, phi_i = (23.13, 277.47) deg, mag = (637.84, 634.71), RMS = (2.25, 1.69) ADU\n", - "freq_i = 100.008250 MHz, phi_i = (2.47, 256.81) deg, mag = (637.90, 634.80), RMS = (2.12, 1.67) ADU\n", - "freq_i = 100.008501 MHz, phi_i = (341.80, 236.14) deg, mag = (638.13, 635.10), RMS = (1.83, 1.71) ADU\n", - "freq_i = 100.008749 MHz, phi_i = (321.25, 215.59) deg, mag = (638.03, 635.16), RMS = (2.15, 1.68) ADU\n", - "freq_i = 100.009000 MHz, phi_i = (300.59, 194.94) deg, mag = (637.84, 635.28), RMS = (2.11, 1.72) ADU\n", - "freq_i = 100.009250 MHz, phi_i = (279.93, 174.27) deg, mag = (638.02, 635.22), RMS = (1.96, 1.70) ADU\n", - "freq_i = 100.009501 MHz, phi_i = (259.26, 153.61) deg, mag = (637.81, 634.84), RMS = (1.99, 1.72) ADU\n", - "freq_i = 100.009749 MHz, phi_i = (238.71, 133.05) deg, mag = (638.12, 635.17), RMS = (2.03, 1.67) ADU\n" - ] - } - ], - "source": [ - "nsamp = 10\n", - "\n", - "prog = QickProgram(soccfg)\n", - "prog.memri(1,1,123,\"freq\")\n", - "prog.memri(1,2,124,\"phase\")\n", - "prog.regwi(1,3,32000,\"gain\")\n", - "prog.regwi(1,4,nsamp,\"nsamp: generator will consume 16*nsamp DAC values.\")\n", - "prog.regwi(1,5,0x4,\"b00100 -> phrst = 0, stdysel = 0, mode = 1, outsel = 00\")\n", - "prog.bitwi(1,5,5,\"<<\",16)\n", - "prog.bitw(1,4,4,\"|\",5)\n", - "prog.regwi(1,6,0,\"start time\")\n", - "prog.synci(1000)\n", - "prog.comment(\"Set trigger.\")\n", - "prog.regwi(0,1,0x1,\"Send a pulse on pmod 0_0 (pin 1 on J48 on the ZCU111).\")\n", - "prog.seti(0,0,1,0,\"Start the pulse.\")\n", - "prog.seti(0,0,0,100,\"End the pulse after 100 ticks (260 ns).\")\n", - "\n", - "prog.comment(\"Program signal generators in periodic mode.\") #TODO: make comments sppear in the printout?\n", - "prog.comment(\"Channels 4, 5, 6, 7 -> DAC 229 CH0/1/2/3.\")\n", - "for ch in out_chs:\n", - " # the channel number here is 1-indexed, since it's the tProc channel number for the gen\n", - " prog.set(ch+1,1,1,2,0,3,4,6)\n", - "prog.synci(1000)\n", - "prog.comment(\"Set trigger.\")\n", - "prog.regwi(0,1,0xc000,\"Trigger both buffers.\")\n", - "prog.seti(0,0,1,0,\"Start the pulse.\")\n", - "prog.seti(0,0,0,100,\"End the pulse after 100 ticks (260 ns).\")\n", - "prog.end()\n", - "\n", - "print(prog)\n", - "\n", - "prog.load_program(soc)\n", - "\n", - "# Constant, real envelope.\n", - "# The length must be at least 16 times the nsamp parameter passed to the signal generators.\n", - "xg = np.zeros((16*nsamp,2), dtype=np.int16)\n", - "xg[:,0] = 30000\n", - "\n", - "for ch in out_chs:\n", - " # Set the DAC channels to be in 1st Nyquist zone mode\n", - " soc.set_nyquist(ch=ch,nqz=1)\n", - " # Upload waveform.\n", - " soc.load_pulse_data(ch=ch, data=xg, addr=0)\n", - "\n", - "# Output phase.\n", - "fi0 = 0\n", - "\n", - "fi_v = np.zeros((2,len(f0_v)))\n", - "\n", - "# Load program.\n", - "for ii, f0 in enumerate(f0_v):\n", - " measure_phase_decimated(soc, f0, fi0, fi_v[:,ii])\n", - "\n", - "soc.reset_gens()" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### AveragerProgram\n", - "Instead of writing your acquisition code from scratch every time, it is usually easier to use AveragerProgram, which combines the QickProgram functionality with a set of built-in acquisition methods. AveragerProgram can also use the tProc to run the acquisition in a loop, which is much faster." - ] - }, - { - "cell_type": "code", - "execution_count": 8, - "metadata": {}, - "outputs": [], - "source": [ - "class SingleFreqProgram(AveragerProgram):\n", - " def __init__(self,soccfg, cfg):\n", - " super().__init__(soccfg, cfg)\n", - "\n", - " def initialize(self):\n", - " cfg=self.cfg \n", - " \n", - " # configure the readout lengths and downconversion frequencies\n", - " for ch in range(2):\n", - " self.declare_readout(ch=ch, length=self.cfg[\"readout_length\"],\n", - " freq=self.cfg[\"pulse_freq\"])\n", - "\n", - " idata = 30000*np.ones(16*cfg[\"length\"])\n", - "\n", - " for ch in self.cfg['out_ch']:\n", - " self.declare_gen(ch=ch, nqz=1)\n", - " self.add_pulse(ch=ch, name=\"measure\", idata=idata)\n", - " \n", - " freq=soccfg.freq2reg(cfg[\"pulse_freq\"]) # convert frequency to dac frequency\n", - " self.trigger(pins=[0], t=0) # send a pulse on pmod0_0, for scope trigger\n", - " for ch in self.cfg['out_ch']:\n", - " self.set_pulse_registers(ch=ch, style=\"arb\", freq=freq, phase=cfg[\"res_phase\"], gain=cfg[\"pulse_gain\"], \n", - " waveform=\"measure\", mode=\"periodic\")\n", - "\n", - " self.synci(200) # give processor some time to configure pulses\n", - " \n", - " def body(self):\n", - " self.trigger(adcs=[0,1],adc_trig_offset=self.cfg[\"adc_trig_offset\"]) # trigger the adc acquisition\n", - " for ch in self.cfg['out_ch']:\n", - " self.pulse(ch=ch, t=0) # play readout pulse\n", - " self.wait_all() # control should wait until the readout is over\n", - " self.sync_all(200) # wait for measurement to complete\n", - "\n", - "config={\"out_ch\":out_chs,\n", - " \"reps\":1, # --Fixed\n", - " \"res_phase\":soccfg.deg2reg(0), # --Fixed\n", - " \n", - " \"length\":10, # [Clock ticks]\n", - " # Try varying length from 10-100 clock ticks\n", - " \n", - " \"readout_length\":1000, # [Clock ticks]\n", - " # Try varying readout_length from 50-1000 clock ticks\n", - "\n", - " \"pulse_gain\":32000, # [DAC units]\n", - " # Try varying pulse_gain from 500 to 30000 DAC units\n", - "\n", - " \"pulse_freq\": 100, # [MHz]\n", - " # In this program the signal is up and downconverted digitally so you won't see any frequency\n", - " # components in the I/Q traces below. But since the signal gain depends on frequency, \n", - " # if you lower pulse_freq you will see an increased gain.\n", - "\n", - " \"adc_trig_offset\": 1000, # [Clock ticks]\n", - " # Try varying adc_trig_offset from 100 to 220 clock ticks\n", - "\n", - " \"soft_avgs\":1\n", - " # Try varying soft_avgs from 1 to 200 averages\n", - "\n", - " }" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### Decimated readout\n", - "First, let's run the AveragerProgram in the same mode that we were using before: decimated readout, where we save the full waveform. If you increase the value of `soft_avgs`, the AveragerProgram will average multiple waveforms before giving you the results, so the measurement will take longer (past 10, the readout time is noticeable) but the RMS of the waveform will decrease." - ] - }, - { - "cell_type": "code", - "execution_count": 9, - "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "freq_i = 100.000000 MHz, phi_i = (323.42, 217.77) deg, mag = (637.98, 635.24), RMS = (1.90, 1.69) ADU\n", - "freq_i = 100.000249 MHz, phi_i = (302.88, 197.23) deg, mag = (637.91, 634.95), RMS = (1.93, 1.79) ADU\n", - "freq_i = 100.000500 MHz, phi_i = (282.20, 176.56) deg, mag = (637.82, 635.05), RMS = (2.07, 1.81) ADU\n", - "freq_i = 100.000750 MHz, phi_i = (261.55, 155.90) deg, mag = (637.98, 635.02), RMS = (2.05, 1.74) ADU\n", - "freq_i = 100.001000 MHz, phi_i = (240.89, 135.24) deg, mag = (638.04, 634.95), RMS = (2.09, 1.67) ADU\n", - "freq_i = 100.001249 MHz, phi_i = (220.35, 114.69) deg, mag = (637.88, 635.09), RMS = (2.21, 1.66) ADU\n", - "freq_i = 100.001500 MHz, phi_i = (199.67, 94.02) deg, mag = (638.07, 635.03), RMS = (2.06, 1.74) ADU\n", - "freq_i = 100.001750 MHz, phi_i = (179.01, 73.36) deg, mag = (638.10, 635.05), RMS = (1.97, 1.78) ADU\n", - "freq_i = 100.002000 MHz, phi_i = (158.35, 52.71) deg, mag = (637.91, 635.22), RMS = (1.97, 1.73) ADU\n", - "freq_i = 100.002251 MHz, phi_i = (137.70, 32.04) deg, mag = (637.92, 635.03), RMS = (1.98, 1.74) ADU\n", - "freq_i = 100.002500 MHz, phi_i = (117.15, 11.49) deg, mag = (637.92, 635.09), RMS = (2.11, 1.76) ADU\n", - "freq_i = 100.002750 MHz, phi_i = (96.48, 350.83) deg, mag = (638.13, 635.19), RMS = (2.14, 1.72) ADU\n", - "freq_i = 100.003000 MHz, phi_i = (75.82, 330.15) deg, mag = (637.93, 634.98), RMS = (2.52, 1.73) ADU\n", - "freq_i = 100.003251 MHz, phi_i = (55.15, 309.49) deg, mag = (638.07, 635.13), RMS = (2.21, 1.72) ADU\n", - "freq_i = 100.003500 MHz, phi_i = (34.60, 288.94) deg, mag = (637.97, 635.15), RMS = (2.21, 1.69) ADU\n", - "freq_i = 100.003750 MHz, phi_i = (13.94, 268.29) deg, mag = (638.27, 635.06), RMS = (2.11, 1.75) ADU\n", - "freq_i = 100.004000 MHz, phi_i = (353.28, 247.62) deg, mag = (637.86, 634.91), RMS = (2.09, 1.67) ADU\n", - "freq_i = 100.004251 MHz, phi_i = (332.62, 226.96) deg, mag = (637.91, 635.13), RMS = (2.18, 1.72) ADU\n", - "freq_i = 100.004499 MHz, phi_i = (312.08, 206.41) deg, mag = (637.73, 635.03), RMS = (2.04, 1.68) ADU\n", - "freq_i = 100.004750 MHz, phi_i = (291.41, 185.75) deg, mag = (637.82, 635.15), RMS = (2.09, 1.79) ADU\n", - "freq_i = 100.005000 MHz, phi_i = (270.74, 165.08) deg, mag = (637.77, 635.10), RMS = (2.31, 1.68) ADU\n", - "freq_i = 100.005250 MHz, phi_i = (250.07, 144.41) deg, mag = (637.66, 634.93), RMS = (1.95, 1.72) ADU\n", - "freq_i = 100.005499 MHz, phi_i = (229.53, 123.88) deg, mag = (637.85, 635.08), RMS = (2.24, 1.64) ADU\n", - "freq_i = 100.005750 MHz, phi_i = (208.87, 103.21) deg, mag = (637.72, 635.20), RMS = (2.02, 1.78) ADU\n", - "freq_i = 100.006000 MHz, phi_i = (188.20, 82.54) deg, mag = (637.79, 634.77), RMS = (2.07, 1.76) ADU\n", - "freq_i = 100.006250 MHz, phi_i = (167.55, 61.89) deg, mag = (637.85, 634.97), RMS = (1.96, 1.68) ADU\n", - "freq_i = 100.006499 MHz, phi_i = (147.00, 41.34) deg, mag = (637.96, 635.10), RMS = (2.00, 1.68) ADU\n", - "freq_i = 100.006750 MHz, phi_i = (126.34, 20.68) deg, mag = (637.99, 634.99), RMS = (1.87, 1.78) ADU\n", - "freq_i = 100.007000 MHz, phi_i = (105.67, 0.01) deg, mag = (638.05, 635.02), RMS = (2.04, 1.73) ADU\n", - "freq_i = 100.007250 MHz, phi_i = (85.01, 339.35) deg, mag = (637.87, 634.86), RMS = (2.08, 1.68) ADU\n", - "freq_i = 100.007501 MHz, phi_i = (64.34, 318.69) deg, mag = (638.10, 635.23), RMS = (1.94, 1.76) ADU\n", - "freq_i = 100.007750 MHz, phi_i = (43.79, 298.13) deg, mag = (638.25, 635.09), RMS = (2.01, 1.71) ADU\n", - "freq_i = 100.008000 MHz, phi_i = (23.13, 277.48) deg, mag = (638.20, 635.12), RMS = (2.10, 1.66) ADU\n", - "freq_i = 100.008250 MHz, phi_i = (2.46, 256.80) deg, mag = (638.09, 635.09), RMS = (2.19, 1.72) ADU\n", - "freq_i = 100.008501 MHz, phi_i = (341.80, 236.14) deg, mag = (637.98, 634.96), RMS = (2.22, 1.77) ADU\n", - "freq_i = 100.008749 MHz, phi_i = (321.25, 215.60) deg, mag = (638.29, 635.14), RMS = (2.04, 1.72) ADU\n", - "freq_i = 100.009000 MHz, phi_i = (300.59, 194.93) deg, mag = (638.05, 635.16), RMS = (2.12, 1.79) ADU\n", - "freq_i = 100.009250 MHz, phi_i = (279.93, 174.26) deg, mag = (638.03, 635.07), RMS = (1.98, 1.69) ADU\n", - "freq_i = 100.009501 MHz, phi_i = (259.26, 153.60) deg, mag = (638.16, 635.17), RMS = (2.25, 1.69) ADU\n", - "freq_i = 100.009749 MHz, phi_i = (238.72, 133.06) deg, mag = (638.35, 635.34), RMS = (1.97, 1.72) ADU\n" - ] - } - ], - "source": [ - "res=[]\n", - "config['reps'] = 1\n", - "\n", - "# change this from 1 to 50\n", - "config['soft_avgs'] = 1\n", - "\n", - "# for f0 in [101]:\n", - "for f0 in f0_v:\n", - " config['pulse_freq'] = f0\n", - " prog =SingleFreqProgram(soccfg, config)\n", - "# print(prog)\n", - " data = prog.acquire_decimated(soc, load_pulses=True, progress=False, debug=False)\n", - "# print(data)\n", - " res.append([calculate_phase(d) for d in data])\n", - " print_results(res[-1])\n", - "fi_v=np.array([[a[0] for a in r] for r in res]).T\n", - "\n", - "soc.reset_gens()\n" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### Accumulated readout\n", - "Since the demodulated waveform is constant over the acquisition window, we don't really need to save the full waveform. In other words, we should use the QICK's accumulating buffer (which sums the values in the window) instead of the decimated buffer.\n", - "\n", - "Since we now get one number per acquisition, the RMS is now calculated over acquisitions, not over waveform samples.\n", - "\n", - "You should see that a \"repetition\" takes much less time than a \"soft average.\" Normally, decimated readout is only used for finding the correct window to accumulate over, or for debugging." - ] - }, - { - "cell_type": "code", - "execution_count": 10, - "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "freq_i = 100.000000 MHz, phi_i = (323.43, 217.78) deg, mag = (637.98, 635.13), RMS = (0.13, 0.14) ADU\n", - "freq_i = 100.000249 MHz, phi_i = (302.88, 197.23) deg, mag = (638.04, 635.22), RMS = (0.13, 0.14) ADU\n", - "freq_i = 100.000500 MHz, phi_i = (282.22, 176.57) deg, mag = (638.14, 635.35), RMS = (0.14, 0.13) ADU\n", - "freq_i = 100.000750 MHz, phi_i = (261.56, 155.90) deg, mag = (638.07, 635.25), RMS = (0.13, 0.15) ADU\n", - "freq_i = 100.001000 MHz, phi_i = (240.89, 135.24) deg, mag = (638.00, 635.29), RMS = (0.12, 0.15) ADU\n", - "freq_i = 100.001249 MHz, phi_i = (220.35, 114.69) deg, mag = (637.94, 635.31), RMS = (0.14, 0.14) ADU\n", - "freq_i = 100.001500 MHz, phi_i = (199.68, 94.03) deg, mag = (638.01, 635.25), RMS = (0.13, 0.14) ADU\n", - "freq_i = 100.001750 MHz, phi_i = (179.02, 73.37) deg, mag = (637.97, 635.29), RMS = (0.14, 0.13) ADU\n", - "freq_i = 100.002000 MHz, phi_i = (158.36, 52.70) deg, mag = (638.08, 635.32), RMS = (0.15, 0.15) ADU\n", - "freq_i = 100.002251 MHz, phi_i = (137.69, 32.04) deg, mag = (637.90, 635.21), RMS = (0.14, 0.13) ADU\n", - "freq_i = 100.002500 MHz, phi_i = (117.15, 11.49) deg, mag = (638.06, 635.25), RMS = (0.15, 0.14) ADU\n", - "freq_i = 100.002750 MHz, phi_i = (96.48, 350.83) deg, mag = (638.04, 635.23), RMS = (0.14, 0.14) ADU\n", - "freq_i = 100.003000 MHz, phi_i = (75.82, 330.16) deg, mag = (638.05, 635.26), RMS = (0.13, 0.13) ADU\n", - "freq_i = 100.003251 MHz, phi_i = (55.16, 309.50) deg, mag = (637.93, 635.21), RMS = (0.13, 0.15) ADU\n", - "freq_i = 100.003500 MHz, phi_i = (34.61, 288.95) deg, mag = (637.97, 635.20), RMS = (0.14, 0.13) ADU\n", - "freq_i = 100.003750 MHz, phi_i = (13.95, 268.29) deg, mag = (638.15, 635.41), RMS = (0.14, 0.15) ADU\n", - "freq_i = 100.004000 MHz, phi_i = (353.29, 247.63) deg, mag = (637.92, 635.14), RMS = (0.15, 0.13) ADU\n", - "freq_i = 100.004251 MHz, phi_i = (332.62, 226.96) deg, mag = (638.05, 635.30), RMS = (0.13, 0.13) ADU\n", - "freq_i = 100.004499 MHz, phi_i = (312.08, 206.42) deg, mag = (638.06, 635.21), RMS = (0.13, 0.14) ADU\n", - "freq_i = 100.004750 MHz, phi_i = (291.42, 185.76) deg, mag = (637.92, 635.23), RMS = (0.13, 0.15) ADU\n", - "freq_i = 100.005000 MHz, phi_i = (270.75, 165.09) deg, mag = (637.94, 635.21), RMS = (0.15, 0.14) ADU\n", - "freq_i = 100.005250 MHz, phi_i = (250.09, 144.43) deg, mag = (637.91, 635.29), RMS = (0.14, 0.13) ADU\n", - "freq_i = 100.005499 MHz, phi_i = (229.54, 123.88) deg, mag = (637.94, 635.23), RMS = (0.13, 0.14) ADU\n", - "freq_i = 100.005750 MHz, phi_i = (208.88, 103.22) deg, mag = (638.19, 635.34), RMS = (0.15, 0.14) ADU\n", - "freq_i = 100.006000 MHz, phi_i = (188.21, 82.55) deg, mag = (638.13, 635.35), RMS = (0.13, 0.12) ADU\n", - "freq_i = 100.006250 MHz, phi_i = (167.55, 61.89) deg, mag = (638.07, 635.28), RMS = (0.14, 0.16) ADU\n", - "freq_i = 100.006499 MHz, phi_i = (147.01, 41.35) deg, mag = (638.14, 635.44), RMS = (0.13, 0.14) ADU\n", - "freq_i = 100.006750 MHz, phi_i = (126.34, 20.68) deg, mag = (638.12, 635.37), RMS = (0.13, 0.14) ADU\n", - "freq_i = 100.007000 MHz, phi_i = (105.68, 0.02) deg, mag = (638.14, 635.39), RMS = (0.14, 0.13) ADU\n", - "freq_i = 100.007250 MHz, phi_i = (85.01, 339.35) deg, mag = (638.07, 635.31), RMS = (0.13, 0.14) ADU\n", - "freq_i = 100.007501 MHz, phi_i = (64.35, 318.69) deg, mag = (638.22, 635.30), RMS = (0.13, 0.14) ADU\n", - "freq_i = 100.007750 MHz, phi_i = (43.81, 298.14) deg, mag = (638.15, 635.28), RMS = (0.14, 0.15) ADU\n", - "freq_i = 100.008000 MHz, phi_i = (23.14, 277.48) deg, mag = (638.24, 635.35), RMS = (0.14, 0.14) ADU\n", - "freq_i = 100.008250 MHz, phi_i = (2.48, 256.81) deg, mag = (638.34, 635.30), RMS = (0.14, 0.13) ADU\n", - "freq_i = 100.008501 MHz, phi_i = (341.81, 236.15) deg, mag = (638.24, 635.47), RMS = (0.14, 0.14) ADU\n", - "freq_i = 100.008749 MHz, phi_i = (321.27, 215.60) deg, mag = (638.25, 635.39), RMS = (0.13, 0.14) ADU\n", - "freq_i = 100.009000 MHz, phi_i = (300.60, 194.94) deg, mag = (638.22, 635.37), RMS = (0.13, 0.15) ADU\n", - "freq_i = 100.009250 MHz, phi_i = (279.94, 174.28) deg, mag = (638.16, 635.47), RMS = (0.12, 0.14) ADU\n", - "freq_i = 100.009501 MHz, phi_i = (259.27, 153.61) deg, mag = (638.18, 635.43), RMS = (0.13, 0.14) ADU\n", - "freq_i = 100.009749 MHz, phi_i = (238.73, 133.06) deg, mag = (638.10, 635.42), RMS = (0.14, 0.14) ADU\n" - ] - } - ], - "source": [ - "# change this from 10 to 1000\n", - "config['reps'] = 1000\n", - "\n", - "config['soft_avgs'] = 1\n", - "res=[]\n", - "for f0 in f0_v:\n", - " config['pulse_freq'] = f0\n", - " prog =SingleFreqProgram(soccfg, config)\n", - " avg_data = prog.acquire(soc, load_pulses=True, progress=False, debug=False)\n", - " data = [[prog.di_buf[i]/config['readout_length'], prog.dq_buf[i]/config['readout_length']] for i in range(2)]\n", - " res.append([calculate_phase(d) for d in data])\n", - " print_results(res[-1])\n", - "fi_v=np.array([[a[0] for a in r] for r in res]).T\n", - "soc.reset_gens()\n" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### Summary, and RAveragerProgram\n", - "This mode (AveragerProgram with accumulated readout) is one of the typical ways that we run the QICK.\n", - "\n", - "The other way uses RAveragerProgram, which has a tProc program with two nested loops: an inner loop for repetitions (just like AveragerProgram) and an outer loop for sweeping a parameter. Because Python can no longer be the bottleneck limiting the measurement speed, this is often much faster.\n", - "\n", - "However, RAveragerProgram cannot be used for this particular measurement because we need to sweep the frequency of both the DAC and the ADC simultaneously - the tProc can control the DAC frequency, but not the ADC frequency. " - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### Analysis\n", - "Now we can plot the phase as a function of frequency.\n", - "\n", - "As explained at the beginning, this data can be represented as the sum of a phase offset and a time delay. Over a small frequency range, this looks like a linear dependence on frequency." - ] - }, - { - "cell_type": "code", - "execution_count": 11, - "metadata": {}, - "outputs": [ - { - "data": { - "image/png": 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Frfd5JkSEq1rWoketLEOw0KyLyp63gPJREFOPVTJNxxKo4shiYYZPLRkZeNI60tBRnle/28biTfsZN7AFTWuWD59tp8GfEccJIBkYZL5PBA4H3KIYp0mNcswe0oF7ujVk9prd9Bq/hF8+matDHyHg8IlcPF4VcSMWX8r1vviUuqi7dpbjk5/+0nVRYaKkApQBwwyfJnfpxPP9m/POLa05dNxFv1eWM+HbzbiXLY+oZ4g/I5YpgBdj/ZSngSxgFkY1vsYPbAkW7u15Dj2aVOWNF6Zx7hPD8XjdWOx2RM8aCxqRENYoFLMuSjIyONqyHZ4/k3ho1nrmb9jLmKubU7VcUrgtjCscppxLpI1yu55bhQXDO/PknF9Z8t4c7vxkBFZv5Mw89WfE0lYpNQTIAVBKHUIn70tE81oVeKnKIexeN1YzMffnrLnhNitmiZjeZ2GYvdOqvboy7b/tePLyJqzYfoCe45fwxS+79OglhOSpD1dKjrx7pkJpGxOuvYAxlQ5idRszT4mQmaf+OJZcU3xSwUm1Yl3ZVULyCxYO31eeJ+f8yglX5CbmopWT8fII632eCYtFuKVDfeYN7cxZqckM+2QNLzzxDseeHBUxYY9YxpHtpHypRGwJkTtP6exrLseaZDxDsNmMWpcw408obBLwOVBVREZjSNmPCIpV8YSPYCEdOtL8cArvfv8H323O5MUBzbmwbkq4LYwZToY1In3EUgD1Kycz4472fPnqTHoNvdMQLHz+2ZgQLIxkgi7nEgjM8CkZGRFTQFlkx6KU+khEVgPdMVZ37KeU2hg0y+IJs+o2CXgS6NmkKg/MXMeAV1fwZOpRBh3fTmL3bhFxw0QzjmwniVaJ2ll4VovQ78hWlPIgyovb6eLLidPo1OJCKpSO8IdflBKJ09MLxKdyPxIo8vhODA2MVkAlpdRk4JiI/EvuXlNy2jeszPxhnXig3EEGPHQLlscf14KFAcCR5aRSsj18ci6BIJ9g4fu2elw8fgmLNu4Lt2UxiSPbFXwl7BjEn8DhFCCNf6YbZwGvBNwiDQBlkxK5k50k+QgWLn1jJi63TmsVF0e2M+Jm9/hNPsHCJ577L5WSbQx+bxUPzFjL0Zz41oMNNI4sZ3hrWKIUf3IsbZVSLUXkFzBmhYlIlP+XRjhduiA+goXjc6vjnLKccQNbcG61cuG2LuoIukptqPAJezQFZv9fByYt2sLUjG0s3+pg6lkuWmxbEzHx9mglJ9dDltMd+TmWCCRks8JEpLaILBaRjSLyq4gMNbeniMhCEdli/q5obhcRmSQiW0VknYi09MPW2CCfYOH/Hr6BfUdzuPzlZbyyeKuWW/eTqImX+4k9wcoDvc5l1p3tabl7E2df3w+PloQpMVFR9xShFGdWWJVizgpzA/cppX4WkbLAahFZCNwCLFJKjRGRhzHWtn8IuARoZP60xVBSbuvH9WIDn95pL6BV3YqMnL2Bsd/8zsLf9jG5fg611q7UvdNCUEpxIFZGLKfhgjoVGV/1MFZTsNCd42TPZ3Opre+LYhHNswjDTZFGLGbifgnwIPAcsAdjVtiMol5IKbUnb+0WpVQWsBGoCfTFkODH/N3PfN0XeF8Z/ABUMPXJ4ppKZey8cl1LJg26gHJrfqJSXy1YWBSOnnDj8nhjPqyRvy5q6L7yPPPVb+Tk6roof8krqA3rMgtRSpFGLEopJSJfKKUuBDaV9KIiUg+4APgRqKqU2mNeZ4+IVDF3qwn87XPYTnPbnnznuh24HaBOnTolNS0qEBGuaFGDbjWysHncJwULj85dQEXdOy2Qf4ojY/wh4VMXpdp3pMmhCry5bAeLf9/PuIHnc37tIC9YFUOcDIXF+j0TBPzJsfwgIiXWBRORMhgaY8OUUkfPtGsB2/6lZaGUel0p1Uop1So1NbWk5kUVZXr3OFWwcFc5PvjhTy35UQBxFS83JWFKXdSJZ/o144PBbTju8nDVlOWM/WYTrqXLIkqwMFLJu2cqJcf2KDcY+JNj6QrcISJ/AMcwHvxKKdW8qCcQkUQMp/KRUuozc/M+EalujlaqA/vN7TuB2j6H1wJ2+2Fv7OMjWJh9YRoJf5di5Bcb+GbDXp7v35yaFUqF28KIIa4cSz46NUrlm+GdGfXlb6z48Cvu/mQEKoIECyMVR7aLskkJJCVaw21K1OGPY7mkJBcy8zRvARuVUi/5fDQHuBkYY/6e7bP9/0RkOkbS/kheyEzjg5ncTwXeV4ppK/9i9Ncb6T1+CSMvb8IA19/Id9/FfXI/86QAZXz2PsslJTJ2QAu2fv8pCe5cRHnxOl2o9MVY4/i+OBOZ2bqGpbj441iuLmDbERFZrZRaU4TjOwA3AutFJG//RzEcyqciMhj4CxhgfjYXuBTYChwHbvXD1rhERLi+bV06NUzl/plrmT7xE/p+OgKbR/dOHdlOrBahYpxLnzQceBnqtfF4nC5cFiuPH0zh9n1ZNKpaNtymRRwRsYx1lOKPY2ll/nxpvu8D/IQRHpuhlHrhTAcrpZZRcN4EDP2x/PsrYIgf9mlM6lQqzfTb2vHzz59hzTV7py4XsngxEq+OJctFSrINiyWK5VwCgRk+tWZksKZ2UxbtSGL2y8u47+Kz+W+nBljj/e/jgyPbyTnVtMMtDv44lkpAS6VUNoCIPAHMBDoDq4EzOhZNaLFYhFa3XIX3/Vdwu5zkipXJrur8J9tJpTjshcVqcWSxMMOnacCCbCePfb6e5+ZtYsFv+3i5Xg411vwY96FTMHIsHfQ9Uyz8cSx1AJfP+1ygrlLqhIg4A2uWJiCkpWFJXwSLFzOvfCPe2F2G6eOXMPrKZvRuWi3c1oWUqJA/DwOVy9h59YYLmb1mNzMnf0rFex7G63Ujcb6aqcvt5ciJXN0ZKSb+OJZpGFOO85LrlwMfi0gy8FvALdMEhrQ0LGlpXAWctzeLez9dwx0frubKC2ry5OXnUb50dErI+4sj28VZqWXCbUZEIiL0u6Am3Wtln1IXlTV3ARXi1LEcOBa/swgDQZHrWJRSo4DbgMPAEeAOpdTTSqljSqnrg2WgJnCcU60sXwzpwLAejfhy7W56TviO1dO/jvmaBqUUmdlOXehWCGULqIv6eOVfcVkX5cjKk3PRo9ziUOQRizlduDFQXin1tIjUEZE2SqmVwTNPE2gSrRaG9TibHo2r8sYLH9HkieF4vG4sMRz6yHK6cbljX86lxPjURWW1bAd/leKRz9Yzf8NexlzdjOrl46cuSlfdlwy9Hkuc0rRmecZVOYTd68bq9eLJcfLnrK/DbVZQcGTpsEaRMav2q/TqyoeD2/J03/NYueMgPccvYdbqnXEzejkpAaTvmWLhj2Npq5QaAuSAsR4LoLuAUUxCt1MFC4fvq8Djszdw3OUOt2kBRavUFg+LRbgprR7zhnbinKpluW/GWsY88Q7ZT46K6dApxLdSQyDwJ3lfovVYNBGIj2ChdOjE+UdSeHv5Dr7bnMm4AS1oVS8l3BYGBP2QKBn1Kifzyf/S+OrVWfQceieJHjeeMc9iXZwek6FTMHIsyTYrpWxazqU4hHI9Fk0kYtY02IHHgZ7nVeWBmWsZ8NoK/tuxPveXO4h92dKormv4J16uB9jFxWoR+h7ZglIeRHlxu1zMmfARnZpfSMUYFGl06MkeJcKfWWEfUYL1WDTRQbsGlZg3tDOD2tRh9fS5qO49UCNHQhSv9+LIciICKXEu51JiunRBbDaU1Yqy2fggqT4Xj1/Cwt/2hduygKMLakuGPzkWlFKblFKvKKUmK6U2BssoTXgpY0/g2SubMa7KYUOw0OPB43ThTl8cbtOKRWa2i5TSNhKsft3umvz4LJWduDidp567jcplbNz2/irun7GWozm54bYwYOiC2pJRaChMRO490+f5lIo1MUT9/n1QU186KVj4aGZFbtt9lCY1yoXbNL/Qvc8A4rNUdhNgzv915OX0LUzJ2MbyrQ6mNHBywfa1UR06BWPCR+sYyTGGg6LkWPJU2M4BWmPI2YNReb8kGEZpIgQfwcL1dZuzdLudr15ZxtDujbjjorOiZgRgxMt17zMY2BIs3NfzHLo3rspbL3zEuY/fG/V1UW6Pl0PHXbozUgIKdSxKqacARGQBhghllvn+SUDnWGIds4faBlh4zMXI2Rt4ccFmFv62j1fq51Br3U8R3zt1ZDtpWadiuM2Iac6vXYGXqh7G6nVj8Xpx5zjZ/dlc6kTwfXE6Dh5zoZQujiwJ/nQ584tQuoB6AbVGE9FUTLYx+bqWTL7uAiqsXUWlfn3wjhiBivDEviNL9z5DQWL3U+uihu0rz9Nf/sYJlyfcpvnFP8WRepRbXPyZbvwBsFJEPseoZbkSeC8oVmkimsua16BLzSxseb1Tp5OsrxdQMQJ7p8ecbk7kerRjCQU+dVF06EizQxV5e/kOMn7fz4sDW0TNqFEX1JYcf6Ybj8ZYxfEQhhDlrUqp54JlmCayKdOrBxa7IViYawoWvr/iD7zeyJL8+Kc4Uvc+Q4IpCZPUuRNP9W3KR/9ti9Ptpf/U7xkzbxOupcsiXvRUSwCVnKLMChNzNUeUUj8DP59pnzOc523gMmC/UqqpuS0F+AQjpPYHMFApdcgUvJyIsTTxceAW89qaSMFHsPBYqzQS/y7N47N/Zf6GvbzQvzm1KpYOt4WAFhMMNx0aVmb+sE6M/nojK6d9hfeTEShvZC+Vre+ZklOUEctiEblbROr4bhQRm4h0E5H3gJuLcJ53gd75tj0MLFJKNQIWme8BLgEamT+3A1OLcH5NqDF7p5Uv7sJ7t7bmuauasfbvw/SesJRPfooMufVMU/5ciwmGj7JJiYy5ujljUw+drIvyOl14IrQuypHtJCnRQrKWcyk2RXEsvQEPxqJeu0XkNxHZAWzBUDoer5R6t7CTKKWWAAfzbe7LP3ma94B+PtvfVwY/ABVEpHoRbNWECRFhUJs6zB/WmaY1y/HQrPWMHvE2WU+EV7BQ64RFDmcNuAxrkh2PxYrTYuWhAxX5fW9WuM36F45sY7KHETjRFIeiTDfOwZDMnyIiiUBl4IRS6nAArl9VKbXHvM4eEalibq8J/O2z305z2578JxCR2zFGNdSpUyf/x5oQUzulNNP+2465b3xG9/+7i0SPG/fzz2JNX4S0bx9ye/IcSyWdYwk/PnVRa2s3Y/EOO3NeXsawixtxe6cGEVMXpQtqS46/ki65Sqk9AXIqZ6KgrkKBcRWl1OtKqVZKqVapqalBNktTFCwW4bKDm0lSHhKUF1wuvpjw0cmHfChxZDupUDqRxAh5aMU9Zvi03Q2XsWB4Z7o3rsIL83+n/6sr2JaZHW7rAMjM0o6lpIT7v21fXojL/L3f3L4TqO2zXy1gd4ht05SEfIKFH5c6i57jlzBv/b8GnUFF17BELpXK2JlyfUsmXns+OxzHuHTiUr58dRbeZ58Nc/jURapWaigRfjkWM2EfyPVJ5/BP4v9mYLbP9pvEoB1wJC9kpokS8gkWPvPCbdSsUIo7P/qZodN/4fBxV+HnCABaTDCyERH6nl+ThcM7czO76XH3dagRI/F2C0/RrcerOHhMj1hKij9r3g/FWLIjR0SOAq8opSb7cfzHQBegsojsBJ4AxgCfishg4C9ggLn7XIypxlsxphvfWtTraCIIH8HCs4HP7mrP1IxtTFq0hRXbDjClgZNWf6wLqiSMI9tJ05rlg3JuTeCoUi6JR0rvQ3k9WJRRdLv2/c85v127kCbRDx134VV6skdJKUodywSM2pWhQGOl1H5z9cinRGSUUmpkUS6klBp0mo+6F7CvAoYU5bya6CHRauGe7o3odm4V3hr7Eec9OTzogoV5M3w0kY907YrYbSiXC48lgVHZVUh+eyXPX92cGhUCGSg5PZm6ODIgFCUU9h3QEGM22Pci8jMwFtgGXCsiFYJonyYGaVqzPGNTD2H3urF6vXhynPwx8+uAXycn10O2002qLnSLDnzCp7aMdK4cMoDVfx6i1/glzFj1d0jqorRSQ2AoynTjz4HPzVzHcIwpvy2A5kAKkCEiZZRSDYNqqSamSOjWDUaPRrlcuC0J3Lu/Aud9sYGHLzmXZLs/Enan55/ep35IRA1m+FSAG4HOjSrzwIx1PDBzHVtmL+ABFhrzAAAgAElEQVQe627K9OoR1NAp6Kr7kuLPf/AQ4FNgDbAeaAysV0p1ERH9n6vxDx/BQunYiZZHUnhr+Q6+25zJiwNa0KZ+yRdZ0sWR0U/dSslMv70dX702i4vvMeqiPGOexbo4PTih0ywtQBkIiuxYlFJbRKQtcDFwPrAOeND8LDRTfDSxhdk7tQMjgJ7nVeP+GWu55vUVDO5QnwfKH8S+bGmxk/tapTY2sFiEKw5vQSkPory4XS5mT/iITs0vJCU5sH1aR7YTm9VCuaTAjJrjFX8LJF1Kqa+VUqOVUi8rpQ4FyzBN/NGmfgrzhnbihrZ1+fmTuajuPVAjR0Ix13vRYY0YIl9d1IdJ9ek5/ju++XVvQC+TaU5P13IuJSPcBZIazSkk2xMY1a8pL1U5fFKw0ON04U5P9/tcefLnlQLcq9WEgXx1UU+PuY0qZZP43werufeTNRw5nhuQyziyXbojEgD0eE8TkdTr3wc19SU8Thcui5VHMyvy391HOK9G0WtSHNlOyiYlkJSoVWpjAp+6qMbAF0M6MHnxVl5ZvJXl2xxMbeCk5Y6S1UU5spxUL58UOJvjFO1YNJGJj2DhhnrNWbbdzpeTl3NP90bc2eWsIml/ObJdWi4/hrElWLj34rPp0bgKb74wjcZPlLwuypHtpJkuqC0x2rFoIhezh9oaWHDMxRNzfuWlhZtZ+Ns+xg1swdnbN0BGxml7qJlapTYuaF6rAuOqHMKat1R2jpNds76mrp+OxetVHDjmorLWCSsxOseiiQoqJtuYNOgCpl7fkl2HTzDiwTfI7drtjMl9R7ZTPyTihMTu3bDY7SirFXdCIsP3VeDJOb9ywuUp8jkOn8jF41W6MxIAtGPRRBWXNKvOguGdGXRiG+JyIR4PyuUyRi750PLncYRPcl++/ZbmAy7h3e//4NJJS1n9Z/71BQtG1z0FDh0K00QdlcvY6Tfsejxz3sbtcpErVtJTzuYSr8JiMaaJ5uR6yMpx64dEPOFTF/Uk0Ou8ajwwcy0DXl3BbZ0acG/ZA2esi3JonbCAoR2LJiqR9u1JWJxO1vxvmeCuwVs7kkh780de6N+c2imlOXBMF0fGO2lnVWL+sM6M/nojP338NeqTESivG7HZoIDkfqY5YtFrsZQc7Vg00UtaGmXT0hihFGev+ptRX22k94QljLisCY2rlwO0Tli8U8aewHNXNWP7sulGXZTy4nW68KYvJiGfY9FKDYFD51g0UY+IcE3rOswf1okWtSvwyGfref35D7lrxafU3bw23OZpIoAGAy7DmmTHY7HitFh5MLMim/YePWUfR7aTRKtQvlRimKyMHfSIRRMz1KpYmg8Ht2X+m5/Tdcj9JHpysfw0o8CwhybO8KmLWlenGUt22Pny5WUM63E2/+vcgASrBUeWk0rJdi3nEgAi2rGISG9gImAF3lRKjQmzSZoIx2IRLj3wO0q5EeWFvBlj2rFozOR+W4y6qJGzNzD2m99Z8Ns+xg1ooaenB5CIDYWJiBV4BbgEaAIMEpEm4bVKExWYgoVYrWCzGbOANBofUpJtvHJdS14edAF/HjhGn0lLcS//npu/+7hYgqeaU4nkEUsbYKtSajuAiEwH+gK/hdUqTeRj1jScqSpfowG4vEUN2jZI4c0XpjH8vYewed0w910dPi0hkexYagJ/+7zfCbTNv5OI3A7cDlCnTp3QWKaJfHwECzWaM1GlbBKPlNoLXg/i1eHTQBCxoTCgoAzavxa9Vkq9rpRqpZRqlZqaGgKzNBpNrCFduyJ2HT4NFJE8YtkJ1PZ5XwvYHSZbNBpNLKPDpwElkh3LT0AjEakP7AKuBa4Lr0kajSZm0eHTgCFK/Su6FDGIyKXABIzpxm8rpUYXsn8m8GcxL1cZcBTz2GgnXtser+2G+G27bnfB1FVKBSyXENGOJZSIyCqlVKtw2xEO4rXt8dpuiN+263aHhkhO3ms0Go0mCtGORaPRaDQBRTuWf3g93AaEkXhte7y2G+K37brdIUDnWDSaCEVEUoFpQCvgM6XU4DCbpNEUiUiebqzRRCQiMhXYrZQaFeRLPQJsUUpdHOTraDQBRYfCNBr/6QAsC8F1egAzQnAdjSawKKWi9gd4G9gPbPDZlgIsBLaYvyua2wWYBGwF1gEtT3POC4H15n6T+CdcWKLzxmC7rzfPtw74HmgRB9/5E8AfGNJC+4DxgAfo73Ouh4GZ+c4/EZhkvn4Io+A3C/gd6F6APTbgiHmdbNO2sH/n5mddgDXAr8B3cfCd5523PPAlsNZs+60x1u4BZru8QKt8xzxi7v870KtItofixgjiH74z0DLfH/4F4GHz9cPA8+brS4F55hfQDvjxNOdcCaSZ+80DLgnEeWOw3e19bupLQtHuMLf9G+Av4ArzH6wdxoM/nVMdS13gOFDOfG8F9pj7n4MhrFrD/KwecNZpbGoC7IuAdvuetwKGungd832VGP/Ofc/7qM/rVOAgYIuhdjc2788MfByLeR+uBexAfWAbYC3U9lDcGEH+49fL94f/Hahuvq4O/G6+fg0YVNB+PtuqA5t83g8CXivpeWOx3fmOrwjsitXvHCiL4Sy2AUOA6cAw4ACGw+mf75zLgJvM1xcD28zXDTF6oD2AxELaeB2wIJK+c+Au4JlQfc8R1vZHgCkYD+T6GD14S6y022dbBqc6lkeAR3zefwOkFWZ3LOZYqiql9gCYv6uY2wuS4a+Z79ia5vaC9inJeUNBqNvty2CM3k+4CHbbu2H8o6YALTAczJUYk19yCrBnGsY/LRgOYppp21YMh/QksF9EpotIjdO06XyMnuKZCPV3fjZQUUQyRGS1iNxUiH3BJNRtn4zRq9+NEUoaqpTyBqYpfhGsdp+OYj3fYtGxnI6iyPAXSao/AMeEkmC12zhQpCuGY3nIT7tCQaDaXg0j9AHGA78T8AlGHuRQAcfPALqISC0MBzTt5ImVmqaU6ogRMlPA86exvQWFO5bTEazvPAEjRt8H6AWMFJGz/TcvqASr7b0wcks1MO6BySJSzn/zgkZEPd9i0bHsE5HqAObv/eb2osjw7zS3F7RPSc4bCkLdbkSkOfAm0FcpdSBA7SgOwW77JoxakkNAU+AsDHHUUkB/YIqI9Ms7gVIqEyOk8A6wQym10bTtHBHpJiJ2jJHOCYzkf0EUxbGE416fr5Q6ppRyAEtMO8NBqNt+K0YtkTJHnjuAcwPUFn8IVrtPR7Geb7HoWOYAN5uvbwZm+2y/SQzaAUfyhpR5mO+zRKSdiAhwU77ji3XeEBHSdotIHeAz4Eal1OYgtamoBLvtSzAe8jWAJIyZWoOVoQY7E7hLKfVFPpumYeRSpvlsswNjMFRm92KEMR7N3xgRqYaRt9oU5nbnP+9soJOIJIhIaYwVXTcWYmOwCHXb/wK6A4hIVYxE9/aAt6pwgtXuM13vWhGxm0uYNMKYAHBmgp18CnJi62OMGTe5GJ51MFAJWIQxHW8RkGLuK8ArGPHx9ZyaoFrj87oVsMHcbzL/TMfz+7wx3u43MXrwa8yfVXHwnQ/G6LH72vMu+ZL3MdjuFJ9jHsCYGbYBGBYH33neeWsAC8xzbgBuiLF2X2lew4kxlf4bn2MeM/f/HXMWWWE/WtJFoykiIvI4UEkpNTTctmg0kUwshsI0mmBxDhDusJ9GE/HoEYtGo9FoAooesWg0Go0moMSUunHlypVVvXr1wm2GRqPRRBWrV692qACueR9TjqVevXqsWrUq3GZoNBpNVCEifwbyfDoUpgkeK1bAc88ZvzUaTdwQUyMWTQSxYgWqe3dwuRCbDRYtgrS0cFul0WhCgB6xaIJDRgZepxPxePA4XbjT08NtkUajCRHasWiCQ5cuuK2JuMWCy2LlgcyKbNh1JNxWaSIdHT6NCXQoTBMc0tJ4+K7xdNi5gXpXX8ry7Xa+fGU5d3drxF1dzyLRqvs0mnysWIG3W3ckV4dPox39360JGstSG7Hy2ttpNagPC4Z35rLm1Rn/7WaumvI9m/dlhds8TYRxdP7Ck+FTr8sFGRnhNklTTLRj0QQFr1dx8JiLymXsAFQobWPCtRfw6g0t2X34BJdNWsbnU2bgffZZHfbQALC7RVtyrQm4xYJTrLxprcNxlzvcZmmKgQ6FaYLCoeMuPF510rHk0btpdVrVS+GtF6bRe+gdKI8br92OJV2HPeKdP89pwaPXjmZS9SPMr3wuzxyswIcTlzJuYAsurJsSbvM0fqBHLJqg4Mh2AVC5rP1fn1UuY+fBpD3YvR6syovX6WTVe5/h9WrdunjGke3k55qNSXjsMf774PV8fFs73F5F/1dX8NzcjeTknm5NNE2koR2LJig4sp0ApJb5t2MBkK5dsdhtKKsVT0Iizx6rynVv/sDfB4+H0kxNBOHIMjojlcrYAEg7qxLzh3Xm2tZ1eG3Jdh687zX2PPy4Dp1GAToUpgkKJx1LWVvBO6SlwaJFSEYGtosu4prEWoz6aiO9JyzhsT5NGNSmNsYid5p4wZHtpELpxFNmDJaxJ/DcVc0YmPs3jW+8lwR3LrkTxsLCb0ns1CGM1mrOhHYsmqCQmWU4lvw5llNIS4O0NAS4BujQsDIPzlzHo5+vZ/6ve3mp9nEqr1oBXbro/Esc4Mh2nvZ+uWD7WpTXjSgvbpeLD59/n7YNm9G4erkQW6kpCiELhYlIkoisFJG1IvKriDxlbq8vIj+KyBYR+UREbOZ2u/l+q/l5vVDZqik5jmwXiVahfKnEIh9Tq2JpPhzclqf7nkfu0uUkX9ob74iRhjSMDn/EPIZjOc0It0sXo7bFakXsNr6rcR5XTF7GK4u34vZ4Q2uoplBCmWNxAt2UUi2A84HeItIOeB4Yr5RqhLGG+mBz/8HAIaVUQ2C8uZ8mSnBkO6mUbPc7nGWxCDel1WNKzaPYPLlYvB68ThfZ33wbJEs1kYIj23X6Ea4ZOmXUKKzp6Ywbfwe9zqvG2G9+5+pXV7B1f3ZojdWckZA5FmWQ9+0nmj8K6AbMNLe/B/QzX/c132N+3l100D1qcGQ7qXy6/EoRqNinJ5YkO16LFZfFypBdZfl63Z4AWqiJNBxZpw+FAYZzeeQRSEsjJdnG5OtaMvm6C/jrwDH6TFrKnKkzdV1UhBDSHIuIWIHVQEPgFWAbcFgplVcFtROoab6uCfwNoJRyi8gRoBLgyHfO24HbAerUqRPsJmiKyJni5UUiLQ0xk/sHmrfm8I4khkz7mXkbqjOqb1MqJhffaWkij5xcD1lON6kFTE8/E5c1r0Gb+im8+cI0Lr7nTl0XFSGE1LEopTzA+SJSAfgcaFzQbubvgkYn/yp0UEq9DrwO0KpVK10IESE4slycW62EiVUzuV8LmOXx8tqS7Uz4djM/bD/Ic1c14+Ij2w3ZD53cj3ryZhGeNsdyBqqUTeKRUntRXg8W5cXtdLL2/c9p0bYdFosOcoSDsNSxKKUOAxlAO6CCiOQ5uFrAbvP1TqA2gPl5eeBgaC3VFAelFAeOlXDEko8Eq4UhXRsye0hHUsvamfrcB7i6dEWNHAk6uR/1nCyoLeY9k78ualR2FW58+0d2HT4RSDM1RSSUs8JSzZEKIlIK6AFsBBYD/c3dbgZmm6/nmO8xP09XSukRSRRw5EQuuR5VrN5nYTSpUY7ZQzowPHE3ltxcLVgYIziKMj39TOTVRY0ahS0jnf7/N5A1fx2m1/glfPrT3+hHR2gJZSisOvCemWexAJ8qpb4Skd+A6SLyDPAL8Ja5/1vAByKyFWOkcm0IbdWUgH+KIwM3YvHFlmCh020D8H78Km6nk1yx8q7U5kanmzJ2XZoVjZwMhZXknvGpi7oO6NSoMvfPWMuDs9Yxb8MextU+TspPui4qFPj9XygiyUCOmS8pMkqpdcAFBWzfDrQpYHsOMMBf+zThJzOrZGGNIpGWhiV9EZ5F6XxaqgEvOMoxbeISxvZvQbsGlYJ3XU1QyHMslQI4KaN2Smk+vq0d7634g2/e/JxSHz6K1+tG7DZEr/USVAoNhYmIRUSuE5GvRWQ/sAnYYxY5jhWRRsE3UxNN/JOIDaJjAUhLI3HEY9x83yBm/C8NqwjXvv4DT335KydcWrAwmnBkuyiblEBSojWg57VYhFs71P9XXdQxXRcVVIqSY1kMnAU8AlRTStVWSlUBOgE/AGNE5IYg2qiJMkoyw6e4tKqXwtyhnbilfT3eWf4HD9z7Krse1IKF0UJmtvO0gqWBIKVPr3x1UeWYv0HXRQWLooTCeiilcvNvVEodBGYBs0Sk6LodmpjHke3EahEqlg5trUlpWwJPXnEeVzn/4uzr7zMECyeORX27EFunjiG1ReMfhRZHlhSfuqj9zVrj2GHnjg9/pu/5NXjqivOoEOJ7NdYp1LEU5FSKs48mfnBkuUhJtoWthqD51jX/CBbmuvhgzPu0rt+MZrXKh8UeTeE4sp2cU61scC9iJvfrAp97vExZvI2X07ewYtsBnr+6OV3PrRLc68cRRZ5uLCIDRKSs+XqEiHwmIi2DZ5omWilx1X1JySdYuLx2U/pNWc74hZvJ1YKFEckZdcKCQKLVwtAejfhiSAcqlrZx67s/MXn0+zhHPaPDpwHAnzqWkUqpLBHpCPTC0PGaGhyzNNHMGVVqQ0E+wcKXXrqTvi1qMHHRFvq9spxNe4+GzzbNv3C5vRw5kRuWzkjTmuWZc3cHRlU9yuAnb8P6xBN4unXTzqWE+ONY8qbZ9AGmKqVmAzowqfkXjmxXUBOxRcJHsLB86UReuuZ8XrvxQvYdzeHyl5cxc/IMPKO1YGEkcOBYiGYRngZ7gpUbc/4gSXlIUF6U08XCKZ9w3OUu/GBNgfjjWHaJyGsYazLNFRG7n8dr4gClFJnZzpIVugWJXudV45thnflf4n76DL8BRo7E203LwYQbx8m6pzD2U83wqbJaUYk2pkotLpm4lJ/+0CpSxcEfxzAQ+AboZWp9pQAPBMUqTdSS5XTjcnvD+5A4A5XK2Lnfvge714NVefE6nfz07md4vVryI1wEpOq+pPhIwiRmpPPQk7fiVYqBr61g9Ne/kZOr66L8wZ/K+xNAMjAIeBpjPZXDwTBKE72UWPMpFHTpYggWulx4rAk8d7wqCW/8wIv9W1CnUulwWxd3ZOZJAIX7njFnjQG0BeYP7cyzczfyxtIdpG/az9SzXJy9cbWWhCkC/oxYpmCoEQ8y32dhrKmi0ZykpCq1IcFXsHBxOoOGXsPG3UfpPXEJH/7wpxYsDDEhU2rwk2R7AqOvbMb7/2lDg63rqT3gcrwjRuilsouAPyOWtkqpliLyC4BS6lDe+vQaTR6R+pD4Fz6ChQOADg0r89CsdYz4YgPf/LqXl2qfIHW1FiwMBY4sF8k2K6VsgZVzCRSdz06lTfUjJHrdWLzGei8H5synqr4vTos/I5ZcU5lYgSGDD+iiAM0p/BMvj64+R40KpXj/P214pl9T3Mu/p0yf3nhHjNS90xDgiNDJHr4kXdwdq92O12rFbUnk/3aX4+VFW3DruqgC8cexTMJY9bGqiIwGlgHPBsUqTdTiyHIiAilRKJEhItzQri5T8wkWZs/XgoXBJOwFtUXBDJ9aRo3C9c0CqvXuxriFm7lq6vds2ZcVbusijiKHwpRSH4nIaqA7xrLB/ZRSG4NmWQg5/t1SDn69gFpXXqrDHiUkM9tFSmkbCdbonYle4dKeqHHP43W6cFms3LW7LP3X7uby5tUR0UvdBhpHtpP6lZPDbUbhmOHTcsDLQO/zqjHii/X0eXkZL9TI5orDW7B07aqfIfjhWMT4j2oFVFJKPS0idUSkjVJqZfDMCwErVpDYqyfVXC5yJ76I99uF2LVgYbGJit5nYfgIFh5o0YajO5K45+NfmL9hD6P6NqVStLcvwnBku2hdLyXcZvhNn+bVaVM/hbfGfkSvoXeiPG68djuWdL3Wiz/J+ykYOZVuGNONszDUjVsHwa7QkZFBgjv3pGDh+8+9R6u653FBnYrhtiwqMeLl0RcG+xdm77QWMNPj5fWl2xm/cDMrdxxk9JXN6HV0h7Ecsk7ulwi3x8uh46HVCQskqWXtPJS0F+X1YFFGYv+X9z7ngrbtwibCGgn4E69oq5QaAuSAMSsMPyRdRKS2iCwWkY3mImFDze0pIrJQRLaYvyua20VEJonIVhFZFzTBy3yChT/Vbc7VU7/nhfmbcLp1UZS/xMSIJR8JVgt3dWnIl3d3pGq5JF4b8yGuLl1RI0eCTu6XiIPHXCgV5uLIEiJduxp1UVYrnoRERh+rwg1v/cjOQ8fDbVrYCOWsMDdwn1KqMUY9zBARaQI8DCxSSjUCFpnvAS4BGpk/txMswct8goUvjr+D/hfWYkrGNvpOXs6GXUeCctlYxZEVvb3Pwji3Wjm+GNKBexP3YMnNRTwevC6XMXLRFIt/iiOjeJTrWxeVkc7Auwey9u/D9J6wlOkr/4rLuih/QmF5s8KqmLPC+gMjinqwUmoPsMd8nSUiG4GaQF+gi7nbe0AG8JC5/X1lfCs/iEgFEaluniew+FTclgNe6N+C3k2r8dCs9fR7ZTmjq2XTP2sr1m46MXcmjjndnMj1xKxjAUNuveNt/fF+PBW300muWHlH1eLGnFzKJun17vwlKgpqi4JPXdS1GHVRD85cx8OfrWf+r3sZV+s4lVbFT11UkRyLmbhfAgRkVpiI1AMuAH4EquY5C6XUHhHJW22nJvC3z2E7zW2nOBYRuR1jREOdOnWKY06BdDu3KguHV+SdF6dxxX3/A48b7zM6MXcmwrEkcVhIS8OSvghvejozSjXgxcxyfDRhKWP7N6d9w8rhti6qiAoJoGJQO6U0H/23LR/88Cfz3viM0h8+itfrRuw2ZFHsP0OKFAozRw1fKKU2KaVeUUpNLoFTKYOR9B+mlDrTwhgFZb7+NaZUSr2ulGqllGqVmppaHJNOS4XSNoYnnipY+OM7s/BowcICiQgxwVCRlkbCY49x072DmHFHe2wJFq5780eemL1By637QSzfMxaLcHP7ekypmXVqXdQ3sV8X5U+O5QcRKdEMMBFJxHAqHymlPjM37xOR6ubn1YH95vadQG2fw2sBu0ty/WKRJ1hoteJNTOT5E9UY8Or3bM/MDrkpkU6mKX8edjHBEHNh3YrMvacTt3aox3sr/uTSiUvZ+Nk38NxzOrFfCI5sJ0mJFpIjVM4lEKT06YklyY7XYsVlsfJ/u8oxd33gI/qRhD+OpSuGc9lmztJaLyLrinqwGU57C9iolHrJ56M5wM3m65uB2T7bbzJnh7UDjgQlv1IYvnLai9O5+b5BbMs8xqWTlvLO8h1abt2HqNEJCwKlbFaeuPw8Pr6tHefs2EC9a67QgoVFIG9J4pguPDXroizPjMLxxdccbHEhd330M3d//AuHjrnCbV1Q8Cd5f0kJr9UBuBFYLyJrzG2PAmOAT0VkMPAXhiYgwFzgUmArcBy4tYTXLz4+ibm+QLsGlXh41jqe+vI3vvl1LxPr5lD15x/iJjF3OvIcS6VYz7GcgbSzKtGy+lES8gQLc5xkfjGP6nF8X5yJWJyeXiDmM6Q2MMvj5dWMbUxctIUfth9gzFXN6N64argtDCj+OJarC9h2RERWK6XWFPDZKSilllFw3gSMCQH591fAED/sCxlVyyXx9i2tmbFqJ7OnzqTckEfiKjF3OhzZTiqUTiQxiuVcAoG9Rzd4bjRelwu3JYG795QnbcHv3N2tEbaE+P7b5Cczy0mtivG1Bk6i1cLd3RvRrXEV7vt0LYPfW8V9ZQ9wm/cvknp0j4nnhz93eSvgDoyZWTUxZmJ1Ad4QkQcDb1pkIyIMbF2bKbVOFSw8On9huE0LG7Fcw+IXPoKF7gULqXtZD15O30rfV5azcc+Z5qvEH45sJ6mxoNRQDM6rUZ7Z/9eB0VWP8t8nbyPhiSfwdOsWE6FTfxxLJaClUuo+pdR9GI4mFegM3BIE26KC8pf4JuYSuGtnWWat3hmXRVFGWCM+HxL/Ii0NHnmEMl06MW5gC964qRWZWU6umLyMmS9/imf0szHxACkJHq/i4LH47ozYE6xcn/MHScpDgvKinC4WTJnOMWd0zyz0x7HUAXwzTblAXaXUCcAZUKuiCZ/E3OE5c3G2bst9M9Zy+werycyKrz9L3MTLi8HFTaqyYHhn/mfbT597b4SRI/F2i+/E/sFjLrwqPid7nIIpK6WsVlSijVelNpdMXMqP2w+E27Ji40+OZRrGrLC8WVuXAx+LSDLwW8AtiybMxFx1YLpX8fayHYxd8Ds9x3/HqH5NuezYn3EhWOjIdpEag/UIgSIl2cb9tj14fQQLV73zGRe2bYc1DgUL43kW4SnkzTzNyCCxSxcernYO989Yy7Vv/MB/OtTngV7nkJQYXdOx/VmPZZSIzAU6YiTh71BKrTI/vj4YxkUjVotwW+cGdD03lfs+XcvbY6fR89MRJHrchthljCb3c3I9ZDvd+iFRGHl1US4XXmsCY05Uxfr6Cl4c0IK6laJgTZIAEjdKDUXBR1aqDTBvaCfGzNvEW8t2sPj3/Uxt4OScTT9HTee0yKEwsw6lMVBeKTUB2C8ibYJmWZTTsEpZZt3Zngfs8SFYmBf2i7fiSL/JVxd13bBr2bQ3i94TlvLBij/iqi4qlqvuS0qyPYFR/Zry4eC2NNy6njoDo6suyp8cyxQgDRhkvs8CXgm4RTFEgtVC2uD+WOx23BYLTrEy0VODIydyw21awInWte7DgpnYl/bt6X9hLRYM70yrehUZOftXbnp7JZkLMuKiat+RFSMClEGkY6PKTKpxBJtZF+VxOtk3Z364zSqUkK3HEreYgoU8PYrPx77HpOOp9Bq/hO82Z4bbsoASMyq1YaB6+VK8/582PHtlM7zff0+ZPr3xjhgZNb3T4uLIdmKzWiiX5E+qN/5I6tEdq92O12rFbU3k/3aVY9KiLeR6/Fm1JLT4842WdD0rNTUAABRFSURBVD2W+CUtjYS0NK4Dzvv7MPfNWMvNb69kUJs6PNanMWXs0f+PpROxJUNEuK5tHS79yqyLUl48Thcn5n9LmSiIqReHTHN6ekzLuQSCvLqojAxcbTtQfV9ZXlq4mYW/7WPcwBacXbVsuC38F/6MWPKvx7IMeDYoVsUwLWpX4Ku7O3J75wZM/+kvek9YwvoZ86M+9JEnfx7Pci6BoMKlpwoW3rmrLLPX7IrJuihHtkvnV4qKGT4t160zkwZdwNTrW7Lr8Akum7SMV7/bhmf59xH1DPFnVthHIhKQ9VjinaREK49e2piLm1TlnRen0XDEfaYkjD1qJWEc2U7KJSVgT4iuaZERh1kXJRkZHGzRhuw/khg6fQ3z1u/lmSubxtSI0JHlpFr5pHCbEZVc0qw6reun8Njn61nw5ufc+skILN7ImXnqVwxGKbUJ2BQkW+KO1vVSaFHtCFYfwcJ9n8+jZlQ6Ft37DBjm1NOawEyv4o2l23lpwWZ6jV/C6Cub0rtp9XBbGBAc2U6a1iwXbjOilspl7Lx6w4X8tnIWVncuoryQN/M00h2LiNx7ps/zSeBr/MTWvRs8+49g4T17y9F63iaGX9woqnr/mbrqPihYLcIdF51F13OqcN+MNdzx4c8MLZ3JHWonpXpGr2Ch16s4EOdyLoFARDjvuitQb01EuVzGiKVLl3CbVaQRS15m6BygNcY6KWBU3i8JhlFxhU9izpPWkUYHyvPqd9tI37SPcQPOp1mt8uG2sEg4sp00rqZ7n8HinGpl+fyuDnz2ykyuuO9/JHrceMaMxpqeHpXO5fCJXDxepR1LIDDDp5Gk7lGoY1FKPQUgIgswRCizzPdPAjOCal28YIY+kjEWp+nVtBoPz1pHvynLGV01iwHZ27B26xoRN8zpcGQ5qdxQJ+6DSaLVwjXHtqGUB1Fe3E4X8yZ/TMcLWlE2KTHc5vmFLo4MMD6V+5FASUQoXUC9gFqjAaDrOVVYMOwi7i6VSd/7b4p4wUKn28PRHC3nEhJ8BQttNt601qH3hKUs3+oIt2V+kTeLUMu5xCb+OJYPgJUi8qSIPAH8CLwXHLM05UsnMixhN3avB6vy4nU6+eHtWbgjsCjqQF5xpO59Bp98kjCPPTMYe4KF69/8kcdnb+C4Kzrk1jOztQRQLOPPdOPRIjIP6GRuulUp9UtRjxeRt4HLgP1KqabmthTgE4yRzx/AQKX+v707D4+qPhc4/n0zWdnCIpsga6mKICBRiQVLQQSsXrVVKrcVtVquRdRqr49QpS6gtgoVXHBF6eJSRQUUMFIgLIpWlF2NoHBrFIQISsKSIZP3/nEOOhkTMpPMljPv53nyzMyZs/zezDzzO79d97rzks3AWZr4AHC5qr4f7rU8I2TCwnsPtaPy0dVMG9WH7q2bJDp137LBkXEWVO1xCrDgukHcV1DE029tY/nHu3mku5+eRck9YaHN1OBttZZYJGhYrKq+r6oz3L+11e1zFLOBESHbJgBLVLUHsMR9DTAS6OH+jQUeCeP83hNyd3rZ70ezrWQ/58xYyaxV25JmwkKbpTaxcjJ9/PG8njz/mwGcuH0TXX+R/BMWlpSVk+ETcnMaVtuQCU84JZZlIvISME9V/3Nko4hk4kyhfxmwDCfjqJGqrhCRLiGbz8dZ3hicarVC4GZ3+9/cde/fFpHmItJeVXeEkV5vce9OBeefkt+tFRNf3sjk1z6gYPNOHuh8iHZr307o3alNJpgcTu/Win7t9lUZF7Vr7iKOTcJSS0lpOa0aZ5GWguvQpIJw2lhGAAGcRb2+EJEPRGQbsAVnpuP7VXV2Ha/f9khm4T62cbd3AD4L2q/Y3fY9IjJWRNaIyJrdu701sWN12jTL5snL8rj3opPJfOdtcs8bmfC702/ry62NJeEyzxry3YSF6RlctyOXqQVF+CuSq22upKzcZsL2sHC6Gx/CmTJ/pohkAMcAB1X16ximq7rbmGrrfVT1ceBxgLy8vOSoG4oxEWFU3nEM71haZcLC/YsW0ywBd6clZeU0yUpvcKvceVLQuKiK/IF02d2Mh5Zt5V8ffslfRvWl57HJMdaopMwGR3pZJL3CUNXDqrojipnKlyLSHsB93OVuLwaOC9qvI/BFlK7pGbkjhwVNWJjOuOKmvLjms7hPWOj8SNjdZ9JwJyxsMngQUy/uw5Nj8igp83P+w6t4cMkWKla9mfAJC0tspgZPiyhjiYH5OG00uI/zgraPEccA4JuUbF+pjTviNm3KZL5+dSH+0wZw05wN/OZva9i171DcklFSaj8Syeysnm1ZfMOZjOjVnmWz5xEYMhSdNAkSVH2qqnxlJRZPiyhjEZFMEcmpy4VE5DlgNXC8iBSLyJU4A82HicgWYJj7GmAh8CmwFXgCGFeXa6YE9+60/YghPD92ALf+9ERWbinh7OkrmL/+i7iUXuzuM/m1aJzJg6P7cXfLPc6EhYEAleV+Kpcti3ta9h2swB+otFKuh0Wy5v31wA5gq4h8KCLjI7mQqo5W1faqmqGqHVV1lqp+papDVbWH+7jH3VdV9RpV7a6qvVV1TWRhpaa0NOGqQd1YeP0gurRqzHXPrWXqHbPZf/vkmN6ZWkNsw3HCJefhy84ikOajPM3HrXuPYXvJ/rimwTp7eF8441imi8gY4HrgRFXtAJwJ9BSRybFOoIlc99ZNmHN1PtOOO8D4u64m687bCQwZEpPM5XCgkr0HDluJpaE4Un06+U7eeeIFXm3cmZEzVvLXt7bHbVyUDaj1vnDGsSwH+uH0BntLRPYBG4CNwNUiMi3GPcRMHaT70vj5vq1VJix87YFnGdQnj9xG0RuUtme/jWFpcPLzkfx8BgOLvznEzS9t4Lb5mynYvJPpnQ7S5v3YjouyjMX7ai2xqOorqvpH4G2cMXpn4QxmrABaAoUisjWmqTR1EzJh4eyMLpw9fTmFRbtqPzZMu0vtR6Iha5ebzewrTuWen/WG1atpeu5IKm+dFNNxUTYBpfdF0nh/DfAPYBpOCaYXsFFV+wI9Y5A2U18hU8LcdvdV5OZkcPnT7zLhpQ2UHjpc70t8V19uPxINlYgw+rROzOywzxkXVek07Je+/q+YXK+kzI8vTWjRyL4zXhV2xqKqW4DTgTlADk512IXue/6jHGoSye01Rn4+vTvmMn/8QK7+cXdeWPMZI6avZMOLi+o1pqHESiye0fycs4PGRfn4bXETXllbHPWehSVl5bRsnGnTuXhYpGve+4EF7p9pgLIzfEwYeQLDerblqfuepcekGwlUVpCWleWsQhdhvbrNUushbsO+FBayt+/pHNyezQ3/XM/rm3Yy5YLeUevFZd3TvS+ijMV4R//OLTi53ddVJiz88pWFdIg4YyknJ8NH4yz7KnmCO+npscALlcqsVZ8y9Y2PGT59BVMu6MU5vdvX+xK7baYGz0v0yHuTQBlDh5CWlYW6ExZeuzOXexZ+yKHDgbDPYWNYvMuXJow9szsLrh1IxxY5jHvmfabdMZuDd0ypV8N+SWm5LfDlcXabmcqONO4XFlJ5xkBO2NOcx1Z8ytKPdjFtVB9O7ti81lNYtYb39WjblJd+ewZzZ87h3Bv/h4xABYE/3YVv6dKIq05V1b0Zse+Ml1nGkurcqo9GwN3A8JPacfOcDVw48y2uGdyda3NKyFi1osZxDSWlfjq1ahTvVJs4y/ClcXHZJ1XGRS188DkG9sujWXb446LKyisor7DpXLzOqsJMFT/+YWsKbjiTC/p2YNXfXyUw9OgTFlqJJYWEjIuald6JEfevYOWW8NdBss4eqcEyFvM9uTkZTBvVhz8fs5f0oAkLA0urTlhYEahkzwE/re3uMzWEjIuadNdV5GT6uHTWv7l17kb2l1fUegobdZ8arCrM1KjHqHPRx+4nUO7Hn+bjtj2tGLurjB+0aQLAngN+VLH68lTiVp0C9AUWXDeIqQVFzHpzGys+LuGRbuWctGXtUapOLWNJBZaxmJq54xp8hYW81/EkFm/LZt4DK7lp+PFc8aOutta9ITvDx63n9uTsk9rx9NRn6XbL76msrEBqGBf1bYnFehJ6mmUs5ujcO9SBQEHpIf7w8iamLPiQgs07+bVvJ+NWz6PLqekQhfENpuE6rWtL+rb7psq4qF1zF3FsSMayu8yPCLS06Vw8zdpYTNjaNM3miTH9mXZxH7LefYfB40Zz48p/cMKvLkzoMrcmOWSeNQRfVhaVR8ZF7WjGva9/RHnFd+OiSsrKadkok3Sf/fR4WVJ/uiIyQkSKRGSriExIdHqMM2Hhz/t3ZGbHUjIDFaRrJXLYD4WFiU6aSTS3cT9t8mQCbyym+38NY2bhJ5z/0Jts+vwbwJaxThVJWxUmIj7gYZwli4uBd0Vkvqp+kNiUGYBmI4bBfX9C/X4kM9NprDXGrTptDNwLjOjVjptf2sgFD7/J+CE/oPn6NQzdth4GZMRsvReTeBKPNdHrQkTygdtVdbj7eiKAqt5T0zF5eXm6Zo2tYhw3q1c7JZUYLgplGr6vD/i5bf5mPluwhGeev4XMygp8WVlQh0lPTWyIyHuqmhet8yVtiQXoAHwW9LoYZ9r+KkRkLDAWoFOnTvFJmXEEdT01pibNG2Uy45J+FK1+kYxABT6tBL9bfWrfH09K5jaW6hZr+F7xSlUfV9U8Vc1r3bp1HJJljKmL4y85j/TsLPD5wKpPPS2ZSyzFwHFBrzsCXyQoLcaY+nIb96361PuSOWN5F+ghIl2Bz4FLgP9ObJKMMfVi1acpIWkzFlWtEJHxQAHgA55S1c0JTpYxxphaJG2vsLoQkd3A/9Xx8GOAkigmpyFJ1dhTNW5I3dgt7up1VtWoNVJ7KmOpDxFZE83udg1JqsaeqnFD6sZuccdHMvcKM8YY0wBZxmKMMSaqLGP5zuOJTkACpWrsqRo3pG7sFnccWBuLMcaYqLISizHGmKiyjMUYY0xUNeiMRUSeEpFdIrIpaFtLEVksIlvcxxbudhGRB9y1XTaIyCk1nLO/iGx093tARCQa5/Vg3L90z7dBRN4SkT6xjjtZYg867lQRCYjIRbGM2b1WUsQtIoNFZJ2IbBaR5bGO271mwmMXkVwReVVE1ruxX+GxuC9246oUkbyQYya6+xeJyPCwEq+qDfYPOBM4BdgUtO1eYIL7fALwZ/f5OcAinMktBwDv1HDOfwP57n6LgJHROK8H4z4DaOE+HxmPuJMldve1D1gKLAQuSoW4gebAB0An93WbVPnMgT8EPW8N7AEyPRT3icDxQCGQF7R/T2A9kAV0BT4BfLWmPR5fjBj/87uE/OOLgPbu8/ZAkfv8MWB0dfsFbWsPfBT0ejTwWH3P68W4Q45vAXyeKp+5+/p3wDXAbOKQsSRD3MA4YEq8Pucki30iMBPnB7krsBVI80rcQdsKqZqxTAQmBr0uAPJrS3eDrgqrQVtV3QHgPrZxt1e3vkuHkGM7uNur26c+542HeMcd7Eqcu59EiWvsItIBuBB4NIox1EW8P/MfAi1EpFBE3hORMVGLJHLxjv0hnLv6L4CNwPWqWhmdUCISq7hrUqfft6SdhDIGwlnfJaw1YKJwTDzFKm7nQJGf4GQsAyNMVzzEKvbpwM2qGnCrqJNNrOJOB/oDQ4EcYLWIvK2qH0eexJiJVezDgXXAEKA7sFhEVqrqvsiTGBNJ9fvmxRLLlyLSHsB93OVuD2d9l2J3e3X71Oe88RDvuBGRk4EngfNV9asoxVEX8Y49D3heRLYDFwEzReSC6IQSkUR8119X1f2qWgKsAOLSaaMa8Y79CuBldWwFtgEnRCmWSMQq7prU6ffNixnLfOAy9/llwLyg7WPc3hMDgG+OFCmPcF+XisgAt7fEmJDj63TeOIlr3CLSCXgZuDQJ7ljjGruqdlXVLqraBZgDjFPVubEJ7aji/V2fBwwSkXQRaYSzVPiHMYgrHPGO/T84JTVEpC1OQ/enUY+qdrGK+2jXu0REssRZG6sHTgeAo4t141OMG7aeA3YAh3Fy1iuBVsASYIv72NLdV4CHcXo1bKRqA9W6oOd5wCZ3v4f4bnaCiM/r8bifBPbiVA+sA9akymcekp7ZxKdXWFLEDdyE0zNsE/C7VPnMgWOBN9xzbgJ+5bG4L3SvUQ58CRQEHXOLu38Rbi+y2v5sShdjjDFR5cWqMGOMMQlkGYsxxpiosozFGGNMVFnGYowxJqosYzHGGBNVlrEYY4yJKstYjDHGRJVlLMaESUSmicgHIvJg0LYcEVkuIj73tYrI34PeTxeR3SLyWtC2spDzXi4iD9VwzUwRWSEiqTSvn2ng7MtqTBhEpBvwI1XtGfLWr3HmkAq4r/cDvUQkR1UPAsOAz+t6XVX1i8gS4BfAM3U9jzHxZCUWY2ohIscDy4HOIrJWRBoHvf1Lvj/f0iLgp+7z0ThTc4RznavFWZ1xnYhsE5Fl7ltz3esY0yBYxmJMLVS1CPgrMElV+6nqfnCqqYBuqro95JDncSbuywZOBt4JeT8nKANZB9zpXudRVe0LnIozb9Nf3P03uduMaRCsKsyY8PTm+yWTY4CvQ3dU1Q0i0gWntLKwmnMddDMQwGljwZkc8IgZwFJVfdU9X0BE/CLSVFVL6xOEMfFgGYsx4TkJ2Byy7SCQXcP+84GpwGCcGWnD4mYynYHxIW9lAYfCPY8xiWQZizG1EJGmwGFVPRC8XVX3iohPRLJVNfRH/ymcNTE2isjgMK/TH/hfYJAGLXsrIq2A3ap6uF6BGBMn1sZiTO164bRzVOcNqlmWWVWLVXVGhNcZD7QElrntL0+6239C9VVqxiQlW4/FmHoQkX7Ajap6aQyv8TIw0e1EYEzSsxKLMfWgqmtxShi+WJzf7Xk21zIV05BYicUYY0xUWYnFGGNMVFnGYowxJqosYzHGGBNVlrEYY4yJKstYjDHGRJVlLMYYY6Lq/wGLmJMD5rMcSgAAAABJRU5ErkJggg==\n", - "text/plain": [ - "" - ] - }, - "metadata": {}, - "output_type": "display_data" - } - ], - "source": [ - "# Plot results.\n", - "# plt.figure(2)\n", - "fig, axs = plt.subplots(2,1)\n", - "\n", - "for ch in range(2):\n", - " plot = axs[ch]\n", - " plot.plot(f0_v,fi_v[ch])\n", - " plot.plot(f0_v,fi_v[ch], marker='.', linestyle=\"None\",color=\"Red\")\n", - " plot.set_title(r\"$\\phi$ vs $f$\")\n", - " plot.set_ylabel(r\"$\\phi$ (degrees)\")\n", - " plot.set_xlabel(r\"$f$ (MHz)\")\n", - "\n", - "fig.savefig(\"images/Phase_calibration.pdf\", dpi=350)" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "For example, if your cavity tone was generated with an IF of 420.9 MHz, you would look at the above table and see that freq_i = 420.9 MHz corresponds to phi_i = 308.7 degrees (that's specific to this board session, for your QICK it will be different). That value of phi_i will be used as the value of the config file parameter associated with the offset phase of the cavity pulse (the parameter is called res_phase in the demo 00_Send_recieve_pulse)." - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "We can try a fit:" - ] - }, - { - "cell_type": "code", - "execution_count": 12, - "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "initial estimate: 113.27 deg shift, 229.28 us delay\n", - "after minimization: 32.03 deg shift, 251.41 us delay\n", - "initial estimate: 42.41 deg shift, 229.29 us delay\n", - "after minimization: 290.80 deg shift, 251.41 us delay\n" - ] - }, - { - "data": { - "image/png": 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p0zh8+DD79u3j6NGjLF26lNTUVEaMGMF//vMfg79N8YmOEqYM0mwfL/+4LdTi+Iwtt6Co846bkAYyMri+Q206N6jMc/O2cCJM6l7lFyiy8wqI92ElnrhsMeMXzmBr1RQ+aN2nVHiy+VKuupdS6qJplFLqJPBf4L8iEuvtJEqpdUB7F9t3odl3nLdnATf5IF+xyWzRClafJ8EpSM2ZIWn1mfX7fiZ+s5ErmiZTId7r1zUNmS6C1IqomDIyqJSezuimaTz1+yk+X7mP2zvXC76gfmD/Tv44Mz7eqynfLdvKqB4P8O0HjxGXk8NPN9xA7JgxF+1buXJlbrjhBm644QZyc829grDbPj5cvpsbO9ahVa2KoRbJK7acPGpWiHf9oVPpdVm4kCmDWtPvtaVMm7eFf97ULrjCFoMsD8HLF9G9O70nT6bXjt94tcttXNO5OrUMli/UeJ0quhpwirOPGbHVbwhAwmN/d5mtwI49dud4GMbuZDm7pzri4Fhw/b39SUuO4bl5m00fu6OlLvJlvlRI2TJa3Z1tyfV5p/P1EBdHbM+eXo+LjTX/BOOZPs2pXDZ8bB8XuUw74sKxoEn18jzQrSFfr97Pb3+a38nPH/WvXfswvn15ChLimXjAzWAcQfjsSCAiN4lIef3/MSLyPxHpYJxoxnPBs+vx4V5rsLSpU5G707TYnd/DKHbHo27ZoYNLTg5TszaQlVvAFJPH7thy8nybRTrRa/CV9K0Zy+vd7mTP3MK6O1999RVnz2r2rClTpnD99dezZs2agMpsJI62j89Xmt/24dGzy41jwd+vakztpATGzDZ/CMMFO6oP6jUA0tKoO/r/+HuvZszfeISfZ0V2ihx/vNfGKqXOisjlQB+0wM1/GyNWcHAZ7+Ehev2p3k2pXj6ekWEUu5OZk+9et+zUwRv27MLQHo2Yu/agqVPMF/F+8pMJF+ruxGmOIRkZTB4+nPIbNrBs2TLmz5/PkCFDeOSRRwIstbEMbl+b1IaVef6HLRw3ue3DWwyLK7tjYlwME65rxbYj50wfwuDXSseBB65oSONyUYxfsBPbxMkRmyLHn0HH7ks6APi3UmoOEBd4kYKHLcfJIO2l9k75+NgLdXc++MXcDd9OlqcHtIsO/kj3RjRMLsuY2etNG7vjcSD1Qo2K8fxf76Ys2XaMb75eDD17En34MPTsyXczZvDII48wcOBAcnJyAiy1sYgIUwa15nx2Hs/NM2/pdaUUmd4mDW5Kr1/dsjq9WlTn1Z+2c/C0LXhC+4mnhLSeiIuJYrLazr6K1Zl+2Q1By5IebPwZdA6IyNvALcD3IlLGz+NNx0UGaS+1dwD6tNIa/is/bg+L2J3MHPfpOICLOniZF19garMoU8fu2Hx0R3XHXWkptK1TkUlrTnNGYqkNPJSVxRfffkv//v3Jzs6moCA8VrKONK5mfttHdl4BSuHbpMHFJHDCdS1RKCZ+s9F4YYtJYWycf3ZHgLRelzJ4yxLe7nwDO6qnRGSKHH8GjZuB+UAfPbizMvC0IVIFCVtuXlGDtJfaO6DNKCcObIUIYRG74/OqwKGDp93Slxvrxpk2dsfXGAh3REcJzw5uw0kVy/Pd7+HLqCj6xMYy/623SEpK4uTJk7z44osBlDh4DL+qialtHxdqIfly/1xMAutUSmR4zyaa7WPLEWOFLSZZPqZpcklaGqMeu46EaGHcE9NRqakBli70+DPo2ICywG36+1jgdMAlCiIXzZi91N6xUzspgSevbsqirceYt8HcsTse1WuOOHXwUad/p3x8jCljd7LcpI33h9a1K3Lf5Q34tE1vNo1/ifP/+AefbdHUUrm5uSQlJQVC1KCTEBd9wfZhxtLrNn+M7G4mgX+7vCFNqpVj3JyNplQBZ/ozsLqgao+uPD3oEpYfz4vI0uv+DDr/QktbYx90zgLTAy5REHE5Y3ajT3bmni4ptKpVgQlzzV13x+dVgVMHr3zVFYwe0JLVe06ZziMq00PaeH944uqm1KoYz+D5i1h+/Difvf8+TJtG+c2bGTZsWAAkDQ1228drP21n/ylzqYCL407sPAmMi4li8qDW7D9lY/qiHUaKWyy8ld7whdsvq6elb1oSeaXX/em5nZVSw4AsAKXUKcLdkSDXg+rJi1NBTHQU065vw/Fz2fxzvnljd2y+qtdcdPAbOmgeUWaL3fFqp/KRsmVimDSwNUd3bqRt6o3E790LY8dSafBgck6H9SL+gu1j0jebQi1KEYrjTlwkW4FOasMqXN++Nm8v2cmOo+fcHBwafM2C7onoKGFK3hZOJpTnpS63R5RTgT+DTq6e6FOBlksNMJ/S2A98jWFxd8Pb1kni7rQUPl5h3tgdv9yLnTq4VnenjelidzwGF/pJr5bVSSobz6sb/iI3Kgby8zmWnU3U+fAul2y3fSzYdISFm81j+/ClFpJHHLQPowa0ICE22nS21UCsdADa9OzMXesX8J/2/Vhfu3nEOBX4M+i8DswCqovIVGAZ8KwhUgUJj15QPjgVgLljd3LyCsgrUMU3umdk0OjdN3ikcRxz1x5kiQlid3LzC8jNVy5rIBWXcSOe4tDsaeyKi2eUCJcrxagwVq/Zsds+xs81j+3jgmdXXDHUo07ah+T1a3imb3OW7zzB3LUHvR8fJPzJgu6RtDSeGnkbVaILGPPIP8nvHBlOBT7feaXUJ8AzaAPNIWCQUuorowQLBjZPBmkfnQq02J2Wpqy7Y3/QFCumxaGDPzL8ehqWjWLM7A0X1COhIhCqC2eGPXAvIydMJeHyOzjR90Zmf/IJN40eHbDzG4oHu6Oj7ePNReZwfy9UrxVjpeNC+3DbZfVoV6cik7/dzBmbOWyrWblaOe6oqJIXOq7QrStjbrmUtafz+fS3vUEpvW40/qTBEaATUEUp9SZwXkQuStQZTmgp1j38BB6y3zrSp1UNerWoxqs/mSt2pzBIrWQdPN52nilsZ+/JTF5fGNqHl62Y0d6eUEpRO+8QVWNzWN3lQfI7XsZvv/0WsPMbhhe7I+i2jw61mbFklylsH8WN1gdcah/smbZPns/mpQXmsK2W1KXfmeva1aJr4yq88O1Gjl1zveGl143GX++1NCLOe83HB7KHDq7F7rRGBMbP3Wga/XKmjxU2XeLUwbv0upQbOmh1d7YdCV3sTkndUV0xdOhQfv11BTnbltGhXhJx8Ynh4b3mg90RtNIViXExjJ0dettHcaP1AbfahzZ1KnJXan0+XrGHdftD7wDiSwE3fxARJg1sTXZePtO63OH1fpudUu295jEDszNeOrg9dufnLUf5wSSxO5klUa+56OCjB7TQYnf+F7rYnUIjbcm91+z8+uuvTJ8+nYrlEplxdyea1qvpVxocEakrIotEZLNe3PAxfXtlEflRRLbrr5X07SIir4vIDhFZV+zEuT7aHZPLleGZvs3I2HWCOX+E1vZR4pWqm5CGp/o0I7lcGUbP2kB+iOPKvJWqLg6NqpbjoaaJ/K9VDzJS2hlWej0YlFrvNb8N0j508Hu6pNCyZgXGmyR2x6+6Hq5wUi9WXreaUWoXq/acClklR1uu3RAduE4dGxtLfn7+hXRIx44dIyrKL0N3HvCUUqoFWizbMBFpiVZ4cKFSqgmwkMJChP2AJvrfgxQ3ca6PdkeA2y6tR7u6SUz5blNIbR+B8uxy1jxU+H0VYwa0YP2BM3z6654ASFp8Auld6ciwu7pTNzGKsbeNJefHn7xmxjcrxfFeq1Yc77WQzQbd4Ldu2YcObo/dOXYum5dMELsTUFWU3slvnPwonfdvZNo3Gzh2NvjZjI1Qrw0fPpzBgwdz9OhRRo8ezeWXX86oUaN8Pl4pdUgptUb//yxaGfbawEC0bOzor4P0/wcCHymNFUCSiNQslvA+BjNHRQlTB7Xm5PmckMaVZebmExstxEaXMLjXhebhgu1j/taQxpVl5uSRGMCVuJ342Ggm3dyRHQXxvJNTLeDnDxY+3XndiWAJmvfaNIrnvRaa2aAbirXM96GDt6ubxJC0FD5asYc/9oVWv1wi9ZozeieX/HymLphOVm4+k78NfuBhwNxRdZRSdOvWjRdeeIGRI0dSs2ZNZs+ezU03Fa9orYikoFXI/RWorpQ6pF/nEGB/UtQGHJeK+/Vtzud6UERWiciqY8e8uKv74FTQunZhTai1IWqbPgcre8OF5uGC7SO3gGnfhy7Tti23gHgDVjoAPZpXo2+rGrzx83b2/bQsLD3ZfBp0lGZ9nK2U2qKUmq6UelMp5Ve0YEhngy4okUHTSwd/qndTqpUvw8j/rScvhLE7JVavOeLQyRufO8YjzRJDErtTomSKLhARBg0aRPPmzRk2bBiPPvooLVq0KO65yqGVcH9cKfWXp11dbLvIEKGUmqGU6qSU6lS1alXPF/fRqeDJ3k1JLleGMbNDY/soaYbwC7jRPDSqWo6HrmzIrN8PsHzn8ZJfpxjYcvICGkfmzLhrWxJVUMDEGQvD0pPNnzXuChG5NBAXDdls0IGSpB/31sHLx8cy8bpWbD70Fx/8stv/8weIEkd/O+LUyR+5s7tedye4sTtGqNdSU1NZuXJlic4hIrFoA84nSqn/6ZuP2CdK+utRfft+oK7D4XWAkln4fXQqqBAfy9hrWrL+wBn+syL4to+Aena5CWkYlniCepUTGTt7Azl5wZ/0GWXTsVMrKYHHYw/yU8NOLGjQKew82fwZdHqgDTw7dRvLehFZ5+8FQzobdKBEXjQ+dHB77M7LP24LWdLFwoE18J08ftVvTLGtY+/JzKDW3bkw6ARQZ75o0SJSU1Np1KgRbdu2pU2bNrRt29bn43X183vAZqXUyw4fzQWG6P8PAeY4bL9bt1umAmfsE69i44dTwbVta3J542T+GQLbR2ZOyTOEu8RB+xDfuxcTm0ax89h53lm6K/DX8oIR3mvO3Ht1K5od38uEqx8mM7F8WHmy+XP3+5X0Yp5mg0qpQ4bPBh0o0YzZ3sHT07Wb7aKD22N3rn55MePmbOS9IZ0Ki8UFiUCroi6gd/AuOTnc0P8J3hYYeEltmlYvH9jruMCWE3jvtXnz5pX0FF2Bu4D1IvKHvm0U8BzwpYjcD+wF7Iai74H+wA4gE7i3pAIAWjt0bIsZGS7bqGb7aEXfV5cy9bvNvHZr+4Bc3heycgOTIfwinLQPPTYvp1/r3rzx83aua1eLupUTA39NN3gsxx0gYrt2YcqpPG5adpbXXv6akWHkyebPoHODi21nRGS1UuoPF58VwYfZ4HNcPBt8VEQ+BzoTiNmgA37V9XCFDx3cHrsz5bvNzNtwmP5tAmaS8onMnHxiooS4mAB3cocOPnrRu/zc6nJGz1rPFw+mBST1hydsuflERwmx0YG7zn//+9+LtlWsWJGOHTtyySWXeD1eKbUM1ytzgJ4u9leAsdGn9pl/To62Gnda/TSsWo6Hr2zI6z/v4JZOdenSONlQcewEKkP4Rdi1D/bv2707Y1u0ZPG2Y0yYu5F3gzTp86kcd4C49Jpu3GRby3u/H+CGI2dpumuDx4mwWfDnadQJeBjNrlIbzaOsO/COiDzjw/H22eBVIvKH/tcfbbC5WkS2A1fr70GbDe5Cmw2+Awz1Q1av+FXB0BseHAvssTuhqLuTadSMy0G9WDk/m5HtKrJyd3BidzJz8kl0LDEeAFatWsVbb73FgQMHOHDgADNmzCA9PZ0HHniAF154IWDXCSo+OBYM7dGYepUTGTNnA9l5wbHL2XILAuO95owL9WKtpASe6NWUhVuOsmBTcDJt+1WOOwCM7N+CcvExjPloOcqL96JZ8GfQqQJ0UEo9pZR6Cm0Qqgp0A+7xdrBSaplSSpRSbZVSl+h/3yulTiileiqlmuivJ/X9lVJqmFKqkVKqjVJqVTG+n1tKlAPKGQ8dPJSxO35lXPAHpw5+0y1X0rlBZaZ9v9nw2B0j9OUnTpxgzZo1vPTSS7z00kusWrWKY8eOsWTJEmbOnBnQawUNH+yO8bHRTBzYil3HzvPOkuDYPmw5ecatAlw4Ftyz7AuaV4hm4tyNnM/OM+a6DgR0MusDlcvGMaJvc347kcf/GncNixQ5/gw69QDH3CC5QH2llA0IfpRgCbmQlywQBmkvHTxUsTuBTjxYBIcpDf5fAAAgAElEQVQOLiJMbZBPVlYOUz9cYsz1dIz4Tnv37iUurjCjU2xsLHv27CEhIYEyZcoE9FpBw0fHgh7NqtGvdQ3e+HlHUJLVBjovmVt07UPsuLFMeW8kB89kBSVZbWZJ1fbF4OZOdelQKYZnu9/L6bIVTZ8ix59B51M077XxIjIe+AX4TETKAuYqT+gDATWy+9DBQxG7kxmoQDxvZGTQeFBvHln+BbP357B0jnEDj8dqr8Xk9ttvJzU1lYkTJzJx4kS6du3Kbbfdxvnz52nZsmVArxVU3FTddGbctS2JjpKgJKvNDIJnF1BE+9Bpz3pujj3Je8v+ZOthY5PVGpEF3RtRUcKUu9I4XbYiLzz5ulfvxVDjTz2dycADwGngDPCwUmqSUuq8UuoOowQ0ioAb2b1kKygfH8uEa4Mbu5MVJIOmvYM/svxLGp48wJhfjxsWuxOw4EIHxo4dyzvvvENSUhIVK1bkrbfeYty4cZQtW5ZPPvkkoNcKGR5S5NSsqNk+ft5ylPkbjbV9BMOdGLhI+zCiZ0PKxRufaTtgueX8pGWtCtzTtQGf5Vbh99rNTV13x996Oi2AikqpV4Gj4VxPxzAjuwengr6ta9CzefBidwzzFHJG7+DxFDAl/R32FJThzZ93GHIpI76TUorNmzdz5swZHn/8capVqxYe9XR8xYcUOfd0TaF5jfJM+sY420duvl7JNhgPZCftQ+XuXTXbx+6TfL16v2GXLVENqxLyxNWaNmXMJ7+S1+tq0zoVlNp6OobNuDw4FWixO60AGD8nOKqMoKjXHDp4lw9f54YOdXhr8U5D6u4YoZ4ZOnQoGRkZfPbZZwCUL18+POrp+IoPnmyx0VFMGdTaUNtHQJ13fMFJvXhzp7p0qJfEtHlbOJ3pe+kKf8g0II7MV8qViWHcNa3YeCafj1v2Mq1TQamtp2MzSvXkxamgTqVEnrxac+Ocv9HYujtBU69BkQ4+uto5yqtcRn+4POB1d7IMMETb6+nEx8cDUKlSJb/q6ZgeH1PkdEqpzM2d6hhm+zAsWNkXMjKIev45pjYs4Iwtl+d/MMaTNCsEjgSO9G9Tg27VYnnpijs4WiHZlE4FpbaejmHpOHxwKri3awot9Lo7Zw2M3THUe80dGRlU7n81o76fzsqTeXz5ZXpAT2/EdwpAPR1z40eKnBH9tEJ9Y2avD/hK3Ii8eT7hoF5scX0f7m1Qhs9+28uavacCfqmQfUcdEWHS3V3JiU9k8vBXTelUELR6OmbDlptnTDoO8Oo1ZI/dOXo2m5cWbDNGBgKYRt4fdFXOjet+pPO+9Tz7x18Bjd0xQi1a0no6YYGb5JjO+v7KZeMY0a85K3efCrjtI1RGdmf14uPHVlGjQjxjZm0IuCepLZSrOZ2U5LIMvaoJ3+QmsTS5ccjkcIc/3mufULJ6OqZCmzEHydjnooNfUjeJu1Pr82HGbsNqmximQvSErsqR6Gimpr+LTWKY+l1gPOqNSjFyxx13BKyeTljgxbHgpo516Vi/EtPmbeHU+cCpGQurvgbZyO6kXizXoxvjrm3JpkN/8VFGYDNth8Jl2hUPX9mIlCqJjJuzUVP5mcibza+7r5TaAoSuOlIAseXkk1wuCIF/HnJg/V+fZvyw8TAj/7eeuY92Jaak1RQdyMnTPYWC3fgdkqE27t6dR85V4fWF27mhYx2uaOJ7FnBX5OYr8guUITPl5s2b07x584Cf15S4cixwWJVHRQlTBrXmmjeW8cL8rUy7vk1ALmvL0VYVQV/puEjQ208prmxalZd/3MaAtjWpXiE+IJcK2WrOifjYaCYNbM3d7//G258s5rGh17jNwxdsvA46IvKkp8+dkneGDUFbBXjo4PbYnUc+WcPM5bv52xUNA3bZwhlX8F03HZOhDs3N55sVOxnzwVLm969B/OVdin3aQH+nl1/23HSffNJj0w9fXCTHdKZFzQrc2yWFd5f9yU2d6tChXqUSX/ZCFpBQrAKcEvTKihVMOricq3ObM/nbTbx5e4eAXCZg5bgDQLemVRnQtibT1x1gUEJl6tsOuJxkBBtffpny+l8n4BEKE34+DIRtuLZhcTrOePEcssfuvLQgsLE7Jc6iHSDiV/3G1I/Ha7E7494t0fI+MzewD62zZ89y9uxZVq1axb///e8LCT/feustNm0KuyQbvuOjY8HjVzelRoV4RgfI9mFvk0G3Mzqjax/qT/gHw5Z/wbfrDrF0e2Aq4IbEjuqBcde0JC4minFXP4zy4r0YLLwOOkqpiUqpiUAyRRN+dkSrcROWBC0y2ksHNyp2J6SzSkfS0+myaw3Xr1/I2x2vY/vCEgw6AVZdjB8/nvHjx3P8+PEiCT9Xr17N/v3GBRCaAi8ZNECL+xh/bUs2H/qLDwNg+wh2Mky3OGgfHsr4igZR2YwNUAVcIzJmlITqFeJ5sm9LFqe0Z944c6TIKUnCzxwgJaDSBAmlVHCN7F46uBGxO0EPxHOHvtIbvWQmZXOyGBXXqtixO0YZaZ0TfsbFxbF79+6AXsO0eHEq6Nu6hmb7WLCVw2dKVmXULKtvR+1DfLQwqXMyu09k8vbikmfaDlpCUz+4O60+LWtW4OMaHUI+4IB/jgQfA7+JyCy0WJ3BwIeGSGUwOfkF5Beo4Keq8OBUcG/XFP73+wHGz91I18bJlI+PLdGlQh2kdgF9pVclPZ1RDWrwzB/n+Wr1Pm65tJ7fpypMMRLY73TXXXdx2WWXMXjwYESEWbNmMWTIEO8HRgJenArsVUZ7v7KEyd9tYnoJbB+mmQg5ORZckZbGNefXMD19BwMvqUVKctlin9qw+L8SEBMdxYy7OwbHccoH/HGZnopWVvcUWtLPe5VS04wSzEjsM+ZQxbB4qrsTqNidUAepFUFf6d10y5Vc1qAyz36/hePn/I/dMeo7jR49mg8++IBKlSqRlJTEBx98wMiRI30+XkTeF5GjIrLBYVtlEflRRLbrr5X07SIir4vIDhFZJyKBsWAXFx+yFdSvUpZhPRrz3bpDLNlWfNtHVm4+IlAm0JVsi4OT9mHsnwuJo4BxJcy0bVg57hJSp1KiaWxNXn8dcSjRqJRao5R6Tf/73dU+Hs5jmo4Zsgeylw5+Sd0k7gpQ7I5pZpUOiAjPNsgn05bN1Jn+lz+w6XaqQHUex4dLhw4deOyxx3jsscdo3769y308MBPo67RtBLBQKdUEWKi/B+gHNNH/HgT+XUzxA4OPTgUPXdmQBsllGTen+LYPI6q+lhhd+1B9/EieWvg+S7Yd4/v1xVdxBy3Jbhjjy5C8SET+LiJF9CEiEiciV4nIh4AvuoiZmKRjGqWm8YoPHfz/+jSjarkyjJpVsro7plGvOXKh7s6XzNqfwzI/6+4EOoNvjx49eOONN9i7d2+R7Tk5Ofz8888MGTKEDz/0rkFWSi0BTjptHkih+vlDYJDD9o/0yrgrgCQRqVmS71FifKi7UyYmmskDW7P7RCZvLd5ZrMsErZaOPzhoH+5a9Q0to2xM+nYj54qZaduwctwRhC+DTl8gH61g20ER2SQifwLb0TJOv6KUmuntJGbqmCEN4PKSjqRCfCwTrmvFxoN/MXP57mJfpnA1Z6JZl97Bhy7/ggbFqLsT6BXqDz/8QHR0NLfddhu1atWiZcuWNGjQgCZNmvDZZ5/xxBNPcM899xT39NWVUocA9Ndq+vbawD6H/fbr2y5CRB4UkVUisurYscC49PqEG2+2y5skc227WvwrfSe7j5/3+7SGlU8vCQ7ah5jYGKZ2rc7Rs9m88mPxVNyGluOOELw+kZRSWWhlDf4lIrFortM2pVQgcrcU6Zgi4q1jHnI+gYg8iLYaol4934zTplE9uXEs6Ne6BlfpdXf6talJ7aQEv08dyhTrbrHX3cnJYWr6u9x+/XimL9rBU72b+XR4oL3X4uPjGTp0KEOHDiU3N5fjx4+TkJBAUlJSQM7vBle6JZc6PKXUDGAGQKdOnYytg2HHg7MLwNgBLUjfcpSxczbw0X2X+aUqy8zJM9fKGy5yKmiflsZtOeuZuXw3N3SoQ8taFfw6nRm918yGXxYvpVSuUupQgAYcT/jVMZVSnZRSnapW9S3NipliWFw5FogIE69rhVIwfk7xKh2aUr1WpO7Oa1zfvjZvLd7Jdh/r7gQ6TseR2NhYatasGcgB54h9da6/HtW37wfqOuxXBzgYqIuWGC+1d6pViOep3k1Zuv04362/aA7oEVtugek8u4CLtA/P9GlGUkIsY2av99u935QqRJMRajeLkHTMwgdyiDuAB8eCupUTeeLqJvy0uXglhANejjtQONbdGdCCslEw6vV5FCxf7vVQm4lSjPjAXAptnUOAOQ7b79adZVKBM/bVvinwwZvtztT6tKpVgUnfbPKrNIctJy84VUNLSNLa1Yws2Mmavaf5ctU+7wc4YEoVosnwq/fqzgP+63rcE5KOaRp3Yi+OBfd2bUCLmhWYUIy6O+Ew46qyfg2j5k1nZX5Zvhr+rNcUOTYDUxfl5ORgs9mKdayIfAZkAM1EZL+I3A88B1wtItuBq/X3AN8Du4AdwDvA0JLKHlB8cHaJiY5i6uA2HDuXzSs/+l5l1BYOD2RdvXjD5Ee57MAmnvtmAyd9zLSdm19Abn6QynGHMT4POiLyGJpNZYeIbBaRR/25kJk6pmlsOuDRsSA2OopnB7fmyNksv2N3jKiwGXDS07npj/lctnc9z3a9k+M/L/W4u1HuqK+99ho1a9akcePGtGjRgjfffNOv45VStymlaiqlYpVSdZRS7ymlTiileiqlmuivJ/V9lVJqmFKqkVKqjVJqVcC/UEnxIUXOJXWTuP2yesxc/icbD57x6bThMBGyqxclP58pC/7FudwCpn2/2adDzVBLJxzwJU7nVRG5G3gMaKGUqg10A1qKyGRfL2SmjmmWmhcX4SIlSft6lbgrtT4fZexm3X7fTWkhqRrqL927I3FxPPvTW2TGJTC1YnuPuwf6ofX444/z0Ucf8dprr7F582YOHDjAkiVL2LRpE2PHjg3YdcIWLylynunTnEqJcYyZvcEn20dWsJLslgQH9WLTs0f4W+MEvlq9n5W7nR1vL8a0zxWT4ctKZzHQGM1rbbmIrAFeBHYCt4qIoa4+RnAh3sNsHcCNEff/+jQj2c/YHTOm47gIXZXT+ImHeKRFOS12Z/txt7sHevV25ZVXsmPHDo4fP06XLl3o0KEDTz/9NI0aNeLzzz/n9Gmj/WVMjhengoqJsYzq34Lf957mCx9sH0YU4As4TurF4XdfSe2kBMbM2kCul75npKNLJOFLlulZSqlxwAq0+JleaDE1eUBlIF1EdhgqZYDJzMknLjoqoEXTAoIbI649dmfDAd9jd8yajuMidFXO0Lu6k1I2ijEfLCFrmWungkCv3gYPHsykSZNITU1lzpw5/PTTTwwZMoSYmBhOnjxJ9+7dadzYfOV+g4YPTgXXd6hN5waVeW7eFk54SW1kpE0uoDioFxNXr2R8zma2HjnLB7/86fEw02TRNjn+PJWGAf8BXgLaA62B9UqpSwizujq2nDzizfhA9mDEdYzdOXjau8E73NJx2Ovu7C4ow/Rx77h0KjDKJjB9+nTuvPNOnnrqKX7//Xc2bNhAmzZt+OOPPyK7ro43fHAqENGqjJ7PzmPaPPdFhfMLFNl5BeGletLVi70nPUavXat4df4Wj33PXo7bykjgGX8Sfm4HOgNfAwnAOrRM0yilAldIPQhoM2aTPpDdGHHtsTsFSjF+7kavpwkLo60j6el03bWG6zf8zFsdB7qsu2PUTLlJkyb8+uuv3HjjjdhsNtq2bcusWbMAipQ8KJV4yaAB0KR6ef52RUO+Xr2f3/50bfswZdyYNxzUi+N/epuC/AImfeN+EmIvx23aZ4tJ8OvX0QeX7/S/sCWotXSKi4vI8LppaTzRqynT5m1h/sbD9GlVw+3hYeG95oi97s7iD/i50aWMimvFFwWKqKjCOGEj71tcXBwDBgxgwIABhpw/IvCQrWB4z8Z8s/YgY2av57vhV1wUS2WaMAV/cCjrXTfrNH9vUZYXNx5m0Zaj9Ghe7aLdTRN0bnJMqGMynqBVDS0Jboy4913egOY1yjN+juekhGHhveaIve7OqKcZlVaDlSfz+Gp1UeN0WDhHRDIeHAsS42KYcF0rth0559L2kWWWUtX+4KRefOCO7jSqWpZxczdcsN84Yppy3CanVA46meFg0HRjxI2NjuLZ69tw5GwW/5y/1e3hYTGwOuNcd2fuBo5PfeGCKsdmxtxdpQkvjgVXt6xOrxbVefWn7RfZPkyZgNYXHNSLcTFRTG4Sxb6TNqb/J/2iXS1HAt8onYNOOERGezDidqhXiTs7e47dCefEgxfq7mTlMnXFUejZE7V8eXi43EYyPjgWjL+2JQVKMfGbonbHwsDJMH7kZGTQ5da+DN64iLc3n2PngmVFPjZNOW6TE8YtoPhkhYvqyUOdk6f7NqOKm9idnLwC8gpUeHxHNzRevZSHf/svs1r14JcazclOX4JSVuBdyPFSe6du5USG92zC/I1H+HlLYc7AC1nPQ53vsCTo6sVRP79HQm4WYxfvL5KM11SZTkxMqRx0MnPDy534Ag6eQxXiY5lwrRa782HGniK7FUZGh+F3tNO9O8PWzCXl1EFG9x7K6dQrAEt1YTpceLP97fKGNK5WjvFzN15oixERra+rF6tmn+XpjM9Ynl+euWsL8xCbqhy3iSmVv44tJz/8jH0uUpL0b1ODHs2q8tKCrUV06BGxzE9LI37BPKbUyWJ3Uk1ePF4OCPPvFGm4SZMTFxPF5IGtNdvHIi1uPGTVegOJg3rx9leeoW2dikz+djN/6cl4TVmO24SUikHnwGkbGw4UJiUMO88ucOk5JCJMGtiaAqWY4BC7EzGum2lpXD727wxuX5v/rtkPQMK877xmo7YIEh682dIaVeH69rV5e8lOdh47FzkpYnT1YnSXLkxtpDh5LouXPlwMhEkWbRMQ8YOOUor7Z65k+Oe/k52Xj1IqPOJ0nHHjOVS3ciJP9GrKgk1HmL/xMBB5uuXRA1pQMVabPSZ++rHL5JMWIcCLN9vI/i1IiI1m7OwNkaFecyQjgzY39OGuNd/x8U4b6+ctDU+P0RAQ8YOOiDCiX3N2HTvP24t3kZ1XEJ4GaQ+eQ/bYnQlztdidsIz+9kByuTKMitkLQJVzJ10mn7QIAV682aqWL8PTfZuzfOcJvl6trVTDbrLnDn2V99Tij6hsO8PoZYc5l2259PtCxA86AN2bVeOatjV5c9EONh78CwjTB7KbFDn22J3Df2Xx8oJt4Rn97YVberfjx/88QfsjO9wmn7QIAV5q79x+WT3a1anIel29HR8TIW1SX+VVyM9m7NKPWJefyOKtx8LbeSdIlJpfaNw1LVm87Rgj/rsOCPMHsot0JB3S0rizc31mLv/zwncLu9WcJ9LSaPLVh9oMs3t3ty67FiHCTYqc6ChhyqA2DJy+jLiYqCJpjcIa+yovPZ3rrrySLzdF8cuOE+GR2T3EmPoXEpG+IrJVRHaIyIiSnKtahXj+0bc524+eA8LcndiNAdceu/PW4p1AmK7mPOElRiScCGTbNgUenAra1KnIQ1c2oln18iETzxD09ihdujBpYGvioqMoG87PlSBh2kFHRKKB6UA/tNIJt4lIiUoo3H5ZPdrX02rOma6Amz94qLsz/tqW5OlVHMMyFslX3JRRDgeMaNshx4tTwT/6Nmf2sK4hES0YNKpajn93SmTYvuVh2SaDiZmfSpcBO5RSuwBE5HO0InLFLnASFSU8d31bnvjiD5qG86zLYWnvrGoa0KYmXzfbT/rWY5QtE8YDqyc8ZDsOEwLetkOOhzZpJ6LjVzIy6HlHP61NTgvLNhk0zDzo1AYc0wzvR6vnUwQReRB4EKBevXpeT9qsRnm+f+yKAIkYQtLS3HbsV26+hJW7T1I+PjYEggUBV6qc8OrghrTtkOOmTZYKwr9NBg3TqtcAV9MiddEGpWYopToppTpVrVo1CGKZn0pl4+jtodZO2ONDGWWTY7XtSCP822TQMPNKZz9Q1+F9HeCgm30tShM+qHJMjtW2I43wb5NBw8yDzkqgiYg0AA4AtwK3h1YkC9MQ3qocq21HIuHdJoOGOKbmNhsi0h94FYgG3ldKTfWy/zFgj5uPk4HjgZWw2JhJFjCXPGaSBYrKU18pFRA9l9W2g4aZ5DGTLGBQ2/aGqQedQCIiq5RSnUItB5hLFjCXPGaSBcwnjyvMJKOZZAFzyWMmWSB08pjZkcDCwsLCIsKwBh0LCwsLi6BRmgadGaEWwAEzyQLmksdMsoD55HGFmWQ0kyxgLnnMJAuESJ5SY9OxsLCwsAg9pWmlY2FhYWERYqxBx8LCwsIieCilTPUHvA8cBTY4bKsM/Ahs118r6dsFeB3YAawDOrg5Z0dgvb7f6xSqFb2d9y8gDy05o/1cQ4FMIAfYEARZ7tDPdxLIdZJlL3AWyAbOBEGW7vp1/gBOAOfs9wnoq++fieb7H4z79LSDLHloqWQqG/zb3ARsBAqATk7HjNT33wr0cdjeV5chDzhsgna9Q29PJx3u3xBgp37/DgdJHjO27RO6LEccznUjcB6tz28Pgiz2dv0HcAqtXW/WP9uNlhj2LJAV4PtU3La9Vf9shE/P+JIMEEb8Ad2ADhQddF6wfyFgBPC8/n9/YJ7+Y6cCv7o5529Amr7fPKCfj+fthtYZMx0ayWlgIlBJb6CvGixLF/1a3YBH7bLon50BJgXxd+kOfOt8n9ACHHcCbwOjgbXAy0bL49RmHgPOBeG3aQE0A9Jx6JhoJQrWAmWABvrvEe3w29yCll3aBrQMcbsW4GG0B88GtHa9C+0BNFH/f2IQ5DFd28bp+aPfv1P6cXHAIeDdYLRrh+2/OcizG3jDoHZT3LbdUP9t1qK3bY/PeG87hOIPSKHooLMVqKn/XxPYqv//NnCbq/0cttUEtji8vw1429fz6rJk65/fhjbo2I/5GDhopCxOx7cFch3e5wKtgvi7dEcfdBzvk96A59uPQ5sVPWu0PE7HzwEOGP3bOGxLp2jHHAmMdHg/X/9d0oD5Dr/XYft+Hn5nw9u1/n4nsMV+rMP9ext4JMj3zzRtG4fnj37/zjsc8yxwLIi/y6doA4vjoLPDiHZTkrbtaj93f+Fi06mulDoEoL9W07e7ShFf2+nY2vp2V/v4et5cfVttoIz9GGAbkGSwLI7cgrasthMFfCwiq4FrPcgfSFnSRGStiMwDmjhdz37cfqBCkORBRBKBK9HUoXaM+m3c4e687tqSp+8VrHZ9GC3/oqv7VzYI8jhimrYNzESb1dvPFePQ5zcD5R0+M7pd90VbjdhRaIPityLyYIDbjTt8bdu+nMvUCT99wZcU8T6lkffxGE9VqIySRTtQpAdaxzzisPmcUqqDiFRD0+3a76dRsqxBy9F0Ts8dNgNtFujtXIb+NmgPpVWAYz2HYP827o5xNbEr7rn83ceX8/pyrtLWtu9BWzW4O5c/1ylpu/4FTdVopyuaTacf8KOIbAmCPIFs22Gz0jkiIjUB9Nej+nZfUsTv17e72sfX88bqx+wHsu3HAE3R1G1GyoKItAXeBR4A8h2OPywiNZVSR9E6ps1IWZRSfymlzun/f4/2u0Q7XM9+XB20WavR98nOrcBcp21G/TbucHded20JQt+ua6A5N7i6f5lBkMeUbRtNvSQikqyfK8+hz7egcEUWjHb9meMGpdRBtME5GpgF9CRw98kdvrZtn0p0hMugMxfNoI/+Osdh+92ikQqccVgGAxeWrWdFJFW0erl3Ox3v8bxAeyBfP898/fOHRaQSMAD42khZRKQe8D/gLuBP+7lEpCzasnuI/v9NwGKDZamh74uIXIY2A8pHT9WvX/8+tM4S7+r3DPB9QkQqoqnWfgzSb+OOucCtIlJGL1nQBM1g61jGIBaoSOEAGbJ2rZ/3LNqgMx/orb8+rP9fw2h5zNq2gXb66wm0+5cLPC4iccC9FL1/Rrdrx21lRaS8ftzf0O5TXQJ3n9zhtW3rv42ryd/FeDP6BPsPbWQ/hHaj9wP3A1WAhWiuhQspdIsVYDqaQXQ9RY1ffzj83wnN4L0TeJNCF0Fv5z2ry2GfDd4P/J1Cl+lNQZDlXTTvmVO6LAW6LP/Qz2N3K90ZBFkeRXOpXIvmFn3c4T69imbgtLtMG36f9M/uQUv579hmjPxtBuvXyEabcToaUkfr+29F9wjSt/en0P0+n9C3651oK3TH+/cBmtdapv69giGPGdv2KbS+7djnb6Gwzxsui0O7/pyiz8NDaDaUDWjhCoHuZ8Vt29v0z0b78oy30uBYWFhYWASNcFGvWVhYWFhEANagY2FhYWERNKxBx8LCwsIiaIR7nE4RkpOTVUpKSqjFsIhQVq9efVwFqY68M1bbtjCSYLbtiBp0UlJSWLVqVajFsIhQRGRPqK5ttW0LIwlm27bUaxYWdjIyYNo07dXCIpIwUduOqJWOhUWxyciAnj0hJwfi4mDhQkhLC7VUFhYlx2Rt21rpWFgApKdrnTI/X3tNTw+1RBYWgcFkbdta6ViUbjIytE5YpYo2C7TPBrt3D7VkFhbFx96uu3fX/kzUtn0adEQkHrgGuAKohZZ8bwPwnVJqo3HiWVgYSEYGWVddxbc5OSwV4WC7diQoReu0NAZUqECrUMtnYVEcXKnTFi4sHIRCrDb2OuiIyAS0FNvpwK9oGU3j0TIsP6cPSE8ppdYZJ6aFRYBwmAFOGDOGb7Ky6A50FqHaJZeQNXgw27ZtY8SIEWRlZfHSSy/Rtm3bEAttYeED9ra9d+/F6rSRI0M+2NjxZaWzUik1wc1nL4tW76Je4ESysDAIpxngpfffz4SMjMIZ4d/+dqFjPvnkkxw9epS9e/eGWGgLCx9wbNvR0RCjP9pNoE5zxuugo5T6zuj+hm4AAB26SURBVHmbiEQB5ZRWg+IoF9eBsLAwD25mgANq1bpI7VBQUMC5c+eoUKEC1apVo1o1V0UuLSxMgKPdxtFZAOCBB6BePVOo05zx2ZFARD5Fq7WRD6wGKorIy0qpF40SzsKixHibAaalcfsbb/DWsGFEnz9Px44dOXPmDE8++SRPP/10SEW3sHCLs93m1VeLOgvcfbfpBhs7/rhMt1RK/QUMAr5HU6ndZYhUFhaBwnEGmJ8P994LkycXiVXYtGkTFSpUYPbs2fTv35+9e/fy8ccfh1ZuCwtPOLtBnzihtWmntm1G/HGZjhWRWLRB502lVK6IWMV4LMyHJ3dRFzPA3NxccnNzmT17No8++iixsbEUFpG0sDARnlz809JMPdjY8WfQeRvYjVY1comI1EerhmhhYR6K4S760EMPkZKSQrt27ejWrRt79uyhQoUKQRfdwsIjrlRqJ06Y0m7jCZ8HHaXU68DrDpv2iEiPwItkYVEMSuAuOnz4cIYPH37hff369Vm0aJHxMltYeMOds4BdpTZyZIgF9B9/HAmqA88CtZRS/USkJZAGvGeUcBYWPlFCd9EjR44watQoDh48yLx589i0aRMZGRncf//9xsptYeEJb84CJnOF9hV/HAlmAvPRMhIAbAMeD7RAFhY+4Zg11wdnAU/cc8899OnTh4MHDwLQtGlTXn31VYO/gIWFG+xt+6OPwtZZwBP+2HSSlVJfishIAKVUnojkGySXhYV7Auwuevz4cW6++WamTZsGQExMDNHR0UZJb2HhHh9c/MN1sLHjz6BzXkSqAApARFKBM4ZIpSMifYHXgGjgXaXUc0ZezyJMcOcuWszcUmXLluXEiRMXPNZWrFhBxYoVAy62I1bbtnBJGAV5Fhd/Bp0ngblAIxH5BagK3GiIVICIRAPTgauB/cBKEZmrlNpk1DUtTI5B7qIvv/wy1113HTt37qRr164cO3aMr7/+OqCiO2K1bYsi+OniH+744722RkSuBJoBAmxVSuUaJhlcBuxQSu0CEJHPgYGA1TFLIwa6i3bo0IHFixezdetWlFI0a9aM2NjYwMjtGqttW2iYPCO0EfjjvZaIttqpr5R6QESaiEgzpdS3BslWG9jn8H4/0NmFXA8CDwLUq2flHY0oguQumpmZycsvv8yePXt455132L59O1u3buWaa64JyPldYLXt0k6YZIQ2An/Uax+g5Vyz/xr7ga8AowYdVyHhF2VAUErNAGYAdOrUycqQECkE0V303nvvpWPHjmTo9ePr1KnDTTfdZOSgY7Xt0kwYZYQ2An8GnUZKqVtE5DYApZRNjM0Vsh+o6/C+DnDQwOtZhBpvKxuD1A47d+7kiy++4LPPPgMgISEBpQx9xlttu7QRphmhjcCfQSdHRBIo9F5rBGQbIpXGSqCJiDQADgC3ArcbeD2LUOLLysYgd9G4uDhsNtsF77WdO3dSpkyZgF/HAattlybCOCO0Efgz6IwHfgDqisgnQFfgHiOEggtxQI+iBaRGA+9bpbEjEHe6bQNXNs5MnDiRvn37sm/fPu644w5++eUXZs6cadj1rLZdCgjRqj0cEF/UCLoarQ6QCaSi6aRXKKWOGyuef3Tq1EmtWrUq1GJY+IqzblsE8vIKvXiC0BmVUuzfv5/ExERWrFiBUorU1FSSk5Mv2ldEViulOhkulAusth1GuFrZPP54UQ81kw00wWzbPq10lFJKRGYrpToCF1UStbAoFibQbYsIgwYNYvXq1QwYMCAo17SIcKyVjUf8Ua+tEJFLlVIrDZPGIvIxYSBcamoqK1eu5NJLLw36tS0iiAiodRMM/Bl0egAPicge4Dyaik0ppdoaIplF5GHSQLhFixbx9ttvU79+fcqWLYtSChFh3bp1IZHHIgyJkFo3wcCfQaefYVJYRDYmD4SbN29eSK9vEaZEYK2bYODPoHPWx20WFoWEQSBc+fLlfdpmYXGBCK11Ewz8GXTWoAW0nUJTrSUBh0TkKPCAUmq1AfJZhCNhFgjXoUMH9u3bR6VKlVBKcfr0aWrWrEm1atV455136NixY6hFtDALJnDxD3f8GXR+AGYppeYDiEhvoC/wJfAvXOSOsiiFhGEgXN++fRk8eDB9+vQBYMGCBfzwww/cfPPNDB06lF9//TXEElqYglJQ6yYY+FM5tJN9wAFQSi0AuimlVgCGhm9bhBHu3EVNXO1w1apVFwYcgN69e7NkyRJSU1PJzjYy6YZFWFHCCrUWGv6sdE6KyD+Az/X3twCn9NogBQGXzCK8CGN30cqVK/P8889z6623AvDFF19QqVIl8vPziYryZ15mEXGY0MU/3PFn0LkdLRXObP39Mn1bNHBzgOWyCCfC3F30008/ZeLEiQwaNAiAyy+/nE8//ZT8/Hy+/PLLEEtnETJM6uIf7vhTxO048HcRKaeUOuf08Y7AimVheiLIXTQ5OZk33niDc+fOUa5cuSKfNW7cOERSWYQMk7v4hzs+6w5EpIuIbEKvbigi7UTkX4ZJZmFe7DPAsWO1V7tKLTo6LN1Fly9fTsuWLWnZsiUAa9euZejQoSGWyiIkOLbt99/XnAXCtF2bFX/Ua68AfYC5AEqptSLSzRCpLMxJhLqLPvHEE8yfP5/rrrsOgHbt2rFkyZIQS2URNMLMxT/c8WfQQSm1z6luW35gxbEwLRHuLlq3bt0i76Ojo0MkiUVQCUMX/3DHn0Fnn4h0AZSIxAHDgc3GiGVhOiJ4Bli3bl2WL1+OiJCTk8Prr79OixYtQi2WRTCwMkIHHX8GnYeB14DaaOV2FwDDjBDKwiSUEnfRt956i8cee4wDBw5Qp04devfuzfTp00MtloWRhLGLf7jjr/faHQbKYmEmSpG7aHJyMp988kmoxbAIFmHu4h/ueB10ROQNwG15UaXU8IBKZBE6PLlBR6C76N///necbJRFeP3114MojYWhRJCLf7jji8v0KmA1EA90ALbrf5dgORJEDhHmBu0LnTp1omPHjmRlZbFmzRqaNGlCkyZN+OOPPyxHgkiiFLZtM+N1paOU+hBARO4BeiilcvX3b6HZdSzCmQh1g/aFIUOGADBz5kwWLVpEbGwsAA8//DC9e/cOpWgWgaAUt20z448jQS2gPHBSf19O31ZsRORF4FogB9gJ3KuUOi0iKWiecVv1XVcopR4uybUsXBDhbtC+cvDgQc6ePUvlypUBOHfuHAcPHizROa22HWKstm1a/Bl0ngN+F5FF+vsrgQklvP6PwEilVJ6IPA+MBP6hf7ZTKXVJCc9v4YkIdoP2hxEjRtC+fXt69OgBwOLFi5kwYUJJT2u17VBitW3T4o/32gciMo/CujkjlFKHS3JxvTyCnRXAjSU5n4UPlBI3aH+499576dev34W6Oc899xw1atQo0Tmtth0CrLYdFvjivZailNoNoA8yc5w+F6C2Ump/CWW5D/jC4X0DEfkd+AsYo5Ra6ka+B4EHAerVq1dCESKcUuQG7Qu7d+8mJSUFgBo1ajBw4MAinyulLsTulBCrbRuN1bbDBl9WOi+KSBTaYLMaOIbmydYY6AH0RCt54HLQEZGfAFfTxtFKqTn6PqOBPMAeLHEIqKeUOiEiHYHZItJKKfWX80mUUjOAGQCdOnVy69pdqrGy5rrk6aefpqCggIEDB9KxY0eqVq1KVlYWO3bsYNGiRSxcuJCJEye6HXSsth1iSpmLf6Tgi/faTSLSEi0w9D6gJpCJZgz9HpiqlMrycHwvT+cXkSHANUBPpZTSj8kGsvX/V4vITqApmvu2hT94M6iWYr766is2bdrEJ598wvvvv8+hQ4dITEykRYsW9O/fn9GjRxMfH+/2eKtthxBvOdNKeds2Mz7ZdJRSm4DRgb64iPRFM65eqZTKdNhe9f/bO/8gK6orj38OIDCioEgMRHSiKROCCsKMFIrLwrKbIGqtboXSKX4o+DvRiqUbVstSFy0TF6OrUcxiFI1i0GjQKAurBlHKQYOgDE6IZBnFZUQQFZlhGHSAs3/c+5jm8d7wfnW/fm/Op2rqvb7d9/Z37j39Tt/bp+8FvlDVPSJyAnAi8EGhz1+22Ky5GTN48GDuuOOOgpdrth0SFgZd8mQ1y3QIPAD0AF7xb4YnwkdHA7eJyG7cC6hXquoX6Ysx9mGz5sYFs+1CY2HQZUFRnY6qplyWUVX/APwhYjmljd0Bxgqz7QJhvfayo9g9HaMQ2B2gUY5Yr70sySRkenhH+1X1ncLJMXLC7gBz4p13Ojbd4cM7NH0jbGytm7Ikk57O3R3sU+AfCqTFyAZ7ES5vrr/++rT7RIRXX301QjXGPmytm7Imk5DpsVEIMbLAXoQrCEuXLj34QUa02Fo3ZU9Wz3RE5GRgMO7lUABU9fFCizLSYC95hkZ9fT1r165l1672V86mTp1aREWdCFvrplORsdMRkVuBMTinswg4C3gDMKcTBfaSZ2jMnDmT1157jbVr1zJhwgQWL17MmWeeaU4nCuwlz05HNj2dHwFDgXdVdZqIfBN4OBxZBmDhohHx7LPPUldXx7Bhw3j00UfZsmULl156abFllTcW4t9pycbptKrqXhHZLSK9gU+BE0LSZVi4aGRUVFTQpUsXunXrRlNTE0cffTQffGCTBISGhfh3arJxOitF5AjgN7iJP3cAK0JRZVi4aIRUV1fz5Zdfctlll1FVVcVhhx3GiBEjii2rfLFee6dG/DyE2WVyqx/2VtU1hRaUD9XV1bpyZYnPmxgMF7322v0j1OyCDJ0NGzbQ1NTEkCFDDtgnIqtUtboIskrftoNDxXBg9KXZdlGJ0razCSQYnSpNVZcVVlInxsJFi8KyZQea8LJlyxg9+gCTN3LBQvyNANkMr/0s8L0nMAI3zGYvh+aDhYsWnbvuumvf9127drFixQqqqqrs5dB8sRB/IwXZLFd9bnBbRI4FZhVcUWfCwkVjwYsvvrjf9saNG5kxY0aR1JQJFuJvpCGfCT8bgZMLJaTTcLCejQ07FJ2BAwdSX19fbBmlh4X4GxmQzTOd+3FzrQF0AU4F6sIQVbZk0rOxcNHIueaaa/Br3rB3715Wr17N0KFDi6yqxLAQfyNDsgqZDnzfDcxX1doC6ylvrGcTS6qr24N2unXrRk1NDaNGjSqiohLEbNvIkGye6fw2TCFljc2aG2suuuiiYksoXcy2jSzJZD2d92gfVjsAVT3whQajHQuDji2nnHLKvmG1VKxZE6vX0OKH2baRA5n0dM7xnz/xn0/4z0nAzoIrKgcsDLokWLhwIQCzZ88GYMqUKQA8+eSTHHrooUXTFWvMto08yWQ9nY8ARGSUqgYHum8QkVrgtrDElSQWBl0yVFZWAlBbW0ttbfvjyTvvvJNRo0Zxyy23FEtaPDHbNgpAlyyO7SUiZyY2ROQMoFc+JxeRfxeRj0Vktf+bENh3o4isF5F1IvLDfM4TCW++Cb/4BTz+eOoHqrffbtN9xJSWlhbeeOONfdvLly+npaUlrzLLxrYTdp3o4ZhtG3mSTfTaJcBcEenjt78EphdAw3+q6i+DCSIyGLgQOAn4FvAnEfmuqu4pwPkKj82aW9I88sgjTJ8+ne3btwNwxBFHMHfu3EIUXdq2bSH+RghkE722ChjqlzUQVd0eniz+GXhKVb8CPhSR9bhpd94M8ZzZYS/ClQ1VVVXU1dXR1NSEqtKnT5+DZ8qd0rFtW+vGCIFMotcmq+o8EbkuKR0AVb0nTw1Xi8hU3HtA16vqNuAY4K3AMY0+LZW+y4HLAY477rg8pWSIvQhXFsybN4/Jkydzzz2pTfi6665LmZ4FpW3b1ms3QiCTnk7iuc3huZxARP4E9E+x6ybg18DtuJDs24G7cUN2qeJYU4Ztq+pDwEPgpn/PRWPW2ItwZUHiuU1zc3NO+cvetsF67UbBySR6bY7/nJnLCVT1HzM5TkR+Ayz0m43AsYHdA4FNuZy/oNiLcGXFFVdcAcCtt96aU/6yse3gUPGYMdZrN0Il4+g1EZklIr1F5BARWSIin4nI5HxOLiIDApvnA4lZFl8ALhSRHiJyPHAixV6lNDHscPPNbnG1e++1qJ0yYcaMGTQ1NdHW1sa4cePo168f8+bNy6vMkrHtoF2PG+fSLCLNCJFsotd+oKozROR83N3aRGApkM/VOUtETsUNL2wArgBQ1b+IyO+Btbh53n5SlOgeexGuU/Dyyy8za9YsnnvuOQYOHMgzzzzD2LFjmTw5r3uq0rBtW+vGiJhsnM4h/nMCbrLPLzqaQiQTVHVKB/vuAO7I6wT5YC/CdRra2toAWLRoETU1NfTt2zfvMkvGtm2tGyNisnE6L4rI+0Ar8GMR+QawKxxZRcTCRTsd5557LoMGDaKiooIHH3yQrVu30rNnz2LLKiwW4m/EBFHNPChGRI4EmlR1j4j0Ag5X1c2hqcuS6upqXbly5cEPTEfyHaAI7N7dvq67XZBly7Zt2+jduzddu3alpaWF5uZm+vffPzBNRFapanWaIkIlL9tO1Wu/9tr2bbPtTk+Utp1NIMGhuEk/f+2TvgUU5QIMjeAd4J49MG2aPVDtBOzcuZPZs2dz1VVXAbBp0ybyunmJGzZ9jREjshleexRYBZzhtxuBZ2gPBS1NLFy00zNt2jSqqqpYvnw54JarnjhxIuecc85BcsYcC/E3Ykg2Tuc7qnqBiNQAqGqr5BtJUGyShx2WLLHnNp2QhoYGnn76aebPnw9ARUUF2Qw7xxJb68aIKdk4na9FpAL/9rSIfAf4KhRVYWPhokaA7t2709raum9qp4aGBnr06FFkVTlgIf5GCZCN07kV+B/gWBF5EhgFXByGqFCxcFEjiZkzZzJ+/Hg2btzIpEmTqK2t5bHHHiu2rOywEH+jRMjI6fhhtPeBfwFG4uaP+qmqfhaitsJh4aJGGlSVQYMGsWDBAt566y1Ulfvuu49+/foVW1pmWIi/UWJk5HRUVUXkeVWtAv47ZE2FxWaENjpARDjvvPNYtWoVZ599drHlZIfNCG2UINkMr70lIqep6tuhqQkDmxHaOAgjR47k7bff5rTTTiu2lOywXrtRgmTjdMYCV4jIR0ALbohNVXVIKMoKRXIYtN0BGkksXbqUOXPmUFlZSa9evVBVRIQ1a9YUW1rHWIi/UYJk43TOCk1FmJx+uvVsjA5ZvHhxsSXkhtm2UYJks1z1R2EKCRXr2RgdUFlZWWwJuWO2bZQYGU+DYxiGYRj5ktWEn3FHRLYC6Xpk/YC4hHjHSQvES0+ctMD+eipV9RvFEGG2nTNx0hMnLVAk2y4rp9MRIrKyWDMEJxMnLRAvPXHSAvHTk4o4aYyTFoiXnjhpgeLpseE1wzAMIzLM6RiGYRiR0ZmczkPFFhAgTlogXnripAXipycVcdIYJy0QLz1x0gJF0tNpnukYhmEYxacz9XQMwzCMImNOxzAMw4gOVY3VHzAX+BSoD6T1BV4B/td/HunTBfgVsB5YAwxPU2YV8J4/7le0DyserNwmYDewPlDWj4GdwNdAfQRaJvnyvgDakrT8H9CMW0xvewRaxvjzrAY+B3Yk2gkY74/fiYv9j6KdfhbQshu3wGDfkOtmIvAXYC9QnZTnRn/8OuCHgfTxXsNuYHMM7Hq9t6cvAu13EdDg229zRHriaNufey1bAmX9CDff5Nc+X1R2vRrYhrPrv/p9G4C1vm52FbidcrXtdX7fDRn9xufjIML4A0YDw9nf6cxK/EPADcB/+O8TgMW+skcCf05T5grgdH/cYuCsDMsdjbsYdwaM5EtgJnCkN9B7Q9Zyhj/XaODqhBa/bztwW4T1MgZYmNxOQFfcD9Yc4CagDrgnbD1JNvNTYEcEdfN94HvAawQuTGCw/797AMf7+ugaqJsLgBFAKzC4yHYtwJW4H556nF1/gPsBmum/z4xAT+xsm6TfH99+23y+7sAnwMNR2HUgfUVAzwbg/pDsJlfbPsHXTR3etjv8jT/YAcX4A77N/k5nHTDAfx8ArPPf5wA1qY4LpA0A3g9s1wBzMi3Xa/nK76/BOZ1EnieATWFqSco/BGgLbLcBJ0VYL2PwTifYTt6AX0rkw90V/TxsPUn5/wh8HHbdBNJeY/8L80bgxsD2S75eTgdeCtTX5sRxHdRz6HbttxtwizPW+H2J9psDXBVx+8XGtgn8/vj2awnk+TmwNcJ6+R3OsQSdzvow7CYf2051XLq/Unmm801V/QTAfx7t048BNgaOa/RpQY7x6amOybTcNp92DNAjkQf4G3BEyFqCXIDrVifoAjwhIquAczvQX0gtp4tInYgsBk5MOl8iXyPQOyI9iMihwN/jhkMThFU36UhXbjpb6uj/isquN+Mm/U3Vfr0i0BMkNrYNPIa7q0+U1S1wzf8VODwCLQm7Ho/rjSRQnFNcKCKXF9hu0pGpbWdSVlZLG8QRSZGmORyTabmp0sPW4jKKjMVdmFsCyTtUdbiIHI0b2020Z1ha3sHN0bRDRCbg4vwTayt1VFaodYP7UVoJ9A+kRV036fKkurHLtaxsj8mk3EzK6my2fTGu15CurGzOk69d1+KGGhOMwj3TOQt4RUTej0BPIW27ZHo6W0RkAID//NSnNwLHBo4bCGxKytvo01Mdk2m5h/g8jcBXiTzAd3HDbWFqQUSGAA8DlwF7Avk3i8gAVf0Ud2G2hqlFVZtUdYf/vghXL10D50vkG4i7aw27nRJcCLyQlBZW3aQjXbnpbAmKb9f9ccENqdpvZwR6YmnbuOElEZF+vqzdgWv++7T3yKKw6/nBBFXdhHPOXYHngHEUrp3SkaltZ1JWyTidF3AP9PGffwykTxXHSGB7oBsM7Ou2NovISBERYGpS/g7LBYYBe3w5L/n9V4rIkcDZwLNhahGR44AFwBTgw0RZItIL1+2+yH+fCLwespb+/lhEZATuDmgP8DZuqO11YDruYumZqj4L3E6ISB/c0NorEdVNOl4ALhSRHiJyvK+PFYm68WmHAH1od5BFs2tfbjPO6bwE/MB/Xum/9w9bT1xtGxjqPz/HtV8bcK2IdAemsX/7hW3XwbReInK4z3cprp2OpXDtlI6D2ravm1Q3fwdysIc+Uf/hPPsnuIZuBC4BjgKW4EILl9AeFivAbNwD0ffY/+HX6sD3atwD7wbgAdpDBA9WbrPXkbgbvAS4hvaQ6bURaHkYFz2zzWvZ67X8my8nEVbaEIGWq3EhlXW4sOjPAu10L+4BZyJkOvR28vsuxk35H7SZMOvmfH+Or3B3nMEHqTf549fhI4J8+gTaw+/3UHy7bsD10IPt9yguam2n/7+i0BNH296Gu7aD1/wFtF/zoWsJ2PVT7P97+AnuGUo97nWFQl9nudr23/y+mzL5jbdpcAzDMIzIKJXhNcMwDKMMMKdjGIZhRIY5HcMwDCMyzOkYhmEYkWFOxzAMw4gMczqGYRhGZJjTMQzDMCLDnE6JIyJ3i8haEbk/kFYhIq+LSFe/rSLyRGB/NxHZKiILA2k7ksq9WEQeSHPO7iKyTERKfe4+I6aYXZcvVrkljIicAIxS1cFJu6YDC1Q1MZdVC3CyiFSoaivwT8DHuZ5XVb8WkSW4N7WfzLUcw0iF2XV5Yz2dEkVEvoebj6pSRN71c1QlmMSB8yktxs0VB24NjflkgIhcKSKr/d+HIrLU73ren8cwCobZdfljTqdEUdV1wG+Bm1V1mKq2gBsiAE5Q1Q1JWZ7CTdrXE7dg1p+T9lcELsLVwG3+PP+lqqcCp+HmZbrHH1/v0wyjYJhdlz82vFbanMKBd379aF9uYR+qukZEvo27G1yUoqxWfxECbuwbNzFggvuAV1X1RV/eHhH5WkQOV9VmDKNwmF2XMeZ0SpuTcDPjBmnFLSuQiheAX+KW5j0q05P4C7USNxNvkB7ArkzLMYwMMbsuY8zplCh+XY02Vd0ZTFfVbSLSVUR6qmryhTMXt8bGeyIyJsPzVAH/Cvydqu4NpB+FWyu+La9/xDACmF2XP/ZMp3Q5GTf+nIqXgTOTE1W1UVXvy/I8VwN9gaV+XPxhnz6W1MMZhpEPZtdljq2nU4aIyDDgOlWdEuI5FgA3+ge/hhE6ZtflgfV0yhBVfRd3B9c1jPJ9JNHzdmEaUWJ2XR5YT8cwDMOIDOvpGIZhGJFhTscwDMOIDHM6hmEYRmSY0zEMwzAiw5yOYRiGERnmdAzDMIzI+H9Dx5N93JbTQgAAAABJRU5ErkJggg==\n", - "text/plain": [ - "" - ] - }, - "metadata": {}, - "output_type": "display_data" - } - ], - "source": [ - "def phase_residuals(data,prediction):\n", - " r = np.remainder(data-prediction+180,360)-180\n", - " return r\n", - " \n", - "def phase_model(x, f0):\n", - " return np.remainder(x[0] - 360*x[1]*(f0), 360)\n", - "\n", - "def phase_func(x, arg):\n", - " resid = phase_residuals(arg, phase_model(x, f0_v))\n", - " return resid\n", - "\n", - "from scipy.optimize import least_squares\n", - "fig, axs = plt.subplots(2,2)\n", - "for ch in range(2):\n", - "\n", - " slopes = -1*(fi_v[ch,1:]-fi_v[ch,:-1])/(360*(f0_v[1:]-f0_v[:-1]))\n", - "# print(slopes)\n", - " x0 = np.zeros(2)\n", - " x0[1] = np.median(slopes)\n", - " x0[0] = np.remainder(np.median(phase_residuals(fi_v[ch],phase_model(x0, f0_v))),360)\n", - " print(\"initial estimate: %.2f deg shift, %.2f us delay\"% tuple(x0))\n", - "\n", - " fit = least_squares(phase_func, x0, args=(fi_v[ch],))\n", - "# fit = least_squares(phase_func, x0, args=(fi_v[ch]), method='lm', x_scale='jac')\n", - "# fit = least_squares(phase_func, x0, args=(fi_v[ch]), method='lm', x_scale=(1,1e-5))\n", - " fit.x[0] = np.remainder(fit.x[0],360)\n", - "# print(fit.status)\n", - " print(\"after minimization: %.2f deg shift, %.2f us delay\"% tuple(fit.x))\n", - "\n", - " plot = axs[0,ch]\n", - " plot.set_title(r\"$\\phi$ vs $f$\")\n", - " plot.set_ylabel(r\"$\\phi$ (degrees)\")\n", - " plot.set_xlabel(r\"$f$ (MHz)\")\n", - " plot.plot(f0_v,fi_v[ch], marker='.', linestyle=\"None\",color=\"Red\")\n", - " plot.plot(f0_v, phase_model(fit.x, f0_v))\n", - "\n", - " plot = axs[1,ch]\n", - " plot.set_ylabel(r\"residual (degrees)\")\n", - " plot.set_xlabel(r\"$f$ (MHz)\")\n", - " \n", - " plot.plot(f0_v, phase_func(fit.x, fi_v[ch]), marker='.', linestyle=\"None\",color=\"Red\")\n", - "# plot.plot(f0_v, phase_func(x0, (fi_v[ch])), marker='.', linestyle=\"None\",color=\"Red\")\n" - ] - }, - { - "cell_type": "code", - "execution_count": 13, - "metadata": {}, - "outputs": [], - "source": [ - "# \"product\" (0) and \"dds\" (1) work as advertised; \"input\" (2) seems identical to \"product\" and 3 to \"dds\"\n", - "# soc.readouts[0].outsel_reg = 0\n", - "\n", - "#nsamp=1 or 2 fails in a strange way: \n", - "#the signal generator plays the entire waveform memory repeatedly for 10-20 seconds\n", - "#during this time, new \"set\" commands don't work\n", - "\n", - "\n", - "# is there ever a reason not to enable both avg and buf?\n", - "# soc.avg_bufs[ch].config_buf(address=0, length=readout_length)\n", - "# soc.avg_bufs[ch].enable_buf()\n", - "# soc.avg_bufs[ch].disable_avg()\n", - "\n", - "\n", - "\n", - "# print(soc.get_accumulated(ch=ch, length=1).T/readout_length, xavg)\n" - ] - } - ], - "metadata": { - "kernelspec": { - "display_name": "Python 3", - "language": "python", - "name": "python3" - }, - "language_info": { - "codemirror_mode": { - "name": "ipython", - "version": 3 - }, - "file_extension": ".py", - "mimetype": "text/x-python", - "name": "python", - "nbconvert_exporter": "python", - "pygments_lexer": "ipython3", - "version": "3.8.2" - } - }, - "nbformat": 4, - "nbformat_minor": 4 -} diff --git a/qick/qick_demos/01_phase_calibration.asm b/qick/qick_demos/01_phase_calibration.asm deleted file mode 100644 index d760146..0000000 --- a/qick/qick_demos/01_phase_calibration.asm +++ /dev/null @@ -1,48 +0,0 @@ -// Signal Generator V4. -// 31 .. 0 : frequency. -// 63 .. 32 : phase. -// 79 .. 64 : addr. -// 95 .. 80 : xxxx (not used). -// 111 .. 96 : gain. -// 127 .. 112 : xxxx (not used). -// 143 .. 128 : nsamp. -// 145 .. 144 : outsel (00: product, 01: dds, 10: table, 11: zero value). -// 146 : mode (0: nsamp, 1: periodic). -// 147 : stdysel (0: last value, 1: zero value). -// 148 : phrst (not implemented yet). -// 159 .. 149 : xxxx (not used). - - // channels 4, 5, 6, 7 -> DAC 229 CH0/1/2/3. - memri 1, $1, 123; // freq. - memri 1, $2, 124; // phase. - regwi 1, $3, 32000; // gain. - regwi 1, $4, 10; // nsamp. Generator will consume 16*nsamp DAC values. - regwi 1, $5, 0x4; // b00100 -> phrst = 0, stdysel = 0, mode = 1, outsel = 00 - bitwi 1, $5, $5 << 16; - bitw 1, $4, $4 | $5; -// regwi 1, $6, 785; // start time. - regwi 1, $6, 0; // start time. - - synci 1000; - - regwi 0, $1, 0x1; // Send a pulse on pmod 0_0 (pin 1 on J48 on the ZCU111). - seti 0, 0, $1, 0; // Start the pulse. - seti 0, 0, $0, 100; // End the pulse after 100 ticks (260 ns). - - // Program signal generators in periodic mode. - set 1, 1, $1, $2, $0, $3, $4, $6; - set 2, 1, $1, $2, $0, $3, $4, $6; - set 3, 1, $1, $2, $0, $3, $4, $6; - set 4, 1, $1, $2, $0, $3, $4, $6; - set 5, 1, $1, $2, $0, $3, $4, $6; - set 6, 1, $1, $2, $0, $3, $4, $6; - set 7, 1, $1, $2, $0, $3, $4, $6; - - synci 1000; - - // Set trigger. - regwi 0, $1, 0xc000; // Trigger both ADC channels. - seti 0, 0, $1, 0; - seti 0, 0, $0, 100; - - end; \ No newline at end of file diff --git a/qick/qick_demos/02_Sweeping_variables.ipynb b/qick/qick_demos/02_Sweeping_variables.ipynb deleted file mode 100644 index e6c4bd1..0000000 --- a/qick/qick_demos/02_Sweeping_variables.ipynb +++ /dev/null @@ -1,306 +0,0 @@ -{ - "cells": [ - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "#
Sweeping variables demonstration\n", - "\n", - "###
In this demo you will sweep the amplitude of a pulse in loopback to demonstrate control over the QICK. \n", - "\n", - "We will sweep in two ways:\n", - "* Within the QICK assembly language (advantage: faster, disadvantage: cannot be used to sweep the readout frequency)\n", - "* With a Python outer loop (advantage: can sweep any parameter, disadvantage: slower)" - ] - }, - { - "cell_type": "code", - "execution_count": 1, - "metadata": {}, - "outputs": [ - { - "data": { - "application/javascript": [ - "\n", - "try {\n", - "require(['notebook/js/codecell'], function(codecell) {\n", - " codecell.CodeCell.options_default.highlight_modes[\n", - " 'magic_text/x-csrc'] = {'reg':[/^%%pybind11/]};\n", - " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", - " Jupyter.notebook.get_cells().map(function(cell){\n", - " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", - " });\n", - "});\n", - "} catch (e) {};\n" - ] - }, - "metadata": {}, - "output_type": "display_data" - }, - { - "name": "stdout", - "output_type": "stream", - "text": [ - "Populating the interactive namespace from numpy and matplotlib\n" - ] - } - ], - "source": [ - "# Import the QICK drivers and auxiliary libraries\n", - "from qick import *\n", - "from tqdm.notebook import tqdm\n", - "%pylab inline" - ] - }, - { - "cell_type": "code", - "execution_count": 2, - "metadata": {}, - "outputs": [], - "source": [ - "# Load bitstream with custom overlay\n", - "soc = QickSoc()\n", - "# Since we're running locally on the QICK, we don't need a separate QickConfig object.\n", - "# If running remotely, you could generate a QickConfig from the QickSoc:\n", - "# soccfg = QickConfig(soc.get_cfg())\n", - "# or save the config to file, and load it later:\n", - "# with open(\"qick_config.json\", \"w\") as f:\n", - "# f.write(soc.dump_cfg())\n", - "# soccfg = QickConfig(\"qick_config.json\")\n", - "soccfg = soc\n", - "# print(soccfg)\n" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### Hardware Configuration\n", - "\n", - "tProc channel 7 : DAC 229 CH3 <-> Readout channel 0 : ADC 224 CH0" - ] - }, - { - "cell_type": "code", - "execution_count": 3, - "metadata": {}, - "outputs": [], - "source": [ - "class LoopbackProgram(AveragerProgram):\n", - " def initialize(self):\n", - " cfg=self.cfg \n", - "\n", - " # set the nyquist zone\n", - " self.declare_gen(ch=cfg[\"res_ch\"], nqz=1)\n", - "\n", - " #configure the readout lengths and downconversion frequencies\n", - " self.declare_readout(ch=cfg[\"ro_ch\"], length=self.cfg[\"readout_length\"],\n", - " freq=self.cfg[\"pulse_freq\"], gen_ch=cfg[\"res_ch\"])\n", - "\n", - " freq=self.freq2reg(cfg[\"pulse_freq\"], gen_ch=cfg[\"res_ch\"], ro_ch=cfg[\"ro_ch\"]) # convert frequency to dac frequency (ensuring it is an available adc frequency)\n", - " self.set_pulse_registers(ch=cfg[\"res_ch\"], style=\"const\", freq=freq, phase=0, gain=cfg[\"pulse_gain\"], \n", - " length=cfg[\"length\"])\n", - " self.synci(200) # give processor some time to configure pulses\n", - " \n", - " def body(self):\n", - " self.measure(pulse_ch=self.cfg[\"res_ch\"], \n", - " adcs=[self.cfg[\"ro_ch\"]],\n", - " adc_trig_offset=self.cfg[\"adc_trig_offset\"],\n", - " wait=True,\n", - " syncdelay=self.us2cycles(self.cfg[\"relax_delay\"]))" - ] - }, - { - "cell_type": "code", - "execution_count": 4, - "metadata": {}, - "outputs": [], - "source": [ - "class SweepProgram(RAveragerProgram):\n", - " def initialize(self):\n", - " cfg=self.cfg \n", - "\n", - " # set the nyquist zone\n", - " self.declare_gen(ch=cfg[\"res_ch\"], nqz=1)\n", - "\n", - " self.r_rp=self.ch_page(self.cfg[\"res_ch\"]) # get register page for res_ch\n", - " self.r_gain=self.sreg(cfg[\"res_ch\"], \"gain\") #Get gain register for res_ch\n", - " \n", - " #configure the readout lengths and downconversion frequencies\n", - " self.declare_readout(ch=cfg[\"ro_ch\"], length=self.cfg[\"readout_length\"],\n", - " freq=self.cfg[\"pulse_freq\"], gen_ch=cfg[\"res_ch\"])\n", - " \n", - " freq=self.freq2reg(cfg[\"pulse_freq\"], gen_ch=cfg[\"res_ch\"], ro_ch=cfg[\"ro_ch\"]) # convert frequency to dac frequency (ensuring it is an available adc frequency)\n", - " self.set_pulse_registers(ch=cfg[\"res_ch\"], style=\"const\", freq=freq, phase=0, gain=cfg[\"start\"], \n", - " length=cfg[\"length\"])\n", - " self.synci(200) # give processor some time to configure pulses\n", - "\n", - " def body(self): \n", - " self.measure(pulse_ch=self.cfg[\"res_ch\"], \n", - " adcs=[self.cfg[\"ro_ch\"]],\n", - " adc_trig_offset=self.cfg[\"adc_trig_offset\"],\n", - " wait=True,\n", - " syncdelay=self.us2cycles(self.cfg[\"relax_delay\"])) \n", - " \n", - " def update(self):\n", - " self.mathi(self.r_rp, self.r_gain, self.r_gain, '+', self.cfg[\"step\"]) # update gain of the pulse" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### Sweeping via the QICK assembly language\n" - ] - }, - { - "cell_type": "code", - "execution_count": 5, - "metadata": {}, - "outputs": [], - "source": [ - "config={\"res_ch\":6, # --Fixed\n", - " \"ro_ch\":0, # --Fixed\n", - " \"relax_delay\":1, # --Fixed\n", - " \"res_phase\":0, # --Fixed\n", - " \"pulse_style\": \"const\", # --Fixed\n", - " \"length\":100, # [Clock ticks] \n", - " \"readout_length\":200, # [Clock ticks]\n", - " \"pulse_gain\":0, # [DAC units]\n", - " \"pulse_freq\": 100, # [MHz]\n", - " \"adc_trig_offset\": 100, # [Clock ticks]\n", - " \"reps\":50, \n", - " # New variables\n", - " \"expts\": 20,\n", - " \"start\":0, # [DAC units]\n", - " \"step\":100 # [DAC units]\n", - " }\n", - "\n", - "prog =SweepProgram(soccfg, config)\n", - "expt_pts, avgi, avgq = prog.acquire(soc, load_pulses=True, progress=True)" - ] - }, - { - "cell_type": "code", - "execution_count": 6, - "metadata": {}, - "outputs": [ - { - "data": { - "image/png": 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nAPjP//xPcnNz2b59O9u3b+fjjz+mqKjorPP/7Gc/40c/+hF79+4lPDycV155pVXel1Jg/b/cdmIbz216jmnvTOPutLv5cN+HXN39ap6f+Dxr5qzhufHPMSl+En7e7X/s0YVyskQRDawSkW3AF0CGMWYJ8DPgxyKyD4gE2uQ3ycqVKwkICODuu+8GwNvbmz/+8Y+8/vrrFBcX1zt2zpw5fPLJJ7X377rrLt577z0yMzO59tprGTZsGMOGDTtr8SCwFhlyn55j1qxZrF69GoD09HTGjBnDsGHDuOWWW2pf9xe/+AUfffRRo3G/9957XH/99cydO5e33nrrnO9vzpw5JCcn8+abb1JSUsL//d//8Ze//AV/f3/Amufp1ltvrfccYwwrV67k5put3wE69bhqDcYYdp3cxZ+2/IkZ78/gtk9uY9HuRQzsMpDfjv8ta+as4fcTfs+0hGkE+AQ4Ha5HcrLX0zZgaCP7DwAjm/XFli2Ao9806ynpPghmnHshnm+//Zbhw4fX2xcaGkpiYiL79u1jyJAhtfvnzp3LokWLmDlzJhUVFaxYsYIXXngBYwwZGRkEBASwd+9e5s2bR8MR6OeSl5fHM888w/LlywkODua5557j+eef5xe/+AW/+tWvzvm8hQsX8stf/pJu3bpx88038+STT57z2GHDhrFr1y727dtHfHx87foU55Kfn0/nzp3x8bH+2cXGxnL48OELej9KXawDhQdIzUxl2cFlZJ7OxFu8GdNjDA9d9RCT4ycT4hfidIhtRsdqum9F55qOu7EpU2bMmMH8+fMpLy8nNTWV8ePHExgYyKlTp3jkkUf46quv8Pb2Zs+ePRf8+hs3bmTHjh218zxVVFSc1e7Q0LFjx9i3bx/jxo1DRPDx8WH79u3nbA+52OlfGjtepyxXzSm7KJu0zDSWHVzGnoI9CMLV3a/mjgF3MDV+KuEB4U6H2CZ1jETRxC//ljJgwADee++9evtOnz7NsWPH6Nu3b739AQEBTJw4kbS0NBYtWlQ7o+sf//hHunXrxtdff43L5SIg4OxicVNTj0+bNq3JlesaWrRoEQUFBSQlJdXG+9Zbb/HMM880evyXX37JiBEj6NWrF4cOHaKoqIiQkHP/SuvSpQuFhYVUVVXh4+NDTk4OPXr0uOD4lGrM0TNHSc9MJzUzlW/yrJqDq6KuYsHIBSQnJBMVFOVwhG2fR/R6ao+mTJlCSUkJr7/+OmAtJvT444/zyCOPEBgYeNbxc+fO5Z///Cfr1q0jJSUFsKYej46OxsvLi3/9619UV1ef9bzExES++uorXC4X2dnZbNq0CYDRo0fz6aefsm/fPsCaMbamRPLkk0+yePHis861cOFCUlNTyczMJDMzky1btpyzneK9994jPT2defPmERQUxL333sv8+fNrezHl5uby73//u95zRIRJkybx7rvvAujU4+qS5ZXmsXDXQu5cdifT3p3G7zb/jipXFT8e/mPSvpvGv2f+m9v636ZJoploomghIsLixYt599136d27N5GRkXh5efHUU081enxycjJr165l6tSptTO9Pvzww7z22muMHj2aPXv2EBwcfNbzxo4dS1JSEoMGDeKJJ55g2LBhAERFRfHqq68yb948Bg8ezOjRo9m1axcA33zzzVkr52VmZnLo0CFGjx5duy8pKYnQ0FA+//xzwCrh1HSP/fe//83KlSuJirL+Iz7zzDNERUVx5ZVXMnDgQG688cbax9zVtJX06tWL/Px87r333ou9tKqDyivNY9GuRdyTdg+T357Mbz7/DafKT/GDIT/g4xs/5u3r3+bugXfTo5OWUpubTjPeSjZs2MC8efN4//33z2rkbm0pKSmkpaU5GkNL8LTPXF2+k2UnWXFoBWkH0/ji2Be4jIuksCSmJ04nOSGZXuG9nA6xTdNpxj3MNddc0+iqdU5oj0lCtR+FZYVWcshMY9PRTVSbahJCE7hv0H2kJKbQu3Nv7QTRyjRRKKUcd6r8FCsPrSQtK43Pj3xOlakiLiSOewbeQ0piCn3C+2hycJAmCqWUI4oqiliVvYrUg6l8lvsZVa4qYjrFcMeAO0hJTKF/RH9NDh5CE4VSqtUUVxSzOmc1aQfT+PTIp1S6KokOjuY/+v8HKYkpDIgcoMnBA2miUEq1qJLKEtbkrKldDa7CVUHXoK7M7TeXlMQUBncZrMnBw2miUEo1u9KqUtblrCM1M7V2qdCowChu6XsLKYkpXBV1FV6ivfPbCv2kWtjixYsRkdoxDM1h9erVzJo1C4CPPvqIZ5+1Rp5/8MEH9ab+vlATJ0684DmkzkWnJlfl1eWsyFrBT9f8lAmLJvD4msfZcmwLs3vN5p8p/yTj5gwWjFzA0K5DNUm0MfpptbCFCxcybty4JmdivRw33HADCxYsAC49UVwunZq846qormB19moWrFvAhEUTeGz1Y2zM3cisnrP4e/LfWXnLSv7f6P/HiO4jOsSSoe2VJooWVFxczKeffsorr7xSL1GsXr2aCRMmcOutt9KnTx8WLFjAG2+8wciRIxk0aBD79+8HrOnGH3zwQa699lr69OnDkiVLznqNmmnGN2zYwEcffcRPfvIThgwZwv79++uVFPLy8khMTASgtLSUuXPnMnjwYObMmUNpaWnt+XRqcnU+Ncnh5+t+zsRFE3l05aOsP7ye6YnTeWnaS6y8dSW/GPMLRkWP0uTQTnSINornNj3HrpPNV/UD0C+iHz8b+bMmj/nggw+YPn06ffr0ISIigq1bt9ZOsfH111+zc+dOIiIi6NmzJ/fddx+bNm3iz3/+M3/5y1/405/+BFhTa6xZs4b9+/czadKk2rmbGrrmmmu44YYbmDVrVu2X6rm88MILBAUFsW3bNrZt21Ybk05Nrs6lorqCDUc2kJ6ZzqrsVRRXFhPiF8Lk+MlMT5rOqOhR+Hp17FXg2rMOkSicsnDhQh577DHAmvRv4cKFtV/KV199NdHR0QBcccUVJCcnAzBo0CBWrVpVe45bb70VLy+v2uVUm6OtY+3atcyfPx+AwYMHM3jwYECnJlf11SSHtMw0VmevpriymFC/UKYmTCU5IZnR0aM7/BKhHUWHSBTn++XfEvLz81m5ciXbt29HRKiurkZE+O1vfwtQW90C4OXlVXvfy8uLqqqq2scafilezJek+xTkNdOPN3UenZpclVeXs+HwBtKz0s9KDimJKYzqPkqTQwekbRQt5N133+WOO+4gKyuLzMxMsrOzSUpKYv369Rd1nnfeeQeXy8X+/fs5cODAWWtZuAsJCanXGJyYmMiWLVtq46kxfvx43njjDQC2b9/Otm3bAJ2avKMqry5n1aFVPLnuSSYsmsD8VfNZm7OWaQnTeGHqC6y+dTX/Pfa/GRczTpNEB6WJooUsXLiQ73znO/X2ffe73+XNN9+8qPP07duXCRMmMGPGDF588cVGFy+qMXfuXH73u98xdOhQ9u/fzxNPPMELL7zANddcQ15eXu1xDz30EMXFxQwePJjf/va3jBxprTyrU5N3HDUN0g2TQ3JCspUc5qzmV2N/pclBATrNuEe76667LqhxujW0hanJ28Nn3pKqXFVsyt3EssxlrDi0gqKKIkL9QpkSP4WUxBRGRo/UBukORqcZV83K05OEaly1q5qtx7eSejCVjKwMCsoLCPYNrk0OY6LHaIlBnZdjiUJE4oDXge6AC3jZGPNnEYkAFgGJQCZwqzGmwKk4nfTqq686HYJqg1zGxbYT20jNTCU9M50TpScI9AlkQuwEpidNZ1zMOPy9/c9/IqVsTpYoqoDHjTFbRSQE2CIiGcBdwApjzLMisgBYAFxStyVjjHal7CDaQxXq5TDGsCN/B6mZqaRlppF7Jhc/Lz+ujb2W6YnTGR87niDfIKfDVG2UY4nCGJML5Nq3i0RkJxADzAYm2oe9BqzmEhJFQEAA+fn5REZGarJo54wx5OfnN9nQ3x4ZY9hTsIe0zDRSM1PJLsrGR3y4JuYaHh36KJPiJtHJr5PTYap2wCPaKEQkERgKfA50s5MIxphcEel6juc8ADwAEB8ff9bjsbGx5OTk1M4rpNq3gIAAYmNjnQ6jxdWUHDKyMlh+aDlZp7PwEi9Gdh/JfYPuY0r8FML8w5wOU7UzjicKEekEvAc8Zow5faG//o0xLwMvg9XrqeHjvr6+tYPAlGrLXMbF1ye+JiMrgxVZKzhy5gje4s3V3a/mjivvYHL8ZLoEdnE6TNWOOZooRMQXK0m8YYx53959TESi7dJENHDcuQiVckaVq4otx7aQkZXBykMrOVF6Al8vX8b0GMODVz3IpLhJdA7o7HSYqoNwsteTAK8AO40xz7s99BFwJ/Cs/fdDB8JTqtVVVlfyWe5nLM9azqrsVRSWFxLgHcC1sdcyJX4KE2InaJuDcoSTJYqxwO3ANyLylb3v51gJ4m0RuRc4BNziUHxKtbiyqjI+PfIpGVkZrMleQ3FlMcG+wUyIncC0hGmMjRlLoE+g02GqDs7JXk/rgXM1SExpzViUak3l1eWsP7yetINprM5ZTWlVKWH+YUxNmMq0hGmMjh6Nn7ef02EqVcvxxmylOoKaaqXUg6m16zmE+4czq+cspiVMY0T3ETp9hvJYmiiUaiGVrko25W4iLTONFYdWcLriNCF+IUxLmMb0xOmMjB6Jj5f+F1SeT/+VKtWMql3VbD62mdTMVJZnLaewvJBg32Amx1krwencSqot0kSh1GVyGRdfHv+yduK9/LJ8An0CmRg7kZSkFJ1bSbV5miiUugTGGLblbSP1YCrpWekcLzmOv7c/42PHk5KYwvjY8dpbSbUbmiiUukDGGHac3EHawTTSMtM4cuYIvl6+jI0Zy4+H/5iJcRMJ9g12Okylmp0mCqWa4D7xXlpmGoeKDuEjPozuMZqHhzzMpPhJhPqFOh2mUi1KE4VSjThw6gBpB61ZWQ+cOlA78d49A+9hSvwUnT5DdSiaKJSyZZ/OJjUzldTMVPYU7EEQhncbzvf6fY+pCVOJDIx0OkSlHKGJQnVoR4qP1K7nsCN/BwBDooawYOQCpiVMo2tQo7PcK9WhaKJQHc7RM0dJz0wnLSuNbSe2ATAwciBPjHiC5IRkojtFOxyhUp5FE4XqEI6XHCcjK4O0zDS+PP4lAP0j+vPDYT8kJTGFuJA4hyNUynNpolDtVl5pXm1y2HpsKwZDn/A+zB86n+TEZBJCE5wOUak2QROFalfyS/NZcWgFqZmpbD66GYOhV+dePDzkYZITk+kZ1tPpEJW6bC6X4XhROdkFJUQG+9EzqmXXKdFEodq8grIClh9aTlpmGl8c/QKXcZEYmsj3r/o+KQkp9Arv5XSISl0UYwyFJZVkF5SQfbLU/ltCdkEpOSdLyCkspaLKBcD3x/fkyZn9WzQeTRSqTTpVfoqVh1aSmpnK57mfU22qiQ+J596B9zI9aTq9O/fmQtdfV8oJZ8qryCkotRNA/YSQU1BKcXlVveM7B/kSFx5Ev+gQpl3ZjdiIIOLCA+nbPaTFY9VEodqM4opiVmWvIjUzlQ1HNlDlqiK2Uyx3DbiL6UnT6RveV5OD8hhlldUcLiytKwkUlJBz0vqbXVDKyTMV9Y4P9PUmLiKQuPAgRveMJDY8kLiIIOLCg4iLCCQkwLlZhzVRKI9WUlnCmpw1pB5MZf3h9VS4Kuge3J3b+t3GjKQZXBl5pSYH5YjKahe5hWVkF5RYX/52iaCmlHC8qLze8X7eXsSEBxIbHkhKjzDiIgKJDbdKBXERQUQG+3nsv2VNFMrjlFWVse7wOlIPprI2Zy1l1WVEBUZxS99bmJ44ncFRg/ESL6fDVO2cMYZTpZUcOllSu2W73T5SWEa1y9Qe7+0l9OgcQGznICb2jbKSgF1CiA0PomuIP15enpkIzkcThfIIFdUVbDiygWUHl7E6ezUlVSVEBEQwu9dsUhJTGNZ1GN5e3k6HqdqZiioXRwpLG00Eh06WUFRWv52gSyc/4iKCGBYfzo1DaqqFgogNDyQ6LAAf7/b5A0YThXJMpauSz3M/J/VgKisPraSosogw/zBmJM0gJTGFq7tfrUuFqstijOHkmYpGE0H2yVJyT5XiVijAz8eLuPBA4iOCGJEQTlxEEPERQcQadjEaAAAgAElEQVRHWkkh2L9j/nt09F2LyD+AWcBxY8xAe18EsAhIBDKBW40xBU7FqJpXpauSL3K/IC3LWkf6VPkpOvl2YnL8ZKYnTmd0j9H4eulSoerClVVW17YLnJ0MSjhTUV3v+KgQf+IjghiZFFHbPpAQGUx8RNuuHmpJTqfHV4G/Aq+77VsArDDGPCsiC+z7P3MgNtVMqlxVbDq6ifTMdFYcWkFheSFBPkFMip9EckIyY2PG6lKh6pyqql3kniqrbSjOsXsR1XQjPXq6rN7xAb5exNu9hUb3jLRKBHapIDY8kCA/p7/22h5Hr5gxZq2IJDbYPRuYaN9+DViNJoo2p8pVxeZjm0nLTGNF1goKygsI8gliYtxEUhJTNDmoWi6X4URxeb3xBO69iHJP1W809hKIDrN6D43t1cVOAlZ1UVxEEFGd/D2291Bb5YmptZsxJhfAGJMrIo3O8ywiDwAPAMTHx7dieOpcql3VbD62mfTMdJYfWs7JspME+gQyMbYuOQT4BDgdpmplNb2Har74a6qEGhtlXCMqxJ+48ECGJ4Rb4wnsRuO48CC6hwXg59M+G409lScmigtijHkZeBlgxIgR5jyHqxZS7apm6/GtpGWmkZGVUZscJsROqE0OgT6BToepWlhpRbU9kMwqCTRMBkUNRhmHBfoSH+E2yjg80B5pbFUPBfhqDzdP4omJ4piIRNuliWjguNMBqfpcxsWXx78k9WAqGVkZ5JflE+AdwPjY8aQkpnBt7LWaHNqZ2naCBtNN1PQeyiuuP7gswNerthQwMjHc7kJqjyuICCLUwVHG6uJ5YqL4CLgTeNb++6Gz4Siwqg+25W0j9WAq6VnpHC85jr+3f11yiLmWIN8gp8NUl8iYmnaCmvaB+smgYTuBt5cQHRZAXHgQU/p1rU0ANclA2wnaF6e7xy7EarjuIiI5wC+xEsTbInIvcAi4xbkIOzZjDDtO7iDtYBppmWkcOXMEXy9fxsaM5cfDf8zEuIkE+wY7Haa6AMYYTpdWnXO6ieyCEsoq67cTdOnkT1xEIMPiw+2G4rq2gvY8uEydzeleT/PO8dCUVg1E1TLGsKdgT+060tlF2fiID2N6jOEHQ3/ApLhJhPi1/GyV6uIVl1fVJoF6f8/RThDi70NsRBBJXYIZ3yeqXjKIDQ8i0E/bCZTFE6uelAMOFB4gNTOV1MxUDp46iLd4M7L7SO4bdB9T4qcQ5h/mdIgdXnF5FYcLSjlcaI8nqJmR1C4VFJRU1ju+ZjbS2HCrnaCmWsiaiC6IsCBtJ1AXRhNFB5Z1Oqu25LC3YC+CcHX3q/mP/v/B1ISpRAREOB1ih3K6rJLDbgmg9nahdbthIvDz8SK2s9VbaGBMWG2PoTh7nYIID56NVLUtmig6mOyibNIy00jPTGfnyZ0ADOs6jCdHPklyYjJdArs4HGH75XIZck+XkZV3hoP5Z8jKLyEz70xtYjjdYAK6AF8vYsODiOkcyFWxnYm1E0HNVNVdgnW6CdU6NFF0AEeKj5CemU5qZirf5n8LwOCowfxkxE9ITkyme3B3hyNsP6pdhiOFpWTmnyEzv4SsPOtvZv4ZDp0sqTewzM/Hq3Z6iZqBZbHhQbWJwJPXJ1AdiyaKduromaOkZ6aTlpXGthPbABgYOZDHhz9OcmIyPTr1cDjCtutMeRWHC+sajLPsRJCZf4bskyVUVtd1Iw3w9SIxMpgrooKZ0q8rCZHBJEYGkdglmO6hAVoiUG2CJop25ETJCdKz0knLTOPL418C0D+iP48Ne4zkxGTiQuIcjrBtqFnLuKahOKegxE4M1tZwCcsgP28SIoPp2y2E5Cu7k9QlyE4IwTobqWoXNFG0cXmleSzPWk5aZhpbjm3BYOgT3odHhz5KSmIKCaEJTofocRpOS12XEKyk0LDR2N/Hq7ZaaFBMWG1bQU17gQ4uU+2dJoo26EzlGVYcWsHSA0vZmLsRl3FxRdgVPDTkIVISUujZuafTITqqZrGarJq1CfJLyHJbn+Do6TKM2+xg7olgcGz9RBAbHkSXTtpWoDo2TRRtRKWrks+OfMaS/UtYlb2KsuoyYjrFcO/Ae5mZNJNe4b2cDrFVlVVW11YHHTpZwiG7sTgrv/HFarqFWovVjLkikoSIYJ2WWqmLoInCgxlj+PrE1yw9sJS0zDQKygvo7N+Z2b1mM6vnLK6KuqrdfsHVVA+5VwvVNCDnFJRyoqj+JHT+Pl7WSmURdYvVJERaPYp0lLFSl0cThQfKPJXJ0oNLWXpgKdlF2fh7+zMpbhLX9byOsT3G4uvd9kfUVlS5yCmwqoRyCkrtwWV1SaHhbKS+3kKPzlZ10OS+Xe1pqQOJ6WwlhKhO2misVEvRROEh8krzSD2YytIDS9mevx1BGBU9iu8P/j5T4qfQya+T0yFetDPlVWTll3DopD2mwL6dlV/CkcL6i9r7egsxna02gan9u9a2D9T8jQrxx1sTgVKO0EThoOKKYlZlr6ptlK421fSP6M8TI55gRtIMugY1urifx3BvND5UM6jMbjjOyi85q1QQHuRLQmQwwxPCuWloDPGRwSREWvMOaTdSpTyXJopWdrriNGuy15Cemc6nRz6l0lVJj+Ae3DPwHq7reR1XdL7C6RBr1SSChhPQuY8rKGnQaBwdFkBCpLVGQXykVS2UGBlMfKQuVqNUW3XJiUJElhhjZjVnMO3VqfJTrMpeRXpmOp/lfkaVq4puQd2Y03cOyYnJXBV1FV7S+nP7G2PIr00EJfUmpKtJDqWV9RNBaIAPseHWl/+4XlHEhAeSEBFEYher0ViXsFSq/bmcEsX9zRZFO1RQVlCbHD7P/ZwqU0WP4B7c1u82khOTGdhlYKskh7LK6tqBZdZf9/WMS84qEYQF+hIbHkjPKGuNAve2gpjwQC0VKNUBXXKiMMbkNmcg7UF+aT4rs1eSkZnBpqObqDbVxHaK5fYBt5OSkMKVkVc2e3dWl8twrKisdkH72iRg3z7eoBtpoK937fiBsb261C5UE6OJQCl1DheUKETkIGAa7jfGdOwhwFi9lVZkrSAjK4Mvjn2By7iID4nn7oF3k5yQTL+IfpedHE6VVtZ++bsvaF+zlKX7jKQi0CMskLiIQCbYq5bFR1qJIT4iSGckVUpdtAstUYxwux2AtY51h13V5uiZo6w4ZCWHrce2YjAkhiZy36D7SE5Ipk94n4v6Mi6vquawPcI4u2YN45qkkH/2OgVhgb7ERQTSt1sIU/t3qy0hxEdYaxf4+ehaxkqp5nNBicIYk99g159EZD3wi+YPyTPlFOWwPGs5GYcyaqft7tW5Fw9e9SDTEqbRq3OvcyYHl8tworjcrZ3ALhHYyaDh3EN+9txD8RFBDI0LJy4isHaEcVxEEGGBWj2klGo9F1r1NMztrhdWCSOkRSLyIJmnMsnIyiAjK6N2Nbj+Ef2ZP3Q+UxOmkhSWVHtsUVnlWQmgrtH47Oqh7qEBxEUEcc0VXeoWtbdLBTrKWCnlSS606ukPbrergIPArc0fTh0RmQ78GfAG/m6MebYlXw+s7qL7CvfVJod9hfsAazW4R4f8iH6h11BVHk5OQSkLPy0lp2BL7aR0hQ2mpg4J8CE+Iog+dvVQrJ0E4uxGY38f7UaqlGobxJiz2qgdJyLewB5gGpADfAHMM8bsaOz4ESNGmM2bN1/Saxlj2HlyJ58cSCc9M53ckmxAiPLpS0j1cCpOX8nRkwGNL2wfHkhM58B6bQRWMggiLEirh5RSnk1EthhjRpzvuMsZcDfMGLP1Up9/HiOBfcaYA/ZrvQXMBhpNFJfq9eX/w2tZf+e4jwEjVJX0pOr0jVQVDaBCwmrHEAyLqVnQvm6dAl3YXinVUVzOgLuHaLlBdzFAttv9HGCU+wEi8gDwAEB8fPwlvUg37wDiqoQfFOQxqaQU30A406s3fgOi6dxnLOKtM5wopdQFVz2JSDjQG6t7LADGmLUtEpTILUCKMeY++/7twEhjzKONHX85VU8AnDoMuz+xtoPrwFUJQV2gz3ToOwOumAx+QZd+fqWU8kDNWvUkIvcBPwRiga+A0cBnwOTLCbIJOUCc2/1Y4EgLvRaExcDI+62t7BTsWw67PoGdH8NX/wafAOg5CfrNtJJHJ8+e1VUppZrThdat/BC4GthojJkkIv2A/2q5sPgC6C0iScBhYC7wvRZ8vToBYTDwu9ZWXQlZn1pJY/cnsGcZIBA30ipp9L0Oovq0SlhKKeWUC00UZcaYMhFBRPyNMbtEpG9LBWWMqRKRR4A0rO6x/zDGfNtSr3dO3r7Qc6K1zXgOjn5jJYxdS2H509YW2ctKGn1mQNwo0HYNpVQ7c0FtFCKyGLgbeAyruqkA8DXGzGzZ8C7MZbdRXIrCbNiTaiWNzPVWu0ZgOPROtts1pkBAaOvGpJRSF+FC2yguehyFiEwAwoBUY0zFJcbXrBxJFO7KTsP+lbB7GexNh9KT4OULiWOhr92uEZ7gXHxKKdWIFksUnsjxROGuugpyNllJY08q5O2x9ncdAH2nW1VUMcPBSyfuU0o5SxOFp8jfX5c0sjaAqYbgrtAn2Spt9JwIfsFOR6mU6oA0UXiikpOwb4XVIL5vBZSfsrre9poKA74DfVLAv93PtaiU8hAtPoWHugRBETD4FmurrrRKGLuWwo4PYdcSTRpKKY+kJQpP4HJB9kb49gMraRQf1aShlGpxWvXUVmnSUEq1Ek0U7YHLBdmfw7eLNWkopZqdJor2pqmk0f96a6BfUIddxlwpdQk0UbRnNUljxwew4yMoOgLiDQnXQL/rrG63OsBPKXUemig6CpcLcr+0Ji7ctRROWGt7022QlTT6zYTug62FupVSyo0mio4qf3/dxIWHNgIGwuLqShoJ11iTHSqlOjxNFAqKT1gjwnd/Ys1FVVUGAZ2tRvB+11kTF/p3cjpKpZRDNFGo+irOwP5VVkljzzIoLQBvf2sKkZrSRqcop6NUSrUiTRTq3KqrrLEau5ZaI8ILD4F4Qdxo6D8L+s3SxnClOgBNFOrCGGMtyLRriZU4jm239ncfBP2utxJH1yu1MVypdkgThbo0Jw9YCWPnx5C9CTAQnmSXNK6H2Kt1inSl2glNFOryFR2ze1AtgQNrrFX8grtaXW77XQ9J48HHz+kolVKXSBOFal5lp2BvhlXS2JsBlWfAP9QaEd5vpjVCPCDM6SiVUhdBpxlXzSsgDAbdbG2VZXBgNez62FqUafu79tKv46zeU32nQ+d4pyNWSjUTLVGoy+Oqhpwv7CqqTyB/r7W/+yA7acyA6CHaGK6UB/LoqicRuQV4GugPjDTGbHZ77EngXqAamG+MSTvf+TRReJC8vVYpY/cyqwuucUFIDyth9J0JSdeCj7/TUSql8Pyqp+3ATcBL7jtF5EpgLjAA6AEsF5E+xpjq1g9RXZIuva1t7Hw4kwd7063SxtdvweZXwK8T9JpiJQ2d8VapNsGRRGGM2QkgZ1dHzAbeMsaUAwdFZB8wEvisdSNUzSK4Cwz5nrVVlsHBtVbS2L3MmipdvCF+jD154XU6yE8pD+VpjdkxwEa3+zn2vrOIyAPAAwDx8dpw6vF8A6BPsrVd9zzkfmUljF1LIe1Ja+s+2Fpbo98s6Npf2zWU8hAtlihEZDnQvZGHnjLGfHiupzWyr9FGFGPMy8DLYLVRXFKQyhleXhAzzNomP2UN8tu5xBqvseo3sOrXENHTShj9r4eYETrITykHtViiMMZMvYSn5QBxbvdjgSPNE5HyWBE9rTaNsfPtQX5LrcSx8QXY8D/Qqbs9yG8WJF6rg/yUamWeVvX0EfCmiDyP1ZjdG9jkbEiqVYV0gxH3WFtpoTW4b9fH8PUi2PwP8A+zpknvP8sa5OcX7HTESrV7jiQKEfkO8BcgClgqIl8ZY1KMMd+KyNvADqAK+IH2eOrAAjvD4FusrbLUniZ9idUg/s3b1prhV0yuG68R3MXpiJVql3TAnWp7qqvg0Aa7XWMpnM6xp0kfZSWNftdB5BVOR6mUx/PoAXfNTRNFB2YM5H5dNzL82DfW/qh+dUmjxzBtDFeqEZooVMdUkFW3ZnjWBjDVVmN43+lWY3jSeB0ZrpRNE4VSJSftxvAlsG+FNeNt7cjw66wxHYHhTkeplGM8fQoPpVpeUARcNcfaakeGL60/MjxxrFXS6HcdhMU6HbFSHklLFKrjcbng8BYraexaCnl7rP09htYN8ovq62yMSrUCrXpS6kKd2GOvGb7ESiAAkb3rln/tMVQbw1W7pIlCqUtx6rDVGL7zY8hcbzWGh/Swqqb6z4KEseDt63SUSjULTRRKXa6Sk7Anra4xvKoUAjpbg/v6zbIG+/kFOR2lUpdMG7OVulxBETBknrVVlMD+FdYgv92fwNcLwSfQ6kHVb5Y1rYiuraHaKU0USl0IvyCrkbv/9VBdaVVL7bJHhu9a4ra2xkxroF9EktMRK9VstOpJqcvhckHul9ao8N2fwPEd1v6uV9ojw2daI8N1bQ3lgbSNQiknnDxYN53IoQ311wzvN9OeJl1HhivPoIlCKafVNIbvXgr7Vtojw0Og91RrZHjvadYMuUo5RBuzlXKae2N4ZRkcXGO1aexeBt8uBi8fq7tt35lWY7i2aygPpSUKpVpbzcjwXUuspJG329of1Q/6TLe2uJHg5e1snKrd06onpdqK/P1WFdWeVMj6FFxVEBgBvZOtkkavKRAQ5nSUqh3SRKFUW1R2yhrctycN9qZD6cm6Kqo+063p0iN6Oh2laic0USjV1rmqIXuTVdLYkwondln7u/S1Shp9Z0DsSPDWpkZ1aTRRKNXenDxoV1Etg8xPwVVprafRZ7pOKaIuiSYKpdqzstOwf6XVGL5nmVVl5RtkTylyvVXi0K636jy0e6xS7VlAKAy40doaTimy82OrXSPxWnuq9FkQ0t3piFUb5kiJQkR+B1wPVAD7gbuNMYX2Y08C9wLVwHxjTNr5zqclCqVsLhcc2Qo7P7ImMDy539ofe3XdokyRVzgbo/IYHl31JCLJwEpjTJWIPAdgjPmZiFwJLARGAj2A5UAfY0x1U+fTRKFUI4yxGsB3LoFdH0Pu19b+rlfaSWMWdB+s81B1YB5d9WSMSXe7uxG42b49G3jLGFMOHBSRfVhJ47NWDlGptk8Euva3tgk/gcJDdVVT634Pa38LneOt6UT6zoCEa3RRJtUoT2ijuAdYZN+OwUocNXLsfWcRkQeABwDi4+NbMj6l2ofO8TD6IWs7k2ev5LcENv8DPn/BGtTXO9maUqTXVKsdRClaMFGIyHKgsRa0p4wxH9rHPAVUAW/UPK2R4xutGzPGvAy8DFbV02UHrFRHEtwFht1hbRVn3HpQpcI374CXLyRdayWNvjMgLNbpiJWDWixRGGOmNvW4iNwJzAKmmLqGkhwgzu2wWOBIy0SolALAL7huUaaaQX67l1pTpX/yhLV1H2ytG953hrZrdEBONWZPB54HJhhjTrjtHwC8SV1j9gqgtzZmK+WQE3usKqrdyyD7c8BAaGzd+hoJ48DHz+ko1SXy9F5P+wB/IN/etdEY86D92FNY7RZVwGPGmGXnO58mCqVaQfEJ2JtmlTT2r4SqUvAPtdoz+tnra+jkhW2KRyeK5qaJQqlWVlkKB1Zbvaj2pMKZE3a7xni7imomhEY7HaU6D00USqnW4aqGnC+skeE7l0DBQWt/zAgrafSbBVF9nI1RNUoThVKq9dUM8tu1xKqiOrLV2h/Zqy5pxIwALy9n41SAJgqllCc4ddhqDN+1FDLXWYsydepmN4bPsqqqfPydjrLD0kShlPIspYWwN8MqbexbDhXF4NfJbgyfZTWG64y3rcqjp/BQSnVAgZ1h8C3WVlkGB9fWrRu+44O6GW9rGsPDGp2UQTlASxRKKWe5XHB4c9006fn7rP09htpJ4zprviod5NfstOpJKdU2ndhTlzQO2/+vw5PsxvDrIG4UeHk7G2M7oYlCKdX2nc61VvDbtRQOrLGWfw3qAn2nWyWNKyaBb6DTUbZZmiiUUu1L2WnYl2F1u92bDuWnreVfr5hszVPVJ8VaQ1xdMG3MVkq1LwGhMPC71lZVYXW33bXU3pbUX/6173U6MrwZaYlCKdW2uVxweIu1ip8u/3pRtOpJKdXx1Fv+dQnkfmXtj+pvlTT6zYLoq7QHlU0ThVJKFWbXVU1lfQrGBWHxVu+p/rMgfkyH7kGliUIppdydybd6UO1cYk2TXl0OQZF104n0nNjhelBpolBKqXMpL7amEdm1BPakQ/kpqwdVrylWQ3ifFAiKcDrKFqe9npRS6lz8O8GAG62tqsKqlqrpQbXzYxBvSLjGKmn0mwmd452O2FFaolBKqRrGwJEv65LGiZ3W/u6D7aRxHXQb0G4aw7XqSSmlLlf+/rqkUbNmeOeEuqQRNwq8227FjCYKpZRqTsXHrWVfdy2F/ausxvDACOgz3WoQv2KyVaXVhmiiUEqpllJeDPtX2GuGp0FZIXj7Wwsx9Z1hbaE9nI7yvDw6UYjIfwOzARdwHLjLGHNERAT4MzATKLH3bz3f+TRRKKUcU10F2RutdTV2La1bM7zHUGtdjb4zoNtAj2zX8PREEWqMOW3fng9caYx5UERmAo9iJYpRwJ+NMaPOdz5NFEopj2AM5O2xl3/9BHK+AAyExdWVNBLGgY+f05ECHt49tiZJ2IKBmmw1G3jdWNlro4h0FpFoY0xuqweplFIXSwSi+lrbuB/Z7RppVmlj679g08vgFwK9p1qljV5T28R4Dcea60Xk18AdwClgkr07Bsh2OyzH3qeJQinV9nTqCsNut7bKUmtNjd2fWI3i3y6uG6/R/warF5WHLv/aYlVPIrIc6N7IQ08ZYz50O+5JIMAY80sRWQr8f8aY9fZjK4CfGmO2NHL+B4AHAOLj44dnZWW1xNtQSqnm53JZ4zV2L7WmFMnbbe2PGW7NdtvveujSq8XD8Og2inoBiCQAS40xA0XkJWC1MWah/dhuYOL5qp60jUIp1aad2GNPk/6xlUCgbsbb/tdbA/5aoDHco9soRKS3MWavffcGYJd9+yPgERF5C6sx+5S2Tyil2r2oPhD1OFz7eP0Zb9f9Adb+zppCpN/1VuJwYM1wp3o9vQf0xeoemwU8aIw5bHeP/SswHat77N3GmPMWFbREoZRql87kWQ3hOz+GA6ugugKCo6z2jH7XW+M2LqMHVZupemoOmiiUUu1ezZrhOz+GvRlQUQz+YTDhp3DNI5d0So+uelJKKXWR3NcMryyDA6utdo1WGAGuiUIppdoa3wDoO93aWoFXq7yKUkqpNksThVJKqSZpolBKKdUkTRRKKaWapIlCKaVUkzRRKKWUapImCqWUUk3SRKGUUqpJ7WIKDxE5gTVn1KXoAuQ1YzjNzdPjA8+PUeO7PBrf5fHk+BKMMVHnO6hdJIrLISKbL2SuE6d4enzg+TFqfJdH47s8nh7fhdCqJ6WUUk3SRKGUUqpJmijgZacDOA9Pjw88P0aN7/JofJfH0+M7rw7fRqGUUqppWqJQSinVJE0USimlmtShE4WITBeR3SKyT0QWOBRDnIisEpGdIvKtiPzQ3v+0iBwWka/sbabbc560Y94tIimtEGOmiHxjx7HZ3hchIhkistf+G27vFxH5Hzu+bSIyrIVj6+t2jb4SkdMi8piT109E/iEix0Vku9u+i75eInKnffxeEbmzheP7nYjssmNYLCKd7f2JIlLqdh1fdHvOcPvfxT77PUgLxnfRn2dL/f8+R3yL3GLLFJGv7P2tfv1ahDGmQ26AN7Af6An4AV8DVzoQRzQwzL4dAuwBrgSeBp5o5Pgr7Vj9gST7PXi3cIyZQJcG+34LLLBvLwCes2/PBJYBAowGPm/lz/QokODk9QPGA8OA7Zd6vYAI4ID9N9y+Hd6C8SUDPvbt59ziS3Q/rsF5NgFj7NiXATNaML6L+jxb8v93Y/E1ePwPwC+cun4tsXXkEsVIYJ8x5oAxpgJ4C5jd2kEYY3KNMVvt20XATiCmiafMBt4yxpQbYw4C+7DeS2ubDbxm334NuNFt/+vGshHoLCLRrRTTFGC/MaapUfotfv2MMWuBk4287sVcrxQgwxhz0hhTAGQAzbLuZWPxGWPSjTFV9t2NQGxT57BjDDXGfGasb73X3d5Ts8fXhHN9ni32/7up+OxSwa3AwqbO0ZLXryV05EQRA2S73c+h6S/oFiciicBQ4HN71yN2VcA/aqoqcCZuA6SLyBYRecDe180YkwtWsgO6OhhfjbnU/w/qKdcPLv56OXkd78H6hVsjSUS+FJE1InKtvS/Gjqk147uYz9Op63ctcMwYs9dtn6dcv0vWkRNFY/WBjvUVFpFOwHvAY8aY08ALwBXAECAXqzgLzsQ91hgzDJgB/EBExjdxrCPXVUT8gBuAd+xdnnT9mnKueJy6jk8BVcAb9q5cIN4YMxT4MfCmiIQ6EN/Ffp5Ofc7zqP9jxVOu32XpyIkiB4hzux8LHHEiEBHxxUoSbxhj3gcwxhwzxlQbY1zA/1FXPdLqcRtjjth/jwOL7ViO1VQp2X+POxWfbQaw1RhzzI7VY66f7WKvV6vHaTeYzwJus6tDsKt08u3bW7Dq/fvY8blXT7VofJfweTpx/XyAm4BFbnF7xPW7XB05UXwB9BaRJPvX6Fzgo9YOwq7TfAXYaYx53m2/e73+d4CaHhYfAXNFxF9EkoDeWI1iLRVfsIiE1NzGavTcbsdR0xPnTuBDt/jusHvzjAZO1VS5tLB6v+Q85fq5udjrlQYki0i4Xc2SbO9rESIyHfgZcIMxpsRtf5SIeNu3e2JdrwN2jEUiMtr+N3yH23tqifgu9vN04v/3VGCXMaa2SslTrt9lc7o13ckNq8fJHqws/5RDMYzDKnJuA76yt5nAv4Bv7P0fAdFuz3nKjnk3LdxTAqvXyNf29m3NdQIigRXAXvtvhL1fgDjtkgIAAAV9SURBVP+14/sGGNEK1zAIyAfC3PY5dv2wElYuUIn1y/HeS7leWG0F++zt7haObx9WnX7Nv8EX7WO/a3/uXwNbgevdzjMC6wt7P/BX7JkeWii+i/48W+r/d2Px2ftfBR5scGyrX7+W2HQKD6WUUk3qyFVPSimlLoAmCqWUUk3SRKGUUqpJmiiUUko1SROFUkqpJmmiUB5BRKrt2TW3i8g7IhJ0nuNfFZGbWys+t9f9u4hceZHPuVFEfmHfdp8Fda+IvN/wfHbf+0oR+X6D/Z1E5CUR2S/WTMNrRWRUM7ynHiLyrn17iLjNzHqO46NEJPVyX1e1HZoolKcoNcYMMcYMBCqAB50OqDHGmPuMMTsu8mk/Bf7mdv+P9nvtjTWKd6WIRLk9fgvWxHzzGpzn71iT0fU2xgwA7gK6XGQsZzHGHDHG1CTdIVjjD5o6/gSQKyJjL/e1VdugiUJ5onVAL7Hm8nef8/8JEXm64cEi8qyI7LAnjPu9vS9KRN4TkS/s7awvNREJEpG37ectEpHPRWSE/dgLIrLZ/uX+X27PWe12TLGI/FpEvhaRjSLSrZHX6AOUG2PyGnujxphFQDrwPbfd84DHgVgRibHPcwUwCvh/xprGAmPNjLq0kdcsdrt9s4i8at9+Vax1DzaIyIGaElnNdbZHMP8KmGOXeOaIyASpW0vhy5pR+sAHwG2NvSfV/miiUB5FrPlyZmCNwr2Q4yOwpnQYYIwZDDxjP/RnrF/uV2ONjv17I09/GCiwn/ffwHC3x54yxowABgMTRGRwI88PBjYaY64C1gL3///t3U+IVWUYx/HvTxKzcAzCnDGCAZ1pTKQJKojaJG4CQUioGXDZRhxEQahV4EbHjSCEq2gbBkGUtaqkIUFjnDK1XOimnboQixhzxn4tnvc0d+4cz/hnwOHO81mdOX/fc2Hue87zvvd5avZ5nfhFbpMJYKDcz3NAt+2fgM+Ad8s+m4BfbN+Z51zz6SGyAWwDRls3ONJxfwgcL288x4H9wG7bg0Rm1Mmy+3j5Oy0B2VGkxWKloirYOPAHkf/qXvwJ3AI+lvQ2UOUp2gp8VM75JdDV8jRceYOoU4DtC0R6iMo7kiaAn4kv6bpxidvAibJ8lihS064HuD7PPbRmEh0iOghK29rDTw/rC9v/lvDZnDegGqeAI5L2AE95pmbFNWDdArctLVKPPeoGpFRMlqfW/0maZvbDzOPtB9melvQqUbRoCBgBtpTjXrM92X5M6yVqV0Zyuf3AK7ZvlNDNnGsDU57JgXOH+v+nSWB1QxsgapCMl+VhYK2kKqyzTlIfkS/oRUnLqtBTg9a8PO3t/qdled7Sm7ZHJX1NjFuclrTV9qVy3qbPNnWQfKNIi9lV4BlJT0taQYRLZlHU8Vht+xtgLzEYCxH3H2nZb7D9WOBHohoZZebR5rK+C/gbuFnGHd56iHv4Hdhwt42SdhCZYT+V9DzwpO1nbffa7gUOAUO2rxCdyYGSbRRJfZLqqrZdlbRR0jIiLHc//iJK8lbtW2/7vO3D5foDZVM/MxlcU4fLjiItWraniMHVM0SI51LNbquAE5J+BX4A9pX1e4CXy0D1b9TPojoGrCnHvk+Enm7aPkeEnC4CnxDhlwc1BrxUfbkX+6rpscBOYEuZSTRM1Pto9Tkz4af3gG7gsqTzRF2GuhoGHxCf1/dEltP7cRJ4oRrMBvaWge5zxBtEVfnuTWDOQHrqTJk9Ni1ZijoBy23fKrOKvgP6y6DuQl7nKPCV7W8X8ryPkqQxYLujnnfqcDlGkZayJ4CTigqDAnYtdCdRHCSmtnaE8puPI9lJLB35RpFSSqlRjlGklFJqlB1FSimlRtlRpJRSapQdRUoppUbZUaSUUmr0H16dcb3MLSzSAAAAAElFTkSuQmCC\n", - "text/plain": [ - "" - ] - }, - "metadata": {}, - "output_type": "display_data" - } - ], - "source": [ - "# Plot results.\n", - "sig = avgi[0][0] + 1j*avgq[0][0]\n", - "avgamp0 = np.abs(sig)\n", - "plt.figure(1)\n", - "plt.plot(expt_pts, avgi[0][0], label=\"I value; ADC 0\")\n", - "plt.plot(expt_pts, avgq[0][0], label=\"Q value; ADC 0\")\n", - "plt.plot(expt_pts, avgamp0, label=\"Amplitude; ADC 0\")\n", - "# plt.plot(expt_pts, avg_di1, label=\"I value; ADC 1\")\n", - "# plt.plot(expt_pts, avg_dq1, label=\"Q value; ADC 1\")\n", - "# plt.plot(expt_pts, avg_amp1, label=\"Amplitude; ADC 1\")\n", - "plt.ylabel(\"a.u.\")\n", - "plt.xlabel(\"Pulse gain (DAC units)\")\n", - "plt.title(\"Averages = \" + str(config[\"reps\"]))\n", - "plt.legend()\n", - "plt.savefig(\"images/Gain_sweep.pdf\", dpi=350)" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### Sweeping via a Python outer loop" - ] - }, - { - "cell_type": "code", - "execution_count": 7, - "metadata": {}, - "outputs": [], - "source": [ - "config={\"res_ch\":6, # --Fixed\n", - " \"ro_ch\":0, # --Fixed\n", - " \"relax_delay\":1, # --Fixed\n", - " \"res_phase\":0, # --Fixed\n", - " \"pulse_style\": \"const\", # --Fixed\n", - " \"length\":100, # [Clock ticks] \n", - " \"readout_length\":200, # [Clock ticks]\n", - " \"pulse_gain\":0, # [DAC units]\n", - " \"pulse_freq\": 100, # [MHz]\n", - " \"adc_trig_offset\": 100, # [Clock ticks]\n", - " \"reps\":50, \n", - " }\n", - "\n", - "sweep_cfg={\"start\":0, \"step\":100, \"expts\":20}\n", - "gpts=sweep_cfg[\"start\"] + sweep_cfg[\"step\"]*np.arange(sweep_cfg[\"expts\"])\n", - "\n", - "results=[]\n", - "for g in tqdm(gpts):\n", - " config[\"pulse_gain\"]=int(g)\n", - " prog =LoopbackProgram(soccfg, config)\n", - " results.append(prog.acquire(soc, load_pulses=True))\n", - "results=np.transpose(results)" - ] - }, - { - "cell_type": "code", - "execution_count": 8, - "metadata": {}, - "outputs": [ - { - "data": { - "image/png": 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s3bqVvLw85s2bxw033MDRo0cB+PnPf05RURHbt29n+/btvPvuu5SVlZ33+o8++ig//OEPycvLIyoqihdeeKFZfi+lPFylLp7f9jzfeOcbzH5rNs9ufZbIkEh+NupnrL5tNS+kv8DcvnOJDo12OlS/4eQVRSywVkS2AZ8BOcaY5cCjwI9EZDfQGWiRnyRr1qwhNDSUu+++G4DAwECefvppXn75ZcrLy+sdO2/ePFasWFF3/6677mLp0qW4XC7Gjx/P0KFDGTp06HmLB4G1yJB3eY6ZM2eybt06ALKzs7nuuusYOnQot912W937/uIXv+Cdd95pMO6lS5cya9Ys5s+fz2uvvXbB32/evHlMmzaNV199lYqKCv7+97/zl7/8hXbt2gFWnae5c+fWe44xhjVr1nDrrdb3AC09rprL/pP7+ceX/+C2d29j1luz+MuWv9A+uD2PjniUnFtzeGn6SyxIW0CXsC5Oh+qXnBz1tA0Y0sD+vcDIJn2zlYvg0JdN+pJ0HwjTL7wQz1dffcWwYcPq7YuMjCQ5OZndu3czePDguv3z589nyZIlzJgxgzNnzrB69WqeffZZjDHk5OQQGhpKXl4eCxYs4NwZ6Bdy7NgxnnzySVatWkX79u357W9/y5/+9Cd+8Ytf8Ktf/eqCz1u8eDG//OUv6datG7feeiuPPfbYBY8dOnQoubm57N69m8TExLr1KS7k+PHjdOrUiaAg659dfHw8Bw4cuKTfR6nLVXCygKx8a57DzhPWolvXxlzLT0f8lKlJU+ne/uKVmZVFZ2b7yIXKcTdUMmX69Ok8+OCDVFVVkZmZyfXXX09YWBilpaU88MADbN26lcDAQHbt2nXJ779x40Z27NhRV+fpzJkz5/U7nOvw4cPs3r2bcePGISIEBQWxffv2C/aHXG75l4aO94cSyqr1KCwrJDs/myxXFjuOW31og7oM4pHhjzAtaRqxHRovv68a1jYSRSPf/H2lf//+LF26tN6+kydPcvjwYfr27Vtvf2hoKBMnTiQrK4slS5bUVXR9+umn6datG1988QVut5vQ0PPLADRWenzq1KmNrlx3riVLllBcXExKSkpdvK+99hpPPvlkg8dv2bKF4cOH07t3b/bv309ZWRkREREXfP0uXbpQUlJCTU0NQUFBFBYW0qNHj0uOT6mGHCw/SLbLSg7bj28HYGCXgTwy/BGmJk2lRwf9N3a1/GLUU2s0efJkKioqePnllwFrMaEf//jHPPDAA4SFnT+1f/78+fzf//0fH3zwAenp6YBVejw2NpaAgAD+9a9/UVtbe97zkpOT2bp1K263m4KCAj799FMARo8ezYcffsju3bsBq2Ks54rkscceY9myZee91uLFi8nMzMTlcuFyudi0adMF+ymWLl1KdnY2CxYsIDw8nHvuuYcHH3ywbhRTUVER//73v+s9R0SYNGkSb7zxBoCWHldXrKi8iJe+eolvvvdN0pem88dNf8Rg+NGwH7HylpW8euOr3Nn/Tk0STUQThY+ICMuWLeONN94gNTWVzp07ExAQwOOPP97g8dOmTWP9+vVMmTKlrtLr9773PV566SVGjx7Nrl27aN++/XnPGzt2LCkpKQwcOJBHHnmEoUOHAhATE8OLL77IggULGDRoEKNHjyY3NxeAL7/88ryV81wuF/v372f06NF1+1JSUoiMjOSTTz4BrCscz/DYf//736xZs4aYmBgAnnzySWJiYrjmmmsYMGAAN910U91j3jx9Jb179+b48ePcc889l3tqVRt16NQhKzms+CbTlk7jD5//gWp3NQ8PfZgVt6zgtZmvcfeAu4mPiHc61FZHy4w3k48++ogFCxbw5ptvntfJ3dzS09PJyspyNAZf8Le/ubp6h04dIic/hyxXFl8c/QKAftH9mJY8jfSkdBIiExyOsGXTMuN+ZsyYMQ2uWueE1pgkVOtx+NThuuSw9ehWANKi03hwyINMS55GUmSSwxG2PZoolFKOO1JxhJz8HLJd2Ww+shmAPlF9+MGQHzAtaRrJHZOdDbCN00ShlHLEscpjdaOVthzZgsGQGpXKA4MfYFryNFI6pjgdorJpolBKNZvSqlJW71/Nin0r+OzQZ7iNm96denP/4PtJT0qnZ6eeToeoGqCJQinlUxXVFawrWMfKfSvZcHADNe4aEiISuGfAPcxImUHvqN5Oh6guQhOFUqrJnak9w4YDG1i5byXvF75PZU0lXcO7cnva7UxPmU7/zv11Vn4LovMofGzZsmWISN0chqawbt06Zs6cCcA777zDU09ZM8/feuuteqW/L9XEiRMvuYbUhWhpclXjruGjgx/x8w9/zsQlE3lo7UNsLNrIrJ6z+Gf6P8m5NYefjPgJA7oM0CTRwmii8LHFixczbty4RiuxXo3Zs2ezaNEi4MoTxdXS0uRtl9u42XJkC7/e+Gsmvz6Z7+Z8l5z8HCYlTuKZyc+wZu4afn7dzxnRfQQBoh83LZX+5XyovLycDz/8kBdeeKFeoli3bh0TJkxg7ty59OnTh0WLFvHKK68wcuRIBg4cyJ49ewCr3Ph9993H+PHj6dOnD8uXLz/vPTxlxj/66CPeeecdfvKTnzB48GD27NlT70rh2LFjJCcnA1BZWcn8+fMZNGgQ8+bNo7Kysu71tDS5uhhjDNuObuP3n/2ejKUZ3LHyDpbtXsawbsN4euLTrJu7jl+P+zXj48cTHBDsdLiqCbSJPorffvpbck80XdMPWBOAHh35aKPHvPXWW2RkZNCnTx+io6PZvHlzXYmNL774gp07dxIdHU3Pnj259957+fTTT/nzn//MX/7yF/7nf/4HsEprvP/+++zZs4dJkybV1W4615gxY5g9ezYzZ86s+1C9kGeffZbw8HC2bdvGtm3b6mLS0uTqQowxfHnsS7Jd2WTnZ1N0qoiggCDG9BjDD4b8gEkJk+gQ0sHpMJWPtIlE4ZTFixfz8MMPA1bRv8WLF9d9KI8YMYLYWKvkca9evZg2bRoAAwcOZO3atXWvMXfuXAICAuqWU22Kvo7169fz4IMPAjBo0CAGDRoEaGlyVZ8xhu3HtpOdn022K5uDpw7WJYfvD/4+kxInERnSeKJXrUObSBQX++bvC8ePH2fNmjVs374dEaG2thYR4Xe/+x1AXXMLQEBAQN39gIAAampq6h4790Pxcj4kvUuQe8qPN/Y6WppcGWP46vhXZLmy6iWH62Kv43uDv8fEhIl0bNfR6TBVM9M+Ch954403uOOOO8jPz8flclFQUEBKSgobNmy4rNd5/fXXcbvd7Nmzh7179563loW3iIiIep3BycnJbNq0qS4ej+uvv55XXnkFgO3bt7Nt2zZAS5O3VZ4rhz99/iemvzmdBe8t4N87/k2vTr3477H/zbq563hmyjPM6T1Hk0QbpYnCRxYvXszNN99cb983vvENXn311ct6nb59+zJhwgSmT5/Oc8891+DiRR7z58/n97//PUOGDGHPnj088sgjPPvss4wZM4Zjx47VHXf//fdTXl7OoEGD+N3vfsfIkdbKs1qavO3wXDn8adPZ5PCvHf8ipWOKlRzmWcnhpt43aXJQWmbcn911112X1DndHFpCafLW8Df3JWMMuSdyyXJlkeXKorC8kCAJYnSP0UxLmsYNiTdoUmhjtMy4alL+niRUw4wx7CreZfU55GeTfzKfQAlkdOxoFg5aqMlBXRLHEoWIJAAvA90BN/C8MebPIhINLAGSARcw1xhT7FScTnrxxRedDkG1ULuLd5PpyiTLlYXrpIsACWBk95Hc3f9ubki8gajQKKdDVC2Ik1cUNcCPjTGbRSQC2CQiOcBdwGpjzFMisghYBFzRsCVjjA6lbCNaQxPq1dpbsreuWWlP6R4CJIAR3UbwrWu+xZSkKUSHRjsdomqhHEsUxpgioMi+XSYiO4E4YA4w0T7sJWAdV5AoQkNDOX78OJ07d9Zk0coZYzh+/HijHf2tlavUZSWH/CzyivMQhGHdhvF42uNMSZpCl7AuToeoWgG/6KMQkWRgCPAJ0M1OIhhjikSk6wWesxBYCJCYmHje4/Hx8RQWFtbVFVKtW2hoKPHx8U6H4XPGGPJK8liVv4qc/Bx2l+xGEIZ0HcJjIx9jatJUYsLPHzmm1NVwfNSTiHQA3gd+bYx5U0RKjDGdvB4vNsY02qDa0KgnpVoLz1DWnPwcVuWvYn/ZfgRhaLehTE2aypTEKXRr383pMFUL1CJGPYlIMLAUeMUY86a9+7CIxNpXE7HAEeciVMoZte5ath7dyqr8Vazav4pDpw4RJEGMjB3JXQPuYlLCJG1WUs3GyVFPArwA7DTG/MnroXeAO4Gn7J9vOxCeUs2u2l3N54c+Z1X+KlbvX83x08cJCQhhTI8xPDD4AS2foRzj5BXFWOBbwJcistXe9zOsBPEfEbkH2A/c5lB8SvncmdozfHzwY3Lyc1hXuI7SqlLCgsIYHzeeqUlTGR8/nvbB7Z0OU7VxTo562gBcaDjS5OaMRanmVFVbxYcHPiQ7P5t1Bes4VX2KiOAIJiRMYErSFMb2GEtoUNsbwaX8l1+MelKqtauqreKjAx+RnZ/N2oK1nKo+RWRIJNOSpjE1aSqjY0cTHKiL/Cj/pIlCKR85U3uGjw5+RJYri3UF6yivLq9LDunJ6YyMHakrwKkWQROFUk3IkxyyXdaVgyc5TE2ayrTkaYyKHaXJQbU4miiUukqeDuns/GzW7F9DeXU5ESERTEmawrSkadqspFo8TRRKXYFqdzUbD24k05XJ2v1rKasuIyIkgsmJk0lPTtfkoFoVTRRKXSK3cbPp8CZW7ltJTn4OJVUlRARHMClxEunJ6VwXe50mB9UqaaJQqhGe8hkr9q0ga18WRyqPEBYUxsT4iWSkZDAubhwhgSFOh6mUT2miUKoBecV5rNy3kkxXJgVlBQQFBDEubhyPpDzChPgJhAeHOx2iUs1GE4VStoKTBax0rWTlvpXsLtlNgAQwqvsovjPwO7oSnGrTNFGoNu1IxREy92WS6crky2NfAjCk6xB+NupnTE2aqoX3lEIThWqDTpw+war8Vazct5JNhzdhMPSL7sePhv2IjOQMYjvEOh2iUn5FE4VqE06eOcnq/NVkujL5pOgTak0tKR1TuP/a+8lIySClY4rTISrltzRRqFarorqCtQVrydyXyYaDG6hx1xDfIZ5vD/g26cnp9Inqo8vkKnUJNFGoVuV0zWk+OPABK/et5IPCDzhde5qu4V25Pe12pqdMp3/n/pocVKtgjOFY+RkCBDp3aOfT99JEoVq86tpqPjr4EZmuTNbsX0NFTQXRodHc1PsmpqdMZ3DXwQRIgNNhKnXZTlfXUnCigoLiCvYfr2D/iUr2n6ig4EQF+09UUFldy/cn9eIn6Wk+jUMThWqRatw1fFr0KVn5WazKX8XJMyeJDIlkesp0MlIyGN5tOEEB+s9b+Te323C0vIr9JzyJ4GwS2H+igiNlVfWODw8JJDE6nMTO4Yzt3YXE6DCGJ0f7PE79n6RajBp3DZ8f/pwsl5UcSqpKCA8K54bEG5ieMl1LaCi/42keKiyuoLC4ksLiSgrqbldwoLiSqhp33fEi0KNjGAnRYUzoE1OXFBKiw0mMDqdz+xBHmk41USi/VuuuZfORzWS5ssjJz+HE6RNWCY2EiaQnp+tqcMpRxhhOnDpzXgLwJIXC4gpOV7vrPSe6fQjxUWH06x7JlH7d6pJAYnQ4PTqF0i4o0KHf5sI0USi/4zZuthzZUpccjlUeIywojOvjryc9OZ1xceMICwpzOkzVRpyqqqnrIygorqTgRAWFxVbTUGFxJRVnausd3yk8mPioMHrHdGBS3xjio8KJjwqr+9m+Xcv72G15EatWyW3cfHH0Cys5uHI4UnmEdoHtuD7+eqYlT+P6uOu1vpLyiepaNwdLKinwdBQXW/0EVidyJSdOnal3fPuQQBKiw0nq3J5xvWNIiA7zSgZhRIS2vuZPTRTKMcYYth3bRpYri2xXNocrDhMSEMK4uHGkJ6czMWGiJgd11YwxHD91pq6j2LuzuOBEJUWllbjN2eODAoS4qDASosJJ79+RhGjrdmK01VcQFR7c5oZYO5ooROSfwEzgiDFmgL0vGlgCJAMuYK72slh8AAAgAElEQVQxptipGFXTMsaw/dh2KznkZ1N0qojggGDGxo3l4WEPMzF+Ih1COjgdpmphKs/U1jUHeRJAXWIorjiveSgmoh2J0eGMSI4iMTqO+OhwKxl0Dqd7ZCiBAW0rEVyM01cULwJ/BV722rcIWG2MeUpEFtn3H3UgNtVEPGs6eK4cDp46SFBAEGN6jOH7g7/PpMRJRIZEOh2m8mNVNbUUlZyu6yAu8Oow3n+igqMNDCNNiLKuAMb27kJCdFhdh3F8VDhhIf7XYezPHE0Uxpj1IpJ8zu45wET79kvAOjRRtDjGGHYc30FWvpUcDpQfIEiCuK7HdXxv8Pc0Oah6qmvdFJWcthNA/VFDBScqOVx2GuPVPBQYIPToFEpcpzAm9Y2paxZyehhpa+X0FUVDuhljigCMMUUi0rWhg0RkIbAQIDExsRnDUxdijGHniZ1kubLIcmXVJYfRPUZz37X3MSlhkq7p0EZ5hpF6mobyj59tJio8UcGhk6fr9RMECMR2tDqHPVcE3h3G3SNDCQrU2fbNxR8TxSUxxjwPPA8wfPhwc5HDlY8YY8g9kVvX51BQVkCQBDEqdhTfHfRdXfCnDfGMHvIkggL7Z77dV1BeVVPv+G6RVj/B6F6d6yWBhKhwuncMJVgTgd/wx0RxWERi7auJWOCI0wGp+owx7CreVXflsL9sP4ESyKjYUdw78F5uSLiBTqGdnA5TNTHP6KFCey5Bgd0sVHCigvwTpzhYcppar8uCkKAAEqKsvoFRKdF1fQRJnbWfoKXxx0TxDnAn8JT9821nw1FgfUjkleTVdUi7TroIlEBGdB/B3QPuZnLiZKJCo5wOU12l0srqugllZxPC2dnG544eigoPJrFzewYnRDHn2vC6khNJncPpFhFKgI4eahWcHh67GKvjuouIFAK/xEoQ/xGRe4D9wG3ORaj2lOypu3LYW7qXAAlgRLcR3NH/DiYnTiY61PcFyVTT8Qwj9b4a8NwuLK7g5On6zUMR7YKIb2BymednhxY4y1hdPqdHPS24wEOTmzUQVc/e0r11Vw67S3YjCMO7D+f2tNuZnDRZ15H2YzW1bopKT58tTW3PKfAkg2Pl9YeRtgsKsEYLRYUxLCmqbnJZQrTVZ9AxrO1NLlPn068DCgBXqYvs/GyyXFnsKt6FIAzpOoTHRj7G1KSpxITHOB2iwkoEh06e5kBxJQdKKjlQfDYJFBRXUFRav5/AM4w0ISqcyWldrURgzyVIiA4jpkM7TQTqojRRtGEFJwvIyrealXJP5AIwpOsQFo1cxJTEKXRr383hCNueyjO1HCip4ECJJxlU1EsK5w4jBWuWcd0VgZ0APFcFsR11GKm6epoo2piD5QfJcmWR6cpkx/EdAFwbcy0/HfFTpiZNpXv77g5H2LqVna6uN5mssLjybCIoOb8AXWCA0D0ylLioMEb37ExcVBhxncKIiwqjRyfrdmiwjh5SvqWJog04fOow2fnZZLoy2XZ0GwD9O/fnx8N+zLTkafTo0MPhCFuP8qoaKwGcqL8ugafkRGlldb3jw4ID6z78B8R1JN4rEcR1CqOb1h1SfkATRSt1rPIYOfk5ZO7LZMuRLRgMfaP68tDQh0hPSichMsHpEFukMzVuDpRUkn/8VN2EssLiSgpLrJ8lFfUTQWhwgNUfEBXG0MSoeusSxEeFEa2lJlQLoImiFSk+Xcyq/avI2pfFZ4c/w23c9OrYi/sH309GcgYpHVOcDrFFKK2srlu/OP/EqbO3j1ecV5LaM2ooPiqMwQmdzlukRmsOqdZAE0ULV1pVypr9a8hyZbGxaCO1ppakyCTuHXgvGckZpEalOh2i36l1G4pKK+stZO9de+jcq4IuHUJI8CpJndi5PUmdrcllXSN01JBq/TRRtECnqk/VJYcPD35IjbuGuA5x3Nn/TjKSM0iLTmvzH14nT1tXBd6L1HgSw4GSSqprz14WBAWIVWMoOpyZg2LtUhPt62YZ66Qy1dbp/4AWorKmkvWF68ncl8kHBz6gqraKbuHduD3tdjKSMxjQZUCbSg7ey1cWFNdPBA1dFUSFB5MYHc6AuI7MGBhbV3dIh5AqdXGaKPxYVW0VGw5sIGtfFusK11FZU0nn0M58I/UbZKRkcG3MtQRI6/yAc7sNR8urzis+57l9bl9BcKDYk8jCGRTfsV4iSIgOJ7IVrmOsVHPRROFnqt3VfHzwY7JcWazZv4by6nI6tevEzJ4zyUjOYFi3YQQGtPxx88YYuwBd5dnF7L1mGBcWV3Kmxl3vOV0j2tX1FSREx5EQFU68vXJZbMcwHUaqlI9oovADNe4aPjv0GVmuLFbtX0VpVSkRwRFMSZpCRnIGI2NHEhzQ8r4Re+YUeK4GCovPJoUDxZWUnbM+QcewYBKiw+jbLYIp/bqREBVWt5ZxfJROLFPKKZooHOI2brYc2cLKfSvJyc/hxOkThAeFMylxEhnJGYzpMYaQwBCnw2zU6epaDpR4laI+JxkUV5w/ucxTXmJ0z851w0g99Ye0eUgp/6SJohl51pFesW8Fma5MjlQcITQwlOvjrycjJYPxceMJDQp1Osw6xhiOllWdM2qosq7D+NDJ0/WODwkMIM6eSDZgYGzdlYCnOqlOLlOqZbriRCEiy40xM5symNYqrziPlftWkunKtJYKDQhiXNw4fjzsx0xMmEh4cLhjsZ2qqrFGDR23rgoKzhlKWuXVTyAC3SNDSYgOZ2zvLnZnsScRWHMKdKEapVqfq7mi+E6TRdEK5Z/MJ3NfJpmuTHaX7CZAAhjVfRTfGfidZl1H2lONtOACtYfOLUIX0S6IhOhwesd0YFLfmLqRQ4nR4cRFhdEuSPsJlGprrjhRGGOKmjKQ1uDQqUNk7stkpWtlXWXWoV2H8viox5maNJXOYZ2b/D1PV9fWq0TqnQQOFFdwrLx+IggJCqjrG/AUofMMJU2MDteFapRS57mkRCEi+wBz7n5jTM8mj6iF8S6+t/nIZgAGdB7AI8MfIT05/arLdnvmE+w/UVFXc8i7eehIWf0Vy7z7Ca65plu92kMJUWF06aDNQ0qpy3OpVxTDvW6HYq1j3WYXSz5acZTV+1eTk5/D54c/x23cpEal8uCQB8lIzrjsyqwVZ2ooOFF53uziC/UTxNr9BBP6xNgTysLsjmPtJ1BKNb1LShTGmOPn7PofEdkA/KLpQ/JPh04dYlX+KnLyc+rKdqd0TOHegfcyPXk6vaN6X/C5brfhiPfooeOnvEYSnb+OcQe7n6BXTHvtJ1BKOe5Sm56Get0NwLrCiPBJRH6ksKzQSg77c+oW/OkT1Yf7B9/PtKRp9OrUq+7Y09W1desTeA8nbeiqIEAgtqPVNzA5rSuJncPr9RN0Ctd+AqWU/7jUpqc/et2uAfYBc5s+nLNEJAP4MxAI/MMY85Qv388j/2Q+Ofk55OTn1HVI94vux/ev/QEDO43HVMdwoKSCtz6tpLB4K4XFVnI4t6+gfUggiZ3bn70q6Ny+LhHEdQojJKh11mhSSrU+Ysx5fdSOE5FAYBcwFSgEPgMWGGN2NHT88OHDzeeff37F77e3ZC8r92WT5cpm38k8ALoEp9LJPYza8gEcOdGBw2Wn8T5VnquCOHvUUJJdktqTDHRymVLK34nIJmPM8IsddzUT7oYaYzZf6fMvYiSw2xiz136v14A5QIOJ4kr9e/Uz/Hvf3zgQ7AYDNZVJ1JycSU3ZACrcUVR3DCU+KoxxqeF1axl7RhF17xhKsJamVkq1AVcz4e5+fDfpLg4o8LpfCIzyPkBEFgILARITE6/oTaKA6Fo3d5aeYHJFJWGhgZT17EfwNXFE9RlLULDWHlJKqUtuehKRKCAVa3gsAMaY9T4JSuQ2IN0Yc699/1vASGPMDxo6/mqbnijOh12Z8PVKcG0AdzWERUOfdOiTAb0nQ7tW33evlGpjmrTpSUTuBR4C4oGtwGjgY+CGqwmyEYWA92SEeOCgj94LopJg1Het7XQp7F59NnF8sRgCQyB5PPSdbiWOTpc3T0IppVqyS7qiEJEvgRHARmPMYBFJA/7LGDPPJ0GJBGF1Zk8GDmB1Zt9ujPmqoeOv+oriQmproOAT+HqFlTRO7LH2dxtoJY2+GRA7BAK0r0Ip1fI0dWf2aWPMaRFBRNoZY3JFpO9VxnhBxpgaEXkAyMIaHvvPCyUJnwoMguSx1pb+aziWZyeNTPjgD7D+d9ChO6TNgH6zrKuOQO3XUEq1Lpd6RbEMuBt4GKu5qRgINsbM8G14l8ZnVxSNOXUcdudA7nuwexVUV0BoR6tpKm2m1a8R0r55Y1JKqctwqVcUlz2PQkQmAB2BTGPMmYsd3xwcSRTeqithzxrYuRx2rYTKYggKs5JF2kyrUzy8zZbGUkr5KZ/NozDGvH9lIbViwWGQdqO11dZA/oeQu9xKHLnLQQIheZzVPJV2I0T2cDpipZS6ZH45M/tyOX5FcSFuNxzcArnvWknjuDXrm7jh0G8mpM2CLhcuJqiUUr7ks6Ynf+S3ieJcR7+Gne9aVxkHt1j7YtKs5qm0G6HHEKuOuFJKNQNNFP6upMDqCM9dDvkfgamFyDi7CWsmJI3REVRKKZ/SRNGSVJywJvjtXA57VkPNaQjtZM3VSLsRek2GkHCno1RKtTI+LwqomlB4NAy+3drOnII9a60rDc/M8KAw6HWDlTT6TtcRVEqpZqWJwt+EtLc6uvvNhNpqq1kq9z1r+/o9awRV0hi7X2MGdLqygohKKXWptOmppTAGirZaCWPncji609rffZA97HYmdO2nneFKqUumfRSt3fE9ZzvDCz4FDESlnB12Gz9Ca1AppRqliaItKTtsNUvtXA771ltl0tt3tZqm0mZByvUQFOJ0lEopP6OJoq06XQp5OdZ8jd2r4Ew5tIuE1KlW81TqVF1bQykF6Kintiu0Iwy81dqqT8O+962k8fVK2L7UWluj50QrafSdAR1inI5YKeXn9IqirXDXwv6NZ2tQle4HCYCE0VYTVd8Z0LmX01EqpZqRNj2pCzMGDn15NmkcsZf6iOlnJw27nIh2hivVqmmiUJeu2AW5K6xFmTzlRCJi7VX8boSU8RDUzukolVJNTBOFujIVJ2BXljWKavcaqD4FIRGQOsVKGqlTIayT01EqpZqAdmarKxMeDYMXWJunMzx3ubX861fLICDIWluj741WM1XHeKcjVkr5mF5RqEvjdsOBz8+WE/GsrRF77dmk0W2AzgxXqgXRpiflW8fyziaNws8AY9Wd8iSNxDEQqBesSvkzTRSq+ZQfseZpfL3CqnxbWwVhUZCabiWNXpOhXQeno1RKncOvE4WI3AY8AfQDRhpjPvd67DHgHqAWeNAYk3Wx19NE4UeqymHPGitp7MqEymIIbGdP8psBfaZDRDeno1RK4f+d2duBW4C/ee8UkWuA+UB/oAewSkT6GGNqmz9EdUXadYBrZltbbQ3s/9hKGrnvQV4W8LBVsDBthjU7vEuq0xErpS7CkURhjNkJIOd3fM4BXjPGVAH7RGQ3MBL4uHkjVE0iMMiag5EyHtJ/A0d2nO3XWPWEtXVOPbv8a9wwneSnlB/yt97GOGCj1/1Ce995RGQhsBAgMVEX7/F7ItCtv7VN+CmUFlr9Grnvwcd/hQ//Bzp0s5d/nWlXvNVJfkr5A58lChFZBXRv4KHHjTFvX+hpDexrsBPFGPM88DxYfRRXFKRyTsd4GPkda6sssSrd5i6HL9+ATS9CSAfoPeVsxVud5KeUY3yWKIwxU67gaYVAgtf9eOBg00Sk/FZYp7MVb2uqrDU1ct+z+jZ2vHV2kl/aTOuKQyf5KdWsHB0eKyLrgEc8o55EpD/wKla/RA9gNZB6sc5sHfXUSrndcGCTVU4k9z04tsvaHzvYXjP8Rl3+Vamr4O/DY28G/gLEACXAVmNMuv3Y48C3gRrgYWPMyou9niaKNuLoLjtprIDCT619USlnO8MTRkJAoLMxKtWC+HWiaGqaKNqgskNnO8P3vQ+1Z6B9jLWuRr9Z2hmu1CXQRKHajtMnIS/b6gzPy7GWfw2JgD7TdPlXpRrh7xPulGo6oZHnL/+au9xqotLlX5W6anpFoVovdy0UfGKt4pf7LpR4Lf/az+4Mj0p2OkqlHKNNT0p5u9Dyr90GWn0a/WZC12t0BJVqUzRRKNWY43vsciLLoeBTwEB0T6t5qt9sLSei2gRNFEpdqrLD1rDbne9ak/3cNdaa4Z5ht8njIDDY6SiVanKaKJS6EpXFsCvb6tPIWwU1lRDayZoR3m8W9LoBgsOcjlKpJqGjnpS6EmFRcO08aztTYa2tsfNdq5zIF4shONyqQdVvFqRO0xpUqk3QRKHUhYSEW53c/WZCbTW4NlhJI/c92PkOBARbE/vSbrSG3UbGOh2xUj6hTU9KXS63Gw58biWNne9C8T5rf9wwK2Gk3QgxaTqCSvk97aNQqjkYA0dzzy7IdHCztT+659mkkTBKa1Apv6SJQiknnDxo1aD6egXsfR/c1RDeBfpkWMu/9pxkNWkp5Qc0USjltNMnrQWZvl5hjaSqKoWgMGvkVNoMK3m07+J0lKoN01FPSjktNBIG3GJtNWcg/0MraeS+Z83bkACrWarvdOgzHbqkar+G8kt6RaFUczMGir6wk8YKOPyltT+6p5Uw+qRD0hid5Kd8TpuelGopSgpgV6a17Vtvra3RriP0nmxdbfSeAuHRTkepWiFNFEq1RFXlsHctfJ0JeVlw6ihIICSOtvo0+tpNVEo1AU0USrV0njXDd620Eoen4m10L7tfI8NKINpEpa6QJgqlWpuS/bAryxp+6/rAaqIK7WiVEkm70Wqi0pX81GXQRKFUa1ZVBnvWWkljVyZUnrBW8kuZYJcUmQ4R3Z2OUvk5TRRKtRW1NdZKfp5ht8Uua3/8CHt2+EyI6eNoiMo/+XWiEJHfA7OAM8Ae4G5jTIn92GPAPUAt8KAxJutir6eJQimbMXBkhzXsNnc5FG219nfufXZ9jbjhuiiTAvw/UUwD1hhjakTktwDGmEdF5BpgMTAS6AGsAvoYY2obez1NFEpdQGmh1TyV+57Vr+GugfZdraaptButpqrgUKejVA7x65nZxphsr7sbgVvt23OA14wxVcA+EdmNlTQ+buYQlWodOsbDyO9YW2UJ5OVYzVPbl8LmlyC4vTVfI+1Gq1Nc52uoBvhDCY9vA0vs23FYicOj0N53HhFZCCwESExM9GV8SrUOYZ1g0G3WVlMF+z6wmqe+XmmtryGB1ozwvjOsWlRRyU5HrPyEz5qeRGQV0NCwi8eNMW/bxzwODAduMcYYEflf4GNjzL/tx18AVhhjljb2Xtr0pNRVcLvh4BbrSiN3BRzdae3vNuBs0ogdrHWoWiHHm56MMVMae1xE7gRmApPN2WxVCCR4HRYPHPRNhEopwOrYjh9mbZN/ASf2Wgnj6xXwwR9g/e8gMs7q1+g7A5LHQ1CI01GrZuRUZ3YG8CdggjHmqNf+/sCrnO3MXg2kame2Ug45ddwqJZL7nrV+eHUFtIu0Jvel3QipU61Jf6pFcvyK4iL+CrQDcsS6nN1ojLnPGPOViPwH2AHUAN+/WJJQSvlQ+84w+HZrq66EveuspLErE756EwKCrHXD+82CvjdCRDenI1Y+oBPulFKXz10LhZ9b/Ro737WaqxBrfY1+M635GtEpTkepLsKv51E0NU0USjnIGDiy0xpBtfMdOGSvr9F9IKTNsq42uvbTznA/pIlCKeWMYhfsXG5daRR8Ahir4m2/mdBvNvQYqjPD/YQmCqWU88oOn22e2rfemhkeEWs1TfWbCUljtUy6gzRRKKX8S2Ux7MqG3HchbxXUVEJYlLWuRtqN0OsGCGnvdJRtir+PelJKtTVhUXDtPGs7U2ENt935rjUz/IvFEBQKPSdZE/z6TIcOMU5HrGyaKJRSzS8k3O6zmAm11bD/Y2vYbe4Ka0U/xFq9r+8M62qjcy+nI27TtOlJKeU/jLFGTX1tl0n3jKCKSbMXZLoRegzRzvAmon0USqmWrzjfLpO+HPI/AlNrdYZ7alAlX6/lRK6CJgqlVOtScQLysq0mqt2rofpU/XIivadYFXLVJdPObKVU6xIeDdfOt7bqStj7vjX09uuVZ8uJJI+zmqf6TodOCRd/TXVJ9IpCKdWyud1w4HN7zfAVcGyXtb/7ILtfY4Y1S1xnhp9Hm56UUm3Tsd1n19bwzAzvmGgv/zpDJ/l50UShlFLlR61Kt1+vgD1rrUl+oR2tZV/7zrD6NUIjnY7SMdpHoZRSHWJg6Les7UwF7F17dq7Gl69DYIhVJt3TRBXR0KKcSq8olFJtj7sWCj61m6jes8ukA/Ejzs7XiOnjbIzNQJuelFLqUhgDR7+25mrkvgcHN1v7O6daSSNtJsQNa5WT/DRRKKXUlSg9YM8Mfw9cH1gVbzt0syf5zYSU8RDUzukom4QmCqWUulqVJZCXY11t7F4FZ8ohJAJSp1hJo4WvGa6d2UopdbXCOsGg26yt+rS1pkbucuuK46tlEBBsXWF4+jUiY52O2Cf0ikIppS6XZ83w3Hfrd4bHDbeSRr9Z0CXV2RgvgV83PYnIfwNzADdwBLjLGHNQRAT4MzADqLD3b77Y62miUEo5xhg4muvVGb7F2t+lj90ZPstvK976e6KINMactG8/CFxjjLlPRGYAP8BKFKOAPxtjRl3s9TRRKKX8RmmhNVcjdzm4NtgVb3tYs8LTboSkcX5T8dav+yg8ScLWHvBkqznAy8bKXhtFpJOIxBpjipo9SKWUuhId42HUQmurq3i7HLa+Cp/9A9p1hD7pZyvetuvgdMQX5Vhntoj8GrgDKAUm2bvjgAKvwwrtfZoolFItz3kVb9fBTrsz/Mv/QGA76DnRWumv7wxo38XhgBvms0QhIquAhubDP26MedsY8zjwuIg8BjwA/BJoqLxjg21jIrIQWAiQmJjYNEErpZSvBIdZhQn7TofaGqtgYe5yK3HkZYE8BInXWcNu026EqCSnI67j+KgnEUkC3jPGDBCRvwHrjDGL7ce+BiZerOlJ+yiUUi2WMXBom5UwcpfDkR3W/u6DrNFTaTdC12t8Uibdr/soRCTVGJNn350N5Nq33wEeEJHXsDqzS7V/QinVqolA7LXWdsPjcHzP2RFUa38Da38NUSlW81TaLKseVTOPoHJq1NNSoC/W8Nh84D5jzAF7eOxfgQys4bF3G2MueqmgVxRKqVap7JDVn7FzuTXZz119tpxIv5lXvWa4Xw+PbWqaKJRSrV5dOZF3IW/V2TXDJ/wUxvzgil7Sr5uelFJKXaZ65US8RlBFxvn8rTVRKKVUS+M9gqoZ+N+ccqWUUn5FE4VSSqlGaaJQSinVKE0USimlGqWJQimlVKM0USillGqUJgqllFKN0kShlFKqUa2ihIeIHMWqGXUlugDHmjCcpubv8YH/x6jxXR2N7+r4c3xJxpiYix3UKhLF1RCRzy+l1olT/D0+8P8YNb6ro/FdHX+P71Jo05NSSqlGaaJQSinVKE0U8LzTAVyEv8cH/h+jxnd1NL6r4+/xXVSb76NQSinVOL2iUEop1ShNFEoppRrVphOFiGSIyNcisltEFjkUQ4KIrBWRnSLylYg8ZO9/QkQOiMhWe5vh9ZzH7Ji/FpH0ZojRJSJf2nF8bu+LFpEcEcmzf0bZ+0VE/j87vm0iMtTHsfX1OkdbReSkiDzs5PkTkX+KyBER2e6177LPl4jcaR+fJyJ3+ji+34tIrh3DMhHpZO9PFpFKr/P4nNdzhtn/Lnbbv4P4ML7L/nv66v/3BeJb4hWbS0S22vub/fz5hDGmTW5AILAH6AmEAF8A1zgQRyww1L4dAewCrgGeAB5p4Phr7FjbASn27xDo4xhdQJdz9v0OWGTfXgT81r49A1gJCDAa+KSZ/6aHgCQnzx9wPTAU2H6l5wuIBvbaP6Ps21E+jG8aEGTf/q1XfMnex53zOp8C19mxrwSm+zC+y/p7+vL/d0PxnfP4H4FfOHX+fLG15SuKkcBuY8xeY8wZ4DVgTnMHYYwpMsZstm+XATuBxhbBnQO8ZoypMsbsA3Zj/S7NbQ7wkn37JeAmr/0vG8tGoJOIxDZTTJOBPcaYxmbp+/z8GWPWAycaeN/LOV/pQI4x5oQxphjIATJ8FZ8xJtsYU2Pf3QjEN/YadoyRxpiPjfWp97LX79Tk8TXiQn9Pn/3/biw++6pgLrC4sdfw5fnzhbacKOKAAq/7hTT+Ae1zIpIMDAE+sXc9YDcF/NPTVIEzcRsgW0Q2ichCe183Y0wRWMkO6OpgfB7zqf8f1F/OH1z++XLyPH4b6xuuR4qIbBGR90VkvL0vzo6pOeO7nL+nU+dvPHDYGJPntc9fzt8Va8uJoqH2QMfGCotIB2Ap8LAx5iTwLNALGAwUYV3OgjNxjzXGDAWmA98XkesbOdaR8yoiIcBs4HV7lz+dv8ZcKB6nzuPjQA3wir2rCEg0xgwBfgS8KiKRDsR3uX9Pp/7OC6j/ZcVfzt9VacuJohBI8LofDxx0IhARCcZKEq8YY94EMMYcNsbUGmPcwN852zzS7HEbYw7aP48Ay+xYDnualOyfR5yKzzYd2GyMOWzH6jfnz3a556vZ47Q7zGcC37SbQ7CbdI7btzdhtfv3sePzbp7yaXxX8Pd04vwFAbcAS7zi9ovzd7XacqL4DEgVkRT72+h84J3mDsJu03wB2GmM+ZPXfu92/ZsBzwiLd4D5ItJORFKAVKxOMV/F115EIjy3sTo9t9txeEbi3Am87RXfHfZontFAqafJxcfqfZPzl/Pn5XLPVxYwTUSi7GaWafY+nxCRDOBRYLYxpsJrf4yIBNq3e2Kdr712jGUiMtr+N3yH1+/ki/gu9+/pxP/vKUCuMaauSclfzt9Vc7o33ckNa8TJLqws/7hDMYzDuuTcBmy1txnAv4Av7f3vALFez3ncjtGhWgEAAAWZSURBVPlrfDxSAmvUyBf29pXnPAGdgdVAnv0z2t4vwP/a8X0JDG+GcxgOHAc6eu1z7PxhJawioBrrm+M9V3K+sPoKdtvb3T6ObzdWm77n3+Bz9rHfsP/uXwCbgVlerzMc6wN7D/BX7EoPPorvsv+evvr/3VB89v4XgfvOObbZz58vNi3hoZRSqlFtuelJKaXUJdBEoZRSqlGaKJRSSjVKE4VSSqlGaaJQSinVKE0Uyi+ISK1dXXO7iLwuIuEXOf5FEbm1ueLzet9/iMg1l/mcm0TkF/Zt7yqoeSLy5rmvZ4+9rxaR756zv4OI/E1E9ohVaXi9iIxqgt+ph4i8Yd8eLF6VWS9wfIyIZF7t+6qWQxOF8heVxpjBxpgBwBngPqcDaogx5l5jzI7LfNpPgWe87j9t/66pWLN414hIjNfjt2EV5ltwzuv8A6sYXaoxpj9wF9DlMmM5jzHmoDHGk3QHY80/aOz4o0CRiIy92vdWLYMmCuWPPgB6i1XL37vm/yMi8sS5B4vIUyKywy4Y9wd7X4yILBWRz+ztvA81EQkXkf/Yz1siIp+IyHD7sWdF5HP7m/t/eT1nndcx5SLyaxH5QkQ2iki3Bt6jD1BljDnW0C9qjFkCZAO3e+1eAPwYiBeROPt1egGjgP/XWGUsMFZl1PcaeM9yr9u3isiL9u0XxVr34CMR2eu5IvOcZ3sG86+AefYVzzwRmSBn11LY4pmlD7wFfLOh30m1PpoolF8Rq17OdKxZuJdyfDRWSYf+xphBwJP2Q3/G+uY+Amt27D8aePr3gGL7ef8NDPN67HFjzHBgEDBBRAY18Pz2wEZjzLXAeuA7DRzz/7d3L6F1VVEYx/9fsNQHbQVRk4oQqIm1IkZQQXRi6aQgFCy0CTjsRFpCAoE6EpxonAQK4kicSgRBtDpSS0MLtaSxD207qJPOooOSFkk0aT8Ha5/m9uZ60tpAws36jU7Oc58Lufuctfdd63XiF7l1poDt5X6eBjptnwa+BPaXfZ4Hztq+ucy5ltNFZAN4Cxht3OBIx/0+MF7eeMaBEeCg7T4iM+ps2X2y/J3Wgewo0lrxkKIq2CRwlch/dTeuA3PAZ5LeBqo8RbuAT8o5vwE2NzwNV94g6hRg+1ciPURln6Qp4BfiS7rVuMQ/wNGyfIYoUtOsC/hzmXtozCTaT3QQlLY1h5/u19e2b5Xw2ZI3oBZOAmOSBoFHvViz4g9g6wq3La1RD6x2A1IqZstT622SFrjzYebB5oNsL0h6lSha1A8cAnaW416zPdt8TOMlWq6M5HIjwCu2r5XQzZJrA/NezIFzk9b/T7PAlpo2QNQgmSzLA8CTkqqwzlZJPUS+oBcldVShpxqNeXma2/13w/KypTdtj0r6jhi3OCVpl+3L5bx1n21qI/lGkdayaeAJSY9J2kiES+6gqOOxxfb3wBAxGAsR9z/UsF9f87HACaIaGWXm0Qtl/WbgL2CmjDvsvo97uAQ8818bJe0lMsN+IelZ4BHbT9nutt0NfAT02/6d6Ew+KNlGkdQjqVXVtmlJz0nqIMJy9+IGUZK3at822xdsf1yuv71s6mUxg2tqc9lRpDXL9jwxuPozEeK53GK3TcBRSeeB48BwWT8IvFwGqi/SehbVp8Dj5djDROhpxvY5IuT0G/A5EX75vyaAl6ov92K4mh4LvAPsLDOJBoh6H42+YjH8dADoBK5IukDUZWhVw+A94vP6ichyei+OATuqwWxgqAx0nyPeIKrKd28CSwbSU3vK7LFp3VLUCdhge67MKvoR6C2Duit5nSPAt7Z/WMnzriZJE8AeRz3v1OZyjCKtZw8DxxQVBgW8u9KdRPEhMbW1LZTffIxlJ7F+5BtFSimlWjlGkVJKqVZ2FCmllGplR5FSSqlWdhQppZRqZUeRUkqp1r/7cFvnRZlkbwAAAABJRU5ErkJggg==\n", - "text/plain": [ - "" - ] - }, - "metadata": {}, - "output_type": "display_data" - } - ], - "source": [ - "sig = results[0][0][0] + 1j*results[0][0][1]\n", - "avgamp0 = np.abs(sig)\n", - "plt.figure(2)\n", - "plt.plot(gpts, results[0][0][0],label=\"I value; ADC 0\")\n", - "plt.plot(gpts, results[0][0][1],label=\"Q value; ADC 0\")\n", - "plt.plot(gpts, avgamp0,label=\"Amplitude; ADC 0\")\n", - "plt.ylabel(\"a.u.\")\n", - "plt.xlabel(\"Pulse gain (DAC units)\")\n", - "plt.title(\"Averages = \" + str(config[\"reps\"]))\n", - "plt.legend()\n", - "plt.savefig(\"images/Gain_sweep_python.pdf\", dpi=350)" - ] - } - ], - "metadata": { - "kernelspec": { - "display_name": "Python 3", - "language": "python", - "name": "python3" - }, - "language_info": { - "codemirror_mode": { - "name": "ipython", - "version": 3 - }, - "file_extension": ".py", - "mimetype": "text/x-python", - "name": "python", - "nbconvert_exporter": "python", - "pygments_lexer": "ipython3", - "version": "3.8.2" - } - }, - "nbformat": 4, - "nbformat_minor": 2 -} diff --git a/qick/qick_demos/03_Conditional_logic.ipynb b/qick/qick_demos/03_Conditional_logic.ipynb deleted file mode 100644 index 99f788a..0000000 --- a/qick/qick_demos/03_Conditional_logic.ipynb +++ /dev/null @@ -1,294 +0,0 @@ -{ - "cells": [ - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "#
Conditional logic with the QICK demonstration\n", - "\n", - "In this demo you will send and receive a pulse in loopback conditional on the value of a number written to the QICK. A similar application of the QICK conditional logic can enable the active reset of qubits. " - ] - }, - { - "cell_type": "code", - "execution_count": 1, - "metadata": {}, - "outputs": [ - { - "data": { - "application/javascript": [ - "\n", - "try {\n", - "require(['notebook/js/codecell'], function(codecell) {\n", - " codecell.CodeCell.options_default.highlight_modes[\n", - " 'magic_text/x-csrc'] = {'reg':[/^%%pybind11/]};\n", - " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", - " Jupyter.notebook.get_cells().map(function(cell){\n", - " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", - " });\n", - "});\n", - "} catch (e) {};\n" - ] - }, - "metadata": {}, - "output_type": "display_data" - }, - { - "name": "stdout", - "output_type": "stream", - "text": [ - "Populating the interactive namespace from numpy and matplotlib\n" - ] - } - ], - "source": [ - "# Import the QICK drivers and auxiliary libraries\n", - "from qick import *\n", - "%pylab inline" - ] - }, - { - "cell_type": "code", - "execution_count": 2, - "metadata": {}, - "outputs": [], - "source": [ - "# Load bitstream with custom overlay\n", - "soc = QickSoc()\n", - "soccfg = soc\n" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### Hardware Configuration\n", - "\n", - "tProc channel 7 : DAC 229 CH3 <-> Readout channel 0 : ADC 224 CH0\n" - ] - }, - { - "cell_type": "code", - "execution_count": 3, - "metadata": {}, - "outputs": [], - "source": [ - "class LoopbackProgram(AveragerProgram):\n", - " def initialize(self):\n", - " cfg=self.cfg \n", - "\n", - " # set the nyquist zone\n", - " self.declare_gen(ch=cfg[\"res_ch\"], nqz=1)\n", - "\n", - " #configure the readout lengths and downconversion frequencies\n", - " self.declare_readout(ch=cfg[\"ro_ch\"], length=self.cfg[\"readout_length\"],\n", - " freq=self.cfg[\"pulse_freq\"], gen_ch=cfg[\"res_ch\"])\n", - "\n", - " freq=self.freq2reg(cfg[\"pulse_freq\"], gen_ch=cfg[\"res_ch\"], ro_ch=cfg[\"ro_ch\"]) # convert frequency to dac frequency (ensuring it is an available adc frequency)\n", - " self.set_pulse_registers(ch=cfg[\"res_ch\"], style=\"const\", freq=freq, phase=0, gain=cfg[\"pulse_gain\"], \n", - " length=cfg[\"length\"])\n", - " \n", - " # Set threshold\n", - " self.regwi(0,1,self.cfg[\"threshold\"])\n", - "\n", - " # Set value of number \n", - " self.regwi(0,2,self.cfg[\"number\"])\n", - "\n", - " self.synci(200) # give processor some time to configure pulses\n", - " \n", - " def body(self):\n", - " self.trigger(adcs=[self.cfg[\"ro_ch\"]],adc_trig_offset=self.cfg[\"adc_trig_offset\"]) # trigger the adc acquisition\n", - " \n", - " # Apply conditional logic statement: When number is smaller than threshold, skip over playing the pulse.\n", - " self.condj(0,2,'<',1,'LABEL') \n", - " self.pulse(ch=self.cfg[\"res_ch\"]) # play readout pulse\n", - " self.label('LABEL')\n", - "\n", - " # control should wait until the readout is over\n", - " self.wait_all() \n", - "\n", - " self.sync_all(self.us2cycles(self.cfg[\"relax_delay\"])) # sync all channels" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### When the value of number is above the threshold, the conditional statement is False so you see a loopback pulse." - ] - }, - { - "cell_type": "code", - "execution_count": 4, - "metadata": {}, - "outputs": [ - { - "data": { - "application/vnd.jupyter.widget-view+json": { - "model_id": "cde83de6d9854e69a156b6dc1bc9e0d6", - "version_major": 2, - "version_minor": 0 - }, - "text/plain": [ - "HBox(children=(IntProgress(value=0), HTML(value='')))" - ] - }, - "metadata": {}, - "output_type": "display_data" - }, - { - "name": "stdout", - "output_type": "stream", - "text": [ - "\n" - ] - } - ], - "source": [ - "config={\"res_ch\":6, # --Fixed\n", - " \"ro_ch\":0, # --Fixed\n", - " \"reps\":1, # --Fixed\n", - " \"relax_delay\":1.0, # --Fixed\n", - " \"res_phase\":0, # --Fixed\n", - " \"length\":20, # [Clock ticks] \n", - " \"readout_length\":200, # [Clock ticks]\n", - " \"pulse_gain\":1000, # [DAC units]\n", - " \"pulse_freq\": 100, # [MHz]\n", - " \"adc_trig_offset\": 100, # [Clock ticks]\n", - " \"soft_avgs\":100,\n", - " ### New variables\n", - " \"number\": 100,\n", - " \"threshold\": 50\n", - " }\n", - "\n", - "prog =LoopbackProgram(soccfg, config)\n", - "(iq0,) = prog.acquire_decimated(soc, load_pulses=True, progress=True, debug=False)" - ] - }, - { - "cell_type": "code", - "execution_count": 5, - "metadata": {}, - "outputs": [ - { - "data": { - "image/png": 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77iI7O5sxY8YwadIk3nzzzVbH3rVrF2eddRbZ2dnMmzcPr9fbaa8jqvgarUTRmSbfCENCfxdOFwR9nXs+1WVoougkxhjmzp3LnDlzKCgooKCggIaGBn7+85/bHVqHKisrWb9+PZWVlezateuodT/96U/ZuHEjBQUFzJs3j4suuoiyMmtE73333UdJSQn5+fnk5+fz2muvUVNT0+r4d955Jz/96U8pKCigV69ePPnkKd3pVrUUDFptFJ2dKFpyuiCgiSJaaKLoJO+99x5xcXH88Ic/BMDpdPLII4/wzDPPUFtbe9S28+bN44033mh+/oMf/IDly5dTVFTEueeeS25uLrm5ua1uHgTWTYYWLlzY/HzWrFl88MEHAKxatYopU6aQm5vLd7/73ebz3n///bz66qttxr18+XKuuOKK5mlG2jNv3jxmzJjB888/T319PX/5y1/44x//SGxsLGDN83T11VcftY8xhvfee6952hKdevw0aZq+I5yJwqGJIppERxvFm3fBga9O7zH7j4VL278Rz+bNm5k4ceJRy5KTk8nMzKSwsJDx48c3L58/fz5Lly7lsssuw+v18u677/LnP/8ZYwxvv/02cXFxFBQUsGDBAo4dgd6e8vJyHnroId555x0SExN5+OGH+f3vf8/999/PL37xi3b3W7JkCQ888AD9+vXjqquu4u67725329zcXLZt20ZhYSEZGRnN96doT0VFBT179iQmxvqzGzRoEPv27Tuh16M60JwoEsJ3TqcbAlptGC2iI1HYoL3puNuaMuXSSy/l1ltvxePxsHLlSs477zzi4+Opqqpi4cKFbNy4EafTyY4dO074/J999hlbtmxpnufJ6/W2anc4VmlpKYWFhZxzzjmICDExMeTn57fbHnKy07+0tb1OWX4aNM3zFBMXvnM6XeD/5u1tKjLYlihEJA5YDcSG4lhmjHlARLKAF4DewHrg+8aYb/bVpYNv/p0lJyeH5cuXH7Wsurqa0tJSRowYcdTyuLg4LrjgAt566y2WLl3KggULAHjkkUfo168fmzZtIhgMEhfX+oOgo6nHp0+f3uGd6461dOlSDh8+TFZWVnO8L7zwAg899FCb22/YsIG8vDyGDx/Onj17qKmpISmp/UFdffv2pbKyEr/fT0xMDMXFxQwYMOCE41PtaJpiPKwlCteR26+qbs/ONgoPcJEx5kxgPHCJiEwGHgYeMcZkA4eB62yM8ZRNmzaN+vp6nnnmGcC6mdAdd9zBwoULiY9vXZc8f/58/va3v/HRRx8xc+ZMwJp6PD09HYfDwd///ncCgUCr/TIzM9m4cSPBYJC9e/eyZs0aACZPnswnn3xCYaHV172+vr65RHL33XezYsWKVsdasmQJK1eubJ56fN26de22UyxfvpxVq1axYMECEhISuO6667j11lubezGVlJTw7LPPHrWPiHDhhReybNkyQKceP22aE0U4G7O16ima2JYojKXpK4kr9GOAi4BloeWLgTk2hPeNiQgrVqxg2bJlZGdn06dPHxwOB/fee2+b28+YMYPVq1dz8cUXN8/0etNNN7F48WImT57Mjh07SExMbLXf1KlTycrKYuzYsfzsZz8jNzcXgNTUVJ5++mkWLFjAuHHjmDx5Mtu2WdNJf/XVV63unFdUVMSePXuYPHly87KsrCySk5P5/PPPAauE09Q99tlnn+W9994jNTUVgIceeojU1FRGjx7NmDFjmDNnTvO6lpraSoYPH05FRQXXXReR3wO6luZEEcaqJ0eMNSmgig7GGNt+ACewEajFKkn0BQpbrB8M5Lez7/XAWmBtRkaGOdaWLVtaLbPTJ598YjIyMszatWvtDsXMmDHD7hCOq6tdvy7t6/eNeSDZmKJPwnfOl35kzB8mhO98qlMAa80JfFbb2phtjAkA40WkJ7ACaOsGBG22mBpjFgGLwLofRacFeZqcffbZbd61zg5vvfWW3SGo06mpRBHuxmwdcBc1usQ4CmNMJfABMBnoKSJNCWwQsN+uuJSKCE29nsLdmK3jKKKGbYlCRFJDJQlEJB64GNgKvA9cFdrsWuAVeyJUKkL47Bpwp43Z0cLOqqd0YLGIOLES1ovGmNdFZAvwgog8BGwAdI4HpTrSXKIId68nbcyOFrYlCmPMl8CENpbvBCaFPyKlIpQt3WO1RBFNukQbhVLqG2iawiMmzIlCG7OjhiaKTtSjR48udZy23HbbbQwcOPCo0d1PP/00qampTJgwgezsbGbOnNlqQsLf/va3jBw5kjFjxnDmmWc2Dyxs6aWXXiInJweHw3HCc1SpU+Crt9oMnGGsIHC6IeiHk5zGRUUmTRRRLBgMsmLFCgYPHszq1auPWjdv3jw2bNhAQUEBd911F3PnzmXr1q0APP7447z99tusWbOG/Px8Vq9e3eY8TmPGjOHll1/mvPPOC8vriVq+hvD2eAJrwB1oz6cooYkizO68804ee+yx5ucPPvggv/vd76itrWXatGnk5uYyduxYXnmldWevDz74gFmzZjU/X7hwIU8//TQA69at4/zzz2fixInMnDmTkpISwPpQf/zxx9uM5f3332fMmDHceOONHc4JdeGFF3L99dezaNEiAH71q1/x2GOPNc8Wm5KSwrXXXttqv1GjRrWa10p1Al+Y70UBVokCtJ0iSkTF7LEPr3mYbYe2ndZjjuw9kjsn3XnS+82fP5/bb7+dm266CYAXX3yRlStXEhcXx4oVK0hOTqa8vJzJkydz5ZVXntDsqj6fj1tuuYVXXnmF1NRUli5dyr333stTTz3FDTfc0O5+S5YsYcGCBcyePZt77rkHn8+Hy+Vqc9vc3FyeeOIJampqqKmpYdiwYSf92lUn8TWEd/oOsNooQNspokRUJIquZMKECRw8eJD9+/dTVlZGr169yMjIwOfzcc8997B69WocDgf79u2jtLS01ZxMbdm+fTv5+flMnz4dsCYgTE9P73Afr9fLG2+8wSOPPEJSUhJnnXUWq1at4vLLL29z+6aqJdPO9OnKRr768Fc9NSUKrXqKClGRKE7lm39nuuqqq1i2bBkHDhxg/vz5ADz33HOUlZWxbt06XC4XmZmZzVOGN+loSvGcnBw+/fTTE45h5cqVVFVVMXbsWMCaXTYhIaHdRLFhwwZGjRpFcnIyiYmJ7Ny5k6FDh57U61adxB+G+2Ufy9GUKLTqKRpoG4UNmm4zumzZsubbglZVVZGWlobL5eL9999vc16oIUOGsGXLFjweD1VVVbz77rsAjBgxgrKysuZE4fP52Lx5MwCPPvoojz76aKtjLVmyhL/+9a/NU4rv2rWLVatWUV9f32rbDz/8kEWLFvGTn/wEsKYpv/nmm6murgas+1Y0tV8oG/gawts1Flq0UWiJIhpERYmiq8nJyaGmpoaBAwc2VxFdc801XHHFFeTl5TF+/HhGjhzZar/Bgwdz9dVXM27cOLKzs5kwwRqv6Ha7WbZsGbfeeitVVVX4/X5uv/12cnJy2LZtW/Nd7prU19fz1ltv8cQTTzQvS0xM5JxzzuG1114DrJsYffzxx9TX15OVlcXy5csZNcqas/HGG2+ktraWb33rW7hcLlwuF3fccUereFesWMEtt9xCWVkZl19+OePHj9cJCTuDrx4S+ob3nFr1FFWkrW6NkSYvL88c209/69atzR9s0WzWrFm8/PLLzfe4iBR6/U7CnyZD3+Ew79njb3u6bHkFXvx3uPFf0C8nfOdVp5WIrDPG5B1vOy1RdHOvv/663SGozmZLY7Z2j40m2kahVKTzNYT3XhTQojFbJwaMBpoolIp0AU/4E4VTez1FE00USkW6gP/IB3e4aKKIKpoolIp0Aa8NiSLURhHUqqdooIlCqUhmjDWNhjPMvdqaJwXUEkU00ETRiYqLi5k9ezbZ2dkMHTqUhQsX4vF4vvFxi4qKGDNmzGmIsG2zZ89mypQpRy178MEHGThwIOPHjyc7O5u5c+eyZcuW5vU+n4+77rqL7OxsxowZw6RJk3jzzTdbHfvRRx9l+PDhiAjl5eWd9hqiRtM3eodNJQodRxEVNFF0EmMMc+fOZc6cORQUFFBQUEBDQwM///nP7Q6tQ5WVlaxfv57Kykp27dp11Lqf/vSnbNy4kYKCAubNm8dFF11EWVkZAPfddx8lJSXk5+eTn5/Pa6+9Rk1NTavjT506lXfeeYchQ4aE5fV0e00f1HZVPWmiiAqaKDrJe++9R1xcHD/84Q8BcDqdPPLIIzzzzDPU1tYete28efN44403mp//4Ac/YPny5RQVFXHuueeSm5tLbm5uq5sHgXWToYULFzY/nzVrFh988AEAq1atYsqUKeTm5vLd7363+bz3338/r776aptxL1++nCuuuKJ5mpH2zJs3jxkzZvD8889TX1/PX/7yF/74xz8SGxsLQL9+/bj66qtb7TdhwgQyMzPbPa46SU1VP2FPFKGqJ509NipExYC7A7/6FZ6tp3ea8dhRI+l/zz3trt+8eTMTJ048allycjKZmZkUFhYyfvz45uXz589n6dKlXHbZZXi9Xt59913+/Oc/Y4zh7bffJi4ujoKCAhYsWHDCd4orLy/noYce4p133iExMZGHH36Y3//+99x///384he/aHe/JUuW8MADD9CvXz+uuuoq7r777na3zc3NZdu2bRQWFpKRkdF8fwoVRs0lijC3UeiAu6gSFYnCDu1Nx93WlCmXXnopt956Kx6Ph5UrV3LeeecRHx9PVVUVCxcuZOPGjTidTnbs2HHC5//ss8/YsmVL8zxPXq+3VbvDsUpLSyksLOScc85BRIiJiSE/P7/d9pDuMP1LxAvaVPXk0LmeooltiUJEBgPPAP2BILDIGPMHEekNLAUygSLgamPM4W9yro6++XeWnJwcli9fftSy6upqSktLW931LS4ujgsuuIC33nqLpUuXsmDBAgAeeeQR+vXrx6ZNmwgGg8TFtR5U1dHU49OnT+/wznXHWrp0KYcPHyYrK6s53hdeeIGHHnqoze03bNhAXl4ew4cPZ8+ePdTU1JCUlHTC51OnQdM3+rA3ZmuiiCZ2tlH4gTuMMaOAycDNIjIauAt41xiTDbwbeh5xpk2bRn19Pc888wxg3UzojjvuYOHChcTHt54Sev78+fztb3/jo48+YubMmYA19Xh6ejoOh4O///3vBAKBVvtlZmayceNGgsEge/fuZc2aNQBMnjyZTz75hMLCQsCaMbapRHL33XezYsWKVsdasmQJK1eubJ56fN26de22UyxfvpxVq1axYMECEhISuO6667j11lvxeq0PrpKSEp59NoyT1EWrpik0wl71pAPuoolticIYU2KMWR96XANsBQYCs4HFoc0WA3PsifCbERFWrFjBsmXLyM7Opk+fPjgcDu699942t58xYwarV6/m4osvbp7p9aabbmLx4sVMnjyZHTt2kJiY2Gq/qVOnkpWVxdixY/nZz35Gbm4uAKmpqTz99NMsWLCAcePGMXnyZLZts9ppvvrqq1Z3zisqKmLPnj1Mnjy5eVlWVhbJycl8/vnngFXCaeoe++yzz/Lee++RmpoKwEMPPURqaiqjR49mzJgxzJkzp3ldS//7v//LoEGDKC4uZty4cfz4xz8+2bdWtWRbY3bTgDstUUQFY4ztP1jVTHuAZKDymHWH29nnemAtsDYjI8Mca8uWLa2W2emTTz4xGRkZZu3atXaHYmbMmGF3CMfV1a5fl7VvgzEPJBuz9fXwnjcYtM773i/De151WgFrzQl8RtvemC0iPYDlwO3GmOoTvR+zMWYRsAis+1F0XoSnx9lnn93mXevsoDcP6kaCNlU9iVjtItpGERVsHUchIi6sJPGcMebl0OJSEUkPrU8HDtoVn1JdXnNjtg3f+ZxubaOIErYlCrGKDk8CW40xv2+x6lXg2tDja4FXTvUcRrtvRiS9bifBrnEUYA260xJFVLCzRDEV+D5wkYhsDP1cBvwamC4iBcD00POTFhcXR0VFhX7oRBhjDBUVFW12BVZtsDVRuLUxO0rY1kZhjPkYaK9BYto3PX5Tz5qmuYhU5IiLi2PQoEF2hxEZmns92fCv7HBp1VOUsL0xu7O4XK7mgWNKdVtBO0sULr0VapTQSQGVimRNVU9HkCWLAAAgAElEQVThHpkNoUShJYpooIlCqUhm1zTjoG0UUUQThVKRrLmNwoaqJ4f2eooWmiiUimR2TeEBoXEUmiiigSYKpSJZ88hsuxKFtlFEA00USkUyu6YZBx1wF0U0USgVyXTAnQoDTRRKRTI7ez3pgLuooYlCqUgW8Fq9j05w1uXTSgfcRQ1NFEpFsqDPnmon0AF3UUQThVKRLOCzpyEbtI0iimiiUCqSBXz2tE+ADriLIpoolIpkAa+NVU86jiJaaKJQKpIFfPZMMQ6hRKGN2dFAE4VSkczWxuwYLVFECU0USkWygFcbs1Wn00ShVCQL+G1szHZZc03p7Ya7PU0USkUyWxuzQwlKez51e5oolIpkAa99JYrmRKHtFN2dJgqlIlnQxqqnppKMJopuz9ZEISJPichBEclvsay3iLwtIgWh373sjFGpLs3OxmxHqFtuULvIdnd2lyieBi45ZtldwLvGmGzg3dBzpVRbAnZ2j9USRbSwNVEYY1YDh45ZPBtYHHq8GJgT1qCUiiR2TuHRnCi0Mbu7s7tE0ZZ+xpgSgNDvNJvjUarr6hKN2ZoouruumChOiIhcLyJrRWRtWVmZ3eEoZQ9bR2Y3lSg89pxfhU1XTBSlIpIOEPp9sK2NjDGLjDF5xpi81NTUsAaoVJcR8B1pVA43V4L129dgz/lV2HTFRPEqcG3o8bXAKzbGolTXZmdjtjuUKLx19pxfhY3d3WOXAJ8CI0SkWESuA34NTBeRAmB66LlSqi12JormEkW9PedXYWNTmdVijFnQzqppYQ1EqUgV8No3zbg70frt1UTR3XXFqiel1ImyszG7uUShVU/dnSYKpSKVMdaoaLtGZje3UWiJorvTRKFUpGoav2DXOApXqOpJSxTdniYKpSJV09QZdk4zLk4tUUSBU04UIvL66QxEKXWSmhOFTSUKEatBW3s9dXvfpETxk9MWhVLq5DXN2mpXogCrQVvHUXR7p5womuZjUkrZxO6qJ7AatLVE0e2dUAdsEdkFtLoxrjFm6GmPSCl1Ypoas+3q9QRWg7a2UXR7JzpSJ6/F4zjgu0Dv0x+OUuqE2d3rCUIlCq166u5OqOrJGFPR4mefMeZ/gIs6OTalVEfsbsyGUBuFlii6uxOtespt8dSBVcJI6pSIlFInJthUorCzjSIRakvtO78KixOtevpdi8d+YBdw9ekPRyl1wrpC1ZP2eooKJ5QojDEXdnYgSqmT1BUas90Jej+KKPBNBtzlHn8rpVSn6QrdY1064C4afJMBdzeetiiUUievK1Q9uUNVT6ZV73nVjZzwRPYi0gvIxuoeC/D3TolIKXVigl0gUbgSAAP+RnDF2xeH6lQn2uvpx8BtwCBgIzAZ68502kVWKbt0haqnljcv0kTRbZ1o1dNtwLeA3aGG7QlAWadFpZQ6vkBoridbR2brzYuiwYkmikZjTCOAiMQaY7YBIzovLKXUcXWFAXehmxct/2yHfTGoTneiiaJYRHoC/wDeFpFXgP2dF5ZSqk07P4B/3GQ1HneFRBG6edHHm3dC/stHSjmqWznRKTy+bYypNMY8CNwHPAnM6czAlFJt+OKvsPE5OLSzxTTjNs8eC+RUrYZlP4S1T9kXi+o0J9091hjzoTHmVWOMtzMCUkq1YAwUr4O9X0AwCLs+spbvXXNk/EIXKFGMNDut5x///sgAvPXPwLu/0K6z3cAJd48NNxG5BPgD4AT+aoz5dTjP7y3eh2vgAEQknKdV6ojag/C3S6Gi0Gqwnv88NFYCUFP4CQmNpTh7ZkBscqtdPQEPHxV/RHqPdHL65HRejKESxSjHHoLixFFTAl88CSMvg3/eYVWPxfeGsxd2Xgyq04npgtleRJzADmA6UAx8ASwwxmxpa/u8vDyzdu3akz6Pv/YgjrLteDy98TpiiRmSSZzfQ8G9D2JWvo53ynmc8fB/ER8ogeRB+NxJfPz1KryHKxkUP5jR485FHA4IBtmy/zBut5uhfXvg8QdxxzhwOoTqxkq2HtrG1gNfcWDD5wzceYhRpR4GpfYnYeQoqqbM4ZPqBqoPfk1OSSmxJfvxuHzsmjqQxpRY+sWncW7tQHoMziSmTx8AjDGU1dbjMn5S3LEA+IqLCRRvx+z/EvfoicSMPg8ThIov1lBdtINehzbQo1c1rqQkPMkTqFlXiAl46TtzCtIrnYAvHm9jDNtjU6msLmdy+QrivBVIYl+2ZV7D3m0HSPnyM0bl9sc3ZgQH4hIoqT9AvNfBwNXraSgrpzqtF6VTsunX4ww27t/Ntu3LmbyjkYExvRgz/RxSYj3UV1ewYetenL5DOOMS2D7uMnZ6y/BX72GGo4LU+F7EDcijPjCErxsCVAR2kVOxjfQPVuPYUUTF4EEUjhpN9YDhjM3fhzfg4ZNzejMy4wIyE8czIjUR39c78O0txiAQNDh6JJIwcSK7avyszD9AotuJ012F8dWQ/tTLJO/aBrFxFF/zI8yoHPom9iCvXxyu8oOYQJBgXBxBdywCfLH7EOX1foYN6stBLxw6sJfUHctIKqtD6mOpl97Ep/WEoYkknDmGjAFnkBKbQjAYwBwupbFgG5X7a3Ae2I/U1BBz+TTWxJZQtPZ9EourcLniYMIIJvQYxdC1f6G+/AM+mjiP2vUrmPJlIj2CNbhGD+RzdzUTAxX0zruOhr7fIVBTQ0zv3jj79uXDXe/y1BePsblXHW5XHH+48A9MHTgVf2Ul21a9xMZ9a9idCkmjx5LgSsDlcJF4qIHRw6cwqv+45i9HxhiKqovYceArGkv2M2rEOaT3GWL97xwoJalXPwKecmIfHQ/Av1JGsKF3HKZyN+c4epNSXEGpewhFtcU4MsdSP+xcVhenk1Z1gLPrtzOppoyes+YRd9EC1hdvpWDHChr3biU5O4eRQy+jtrIPvRMgs+xdnGXbMJNvwiQPoKi8lrr1rxHjb8Q1YixDh+chCPur6llX9iF1gSouGHAZv3lzFxv3VjIjJ5Vv5ybT1+0nuUogOYWv/Y0cbNxJn4QURvQ8A9ehr/GJg73OJPL3BhmyextpX3xI4tlns2l4Go+tfZxhpoG8+h70lkF83qeKL/x1NBT2Z9jgC7jq7P6sPriMAYkDuDTrcvaUOUlLdJN2cDeHP/8X8UlJOPs5eaW0ilWHXJR5+/I/F/RnRJKPen8KT7/2FQm7CznPeYjek/JImj6DcmcCawr208MRYGpaPHUb1lOb/yWy7wCxWUOJnzyR2oZ8HOlj6Zdz3kl//gGIyDpjTN5xt+uiiWIK8KAxZmbo+d0Axpj/19b2p5ooVqy4m30v/oMLNxgQYdNQYXiJIbEevhoWT86uBhpjYe9oHzF+4LCLvhXgcUFtPLiD0LsGEhoMvhgoSxVK+sUR64dgMECd009BqnXMs7YbXAHrvDVxkNh4pN7P56R5XRBrud8BBQMgzgdZpRAUKBuTzvtT+rDHv4Oxm3ycn29I8LT/+gzQsjzkc0J9HKS06MlYm2AgKPRotJ77HVCeAqlVBgRMnKEhFpIOHamlrEiCjUOFiiThgq+CpFUdOV51PJT0hqR6GHD4yGsKOmDbEDBOyPnaYBxQ1hfy0x0MKjf0PwSFA4QtGcLevjC8IkhauZBVYsg8aB2n0Q1xLSo8g3Jk+aYswR10MLbIj9vbuhToi4GAyxB0wr9GONiWLpybbzizyFA+CGIrhdgGwwdjHSQ3xJL3dYN1zY/DYBDaLnUGBfxOiAmAN8a6li0FHOAMQqOr9bom64YJh5Jg0g5DUgM4Qv+u64cJ+9MMZ+1PIXV3VZv7BnomsX2QUOqsY0R9Cmk7DxMTMM3nfuZiJ8W9DTM2WH+ftXGwaYSbfZlJpFc76FtcQ1x1I4PLICZoHbMy0XotaVXgcQvVF0wgrm41+8sTGFbg4HAPqI+FnnWQcszMHl4nfD5SGFhhGHog9B45DJvGuKj3BRi/05DogYMp4PZbxyjvZWhwQ2KdkFIfOmeyoW+5ISb0B7A3zUFNL6FHZYCggbo4ONBXGHJISKkCjyNIUCC5wTomwK5+8OlIBxXJ0P+w9XfgcUJJbyGr1JC9/8j1OZgCH54pXLTB0KfmyOvxxECs3/qfqUgGMVAbB1WJQs8Y6FsSJKnm6L8NnxPKk6EqEdJqDCk14Awe2cbjNsR6BSOGPf2FnvWG5Cqa/8a8TjiU7CStMmD9LcQGOXxWJmcveqvtP6DjiPREcRVwiTHmx6Hn3wfOMsYsbLHN9cD1ABkZGRN379590ud56/e/ZNBfnuXzCfG4HEFytnjZM8jBBxOCfJVhmLof8j51kb3Th9cJB1OdSFpfYsRNoK4aj7+W8kThUIKTlKCDwXsbGXjQ0OgCr8v650poBK9LaBjixp2Rgn/0WP7eYwDrGz9kSFk5k/bDyBovvaSeyoEegikB+lYb+m134S2Npda4WDM2SG2jg4vWWUkqwWslgD0jerCpbyMNEuRgCtTFO3AHUuh7uJYeHh8xQUNCnwAxvXuzmzSGba8msT7IofQk1g3zE1NTw8zPvdS5XZT3ciMphszyBpIrAxT0TqAmcJiedUGS6uHggBiKx/UlpTCGMdsrGVZSi9traEyB1TPPoKRPT877+kuGFlZS7XETSEyi5/ARVPUOstlXRcP2GkYX1ZLo9fP5mbF4A40MK4VhB4K4esbiH9if6l2H6X34yIeeJ8GJr18ymwYM4p+DkylKP8QE51i+X1ZC2q41FPdvIMHjZfAmobLChTcobBjq5MshsK+P4HeCA8OZhwMMKnLhN4ak+iC5XxucATBieOrSGN46U+hTZ7jvH15SDzjwOIXPzxDyhwgBB6Q1GlJ8Bo8jlh6OGBL8PnyeRqqNE3AwZPBoygcmsy52N2X+MiZW1HFJcQOUJ1NOPBUOBzFeoT7eyYH+Tnb1qqewlw9H0PDjfxmGVjlh4GBSBieTXFWEFBezOSmGiuokhm51EGNiqEhOpPy8Ij7rOZiRO9xM+3Qf4hMOpghvTomlYXg6g/3J+MsryOgzlMuyLqPhw9XUb9tGzaED7E/ys3dwHOlXfIfzRl1K7e8fpW611d4hCQnEzv82pTs3E//FFtx1XgIO4dDAJOLS+pE0cgyxw4axb9eXmP2lOOs9VJ3Rn8NfrmPcphpiQslu5xnJZPbJ5cvCEhyJ1aztl8GlV5zP3tIUNn62hivrNpKxZS+1A5JZN74Pr6Xu4zufeJi0w+BNcNAwLIsdvUfRZ8da4uIrKevjIak8Bp/XxaH4eOJ7VODwGFIqHRwa0hOT4iajYjemKJb4eqGyj4ueDgcJtX6cFQEOpQilfQ29AwFcQRelMQlsHRwgrdFw5i4/vUqsbwIG2JcaixNIrfJS0ztIfrZhea6LsbsNsz+GvuVBvAMG8OkZ6QxN2MjY/YeRegcHe0GR6U2g2kFaI/T01XDI68TR4GBvmlAyPAlHWiP7g25iKxxM8PZmUFklgcpqCnrEsD/Zgb+HkNajirLehvf79CLukIfJ24Pk7RIqkoWv+wZpTISUnh6Se3r5sEc8O42bM3cZcgsNsVPO44d3PH6qn7URnSi+C8w8JlFMMsbc0tb2p1qi8PkDNBYWkjTymCEhwSBU74PkgeBw4D98GGdSEhLTuknHGEMgaIhxOkK7BmkINBAfE4/HF+TZNzZQ7XQzNWcQZ2X17rjNI+AHT7X1462D3kPBFU9FrYcvN2+iYfNqhv3zI5JGjSV14UJc/fvjC/j4qrSQ/kk96ZeYhtPh5OuyWoyBYamJ36iNpcZbQ1FVEVkpWfRw92hevvdQPVtLqhmS5GRoei9crpimNwNTuQdJGQQOZ4fHDpogxhicx2znKz2It6gId1YmMampJx6/rxFEICaWWk8de2tKqavdQ01lCiWNKZw1LI3MPvF4Ah7ivAb/oUM44uLw9kyk3l9PijsZ18GtUF2CiUthW2Iydf4Gsntlk+JOto7dkt+DT4SACRIXE3f0uoAPGqsgsW+HIRtj8AUMTofgdEjLFXgCQbaW1LBu92HW7z6MU+A7ZhX35venikQ2uq5nR/9LuHTv1Wz8z8vpmdhxzydjzFHvpQkEqHn3XZzJycSNHo0z2WrnMMEgvj17iElNxZGY2OExA8EAb275lEHPfYcMp4/fOm/gHfdFJMbG8MT3JzLnT59Q77WKyldNHMRvvjMOEZrjCAaDlFQ10ugLMCztyO1tPP4AbqejebvdFXW8uHYvs8amM6pfIjhb/B96aiAm/uhlx/I1QEwctd4A8S5n83vtO3AA09iIs29fnD16HL2PMTT6g8TGWFXLnsJCYocOxYODd7ce5JyMeFKkDhJ6N49Iz99XRVo8pLk9FPiq6BXXi77x7f8NeP1Bqht99E5w46jeC8bgTx7Mb1ZtorLBx39dOZHYGKdV1VzdSJLTR3ygGhqr2IqfTYe3khKbwhm9zmBYz2EdXqv2RHqiCEvVk1KRxOsPcu5v3qO02sPrlzSwQzL4jzfLWHPPNNKS445/gE6wbvchRj01kgTxMNfzIFtiRvKPm6cysn8yb20+wBe7DnHuGamcO7wvDod2DOlqTjRRfJPZYzvTF0C2iGSJiBuYD7xqc0xK2cod4+D2i89gdHoyI86dS7DHAAA8/qBtMdV6AtRjdajYbfrxq2+PZWR/q3QyM6c//zlrNOefkapJIsJ1ye6xxhi/iCwE3sLqHvuUMWazzWEpZbsFkzJYMCkDwKoWwaqqsUudx0+DiSXg7sG7//c79EyMtS0W1Xm6ZKIAMMa8AbxhdxxKdVVNiaLRZ1+Jos7jp55YAj37aZLoxrpsolBKdSzWZXUEsLPqqc7j5/3geAaPPBMbJxJRnayrtlEopY6jS1Q9eQP82v89nOffYVsMqvNpolAqQsU1lShsrHqq9fhxOYXYmI67Q6vIpolCqQjVFUoU9R4/CW6twe7uNFEoFaGOJAp7u8f2iNVE0d1polAqQsV2gaqnOo+fxFitduruNFEoFaG6QtVTnVernqKBJgqlIlRXqHqq8/i16ikKaKJQKkI19TSyN1EEtOopCmiiUCpCuZyCCDT67Kt6qvX4SdQSRbeniUKpCCUixMU4bS1R1Hv9JGobRbeniUKpCBbrcuCxsURhVT1poujuNFEoFcFiYxy2lSi8/iDeQJAe2kbR7WmiUCqCxdpY9VTnsW4lqt1juz9NFEpFMKtEYU/VU53XShTaPbb700ShVASz2ijsKlFYCUrbKLo/TRRKRbDYGCeNNpUoapuqnrSNotvTRKFUBIuNsbNEoVVP0UIThVIRLM5lX2N2vbepMVtLFN2dJgqlIpidjdlNCarpBkqq+9JEoVQEs3McRVOVV9PkhKr7suUKi8h3RWSziARFJO+YdXeLSKGIbBeRmXbEp1SkiI1x2tZG4QlY53Vrouj27GqFygfmAk+0XCgio4H5QA4wAHhHRM4wxtg3R4FSXVisy76qJ2+oJBPr1Kqn7s6WrwLGmK3GmO1trJoNvGCM8RhjdgGFwKTwRqdU5IiNcdBoV4kilKBiXVqi6O662hUeCOxt8bw4tKwVEbleRNaKyNqysrKwBKdUV2NN4RHAGBP2czeVKNzOrvYxok63TrvCIvKOiOS38TO7o93aWNbmf4AxZpExJs8Yk5eamnp6glYqwsTGOAga8AftSRQxDsHhaOvfVnUnndZGYYy5+BR2KwYGt3g+CNh/eiJSqvtp6prq8Qdxhfmbvccf1B5PUaKrXeVXgfkiEisiWUA2sMbmmJTqspraB+y4J4XXH9QeT1HCru6x3xaRYmAK8E8ReQvAGLMZeBHYAqwEbtYeT0q1r+kbvR1jKTRRRA9buscaY1YAK9pZ90vgl+GNSKnIFBtzpOop3Dz+QPP5VfemXweUimBNJYpGO6qeAlqiiBZ6lZWKYM1tFHZVPWnX2KigV1mpCNZc9WRDicLjD+pguyihV1mpCGZnY7ZHSxRRQ6+yUhGs5TiKcPP6g8TqFONRQROFUhHsSInCnqonLVFEB73KSkWwI20UdpQoAjoyO0roVVYqgjU1JjfaUKLwBnQKj2ihV1mpCNZc9WRDicLj03EU0UKvslIRzM6R2TrgLnroVVYqgtnamO3TqqdooVdZqQjmcAhup0NLFKpT6VVWKsLFxjjC3kbhDwQJBA1uvV92VNBEoVSEi3U5aAjzFB7eQLD53Kr706usVISLdztp8PrDek69X3Z00ausVIRLdMdQ7w1ziaIpUWgbRVTQq6xUhIt3O8Ne9dTUeK69nqKDXmWlIlyC20mdJ7xVTx4tUUQVvcpKRbgEG6ue9Fao0UEThVIRLsGWqifrfFr1FB30KisV4RLcTm3MVp3KlqssIv8tIttE5EsRWSEiPVusu1tECkVku4jMtCM+pSJJgjuG+jC3UTSPo9BEERXsuspvA2OMMeOAHcDdACIyGpgP5ACXAI+JiFaCKtWBBLeTel8AY0zYztk0ElxLFNHBlqtsjFlljGn6CvQZMCj0eDbwgjHGY4zZBRQCk+yIUalIEe92Ykx4Z5BtKlFooogOXeEq/wh4M/R4ILC3xbri0LJWROR6EVkrImvLyso6OUSluq5EdwxAWLvIaq+n6NJpiUJE3hGR/DZ+ZrfY5l7ADzzXtKiNQ7VZnjbGLDLG5Blj8lJTU0//C1AqQsS7rQ/rcDZoN/V60hJFdIjprAMbYy7uaL2IXAvMAqaZI5WrxcDgFpsNAvZ3ToRKdQ8JoUQRzi6yOtdTdLGr19MlwJ3AlcaY+harXgXmi0isiGQB2cAaO2JUKlLYUfXUPIWHzh4bFTqtRHEcjwKxwNsiAvCZMeYGY8xmEXkR2IJVJXWzMSb8t+5SKoI0VT01hLXqSUsU0cSWRGGMGd7Bul8CvwxjOEpFtAQb2ii06im66FVWKsIlhKqe6sPZRhEI4nY6cDja6n+iuhtNFEpFuOYSRTjbKHx6v+xooldaqQhnS9VTIKCJIorolVYqwjVVPYW7e6zO8xQ99EorFeHcMQ5iHBL27rFaoogeeqWV6gbiwzzVuJYoooteaaW6gQS3M6zjKLxaoogqeqWV6gYS3THUeTu36unxD7/mX4XlQKjqScdQRA290kp1A/GdXKI4VOfl4ZXbeHz1TqCp6klnjo0WmiiU6gaabof6/vaDLFmzh90VdQAYY9i8v4pg8Jvd1OiTwnKMgXVFh/AHgngCWvUUTeya60kpdRoluGOorPfyH0s3crjeh9MhLPnJZHaU1vCf/8jn+5OH8IvZOYTmVuuQLxDkNyu38d62g5ybncoN5w9j9Q7rni913gCb91fj8QVwJ8V29stSXYQmCqW6gQS3k3W766j1+Fl44XBWbNjHff/Ip6LOQ0q8i79/tpuAMTxwxWiqG/y8tG4vb28pZcLgXvzb5AyGpvYA4KviKn7x+ma+KDpMbkZPnv98Dxv2VlJa1ci3MnvxRdFhPt9VQZ3XryWKKKKJQqluIN7tpDY0juLi0f0YPSCZm55bD8ArN0/lzfwDPP7h16zeUUZpdSO+gGF0ejJ//6yIZz/bzW0XZ7N5fxVvfHWAXgku/mfeeOZMGMhrm/Zzy5INANx+cTbltV4Wrd5Jea2X688datvrVeGliUKpbqDpnhQxDmFk/yTOHJTC3AkDSU2K5czBPTlzcE9yM3ry2AdfMzOnPwsmZTA8rQcHaxq5e/lX/Pdb20l0O7ltWjY/PjeLpDgXALPGpfPPL0tYufkA52T3ZcOeSpau3cuEjJ5876whdr5kFUaaKJTqBprme8rul0Scy3r8+3njj9pmRk5/ZuT0P2pZWlIcf702j9UF5YwZkEyfHke3O4gIv7v6TH60P4tBvRKYProfb3xVwsPfGYdTZ46NGpoolOoGmm5eNHZg8knvKyKcf0b7951PjI1hUlZvwKrW2vjADE0SUUZbo5TqBpqqnsYOTOn0c2mSiD6aKJTqBppKFGPCkChU9NGqJ6W6gWmj0iipGhaWEoWKPpoolOoG0lPi+b8zR9odhuqmtOpJKaVUh2xJFCLyXyLypYhsFJFVIjIgtFxE5H9FpDC0PteO+JRSSh1hV4niv40x44wx44HXgftDyy8FskM/1wN/tik+pZRSIbYkCmNMdYuniUDT1JazgWeM5TOgp4ikhz1ApZRSzWxrzBaRXwL/DlQBF4YWDwT2ttisOLSsJLzRKaWUatJpJQoReUdE8tv4mQ1gjLnXGDMYeA5Y2LRbG4dqcyJ9EbleRNaKyNqysrLOeRFKKaU6r0RhjLn4BDd9Hvgn8ABWCWJwi3WDgP3tHH8RsAggLy/vm92VRSmlVLvs6vWU3eLplcC20ONXgX8P9X6aDFQZY7TaSSmlbCTGhP/LuIgsB0YAQWA3cIMxZp9Yt996FLgEqAd+aIxZewLHKwsd51T0BcpPcd/O1lVj07hOTleNC7pubBrXyTnVuIYYY9qfETLElkTRlYjIWmNMnt1xtKWrxqZxnZyuGhd03dg0rpPT2XHpyGyllFId0kShlFKqQ5ooQj2nuqiuGpvGdXK6alzQdWPTuE5Op8YV9W0USimlOqYlCqWUUh3SRKGUUqpDUZ0oROQSEdkemtb8LhvjGCwi74vIVhHZLCK3hZY/KCL7QtOxbxSRy2yIrUhEvgqdf21oWW8ReVtECkK/e9kQ14gW78tGEakWkdvteM9E5CkROSgi+S2WtfkehXMq/Xbi+m8R2RY69woR6RlanikiDS3et8fDHFe7101E7g69X9tFZGZnxdVBbEtbxFUkIhtDy8P5nrX3GRGevzNjTFT+AE7ga2Ao4AY2AaNtiiUdyA09TgJ2AKOBB4Gf2fw+FQF9j1n2G+Cu0OO7gIe7wLU8AAyx4z0DzgNygfzjvUfAZcCbWPOaTQY+D3NcM4CY0OOHW8SV2XI7G96vNq9b6P9gExALZIX+Z53hjO2Y9b8D7rfhPWvvMyIsf2fRXKKYBBQaY3YaY7zAC1jTnIedMabEGLM+9LgG2Io1a25XNczDeekAAAWVSURBVBtYHHq8GJhjYywA04CvjTGnOjr/GzHGrAYOHbO4vfcobFPptxWXMWaVMcYfevoZ1nxqYdXO+9We2cALxhiPMWYXUIj1vxv22EIzR1wNLOms87eng8+IsPydRXOiaG9Kc1uJSCYwAfg8tGhhqOj4lB1VPFiz964SkXUicn1oWT8TmoMr9DvNhrhams/R/7x2v2fQ/nvUlf7ufoT1rbNJlohsEJEPReRcG+Jp67p1pffrXKDUGFPQYlnY37NjPiPC8ncWzYnihKc0DxcR6QEsB2431s2d/gwMA8Zj3ZPjdzaENdUYk4t198GbReQ8G2Jol4i4sSaWfCm06P9v795C46jiOI5/f02kF69URUUotGIQqWhpRZCCBCIYUaH6Uu1DvSAIKqiIlwZ9UhCRvojFW2lsiSiipX0opaAExT6orU2baL0VFFFSKL5IQVL9+3DOymTYnW5iMxvY3wfCbs6emTn5z7D/mdnN/8yHmFWZF8edpCHgFKnMP6RYLYuIVcATwLuSzqtxSK3227yIV3Y3009Iao9Zk/eIll2btM06bt2cKNouaV4HSWeRDoCRiPgIICImI+LviPgHeIs5vORuJSJ+y4/HgZ15DJONy9j8eLzucRUMAgcjYhLmR8yyVjHq+HEnaSNwG7Ah8g3tfGvnRH5+gPRZQF9dY6rYbx2PF4CkXuBO4P1GW90xa/YeQU3HWTcnii+BKyUtz2el60llzmuX731uBb6NiM2F9uI9xXXAeHnZOR7X2ZLObTwnfRA6TorTxtxtI7CrznGVTDvL63TMClrFqKOl9CXdAjwN3BERJwvtF0vqyc9XkOatP1bjuFrtt93AekkLJS3P4/qirnEVDABHI+LXRkOdMWv1HkFdx1kdn9jP1x/SNwO+J50JDHVwHGtJl4WHgUP551ZgB3Akt+8GLqt5XCtI3zgZAyYaMQIuBD4GfsiPSzsUtyXACeD8QlvtMSMlqt+BKdKZ3AOtYkS6JfBaPuaOAGtqHtePpHvXjePs9dz3rryPx4CDwO01j6vlfgOGcry+Awbr3pe5fZg0HUKxb50xa/UeUctx5hIeZmZWqZtvPZmZWRucKMzMrJIThZmZVXKiMDOzSk4UZmZWyYnCupakSyW9J+knSd9I2iOpL1cFndX/X+Tqohedps+m0u/7T9N/VNKa2YzH7ExworCulP+BaScwGhFXRMTVwCbgkho2Py1RRMSNNWzTbNacKKxb9QNTEfHfHAIRcSgiPit2krRI0jalOTm+ltSf23skvZLbD0t6tLTcYkl7JT1Yan8JWJznLxjJbX8WXn8qr3Ms9y0uu0DSO5JeyNsfljSe+z9+pgJjVtbb6QGYdchK4EAb/R4GiIhrJF1FqqTbB9xHmh9hVUSckrS0sMw5pLL12yNie3FlEfGMpEci4rryhiQNkspE3xARJ0vr7CUV8BuPiBclrQYuj4iVedkL2vy7zWbMVxRm1daSyksQEUeBn0mF3wZI5S9O5deKcxjsAraVk0QbBvJyJ5us8w1yksi/HwNWSHo112+qqiRq9r84UVi3mgBWt9GvWbnmRnur+jefA4P5c5CZqFrnfqBf0iKAiPgDuBYYJV31vD3DbZm1zYnCutUnwMLiZwiSrpd0U6nfp8CG/HofsIxUnG4f8FAuP03pNtHzpGKFW1pseyqXjC7bB9wvaUmTdW4F9gAfSOrN36xaEBEfAs+Rpu80mxNOFNaVIlXDXAfcnL8eO0Gat7lcs38L0CPpCGkugnsj4i/SGfwvwGFJY8A9peUeAxZJernJ5t/My40UGyNiL6ly6leSDgFPll7fTKpSuoM0W9lo7jcMPDuDP99sRlw91szMKvmKwszMKjlRmJlZJScKMzOr5ERhZmaVnCjMzKySE4WZmVVyojAzs0r/AoQYQvoyIyTbAAAAAElFTkSuQmCC\n", - "text/plain": [ - "" - ] - }, - "metadata": {}, - "output_type": "display_data" - } - ], - "source": [ - "# Plot results.\n", - "plt.figure(1)\n", - "plt.plot(iq0[0], label=\"I value; ADC 0\")\n", - "plt.plot(iq0[1], label=\"Q value; ADC 0\")\n", - "plt.ylabel(\"a.u.\")\n", - "plt.xlabel(\"Clock ticks\")\n", - "plt.title(\"Averages = \" + str(config[\"soft_avgs\"]))\n", - "plt.legend()\n", - "plt.savefig(\"images/Conditional_False_Pulse.pdf\", dpi=350)" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### When the value of number is below the threshold, the conditional statement is True so you don't see a loopback pulse." - ] - }, - { - "cell_type": "code", - "execution_count": 6, - "metadata": {}, - "outputs": [ - { - "data": { - "application/vnd.jupyter.widget-view+json": { - "model_id": "c8e9293de2e8476fb38de0bc2305d290", - "version_major": 2, - "version_minor": 0 - }, - "text/plain": [ - "HBox(children=(IntProgress(value=0), HTML(value='')))" - ] - }, - "metadata": {}, - "output_type": "display_data" - }, - { - "name": "stdout", - "output_type": "stream", - "text": [ - "\n" - ] - } - ], - "source": [ - "config[\"number\"]=10\n", - "\n", - "prog =LoopbackProgram(soccfg, config)\n", - "(iq0,) = prog.acquire_decimated(soc, load_pulses=True, progress=True, debug=False)" - ] - }, - { - "cell_type": "code", - "execution_count": 7, - "metadata": {}, - "outputs": [ - { - "data": { - "image/png": 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t2jQuuOACnn76aZLJJI888gi/+c1vKCsrA1TdqauuuirnGCklCxcu9Eqn9Gm59IZlcP/pkCkkqoMBHWmDL/xqESu2tQ10UwJ8AjGgeRoDgpdvgx0re7x7VFqMM51igZEKipbMOvwk+HLpSYVWr17NaaedlrOupqaGcePGsXHjRiZNmuStnz59OnPmzOGiiy5C13Vef/11fve73yGl5LXXXiMWi1FXV8eMGTPIz3wvhd27d3Pvvffy97//ncrKSu677z5+/etfc9ddd3HPPfeUPG727Nn85Cc/YeTIkVx55ZXcfvvtJfedPHky69atY+PGjYwdO9abX6MUWlpaOOSQQwiH1Ss4evRoGhsbe3Q/3WLnGti9ATp3Qll135xzEGFrS5JNuxJs2BFn0phDBro5AT5hOPhIYwBQqoR4MeXy5S9/mZtuuolMJsOCBQs4++yzKS8vp729nZkzZ7JixQpCoRAbNmzo8fXfe+891qxZ49Wd0nW9wE+Rj+bmZjZu3MiZZ56JEIJwOMyqVatK+k96q8KK7d9nZdZtU/1rHZw+ko6Ums9et4Iw8QB9j4OPNLpQBMWQNhLUt9cDcNyhxxHWev/IJkyYwLx583LWdXR00NzczHHHHZezPhaLce655/LKK68wZ84cZsyYAcCsWbMYOXIkH374IbZtE4vFCq7TVbn0888/v8sZ+fIxZ84cWltbGT9+vNfeZ555hnvvvbfo/h988AFTpkzhmGOOYevWrcTjcaqrS4/yhw8fTltbG6ZpEg6HaWho4Igjjuhx+7qEbal/LaNvzjfI0O6QhhGQRoB+QODT6Ab+EfHe+jTOO+88kskkTzzxBKAmRrrllluYOXMm5eXlBftPnz6dP/7xj7z55ptceOGFgCqXPmrUKDRN409/+hOWZRUcN27cOFasWIFt22zbto0lS5YAMHXqVN5++202btwIqMq2rlK5/fbbmT9/fsG5Zs+ezYIFC7xy6cuXLy/p15g3bx6vvvoqM2bMoKKigmuvvZabbrrJi4ZqamriySefzDlGCMHnP/955s6dC/RxuXRPaRycpNEWkEaAfkRAGr3A3kZQCSGYP38+c+fOpba2lmHDhqFpGnfeeWfR/S+44AIWL17MF7/4Ra/A4A033MDjjz/O1KlT2bBhA5WVlQXHfe5zn2P8+PGcdNJJ/PCHP2Ty5MkAjBgxgscee4wZM2Zw8sknM3XqVNatWwfAypUrC2YErK+vZ+vWrUydOtVbN378eGpqanj75ZexOjqYNWuWF3L75JNPsnDhQty5TO69915GjBjBiSeeyMSJE7n88sspNs+J61s55phjaGlp4dprr92Lp1sELmnYBydpZJVGkFsUoO8xYKXR+wt9XRo9rsfZ2rEVgGMOOYaycNk+t/Gdd95hxowZPPfccwUO8v2NCy+8kFdeeaXH+2fq65G6QezY2n5sVS56/fu9NQv+fjdc/SKMP7vf2nWg4mcvr+PBf3zM98+r5QfnHzvQzQkwSNDT0ugHn0+jl8gxT/VRVvhnP/vZorPxDQR6QxgA2Db9M2N6H+IgN0+5SsO0A/NUgL5HYJ7qBT5pqmyvYNtwoD8H6+AmjY7APBWgHxGQRjfwq4ug0i3IwUAaB3nIbVtK3bduBu9rgL7HgJKGEOJLQoj1QoiNQojbimz/rhBipRBihRDiLSHEiQPRThcHg9JIm2nqWusw3Y43H9YgIo2D3hEekEaAvseAkYYQIgT8FvgycCIwowgpPC2lPElKOQn4OfDr/dzMfvFpHMjIWBl0S0cvMUqXdmGo7wGHg9yn0ZYMSCNA/2EglcYZwEYp5SYppQ48A+QE6kspO3yLlQyAB9ZPFAeD0nDv15aFHY6UEvahBtd+Q5DcBwQ+jQMFG1o3sLpl9UA3o88wkKRxJLDNt9zgrMuBEOJGIcTHKKVxU7ETCSGuE0IsE0Iscyut9gf2RWlUVVX1SRv66jzF8P3vf58Tx5+IbdseaTz22GOMGDGCU089lWOPPZZL//3fee/993OO++Uvf8nxxx/PxIkTOeWUU7wkRj/+/Oc/M2HCBDRN63HNrL3GQezTsGxJPK3uPygjcmDg/y7/v/z3e/890M3oMwwkaRQrNFTQK0spfyul/BRwK/CfxU4kpXxYSjlFSjmlWBLZvuBgURq2bTN//nyOGH0Ey95dlnPf06ZN44MPPmD96tXccu21TL/5ZtauXQvAgw8+yGuvvcaSJUtYtWoVixcvLvqcJk6cyHPPPcfZZ++HvAnPp1HCL/MJhhs5BWAEjvADAhkrQ1vmk1NxeCBJowEY41seDWzvYv9ngMv7tUXF4Ov/+jp66tZbb+WBBx7wlu+++25+9atf0dnZyXnnncfkyZM56aSTeP755wuOXbRoERdffLG3PHPmTB577DEAli9fzjnnnMNpp53GhRdeSFNTE6A6+AcffLBoW9544w0mTpzIt6/7Ni8/93JR8xS2zTlnnMH/ufJKHnroIQB++tOf8sADD3hVbYcMGcLVV19dcOgJJ5xQUGer31BCaWzt2MpFz11EU2fT/mnHXmLL1dfQXuQ37wna/aQRKI0DAqZt0ql3dr/jIMFAJvctBWqFEOOBRmA68A3/DkKIWillnbP4FaCOfcR9S+5j3Z51Pd7fsA3PKRwNRYlokYJ9jj/0eG4949Zet2X69OncfPPN3HDDDQA8++yzLFiwgFgsxvz586mpqWH37t1MnTqVSy+9tEdVYA3D4Hvf+x7PP/88I0aMYM6cOdx55508+uijfPe73y153OzZs5kxYwZnXXAW9/z4HjJ6BvJrIjrJYpNOOIHHXn6ZeDxOPB7nU5/6VK/vvV9RgjTe3v422+Lb2BbfxqiqUQPQsO5hxeMk//lPyo49liF7UYurLYc0PrnKeDDBkhZxPV6y2vVgw4CRhpTSFELMBF4BQsCjUsrVQoh7gGVSyheAmUKILwIG0AoUDmEHMU499VR27tzJ9u3b2bVrF0OHDmXs2LEYhsEdd9zB4sWL0TSNxsZGmpubC2pEFcP69etZtWoV559/PqCKI44aNYqOlEFFNEQ4VCgudV3npZdeYtasWehhnZNOO4mFf1/IN67I4XCVo0FWfB2wH4FHGrnmqVW7VwFgygPXbGVsV2JbplN7dbyrNCIhMWh9Gun1G5CmQfmECQPdlD6BZVuY0iRtpSkPFxYoHWwY0DIiUsqXgJfy1t3l+//3+/qavVUEu1O7aU40A3BYxWGMqOhbn8mVV17J3Llz2bFjB9OnTwfgqaeeYteuXSxfvpxIJMK4ceO8MucuuiqDPmHCBN59911vmy0lqxvbGTkkxmHVhSXVFyxYQHt7OyeddBK2tEkkEzxX9VwBaeBU1v1w7VqOP/54ampqqKysZNOmTRx99NF98jz6BCWUxpoWNY+5dQCHDRuNijTsVLqbPYvDJY3hVWWYg5Q0dv7ql9idCcY9/dRAN6VPYEn1vsX1+CeCNIKM8G7Q33ka7lSqc+fO9aY+bW9v57DDDiMSifDGG28UrVN11FFHsWbNGjKZDO3t7bz++usAHHfccezatcsjDcMwWLlyFRL4/YO/4/777y841+zZs/n973+vSqCvXc6CZQtY9Poikslkzn7Stnlz6VIenTuXf3Mq0t5+++3ceOONdHSo6OiOjg4efvjhPns+e4UiyX1JI8mm9k1A9iM+EOEpjcxekkZSEeXwqrJBa56S6Qx23rs3mOEq27j+yZh+OCCNXqA/oqcmTJhAPB7nyCOPZNQoZWf/5je/ybJly5gyZQpPPfUUxx9/fMFxY8aM4aqrruLkk0/mm9/8JqeeeioA0WiUuXPncuutt3LKKacwadIkbz7xurr1DBs2LOc8yWSSV155ha985SvqHpFUVFZw+mdO58UXXwTUhEyTJk3ixClT+MXvf8/sWbO8Nl1//fV8/vOf5/TTT2fixImcc845VFRUFLR3/vz5jB49mnfffZevfOUr3jwh/YIieRrr9qzznPt9pTRSH37IxxdfjNWZ6JPzARjOlLe9VRq74hnO/vkbvLpGqeLhVdFB6wiXloXMZAa6GX0G9337pJBGUOW2G7jqQhPaPimNzs7S0RMrV+bOWT58+PAc81Kp8/z85z/n5z//ecE+kyZNYvHixd5yxrBY3xxn25YtfO1rX8vZt6Kigj179hSc45GnHmF09WgArrnmGgCMXbswm1Wn5JYSEULwox/9iB/96Ecl7w/gq1/9Kl/96le73KfPUMQ85fozoO+URmrFCvSNH2PubCZU1TfmOVdp2L30aWzdk/T+YhGNirLwoPVpYJqfKNJwS/J8UkgjUBrdwCUKIcSgzdOwnWY//sw8b1KnUnDvsWjIbR91QomMScboRxNRkTIiq1tWI5zUoL4iDXN3CwAyvXempGLwzFM+pWGnUnQs6LqEfdr3PA8pjxINaQes0kjqJi+tLB32LE0TW99PiZlSwsq5/Vo9wO/T+CQgII3uIBVhCMSgrT1lO0TQE87rqowIfrPOPhBoQ2uK5o6+62gLUIQ0tnRs4YgqNQd5yWKMvYS5R5GGne67UXFWaWSfT8ff/kbjzTd724ohpavf5pQxhzDxyCFEQgLDPDDf11dXN3PDU++zobl4J7pfzVPNq2DetVD3Wr9dwn3fOo1PRq5GQBrdwK80inakgwCueuhJF9Jl7Sn/pD77QBqWLTHtfuzQXHLzOcJ1W6cqokqw9JXSsFqUWW9vndb5sFMprJZC9WI07VDbu1A0KUdp/OrrJ/PIv55G5ABWGq4q2rizRCdq7UfzlO74o9L9l7Htvm8dekc3ew4OBKTRAwgGu9Jw/+2R1FD7Fst+7yPSsKWkPznDUxg+n4ZhGV64Y185wk2ng9/b8Nh8GE7mvlZZmUMQ5s6dAEijtAnFVRrl0TBCCCIh7YD1abgDhk27sqRx35L7+M0HvwFAmhZS1/ePOdh0nnOm/1SA+759UrLCA0d4N/hk+DT6xjyVqzT2ri1SSmwpsfpVaRQm9+mWTiysclT6Tmk4qqCPlIaboxH91KfQN2701mdJo7RZzVUa5ZGQOkf4wFUalkca2aiz5c3LqYmqUjTSyQeShoHoxge3zzAdRdOP/oYg5PYgg5v13J9Ko79r07j9876ap9zkPv9+e9uWHqmevUWR6Cnd1rNKQ1pIKel46aUuR+/5SLz3Hkaz04FLielEne2LT2NHYgfvbFch0a7Pomz8eOx02hukGLtc0ijtHM4njUhIHLB5Gi6Zfbw7SxqGbZCx1HOUpvpN9ouJylMa/deh+0NuN+3q5IOtrf12rf2BgDR6AIFQIbf74vxtaOCyyy6jtraWo48+mpkzZ5JxPorWdCtbOrbs1fnr6+uZOHFil/t4Po3emKcc0rjsssv4zGc+46y0EUJw7wMPMPaYY5g0aRK1tbVcccUVrFmzxjuFYRjcdttt1NbWMnHiRM444wxefvll57wOKdmS+++/n2OOOQYhBLt37+7NbXcNL0/DRxqWnmOeyqxfT+N/3ELCyWHpCbbdcCOtTz6pLpFIen6HfVEav172a25+42YAzN2qrH9k7BiwbY/QzJ1qfU/MU2Vh9UlHQhqWLbH71Q64d7B85imPGH2kgekojf1CGs41+tM85UZPGXFm/b2OW/78Yb9da38gII1u4Jmn9kFpSCm54ooruPzyy6mrq6Ouro5UKuXlNrj+g/5ytO+NeUpKSWtrK++//z5tbW1s3rxZmac0tf37N97IihUrqKurY9q0aXzhC1/Ancvkxz/+MU1NTaxatYpVq1bx4osvEo+rkZzbiVlS8tnPfpa///3vHHXUUX18w4Wl0Q3byFEabsZxT1WCtG1kMomdUJ2L5UROqXPsHWkYlsFbjW+RMlNkrAxSNyAUIuTMmSLTaaRhZM1gXZBG2rCIRTQ0TYUVR5waY4Z94JmoXJ9GPG2yu1MRu2FlC4N65qn9SRr9qPT9eRop3WR3fHDnoASk0R2k4wgvEj3VGG9kd6r7EfLChQuJxWJ8+9vfBiAUCjFr1iyeeOIJlaznmY8k06ZN46WXsuW4rrnmGubNm0d9fT1nnXUWkydPZvLkyV6Wtx+PPfYYM2fO9JYvvvhiFi1ahC3hnX8s5MqLvsDkyZP5+te/7iUJ3nXXXbzwwgu7OEQYAAAgAElEQVS+280yy9y5c7nkkku8UidKaRTe37Rp07jgggt4+umnSSaTPPLII/zmN7+hrKwMgJEjR3LVVVcBuWapUyZNYty4cd0+v16jiHnK7wg3bVN10JDj92h95hka/+M/ip5SOnkDrtPbzdEA1blv3Bnni7/+B62J7vMLnl77NNe+ci3/3PFP4oYi07geR5oGIhxGxMq9a5ktLR7b55DGy7fCGz/1FlOG5ZmmAKIuaRyAJiq/P8t1hucqDfWb2Jn9kKuxj+aphpt/QOszz5TcLqXEkhbVScl3fraSquYGOtLmoK0LBgehI3zHT39KZm3PS6NnrAyWtEkLDSlttvgKjiXNJJoIYU48hcPvuKPkOVavXs1pp52Ws66mpoZx48axceNGDq9V1WttaTN9+nTmzJnDRRddhK7rvP766/zud79DSslrr71GLBajrq6OGTNm9HgGvF27d/HI//6SPz77ApOOPpz77ruPX//619x1113cc889Ofv6TVjPzHmGu39yNyNHjuTKK6/k5ksvRYRchsvtjCZPnsy6devYuHEjY8eO9ebXyIffWmLZUKTo7r4jL0/DljamNHMc4a5/QPr8NKkVH5JYurToKd1Rr2uKylcaqxo72Lizk617kgyt7Np5u3L3SpbsWMLm9s3eurgep9wwEJEIWkyRrUynsNp8oaCmzxG+eTFUZotnpvRc0oiEFLsbpg1lXTZnv8PfYX68K8Gnjx6Gbute8qV07rMrH07fNWbflEbi7bfRyqIMdYqN5sM1TR3WBiN36gxrqoeyY2lLGQyvOsB+mB7ioCONfUH+mK2nY7hSJcTzfQxSSr785S9z0003kclkWLBgAWeffTbl5eW0t7czc+ZMVqxYQSgUYsOGDT1u9/IlS9hUt54Zl15AWVhD1/Wsn6IEdu/czccbP+bMM89ECEE4HGb1hg2cPMGZOyNPdfXUH+NXGv3mDM+rPeWaPXIc4c6oXZo+575lefb0glM6pOGas8yWbOkVmc4QT7vX6n4EmXZGt7tSu6gIV5A0k3TqnZSbJiISySqNdBrDiZyCPKWR7oDYId5iyrAoj2ZJI+wpjV6MaPUkfPw6nHBJz4/ZC5i2JKQJwprIKg3LyJKGa55aswCOORpChXPY9F1j9j7kVto2dmdnlyHXLmmEnZ8hnE5CGbQl9aKk8Xbj25ww7AQOjR3a6/bsLxx0pNGVIiiGbfFtZMwMsXCMpJnkqKHHAmr0urZlLbFoFYfXdG2TnzBhAvPmzctZ19HRQXNzM8cddxxtlhpNSiSxWIxzzz2XV155hTlz5jBjxgwAZs2axciRI/nwww+xbZtYrLDEealy6baUTD3rXGY99EeOP7y4AnDhmqcW/GUBra2tjB8/3mvvn19+mZMnOuavvA7/gw8+YMqUKRxzzDFs3bqVeDxOdXV1wfn9jtl+C7u1c/M0dFv9WxYqQyCwbMszN/nNU9I0csOKffCUhvNMzRZlltSqqrAzaeIZZ17uHkyxmrbSHF55OLql8+XxX+aptU8R1+MMN5R5SiuPedcyS5FGJp6TvJjOIw3XPNWrXI21L8L86+D7H8HQPvYz+WDZkkhIcMSQcpqcygCGbWT9aS5pvHYvnFALx1/Ub23ZF6VhJ1MgZZd1wtzIqWrKgU7C6QQMgT2JQv9UXI9z/d+vZ+apM7nu5Ot63Z79hcCn0Q2klCAoiJ5yX4aejLDPO+88kskkTzzxhDrWsrjllluYOXMm5eXlBWGu06dP549//CNvvvmmVw22vb2dUaNGoWkaf/rTn7CswhHxuHHjWLFiBbZts23bNpYsWQLApNNOZ8Wyf1K/6WNAVbZ1lcrtt9/O/Pnzc+8XeHn+y/zlr3+hvr6e+vp6lr7zDnMXLEAI1zyV7YzmzZvHq6++yowZM6ioqODaa6/lpptuQnc65qamJp50oo78Jvb+Uxq5pdENR3FEQ1FCWqik0sA0c01APkhPaTjmqZY9aDU1aNXVyHSGznQvSMNMc2TVkSy6ahFfq1UFJDuMDqRuOEpDkYadSnuRU+AjDSkh05Hjs0nmm6fCjnmqNz6NjJOxnOrfkFDTloQ1jXBIYFkSKWXODJmeT8MS/d6WfVEablCETJYmDTdHoyZUCUDYecatyULTW317PRJJR+bAzhwfUNIQQnxJCLFeCLFRCHFbke3/IYRYI4T4SAjxuhCi/4Y/XbWzSEa4Kzu7i6gydu7E2LqV5557jrlz51JbW8uwYcPQNI0777wzZ1+3w77gggtYvHgxX/ziF70CgzfccAOPP/44U6dOZcOGDVRWVhZc63Of+xzjx4/npJNO4oc//CGTJ08G4NBhw7nn1w/wwxuu5eSTT2bq1KmsW6f8OitXrsyZEVAiadzaSFNDE1POmOKtH3/UUVRXVbHkQ1WR9/89+LAXcvvkk0+ycOFCRoxQNvZ7772XESNGcOKJJzJx4kQuv/xyb5stJSOTrQxNx3ng/t8wevRoGhoaOPnkk/nOd77T3U/RM+T5NAyHPKJalJAI5SgN6Vcahom0Lab/dTpLd+T6Nux8pbGnhfCwYWhlZchMmk5HaWRKmLceWLSRW+d+BCjSiIVjCCGojio11ql3Klt+JIxW7pqnUkppRCJO+xzS0BOAzKmtlTIsYjk+jVzz1F82/oXv/r30dL/qptzw0951Wk/9cws3Pv1+j/e3HPOUJgSWlF50kSUtDFPPOv7tIm0xdXj487D5zV61sXRjnM47P/HOu87iwmMANr+J/agi/K6i59zB5RCHNCIOORULmKjvqAcgYar8la3XXUe7Mz3BgYQBM08JIULAb4HzgQZgqRDiBSnlGt9uHwBTpJRJIcT1wM+BafuznaUywj3S6Ga0bCeT2J2dHHHEEV6U0jvvvMOMGTNYvnw5p512WlZpOKG3kUiElpaWnPPU1tby0Ucfecv/8z//Ayh1sWrVKq+NTz1VONvZ5t0JPv25s5nztzeYcOSQnG2GYeT4NySSsUeNZeHKhbmEKCXvPvsskQqLycdN4r9+cgfhkaOL3nM0Gi1Ztt2WkgozjRaK8m/X38itPywerbRPKOHTiIQihEQIU5rZDtifsGiaSNNidctqVu5eyemHn57d5kTyuORh7W4hNOxQ7EQSO5X2lEamhNJ4Y91OdjqhlmkrzeEhRdQuacT1uMqAjkQQZa4jXJmnIqNGYWzdms0IdztSn9JI6RYjfDZylzRc5fNq/assaVrS9XMznRFzLyOJPtjaxpsbdnW/owPDsomEBCFNYNvSI3UAPZOdfElaorAtqVbY/j40fQjjz+pVO4vCrzSkxAsPTO1R12lYCuPPLjxu+wfY29cBI7BTXZinnH6iRlNzzJQ5ta72FFEabmBEwlD7JN5+h+hR4xhySf/6mHqLgVQaZwAbpZSbpJQ68AxwmX8HKeUbUkr3LXoPKN5L9TM8pVHMPNWdO9yR2mZzsxcV8tnPfpYtW7ZkI6q8gKT+Mde4foRi3dkrr+SW3FZNEM7+dt56b1NuHapetQWElAgp+6rSepGL5IbcuqQR1ZR5ypZ2VmkYfp+G6RFOToZ+Yjdys5rfJKs09hA+1Kc0EmnObPwQvUTJ98bWlFeoL2WmvEiuinAFmtCckFsTEYlmlUbKIY0jj3Da6nSubkfqJw3DJB5anlVVPqUhpWR1y2oM2+g6F8jYu/BT07JJ6FaP319XaYQ0pTT8pJHW80kjT2l4Jqw+qpLsqitp5Z7TcIggXVx1pdMJLF09Y9kFabgqqlqo37TMub+2ZKFPw1UaSSOpfusDdDKqgSSNI4FtvuUGZ10pXAu8XGyDEOI6IcQyIcQyN8Gsr+CVERHKPOV+GD1VGtKyEGVlSMvCKjERU77S6Gtkk/tkt+21bBvTdkgjp4NxFFfIEad7mYhoS4lA/fW/T8PxM9hZpREWYZWn4fo0cpSGoeKApcwtY738j9ivqNBkT2m0thIaOhQRi2GnM4xat5w7l/6J8Aa/UFYwLJsdHWnShnpmGStDWUipAtdE5SmNcBjN8WnITBpz1y4iR5QijSzhJdnKKvN+3ml8x7nXbJ7GjsQO9qRVtJdudRHGupc5C6ataomVUlnF9g9rmjJPFSiNbAds20WURl6Qwz7DTxR+v4a7Pt1e9LANDbuwTec76QFpVGrqN43p6rx7ujBPdRqdWXPo/ppXpBcYSNIokiZWfNguhPgXYArwi2LbpZQPSymnSCmnuLbzIvvsVSP9GeH+5Z76NKRloTnmhlIp2f4s7P6AP0ipuytIJEjNOa5IVVs3/HFvScOWaFKi0bPoqV4/EykLlEaOT8N1hBeJnsJRHUJmTQQApNuRjkPZHVXaySRaZaVSGuk0objqXCLbCudz39GexpZZf0faTHvhvwBVkSrihpPcF4kgXKXR2YnV1kZkpDJlZUmj0DyVtlTn6pbfdvM0TMtmdctqbz8vga4YuukoSx7mPBvXr9Md/ErDljKHyAw924kXNU+5fpy+VhqQ69fo5llYegrbcEijK5+G009EbfVNlevqem155inLttjSrt6dpOErUaMHSsOPBmCMb3k0UDDLjBDii8CdwKVSyr16grFYjJaWlr3ulAXZ4m/ePNM9UBrStlUWddgdnXfj/+inMiL+Nnb7CKTE5fOce/NIw7mXvTZPqeME3ddFklLS0tJSNLy49EFuu4TqVH2dUjQURROacoQXy9NwzIchO888pSdVB4ZSGtKykOk0WkUForwcO5NBcyJpotv94lmhoVURTdpQpiLXEe6iJlqjHOGu0nAGGW4Bw/CI4RAKZUnDNZn4HOGGY8VNmSnsRIKqmd/mmLYG9DzS6FJpFDFPNf/Pz9j1v78p2LXlD4/S9OO7ADCd3zTRQ9IwLJtwSBAqojQyOeYpCs1Dnnkqex+vrWnmyt+9s3dZ1n7S8CsN71kUN09JI41tZM1TpUK1XTN2VKoghXJnsJKvNJoSTV6CY8JIeES032Yw7AUGMk9jKVArhBgPNALTgW/4dxBCnAo8BHxJSrmz8BQ9gxuhszemq92p3UplyAgZuxNrhyQSCtGeaSdhJFQ0TnNxO7a0LMzmZrRkEjseJ5RKo7lzbPuwJ72HtJkmGU2yM7rXt1kSTe0pz38Qao959YmKYUeiGdsKgWbQGe1kd1TlI9jpFNaeVkLJGFY8jdYeItTZ+ykyW+Jp2uJ7sLQQic4U8eaus6djsRijR/fCleV2pJFyMJJgW17IbURT5im/0siJnnJIQ8tXGkaWNDBNbKeOllZRoZRGKkU4qfYv29FQ0KTGtqz5IqFnVHZ6KEsafvOUVhVDRCIQDqM3NgIQGjYMEYl41V/zfRqmZWOJJBEUaRjNzWib6jimpgHDkjnzo3etNAod4cllyxDRKCNu+l7Orslly9A3bVKH2b1XGmFNoGlq7GH4yE83Ut5I1i6qNAp9Gqsa21m2pZWPdyU47vDC3KAukaM0/OYp16dRXGkIM4VlZL8jmcl4CjHn9E7IbdQx+VY4xJ/v03BNU+OGjKMj0+FTGgFpeJBSmkKImcArQAh4VEq5WghxD7BMSvkCyhxVBfzZyajeKqW8tLfXikQiXpJabzHjrzM4JHYImfYTWNr5CM986SVOGDmGWxffykubX2JI2RDemv5W0WPTa9ey+caZjPrve2m68z857LZbGXbNNQX7fe/177GoYRE3TrqR757QTVhkCWzp2EKn0cmEYRMKtl151wJsqcIyl9xxHofVlB65X/vkTPa0HEm4ei1fP+5yfvI5FRYcf+EZGn70X4y79xrq//Mxhp9zGCMe+keXbYovWoT+8SYiow6n5iKVoPWdX73ELY/cQtvQw3nkOz/jT9eeslf3WxKuacolDUv3fBrF8jRyoqccAtFsvJpQAOiJnJluzT0qd0CrqFA+jUyGUEqNkCuaGwua1NiaJY32tNrPrzSqIlVs69wGhlCEAWixGIZDGmGXNEo4wtOmDZrqZFIdjchdKwAoNzPoTjRYdaSauBH3nkVReCG32XuXloXdUTjatlOpbBVeR4UnMrmDpz0JndXb2zmrNtdkrDLCNUKawLDsHKVh6Gmv6onM82ls79xOc8taTgV2GnG27FjK6Yef7imdjxraipNG4/sQGwLDPlXkntNQNgQy7Xk+DedZlDLVmRlPaYAyUWlFSMNVGhHHPOWSRn70VH17PQAThk3g9a2ve5UH5P6ov9VLDGiehpTyJSnlsVLKT0kp/9tZd5dDGEgpvyilHCmlnOT89Zow9hWWtAiJEBlnVJF2ZHG7rl4mo4sJ6d26QeHhw50VxRWJOxrpchTYDf73/f/lrrfvKlgvpSRlWNSUq/FBdxnCljSRhJB2lO0d2bpHMqE6SlGt7kXqXduUpZQ03vR9dv7iFzT+xy1YTsdjJtVxEdvs8ci0V/BIo8JZziaNRbSIl6fhyv6c5D4ja57KVRop1YE5cOtOaZUVaLEy7HSacidUtGL3Dk+xuGhozZpc4s5+pZSGiKjfSZTHvEmZQoceWpw0pAW2TUq3ECFFTMl1LyJfV4UMy80MDYlNxPU4k0eqnJ2uzVOu0siShDQNrPbCjlOmUt59ljJPzV6ylasfXeJFjbnwlIZjnvITmW5kCTbfp/Hghw/yw9UPAvCn9FZufP1GNa+JQ1orG0t08H+5Ad747+LbzAxUDnMu7hsodBM9pZlpz6cBIJPJovtly4iofcssi0OigvaUkePTa0o0EQvFGFs9lpSZwnIGIQei0ggywrtBljTUcsYhjbjzMvtHSQXHtqqONuw450vNvOaORtL74Nxr19tJmYVRHLplY0uoiakRbHcZy7a00NDAjtLc6RtxOiNkEasCTUA3Djq7sxOp60SdKrZuKXLT+RjClkk83R+k4XRQEWfUZxm+MNQoYS2cmxFewjyV49Pwm6fAm3xJq6xElMWQ6QyVzm+nWSZGQ66Jym+eandKTviVhkcaTu0pAC1W7jndw8OHI8LhQkc4gG0o0nCVRmcTdkoRXszUWd2mQoXPG3ueOrQnjnC/Sci0sNvbC3x3xZRG/iAgkTGxJezuzL2mYdk5jnD/wMvwzU2ilEb2XnemdtLmkHmrlSFlppQ5zrn+Rw0lSCMT70IxpKHCGdT1InpKs9JYeUqj6OmdQUzEN+g4KqZchO0pX6ixmaYiUkGFM9hJJdV1g5DbQQjLtghpIdIeaaj/eErDNoo6w3ckdvDAP+4DIOQojfwRqAvXAe4fBTb8oOuSy/lIGsmiBOaGedaUq86ou7ISFhbRUJSIFqM15XcGq49ClFUhQgJpZHjyvS3cNPuD4udxCDNyxCjAV4bDKe4WtkwvIa5P4SoNt1O29BxHeEiEnNLouSUrwEca+UpDTyj7ugPLZ57SymNgmQzJJEg7kWWZzdnqtaBIw41mijvJXfmO8ISRUJ2wEzThVrq1QmHmrN6jyKQYaVg6KcNChBzSEMJ71uVWhnUd73Hy8JMZXa38Qv537MbXb+Rvm/6WPZdZ6PyVliLY/FwE25nrA8CwJWHbZNQdN5JYkk0gHPbhP7nvzQe47a2beGlTtty/W3uqmCPcMLKdpG2hOnzn+9qT2oMuTTIC4lId05ppxXKUzpqmjuIFGs2Uk0UPv1j6C3674re+bRmodEgjZ6CQyh5rFo72Q7buhdyCU4eqCFzSCPuaNTqqFvzO8LSVpixURmVEZY6nOp16dPuj0m8vEZBGN3CVRlpXL0jKeYH89WFc85IfCzYvIL1HOZHDQ4eCpmUdmXlwj09b2dFK8p13iS9c2ON2JoxEUVOZaxoYUt4zpSGlRVgLEdHKyPg6GKk7H0WsEhHSkHqG5Vta+fvaQsc++ExzTrioa6N1i7uFrf1knvIpjYgWUdFTparc+pRG2kpnO7M8pWG1OkqjogJRpjr/oZkO6g5RwYD65vpsc2zJ9rYURw1TnUHcyUPICbmNqkmXLD3jKQ230m1bWRXLtrQ65ik3I9ynBCxDkYamzpsSwiPEcitBU3oD5445l2hIBRz4lcY729/hvab3sucqEj3lPhMrz68hfUrDsm2q9SSVH68j9cEKb5+hG1dzcssm1jS/x4e7srPVuVVuNa0YaeSF3EpL+aaAlrQyC8Y1jbjzzbSl2zAcM49u2mxoLpJjYqQ8Qli6Y6k3va5qfAYqDi2479yoqkITVdhOY+ualzggSxQtdM1TEd/7c4RDGv6w27SZSxqZpDNpWeDTGHywpFIaKee3y1hKWXToHUQ0d/Re2Fm/se0NapISu1JFw4hwuGQxPNc81djeQXNHNtTO63wa34c9m7psZ8JIZD++1i2wVXUG7jSgNbGe+TRsLMJamLCIYEkfaTgjQFFeiQiFwDTRdZ2kbpHUC+/LM80dPlIdn1FzXkuHPDTToDNj5oTdZj7+mPT69V22r1t4pOEqDSMnIzyshZ3aU6XNUyHnESWc0ak/5BayZdGVI1wpgkPTcXZUHEqqohrdpzR2xjMYluSYEYoYOo3iPg11fSPHEQ7QVlZNQjeL+zSc+0vpFlrICbnVNG+/ClQne+6Yc4lquaQhnZpPu5K+iEKziB3fJY33/5ITZp1vngo777DVkTXnhDvVeaImOaZTyy1Y6JKG7/sxfWZP75ln4kgpvQTFuKbR6XTGbZk2TMfcBUVMVFIq0nBMTxkrQ3vGt4+ZhmgVhMvzSMNHAkVMVGFHaWgVIe95FIP7bYd8n93IkHqmfqWRsVQlbY80EqotgU9jEMKyldJIuYElpkHCSGBJy6t5n28Wak23smLXCqpSYFWrEa+ySXdtnvpnfTOPv1OvOtdMBqOxUTls/3J9zixtxZBjnnrr1/CnK8BIk9oLpRHRwoS0CJb0l+JWH4Uoq4JwCGmDcEZgLZ2FL7arNCKHZ81TGdMm4ig1zbbQpE3CRzjN//MzdvzXPQXn6hWKOcLtXPNUTnJfjiPccNqmFr2scCOZEz1l7cmShuYojahtkoiU037ICC+/AmCXU2/qqGGqPQnHzFcWztaJ8kjDMBBhR2k45dFbyypJ6lYXpKGTNizKNNXWVKzGM6WVyzaqwyM55pBjvAx0t4N2R8A7U74Qb7/ScKsIOMEb1l9/DA1Z05OdTqt5zC1LZXg75/M7zaOJLGn4/XVuJ68VKSOSozTsLGnEjXh22lRNo8O5XmumFdOSHF4ToyIaoq45r+qCpQPSM09lrAytaV/lXDMDoSiUVeWZp3w+iiKkEZE6liEIVbhZ4SV8Go4iCvnen0OFut8On3nWNU9VhNV7ojum4cCnMQjhmqcSuvqIMqbuZd0OL1e20HzSeLPxTWxpU50Cs8bpvCKRkj6NrHnLMdmYphrV2TbGli1qlNRFlq6UkoTpUxqZTjASsHmxZ57K+jRKk4aUEiksIqEwYRHFJntfrtIgVoUIhZBSEHbCUvMdnQCm69NwlIadzpDULWI+k1ckzxlutbUVjdTpFYr4NLw8jVCksDS6VWie8pSG69cwkjnRU6bPPOXOfQFglFeQjsQ8pz+AbuU+/4ReRGlEXNLwOcIdMmqNVqmopEi4MLnPub+UYSFD6jdIhkLeCL3cSnJU7HSEEAXmKbcDzlUaTsdnG555xn0mtq55Ha/UdU+BSFNNXeoqDbs927Zo0kl4zFMaps+nkV+w0MzPCAfIdNCSyhbwjGsacaF+pPZMO6YtiYY1hlZEaUvlDWBc34SPNOK6Q0BSqnsOx5TaKOYIh6LfXlSqkNtQuWqHnSoRPeUqDd935wZN+Adw7pw9rtLwSCNQGoMD0rbZ8q1/Jb5okepgpMA03UltTE/eDitXoXruB+hiccNiysPlVKckRrWyTYtwuCRpuC8WmkHGsHPsmJlNm9ULrBd/KUGNUmxpKwev+yEArP+bpzR6Ej3lKp6wFiasRZD4TDe6a56qVqNeG0JOiGJJpREKZYMAMmkSGZMynykiP+zWjsexE4mCc/UKBT4N08u0DYuwSu4rVRrd59MAR2nYqpCdtISKGiPXES782epVVWTC0RxThVuPqdoxDybMQp+GqzQwTa96gKs02sqqiiuNcDY6LKVb2Jq6n5QQXmcbMyRHRlV5e1dp5JPGkRv2sOnrX1fKwUxnz+uomUxandfShfds/ZFC0jAw/OYpH+mX+ZRGyso+k5TYwir+CykyBUrDcv1+WjYQjnSHZ5oCxzzl/L813Ypp24Q1wZDyCB2pPFOxSxpGAmybjJlRc1bovvlIwmVQVoXe0cZrZ17Aytff7ZI0LFsSlTq2IQiXOeRZInrKVXTCsnHHHZWOivEP4DJWhlgoSxpm0kfQwPef+YCn/7m16DX2NwLSKAKZyZBcupTU8vexpY1tC6RTBiBjGZ7SGBZTpJHv0/i47WNOOPQEqlNgVKuPX5FGCUe483UIYZA2rZyICX3zZjXqM0p3pv5IH9M2s0689QtIO7Z7N0+jK6XhZa+GwkS1KLaPNHB9GpGoMqFIQaQLpWG1thEaMiRbsTWjlEY0jzRcnwuAlUj0HWlEXdJQSiOiRRBCENLySqM75im35Av4zFN6p+eEtS1ByOn4zT0tEIkgolGvjDmAqK4mEy7LGXW60WouaaScDiM/5BYpEaaVE3IL0Batyvo03EFHJg4Vw7z7S+g6dkjdTwqpCv0BMV0wNKRmmnSVhuvfcUnj6B2QWbmK9OrVqoOtchLxMh3Ytsyap3TNy7b3k6I0VL5BxJ0Tw+cwjzmj5aiRa55Ka9tIsAWdFmw7N6LLdN4zLRLKMU/5SaM5FPI64LZMmyKtkMaQ8khOGKs6oc/XYCQ90mzLtGWJIRyDaDWd2/cwevc2Gt98zyGbrNLxI2VYRE0TEETKnJL5paKnnG9KMy3iDh+X6YVKI2WmlHnKGey4oenSULNJ/mPDLpZt2cOBgIA0isAfMWLapqr6Kl2lYXRpnpJS0pRoYkz1GKpToDtzHChHePHkvk5XWQiTtJFbDnnr6ve6VRp+0jBsI/sxdO4g2qwmTfJ8Gl2QhlcnRwsT0aKQY6WOvUkAACAASURBVJ5yR2VhCCulETUdn4a/js7av8I792NtXUto6FCvjpJMZ0johUrDXxnV7uzETiT2rXCj03ltbnfn1FAZ4W6n6dWe8pSGs59PBfqVxrsNb9KmaUhLECp3SaMVrUJ93JpPaWhV1aRD0ZyZ3AxXaZSp53/YinVEDFlAGq5JTEQd0nB9GrFqkhmf0nBn7XMjfmyDDp9ZJYXtjdBjegjLUoOdAqXhdGYR57bTH30ESKjMksaWPUlCto80nPfcH34rdUON9PMc4dKyiDm5PREr1zxlO74yW6QLoqdMZ8CjRQXSdgpWZOI55qnt4WwhC9cRHtYEU+WHhDp3kAOfb8LOZDPi29Jt2VBaR2m4AxZ7104nf8Mh5jylkUwbRJ0BYLTMCVwpFT3lDghNm1SZhiWgzIlE1POVhs88ZaVziTmpW9lvZfsH3QbG9CcC0igCjzTa27GljWUJkO5I3fASvw4pO0St8730HXoHCSPB+IrRlOtZ0iAcKmmeSjmj3mhEvRh+0ti2+j2ahO2NeIuhgDQsHYYfB0DlbhUC2RPzlJcEF44Q0SJIUcQ8FQqpDkxCxFJt8pSGqcOz34JX78T6eCmhIUO8kbidSZPMWJT5fRq25VV+lYahJL5tl5T6PYLzkT6/2nF2OhnhLmmERVjNp+GF3Lr/Zu/V7cB3JHbw3bduZ05NFdISaDE18hSWBY6CckNuAeyKSlKhSM5I3FV21bEwhyX28KU/vMwZG2SOT6MyUknY6eg985SjNNrLXKURVW3WOwHpUxoGbc5I+FDLIiUt2lBEEdOld/1SSiNiKoZMrXIm+Ko8TP2bifPRtlZCboFOPWsvyklkMw0VQutua1MdrNXRgebUVI4aMkdpuAEWUqRzzFNhLYzlkLkW1bAdde9XGiEE28PZGQrbMm3KER8SfLf5J/xn4qfk1nzJ/ha6zwFeqDQqsRNOsEfLbrWtcjggCkkjlfRKiITLbPU9lHKEexWXLawQJKNhIg6Z5vg0nHL5sVAMTWg5JGSm0uimTcbJuWL+9bCwRIb7fkBAGkXgdih2R7uagtIC6TyqjC+E042v95NGU6IJgKOk+qjTVepjFeHSjnAbZzSiGaQNy6ulb9ZUcMQeaBdalxPfF1UaTqdiOaOpmp4oDTemXAurkakws6UOnPOIUEiZ2myBdFTDbtenYaZVldmqkVgZjdCQas/mLzM6Cd0k5jPRRSzT+xD8Zql9MlE5H2laOoUQnTwNNzzaM0/lRU/5f5uYUPuublmNjU2LFsK2IVTmKxvhdOp+R7hVWUUyFMVOJj21pHukEaHC6aRipvDaA6qzLHPKwGXNU4psW8uqVYKmW+XWjZxyE9IsnbjjWxppWujSIuXUOSqzLEwnYk8TGmEt7I20vQGCqzRWO/OAeOapOCu3ZjtZWxdZ81QydxRsWpKI8+7YSTWBkBty7V4jR2k4Zk+LtHKEO+etilRhutF1YZDOfbikcUjZIVRrUZocYo2FYrSl2zAtSZmQlNkpJso6WP6Ydy2/0siks2VxFGk4g51wGWgRbKd2VqRtjzouUg6xmoJSIslkwkvs08ISESsrHXLr+jQMCyskSEVCaKkkkZDIMRX7pwCuDFd6eU0AKed5e1MJp9u67A/6GwFpFIOnNDqwbMtRGmp0o/uSxdzwOD9pNHaqInOjDLUtXemEUBZxhEvLYsu3/pWJdY79EkOVz3bMValxI6lKQ9rQujRPJX0q5F/+8DbpVFKFEAK2SxqO0nDNJYl33mHztGk50RnuqKgsHKUsFEVoJmmn05GG4b0tIhwBO2vaaXGVhqsiYoco0qipypqnMmmSupmnNEzSzofgn6CqL0gj5ZS9S360novuXMCwpGq8N0d4XvSU/7ep1ioJiRArdyvTXltImae0iMTWnLlGygqVhqysIqlFlVpynqs7mqwqCxN12lYulX/Fj0q3TJ+bEe6Yv9qc39EKhXNJo9wxT1k6nQ5pHObcS0r6ylv4/CtlobICR7ircPQt21TVVp/SWLMta0PPMU/lmU4MX/QUKJWRTxrJEuapT9mb0Zc8hEBQEa7AdsOeIyqvj3A5erKNF1etpzJ8CNUi7JmnRlePViG3tk2FcCbHkgL5+n9lCcFXyyrjUwyt6Vaf0igDLeyRRqx9TzYoIDakQGlkUklv1j4tItFi0ZLmKfc5C8vCDAmSUUUa0ZDmvRtSSs8RDii/hk/NpTpd0nBIRk/kJh86+Pc/LeMbj7xXsL6vEZBGEfjNU0ppZEnD8MX9u04rvyO8qVMpjWGW6lTS5eq4Yo5wo7GR5NKljG90nGnCUOYpxxSUGeoQjxVSmat+2e2DX2msb27DyKRUCCFgOY7F/IKFHa++SvrDj3KiXdwSKWXhMGWOOSPuziBm6gi3pHokjJQCabtKwzVPOfuW1WDqGuGaStUJahp2Ws1cF7WzL3vU9imNPiKNlNPeNFFsC5p+N49DdnRybL1qa/4kTG70lD+HJirCVEYq2ZFQ9vG2kIa0Q2iaieE8F9MhC1cRAIiqKpKOgnDDbl1HeDSsUekoypgsLC5djqNIHaVR85WvoP3oTlpjNQBYmvP+uKThM08lTPXsRjjvras01IPIdj5lobIC85SrNJCSdGsEqhRp2Kl21jVmO/7uHOE5pNHe4eXpgPKbpIspDZnmEvkGRrKFiBYiGop6ylgLS6QpIVZDor2VDqONsKyhSoSJO7MSjqk6kvZMO7plUyXUfa6TYxHpdkg51/ddN+NL6mvPtPuURgxCYaSu3sXKTodQIjFVATePNNLpzqzSiNho0UiOH8sPT2mYFrYmSEU1RCJBJKx536Jpm1jS8vxOlZFK8A3mMk6Rz4xhKZ+W3glFCk92pMwuA136CgFp5KO9AbnpbcAZMUkL3SRLGpbhkYSrNN7b3OyZI7YntlMeLqcirZb9pEFecl/GmY8g6nScSmlkTSdmmepc0tLprPUinamUJLa96y0KYaFZGYgqh5ptGkRCgvKo236nXSvVHAt2KqVGYxteIemM8mKhiJd85pa9wDQ80hChsEruczoeL+TWGcXaWjXYglB1hZoqN6aK+ummTczOdmJ+R3h3pCGl5I2tb3hBCG/V7S6Y/Qyg/s0V6J0hUjLKnnVV6Nt3Yws4qtGxm+dN9+oFJ/gIPUqIqkiVt9ymhbBtDSH+f/bePNi29Czv+33DGvZ0zrlzj+pWqyWDBAhkCTs42JgklBQPUMRmiE2wK4XLjh3iKjsOxLET49mJQ4ZKbMcxJB4oBjsyCmZSCRBi1IQk1ELdre6+3X3n8ZyzhzV8U/743rX2PrevDDE0Usmsqlt3Oufstdde63u+53ne93kDTprvfClVcbslt9MtaAxm8egpWM1cegsm9wGN2Qga4r2cPYt/+x8Y/9+P8pRIJYMRHhwbAY2BaXQ7oKF2ekZKU76CaRQeujrfG6s7Je91mV3cuXObvttek8w0pOR2R7+PfZ/7LnbKzuPx0SuYRkhhZORD/0+k5SvSB3EKCpUl0egHppGIIUG1ILRHvO3FWyzinD21vXaPTh+gCx0+dsx1fl93k3xuQ1yKa2nuFPRLcwI07nZ3t18jTGMAjdp1hHUDtsa5GetnT0bl9M1mTLg1RUJVRfZ5rvwS3H7uxNeO5fQ+4I1mXRpYryiNHu+NIT5oKI6YFTPYufbNABo+biXg+zCNPkRK++ov6b8FGrtHDPB9f5T0rv8i/3W5RMWED4wltwPTUKix1v5//olP8uyN/OBeXV3lwdmD46CeZiKXuHilPDXEhJT9jrbputHTcANoDB/T/czw6x9n86Hv3v5dBXTssx6rC2Jw1NZQyu6s85HY97TPPJPfY9PCr/y/8D1fx+ZOnjpXFQUTAY2VlAcm58c+hWyEKwyRymrubPrsfQzdxiGDqZnln6GritRn0Kh2so+K4EeddleeCvcBjXe/+G6+9Se/lR967ofofeSbv/v9fNfPnAwGbJ95hvSd/xe3Pr6gpeTuc1Nmb36C669Z8MhlqcpROhvh91RP7X42BYaZgC7AXZGnlPK0WhhbuX1vAK6oKKqClfghw258kCAKo5jJDruKWyN3OKbsVNnJsRsu6ZWB3m0b0Can5GL1NAIaF+Ra9juNiGpHNin1K0GjjprDPUPx4DlevjPhzzz3PVwra46P7mCG6ZRKmvvCK+WpICXds523FI6OTjCN0TcROWjw8Ep/jUfVDZxSFMpk0BjkKRshJFIxx12/w7f/y0Pe/Ik1C7Vdsh6Z5sbRLi6Zkn/2IdLzMo6Fbbj0vtPc+Nge3U6V2SuMcF2Q+p3rfbQBW3Pnl1pe+t5rJ95P327ol5aowFQRXegsA37vH4Wf+pvsHgPTwAeiUbSlgmZDYfS4YRo+k4FpTIsput+CRrfZkaeGjeN90opdiONs+Ffz+C3Q2D0++F1w5ZdIg3aYEtMug34hi4WLfjRWC0k1VSqMnc2XV5d5cP4gcZlv0I2Yp/czwoeMosptb9Y2dKOn4ar8JP5rmUa/Ya13PkYVMLHP0QgmT3urS4NSajTfuqefGSMzUrMZf267yQ9GZezINEbQ8A4lN6QqsqdREHj41ISUJEdHdj8h5B2TmctuvKqIbUcfMmisRdEpoh9TeIfrBa9kGmu35m9/ICcG3+3u0vpAiGkEashM5Np3fAcqRrpji/cav7FMn3yQq49OeeDShhRjrtAJfsfT2HY2D0eV7NilDXCkNSnkPppGmERfVOO18ErTTWaUVrO+R54aJIjCaKayWFbplaAxodheWzl2q2ucEqYxyBLVdnFspYrtnACg/3SgYcqtPCUlt4tU0+rA/K1vor5sKV1iVc1R/RIzZE2VEJwi+Vf2JPihD2h72rlU/e5dgizwA2gMZngSpjFrX5D3pii1pTTlyDSUlLAlO8ctM7uadYa5LFlVjJwvs3TnWDEj/+yRaci96G7cwjeG0Gk68X600lJyKwvv8KzsqMfuuINigl8nSLB63/u2/9duWF2puX72DNomdKFJqyUcXzrhoeTPQt689wStcSYHSlZWb1m/v4dp2Bm68+MkwHZXnhoM8Psk7/Y+jpvDV/P4jIKGUurtSqmnlVKfUkp9233+/3crpT6slPJKqT/0qp7M6ga856/C418O9anxn+dtVpVOTfMH6mKWp0pTjiFwqJA/UHL11EOzhwhyo2+GL7mPET6ARukjKuVFqA/t6GmMoMG/BjRCz3pnfKsaQEN2T4SeSZF/zmC+tU9tx3/mDCGpOJIBQZOiZCqL4nqYbxD8CBrYgWkEHj7IN/btdTcuaMFJpdJUTN2qIrUtnQtU0bEWRaeI/cg04vqVoHFldYWv/pdfze/9/t/Lzc1NrLJZw5bF9Pmb2+uxes97aD74ITbTKf3SMl3m8y4v7HPpkZqqi/QvvIBRhhj8mK10v+qpwdMAeLTYy13WPqFwdAIK7U52lLMlrp5SGsNa7olhYd2WvGomww77PkxjkgbQ2GUaO6AhQYQXN9f5Qw89wJGUsxJ6urSiTIaFLPIxKry8hNkBjft5GrNU0JpA8ZYnMUHxhRcTXTVHd8djua2qgKTG97RbcuuFFS/MduMTDo8Idw+5W82JCooh/UQWxyFpoHRXWKcKh6JQ+qQ8JaF+Sc9ZC0Ooe8tCTP55TJwSedizGpnGXU7KU+2nXpLLpOlkwT1bn30F00jKgIN+2Bwe52fIN/l9nUicvnqZ7qjg+UefkM9MEZdSNHBPo++WaXiCUTibe54Ko+nl3huYxmCEz4oZ1gXMIm8MnLDW9ldhGr3/HJenlFIG+N+AdwBvBL5RKfXGe77sJeCPAd/zqp+QKeGL/jD8vv+R9PCXjv88a6HziVPTvDj64Me6/4FpoHIV0MZtOOwOeWj+EPF4SVcqei1G2H2M8O6igIZLI2h0sR/7NLpSJKX0r5GnomO9Q9m16jGErbkX3Agahc06avPxHdBomtFg78ZZDwWTATTcwDQC7DCNFMGqwCOnBDRWO0yjz69npkPMd03sO7oQqUPPSkCjVt2n8TTy+/xb7/9bXF1f5Wtf/7X8nd/9d7gwu8Bxfzx+zwu312NJ8DDD4hNPvo7oNI/cykF85fk5Lz+cF/L24x/HaIPajUP/NPLU4Gl8cXWOYkh50QFn8qKyMdvZ5r0p8JMZVaFprYBGMxjhUeZhqx2m8crHrr6n5BZOlkf3Kvf5PLV6iaerkpf8duRrHzfUyTIRIDQemqlUi3X3N8IHf6GOFmcU/ZMHuDLx1mcTva3At2MIoamlV2O5PvHe8stLuezOWwrHR/i7dzkuZzgLVZ/fU+ObnG8moOFSz4vpgexpoClMQRyiXOS5iapgKV5g7ewgPrGIkQMt0iBLJgIaRyPTkFG4z1+V89R0UjByYXbhFSW3bdQkB3dPZcnLrzzYmrDK72/90+/bRs5/PJcnP/34F+RzNWm76bknUmjLNAJBa7xVpK6nvA/T2JWnTB8x+5lJ9ZKnlZnG+sT72z26z3XQAL4U+FRK6fmUUg98L/DVu1+QUrqYUvoY8OqXBEwO4Pf9XTj3BtJDW9CYN4nOwcO1h6Tw0RHbljc/68dae6UCnYtjj8ZDs4cIqyVtbbYld8XJjvCwXBJu5nkbVZ8w5JU0JocTo7GvpAv9HqbhvOfvvO/78SFA8Gx2mEahTtaep+CoC5EJBqbx4fdjLsg0waYZb/ROdqWZaeTzWQvrSSHkSHTECE8Ku8M0bq26cfczjAUxsnCpqhqN8Cp4NtIkN1HdWD0VVisYylnXa9778nv5yZd/kj/55j/Jt33pt/H2176dvXKP4+54ZBq9j1w5bODizxLv3gStubmXGcLnXX0JSJTnplw5rXClofn4Uxhl0DsFCSOQ74JG0qOn8cX2YOya1ibhBTg3Zss0Om1xkxml0bQCJmnH0xh05kkamMavDTTcjjzVY3LRg7DBVguViB6fNkySYSIAWgboR9A4KU/d62mUIe9+l2HN1cciv/3ZRKctyndoYS62GnwnKQ1vdplGXrxm0kaftCEeH+MENDoLpc/XpPENPibQUuWlIksm9EphhWmM+V9mkA81SwHPqtcsRHrbi5EDYXWBFdOUz2nTl9x5dsqdf/HDuGvXaC7mzUPsNZ1sui5ML3DUHRHk7z/xqWNWPUSnCKfPsrEVYRWhqPGrDjv1xPWa9Qc+AMD8k89Q7Ttun3qQRk9zpdfA6O4JL/XRo1Vmid5ovM15UoVR4308GOGDJDwrZhQ+ovf2832w62mM8+Hvb4RXn+Og8TDw8s7fL8m//f8+lFJ/Qin1QaXUB2/evPmrf8OvcqRzXzD+edbCtaOer/I/QZ0CMTQ8/IvP86f+6R30DaGkKtD6wI1NvkHPT89npjEx2x4Oc1KeGmcuaE3lE3qo09cOL409fZkfkBE05Cb/7g//BP/k+b/K3/vAO0We0sNX7IBGndlTdNQD0zC5zK+/+BK3z0vM9PHt8UYfHqpXMA3fQ0xb0CgsRIUl8uD+ABr91gjfkYphK0/1PlJ5P8pTterHPo24XKEXC9RkQlyveddz7+L85Dzf9MZvGq/ZfrXPUX+0bXICXrx0Cf7xHyS98H7UdMrxPEsWT96+RDELaJNolePowTn9xYsYdZJp3E+eKjC84dQbePLgSV6ryhE0lEkEWazXO815L+4/yPLhxyntFjS28lQap/bVIpoX9wGNSdz28wzHiZgJeVQH0OgHHyv0eBpqDBOpLCo8hMn9mcb9qqechWV3xEuPRA424FYaFfpRnqrElBg6pndLbqMwjanIU3H/YJSnjqoJvYXKi6QXcmyIUvmab1RilSbZ0xAjfPCYRtCImrV0rRdOsxA2NY+RPQHaoDbUwjQeu3KH6x864Po/+H5e/pZvoZW8pujVaISfn54nkcamyD/3zk/yiy8dE72i3ptzu97DN5qkKsKqZe81LShF8+FfIqXE9NI1Zg90YGpumwuo5ipxqHa6pyx+SMlOg6dh82TF0qjx8+38SXlqaqeUDtRcwgvb4TNLhHbwNP7tNMLVff7t3yh0KKX0f6SU3ppSeus5mcf96zu2mvO8hd7DKbWhSJBiR3mYH1yzkQ9OBVoXR6NvWkwJy2O6iR1B415PY/QzXvc6KsfINJTy9LKTG+Sp/h4j/LnbGRh/9up7RZ5S7MvXFGrI0ynBWFT0Y7ltZTWxyzHfm3n++uOjGyPTcG44/5K5lJQ2rpNocFBDfIO1o6dxfi+Dy1GzjdOOQaFMRElPRpan+hE0RnkqdSf6NMxshp7NiOs1Xeg4MzlzonP6XqYBEJ7+cYg+V4FNJnTTEmUiJiWKRciBhdERy4LU91meckNmh9rKU+4kaHzj530j7/zqd3IqhNHIVToRZCe3VFt56jv+nf+UZ//gN1FaTTfIUztG+CAZVEO2V3zlrX9vRzjck4Iqj2ojTZ7t0BwYekLyVEmdAI0koGG7T2OEj6ARcSbnbC2laMMljQodlRB8O3QADkUDbQPy+l4km6nKj67b2yccHxMPD1lWJc5C7YewRmEaAhqNghUTkadyfPvINOwwzwMakXGKLrAQNrWIEZt8joXBMUn5fWr5XB78z7+e7tlPEdY95UH+Hi9M6cIsS1B3pQS3p+AT1xui08xOLTis5/hGE9psghczj9lbEO7eJa436BCxk0C0NT+w/8fR/e2tKnWPPBViHmqWnCNoRbBAyh3s9zKNwQivTUXpgIUkTpzwkJbDH7j3+LfBCL8EPLrz90eAK5/ma39Tj90ZC/MWQLMwPZZEiD2FmKzGDem0gdaFE1UQcbmivwc01s0Rf/Fn/iIA3cWLYAzlkxk0rJKVVDt8k3c2nTw4btDABTQuH+Uqp2eXH8D5lo3WHMjDZLXseMQIVztGeGE0pVRItZP80K9Wd8bd0TAAZ1IWzIp7QCMBoucPfRqWwLS0LGrLU0fv5c8+808AuHqny5RdFjhdC9MIkSLEETQqtkZ4WK/Q8zl6NiWuVvjoTwAGZKZx3G9B423XPsHZv//dpETe6dUTrIqUC4mD2IsMk/tSkauPduUpNZnct3qq2KluOvB+CxomkYQ1HMsCnSfg5Ul01S7TGPo0dh7kaliow31AY3hNuytP7VTVyaO6kWq2cckIjoinUIqJmLhFyCwvaEOxM5/ifvKUcZHewnG/Yl1sQUPHHmkxQgmLGKS82LTo+TCiNv/bREW80vTTBe7yZdLymGVd0luYiCvfhhYfIkim2UbDOtXZCEfdI08JcwkKadTG9P1o9i9i7lUoTUlMjjq1YCqsXIO93/Um5l/5lQDMHs2vP8hrD4jkevf203ItC7qoCE6xf3qP43qGbwy+GeS5mEHj8C7hMPefmDKSbMUHqt+BfuD1EBWpOnVfI9wqC84RjMEJkZwSxk3BvUZ4lQwaSMKaw86oBN8M3okbU5k5vgJ/79/ltL/5Oe9pfAB4vVLqtUqpEvgG4F2fwfMZj91d56xN/KHf/hredM5SpESIjlI6oNUwC0LlJrWRadjMNPppMTYCqsLi+473Xcqle/F4iZnPUYv5SdBQWZ5SVYWTjO6RaYh8dF0qs/q05iPHL7DWin1Z/MzINCowBSr5bfWU1ZTNABqyCC3vbJmGgN6srJhJH0LjO3ANKaqRaQzZU5ZAZTUH04Ir7Sf4meNPAfDi9TXKJHqRUlRZEbsW3/XYmGgqRSRPP9sa4Wv0YjEyDRfduAAMx8A0hsFSX3TnefTlDckrYuuI9QRLoFxIRMYeOXsqOFJhSX2P1RYtO1dd1zvy1E5z345Rve/djqcBVljb0Rhgue34Lo2mMwUoNZrFfYgU9iRo2JMKRv6/NEh/W9DodrOJ5Jy6ATSSz56VdyQ8JWBMQWUqCg9WJ3xVnwCNylRjmsE2sjtmecqvWVthD1GhY89UfAo1+BXDQKamGSt7ojCNkojXhn4yp3vmGUiJX3j0NfQWaqkWGzwNJaCxVoolIk+hKHWZN2zGbIEqqLEnVnftDmgk8DnkL+KoUwPljEpkO5U8D/6V/47zX/UIs8fEL5Tn9vEP/TMAXrr8fkJSfM1bHiMkQ/Ka2cGc5d4BbmPwh/nrbR0xe/M8JOxufn5MFcHW9D6ivvg/yj///Fvua4QbneUprxVeNoITFbdMw5/0NGqZ3RNl6mfYyaEK7cmpjQDc/CRc/2We5MXPbdBIKXngzwA/BvwK8P0ppaeUUt+hlPqDAEqptymlLgF/GPgHSqmnflPOze+CBnzZE+fZNw6bIKaeainhfV2PQoMK2IvPkV7KuVO1qYnHS9y0ZNP3PHXlCKxFhzhS0dRnYGBSUzko1FaeCm2bQUOqbcblTHbut9ZHvO3piIqKnzx6hrXSHMiiZxlAowad5alqBzSqRobrFIm2gHZ1PO6OhljqSWGZS7ZS6zPTIDGOIsUaUgJDoC4M+5OCxjc4MXqPjluUyZ2zAKrORvjQSWwmU7yFMroRAOJyiZ7PMNMtaAxM48phw0dePmSv2sMnz0quw+fbXEgQvCJ2jlBNcsPhniyI+zCOe7V2ZBrDoq0nE4J3fOL2J04Y4WbnsSjchoV8AMokSilOOBQ5yQ9msVb5gVWKVE/GWIlRZ77zAgd9lhXtblnH8hpc/NmxDPcjV7dVZIMRPisNzSBPSUR9Fx2YUj6zkLs8TMnETig9VDriy5pCdtXXjlqev9GybBtur7ptgUbvsjzlG5ay4LikMbGjlssw7PrHaX1Ng97PJu3QjFemgNMWN5Ukgj/wtTx3dpGrp4RZNb7J1W4j09AsU52b+0SeyoOozPiaKSlckJynvmMhm6OBaVS2IilHFXN0Tqk1qIRKHnvuHGe+dB8rSdNJZja/7sovY1LiJTpaSr7si65SiTJuZhO6s6chKTbP5U5wU0fMYoq/ezgyDV0llK1YpudZTTK7PFwn7iw3/PMPXSIK8x89Defwess06hRe0RE+VE/V8n7jLK8JYSf1Ou5OFxzmvfcty0s1i7T53AYNgJTSD6eU3pBSpjSMsQAAIABJREFUel1K6a/Lv/3llNK75M8fSCk9klKapZTOpJTe9JtyXgMNN4p5k5uB6NdYEjF5apkfkboWhUWpwBv/2f/Kg9/9Y0CWp8JqhZ+UXD5a8ed/4GMoW6BCHMsOY5dBI1UlpYOCrTwV2g5dljjZ4fmkAQVuzVHjeOKly/yX/0/kS55+iJ86/hQbrdgXSa0QAzHoCkyJjn5HnlKUEkPRFYneQr8+vi/TWAjTaH0HvYw7HWK77ba5ry40B5Mse0QppjTegwUnTENXNanrxsjzeraHM/cyjRVmNkfPZoTNGhccVuSw73z3M/zpf/Zh9su8UN3t8m7vYfLvwZwmdgFf1lkyO9exLqfoU5rku6zjy7hUow122LlOJ3T9hr/0s3/pHnlq57FwDXtuiE9JVAIad2XWwyAhFUaPD2yq652O8JRB4z3fwWuOfwm4h2m8+y/DP/1aKvE5/tw7PzruQIdF5WBa0gjbbAfQCB2YguA6lAq5jMIUTOyEwkOlAr6qKSV77Lt/7gXe//ySje/43g+8vC0F7R2ptCx9w1qq7EJUmOioBqYx7vrvxzRksxIDXhuOH3iM4qGHaP+Tb0GZlt4qanm/Y/WUeBpeKVaqGj2NylQ5ll5vmUbo0+gtm77jTAicS4rX9w5CR6UrEgNozCi1znbLUI3hW/RMBnJtPEWC6pHfwSOq5GJR8KHJlP/2F/8C9nx+Lsy0xp/LES3NJ3OPh60CZjHNTEM6w1NlKKzh+uQf8p5bOcbnk5eW3Flu+PM/8FGeupJ/XkhhZBq55DafSp38+Dnfa4RXkmvlp8NYga08FbudXi0pu9185BNc+pnTPHnr0ue8p/HZewydtVPLrM0hd7gNRRpAQ0Cl7dBYUIHq8A76eI1CUfQRnMPPKnxyrLs8xlPvaJip61FVCZMKDUyidBgrR+h6VFlumUZSOaK5X/P8zRWn23zjvObijJfdEY3WHMiOd17K7gULpsAkx0QM9dIaSqG3nU10BbjNevQ0ojxoE1swLSZyrv0O0xhi3rM8ZVSksplp9PK9TinK4MEq/CBPVRWx60hSyTOdH2TQiG4EjbBei6dxH6Zx1HB307NX5br1IwG+KgzBd1Ni53FlhSEye6DnL/+x/55YS/c3Kc9o7/vMNGSnH6tyC+Q7kqQ9ARprFjI7QZtELaBxO54MgCysphL5LlX1TmChGOHNnVEKM0M8SHDwzI+Cbyllx96pmGeCswWN/UkxhhB28nWtb8GUBNeDyvIUumCmakyCGk+oJpTiUzV9yDt5leeyu+hQKYFzqLLkOLQcy4IWAtjYM1EDaMi1GDZTbTv2EAzzLwbQeP73/H5e9+4fp5/MUbqlL6AKiZQUrc+exlA9BbDSGqc0BdlzMREwGl3k195sepQsotZ11MHxE/FhvqJpwHcUpgTtKOMgTymUTqQx5XaDEZlHrXvqGOF1/x6P12d5obA8VZVyT0rMzLTCnM9zcppnXwZj0GXCLGrC3btjplaaWEqjibTcrOTeb2Ainew3xPf00WePLGbPxwkYVinSD30a95TclpIQ4Soj9+2WaaT7MI3+Sq7aPLM5/txnGp+tx7CAuNowbxNGmcw0Uu6jmKyFpnctCoPCU6+O0E3PxE7GSIwwq4nJU/ol6uPfP2rp3/APf5q7hyt0WYHctPMgT6zyIwvphx0ZCsoF9Buev7lmIYvv665vdfiDMERw59+baIjaYgg7HeGKWm66VkAjNJuRaQSRqQpTjEN7BnkqRTV2KytrIIFNnrrQ7E0K3DCnQcGejkSjCN2aD1z7AO+69KOktt0yjfkB3ipscGMnfVyJEV4Z4s2X8W49gsb14zwqdlHkhWoILbQDuDtN7ANdWWEFaIvC4jH0MptalcUoTw2Dh45Ugwm50e3TMo1+w0xisJVOVPVghBd0PozyVDHIU0Cs6hPZU6VR0K1yAB9gBoP7pV8YE1QLqfMPNo5z03sfUSonFG+EifRynplplDnFWAfKBJiSuZRuT3CEuqYSpuFCxKoSpSLrrsMHt2Vcdc310ODE5A8hYVM/Mo2flJHFY6VZ06BFhhriWFToCeWaS80vo4yh8wFlmrw58AFSscM0PEYqFBsNvVIUCdpeoyMkrTCy+TlcNVRDbUcvqQPVNiqk1CVK+RE0SgVKQz+UGrsWI1VIug2UKcFDX8LjB0/yki14SkYGXDrK0qGeVOwvCmwdSM5jD/ZQKueopbbFXb2Ws7jqisIokvJcl+l9bCKlXLMh+dlHP3pkzmiceBp19Cc6wi2a4vu+GdjGrrhCocvyxPgC+jVXfvGA25+c7USl5KmGe+36t5jGZ+oYFhA/0cxbRtAoyKF8U6mqiG2Wp2Z9h44B0/S5cmqVd/NhWhGT50n/KdTmGlp0zo9evslquUGVJbEeQEPq9LUjDaAhC2CIkMoJuDXP31qxJw/E6+9c4/U674r2ZfGaDju0YInKYvFjn0ZpNZV0xTZFpCuAZhsjEqRE1khMNZD9ANfk6ilhGoNMZVP2NA6mBT4JaKDYV5FoNLFveOrWU7zcX4eUsE1+7XIyJ1iFFaYxTO0zizna9MQu4LrlDmjk91uovFAtBTTMYMwOoGErjAokpamKgp5ylNyULV7hadyMx5gEPrixnBTA7j4WbsPEDU2Nid/2lW/ghW/+Vo6qOavWn5Sn5IENVZ0zvdjxNPoVSUBDDSXDT//I+DKlgIY3kXUvoBGytDWvLOsRNISRhA6MJfoeRaAkgbEjaFSpI1YTat+RUqL3CSNhimvX4po74+JkqgnXYjvq7T5m6VDwkY9OpWFx6KlpGtR0giqKUZ7y/ZpgPJfbj8p5RpRdEUpL4R0pliz7zehpzExeyBulxNNI3F1HbMweni4SKMVy0yBjuClclz+nchsVUsqwsDJsoJxjUaATbgAN36CqCbqymE5RpwQPfTGPP/AWeq14vxg3N47zwmsmFTPjKcUXM6fz82Vm8jxcvEgoNdHUsknwXC0lU6uNlLLRGwaThRQopcjBqy1oVIQTHeEVKrNO8kx1AFdolIDG0L8b7h5y9MKEzY1qNMKd9Ist2n8LPI3P1mPwNPpaZXlKZXnKJqjaLeqntoVkOBCD17aZaYTjvKjF+YRI4OF4Wcw5UDGBdphujUotSZjGJGgUCpQj9uJpqCE4UeHKGfQbnrux5rTs7k53S77sOOuvixhRSVEXgX5lWP/QT3D3w0cUvT/R3FeJZNRY6Ips5rsh0nwYu6nsmKvVhR76NSmBKkWeEq+hIC+I+5MCpGprRUEdHcFqomtyKrAsRsUm76rL6YJoDdZ7OhfGhFs9m6NLQwoa71qstmx6P4ZBWjJorF2+vloWMd8rYhdobIUlgrY50oOSfgANmbFtUxhjQa7HfD7OnWQaJu2UxLoNlYCGNnD+bEnzVTmyfNV53GCEmy3TCFV9InuqMBq6LWhoH3P21dP/Ch77XXLvZED19qQ8VRrNtNxhGrtlmqbMQ7aUz0auKVmIN6Z1hKqi9jm63IW4BY2+wx+9PIKnrSZcTT1StEMKiQJPLZuWGyJvDkZ4bFv0ZJqv6Tgut8MbWIW8Y+98RNljdD1BewexYNU3+JCrpxYmf5aNThk0UkJToAU0lMq7/s2moxa5xrr+FUzjtc83LPqWImSmYVNCqe0cmTyBr0bPakyXmwiZn+fxC2+W14cnD57EyD2mpyU1/bYC73R+vsxUhrC98AKp1ARTYTWgIpfNMSiFagOGwKw047iAEMNY5OB2QSP68bNsQ0uVUm5KCY5SNiKdTfmZc44DAW737B1A5Wh2ubfdzXwfx37Di5tf4tU+fgs07ncMTKNWTHowCeg32JSYbraSUGxbSJYDqcqwrRd5KjONOJuQ8LwmXmaIh7IRlOqZra+hbn6MJObjxEdKmZZH159gGibCppiA2/DinQ37vWNY177kJcM0Rh53Dp0UpQ3cemoB3/WPufWjVzAXw4nAwkoa+DZFpCsUlUvcFk11AA2jTfZxksaFzDSI6oSnAbliBuBgUoD0h2yUpfA9wWhwLX3sR9Co2rybq+f7xMJgQy5VHgIK9XyOlgVKt9nTuH681XN1ytr0ygnIDKDRKkjQmIqJiShtqayhY+u15Hj2HhPDuFiu5Q9N293jaeyARr+hFNDw9RS6JfM6v6Fl608EEg4RDqHcjv8c84D6JUN2nfIBNnfg7kX4vN8Hk9Pj3OigIytpTMiAo5hVhpWARhoWGvE0MmiEvOjogicmj+T3qxNUBRPf4UIc5SmAxrf448sj0yjqKRviaNIGAbchYPFIPpMUPSnGLE/VdWYa46z1XkAjV7T1Ahq2mmL6jpQK1iPTCCy0DBjTOfO2SKAoMBGcdH3r+ZS+6ajlkSt9l5N27STPv2g3fN3//nH+/Y8f5Xn15SzHuWuIw5hXtwE7wcwnFJ2iFq/utftPjB/x1/22r2Mqt5muCircWIFnz+RhV1aaVvqXXyaViqArjPgXh36JOThANRGTAmcX1VaeSn7MGgva4OR7iphHKYeY6HxHPbj9boOVUQnOZj9Q931+xoDuOVlbvBqNcHf7WO6Jjndf/b+J6dVNXfot0LjPMcpTQwxG78FleWra7OQWtR1g2Bf2YUJiTkVYDnOcpyTleYwrY627CVmCUs6hdSB02cSqQ8QoC0RwYoTrXdCooV9x47hl0ThuPjzHK83epRW/cPk2r/cak8CagG817vHXokqNXsWxI7ywejRGNzbLU6WDm6L7pyHmYsjUQryKoblvjAPPq0slq+D+pBhr7xtl0V1LsAblG/qwBY3SXQRgMt8nFRYTfJ6JPjCN+Qwt0Sm2DQIa2z6D4EuMMmx8fkiGzm6/FknOFNQmgbbUhaZNxdjlPjANE9x2xOmQNxnDCaZhh47t4CA6jBjh/eIANndYCGisuq08ZXeqp3y59TRciJRaCdOQF3AB+mFs6yk4eJRCmEYwYWQaQ2rptLSIjbY999Dn6infoXSgJIIp+OOv/yP5PZmEsYoi5nPcBY2Na3HLq0yGc59IWqwY3skPvQTCuKXpL/kwhmmqSQ1lQeoHAT6DxiZumYa2S8rpHOV6CAUb19CHgNKBhZFCC53olaJMEZUsJoIfyl/nM1LTUwu51yllD8UUYPM1NjEx7T1WQMPGDBoj0/B51reZTyk6KMtc9bVXHJAkwv8dj7+DA9Hm9KSkUlumYc7mWexmqD8OAapEMBXGiMdDglP7mC6gCZyZlTn1mcw0htiYXml6qcIYenZciLS+oR7kUddgJSWhLbIXh3ccTAsq39O/LMUIXkPoSH2PP8z3zt4q8fVP/Nlc7fkqHr8FGvccP/LCj/Cjz/4rAHyxjS8YjPBps8M0fuXHOAjH7DdbyWrPFyPTSLMpEHiCK0PqgpQU9ijvcyzFOsdvTVzEKA0qQp+ZRicNWCbCM8tA6jf8qe4fsdh0NKen3DjzMPbSXdAlrd3HJjA6g0a/fxpzUMMmnWAapR9AI5GqgtrBjYFpCGgYKZdR2C1oRDVOlUMyqCzb6p6RaVBA2xKLAu1b+tAT5fWn/vn8++yAVFqsD5lpjPLUbIyPsH2kQJ0AjU0f2K/2acIym5DiDQygsdKlgIahLvL0voFpmKKCGDGuGxfethg+E3+iuW/s05AO/EqSOPr5ATR3WFT5G1ftVp4qjBo9DVdUJ8a9TrUT6SH/HOV30kqLKew/imnWWR4yfmuEi7Q1Kw1LAbKh8qsNmWl40bWrlOWpoTxTmYQW0OhDrtQpJTfrC1bvxa9uMBHZp6izVOQG0BA2U0sIYD9UT4UwxqK/79b7OQ4bkpQAD/JUF+/gvucb6JxH2WOq6R4qRvaDgxsfohdPbV8LaKiIV1DECAIaQQR8PZ+R2p7JTpN16gQ0TDmGBBYhiDw1z5+lVkTfZQlwAI29OVWrqGupjPKR2J1n3z7AQX3Ao2lBIqFLTZW60dOw53LkiKm37FNXiWhqjN4JIN1fYFuPSZ4z82orT6WwNcKVxtkt04AMrl13lD8/yExDQKO3CV1WaOe4O/0nfEn7I6QAxV7uXk+u43/44f8aEtydwekVvH7xBl7t498YNJRSP/QbeSKfLccHr32QS3cvgoKhoEk3uWrDpsS02YnVvv0yZ8MhBzugsXCWcJxBo59OQEUeVrdAmEaWpxyEiDIQVrkWvApROqATuB5dlXRyU+oIF5tI7FZ8nXkvsybg5xOefvOXU19fsbpcsjL7FORZBaE1NItTqL2KtIFqSLm1mlIe8sZGiuk8M404MA0BKVlcNEWOQXENoEdZamjyK4QG70+L/J6ALlmIkVAU6NDiosPUeYE4v8o17tMLD0FRYELIertEoevJBF2IR9ArbLfixo48teo8e+UeTcjjMnFDBEn+npUqqHUEXVBZTZPs6Ndo8WNs34+eRic7aDPsYOUYmYbb4BrNmz9xl4+8VtHOD2BzeytPdW5swCt3mIYrKtJOye1MDTNJpN/D+bFRk3IGB49h2w3eZBa69TRS9jQqixMgHwCvCx3oIsuHQJky0xgqbZRGmEZuInM+8kTIKT1fvfkeQuioZXPbink+MI0ooGFlsNFgkKcQxvf1kzd/noaeoV17yFZKKnHj+R+n2VxGac9slntrzrkO51f4VW6Y2x9izWVuRpESKuWS2ySlvutaEduOWZ/wcs9F53NGiq2JIumVQ+d8OcOESFIZxHbnZegHn6TuDaXkTq07T3fz7bzjwT8NwOlQ0VQKRaTEUcwC5779L7D31V8DyuQOcDlMmYimGuPbAbr9KUXn0Slwdr6Vp3aZhsPQiTxV7jKN7oh6kJRcO8YTNTqiyhLje47UxzgTXgSgfrAmOsV7bn2YD300F1O48x6doFwf82ofvx6m8S2/YWfxWXSs/RoVIkrn8kcAu8m7oyIlZgIa/d6E1DumyXFmJyp64W1mGkVBsCVKJZJKo6dhAhjjwEeUScTlRQAqH9BKo3VE9z2qPOlpXIuKn46HLNSGaQNxf8anvuztdAcV137BcvRJzRuuBGJ0+E6znh3AwYS0VvcwjR5lIp2CYrbITEPKZYcxnEN8h8YS0mCEK9iJEcnXYytPDUzDS6d0LEts7HJYoIytffi2YlnD4uA8qigwQxObxCSoosQMOzEHRXd8gmms+wwabVxRWk0aYtXX+TyOVZnLRLWlLgybWIwBfcNYVtM224V3kB8jud8B8HrEd3ANNz6yhw2J7/oqTVvvweYOc3k/q9bnElKyPDV4Gn2RPY1ctRRZjKCRf1M+gNthGgePYrzPi7byO/JUGJmGFyAXRYTDZkMT9VjqvAUNAUlhGiZF+t7hQuSNPse8OEXe3YvzfejEZB37MeS+F6YxgAYh5L4eoC0SzuxGy7sRdK5YSzzOM1vmi2wkz12iVQonIYH7UmjRm3z+RYooSnSEqPOl+pi7xLxTlA76aTa/o1ciT5UiD0OxAxpamEby4sUB1zaKzWSPuk08dLWne/551l0gbJ7gC069laMf/EEuvLRhU2Zvpkw9SsHs6/8IxfnzUExRsUPv5ZJvWwWiqVFmK2k280pAw3N2VnBnnUcg++THgMosT8kzFrYSZNuvd5hGgxHJr7Uxexre5woxCWU0iykpaP728z/IF/oHAPiCfalMPLzNq338G4NGSunqb+SJfLYca7fGxARGEWUB07K7ssC0CfQW3N6E2AcKEmea7W545gxheYxZLIhDPpFSKNk9mQiTKkJIaJ1ImyxP1S53jlqdUM5leUoCREyEX5gc8q0XzvG0Lqg8pL05s9mEm289R+gU8eeXfPMP57JfomI92SPtTUhOUfdC442mDB5tEz0J6orSw11ZeBCmYSWMz6gSL0wjRTVWTQ0ZVEbkqUVtxoatKPQslRU2Dt3Ykjx6W3FrX3NhegFVllh52HvxhFRZouWhqnsomiOuLztm4smsusBetUcf11RGk0ReiQIaR9gd0NCs49YIN9LhXnTdyDQGecpG8H1HMoagt9VTcXXI8YsTPvCGh7h2WtFW8xOexrLbVsAURmGNRisZBZsSqcsjbodRpGpgGn6XaYg8FSDozEK3RniitJpJaUfQsBFOJc1zt+7y9M0ufz5AEUPOoho8B5OGymhc2+F84E3drwDwg+b30NsJRkDjViufmVZExQgaJoo8tcM0nr2Wk3ym0/2cWLAzj2QXNMLmWQD2FtlInrtEozRevJyJUtQx4gU0yhhQMTMNbRXPlAVX9Yr9jYKocBKQmILaYRr5um6Zxhwdg4BGN4LG933kJu+71lP4xB/4zvdz/a/9NTayMB+8/BxX/qtv49QLh1w5o2j8hjJ19MnghiDuos6L+aksbRVVINkKo7fsYzkzFC4QA5ybWWKCw02Pjx47MA1lRmAudphG5zbUsvlI/Zr259/PuoLGBlJRUASX+70ExO1e9mWO1se8Y/JWUDA5LffBZwtoKKVeUEo9f++vV/vkPhPHxm3QEZRWBNHX9Q7TmLaR5QRSWRB9okhwsPF00tcwczqHES4WpLHUDuI8G2o2yKyAkMvpBjZT+pyGqQ0Yn7vF3RAqFxOXJln3vyazCTjYY15b2tOW1//xiuUbz3H6GArJxTqaLIj7Wauub2ezvSo0hfc5TJBEqkt0giiLRCKg0CgxYIyyBJx0hKsT0eiQu4AB7M6OK6ahK7qiSgIaUlZchcDsgbexX+2jqxLrI5DG6GdVFhjpOJu3UGzucP245YlzecFYizzVxxVTtX1ghxFdh1hKHUEbKjt4GgK8Ahqm77FSHTQshjpKxLc1RC2+E5BWh4Di9iy/flvNoTuiUoHCKOnTGEBjKwH24/S+5oQ8pcd8Sz+GT1LO4eA12QA2gO5PlNwWJs929zvy1BllcLFnHfQYB1JFL57GFjTEesI1HQ+5i1zweUF5V/qdXHvsP6SQTusrK6ngU4Zg9egVDdH2ccfruHKUNzmPn3kyB2oOicHeE4ShXrGGvs9ftxDQmLpIqxVOQKNOME2JYIQtxAAp34/J5E7xTQWlsEk/k0wrr0GLpyH+TRFSvgXKGdp7opbKIpGnjoPlruQ6lY3HXb3GWoB5epSvyYvf/vv5G1+vOeyPKZOjo9wOwbIT8C3mIINGWTmSqdF6e98fytCr0GrOzgSMV73IU/lrvNpmT9mhrN9HutDm/hFg+VM/z+bnfo5/8RUlXXIkW+RKKxxFkg3QqSz5TXrYu9NiFyXFTKTl27/+eUK/2vFrZRpvBd4mv74c+F+Af/pqndRn8li7dTYbjRoXdCONWjbBrMmgQWlJQRFSwbxJ3JrnG2rqFGG5RC8WBNlhXEqniXXeHegERmc2oM68ZvRNSpflKaMi2rvcp5G87HyhE13ipoCG2d9nXllM8qiq5HBvHxtg/6qMvazm+P1cFVPcvJZfw2isMA1HApFsVD9oswG1M0vEqhw7PVZPDZ6GMA4j8lQXdwLV0hCuM6Gkz6BRb2dP+LOZTuuyzjKRcrhm6ztoiZSdtVBsbnPjuOWxM1O0yqCxX+3jWLPgZJoowN1kqXaqpzoKejH3rcwHMV2LDRB0IgySYYT08XeCVq9gGgCNzt/bltmbUe0h88qy3JGn5oefhL//5Vwwq+3I1/UGFxKTJPNIkiIoUCGQhrRSkaf0yDREnrr4s3z79T9HrbMZ7mVBzqBREOhpgiaMg51EnhqMcJ2wZiv/vbX7xdwASO696aOnlEytw03+nrmuiIUemcYAGgfDhQqBa8eXAHhg72GcSaMRrrwnmIIzPnLVWnon3sUiz7dZ+ECjFEFAoyQyj5FgpHEzBlIqsSGRTG76W++Yz35+rzxVj6yq8NApBeUsV8KpXFk0MI1NLDmUai1XW/yNGyPTqI9yY1z92tcSteKwO6ZIHS3F+NkOTMMenAKgKh3R1mOGFsCdSb5m6xsVr/mL38p+t+T2qiOkHU9D2y1oxG2xQxt7KmVIEa7/o3dSvfHzed+XTul8R7AF5cgmBRhOZclv0oO+fpvioMTK69ubr/50iV8TaKSUbu/8upxS+p+Ar3yVz+0zcqzdGhOEqgvTUOtBnkrMm8RyovJ8hqA4jPvMNtBIx+ikV4S7dzGnThFEy7zOHklyZWyAUrqn1f45gtV4DaX3ObZbB6x3qLLCR09S250vwKEU05uDAxa1pSAQleXGVAzHS/khvFPO6Bd5d6Zu5Ae4KjQ25Gl2PQkmA2hIhzsRrXZBo8hMY3ntpDwlJbdmmM+9OxBm2JZOphhiNqLLHdA4L9UoVZbGlO7ww+64LNGqAQXzNmG7JdePOx7Yq5lVllXnmRdzPA1Tdkpq5LgTDaWKo6fRppJrEo2xN8873hE0DCdBY32bpCJRMXbup3Ve4Fqp9Gllxgib20xLS+u2SaUHz/wAXPsYb9GfopVdrV/nGebT1GZZBWhkQGMa5iKUU6j2M9sxgHa5euqF9/LG/pc5rVcCGlumcUoVJBxrr8aI8yK4ezwNxj6C0HU86l+i0Wfkc3a03o1MY0/ux5mtiWY72VCJPHU2FHidmc/147woleUEP+zoyT5N1JaHvOeKtWzSIcQp1TRvluYu0miNlx6bmsSjzpOqIfk3kKKVGJHERpjGcCSZYreVp6qxUqwIOYqEcj4yDRW2TGMTCz76wOfzfV9ZcvEdX0hcr9kcCXgd3QFj2Dv3IACHbolNPR3ldtiXrU8wjapyKFueyNC6JVUFt39ljnn+OT7vzkvcWvfZ0xj6NJTJLEjrE0yjjYG63s9x7LePOPX130BR1HQhg8YAFkVIoBN6P3+Okx7SnUPszObChyqgbl3n1T5+rfLUW3Z+vVUp9SdhnPH+OXVs3EZC0xRp8DSEaRQpsdfAcgqUlhgUGzdn0iu8NKnWfcLfuY09fZoQ8oN+TE2U6g8ToY7DcKIpzk6kX8JjlKGSBUtVFS54kk6j+Qlw2+UFrNifs6hzTEhQBZeqvPs4fyXfjDeLOf10ijIJdU0edKPRPqJtykN8agENkQCUCuhdpqFLIh5YO35UAAAgAElEQVQOX5bAwpNGuBF5qgnb6XBKbqkhm6h17QnQiOcz0zDVJDMN3e0Y4QXKNahaMWug6NY0LnBhr85RGp1nWkyByExMwVBtb+HDVFCokEHDGlpKXigK5sWMval09nYdhQdvRb9HjPAISYUMGgPT2OSFZTM0ognws7nDF6nnqJrrEgWRmF18NwCv01dpTP6sh6qwSVoT5cU2cim2TGMGWpOSySW3yuUYkWW2DGcqz5N2AhpFgAW5L6aNdgsaKU9eGqunTMKKfOLajvPxJo09Kx+So3E9VjyN0zpf/4WdkgqzjTkRae/AVUQFq5S4KedVlDV+xwjXPpKM5WHvuGItSxqKMEff+UT+2QJEG+nmr1LkjX2PVh1veTZSekeKFhMVcWQa40dLXAzylIDGznstfRqZBsETlcqd48I0VtFyE8u/+B2R/sG84LrrWbK1d25hz53jQO6Pu26JTQ6XzA7TmObgw1OZaUxqB6YCtd243JBmkv44f/aPrG5w47jluOnG53dgi5QFRq6t84GOSFWfpl9K/9MTr82zT0KfQUNM88KTQeMgv4fTzhAODzEyUM1OIty6wat9/Frlqb+78+tvAm8Bvu7VOqnP5LFyK6wwjcHTUJuhHhxOL3NNNIUmBYVdS/npQuKNu0i4dRtz9gw+DOF2FUEkCxNgIiWuagc0bO/RWlPJIqCqEp8y0xiqL4qUaIXfVosZ86qgwOMxfKrIN9KFa/mcb+uaLlmKqSdeyXM+qsKgQ0LZhFOgaomc6GVnrSJmZ/BRoQs0HXRHOQJjEMmFcWgpE9xlGlq270ZAo/Mtut7ZMl7IO7qizhHeSncEma+cIxM2UJvsaYSemo6zi5JZZVl3gVmRf+4kZZ/J1VuQ66uWQomnIfLUxaLg8fkjuUmKHK9to1RJST+AiRCTIhGI+pVMYyWgMYABm1v8rfav8I4b/ycuRJ5UlymOLgLwOFdYTvJ+qnlZenBSMzb2NTJSNW1WoO2Y55WSzjtkLUb4MkuKU+0ojB5nk08CmGRAOxyGID+4DB603XoaOlEIaPim40K6QVtckP/ztN5h5f68QL6Ws2JOsibHnADEngiccQuihtskbq8yMyjLCcEwGuE6RJQxPOkcl6zlo3XBm/wN1Hv+GwAWEna49rl6qoqRN3U9b3sm8W3/PDK5mbvrTVREnVgqc4JpIFPsYtiRp4ZYdg+dIstTIRC0QcctaKxDwVoYWDyb2UK4md+HunMbe/48B3UGjUO3xiZHT5GnDILIUy3V5/020vkLmCKibDmW3E7sjOvlht3jNaub/L2feo6rRxvazRAFL0y9LMfcNH37GVqlqOYP0EvMcPnEE+M8d6/tDtPIRF4fZMnvVG8zaFRDk2Yg3vosMcJTSr9359d/kFL6Eymlp1/tk/vNPmKKbHxmGkkrojhYSoza/SOoHbzwgEIVhugVs02+hLPZkt5AfXeTJ8SdPoOXcpJjVdOLUW4jOfsfUNMZzmTQKJzLmU/DCMcyd12g8yQ5nSa07aOYVqqLZhPmlaVQgS4ZrpvTNHXK0RCVYukSXdQUs4C7smUayifJRcl9EQDaDfpXGhv78tdXWNVlPyOlsT9jYBo67uQgDYfs0q3MW2hdN4ITgHpAmEaZI7w1/Ql5in4NEklfpMQpViyqYpSnBtAY2Fo/zefSFqAmlzNomIJKmMbFwvLa2cPjRDzTtcI0QO/KU7JYZdCQ+2GTpZSVyjSyG0Dj5jPspyUP9C/iQuSr9Ifyv59+gsfSFS6fewxzcMDmp94r59qM8lQ7RHK068wyhssWdV6ElfRpyI5+IqARlSYqmIaUQUN5egyBXXlqaw6rejpOcYztmvPcpisfkA/B03mHFXnqYXOMSYl5uSAW2wj/FBxRw4X2NFHD00aPYwOKapLlNJGntI8orfmPj5acNhV3jOExv0LJwronvQcr6eavibzRJS5k24iiCfQhYoIi6MRKWTbV1tNQwjTSTsntEJZYBuiUhnJOco6oNTr0IJM0lzF3owNw5rR8hnlHnm7ewJ4/x151gEqJQ7fCREePHSvjshHecPA1X0Pzj/4xSoOyFUnkqVPlWW6rFV6KIYpHHuKx5ha3131u1pUO+zA8W0WBEbCdv/zjJKWYXPgCuqVFT0vM6dMjaLgdecoKaJh9URVWQAiYGnoz46Hfecijf+M/49U+fj3NfW/59b64UurtSqmnlVKfUkp9233+v1JKfZ/8/y8qpR7/9b7mpzturTre+tdzJ7iJeQDTCBoSCXHqRr5czz2oUIUmBZjKvbg3PaQtob6enwJ79gxOFool5VhRY2Kilg5sNZnT21qYRk5gLeWhjMNsBp2okvr/2HvzYNvS86zv937DWmtPZ7jD6eH2cFvqlkCSJUuWZIzByCAmU2AguIJDClKVhCKxiQtSQOUPKMcUlUqlyASkgh0qAySQAIVswHbKlnAMBhk7WBgNLavVLfUkdfe99wz77L3X8A3543vX2ud2C4ogZLuSXlVdffue3WfvvYbv+Z7ned/nZSW3yWHFYldmbM+NqKcRaJPhlBWXK6XTM8O6LX/v55Hh5bIA1TZDhDxWhWnTnQx7pjGW20JhGlYG1D/lr/zMizzz6uW+5FblqXEeAIDRhcivSk17FzusmtBbV+MOy07P6XtXeVcmkxltHhy2MHMsdxmfM9dkzfHH/g7f+bH/iU0XWLiyeFQKvN0IGhXY5iXc5GkYthhecY7b8wem5j7blY7wwcrUpW8SpFzOdbzKNLRq7tKU79KOsdMvfByAB4cXGELiN9h/Qnjw6+Hxb+bR9BL32sjyQx+i/6m/j0mROm3LDhnYaUwK7brIKXoUpgG11xgRZRozetwYWW4Ns5CxWEQyrVgiY4dxUtAYYz6WOAUNe/ElLJm2uVV+JoEuDlOfxkP2lFVKLJsj8BYbSjVSjgPRQJQ5YgynyOSv1X5GMFoJRsZFsNawypk/9pYy/vRGzNMEvgOtsrqIl3r9Ajfx3DjVnp8uKtMoRQobY9k2V0Gj3C+TPOWaKcLEX2EaOQSyHZlGuS83yU+lyaIDluTeHSpnCK+9hj85wbmGg5Q4C1ts7pVpZH70uR/lj6SXpt8Vx9kWrtaRY3BU3eAyXLCrG5rjnsV7v46HL14rybQSMeN8DDuGsPkS4gjMX/xY+avlg/RrR3WyQkSmee6DcYVF5lw2Oxb+4ifKTI8HzrSMv4ps3RGuTvhx3PPX8Phqmvv+g6/mjUXEAn8B+K3AO4DvFJF3vO5l/y5wmnN+EvivgP/8q3nPf9HReMtpW25oGyEZg0iicyDavLd6zdN6ePkaGC+kKMx3mo8/27KroXq5VGPYa9cZtDrlUmo6v5ennC6yZr5ksAoaw4AxppQeAsmP8zXg69wNPnj4+0hxwcEW1jOYx6ieRmQbDad5yUZBQ+aO19YdbbLUh4F4dsbwyqvMc0sKwljgZOaF8tuxrFGkRJnoUdu6RLXrQvHyuudjT78yyVPjYPv7jHAtaqoOijHfxx7vKrKveHV2RKWNhk7HybrckXToVPkftqRFxbItfTFHsmb2Ez/GU8/+Uy4nTwPqqE1mi7L7bz3Y2Yt4iqdRO8tZpTOhm5sT0zB9AY3egpV9l35hGqgRrl9P86C2Zo5g2KVQ9O0XfgaARd5Qb1/m6+RZ8u1fCzee4iif8fRzL/DSO95Pvrjgnfe+QB23e6ZRj0xjW0xwxlMpJCNUPtK2LWyKfLIwwz5y3ZYpeKLFBq3I1JBZ5RKNnvsOqSqkXk6jf+1FAaDd7JGSpGzK3HQfBSRzy97hT965x7/9jt8P3pfzI8XkTgY6MyuVfXlflFEp0zAhYE3AJfCKwt/29u/gQ5t3Iunbpgl8S5VjLpJGs+REthU3T8dO/UCIGZOFYGAjlmG298LcYkZC9vKUrUp3OAoaxpWFPBSmYdMw5XttcjM1n/rVATKfY0/vcmQi6fwcd3IC1nGkoOHSQJ89Q0x89PmP8hPxfDLVx0wr46oJNA6q62zDmr//7q/jgW84p3r0IVbtmj/7W55QpqGPxrgh8x4z9NzgnM1l6Z15YPEA/YWnvqn3t3oagymhNjYVeSpY+KESIsG1U62YqiIbVzZjMmaafQ2Pf2nQEJFjEfmgiHyLiHwL8Je/yvf+IPBMzvnZnHMP/DXg21/3mm8H/mf9898AfoOMTQT/mo+5t6CGoFOmkaUMKkKN2tVrlmcfLNKVcUKOMjGN7Qx2FRgdiOKuX5vo8wY/SRsugdMuZZkd0Nmazgu263HiqJUSp2pc2eEhu+TdN99NDiuWOwWNFIo8RWQbhA0N27Ihxi4q+ph4bZtotOmn/dQnmUmp4kkan+HUdxh3QhHw5qo8VYFEopacRjH8/IvnDAosoqBxlWlMYXdqGg5pwFtPripenR9PURt+ZBp0ZVKhLur0l6R5PclT1/MF8sxn8aFn0+/lKa/m+05BI3gwzYsYomZPGS5UZ77dXIcJNHoFjTyBhkm5LNre3880xqRaW1HbunzP2TXQrmaA26/8GJVE5Nb74PpTAHzT4Sl/6uUFeM83fulTVGkPGr02KuZ2VwBoPG9qAHsXmfd7Xbq5wjSChTrkqf+nFQsm89DdjDszU/aU1DXUSyx6P69LRc1ufovKNIj0DCngo8HYzMNylw/vBt5+8h7wDhdLCesoT/VmjhWDj3CokeZVVUBDYqAx2o2sACGLG7zIH+ai/oY9aCgruNAChiYHsq25oakXrk9FnkoQTGYjhkHvESiBgYNzKk/dzzSqAK2fgQgMgWQdJg/QlQV0zXwK1Kxdg795k+rsLg9FrYq8eQLGcRQTp2GLST0DliFmPnf6LIHMoH01KYygUeZ4AKzcdTKJpx95AHdj4LOrsvn80HwLpInJj6CRq8I0vtX+HF/UzeHj9gHCzlBd15GvKk/16jH6UOSp3sEzw5IksLynJbhV4NKV5238zl/L41+2eurfA34S+D+B/1T//b1f5XvfAl648t8v6t99xdfkEox0Dlz/Cp/vD4rIz4rIz7722r9ac4sxwlxHhJUoAyFTQEPanmwalnfg2QfVPLUAwuEmEkypimkryrwMwF6/AUplN+Jp7b56ymnlhCwO6GxF50vTmRGDH+Up3ZEjGRDe8+gRLq9YtJlNI8zDwFLlqcvBAMLuQGWjVXEQX14HmuMBjKH95Cep4o4UhEFN4ayyEf14UwvuCtNoXEWURJiXyxKN5Z+9dM4wVkiNoBH2oMFQDPNmWRAspIHKVoRbj/H08eN70Kh18U8tub/CNIYtcaGgkTKPXb4CbYsfOja7fg8aqldvlwrGLmPchjVhKrm9rLZIzjzmVnum0bX4WCIz3JUu/YQleU+S/TVMWjXXW09tm8KotMpmo5LVU6+UwTn21nvhRgGNP/SuyGfOIhdPvJ1fefpFqrCZmh776irTuCpPCdmAc5GbnO6vAf3UOBhsGZ2KjprdUQYYfc8PRvj4snSEa9gl1QqL9kAoaHTzB6lt2XWHFPBREJu5Lms6f1AWXe9xsVQjpRhIJtPbGRjDrSHwxOIxAOp6UYoJYqS2mgElmYCB5pA+JAa3ZNyDzNRcX2uDWh0j2XhurnVD1gaGmLXJsZTcJtfQK6t1tWOwtjAN4wurGMZIDmidThccBpK1OAWNLMXbGiudalvjTk6oz+/x0FAWWHdyAsZzlBLnscXkQWP1A1/QAoedgkVSpiFXmMbN+lEA7ixf5c8fH/G9p3+rfOkXnkckItpMOpZN4x0y9HxAPsvnmhWC8NA9bfK95qbP2cWOVhOnfSzA0VpTvpOHo3PtI/MDG7MkYqD95ZM99T2Uxr4v5py/FXgv8NW2Hn4lxpD/FV5Dzvn7c87vzzm//+bNm//KH6ip1XBKmWgFRKfbdT3dZoENxc8Apofh2mXPegZn1u31asAdH2FGTZXqPtCwV0Cjl5regek6rLFlNCYQNWQQA2ThvY8d81/87l9dFjwHs9BRO4uXyFor/9qj8h6VNvVddGBcpr79KLtPfpK6WwPCoB3az16Ow20ySSyB+5lGbWuiZLpZMVCDGL54d8s97abl6kCg8QgZM5uxXBYjfMiBylR8+T/7C/zVt394klpGplHnnqRR8MQAsScuGwzge+HR033deb/tJtColN1slir7qU+zlqDylGFXrXk4RJqcJk/D9D31kOm8FClLr0nOlqgd4TKONdUCiMI0msI0FDSeWbyXjooHNk9zmpfI8W04vg3G8Wgq1WpbV+NjwMct2RWQ6WtlGv39TCNFIQsYM/CA3Jv+vqGfzlkwmSpk0pjXUVnypfCWV0A6o819ZYAX9RKrvo/f3eWVfITxMxpXmEYmFtDQ26zTzyfe42PxCHKMZGUaSQzfsO34zid+V/lc9bzIUzFQGx3jK4nzvAIRupCI1cHENLRnk3PV3Os0EGPNfDSE+0wYhjK5z5TIEcnV1CjpKsvg3N7TqFckBY0qQKc9NMXTcLjUF9CoV4BM7fgjaMzXp9zsr4KG4yhGTmOLTT09jtd2rxBV4mtTCzlPGWXG12RlGr/i4Jt5uHk7z538PH/5cMWrR5CdZXjuC4jkK0xj3Kx5ZBi4Iec8W895aPEQPF+KVepjTRZQT2On5nk1QB2gJL4kdnUp7y/3fvFgNsx++TANoM25BJ+ISJ1zfhp4+1f53i8Cj17570eA17czTq8REQccAvf4Gh2NTqUpOUB7pkHX056Vm3LPNMqCeX3TsZ7B83JAOwbgHR6WRjUdObkRz25Mho0Wq3XXZnlMZ6ppgp4Tt2caY2SHwNhQcGN2o5TdmYzT7KJaImv1Tvpr5TM2xxp1rT0XzdvfQvvJT1Htiknfa6TGJ1/TiI0AwS0IIjz8Ws9zv/vfoH/+eRpX6vM39Un5TAoo//h53c3ojvwq05A+IbOGRgPmApHKaqOUyBTqV83Kz33qyP1QSmI1xC8sxl3jjAfO9rtu27d4KT9zYznlamQaupOVPdPoqwtuDwOE9grT6KmHElboNYrE5FJyG60txV+6mxwD8TrraFzDLuxgXojuvdltnqeA6ad4S9mlWw/Ht1msnyvnJRtcTriwIet401BfkaeqORc/8iO88N3fXSrUDGAGHpD9d65lL08NNlPFTIgjaHjq5/Wm06qi0dOgWmJUCqq293gp38Bbw8zNwOjgpgRjQc/OamJBVeEjbHCklEBgsHOykbJd00W+rgpo2JiopVy3uQTuaftWHxLBrxABsabE5+TMuS60VewZNvuiizJUqCuT+ySzM0JKFVtfIzZRuVyuz+hpVMtJ8nMJOjOOpC2g4RmgvSD5ct7ldUxjuT7jhs5ndyc3wViOY+I8dZhYFuEvbfZCSAcQB7Le68bVUzc+2fHrb/4hohmIFO8pPXxC/4XnQBLXtl/SS6TylLMw9NyQc77gDLcPb9N/4QsA+FWaPmcXO3YaAFoFmAVonYDp2Y39PsZiTGlG3Mr8lxVovCgiR8BHgB8TkR/kjQv8/9vjZ4CnROQJEamA3wv80Ote80PAH9A//x7gYznnNzCNf11H5fcBgdEUk7DzJcN/2JVF59XiN00RDTc2O9ZzeMkspws5TvsamcYOx0afzib7aeKcLI7oxKsE1qo8pdEPbiztyZMRfa25VnpILNAX3dRLpFfpY3dryf/2rcLxNzzO0dwz6A3XvO028d49zAtfAKDTXffPfbklGHADDGZGFHj8pZ7205/my9/3p1mofXTuyveJui39c/+4PARpAFKcmMY8Ff22jAItTCLmMkxp7K4d5alaQaNKHfR92R0rEA6rAgwpzDm8t5muTx17Uiyf3Y+NW+ppNHZMui19GsZEhvoeb+sHHfmpoDEoaDjQtViZhilzzY2yAJh6HnrrmbmmgONM6/nnt3k2PwzAp+XJ6TMyv0E1lMVol0qFmQsbknoBYzNi7lqolmw+/tNc/vhHSZepPI1yP2g0eZSnEp0rJdWDVj0Zb1k+r7tX3YGnbZnfTb3EarFA3Z0V0HAFNMQMiCSqCEavx8aUxV58hYslZj7HRDYQ7IwkpkhoCqh1vSBaMCHipVy3BT2nWcuTQ0SqJYhBvJCDsEyJjUqCdQqE7X75SUHIacAm6E1mK0IMnp1vMC7jiQRrrzCN5VSRBjBIRc4ZYiSPhRq7e6RKjb7XMQ0fBx46+3LpmTg6AhEOM7Q50qaePnu+tHt++v2tCITd5GlYX5MI5CyEKBzZJ3js5V/Df3K3XLtwvCLcOwUiR+pRRZWaUuWQYeCaXPCiidw+uE24dxc7MxhlNpWt6GPPRq6ARszsHFS+24PG6gBJHV127GQO3S8TeSrn/Ltyzmc55+8F/iTwl4Df+dW8sXoU303xRz4D/B8550+JyPeJyO/Ql/0l4LqIPAP8UeANZbn/Og/vywUrzV8lJ6jzQu4CcbDESopsBbixRnvXcjkTXjXNHjR0rrBT0GjFshkX8OSnOnhZLOnMCBpFnnLKNFptPBMps2RgDxpYoCug4YgEihxT1Uv+9jca7MGKR45nBGUasyeLDp0+/QsA7LTZ7mIT6ZwpzVF2TkBYbjVD5x/8A578J6UV554tlVDJGB6/PueO7vZjZyAF2tgiCPOUMUPCNA24Miw0ScZbT6egUY/lutoj0uS+5Bd5P4X4DUstr9w11GcdTns7mtCz6TI5eVzfITax1dnNMwXx81zSXl/aPAuSeGfXQdhNTEP6Ahq9B3/F08hJiM4WZteX65b7HgxkMQU0YjsxjYvlbZ5JpVHxs+YKaPgGE0sX9y6VeRYubMiizWkaq577Dvx8GthFyGUoFz0PyBldU9hdlTu8MWD6adJir1GpVc4svmQ1mbbswNN2W6ri6hWioNF0l7yUb1JZYe6biWlUISN+BI2y2JuqxkXYiCOnElsR3KKARmKaOzJrlgQj2JyZ5XIvLum4l1fEVCLhvXdQH2BsJkVhmfb7vTr0hEttdLSmgMbQY1OmN5mdMfSDY+trjM04Upk7H97INICyQRpHzzrPpyvPq5tXiNXrmIar8Q+Uc/vYFz+NOzmZAjqPtcdonUvj5Ku7F6ff34rA0E4d8NbXJZctl36OISYW67fwTVppGRZVubaSaLSXxSvDz95C34O9pJXE7cPbpPUlpnHTM9DYhm7YEtWsrwZoQmZwcPN4OzWJxtUBhI4Ox878MgKNq0fO+f/KOf+QVjx9VUfO+Ydzzm/LOb815/xn9O/+VM75h/TPbc75O3LOT+acP5hzfvarfc9/0eH8OLa1gEZA6D3kIRI7S5xd8Sz0JrQZLmZwz/hJnhpHRI674Z041mrPzLJFRtDwFR2ey5lACMx3Ga+L624c6mCYZKCj+qjEeluZygk9gQHHwczj/ZwoQjSeW0ezSZ6qbz8EzjF8ppy+nY5tNdkwVJaqL2WVUWC5jWAt/rHHePynngbgnmhvhff82qdu8LZbx5hZRewVNEJLY2uqnDEqT+EbBn0YK1PRK7samYZoWOIs6ehbX03sqVfQkFcskmD+gQ+U7xEH7m17cqpxQ1uCF53w0jU4XJZrd6olt8+cl8/+zr4vsoeyK4mJeiglup6xeqqARnCWbJh206kbQD/v3M2KEf7AO2F+ncvVW/h4fDutmfEZ9yuu3EQzJOw4nFVsYgl1NMOGrPlVefI0Oqjm+9HAlC7umHpOOOWyeZA+Wyp6vBPEdLRe8APsFDSOTy8xSfiFh0smU8buQaNaYfMYyR55KV8vszn8vCygUtJXxY8NqHt5qoCGJ+eyaYluXqI5skzSXeUbRpXsrfHzABzkHad5yRATfUhFimwOMDaSgzBLV56f2DFcJHa2Ih8sCmjEDpsynaH8MzhePLhJdRDwkojW7Etu6xX5yu8L2U2Alr3nDz9wk/+eU4LTfB/ZM43qySdJIhyevkr99r3KfqTL4ZlEejyvtXt5qjVSFvTXMQ2yZQjl+0axU1rtMK+IF2UBtwmQzEwLT5Jz5K7lZV0vbh/cLuMUZm7qYh89jXeuf6J87lD8rMHC6uDOtNbE1QGQ6ZKjNb+85Kn/XxxWs/2tMo1OhKGy5D4SO4izvUnsrwTmXc7g3Fj61zGNWit8WgznyjRmyaLp35i6ohXHF8rGh5svrHG6uLb6PIjs5SlrrFa8yBWmERiwpdFP5x8HW3HraE7QhgxjoX7bU7SfU4NWjXCbhaFypSpDZgSExTZij4/xtx6m0uykVzTozlWeP/3t7+Jvf/c3Y5dNYRpxoIsdta3wKNOYzcHN6PU7FKp9vzw1dqM3aYAwaDd4eb9uVXbl1YvaAPX+95fXxp57lz2kGtf3GFseoj/6Bx0PPbVBsudMSsrtZ+59GuKMWyHCsGcaJslXZBokSkev5Ak0cj+QncEZKZ5G3ME7fgf8sc9jmxV/P72bP/rE32Y9ljsCuBqGlsOZY5MMLkVs2JJEc7409qSwqwXpYr8ztAb61PKAnLL2N2ipCtOwBjEdXQVuEHqNkql0M3H3QHfsQRQ0FlAvJxM6J+G1fETlDI1rSjQ/kSrmKXzygiKf2brGB9iakro6MQ1jyHnPNIz3oBLqLJR7cZE2nLIipEyn881pDhETSFGotVQ4J4eEgXiZeHV+TK48OZaQQZPKNW1NJsWKv/qu38hjH7qHlUhyZl9yWy0L69AjYqc578l57ljL3dQTRk/D7D2N5m1v4w98+5/h737vX+KR/+a/nn7HkTKNcwpo3OlepM7l4dyJQGj3Jbe+eBo5O4aY6WJCjJtAo5u5aUNgYwHfcS5Mqiy5a/mC3pNPHD5BulhjZnu2XWNIIiy4U671UDrfgwOpX5xUjTBmvGXHf3f8x+H3/yBf6+NN0LhyiO0h2yJPWdgZIVSGNCTiLpOugEZ1pfPyYi5c2kz0Y7ltAY1Gdw3BWM416XKWzDQESOqaTtxkrp88v6YaRz2yZxr5Cq33ISPOTLtyl5VpNB6vVHywnlvHe6ZBGpi96+vKfGVgo42GFYahdvi+NEAFgdkmYo8OMaG/MUEAACAASURBVPMFTqn2WqulfOURKcOG7Gqm8lQsTMNU+JxxvcpT1rFDzf+rnoa9n2k0uS9Dp6pqMsI77f6t73QYn6jfVkpZ69hfYRpDydAyGZcsAlSy4IwExvCpu5+C7tHC78Le02AQXILWy30ltyQh2FLBNEZjpD6QnaXWxXYy/K8Y+us+TSWx5cuW2QtH84pBDE6zoXLW6q2xTyNJYRo6Hx3AmEyfeq7LKafmGi01Ve5xRsB0pTQ7QM5jz48On1qIXuZ4hWksQb3rFIW7+WAywounEalCmsD0LCloVDUulWpAmwQjkKt58bMSUxQ6zk2DxWo9L1YCp3lJN5QxvgU0jjAuk4LB6RwAwUJoCWcDr86PSVVVmEbosTkTBXYmQvLYK1MikzVlnoZ6GlflqRhlAo3BlQX3gjSBxtWS25Qyd6iw129MkTgAR/q8nBHZiOEivEadSq1OJ8LlZl2CECmBjfGKPNWHhFh/H2jkzQZJpYxYTOZYizWSs+Su4znv8DhO5iekyzV2Xk+d57XeNzOt+6lCydgaLFzy7MQ0xjkjbXZ01TE0h3ytjzdB48ohpiPH+SRPtSKkypEGiLtImvvpteNAFIDLBtrmDnGcBHf9BinlfTChhXOugMY4jKeqaLFczgV3csTNL57z1uc77jYHbLQbViRP8lROpfnpvW5WmEZKGBIh2yJP1cX0G6zjkePZZIQTB5p3vXP6vGdaGjxzjqF2VAOcxZqAMNtG3NExZj7D6ES9ViekuWr/gNnlfPI0utjRGI/PpbvczMuifzY2gtl9zLRXT8hoHlUdB+R1TKOvK3pX7IXZtQGj71uHgdNNT441tg8YmwlGs5iAuVlyJpnWWJ45fQY7PFYqVkKLiJCtZaQ/b2Qa5XeJkWlhzEMsoOEtMze7r0ps9GbWbSiew3hojPbhzBPFTrlBMZUIfK+NlTlRPI2LiwnQjnWh+HwTOctz2uzxqUNE8K4v+VqDTMUA4+TD9Qgafb7iaSwR0SbVJNzlgGoEDSmZSD5mjPbsnOaRaTT4APes1cUOjK2JoxEeSt+PnH0BoxEmJowhiXA3H5RodyhjhtXTyEGQNObCO8JlR//qlqePH5tAY/w9UcE754pmHJ5FJFs9b+ppjDFtACHtQaPXc3xuDb19ozy1043Zot5vAgGuqel8ag3nytJcLCGPrRG+dOds2lBYX5dokmzpVZ4y1k1jW1tllPMOJJZzc00f/OQNue95xTkWHGPEEC/WmHkzyVO1eptLLYqoAhAhiuc87JnGMCvP0S65aUP2tT7eBI0rR5aWFBtsgsGU3UWqPTlk4naA2VXQ2KdaVtdOwETS6Glcv0YbIgfjTF+b0D4cmiSl1t4AxtCNBvntE25+/i7v/HzLxx98B63eNCJ7pjFGQd+qloVpaJ7OJE81e9C4dVSM8DvG8PPnzzJ717umz3tP9bGFdcSmgMZp8ESB2TZij48wLk3pt22n9f71lViHg7l6GgNtbKmNn5iGaA/GhSu7Hm88XSxyxWg6jiGGVQyYiWmoEW4Ml9p32Fwr8dmg8tRG5akhIC7TS8Kq7LG0K84EPpu6MscgPs4g+91bspbcl1u+82U+ChTQEO0PwJhSVppzYZivYxrrfs3f/IW/yc9f/Ajizth0Ae+EkAI/+eJPku0oT3mCMVM+V4jFHxsZSmEaC+LlJfP3vAeAR1LAG89PLhouoqelwutMC+uKES5BiHkEDU2OnY9MI93naUBZrHKCO/kQbw0PP3vOrC8rmQ9paqq8lzTWpWoK0zAGk0rTq3dGQaMwjWws8TM/jFHfbcxREpO5yyEXOx1w5G2Rp1wqfShRvarsuHyuhwwff/CdChpmqjYc55yQKmq955yk8l3G5r56VdINdEORokzS2QgaF8YwaFbZKE9VtpomI86vbIIADqVEdty1lvWYlxKL9LgTwyt3Tyem4aqaIRWmMagRLtYjQCOOneZmzTto4wxM5rode7AsaQi8ai2VHPOPPn+XeHGBXcxg2HK+G7h3Tz1LV85JFco9M8iMTJ56woLKvG12k/T7tT7eBI0rR6KDVE+gsRMh1x4QUhdhMd7AHpP2MySeerxo7mfHBnFC/eSTbLrIoXbkWpNYZyEBsyz4UKJIQsp0Yy/FIwcszjqaPvPTD76TTm9OI7nEkrPXk6VpSpWEvmaSpxalymg4vMXtGwtmTc3/cnjAv/P0D3D68IpeN1b3nDZUOUesPXUPd/qKIEKzCdijY0xcI6oZt8oAqmoPmna12FdPhZbauL08pTfyhS+gMTKN+spOyKg8VadQmIb3JeGW0kS4mUBjmPoN6tjz6rpTeaoMkwoSMco0Dv2SMwOfTUXymfMYg1RT2mk0hqw9LZ2HTjTlN5Uu8EESYk3ZTYeOHCiT05yh0ea+jzzzEb73H30vf/flP0998qNcdgFnDB955iN810e/i89JSVctoOGwakiFkOgtVGZkGkKWmrzbMfvA+wnzitWi54Mn7+PvzWfc6QwtFU6n51nXl8SBACmV6zBT1XKn40XjZQshTEwDiuQVo+WCOT4FvvHP/DC/6ed6RBIupEkmvBOKjzRmgq1FcCmXPDRriAgk4d7Fli7Dnaf/wX7871hCbuBOPuCi1QorBQ1jMykIUYHJYFl/AdzRjGcPHyZWNSnIlMmmg+7IqaKu90yjSLVXqqeCgLKFGPfPR6dYcGEMnbJdJCBYnHFs+q/MNIzxHGO5ZyybETSGIjW3Ipyf7585sQU0BDcZ/0Z7sRrjp4TeeQfbNENM5pp6ptEZiIk7YunDEb/vL/4UebfDLOeQBv7Xn3qGj36ilPv2+sjVA5CEXgsWgoLGoJWQu/QmaPySHImWnKqp5LY1Qq6v7EbmChrGI2nPNN73tg8BcHa94u3f8xD1E0+w7QMHtCX+2yTWIRMtNDHjY6HgQ0x0GSRn5gc6Jc7DJ24+STvt3pjiqKcBO7XKU9pZHrAcNA4/07ynh97Dsnb8jf/w13HPGoYc+YHP/I98UQ33e9qPsnCW1DjqAc5CRchCo0a4Ge4hQZCUafti1lb1FdA4XJKCIbVtkafEUZFxQ8YoZd5ojXypnkr33dQj05ilWL7XFdAYRCamMbs2IFrSeUDk2TsbcqrxQxkm1RMxyjSO6xVnRngubpm5GTNznU7qqeIlCaQrTGOXNbAxgcRcZl5bUzrTh5JMG1wpZ65dWSReunyJmZvxjsNvxDYvctkGKmv4ey/8PYASAJICR40QxGBzJmeIQ2Bw0Ni9PBWH8lnctes8/Xu/ietPXPLrH/wgL3jPp9vNfaDhXE/nBRAd8QdVLo2evZ6reF7O3+RpUFhumypA8KHDxMThZpReEqYu//NrE2jotUMwqSTXVs4QlGlcrncEsYRuix2vp+aNicncyYesFTSaykJzgLhMjmZiGnUvbF62zL/uYRAhVjU5CEZlwdGqyKliNjINEtgRbE2Z3JcEUfKbYgaVp1pNB9gZw9bobHAfEfWC/nlMA+O4noW71rBx2mTbl2eqFSGFbZkICOBKH4WoEd7HEskP0BjHpimfYdFmQnSIwJEy5qjn7VQMZ+sFi9ET0umEd87OWWhx6giAS1XDf9Xb3lrOjcpfg45S3kb7pjz1S3GEvCOnGhuhN9CKgWq/GzFLnTMtDsOeabz7yW+CuMDQIOcv8F/+2C/wO//CT7GUHQ7B2sRlSEQDTUIjjoUhZGJOGKDhGQA+9RbDYD1duMI0VLydQKOZqzylxt9YcjtOjEtjhUvFRvX2v/W5vzVFoNzV9NelteSmou5hQ4Mdyq7bHh1hujJvoB6g12a1+5jGQVmU4uk92tDynp9b8wd/wBWjXpnGTkHDGbevptFDjCE4QxMjNgbWUfbylAiXM+GymuHmERMLoN70mWdfvYRU4YeE2MxAxGgW081qwbkxPBvWPH7wODPv6PEw7IipGKxXQWOt3cs25SJPSUKMJYXAJz7/EjkKg87mmOmM6RfWL3AyP+HJw3dh6jtchjXW9Xz85RKXvlaf5FqVp8FJpD1ozHQRyElI/XguV2x1Qft1x8V7era5Q5srbBr9go5WT7+JgjcV9JHBM40lDucFXM1icYVpJFo12ypdlJdqzdghTuD95XEipDKNy1wMXOtsGTcrBjJsd60ytg47LlLDHjTuccBFe8XTaA6LER4Fy5zv+Ujkv/3+18hRWL679A/FqiFFwcTR09CbJFU09VgeHqbIkzwMIEKOBqPjC3JIk6fRub3ZcVcD/2qfGOOdt8o05tX9TAPruZaKn7NTKSn0BwimbCCHdmIa2Io+9QilB6kPCatNhY04LisFjQ5ScojNHBkFRe2NkSi07ZKl+hhmVa7Zer1mpd3mvRMysNJrdqwz16XRZ11BdZcc/k2m8Yt/9HkHUZmGZFoR5MpuxOj0MCduKmeMYmiOj1ld/j6+uX8KLl/hH372JWbe8tg84EUwJtLGUEAjJnyAwRqGlAgplsjp9gU+8aGOj/waXdTGfCqBHO8HDdPMy82rFVRFnnJ4cz9oYDyXKoeEHPjoBxzf/1sM51ZD4rxFZr70LWRPMy4mx8cY9WxmgyVqSWXV7D0Ne1AW3Hh2Shc73v7z50iCn/7gisPf9tsAaGudCDzENzANgFhZqhDwKfJalwvTcA1DDvzwr674ga//7SWGoj1DvOe6i6y7oEwjIzbTEzC6GDxQz8ki/LP+LrcPbtN4S0cFoeXlsx0YiP0oTwlrUc8llmTbXhJBLJLhU597hhSF3vnJ0wB4/uJ5bs5u8taDX1lOcf0SW/MZekWACTTqOAXU5STEEBgszKYyWIidGsmrAzYKfA9guRYja9/RUmHHGH3bT1q9GTK1raGPBAdJpZRwWhihWew9DWMzvVYtOS0lXrZgY8Z3A+bxr+fHHv+PeXFQZqK9BK+aARdhbos8F7DkLLS7jiiWHDqsTnIcCztitWDAsW7faISnIHiz4uufzZwvDNffsWb+jsfL7VE3Kk/pojqCQ66YN4UlOeK+hFifgxQFr6w5DXECjdbt5yOf6hJXuQQKzJ3KaY1/HWgYx/UYuWcNnRvwsqAPBosva8Gw2zMNWzPEASuObR/oQsJoTtZMHOuqXJN5CylaROCQ+5mGi5DDAQv1cqzOoNls1tPc9rV4gpeJaRwfFGP+5afm3Hz3BZsTDdBMbzKNX5KjTzsklp3NYAsllSs3ltXpYRajlSmGdTVHRDhI72GZS6NQtXmZDzxxjQfqAS8GMZEskWigDoEqKmjEREwBo41/L74j8sJNre4Zx2iaPAUD7pmG6rQ7jSzIllXj3wga1rMRg9ct2qPXF/z4ew072eFyZuEE5gUkUxKaneZqHR1qLT+shgVx7Cy+ChqH5QaPp2d0oeXmi1teejzxN3/HMdXt2+Vz6G43by/3zV7jEQPJCXaI+BR4tU2Fafg5Qxx47rGGH3/4/SQMbF5DZjOOdNBFTjXNANFBz4DogvtQU0B9nXqeOHyC2hVfgGHH51+7LM1zV5mGKdKDT4Vt9BLpc+l8Dve+QI5CZypqvweNly5f4ub8Jm87Lg19tnmJtf2nNLb8fK0VRUdVASAoHf0pRAYLc8lEKRVNqdWU0tWS7bi93p1xFBOdDQU0lGkY0xH0XpSYqG2NaXuGCrIukuFMQeOKpyEmM7wONBZt3rONBx/lM499J0OkmLljsGOCZcw458uMcu0I77ueaAzEdpKnGr3dwrycz4udylPeTEyDBDNZMuvgnz054+Tda6wWTISqgSxUw+g96T2SKpaVA+OQfD9o5BghlUgNUKahnsbOhuk2O9Xr4Vwg630S1CP0r19kjeNaGLhrLa0bqOWgMAipy1oQWiT1JASMpU893ngudgND3HsatVjONfx03kFOFjGZQ1Ungva3VAFSOGAxMY3yTO02lxxqdeaXOCQ6WOrcnqPlTSpT0cxm3HjHJUZHBGyjvf/5+hoeb4LGlaONW1woF743pczOXKGwXkHDqXmdneNSI77nleV5SqzEg7tnOJ5X0F3gxWIkIhIJFppuiw/QO0OImZjjdBHKYD2t81amYTRtFK4Y4bP7QSNZz5Mnyz1oxJFpOC6N4VfNH+Fac41fnxtc1miPnJk7kLG0NyRmChru+BijVPowLEnj4Jz6K4DG2Rn1vQ2zdeD0JDGk/QM7jExjc0EfX8c0PvFXSLTYfqBKgS9vYym5rRaEFLDiSBiG+hg2r2FmMw61bJJUUw1lhkafB4wawzft/vNNTCN7CB2ff21TADjvjfCtvQmSqVIuncgS2aai3dvzF0hRaG1F7ewEGkMaOJmdcHN+jdRfw64+zV1+hg8//mEEYa3JuUc+3Mc0UijXf55zaZRLQtQduTk4YDOCRnvGUYr0ZijylJr42I6gjXgmFKYhbWEfaazKuVdkRDOfl9JfsYiFoJ6P06j+5a78A0WKHGWabR8n0PARljEhzlFZWyLPszB0fWFjsceNcoxuvkfQGJnGVD2li/3xUGGAQU1cGc+pspum05kVVzyNRe3AeiQFnLkCGt3Yma73+hDJOpRpa/aNt2daiGBtnAoIxkbTsfx7Oqzn2tCzM4ad31LLIV1MOKlpxWBCi8SeAQ8iZZCVrbhoA31IuNEIF8t6rFBsoQqR7IRVHkHjCtMYrjANnWq526050iKaL8kBwWUWrVb61TXvPXkvT9Sl4daqCrCN9k0j/Bf7CCkwpB5zFTREpmweAHdYFkGVkInes2nKju7aouYfD28hN0d8c/wZjmceujVeHGISjExje4aLsDWePqYCGuNcbTIjse6UaRTt9nVGuIb9oam1f/bffD/vunX4Bk8DW+SpE9Pw49/x4/yeWLHQJ7LKmZnLZNVGCYn5eGMeHWG0efEoznC6Q2quGuFHChrnFzz8Yvn5xUliyHtpIOrOn+15kaeu7uye/mGyhUp32y9vI6m7LEwjFdoPMDQ3Cmg0Dcusi2zwJULbZbrUT1r1sdlLibcPC2jssoew49nXLqeQSSgG48beREQrU4COMm+dLCy2L5KjsLM1lTUTkwC4Ob9J7QyxvYWbfxHIfPd7v5uFX7BW0DxwcfI0SmZTIFhhlhPZCDlB0h25Xa3YaAghu1OOYiLYIk+ZcTSw6YgjaMTEzDXYbijzOfRrh9NyP5j5vOia9bKwK926O/U0Fi0caB2HOz6eDOFdH6dmPxdLQB7e450QjSVnMCkSxRTQ0M8znr+ksfGjET5TI9zoA3NNn60wgUaNEeg13HLRv7HkdllbMA5SmK5f7vspTHL0NAhxyoXamp4TlarOtOTZ2kBKlpwzwwQab2Qa1/UzbPwFnlXJ0DI1W2OQsMOkYep/6lNPbSrW7UAfE2Y0wsWwyx3UlnmXObnckGaGpVZcBgXRKkCOq8nTsIcFdHO345q+9hVWBJuYKzM0VcX3/6bv548/+CG9pgU02uzflKd+sY+NdiPboey0BlM8DTeaj7OaWhdBp4t8cHvQuLGseHUT6J74MN9qfo4H6g5ywhuHSJxAw4YSFLexFUMsnoaoPGWuMI1+9DSMTFUhaQQNjR1nW7pFR1r8Rnmq4tIYFlL8Dgk9C+1Mr5RpZAUCiWmaQmiPj6feiKM4n4b51FfkKXdUdkXx7JxHX+xIBtbX72caUYcMmd35/Z5Gv4Fnf4LsMvNOe0EwbDcXUBXQMMrm4ryAhsznzPR7VVo7PHjoUo/oDvIo72/nwjQMu1zB0PLcnQ3e7gGt87BzJ2AyqiQwmMigmUsnfQGNra3vk6cAHpg/QO0NafcIAG91v5Nby1usqhXrPJYzh2IeoxU/yjRmOSpoCFFBg8WSTRyTWc84Tonke1oqRCtrsnQk7V6uU6Z2NaYd6L2UHbjJmqrKNMaXaoXYMpUQmKL6ly2sVO6wx8cT09j0oUTUA48Os1KK7Cqq0QhPYFMiW4dNPX7cWSvTSMti0n6lkluAY71ucbyNXIM1Ql+XzzvT4o+RdE1Mw1hIAa8Gd+66iWlYNZwZ4vScbKTlsXEmeR6fo0BOnm0f/8WgoWMLkgmYXDaJXmq2YnFxV6b6ychYempXcbErTMNOnoalDS25Nqx2cH27YZhb5srYB/U2loOD7FiOcetHmiQhPce6UXtNlgQHM5VVpaowYhCdH+IVNHreNMJ/0Q8jht/95O9B2nLjDybRGoNT/dEeLKl0R+S16/NTv+7DfPTrfxMAN5Y19zY9dx/5MNfkkqfWPw2UyiGRCEQdJYrKU0KImZQTRi+DrVdkESBNoGHMVaahD8Bc89m3OhZUZZnXy1MRYWcMy7HsJHTM875cs7EZlGlICCx3Rb0xyyWiQHGUGqyUP89m9XS+pG4wLjGcn/PElxLbB+dYmxnyHjSyatZue6rNfboafP5jEDvwhoXuoAbjYP0KLB8ooDHOU57fgMtXMU1Do9+r1lLVnRf6NEwG57GuHyf+gLmfUzvLNpeO8NPtgDP3g4b3K8QI1ajJW8DPyNnwvlQSgS+lLkb4G5iGZTh/H92rv5En62L8L6slazXEl+aqPAU5BJ28F8BASoa02YAIG1vTj3ShPecwRqJp2eILaOQM0pUUXqDKiZVfYbuBrjb4nDE2E+/e0/tDQUOZxhjsZ3UX7SNc18gre3RUGAGFaURla795eJycBPGVVk8VI9zmSF17bB7w1ShP6YlflqDO++WpI0SZxpGCS1aTGFdhROh1GNXs9c19eQSN+5lG6vtpQNbINGSIk3y7puXREUDSGP1SGvE2XWAIo6fxFeSpuGejEhU0TM3OWFzaIWkg6LUa0kBtKy7aQeUpBXWEXdiRa+HW3YzLmXZRMw+lCjDqxL9VLPfUY1UiIZhDBQ06rucCMP93foK+aZipET5NuLTlWfRBo3feZBq/+MeqWvG9v/pP4XalDLDTXenog9uDFZXuNkfQeOap9/DywyUW+/qyIqbMp+cfoM+Wp577K+W1xoN6GtGC5EJLB4fKUwEZQWP1kH6avN+xG/tGeWqh+TLbO/oat38v9kxjE8c5ByNotCxUyqlyZm4zKNMwMbDawTATJAesPoxHuZnyk57Z/Sx//Rf+Op+++2kwDlsn+rML3vqlzPaRJVXOE9jBPkG12p7dL0999kdKRs7yiIU+DHF2l2rzEhw+SkgB0QdTViewuYOZNbihKxHwuuu6HNWysdktDPiceWJWgL/2hm3yEFraIeJ1pkKinP+5rxFrqcbqH1NYWxZHped/LXUpuXX7edUnsxMab8hxRX/3N1DrDnPlV1xq2WiVe+yYd5WFPEQFjQGxQky2REesVlx0JSAPgPaM45jIEtngEDLEniwtjB5Cyhw1R9gu0FVSQMPlfZighthRLRHDNG5Uun30zYOneynyqqfRqXn/hDkuwVW+0j4NR85QS8ZVHpcHvH7vUZ7Kq1LZc3/11GqSp5Z6/6IZbSPTaCsNr9SfWxl7WSqWV0DDfyV5ymWiyUgfpuqpi3zJ9RhZpMxWy7WRgZw8l11gSPfnoE2HVk+NRwpjDE7NTgxOp/qFK0yjcRXbPrIbIpUvUlqDoY0tuc48pvNNN/MZ1XCJFUuva8sqlO/9aBXZ+RpRf3RGzw3Ks3suDX3TUGulnWisCnruqzgyDf+mp/FLcYgIKy1r7HSBGSUNe7Si1pvbq066Ts1UsXB9WS7mZ08zH0vv4+DOz5XX+vkkTyXtaK2i0FsmppHEw+oh7LJ0dFsZJrYgxuznBIxG+FJTVTcKGiPTUE11HIp02Y9zDq4yDa3Zz5nGJmh0cU4FNOKs9EuISgFHyaNFS/zvz/85vu8ffR9/4if/xAQau3/yNKsW2tsrfC6ANc7JMjpzpG7P6ELcV3c8/3F44luQxeFeq735D/m0aeHoUY1n0LkbqxPo10hdk3Y7bh3PqLWr+1znbR+ovCFhy5P9wPsOSgNU4yzb5MnDjthtsMo0ei8gJbkW56l0axtNiX/P2GnAz8XINK7IUzfmN+5bcMbJegfVAWv1IAgtlXbr5gQy7JmGGIjJkdZr7HLJ2a7fM43dGYe6qHXawMWwJUlH0hLXOqcSk99F2srgYVqYgam5knqJsXmaeW76PWg8dK9Ik2Y2uwIagZ1KfEbsfUxjEFsqoAwY5/B5wM3L+9wYg3oPSvfo6GnUzoD1mGtlWNV8W3bFRypXYSusCK3KmPWY62QEQahsxVtuLkpsSAx4rYrK/TDJU2IzyYG5YoQPJnMUEwcZ2niJt0LMxfva9pEh/PPlqWtpDxphUNAwDa0x+NRiUiBeAY2Zjhm4t+nLom0cM4QudESfpw3JxXyO7dc44xh0bTlmzrtuHXAQWzauIes9tpCWm5RzJWaYSq3hCtPQsceLUHysjjc7wn/JjgN9dnv7etA4oqpmSM7UupO/mxbThbqhs6o/9+ol3zX8R7zy738C/vhzuOZIE8tiGSGboApCcKXEMeZIb5bwRz6FU5q+MLsi0WTAmDcyjWWhsXt5SnfauhueQEP1zqV6MISWGbpDyZnGZkSZhg2B1RZiU4bNjIvQYSqmM5RF9due+DZeunyJJAZbJ/J6yws3oHvvDTyQKRVhAOO0tPnu3v2eRnsGixPM6oi5bj4HW2IfOHpMmZKyFF2IjIfU7rh1NKNR0DjTqIbf/41P6S/Z8dde/jJ/6HaRi2qvJbehox7O9vOw9SFcVg0yP0JUJogGvK8QhF0o5+lMZtTelL4ICiOduRnOlsh02O9Yl9WS9VjtNLQ0WpmWk4B6Gk3QSPdUorPNwQHnu6FUeem5OVaJ5Du+5fb0u5K0iDKNOkaO6iOqPrPzhfkqyURmM0TBpTCNjEkJawTafeDig6eZpA2aM783wjdjUYYU41uqpiy6Kk8tHIj3VAzkgyVfvFka2JCM0R6CizbQeIMZB4n9W3+53AfrUt3127W5DldjjNCp7Nvopsg5y9zPefr7fivvfuRo8jSqCTR60ihP2ZK0YIY904gGjlJimY2ChiHcNzBJO+JfL08ZR51hqaA99ApmtqET8KnFfkQGkQAAIABJREFU5sI0cs4MaWCuoDHEXO4D42kQ2tjSV3sAurc4RLpzrFg6lafedniNH/yuX0PT7bj0M7a5/K7rXDAb5yFIYNjXn+xB4/AWACdDGXfQ4/+/XXIrItdE5MdE5HP67+N/zut+VETOROTv/GJ9tuVYiaJg0aQeJJeKIlfhc5EYcA2XqZrSTm8o0/jcK5dELIcnj8H8Wtn9S0QklAE/WFws8sgQEynHYvoai3Hldxy4ji4GbAashZTIKe1BY74qq+jmfnlq1N13unCN5v4eNDoWOtfBU0DDqKdhY2C1y8Q6l0l3BrCGg2QnpnG0eID3nryXIQ3cGS6xqk3/D7/ZMjcGr9JGP+bzKNOYd3f38lTO0J4Xg3RxMJ33YEtAJIePEWIZbuOM4FYn01fM2x2PHM9ZKgu5p6NT5wq2DLsyZlt3bI2zdHgkdsyHM0RLNjv1qRZ+pvKUNmoa8FVFjomfT6UPYyMVld3LUyezk+kzjw/puPisqhXroGVJYUczMg0q0Oa+KvZYkwjJki4usKtVAY1RntqdoY4V56Tpd0XKOGAkU6fAkT+kDnDmAj5nRgtoMsEB6gOC8/gY8VZIu330zck5ZK0GHDOYNn0pOYYSlUMSxJfqsUEsZJhbwXlLJRFHxc8+pcBgMkav1cVuKNIU93+mal2M+mNTdsejPNVpyW01goZxzNxsAp1JnjJj6Xl/H9PIVrAhkbQ6LFhYhszy/2nvzaNku+r73s9vn7GGHu+kO+hKuhrRABIoTDJoQIDhxRYJARtCwmQTsJXnDLaRh5d4OckKie14rZcXv4TYsXGCnxMnz4H1MjHEOHYc2xEOAmQMYpbQtXR17+17u7u6hnPOfn/svc9QXVVdPbfE+a7Vq7urTtXZteuc/d3f36g9epkhjUHWQ2emRH9/nCPcbr4WXffMni174sf0RIiyLl42IBWfRCdoNK2g8PMZpeER2cCWFUsal+I2nWAW6V7CVz7nMiPN5qWJp4Sot8pq0GDFmllP++cRQGWK0E/ol6qduEAF5kzJ9uOJ6S7YJ1j/eXYJ+6U0HgI+qbW+Hvgk49u4/gzwl/ZsVBSk4SI44mTA8T+zxMIbH8ALQnw0jbQHzUOV3ANHGl85t0Ij8PJsU1/5aBKQlL7y0AvXWUe4ZmDNU2K3wJ5dmOa8Lr2kj6cF7UpRpGleslvC0PgEOlXzlDOhONJw5qmW682R9mgqe4NqTaw02IvQTxLmVyFrZjDoIgIqDmmnChepet3ijZxoG1PDk/0lFm9YZfDOV/CF00JTa0JLGs6nkjFANLT6F7mw2udQ21ayzRKIZ/PkLiiSKZ15SmuPVuQjbbN7FS8j63Z5511X864Xmailx2zV4dj5G2ztqnw+Ao+urQh7WJ834WkUSqMVxhD4zC9bW3gTojCENOVTzdebt/QCXnnD4XxujzSP5GOO7HfsbtaZcIaVQccs9YMub7jT+Me0CpEkJfMgSBOUykgyRbqygpqZYakzKPk0LjFviX3JBmAPeitoEiItKF8TZSkLtn3sip9ZpWEjpMqk8ZL38LW5OwmzAYGn0GuF0lAasKRROMITVq15yscoDcKI0FcMlI/Wxn/iBW4VC3j4ehvVo8BrG9JIMl3JtnYFLP0l46hfUBfy70mJ0LNzO7tkvr+1xajiQyp8GqOVRuaZ4JKBzfNIPWhniiYBPb1K4IktY15UpC1/b8V5HGmY59fWzFzGXkRPNKHu4ekBiQpz83ErKsyWRmn42LJTXLKbqqWZQ/T9NugUXzweF+NnmbcKN+h2WA1ilhOPp8NT3KM+Y4aTBfhBn17Z9OiURjzLqpqhQRctHhnqOe8IfwD4kP37Q4zpN661/iSw+/0LS2i7NdrOTCNZY/7MGtH1NyFehK81jbQLzcWKc3e+EaAEeknGYqsITQ1UYLIvJDPRNOE8QZIx8E28uNYpyi62vg2jm/G69FMbo2GVjE7TQmkEgSWNqnnKVya01vV9yJVGJpBlkPZpiiMNiLwMFbqs3j5zHcgaaV7TXzVi2qnOSePmo7dyomVI42z3GRqHBiy/zJSCaGaaQBVRJe63pxXNwRJZlnJyoQFdawCP5/AbxQI38E3uim4e5txKh04P4wRtmYgcJQnZ2ho3tHvc1fhTAL5mCzk1SkqjPB95RjhwXC7g2l50fYXOPJphgHg+i5fMeM/Nial1lGUo+znvuuUEd5xeIFTGbHW0WSiN2G4YctIIZsjI6Ngub7debcau8Y3N3VOQ9vFVSpKpitIooqeWmLemsCUbLrratT0VUkF5mihNWLAVY7uh8SuPJI0Td/DMzHUEWUroKbK1tbyqLYDYXBuXp9Hpp6y6SCsxyXwSNoroqcxch4HLXdIBXz0Oqy0xpNEsGgCVlYarRSYXztP1AtZsuXKjNKBvnbqtS128MGPtUKNKGp4PWUpgc4dMcp+rNmsqMwQJ9Pqu6Rk0U0WDiL5ewfeEftZDa6M0klTjKTEmuzLsBu1QmiLaY7VrFbzfoCeaWHfx9IBMglxNt8IhpeEFefXhC5ZPlucOk9iyLr4ovuobM127Z+/7ziorQYPl7oCHo5dyWNvQ6TTC97t5AUYomaeAC4HZUGV2k/Rc92kc01qfBbC/j25w/ESIyHtE5GERefjcuXPbGljLVXu2MxPbMEX8CLyAK5OEq/sdaBjScLHRSgmLLXMBzZeaNUVeZEquS2J6HPf7pvS6b3Y8GSmetd8re6PMqD79tI+nyZWGToqQQhWGEM9S9IEtztfwG7nSWB4Yvm1rbUJcgZZnTQVaEymNrxTdAI6sGILJGkleSlw1YoJeH5WYm+e2K27Llca31ozK6dgyBo0sy81TiY086qd9lFYoMuZZ4eR8w5imAOI5vBJpJJ5w0Z/j0bPLfP3CZS53NFcuNqBldvZKepAk6A+/ley//hxgwmbNZ3akYc0vdtE1tafMQcflfNU8pQMagYd4nhMgnJuDhi3gd92M+SxvecUNgAmSOD17mpsWi37ghdIozFMAK0qZxk+uK5yEqCRD+wJpH08SkkSM0pidNWU3XDb7oMOMF6FEsWS/s9WeMedEGYividMBc7ahUS+AEI2yC3mFNADCEE9nhGJ8Qv7hw3nGtdisfrfAd/qpKRwJeIF5TlqLnJhvkHmBiQJLU3x7fJaFaBG+fMscwXxYhFTDSKXBYMBq0OCjR98HfgNah/HE1PfCquF4sc/VzSNcNXtV8RmUD9mg4tPQvUJpaF+s0ijKkFxKD6PUAgO9SuBpNBlkhdLwhwnDfGgAbugPaHIKbc26TT8mFfDp4+sBqQryWmMzYUlpWEe4e+Rcw+bpXHGc1qzZQHgIz2RrrMQUeVGdVTp+zEov4bf0nfn76ayB+F26paTUMmksOdJQNort2U4aIvIJEfn8iJ8HdvpcWusPaq3v1FrfeeTIkY1fMAFNOyPOPBW5hciPwQv5tSef4vsvXYbmocL5ZeGc4WWlMR/N09eriKRkysbmA4PAOOQyMmOrBjyXGet3GWQJvtbGpwGQJoXScOYpB1WQRuybvg8Aq32nNFLT8hRo2k5mgdaEKsPDlGN/ngvxjfp5Bz3VaJCtdfBsldSbj91GM2gyF81xtmtUTseeq5kludJwu7Bykt6crHJqoWn6gABEcwQV0oALXotnVnpAyh2nD/Gr73oJhKbMt9iEqOzrf5iHW7peA41wmDSs2SpQuXnqCrlQkEag0No3Zhm7sF9uQC8UmpY0XnONIYC5+XY+xo++4aO87Xlvy/+PhpWGJY3Lnm9Uj31vjY9Kbdn1/iqeMk2J0uVlvJk2S50BjdJceEGL2XCWJZtjsGqJNs5AfIiSHjO241fPOcLD0aQhtrVvU6XotS6q2WTNLmbKJmh6yrSvXRuUSMMpqtYC1x1t8777DHnqJM03SonN8P7EA9/F1Z/4dMXc0yiV35EoMhnqQMePePjQd8ND34DmIkoJmQaxfqZ4ccDfvuaN/OzdP1t8CGueCm3L1qxknjI+Dc/Uc3MZ5R68T/80Z9svRZPg+WZ11tpWpE2z0aYce/2+b+kSt8lPFp/FbuZEevh6QKaCXE3PlkyshXnKXGdP2cXkVXe/gHe/yjTa8qy/Y7kB/uoAnWWIVRor3YTf7Z5h1TP3dpY2QXXGksalyERbZrb8e6vcxmEXsWukobW+X2t964ifjwBPichxAPv76d0ax7RIzp3jsfvu49ZHPgVAancijV7HaGDPNzZYMF97c3FdPSXn15hvFl/sXDRHL1vJlUZ6ySwAiZeROEd4bp5y0VM9BunAlCuxC6BOU5MRLmIWo6hwIq9TGtZMszJYQTQ00izvKdH2zSIYWaXhaW1MHE+Z3aw0NazZTPNmg2x1FT+LSAXmY7PInGid4MmO+co6joyydF2eSD/t5/kWc6yuUxp+o1iQBx5ckCaX1kz/6rk4Lua2dRjVN8omy8K8N7QrFR7b8MPCPOV2Xl5unrpWzpLZBbTnK8gCGqGXRxo9Yzm4bXfFumNb9ZbMOUqKzoPm/Z0jvIieAlgJG5D0EJsxndlCefgKdIooTdQdIFqjZkz0VNwomWOCBvPRPEtW8XVsP5MoNQ7vaNCnbdVfN4BAhYhdpNeRhvVZxaTGPNVo0LVmPTVfbDxakUl8W7YBP57dyTu15HJOdD8lsOfq2QizRriABKEJlbXTUzFPieQmqn7YMLt8G/ThKSHVGnHf5eIA1VjIN1JmoM4RPso8pdG+h59oBtY8JX5AFMSI7ZeiArtR0QGD1JiFR2ZPW9IQFRD6xT3ctGZjUQPrCA/zjdFMyacROKVhletTlpzDkydRNiHXLevdGPTlVbJOB7KMThBzuTvgXCfla4t3ATBI22jVoVsq9V6+Hi9FRvUn9r5bV+p9l7Bf5qmPAm+3f78d+Mg+jSOHmpsjefIsV/XN4pmbp5I1ozKgsjgbpZERlsL2DjmlUTJPLUQLaDLEXzFK49IlMiV89mpT5VaT4UnVPBUr067URxe71YFRGhKGZuEqK41Sob6G32AtLaKnWghKJyXSsI2RtCaUDB9DGso2ppFmmvtKVLNF1unQGJwhU8UFeaJ9gifXngKgY00ozSRd59PoZ32UNQ+davTM7rNEGlGzRBo+XJTYmGokyUMZAWgdQV34gpmHF72HzHYUXLBTX5CGUxrOEa54OLuBvtfkdvUVtM2z6fkKrQOaJdI4N2t3ujbiySlCVV7Mh+DMU2EpTwNg2TfdAiVwrUjd92ur1CpN3OuTiqJ118tZWuvTLCkNgiYL8QJLNhJrtW/MjHGq0T6ESY+wb3M5QiEMGnkf9fWkYT5Pk4ysu4ZqNOg1LRHMF0GLC82AC6t9LlvBqdfcAuxVfmdJkvfR8Adz9J7+Tm6YeVkxdPtcHFSXFtcT/oqTh3nbSwvTk6eENNOI9cn4x5tw8kXViVY+JH0CW3nZ5GmUzFOeT5hC0u+iRWhELRqhh05t/o5v5k9nPv0kY5Do9dngUNzfflQJx21Y0khURqzXyFTh04j8kBm7w48849OIbcjuF04Lj7zuNK27Xg62eKcjjUGsSZcukT5jNkMXoxm++KcrJJnmazf/AJfv/XskaZuUDmulSgauNhjASmySgV2y4bNeaWyADwCvFpHHgFfb/xGRO0XkF91BIvI7wG8ArxKRJ0Tktbs1IBWGeAsLBM+YHXQePZVpCBxpFItz7tPwJisNtztX/jKZPfZLr76Jbx3R9BJDGsouyJ41szTokmSJSZx1dvE0QfcHhTytmKeKiyX24twRvjJYoY2YDn+WNFphiTSU6eXhduyJwoTROtJotdCrHdp6gUyKcxxvHefs6lNooJP1EIQ47ZvGQBRlTAbpAGUv6GtcQkZOGrMErlovxjx1kZClzgAkGyKNo3kpiuzQbehUEE9zs718G440+s6UWERPnWOB/3rF9wGgbYOhXuCB9s1u2M7vOTudgV8ljfLObhhjzVO+qXflbvCCNNxO1rz+31/7Cr7cOsaltYRWhTQazEVzLNlAhlWbb9PIMvCFcNDLy2iYcijNvBqzao1RGjpDd9ZQcUzftS1emM+POzYb89TlLpcHmgwhW3OqzZVEcJuXLB//xZ5H//w9zATFtRhYhT7cqyInjSsOcevJ4nhPhExrxBe8OOX8vT8OjXmqL/ahv1o0Yer1yLo9UAoEdOCbxmb9HpknNP0mrdAnGbj71l5zOjA+jSwbHZ7q7iMvrDzfsmbjrihmWSXzwnxjFKqQWRvF50JunXlq4AuPP3C7aW0cugrZZn6y2FSIHjxt1psLjVk++4TZsB696maiu96HThskdFhzRRmDwCT7WnSaVmnIt4HS0Fqf11q/Smt9vf19wT7+sNb6+0rHvUJrfURr3dBan9Ja/5fdHJd/9CiJ/RJd9FSs9USlUZa5h8b4NADEW+PiXExw5ZV89Y0vBtVntZciZPhWaXjWoRuJVRpa5yYObUNu851GRWmMdoSv9FdMNng6yH0acdiC/gKnksQoDa3p2qqjF9vgC0UhxNYMWafDYuShS07Ok+2TrKVdlpSik/RoBk0kHRBameychP2sj1h760lXPKdinipIY+DBORrGPKVSIr8010duRM0bG3smpmGPeJqXpwFHGkcmKg2A/9L+bj6TnSG1BfW6qkHWP0Qj9AulMWd3usGQ0ogL88MwXI5Obp4KrHnKDyqO8Cx1Pivb16KZ4h07wodvfDX/4yvnubw2YLYZFb6pIGYhWuDiwJhVVm3odDMzOQnBoEdmzWfdAPz2cdScKZU9rDRcL/aYhKzbRRoNBnZz4y8s5scdm415ernHci8l9bycNNz15+ZJD9J88b7genKUFlh3PzSGSEOatj94u1153FOmBpsstugca7B285vXT7Tyob9ietgoMeapbheJIs7JAoOgTZBA2u+RWtJoRz4DSxpaOfOUVRqpHkMahdIoK5G23cz1RGhJD11SGoEXMGOrKhjSKJQGwHzDfC+ONDzr8JcYkqUlkqdN4M5Ke4HPP2nujTNH2kS+x2JjHtB5noYqqQyAtYYhjQGONJ7bSuNAwj961ISmMkwadrdZUhq6ubjeET4iemohKkwA/+nuqzjzH/4/oplZRCWcW14DyQjtLs6z54mkh9YpYdk8lUxQGqVxxX5VabTEg6xQGiqM4Ss/yFsvr+BLhoemZ19+sW3rajmfRrtN1ulw1zULtErFCo+3jSx+0vdZy/o0/SakvXWl2QfpAGXzQo6HdufavWTG68eouHhP7QUs6SD3aQQl5z6v+luoN3/QHJeFpjWop3mzbvCxv/CxvCT1MGm4Rf38muZN/Z+ic/NfAGC1ewvdb73FRE/5VZ+Gb/0eWce810SlYUkpHIqeWvb8CmnoxJGG7ftx2zLX/foHac7P8pVzKyx1+sw1gmJzEjSZj+a51F9GA5et0phJMzJP8Pu9fHzdEIIXvAW566+Y8a4zT1kCJSNbM+appG3L4ZRI4+hsxNOXeyx3B6RekCcCuvnBXuc6yaxTD87bfUBQikRyi3EjHFYao0lDWaXx+Z/6N7z59p8i8EcsfFZpAKTKRCBmnQ6q3eJV2S9wuXUVoSWNzBOaQZNW5NPr2Q2AVRo6M+0IBkk22jzlTLBegK/KSsPM6Zr9nFoNKQ2bIJs7wkulSOZbNqDAbmxc9GzQUOhOh8ETjwPQn1+kO8iYif08oOb9r7nDPJcH4ZUsHUAWL7CqI/oExIFaH0K8S6hJowT/aBF5lSpjwlFQUhrFl5ZYMqg4wmfWK425qFjcfS9EhSFN+35PryxXSMO38jikC5IS6Czf6WHzNNaThhQXO1WlsTpYpY1XURpe0CCxIlnpFD/LcvPUxRkxJjGrNKQ9axanJMnzRYA8V+NJ36OTDUxG9gjzVD/r46uAVR1x2Eaw0LtsnPgiSCnyJAqPkOgeS2sD89nLpCGC2OzxLPPRiUlyEy8yc+bMCs4RnveFNt/NUqfPAJ/A+id6XggoI+ftIvX0CKUhYVgxBwwjd4QrRx4hsRez7HmV6CnngwksIYmAmjvKmSMtvvjUMqv91Gw0nPM1aDAfz9NLe6yJcGmwiqBo6YzMt6RhF/VeAKEfmb7ggNcq1BuAZxtnNXSCXltDNWIySxrh4qH8uGMzMf0044mLa2SenwcCOPOUK2ECmHL9wOOXzeLol5WGCyAZNk/Zufdm1iuNNNMM8OhLOH4xz0nDo7/WNaTRbNLPBMLYKI1BzzS6skpjze6GEnHmKac0xpin3ObDiyrPtyNnnrKk4RWO8NALmbWBBYFf9WkAzLdMhBN+aGptWdNV3LDBBF/6EtJo4FsyPXOknQdbzNu1YxxpBL7Ht/Rh1rRPa49UBtSkUYF/tEgXSTxy2+Qo81Tfkkb5In/5tYf56/ffwIuvKXZwC3GhNBwpNKyN9NzqMpDlphgXMRJI35KGzs1ROicNOwYXPeVVL6SG3xhSGn5FaXhhg9SGwZIlefQUwIW2aQRF57yJFGu1QGuy1ZXKouGyos/7AR2nNJJ+XvW0rDQCFbJEmwWxKsCWEAEqSkNFTZCEpy53gSSfq/x5W4Qv6/XJdGi6wbnP7o5NuiZHQ6p29Ysd67S0aqlXyhh3n+uZWRAEz37H6aVLqJkZJsG9f9lE2Q7bLCtloqecT8NWgfVLiWDEc5w53ObRbxnTyVwjyPNLnNIAWAoiLicdYtUmJCXzFX6/myuNXmASSJX1iQwrDc8qpUinuXnq7N038YuvUUTtYkNzbNa2s11aI/OD9eap0qbBhS7f/byTvO2lp3nl9Yfz59xcRMPmKfv9qdaQ0lBCqsnrQY1dzK1/J1GKbseRRosk06Y+VgrpYECqzP3Vijw63QC0yknDE+fT2Jx5aiYcQRrWBBuogJmK0vCqSqNREDNhi8DmVrWs37P7xS/hHz3CjPWLXHu4IH234XQVDIZJI/QVfz95Kx9pvZlmtDf+DKhJo4KgRBqpIg+dG6U0+tb5V7744sDjh+6/PjeLgNn1uC50LrrI1Yg631kFyfLjXRRVoHuIZIRkeZy9MU+NUBpe1c4Z+3GhNPqrzCgf0iRP7vPDiCQnjbRKGjNickM65yFo5Pbx9PJyUQSP4mJe8v2S0ugR2kWv7NMIvZDLusWMton93csmMRGQkr/AD2KQAd9aWgXRuanLwe1UdXcNrUPT2McdU1Ylpe/IKYGlVVt11ZJU1zXLCY15ahAHrMbgS5Q7q9MLF/BmS2HNI5A7wlV5gZnhi5Lwn7OlPPAhc/0bHGnEc6A8zhxp5XWQjHnKjt2PC9IIG1xKu8Rem4CU1J4zvWjeP/XEkIbzGawjDUuQ2QDd7aLiBumJo3zsRapCzMdmbZ0sDdr3S6RRdYQDiJjP80OvvY2/+4bbODpb+h7HKg0b/jrs0xDIsgnd9KAS6FFVGg0TeRU2CBLIkr7JBveNearTSxHdYIBxMPsS2eipyXkaw47wGevTWHOkoYJcTYdeyOw6n0bRU8Z9j+aANp4ljfmWmbP+179OcOQobfseZ44UpOGi8cYpjdBX/FZ2B7+nb6uVxn6hrDRSr0waVZ9Gn4CBshJ/gyxMEaHtW4Kxi5tTGhc7KwgZsV+UAQHw6YIkhFojbiFJTUZ44Qi3C9rQjrwccrs8WKYlAaT9wjwVNcicUTpL8HTGWtkR7sxTfiPvy5AuXy6ym+3naAdtljyfTpYUSkO5ip9FnsZsFLOi2jQzY5evKA27C049MRWE1YDzq2uVuXJwi2G2ukqW+SaaKlcaefZMhURDTyECyzac2JUq79ljmoFHcOIEl84cBTGluJ2pL7l4cQrSWK80Ts+c5vN0+ZFghc9d/GPz+azSCFz2sI2oO3OkWEDnmmOURtTicrJG058hwOT6AKTnz5PFRfOt4MQJU332dCmTmkJpNG2DI9VscNXsVRxtHB0ijWLhzxpN0vOuRE015Nb8U5Q2H0bu0xgTcqvaQ+YzZ54a17cbKtf4wPPor1mfjiUiHcV4GmS1S6I0zcCYp1b7CZI16XPJzlNoq9xm6yvcQkGMpZBbXwlNe7/23ObAj/KNUTl6KrJ5GipL86KFZUsDYQvfmq4W25bc0xT/6FFTMoeha8KZp1wF42HS8Arz615FTkFNGhVUzFMKYrcQDZmnLssM/WyCnB5CO1cldofrmYtwNemCZMRB1Tzl6z5CSoDOC5Q5paGCYaVRvZBiLybJEvppn7VkjbYKK+apIGwAYtSGzTrPfRptU/2WbABBnIdvZpeXi9Bfi/loniVP0dGF0nDhqq6MyCAbcHphlhfdeAavayublkjDKQ0/jGl4EYjxZ8AI0piZAaVIlpbIUmWVRumzl3aJDiJCbBe7RuCh7K676xVK4+hDD/HHP/lGwBQwdItjeuFCJfltFIZDbgF+/p6f5xfiGwFYSi4DmsSWAg+tmcOFlJZ3lRWlYX0aAEutRS4lHRreDIEkJHZ8yfnzaGtuC72Q4PhxbvyjT9O47dbKGJ3SaNlifhLHvOG6N5gAglIC3ZGZwnS2euUZEluOx20WykrTmafyzVQJbhM17Ah30VPekMlPiUnum2ieKvnsEuWTdA1puM6Q2vpm4vPL9JXOlUamIUsbuBIlgYryMiKTQ26LirFhqZdK182XVxQsXBc95ZneH4405sLSNRS28LIUX8N8ybdjSMNc7xWlEQ0pjWi90gC42BnsWY4G1KRRgT9snnKk4fI0REjwuSSz9JMx3b9GYMZeOC4k1V2EIn1jnnLRUy7Jjz4iqQm5tY7Zac1TruTBM7Y2VMs2sHFKw7dOvcw6yD2d5eapi23JozvKSiO5cKGyaIAlDeXR0VZppAMCu1MuZ4QHXmCyYR1pOEc4RWSSCkMafoyoQV5OfdinIZ6HNztLurSETgXlZ9XP7o73qzeWc4Y3Qi+fuyyKEDGLvojkEVORF+ULlO718GYnk0ZRybgcPRRwtd0krAxWEAWJTcRzPeZpmN3n6cVm/tqqT6ORR91dbMxyOevTCmYISHNOfjDlAAAgAElEQVTSGDz5ZO4ncAQrQyGZAL5VV82uS1ZsIiJ4qvp9xoGXR/31rr0xfzxXmKXjxVVN9taThj82T2N8yO3G5qmSL1H5JL0h0jhsfGzNZ1YZqCyPngKKXA2M0jBlRDbwaXiFTyP0VX5PdVy6uxfmpXoCFQxFT5nNWKxNS4KKmTVsEWQZhzUEs1XSmIl9RODqQwVpRF5E5EWlkNvRSuNyd7CnSmPv6OlZAP/QIWPqyDJSDxrDSgNIJWCJGdqTdkZDcLsNFyWVd4FTA5Ro/KHoKZX1LGlQlEJOU7JBHy+0cjecAWSkTwPgqY7J2J7z4qrSsKSRimd8GgL/8wbheq7gW4fP4X/TxQTGNG67FW9uzpQ+OXmicp75eJ4LSujo1CiNpEdgybVceypUoTHHrK1XGs5PIWFoTAATlAaAt7BgbPkJVUc4jFQaZj48wPR3aLzwhRx+8EG+8cw1NLKiJIg7V+RFSOn79OamUxrDJsqWDa9c6a8gSpM5pRHbBcGqiMBTnD7U5KvnVplvBMXOPWgwG84iCJeiFpfWMq702wQkXDw0y0ycMnj8cZo3P48feMH38IKjLxg7Rt8SS9x3pDE+7+TYTMxSZ4C+oSjKKKPMU67BygilUWSED/s0RjvCXRmRQZqhhNFhoxXzlE/aMyG3EjcgAQ4ZR3zUGZDOuegpVx26FKHnhQxSTZJmhP4GGeE2Ii7yFYEKWAwX+EZgTax+yGee/gyL8SIL8QKvvWWG86t9rjrUNMSTDWhoTTh0bxK2edvyOc71NTLfRs3MkC0v4x89ylvuPM2NV8ysm7e5cI7lwJZ0GeHTAOOHqn0a+wTxfUMcDJunipsjVT4Xmcl3RtOUI56L3CJhlYZX1LIRKZURsfJXtIme8tG5TVonQyG3SpkduxqtNM6unAVg3osrPo3Q7nYzMTuiIMtYbgqfvGceLYJfsqt7c3Mc+eG/aeemep6FaIElJazplKbfsHka5txlpRF6odlZJ2vQWza5FHbRdEpDwpCW9WnABNKYnzdKY5CZzoIV0nAO2yHSKCkNFUUcefAHCeK4sjNzZB15UZEBDRv7NAIXcltdgNo2kWu1vwLK1GsCiBxpNAo795nDZhGdbQTF2IMGnvKYjWa54AcsK2FOK3xS+o2I5e99pxlfs8n7bn9f3lVwFHw7x401m+E+IVnx2Jw1F15/YzEPTmmUzVNsTBrrkvtcyO2QT0OJURr9cSYjqJCG9sM8TyO1dZ+8IV+kywiHKmmEKqafpBPMU8U1FJQ2BCLCjQs386g1D6XK43e/9bvcc+U9KFEstEJ+8N7rzCbE1smK05R5NTQ/YYs7uj1e01mDIMazBSP9o0e48YoZ3vLi0+uGNBvNTnSEO9TRU/sIZ6LSApGbnpLSuBge58v6ylL3r40Tao61DBEdss7cvFeADBDRRZVbSx6ijdIwzXUsaaRJ1REOZsc+xjx1dtWSRtCGQTdXGpEzT4mfO8KBPEw3cGOzn3n+jW+k+eIXExyrVq+fi+Y4p4QETdPeHFEQE6iApztPs9xfppN0TMKbKwux9E07bmueEkGiKCcNJMmVxrB5CpzSuEjWT6vRU1CxR5fhdm5lkmiGXmVHVyaNshnOm5tMGlcttmiGHoda1cUhDNqEmWald8lEGvWNjyduWHt+qUzGnVcvcPWhplnE/IKwwZgAn9B9tAgLOmVeVlglJnnDm4hvvZXw5KmJ4wMIZmwv6Uu2NEyjOfbYY9av0Z5rEV1/PVDyaZR8WiKuJP8oR7iNnhoyl4Snr0LNzeEtLlYez5VGosebekumMR2EqLUODAYkljTCuTkSqxwSJbkjHEx5cTAbstD3bcFCXUneK85TCrkdauV7y+Fb+WoQsCrCl3iGlcEK95y6Z8R7+JAOuLLf47roUPW5sGXyTZIu+A28BRu2f+zY6M+NiaBKPUF7aqwjHPZWadTmqSH4R4/CF78IArFzfJV2VL/0vF/i3376W9y+CZ/GFban97VHjLkj92moPiJZvmg50kAP8ugpt1M0yX2D6oUTz1ZuqPJ756TROmbCbTvnQfmELu/DKg3PNldwfcX9oGkywm3EiCjF6V/6xTz3wWEhXmDgKpraxcPzY15y/CX89hO/zfOPPJ9MZ7z8xMvh6a+YAy9+ww6yMPtIHCNhaPp1qwRRrjf7aKXR/dzn0IOkGj0FJdKoLuDOhFQmiWboVT6OUzWhF1Z21GoD89Rd1x3ikb/9mvW7Vj+irTNWe7Yvec8QYaNhSSguSOM9rzjDu7/jmvx1ZkBm7uejeb65asyMR7rnuUIu8sfZVZyOQ67+tQ9XxjoOwcwMj7cOceTrXzSfaZJ5ykZQtSOf+NZb6P3JnxTmqcq5MjP3sn7DNE5pzLzm1czcd+86v4uJnoIkG1N5FqoRgmFEdN7MSWKj0aLQpzMXM3t+zST3BU2TnwR50cLIM21rXbvXkeap0sbDzx3h5nM8/8itaBG+EIV8Nvk6sRfz0hMvXf8eng9rF/nZ5S684H+vPhe2obdiVHcQ49lAC39CO4fZ3P8XTlYatXlq/+AfPQq2RlDD5TOUuogFQUAvpXDcTWGecmF3wZAj3NjwC/OUc05mAJISao1nd1PrzFNglcb65D6AP1013e3mZ0wDei49YUp3KCH0FFr5xqeRVZWG6x5YVlcSBJWdJlTjz5s2Exwv4t4r7+Xx5cf55c//MovxIrcdvq1YJJfWk4aKIiQI8lh4UVbxyCifxjyJrQo6XmkMO8JHKQ2/sqg50o69uKo0NnCEi8hoM0fQoJVlLHcvIkojNtKu0bRmqZJ5SqnSe3jrlcaTayaK6cT5RwH4bHbGhBKH4brghFEIPMVj81cS2AZFMqFqr8vVaMc+jVttFNYoR7jKRjrB3flgfZVbERnpqPekcISPVe3l7zmKaXSNb6Eful7wiu6CzSkq5WlAYZ6KPNO2tj8pesorNh5lRzjAbUfNfHwmivhfvS/z0hMvrXYXdFCmhIwHeK0hMghbJklRZ+A38BcWUO32+sZZJbhcDaJ4XfRUpajiHpqnaqUxhIW3voXspjPQ/xlit/MvKY3QMxfeZqKnXLx1nhHuuV18H0ql0X27O0pE0Col1OC52P40WU8ar/xhExlVQllpeOIxM2tNGJcezz/HTz9wC43fiWzIrTl3N+3ii49Ye3weMTYGVdJwsj7k7lN383f4O3zhwhd4w3VvMETozDFOaZR6gUjDKA1XftqVsXa9KcrwFxaM1w/WKw1vsnmqTBI/cO+1OelDoWpCr7oQexuE3I6FH9PONKv9y5TbQjSP3gD3/STc9GfHvK5I7gMzx6k2KuXYhcfItPCovjr3pUyDwBMemz/F3d+yfacnkMbrbzvOpbUB1xxqoV//epJzzxDfaCKpKhnhOl0XpVY+H6x3hI+DM0/1kzEmI6goDRXH+Dbjuh8UHRovL7SA88anETRpu513iTQCT7HcTUimKlhoHeH29+HGYY4kGf98fpZOdpk33zCisGL5PQCaVVOcK1oImAi5t/0lWi9/+ej3sXBrR+NvvI+Fm15YeS7aJ6VRk8YQ4htvZP7MKfi1MmlUm8drDWsD67CdgjRc+KRTGr7yQStQA9NPw+7ilL1pXLmCSJsSCTCijAjAtfetO1fZpzEXzaHa1l566Yl8B/u9Lz4Nvx9Y85S5BAbZwDjoXb/tYPzuB4ZIw82TF3GsdYxbDt3Co+cf5d4r77WDsjvrkUrDkEYeHGD7J1cyaS2c4xCYKk8DihurTBqvuL66A3SqZrOO8LHwY1pZlkdPOTTbC/DKHxn/Om+9ecphNsv4sj5Bh7hScWAjhJ7iS/OF72MSaRxqRzx43/X2hLMc+asPlsZWIo2sO1Zp+GPMU+OgSiG3Y4NKSirHK9Ur69uNRhQoBovGX1QojWr0VORFRL7iQmrMUyOT+0rXkAtuKI/pTE/4g5bwotatvOLUKzYcK80RPg0HG504nFczDKc0Wv/b62g0q9dteWx7qTRq89QIRF7EofgQV4rb+RU3iDNHdaydeqRtdAgnZ04SezEn28ZUJCIoQkT6lSZM7rcrVxBoDc48NbCO8HD0Ds/BqZjl/rJZdJxEXru4fpHNktw8BZbUHFn4GyiNuEwaRSYtwOuveT0L0QIvPW5tvu7Yb/yeaSYxc0X+2vCq0wSnThLZ18YNU4tpJGkslMw6rVmYL0WbjMnTyJXGhDj2vFDkkNJQWyWNIKadZawOVvNEdYA4Xq+eqgMZMk+V5nguy/icPgNsrhf0TBzw9BVX5/+Xi0RuBhXz5GB5gtIYndw3Dp5AspF5yn23KsiLTgJ0ndLwPbJDZiOS+zRc9FRmfRpWPbiChSMtBKWQ22BEOPXNXZ+ZNONtx/7ChA9U2tSVzJDmzUrf/yjT1ghcO38tM+HMSOW9Xz6NWmmMgK98Pv6mj+P/2lvMA8FQH2BgpeccthvfwIvxIr/3lt+rOHc9iUBVScMtXq4Ec1RO7uv3IMtG2oXLiEuLvSGNophchQhy0ijMW6ZibGPdZx6F0UrDjO1tN7+NN9/45mIsTll0l+Al762M6eTP/zyIED/xW+a04TIDqgumQ1lpyBv/Cdx+f/XzwIg8jY13vhVfU3lXu4EjfCz8Bm2tWUnWKkrDjyYTcTnkFtYrjUeyzZNGI/T43Z/+Lr75R/+M/te+NtERPgmVjPDB5Qk+DWuemlINqbyMyBiTEZTMRjFhqUR/14+ALnHgoQ+bBdrVnlJKaIYea05pKOPTWBukaL1B5rkXEpTyNBzuWWnyvuU/5ksvuGL9a/P3KC2pGyiNaXD/6fu559Q9IwNDqtFTz3GlISKLIvJxEXnM/l4YccztIvI/RORREfmsiHzPXo4xUAHijVcaq66e0ZQ38PCX7hEinu1xYQ3f7rdTGmHJPOWa7qiNlEZpBzMfzZuxu0W7HFdvM1eVTsmrQii/uLA3UhoV0qg6cpWoCnmhPDOG9jG498cr7yO+aYTkcg0kWKLhN0bmHlSURnumGr0zJk/D2f8nZcxWlIZrbxrHeW2sTcOPjHkq7eY+jUyGI5BGvc710zDfoTNrRmK6wX3OkcaUph+HwFPEt946tfN8JMqk0bs0MkcDzEIW+Qo1ZW8H17lvrHMaSioyIm4W1/da3jdFIYfNAu18GmDan+bmKas0Ov0JZuU8Izxc5wgHSFSDhtZ4wYR70L2HeNWeN1AljSmVhgm2GL1RDCp5Gs99pfEQ8Emt9QdE5CH7//uHjukAf1lr/ZiInAA+LSL/RWu9tGejzAuYFQugc4yt9KdXGiPfWiJUZMJir7A1953i6Lj+DFqDrYyaN8XZgDQiL0IQNLrYrbeOmEzsEUqDLMEH+tjFM5hOaYReSAthFU1Tu9DkCWN79U/D4RvX30gWjmSazRWawbo9BDDk0xhOUhuXp2FJIJ6CNMplRLasMgAa87SzjJWsnyuNZAozJs9/s1FhdkF2399sNM/Ky36UR37rWmC64IthHHr3u2i+6EUbHzgGVaWxDP7VI497051Xct3RDcxwJZQLFo43TxW+xbhVfO9rfuEI92wvnEyJqUKACR0+txzgS5BHT63mFoIJPg0/KkJuS3M9sPlIatKGyo21ubg+JLlsYtrg/poG+6U09os0HgDusX9/CPgUQ6Shtf5S6e8nReRp4Aiwd6ShqrZ6gMDe/M6nsWXSIMSLngDg1sPGGTbs0wi1RuyuSbtS1RuQhinSZ8qj52qgdQTOf7m6O/QCSxp5dw3r03DRUxtf1PP4rDKgmVeYnbAzf9E7Jr6Xc4RfHpznePvGkcd4s6Z5E1qvDx0dk6eRJ/dNYZ6KvChXGlt2ggO0jtLONAkabUkjnSIJlEPXmh8L9/3NRvP07vphst/6BCLTJZQOI77pJuKbbtr4wHEoKxTRY7/rG6+Y4cYrJvchKUOpzSmNRtDAGVRXVaE0XIKcBEFeHsY4h4WGN5PnafSSCTWuvMlKw1W2nqg03Hs0Ftc/NxQ9tV2USWMvlcZ+OcKPaa3PAtjfRycdLCIvBkLgK2Oef4+IPCwiD5+z1Tl3BCVbqkNob57cPLVF0vDtriX2Glw9ezVQ5GkUpAGSKw1bf2bSBWvhTFR5q1nnDF+nNFJIB3mz+4rSmEI+z1uSW1dCfgtwjvBMZ9Vy0iWI7+eL+XilMSZ6amqlYU2FG2SDT0TrMO2htsHZJvwQDo405qK5ormRX9TM2ktUMsKVnqwqNwFPjNLoJZOipwrF3ywpjVXPJ/SMKSyeXeBP5+HyYnENOmf4FY3TnGyfrLz/SNJoHjJBCAtXVarcOiSeq8o84d5wYx32Z8CQeWprvqXKqZTk5PacUBoi8glglMfoJzb5PseBfwm8XWudjTpGa/1B4IMAd955px51zJaQm6dKyX32S1rZpE9jGIGYi/t5i8/LycLlaaxVzFO27EeuNCY7wqHYteetZnPSGKrVlA6MM9w+VDVPbXxRz+PT0OC51nRjbK/TwI25Mu4R8ObnSS9dWh8FtEEZkUl5A1WlYbPz59Y74qdG0KBlNwWpte1vhTTcPMyGsyXH7N4tDmVUzFPCZFW5CTjz1KW1Adccbo05qMgDiprmOkmDkF4qRRVjv8GD7/E4PVeEpbpSIg/e/A+5+4aj/KOPP5Y/N1KtNRfh/V830VNPm3yhCmn4TTucCZ/dbTSHczRgx81TYDatgzR9bkRPaa3vH/eciDwlIse11mctKTw95rhZ4D8AP6m1/v1dGup4lJJ9HNxFtNpPxlflnAKONG47UsRp545wS1YhGnG1opxPYzNKw+3Y21bIDSuNwZolDQH0kCN8CqWhQhopeV2r7SwkZcd3rpBGwFtYgG98Y30U0LjoqdwRPv5SryT32cV5W+YpoB3NABmJp83sbmGx95XPTDjDbDSbL3KbiZzaUZQ697GDSkOJkGlY6gxMefiRBxVKw5V6T6KYXpIWIdV+g9QTGlFBPC4rPA4CPOXlVgKYsNmz9/pwch9A6jnz1CTSKPk0hrHDSgOMMzyYlOOyC9gvn8ZHgbcDH7C/PzJ8gIiEwG8Cv6q1/o29HZ5F6WJ1yEmjl27ZnwFw5vACT5yFWw7dUpzOkkbHXnhRpsEl93Wm82lA4VQufBo2xLUSPeUXPg0ZYZ6aYif0F8Pj3HX5YtGabhsLybpQ4TFwzvCx5ql1/TTWZ4QP48qZK3nw9ge5+9TdcMmUdd+WIxxox/PABRJPCDAtVLeC9/+Z93Pt/LV4ShDZurLdLsol40Wxg0rDlORZ7WemPPwo5I7wKI8e7Icx3UGWk2jTqgD3GwrScCbkoBSMsNG9648wTz2y8Br+8Cl4XzhhwXeqaJR5yo/N5Olsw+TZaRF6Cr2HKgP2z6fxAeDVIvIY8Gr7PyJyp4j8oj3mzcArgXeIyGfsz+17OkpvhNLwipDbrfozAK6YMTvZWw4XpCEi+OIX5ik04kfg+6a9JdORhlMaFUc4rFcaqY2eKveV2IQj/LZgnu/q6bz/+HYWkgppjMjRcPAWFoxTdjhfZRs+DSWKv/KCv8JCvFAoje34NIB2bBaNgb1E9CbDZB0euO4Bbj18qwm9VGoflUbZPLWDSkMJvSRDa/K2qesPKjZv7vrvB9E6pQFFuC2Q99QIRkRCDZezH4arcls2By63ruJD6WtHZ5MPj3WUI1ykMFFNmaexEUJf7ak/A/ZJaWitzwOvGvH4w8D32b//FfCv9nhoVbgLoJzcV8rT2M6u79TMKU62T3J6plpDX4mybSUz49OwWcpZ1zVimcKnsU5pjDJPeVZpDKx5yiqNxWuMWW622nRpJLzQEEbSt++/ddIIVZiHCk8yT0XXXUd46tR6Z/CYPI3Ti00CTzgxP91NqtqmOU545tqND56AdvMwXHqMQR6atnV/j0Pgyf75NCqOcHbMvFJevOebY4ioZCZ2pNHzI7qDrOiXYu/RUUrDH2Ha26jQ6EwcMBv7nFoo7n13rokqRU1QGmBMVL3LU+dpbITQV6g9DoyoM8InYVTIbSkjfDvOp7ff8nbe+ry3rlv8POWxJtbJrjUok/zmfBobJfeB2XUpUaaXBRRKY0QZkcKnYUnj1J3wY09MtxOKZqB7uaQ0tr4wigiRF9FNuxMd4YvvfAeLf+lt658Y4wi/4/QCn/up105dQE81Glz/3393w8z7jdBqHYNL0LMLlgTbv9V8T22qWOFOQqYMud0svNL1P41Pw0UTrvkR3UGak+hopTFkniot9htZCRqhx//8yfsrx7lzTQx5nuTTAEMayq/6iLYBl0y5l6hrT02CW2S9UY7wtGIj3SyUqJFZz774rIkJAFP4RtL6PtmqIY1pdqwN37QLzftA5z6NUcl9Kb71peTlyKeVzvG86Q1gW4ludyFxYbfjQm7B9PcYaaIbk6cB01dczd8qDLcd1tpuG6XWyUlj++acYB8WiBzrlMbOmaccxpNGoSLdd7/mmX7f+e5fBQQqqCgNRxqjwmen8UdGvle5Dtzcj63GC5PzNMCQxg6pDDemvYycglppTMZtbzI7htIN4nYeaTahVs42oJSihyENz3494nkkZ89CEBBeddWG7/E9N34PLzn+kuKBxjy89u/DDa8tnSgweRpZkudpjCtXMBYuu3vV5saM6OS2GTgSneQIH4sxPo39Qjh7BYHWrNhFbbvKBSD0JG8KtNeQ0kK5oyG3UjZPTe/TWFUh3UFacZ7/2Et+jOcffn7+//03H+OvX+5xetEQSfl+3UqC5BvuOMl8M5hslr7mbnjlj8LJF45+PmzvmD8D4MH7rt/zjURNGpNw+DrzU0L5gtmOI3wc8u59FKSBXShaL34xXnvjEg3PP/J8nn/k+dUHX/YD1f+dTyMd4EkAusgTmRq2bSur5wwJTdqBTQFnYphknhqLMf009g2tI8xkGSv2etlyHasS/P1UGmXz1E6G3E6lNAozsfPpOdIom+vedMObKi873I74ofuvz//frNIYxjWHW1xz+JrJB8WzcN+EVLSwtWM5GgCvvnl8q9jdQk0am0TFLroLN3CZNHxbJkF8c6O077t3505U8WlE9nybJQ27uK+c25YT3CHyImIvHt0RbSMcMKVB6yitLOMpXwGaKNp+iOWphQZXLuxMqOZmISKGONJ0x5P7HMaSRh7FGOc+vWUVGEf4JnuLOOyGlWAqLF5reoQ/i1GTxiax3d3KRsizw7Vm1lb0dE7ImXt3gzQKn8aWSWP13I7s8GMvnhhuOxEjghb2Fa3DtDNNxzeJk4szEyvlTIUPvevF7G2cTBXieeg0tWVEdtY8FflqvO+pVLDQmaeWxaeXpJuq+Fu9d/dpJl/zd4GdK1qxH6hJY5MoX2y7ceE5pRFqjbhy4Z5HdPPzCE5MEQY7LVztqWyAt1XScG1bV5/eEede7Mdb82fA2OipfUM8T0trXAHgnXKE7yt8H/p9qzR21jw1VmVA1TxlzXwdL2KpM1jXi3wSgoOgNHYoamo/8ez/BHuMsGKe2nmnZJk03I15+MEH8Y8cnvSyzUN5psl97zKefxUkRQ2mqZE3V7oEW+2nXcI7b30n/bS/tRePydPYNyjFO3seSntANlVS5kGHKGX2yDuqNMzvsU5wqJCGt7jIE296F79z6QRJpjfX+naXrQTfLqhJY5MwTVGEQaoJd0NpqPWkMfddf3bHz5ObpwAvnofun27dPAU7YuP+jpPfsfUXHzSfBvDK8BAXVI+nGOxI9NR+w5lJRdg50phKaZSS+0RY+fNv4Zl//QjAJpXG7loJvl1Q0+0WMCpZaKcwSmnsCkoE4dtexpsmjbBN3gR7v30JB5A0OHoz0jJz+1wgDXyTNyR+AHOnNz5+ChTmqQnfW3PRmD/nTbh5q5SXsJkcnM1khNcYj3rmtgB3we0uabA3pDF3Gt9m0W6aNJQqwm7325dwEEnjgX+CvPT7gecGaYjnGeJ46JtwautdAMtwjvCJSqO5CO//Gpy5ByiS9mBzVX83kxFeYzzqmdsCwhEZpjsFZ56KtN7dhdgtsiduz4lq0z4NKExUOxSCuWXkPo0DtDh7QV724rng08D3TA2qcOfCfqdyhIPJbcg78m1NadQ+jZ1BPXNbQLCL5imXYBfonXM2joSL4jj5wiLMd7NKA8Al4u1QsteW4QjvICkNikJ/zw2l4VdrUO0AnNKY6AgfQpU0Nq80ZBt9cGrUpLElOEm8G45w11Nj75TGHQVRPauVxgHL03B4LpGGUpVqtzsBV4F2Q6VRQtU8tXmlUauM7aGevS1gN5XGqOipXcHsCaMSjt++PaXhSGO/F+u5k2Ys0cz+jmMILpv/uWGe8iuFC3cCaktKoyCKzSiN3Kxck8a2UIfcbgFux7KbZURC2F3SuOXPww3fCWErP+ema0/BwXGE3/wG83l2sK7PTsApjOeE0vC8HVcazkw0tgHTCFSipzahNIrNXm2a2g72hXJFZFFEPi4ij9nf62phi8hVIvJp27HvURF5736MdRR2U+bmpCH+7pKGSN6z2CmMTVe5hYNjnhI5cIQBRR+N5wJp4Hs779OY1hFeglKSd6vbTH8RTwmekto8tU3s1+w9BHxSa3098En7/zDOAi/XWt8OvAR4SER2sI7G1uF2KrsaPXX8dnjh23f8/UeeU7bjCLdKY78d4QcUzzVHODtcBeFl1x7iB++9lttObq6igHOGb7aTYeipmjS2if2avQeAD9m/PwS8YfgArXVfa21bwhFxgPwv4TQdvLaIPPz1yE07Fgu/ERxZbM08dUCUxgFFThrPAZ+GcYTvLPnNxgE/8tqbNr2QO2f4Zhtshb6qzVPbxH4txMe01mcB7O+RJUBF5EoR+SzwOPAPtNZPjjnuPSLysIg8fO7cuV0btIOLmtrNfhrhHoaOPicc4QcU/tGj4PsEJ47v91C2D3/nQ263ikJpbO4eDGqlsW3smiNcRD4BXDHiqQkdSqrQWj8OPN+apf69iPxbrfVTI477IPBBgDvvvHPX6wNwgrkAAAu1SURBVA7nPo3dNE/t4c59eyG3B8QRfkARnDjBjX/4B6jm/vTB2EnshiN8q3ARVJtVGpFfk8Z2sWtXgNb6/nHPichTInJca31WRI4DT2/wXk+KyKPAK4B/u8ND3TR2NeR2O9nZWz3nTiiN2jw1Fs8FwgAQ39vxkNutojBPbVZpSG2e2ib2i3I/Cjgv79uBjwwfICKnRKRh/14A7gK+uGcjnIDdjPfeD6WxLUd4fEAywmvsOhbf8Q4Ov+f793sYwDYc4bXS2Db2a9vwAeDfiMi7gW8CbwIQkTuB92qtvw94HvBzIqIxpVR/Vmv9uX0abwXBXuRp7KFPI3eEbyd6qlYaz3m0X/nK/R5Cjlbko2TzwSi1T2P72BfS0FqfB1414vGHge+zf38ceP4eD20q7Elp9L10hG/HJNY+CuEMzJ3a4VHVqDEeVx9qcmqhaXqXbwIn5xvMxLX/bTs4GAbKZxmK5L5dbML0bCGNaAZ++IsQPDfs9jWeHXj3d5zhL7/s6k2/7h+/9Q5kXzutP/tRk8YWsKs+DdkHn8Z2HOGQZ5bXqLFXMNndmw//3awPpMZ61Ma9LSDYzX4azjyl9k5pOIWxZdKoUaPGtw1q0tgCdrX2lHLZ5nsYcrud6KkaNWp8W6EmjS3A+TJ20xG+l+apY61jxF7MfDS/Z+esUaPGsxP11nILyJsw+btXe2ovzVN3nbiLT33Pp2gFtW+iRo0ak1ErjS0g76exC3V49iN6SkRqwqhRo8ZUqEljC7j3xqP81fuu49TCzvdv2I88jRo1atSYFrV5ags4OhvzN19z46689374NGrUqFFjWtRK44AhN0/toU+jRo0aNaZFTRoHDLV5qkaNGgcZNWkcMNSkUaNGjYOM2qdxwHDf6fvoJJ06Z6JGjRoHEjVpHDCcmjnFe1/w3v0eRo0aNWqMRG2eqlGjRo0aU6MmjRo1atSoMTX2hTREZFFEPi4ij9nfCxOOnRWRb4nI/7WXY6xRo0aNGuuxX0rjIeCTWuvrgU/a/8fh7wC/vSejqlGjRo0aE7FfpPEA8CH794eAN4w6SEReBBwDPrZH46pRo0aNGhOwX6RxTGt9FsD+Pjp8gIgo4OeAH9nozUTkPSLysIg8fO7cuR0fbI0aNWrUMNi1kFsR+QRwxYinfmLKt/gB4D9qrR/fqHm81vqDwAcB7rzzTr2ZcdaoUaNGjemxa6Shtb5/3HMi8pSIHNdanxWR48DTIw57GfAKEfkBoA2EIrKitZ7k/6hRo0aNGrsI0XrvN+Yi8jPAea31B0TkIWBRa/2jE45/B3Cn1vrBKd77HPCNbQzvMPDMNl6/W6jHtTkc1HHBwR1bPa7N4aCOC7Y2tqu01kc2Omi/MsI/APwbEXk38E3gTQAicifwXq319231jaf50JMgIg9rre/cznvsBupxbQ4HdVxwcMdWj2tzOKjjgt0d276Qhtb6PPCqEY8/DKwjDK31rwC/susDq1GjRo0aE1FnhNeoUaNGjalRk8Z6fHC/BzAG9bg2h4M6Lji4Y6vHtTkc1HHBLo5tXxzhNWrUqFHj2YlaadSoUaNGjalRk0aNGjVq1JgaNWlYiMh3isgXReTLNndkv8ZxpYj8loh8QUQeFZEfso//lK32+xn78/p9Gt/XReRzdgwP28emrlq8S2O6sTQvnxGRyyLy1/ZjzkTkX4jI0yLy+dJjI+dHDP5Pe819VkReuMfj+hkR+RN77t8UkXn7+NUislaat3+6W+OaMLax352I/Jidsy+KyGv3eFz/ujSmr4vIZ+zjezZnE9aIvbnOtNbf9j+AB3wFOAOEwCPAzfs0luPAC+3fM8CXgJuBnwJ++ADM1deBw0OP/UPgIfv3Q8A/2Ofv8k+Bq/ZjzoBXAi8EPr/R/ACvB/4TIMBLgT/Y43G9BvDt3/+gNK6ry8ft05yN/O7svfAIEAHX2PvW26txDT3/c8Df2us5m7BG7Ml1VisNgxcDX9Zaf1Vr3Qd+HVOJd8+htT6rtf4j+/cy8AXg5H6MZROYqmrxHuFVwFe01tupCrBlaK3/G3Bh6OFx8/MA8Kva4PeBeVtWZ0/GpbX+mNY6sf/+PnBqN869EcbM2Tg8APy61rqntf4a8GXM/bun4xIRAd4M/D+7ce5JmLBG7Ml1VpOGwUng8dL/T3AAFmoRuRq4A/gD+9CDVl7+i702AZWggY+JyKdF5D32sQ2rFu8hvpfqjXwQ5mzc/Byk6+5dmN2owzUi8r9E5LdF5BX7NKZR391BmbNXAE9prR8rPbbncza0RuzJdVaThsGoMrr7GossIm3g3wF/TWt9Gfi/gWuB24GzGGm8H7hLa/1C4HXAD4rIK/dpHOsgIiHw3cBv2IcOypyNw4G47kTkJ4AE+LB96CxwWmt9B/A3gF8Tkdk9Hta47+5AzBnwFqqbkz2fsxFrxNhDRzy25TmrScPgCeDK0v+ngCf3aSyISIC5GD6stf5/AbTWT2mtU611BvxzdkmSbwSt9ZP299PAb9pxPOXkroyvWrwXeB3wR1rrp+wYD8ScMX5+9v26E5G3A38W+IvaGsCt6ee8/fvTGL/BDXs5rgnf3UGYMx/488C/do/t9ZyNWiPYo+usJg2D/wlcLyLX2N3q9wIf3Y+BWFvpLwFf0Fr/o9LjZRvknwM+P/zaPRhbS0Rm3N8YR+rnMXP1dnvY24GP7PXYLCq7v4MwZxbj5uejwF+20S0vBS4588JeQES+E3g/8N1a607p8SMi4tm/zwDXA1/dq3HZ84777j4KfK+IRCJyjR3bH+7l2ID7gT/RWj/hHtjLORu3RrBX19leePufDT+YCIMvYXYIP7GP4/gOjHT8LPAZ+/N64F8Cn7OPfxQ4vg9jO4OJXHkEeNTNE3AI0+v9Mft7cR/G1gTOA3Olx/Z8zjCkdRYYYHZ47x43PxizwT+x19znMOX/93JcX8bYut119k/tsW+03+8jwB8B37UPczb2u8M0cvsK8EXgdXs5Lvv4r2CqcZeP3bM5m7BG7Ml1VpcRqVGjRo0aU6M2T9WoUaNGjalRk0aNGjVq1JgaNWnUqFGjRo2pUZNGjRo1atSYGjVp1KhRo0aNqVGTRo0agIhcISK/LiJfEZE/FpH/KCI32OqlW8rvsFVQD29wzI8P/f97Gxz/KRG5cyvjqVFjJ1CTRo1ve9hkqd8EPqW1vlZrfTPw48CxPTh9hTS01i/fg3PWqLFl1KRRowbcCwy01nkPBK31Z7TWv1M+SERiEfllMf1E/peI3Gsf90TkZ+3jnxWRvzr0uoaI/GcR+f6hxz8ANGz/hQ/bx1ZKz/+ofc9H7LHl1yoR+ZCI/F17/l8Rkc/b4//6Tk1MjRrD8Pd7ADVqHADcCnx6iuN+EEBrfZuI3ISp9nsD8E5Mb4c7tNaJiCyWXtPGlNr/Va31r5bfTGv9kIg8qLW+ffhEIvI6TGnrl2itO0Pv6WOKC35ea/33RORFwEmt9a32tfNTfu4aNTaNWmnUqDE9vgNT3gKt9Z8A38AUpbsfU4Ijsc+VezB8BPjlYcKYAvfb13VGvOc/wxKG/f+rwBkR+ce2ntSkiqc1amwLNWnUqGFqBr1oiuNGlZh2j4+rx/PfgddZv8lmMOk9fw+4V0RiAK31ReAFwKcwaugXN3muGjWmRk0aNWrAfwWiss9BRP6MiNw9dNx/A/6iff4G4DSmaN7HgPfaktkMmZL+FqaQ4i+MOffAlrkexseAd4lIc8R7/hLwH4HfEBHfRmgprfW/A/4PTIvSGjV2BTVp1Pi2hzZVO/8c8Gobcvsopkf1cM+BXwA8EfkcppfCO7TWPczO/pvAZ0XkEeCtQ6/7a0AsIv9wxOk/aF/34fKDWuv/jKnu+rCIfAb44aHn/xGmmuq/xHRh+5Q97leAH9vEx69RY1Ooq9zWqFGjRo2pUSuNGjVq1KgxNWrSqFGjRo0aU6MmjRo1atSoMTVq0qhRo0aNGlOjJo0aNWrUqDE1atKoUaNGjRpToyaNGjVq1KgxNf5/Shy10Yg7XbUAAAAASUVORK5CYII=\n", - "text/plain": [ - "" - ] - }, - "metadata": {}, - "output_type": "display_data" - } - ], - "source": [ - "# Plot results.\n", - "plt.figure(1)\n", - "plt.plot(iq0[0], label=\"I value; ADC 0\")\n", - "plt.plot(iq0[1], label=\"Q value; ADC 0\")\n", - "plt.ylabel(\"a.u.\")\n", - "plt.xlabel(\"Clock ticks\")\n", - "plt.title(\"Averages = \" + str(config[\"soft_avgs\"]))\n", - "plt.legend()\n", - "plt.savefig(\"images/Conditional_True_NoPulse.pdf\", dpi=350)" - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [] - } - ], - "metadata": { - "kernelspec": { - "display_name": "Python 3", - "language": "python", - "name": "python3" - }, - "language_info": { - "codemirror_mode": { - "name": "ipython", - "version": 3 - }, - "file_extension": ".py", - "mimetype": "text/x-python", - "name": "python", - "nbconvert_exporter": "python", - "pygments_lexer": "ipython3", - "version": "3.8.2" - } - }, - "nbformat": 4, - "nbformat_minor": 2 -} diff --git a/qick/qick_demos/04_Reading_Math_Writing.ipynb b/qick/qick_demos/04_Reading_Math_Writing.ipynb deleted file mode 100644 index dbe4a86..0000000 --- a/qick/qick_demos/04_Reading_Math_Writing.ipynb +++ /dev/null @@ -1,318 +0,0 @@ -{ - "cells": [ - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "#
Reading, math and writing demonstration\n", - "\n", - "###
In this demo you will use the tProc to do some math and/or bitwise operations on two variables that you will pass in through the config dictionary and take out with single_read ." - ] - }, - { - "cell_type": "code", - "execution_count": 1, - "metadata": {}, - "outputs": [ - { - "data": { - "application/javascript": [ - "\n", - "try {\n", - "require(['notebook/js/codecell'], function(codecell) {\n", - " codecell.CodeCell.options_default.highlight_modes[\n", - " 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n", - " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", - " Jupyter.notebook.get_cells().map(function(cell){\n", - " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", - " });\n", - "});\n", - "} catch (e) {};\n" - ] - }, - "metadata": {}, - "output_type": "display_data" - }, - { - "data": { - "application/javascript": [ - "\n", - "try {\n", - "require(['notebook/js/codecell'], function(codecell) {\n", - " codecell.CodeCell.options_default.highlight_modes[\n", - " 'magic_text/x-csrc'] = {'reg':[/^%%pybind11/]};\n", - " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", - " Jupyter.notebook.get_cells().map(function(cell){\n", - " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", - " });\n", - "});\n", - "} catch (e) {};\n" - ] - }, - "metadata": {}, - "output_type": "display_data" - }, - { - "name": "stdout", - "output_type": "stream", - "text": [ - "Populating the interactive namespace from numpy and matplotlib\n" - ] - } - ], - "source": [ - "# Import the QICK drivers and auxiliary libraries\n", - "from qick import *\n", - "import time\n", - "%pylab inline" - ] - }, - { - "cell_type": "code", - "execution_count": 2, - "metadata": {}, - "outputs": [], - "source": [ - "# Load bitstream with custom overlay\n", - "soc = QickSoc()\n", - "soccfg = soc\n" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### Hardware Configuration\n", - "\n", - "tProc channel 7 : DAC 229 CH3 <-> Readout channel 0 : ADC 224 CH0" - ] - }, - { - "cell_type": "code", - "execution_count": 3, - "metadata": {}, - "outputs": [], - "source": [ - "class LoopbackProgram(AveragerProgram):\n", - " def initialize(self):\n", - " cfg=self.cfg \n", - "\n", - " # Move value of A into tProc register\n", - " self.regwi(0,1,self.cfg[\"A\"])\n", - "\n", - " self.synci(200) # give processor some time to configure pulses\n", - " \n", - " def body(self):\n", - " # Do math: add value of B to the register value\n", - " self.mathi(0, 1, 1, '+', self.cfg[\"B\"])\n", - " \n", - " # Write the result to address 123\n", - " self.memwi(0,1,123)" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### Here we will add the value of A to the value of B using the tProc. We write the result to tProc memory address 123, and then read out that address value at the end of the program." - ] - }, - { - "cell_type": "code", - "execution_count": 5, - "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "Result = 50\n" - ] - } - ], - "source": [ - "config={\"reps\": 1, # fixed\n", - " \"A\": 100,\n", - " \"B\": -50\n", - " }\n", - "\n", - "prog =LoopbackProgram(soccfg, config)\n", - "\n", - "soc.load_bin_program(prog.compile())\n", - "# Start tProc.\n", - "soc.tproc.start()\n", - "time.sleep(0.1)\n", - "result = soc.tproc.single_read(addr=123)\n", - "print(\"Result = \", result)" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### Here we show how similar register operations can also be done using the QickRegister object. \n", - "\n", - "The QickRegister object keeps the register page, address, gen_ch/ro_ch, and reg_type information, so unit conversions like freq2reg/us2cycle/deg2reg can be automatically used when we assign values to registers. This makes qick programs easier to write and read especially when a lot of operations on registers that correspond to physical values are involved. \n", - "\n", - "In the program below, we assign values to the frequency register of a generator, all the assignments are done directly using frequency values in MHz, and no explicit reference to the low level register value/page/address is needed." - ] - }, - { - "cell_type": "code", - "execution_count": 6, - "metadata": {}, - "outputs": [], - "source": [ - "from qick.qick_asm import QickRegister, QickRegisterManagerMixin" - ] - }, - { - "cell_type": "code", - "execution_count": 7, - "metadata": {}, - "outputs": [], - "source": [ - "class TestRegProgram(QickRegisterManagerMixin, AveragerProgram): # inhered the QickRegisterManagerMixin class\n", - " def initialize(self):\n", - " cfg = self.cfg\n", - " self.declare_gen(ch=cfg[\"gen_ch\"], nqz=1, ro_ch=cfg[\"ro_ch\"]) # this \"ro_ch\" will be automatically used for freq2reg operations later\n", - "\n", - " # get the frequency register associated with gen_ch\n", - " self.gen_freq_reg = self.get_gen_reg(cfg[\"gen_ch\"], \"freq\")\n", - "\n", - " # declare another frequency type register on the same generator page, initialize it to the integer that corresponds to frequency \"f1\" in MHz\n", - " # the \"gen_ch\" and \"ro_ch\" of cfg[\"gen_ch\"] will be automatically used when converting a physical frequency value to integers of this register\n", - " self.gen_freq_reg_temp = self.new_gen_reg(cfg[\"gen_ch\"], name=\"freq_temp\", init_val=cfg[\"f1\"], reg_type=\"freq\")\n", - "\n", - " self.synci(200) # give processor some time to configure pulses\n", - "\n", - " def body(self):\n", - " cfg = self.cfg\n", - "\n", - " # set the register value to the integer that corresponds to frequency \"f0\" in MHz\n", - " self.gen_freq_reg.set_to(cfg[\"f0\"])\n", - " # Write the result to address 123\n", - " self.memwi(self.gen_freq_reg.page, self.gen_freq_reg.addr, 123)\n", - "\n", - " # assign the value of register \"gen_freq_reg_temp\" to register \"gen_freq_reg\", which should corresponds to \"f1\"\n", - " self.gen_freq_reg.set_to(self.gen_freq_reg_temp)\n", - " # Write the result to address 124\n", - " self.memwi(self.gen_freq_reg.page, self.gen_freq_reg.addr, 124)\n", - "\n", - " # add 300 MHz to the frequency kept in \"gen_freq_reg_temp\" and assign it to \"gen_freq_reg\"\n", - " self.gen_freq_reg.set_to(self.gen_freq_reg_temp, \"+\", 300)\n", - " # Write the result to address 125\n", - " self.memwi(self.gen_freq_reg.page, self.gen_freq_reg.addr, 125)\n", - "\n", - " # sum the frequencies kept in \"gen_freq_reg_temp\" and \"gen_freq_reg\" and assign it to \"gen_freq_reg\"\n", - " self.gen_freq_reg.set_to(self.gen_freq_reg, \"+\", self.gen_freq_reg_temp)\n", - " # Write the result to address 126\n", - " self.memwi(self.gen_freq_reg.page, self.gen_freq_reg.addr, 126)\n", - "\n" - ] - }, - { - "cell_type": "code", - "execution_count": 7, - "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "\n", - "// Program\n", - "\n", - " regwi 0, $1, 312076190; //'freq_temp' <= 312076190 (500 MHz)\n", - " synci 200;\n", - " regwi 0, $15, 0;\n", - " regwi 0, $14, 0;\n", - "LOOP_J: regwi 0, $22, 624152380; //'gen0_freq' <= 624152380 (1000 MHz)\n", - " memwi 0, $22, 123;\n", - " mathi 0, $22, $1 + 0; // 'gen0_freq' <= 'freq_temp' + 0 (0 MHz)\n", - " memwi 0, $22, 124;\n", - " mathi 0, $22, $1 + 187245715; // 'gen0_freq' <= 'freq_temp' + 187245715 (300 MHz)\n", - " memwi 0, $22, 125;\n", - " math 0, $22, $22 + $1; // 'gen0_freq' <= 'gen0_freq' + 'freq_temp'\n", - " memwi 0, $22, 126;\n", - " mathi 0, $15, $15 + 1;\n", - " memwi 0, $15, 1;\n", - " loopnz 0, $14, @LOOP_J;\n", - " end ;\n", - "Result= 624152380 , expected: 624152380\n", - "Result= 312076190 , expected: 312076190\n", - "Result= 499321905 , expected: 499321905\n", - "Result= 811398095 , expected: 811398095\n" - ] - } - ], - "source": [ - "config={\n", - " \"gen_ch\": 0,\n", - " \"ro_ch\": 0,\n", - " \"reps\": 1, # fixed\n", - " \"f0\": 1000, #MHz\n", - " \"f1\": 500 #MHz\n", - " }\n", - "\n", - "prog =TestRegProgram(soccfg, config)\n", - "\n", - "\n", - "soc.load_bin_program(prog.compile())\n", - "# Start tProc.\n", - "soc.tproc.start()\n", - "\n", - "print(prog)\n", - "\n", - "time.sleep(0.1)\n", - "\n", - "\n", - "# compare the result with what we should get using freq2reg functions\n", - "result = soc.tproc.single_read(addr=123)\n", - "print(f\"Result=\", result, \", expected:\", prog.freq2reg(config[\"f0\"], config[\"gen_ch\"], config[\"ro_ch\"]))\n", - "\n", - "result = soc.tproc.single_read(addr=124)\n", - "print(f\"Result=\", result, \", expected:\",prog.freq2reg(config[\"f1\"], config[\"gen_ch\"], config[\"ro_ch\"]))\n", - "\n", - "result = soc.tproc.single_read(addr=125)\n", - "print(f\"Result=\", result, \", expected:\",prog.freq2reg(config[\"f1\"]+300, config[\"gen_ch\"], config[\"ro_ch\"]))\n", - "\n", - "result = soc.tproc.single_read(addr=126)\n", - "print(f\"Result=\", result, \", expected:\",prog.freq2reg(config[\"f1\"]+300+config[\"f1\"], config[\"gen_ch\"], config[\"ro_ch\"]))" - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [] - } - ], - "metadata": { - "kernelspec": { - "display_name": "Python 3", - "language": "python", - "name": "python3" - }, - "language_info": { - "codemirror_mode": { - "name": "ipython", - "version": 3 - }, - "file_extension": ".py", - "mimetype": "text/x-python", - "name": "python", - "nbconvert_exporter": "python", - "pygments_lexer": "ipython3", - "version": "3.8.2" - }, - "vscode": { - "interpreter": { - "hash": "618feb7b2b0a35f7e820dec88779cac1ef83ad948f0212540d069fdb92cbb234" - } - } - }, - "nbformat": 4, - "nbformat_minor": 2 -} diff --git a/qick/qick_demos/05_PhaseCoherence_QickProgram.ipynb b/qick/qick_demos/05_PhaseCoherence_QickProgram.ipynb deleted file mode 100644 index 6fa3721..0000000 --- a/qick/qick_demos/05_PhaseCoherence_QickProgram.ipynb +++ /dev/null @@ -1,472 +0,0 @@ -{ - "cells": [ - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "#
Calibrating the QICK for phase coherent readout\n", - "\n", - "###
In this demo you will calibrate the QICK clocks to have the same phase.\n", - "\n", - "Before you measure a resonance with your QICK this is the first calibration you should do. It is a calibration for the two synthesizers which belong to the QICK signal generator and the QICK readout, respectively. The two synthesizers are running at the same frequency, but there is initially a constant phase difference $\\phi$ between these two synthesizers. Doing this calibration results in you finding that phase difference $\\phi$. In your subsequent measurements, you can specify this initial phase difference $\\phi$ to compensate for it. From then on, the signal generator can synthesize any frequency and then if you read in data (doing a digital down conversion in the process), the readout will still be phase coherent with respect to the signal generator. \n", - "\n", - "
The angular frequency $\\omega = 2 \\pi f$ .\n", - "\n", - "
Also, $\\phi = (\\omega t) + \\phi_0$. \n", - "\n", - "
So, $\\phi = (2 \\pi f)*t + \\phi_0 $. \n", - "\n", - "If $f$ goes up linearly, the phase difference will also change linearly (it will either increase or decrease, depending on whether the readout is ahead or behind of the signal generator- this is randomly determined each time the board clocks are initialized). Once the phase hits 360 degrees it cycles back to 0 again. For a readout frequency of interest $f_i$ there is a corresponding phase difference $\\phi_i$. In this demonstration we assume $f_i \\approx 180$ MHz. You can plot $\\phi(f)$ and evaluate $\\phi(f_i)=\\phi_i$." - ] - }, - { - "cell_type": "code", - "execution_count": 1, - "metadata": {}, - "outputs": [ - { - "data": { - "application/javascript": [ - "\n", - "try {\n", - "require(['notebook/js/codecell'], function(codecell) {\n", - " codecell.CodeCell.options_default.highlight_modes[\n", - " 'magic_text/x-csrc'] = {'reg':[/^%%pybind11/]};\n", - " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", - " Jupyter.notebook.get_cells().map(function(cell){\n", - " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", - " });\n", - "});\n", - "} catch (e) {};\n" - ] - }, - "metadata": {}, - "output_type": "display_data" - }, - { - "name": "stdout", - "output_type": "stream", - "text": [ - "Populating the interactive namespace from numpy and matplotlib\n" - ] - } - ], - "source": [ - "# Import the QICK drivers and auxiliary libraries\n", - "from qick import *\n", - "%pylab inline" - ] - }, - { - "cell_type": "code", - "execution_count": 2, - "metadata": {}, - "outputs": [], - "source": [ - "# Load bitstream with custom overlay\n", - "soc = QickSoc()\n", - "soccfg = soc\n" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### Hardware Configuration\n", - "\n", - "tProc channel 7 : DAC 229 CH3 <-> Readout channel 0 : ADC 224 CH0" - ] - }, - { - "cell_type": "code", - "execution_count": 3, - "metadata": {}, - "outputs": [], - "source": [ - "class LoopbackProgram(AveragerProgram):\n", - " def initialize(self):\n", - " cfg=self.cfg \n", - "\n", - " # set the nyquist zone\n", - " self.declare_gen(ch=cfg[\"res_ch\"], nqz=1)\n", - "\n", - " self.r_rp=self.ch_page(self.cfg[\"res_ch\"]) # get register page for res_ch\n", - " self.r_gain=self.sreg(cfg[\"res_ch\"], \"gain\") #Get gain register for res_ch\n", - " \n", - " #configure the readout lengths and downconversion frequencies\n", - " self.declare_readout(ch=cfg[\"ro_ch\"], length=self.cfg[\"readout_length\"],\n", - " freq=self.cfg[\"pulse_freq\"], gen_ch=cfg[\"res_ch\"])\n", - " \n", - " freq=self.freq2reg(cfg[\"pulse_freq\"], gen_ch=cfg[\"res_ch\"], ro_ch=cfg[\"ro_ch\"]) # convert frequency to dac frequency (ensuring it is an available adc frequency)\n", - " self.set_pulse_registers(ch=cfg[\"res_ch\"], style=\"const\", freq=freq, phase=0, gain=cfg[\"pulse_gain\"], \n", - " length=cfg[\"length\"])\n", - " \n", - " self.synci(200) # give processor some time to configure pulses\n", - " \n", - " def body(self):\n", - " self.measure(pulse_ch=self.cfg[\"res_ch\"], \n", - " adcs=[self.cfg[\"ro_ch\"]],\n", - " adc_trig_offset=self.cfg[\"adc_trig_offset\"],\n", - " t=0,\n", - " wait=True,\n", - " syncdelay=self.us2cycles(self.cfg[\"relax_delay\"]))" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### First, sanity check that we can see the pulse we want to calibrate" - ] - }, - { - "cell_type": "code", - "execution_count": 4, - "metadata": {}, - "outputs": [], - "source": [ - "config={\"res_ch\":6, # --Fixed\n", - " \"ro_ch\":0, # --Fixed\n", - " \"relax_delay\":1.0, # --Fixed\n", - " \"res_phase\":0, # --Fixed\n", - " \"length\":400, # [Clock ticks] \n", - " \"readout_length\":200, # [Clock ticks]\n", - " \"pulse_gain\":10000, # [DAC units]\n", - " \"pulse_freq\": 100, # [MHz]\n", - " \"adc_trig_offset\": 200, # [Clock ticks]\n", - " \"reps\":1, \n", - " \"soft_avgs\":1,\n", - " }\n", - "\n", - "prog =LoopbackProgram(soccfg, config)\n", - "(iq0,) = prog.acquire_decimated(soc, load_pulses=True,progress=False)" - ] - }, - { - "cell_type": "code", - "execution_count": 5, - "metadata": {}, - "outputs": [ - { - "data": { - "text/plain": [ - "" - ] - }, - "execution_count": 5, - "metadata": {}, - "output_type": "execute_result" - }, - { - "data": { - "image/png": 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9Dmk0q9Tik5jNsdw4NEKDm96N6opSRh+w4l8MVgcNGoukxfz3+Uhup8+c7/ErkjhYAZ2OI0NbsaRtFlEbBIFna9EGt0Gbmknsn+/gU91+/rJTT3hClX2fVjs7kOtiwaNC4lkJolVLWi76iJfSPyDr4A6e2+WKqcJIvqfA0DqQ9jvT0JvB2MyAW1E1Jkctzd95i3cT5zPpizMUegjOtNIzMM5ESbA3yzoXMkDfBfe4NBzKqwjwaUdF93bEp+4l8oiRIncNGnc3fDNKiemp5WSA5InNErOQaPV6DNWS98bpKHCx8vcNenwyy6jVa3D57D+07zWcwsP7Ofvu21BcQrVBS1xbWNk2jwI3SZczVgYnO9C1xoetA1yJ9jpN5HkDUSvK7Q11agvYHKGhe66B/rGVmPQadLVWKiI6kOhnoteGdGq1gAakhH2dBQS0oEc6uJ3KQSMlqRP6EDeyLUcP/8hLn5XhUld2cmsNaf4aOmSacbCAEAIPvQdmq5lyUzkGswa/YtsvbIuXO9oBvYlpVcwKfRxjTzhz754qWw/GIsnzd2bREBNBxQ6MPumCqbYKIQSuOlechSOW9DNYXAxoK6oxaWFvpAudLD5Yss5TpTEjn3mUgff9hdjcWGoK8qjed4DUohSqLdX4lGvofkbg0Lw5MjCA5km55DpUsMo3g9iWNTy+2UrvUxKNmxtWo5EyNy27O1lpny3omGXF4iDQmiUH7m+PsbUXd314iNNjetA115Hy2EO8MEUQmCt55kcrOrOk2kVH3Lwp7DUeY9xbB2lmlGjc3XAprqZ0was8mTKH/1kp6ZBlJbZ/c3rvLeK0r5WFD7ngl1fL6IOSDmGDaDduMi69e7Nh/5eUvzefsONl1Hi54Pv8DI6FOvHVnvn03pnDXXESXFxo/tyznL6zPcxfjOeaPRQ9NJiyklyCtiaxv5sjAb7tab0lgRM9m3Fn/0co/GC+PRBFD9ZzpC3MXWpG98C9vNz3DH47EvjLetsPDYBKRzjRzoEW+WZ8S+Fwn2b0PlDMWW/Jhp4axu/X4FdgprilG/23Hbzq9q+uHb0tA8jDwMhfBJDeUspnG8vf1B4IgDSZEDqdffr89g1U/LiRwKgZ6IOC2HxmM3/dPoNBpxx4pnYAwVOexik0FCklp4/vwvLeIqwHjuAyaCCFf3mA+QXRnD59mKEpBh6x9MT3vgeoGdiDD+M+pJmhGSNbDycwX6IPDKRIU8WY78cQmFzCkHhB/5FT6DjucbSenqSWpNJM74lLVhH6wEA0BgNSSr7aPg/3BdGEHC9CTp1El7++Sq2llmUnl+H8wx66Lz2A58MP02LOa/VOayQWJrL5zGbOlJ2hd4vetHZsgeeBZLyOpuHcqxee48YBUJp2ivP/fhuf8L6433sPZr9mPLbxMYx553jnaCfcKqw4hYfjFTWNZ7c/S2xOLP8JeI7uDkFo3VwxhIVRYjaSV5FLYKEGfUAAGhcXzFYzc/fPJTolmrva3MXfev2Nlq4tyUw5wpbP/4EmIQXn0DBGTX0L5+C2lNaUsvu7+QT/71cIR0c8774H3/95iZmHXiPmTAyB7oG80PMFhrQZAkCtpZaU3etwmPkOQqfD728vUjqkBzFnYshJjOXBj06gt2po/ckiSlt78W7su2xI38DD7nfyYvgMnIPbXvIYKa4u5mTRSaSUhHqH4mmwnU7YeXYnP6T9QA8RiP5MDqerMmneeyCDA4fQ1qMtpStXUnX8BK4DB+A2fDhCp+PoluWcW7cKc2U52scm0C/ifpo72U7jmYuLsZSU4BgcDEBhVSHLdr6P89kCQltH0mPYJCSS+IJ4TFYTwR7BtHRtCUBCYQJLE5bSocaTwZ69aNdzqP1UWWZZJs2dmuOQW0zh55+zjZP8q/VxHuw4jukR02lmaNZgmyv27aPk229x7NSZrN5tmJ/7LYdzD+Omd2P+sPl09+l+1d+1ouoiFh5bSBuXVow650vFzl04+Pni/cSTZFkL0Gv0uB1JwbhtGwnms8xofwBXvRuvb/Sg1UHbD0T/f/4T47CeOOmccC+soXDhAtxGjMB14EAAChKOUjjvPxgsGjzHjcPjvvtYHL+Y3IxE7l6ahD7+NA4tWpD7/l/ZXn4EvVbPn7v9udF9UJuZiYO3NxoX26nRanM1ORU5BFTo0bi4oPWwnaqVFgs5c+dSsnwFANpHH+bZkP1kV2Tz9DFf7txg6+m53z8a5789S+IrL9Jsx3EANO7utNuwHrOHC0fzjkLmeVoZ9WhcnFli3Qs6LUP03fB+9m0sxcU49+6N6aWncPD1JcgjiJq0dCxFhThH/moMaNTtGkB+k1NYV+qrk1/R3rM9ffwbvipbSomlpAStp6e9wS6rLUNKab8WcDmlNaVkV2TT3Km5vSG5EqbcPPs59ouZCwvRNmtWL3hcqxpLDbWWWtz0bvXXZTVTXltub1B/jZSS3MpcWri0aDAvtyIXX2ffBvU25eai9fKyX1cyW83kV+bj79rw+hOApaQEodejcXaul26trERaJVpXl19d5+3OKq0UVhXi4/yrg7DWU1Zbhk6jw8nB6dczXwfF1cW46l2R53NJf2gcXo9Mwve5566pTEtJCWi1aN3cfj3zVZBSUrJiBcLghOeDD2Cy2G6U8TR4UrZhA6bcXJpNnowQAmtNDfnv/x+6Fi1wGzEcXYuG34cG9S4tBSHQurtf13rfrgHEATgFDAPOAYeAR6SUCY3lv9EBRFGUm+uXZwqU6+NKA8gtdReWlNIshIgCNgFa4PNLBQ9FUW5/KnjcXLdUAAGQUq4H1t/seiiKovy3u+UeJFQURVF+H1QAURRFUZpEBRBFURSlSVQAURRFUZpEBRBFURSlSVQAURRFUZpEBRBFURSlSVQAURRFUZpEBRBFURSlSVQAURRFUZpEBRBFURSlSVQAURRFUZpEBRBFURSlSVQAURRFUZpEBRBFURSlSVQAURRFUZpEBRBFURSlSVQAURRFUZpEBRBFURSlSVQAURRFUZpEBRBFURSlSVQAURRFUZpEBRBFURSlSVQAURRFUZpEBRBFURSlSVQAURRFUZpEBRBFURSlSVQAURRFUZpEBRBFURSlSVQAURRFUZpEBRBFURSlSVQAURRFUZpEBRBFURSlSVQAURRFUZpEBRBFURSlSVQAURRFUZpEBRBFURSlSW5KABFCPCyESBBCWIUQkb+YN1sIkSqESBZCjLwo/e66tFQhxKzfvtaKoijKxW5WDyQeGAvsujhRCNEFmAiEAncDHwkhtEIILfAhcA/QBZhUl1dRFEW5SRxuxkqllCcBhBC/nDUGWCGlrAHShRCpQO+6ealSyrS65VbU5U38bWqsKIqi/NLv7RpIAHD2oumsurRLpTcghJgqhDgshDicn59/wyqqKIry3+6G9UCEEFuAFo3MellKueZSizWSJmk80MnGCpBSLgIWAURGRjaaR1EURbl2NyyASCnvasJiWUDri6ZbAefr/r5U+nUnpWTZgUzu79YSD2fdjVqNoijKLe33dgprLTBRCOEohAgGQoCDwCEgRAgRLITQY7vQvvZGVSKtoIL/XZfItK9jMVmsN2o1/zWkVB1BRbkd3azbeB8UQmQB/YAfhRCbAKSUCcA32C6ObwSekVJapJRmIArYBJwEvqnLe0O083HlzbFd+Sm1kNfX/XydXkrJykOZxJ8rveZ1WK2SWvPtH5yW7T/DsHd3crao8oqXqaq13MAaXZ2b8Rn9no4Lk8Xa6A8Ak8V6zT+uas1W8ozVVNSYr6mcy6kx/36OpdvRTQkgUsrVUspWUkpHKaWflHLkRfPekFK2k1J2lFJuuCh9vZSyQ928N250Hcf1bMVj/YP4cv8Z0gsqAPhsTzozo0/w8IJ9bE/Kq5d/+cFMNsbnXFHZpVUmHvl0P73e2MKy/WfsDcbZokpOZpeRb6yx57VYJZ/uTuPD7amk5pXXKyc6Nosv92Vc8RfZZLFS3siX9URWKfM2n6pXTnFFLcsPZvL6ukRKq0z29B+PZzNjZRwvrT5BdmmVPX3nqXze+DGRn1IL7A1OYXkNb29IIq2ggieXHK637uQcI//ccJLSyp/LXn4wk+Hv7ST0tY2siTvXoJ55ZdX1GrO9qQX8c/1JtifnYW5kHxSW13Ayu4yMgooGjaDVKsktq77s/toYn0P3f8Tw3uZT9rTDGUW88M0x/vpNHLFnihtdZ7Wp6Y1Wco6RXm9s4dnlRxs0fhe250IwllJyOKOIf29Krre/SitNzFmbwIyVcUTHZtnTa8wW3o1Jtv8AklKyOTGXuT8ksjkxl5PZZZwv+fkzLaqoZeS8XTz08V4Ky23HZL6xhqivjxD+jxge+njvZY+9WrOVpJwyknLKGuyTnNJqhvx7B73f2ErfN7dyKtdon/fNobO8F5PM0cxirNafP7eyapO9Hhfbm1rARztS6+U9nV/OHz89QMTrm4k7W3LJOl5grDbx/dFzzFmbQJ7x5+Ni7+kC3t+SgrHadMlld6fk8/q6RDbGZzd6vJVWmTiZXUZmYf0fUWaLleKK2kuWm1dWXe+4tlolqXlGTmbX359xZ0v418akeu1DcUUtyTlGbjRxO59eiIyMlIcPH27y8nll1fR/axuT+wfRv503Ty49zLBOfuSUVZGcY2TH34YQ4OnEnpQC/vjZAQCeGxZCZJAXCefLOJhehMlipaWHE0M7+zKsky/55TU89vkh0grK6dLSg2NnS3B1dKCZi57MuoZBr9Xw3oTu3NGuOTOjjxOTmAuAViP4+sk+9GnrzZHMYsZ9vBerhI5+bnz2WCStvJypNln4bE86ZdUm/jKoHc1c9ABsS8rlH+sSOV9SxZMD2/Ls0PY46x3YlpTLM18dpcpk4cURHYgaGkK1ycJd7+0kq9jWmAwMac4Xj/ViV0o+Tyw5jLeLHmO1mbY+rqx6qh+n88sZv3Af1Sbbwf7MkHb8bWQnXvk+nq8PZvLa6C78Y10igzv48MmjkRxML2Lql4cxVpvp4OfKgj/2JP58GdOXHyW8tScWqyQ518jyP/elZ6AXuWXVvLn+JGvizvNAeEv+ObYb3x3N4tU1CVjqGo2BIc35+I89cXV0oLiili/2ZrBg52l7cA7wdKKtj4v9sz2ZXUZBeS1DO/nSt20z4s6WENrSg9HdWtLG25lvD59lZvRx3Aw6SqtMvHxvZ5z0Wl5fl4iTXouUEgmsnnYH7X1dOZxRxOs/JHI8q5Q+wc1Y/ue+aDSCs0WVvL0xia4BHozq3pIATycA4s+V8vGO05RVm2jTzJnnhoVQa7EycdF+SqtMGKvN9A5qxr/GdcPDSddgex4Ib0luWQ370grt2/T0ne1s/5bFciCtCE9nHUUVtax/biAd/dx44dtjfHfkHM56LdPubMfe04XsPV2IRsCFtlcImNirNfd29eeDbanEnS1BAC09nXjzwa78a1MSJ7PLGNLRlw3xOTx/VwjP39WBnFLbZ1RcWYu3i56urTxZui+DM3WNppNOy4CQ5gzr5EuAlxP/2phMWn45L4zoyLwtp+gZ6MXiKb1Zd+w8zy4/at+m5q56Ovu7U1lr4djZEsxWSfdWHrw6ugs9A5vxzeGzzP7uBBarZPqwEP46vAMns8sY9/FeNBqBs16LVcLKqX0Jbu5CUo6RbUl5HM4oqivLk7vDWvDUslj78T62RwDvTQgnz1jNiHm7KKk04ePmyLzx4QwIac7xrBLWn8ghMbsMY7WJo5kl9fYhQEsPA0M7+9LC3cDCXWkYq20/nqYOasusuztxvrSKyZ8f5HR+Rb3tMVusLNt/hqX7zpBWUEGIrysv39eZXkHNeG5FHFtO5tqP5yl3BBF3toQfT2QjJei0gt7BzaiosXA8q4SwAA/WRg1oStOHECJWShn5q/lUALm8qK+PsDM5H6uUtPVx5Zu/9KOgvIZB72xn2p3teGpwO+7+z24cdRpCW3qw7tjP1/ZDfF1xcXTgdH45xmoznf3dKa2spazazMI/9aR/O292nspnU0IO+cYaBrRvjp+7gc9/SufwmWIEtlvNXh3VhXvC/Bm/cB9CwOeP9WLq0sNU1VqYeU8n/uf7eFp6OPHM0Pb8a2MSWcVVaAS4GXTc370l50uq2JqURzsfF8ICPFgMh5uVAAAgAElEQVQTdx5/DwMRbbz48UQ2oS3d8fcwsPNUPt8/cwc7kvN5Z1Mynz4aSWFFDTOjTxDo7UxuWTXtfW374GB6EY8vPoS/hxNl1SbcDTpWTO3LvC2n+P7oOR7tF8SSfRk82jeQf4wJ48t9GbyyJoHurTw4fq6Udj6uPDOkHa98n0B5jRkhoFdgM5Y92YfyGjMPfPgTOaXVjOruz6b4HExWyZCOPmxKyMVBIzBbJQNDmvOfCeFsiM/htbUJeLvo8XDScTq/HKuE+7u35J6wFhRV1rLrVD55F/XsWns506aZM4v3ZlBeY6alh4HzpdU467U8Pbgd729NoV87bz78QwR/WRprb6gjA734dHKkvY46rYa7w1rw9YFMfN0d6RPszarYLF4d1YWHI1vx0Md7SS+owGSRuBsceG98ONuT8/j6YCaeTjoCvV1IPF8GwvaL3dFBw7dP9SO9oIKXV8dTY7Zgscp623P8XCmf7U7H2VHLC8M7MLp7S97emMzyg5n2huydcd0Y3sWPQf/aTtdWHgQ3d2HZ/kyeHBDM3tOFJGaX2RuhP/QJJO5sCaVVtRzKKGbJ3gzMda3h+xPDCfB0Iurro+TU9dgW/DGCu8P8eX7FUX44ns0f+wYSk5BDSZWJji3cOFtUSUF5Le18XHj6zvboHTQczihi68k8ztX1cISATx+NZFhnPz7ZlcYb608yJrwlG+Nz6NbKgw8fiWBfWiFbT+ZxtrgSB40gMqgZro4OrDiUSV5ZDZFBXvyUWsiA9s3xdXfkuyPnGBsRwIG0IsxWK6un3YGx2sxDH++lvMaMl7OO4roeb0c/N/QOGk7U9caau+p5f2IPdqcUsGDnaZY90Ycvfkpnd2oB/364Ox9uS+V0fjn92nmzO6UAB42gk78beq2GYZ39mHJHEPHnyiiqqKGowsSO5Dx2pxRQZbIwMKQ5E3u1YU9qAcsPZhLk7UxxpQkpJX/qF8jaY+fJK6vhkT5t2HUqn9P5FfQK8mJQiA/fxJ7lbFEVDhqBRUpm3NWB1s2cWLgzjaQcI17OOh6ObM0jvdvwye40ErPL0Gk19AluxrDOfoS39mxSu6cCCNcngBxML2L8wn34uTuy5pkBtPAwAPDkkkMczSyhRxsvtiXlsurp/oS38iThfBnVZgutvZzteU0WKxvjc/jn+pOYrJLFU3oR2tLjkuusNln4YFsKWiG4O8yfLi3dAdifVsjERfsB0AhY8nhvBob4sDsln8e+OITFKung58o/7g/D21XPvM2n2JGcj0bAc3eF8Fj/YPQOGmLPFPHqmgRO5RrtvZFqk5UR83ZhrDahEYKBIc1Z9Kjt+Fm6L4PdKQW4GRz4+8hO9u1ad+w8a4+dx9FBw3PDQgjxc6Os2sTIebvILq1mRBc//m9SDww6LQBz1ibw5f4zPNovkBnDO+Bu0HG+pIoN8TmcyjHy97s74u3qCECesZo3fzzJ93HnGdrJl9dGdyHQ24Ufj2ezP62QASHNGdrJF53WdhZ2d0o+X+3PxCIlnVu4MSK0BWEBl97HF5RWmqioNdPS04ms4kqmLo0lMbuMEF9XvpvWHzeDjlqzlRPnSgBB1wAP9A62dR7PKmHO2gSOni0hvLUnn03uhZezjieWHGbXqXyc9Voqay0sfbw3LTwMPLn0MGn5FWg1gkf7BfL8XR3wcNKRXlDBZ3vS8Pdw4r6u/gQ1t/WU8sqqWbgrDRe9tsH2FFfUonPQ4Opou5FSSsm+tEK2JObRupkTU+4IBuDT3WnM/fEkQsCU/sG8MqozJovt9F0rL6fGHublXEkV50uq8HbR09bHFYCKGjOf7E7D38PAhF5tACiprGVm9HF2JOfj7qTji8d6ERbggdUqSS+soLWXs31fXahjal45JVUmfN0cCfS2bWeN2cI9/9nNuZIqBnfw4Z9ju9qPg8YUVdTy+OJDnMo1Mn1YCE8MCEZKeG1tAj8eP4/JIvnmL/3o2sq2v84WVbL+RDbJuUb6BDdjSEdffN1tx3DsmWK+PXyWp+9sR6C3C8ZqE3e+s4PCulNL/3NfZ54c2NbWo18ay5HMYp6+sx1T7gjGw+nyd2hWmyycL6kiuLkLQgjb3Z37z7ArpQCDTkvUkPZ0bOFGUUUtTyw5RNzZEnq09mTqoLaMDG2BEIJqk4UtJ3PZn1bIkI6+DOvsB9hOf2UUVhLc3AWtprGnH66NCiBcnwAipeTL/Wfo19abED83e/quU/k8+vlBAF4b3cX+hb2cWrMVs9WKs77pd09/e/gsRRW1jAhtQXDzn0/JbIzPoaC8hgm9WtsbVbAdxFKCk15brxyrVWKyWnF0+Dk9u7SKuT+eZHddT+RC43G14s+Vsj+tkCl3BNc7uKWUlFWbf/WLd7Fqk8UegH4LxmoTn+/JYFxkK/vppl9TXmPGRa+1N8YF5TUs2HGailozd3X2s3/piytq+WxPOvd186ezv/sN24aL1ZqtLNx5mkEdfOjexF+jv6baZMFBI3DQNv2SamWtGY0QV/xZmy1WqkwW3Az1jyWTxUpljeWabr/fk1LA4TNFDOnoW2+fWa2S8loz7obrf2u/lJKKWov9B8HNpgII1yeAXIrVKpn8xUG6+Lsz655Ojf6Su1VZrRLNDfhVoyjKreFKA8jvI9zdgjQawZdP9LnZ1bghVPBQFOVK/N4eJFQURVFuESqAKIqiKE2iAoiiKIrSJCqAKIqiKE2iAoiiKIrSJCqAKIqiKE2iAoiiKIrSJCqAKIqiKE2iHiRUFOWamUwmsrKyqK6+/BD5yu+LwWCgVatW6HRNG55FBRBFUa5ZVlYWbm5uBAUF3VbD+tzOpJQUFhaSlZVFcPCvj+XXGHUKS1GUa1ZdXY23t7cKHrcQIQTe3t7X1GtUAURRlOtCBY9bz7V+ZiqAKIpyW3B1bdrrB25UOY157rnnCAgIwGr9+VW1ixcvxsfHhx49ehASEsLIkSPZu3dvveX+/e9/06lTJ8LCwujevTtLly5tUHZRURHDhw8nJCSE4cOHU1zc8JXL15sKIIqiKL8Bq9XK6tWrad26Nbt27ao3b8KECRw9epSUlBRmzZrF2LFjOXnyJAALFixg8+bNHDx4kPj4eHbt2kVjr+F46623GDZsGCkpKQwbNoy33nrrhm+TCiCKoty2Zs6cyUcffWSfnjNnDu+++y7l5eUMGzaMiIgIunbtypo1axosu2PHDkaNGmWfjoqKYvHixQDExsYyePBgevbsyciRI8nOzgZsjf2CBQsarcv27dsJCwvj6aefZvny5Zes85AhQ5g6dSqLFi0C4M033+Sjjz7C3d32EjIPDw8mT57cYLk1a9bY0ydPnsz3339/uV1zXai7sBRFua7+sS7B9p7366hLS3deGx161ctNnDiR559/nmnTpgHwzTffsHHjRgwGA6tXr8bd3Z2CggL69u3L/ffff0XXBEwmE88++yxr1qzBx8eHlStX8vLLL/P555/z1FNPXXK55cuXM2nSJMaMGcNLL72EyWS65O2zERERLFy4EKPRiNFopF27dr9ar9zcXPz9/QHw9/cnLy/vV5e5ViqAKIpy2+rRowd5eXmcP3+e/Px8vLy8aNOmDSaTiZdeeoldu3ah0Wg4d+4cubm5tGjR4lfLTE5OJj4+nuHDhwNgsVjsDfel1NbWsn79eubNm4ebmxt9+vQhJiaG++67r9H8F05RSSl/1zcnqACiKMp11ZSewo00btw4Vq1aRU5ODhMnTgTgq6++Ij8/n9jYWHQ6HUFBQQ1uZ3VwcKh3sfvCfCkloaGh7Nu374rrsHHjRkpLS+natSsAlZWVODs7XzKAHD16lM6dO+Pu7o6LiwtpaWm0bdv2suvw8/MjOzsbf39/srOz8fX1veL6NZW6BqIoym1t4sSJrFixglWrVjFu3DgASktL8fX1RafTsX37ds6cOdNgucDAQBITE6mpqaG0tJStW7cC0LFjR/Lz8+0BxGQykZCQAMD8+fOZP39+g7KWL1/Op59+SkZGBhkZGaSnpxMTE0NlZWWDvDt37mTRokX8+c9/BmD27Nk888wzlJXZTguWlZXZr49c7P7772fJkiUALFmyhDFjxlz1vrpaqgeiKMptLTQ0FKPRSEBAgP1U0x/+8AdGjx5NZGQk4eHhdOrUqcFyrVu3Zvz48XTr1o2QkBB69OgBgF6vZ9WqVUyfPp3S0lLMZjPPP/88oaGhJCUlcccdd9Qrp7Kykk2bNrFw4UJ7mouLCwMGDGDdunUArFy5kj179lBZWUlwcDDR0dF07twZgKeffpry8nJ69eqFTqdDp9PxwgsvNKjvrFmzGD9+PJ999hlt2rTh22+/vT478DJEY7eD3S4iIyPl4cOHb3Y1FOW2d/LkSXuD999s1KhRfPfdd+j1+ptdlSvW2GcnhIiVUkb+2rKqB6IoinKd/PDDDze7Cr8pdQ1EURRFaRIVQBRFUZQmUQFEURRFaRIVQBRFUZQmUQFEURRFaRIVQBRFuS1kZWUxZswYQkJCaNu2LVFRUdTU1FxzuRkZGYSFhV2HGjZuzJgx9OvXr17anDlzCAgIIDw8nJCQEMaOHUtiYqJ9vslkYtasWYSEhBAWFkbv3r3ZsGFDg7LT09Pp06cPISEhTJgwgdra2utadxVAFEW55UkpGTt2LA888AApKSmkpKRQVVXF3//+95tdtcsqKSnhyJEjlJSUkJ6eXm/ejBkziIuLIyUlhQkTJjB06FDy8/MBeOWVV8jOziY+Pp74+HjWrVuH0WhsUP7MmTOZMWMGKSkpeHl58dlnn13X+qsAoijKLW/btm0YDAamTJkCgFarZd68eSxdupTy8vJ6eSdMmMD69evt04899hjR0dFkZGQwcOBAIiIiiIiIaPBSJ7C9/CkqKso+PWrUKHbs2AFATEwM/fr1IyIigocffti+3ldffZW1a9c2Wu/o6GhGjx5tH27lUiZMmMCIESP4+uuvqays5JNPPuGDDz7A0dERsI2DNX78+HrLSCnZtm2bffiWGzHE+015kFAI8Q4wGqgFTgNTpJQldfNmA08AFmC6lHJTXfrdwPuAFvhUSnnj35aiKMrV2zALck5c3zJbdIV7Lv2VT0hIoGfPnvXS3N3dCQoKIjU1lfDwcHv6xIkTWblyJffeey+1tbVs3bqVjz/+GCklmzdvxmAwkJKSwqRJk7jSkSwKCgqYO3cuW7ZswcXFhbfffpv33nuPV199lddff/2Syy1fvpzXXnsNPz8/xo0bx+zZsy+ZNyIigqSkJFJTU2nTpo39/SCXUlhYiKenJw4Otma+VatWnDt37oq250rdrCfRNwOzpZRmIcTbwGxgphCiCzARCAVaAluEEB3qlvkQGA5kAYeEEGullImNlK0oyn+ZSw173thQTffccw/Tp0+npqaGjRs3MmjQIJycnCgtLSUqKoq4uDi0Wi2nTp264vXv37+fxMRE+zhYtbW1Da5r/FJubi6pqakMGDAAIQQODg7Ex8df8nrL1Q471Vj+6z00/E0JIFLKmIsm9wPj6v4eA6yQUtYA6UKIVKB33bxUKWUagBBiRV1eFUAU5ffmMj2FGyU0NJTo6Oh6aWVlZeTm5tKxY8d66QaDgTvvvJNNmzaxcuVKJk2aBMC8efPw8/Pj2LFjWK1WDAZDg/Vcboj34cOHX/ZNg7+0cuVKiouLCQ4Ottd3xYoVzJ07t9H8R48eJTIykvbt25OZmYnRaMTNze2S5Tdv3pySkhLMZjMODg5kZWXRsmXLK67flWjyNRAhxPUa9OVx4MLtAwHA2YvmZdWlXSq9sXpNFUIcFkIcvnDBSVGU29uwYcOorKxk6dKlgO0lTy+88AJRUVE4OTk1yD9x4kS++OILdu/ezciRIwHbEO/+/v5oNBq+/PJLLBZLg+WCgoKIi4vDarVy9uxZDh48CEDfvn356aefSE1NBWwj8F7owcyePZvVq1c3KGv58uVs3LjRPsR7bGzsJa+DREdHExMTw6RJk3B2duaJJ55g+vTp9ruqsrOzWbZsWb1lhBAMGTKEVatWATdmiPdruYj+58vNFEJsEULEN/JvzEV5XgbMwFcXkhopSl4mvWGilIuklJFSykgfH58r2xJFUW5pQghWr17NqlWrCAkJwdvbG41Gw8svv9xo/hEjRrBr1y7uuusu+8i506ZNY8mSJfTt25dTp07h4uLSYLk77riD4OBgunbtyosvvkhERAQAPj4+LF68mEmTJtGtWzf69u1LUlISACdOnGjwpsOMjAwyMzPp27evPS04OBh3d3cOHDgA2HpEF27jXbZsGdu2beNCmzZ37lx8fHzo0qULYWFhPPDAAzTW3l24FtO+fXsKCwt54oknrnbXXtZNG85dCDEZeAoYJqWsrEubDSCl/Gfd9CZgTt0ic6SUIxvLdylqOHdF+W383oZz37t3L5MmTeK7775rcHH9tzZy5Eg2bdp0U+twOTd8OHchRDqN/OKXUl7+HYuXLu9uYCYw+ELwqLMW+FoI8R62i+ghwEFsPZAQIUQwcA7bhfZHmrJuRVFuf/3792/0LYM3w+85eFyrK72IfnEkMgAPA82uYb3zAUdgc91dAfullE9JKROEEN9guzhuBp6RUloAhBBRwCZst/F+LqVMuIb1K4qiKNfoigKIlLLwF0n/EULsAV5tykqllO0vM+8N4I1G0tcD6xsuoSiKotwMV3oKK+KiSQ22Hsml7x9TFEVRbntXegrr3Yv+NgPpwPhL5FUURVH+C1zpKawhN7oiiqIoyq3lWh4kjPj1XIqiKL8NV1fX31U5jXnuuecICAio9zT74sWL8fHxoUePHoSEhDBy5MgGAzn++9//plOnToSFhdG9e3f7A5MX+/bbbwkNDUWj0VzxGF7X6loeJHz6utVCURTlNme1Wlm9ejWtW7dm165d9eZNmDCBo0ePkpKSwqxZsxg7diwnT54EYMGCBWzevJmDBw8SHx/Prl27Gh3nKiwsjO+++45Bgwb9JtsDVxFAhBBeQojeQohBQohBwJc3sF6KoijXbObMmXz00Uf26Tlz5vDuu+9SXl7OsGHDiIiIoGvXrqxZs6bBsjt27GDUqFH26aioKBYvXgxAbGwsgwcPpmfPnowcOZLs7GzA1tgvWLCg0bps376dsLAwnn766cuOmTVkyBCmTp3KokWLAHjzzTf56KOP7KPvenh4MHny5AbLde7cucG4Xzfald6F9STwHNAKiAP6AvuAoTeuaoqi3IrePvg2SUVJ17XMTs06MbP3zKtebuLEiTz//PNMmzYNgG+++YaNGzdiMBhYvXo17u7uFBQU0LdvX+6///4rGq3WZDLx7LPPsmbNGnx8fFi5ciUvv/wyn3/+OU899dQll1u+fDmTJk1izJgxvPTSS5hMJnQ6XaN5IyIiWLhwIUajEaPRSLt27a56238LV3oX1nNAL2wP/A0RQnQC/nHjqqUoinLtevToQV5eHufPnyc/Px8vLy/atGmDyWTipZdeYteuXWg0Gs6dO0dubm6DMasak5ycTHx8PMOHDwdsAzf6+/tfdpna2lrWr1/PvHnzcHNzo0+fPsTExHDfffc1mv/CKapLDVP/e3GlAaRaSlkthEAI4SilTBJC/LZ9JUVRbglN6SncSOPGjWPVqlXk5OQwceJEAL766ivy8/OJjY1Fp9MRFBRkH5r9gssN3R4aGsq+ffuuuA4bN26ktLSUrl27ArbRep2dnS8ZQI4ePUrnzp1xd3fHxcWFtLQ02rZt0shRN9SVXgPJEkJ4At9jG35kDXD+xlVLURTl+rjwuthVq1bZX+9aWlqKr68vOp2O7du3NzpuVmBgIImJidTU1FBaWsrWrVsB6NixI/n5+fYAYjKZSEiwjaw0f/585s+f36Cs5cuX8+mnn9qHbk9PTycmJobKysoGeXfu3MmiRYv4859tA57Pnj2bZ555hrKyMsD23pAL10dutit9DuTBuj/nCCG2Ax7AxhtWK0VRlOskNDQUo9FIQECA/VTTH/7wB0aPHk1kZCTh4eF06tSpwXKtW7dm/PjxdOvWjZCQEHr06AGAXq9n1apVTJ8+ndLSUsxmM88//zyhoaEkJSXZ30p4QWVlJZs2bWLhwoX2NBcXFwYMGMC6desA28ul9uzZQ2VlJcHBwURHR9tHyH366acpLy+nV69e6HQ6dDodL7zwQoP6rl69mmeffZb8/Hzuu+8+wsPDb/hAjjdtOPffghrOXVF+G7+34dxvllGjRvHdd9/Z3zFyK7jhw7kriqIov+6HH67Xi1pvDdfyIKGiKIryX0wFEEVRFKVJVABRFEVRmkQFEEVRFKVJVABRFEVRmkQFEEVRbgtZWVmMGTOGkJAQ2rZtS1RUFDU1NddcbkZGBmFhYdehho0bM2YM/fr1q5c2Z84cAgICCA8PJyQkhLFjx5KYmGifbzKZmDVrFiEhIYSFhdG7d282bNjQoOz58+fTvn17hBAUFBRc97qrAKIoyi1PSsnYsWN54IEHSElJISUlhaqqKv7+97/f7KpdVklJCUeOHKGkpIT09PR682bMmEFcXBwpKSlMmDCBoUOHkp+fD8Arr7xCdnY28fHxxMfHs27dOoxGY4Py77jjDrZs2UJgYOANqb8KIIqi3PK2bduGwWBgypQpAGi1WubNm8fSpUspLy+vl3fChAmsX7/ePv3YY48RHR1NRkYGAwcOJCIigoiIiAYvdQLby5+ioqLs06NGjWLHjh0AxMTE0K9fPyIiInj44Yft63311VdZu3Zto/WOjo5m9OjR9uFWLmXChAmMGDGCr7/+msrKSj755BM++OADHB0dAfDz82P8+IZvGe/RowdBQUGXLPdaqQcJFUW5rnLefJOak9d3OHfHzp1o8dJLl5yfkJBAz54966W5u7sTFBREamoq4eHh9vSJEyeycuVK7r33Xmpra9m6dSsff/wxUko2b96MwWAgJSWFSZMmXfGb/QoKCpg7dy5btmzBxcWFt99+m/fee49XX32V119//ZLLLV++nNdeew0/Pz/GjRvH7NmzL5k3IiKCpKQkUlNTadOmjf39IDeTCiCKotzyLjXseWNDNd1zzz1Mnz6dmpoaNm7cyKBBg3BycqK0tJSoqCji4uLQarWcOnXqite/f/9+EhMT7eNg1dbWNriu8Uu5ubmkpqYyYMAAhBA4ODgQHx9/yestv8dhp1QAURTlurpcT+FGCQ0NJTo6ul5aWVkZubm5Dd7SZzAYuPPOO9m0aRMrV65k0qRJAMybNw8/Pz+OHTuG1WrFYDA0WM/lhngfPnz4Zd80+EsrV66kuLiY4OBge31XrFjB3LlzG81/9OhRIiMjad++PZmZmRiNRtzc3K54fTeCugaiKMotb9iwYVRWVrJ06VLA9pKnF154gaioKJycnBrknzhxIl988QW7d+9m5MiRgG2Id39/fzQaDV9++SUWi6XBckFBQcTFxWG1Wjl79iwHDx4EoG/fvvz000+kpqYCthF4L/RgZs+ezerVqxuUtXz5cjZu3Ggf4j02NvaS10Gio6OJiYlh0qRJODs788QTTzB9+nRqa2sByM7OZtmyZVe7266ZCiCKotzyhBCsXr2aVatWERISgre3NxqNhpdffrnR/CNGjGDXrl3cdddd9pFzp02bxpIlS+jbty+nTp3CxcWlwXJ33HEHwcHBdO3alRdffJGIiAgAfHx8WLx4MZMmTfr/9u48Pqrq/OP452GRIIKsKrLIKkpZBFEQVyqKoILWtoJaqRatP7Wv2urP9We1Lq1Way1WcF9wr4KCShXZFEUQRDYFZQu7CGHfAknO74/nxkySCYQbMhPt9/16zSvJmTv3Pvfcc89zzp3JHTp06EC3bt2YP9/fB5ozZ06xbzrMzMxk2bJldOvW7fuy5s2bU6tWLaZOnQr4jCj/Y7wvvvgi48ePp0GDBgDcc889NGjQgLZt29KuXTvOO++8759LNHjwYBo3bsyKFSvo0KEDgwYN2teq3SPdzl1Eyqyi3c598uTJDBgwgBEjRhR7cz3VevXqVe7fy1EWup27iEiC7t27J/2WwXSoyMmjrHQJS0REYlECERGRWJRARGS/+DG/n/pjVdZjpgQiImWWkZFBVlaWksgPSAiBrKyspP/vUlp6E11Eyiz/o6L5N/uTH4aMjAwaN24c+/VKICJSZlWrVv3+P6rlv4cuYYmISCxKICIiEosSiIiIxJKWBGJmd5vZbDObaWZjzOzwqNzMbLCZLYye75zwmoFmtiB6DExH3CIiUiBdM5AHQggdQgjHAO8Af4rKewOto8eVwFAAM6sL3AF0BY4H7jCzOimPWkREvpeWBBJC2JzwZw0g/8Pj/YBhwU0BaptZQ6AX8EEIYX0IYQPwAXBWSoMWEZFC0vYxXjO7F7gU2AT0iIobAcsTFlsRlZVUnmy9V+KzF5o2bbp/gxYRke+V2wzEzMaa2dwkj34AIYTbQghNgJeA/G+pL/6dlD47Kam8eGEIT4QQuoQQuiS7P76IiOwf5TYDCSH0LOWiLwPv4u9xrACaJDzXGFgVlZ9WpHximYMUEZHY0vUprNYJf/YF5ke/jwIujT6N1Q3YFEJYDbwPnGlmdaI3z8+MykREJE3S9R7IfWbWBsgDlgJXReWjgT7AQmA7cBlACGG9md0NTIuWuyuEsD61IYuISKK0JJAQwgUllAfgmhKeewZ4pjzjEhGR0tN/oouISCxKICIiEosSiIiIxKIEIiIisSiBiIhILEogIiISixKIiIjEogQiIiKxKIGIiEgsSiAiIhKLEoiIiMSiBCIiIrEogYiISCxKICIiEosSiIiIxKIEIiIisSiBiIhILEogIiISixKIiIjEogQiIiKxKIGIiEgsSiAiIhKLEoiIiMSiBCIiIrEogYiISCxKICIiEosSiIiIxKIEIiIisSiBiIhILEogIiISixKIiIjEogQiIiKxKIGIiEgsSiAiIhKLEoiIiMSiBL+1IyoAABRySURBVCIiIrEogYiISCxpTSBmdoOZBTOrH/1tZjbYzBaa2Wwz65yw7EAzWxA9BqYvahERAaiSrg2bWRPgDGBZQnFvoHX06AoMBbqaWV3gDqALEIDPzWxUCGFDaqMWEZF86ZyB/AO4EU8I+foBw4KbAtQ2s4ZAL+CDEML6KGl8AJyV8ohFROR7aUkgZtYXWBlCmFXkqUbA8oS/V0RlJZUnW/eVZjbdzKavXbt2P0YtIiKJyu0SlpmNBQ5L8tRtwK3AmclelqQs7KG8eGEITwBPAHTp0iXpMqW2YwNsWgGHtS/TakREfozKbQYSQugZQmhX9AEsBpoDs8wsE2gMzDCzw/CZRZOE1TQGVu2hvHx9+AA8fiosmlDumxIR+aFJ+SWsEMKcEMIhIYRmIYRmeHLoHEL4FhgFXBp9GqsbsCmEsBp4HzjTzOqYWR189vJ+uQe7dj6EXHh9IGQtKvfNiYj8kFS0/wMZjc9QFgJPAlcDhBDWA3cD06LHXVFZ+cpaCE1PgJxdMGVouW9OROSHJO0JJJqJrIt+DyGEa0IILUMI7UMI0xOWeyaE0Cp6PFvugeXsgk3LodnJ0PwUWDSu4Lk1X8LYO32ZRN/Ng9H/C9uy9n88IcD6Jcmf27jMny9q08rk5RXJtizYtT3dUcSTu9vfI0u0bR3s3JyeeNJh4/LUt7HNq0u/zRBg/WLYta10y2/IhLy82KGVuxBg0kPw5VvpjgSoAAmkwtqQCSEP6rWCVqd7I1y/GHbvgH9fCh//AyY9WLB85ifwTC/47An4968KJ5edm2DJJMjLLSjbsgZWTIfcnNLFM+EvMPgYePVi2Jzw9s+kh+Dh9jD6hsLrn/06/KMt/OemwuvZvdNjzd66923m5njcRTvEvFxY+mnxRBkCLJ+WPCGsmgk7NhYuW/KR79OwvoVjT2ZDJrzcH54+E0bfWHj57+Z5Ei0a+8rP/YMQpRFC8vWAH/d578D80QX7sGgCDO0OD3fwfQbYvt7L/tkBPn+ucCf36aPR4GJd4XVvWQPfzS8S+274dAgMH1Q+gxHwQdCbV/nMOr8NZm+Bb+cU75xzsmHp5MLtIC8PxtwOD7cr2+x8xXRv00s/LVyeuxtWfVH8/JjzBjx0FHx4f+HybVkw/AqYO6KgbNkUeKQzDO4ErwwoSAzJ9gfgq5Hwz47wdE+YO9yP+bx3fD2lPU+3rIEZL8Drl8HkfxWvyw1Lkw8Et66FdQuL7M8gbwe5uwvKvxwB4/7sl9UnPVR4HeuXJD9+5chCRR+hlkGXLl3C9OnT975gMvNHw6sDYNA4qF7HG2KfB/0gTXkUGh8HK2fA5e9D1eresR3cCDpfCmP+DzpdAn3/Be/dDNOegrwcOG4Q9PorTBkCH/4Ndm/zdXe7Brr/zpeZ9CDMe9sbQZvecOpNfintqZ7QsKO/L9OgDQwaD1+/C69d4kkuayEcfS787ClYNQOGnQcH1IAd6+Gs+6Hrb+Hjh+Cjv/t2m50Mv3oTKleFL16CTx72Trn9L+C0m70O3v49zHgeKlWFtv3gp7d5I59wD6yeBVYJWp4OZ9zl2/nwfk8KjY6Fi/4NNer7CP39W/3krNsSLhkOdZvDgrFev9XrwtZvoeef4aTr/OT+aqSPGA9rD427eCJ4uT/kZsMhP4Flk73Oet3r+zTuLo/38M5w+u3eoU8ZAjs3Qq3G8KsRUP9Ir6NlU7yeAbI3w6LxnjR2bYOta6BKBlzwlNflgrEw9g5YM7egXRxYHw7vBAs/gDrNPd4DasBVk2DktfDVW77/y6fCgNegzVneWT3bBwiQcTBc8DQ0P7WgHeRmQ78h0PFCj+WVAdE2zY/tCVfD1u88aVWvA0edDR37+7EDr58ZL/hxb3Rs9KlB8+2tW+DHZPd2qNMMTvlf+GqUD3QqVfFt120Jrc+EL9/0Y9H8VOjzgLezBWPhPzfC+kVRO+gLXf/HB1BfvwsHHeb1fNXHUL+1nx/Tn4HFE7xOq9fxNlLrcB/4LPnIj+mpN/rA6okesD1Kqh0HwGm3+L6PuxvWzoND2sI5D0PTrn5cnzsbzPwYDhoHhx/jdfbC+X58wdvjsb+GId2hUiVocRrMGAZn3uvn6Li7C/an+7XQ807vwId09fa4cxNs+65wf5BRG1qfAUeeBS1/ChuWwDfvw8KxBYOUvFzYuLRg+Z0bvT/o/YC/l/rRA55UKh8AFw6DVj09qU15FCbeB7u2Qof+vq+fPhq97xrg0PYw4BXf78dO9vOnTnOY+4b3SR1+CRP+6sc05HqbP+0mOOYS3/8YzOzzEEKXvS6nBFKCyY94IrhxiZ8E/+zoJ8T2ddDlN95RDT3RO52Mg71RXDEBajWE8fd4Y2l2MmROgo4X+ck+43mo2RC2rIY2feAn5/tU9Ot3veMKwU/oVmdApcreQCtX9fIa9eHqKfDNe/Dmb+HE67zBHHI0/PpdmP4svH8L1G3ho/U6zeDyMTDqWn9NvdaQtQCOOgcObQcf3gdtzoaDGvho+fDOUK0mLPnQlzmwrp90x17mCXL6M5Cz0+umZkNPbJtXwtQnIHuTl2cc7CfMZ09CtVp+6e/r0R7/cb+BmS950jnxOu846zaDgW/DqN/5vp5+h8eaOangODQ9wTvjWo08+TRo47OqqY/BATVh1xZodwE0PMa3uymaQRx1jp/w4+/15FYlw0/Qohoc5fVRuSo0Od6T6crpBeuu1wqOu8Kfy97iM8HVs+Dk6z3pL/sUXjgPqh7onXSP2+CkP/iA46BD4ZIR8PgpPpv9xbPw9nU++q/dxI9Tmz6+3sxJ3nGv+8ZncOc9CgfWg1cvijoo88S1fZ13mPXbeDLI2Qnv/AGqVPM6WPWFDxDyVa4GzU70jnHxBNie5evqchn89HZPblOG+n407ODJafIj3tbzE2G9Vr6/386F6U/7Nqtk+Ovb/xwe7Qo1GnhnPPZOn90ecYLv/8ZlsGKa779VgkN/4uvJT35VqsPAUT5omPwI5EWj7YObepuZ9rSfLyf+HqY+DjXqeZ0+2weqHQQXvuhXBLaugV8O83b61Ug/Z3du8gFe4+M8wSyOPk1ZtyWccgMsGONJM/91SyfDbz+C2k0Lf2hm/WJvnwvej+ovYpV83bWbFpTVb+ODhkN+AhPu9QFhnWY+i9i80pPkt3M9OZ70R09kc4d7YmrQxmccebs9/v4v+/beugaqZvjVj9zd8NsP/Zi8ehEs+MDP1W3r/Jg2OtbP2+VTvf8Z+LYnnn2kBEIZE8jb13lDvCmabr7zRz95Ol0C5/wTKlfxUcvYO71hXfy6n+Dgo4o3fu2vb3eBjzhDHrxxuXcevf4CRyb8G8ziifDNGD/QR/f1EQj4DGfucO+AjxngI8u8PHiyB6ye6Z3qFeOhZvTvNnOHe5wdLoQet0L12t7gPnvSG3LngXD6n3w7E+/zGUPIi/bpYR+RfvSgJ5e8HGj/Szj/cR/FbMiEOa/DYR09MVTN8G1uXQtfvAD1WvrIrFpNvyzx8T8g82Nftte9fpKt/QbeuspHzAcd6gn34EY+XR8xyGcDlarAuYOhxanw+fN+MrTtBz1u8ZMK/HLC1KE+oq3bwhN6pUre8c56xUfCzU/xZTcs9c4hd5cv26KHzxjAk36NeoWP+65tfhLvWO+jvGMHeue8J3Pe8H2qeRh0u9o7x2lPwbvX+35vWgmXjoTmJ3uyeP0yH8H2+qu3g5xsr/evouvav3jOO1rwTmPHRk/i1Wt7W/jmPXjvFl8HwBEnQf+X/PmcbL+Uli/jYDjgQP99xwaY9Zq3r/y2mi8n2+vDzI/puDth4Xg4/go44ZqCOtiw1GfIR58LdY4oaL9vXe0dZN0W0SyzRcG6d272ej2gBmTUKtyu2/8cGkW3vFu30Dv0Rp2h2Um+zR0bvaNc+onPRi5+w9tM5ifw8oU+KKhUBS59y18TAsx+zWelnS7x8wBgy7fenpp2gyO6+zHKyfaP6a+d58mg77+g08UlH+e8XI998QQ/rq3OKN5+ilo80S/1Va7qx7tpV09s717v5xP47PvE33vd59dV9dp+zMH7jFcG+Cz6rPugfisvz94Cw/r5/ve+v+CY5tfBjo3Q7ao9x1cCJRDKmECeO8dHWoPG+t/bsrwRH31u8YweQvGyXdth/ju+fH5DSLZcHMunwejrvcE37LD3WEoqz7+uW7nI/5Pm5fryRcv3h7w8mDfKO4MGRxaOb+FY7/CaHL//t5tqu3f6eyHZW3yE2/qMgufyz7mytIW8XE9a6xdD2/MKEnq6ZG/16/Nt+vhseX/avdMTzlFne8eab/VsGHk1nHCtX9KLY9VMGHmNzxyP6rN/4i2tZVM8Abbqufdl9+W83g+UQChjAnmorY9iz39s/wYl/z3WLfCRbb2W6Y5EZJ+UNoGk7W68Fdqu7dF0XCe+lEH91umOQKRc6WO8yezeDu1+7p8WERGRpDQDSaZGffj50+mOQkSkQtMMREREYlECERGRWJRAREQkFiUQERGJRQlERERiUQIREZFYlEBERCQWJRAREYnlR30vLDNbCywtwyrqA+v2ulTqKa59U1Hjgoobm+LaNxU1LogX2xEhhAZ7W+hHnUDKysyml+aGYqmmuPZNRY0LKm5simvfVNS4oHxj0yUsERGJRQlERERiUQLZsyfSHUAJFNe+qahxQcWNTXHtm4oaF5RjbHoPREREYtEMREREYlECERGRWJRAkjCzs8zsazNbaGY3pzGOJmY2wczmmdmXZvb7qPxOM1tpZjOjR580xZdpZnOiGKZHZXXN7AMzWxD9rJPimNok1MtMM9tsZtelo87M7Bkz+87M5iaUJa0fc4OjNjfbzDqnOK4HzGx+tO03zax2VN7MzHYk1Ntj5RXXHmIr8diZ2S1RnX1tZr1SHNdrCTFlmtnMqDxldbaHPiI17SyEoEfCA6gMLAJaAAcAs4C2aYqlIdA5+r0m8A3QFrgTuKEC1FUmUL9I2d+Am6PfbwbuT/Ox/BY4Ih11BpwCdAbm7q1+gD7AfwADugFTUxzXmUCV6Pf7E+Jqlrhcmuos6bGLzoVZQDWgeXTeVk5VXEWe/zvwp1TX2R76iJS0M81AijseWBhCWBxC2AW8CvRLRyAhhNUhhBnR71uAeUCjdMSyD/oBz0e/Pw+cl8ZYTgcWhRDKcjeC2EIIHwHrixSXVD/9gGHBTQFqm1nDVMUVQhgTQsiJ/pwCNC6Pbe9NCXVWkn7AqyGE7BDCEmAhfv6mNC4zM+CXwCvlse092UMfkZJ2pgRSXCNgecLfK6gAnbaZNQM6AVOjomujKegzqb5MlCAAY8zsczO7Mio7NISwGrxxA4ekKTaA/hQ+qStCnZVUPxWp3V2Oj1LzNTezL8zsQzM7OU0xJTt2FaXOTgbWhBAWJJSlvM6K9BEpaWdKIMVZkrK0ftbZzA4ChgPXhRA2A0OBlsAxwGp8+pwOJ4YQOgO9gWvM7JQ0xVGMmR0A9AVej4oqSp2VpEK0OzO7DcgBXoqKVgNNQwidgD8CL5tZrRSHVdKxqxB1Bgyg8EAl5XWWpI8ocdEkZbHrTAmkuBVAk4S/GwOr0hQLZlYVbxgvhRBGAIQQ1oQQckMIecCTlNO0fW9CCKuin98Bb0ZxrMmfEkc/v0tHbHhSmxFCWBPFWCHqjJLrJ+3tzswGAucAF4fognl0eSgr+v1z/H2GI1MZ1x6OXUWosyrAz4DX8stSXWfJ+ghS1M6UQIqbBrQ2s+bRKLY/MCodgUTXVp8G5oUQHkooT7xmeT4wt+hrUxBbDTOrmf87/ibsXLyuBkaLDQRGpjq2SKFRYUWos0hJ9TMKuDT6lEw3YFP+JYhUMLOzgJuAviGE7QnlDcyscvR7C6A1sDhVcUXbLenYjQL6m1k1M2sexfZZKmMDegLzQwgr8gtSWWcl9RGkqp2l4pMCP7QH/kmFb/CRw21pjOMkfHo5G5gZPfoALwBzovJRQMM0xNYC/wTMLODL/HoC6gHjgAXRz7ppiO1AIAs4OKEs5XWGJ7DVwG585PebkuoHv7TwaNTm5gBdUhzXQvzaeH47eyxa9oLo+M4CZgDnpqHOSjx2wG1RnX0N9E5lXFH5c8BVRZZNWZ3toY9ISTvTrUxERCQWXcISEZFYlEBERCQWJRAREYlFCURERGJRAhERkViUQESKMLPDzOxVM1tkZl+Z2WgzOzK6y2qs/x+J7tZafy/L3Frk78l7WX6imXWJE4/I/qAEIpIg+sesN4GJIYSWIYS2wK3AoSnYfKEEEkLonoJtisSmBCJSWA9gdwjh++9wCCHMDCFMSlzIzDLM7Fnz70P5wsx6ROWVzezBqHy2mf2uyOuqm9l7ZnZFkfL7gOrR90e8FJVtTXj+xmids6JlE19bycyeN7N7ou0/Z2Zzo+X/sL8qRqSoKukOQKSCaQd8XorlrgEIIbQ3s6PwuxIfCVyGfzdFpxBCjpnVTXjNQfjXAwwLIQxLXFkI4WYzuzaEcEzRDZlZb/x23F1DCNuLrLMKfuPDuSGEe83sWKBRCKFd9NrapdxvkX2mGYhIPCfht9gghDAfWIrfMK8nfhuQnOi5xO+QGAk8WzR5lELP6HXbk6zzcaLkEf29GGhhZo9E97fa051ZRcpECUSksC+BY0uxXLLbYueXl3R/oE+A3tH7LPtiT+ucDPQwswyAEMIGoCMwEZ8lPbWP2xIpNSUQkcLGA9US36Mws+PM7NQiy30EXBw9fyTQFL+h3xjgqug23xS53PQn/CaPQ0rY9u7o1txFjQEuN7MDk6zzaWA08LqZVYk+6VUphDAcuB3/GlaRcqEEIpIg+N1FzwfOiD7G+yX+ndxFvzNhCFDZzObg3wXx6xBCNj7iXwbMNrNZwEVFXncdkGFmf0uy+Sei172UWBhCeA+/C+10M5sJ3FDk+Yfwu76+gH+73MRoueeAW/Zh90X2ie7GKyIisWgGIiIisSiBiIhILEogIiISixKIiIjEogQiIiKxKIGIiEgsSiAiIhLL/wOKCUnB83Y0ZwAAAABJRU5ErkJggg==\n", - "text/plain": [ - "" - ] - }, - "metadata": {}, - "output_type": "display_data" - } - ], - "source": [ - "# Plot results.\n", - "plt.figure(1)\n", - "plt.plot(iq0[0], label=\"I value; ADC 0\")\n", - "plt.plot(iq0[1], label=\"Q value; ADC 0\")\n", - "plt.ylabel(\"a.u.\")\n", - "plt.xlabel(\"Clock ticks\")\n", - "plt.title(\"Averages = \" + str(config[\"soft_avgs\"]))\n", - "plt.legend()" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### Now we perform the calibration: Params 1 (spacing between points is too large) " - ] - }, - { - "cell_type": "code", - "execution_count": 6, - "metadata": {}, - "outputs": [], - "source": [ - "sweep_cfg={\"start\":100, \"step\":0.0005, \"expts\":40}\n", - "\n", - "gpts=sweep_cfg[\"start\"] + sweep_cfg[\"step\"]*np.arange(sweep_cfg[\"expts\"])\n", - "resultsi=[]\n", - "resultsq=[]\n", - "for g in gpts:\n", - " time.sleep(0.1)\n", - " config[\"pulse_freq\"]=g\n", - " prog =LoopbackProgram(soccfg, config)\n", - " (iq0,) = prog.acquire_decimated(soc, load_pulses=True,progress=False)\n", - " di0 = np.sum(iq0[0])/config[\"readout_length\"]\n", - " dq0 = np.sum(iq0[1])/config[\"readout_length\"]\n", - " resultsi.append(di0)\n", - " resultsq.append(dq0)\n", - "resultsi=np.array(resultsi)\n", - "resultsq=np.array(resultsq)" - ] - }, - { - "cell_type": "code", - "execution_count": 7, - "metadata": {}, - "outputs": [ - { - "data": { - "image/png": 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WBrbHmuhYXrg+FD+w9eDDuODsmxn56UJO/OnZVJvRhSELTMIIEd///vdzfu748eMZP358HqNpnTPPPLNdz29SpcSe2O/aMcLaLdvtaqlwJ4z6WJx5/Q5kXr8D+U+kP9VuB2TwFaHwkjKEj+SEUVZaQueKUr5siGVdVhs06hsta5hunSK8sOgzEk3hPh6G7AhFwgj7l0QYaVJIrhzu2jHSXC1VCPxyjjXYCeOU4f344qtG3vx4o8sReYjZs+HWW03lWCsEPmF06NCBjRs3+uYDbcgPTaqUluzMGF07RhDgy4ZY3t9L7fUwOnTokPfXzjfOCKO2qpKOkVKmLQhFpXrbzJ5NY81omiZNMuXGrRD4OYz+/fuzevXqZsM5Qzj47MvtlJeVUL++vHnblq072KjK5i75/2J3VtzzOvWNlkFk987ljD6wFy8s+ozrvzWUstLAXzu2zqxZlMYaKdEmtLERMeXGKQl8wohEImYVtBDy3ZteYuzQPtxy6oHN26a8+QlXPbWI5392DAdWtu4hFVQcSapTeSknV1UybcE63vp4E0fuv6fLkblMTQ2xsggajyGRCKU1NW5H5ElCflkRfPSNN2i65ZbQDbHrGxN0iuxaETVuaB9KhFDLMPVJCaNmcC86Rkp5dmF4j0cz0Sg/Ou/X3H7MBH4/8W4zukiDSRhBZvZsYqPGoJPCZQPR1KQ0xBJ0alFCu+duFYzctwfPLVwX2jmthpiVMDqWl9KxvJQxB/Zi+qLPiCcKUwzgJ+b0OYA/R8/iL/E+zSMxw66YhBFkbF221NZlsU0Mg872eAJVmh1qk6mrrmTFF9tY+tnXF0oKA/WNcUpLhHJ7zqKuqpKN2xp58+NNLkfmLk1NyvZYE4fv052GWIJZH6xv+0khxCSMIFNTQ7wsQlxKSJRFLHfSEJAsu7TEkaWeC6kMs22HJdU5bsU1g3vRqbyUaSE9Hg7OyOu4wT3Zc7dyI9OlwSSMIBONctmPbuf2Yybwq5/8PjS6rCMnpOrqdmSpaSGVpRoaE7scl47lpYz+hlUtFWZZyrnI2L1DGeOG9mHmkvVGlkqBSRgB552+3+CeI8/i8Uh/Vm2qdzucotDaCAOsHoQVG8IpS9WnmNs5ubqSTSGXpZovMiKl1FVX0hBL8LKRpb6GSRgBpyGW4Ci7ZPL5ReEYZju9BukSxonD+nDo2iV8cdV1oSkEcGhojH9tbseRpZ4Nc/VYzDlnyjhiYA/23K089DJdKkzCCDj1jXG+0Wd3qvp1ZdrCz9wOpyjsvFpM3Wa058J5PDJ1Ekc++Ac0RNVjYJcbt0ikHSKljDmwN9MXh1eWSh6VlpYIJw4zslQqTMIIME7lR8fyMmqrKpm/aksoZKm2JClmzSKSiFGavIhQSEiVMMCqltq0rZE5K8IpS7Wc96qtMrJUKkzCCDBO5Uen8lLqqiqBcMhS9bE2EkZNDVJRQVxKiIeoegzsSe/I149LzeCedA5xtZRzkdHZluuMLJUakzACzM4PQSl79ehkyVIh0Kkb7DmMtGtfRKPIjBk88e2L+MWFv0OTlngNOvWxeMpEGnZZqr7FOWNkqdSYhBFgdg6zraumuupK5q/+MvCy1E5JqhWrtGiU+OUTebbzPqGqlrLKalMfl9oQy1INKWRMI0t9naIlDBHpICJvich8EVksItfb2weKyJsiskxEHhORcnt7hf14uf37fYoVa1DYWflhfQgcWSroTWttzmHYnDgsfE189Y0JOqc5LjtlqbVFjsp9Up0zzbJUCEblmVLMEcYOYLSqHgQMB04UkZHAr4E7VHUQsBm4wN7/AmCzqu4P3GHvZ8iC+hYTeQO6d6K6f9fAf0E2NCYQgYqy1k/vsDXxqab22HJwZKm1z88kcXO4DCuTPbYcmmWppeubJauwU7SEoRZf2Q8j9k2B0cAT9vaHgG/b90+xH2P/foxI8hpqhrZoHmYnTXLWVQVflrKuosvI5HSpqw5PE9/2WFNajy2H7zSt4Z4Hr6DkmmtCZVjZ0mPLoa6qryVLLTXr6UCR5zBEpFRE3gPWAy8BHwFbVNVJ36uBfvb9fsAqAPv3XwI9ihmv30ml5deGQJZqiMXTT3i3IEzeUm01NAIc+vF8Iok40pQIVcmxY4ff8iLj8IHd2XO3ilCcH5lQ1IShqglVHQ70Bw4HDky1m/0z1eXh13QDEblIROaKyFyzqt6utKz8AEuWOqh/10CXC6brNUjFnrtVEN2vB9MWBF+WailRpiIyZjRNEcuwUsvLQ1Ny3NJjy6G0RDhpWB9mLP3cyFK4VCWlqluAWcBIYA8RcS6B+wPOjNtqYACA/fuuwNfKN1T1PlUdoaojevbsWejQfUWqyg+wRhkLAixL1afpNUhHbVU4LM8b2upPAYhGmffAE9x+zATmP/hEaAwrW7vIqK2qZHusychSFLdKqqeI7GHf7wgcDywBXgbOsHc7D3javv+M/Rj79zM16JeAeSZdtZAjSwV1lNGQxQgD4MSQrMSXafXY8LNO4qHjzuGxMu+vUZ4v6lspN3ZkqTBWj7WkmCOMSuBlEVkAvA28pKrPAlcAvxSR5VhzFJPt/ScDPeztvwQmFjHWQJCq8gN2ylJB1WXrG+Ot92C0oIctSwV9Jb5miTKNx5aDUy0VJstz65xJnUgdWWrTv16h8aabQ1MIkIpiVkktUNWDVbVaVYep6g329hWqeriq7q+qZ6rqDnv7dvvx/vbvVxQr1qCwbUfqyg+wqoMWrP6STzcGT5aqT6NHt0ZdVV9WfLGNJeuCK0ulkyhTUVtVyeb6GLNXbCx0WJ6grXmvs2Kr+d+Hr6Ts2mtDVT3WEtPpHWDSVX4AnDTMrpYKoLdUa70G6Rg3tDelJRLYURdkLknBzia+IB+PZNJ5bDkMXTaPSCJOSciqx1piEkaASVf5AbYsNWCPQOr223ZknzB67FZBNOBNfKmq5tKx01vq81DIUuk8thxKRo2iKVIeuuqxlpiEEWBSra6WTF1VHyJvzWHL1dcHaojd0BhvU6dPRW1VJR8HWJbKyGMriTB5S7XmsQVANMoHDz/F7cdM4I17HwtN9VhLTMIIMKlWV0vm2w2fMmXqVXS55YbA6LKq2maiTIcjSwW1GiYbSQrC5S2VSe/OkNPH8fgJ32VKSd8iReU9TMIIMG19CHrNm0N5Ik5JU3AWEtoRd+wvsk8Yjiz13MLPAilLZeqx5RAWWaotjy0Hp1oqzN5SJmEEmDavmmpq0HJLl22KBEOXzfYquiVBlqVaK4JIRxhkqZ0eW5lVj4W5ic8kjADTVuUH0Sgbn36O24+ZwNP/81AgdNlM/JJaI8iylOWxld3cThhW4ms+ZzJwBwi7t5RJGAGmrcoPgN7jRvH6WRfxQKKySFEVlpaLRmVLkGWpbDy2HDpEShkd8JX4mkelFW2fM2H3ljIJI8A0NCYy+hDUVfVh4ZpgNPE1f/iz8JJqSV21JUu9v+4/+QrLE+SSMMCyxA+yLJWRx1YSYZalTMIIMI5m3RZBauJr7xwGWJbnI9YuZeNVQSs3zr4DHoIvS2V7zoRZljIJI6BkWvkBwfKWaohl3pyWju4L3mHK1Ks46qE/oAEpNwZLq++cg1QXdFkqU48tB2slvt6hrJYyCSOgZLK6WjJBsTzPtjktJbNmEUnEKdXglBtDbh5bDnVVfQIrS2XjseUQ1pX4TMIIKNlWCwVlJb58SFLU1CAVVrlxvCwSiHJjyM1jy6FmcC86BVSWyuWcCassZRJGQMlkdbVkgrISXy5Xi18jGkVmzODvp/6Qn/3gt+jIkXmKzl1ynfSG5Ca+4MlSDVl+VmBXWcp5fhgwCSOgZFv5AcGQpfIiSQFEoySumMhzuw0MTLWU1ZeT+3FxZKk3Pw6WLLVzNJ7dsamtqrRkqQ/WFyIsT2ISRkDJZZgdBFmqoTGOCHSItP/UHje0T2Asz1W11UWCMqFmcC+i6z9k63U3BqYQACyTTsh+VHrEwB7suVt5IB2f02ESRkDJtvIDLFmq2ufVUs563tnYX6Sje+dyy/J8gf8tz3fEm2jK0WPLocPct3hoypUc/8ifAlU9lq3HloMlS/UJlSxlEkZAyVXLr62qZL6PZalcnWrTUVddycqN9b6XpfIytzNrFmXxOGXahAaoemzbjuw9thzCJkuZhBFQtuX4BVFny1LP+7SJL9fmtHQERZbKVXbZheTqsdIgVY9l77Hl0CxL+fz8yBSTMMAaWt96a2CG2GBp+ZC9BDGgeyeq+nX1rS5b3xinUzsmdlviyFJ+95baeT6049jY1WPPnfVjLjr3NuKHH5Gn6NylPdVjpSXCuKF9mLkkHLJU0RKGiAwQkZdFZImILBaRn9nbrxORNSLynn2rTXrOlSKyXEQ+EJFxBQls9mwSo0eTuGpSoHTZ9lQL1VX7V5ZqT3NaOoLgLbVtR/s9tgCIRimf9Ctm9dg/ME187UkYYJ0fYZGlijnCiAOXquqBwEjgJyIyxP7dHao63L49B2D/7mxgKHAi8GcRye83AcCsWZTEYpQGTJdtTwObn2Wp9n74UxEEWSovDY02QWvia6+MGSZZqmgJQ1XXqeo8+/5WYAnQr5WnnAJMVdUdqvoxsBw4PO+B1dSAvYhQrKQsOLpsjpUfkCRLLfysAJEVlkIkjCDIUvnw2HIIWhNfe8uNHVlq00uvELvp5sCoFKlwZQ5DRPYBDgbetDf9VEQWiMgDItLN3tYPWJX0tNWkSDAicpGIzBWRuRs25ODrYuuyr517CRPOvpktBx2a/Wt4kFxWV0umtqqS+au2sHqzv2SpttYxzxVnJT6/ylJ5a2i0CZLleX07GxoBxsdX88DDEym99loIkLTdkqInDBHZDXgS+Lmq/ge4G9gPGA6sA/7H2TXF0792eaeq96nqCFUd0bNnz9yCikbpftO1vN33G7y4+PPcXsNjtKfyA5JkKZ+NMjK1dM8WZyU+v8pS+ZSkIFiW5+3x2HIYtuxdIok4JU2JQBlWtqSoCUNEIljJYoqq/h1AVT9X1YSqNgH3s1N2Wg0MSHp6f6Bg62ZW9etK/24deTYAHwBovzSzV49ODOvXhWVPv+SrCrJ8l9U6+H0lvlz8klojSJbn+ZAxS0aNoiliSdtaXh4YabslxaySEmAysERVb0/anrw26KnAIvv+M8DZIlIhIgOBQcBbBYyPuupK3lj+BVvqGwv1NkUjHx+C75d8xvV/vAS9+mpfDLNVNe+Ne8k4stSSdVsL8vqFJN8jDAiOLNXQmMiL99jSh//O7cdMYPZ9j0E0mp/gPEYxRxhHAd8FRrcoof2NiCwUkQXAKOAXAKq6GHgceB94AfiJqha00LmuqpJ4kwZClmrIQ8IY/dn7RBJxJOGPYXZjoolEkxYsYTiy1LSFBRvoFgynD6NDWf6OzU5Zyn/HwyEfHlsOQ08/kcdPmMCUktZqefxNMaukXlNVUdXq5BJaVf2uqlbZ27+lquuSnnOzqu6nqoNV9flCx+jIUkHQZa0PQfuumvaoHUuiLEK8pAR8MMzeKbvkf9Ib/C1LOR5bJSXt99hycKqlXljkX1kqHx5bDmFo4jOd3kmICHVVlbweAFkqLw1s0SjT7vg/bj96Auufmub5YXYhZJeW+FWWqo8l6FyR/+NSW1XJ5voYs1dszPtrF4O8eGwlEfQmPpMwWlBXHQxZKh+VHwAjzq7jz9GzeLrj3nmIqrAUI2H4VZYqVDGAI0v5tnosHx5bSQS9ic8kjBYERZbKVwPbXj2sJj4/VI81S1IFKKt18KsslW+PLQe/y1J58dhKotnyPKCylEkYLQiKLNXe1dWScZr4vO4tlevKadlSW1VJt/lzWf+r6zxfOeZQCI8th7pq/8pSzaPSPF5kBNny3CSMFNQ61VLv+1OWymflB/jHW8qRFwr1xehQ99XHTJl6FT1/c5Mvyo0hP1Vz6TjuAP/KUoWQMYO8Ep9JGCmo7m/JUn78AEB+Kz9gpyzldW8pRwIoxORuMl3feoPyRJySJv8YVhbCY8uhQ6SU44dYslTMZ7JUvhsaIdgr8WWdMESkc0FcYz2EI0u9tsyfslS+Kz/Atjz3uCy1U14orCRFTQ1qG1ZqxPvlxmAVQRSq3Bh2VkvN8Zksta1AMmZQZak2E4aIlIjId0Tb6uKBAAAgAElEQVRkmoisB5YC6+w1LX4rIoMKH2bx8bMsle/KD/CHLJXrolFZE42ybdoL3HHsd3n0lsmeLzcGZ9K7cMfFkaX8JsMUqrIuqLJUJiOMl7HMAa8E+qjqAFXtBRwDzAFuE5EJBYzRFfwsS9XvyG/lB1iW59X9vb0SXzHKah26jjmO+RP+H39JVPqiWqqQk96wU5aavthfslQhJCnYVZZyijGCQCYJ43hVvVFVF9gGgQCo6iZVfVJVTwceK1yI7pBcLfVlfcztcLKiEJUfYFdLeXglvvoilNUm4xfLc1Ut6KS3Q21VJQOXLWD15df4ohAACnuR0SxLLc1h2QWP0mbCUNU2vy0z2ceP1FZVEksoL77v7cnelhTqQ+DIUl4ddTXEEnSIlOTV/qI1/GJ53phoIl5Ajy2Hmk3LmTJ1Env9/lYfVY/l32PLwZGlvH5+ZEPGk94icqaI7G7fnyQifxeRQwoXmvs4spTfmvjyubpaMo4s5dUPQD78s7LBaeKbtmCdp2WpQntsOVS89m/Km2KU+qx6LN8eWw6OLDVj6eeBkaWyqZK6WlW3isjRwDjgIazFjwKLiFDrQ1kq36urJVPnYVmqfkeiaHKUQ111JSs31ntalira3E7ScsdNkYgvqscKaYcPlkqxPdYUGFkqm4ThFBTXAXer6tNAef5D8hZ1VZVUffo+n142yRdDbCi8LgvelKUK2WuQjnFD+3helipawohGib/4EnfWnMu9V9/ni+qxQnlsOQRNlsomYawRkXuB8cBzIlKR5fN9SfWq93nksUkMuft3PtJlC9fxPKB7Jw7q39WTMl2hrxZT0b1zOUfu521ZqhgeWw4VxxzNyosu4f54b19US+XTESEVQZOlsvnCPwuYDoxT1S1Ad+CygkTlIeSVVyhPxChVf+myULgrytqqShZ4UJZqaIwXvgcjBbVV3paliuWx5eCnJj6r3Ljw3mNBkaWySRgNQGfgHPtxBNiS94i8Rk0NlFcQlxISZf7QZQtZ+QE7ZSmvjTLq87HUZg44spRXe1SK5bHl4KcmvobGBJ0LfFyOGNiDUZuWE7/5Zl8oFK2RTcL4MzCSnQljK3BX3iPyGtEoMuNf/GXs97jt0j/5Qpd1tPxClZc6spTXdNlC69HpcGSp5xZ6U5YqhFVMaziW535o4ivGvFfpm3O496GJ1P3tbtQnsnY6skkYR6jqT4DtAKq6mRBMegPIkUey+ZJLeYhKX1RLFUPLr6u2ZKlPN3pHlqpvTBTU/qI1HFlq8VrvyVLF7IB38IssVWiPLQBmzSISj1HmI1k7HdkkjJhtOqgAItITyPjyQUQGiMjLIrLE9qH6mb29u4i8JCLL7J/d7O0iIn8UkeUissDtng8/NfEV40r7pGF2tZSHvKUKPYHZGl6ulmoo8hwG+GclvkJ7bAGWjF1hlRvHS8t8IWunI5uE8UfgKaC3iNwMvAbcksXz48ClqnoglrT1ExEZAkwEZqjqIGCG/RjgJGCQfbsIl3s+/NTEV6jV1ZIZ0L0TZ8VW0/F3v/HMELsoV4tpaK6W8qAs5cYII3klPi/LUoX22AJsWXsGM//rp5z7nVuoP/Swwr5fAck4YajqFOByrCSxDvi2qv4ti+evU9V59v2twBKgH3AKVhMg9s9v2/dPAf6qFnOAPUSkMtP3yzfJludel6WK8iGYPZtb7vo5/zXtLzSNdl+XjSWaiCUKb3/RGnVVlXziQVmq2B5bDn6QpYrhsQVANMpu113NnN6DfV0tlY01iAAjgB6q+idgm4gcnsubisg+wMHAm0BvVV0HVlIBetm79QNWJT1ttb3NNeqqLcvz6R6XpYryIZg1i1Jbl8UDuqwbV9EtGetRWarYHlsOXpelGuPF8dhyaLY8X7i2KO9XCLKtkorSziopEdkNeBL4uaq2dimW6uz+2lhfRC4SkbkiMnfDhsJm7qp+/rA8L0rHc00NUl5OvKSEmAd02UI2K2aKV2WpYntsOXSIlDL6wN5MX/w5cQ/KUsXy2HIIguV5UaukRCSClSymqOrf7c2fO1KT/dNZomo1MCDp6f2Br6VmVb1PVUeo6oiePXtmE07W+GUlvqJo+dEozJjBvAt+wTnjb+LTAw4q7Pu1wc7mNHcXg/SiLOUY7LlBXVUlm7Y1MmfFJlfevzXqY8U/Z/zexFfMKikBJgNLVPX2pF89A5xn3z8PeDpp+7l2tdRI4EtHunITR5by8kp8Ran8AIhGqbztBub1O9D1aqlCGi5mQ3MTn4dGoUXT6VPgyFJelGG27Si+jOl3b6lcqqR65VgldRTwXWC0iLxn32qB24ATRGQZcIL9GOA5YAWwHLgf+HEW71UwHFnKy12sRZn0thnQvRMHDdjD9ePRUIBlaXOhmy1LffLsv9BbbnG9GADcMWV08LIsVUyPLQe/e0tldDlmjw5eBd4BxmDNL3xbVZdk+kaq+hqp5yWwX7Pl/gr8JNPXLxYiQl11JZP//TFb6hvZo5O3ehdVtehfEHVVfbjluaV8urGevXp0Ktr7JuOFSW+Hc1nL0fdeCpqA8nKYMcNVhwC3OuAd6qr68M/5a5mzYhNHD9rTtThaUmyPLYfaqkoenvMpLy/dQF21a4WfOZHRCMP+8v6Hqi5V1btU9U/ZJIugUVdly1KLvSdLNSaaSBSx8gO80cTnNKd1LHD/SSYcvXoxkUQcSSS8UUEWc2fS26FmcC86lZd6SqaD4ntsOfhZlspGkpojIv7tOMkjVf26MqC7N5v4il35Ad7wlvLSCKPj2DEkyiLEpQQtL3e9gqx+h7sjjGRvKS/JUsX22HIoLRHGDfVntVQ2CWMUVtL4yLbqWCgiCwoVmJdJXonPa9VSbn1xOpbnbnlLeSlhEI3y6t2PcvsxE1gx9WnXDSvd9NhyqKvq47lqKTfPmbrqShpiCd9VS2WTME4C9gVGA98ETrZ/hpKTq/p6UpZyM2GAe7KUF/owkjn07DruPWo8T5QPaHvnAuOmx5aDF2WpZhnThWPjV1kqm4Rxeorb8SIyvBCBeZ1h/bowoHtHnvXYP9yNyg9wX5bySlmtg5csz9302HLoECll9Dd6eUqWcvOcSZalnM+sH8gmYYwAfoRlz9EPyxCwBrhfRC7Pf2jexmri68sby79g8zbvyFJuVX6Auyvx1TfGKS8robTI9het4YUmPi94bDnUVVWyz4fzWX3FNZ4pN4biX1w51FXZstQH69ve2SNkkzB6AIeo6qWqeilWAukJHAucX4DYPE9ztZSHvKXcqvyAJFnKhVGGm70G6RjrgSY+L83tjN78EVOmTmLAHbeCBxYSaoglqHDxIuPwgd0tbykP93S1JJuEsReQfCkdA/ZW1QZgR16j8gnD+nVhr+6dmLbQOwnDrcoPsGSp6v5dXfmC9MLEbku8IEt5aW6n4vV/U94Uo7TJGwsJ1TfG6VzhnlRXVlriO1kqm4TxCFaV1LUici3wOvCoiHQG3i9IdB7HqZbykizlXFF2dkmzrnNJlmqIxT3xpdiSWpdlKa94bAFWeXG5tZBQUyTifrmxix5bDn6TpbJZD+NG4EJgC/Al8CNVvUFVt6nqfxUqQK9zcnUl1aveZ9XlV7s+xAZ3Kz/APVnKkqS8MeGdjNsr8e3U6T1wbKJR4tNf4s6ac7nvmvtdLzd202PL4fCB3enRudxT1WOtke16GAcCXVX198D6XNfDCBJDP1nMI49NYujdv/OELuu2Zu3IUm4kDC+OMNyWpRyPrc4V3jg2FccezUc/uJj7471dr5bywrxXWWmJZXm+xB+yVNHXwwga8sorlCdilHpkgXe3Kz/AGmXML7Is5YWrxXTUVlWy0iVZyu0LiFScXO0Ny3O3PbYc6qoqOXDlIj69zBsqRWsUdT2MQFJTA+UVxKWERJn7uqxbq6slU+eCLOWF5rR0uClLecljy8ErTXxue2w5HP7ZBzwydRL7/+nXnlApWqNo62EElmgUmfEvJo/7Prf88k+u67Jura6WjBuyVENjwlNfisl071xOdF93ZCkvjjC84i3lFRmz7N+vEvFQ9VhrFHM9jMAiRx7J5ksu5a9Uul4t5YXKDyi+LFUf864kBTtlqffXFVeW8mLCAG94SzV4pRTbY9VjrZFNldQU4HLgVmAd1noYfytUYH7DK018XtHy66oqOWTNEtZNLE5XrxcmMFtj3NDershSXurDSMYLspRnzploFH3pX9wz5jzumHi36ypFa2QzwsCsh5EerzTxeeVDMOCD+Tz62CQO/csdBddlE01KY7zJc1+KyfTYrYLovj2YtqC4spTXPLYcvCBL1TfGXffYcig7+ijW/fgXTI738XS1VJsJQ0R+2dqtGEH6geQmPjctz60PgQe+OGfNIlKk6jGnOc2tZsVMcUOWqo95z2PLwU1ZykseWw5+aOLLZISxu30bAfw/dpoP/ggYUrjQ/IcXVuLzTANbEavHvCq7tMQNWcorEmUqdspSa4v+3l6c2/GDt1SbCUNVr1fV64E92dV88FCgf6ED9BNesDz3Sm050SglM2cwpe4H/OondxRUl/Xihz8VPXarYOS+3Xlu4WdFk6W27fDIxG4KdspSnxddlvLiRUayt5RXV+Jrj/lgI7BPpk8WkQdEZL2ILEradp2IrBGR9+xbbdLvrhSR5SLygYiMyyJO10i2PHdLlvKUCV80Sv2ll/N4ZEBBq6X8kjAA6qr68vEX24omS3nVY8uhrsqdJj5PeWwl4fWV+LJJGP8HvGV/yV8LvAk8lMXzHwROTLH9DlUdbt+eAxCRIcDZwFD7OX+2e0A8j9uylNca2JwmvucLuBJfQ8zxz/KAFNcGxZalPCNRpqFmcE86uyBLecpjKwmvr8SXTVntzcD3gM1YBoTfU9Vbs3j+q0CmlxGnAFNVdYeqfgwsB3zhW+XIUm6VC3phdbVk9urRiap+XQuqy/pphOHIUiv/OQO95ZaClxx7pTktHR0ipYw+sDcvLCputZTjseW1c6a0RCxvKY/KUplUSTWXV6jqPFX9g317N9U+OfBTEVlgS1bd7G39gFVJ+6y2t6WK7yIRmSsiczdscH8Y51RLve6CLOXFyg8ofBOfF/yzsuFc1vK7e38J11xT8JJjL096O9RVVbK5PsbsFRuL9p5evsiorfKuLJXJCONlEblYRPZK3igi5SIyWkQeAs7L8f3vBvYDhmM1A/6P8/Ip9k05S6iq96nqCFUd0bNnzxzDyC9uyVJe/RAUWpZyc9GoXDh69WIiiTiSSEARSo69flwcWaq41WPuLgPQGl6WpTJJGCcCCazFktaKyPsi8jGwDMu59g5VfTCXN1fVz1U1oapNwP3slJ1WAwOSdu0PFL/2Lkeq+nV1RZbyYuUHFF6W2ubiOua50Hnc8STKIsSlBC0vL3jJsdd0+pY41VIvLPqMWJFkKa82NMJOWWrG0s89J0tlUla7XVX/rKpHAXsDY4CDVXVvVb1QVd/L9c1FpDLp4amAU0H1DHC2iFSIyEBgEPBWru9TbNySpbxa+QGFlaW8mijTEo3yyp8f5fZjJvDx1KcLW3LscY8th1pblppTJFlq58qU3jw2dVV92R5r8pwsla01SExV16nqlmzfSEQeBWYDg0VktYhcAPxGRBaKyAJgFPAL+30WA49jLf36AvATVfVuv3wKdnpLFU+W8vJVUyFlKa9Kca1x6Nm13HvUeJ6sGND2zu3AK1YxbdFcLVWkpjWvX2RYTXwVrjQ1tkZWCaM9qOo5qlqpqhFV7a+qk1X1u6paparVqvotVV2XtP/Nqrqfqg5W1eeLFWe+qOrXlf7dOha1a9OrlR9QWFmqvjFBpFSIlBbtdG43xWji84PHloMjS617YSaJm4tTPQbevLgCS5Y6yYPVUll9wuyJ7o6FCiZIiAh11cWVpbx+pV0oWaqhMe6bCqlkCt3E5xePLYfvJNZwz4NXUFKE6jEve2w51FZVek6WymZN759hVTItF5ElIvLTwoUVDIotS3lxdbVkCrUSn9eb09JR6CY+r8suLTl05Xyreqyp8NVjfig39qIslUkfxu9F5FzgZ8CBqtoPOBYYIiI3FjpAP+PIUsXs6gXvjjAcWSrvCcMnE7stKbTludfPh5ZExoymKVKc6jFPWeikwYuyVCYjjFeA/bHMB98QkXnAb4GPsCqZ9ihgfL7G8paqZNvL/2b79TcVUZf17gehELKUZwwXc6CQlud+OB92IRpl3uQnuP2YCcx/8ImCVo/55Zypq7ZkqZlLvWF5nklZ7VOqeg0wB8uy43gsD6k40B2YJSLLCxqljzkztoq/Pvorym+4rihdveBtCaIQspQfmtPS4chShSgG8JPHlsPw8Sfx0HHn8FhZYY2wrXPG+8flsH0sWcorTXzZTHr/BHgYqxv7YGAYsFBVh2PWxUjLfovnEknEKSmCLuv1yg8ojCxlXS16929uDUeWem5h/mUp340wKF4Tn9c9thxKS4TaKu/IUtmYDy4DjgCeADoCC7Ca7VBV95aY8zgyahQaKS+OLuuDyg/IvyzlBz26NeqqLVlq8dr8ylJ+89hyKEYTn1/6U8A6HkNWLuaTy64uuKzdFtk27jWq6jS7R+JOVd1cqMACQzTKJ48/ze3HTGDmnx4pbFfvDn98CPItS/npw5+KcUP7FKRaym8eWw7F8Jbyk4x52LoPeGTqJA74028KLmu3hX86nXzMft86gWdqz+Ov9C3o+/jlSjvfslRDLEGnCu//3eno3rmcI/frwbQ8y1J+kChT4VieF3IlPj94bDmUvvoKkaYYpU1NaIFl7bYwCaMIFKuJz+urqyWTT1nKLxOYrVFbVckneZal6j3syNoWhV6Jz1el2DU1UG7J2k1lkYLK2m1hEkaROLmqb8Etz/3UwFZXVckha5awduI17RpiNzUp22NNvtPpW+LIUvl0OPbjpLdDoVfi85WMGY3Cv2Zwz5jzuX3inwsqa7eFSRhFohgr8fml8gNgrw/n8+hjkxjxlzvapct62T8rGxxZKp/VUn702HIopCzlJ48th9KjjmT9T3/B5EQfV6ul/Hcm+RSria9vQWUpP9gdNDNrFpFEjFJtny7r56voluRblvKrx5ZDXVWfgshSXl4GoDUcbyk3m/hMwigihV6Jz0+VH5YuW0FcSoi3Q5fd2azoDymuNfItS/lJokxFzeBedCovzfuo3K/njBea+EzCKCLD+nVhr+6deLaAZnN+qfwgGqVk5gym1P2Aq35yR866bH3Mn1eLqWiulsqTt5SvJnZT4DTxTV/8WV5lqeZRqc9GX17wljIJo4g4K/G9sfwLNm/Lvyzluy+IaJT6Sy/n8ciAnKul6n1gh5INdVWVfLopP7KUX/ySWqMQspSfZUy3vaVMwigyJ1c7luef5f21fVX5YdPeJr76Hf68WkzH2KF9GLF2KV9cdX27G7R8JVGmoRCylOOx1anCJ6PxJNyWpUzCKDJD+9qyVJ7N5pzKD79p1u1t4ts5gemvvzsd3Re8w5SpV3H0X/+AtrOr188eWw4dIqWM/kavvMpSfh5huC1LmYRRZJwmvjc+2phXWcqvlR/QviY+p6zW79JLM7NmEUnEKdOmdptV1jcm6ByA43JytdXE9+bH+ZGl/Oqx5eDmSnxFSxgi8oCIrBeRRUnbuovISyKyzP7Zzd4uIvJHEVkuIgtE5JBixVkM6qoqSTQp0xfnT5byg7V5OtojS/n5ajElNTVIhdXVGy9tX1evn/pyWiPfspRfPbYc3FyJr5gjjAeBE1tsmwjMUNVBwAz7McBJwCD7dhFwd5FiLApD+3Zh7x6dTFevjSNL5XI8/Px3pyQaRWbM4O+n/pBLfvBbdOTInF+qwW9FEGlolqUW5UeW8qvHloObslTREoaqvgq0HFOegrUYE/bPbydt/6tazAH2EJHK4kRaeJqrpT7ayKY8yVJ+/+Ksq65kQQ6yVIOP/ZLSEo3SdMVEnt99YLuqpYLgseVQV1XJxjzJUn722HJwS5Zyew6jt6quA7B/9rK39wNWJe232t4WGBxZ6sU8yVJ+XF0tmVxlqfrGBKUlQrkP7S9aY2w7m/iC4rHlUDO4Fx0j+ZGl/C5JgXuylFc/ZalWAErZySQiF4nIXBGZu2FD8SeBciXfspTfRxgDuucmSzmW7iLeXjQqW9rbxBcUjy2HjuWljDmwF2ufm0ni5lvaVT1WH/Ovx5aDW7KU20fsc0dqsn863SirgQFJ+/UHUqZSVb1PVUeo6oiePXsWNNh8YnlL5U+W8nvlB+QmSwWhOS0d7Wni8/sFRCr+q2kNdz94OSXXXNM+w8rGhK8/Jw5uyFJuJ4xngPPs++cBTydtP9eulhoJfOlIV0GiNo/VUkEYZuciS/muuz0L2iNL+dUvqTVGrFxAJBFHmhLtKjnetiMYczuOLFXMJr5iltU+CswGBovIahG5ALgNOEFElgEn2I8BngNWAMuB+4EfFyvOYjK0bxf26dGJaXlo4tsWgAa2XGSphsZ4oL4Uk2mP5XmQPLYcImNG0xSJEJcStLw855LjoFxkOLLUjKWfF02WKmaV1DmqWqmqEVXtr6qTVXWjqo5R1UH2z032vqqqP1HV/VS1SlXnFivOYuJUS21/9TW2XXdju7t6wd+VH5C9LOVHO5RsyNXyPGgeWwBEo7wz+W/cfswEFj70ZM6GlUGSMYstS7ktSYWeMxpX8X+P/oqON17fLl02KJq1I0tlOsoIesLI1fI8aB5bDsPPquXB485haln/nF8jCB5bDsWWpUzCcJmBi96mPBGnpJ26rJ9XV0tmQPdOVPfP3FvKV4tG5UCuslTQPLYcOpa3v4kvCB5bDqUlwonDerPpX6/QeNPN7TasbAt/f7sEABk1iiZ7gff26LJ+X10tmdqqzGWp+lgwJjBbIxdZKnAeW0mcXN2+Jj6nFDsojI+t4YGHJ1J27bXtUikywSQMt4lG+fTxZ7j9mAm8dOeU3BcS8vnqaslkI0sFSY9OhyNLZVU9FhCJMhXt9ZYKmow5dNk8InlQKTLBJAwPsO83j+e5k8/nr9o359cISuUHZCdLBe1qMRXNTXxZyFJBThjOSnwv5ChLNcSCdZFRMmoUpR0qoLQU2qFSZPReBXtlQ8Y41VKzV+TexBe0K+3aqkrK3pzDlqvTLySkqoEx2GuLbGWpQHpsJeGsxJeLLBWkSW+g2bCSG2+EGTNyVikywSQMj9DeJr6gfQhO3f4pU6ZeRZdbbkiry26PNaEarOa0dGQrSwXVY8vBkaWyXYis2WMraOdMNApXXlnQZAEmYXgGx1sq1/K4IFV+APSeN8euHku/kJCfF43KlmyrpYLqseXgyFLZrsTnFAMEYWEpNzAJwyO01/I8KKurNVNT01w91pRGlw1kc1or1FZVsnJjPe+va1uWCppEmYq6KmslvjkrMpelgjy3UwxMwvAQ7bE8D8rqas1Eo2x6+jluP2YCz/zuoZRD7bB9+Jub+DKQYepjCTpXBGfEmYqawT3pnGW1VBA9toqJSRgeoj2W50Gc/O09bhT/PuNCHmhKvXZWmCQpsGSp6L6ZyVJB6stJRy6yVBA9toqJSRgeoj2yVJBWV0umNW+p5qvFSPD+7nTUVWcmSwWt1yAdtVnKUmGTMfONSRgeIxdZKmirqyXTmuV52CQpsGSpEWuXsvGq9OXGEECJMg07ZanMVp5rXgYggJ+VYmAShscY2rcLe3XPTpYK2upqyTiW5ykTRoD/7nR0X/AOU6ZexVEP/QFtxQYi6B5bDtk28e28yAjPqDSfmIThMZJlqc0ZylJBv9KurapkfgpZKujNaSmZNYtIIk6ppi83hnB4bDnUVlWyuT7G7BUb29y3PoznTB4xCcOD1GXZxBf0yg9Hlnp+0a6jjFBeLdbUIBVWuXG8LJLWBiIMZbUOjiyVSQ9TEFamdBOTMDzIsH7ZyVJBr/zYq4e9Et+CdAkjmH93SmwbiL+f+kN+9oPfoiNHptwtDB5bDsmyVKwNWWpbGM+ZPGIShgfJVpbatiP4lR+pZKmGxgQiUFEWstM4GiVxxUSe221gymqpMHlsOdRVW7LUnDZkqVDKmHkkZJ80/9BcLfV+27JUGCo/UslSQbe/aI3WmvjC5LHlcNwBPTly/Ydsu+6mNqvHguyxVWg8cdREZKWILBSR90Rkrr2tu4i8JCLL7J/d3I6zmAzr14UB3TsybWHbCSOoq6sls1ePTgzr12WX49EQi4fqSzGZ1ryltoWsoRGgw9y3eHDKlRz/6J9arR4L80VGPvBEwrAZparDVXWE/XgiMENVBwEz7MehoVmWWv5Fm7JUkFdXS6auqi/zV21h9WZLlgpLc1o6HG+plpbnDWFsTps1i7J4nDJtQlupHgtTMUAh8FLCaMkpwEP2/YeAb7sYiyucXNWXeAayVFgmf5tlKXuUEfaEkc7yPCznwy4kV4+VlqWtHgvSQmNu4JWEocCLIvKOiFxkb+utqusA7J+9XIvOJYb168KJW1cgt93Wpi4Lwf+CcGSpZ+0vyLA0p6Uj3Up8YfPYApqrx54/68dceO5txA4/IuVuDY3hlTHzgVcSxlGqeghwEvATETk20yeKyEUiMldE5m7YsKFwEbqAzJnDnX+5nNOeureNrt7wVH7UVlU2y1JB9c/KhroUK/GF0WMLgGiU8quv4pUeg9JWS4V9VNpePJEwVHWt/XM98BRwOPC5iFQC2D/Xp3nufao6QlVH9OzZs1ghF4dZsyhLxNrUZcNU+ZEsS4XFL6k1xqaQpcIy4kzFcQfY3lJpLOBNwmgfrn/DiEhnEdnduQ+MBRYBzwDn2budBzztToQuUlMD9iJCsZJWdNkQVX7s3aOzXS21LnS9BqlIJUuF0WPLoUOklOOHWJbnqZr4GhoTgTTpLBauJwygN/CaiMwH3gKmqeoLwG3ACSKyDDjBfhwubF32tXMvYcLZN7PloENT7ha2yo/aqkreW7WFz77cHsovxZa0lGNBha0AABBrSURBVKXCJFGmwvGWSiVL1cfigV9YqpC4njBUdYWqHmTfhqrqzfb2jao6RlUH2T8zX4cxSESj9LjpOt7u+w1eXPx5yl3CsLpaMo4stSPeFD6dPgWOLOVYyYTSYysJR5ZK5S0VtourfON6wjC0jdPE92wab6kwrK6WzN49OjO0bxcgnLJLS1o28YV5DgNa95YKk8dWITAJwweICHVVfdM28YVxIq+uupJD1izhqCfub7XkOCwky1INjQlKwuixlUQqb6kwemzlm/CeUT6jrqoybRNfGKuFTt3+KVOmXsURD/weWik5DgvjkmQp6wKiLBRFEOlIJUuF0WMr35iE4RN2Wp5/PWGEsYGt8t036aAJSpoSrS4kFBa6OdVSC9bZHlvhOh9akkqWCmVDY54xCcMnON5Sr6eQpcK0ulozNTVIeTmUlkJ5edqS4zBxcnUln26q562PN5kvRb4uS9WH0WMrz5iE4SNOrk5teR7Kyo9oFGbMgBtvtH5Go25H5Dpjh1iy1EcbtoWqCCIdLWWphhD3p+QLkzB8xNC+liz1bIqV50JZ+RGNwpVXmmRh061zOUftvydgvhRhV1kqnmgKffVYPjAJw0eICHXVu67E19RkKj8MO6mr6sMha5Yw/l9TQl8IADub+Gav2Ej9Druh0fTu5IxJGD6j5Up82+MJU/lhaOakrSuZMvUqznj6XlM9BtQM3ilLmRFG+zEJw2e0lKXMh8CQTJc3X6eiKU5pU5OpHmNXWWrrjhhgPivtwSQMn9FSlgrl6mqG9NTUUFJRYarHknBkqZlLreUPzGcld0zC8CGOLDV98WdmhGHYFVM99jUcWWr6YkvGDV0Jeh4xR86HDO3bhb17dGLawnUM7rM7YBKGIYlo1CSKJBxZ6pn5awHzWWkPZoThQ5wmvjc+2sjaLdsBU/lhMLRGre1wLCH32Gov5sj5FEeW+sd7awBz1WQwtEbN4J4cuf5DLnnzCWTOHLfD8S3mstSnOLLUy0utlWtNwjAY0tNh7ls8OOVKSmMxGPOYmd/JETPC8CmW5bnlYAum8sNgaJVZs4gk4pSqKTduDyZh+JjaKmtNiB/Pfpwu7851OxyDwbsYs8q8IM7C8UFgxIgROndueL449Y032FEzmrJ4jNIOFYgZZhsM6Zk92xpZ1NSYz0kLROQdVR3R1n5mDsPHyCuvUJ6IUaJNqDPMNh8EgyE1pty43XhekhKRE0XkAxFZLiIT3Y7HU9TUIBUVaGmpNdw2w2yDwVBAPD3CEJFS4C7gBGA18LaIPKOq77sbmUeIRi0ZygyzDQZDEfB0wgAOB5ar6goAEZkKnAKYhOFghtkGg6FIeF2S6gesSnq82t7WjIhcJCJzRWTuhg0bihqcwWAwhAmvJwxJsW2Xsi5VvU9VR6jqiJ49exYpLIPBYAgfXk8Yq4EBSY/7A2tdisVgMBhCjdcTxtvAIBEZKCLlwNnAMy7HZDAYDKHE05PeqhoXkZ8C04FS4AFVXexyWAaDwRBKPJ0wAFT1OeA5t+MwGAyGsBMoaxAR2QB8kuPT9wS+yGM4+cTElhtejg28HZ+JLTf8Gtveqtpm1VCgEkZ7EJG5mXipuIGJLTe8HBt4Oz4TW24EPTavT3obDAaDwSOYhGEwGAyGjDAJYyf3uR1AK5jYcsPLsYG34zOx5UagYzNzGAaDwWDICDPCMBgMBkNGmIRhMBgMhowwCcNgMBgMGWEShsFgMBgywiQMg8FgMGSE572kComIdAVOxFqUSbGs06er6hZXA2uBiByNtfrgIlV90QPxfANr5cPk4/aMqi5xNbAWmOOWcVx7quoXSY8nYB834H51uZRSRMYB32bX4/a0qr7gclxeP255P99CO8IQkXOBeUAN0AnoDIwC3rF/5xoi8lbS/QuBPwG7A9eKyETXArPiuQKYirW41VtYFvQCPOqB2Mxxy43mZCoik4DvAu8AJwC3uxWUHc/vgZ8BrwC/AX5r379ERP7gZmx4+7gV5nxT1VDegA+APVJs7wZ86HJs7ybdfxvoad/vDCx0ObYPgUiK7eXAMnPcfH/c5gGd7fsRLxy3NNvFHLfWj1shzrfQjjCwTrhUQ8YmUi8NW0xKRKSbiPTAaq7cAKCq24C4u6HRBPRNsb3S/p2bmOOWGx1F5GARORQotY8XqhoDEu6GxnYROTzF9sOA7cUOpgVePm4FOd/CPIdxMzBPRF4EVtnb9sIaTt7oWlQWXbGGtgKoiPRR1c9EZDfcT2Y/B2aIyDJ2PW77Az91LSoLc9xyYx07JZRNIlKpquvsxOt2oj0fuFtEdsdashmsZZv/Y//OTT7Du8etIOdbqK1BRKQbMA5rUkiwTsjpqrrZ1cDSICKdgN6q+rHLcZRgTe4lH7e3VdXtq6qUmOOWGyJSClSoar0HYulD0nFT1c9cDiktXjluhTjfwjzCQFU3i8jLJFUReDVZANgnoKtfenYcTcAc57GIdPfCl56I7KEpKty8ctywzjHn1pT00xOISMSWUwBQ1YSdbF1PGHaCcEaLB4jI9lT/62IiItWquqDldvuz4PoxowDnW2jnMERkuIjMAWYBv8auvhCROSJyiMuxVdtxrBKR++yRkPO7t1p7bhFim5R0f4iIfIhVWbZSRI5wMTSAL0TkXyJygYjs4XIsuyAiY4FlwHVALVAHXA8ss3/nGiIySkRWA2tF5EUR2Sfp166WI4vIn5PuHw28D/wPsFBEal0LzOJdEVkuIjeKyBCXY9mFgp1vbs7ku1xF8B5wRIrtI4H5Lsf2GlZ/yB7AfwOLgf3s373rcmzzku5PA06y7x8OvOFybAuBk4EpwEbgaeBsoKObcdmxLQH2SbF9ILDE5djeBoba98+wv2hG2o+9dL69DBxi398XmOtybO8Cw7DmQ5cD84GJqf7PLsRWkPMttCMMrBK4N1tuVNU5WGWYbrKbqr6gqltU9XdYk1QviMhIUld2uUVfVX0eQFXfAjq6HE9MVZ9V1f8C+mMljrOA1SLyiLuhUcbOSdtk1mCVYbpJuaouBlDVJ7Ca5B4SkVPx1vnWRVXnAajqCqDU5XhUVRep6lWquj9wIdAL+LeIvOFybAU538I8h/G8iEwD/srOKoIBwLmAqx2kgIhIV1X9EkBVXxaR04Enge7uhsa+IvIM1iRafxHppDsn99z+4muuhFLVBuBx4HG7o//brkVl8QDwtohMZdfz7WxgsmtRWcScijIAVV0sImOAZ4H93A2Nb4jIAqz/7T4i0k2tuccSPHS+QfNF01sicilwrDshNVOQ8y3sVVInsbN13qkieEZVn3M5ru8AK+zRTvL2vYCrVfVCdyIDETmuxaZ5qrpVRHoDZ6jqXW7EBSAi/22PyDyJiBxI6vPtfZfjOh7YoKrzW2zvCvxUVW92JzIQkb1bbFqrqjER2RM4VlX/7kZcYH1OVdXtkWta7HmVb5HH8y3UCcNgMBgMmRPaOQwR6Soit4nIEhHZaN+W2NtcrbBJim2piS0YsbWGiDzvdgzpMLHlhtuxiUgXEblVRP5PRM5p8bs/p3teW4R5DuNxYCYwytFu7eag84G/YXV8u4UTW02L2M4zsfkztlZKtQUYXsxYvhaAiS0nvBwb8L9Y1W5PAt8XkTOA76jqDqxK0JwIrSQlIh+o6uBsf1cMTGy54fHYElguq6ksSkaqqmsVZia23PB4bO+p6vCkx1dh9WN8C3hJVXPqNQvzCOMTEbkceEhVPwewJ27PZ2dVgVuY2HLDy7EtAX6oqsta/kJETGzpMbHlRoWIlKjlyoCq3mw3Z74K7Jbri4Z2DgMYD/TA6u7eLCKbsbq+u2PV7ruJiS03vBzbdaT/vF1cxDhScR0mtly4Du/G9k9gdPIGVX0IuBRozPVFQytJGQwGgyE7wixJeXbpRzCx5YqJLTdMbLkRtthCO8IQa+nHA7A6vZ0W+v5Ynd7LVPVnJjYTm4nNxGZiS3rdECeMD1X1gBTbBWtZyEEuhOXEYGLLARNbbpjYciOMsYV50tvLSz+a2HLDxJYbJrbcCF1sYZ7DOB/vLv14Pia2XDgfE1sunI+JLRfOJ2SxhVaSchAPL/1oYssNE1tumNhyI0yxhT5hGAwGgyEzwjyHkRYRmed2DOkwseWGiS03TGy5EdTYzAjDYDAYDBkR5klvoNlrqLmxxfEg8gImttwwseWGiS03whRbaEcYIjIcuAfoirXOLViNLVuAHztrB5vYTGwmNhObic1GVUN5A94DjkixfSQw38RmYjOxmdhMbLvewjzp3VlV32y5Ua11tDu7EE8yJrbcMLHlhoktN0IXW5jnMJ4XkWlYXiuOd/0ALK8Vt43DTGy5YWLLDRNbboQuttDOYQCIyEnAKSQ1tgDPqOpzrgaGiS1XTGy5YWLLjbDFFuqEYTAYDIbMCe0choh0FZHbRGSJiGy0b0vsbXuY2ExsJjYTm4ltV0KbMIDHgc3AKFXtoao9gFFYZWd/czUyE1uumNhyw8SWG6GLLbSSlIh8oKqDs/1dMTCx5YaJLTdMbLkRxtjCPML4REQutzshAasrUkSuYGdVgVuY2HLDxJYbJrbcCF1sYU4Y44EewCsisklENgGzgO7AmW4GhoktV0xsuWFiy43QxRZaSao15P+3d/cuUl1xGMefhw26S2KlYBfFRvANxVglAVMEC/+BSBA0VQorsbGwsVZBksJCEkQkVqKJKAiJMYVg5aJJIFVEtLIQ8WVF0cfi3uLuzSx7PJPdEef7gYWZc2bOeWYY5se55+5ce2+SH0edYxCy1SFbHbLVeV+zUTAGsH03ycejzjEI2eqQrQ7Z6ryv2cb2P71t35qrS9LKOfoWBdnqkK0O2eqMY7axLRhq3rQdak4967Kk64sfZxay1SFbHbLVGbts41wwLkr6KMl0v8P274sfZxay1SFbHbLVGbts7GEAAIqM82m1AIC3QMEAABShYAAAilAwAABFKBhAIdtHbf9t+7tO25Tta7Yn2vuxfbrT/4HtB7Yvdtqe9MbdY/v7OeZcYvsP2+N8RiPeEXwIgQK210j6NMm6Xtc3ks4ledXefyppg+2pJDOSvpR0v3beJC9s/6rmt4HO1I4D/B9YYQDzsL1W0jVJq2zftP1hp/trSRd6T7ksaWd7e5eknwrn+db2dPv3r+2rbdf5dh5gpCgYwDyS/CPplKRDSbYkeSo1h4skrUlyp/eUs5K+sj0paZOkG73+qU5hmJZ0uJ3nRJLNkrapuf7ysfbxf7ZtwEhxSAoos1H/XUmsUHMFs1mS3LK9Ws3q4tKAsWbawiCp2cOQ9Emn/7ik35L80o73yvYL28uSPB7mRQDDoGAAZdZL+qvXNiNpco7H/yzpiKTtaq5LUKQtHqsk7et1LZX0vHQcYCFQMIB52F4m6WWSZ932JA9tT9ieTNL/Mv9B0qMkt21vL5xnq6QDkj5P8rrTvlzSgyQvh3ohwJDYwwDmt0HNPsIgVyR91m9Mci/J8becZ5+aK6Jdbfc3TrbtX2jwoS1gUfHjg8AQbG+RtD/J7gWc45ykg+3mOzAyrDCAISS5qWZFMLEQ47dnYp2nWOBdwAoDAFCEFQYAoAgFAwBQhIIBAChCwQAAFKFgAACKUDAAAEUoGACAIm8APQ056ADb2kEAAAAASUVORK5CYII=\n", - "text/plain": [ - "" - ] - }, - "metadata": {}, - "output_type": "display_data" - } - ], - "source": [ - "# Plot results.\n", - "sig = resultsi + 1j * resultsq\n", - "amp_array = np.abs(sig)\n", - "phase_array = np.angle(sig,deg=True)\n", - "for x in range(0,len(phase_array)):\n", - " if phase_array[x] <0:\n", - " phase_array[x] = phase_array[x] +360\n", - "plt.figure(1)\n", - "# plt.plot(gpts, resultsi,label=\"I value; ADC 0\")\n", - "# plt.plot(gpts, resultsq,label=\"Q value; ADC 0\")\n", - "# plt.plot(gpts, amp_array,label=\"Amplitude (DAC units); ADC 0\")\n", - "plt.plot(gpts, phase_array, label=\"Phase (degrees); ADC 0\")\n", - "plt.plot(gpts,phase_array, marker='.', linestyle=\"None\",color=\"Red\")\n", - "plt.xticks(rotation=90)\n", - "plt.title(r\"$\\phi$ vs $f$\")\n", - "plt.ylabel(r\"$\\phi$ (degrees)\")\n", - "plt.xlabel(r\"$f$ (MHz)\")\n", - "plt.legend()\n", - "plt.savefig(\"images/Phase_sweep.pdf\", dpi=350)" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### Params 2 (We try again with finer spacing and now there is enough data for us to calibrate phase)" - ] - }, - { - "cell_type": "code", - "execution_count": 8, - "metadata": {}, - "outputs": [], - "source": [ - "sweep_cfg={\"start\":100, \"step\":0.000125, \"expts\":160}\n", - "\n", - "gpts=sweep_cfg[\"start\"] + sweep_cfg[\"step\"]*np.arange(sweep_cfg[\"expts\"])\n", - "resultsi=[]\n", - "resultsq=[]\n", - "for g in gpts:\n", - " time.sleep(0.1)\n", - " config[\"pulse_freq\"]=g\n", - " prog =LoopbackProgram(soccfg, config)\n", - " (iq0,) = prog.acquire_decimated(soc, load_pulses=True,progress=False)\n", - " di0 = np.sum(iq0[0])/config[\"readout_length\"]\n", - " dq0 = np.sum(iq0[1])/config[\"readout_length\"]\n", - " resultsi.append(di0)\n", - " resultsq.append(dq0)\n", - "resultsi=np.array(resultsi)\n", - "resultsq=np.array(resultsq)" - ] - }, - { - "cell_type": "code", - "execution_count": 9, - "metadata": {}, - "outputs": [ - { - "data": { - "image/png": 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ioqK499578/7myvjx40lISODmm2/m+PHj9OvXz/P/1GsQsD29hRD1gFlAKA5H9YWUcqQQYhlQEUcwtB54Rkp5VnMgHwOdgXPAY1LKq2520ahRI1kU98MYtWgryav2s6FjaT4ZMQ1at+al1/sEe1hBYfSirWz9ejFz5g5DzcqC8HDCfllmiLTUtm3buP322312vcxT5xFHDlP5zHEE2oyjWjWIjPTZPXzNn3/+SUJCAp9//nmhXn/27FlKlXLUsMaNG0dmZiYffPABmafPIw773hYLFixg3bp1jBo1CoBOnTqxePFir67pbwp6nwkh1kopG13rtYFUSW0EGhRwvO0VzpdAf3+PywzYVUlIiCCsRXMyni7FT5sP80yunYgw32rZjYAqYVONOoQsS2Hm6BnsrtuIMQZwFv5AAucjSsC/J5GqihQCcZU8uB5o0KABbdq0wW63F2otxvfff8/YsWPJzc2lZs2azJw5EwApNVucPYmUKggBPrBFbm4uAwYMyPtd787CW6zmgyZASkmIVhyMqxfJ7m9/JmPQcm56sOippVTpcJ4oCmdeqUBSyk5e/OcCla8rmmLj8+HFELfcwskjxzkdVoyaJUsWqCbRE48//nihX9ujRw969OhR4N/O24rBrbdw7NDfqCVLUUWbiXjDgw8+6PU1jITVGsQE2KUkNMTxGGhxNJ3E5HhqfTCuSBZ8VSnRTEHXelVokLGNjEGvFzk7gIuksFQpqBLJP6ERnMu+vOVGkUGAKFWKnEqV+RsbdrVIiiq9wnIYJkCV5D0kbb8tL9JqKbt60XnevHszSfPiiZlsHLWUT2uKUiK0+UTp4mGaWsr93lJmQsqLOv0yxW0UyzpPdsbBImcLb99flsMwAap6MSVFbGyRVkup0kW7n5pqKLVUsWLFOH78uM+chutVws6d09RSR3yuljIGTpGxQ2bsVEtRhGzh3A+jWLHCp2etGoYJUF1qGCgK6pKlfDJiKqFt2/BCUathqJLQS5xnBLlZWRBmI0znzrN69epkZGTkNZ3zlpPnsrmQoyJOF4PTp5GnTl2sX2RngyY5LQpYtnDg3HGvsFgOwwTYVfLSMAC2ls3Z/3RJlm49wtO5KuFhRWci6VrDQFEIWZbCjNEz2BvViNE6d542m63QO6EVxMAvN/DbrhOkDXWk42S3btgvZCFt4dhSl4EPJbx6Z/D8jaTuPM7K19o7tgS47z5kVjYiIpzQZUXLFt5QdJ4kJkZKSf4OCnFRkdy8e1ORK/janSopJ4rC6ZdfJTGkGkfPFK29sh21rYszT5GSwsJuT9P/8beRLovIigJ26TLzVBRYmsKn7fowYcikIqck9AbLYZgAV5WUk1bHHWqpmkVMLSVdH5IaXaMjaZCxjYOD3igydgCnxNjlgKKgDhnK32ezODxkeJGzhWtfqtDmzch87hWm5VbhfFFWjnmI5TBMgFrAQzL8t/8VSbWUq0rKyS17NpE0L556n71XpJznJbUtjS5n9pKYPIzK744pWrYo4H3RNTqS2/dt5kARm4V7g+UwTIBDJZXvYBFVS6kFpOfEr78aSi3lK+yuAgCN0it+J9yeS0gRCyRcpedOGh/eQVJyPDd9NL5IOU9vsByGCSgokkRRyF3yMx+3eZTPXp9cZPK0qrz8IZmnlipiO/FJyWXOk9hYpBZISFt4kbHFZbUtIOx/y7EVwVm4N1gqKRNQUBoGIKJlC/Y+WZLlO4/xpF3FFmr++EBVL0/POQq+S5kxegYZ9RrzZhFxngW+LxSF8z8u5rM3p1Pp7k48WkRsIQsKqpyz8KxshM1GaBFxnt5g/idIEeCSxWr5iIuO5Mb0jWQUkYJvQZEkgGjWjNMvvcrnoip/n80KwsgCT4EzT6B0m1ZseORZpuZW8e3Kch1TUHoORUH+vJRJ7frwgaWWcgvLYZgAVUquNHmIPbGLxOR4bnh/bJHI00pZQD1HIy46kpgi1FvqSg4DHAXfCpvWcuS1EUXEFgWk54CwFs059OzLTLNX4UKOpZa6FpbDMAFXezBEFDG11JXScwC373P0lor+tGiopVTJpbJaF+LO7iMxeRiV3h5dNGxxlfdFXHQkt+7dzIGBRSOQ8AbLYZgAu3plh1HU1FJXS88VNbVUgWkYjetWFi211NWCKuXIThKT4/k/Sy11TSyHYQJkAZLBPDS11EexjzJ5+BTT52kdKqkr/LGIqaXyL1a7hCKmlrJLCqxtgUMtVZRm4d5gqaRMwNXSMOBQS+1+ogRpu4/zpF0lzMRqqatFkk611PRRM8hs0IThRcF5Xul9oSj8+/1PTB41g6r3dOJhk9viarUtSy3lPuZ9chQhrhpJanSNjqTmzg0cHGxutZRzu9orIZo14+RLA9iUcZpzb442tS0cEuMr/71Mu9as7/0MU+2RpldLXS0951RLTWzbh49e+9T0s3BvCJjDEEIUE0KsEkJsEEJsEUK8qR2/UQixUgiRLoSYJ4QI145HaL/v0v5eK1BjNRoFLlbLR9uTu0lMjqf6BHOrpQpa0ZufB7IP8Pnc1yg2coSpbWG/2mxLIy46knIb1nBs2AjT2gGuMfPEoZbKeOYl1uw9Qe6YMaa2hTcEcoaRBbSVUtYHYoDOQoimwHhggpSyNnAS6Ked3w84KaW8GZignWdRAFdTwziJ+L1oqKWupoZx8n+bV2Oz5xKi2h17IZjUFgUuVstHV00tVWG8udVSqnrtz0iP3AymfD6EkDeGm9oW3hAwhyEdOLe2smlfEmgLzNeOzwLu1X6+R/sd7e/txLXyLkWUq6qknMTGgs38aqlrRZIAok0bpGYLGW7egu+1alsAZVf9USTUUu68L+rv3lAkAglvCGgNQwgRKoRYDxwFfgZ2A6eklLnaKRlANe3nasABAO3vp4HyBVzzKSHEGiHEGl/tVGY03IkkURRylizhw9hHmGZitZS9gM69l6Eo/PXFNyS07M2yj5JMa4srLVa7hCKilipoC4D8hLVtg2qzmT6Q8IaAOgwppV1KGQNUBxoDBW1z5ay+FfS/e1llTko5WUrZSErZqGLFir4brIFw58MAUKxVS3b1e4G0PSdQ33rLlFPuq6phXLjp7g58G9eH2aKq/wcVJK6qknKiKJxZ9BMTWvVm3rgZJnee17bFpplfkdCyN2unfWlaW3hDUGS1UspTQohUoClQVggRps0iqgOHtNMygBpAhhAiDCgDnAjGePXOtdQwrjykHuSOGQMRqh0iwiElxVQfDHfSMOB4eHSNjmRd8g9cOLCEYh3bmcoO4F4aBqBc+9as3RPO4rPZ9ArAuIKBY6/3a58X/WAX+u4I42hYFRr5f1iGI5AqqYpCiLLaz8WB9sA24BfgAe20PsA32s/far+j/X2ZNLv2r5C4+2AAaLxvEzZ7rsNhmDBP61YkqXF/9gFmz32NcJOqpewFde69Al2jI7nuz9WmVUu5+xkJDwuhQ53KHP5pGbljzDkL94ZApqQigV+EEBuB1cDPUspFwGDgv0KIXThqFNO086cB5bXj/wWGBHCshsIThxHevq2p87Tq1fT2+ai9dY2pi5zupucAuv7rUEuVHzfKpM7z6utzXOllP8iU2UMIeeMNU9rCGwKWkpJSbgQaFHB8D456Rv7jF4AHAzA0w+NuGgYARWHllC9Im/YV/3nxIeqYMQ3jZhiUp5bKySY0PBxhMufpyfvi+tVp2O25hEj1ovM00Xvjqu1z8tFgz3owsS28wVrpbQIK3FntKjTsEce0lj35wlbdf4MKEu4sVstDUdiTvJCElr355ZO5pnsoeDLzdFVLqSZUS7krDAEIa2vuWbg3WL2kTIAnHwaAkhFhxN5akQM/pKBu/oaQNm1M87CU7shqXbjl3o4s3B7GDnEdbf04rmCgXqXh3mUoCv8s+pGpo2dQs1tXepjk/eDEnfY5eSgKG2Z8xS+ffUGH53rQwGS28AbLYZgAjyJJjYfVQ9w5zXxqKY/SczgK5F2iI9n05U9cOLCYYu3No5ZSPahhAFzfPpbVu8I5tG09PcaOdUTWZrGFB7UtgOgHO/PYjjCOh0ZenkcvwlgOwwQUuI/1NWiyfxOh9lyEyfK0jkjSs9c8mH2AV5OGEq7aYexb5nKeHhqjj8ik3cRXkNKOCDdPIOFOjzFXitlCaX97JTIXL8O+YxGhbc0zC/cGq4ZhAq62ReuViDCpWsrTSBLglu1rTamWkh5IjJ20PrTVIbu2m8sWnqiknPSyH+SzmYMttZQLlsMwAW71ksqPopD22RcktOzNjjkLTBM9qR7WMABCTNpbypGe8+w1pTu3xx5mIzckBExkC7fa5+Sj4d4Npl6zVBgsh2ECPCpuutCwZxemtuzJF7YafhhVcLBLzyNJFIXdcx1qqeUTk03kPAsXSCz5MJGEFr05OP8709jC7sYWAPmxtTPnLNwbrBqGCfC0uOmkdDEbrWpraqlNC02hlvJksZort9zbka+3h5EeUobWvh9WUFAL4zyBRr3ieGFfMUoWr0l/P4wrGLizBcBlKArrps1n+ZQv6dS/J/UN/tnwBZbDMAHubKB0JXrLgzSZ+ipC2h0pCIMXOT1VSTkJCRF0jqrC1q8Xk/XXT0SYQC3laaHXSWSZ4jS8oSy7v/kZVnxpCrWUWpi0LRDTowv9doZxMqwa9f0wLqNhOQwTYFc90Jjno+mBTYSZSC1VmBqGk+65GdyYOBSbSdRShVFJOekrMunwycumUUsVKj2HQy3V9vbKZP64DPu274q8WsqqYZgAKSlUVA1QrH077CbK0xY2kgS4zWRqKY8Wq+UjNtNcaqnCzjwBHrZnMGnmIEstheUwTIFDJVXIFysKf3w6j4SWvdmZaHy1VGHrOWA+tZQ729Veieu6dDCVWsrT9jmu3LFvo6WW0rAchgkobHHTScOecUxp0YP54cZXS3naJuUSFIWdiQtIaNmb3z41vlqqsDUMABSFn96fQ0KL3mR+vcjwtiiMSsqJpZa6iOUwTEBh87NOyhS30eLmCvy1KAVp8J34PNkPoyBu69aJLzs+wh+7jsPYsYa2RaEkxi7c0SuOiUp3Fhar6cNRBQevgipFYc20L0lo2ZtNs74yvPP0BqvobQJUSaGjJye95SGaTX0VDK6WUguxWM2V0BDBU2GH6T3iGcMXfAuzWM2V6uVK0D0ngxLvfQsRfQ1pAyeFaZ/jSoPucfTbYeMfWzXq+XBcRsOaYZgAr2oYGs0PbDZFkdPb2RZAp793mMIW3qikAEhL461PXubh76eitjV2sdeb2hZA8fBQ+oUepson72P//Q/fDcxgWA7D4Dh3rfUm9QBQrGM7R5HTwHlaKaVXslon1e7tQm6oDXtIqKELvl7VMABSUwnNzSHMVXJtULyqbQGkpfHKuGd5JmUmtDe28/QGy2EYHLuqOQwvH5IoCr9NSiahZW92z11oyPSDc8d3b20R2rwZs0ZN5YPWvbnw02JD2kJVfRBIxMYiwsPJDQkhJzTMsI5TSlmoRoyXkJpKSJ7zzDG08/QGq4YBkJaG+ssvhmyNoT0XvIueNO7oFcfTu8Oxh9dgqNdXCzx2zWN4U8NwEv1gZx46VY5by95MV+8vF3BU6YNAQlEgJYW1M75i/PkqfHBrfYyoo8v7jHhjC8152rOyHc6zVWtCfTM8QxGwGYYQooYQ4hchxDYhxBYhxEva8RFCiINCiPXaV5zLa4YKIXYJIXYIITr5ZWBpadjbtkWNfx1pwEU5zgeDtxMMgLIlwnmUTK7/MAH5h/HytBdt4b0xmtxYnjYndpE7Zozh3hPg6jy9n3lWHTeSddVu58fNmT4YWeC56Dy9uIjmPHf2H8hDPUazJvJW3wzOYAQyJZULDJBS3g40BfoLIepof5sgpYzRvn4A0P7WE6gLdAYmCiF879RTUwnJcUw1ZZbx8rTOD4O3KikA0tJ4LeF5+i2ejmzX3nAPSlV1fPfFbCt05Qo+mzWErl9OMmQg4UzP+eJtUeP6EjyQfYBi775jODuAS9rWB87zhndGYQsN4czwUYa0hbcEzGFIKTOllOu0n88A24BqV3nJPUCylDJLSrkX2AU09vnAnHlaYcw8rc9qGHBJkVMasMjpk0jSSWoqNgPbwvm+8FUgMXbiKzy0aAqqgZ2nLz4jJddqb9OBAAAgAElEQVSt5vO5rxGb+JEhAwlvCUrRWwhRC2gArNQOPS+E2CiEmC6EKKcdqwYccHlZBgU4GCHEU0KINUKINceOHfN8MNpUM63vyzzUczTHohp6fo0g4szPeh09wcU8bUgoOaFhyNbGavRt90Xe3klsLEQ4AolcAwYSPqlhOElNJcxZ8DXgLNyXtS2HLXJNoRwrDAF3GEKIUsBXwMtSyn+AScBNQAyQCbznPLWAl8vLDkg5WUrZSErZqGLFioUblKJQ8a3hrK16Oz9tOVy4awSJPDWML6JqzXlufnoAD/UYzZaadX1w0cAhtZSUTx6SioJISWHpQ8/T5+GxXGjk+8mtP/FHIGFUtZRPnWdsLCIvkLAZzhbeElCHIYSw4XAWiVLKrwGklEeklHYppQpM4WLaKQMuEWVUBw75a2y3Vi7Nf/7dh238OENNM1VfFTedKAo13hlFiBCciH/TULbwWaHXiaJQavjrpFW6hdQdR31zzQDhj0Bi9eOv0KvHaA7dHuODiwYO1ZdpWy2Q+Pb+Z3jmsfGoTZp6f00DEUiVlACmAduklAkuxyNdTrsP2Kz9/C3QUwgRIYS4EagNrPLb+FasYMKUV3ngm8mGyk3afagMcnL9xrUkJg+j+awPDGULn9YwNJr+3/XEHt9F9mhj9djyRyBRZeybmlrKYLPwvBqGjy6oKIQOe42Usjexbv9JH13UGARyhtEceARom09C+7YQYpMQYiPQBngFQEq5BfgC2Ar8BPSXUtr9NjqXPK2RipzSFxrz/KSmYrPnEmqwPK1PFqvlI2zVSibPHkzcFxMN5Tz9EUjcWKEk913YT8Q74w1jB3ARAPjwfdH2tko0PryD02+MNJQtvCVgC/eklL9RcF3ih6u8Zgwwxm+DciU2FsLDyb2QhT0kjAiD5Cbtvkw9OHHmaS9kIcNs2AxiC9WHapg8UlOx5Tp2JFSzsxEG2ZHQL4FEWhpvf/pfRHY26s+zCTFIU0bpB+dZ+s81zJn7GiE5Ocj5kxEGsYW3WK1BnGi5yT/6vMRDPUdzPNoYainVR72kLkGzxfx7n+KVJ95FNjVGntbuyzUpTgyqlroYVfvwogZVS/m8tgVFVi1lOQxXFIXyY4YjJRwY9IYhppqqL5VBrigKuYOGsKhULXYcOePba/sJZ0rKp6bQnOfPvZ7nMQOppXy56j0Pg6qlfF7DgCKrlrIcRj7q7NtC0rx4oj991xD796q+1Jjno3NUFe44tI1jr43QvR3AD4VeJ4pCieHx/F7pFpbvLMRanyCQt+rdlw5DU0ut6vsyvXqM5nCdBr67th/xqUrKiRZIfHP/M/R//O0io5ayHEY+xK+/Em7PIdQgxW+fLlbLR4VN60hKjqfZTGOopfxSw9BodlN5Wv6dTvZoY/SWupiq9PGFFYVKY98E4ODg141lCz/MwsXQoSwp83+szzjl22vrFMth5Cc2FsIjyBUh2MP0P9WUfnQYDrVUjmHUUj7rGVQAtlUrmfb5EDrPM4Zayp+BxM27N5E0L56YyQmGmIX7QyXlpN3tlbkzczunXi8aainLYeRHURApS5nW6XHG/Pcj3Ssf7P6qYYCWp3U4z1xDOU8/XNylyGmEmae/AwkjzcKdM09/mKLM+jXMSR5Gq88/NEQg4S0eOwwhREm/dI3VEaJZM06+OIDZVOXkv9nBHs5V8WcNw5mn/fKep/jvU+/p33n6QyXl5JIip/4LvnYfdu69DIPNwv1W24I82XVRUUtd8zEjhAgRQjwkhPheCHEU2A5kantavCOEqO3/YQaertGR1D+wlQOD9J2ntat+UMO4oijkDBrMdyVqkq5ztZSz0OsXW2jOc0nP/jz+8Fiy7tS3Wsofq97zUBRClqUwu0s/hr/0ge4DCb/VMKDIqaXciUt/wdEccChQRUpZQ0pZCWgJrADGCSF6+3GMQSFqv0MtVXeSvtVSflmglY/OdavQ8NA2jupcLeXXSBJAUSj+Rjzncuxk6Fx27dO29wWhKJx++VWSQqpx9MwF/9zDR/jVFlogsbDb0/R//G3DrFkqLO44jPZSylFSyo1ag0AApJQnpJRfSSnvB+b5b4jBwShqKbu/1DAuVNryJ3OT42k6431dO0+/RtUaLY6lk5gcT60PxunaFr7cA+JKdK0XSYOMbRzUufOU/liH4YqioA5xqKU2Zpz20030wTUfM1LKHF+cYzgMkqf163TbiYtaStfO048qKSe235YTruYQqurcFv6ebQG37NlM0rx46n32nq6dpz9VUk461qnMnYe2c/J1Y3V49hS341IhxINCiNLaz/FCiK+FEMbon1EYNLXU1I6PMW7Ax7rN0/plUVJ+DKKW8uc6jDycPcdECKpNz7bww6r3/BhELRWIoKrshrXMSR5Gi9nmVkt5ksh4XUp5RgjRAugEzMKx+ZFpEc2acfyF/zKLSE6f1+ckyvmQ9Gf05MzTzrv7SQY9o1+1lE/3N78SioJ9yc983OZRJsZ/pl9bBCCqNtws3J+20Do8m10t5YnDcLYW7wpMklJ+A4T7fkj6Ii46kuj9W9k/UJ9qKbs/+icVhKKQPXAwC4rVZPexs36+WeHw6aZBVyG8ZQv2P/USU3Iqk52rXvsFQSAgsy1tFj6z8+OMfOlD/TpPf9cwoMiopTxxGAeFEJ8BPYAfhBARHr7ekMRkbCNpXjx1Jr6jyzytDERUrdE5qgoND27jyJDhurMDuAoA/G+LLtGR3Lx7Exk6lV37XSWlIZo145+XX2VOSFX+Ppvl13sVlrwaht+dZwpf3/c0Lz7xjmnVUp488LsDi4FOUspTwPXAQL+MSkfoXS0VyIdk5Nb1zJ0XTxOdqqUCoQxy0uq4Qy1VU6dqKb+ues9HXL1IYjK2cUCns3C/dO4tCEVBHTyEI/9c4IjOJeiFxROHcR4oCfTSfrcB5u+4pfM8bUBSD050rpbyyx4QVyDit//pWi0VCJWUk1t1rpZS/bnqPR9xZ/eRmDyMSm+P1qUtvMWTj9ZEoCkXHcYZ4BOfj0hvKAosXcqUDn15e6D+1FKBytsD2mZC+lVLBSySBN2rpS72T/K/LfQ+Cw/E+hwn1638nXB7LiE6DSS8xROH0URK2R+4ACClPEkRKHoDhDRvxrHnBzBTrco/F/SllvL76mZXFIWQlBSS73qSwc8k6M95BrCeg6KQu+RnPop9lM9en6w/WwRCJeVE57PwQKZtiY1FaoGEtIXrzhbe4onDyNGaDkoAIURFwG2JiBCihhDiFyHENq0P1Uva8euFED8LIdK17+W040II8aEQYpcQYmOw13x0rVeFqP1bODBQX6taA1XczENRuPDqIPYd/5eT8fpapOS33QevQETLFux98kWm5FYmx64vtVQgo2qnWmpG58cZ/Yr+Ojz7tXNvfhSFcz8sZkKrR5j71jTd2cJbPHEYHwILgMpCiDHAb8BbHrw+FxggpbwdR2qrvxCiDjAESJFS1gZStN8BugC1ta+nCPKajwYZ20maF89tE9/WVW4yICu983HP+f0kJg+jzNiRurJFINqk5CcuOpIb0zfqrrdUoAMJ0awZp14awOeiKid01uHZ7o/dB6/CdW1bsb73M0y1R+Y5K7Pg9kdLSpkIDMLhJDKBe6WUX3rw+kwp5Trt5zPANqAacA+ORYBo3+/Vfr4HmC0drADKCiEi3b2frwlZruVpdZabzCt6B/AhWXFtWl6eVk+LlAIaSWq0ObmLxOR4bnh/rK6cZ0DFEBpxzg7POlNL+W33wasQFx1JuQ1rODZshK5s4S2etAYRQCOgvJTyY+BfIUShejwLIWoBDYCVQGUpZSY4nApQSTutGnDA5WUZ2rH813pKCLFGCLHm2DE/7rccG4vUYZ42IBrz/LjkaVUd5Wn9ugfEFdCrWiqgtS2NOvscHZ6jPtVXh+eAtM/JR1dNLVVhvLnUUp6qpBS8VEkJIUoBXwEvSyn/udqpBRy7bH4npZwspWwkpWxUsWJFT4fjPoqCWLqUyR368t6gT3STmwyoMsiJonDimx9IaNmbhe/O0p0tAviM1K1aKhi20KtaKiDtc/JRdtUfplRLhXlwbhMpZUMhxJ/gUEkJITxSSQkhbDicRaKU8mvt8BEhRKSUMlNLOR3VjmcANVxeXh045Mn9fE1I82Yc7V+Guav283xWLiUjPDGffwhGJAlQqVMbft8Vzv9USbeA3vnKBKOeg6KQu/hnPhkxjeId2/GsTpxnIDr3XoZTLZWVBWE2wnTiPO1BCiRkeDi52dmE2MIROrGFtwRSJSWAacA2KWWCy5++BfpoP/cBvnE5/qimlmoKnHamroJJl6gq1P1rC3/pJE97URkU+HvHRVXBtmoFp3TS0jkoDgOIaNWC3U+8wNScyuTqRC0VyFXveWhqqemdHmfMf/WjlgpGbQtF4cyin5jQqjfzxk7XjS28pTAqqUqFVEk1Bx4B2goh1mtfccA4oIMQIh3ooP0O8AOwB9gFTAGe8+BefqNR5g6S5sVz6yf6UEvZg/SQBLj3gkMtdd1b+lBLBaOG4aRrdCQ1d27g4GB9qKWCUtvCoZY68eIANmWc5vybo3Vli0B/Rsq1b83ah55hmho0rY7PcSunos0OlgNrgXY46gv3Sim3uXsjKeVvFFyXQLtm/vMl0N/d6weK0OW/gotaSqSmBjV6kIFclJSPyutWYLfnEuLa0jmItgjIHhBXoN3J3bRJjidczYGJCZCSUmRt8WD2AV6a+xoRqh3Gv6UDWzi+ByuQWDBxPseG/ULF/3Qy/EzDrRmG9vBeKKXcLqX8REr5sSfOwlS4Fjl1oJYKtMb8EmJjUZ22CA++Wiqgq5vzEfG7vtRSwaptAfzfltXY7LmEqHZdyK7VQG0BUABd/3WopcqPG6WLWbi3eJKSWiGEuNNvIzEKigJLU/i0XV8ShkwMesQQFGWQE0Xh+EKHWupbHailgrH2II/YWLDpRy0VTFuINm2Qmi2kHgKJIDrP61frc81SYfHEYbTB4TR2a606NgkhNvprYHomtHkzDvd/mbV/nSR79JigRg0B2U3sKlTp3IblDzzBDFk1KPd3JZj1HBSFnCVL+DD2EaYNnxJ053lRJRWEmysKf33xDQkte7Ps46Tg2yKY7wudrlkqLJ7oQrv4bRQGpHtOBrXnDCVMtcNbY4KWpw3GoqT8xEVHsnTaQk4fWUqZLh2D9oAI5B4QBVGsVUvSHy/B6n0n6afKoES0ToKiDHLhprs78O32MLaKUpcXKANMUGeeisI/i35k6ugZ1OzWlR4Gr2F44jDuL+DYaSHEWinlel8NyChEpf+JqoOCr91Z0Auiw7jvwn4eSx5GhJoL744PmvO0B7GG4SQuOpIji3/h0OBfqdEtLmjOM1gqKSdCCLpGR7Ju3g9c2L+EYh3bBc0WAd0CoACubx/Lml0RpJzPoUdwhuAzPJmwNgKewdGeoxqOhoCxwBQhxCDfD03fhLRpg6qDPK0zkhRB3Cw38s+VusjTBnIPiCvR/tRuEpOHUTXhraAWOYMaVWs8kH2A2UmvET5yRJBtoYdAogol163iuMF7S3nymCkPNJRSDpBSDsDhQCoCrYC+fhibvlEUts/5moSWvVkxeV6RjSQB3ailgqmSclL8j98IV3ODrpYKRsO9/Ny8dY0u1FL2PJVU8N4Xd5//i8TkYZQzuFrKk7fTDYBr3+IcoKaU8jygz93f/Uydbp1Ibt+bxJDLeiIGDD1EkigKxxZ8T0LL3ix6b3bwUg9BrmEAjiKnLfhFzmCtendFL2op56r3YAYSZlFLeVLDSMKhknK27rgLmCuEKAls9fnIDEBYaAid6lZh36Kl5Oz5EVu7tgF/WOohkgSo2qUtv+y0sUKGcHeQxhBUNYwTRSF78RImjZhGmS4deCJoM0/H92A+JFEU9iQv5Jv3k7izbzfaBMsWegkkXHpLhRhULeXJfhijgCeBU8Bp4Bkp5Ugp5b9Syof9NUC90zM3g+mfDyF0+PCgTDX1oJJy0jW6CqSl8c8bI4My5Q5K/6QCKNG6JTsee560PcdR33orKLYI5kpvV265tyPfdOnDHBE82bUeZlsoCqe++5GElr35+u2ZQZcaFxa3Zxhae5DbgTJSypFCiBuEEI2llKv8Nzz9E5X+JzKIailn9BTUGobGfRf20y9PLTUu4GopPaiknDysHqLxtIEI1Q4R4QG3haqH2haOukGXqCps/PInLhxYTLH2gVdL6SWoqtAhlpW7wvkl284DQR1J4Qn4fhhmI7RtG1SbLWh52ovKoIDetkCqbVgV1DytLmoYGk0PbMRmz3U4jKDYwvE92A9JgAdzDjAraSjhI0YEZxaugxqGk7joSIqvWcmJeH10ePYUTxxGEyllf+ACOPbDADzaD8OUKApbZjvUUqumfBGU6ClEBFcBkoeLWioozlOVCJ3YIqJ9u6AGEvYgdwBw5ZZta4OqlrIHeR2GK3efc6ilyo7VR4dnTwnYfhhmJuqBziS1e5i5oYFXS6lS6iKKBEBROPLVIhJa9ub7CZ8H3HnadWaLtM/mkdCyNzvmLAi4LaSUunhAQvDVUlLqJ5CouNbYailPVFL598N4AIj3y6gMhi00hI51KnPwh2Xk7PohoGopu5S6iCKdVO/ajpSdNlbLMP4T4HurMvg5e1ca9IzjyfRwssJr8HqA720PcmuSS1AUds9dyLcfJNHksW60LsqBhMHVUm47DCllohCi0PthmJ2euRnc/vkQQgPcW0pKfUy1XYmLjuTX2d9wJjOF0p3bB8x5OlNSeuG6YjZa1q7Age9TUDcuJKRNm8DZQuojonZyy70dWbAjjJ2iDK0DfG9dBRKKwslvf2TGmBnc1P0/3G8wtZRHm1JLKbcD2/00FkNTf/eGoKil7KrUz4dB4/6sv3hqrqaWemdswJynKnUUVWv0lodoOvVVhLRDeODUUqrU1/siJETQOaoKW75aTNb+n4gIoFpKb4FExY6x/JFu4+jujdw/dqwjRWcQx3FNhyGE+O/V/p5vf+4iS2jbNmSPtJGbk0NoeOA2fddVDUOj+sbVQdmJz67qQxXkinJgE2H2XESAbeEUQ+iJ7jkZ1Eocik21w9jA7cSnx0CirzhEp49eRko7IoCBhLe4U/QurX01Ap7lYvPBZ4A6/huawVAUNs36ioSWvVkz7cuARk96qmEAQVNLqToq9Dop1qEd9iCopfRW2wK4dXtw1FJ6DCRiM7c6ZNd2fexK6C7XdBhSyjellG8CFbi0+eAdQHV3bySEmC6EOCqE2OxybIQQ4qAQYr32Fefyt6FCiF1CiB1CiE6e/bOCQ/QDXZjT5qGAqqVUHdYwUBQyv/qOhJa9+fH9OQHM2+vvIYmi8NukZBJa9iY9aWHAbOGobenLFiFBUkvpMZAoG9cRe5iN3JAQR6rSIMVvb5oPZgO1PHj9TKBzAccnSCljtK8fAIQQdYCeQF3tNRM1Sa+uCQ8LoUOdKhxd/Au5YwKzE59dh9NtgBu6tmfJPY/zx+6/YezYgNhCb3l7J416dmVKix7MD68RsHvqSiXlRFFIn7uQhJa9+d+k5CIfSPz4/ucktOjNkQXfGyIdBZ4VvT8HVgkhFuBYi3EfMMvdF0splwsharl5+j1AspQyC9grhNgFNAZ0v8qllz2DurOHOKbdY/yvlnJozHX2YdDoF3qYexNeCFie1q7qSxnkpEwJG81vrsBfi5Yi1y9ABEAtpceoGuC2ezvy2PZQdoeUpVWA7qnXQOKOnl15eX8JyhS7gaeDPRg38aT54BjgMeAkjgaEj0kpx/pgDM9re4RPF0KU045VAw64nJOhHbsMIcRTQog1Qog1x44d88FwvCNmz4aA5mn1qJJy0v7ItoDmaaWUhAa5a++VeEQe4v0pr8IbbwRkha8exRDgUEt1iYrkVMpyskcFaBau00CixvUliK5Wht3f/hywWbi3XPPjJVwsLaVcJ6X8QPv6s6BzPGQScBMQA2QC7zkvWcC5sqALSCknSykbSSkbVaxYsZDD8B1hAe4tpcsahkaF/3QkN8yGPUB5Wruqz4ckQLMDmwPqPFUdFnqddM/JYGbiUMJGBKbDs54DicdCMnnzw5eQr79uiFYh7pjxFyHEC0KIG1wPCiHChRBthRCzgD6FubmU8oiU0i6lVIEpONJO4JhRuCZ8qwOHCnOPgKMobJjpUEutm+5/tZQuVVIaolkzvn57Jgkte3Pqux8DkIbR70OyeMd2jiJngAIJvda2AG7bEVi1lJ4DibaHjaWWcsdhdAbsODZLOiSE2CqE2Auk4+hcO0FKObMwNxdCRLr8eh/gVFB9C/QUQkQIIW4EagOGaaNe78HObLwphiPfLi6yqQcnDXrE8UnT7iwqWcvv93IUN/1+m8KhKPxv0lwSWvZmz9xvAlLD0OvbIqRNG9QAqqX0HEgYTS11zaK3lPICjtbmE4UQNhzy2vNSylOe3EgIMReIBSoIITKA4UCsECIGR7ppHzhqP1LKLUKIL3Ds5JcL9JdS2j25XzCJWL2K6YlDCcnJQS6civBjsdcu9dG2+UrcVqU0/zm7j7C3F8HAR/36oNRrcdPJHT278vTuCGREDQb7+V6qHlVSThSFnYkL+OGjuTR74n5aBEIAoONAYtGEz9n9xSIeG/YYFXWulvK0NUgOjlqDx0gpexVweNpVzh8DjCnMvYJOaiphuY6Vzmp2NsKPq3v1HEkCiBUrmDD1VUR2NvKnWf51njpOPQCUKxnOoxyi3AcLkNc9hmjWzG/30nNUDXB7t068t2Qnty5aAjdXLNqBRI84BhwowfXFb+CJYA/mGujV7xqb2FhEhGPKnRsa5tdppqpjlRSgOc8cwqSK9HOOVkp97P9wRdLSGJbwAo8vno5s196v6Uq7TmW1TkJXruCzWYPp+uUkpJ+LvXoPJGpVKEm3C/uJePdtUxS989AK3cX9NRjToCiIlBR+6v4cTzw6jpzGTfx2K73XMIiNBa1NSE6If52nXYf9ky4hNZXQgDlPnb8vUlOxWYGEg7Q0xn/6X3p9NwVV50optx2GEOIlHOmoXUKIbUKI5/03LBOgKIS/Pozl5WuTtvu4325jV3X+YdCc5+99XuLhnmM4Ue8Ov93KCM5ThIdjDwklJzQM2dp/jb51udLbldhYCNAs3AiBhHMWTpa+lVLurMN4XwjxKPAScLuUshrQCqgjhBjl7wEamVa3VKTZ0Z2ce3O036IGPe2sdkUUhfKjh7Om6m0s3nLYb7fRvcNQFEhJYdPTA3iox2i21Yry2630th/GZWiBxLKHn6fPQ2M5f0fja7+mkOj+faEFErkhIeT42Xl6izszjF+Bm3Goo/4QQqwD3gF245C+lvXj+AxNsTWrmJk4lPZzP/ZbnlbPentX6la9jrizewkdP85vzlPVuWIMAEWhxtsjEQL+HjbCf7ZQ9btYLQ9FodTw10mrfAupO4767Ta6dxhaILGq78v06jGazDoxwR7RFXGnW+0CKeUbwAocPZ7a4+ghlQtcD6RqvZ4s8qOppfyZp9V9JKkhVqzgg6kD6bbgM/85T72nHjTKb1pHUnI8zWd94Ddb6P4hqdH4xuuJPb6LnNH+axNilECi8rg3WVftdn7c5L9ZuLd4EoP0B+bgaN/RAIgCNkkpY7D2xSiYS9RSNr9MNR0qKZ9f1vcEQC2ly66kBZGais2eQ6jrpko+xq5zWa2TsFUrmTx7CHF+VEsZJZC4qWIp7rvwFxHvjNdt4duT5oPpQBNgPlAc2IhjdTZSyuyrvLToouVpf+j+HE89Oo5cP6iljBJJBkItZSRbiIgIRyAR5p9AwhC1LQiIWsowgURaGm9/OoAe303xu9S4sHi6cC8b+F77snAHRSG8dC1S56xj5d4TNL+5gk8vb9dxL6lL0Jznb599wSdqdabUvwNfF79UFX2vSXGi2WL+27P5vXoUHzZtWmC3TW/QvUrKiVMtdSELNTSM8KIcSGizcCFV1Cz/LvgtLHovi5mC2FsroRzdydkRo3weNUgdd6u9DEXh+tHDWV31NpZsPeLzy9t1vur9EhSFnEGD+a5kLXYeOevzy6s63iflEjTnufSh5+n78FguNPK9WsowgYRTLSX0q5ayHEYAKLZmFbMSh9IuyfdqKaOopJxEVytDp3/2IMb5vv+/NJgtOkVVoeGhbRx7bYTPbWGYhySAolDijXj+qHQLy3f6fk8bwwQSmlpq5WMv06vnaI7WbRDsEV2G5TACgR/VUoaZbmuIFSv4eNog7vva92opvbeAyE+lzX8yNzkeZeb7Pt8LQdcN9wpAuak8rY6n+2VTJV03YsyPolDprRGsq3o7P27Wn1rKQG8pA+NHtZRqsIckqamE2f1T5FT13gIiPy5qKV/bwm6wQMK2aiVTZw+h8xcTfR5IGC2oql25NHef+4twHaqlPCp6WxQSLU/7/fuJLCxzC1ObNCXUR5fW8457BeJUS13Iwh4SRoQvnadRlEFOnGqpC1nIMBs2n9rCGLLaPFJTseXmOgq+Pu7wbDdaIJGWxnuTBzg6PC/2b4dnT7EcRqBQFMJK1uKXpHWs2nsC5abyPrmsYdQwTjTn+b9Pv2Ai1Zka04gyPrq03ttYX4Zmiy/Gz2ZlzWg+8OFDwVBpGPCrWsowEmMnOlZLWSmpANLmtoo0PbLDp2opw6hhXFEUyo56A7sqOTDwdZ/Zwq4aY9X7JSgK2QMH8U3xmuw6esZnlzXcbEtznkt69ufxh8eSdafv1FJ2vW8BkB/XNUs6U0tZDiOAlFi7mtlJr9Em8SOf5WkNF1VrxGRsI2lePLdPfMdnBV+HSsoHgwswXaIjaXhoG0eHjvCh8zRW3h4ARaH4G/H8VukWfkv/22eXNUr7nDw055nW9yUe6jmaY1ENgz2iPAz48TIwLmopX7WEcBR6vR9aoBG//kq4jwu+hnxIApW3ONRSTWb4Ti0ljVbD0Gh+cwVaHNvJhZG+U0sZohFjfgv5cXUAACAASURBVBSFim+NQErIGOS7Wbi3GM2MxsYPainDqaScxMZCuKM9ht1H7TEM0wIiP35QSxltfY6T8NUrmT5nKJ3mfeLTWbgRPyO37tlM0rx46n32ns9l14UlYA5DCDFdCHFUCLHZ5dj1QoifhRDp2vdy2nEhhPhQCLFLCLFRCKGfOZk3aFPN7x54lmf6jkdt0tTrSxr1w4CiwNKlTOnQl7cHfuyTop7hlEFOYmPBx72l9L7X+xXxw5olu0EDCX/Mwr0lkDOMmUDnfMeGAClSytpAivY7QBegtvb1FDApQGP0P4pC6LDXSCl3E2v+Oun15YwaSQKENG/GsecHMFOtypkLOV5fz1HP8cHAAo2iEJKSQvJdTzLomQTfOE+jqaScXDIL903B16jpOX/Mwr0lYA5DSrkcOJHv8D049tZA+36vy/HZ0sEKoKwQIjIwI/U/bW+rRJPDO/hn+Eivp5mqijEjSY2u9aoQtX8L+we+4bUtjFrDAEBRyBo4mAXFbmDv3/96fTnDzra0WfjiHs/R75Fx5Pigw7PdKFsA5EdREClLmdH5cUa98qEupLXBrmFUllJmAmjfK2nHqwEHXM7L0I5dhhDiKSHEGiHEmmPHfN+Hxh+UWreaz+e+Ruwc79VSRlVJOWmQsZ2kefHcNvFtr/O00mgLtPLRJaoKDQ9u4/DQ4UXeeUa8Hs+/Wbk+kV0bNm0LiGbNOPXSAD6nKsfPZgV7OEF3GFeioP9dWdCJUsrJUspGUspGFStW9POwfIQP1VJG/jAAhCzX8rSq93lao2yUcyWqblvP3HnxNJ42wQfO09i2aHk8ncTkeGp+MM5rW6hG2QLgCsRFRxKTsY2MQd7Pwr0l2A7jiDPVpH13buybAdRwOa86cCjAY/MfPlRL2VVjR9XExiJ9lKdVDVzPAXyqljJybQsg4rf/Ea76JpAwXPucfNTZt4WkefFEffpu0NVSwXYY3wJ9tJ/7AN+4HH9UU0s1BU47U1emQMvTfnv/Mzz72NteqaWMHkmiKIilS5ncoS/vDfrEqzytIVe9u+JDtZThFqvlx2W1s2rzMqgyuPPUk1oqkLLauUAacKsQIkMI0Q8YB3QQQqQDHbTfAX4A9gC7gCnAc4EaZ8BQFEJee40T/2aROaTwU02jfxjAoZY62v+/TFcj+Tcrt9DXUaWB9oAoCE0tNfc/TzL0Oe/UUoZcrOaKopC75Gc+in2Uz16f7JUtpBkCCZ2opQLWfFBK2esKf2pXwLkS6O/fEQWfDqf30Cl5GBFqLnz8HhSiK6VhF+7lo0tUFTZ++SN/DVxOnV53F+oBYfQaBgCKwvlXKzH/h+28ePwcN5QvUajLGL22BRDRsgV7nyzJ/9KP8ZRdJayQHtBwvaTyo6mlpo2aweEGTRgeRLWUkWMQw1My7TfC7bmEeJGnNax8Mh+NMneQNC+eWz8pvFrKsCu989ElKpKGB7eROdSLmadJAom46EhuTN/oVcHX6DUMcKilTr44gNlU5eS/2UEbh+UwgklsLFLL00pbeKGmmobrSnoFQpf/6ij4euM8TfKQrLFjA3PnxdNoauHVUoZdrJaPNid3kZgcT433xxY+kDC4SspJ1+hI6h/YyoEg9payHEYwURSyflrCB60fYdaoqYVOwxi9hgFcWuQsZJ5WlZjDFj5QS9kN2rk3P75QS5khPQcQtd+hlqo7KXhqKWsDpSBTMrYlW/cVY/vhM/QtRHFOGl0N40RRYGkKn46YxvnmLRhYGOdp1P5J+XGqpbzYic8sD8m8QCIrG2GzEVoIW5hBGAIX1VIhWiARjI2VTBCDGJ+46Egqb1lH5hDPV/iaJZIECG3ejCP9X2GavQrnsj1XS0mDr3rPQ1NLJXZ9gmH93y/UQ0E1+vocJ4pC7uKf+TD2UaYMn1I4W0hjt8/JQwdqKZM8aoxNpzN7SUweRpV3x3g81TRNJKnRJboKdfYVrreUWQq9ACgK5wYMYtfRM5x+402PbWGW2hZARKsW7O73AlNzK2NXC2z4cFVUo6uknGhqqakdH2PcAN90ePYUy2HogFKFVEtJKU1T3HTS5PBOkpLjqf3x+EI4T5NE1Rr3XdhPYvIwSo8Z6bEt7GaZbWnERUdyw44NhVJLmSmoEs2aceLFAcwiktPnve/w7CmWw9ADhVRLOYMts3wYQFNLFaLIqWrGMJG/oMqfK/ICCU96jjkDCVPUtjTandpFYvIwqk94yyPnKaU0XSDRJaoK0fu3st8HjRk9xXIYekBRuPDjEt5v/QhzRk9ze6rpnJ6bpYYBFLolhCo1W5joIUlsLKrTFuGeBxJmKPQ6Kfb7b4SruR4HEjIvqPLf2AJNTMY2kubFU2fiOwFXS5npUWNoSrVpyeZHn2NybmWkdC9P63xImimSRFGQPy/l03Z9eH/IJPedp2YLM0WSKAp/L/iehJa9WfTebLdt4XxfmMkUxMaCzfNAwm7CQCKYvaUsh6Ej4qIjqbR5ndv7IeRF1aZ6MkBYi+YcfPYV1vx1kpzRY9yyhTRheg4gsktbUrs9wUzp/v5hzpmn2Zxn9mLHmqXpI9xXS6lmDCSCqJay1mHoiC5n9nKXs7fUh+9es7eUasLptpOeuRnc8vkQQlU7vDXmmrawm7CG4aRrvUhSpi/kn8MpXNelwzUflmZ1nsVbt2Tn48X5c/8p+rm5eltVHd9NZQtNLTXlzWmcbNyM1wKolrJmGDqi9IrfPVJLXXxImujDoBGV/ic2ey4hqt2tgq9ZZ1sA957/i8TkYZQa86ZbOWszpmGcxEVHUn37eg4Odk8tZcr0HA611LHnB7B+/2kujBodsDqG5TD0hIdqKSnN6zBC27ZBtdkctnCj4OuMJE1Vz9GotmGVR2qpi7WtAAwuwHQ4vYfE5GFUS3BPLWU3cSDRPecAs5KGEj5iRMCK35bD0BOKwrkfFjOh1SMkvnVttdRFlZT5PgwoCls//5qElr1ZOeWLa9riokoqEIMLMC5qKfecp3nfFyX+cKil3J2FSxMHErdsX+vRLNwXWDUMnXFd21Zs3BvBohPn6H2N3lJmrmEA1L2/M323h3EwtCLX2pPQlCopJ4rCka8XkTR+NnUeupv/XNN5Or6bceZJbCzSFk5udjbCFn7N3lJ2EwcSIW3aYLeFk5uTTWh4OCIAxW9rhqFDukZHUn7jWo68NuKq00xTKkBcsIWG0KlOFf5eknpNtZRq4vQcQPW4diy7rx+z3FBLmVIl5cSlw/PMkddWS5n6M6Io7Jq7kISWvfnfpOSAtAqxZhg6JO7sPu5xqqU+eOeKCiFTLlbLR097Bre5oZYypRomH3HRkaTO+ob/b+/M46Mqzz3+/SUhLGETcEEFabW2LigKtQwVm4iiQG+1rQtUVLr39mNvW9vb6u1mr9W2ty2tt1qX1gWty1XcQAQXMFYrCBhAVESsK4JLFdtqq4Tw3D/OmTAZJjAjyZyTeZ/v5zOfmXnPJOebN2fO8y7Pe84/1s+nz7FHtXuCsAqd6M1SVz+WVc/35LGX/sZnt5MttbmCE0MAPnj8eKY9Wc3T6s8RZdif9zBSSN+Hi8uWquQsqSwHPb28qHHaLVlSZZQrM5965wWuvf571P3knG1OclZyllSWSQftxu6rlrH+rG1nS1X08BxRz2nCgYN5c8GfePfc4tYs7dD+OvW3F4mk5yStlLRc0tK4bICkeyStiZ93StqzbBSZLdWab1+pTUmKz5bKBs9KnNzMsuejxWVLVfpJEmD836IrPA/+1bazpVoCaEic1LyWGdeeTbdzftTp2VJpqsYGMxthZqPi92cB883sA8D8+H0YZDK8PWcevz7iVK4//4p2hx4qebFaK5kMK2fczPSxU1n6h5u2MQwTPVdyq7rYbKnNlTyHEVNX5BWeNwfQkPjQ6vJlS6UpYORzHDAjfj0DOD5Bl7LTb9zHWD71Kyz8y+vY+ecXbDVU8mK1XIafMIE/NnyG66v3aPczW7KkymWVAJkMr9w8m+ljpzL3N39sN3hW6mK1NhTZCw9hnq+qoYHqHt2huhpKuEjleyEtk94G3C3JgEvN7DJgVzNbD2Bm6yXtUugHJX0J+BLA0KFDy+VbFk5jHUdceiZYS3Qg5E34VuTFBwtQW1PF+AN24+W5C9j09Bxqjjxyq5NlpWdJZdlz0lHcs7obS62Wie18pqLX52TJZHhn3t1c8uPLGThpPJ9tN3hGz5XekND8+VHPor6+U7Ol0hIwPmpm6+KgcI+kJ4v9wTi4XAYwatSo0m/HlWIOX/s43Vo2IcsZs24TMKLnSm49ZZmyaS37X3NW1O0+b+tsqUrPhsll4vDBPHDNLN5ady+9C2RLZY+LSm9I9K4fyxPP9aDm4UVMO/981NCwVV2EkBgCRH93GdJqUxF3zWxd/PwqcCtwGPCKpMEA8fOryRkmQ90xR9FS0/6EbxBzGDEHP7Nim+O0lXgPiPb49MYoW6rXT84pOMkZwjBMlqm2jgv+8G344Q8L1kUlXz4nCRIPGJLqJPXJvgbGA48Bs4DT44+dDtyejGGCZDLcd9F1TB87ledvnNX+MEwAJ8ma7WRLhRQ8hz66ZJvZUkHMYcSMeXFl1AtvKdyQqORrSSVB4gED2BV4UNIKYDEwx8zmAT8Djpa0Bjg6fh8cIydP4pIxJ3FL963nZ0JYrNZKJsOKq6JsqabLt86WCmUOA9hutlRFr/TOo8fR47bZC9/yHSm/WyWS+ByGmT0DHFyg/HVgXPmN0sXOfbpz2PsG8Ozse2HpzW0mtUJYrJbLQScey+eerOHVmt0YmbctqICRybBu5mz+7xfXMHzqcUzIC56Vej+MgmQyPHjJDTwy41aO/+Yp7BtyQ6IMJB4wnO1zOuupv/ibmLWgnGyplkCypLJ0r6nm6P135eV5C9j01BxqjmzICZ7RZ0IZehg6aRx3ra7hrafXMOGnP23TkKjIe71vg1GTJ/GVv9TSUjuEs/O2ecDoWDxgdAHGriucLWUBTW5mmdLyEgdeHV9b6ryc4Nm6QCthwTIhiS9Uv8zx08/YqiERSrp1ln69uvHRfQbx3B33YstvbZMtFUSKcRkJpA3Stemdky2VuzCnJaQ5jJhDno2uLaW8bCkLcHJz3KurCk74hpQlleVUW8dvfr91ttSWFOME5SoIDxhdgUyG+RdG2VIv3jRrqzmMil6UlEfNkUcWzJYKJt8+h50/fgybarrRUtW2IRHCtaTyGfPiY9sOngE1JDqTgE41XZtRkydy8ZiTuKX7Xq1lIS1WayWTYdkVM5k+dirLr5y51RxGSHWhMWO4+edXMX3sVN6cPXerYZiQGhI9xxfOlgryO9KJ+BxGF2GXvj348F4DeHb2PbBkZpRaOegDQHitp4NPmsDnn+rG69WDOSQuC2ntQS6HnDyR773Sh917D+OUuCzIid5Mhgcuvp6mq2/j02dOZe9s8AyxLjoRDxhdiNO1jiN/tyVbqu7KmUB4J8ke3aoZt98urL9rAS2r74gugT5oHyCMtQe57De4D+8bVMdTt90NC/4adENi5ORJfPkv3dlcO6T10tZbUowT06ooPGB0IY5Y90SbbKm+D/8ZascE2Xqa0vISB1/13fjaUrXUXXETEF5LMsqWWs+nfnlG8A2JnepqGbP3QF6Ycy+27BbU0EDLwKghEVrw7CwCGuXs+vQ5Ns6Wiic53/jwGCC8kyTAyGdXtMmW6rf4ISC8kyTAUa8+2WbCt+/DfwbCPC5OYx2/uvRbrdlSvZsWA+GkGHc2HjC6EpkM9/z2WqYfPpW1M2fz5sHRvaZCbD11G9c2W+qNUVHwDLEudvm3bLZUdD+EDQE3JD6avcJzS9uGRIjHRWfgAaOLMXLyRH6XOYnbegwNbrFaGzIZmi6/ieljp/LoVTez4eDoYiEhniQ1Zgwzf34l08dO5e93zGNDwA2JXnnZUtmGRIBV0Sl4wOhiDO7XkyktL1E3/Zf0W74ECPPEADDi5Iks23sE62fNo++yqC5CDBgAI06ayEWjT2RO72E5K70TlkqCTIb7L76e6WOn8uwNt/NGwA2JzsAnvbsaCxdy7m+/Dhs3YvdezaEnnkuVjkjaKhF6LF3MjGvPpqq5Gc28LKqLqrFJayXCAbv3ZeJbz1L98zn0/eQEoCrYhsSoyZP49790R92HMNzTajsUDxhdjcZGqjc1I9vMpuaNjH5hZbhfhsZGajZtoso209LczOgXVgZ1OYxctGgRF/zhP9HGjTDnyqAbEgPqajnV1tH/glvpM+UThBw8Oxofkupq1Nej2lo2VVXRXFXDoqHDwx2fra9H3aP7QmTrIthsmMZGajY1U2ObURw8g21ILFzI93/9NT477woO++JJHPrSqnC/Ix2M9zC6GpkMzJ/Psqtu4af/3JWmPfYLt/WUyaD585nzm2uZUTss7Lqor4faWja98y7NVdUsGjqcEwKtija98I1xLzzU46KD8YDRFclk2H2/ETT9bAEQ+PhsJkNN3TCarmsCAs6GiYPng5feyP+27BF88FRtLS3vvtva8zwx5O9IB+IBo4uyR/+enNy8loFLH6LH0joYX5+0UmI0fGhnRr+ymkOfWUGPpb3gmIaklZIhk2HAkP1oujDchXtAay/80atv5dy3domCZ6h10cF4wOiqLFzIeRd9AzZupPr4m1pvnhMivR5ZwtXX/RdVzc1UfTLsuhi+Rz+O+fsz7P340rAbEpkMQ4Yfir76W7668Ea6h9yQ6EBSP+kt6VhJqyU9Lems7f9EIMTjtDW2OcqMia//HySNjXTbtMnrgihb6sLLv8OZD/yRQcdPbL2RUIgMWtnEdTd8nzMf+CM7f3JS0HXRUaQ6YEiqBi4CJgD7A1Mk7Z+sVUqIx2mprm5z85wgibOlqK6O6iTkumhspKYlakgQePCksZFuLd6Q6EjSPiR1GPC0mT0DIOkG4DjgiUSt0kA8TktjY3SCDHQIBvC6yCXbkNi40YNn3JAwr4sOQ9l7IacRSScAx5rZF+L3pwIfMbMzcj7zJeBLAEOHDh35/PPPJ+LqOKlh4UIPnlm8LopC0iNmNmp7n0t7D6NQakObCGdmlwGXAYwaNSq90c9xykUm4yfHLF4XHUqq5zCAtcCQnPd7AusScnEcxwmatAeMJcAHJL1PUi0wGZiVsJPjOE6QpHpIysw2SToDuAuoBq4ws8cT1nIcxwmSVAcMADO7E7gzaQ/HcZzQSfuQlOM4jpMSPGA4juM4RZHqdRilIuk14L0uxBgE/LUDdTqStLq5V+mk1c29SiOtXvDe3PYys52396GKChg7gqSlxSxcSYK0urlX6aTVzb1KI61e0LluPiTlOI7jFIUHDMdxHKcoPGBs4bKkBbZBWt3cq3TS6uZepZFWL+hEN5/DcBzHcYrCexiO4zhOUXjAcBzHcYrCA4bjOI5TFB4wHMdxnKLwgOE4juMUReqvVtuZSOoHHAvsQXQnv3XAXWb2ZqJiOUg6nOje5o+Z2d0Ju3yI6J7qufU1y8xWJemVS5rqK/ZJXZ1JGmRmf815P5W4zoDfW4Kpk5KOAY6nbX3dbmbzknKKvdJcZ2U7xoLtYUg6DWgC6oFeQB3QADwSb0vKa3HO6y8CFwJ9gB9JOitBr+8CNxDdNncx0c2tBFyfsFcq6yv2SWWdAa2BVNL3gVOBR4CjgelJSUn6DfB14H7gf4BfxK//Q9IFSXnFpLXOynuMmVmQD2A10L9A+U7AUwl6Lct5vQTYOX5dB6xM0OspoFuB8lpgjddXl62zJqAuft0t6WOsnXIlWV9pr7NyHmPB9jCIDsJC3cjN8bakqJK0k6SBRAsrXwMws7eBTQl6bQZ2L1A+ON6WFGmtL0hvnfWUdIikkUB1XFeYWTPQkqDXO5IOK1D+YeCdcsvkkdY6K+sxFvIcxnlAk6S7gRfjsqFEXcxzE7OCfkRdXQEmaTcze1lSb5INZN8A5ktaQ9v62gc4IzGr9NYXpLfO1rNlGOUNSYPNbH0cdJMMstOAiyX1AdbGZUOAv8fbkuRl0llnZT3Ggr40iKSdgGOIJotEdJDeZWYbEhUrgKRewK5m9myCDlVEE3259bXEzJJsYRUkDfUVe3SlOqsGupvZPxP22I2c+jKzl5P02RZpqLNyHmMh9zAwsw2S7iMnuyCNwQIgPiATPfmZ2WZgUfa9pAFJn/gk9bcCWW1pqK8Yy3lsznlOHEnd4iEVAMysJQ60iQaMOEBke4n7Snqn0P+4nEg6yMwezS+Pj/9E64syHmPBzmFIGiFpEdAI/Jw4I0PSIkmHJuh1UOzwoqTL4l5Qdtvibf1sJ3t9P+f1/pKeIsooe07SR5LyAv4q6V5Jn5fUP0GPrZA0HlgDnANMBCYBPwbWxNuS8mqQtBZYJ+luScNyNieWiizpdzmvDweeAH4FrJQ0MSmvmGWSnpZ0rqT9E3ZppezHWJKZB0k+gOXARwqUjwZWJOj1INHakP7At4HHgb3jbcsS9GrKeT0HmBC/Pgx4KEGvlcDHgWuB14HbgclAz6ScctxWAcMKlL8PWJWg1xLggPj1CfEJZ3T8Pi3H2H3AofHr9wNLE/5fLgMOJJr7fBpYAZxV6P9bZq+yHmPB9jCI0uIezi80s0VEKZlJ0dvM5pnZm2b2S6KJq3mSRlM4qysJdjezuQBmthjomaBLs5ndYWanAHsSBY6TgLWSrkvQC6Ih37UFyl8iSsdMilozexzAzGYSLZSbIemTpOcY62tmTQBm9gxQnbCPmdljZvY9M9sH+CKwC/CApIcS9CrrMRbyHMZcSXOAq9mSXTAEOA1IclWpJPUzs78BmNl9kj4N3AwMSNDr/ZJmEU2q7Smpl22Z6Evy5NeaCWVm/wJuBG6MV/Efn5hVxBXAEkk30PYYmwxcnpgVNGezyQDM7HFJ44A7gL0T9PqQpEeJ/qfDJO1k0TxjFckeY5CXcRc3lBZL+hZwRDJKQJmPsdCzpCawZUl9NrtglpndmaDTZ4Bn4p5ObvlQ4Adm9sWEvD6WV9RkZv+QtCtwgpldlJDXt+OeWCqRtB+Fj7EnEnQ6CnjNzFbklfcDzjCz8xLy2iuvaJ2ZNUsaBBxhZrck4QXR99LMku6xFiSeU/kEZTjGgg4YjuM4TvEEO4chqZ+kn0laJen1+LEqLkss2ybH60n36rpe20PS3KQdCuFepZOkm6S+kn4q6RpJU/K2/a69n3uvhDyHcSOwAGjIjuXGC4amATcRrfhO0qs+z+t09+pSXmwjPVvAiHK6tNm5e5VMit2uJMpyuxn4nKQTgM+Y2btEGZ8dSrBDUpJWm9kHS93W2bhXaaTVK95/C9HVVgtdomS0mSWSXeZepZNWN0nLzWxEzvvvEa3H+ARwj5l16JqykHsYz0v6DjDDzF4BiCdwp7El28C93GtHWAV82czW5G+QlKSbe5VOWt26S6qy6CoMmNl58aLMPwG9O3pnwc5hACcDA4lWd2+QtIFo1fcAojx+93KvHeUc2v+Ofa2MHvmcg3uVyjmk0202cGRugZnNAL4FbOzonQU7JOU4juOURshDUmm+HaR7VYAXpNfNvUonrW7l9Aq2h6HodpD7Eq30zi6t35NopfcaM/u6e7lXJbq5V+W4ldsr5IDxlJntW6BcRLeK/EACWu5VImn1ih1S6eZepZNWt3J7hTzpndbbQbpXaaTVC9Lr5l6lk1a3snqFPIcxjXTeDnIa7lUK00inF6TXbRruVSrTSKfbNMroFeyQVBal9HaQ7lUaafWC9Lq5V+mk1a1cXsEHDMdxHKc4Qp7DaBdJTUk7FMK9SiOtXpBeN/cqnbS6dYaX9zAcx3Gcogh50htove5Q64KX7PWIksa9SiOtXpBeN/cqnbS6lcsr2B6GpBHAJUA/ovvfQrTg5U3gq9n7CbuXe1Wam3tVjlvZvcwsyAewHPhIgfLRwAr3cq9KdXOvynErt1fIk951ZvZwfqFF99KuS8Ani3uVRlq9IL1u7lU6aXUrq1fIcxhzJc0hugZL9nr2Q4iuwZLkxcTcqzTS6gXpdXOv0kmrW1m9gp3DAJA0ATiOnAUvwCwzu9O93KsjSKube5VOWt3K6RV0wHAcx3GKJ9g5DEn9JP1M0ipJr8ePVXFZf/dyr0p1c6/KcSu3V7ABA7gR2AA0mNlAMxsINBClo93kXu7VAaTVzb1KJ61uZfUKdkhK0moz+2Cp2zob9yqNtHptb/9eZ6Xt2/+XhSm3V8g9jOclfSdeIQlEqyUlfZct2Qbu5V47Qlrd3Kt00upWVq+QA8bJwEDgfklvSHoDaAQGACe6l3t1AGl1c6/SSatbWb2CHZLaFpI+a2ZXJu2Rj3uVRlq9IL1u7lU6aXXrDC8PGAWQ9IKZDU3aIx/3Ko20ekF63dyrdNLq1hlewa70lvRoe5uAXdvZ1um4V2mk1QvS6+ZepZNWt3J7BRswiCrzGKKUtFwEPFR+nVbcqzTS6gXpdXOv0kmrW1m9Qg4YdwC9zWx5/gZJjeXXacW9SiOtXpBeN/cqnbS6ldXL5zAcx3Gcogg5rdZxHMcpAQ8YjuM4TlF4wHAcx3GKwgOG4ziOUxQeMBynSCT9StITkn6bU9ZT0v2SquP3JumanO01kl6TdEdO2Vt5v3eapAvb2WetpD9JCjmj0UkJfhA6ThFIej/wUTPbP2/T54BbzKwlfv82cKCknmb2L+Bo4KX3ul8z2yhpPtE1g659r7/HcToC72E4znaQ9EHgfmAvScsk1eVsPgW4Pe9H5gKT4tdTgOuL3M9XJC2PH89Kui/edFu8H8dJFA8YjrMdzGw1MAP4gZkdYmZvQzRcBLzfzJ7L+5EbgMmSegAHAQ/nbe+ZExiWA/8d7+cSMxsBfJjovszT488/Fpc5TqL4kJTjFMdwtu5JDCK6s1kbzOxRScOIehd3Fvhd/4oDAxDNYQCjcrZfACwws9nx72uRtFFSHzP7x478EY6zI3jAcJziOAB4PK/sX0CPdj4/C/glUE90TuB2PwAAAO1JREFUv4KiiIPHXsAZeZu6A+8U+3scpzPwgOE420FSH6DZzP6ZW25mGyRVS+phZvkn8yuAv5nZSkn1Re5nJPBtYKyZbc4pHwi8ZmbNO/SHOM4O4nMYjrN9DiSaRyjE3cDh+YVmttbMLihxP2cQ3Sntvnh+4w9xeQOFh7Ycp6z4xQcdZweQdAhwppmd2on7uAU4O558d5zE8B6G4+wAZraMqEdQ3Rm/P87Eus2DhZMGvIfhOI7jFIX3MBzHcZyi8IDhOI7jFIUHDMdxHKcoPGA4juM4ReEBw3EcxykKDxiO4zhOUXjAcBzHcYri/wGHzvjNt1+XaQAAAABJRU5ErkJggg==\n", - "text/plain": [ - "" - ] - }, - "metadata": {}, - "output_type": "display_data" - } - ], - "source": [ - "# Plot results.\n", - "sig = resultsi + 1j * resultsq\n", - "amp_array = np.abs(sig)\n", - "phase_array = np.angle(sig,deg=True)\n", - "for x in range(0,len(phase_array)):\n", - " if phase_array[x] <0:\n", - " phase_array[x] = phase_array[x] +360\n", - "plt.figure(1)\n", - "# plt.plot(gpts, resultsi,label=\"I value; ADC 0\")\n", - "# plt.plot(gpts, resultsq,label=\"Q value; ADC 0\")\n", - "# plt.plot(gpts, amp_array,label=\"Amplitude (DAC units); ADC 0\")\n", - "plt.plot(gpts, phase_array, label=\"Phase (degrees); ADC 0\")\n", - "plt.plot(gpts,phase_array, marker='.', linestyle=\"None\",color=\"Red\")\n", - "plt.xticks(rotation=90)\n", - "plt.title(r\"$\\phi$ vs $f$\")\n", - "plt.ylabel(r\"$\\phi$ (degrees)\")\n", - "plt.xlabel(r\"$f$ (MHz)\")\n", - "plt.legend()\n", - "plt.savefig(\"images/Phase_sweep.pdf\", dpi=350)" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### Params 3 (We zoom in on the frequency area of interest and then print out the associated phase of interest)" - ] - }, - { - "cell_type": "code", - "execution_count": 10, - "metadata": {}, - "outputs": [], - "source": [ - "sweep_cfg={\"start\":100.0075, \"step\":0.000125, \"expts\":40}\n", - "\n", - "gpts=sweep_cfg[\"start\"] + sweep_cfg[\"step\"]*np.arange(sweep_cfg[\"expts\"])\n", - "resultsi=[]\n", - "resultsq=[]\n", - "for g in gpts:\n", - " time.sleep(0.1)\n", - " config[\"pulse_freq\"]=g\n", - " prog =LoopbackProgram(soccfg, config)\n", - " (iq0,) = prog.acquire_decimated(soc, load_pulses=True,progress=False)\n", - " di0 = np.sum(iq0[0])/config[\"readout_length\"]\n", - " dq0 = np.sum(iq0[1])/config[\"readout_length\"]\n", - " resultsi.append(di0)\n", - " resultsq.append(dq0)\n", - "resultsi=np.array(resultsi)\n", - "resultsq=np.array(resultsq)" - ] - }, - { - "cell_type": "code", - "execution_count": 11, - "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "Iteration i = 0, freq_i = 100.007500 MHz, phi_i = 355.168452 degrees\n", - "Iteration i = 1, freq_i = 100.007625 MHz, phi_i = 344.942773 degrees\n", - "Iteration i = 2, freq_i = 100.007750 MHz, phi_i = 334.561054 degrees\n", - "Iteration i = 3, freq_i = 100.007875 MHz, phi_i = 324.265874 degrees\n", - "Iteration i = 4, freq_i = 100.008000 MHz, phi_i = 313.901978 degrees\n", - "Iteration i = 5, freq_i = 100.008125 MHz, phi_i = 303.607619 degrees\n", - "Iteration i = 6, freq_i = 100.008250 MHz, phi_i = 293.346924 degrees\n", - "Iteration i = 7, freq_i = 100.008375 MHz, phi_i = 282.962804 degrees\n", - "Iteration i = 8, freq_i = 100.008500 MHz, phi_i = 272.687116 degrees\n", - "Iteration i = 9, freq_i = 100.008625 MHz, phi_i = 262.384146 degrees\n", - "Iteration i = 10, freq_i = 100.008750 MHz, phi_i = 252.026269 degrees\n", - "Iteration i = 11, freq_i = 100.008875 MHz, phi_i = 241.732993 degrees\n", - "Iteration i = 12, freq_i = 100.009000 MHz, phi_i = 231.350591 degrees\n", - "Iteration i = 13, freq_i = 100.009125 MHz, phi_i = 221.087037 degrees\n", - "Iteration i = 14, freq_i = 100.009250 MHz, phi_i = 210.793508 degrees\n", - "Iteration i = 15, freq_i = 100.009375 MHz, phi_i = 200.399291 degrees\n", - "Iteration i = 16, freq_i = 100.009500 MHz, phi_i = 190.139522 degrees\n", - "Iteration i = 17, freq_i = 100.009625 MHz, phi_i = 179.734384 degrees\n", - "Iteration i = 18, freq_i = 100.009750 MHz, phi_i = 169.496957 degrees\n", - "Iteration i = 19, freq_i = 100.009875 MHz, phi_i = 159.184603 degrees\n", - "Iteration i = 20, freq_i = 100.010000 MHz, phi_i = 148.810858 degrees\n", - "Iteration i = 21, freq_i = 100.010125 MHz, phi_i = 138.574445 degrees\n", - "Iteration i = 22, freq_i = 100.010250 MHz, phi_i = 128.281286 degrees\n", - "Iteration i = 23, freq_i = 100.010375 MHz, phi_i = 117.892335 degrees\n", - "Iteration i = 24, freq_i = 100.010500 MHz, phi_i = 107.620575 degrees\n", - "Iteration i = 25, freq_i = 100.010625 MHz, phi_i = 97.225735 degrees\n", - "Iteration i = 26, freq_i = 100.010750 MHz, phi_i = 86.949832 degrees\n", - "Iteration i = 27, freq_i = 100.010875 MHz, phi_i = 76.650230 degrees\n", - "Iteration i = 28, freq_i = 100.011000 MHz, phi_i = 66.272948 degrees\n", - "Iteration i = 29, freq_i = 100.011125 MHz, phi_i = 56.004722 degrees\n", - "Iteration i = 30, freq_i = 100.011250 MHz, phi_i = 45.684729 degrees\n", - "Iteration i = 31, freq_i = 100.011375 MHz, phi_i = 35.369000 degrees\n", - "Iteration i = 32, freq_i = 100.011500 MHz, phi_i = 25.065924 degrees\n", - "Iteration i = 33, freq_i = 100.011625 MHz, phi_i = 14.665463 degrees\n", - "Iteration i = 34, freq_i = 100.011750 MHz, phi_i = 4.390865 degrees\n", - "Iteration i = 35, freq_i = 100.011875 MHz, phi_i = 354.139750 degrees\n", - "Iteration i = 36, freq_i = 100.012000 MHz, phi_i = 343.761122 degrees\n", - "Iteration i = 37, freq_i = 100.012125 MHz, phi_i = 333.467373 degrees\n", - "Iteration i = 38, freq_i = 100.012250 MHz, phi_i = 323.097440 degrees\n", - "Iteration i = 39, freq_i = 100.012375 MHz, phi_i = 312.817796 degrees\n" - ] - }, - { - "data": { - "image/png": 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WcO+cL1i8fhePNfiFKosW2uZMxsRIbiAU96XN3WIJI8HUqpLKxEFn8vyC9fxv4mx80++JzHOk2uZMxsSCDUmZCi0pSbixy4n8q+4ekvODSChEOC+AZtnmTMaUtZxgyBNPeYMljITW8JI++JzNmfKSfDyaW5e92UG3wzImoeR4qErKhqQSmbM5U1JWFu/XPJl/b6rMG2MWMPbKNrRtXNPt6IxJCDnBkHt7YcSZJYxE5/cjfj8XAo037WHI1GUMGL+IO3qdwnWdT/DEw0bGxJL1MExCat2oBm8N68zw11by8NtrWLR+J081zqH6px9bFZUxR8hLcxiWMDymeqUUnr6yLVM++Z43xr9K2tS70VA+kmZVVMYcidygd8pqbdLbg0SEP519PGPr7SUlP4iEI1VUYauiMqZUgqEwwZB6ZkjKEoaHHXdhb5KKVFHdvy+D7fty3Q7LmAqjcD9v62GYhFdQRTV6FB+Pf5mXkxvS56mFLFz7k9uRGVMhFOyFYXMYxhucKqoewOs/7uOml5bxp0mfMKTbSdzSoxnJPvudwpiDyQ2EAW9sngSWMEwRJx9XjdeHdGTknC8Ym7mOTzbs4tkT8qj92SKrojKmBNnByI6XXhmSsoRhDlA5NZnH+7fCf2JtZoybQZUhwwmH80myKipjfqNgtz2v9DBsvMGUqF/bhoyrt5eUUJCkcIhQXoBQplVRGVOU1+YwLGGYg6r9+16FVVSBJB/37qnD1j05bodlTLlRUCVlz2EY41RR+R4YzZJ/z2BOpcb0HbOArDXb3Y7MmHIhp2DS2xJG2RKRRiKSJSJficgXInKLc/w+EdkiIiucjz5F3jNcRNaJyNci0itesZoi/H4YPpxzBl3IG0M7Ubd6Ja5+YQkPz/2KYCjsdnTGuKpgSMorcxjxnPTOB25X1WUiUg1YKiLvO689qar/KHqyiDQHrgBaAPWB/4nIyaoaimPMpogTMqoy66YOjH7zS577cD17Mz9keOUfqX7+eTYZbjzJa3MYcUsYqroN2OZ8vk9EvgIaHOItFwHTVTUP2CAi64D2wKKYB2sOKj3Fx4OXnMb5+zZwxrW3kBIKEnr8YXyZmZY0jOfkBLxVVuvKHIaINAHaAJ84h4aIyEoRmSQiBRs1NAA2FXnbZg6dYEwcddryBemaT7KG0bwAmeNfIZBvQ1TGWwrmMNKTvTEdHPdWikhV4FXgVlX9GXgWOBFoTaQH8kTBqSW8XUu43vUi8pmIfLZjx44YRW1+o2tXJDUV9fnQlFTGhRvQf/zHbNqV7XZkxsRNTjBEqi/JMysixLWVIpJCJFm8pKqvAajqj6oaUtUwMIHIsBNEehSNiry9IbC1+DVV9XlVbaeq7TIyMmLbAPMrvx/mzUNGjyZlfibX/e0PrP/pF/qMWcDcVdvcjs6YuMj10G57EN8qKQEmAl+p6j+LHK9X5LRLgNXO568DV4hImog0BZoBn8YrXhMFp4IKv5/zT6vH3GGdOSGjKje9tIx7Z68urFE3JlF5abc9iG+VVEfgT8AqEVnhHLsbGCgirYkMN20EbgBQ1S9E5BXgSyIVVjdbhVT51qhWZWbc4Ofxd9cwYcEGfpm/gBFVf6RW3142IW4Skpf284b4VkktpOR5ibmHeM+DwIMxC8qUudTkJO7p25yeP2+g5VW3kRIKkv+PR0nOsioqk3i8tD0r2JPeJkbO3LiysIqKQIB3n55uQ1Qm4USGpLzzY9Q7LTXxVayK6jlpxCXPfMz6HfvdjsyYMuO1ISlLGCY2ilVRDb3nKn7Ym8MFYxcyZ8UWt6MzpkzYpLcxZcXvL5y36Aa8NawzQ6ct55bpK/hkwy7+/vvmnhr/NYkn12NzGJYwTNzUr1GJ6defzRPvfcP4D74l54OF3GtVVKYCywmGPLO0OVjCMHGW4kvirvN/x3l7vqXFVbeRbFVUpgLLCXprSMrmMIwrzti4krQiVVRvj5tGtrOQmzEVRU4gRLqHehilThgiUkVEvPM3ZGKjaBVVaioTfI25aNxHfP3DPrcjMyYqobCSlx+2HkZRIpIkIleKyFsish1YA2xzNkF6XESaxT5Mk3CKVlFlZfKXewezOzvIheMWMv3T71H9zTqTxpQruR7bPAmim8PIAv4HDAdWO4sEIiK1iBS/PCIis1R1SuzCNAmpSBVVJ2DuLZ247eUV3PXaKj76dieP1NtPlUULoWtXm98w5U7hbnseGpKKJmGcq6rB4gdVdReRlWdfdVahNeaoHFstnRevOYtn568j64U5+KaPQMP5SGoqzJtnScOUKzkBb+22B1EMSZWULI7kHGOi4UsShnRvxr+O20tyfhAJhQjnBdCsLLdDM+YABUNSXiqrjXrSW0T6O3txIyIjROQ1EWkbu9CMlzXq1wdfehqhJB95ST4ey63L3mz7vcSUHzkenMMoTZXUvc5e3J2AXsBkIrvlGVP2/H5k3jxk9Cjee+olJuTXpe/YBSz/frfbkRkD/DokZQmjZAVLjfYFnlXVOUBq2YdkjMPvJ+nuu7nopsuYcaMfVeg/fhETPlxPOGxVVMZd2U4Pw57DKNkWEXkOuByYKyJppXy/MUesTeOazB3WmXNPPY4H537F/734GT9nfggPPwyLFrkdnvGgXA/2MEqzNMgAoDfwD1Xd42ytekdswjLmt6pXTuHZP7blxUXf8dZzr5E67W40lI+kWRWViT+bwzi0HKAKMND5OgXYU+YRGXMIIsKgDk0YU38vKflBJBypogpbFZWJMy8+h1GahPEMcDa/Jox9wNNlHpExUah7YW+SilRRPfjLcez6JeB2WMZDvPgcRmmGpM5S1bYishxAVXeLiE16G3c4VVRJWVnMz/gd/91YibeeWsC4K9vQrkktt6MzHmDPYRxa0Fl0UAFEJAMIR/tmEWkkIlki8pWzDtUtzvFaIvK+iKx1/qzpHBcRGSMi60RkpT3zYX7D70fuvpvzr+vHazd1IC0licufX8yz87+1KioTcznBEMlJQorPO7U/pWnpGGAWcJyIPAgsBB4qxfvzgdtV9VQiQ1s3i0hz4C5gnqo2A+Y5XwOcDzRzPq7Hnvkwh9CyQXXeHNqJ3i3q8ug7a3jw3klk3/+AVVCZmMn22PasUIohKVV9SUSWAj0AAS5W1a9K8f5twDbn830i8hXQALgI6OqcNhmYD9zpHH9RI8uWLhaRGiJSz7mOMb9RLT2FcVe24ff/3kjXm24iJZRP6JGH8GVaBZUpe7lBb+2FAaVbGkSAdkBtVR0H/CIi7Y/kpiLSBGgDfAIcV5AEnD+PdU5rAGwq8rbNzrHi17peRD4Tkc927NhxJOGYBCIinP/T16RriGQNo3l5LJo4k5ANUZkyluPBHkZpq6T8HGWVlIhUJbLK7a2q+vOhTi3h2G/+16vq86raTlXbZWRklDYck4iKbM4UTknh8bx6DJr0Kdv35bodmUkgXtueFUqXMM5S1ZuBXIhUSVHKpUGcZdBfBV5S1decwz86DwHi/LndOb4ZaFTk7Q2BraW5n/GoYpszDRg6gCUbd9HnqYUsXPuT29GZBJETDNuQ1CEcbZWUABOBr1T1n0Veeh0Y5Hw+CJhT5PhVTrXU2cBem78wUfP7YfhwpEMHrmjfmNeHdKJm5RT+NOkT/vHu1+SHov7WNaZEuYEQlT3WwyjNcxgFVVLHOlVSlwEjSvH+jsCfgFUissI5djfwCPCKiFwLfA/0d16bC/QB1gHZwNWluJcxBzilbjXmDOnIfa9/wbisdeye9wF3VvqBY3qfZxPi5ojkBENkVEtzO4y4iiphOL2DD4GjqZJaSMnzEjjXLH6+AjdHe31jDqdyajKPXdaKvvu/o/11w0gJBQk99jC+zExLGqbUvDiHEVXCUFUVkdmqegawJsYxGRNTXbZ9gWo+omHy8wLMf24GHduf5akHsMzRywmEPLUsCJRuDmOxiJwZs0iMiZcDqqhSGROqz8DnF7N1T47bkZkKJCcYolKqt37JKE1ruxFJGt86S3WsEpGVsQrMmJgpUkWVOj+TQbcP5KttP9N3zAKy1mw/7NuNAW8+h1GaSe/zYxaFMfHm9xfOW1xEZGmRm19axtUvLOHGLify154nk2xDVOYgVNXmMA7j0hKO7RWRpaq6ooTXjKkwTsyoyuybO3L/G18y/oNv2Zf1oVVRmYPKy4+UZVdKLc2P0IqvNK1t53y84XzdF1gC3CgiM1T1sbIOzph4Sk/x8XC/0+j98warojKHlFO4Pau3eqGlaW1toK2q3q6qtxNJHhnAOcDgGMRmjCu6bPuCdM131qIKkDX+FQL59qCf+ZUXd9uD0iWMxkDRLc2CwPGqmgPklWlUxripWBXV2HAD+j+3iO93ZrsdmSknsj242x6UbkhqKpEqqYKlOy4ApolIFeDLMo/MGLcUVFHNn09q165cV7UJf3t1JX3HLOCRS0+n7+n13I7QuKxgtz2b9D4IVR0tInOBTkSe2L5RVT9zXv5DLIIzxjVFqqjOJ1JFNXTacm6euoyPv23M3+vsJW3hAuja1eY3PMirQ1JRJwxneZBTgeqqOkpEGotIe1X9NHbhGVM+NKpVmRk3+vnHu1+zZNpb6Msj0HA+kpoK82yDJq/5ddLbWwkj7vthGFNRpfiSGN7nVB7P2E1yfhAJhQgHAjB/vtuhmTgr6GF4bQ4jrvthGJMITuz/e3zpaYSSksgTH2PDDcgO5LsdlomjgjmMyjYkdVBHtR+GMQnD70fmzYPMLGZXPZF//lCV18d9xNN/aMvJx1VzOzoTB4VDUpYwDupo98MwJnH4/fj8fgYCjdf9xC3TV3DhuIXcf2ELBrRrRGTKzySqbI/OYZSmSuolETni/TCMSVQdT6rD3Fs6cdvLK7jz1VUs+nYnD9XbT+WPF1oVVYLy6hxGqRZCUdU12H4YxvzGsdXSefGas3gmax3zJ88habpVUSWy3GAIEUhL9tbSIIdNGCLyl0O9Xmx/bmM8y5ckDO3RjIvf2RupotIw4UAAycpCLGEklIKlzb029BhNeqzmfLQD/gw0cD5uBJrHLjRjKqZG/fo4VVQ+8sTHP4P12ZcbdDssU4a8uLQ5RJEwVPV+Vb0fqMOBiw+eATSM9kYiMklEtovI6iLH7hORLSKywvnoU+S14SKyTkS+FpFepWuWMS5yqqhk9Cjm/msKz+Qdy4XjPuKLrXvdjsyUkchue5YwDqX44oMBoEkp3v8C0LuE40+qamvnYy6AiDQHrgBaOO95xinpNaZi8PtJuvtuLr25P9OuO5ucQIhLnvmYKYu/Q1Xdjs4cpVyP9jBKM+n9X+BTEZlF5FmMS4DJ0b5ZVT8UkSZRnn4RMF1V84ANIrIOaA8sKkW8xpQL7ZvW4q1hnfjLK58zYvZqFq/fyaP1f6HKIquiqqiyA97sYZSmrPZBEXkb6OwculpVl5dBDENE5CrgM+B25wnyBsDiIudsdo79hohcD1wP0Lhx4zIIx5iyV7tqGv8ZfCbjP/yWzElz8E2/x6qoKrCcQMhzJbUQxZCUFCkDUNVlqvqU87G8pHNK6VngRKA1sA14ouCSJZxbYj9eVZ9X1Xaq2i4jI+MIwzAm9pKShJu6nsS/6u75dS2qvACaleV2aKaUvDokFc0cRpaIDBWRA359F5FUEekuIpOBQUdyc1X9UVVDqhoGJhAZdoJIj6JRkVMbAluP5B7GlDcNLylSRZXk49HcuuzJDhz+jabcsCqpg+sNhIhslrRVRL4UkQ3AWiIr1z6pqi8cyc1FpOhONJcABRVUrwNXiEiaiDQFmgG2jLpJDE4VVdLoUbw/5iUmhurSd8xCln63y+3ITJS8WiV12DkMVc0lsrT5MyKSQqS8NkdV95TmRiIyDegK1BGRzcBIoKuItCYy3LQRuMG55xci8gqRnfzygZtVNVSa+xlTrvn9iN/PhcDxm/YwdNpyBjy3mNt7nsyN55xIUpK3HgiraHICYU/OYZR2aZAgkbmGUlPVgSUcnniI8x8EHjySexlTkbRqVIM3h3Vi+GureOydr9nx3nxuT91G1V7n2mR4OZUbDHluaXMoZcIwxsTGMekpjBvYhouyv6Pzn28mJZRP6NGH8GVmWtIoZ1SV7EC+zWEcjjPRXSlWwRjjZSJCzx1rSNcQyRps1PTvAAAfJElEQVRG8wIsmDCTUNge9CtPAqEwYfXeXhhQioQhIrcQGY5aJyJficiQ2IVljEd17YqkpqI+H+GUFJ4M1uPKCYv58edctyMzjtxAZN84L85hRPMcxr+cB+tuAU5V1QbAOUBzERkd6wCN8RS/H+bNQ0aPJnV+Fn+49QpWbt7L+U8tYP7X292OzvDrXhheHJKKZg7jA6ANkeqoj0XkZ2AlsAq4UUSeKG3FlDHmEPz+wnmLS4lMig+ZuozB/1nCjV1O5PaeJ5Pi89Y+DOVJYcJI9d6/QTRltbOAWSJyNnAbkWGpVsDpQC1gvohUVdWTYhqpMR510rFVmX1zR+5/40vGf/Ate+Z9wPDKP1L9/PNsQtwFOR7dnhVKVyV1M/AKsIJI7+JUYJWqdhWR1FgEZ4yJSE/x8XC/0+izfwPtrr2FlFCQ0OMPWxWVC37tYXivyDTqPpWqrgXOAmYClYgMS13ivGbrGhgTB523fEG65hdWUWU99wrBUNjtsDwl18NzGKUahFPVgKq+paoPqupYZ2VZY0y8HFBFlcrYUAMGPLeILXty3I7MM7I9PCTlvVkbYyqyA6qoMrnmjitZ++N++jy1gHlf/eh2dJ5gk97GmIqjSBXV74GW9atz89RlXDv5M64/5wT+dswukhd8aJszxUiu08Pw4nMYljCMqeCa1KnCq3/uwINvfcVn094i9PIIfLY5U8x4+TkM7/WpjElA6Sk+Rl/ckgdr7cRXsDlTIADz57sdWsL5dUjKEoYxpgI79YoLSUpLIz8piTzxMTG5MXn5tjNAWSp4DiM92XsJw4akjEkkfj9JmfMIZ2YyNbUJo3fWYPazixh3ZRuOr13F7egSQm4wRHpKkif3LLGEYUyi8ftJ9vu5Fmj4xQ/cMeNz+o5ZyMP9TuOCVvXdjq7Cyw54c3tWsIRhTELr1aIuLeofw7Bpyxk6bTkff7uT+zL2krZwgVVRHSGv7ucNljCMSXgNa1bm5Rv8PPHeN3w69U305RGoVVEdsZxgiHQPTniDTXob4wkpviTuOv93/CNjN8lWRXVUcj08JBW3hCEik0Rku4isLnKsloi8LyJrnT9rOsdFRMaIyDoRWSkibeMVpzGJ7IT+v8eXnkbIqaJ6OtywsOrHRMfLQ1Lx7GG8APQuduwuYJ6qNgPmOV8DnA80cz6uB56NU4zGJDa/H5k3D0aN5rXHJvP4vlpc/PRHrNu+3+3IKoycYMiTz2BAHBOGqn4I7Cp2+CJgsvP5ZODiIsdf1IjFQA0RqRefSI1JcH4/vnvu5g+3XcHka9qzY38eF45byOzlW9yOrELIsSEp1xynqtsAnD+PdY43ADYVOW+zc8wYU4a6nJzB3GGdaVm/Ore+vIK7Xl1J3oKF8PDDsGiR2+GVS17uYZTXKqmSnojREk8UuZ7IsBWNGzeOZUzGJKS61dOZet1ZPPm/b1g0xaqoDsd6GO75sWCoyfmzYJf7zUCjIuc1BLaWdAFVfV5V26lqu4yMjJgGa0yiSvYlcUcvq6KKRk4w5MmVasH9hPE6MMj5fBAwp8jxq5xqqbOBvQVDV8aY2CleRTUm1IBf8vLdDqtcybUhqdgTkWlAV6COiGwGRgKPAK+IyLXA90B/5/S5QB9gHZANXB2vOI3xtIIqqswsZlc9kSd/qMqccQsZd2VbTq13jNvRuS4YChMMqWeHpOKWMFR14EFe6lHCuQrcHNuIjDEl8vvx+f0MBI5f9xO3vLyCi5/+iJEXtGBg+0aIeG/RvQJe3s8byu+ktzGmHOhwUh3mDuvMX15Zwd2zVrHtnUyGJG0m7dwenpwM9/JeGOD+HIYxppzLqJbG5Kvb84+G2dz0wA34Ro4k3L2HJ8tuC56K92oPwxKGMeawkpKEy/atIz0cIlnDhPPy+Gzya0RGj73DehjGGBONrl2RtFTU5yOUksJDvxzHDf9dyt7soNuRxY31MIwxJhp+P8ybh4weTWpWJn2u70fmmu30GbOAZd/vdju6uCjoYXj1OQyb9DbGRM/vj5TeAv8HtGtSiyFTlzFg/CL+1vsU/q/TCQm9dWmux4ekLGEYY45Y60Y1eGtYZ+6cuZKH5q5h+7vz+UvqNir3TMwqqpxAGLAhKWOMOSLVK6Xw7B/b8swJedz+2E2k3j+SUIJWUeV4/DkMSxjGmKMmIvTZ+TXpGqmi0rw8Fk96lXA4saqocgKRZVK8OiRlCcMYUza6dkVSI1VU4ZQUHsuty9UvLGHn/jy3IyszVlZrjDFloUgVVUpWJv1u7s+i9TvpO2Yhn24ovndaxVQwh5Ge7M0fnTbpbYwpO0WqqP5IZFJ8yNRlDJywmL+cdzJ/7nJiha6iygmGSPUlkeyzhGGMMWWqZYPqvDG0E8NfW8Xj737Nzvc/4PbUrVTpdW6FrKLKDYZIT/FmsgBLGMaYGKuWnsLYgW34/S8b6XLTTaSE8gk9+hC+zMwKlzRyAt7dCwNsDsMYEwciQu+filZRBfj43zMJVbAqqpygd7dnBUsYxph4KVZF9Y9APf408RO2/5zrdmRRyw6EqJTq3YEZSxjGmPgoVkV1xS2Xs+z73fQZs4AFa3e4HV1UcoMhKtkchjHGxEGRKqoBQJtGNbh56jKumvQpN3U9kduq7CR5wYfQtWu5nN/I8fB+3mA9DGOMi5odV405N3fi8naNWDTlTULde6D33gs9yufSIjkBm8NwnYhsFJFVIrJCRD5zjtUSkfdFZK3zZ0234zTGlL1KqT4eufR0HqixE19+EAmFCAcCMH++26H9RqSs1hJGedBNVVurajvn67uAearaDJjnfG2MSVDNr7yQpLQ08pOSyBMf/0k5nkB+2O2wDmBVUuXXRcBk5/PJwMUuxmKMiTW/n6TMeej9o5jywETu/6k6/Z9bxKZd2W5HVsjrcxjlZdJbgfdERIHnVPV54DhV3QagqttE5FhXIzTGxJ7fT4rfz3VAw1Xb+NurK+k7ZgGPXdaK3i3ruh2d5+cwykvC6KiqW52k8L6IrIn2jSJyPXA9QOPGjWMVnzEmzs4/rR4t6ldn6LRl3DhlKYM7NOHumrtJXbjAlSqqUFjJyw97uodRLoakVHWr8+d2YBbQHvhRROoBOH9uP8h7n1fVdqraLiMjI14hG2PioHHtysy4sQPXdGzKyhlvoz3Oda2KKtfjmydBOUgYIlJFRKoVfA70BFYDrwODnNMGAXPcidAY46bU5CT+fkFzHq2z29UqKq/vhQHlIGEAxwELReRz4FPgLVV9B3gEOE9E1gLnOV8bYzyq2YDfk5T+axXVeGlU+Ft/POQEIvfyclmt63MYqroeaFXC8Z1Aj/hHZIwpl/x+kubNQzOzmFGpKY9sP4bZT3/E039oy4kZVWN+exuSKgcJwxhjoub34/P7uQpotGY7f3llBReMXchDl5zGxW0axPTWOZYwysWQlDHGlFq33x3L3Fs606L+Mdz68gqefvC/BB94MGaT4QVDUjaHYYwxFVC96pWYdt3ZPHjcz1xz3/+R9Pe/E+4emwqqbJv0toRhjKnYkn1J/CF3I+nhED4NE87LY9WU2WV+n9yADUlZwjDGVHxduyJpkc2ZQskpjPw5g7+8soJf8vLL7BY2h2GT3saYRFCwOdP8+SSf04Vzcurw1Ly1rNi0h6evbMup9Y456lvYcxiWMIwxicLZnMkH3Aq0b1qLW6av4KKnP2LkBc25sn1jROSIL2/PYXggYQSDQTZv3kxubsXZN9hUPOnp6TRs2JCUlBS3QzGODifW4e1bOnPbyyu4Z9ZqfngniyFJm0k7t8cRrUNlz2F4IGFs3ryZatWq0aRJk6P67cKYg1FVdu7cyebNm2natKnb4Zgi6lRNY/LV7XntmZn0ve0GfKF8wg89RFLmvFInjZxgCF+SkOLz7s+RhJ/0zs3NpXbt2pYsTMyICLVr17ZebDmVlCRctm8d6eEQyU4V1fIXZ6GqpbpOdiBE5RSfp3+WJHzCADz9D2ziw77HyrliVVSj9x/LkGnL2ZcbjPoSucEQ6R6e8AYPDEkZY0zRKqqUc7pwbvBYnnjvG1Zv2cvTV7alZYPqh72E1zdPAo/0MNzm8/lo3bo1LVu2pH///mRnZ7Nx40ZatmwZtxhycnLo0qULodBvV/ccPHgwM2fOjFss0fjrX/9KZmZm1OdfdNFF+IuNSd933300aNCA1q1b06xZM/r168eXX35Z+HowGOSuu+6iWbNmtGzZkvbt2/P222//5tobNmzgrLPOolmzZlx++eUEAoEjb5hxj98Pw4eT1LEDN3U9iWnXnU1eMEy/Zz7mv4u/O+wQldf38wZLGHFRqVIlVqxYwerVq0lNTWX8+PFxj2HSpEn069cPny923/D5+WX3kNTQoUN55JHoVrTfs2cPy5YtY8+ePWzYsOGA12677TZWrFjB2rVrufzyy+nevTs7duwA4N5772Xbtm2sXr2a1atX88Ybb7Bv377fXP/OO+/ktttuY+3atdSsWZOJEycefQON69o3rcVbwzrhP7E2985ezROjJpM3+oGDLiuSEwx7fkjKEkacde7cmXXr1gEQCoW47rrraNGiBT179iQnJweACRMmcOaZZ9KqVSsuvfRSsrOzAZgxYwYtW7akVatWnHPOOYXXuOOOOzjzzDM5/fTTee6550q870svvcRFF10ERKp6hgwZQvPmzenbty/bt/+6meHSpUvp0qULZ5xxBr169WLbtm0ALFmyhNNPPx2/388dd9xR2Dt64YUX6N+/PxdccAE9e/YE4PHHHy+MZ+TIkYXXnjJlCu3bt6d169bccMMNhEIhQqEQgwcPpmXLlpx22mk8+eSTABx//PHs3LmTH374AYC///3vvP766yW27dVXX+WCCy7giiuuYPr06Qf9u7/88svp2bMnU6dOJTs7mwkTJjB27FjS0tIAOO644xgwYMAB71FVMjMzueyyywAYNGgQs2eX/bITxh21q6bxn8Fn8kSjbG5+4AaSR4486FpUuYEQlVK8/SPTU3MY97/xBV9u/blMr9m8/jGMvKBFVOfm5+fz9ttv07t3bwDWrl3LtGnTmDBhAgMGDODVV1/lj3/8I/369eO6664DYMSIEUycOJGhQ4cyatQo3n33XRo0aMCePXsAmDhxItWrV2fJkiXk5eXRsWNHevbseUB5ZyAQYP369TRp0gSAWbNm8fXXX7Nq1Sp+/PFHmjdvzjXXXEMwGGTo0KHMmTOHjIwMXn75Ze655x4mTZrE1VdfzfPPP0+HDh246667DmjXokWLWLlyJbVq1eK9995j7dq1fPrpp6gqF154IR9++GHh9T766CNSUlK46aabeOmll2jRogVbtmxh9erVAIXtAmjbti0fffQRl156KaNGjTro3+u0adMYOXIkxx13HJdddhnDhw8/6Llt27ZlzZo1rFu3jsaNG3PMMYd+Anjnzp3UqFGD5OTIf5WGDRuyZcuWQ77HVCxJScKlP69DwyFEw+Tn5bF88izann32AcUMOcEQdaqmuhip+zyVMNySk5ND69atgUgP49prr2Xr1q00bdq08PgZZ5zBxo0bAVi9ejUjRoxgz5497N+/n169egHQsWNHBg8ezIABA+jXrx8A7733HitXriycg9i7dy9r1649IGH89NNP1KhRo/DrDz/8kIEDB+Lz+ahfvz7du3cH4Ouvv2b16tWcd955QKT3Uq9ePfbs2cO+ffvo0KEDAFdeeSVvvvlm4fXOO+88atWqVRjPe++9R5s2bQDYv38/a9euZeXKlSxdupQzzzyz8O/k2GOP5YILLmD9+vUMHTqUvn37FvZSAI499li2bt16yL/bH3/8kXXr1tGpUydEhOTkZFavXn3Q+aHSllKWdL5VRCWggiqqQICQL5kHfzmWjClLeezSVlSvHHkYMzuQT6XUSi4H6i5PJYxoewJlrWAOo7iCoRCITIwXDEkNHjyY2bNn06pVK1544QXmO3sXjx8/nk8++YS33nqL1q1bs2LFClSVsWPHFiaVg92/+DMCJf3QU1VatGjBomLd8d27dx+yfVWqVDngGsOHD+eGG2444JyxY8cyaNAgHn744d+8//PPP+fdd9/l6aef5pVXXmHSpElA5BmaSpUO/R/05ZdfZvfu3YUJ8ueff2b69Ok88MADJZ6/fPly2rVrx0knncT333/Pvn37qFat2kGvX6dOHfbs2UN+fj7Jycls3ryZ+vXrHzImUwEVq6I6P1SXR99ZQ58xCxh7ZRvaNq5JbjBMpRRP/cj8DW8PyJVT+/bto169egSDQV566aXC499++y1nnXUWo0aNok6dOmzatIlevXrx7LPPEgxG6sm/+eYbfvnllwOuV7NmTUKhUGHSOOecc5g+fTqhUIht27aRlZUFwCmnnMKOHTsKE0YwGOSLL76gZs2aVKtWjcWLFwMccp6gV69eTJo0if379wOwZcsWtm/fTo8ePZg5c2bhfMmuXbv47rvv+OmnnwiHw1x66aWMHj2aZcuWFV7rm2++KewpDB8+nFmzZv3mftOmTeOdd95h48aNbNy4kaVLlx40vldffZX33nuPgQMHUrlyZa699lqGDRtWWPW0bds2pkyZcsB7RIRu3boV9uAmT55cOBdkEkyRKqrrzjmBGTf6EYEB4xfx/IffctK3K+n1xqSYbdBUEZT7dCkivYGnAB/wb1WNrnSmAhs9ejRnnXUWxx9/PKeddlph5c4dd9zB2rVrUVV69OhBq1atOP3009m4cSNt27ZFVcnIyChxUrZnz54sXLiQc889l0suuYTMzExOO+00Tj75ZLp06QJAamoqM2fOZNiwYezdu5f8/HxuvfVWWrRowcSJE7nuuuuoUqUKXbt2pXr1kuvWe/bsyVdffVVY4lq1alWmTJlC8+bNeeCBB+jZsyfhcJiUlBSefvppKlWqxNVXX004HAYo7IEEg0HWrVtHu3btAFi1ahUXXnjhAffauHEj33//PWeffXbhsaZNm3LMMcfwySefAPDkk08yZcoUfvnlF1q2bElmZiYZGRkAPPDAA4wYMYLmzZuTnp5OlSpVSpwrefTRR7niiisYMWIEbdq04dprr43yX9JUZG0a1+StYZ25c+ZK3pkwi5em30NaOB9enQDzSr+0SEJQ1XL7QSRJfAucAKQCnwPND3b+GWecocV9+eWXvznmRcuWLdM//vGPR/z+ffv2FX7+8MMP67Bhw8oirIN67bXXdMSIEYVf9+zZM6b3Kwv2vZaYwuGwLrvxDg1Kkiqo+nyqDz3kdlhlCvhMo/iZXN6HpNoD61R1vaoGgOmAjQccgTZt2tCtW7cSH9yLRsG8ScuWLVmwYAEjRowo4wgPlJ+fz+2331749bvvvhvT+xlzMCJCm6suwZeehvp8kJoKXbu6HZYryvuQVANgU5GvNwNnuRRLhXfNNdcc8Xsvv/xyLr/88jKM5tD69+8ft3sZc1h+PzJvHsyfH0kWXhyOovwnjJLqFw+ocxSR64HrARo3blziRVTVSiFNTGkpy3VNBeRs0ORl5X1IajPQqMjXDYEDCvNV9XlVbaeq7QomM4tKT09n586d9h/axIw6+2Gkp6e7HYoxMVXeexhLgGYi0hTYAlwBXFmaCzRs2JDNmzcXrh9kTCwU7LhnTCIr1wlDVfNFZAjwLpGKqUmq+kVprpGSkmK7oBljTBko1wkDQFXnAnPdjsMYY7yuvM9hGGOMKScsYRhjjImKJFL1kIjsAL5zO44jVAf4ye0gXODVdoN3227tLn+OV9XflpkWk1AJoyITkc9UtZ3bccSbV9sN3m27tbvisiEpY4wxUbGEYYwxJiqWMMqP590OwCVebTd4t+3W7grK5jCMMcZExXoYxhhjomIJwxhjTFQsYRhjjImKJQxjjDFRKfeLDyYaEUklskz7VlX9n4hcCXQAvgKeV9WgqwHGmIicCFxCZJ+TfGAtME1V97oaWIyJSC/gYiK7SCqRfV3mqOo7rgbmIhH5u6qOcjuOWHH+zRsC81R1Y5Hj16jqJNcCOwpWJRVnIvISkURdGdgDVAVeA3oQ+fcY5GJ4MSUiw4ALgA+APsAKYDeRBHKTqs53L7rYEZF/AScDLxLZFAwiP0iuAtaq6i1uxeYmEfleVUveJrOCE5GHgE7AMiLf8/9S1bHOa8tUta2b8R0pSxhxJiIrVfV0EUkmsilUfVUNSWQP2c9V9XSXQ4wZEVkFtHbaWxmYq6pdRaQxkd+227gcYkyIyDeqenIJxwX4RlWbuRBWXIjIzwd7Caikqgk5yuF8r7dx9vSpAUwFvlbV20RkeUX9Xrc5jPhLcoalqhHpZVR3jqcBKa5FFT8FPyDSiPwdoKrfk9htzxWR9iUcPxPIjXcwcbYHaKaqxxT7qAZsczu4GEpW1XwAVd1DpJdxjIjMAFJdjewoJGR2L+cmAmuI7CB4DzBDRNYDZwPT3QwsDv4NLBGRxcA5wKMAIpIB7HIzsBgbDDwrItX4dUiqEfCz81oiexE4HvixhNemxjmWePpWRLqo6gcAqhoCrhWRB4BL3Q3tyNmQlAtEpD6Aqm51uqvnAt+r6qfuRhZ7ItICOBVYrapr3I4nnkSkLpFJbwE2q+oPLodkYkREKgGoak4JrzVQ1S3xj+roWcJwgTN23Z4DK2Y+VQ/8Y3i57SURkd95LXEW8GrbK3K7LWHEmYj0BJ4hUk5a8FtGQ+AkIpVC77kVW6x5ue0Hk8iVQofj1bZX5HbbHEb8PQWcW7QuG0BEmgJziQzXJCpPtl1ExhzsJaBGPGOJN6+2PVHbbQkj/pL5deKzqC0kdqUQeLftVwO3A3klvDYwzrHEm1fbnpDttoQRf5OIVApNBzY5xxoRefp7omtRxYdX276EyCT/x8VfEJH74h9OXHm17QnZbpvDcIGINAcupEjFDPC6qn7pamBx4MW2i0gtIFdVs92OJd682vZEbbclDBc531SqqrvdjiXevNp2r7YbvNv2RGq3PekdZyLSWESmi8h24BPgUxHZ7hxr4m50seXVthdp9w4i7V7ihXaDd9ueqO22hBF/LwOzgHqq2sxZR6geMJvEf9Lbq20vaHddp90n4Y12g3fbnpDttiGpOBORtQdbbO5QryUCr7bdq+0G77Y9UdttVVLxt1REngEmc2Cl0CBguWtRxYdX2+7VdoN3256Q7bYeRpw5K9VeC1zEr5VCm4A3gImqWlLddkLwatu92m7wbtsTtd2WMIwxxkTFJr3LERH5vdsxuMWrbfdqu8G7ba/I7baEUb6c6XYALvJq273abvBu2ytsu21IygUi8jt+HdssWOL7dVX9ytXA4sCrbfdqu8G7bU/EdlsPI85E5E4iddgCfEpkzRkBponIXW7GFmtebbtX2w3ebXuittt6GHEmIt8ALVQ1WOx4KvBFRa3PjoZX2+7VdoN3256o7bYeRvyFgfolHK/nvJbIvNp2r7YbvNv2hGy3PbgXf7cC80RkLb8+0NOYyK5zQ1yLKj682navthu82/aEbLcNSblARJL4dV/rgiW+l6hqyNXA4sCrbfdqu8G7bU/EdlvCMMYYExWbwzDGGBMVSxjGGFMBiUh/EflCRMIi0i6K81uLyCLnPStF5PLS3tMShjHGlHMi0lVEXih2eDXQD/gwystkA1epagugN/AvEalRmjgsYRhjTAWkql+p6tfFj4uIT0QeF5ElTk/iBuf8b1R1rfP5VmA7kFGae1rCMCZKIvKEiHwpImOLHKskIh+IiM/5WkXkv0VeTxaRHSLyZpFj+4tdd7CIjDvIPVNF5EMRsRJ4E61rgb2qeiaRdauuE5GmRU8QkfZAKvBtaS5s34TGREFETgA6qmrzYi9dA7xWpFTyF6CliFRS1RzgPGDLkd5XVQMiMg+4HHjpSK9jKiYR+QRIA6oCtURkhfPSnar67kHe1hM4XUQuc76uDjQDNjjXrAf8FxikqqV6iNB6GMYchoicAnwAHC8iy0WkSpGX/wDMKfaWt4G+zucDgWlR3udGEVnhfGwQkSznpdnOfYzHqOpZqtoa+D8iCxe2dj4Oliwg8szH0CLnNlXV9wBE5BjgLWCEqi4ubTyWMIw5DGeceDJwr6q2UdVfoHBdoBNUdWOxt0wHrhCRdOB04JNir1cqkhhWAKOc+4x3fjicSeQhr38656+mAi+JbeLuXeDPIpICICIni0gV5/t1FvCiqs44kgtbwjAmOqcBnxc7VgfYU/xEVV0JNCHSu5hbwrVyivz21xr4e7HXnwIyVfUN53ohICAi1Y6uCSaRiMglIrIZ8ANviUhBr+PfwJfAMhFZDTxHZPphAHAOMLjILyytS3NPm8MwJjotgC+KHcsB0g9y/uvAP4CuQO1obyIig4Hj+e16Q2lAbrTXMYlFVecD84sdm0Wkx1D83DBwt/NR1BTn44hZwjDmMJzf7IOqml30uKrudkoY01W1+A/zSUQqVVaJSNco73MG8Fegc9HJSBGpDewovlS2MfFmQ1LGHF5LIvMIJXkP6FT8oKpuVtWnSnmfIUAtIMsZLvi3c7wbJQ9tGRNXtvigMUdBRNoAf1HVP8XwHq8Bw0t6SMuYeLIehjFHQVWXE+kR+GJxfaeyZbYlC1MeWA/DGGNMVKyHYYwxJiqWMIwxxkTFEoYxxpioWMIwxhgTFUsYxhhjomIJwxhjTFQsYRhjjInK/wPx8ia7m5Ur/gAAAABJRU5ErkJggg==\n", - "text/plain": [ - "" - ] - }, - "metadata": {}, - "output_type": "display_data" - } - ], - "source": [ - "# Plot results.\n", - "sig = resultsi + 1j * resultsq\n", - "amp_array = np.abs(sig)\n", - "phase_array = np.angle(sig,deg=True)\n", - "for x in range(0,len(phase_array)):\n", - " if phase_array[x] <0:\n", - " phase_array[x] = phase_array[x] +360\n", - " print(\"Iteration i = %d, freq_i = %f MHz, phi_i = %f degrees\" %(x,gpts[x], phase_array[x]))\n", - "plt.figure(1)\n", - "# plt.plot(gpts, resultsi,label=\"I value; ADC 0\")\n", - "# plt.plot(gpts, resultsq,label=\"Q value; ADC 0\")\n", - "# plt.plot(gpts, amp_array,label=\"Amplitude (DAC units); ADC 0\")\n", - "plt.plot(gpts, phase_array, label=\"Phase (degrees); ADC 0\")\n", - "plt.plot(gpts,phase_array, marker='.', linestyle=\"None\",color=\"Red\")\n", - "plt.xticks(rotation=90)\n", - "plt.title(r\"$\\phi$ vs $f$\")\n", - "plt.ylabel(r\"$\\phi$ (degrees)\")\n", - "plt.xlabel(r\"$f$ (MHz)\")\n", - "plt.legend()\n", - "plt.savefig(\"images/Phase_sweep.pdf\", dpi=350)" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "For example, if your cavity tone was generated with an IF of 420.9 MHz, you would look at the above table and see that freq_i = 420.9 MHz corresponds to phi_i = 308.7 degrees (that's specific to this board session, for your QICK it will be different). That value of phi_i will be used as the value of the config file parameter associated with the offset phase of the cavity pulse (the parameter is called res_phase in the demo 00_Send_recieve_pulse)." - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [] - } - ], - "metadata": { - "kernelspec": { - "display_name": "Python 3", - "language": "python", - "name": "python3" - }, - "language_info": { - "codemirror_mode": { - "name": "ipython", - "version": 3 - }, - "file_extension": ".py", - "mimetype": "text/x-python", - "name": "python", - "nbconvert_exporter": "python", - "pygments_lexer": "ipython3", - "version": "3.8.2" - } - }, - "nbformat": 4, - "nbformat_minor": 2 -} diff --git a/qick/qick_demos/06_qubit_demos.ipynb b/qick/qick_demos/06_qubit_demos.ipynb deleted file mode 100644 index bd7e2e5..0000000 --- a/qick/qick_demos/06_qubit_demos.ipynb +++ /dev/null @@ -1,1383 +0,0 @@ -{ - "cells": [ - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "#
Qubit demos - working with a real qubit\n", - "\n", - "The measurements in this notebook were used for the QICK paper https://arxiv.org/abs/2110.00557.\n", - " \n", - "**These measurements were made a while ago, and the QICK API has changed a lot in the meantime. We try to keep this demo up to date and we make sure it runs, but we cannot guarantee that it still behaves correctly when connected to a real qubit.**\n", - " \n", - "*It's recommended to look at the other demos to get an understanding of how the QICK programs in this demo work. You will learn things that you should know when writing your own programs.*\n", - "\n", - "The following collections of QICK measurement code (shared by QICK collaborators) may also be helpful:\n", - "* [Connie Miao, Schuster Lab](https://github.com/conniemiao/slab_rfsoc_expts)\n", - "* [Chao Zhou, Hatlab](https://github.com/PITT-HATLAB/Hatlab_RFSOC)\n", - "* [Sara Sussman, Houck Lab](https://github.com/sarafs1926/qick-amo)\n" - ] - }, - { - "cell_type": "code", - "execution_count": 1, - "metadata": { - "ExecuteTime": { - "end_time": "2021-09-30T07:30:23.590904Z", - "start_time": "2021-09-30T07:30:20.325164Z" - } - }, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "Populating the interactive namespace from numpy and matplotlib\n" - ] - }, - { - "data": { - "application/javascript": [ - "\n", - "try {\n", - "require(['notebook/js/codecell'], function(codecell) {\n", - " codecell.CodeCell.options_default.highlight_modes[\n", - " 'magic_text/x-csrc'] = {'reg':[/^%%pybind11/]};\n", - " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", - " Jupyter.notebook.get_cells().map(function(cell){\n", - " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", - " });\n", - "});\n", - "} catch (e) {};\n" - ] - }, - "metadata": {}, - "output_type": "display_data" - } - ], - "source": [ - "%pylab inline\n", - "from qick import *\n", - "from tqdm.notebook import tqdm" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "# Helper functions" - ] - }, - { - "cell_type": "code", - "execution_count": 2, - "metadata": { - "ExecuteTime": { - "end_time": "2021-09-30T07:30:24.080777Z", - "start_time": "2021-09-30T07:30:23.598393Z" - }, - "code_folding": [] - }, - "outputs": [], - "source": [ - "#Figure params\n", - "rcParams['figure.figsize'] = 16, 8\n", - "rcParams.update({'font.size': 22})\n", - "\n", - "#helper functions\n", - "def hist(data=None, plot=True, ran=1.0):\n", - " \n", - " ig = data[0]\n", - " qg = data[1]\n", - " ie = data[2]\n", - " qe = data[3]\n", - "\n", - " numbins = 200\n", - " \n", - " xg, yg = np.median(ig), np.median(qg)\n", - " xe, ye = np.median(ie), np.median(qe)\n", - "\n", - " if plot==True:\n", - " fig, axs = plt.subplots(nrows=1, ncols=3, figsize=(16, 4))\n", - " fig.tight_layout()\n", - "\n", - " axs[0].scatter(ig, qg, label='g', color='b', marker='*')\n", - " axs[0].scatter(ie, qe, label='e', color='r', marker='*')\n", - " axs[0].scatter(xg, yg, color='k', marker='o')\n", - " axs[0].scatter(xe, ye, color='k', marker='o')\n", - " axs[0].set_xlabel('I (a.u.)')\n", - " axs[0].set_ylabel('Q (a.u.)')\n", - " axs[0].legend(loc='upper right')\n", - " axs[0].set_title('Unrotated')\n", - " axs[0].axis('equal')\n", - " \"\"\"Compute the rotation angle\"\"\"\n", - " theta = -np.arctan2((ye-yg),(xe-xg))\n", - " \"\"\"Rotate the IQ data\"\"\"\n", - " ig_new = ig*np.cos(theta) - qg*np.sin(theta)\n", - " qg_new = ig*np.sin(theta) + qg*np.cos(theta) \n", - " ie_new = ie*np.cos(theta) - qe*np.sin(theta)\n", - " qe_new = ie*np.sin(theta) + qe*np.cos(theta)\n", - " \n", - " \"\"\"New means of each blob\"\"\"\n", - " xg, yg = np.median(ig_new), np.median(qg_new)\n", - " xe, ye = np.median(ie_new), np.median(qe_new)\n", - " \n", - " #print(xg, xe)\n", - " \n", - " xlims = [xg-ran, xg+ran]\n", - " ylims = [yg-ran, yg+ran]\n", - "\n", - " if plot==True:\n", - " axs[1].scatter(ig_new, qg_new, label='g', color='b', marker='*')\n", - " axs[1].scatter(ie_new, qe_new, label='e', color='r', marker='*')\n", - " axs[1].scatter(xg, yg, color='k', marker='o')\n", - " axs[1].scatter(xe, ye, color='k', marker='o') \n", - " axs[1].set_xlabel('I (a.u.)')\n", - " axs[1].legend(loc='lower right')\n", - " axs[1].set_title('Rotated')\n", - " axs[1].axis('equal')\n", - "\n", - " \"\"\"X and Y ranges for histogram\"\"\"\n", - " \n", - " ng, binsg, pg = axs[2].hist(ig_new, bins=numbins, range = xlims, color='b', label='g', alpha=0.5)\n", - " ne, binse, pe = axs[2].hist(ie_new, bins=numbins, range = xlims, color='r', label='e', alpha=0.5)\n", - " axs[2].set_xlabel('I(a.u.)') \n", - " \n", - " else: \n", - " ng, binsg = np.histogram(ig_new, bins=numbins, range = xlims)\n", - " ne, binse = np.histogram(ie_new, bins=numbins, range = xlims)\n", - "\n", - " \"\"\"Compute the fidelity using overlap of the histograms\"\"\"\n", - " contrast = np.abs(((np.cumsum(ng) - np.cumsum(ne)) / (0.5*ng.sum() + 0.5*ne.sum())))\n", - " tind=contrast.argmax()\n", - " threshold=binsg[tind]\n", - " fid = contrast[tind]\n", - " axs[2].set_title(f\"Fidelity = {fid*100:.2f}%\")\n", - "\n", - " return fid, threshold, theta" - ] - }, - { - "cell_type": "code", - "execution_count": 1, - "metadata": {}, - "outputs": [ - { - "data": { - "image/png": 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AQC8Fugkq5EMI+W1NQYJY1tgmBREEFfJi5gkQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAQPsCggrtW2k5MwKCCjPjqlcCBAgMnEA7QYUdj9s+bHPE/KbwQR4jhhQawwn5+jSfRj1oHC0h1bfzWgtExI5yoy/E5VKfFxlRoR1GbQgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECgzwQEFfrsgA3g5goqDOBBtUsECBCYCYG2gwqHZ0GFhmBA2p6pRktI7eJrCirE+RQsiPOdTGl9tWVy25T6E1ToRFNbAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIEOgXAUGFfjlSg7udggqDe2ztGQECBCoVaDeosOCILUvXm4IDZUGG/IIzFVRIIYW4LkGFvLh5AgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIEBgUAUGFQTmS/bsfggr9e+xsOQECBHoq0E5QYaf3bB+2Obw8qJA2OB9CqJWNjTWNwlBrk5VnFU0jKozlxltors1GY4jLZdNUgQhBhRqT/xAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIDAgAkIKgzYAe3D3RFU6MODZpMJECAwGwIzFlRYHCqI+5QPFqSwQVN5LqSQZttZrshMUKFIRRkBAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQI9LuAoEK/H8H+335Bhf4/hvaAAAECPRGYsaBC3PqSERBSWKEuiJDSCbXlxne9rr4k+DDesv6/ggr1Ht4RIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAwGAIPPLII+HOO+9s2pmVV145rLTSSk3lCghULSCoULWo/ggQIDCgAp0GFXJ5gUxkrE6lLliQq5mXm8/PpsBCyBrMi/9pmCbqs/J83w3NsjxE/XZcfMJl4YpTrmpsVvd+dHQ0jIyM1JV5Q4AAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgUC4gqFBuo4YAAQIEcgKdBBXq8wD14YDYZT5MkK9tjiCMb0A+YJBfNm3eVPWxXb5NWu7iEy7NggpXp7eFr4IKhSwKCRAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQKlAoIKpTQqCBAgQCAvMFtBhcaAQTdBhfHgRD4SMb5nggr5I2yeAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIFCNgKBCNY56IUCAwMALtBNU2PG47cM2h2+ZjZjQmqMxfJBaN4YQitrl20yO3DAZQsjXx34L24RsA7P/d9FH4ogKV6XVF74aUaGQRSEBAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAoFRAUKGURgUBAgQI5AXaDyrMz4IKrZMKRQGEuK78cu21yW/heFihvo/m+vx6BBXyPuYJECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAtUICCpU46gXAgQIDLzATAcV8gGDiDk+EsLkSAkJON9ucrSE2hK1Jqm+vi4tPVYXhhBUSC5eCRAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQLVCQgqVGepJwIECAy0QDtBhZ3es33Y5vAts5BB8+gGEaesvAguHzTID9CQ+sjGX8hCB81LTtbHuvoGje0FFZr9lBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIEpisgqDBdQcsTIEBgSAS6CSpEmjTCQZxPIYJ8WSwvmqYOKtT3nfpI6xh/PxlUaAwpxHpBhaTmlQABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBQnYCgQnWWeiJAgMBAC1QaVIgjHUxmCJrc8iGFWJkPGTQGEfJ1sW1jfSxLU2NbQYUk45UAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgUJ2AoEJ1lnoiQIDAQAu0E1TY8bjtwzaHzy8cRSHipJEU6sMEU7Ol5WLL+mXzaYexWkflbdN6Jpe5+IRLwxWnXJUqCl9HR0fDyMhIYZ1CAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgACBZgFBhWYTJQQIECBQIDAnggpZFmEs+7/JKYUOJsumDirEpceXE1SYlDRHgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIEKhKQFChKkn9ECBAYMAFOg0q1I98kHCagwWppvVrWi62mgwlpMBBvmxeDCFk/2+s1izfNr+G8f4EFfIm5gkQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAEC1QgIKlTjqBcCBAgMvEA7QYWd3rN92ObwLbOQQOuAQD5YMA43HhyYN/5SK6rvIt9frtFEaCGLJywurl93vm3+EI33Nx5UuDpf0TQ/OjoaRkZGmsoVECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIFAsIKhS7KCVAgACBBoFeBBXiKicDB/kNKAoq1JdNLldfnu9lcl5QYdLCHAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECgWgFBhWo99UaAAIGBFWgnqLDjceMjKpSNmNBc3i7X+IgJ46Ms5IMIafn8yAn5+nx5bJuvC8GICsnPKwECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECgOgFBheos9USAAIGBFug+qJAPC9QHBdoFm5eGS8gWGBtPKzQsWraOsvLxxQUVGhi9JUCAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAhUICCoUAGiLggQIDAMAu0HFeY3cLQOCzQ0LnybggrTG1GhOSQhqFDIrZAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgMC0BQYVp8VmYAAECwyPQfVAhbxRDC82BgRDyYYbYvqhN6qexbWP7fH2+n3khDsyQH5BhPKhwVeq48HV0dDSMjIwU1ikkQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBBoFhBUaDZRQoAAAQIFAtUFFWLn9QGCgtU1tMm3yAcRUnlZf5PlaVSGuEQKKwgqJD+vBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAIHqBAQVqrPUEwECBAZaYOaCCpFtqvBBnradtqnNZFChtpZsSIUUUojvBRXyruYJECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAtUICCpU46gXAgQIDLxA50GFGBYYDwrEcECWEcim4gBBMV5928k+ilunAML4eorbjJemfgUVWimpI0CAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAh0KyCo0K2c5QgQIDBkAp0FFSbDAGMpQZB5zZtIEdSPdFBMWdZHc+vcKhYHIprb1JeM921EhXoV7wgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECVQgIKlShqA8CBAgMgUB3QYWxkEIE3Y+oEHHH+5nIORR416+noEFT0bwgqNCEooAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgMG0BQYVpE+qAAAECwyHQflBhywyknRET8m5p9IT8cqkstsuXT7Vcvj7Ox37Gl49hhnzYYTyocHXjAnXvR0dHw8jISF2ZNwQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAuUCggrlNmoIECBAICcwc0GFskBCWXluo2ohhPh+qiBD1iINuZC1TmEFQYW8pXkCBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAQDUCggrVOOqFAAECAy/QflBhfocWKZBQFDaYHA2hvNOp2kzWp6yCoEK5phoCBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAwHQFBBWmK2h5AgQIDIlAJ0GFFAjI04yHA1IoIV8zlo12MP4+BQhSbSwvKkv16XVeXaPy/lL7tL6FJ14arjjl6lRc+Do6OhpGRkYK6xQSIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAg0CwgqNJsoIUCAAIECgZkKKoyl1EC2znzeIFdcWp42c3y58RBEWX+pbXxNfV98wqVh0amCCnkb8wQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgACB6QoIKkxX0PIECBAYEoFOggqRJIUB4nwtQjAxmMLETGw10S4fUojL1C2fX2SKuvyyjX3GujTF/o2okDS8EiBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgSqExBUqM5STwQIEBhogc6CCilZkKUBSqYURGgOE4wvWz4ywtR9p1WmdcT38yZWNLlNcUSFK04xokLy8kqAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQqEJAUKEKRX0QIEBgCAS6CypEmMlgQJ4phQgm8gO1yhRCiCMqTC5X3GayPt9vfj7XRS6oEFuMLyuokNcyT4AAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBCoRkBQoRpHvRAgQGDgBToLKrTHEYMEtWjCZD5hYsH6kMFEcTYTG08dUohNUqvxoEPzcoIKeVfzBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAIFqBAQVqnHUCwECBAZeoN2gwtaHzc9GL5jkSIGDfNl47XijspET0nKx7bzcwql9rqjWXb79eP/1y03GFrK5xQmGGFRYdOrVqXnh6+joaBgZGSmsU0iAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQINAsIKjQbKKEAAECBAoEphtUiF3Whwu6CSqMTYQM8v2l4EHjZucDDoIKjTreEyBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgMCgCtx0003hwx/+cNPu7bnnnmGPPfZoKldAoGoBQYWqRfVHgACBARVoN6iwzeHz6wQaQwT1YYXJ0Q3iQvm6/HL58onOs1ERFg+MEGqRh+w/+WUa+4vvU33qL46ocMUpRlSYMDVDgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgMhsGjRorBgwYKmffnABz4Qjj/++KZyBQSqFhBUqFpUfwQIEBhQgaqCCpEnBQXifAoPtFse26UpLTveXycjNIz3IKiQJL0SIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAwCAJCCoM0tHsz30RVOjP42arCRAg0HOBboIKKUjQuLFVBBXyfQsqNAp7T4AAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQLDLCCoMMxHf27su6DC3DgOtoIAAQJzXqDToEI+SJDfuRgqyNd1GlrI95Xm2+kjtY2vaf0LT7w0XHHK1fmqpvnR0dEwMjLSVK6AAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAjMVQFBhbl6ZIZnuwQVhudY21MCBAhMS6D9oMKWWRBgrHBd8xYnCvL17YQMSrqbWEc7fUw0zmZSfxefcGlYdKqgQt7GPAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAj0v4CgQv8fw37fA0GFfj+Ctp8AAQI9Emg3qLD1YfNLt6iToELsJAYQUqigtNPF7VJ9Y/t8iCG2ydcLKiQ1rwQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECAwSAKCCoN0NPtzXwQV+vO42WoCBAj0XGA6QYUUFsiHBNIOjNdliYQwVhciSPVFr40BhtR/bFu0jqI+YpmgQpmMcgIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBDoZwFBhX4+eoOx7YIKg3Ec7QUBAgRmXKDboMJUIYI0ykLcgbE2UgZF/RWVtQMiqNCOkjYECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAg0G8Cggr9dsQGb3sFFQbvmNojAgQIzIjAdIMKrTIIMazQTkgh7lgKJTT2V1beCkNQoZWOOgIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBDoVwFBhX49coOz3YIKg3Ms7QkBAgRmVKDToEI3wYEZ3YGs87hN+YCDoMJMi+ufAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBGZDQFBhNtStMy8gqJDXME+AAAECpQKdBBVSSCF2lg8GlHbeg4qibRJU6AG8VRAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIBAzwUEFXpOboUNAoIKDSDeEiBAgECxQCdBhdhD4+gFxb32trRxmwQVeutvbQQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECDQGwFBhd44W0u5gKBCuY0aAgQIEMgJdBpUyC2amx1bPD8vV1b9bBo9YarRHAQVqrfXIwECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAjMvoCgwuwfg2HfAkGFYT8D7D8BAgTaFOiXoEIKKcTdElRo8+BqRoAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIDJSCoMFCHsy93RlChLw+bjSZAgEDvBaoJKvRmu2NYYaqQQtwSIyr05nhYCwECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAj0VkBQobfe1tYsIKjQbKKEAAECBAoEeh1UGFucNJiXHyKhYLumUySoMB09yxIgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIDAXBUQVJirR2Z4tktQYXiOtT0lQIDAtARmK6gQN3qmwgqCCtM6JSxMgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAnNUQFBhjh6YIdosQYUhOth2lQABAtMR6HVQIW5rHFVhpkIKsX9BhahgIkCAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAIFBExBUGLQj2n/7I6jQf8fMFhMgQGBWBDoJKsSAQZxmMmTQCqHd9QsqtFJUR4AAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQL9KiCo0K9HbnC2W1BhcI6lPSFAgMCMCnQTVIgb1OuwQgoptLNuQYUZPWV0ToAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQKzJCCoMEvwVjshIKgwQWGGAAECBFoJdBJUyPcTgwOdhBU6bd/Juhr7FlTI65knQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAgUEREFQYlCPZv/shqNC/x86WEyBAoKcC0wkqxA1tDCukkQ/y5amsqH3a2dQmv1ysKytvXC6+T8sKKiQdrwQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECAwSAKCCoN0NPtzXwQV+vO42WoCBAj0XKCboEIKD6SNTQGB+D7V5ctalac+prtc7CetU1AhqXolQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAgUESEFQYpKPZn/siqNCfx81WEyBAoOcCnQYVUqAgv6EpIJAva3c+9TedPtK6Ul8LT7wsLDr16lRc+Do6OhpGRkYK6xQSIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAIG5KCCoMBePynBtk6DCcB1ve0uAAIGuBToJKqQgQOPKug0Z5Pvrto/8tqT+BBXyKuYJECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAYFAEBBUG5Uj2734IKvTvsbPlBAgQ6KnAXAgqVBlSiHiCCj09hayMAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBHokIKjQI2irKRUQVCilUUGAAAECeYFOggr55fLzaSSDVDYvzeRex7L5dgMJqb/G9rG8sSyuIrVPqxNUSBJeCRAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQGCQBAQVBulo9ue+CCr053Gz1QQIEOi5wEwEFeJO5MMKMaSQpqKgQapLryl4kG+bymKbsvK0vKBCkvBKgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAoMkIKgwSEezP/dFUKE/j5utJkCAQM8FehFUiDuVwgr5kEHZzqZQQr5tKovLlJWn/gQVkoRXAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIEBgkAUGFQTqa/bkvggr9edxsNQECBHou0E5Q4YXHbhe2Pmz+xLblR0uoFc5rKplo2ziTDxykunzwIJXF13zbfJuy8rTsxSdcGhadenV6W/g6OjoaRkZGCusUEiBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgACBuSggqDAXj8pwbZOgwnAdb3tLgACBrgW6CSrEldVFE6YZVKj1V9BHWSChrDwhCCokCa8ECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgMEgCggqDdDT7c18EFfrzuNlqAgQI9FxgzgQV4p43hBXqAgmpfmwsjOWUaoGJhuUEFXJAZgkQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIEBgYAQEFQbmUPbtjggq9O2hs+EECBDorUAnQYV5KRCQCws0BgXy4YKiPUl9NLbLj9CQDyKkPsrqJ8rTtmULCCokNa8ECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgMEgCggqDdDT7c18EFfrzuNlqAgQI9Fygq6BCtpX5oEFZ+KBoZ1LbWFfXR65xV0GFuPzisIKgQg7TLAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgMjMANN9wQ3vGOdzTtz/777x/i/0wEZlpAUGGmhfVPgACBARHoKqiQG1EhMsRRDYrCBUVEZUGF1E98LeprYuSEhvp8eVw2hhUEFWoS/kOAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQqFRAUKFSTp0RIEBgcAXaCSrseNz2YevD5nc0AkIUS6GEupETFo96EOvz5fF9mtJyWYNUVBdeqIUTFvdT1MfCEy8Li069emLZopnR0dEwMjJSVKWMAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECgQEBQoQBFEQECBAg0C8xUUGEibJCtMh8mKCvPb9lEm7KgwhRhB0GFvKZ5AgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgEA1AoIK1TjqhQABAgMv0HZQ4dDn141qEGFqIxtkr5PjHkxy5cMG+fqJ0RCyEEK+fHLJ8bnUdypvbFvrv6QPQYWk5pUAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgUJ2AoEJ1lnoiQIDAQAu0FVQ4druw9WHzS4MFdaGCxaMd1I2ikBPMBw7ScvmyXNOJIEQs66SNoEJe0TwBAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAoBoBQYVqHPVCgACBgReYC0GFiDxVEGGq+nwfggoDf9raQQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQGAWBAQVZgHdKgkQINCPAp0EFcr2ryhEkEZLmFgmjrQwNtYykFDUT1o+9dfYJpXHdqlOUCGpeSVAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIVCcgqFCdpZ4IECAw0AI9CSrEkMLiaSwLKxRNqUVxbQipPi6bb1NULqhQJKyMAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIDA9AUGF6flZmgABAkMjMN2gQj40kEfLBwhq5YvDCt0GFWIfqc/8OovKBBXyR8I8AQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQKAaAUGFahz1QoAAgYEXaCeo8MJjtwtbHza/2SImBlJSIFcbi/JhglxV02xavLR9wTrSMrGzouUEFZqYFRAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIEpi0gqDBtQh0QIEBgOAS6DirkEwK55ECazVeXSaa2sb60farINc7NFi4nqFAmrpwAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAg0L2AoEL3dpYkQIDAUAlMO6iQSw3kZgsDBI2wbbUvCCrEfuKyqaqxX0GFRhHvCRAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQLTFxBUmL6hHggQIDAUAp0GFVoFBFoFD1otF6HTso3hg6mWazxIsf3FJ14WFp16dWNV3fvR0dEwMjJSV+YNAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIBAuYCgQrmNGgIECBDICXQSVEhhgrh4Y6AglpXVl5XHZdJU1KaoLLUvek3tBRWKdJQRIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBKYnIKgwPT9LEyBAYGgEugkqFIUUIlgKCsT5fJuy8tguTalNfrlYV1aelmt8je0FFRpVvCdAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQITF9AUGH6hnogQIDAUAi0E1TY8djtwtaHzR8PH8QkQUoPLBZKb2shg8VJg3mpMGszUZ6VpeLFzSaNU0FqMFkzOZdrE5ult5MNxucWnnhZWHTq1Y3Fde9HR0fDyMhIXZk3BAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAEC5QKCCuU2aggQIEAgJ9BRUCGfDMgFCtLsWK6+LqhQVp7bjrrUQeqwpL6u73ybxfOCCgUoiggQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAEC0xQQVJgmoMUJECAwLALtBhW2ykZUmAgTNAQJ0tuJoEJWkMqiYy2nEP+zuDC+5LILscn4lGuTiupe00KL+09v69pkbwQVGkW8J0CAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAhMX0BQYfqGeiBAgMBQCLQTVHjhsduFrQ/Nggr59EFeJyUGcvW52eJQQn75bD61T12l6sLyfKPUIC2QvQoq5DDMEiBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQqEhBUqAhSNwQIEBh0AUGFQT/C9o8AAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgUI2AoEI1jnohQIDAwAu0HVQ4LBtRodWURjnIjXAQZ1Nxq0VTXVH7orKJTnPrSn3EVyMq5DXMEyBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgSqERBUqMZRLwQIEBh4gU6CCikXUBo+KKtIC0bN1CZfli/Pi5e1yZWn2dRtXFxQIY9ongABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBQjYCgQjWOeiFAgMDAC3QTVIgo+WDABFJhYVab0gSNC5aVpw7L6nPludmJbRJUSIBeCRAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQLVCQgqVGepJwIECAy0QCdBhSkh2gkqxE5Su5QySO+LVtDYJr3PtY1F+S4EFXI4ZgkQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECFQkIKlQEqRsCBAgMukBHQYV8GqAIJh8iyLWdlyvPFdenC3JtJrrON87qU5N8cV1CYfGCC0+6LCw69eqJbopmRkdHw8jISFGVMgIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAgQIBQYUCFEUECBAg0CwwkEGFE7OgwmmCCs1HWwkBAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAoHsBQYXu7SxJgACBoRJoO6hw6PxmlzTEQaqpG+ogFbb5OlVfU9Wn1WTtFp4gqJA4vBIgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIEqhIQVKhKUj8ECBAYcIFugwrzFgcH6rIJdW86g6vrr6iffFChqD6ubnGbhXFEhVONqNDZEdCaAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQINBaQFChtY9aAgQIEFgsMOeCClOEEGqbXdQmF2QQVHB6EyBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgSqFxBUqN5UjwQIEBhIgW6DCqUYMTBQFiQoKi/tKFdR1mdqkgspxCJBhQTjlQABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBQnYCgQnWWeiJAgMBAC7QdVDhsfnEAIa+TDwzkQwll5flly+bTsvn+8m1Tfa5MUCGHYZYAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgUJGAoEJFkLohQIDAoAu0HVQ4NAsqTDXlQwONwYJY11g2VX+xPvXZatnUZnF/ggrtwGpDgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIEOhMQFChMy+tCRAgMLQClQQVUlCgVZigTLjdAEMH66gFFU67umyNtfLR0dEwMjLSso1KAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgACBSQFBhUkLcwQIECDQQmBWgwopfBC3b6qQQwdtBRVaHHBVBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAIEuBQQVuoSzGAECBIZNYFaDChHbiArDdsrZXwIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBDoUuDKK68M22+/fdPS//Zv/xbi/0wEZlpAUGGmhfVPgACBARGoJKgwkxZpJIWpRlzIbYMRFXIYZgkQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIEBgYAQWLVoUFixY0LQ/H/jAB8Lxxx/fVK6AQNUCggpVi+qPAAECAyowp4MKKaQQ7QUVBvQMtFsECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAg0K6AoEK7UtrNlICgwkzJ6pcAAQIDJjCngwrROoYVOggpxEWMqBAVTAQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECAwaAKCCoN2RPtvfwQV+u+Y2WICBAjMisCcDyp0oSKo0AWaRQgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIEBgzgsIKsz5QzTwGyioMPCH2A4SIECgGgFBhWoc9UKAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBGZaQFBhpoX1P5WAoMJUQuoJECBAoCYgqOBEIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAEC/SEgqNAfx2mQt1JQYZCPrn0jQIBAhQKCChVi6ooAAQIECgXGxsbCgw89UKtbYoklwgrLr1jYrl8Kn3ji8fD444+HJZdcMiyxxJIzvtm9Xl+VOzT68ENhqSWXCssss2yV3eqLwEAKPP74Y+GJJ54ISy+9zIztXz9/nsTvkodGHwzLj6yQffYuMSNG8bP9gQfvq/W9ysqrhnnzZmY9M7LxOiVAgACBgRIYpGuo2fj9MRvrrOoEdA1VlaR+hkHANVTro+waqrWPWgIECBAgQIAAAQIECPS7gKBCvx/B/t9+QYX+P4b2gAABAj0REFToCbOV9ERgLPzwp98NDz30YE/W1molu77klWGlFVcO//vDb2XNxgqbrrfOU8L8LRYU1k238J///Ec478Jzs5sdHy/sarsFO4fVnrTGRN3vfv/r8Ps//nbi/UzMxJuUX/TClzXdfHn9Db8Kf7jx+mmtcsnsJujY93LLjUzRz9jiYzJFs8XVSy+9dFh2meXCsssuF1Zd5Unh6U97ZhhZbvn2Fi5o9Y9/PBx+fP73w6OPPlJQW1w0b968sEq27tVXW7P2vzVWWyuMjHS/DcVrmfnS87Pz8eLLzqutKJ57xxz53mmv9NIrLgh/v+euun7ijas77bBr5UGIsbEnQjxXr/nFonDHXbeFBx64LwspLFULK6yyyqoh/j0v2GqH8NQnb1C3Pd2+6fX6ut3OxuXuuvv2zOnX4a677xj/39/vCPHzKE4rrrBS7RxebbU1QjyPN3/288PKK63S2IX3c0rA92o6HJ1+r6blOnm9M/tsOevbX6wFoA478G1N35ed9JVv26+fJ3Efbr/j1nDjTTeEO+68bfx/mdFjjz1a+/xdY/W1wtprrhvWWnOd8IynbxzWXWf9/G63OT8W/vK3m8Ivf31NuPnWv4T7778vC0I8lC07/tsthtGetOrqtd9M8Xt442c+Ozz9qRu22Xdjs+LfICtkn40777DLjAQiLlj44/Dgg/fXbciGG2wSNt3kOXVlVb957LHHst/kZzd1G78Hds5+r5nmmoDP+nREOv2sdw2V5OpfXUPVe0znXT9fQ83G74/ZWOd0jm9a1jVUkhiUV9+r6Uh2+r2aluvk1TVUs5ZrqGaTTkpcQ3WipS0BAgQIECBAgAABAnNBQFBhLhyF4d4GQYXhPv72ngABAm0LCCq0TaXhHBeI/yj97x9+z6xv5QZP3yi8cd8jshvO5oVzf3J2WHT1wpJtmhde96oDK79ZLD4p66vf/Hxp8CAGBg478Jiw5hrrTGzXzy76Ybjo0p9OvJ+JmXhT9zuO+tfazcr5/s+74Adh4eXn54u6mn/1K94QnrPZ/CmWHQsf/NBxU7Qpr47HdN11npzdELlR2HzT54e111q3vHFBTbzR/axvn15Q01nRilkIZqftdwlbZkGXfnjS86+v/0X45tlnTuxkVUGF07/8qfDnv9440W+a2X3XV4Wt52+f3k779cabfh++94Ozwn333ztlXzGosM9eB0zrBvxer2/KnWqjQbwBIf5jbvy8i0+Db2eKNwA/b/Otwg7bvrh2I3A7y2jTWwHfq+Pe3Xyvdnqkfvu768LZ55wVHnnkn7VFN9t0i/Ca7LNkulM/fp7EfY4O52e/TeJnSvSfepqXfe5vG16y0+61cOHU7UO4Nguexd8+997393aaT7R51sabh11f/IouPrfKf4Mcddixdb/LJlY2zZlPnvY/WWjs9rpe4ihAb9z38Fr4sq6iwjfxO+FDJ72/qccYLjn68Nn/rd60YUNe4LN+/ATo5rPeNVR7fzyuodpzamzVz9dQs/H7YzbW2XjMOn3vGqpTsf5o73t1/Dh1873a6RF2DVUv5hqq3qPbd66hupWzHAECBAgQIECAAAECsyUgqDBb8tabBAQVkoRXAgQIEGgp0FZQ4d3bhq0OnV+78Tp1lm4aiv/onJ/KyvNt0nw7bdtpk/pLrwtPvCwsOu3q9LbwdXR0NHsq+VRPXy9cVOEcFZgL/xi4/PIrhrcc8q4QbySPU7xh98tf/2ztacBFbEsvvUw49I3HdHzDe1FfqeynF5wTLrn8Z+lt3Wv8e91vn4NrTwTOV/TiJpstnrt12Gv3ffOrrc33U1Ahv/ExILDtNjvWRnJYaqml81Wl81UFFdIK1l5rvfDyXfYOT3vKM1LRnHu9/Y5bwufO/ETdKBL9FFS4bNGF4Sc/Oye7Uba9m+/jAYhPjN7vNQeH9dd9asfHo9fr63gDCxa47ldX10YKeWi0u9Fs4t/S5ps+L+y1x761p6QXrELRLAn4Xh2H7+Z7td1DFn/nnn/RuWHhZec3LRJvht92m52aytst6MfPk7hv8QnlP/jJd7LRDaYOhzVarJSN0rLHrq8Om2y0WWNV0/tvnH1G+M311zWVt1MQw5fbZcfmxTu9vJ3mi9vMjaBC3Jg4AtUhB7w1C0es3cH2t99UUKF9q7nQ0mf9+FHo5rPeNVTnZ7BrqPbM+vkaajZ+f8zGOts7kuWtXEOV2/R7je/V8SPYzfdqu8feNVSzlGuoZpNuS4qCCrEv11DdilqOAAECBAgQIECAAIGZFhBUmGlh/U8lIKgwlZB6AgQIEKgJCCo4EQZFYPb/MXBeeMNrDwkbbbhpHek//vFw+OwZHwt3//3OuvL0ZpVVnhSOeNPbQww5THf65W+uDd/+3pdLu3npznuE7V/woqb6Xtxk85ZDjw1rrTk5ikPaiH4NKqTtX2P1tbOb/Y7Ogk/Lp6LS16qDCmlFW27xgrDnbvtkb+uDY6l+tl5HH34onHb6yU1Pq+6XoEIM/MR/XO9miiGkIw56e4jnR7tTr9fX7na1alflOX3c2z8Ylh9ZodXq1PVYwPdqCN1+r7ZzqOLvg29l39l/uPH6wubxZs4D9zuiqyff9+PnSUS4/MqLw4/O+26hRyeFcWSFOFpLq2k6QYXUb2cj+MydoELc/vj78/AD3xZWyMJ1VU+CClWLzmx/Puu7/6x3DdX9uekaqtyun6+hZuP3x2yss/zotVfjGqo9p35t5Xu1++/Vdo65a6hmJddQzSbTKSkLKsQ+XUNNR9ayBAgQIECAAAECBAjMlICgwkzJ6rddAUGFdqW0I0CAwJALtBVUOHa7sHU2osKsTtkTZ2tTwwgOsSw+SSk/soMRFcaphu2/s/2PgS/Yesfwspe8spA9hhRiWCH+g1rRFJ+If+DrjwxLLLFkUXVbZbfc9tfwhS99Kjz22KOF7Z+72ZbhVa94fWHdTN9ks+EGG4cD9j2icN39HlSIO/XUJ29QO37xCcutpipvSGgGTEQAAABAAElEQVRcz3YLdg67vGjPxuJZex9HEznzrFPDTX/+Q9M29ENQ4U/Zdp/5tVM7GkmhcUfjk6oPz0JIMbQw1dTr9U21Pe3U33Pv3eGUL5wU4g2pVUyCClUoVtuH79Xuv1enOhLx7+aMr54S4nd3q2nDDTbJvj8Pb9Wkqa4fP0/iTtx861/C58/8ZDYa1eNN+9R5wbywz177Z6O1bFG6aBVBhTii0pEHvzMLpa1Vup7JirkVVIjbtd46TwkH7X9U9j3V3shQk/vSek5QobXPXKv1Wd/9Z71rqOmdza6hmv36+RpqNn5/zMY6m49aZyWuoTrz6sfWvle7/16d6ni7hmoWcg3V/ECcZqXOSloFFWJPrqE689SaAAECBAgQIECAAIGZFxBUmHlja2gtIKjQ2kctAQIECCwW6LugQtzuXFghhhTSlMIKggpJZLhe4z8GnvDxf5+RnX48u2muLGQQV7juOk8Oh77xmLDkkuVBgz/+6Ybw5a9/tvTG5/Gn4r+mq+1/8KEHsifXfzTc/8B9hcuvv95Tw0FvOCostVTxjfQzfZNNvMky3mxZNLUKKkx143++v7332Dds/uzn54sK5stvEhw/dpMjEsSbROI51e4UR6qII1a0mloFFVYoGFHjn4/8szR4UrSeA1//5rDB055ZVNXzsh/+9OxwxVULC9c714MKDz88Gj5x2v8XRkcfLNz+WBj/luJTqO+//76W58n85y0Ir3j5a0v7iRW9Xl/LjWmzMn73nvbFj4Zbb7u5dImVV141rLXGOmHllVbJzuPHss+ne8PfbvlL6TldRVDhxpt+37Q9a2cjuczEE8ObVjSABb5Xu/9ebXU6xEDhl846Lfz5rze2ahY2fuazw9577NfWiD2po378PInbHn9jxeDTvff9Pe1K4esSSyyReaxQ+3zOXwMUNY4jHb3tyPeF5ZYbKaoORUGFFVdcOay+2pq10V3uu/+e2mhYU4Wx4m/Aww48po2waflvkKMOOzasmX1eVj1NdZNNXN8mG20W9n31QXWh7+lux0wHFXzWT/cI1S/vs777z3rXUGHx9a9rqPq/qu7f9es11Gz8/piNdXZ/ZMeXdA01XcH+WN73avffq62OsGuoZh3XUK6hms+K8hLXUOU2aggQIECAAAECBAj0u4CgQr8fwf7ffkGF/j+G9oAAAQI9ERBU6AmzlfS5wPkXnhsuvuy8wr1YZplla0/TjTdfTzXFG7fjzQdl0+67vipsPX/7surC8scffzyc/pVPhb/d/OfC+pWym4SPyJ7qHm++K5vuvOu2cOddd5RVT1n+SHZD/Xd/cFZhu7Wym4TfcuixhXWxsCyocMyR7w3tmJZ2XFjRyU2CY+HBhx7MbkS/N9x59+1h0VWXtHzy9bLLLhfedfS/hXg+lE1lQYV4jOKyRdPoww/VtuHmW/8aLr3igvD3e+4qalYrW3ed9cMRB70jm5+8Wai08QxW/Py6K0vPh7jauR5U+OkF54RLLv9ZoVA8VnHkiviU7hiOi+d+/Gy45PILCgMLsU28AXWN1dcu7C8W9np9pRvSQUUMKJx6+kmFS8SbbXfeYdew6SbPabrx9dFHHwm//+Nvw6KrL2m6SbuKoMIHP9T8WbPPXge0fKp64U4onHGBQf9eLQOMowV89ZtfCH+48fqyJrWbPmPwLY7U1OnUj58ncR/P+dG3w1XXXlq6u/Fm+p13eFl2M//aNZ9HH3003Hr738JPfva/pb9/YmetQoTfOPvM8Jvrf1EbDSGGRZ+7+Za1gEJ+I+INhb/45VXhvIvODQ8+eH++qm7+TVlQ8OlTBgU7+Q1S133Xb9oJKsTOt9lyh/DyXfbuej2NC850UMFnfaP43H0/6J/1rqFC7XdufdDKNVS3f5H9fA01G78/ZmOd3R7btJxrqCThtVuBQf9eLXNxDVUs4xpq9oIK8Yi4hio+L5USIECAAAECBAgQINB7AUGF3ptbY72AoEK9h3cECBAgUCLQaVCh8emlaRSDou5j26L6VuWpn6blsr7i2Am1229zIyqk9vE1bdslJ10eFp12db6qaX50dDR7ImvxE1abGisYaoE/ZU/oPvOsUyfOr0aMV+35+trNbY3lZe+//8NvhGt+fkVhdXxS8AH7HtHRU/FjQCDe1FA0LbXU0uGQA46ujfhQVF9VWasAxit3f114/nO3KV3V3A0qNG/yDX/4Tfj6d74YYjikaNrjZa8OWz1/u6KqWlk3QYV8Z/HJfFf//PLaDZ358vz8EQe9Mzve6+eLejr/t1v+HE7/8qczo8dK1zuXgwpxdJKPfea/QrwJtnGKIwMcnP09rbrKao1V4ZpfXBG+f+43mspjwWZZqOE12c3yRVOv11e0Dd2UXbbowvDj87/ftOhaa64bDt7/qNInmOcX+O3vrgs/yvq47757asWCCnmdwZ4f1u/V+Dv1m9/9Uu3m+LIjvOqqq4XX7X1gV9/b/fp5Ei1Ozj537723aDSFednn5/61z9Eis2gaw2LxqeZFU/zcfmdJEDAG/x7IRqJ62lM3LFq0riyG0mIotGwUmd1euldYsNUL65ZpfjN3gwpxW1/2kr2ycMxU+9C8V0UlggpFKsNXNqyf9Z0caddQ41quoUI26lj/XkPNxu+P2VhnJ3/bZW1dQ5XJKG9HYFi/V11DlZ8drqFmN6gQj4xrqPLzUw0BAgQIECBAgAABAr0TEFTonbU1FQsIKhS7KCVAgACBBoFOggopCJDvoilQsLgy3zbfpp3y1H87y6W28TX1vfCky8KVp12Tr2qaF1RoIlFQIDA6+mD49OdPLH2K7vM23yrsved+BUuWF8UngZ3x1VOaniaelhgZWT4cno2A8KRVV09Fpa9XXHVxNkLDd0vr483R8SbpmZzi393HT/lQuOfeu5tWs+IKK4V3HPWv2dOPl2qqSwX9FFSI23zlNZeEH/z4O2nz6163eO7WYa/d960ry7+ZblAh9RVH5Yg3NhVNL9pxt7Djdi8tqprxsgeyp02fdvpHQ3xtNc3loEJ8OnccuaJoOuSAt4anPPnpRVW1sm9//yvhl78u+u6ZF956xHvC6qut2bRsr9fXtAFdFnzlG5+rjYzQuHgcPaL+qbqNLerfP/yP0Sz8c0a46c9/CIIK9TaD+m6Yv1fLbk5Lxzp+RrzpDW8JK7UYASm1LXrt18+T+7KRiz76qf8o2qWw7TY7hV1f/IrCunzhV7/5+RDDhEXTmw95V1h7rfWKqjoqi8GGU7PvuHgTfuP0/OdtE1758tc1Fje8n9tBhXjd9bpXvSk8a+PNG7a787eCCp2bDdoSw/xZ3+6xdA01KeUaqr+voWbj98dsrHPyjO1+zjVU93bDvuQwf6+6hio++11DFY3qVGzVaWm7o9LFfl1DdaqrPQECBAgQIECAAAECMyEgqDATqvrsREBQoRMtbQkQIDDEAtMOKkS7ghEOUmhgvLo2DkJNuZ3yWsNat5PLxbK0bD7AkNrm6y/JggqLBBXyNOa7EhgLX/7658Ifbry+cOl4s/WRB78zLLPMsoX1rQpHH34onPbFk0ueHhxqN/oeduAxLfu+MRvp4UtnnZb9XTxRuKp4s3q8aX2mp9/+7pe1UQaK1vOiF74s7Lj9LkVVE2X9FlSIG/7RT//nxFPgJ3Ykm3n6054Z3vT6N+eL6uarCirEER3+52PHF94sGW8w3PfVB9Wttxdv4ggKcSSF+DTQqaa5G1QYCyd96j/D/dlNs43Tc579/PDqV+7fWFz3Pv5DcQztFI0msfMOu4adsv/VT71eX/3ap/Pufz72gRBvlshPyy03Ev7lHf8vX9TW/BNPPFELhyzYaoew9NLLtLVMWaMPfujYpqp9ssDW5jMc2GpaqYISgeH9Xr3zrtuzm9xPCo89VjzazBqrr1X7/lixy5BC9iu5x59fJYe4i+LrfnV1+M7/frVpyaWXXrr2mdIq7JgWiiOzxO/moul1rzowbLrJc4uqOi77wY+/nQUWL21abr11n1ILmTZV1BXM7aBC3NQ4EtdB+78lrL/uU+u2vNM3ggqdig1a++H9rO/kSLqGmtRyDdXP11Cz8ftjNtY5eb5OZ8411HT0hnnZ4f1edQ1Vft67hpobQYV4hFxDlZ+naggQIECAAAECBAgQ6I2AoEJvnK2lXEBQodxGDQECBAjkBDoJKuQWq5/NnqiepjQ3VZggtq+LIaSwQ66vogBEXK40sLB42TiigqBClDJNR6DVU7uWXHLJcOgbjwnrrvPkrldxx523hc+d+fHwyCP/LOxjk402q91wXvS3FEcvOO30k0N8GnnRNH6z+puyqrq/sqKm0y77/Jc+Ef76t5ua+on/UPPOo98flh9ZoakuX9CPQYWvfesL4Xe//3V+N2rzU92AX1VQIa7s82dm7jffVFtv/j/xif/xyf+9nr77g7PCz6+7sq3VTuXUVidZo9O//KnCkUl23/VVYev527fbzUS7m2/5S/jsGR+beJ+fOTALoGyQBVGmmr789c8WhpvWWnPd8JZD3123eK/XV7fyab75rxP+T3j00Ufqeok3Fb/vXf9Ve6JcXUUP3wgq9BC7i1UN6/dqHEkpfrbcetvNhWprrrF2LaSwQjYKUbdTP3+elD0Vef31nhoOO/BtbZN85OMfDA899EBT+26/E5o6ygqu/cWi8L1zv95U1V5Qa+4EFeLn9aOPPtq0H7FgheVXrLmvuupqhfXtFAoqtKM0uG2G9bO+0yPqGmpSbKprA9dQ41ZTOU2Ktp6r8hpqNn5/zMY6W4u2X+saqn0rLScFhvV71TXU5DlQNOcaqvdBBddQRWeiMgIECBAgQIAAAQIE5oKAoMJcOArDvQ2CCsN9/O09AQIE2haoMqiQQgpx5UU3V8fyFDKotYn/SVMKKsT3KayQL0vtatWTa6pbj6BCTsnsdARuue2vtRvB45Pri6aXveSV4QVb71hU1VHZDX/4TYg3vef/LvId7LDti8NLdto9X1QLNsQbHuOTxYqmtddatxaimO6TyYv6bixrdZPAlltsG/bcbZ/GRZre92NQ4exzvhZ+8curmvZl7bXWC28+5F1N5amgypts4tOn4xPUGqf4VO6jD39PY/GMvl909cJw7k/Obnsdc/Emm7jxZf/QG29APe5tHwxLLLHElPvYyuKYI98b4r6nqdfrS+ut4vVjn/nvEANTjdN++xwcYshqtiZBhdmSn3q9w/y9+rOLfxQuuuQnhUjx8+Uth7w7rLzyqoX17Rb28+fJwsvPD/G3QOP0zGc8K+z/usMai0vfFz2lODbe7aV7hzhiSxXTr35zbfjW977c1FU8fu886v1N5fUFcyeo8PrXHJL9/jw9+/1ZPCpX/C0RA7nx/OxmElToRm0wlhnmz/pOjqBrqHot11D1HmXv5uI11Gz8/piNdZYdk07LXUN1Kqb9MH+vuoZqff67hup9UME1VOtzUi0BAgQIECBAgAABArMnIKgwe/bWPC4gqOBMIECAAIG2BKYdVEihgsVrSxGCugBB2pKsbaqPRXXPes+HElKf+bLUR/aabuquLZ/apGWyeiMq5LDMdiwQRzg45Qsnhb/fc1fhshttuGl4w2sPyerqzuDCtu0UXnL5z8JPLzintOk+ex0QNt90i1p9PPfP+vbphU/zjw2Wz56Ce8Sb3h5WWeVJpf1VWfHNs88Mv77+FwVdzgtvPeI9YfXV1iyoqy/qx6DCZ7/4sXDzrX+p35Hs3ebPfn7Y55X7N5WngiqDCmd+7dRw4003pK4nXtdb9ynh8Owc6NX0pz//IXzprFPDE0803uw4LwvZvDycd2Hzzadz8Sab6FX2ZNv49xf/DtuZ4ufGx0/5UGHTvXbfN2zx3K0n6nq9vokVVzBTNnLEqqusVhs5Yplllq1gLZ13IajQuVkvlhjm79X77783nJwFe+ITQYum+J0RvzumO/Xz58mlV1xQC4o1Gqy80irZyEz/1lhc+D76/veJ/xoee+yxpvp4Q8nGz3x2U3k3BedfeG64+LLzmhZ98vpPq93Y31RRVzB3ggrHv/cj4cprLgk/+PF36rYw/+ZpT3lGeON+R4Y4ilink6BCp2KD0X6YP+s7PYKuoerFXEPlPfrrGmo2fn/MxjrzR2g6866hpqM3fMsO8/eqa6ipz3fXUL0PKriGmvq81IIAAQIECBAgQIAAgdkREFSYHXdrnRQQVJi0MEeAAAECLQTaCiq8e9uw9aHz63pJgYOmW7UXBwfqwgS5JdNysSgfNKhrnwsf5NunbupCELmAQqyP7WNQ4crTrknNC19HR0fDyEh3Twkt7FDhwAh8+/tfCb/8dfH5s+KKK2dPPn5XLRBQ5Q6XPR0/rmOppZYOhxxwdFh3nSeH8y/6Ybj40p8WrjreSHbg698cnvrkDQrrqy687757ajdfFj2NN94QGG8MbGfqt6DCgw89EE7+9H8W3gz5ohe+LOy4/S6lu11lUOGET/x7ePDB+5vWtVl2U/1r2rypvmnhDgvuve/v4bTTTw6jDz/UtGS02GSjzcNnPn9CU91cDSp86KT3h3hzZePU6Y3EMahQFHTadpudwq4vfsVE971e38SKK5j50XnfDZdfeXFhT+ut85RwwL6HZ9+xyxfWz2ShoMJM6nbf9zB/r/7wp98NV1xV/LfynCyg8OoW4bZOxPv58+RXv/15+NZ3v1S4uwftf1SIN8xPNf32d9eFr3/njMJmcZShOELAdKcYhjg1+867/Y5bmrqa6ibb8QXmVlAhbtOPz/9+uGzRhU37kwqes9n88OpXvCG9bftVUKFtqoFqOMyf9Z0cSNdQzYEy11CTZ1C/XUPNxu+P2Vjn5BGa3pxrqOn5DdvSw/y96hpq6rPdNdTsBBXikXENNfX5qQUBAgQIECBAgAABAr0VEFTorbe1NQsIKjSbKCFAgACBAoF2gwpbZUGFfCghHyCYKE8Bg2w9KXgQVzlRH8tjweIpHzioa98Qdkjt02t+uWxFqXiib0GFCRIzHQr8/JdXhu+ec1bhUvG8e+O+R4QNnr5RYf10Ch9//LFw+pc/Hf52y58Lu4lPFd5uwc4h/mNd2fTKl78uPP9525RVV17e6h9m3vSGt4SnP3XDttbZX0GFsXDm104rHMkgnh9HHPSOsM7a65fud1VBhet+dXWI4ZaiaYcXvDi8ZOfdi6oqLXv00UfC5878ROENm5tstFnYb5+Dsrrb+iaoEJ/Yd9Kn/qPQ6Ni3fSCskI1W0u50zo++Fa669rKm5s94+sbZ06mPqJX3en1NGzPNgjvvui18+nMn1H3X57uMNwXHm1tjwKqXk6BCL7XbW9cwf6/GENdHs8+VRx99tAkrfq8fddhxYdlll2uq67Sg3z9PYujuxE/+R/Z50jgyTwirrLxqePMh7w7LLVceLo4Bwk9/9iOFobkYmDr2mOPDEkt0PipA43E49yffCYuuvqSxuPb+da96U9h0k+cU1k0Wzr2gQrz++kY2OlYMepRNL9zupeHFO+5WVl1YLqhQyDLQhcP8Wd/pgXUNVS/mGmrSo9+uoWbj98dsrHPyCE1/zjXU9A2HpYdh/l51DdXeWe4aavaCCq6h2jtHtSJAgAABAgQIECBAoHcCggq9s7amYgFBhWIXpQQIECDQINBuUKFsRIXY3UQQYXHAoLaK7MaXGCGYqKsVNgQVYllaZnH78aLxpfLhhcWLT/YXl8uFFGJ9iiwIKiQtr50I3P33O8MpXzgpu6HwkcLFdtg2uwF8p5m7ATzeaHfaF08O8R/fO50WbPXCsNtL9+p0sa7bxxvQ4k3dRU+fX3ed9bMb9t/Zdt9lQYX41P2ll14mLJ/dZLj8yAphzTXWDjEk8uT1njqNGw67v0nwodEHsxEtzg3X/PyKwn3bcottw5677VNYlwqrCCrcc+/dtfO0yD6uZ799Ds5GMtgsrXLGXuONjb+5/hdN/ccb1A878G21m29vv+PWvgkq/OHG68OXv/7Zpv2ZN2+J8H//5cNZeeO3WVPTiYKLslFPfpaNftI4rZSNyPKut/7fWnGv19e4LVW8/2Z2Dvy64BxIfS+xxBJh+wUvCjvtsEtYcsmlUvGMvgoqzChvx50P+/fqzy7+Ubjokp8Uuu320r3Dgq12KKzrtHAQPk/i52/cj6IpBp723mPfsNaa6zZV33rbzeHsc74W7rjz1qa6WLDLi/asBT0LK9ssjCPkXHzpeSHeMFY0rbjCSuGdR/9b9ttkiaLqXFn3v0FynXQ0+8nT/ifcdfftTcsc/96PTJQ99tij4Ytf+UxpWDY2fOXuWRj2ue2HYQUVJniHYmbYP+s7OciuoZq1XEONm/TjNdRs/P6YjXU2n7XTK3ENNT2/YVh62L9XXUO1f5a7hjo2+/8rXqd9sDZbuoZqE0ozAgQIECBAgAABAgTmjICgwpw5FEO7IYIKQ3vo7TgBAgQ6E+goqFAQKsivrWykg1qbxcGCFCaIZXW3faa+s/IUUGjZX63T8f+kPlP7hSdeGhaddk2uRfPs6OhoGBkpfzpr8xJKBlkgjmjw2TM+Fm67/ZbC3Xzy+k8LB+9/dBs3oRUu3nbhbbffHD7/pU8UPn25rJMNN9g47P+6w7LMz1Q3yJX10Hn55VdeFH503vcKF4xPUX/OZvML64oKy4IKRW1jWXw68rZb7xi22XKHLp5E3f5NgjGwcv8D99WCI3+86YbaU5TLQiwrZjegH3XYsWFkueXLNrtWPp2gQnwi9+VXXRQuufxnhQGRuIIY7njrEf+SnQt1n64tt6mbyosvOy+cf+G5TYvGJ4PHkEK80SZO/RRUKBulIo6kEEdU6GS66tpLwzk/+nbTIksuuWR4/3Ex9BBCr9fXtDEVFMTQzOfO+HiIIZ5WUzwvY5Bqow03bdWstO7hh0dLz/nGhU7+zH81FoWX77J32HjDZzeVFxXEz5cqnnBf1PewlQ3792rc/498/IPhH/94uOnQx9EB3nnU+8Myyyxbq3v88cdDDCsuvdRSYfnlV8jKOvsMH4TPk5tv+Uvt988TTzSPqhCR4ogI85+3IDwl+z0WR1m4Lwt1/uVvfwrXXrcolC2zUjZqxduOfF9YKnPtZPrt736Zff/fW1vHXXffUQtQpGuTxn7i920MCG78zHY+Y9r/DdK4nm7ft3OTTex7NPsc/2z2eR4/14umGMKIvzXjyEDtTN0EFXzWtyM799oM+2d9p0fENVS9mGuocY9+vYaajd8fs7HO+rN2+u9cQ03fcJB7GPbvVddQnZ3drqFmL6gQj5RrqM7OV60JECBAgAABAgQIEJg5AUGFmbPVc3sCggrtOWlFgACBoRfoKqiQqRXdsFN3c2x+tIPcTbP55epuw1rcpqk+LZvvL3fUUkghFqX1LzzxsiyocHWuVfOsoEKzyTCXnPuTs7Mb0RcWEsQbCo88+J1h1VVWK6yvuvA3118X4tPqJ8cIKV/D6qutWbsxPG5jr6axsSfCyZ/573Dfffc0rXLl7KbAt7/l/3Q04kGnQYW00nhDcQxFPPMZz0pFbbyW3yQY+1syuxEyTo9lN5gW3VxatII40sMbXntoW+dHWVAh3pyy3YKdm7q/9ba/1W5kjTcz3HnX7VNu0+67vjpsPX+7pn6qLLjhD78JX/vWFwq+A+LNmgfVjebQT0GFK6+5NPzgx83hgnh8jzrsuI4If/3bn4dvfvdLhcu8/7gP1UYX6PX6CjemgsJ4jE//yqemPDfjquKNvDGw8KRVV297zQ//YzSc/On/ajuo0HbHJQ1fsvPuYYcXvLikVnEnAsP+vXrjTb8PZ37tlEKy+PToddZeNxuV5rpwd/a0/geyUFz6/RtvCI/f7fHv5Xmbb9nWEyIH5fMkjj4Rn6BaxRSvCfbZ64Cw2bOe11F38TfOv3/4PW0v09mIDeW/QWLYcbaeBpp2Nj69N4bP4udu0RR/qxxywNGFI1s0tu80qOCzvlGwf94P+2d9J0fKNVS9lmuo5NG/11Cz8ftjNtaZjlSVr66hqtQcrL6G/XvVNVTn57NrqNkZUSEdKddQScIrAQIECBAgQIAAAQKzKSCoMJv61h0FBBWcBwQIECDQlkBXQYUsNJAPCKQVpaBA7X0+WJDCBllFuhErtqkLKtQK5jXXx2XzfcV2DVPallp/WXtBhQYgb1sK/O73v67deF3W6LV7vzE8u8Mb3cr6arf8wuxmvQumuFkvhhPi0+vjDY29nH5z/S8WByma1/rSnfcI27/gRc0VLUq6DSqMdzkvvHjHl4UXbvfSFmvIV5XfJJhv1e583NcXbvuStp/AXhZUaHd9rdqtv+5Tw0H7H9Xxk6Nb9dlYF58sHUceiTcgNk47br9LeNELX1ZX3E9BhYWXnx/iudg4Pe0pz6i5Npa3et/qH9ePe/sHw/IjK4Rer6/V9k637uZb/xK+8vXPhdGHH5qyqyWXXKoWytkx+5tt5ynnMRD10U//55T9VtVAUKEaSd+rIfz4/O+HyxZdOC3Q+Lt6i+dsHeLN8DFMVzYNyudJvEb43rlfDz+/7sqyXW2rPI6+8OpXvqHjkELsPG7Dv3946nBavGl/7z32C8/aePO2tmm8UflvkLkQVIjb+Je//imckQVs4tNsi6aVs9Es4m/PlbKRpFpNnQYVfNa30py7dT7rOzs2rqEmvVxDTVr08zXUbPz+mI11Th6taudcQ1XrOQi9+V51DdXNeewaanaDCvGYuYbq5sy1DAECBAgQIECAAAECVQoIKlSpqa9uBAQVulGzDAECBIZQoK2gwrHbha0Pnd8cIkhei4MIdSGExWW1JtlNPxNhglSeK0vdNL7Wgge5wok+Ylmun9Qk1V9yUhxR4ZpUXPhqRIVClqErvD97ivFnPn9CePjh4qfHzt9iQXjFbq+dBZex8OGP/t+WTymPT/2ON9X2eoo3qsfhxRunZZZZNrzzqPeHTkd3mF5QYXwrXr7Lq8I2W27fuEkF78tvEixoPGXRRhtuWrsRMt6oGG9anGqaqaDCWmuuU7uZfmS58htZp9q2qerjTYenffHkEJ8W1jhFhze89pCsuP5Tu5+CCudfeG64+LLzGnetdhPqvq8+qKm8VcFtt98cTvnCSYVN3vbm99VGFOj1+go3psLCBx+8P5x9ztfCH/90Q1u9rrH62uH1rzk4rPakNVq2d/NqS545Wel7dfywfPpzHwl33HlbJcco/p3EkXvKgomD9XkyFr7yjc+H3//xt13b7bfPwXWj+3TSUbtBhRi02mPXfcIWz90q677+u698feW/QeZKUCFu+69+c2341ve+ks2lK6v6PVpn7fXDwVkwMv7uK5sEFcpkBqfcZ33nx9I11KSZa6hxi36/hpqN3x+zsc7JM7f6OddQ1Zv2a4++V8ePnGuobs9g11DdyhUt98nT/ifcdfftTVXHv/cjTWWpwDVUkvBKgAABAgQIECBAgMBsCAgqzIa6deYFBBXyGuYJECBAoFSgF0GFsgBDvrxoA/O3/eRvlSkbuSG1WZgFFa4UVCgiVZYTGBt7InzxK58Jf/7rjbnSydk111gnHHHQ27Onfi89WdijubInBeZXH5+ufPib3l676TlfPpPzf735pvD5Mz9RuIoFW+0Qdnvp3oV1rQpTUCHe6B+f0BtvfHvsscfCPffeHR599JFWi07Uxc+EA/c7Mjz9ac+cKCueKb9JsLh9e6XxHHn5LnuH+c9b0HKBmQgqxH3e5xVvCCtO8XTjlhs2RWX8rP7qN4tvHI030B5x0DsKgxr9FFT46QXnhEsu/1mTxGbZaCqvyUZV6WSK/6AZ/2GzaDrmyPfWbs7v9fqKtqX6srFwxVULQ9y3+Dc81RRDTa/Z64Cw4QablDYVVCilmZMVvlfHD0u80eikT/6/So/RCiusFI4+/LhQFEgbpM+T+D0ZQ09FI/e0C7rO2utlny1vLA12tOqn3aBC6mPzTbcIe++5X4ijxUw9lf8GmUtBhbgfCy/LRhm6sHmUobSP8ebaGDabN2+JVFT3KqhQxzFwb3zWd35IXUMVm7mG6u9rqNn4/TEb6yw+e6ssdQ1VpWY/9uV7dfyouYbq/ux1DdW9XdGS3QQVYj+uoYo0lREgQIAAAQIECBAg0AsBQYVeKFtHKwFBhVY66ggQIEBgQqDdoMJWhzx/Ypk4kw8RpIoUFKjVpREPssrGQEItaDDFiAqN/ae+07pSH+l9fE1tBBXyKubLBC5c+ONwQfa/oik+KTeGANZac92i6hktGx/u/fRsHemMLl9dDFMcduAxLZ9qW7505zVf/84Z4be/u65pwXij2jFH/ktXoYl//OPhcO9994S111o3u+Gt/i//gewp7fHp9PFJ93/9201N680XxOWPPPhdTX3k20TTD37ouPqiCt89d7Mtw5677ROWXnqZwl6rDCrEgMAuL9qz9sT/wpVVWBhvVoz/4FY0vXL314W1svOwaIpBhe//8BtNVSuvtEr4/9k7E0Apimt/F5t6WUVQFBfc9w3BBbdoXOIad+MSUSEaFTEKRhKNmpfkn5e89xKX6EueQWNcYhKNiQuIK6ioKIr7iuDCIqLifjWs/zrVXd3VPd0zPTM9c2fu/TpmuvrUqVNVX82dqWbq13XsESdH7LIrRBq3iKNzcf3N/5soNDpo/yPUjjtk2WEjDPbwY/erKY/eGxr81Ibrb6pOOu70Ansxw9x576hrb/xdosvY0ZeqnnrBcb3rS2xMjYyy68aE+25Xb709s2QN8jd/5LdPVLLYN+lAqJBEpXFtfK96YyPfk/J9mfex7dZD1BGHHF8Qtr18nkx+ZJJ65PEHCvpXiUFEjyefcIYauOa6ZRUvV6ggwXcfpne4+kaWHa7S5yCNJlSQft11z61qxvNPSjLxGDp4mDr4W0cl5iFUSMTSbox81pc/lNxDFWfGPVSUT7PcQ7XF/KMt6oyOTu2uuIeqHdtGj8z3qjdC3ENV9k7lHir53yMro+mVqlSoIKW5h6qGPGUhAAEIQAACEIAABCAAgUoJIFSolBzl8iKAUCEvksSBAAQg0M4JZBIqjB2mho7cIULCXU5sl1O7Nr1aOPCPCxVsRuihLdZfCxiSjmRr1NPGE6HCU+yoEIXDVYSA7KIguynIk8uSjoO/daQaOnjXpKya2mRRwnU3XaUWL/535no23XhLddxR8lRb+xeQuWhZjp98skhd+X+/SmS2xWbb6oXnw8uKV67zG2++ou576C4lP+CnHUfJgucto6KqqG/6IkF5qvsqelcHeyxdtlS1fvWl6tK5i/q3Ho8vW79Qn332ic1OPa85YG0tHjlHP125S4FPuUIFEYCsvPLKSp48L21bo/9aav31NlKD1tvQPJW/oIIaGF5+9Tl12x031SByNORpeveScheU5ilUmDb9EXXvg3dGG6Wv1lpzbb1jxHkF9mIGea/KDhRJx4Vj/1MLMrqpeteX1JZa2+S9I0xFcFTsEB4jTzrHiJXifsuXL1OLPv4wbk69TtrJYv9vHqo22Wjz1DJuRo/uvZTsVsNRPgG+V0NmTz3zmLrn/n+GhpSUvPf79xugenTvqQV7i/R7/SMl7/lix4nHfk9tvGH0/dwePk9qsTCpd+9VzY4/wjf7sUKLWO83c40PP1qo5P9Lly4pWlxEdj8448dKdr0ofqTPQRpRqLB8+XL1l1vHq1lvvZHaLRFM7rrzXgX55QoV+KwvQNiwBj7ryx8a7qG4hyr/XZO9RFveQ7XF/KMt6sw+Gvl4cg+VD8dmicL3ajhS3EOFLLKmuIc6X8kDfPI+qhEqcA+V92gQDwIQgAAEIAABCEAAAhDIQgChQhZK+NSSAEKFWtIlNgQgAIF2RKBmQgVh5C+cRqjQjt4w7aArX33Vqv5w3W+UbCuedGyx2TYFT3tP8svbJgvh//jnK5Q8QbzcY/dd9NN898ryNN9yI4f+kx64Qz359KOhwUmNOOlste7a6zuW2iS//PJzj1GKYGDzTbdW3znylCKVV7dIUOqfo5+WP33GY2p2kafF77X7/uob+v/xI02oIE9+lkWO7tG1aze9U4bszFBbAYpbZzy94P35WjjzO7VkSfFFmvFylVy35SIbaa88NVqefBY/+vTpq84986K4uej1cy9OV3dM+FuBjwhPLhn3X8Ze7/oKGlMng4iuHtJPSX/y6am6xnTJYd9V+6kzRoypeneY//jV+QU9O+qw76bu2FDgjKEiAnyvRrGVeqqlCA323HVfte46g3TB8DN+6dKl6vGnpqhHH38wdXF8H734ftRp44zgydba7J8nImb6/fj/UV993Wq7FDmL8G+XHfdUm228lRZ2rGEEfCLqWPjBe2rqtIfUewvmRfzdi8022cqIOV1bOellWrQoC8hEKCli0rRjpyG7qwP3Ozwt27dXNwcpETwxu5pFNhJQBAd/uvnqIn3vpI45/Ltqy823i9RfrlAhUjjDBZ/1GSDVwIXP+sqgcg+lFPdQlb13spRqy3uotph/tEWdWcYhbx/uofIm2pjx+F6Njgv3UFEepa64h1KqEcXeMm7cQ5V695IPAQhAAAIQgAAEIAABCORNAKFC3kSJVy4BhArlEsMfAhCAQAclkFWosGNsRwV3uaFdYuXaXJxp+dZufd3yxfLEP54vNltedlSYzo4KgoQjgcBf//En9frMlxNylJIFgGeMGGueYJ/oUCOjLISTHR7mzHs7sYaV9dP0t9KLwOSH+bTjSL2bwDZFdxNIK1naLj+y/Pbqnyfu9LDO2oP009BHlw6Sk8f7C+era2+8Si+eX1wQURb8X/CDnyXuZuA557dIUEQH/7jzJr2YdGlBO2RRpSy6lidlu0eaUKFXrz5qzKiLXdeq0yIQu0yPmQhgyj2+ueeBardd9tb9u1m99Mqz5RavyL8tF9lIg9N2jpD31I/H/L+y+vT4k1PU/ZPvLigjO2OMO/fnxl7v+qTSPN4TBZ3KaBBhzz/vvkV9UWR3hQP2PVztPHT3jBGT3Vi8msyl1la+V6OERfSU9H3ds2dvdegBRyvZCanY8fEnH2mR2NWpfy+nnHiWGrTuhkGIen+e5P1ZksZLOrjOwEHqiEOPT91FSNry7PNPqQn3/UPvRpG0S1YnIwRcddXVAl6VJGRXhTv1uL748ozE4rI7xoVjf6nzku5QbJH85iA2YqlztUIFiS/C3vE3XKk+TxH4du3aVQ0//oyIYBWhQqmRac58PuvLHzfuoQqZcQ9VyKQaS1veQ9V7/iGc2qLOvOc95Yw391Dl0Go+X75Xo2OWdk/APZRS9t/oXGJpvMSHeyiXVPlp7qHKZ0YJCEAAAhCAAAQgAAEIQKBtCSBUaFv+1K5/HdX/iGrXa8IDAhCAAAQgkEqgnkIFaYT75eQu5XHttrFp+a7d+rqxESq4VEi7BJ56Zqq65/5/uaYgLU87P+XEM9V662wQ2OqV+NeEv6rnX3w6sTpp14nHjlQbbbCZKuYnC8VOPXGUGrjWuolxqjGmLbyWmMccflLBk3SrqStL2QcfnqimPvFQouvo7/8odUGjfAL9x69+mFiukidxvfHmK+qW265LjCeiERGPuEd9hQrL1c9+fYFbfea07M4hu3TcdsdNZjFI5oJVOLblIhtp9vz35pjdOpK68JMf/rqI+KWwxANTJqjHpk0uyFh74Hrqe8PPMfZ61yeVrlhR/XuioFNlGFq1aObGv12jZKeOpGO1vv3V6O+P01lp3/JJpaI2hApRHvW44nu1kLJ8L8j3Q/wYOnhXdfC3joybE6/fnP2auvnv4xPzDtzvCLXTkN2CvHp/nuT5WbJ8+TL1P1f+R+JuCt1beqgzR45Vsjip1CGfufLZm3TkteuUtFUWrSz6+MOkatS5Z/3ECF4TM40x3zlIej1hTh6LbCSafG7LzgryhOekQ8Zq5PDRwfwLoUISpea28Vlf2fhxD5XMjXuoZC6VWNvyHqre8w/h0xZ15jnvqWSMuYeqhFrjl+F7tXCMuIcqZGIt9t/o7DX3UB6JSv4d1zIsduYeqhgd8iAAAQhAAAIQgAAEIACBRiSAUKERR6VjtQmhQscab3oLAQhAoGIClQgV4qICu6QwbreNsvly7fpYu2uzZeRs8yXt+rh2yZPDzUeo4DHhNUpAFlnJE2Fl94KkY+89vqX23G2/pKya2ootrpOKD9j3MP2U8T1MG6Tt19/8ezV3/juJbeqlF/Oddsq5Ss55HfKE4iv+8Ev12WefFISUJxSfo4UBIqao5zFz1qvqL7dem1jliJPOjjzVN+qU/yJBWUgqC0rjR/9+a6hRp0WFAggV4pTC67ZcZCOtkMWX//nbn+iU+23ite90/Te11prreBcZXuW9Ke/R+DF4u53Utw881pjrXZ9U2taLbKQNstDm+r/8Xn3w4ftyWXAU//stcC8wIFQoQFJTA9+ryXhv0oKcWW+9UZApcwyZa2Q90p6yusP2O+udGY4JwtT78yTPz5I5c9/Wu0dcFfTFTRx92HfVVlts75qKpFeoa2+4KnF+NGi9jdQpJ5xZpGz2rFdff0H9/Z83JBY46bjvqw3X3yQxzzPmPwcpUpnJymuRjQSTuc5fbr3OfJck1StiMxHjtbR0VwgVkgg1r43P+srGjnuo4ty4hyrOJ2tuW95D1Xv+IUzaos485z1ZxzXuxz1UnEhzX/O9mjx+3EMlcxFrXKjAPZTHqtGFCtJK7qG8seIVAhCAAAQgAAEIQAACEKgtgY8//lhNnjy5oJIttthCyf85IFBrAggVak2Y+BCAAATaCYFyhQqFSzhDEFZAEPex9tDTS8X93Hwp4+anxZAyrp9cI1QQChwugSVLFqv/+9Nl6qNFH7jmIL2+XsQ2/Pgz9IL7Yu+0wD23hDxNUhYipm2EFV+MKBV/8cVn6po/X6E+//zTxHasvdZ6emeIs5TssJDH8dIrz6p/3HlzYqhv7XOY2mVHT0SR6FAjo/xQ/99X/jQx+vFHj1CbbrxlYp58WuS5o4JU8sprz6tb/3VjQX0i3rhw7C8j49BsQgXhvHjx4oK+ZTV8uGhh4hPBV1ppZXXmiLGRML169Slr1wIpfP3N/6vemTM7EkcuDtr/CLXjDuHTxgscUgxX/P6X6pNPFxXk7rX7/uob+v9ZjiVLlqj/uuJitXRpoSAq/vdS7/oaYZGNMFzw/jx1zfWXJ37uHXbQd9T22+6YBXWiD0KFRCw1MfK9mo71Nv2d8LL+bogf5QoiH33iQfXQw/fEwyh3dxabWc/Pkzw/S15+9Tmze4/th3sed+7P1SqrtLimounJj96rHnns/gIfEVX+4IwLC+yVGL7++iv168svTix60P5H6u+eXRPzPGP+c5AilZmsPIUKEvCZ555Qd0/6R2q1666zvhp+3BlGFPyry0T8Fz2SRJxRj2xXfNZn45SHF5/1lVPkHqo4O+6h0vk00z1UPecflli968xz3mP7UMmZe6hKqDVeGb5X08eEe6h0NnGhAvdQHqtmECpIS7mHSn9vkwMBCEAAAhCAAAQgAAEIQAAC7YMAQoX2MY70AgIQgEDNCZQjVIgLAoLGrfBy3EXerm/a0m/XJ4ilE9bfzbc210/Sro/NQ6hgSXC2BO6Y8Df13IvT7WXkLE9+lUXTslC6nsfCDxaoa2/8nXkqYFK98gTg4cedrjp37lKQPX/BHPWnm/5XL4ZeUpAnhm222kEdeegJiXnlGv94/RVK6osfK6+8ihoz6mIli87rfcgT6P7vT79NrPaEY0aqTTZKU4bnv0hQdre49obfJbbl9FPO00/iXzvIazahQtDwChPvL3xP/eG63xSUlqcuj9Y7cVR75C1USHt6+cC11lWnnfyDTM19febLRnyU5CwCokHrbhhk1bu+RllkIwBE/CQL+OJHuU+cj5dn8WqcSO2u+V5NZzvh3n+op599osBhu22GqsMPPq7AnmYQsYMs2IkfsmvSmLMviZjr+XmS52fJtOmPqnsfvCPSF7no2aOXGjv60gJ7MUPad6zMoy6+4Fe6aNrdRLGohXn/+duLEuduImgTYVv6kf8cJL0uLydvoYJEfWDKBCW7gaUdW22+nTrkgKMTBR0IFdKoNa6dz/rKx4Z7qOLsuIdK59NM91D1nH9YYvWuM895j+1DpWfuoSol1zjl+F5NHwvuodLZxIUK3EN5rJpFqCCt5R4q/f1NDgQgAAEIQAACEIAABCAAAQg0PwGECs0/hvQAAhCAQF0IZBUqDB25Q3p7SggVpGB8aVCSwMBWYH1dH2uzPnJ28107QgWXBukXX56hbr/rL6kgij+BP7VYVRnypPo//vnKxKe3S+C+q/YzC6NFRJF2FHtKp5TZd6+D1W677J1WPJP93TlvqT/dfHWi764776X22/uQxLxaG4s9jeqMEWPUgDUGpjQh/0WCxRamjxw+Wq0zcFDQlrRFlCKSEdFHnkcjLKhopkU2wl4WFsuP44VHJ3X+6EtUD71wttRx5z1/V88+/1SBm/wt//Ccn+pdWzoHefWuL8/3xF2TblXDdtxT9e83IOhPOYkZzz2pJEb82GG7ndWhBx4TN2e+RqiQGVVVjnyvFsf3sH6q/xT9dP/4kbQTQtzHvX7qmcfUPff/0zWZ9Or9B6izvvfDiL2enyd5fpY8+fRUNemBf0X6IheyK9SPx/xSizXDz8wCp5ghTdghbpf+6L/1a9LdRCxIict///trlbRTgBQ7YN/D1M5Di+0ylf8cpERzVS2ECnIHdtu/bkrcNcS2Z+jgYYliHYQKllBznPmsr3ycuIcqzY57qHRGzXQPVc/5hyVW7zrznPdwD2VHsWOe+V4tPu7cQ6XziQsVuIfyWDWTUIF7qPT3NzkQgAAEIAABCEAAAhCAAAQg0PwEECo0/xjSAwhAAAJ1IVCNUCG+3KdAOCAChk5xL92tFLv1jMTxfW2ehRLxsUb/jFAhBqQDXy76+EP95P3LEp98K1h2GrK7OnC/w+tKaNmyZeqGW/6g3p37VmK9slPByJNGK1mIWOp48OGJauoTDyW6yQ4nxx11qtp04y0T87MY/3b79UoW18cPWTj4gzMuVL17rxrPqvn1smVL9U4UV6n3FsxNrOuCc3+mWlZJE3jkv0jwn3fdol54+ZnEtsjToOWp0Paop1BB6pQFlZUcskC0S5eulRSNlGmmRTbS8C+++Ez95qqf61ThN4wsnpdF9MWO5cuXq8uu/rn64svPC9wGb7uT+vZBx0bs9a5PKs/rPfHHP1+hPte8Rnx3lFq1z2qRfmW5SBMqlH4iefHoCBWK88kjl+/V0t+rs99+Q93412sKcMvn6ujTx6k+ffoW5CUZZDGb/K3Ejw0GbayGH39GxFzvz5O8PkuKiQvO0LtdDVhjrUg/i13c99Bd6omnHi5wEZHZ+WXuzlAQxDe8M2e2kt18ko6jDz9JyW4C6Uf+c5D0uryc2ggVlN7Ra6m64a9/UHPmvl2qCZF8hAoRHA19wWd96c/6YgPIPVQxOl4e91DpjJrpHqre8w+h1hZ15jXv4R4q/X3f3nP4Xi39vco9VPpfQfzf6LiH8lg1l1CBe6j0dzg5EIAABCAAAQhAAAIQgAAEINDsBBAqNPsI0n4IQAACdSIwf/58tfbaaxetbY+xw1R8R4W4cEACRJZ2+rssmMCuWCHF7sYL4ji+sujaHkG+NcTOCBViQDropQgCrtML2ucvmJNIYM0BA9X3hp+Ty4LsxApSjHdM/Jt67oXpibnyPpcdHjbZaIvE/Lhxhf4b+es//qTeePOVeJa5XmmllU0fs4ge4gHkh9Srrvm11hUV/sVtveVgddS3T4wXyXz92WefmKck9+zZO3MZ65i2cFPy+622ujpbLwJNP/JdJDhv/rvqupuuUrJAPX5069ZNXTj2PyPmegsVIpW3wUUzLbKxeK698Xdq7rx37GVwXnXV1dSo711gnvIdGGOJadMfVfc+eEfM6l2ecMzIxL/reteX2LgKjLLIZv57c8zuL6eccGbZoqW77tELsJ8vXID9nSNPUZtvunUFLfKKIFSoGF2mgnyvKpXle3Xx4n/rp+5frL8/C78btthsG3XsESeX5P3ppx+rq8f/t1qyZHGB785Dd9dP7y8UWTbj58m8995V4/UOU0mHzIVOOGaEzgrvAZL8xPbV161GmCrc4sc2es5yZGzO8va7s1QfLbaUHayyHyu0SOH3SsQKSUdpYUW+c5CkNsRttRIqSD1ffdWqxt9wpZL5YtYDoUJWUm3rx2d9ts/6tFHiHiqNTGjnHipkkZRqtnuotph/tEWdSWNVro17qHKJtQ9/vlezfa9yD5X9/c49lMeq2YQK0mruobK/z/GEAAQgAAEIQAACEIAABCAAgeYhgFChecaKlkIAAhBoUwI1EypIr+wCZ0dkYDor9pjNLkEqWBLtx7BChYL8BHoIFRKgdEBT2pN1BUW3biup7596nlnYXk808qRfaVfasf83D1XDdvpGWnaiXX7Mk4ViH3z4fmK+LMI77ZQfFNllILGYuuf+f6qnnnksMfP0U85Va625TmJeFuPjT05RDz0yyTyhfvdd9s60yFl2Unjk8QfVI4/dn1rFbjrWvnsdnJovcqr/+NUPE/PL/YHrlddeUP+8+xb9VOElifE23nBzdeKx34vkIVTwcKzWt78a/f0fRdhUciFPtU5aMHrQ/keoHXfYrZKQZncMecJr0iF/m/I3mnR8tOgDJQtPkp622b/fACXvL/s95paX3TjqWZ9bdzVpu8hGYqyySos69ICj1ZZFnyQe1jZn3ttmse/y5ctCo5+SnVpEFFLp8bNfX1CwOPwY/ZTzrG2rtN6OUo7vVW+ks3yv3vz38erN2a8lvjWyPHn/5r9fm1r+pOO+rzZcf5OC2M34eSJiyN/87j/Ul61fFPRHDPvtfYjadee9EvOsUWL85dZ0Xocd9B21/bY7Wndzvv3Om9VLrz6vttpiO7XHsG+qNVYvvXPDY9MmqwemTIjEsRe9e/VR54262F6mnPObg6RUUGCupVBBKpMF2dfe8DvV+tWXBXUnGfISKvBZn0Q3Pxuf9R7LLJ/1SdS5h0qiEtq4hwpZpKWaTajQFvOPtqgzbbzKsXMPVQ6t9uPL96o3llm+V7mHyva+5x7K41Tuv+Nmo6sU91BZSeEHAQhAAAIQgAAEIAABCEAAAhDwCCBU4J0AAQhAAAKZCJQtVEgQGdiKrNhAruOCAsmL28TPlgme2p4mYPAFC3GBgxtD0nKIUOGpP87wLlJeW1tbVUtLS0ou5mYnMHPWq3rR2nW6G0nvOqWSFq3Vus/Spltuuy5xhwKpe/C2O6lvH3RsRc34+JOP1B+vv8I8UTgpwAaDNlbf/c7pZheDpPy47euvv1K/vfrniU9yHrTuhuqUE8+KFynrWoQK90++25Tp0qWL2n6bnfTC8l2V7PzQuXPngliywF9+3JV+ph2dOnU2i8FlEVz6Uf0iwc8//1Q9o58E//BUEUwkv7+k/uF6IekGsYWkCBW8kWlkoYJ8F/2vfor5hx8t9Bobe/3G7vurPXfdN/I+lcVEf7l1vPpMvzeSjmKLkutdX1L7KrG5i2xs+W222kHtvoss+F3TmgrO7859S936rxvVF198VpC38sqrqB+d93NttzODApeSBtldJr7geSstoJCn4HNUR4Dv1Si/Ut+rs99+Q93412uihYKrTlqUuKfa5xsH6V2dugRWScjnyB0T/qpmvz0zYrcXvfUuAD8448f6MyhaTvKb9fNk4n3/VNNnJAsjpV+bbryl+tY+31by3RE/3n7nTXWfnk+8t2BuPCu4FgGBCAncQ4QKL77yrG/qpOvYQg0dPMwIFvr0Ft/wc0h2aZhw3+1K/gbSjmJCtrBM9XOQMFa2VK0X2UgrRHx2wy1/0MLNpSUblZdQgc/6kqgrduCzPoqu1Gd91Fsp7qHiRMJr7qFCFqVSzSZUaIv5R1vUWWrcsuRzD5WFUvvy4Xs13aIdzgAAQABJREFUOp6lvle5h4ryKnbFPZQy/wa8ev/0f38qxq9YHvdQxeiQBwEIQAACEIAABCAAAQhAAAIQKCSAUKGQCRYIQAACEEggkFWosOPIHaILrGOCAgkdLumJLt/NZLdCBBPIKxEpl5Afr1Ou5UCo4HHoqK+yAPb31/1WtaY8nVe47Dx095rh6dmzt9pt570jT0//4MMF6tobr0p82ro0ZL11N9AL288oWLBYTiPf0osab/r7H9Xy5csTi4kQ4KD9j0zMixuLPTX4uKNOVZttslW8SFnXrlDBLSgLL/uttroRLMjizUWLPlQfLlqYys0tO2T7YeqQA45yTQnp9EWCG66/qa43KnJYtmyZWrxksZJdKxYvXqw+0m359LNPEuJGTWsPXE99b/g5UaO+QqjgIWlkoYK08OVXn1O33XGT19iEV1loKU/oX0nvzPLe+/PUK689H/1+dMoMWGOgOmPEedrifqM5DjpZ7/qitVd2lbTIxkZaZ+1BaustBuu/5f6qj15UvXTpMvXRxx8YTq++/qJ1KzjvNGQ3deB+RxTYMbQ9Ab5XK/teLfZ3IqMqTxWV7/819eeEfHfLwsQ3Zr1iFrqmjfrhBx+ntttmaFp2U36efPHl5+qqa35d9Lte5gdrDhio+q+2hurevYcRdIigbOEH76WykIyttxysjvr2iQU+UaFCNFuETfI5L2fZMeCzEt/74ifike7de0YDFVylz0FkR4fV+vYrKFGOYaDe6WoPLaRzj3osspH65Hvw1n/J92a6gFP88hIqSCyO/AnwWV/ZZ707EtxDeTS4h3LfFeWnm02oID1si/uZtqiz/NGMlig2N+QeKsqqPVzxvVrZ92qxvxN5X3AP5f11cA+ljMice6j28GlJHyAAAQhAAAIQgAAEIAABCECg2QkgVGj2EaT9EIAABOpEIKtQYagWKpjDCgaKCBWSlqjIEs243V22KU9ECw4ntvVJy5cy1seWR6hgSXS8s7xPbvzbNUoW7bflMeq0C8xiLGlD61dfqvF/vjJ1N4BV+6ymTjv5nAwL3Er36KlnHlP33P/PVMeDv3WUeWJwqoPOWL58mbr8979U8tTL+CEigrNPv0Cb4391cc/i12lCheKl0nPNFvIn/0DvktI93cnkpC8SLFEwc7Y8tXmkFinEn94sARAqeBgbXaggrfzb7deb8fJaXNlrt27djGBFFqCWOupdX6n2lMovtXigVPl4vny2nDFijOratVs8i+s2JsD3auXfq7KQ/prrL9O7Ey3JZRTlCaQn6d16Ojnz5KTAzfZ5In14+tkn1IR7/5HUnYptskvTaXpu0E2LyuJHMaFC3LfU9QH7Hp5RAFvbOcgmG22hTjhmZKS59RIqSKVZ5nYIFSLD01AXfNZX/llvB5J7KEuisjP3UCG3ZhQqSOvbYv7RFnWGI1V+inuo8pk1awm+Vyv/XuUeKvu7nnuo7KzSPLmHSiODHQIQgAAEIAABCEAAAhCAAAQgkJ0AQoXsrPCEAAQg0KEJlC1UsLSssEAvlrJLlo3UwNqtX9rZKScu8iNOcLgLsHy7uygr4msLOWVEqDD9jzNsTuK5tbVVL2puSczD2LwEHn3iQfXQw/e0eQesUEEWrNxwy/+pd+bMTmyTPIV35Emj9VOg8tuq+q5Jt6oZzz2ZWJ88kXj4caerQettlJgvxhdefkb9865bEvMP/taRWuiwa2JeOcYsi9myxmtZpbsWBow2OzGULlPbRYLSllNOPCt1PBEqeCPUDEKFf//7ayULST5a9EHpt1WKxxGHHK+23XpISm7UXO/6orWXfzX+hivVvPnvll8woUTnzp3N3/DANddNyMXU1gT4XlWqmu/V516cru6Y8Hc9jM48t4JBlc9NWXS/yiql567N9nlicTw4ZaKaOu0he1nVWeZXwksWxicdeQkVBm+3k/r2gccmVZFgq+0cpK0X2UiHRWwiC6bSDoQKaWTa3s5nfXWf9TKC3ENV/j7mHirKrlmFCm0x/2iLOqOjVd4V91Dl8Wpmb75Xq/te5R4q+7ufe6jsrJI8uYdKooINAhCAAAQgAAEIQAACEIAABCBQHgGECuXxwhsCEIBAhyVQtVBBk7MigrKECk45gR8RH1jRgSNesHUU+IrBHn45hAoWSMc6z5n3trr+5v/VOwIkby9eTxpWqHDXPVo08HyyaEDe08cddaradOMtc22aiCP+fMsf1Ltz3kqM272lh1m8t+qqqyXmpz3lT3YrOO+si/WTiat/4nleQoXV+6+pvnPkyRlFCtLd2i0S3HzTrdXB+x+pevbsnchVjAgVPDTNIFSQlopI4ea/j0/dDcXrTdJrJ7XPNw5Uuw/7ZlJmqq3e9aU2JEPGJ58sUnfrBamz3no9g3e6S5cuXdUB+x5WcqeX9Ajk1JIA36se3Wq/V59/6Wl158S/Vzw/WWvNtfV8YUTiTj1p499MnyduHx55/AE15dH79H1B5XM5+Y459MBj1PpFRJl5CBWGbD9MHbT/4UpEoNmO2s1BpP5GWGQj43bLbX9SM2e9mogEoUIiljY38lnvDUG1n/XcQ1X2VuYeqpBbswoVpCdtMf9oizoLRy2bhXuobJya3YvvVW8Eq/1e5R4q+18C91DZWcU9uYeKE+EaAhCAAAQgAAEIQAACEIAABCBQPgGECuUzowQEIACBDkmgIqGCIyAw0KywQC7iecWo6nKyG0OBwMHGc2JZoUKBrxvfL4dQwYXSMdJff/2V+sOffqs+/fTjhuiwCBXenP26uvfBO1Lbs+9eB6vddtk7Nb+ajNbWL9Q1+mnwaTxkBwfZyUGeOBw/pky9T01/5jHV+tWXkaw9dt1XfXPPAyK2Si++1O177oXpSp6SJtu6l3t07dpV7bDdLmrfvQ7SwomVyiie7yJB+Vxab50N1M5Dd1dbbLZtyXYgVPAQNYtQQVorny233XFT5gX58jd15KEnqM022ark+yHJod71JbWhHNtLrzyrHn3iIbXwg/fKKWZ8N9pgM73I9wgl7weOxiPA92p0TKr5XpVIb73zppp43+1lfed16tRZDd5uR3Xgvoerrl3LFwk22+eJJS67UN096bayWElZEVLuMWwftevOeykRQRU7Zr/9ht69YbJ66+03tZu5uyjmHskT4eZ+ex2ix2aniL30Rb5zkHh9jbDIRtq0ePG/1Z+0cHjB+/PiTTQ7XMgcmaNxCPBZHx2Laj7ruYeKsix2xT1UMTpKNbNQQXrWFvOPtqiz+CgWz+UeqjifZs7lezU6etV8r0ok7qGiPItdcQ9VjE56HvdQ6WzIgQAEIAABCEAAAhCAAAQgAAEIZCWAUCErKfwgAAEIdHACZQkVHOFABJsVFkSM0QsRJMgRWQrkxnNjWLu2BeWsTYK4vnJtD99n6uXT1PQ/zrDWxHNra6tqaWlJzMPYfATyekJ/Xj0/7eRz1XU3/U4tW7YsMeR2Ww9Vhx9yXGJeXsb3F85X1954lVqyZHFiyGJCiaVLl6qXX31OPaUFC/MXzNEL/rqoc8/6ierZo1dirGqMc+e/Y0QLs/Siwc8++6TIE6c7qTUHDFSbbLi52mnIbkV3LijWnv+58qdKhBLlHCKGEAY9uvc0DITDoPU2VFtsuk1Z7UgTKsjTsk8/5bxymtQUvmmLbNZdZ3014rtnV90H2e3gzdmvFcSRxe877rBbgb1Sg+z4I/XI34MIkGLfZCasvCeG7rCr2RlA3ifVHPWur5q22rJv60XYz+mnxsv5U/13nHasskqLWr3fALXLjnuqLTcvLe5Ji4O99gT4Xi1kXM33qkSTp4o+89yT6sVXZqi5896J7ibmVNeySnez25KIGVfvP8DJKT/ZjJ8n0ktp92tvvKh5TVPv6B2ili5dkth5EST0W211tfbAddU3dttf9em9aqJfmvGTTxeZOcgLL8/Qu+cskprTXNUaq6+ltt5ye7XzkN0ThZ6pBYOMFeqXv7kodV4WuFWY2H7bHdVhB30nUvrPf/m9evvdWRGbXFz6o/8psOVp+PyLz9T4G6408zo37iC9y8UpJ5zpmki3MQE+6wsHoJrPeu6hojy5h4ryyHrVHu6h2mL+0RZ1Zh3TND/uodLINK+d79XCsavme1WicQ9VyDTNwj1UGpl0O/dQ6WzIgQAEIAABCEAAAhCAAAQgAAEIZCWAUCErKfwgAAEIdHACWYUKO47cIXVBVapwwGdrxQZyGVn+kyQ+iNlsWfnH9uAoJVS4TAsVxiNUCHiRgEAVBObNf1cvPP5YLyrerooo2YquWLFcff75Z+oTXZ/sBrF8+XItKOquunfvofr1Xd2ks0XCCwK1IfDV1616MetH6pNPPjZPje7du4/qu2o/vTi2r+rcuXPulda7vjw6IAt/F338oWpt/dLszNK5cxfVXy8k7q8XXNdC7JRHm4kBgXoTkKeLvv/BAvXll59r8dyXWgzXWYvhepmF9iJek90U8j6a8fNEGIjo870Fc9XnX3xqPlNkIfCqfVYzIo6+q66WG6tly5aqT/TcQ+Y88hm/ZOliJaKRHj16qgFapNCzZ++8h4R4EIBAOybAPVQ7Hly6VhaBtph/tEWdZUFJcOYeKgEKJgjECHAPFQNS5JJ7qCJwyIIABCAAAQhAAAIQgAAEIAABCEAgVwIIFXLFSTAIQAAC7ZdAVqHCUC1U0EqFZBBpwgHHWwQHBaXdeBLDvZayblw3z7XbOpz8qQgVLBXOEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAgNwIIFXJDSSAIQAAC7ZtApUKFTr5YwIgPHJFAObRKxnAFCU4dtpzUFdlpwa8coUI5o4AvBCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhDIRgChQjZOeEEAAhDo8ASqFSoIwCSxQBawVnCQKnZAqJAFIz4QgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQKAuBBAq1AUzlUAAAhBofgKZhApjhqmhIwendlYEB6lihRSxQUEw189mOrsoKNXJ/GeyHHsnsetjhf6fPdhRwZLgDAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAE8iOAUCE/lkSCAAQg0K4J5CVUEEhxsUJkxwRL0REZWJM5O0IFT3oQi+fk64qCorYOMdj6ESoEeEhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAIHcCCBUyA0lgSAAAQi0bwJNI1SQYbBihQShgpEu+HaECu37PUvvIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEGgbAggV2oY7tUIAAhBoOgJlCxVELOAIBcrusC4vOybY3Q/KLl+sgC9kmPrbJ9T08TOKearW1lbV0tJS1IdMCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAgZAAQoWQBSkIQAACEChCoCyhgt3RQOJVKFbo5MTIXaxghQqXaaHCHxEqFBl2siAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAQNkEECqUjYwCEIAABDomgYqEChWKFCxhESvkLlKQ4AgVLGLOEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAgdwIIFXJHSkAIQAAC7ZNAJqHC2GFq6MgdKt5FoVxynVQnLTqQ6lakFxVRQkr+1Mumqenj2VEhHR45EIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCECgfAIIFcpnRgkIQAACHZJAQwoV/J0RUoUKfr4ZsASxAkKFDvlWptMQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEI1JgAQoUaAyY8BCAAgfZCILNQYcTgunW5UymhgrSEHRXqNh5UBAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEhABCBd4HEIAABCCQiUAmocKYYWroyGxChUwig0wtq9yJHRUqZ0dJCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCCQRgChQhoZ7BCAAAQgECGQp1DBihSkghUrVkTqqecFQoV60qYuCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABDoKAYQKHWWk6ScEIACBKgnkKVSQpohYoS1FCtIGhApCgQMCEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCORLAKFCvjyJBgEIQKDdEshbqJAOqpPO8ndZkJNc1uhAqFAjsISFAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAoEMTQKjQoYefzkMAAhDITqA+QgVHlbDCFytIEx1z9haX9kSoUJoRHhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAoFwCCBXKJYY/BCAAgQ5KoD5CBYHLjgod9C1GtyEAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhBoJwQQKrSTgaQbEIAABGpNoFKhgt0YoVONdkWw/U6vx1bs7NDgJ6dePk1NHz/Dhkg8t7a2qpaWlsQ8jBCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAKFBBAqFDLBAgEIQAACCQSqFipITKsZSIhfrSlZqOBWiFChWsaUhwAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAIHmIPDhhx+qCRMmFDR2++23V9ttt12BHQME8iaAUCFvosSDAAQg0E4JVCpUUI4+oJZChXTsIlZwGxFesqNCOjVyIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQKB5CTz11FNq5513LujAT3/6U3XppZcW2DFAIG8CCBXyJko8CEAAAu2UQN2FCq62wN0YoVK+CfGmXjZNTR8/o2jE1tZW1dLSUtSHTAhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAQCMRQKjQSKPRMduCUKFjjju9hgAEIFA2gaqFCuWKDRKEBWU32i2QEA+hgguINAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQi0FwIIFdrLSDZvPxAqNO/Y0XIIQAACdSVQtlDBCgPKFShIr6RssXI2tvgW85P8pMOPj1AhCQ42CEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEGh2AggVmn0Em7/9CBWafwzpAQQgAIG6EChHqLDCERJ0ShMSWB8nf4VTsFNKQeviFCsQKwQ+EScHk1/31MunqenjZzgZhcnW1lbV0tJSmIEFAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCDQoAQQKjTowHSgZiFU6ECDTVchAAEIVEMgs1BhxGCzIYLUZXQCSWIBK1IInMKWWbECQoWQCSkIQAACEIAABCAAAQhAoO0ILFy4UK2++uoq7R6l7VpGzRCAAAQgAAEIQAACzUrg/fffVwMGDGjW5tNuCEAAAhCAAAQgAAEIQAACEIAABJqEAEKFJhmodtxMhArteHDpGgQgAIE8CWQRKuw+Zhc1dMQOnkDBVh4XKliRQtxu/e05q5/1Tzh7Oyus0O2JVeZfTr2MHRUSsGGCAAQgAAEIQAACEIAABBwC//Vf/6X+8pe/qEsuuUQdccQRCBYcNiQhAAEIQAACEIAABCoj8P3vf1+9/vrr6tJLL1V77713ZUEoBQEIQAACEIAABCAAAQhAAAIQgAAEShBAqFACENk1J4BQoeaIqQACEIBA+yCQXagwOCoMcDQCpXZLiJCyQgUxOjEiPiUubH1eCCeIn0SoUAIg2RCAAAQgAAEIQAACEICAEqHCuHHjDIltt91WXXzxxerII49UnTt3hg4EIAABCEAAAhCAAAQqIiBChWuuucaU3XPPPY1g4Zvf/GZFsSgEAQhAAAIQgAAEIAABCEAAAhCAAATSCCBUSCODvV4EECrUizT1QAACEGhyAlmFCjvqHRUih6MPsMKBTp0cY8TZuchFqCDxvECRXRUQKjigSUIAAhCAAAQgAAEIQAACxQi4QgXrt8022xjBwlFHHYVgwULhDAEIQAACEIAABCCQmYArVLCF9thjDyNY2GeffayJMwQgAAEIQAACEIAABCAAAQhAAAIQqIoAQoWq8FE4BwIIFXKASAgIQAACHYFAFqHCHmOGqaEjB0dxJAkOXJv2lssC7YI2rtD/MwKDuK7BLy/5csSFDyv8/IKYxlu/+PlTL5+mpo+fYa2J59bWVtXS0pKYhxECEIAABCAAAQhAAAIQaP8EkoQKttdbb721ESwcffTRCBYsFM4QgAAEIAABCEAAAiUJJAkVbKHdd9/dCBb23Xdfa+IMAQhAAAIQgAAEIAABCEAAAhCAAAQqIoBQoSJsFMqRAEKFHGESCgIQgEB7JlAroYKvGTDoXGGB3X1BMiJCBKdAklDBihS8ciZs4QtChUImWCAAAQhAAAIQgAAEIACBRALFhAq2wFZbbWUEC8cccwyCBQuFMwQgAAEIQAACEIBAKoFiQgVbaLfddjOChf3228+aOEMAAhCAAAQgAAEIQAACEIAABCAAgbIIIFQoCxfONSCAUKEGUAkJAQhAoD0SqEio4IgKDBO7M0LMbi9doYL4e2IFvadCajmvZFzIkBbPtMFm6gt2VDBEeIEABCAAAQhAAAIQgAAEihDIIlSwxbfccksjWDj22GMRLFgonCEAAQhAAAIQgAAECghkESrYQrvuuqu65JJL1Le+9S1r4gwBCEAAAhCAAAQgAAEIQAACEIAABDIRQKiQCRNONSSAUKGGcAkNAQhAoD0RKFuo4AsCHF2AxuFdxYUFAScrSAgMXsLuklCQbQ1uJdYWiyGX7i4Ncv3Y5U+q6eNnSDL1aG1tVS0tLan5ZEAAAhCAAAQgAAEIQAAC7ZtAOUIFS2KLLbYIBAtdunSxZs4QgAAEIAABCEAAAhAwBMoRKlhku+yyi9lh4YADDrAmzhCAAAQgAAEIQAACEIAABCAAAQhAoCgBhApF8ZBZBwIIFeoAmSogAAEItAcCZQkVHOGAk9QYqhMqCMeIDsFeuJVYWwx6XKQg2Y9dPk0LFZ6NeUYvESpEeXAFAQhAAAIQgAAEIACBjkagEqGCZbT55purn/zkJ+q4445TCBYsFc4QgAAEIAABCEAAApUIFSy1nXfe2QgWDjzwQGviDAEIQAACEIAABCAAAQhAAAIQgAAEEgkgVEjEgrGOBBAq1BE2VUEAAhBoZgKZhQojBhd0M9QRlBAqSMm40EAXseXjWYGvdbA1xx2DGFFHdlSwwDhDAAIQgAAEIAABCEAAAmkEqhEq2JibbbaZESwcf/zxCBYsFM4QgAAEIAABCECgAxOoRqhgse20005GsHDQQQdZE2cIQAACEIAABCAAAQhAAAIQgAAEIBAhgFAhgoOLNiCAUKENoFMlBCAAgWYkkEWosPuYYWrHuFAhLhrQnV8R1QuIxSDpFCgPPEIrjD1mdeM5cTxf0Tm4Dl4ceXVcA4+pZkeFGaFTQoodFRKgYIIABCAAAQhAAAIQgEAHIpCHUMHi2nTTTY1g4YQTTkCwYKFwhgAEIAABCEAAAh2QQB5CBYttxx13DAQLnTol//u49eUMAQhAAAIQgAAEIAABCEAAAhCAQMcigFChY413I/YWoUIjjgptggAEINCABLIKFYZqoULkp5DIhd8xrRoIhQNhyhUZWOGBlHDtQfCwmAlq/SO+fnVyct1tkxAqOIBIQgACEIAABCAAAQhAAAKJBPIUKtgKNtlkk0Cw0LVrV2vmDAEIQAACEIAABCDQQQjkKVSwyIYOHaouueQSdcghhygEC5YKZwhAAAIQgAAEIAABCEAAAhCAQMcmgFChY49/I/QeoUIjjAJtgAAEINAEBCoWKkjfrDJA0r5iwBUOiDFJYCDigyS7iRcNoD09Q6K/1KsP8XCbglDBYOEFAhCAAAQgAAEIQAACEChCoBZCBVvdxhtvbAQLJ554okKwYKlwhgAEIAABCEAAAu2fQC2ECpbakCFDjGDh0EMPRbBgoXCGAAQgAAEIQAACEIAABCAAAQh0UAIIFTrowDdQtxEqNNBg0BQIQAACjUwgi1BhjzHDlOyokEU0kNpXqySICRGsf6nYNl/8I6IFG9cG0uepl01T08fPcCyFydbWVtXS0lKYgQUCEIAABCAAAQhAAAIQ6BAEailUsABFsHDhhReqk046CcGChcIZAhCAAAQgAAEItGMCtRQqWGw77LCDESx8+9vfRrBgoXCGAAQgAAEIQAACEIAABCAAAQh0MAIIFTrYgDdgdxEqNOCg0CQIQAACjUigEqGC9CMiFijVMVdMUEKokBYboUIpyORDAAIQgAAEIAABCEAAAuUQyCJUWH31fuqDDz4qJ2yi70YbbRQIFrp165bogxECEIAABCAAAQhAoPkJZBEqDFx7gJo/7/2qOzt48GAjWDjssMMQLFRNkwAQgAAEIAABCEAAAhCAAAQgAIHmIoBQobnGqz22FqFCexxV+gQBCECgBgTKEypIAzylQVlCBSkmYoUUkYJkpwoRJFMfRfNdIYT2ZUcFg4wXCEAAAhCAAAQgAAEIQKAIgSxChQsuPEstWvSJmvzg42rWzLeLRMuWteGGGxrBwvDhwxWChWzM8IIABCAAAQhAAALNRKCUUKFbt67q4p+NUa+/NkvPMR9T8+cuqLp722+/vREsHH744QgWqqZJAAhAAAIQgAAEIAABCEAAAhCAQHMQQKjQHOPUnluJUKE9jy59gwAEIJAjgSxChd3HDFNDRww2WgNbtRUOxAUL1u4pE6y3nAtVCm7ZsFx0twZrT/N1a7A+Uy+fpqaPn+FmFaRbW1tVS0tLgR0DBCAAAQhAAAIQgAAEINAxCGQVKvTq08vcC73zzjw1+f6p6s0cBAsbbLCBESycfPLJCBY6xtuNXkIAAhCAAAQg0EEIZBEqXPLzMfofwfXTd/Q/mRvBwgNT1bwcBAvbbbedESwcccQRCBY6yPuNbkIAAhCAAAQgAAEIQAACEIBAxyWAUKHjjn2j9ByhQqOMBO2AAAQg0OAEKhEqWPGA7ZoVCMh1mOduc1AoUhDf5HKhPYwV2qJ1yFV42HgIFUImpCAAAQhAAAIQgAAEIACBZALlChXMYjIdao4WLDykBQsz33grOXAZ1vXXXz8QLKy00kpllMQVAhCAAAQgAAEIQKARCZQjVDD/gq4FCyv0P5/P1DssPKQFC3PnvFd1t7bddlt18cUXqyOPPFJ17ty56ngEgAAEIAABCEAAAhCAAAQgAAEIQKDxCCBUaLwx6WgtQqjQ0Uac/kIAAhCokEAWocIe/o4KntygUHRgBQLlNqGUEMGTOnivbq2epbA2L14n9Rg7KhTCwQIBCEAAAhCAAAQgAAEIRAhUKlSw9yPvvjvf7LDwxuuzI3EruRg0aJARLJxyyikKwUIlBCkDAQhAAAIQgAAEGoNAJUIFabmdY76u55Yiip2r55rVHttss40RLBx11FEIFqqFSXkIQAACEIAABCAAAQhAAAIQgECDEUCo0GAD0gGbg1ChAw46XYYABCBQCYHyhAquXCCsrXZCBfvzjNkFO6gwtAYmk7DCh8cuf1JNHz8jmhm7am1tVS0tLTErlxCAAAQgAAEIQAACEIBARyGQVajQu08vD4l+2q0c5tV/EdOcd+arB/Visjf0U3CrPdZbbz314x//WI0YMQLBQrUwKQ8BCEAAAhCAAATagEBWoUInf25pd+2KzzHfeG22evC+R9WcHAQLW2+9tREsHH300QgW2uA9QZUQgAAEIAABCEAAAhCAAAQgAIFaEECoUAuqxCyHAEKFcmjhCwEIQKADE2gMoUIodXB3bQitpYUKVqQgQ+ntqPBs0VFFqFAUD5kQgAAEIAABCEAAAhBo9wSyCBXGXTRK9erdM2ShF5R5a8r0UjLvPy9PG+Wptw/eN1W9/uqboX+FKREs/OhHPzKChZVXXrnCKBSDAAQgAAEIQAACEKg3gSxChUt/MTbarCJzzJm+YOHdd+ZFy1RwtdVWWxnBwjHHHINgoQJ+FIEABCAAAQhAAAIQgAAEIAABCDQSAYQKjTQaHbMtCBU65rjTawhAAAJlEyhPqBANb57ypE2uSCDq4VyJAsFb0RMYbXkxRPdq8K4KhAortF1+tAkieIlI/drlsSum6R0VECrEMHEJAQhAAAIQgAAEIAABCDgEqhIq+Pc2wb2JTtin4s599z3z9FsRLMgtTDXHuuuuawQLI0eOVAgWqiFJWQhAAAIQgAAEIFAfAlUJFQrmmFYkq9TM197Su3g9qt55a27VHdlyyy2NYOHYY49FsFA1TQJAAAIQgAAEIAABCEAAAhCAAATahgBChbbhTq0hAYQKIQtSEIAABCBQhEClQoVgQY6OHRcKmOqiDmELHLFCmotdzWMX+kjhFc4Kn4jdlTj4i4DMjgrXFhcqTJgwgYU+4aiQgkBTE9hoo43U+uuv39R9oPEdl8DkyZPV8uXLOy4Aeg4BCCQS2HrrrdWAAQMS8zDmRyCLUOGCi85SvXv3CivV9zPmlkbOoTUUVPtGyZ07VwsW7n1UvfbKTHuL45YoK73OOusEgoVVVlmlrLI4QwAC7Y/ASy+9pBYtWtT+OkaPIACBqgj06NFDDRkypKoYFK6eQCVCBfPv3TKPLDLHtLPPmW+8pR6495FcBAtbbLGF+slPfqK+853vqC5dulTfeSJAAAIQgAAEIAABCEAAAhCAAAQgUDcCCBXqhpqKUgggVEgBgxkCEIAABKIEsgoVhowYHCnoLsopKVSQkvZJomZVjxcqGsMJ74sSIoKEcoQKGXZUcGojCQEINDmBvn37qrvuukvttttuTd4Tmt8RCay00kpqyZIlHbHr9BkCEChC4K9//atZLFTEhawcCGQVKvTq3VPLDry7F7uILLxX8e9q9Cm4vzHp0D5/zgJ1v15MlodgYe211zaChe9973sKwUIObwJCQKBJCRx88MFq4sSJTdp6mg0BCNSKwDbbbKNeeOGFWoUnbkYCWYQKl/xijIlWzhwznH/qonqq+eYbbxvBwtuz52RsWbrb5ptvbgQLxx13HIKFdEzkQAACEIAABCAAAQhAAAIQgAAEGooAQoWGGo4O2RiECh1y2Ok0BCAAgfIJZBEq7D5mFzXUChVEcBCswPHqsz+oWC2CbUXMzdMqOIID61fwpCg/I3UXBRtDV2DrDmLpxNTLp6np42e4JtIQgEA7J9C9e3d16623qoMOOqid95TutTcCCBXa24jSHwjkQwChQj4cS0XJVaigKws02c59irugbN68BWYx2asvvVH1DgsDBw5U48aNU6effjqChVIDTT4E2iEBhArtcFDpEgRyIIBQIQeIOYSoXKig/6U7+Ad1P2HmlV6j3Hmlm35zpt5hYdKj6q3Z71bd+s0228wIFo4//ngEC1XTJAAEIAABCEAAAhCAAAQgAAEIQKC2BBAq1JYv0UsTQKhQmhEeEIAABCCgCZQlVHCVCMGPJqFYICU7wtkVH7gZ7o8r1u76uvlpdlsOoYIlwRkCHYtAt27d1PXXX69OOOGEjtVxetvUBBAqNPXw0XgI1IwAQoWaoY0EzipU6N27V1DO3JfoFWThIjLJ8laQmVsk/z7JCqqD+xjn/mn+3PeNYOGVl17PRbBwwQUXGMFCS0tL0E4SEIBA+yaAUKF9jy+9g0ClBBAqVEou33JZhQp2vhg8xKfEHDPw181NmmPOmvmOFiw8rGbPql6wsOmmmxrBgvwbW5cuXfIFRDQIQAACEIAABCAAAQhAAAIQgAAEciGAUCEXjASpggBChSrgURQCEIBARyJQK6GCMHTW4gRIV8i+Cq6iwc8JflwJPLWb3TlBbDqY/TEmiGEqsNawIEKFkAUpCHQ0Ap07d1aXX365Gj16dEfrOv1tUgIIFZp04Gg2BGpMAKFCjQH74bMIFcZdNEr16t3Tv7kxNyXefYl/s+OfdL5/XxLYvYQnbAj7E9y96Oz5ssOCfvrtyy+KYCHhJiksVjK11lprKREsyMI4BAslceEAgaYngFCh6YeQDkCgJgQQKtQEa9lBswgVLv3FWC+umTLqF/OfPTtVOuKFYB6ps905pmuXOLNmvq3nmI+oWW++4wSqLLnJJpsEgoWuXbtWFoRSEIAABCAAAQhAAAIQgAAEIAABCNSEAEKFmmAlaBkEECqUAQtXCEAAAh2ZQCahwnm7qKEjBgc/mARCAQFnf0TRSbO0Jr7ARue7h/3hpGAhjvtI0ngMCRCLE8b0MtxshAohHVIQ6KgELr30UvXTn/60o3affjcRAYQKTTRYNBUCdSSAUKE+sMsTKoR3HNGFYX5bU4QK5n7Judex90P2/kau58/XOyzoxWQvvfBq1TssrLnmmoFgoXv37vUBSS0QgEDdCSBUqDtyKoRAUxBAqNAYw1SeUMGfY+qTmSeGl15nUoQKWeaYs998W92v55hvauFCtcfGG2+sLrroIvXd735XIVioliblIQABCEAAAhCAAAQgAAEIQAAC+RBAqJAPR6JUTgChQuXsKAkBCECgQxEoR6jg7nrgCg2s3bVFIIZrerwfXPzMiL+zeCdxdY4TIxJbfpXxD5tCqGCJcIZAxyYwatQodeWVVyrZZYEDAo1KAKFCo44M7YJA2xJAqFAf/mUJFWyTgsVi3t2Hdxuj095/gcC6QJDg3O/YRWjWx8Z4TwsW7p/0sHrx+deq3mFhwIABRrBwxhlnKAQLdvA4Q6D9EECo0H7Gkp5AIE8CCBXypFl5rLKEClKNP0+0c8LQFJ1j2rmjaZk3FfV2VjCGUOhg/Wy82bPeUffd87B68423fM/KTxtttJERLJx00kkIFirHSEkIQAACEIAABCAAAQhAAAIQgEAuBGbMmKH23Xffgljjxo1T8n8OCNSaAEKFWhMmPgQgAIF2QqASoUJ854SKhQqyB4MJpmGaH1f8X1gq2FHBDodEQKhgaXCGAASOP/549ec//1l169YNGBBoSAIIFRpyWGgUBNqcAEKF+gxBZUIFfxGYNFGv/rILwPxLr+H6psQuEHN01cFCMpPn+Nj7KRvjvfkLzdNvX3julVwEC+eff74688wzVY8ePbz28QoBCDQ9AYQKTT+EdAACNSGAUKEmWMsOWrZQQWqQeaWtyZ1jmjmjl+HOGUNnKeqVLDXHnD3rXSNYmPn6bFtTxWcRLFx44YVKBAv8m1vFGCkIAQhAAAIQgAAEIAABCEAAAhCAAASamgBChaYePhoPAQhAoH4EsggV9hgzTA0dMTi6SMb/AcS0NElYoDPsjyTBzgnOYhwptyJQKZgLMZkjKGcNcnbr8ON4GgdH7OD7P3b5NDX92mfd0qQhAIEOTOCAAw5Qt912G4vzOvB7oJG7jlChkUeHtkGg7QggVKgP+8qECimLyHSTg1sk977HWzdmOmTvc+KLyGShmY1qY4jvgvc+MIvJnn/25ei9WAV41lhjDSWChbPOOos5UQX8KAKBRiOAUKHRRoT2QKAxCCBUaIxxqEqoYOaOembon6VH7vww6GGGOaade8ZjvDV7jrp34mT1xmvVCxY23HBDI1gYPnw4goVgcEhAAAIQgAAEIAABCEAAAhCAAAQgAIGOQQChQscYZ3oJAQhAoGoCtRIquD+EBEIF3dqIvUKhQiSGK2DwaZQjVDjsqoPcVkTaVw5ct49uObetrt31tz5JNreMSTv9tZtRiN3GKPAvYXDrdF2T4rm+dnGVlInY7S9nbjDPKbDYdnu/tzm/qgUepRNuna53yXY77XNjJJVzxTG2zVJXoq/biJS0W5/rkhbP9bc+rk1iWLsbry3bndY+157YZulAGe/txV8sVveMuz/S7VIXw4YNUxMmTFB9+/Yt5Uo+BOpKoJRQ4cADD1Snn356XdtEZRCAQG0JvPbaa+rHP/5x0UoQKhTFk1tmFqHCBReepXr36eXV6c8lvZM3jw2nl3ZBmXbVWe58WQqH1yZlfAK75HuTY/8s1xLPq2PBewuNYOG5GdULFlZfffVAsNCzZ09pAgcEINCEBEoJFdZcc0115ZVXNmHPaDIEIFCMwM9+9jP10ksvpbogVEhFU9eMLEKFS34+Jpjr2QmgnQ9KYwvT3vzQdMSbIgZC12DuaQoajyDPxvGnlaZOO8d8e/a7atKEKer112Z5hap43WCDDYxg4eSTT0awUAVHikIAAhCAAAQgAAEIQAACEIAABCAAgWYigFChmUaLtkIAAhBoQwJZhQpDTt2+sJX2Fw5ngbF1sj94uAuU3Txv4bez/NtJip+Uj5hidQT5MbuUzSpUWG3DvurUiSdG6vF+5/F/7TEN0S+RhohRH46LLLBOcvEcnR+RfEMqk1hfLEMbx13ILTa3zkztdttsAmRvd2KbNYSkCFnbHTbHT8nJ7ZS0UY7Q0bsuwjtcAGZdCwOa906MtanGvp/lIpbvRvGa4zQqS7uLtLmgblO9W6N4+H8TsXZlZW3Ke1HMa5CMV+N0y/iU024dK/5+kPGI2yRuxe12WC/99zI1Yewk9eYD2Z/+tvXWW6t7771XDRw40HSPFwg0AoFSQgV58vXVV1/dCE2lDRCAQE4EnnjiCbXrrrsWjYZQoSie3DKzChV6aaGCmSbJfNH8552lIcbutyiY40i2M7f0pQliDP2dgtZqwvvlpHw0hvJ2WJj0sHr2mZf0dDU+kSsPiwgWxo4dq0aNGqUQLJTHDm8INAKBUkKFjTfeWM2cObMRmkobIACBHAnss88+6qGHHkqNiFAhFU1dM7IKFYK5oZkEyrwyaY4pc0Kv+WZuaNPhrDIyZ3TMXjxd1IT3g7hzTDsdNTss3DNFvfbKm1VzWn/99QPBgvx7BwcEIAABCEAAAhCAAAQgAAEIQAACEIBA+yWAUKH9ji09gwAEIJArgSxChd3P20UNHTE4tV53AY11KrlwxvwSYn8OMSucbdHg7MZNjWd/qXEW6pQjVDhFCxVsK6Ris9xHXlxj0KL0hOueKYZxylaPG1takFTU2tJbmJxjYwdtFjdrTCpiKyrmkxDCFnPDu7aCqiSzSB02y8SwgayxIJg2lIhni8RDJIUO6ow72yApZ9c9iCG+bka8bN7tjsfPcO02L/gzc43xGEnQ4j7+tRvGFpOsNHs8zPJly9X9F09WL9/+ajwr9XqDDTZQ9913n5KFOxwQaAQCCBUaYRRoAwTqSwChQn15F6utWqGCO2cJFppJhfoexd6myMwm8NOJ4CowhjYpY++BvEVkJpjpgnH3Xxa+/4G6d+IULVh4WS1fvtzkV/rSv3//QLDQq5e/c0SlwSgHAQjUjQBChbqhpiIINBQBhAoNNRypjalWqOBME2Vy6M0l/XlgnnPMoB4/9jtvzVGT9Bzz1ZerF7oNGjTI7CJ36qmnKgQLqW8VMiAAAQhAAAIQgAAEIAABCEAAAhCAQFMTQKjQ1MNH4yEAAQjUj0CbCRWki+EvK3ohubtMOey/XahTUqggRfwYVQkV3GYEv9ZI7LBN4Uojx6aT1j3SFWuMumaKZ4u4IdKakVin6yzB3EB+cNeUGMM2Qs4Z4rnukdhOhrVH6pP8ICPB2TFFXLO0yfWxdcTiuZfWxS2WWqd1Fge3gGt3gltzpO/W6PiZZIZ4togbIq1YYp2uswRzA/nBXVNiDNsIe3ZjuoVtvnN2s5OKReqTcraA66zNj/z3Y+rp6551IhdPDhgwQE2aNEltv33CTjHFi5ILgdwJIFTIHSkBIdDwBBAqNM4QZRIqXHSW6tW7p56GeBMRc38iC8bsvMR2R2ySdjK8pLVbR5nSaE+/vHcK49n7n1CoYII6Yf0S+vT+gg/Vffc8rGY8/WLVgoV+/foZwcLZZ5+tECyEY0UKAo1KAKFCo44M7YJAbQkgVKgt37yiZxIq/GKMqc6fKeq5np7cyXzSm+qFTRGbXDkZXrLQ13j65b1T6FM4x7RxbVV+CX165615atKEyeqVl9+wmRWf11tvPSNYGDFiBIKFiilSEAIQgAAEIAABCEAAAhCAAAQgAAEINCYBhAqNOS60CgIQgEDDEchDqGB+RHF6lioqcHyCpP2RpWBFcuDh/RCTlm/Li7vvU65QIagptvjZ2OU3mjR7UNBJZPWN+3m/BTmBoslizUhDE43gXyXUY2LH2yPucd8sPrFK09qdyDRWNriMt8NmJLVH8uL+cb94vo2X5RyPZetLsyfFzOob96uw3VKsbu8R6W+Z7Tbty8opyU9sOsj0P85Qj/728cL6U8r06dNH3XnnnWrPPfdM8cAMgfoQQKhQH87UAoFGIoBQoXFGo3KhgtyixCZn+rrAprsqtrirELC+Jor4+FgCuzbYtE45MaxnmL/wfREsTFHPTM9HsHDeeeep0aNHq969e/ut4gQBCDQaAYQKjTYitAcC9SGAUKE+nKutpXKhQji/C9qQMMf05pbu/DDwDuaP6XPMsFw415TyhXPMd9+ZqybdrXcyfSkfwcKPfvQjJYKFlVdeOWwwKQhAAAIQgAAEIAABCEAAAhCAAAQgAIGmJYBQoWmHjoZDAAIQqC+BbEKFYWroiMHB4pj4OuQsq6DtDx9pIoZS+UHlgsdZdW3LeWavZRUJFQo6VYNxCH/vybyYuqAVecQoCFrEkEd9bgypqhlZN2u76826Gk7u+6TCdr942yvqgZ9OViuWZQvQ0tKi/va3v6lDDz1UWs4BgTYhgFChTbBTKQTalABChTbFH6k8q1Chd+9eQTlz/6HnLe59iMm0YgNv5ZhnklezuMxcRl6kvJn+2LOfa+NKGOPhz5Gs3S4ik/x4+oOFH6p7J05RTz/1QtU7LKy22mpKBAvnnHMOgoXIyHEBgcYggFChMcaBVkCg3gQQKtSbeGX1ZRUq+LNBU4mZ68n8z5vkhRXbuaJj96aBoeDAOgd2MdhyfqaNK2HsHNOePRdTWopJYWOy6Xffmafuufsh9YoWLKT9274Xo/Truuuuq0SwMHLkSAQLpXHhAQEIQAACEIAABCAAAQhAAAIQgAAEGpoAQoWGHh4aBwEIQKBxCFQtVHBEA2m9sj+ESH7ajxnWJy3fxPZ+HclXqDDhxLRm18Yuv/NkW0OdXn8eMdKjJ+fkUWceMZJbl2zNo748YiS3Lt2aR515xEhvYXJOHnXmEGPm/bPUxPPvU8sWL0tuZ8zatWtXde2116rhw4fHcriEQH0IIFSoD2dqgUAjEUCo0DijkUWoMO6iUapX755ho/U9ibktkXNojS4Gc/Miaa+AKSd2N8+PZe+LdJa3iEzsNu0V9BeQeRni5x1eQq4/WPiRunfCFDX9qeerFiz07ds3ECzIjlQcEIBAYxBAqNAY40ArIFBvAggV6k28svqyCBUu/cXYSHAzB5TpXHx+6F4npYO5oBT156f27NRQMMfU5YLZrIkhc1NbIJoWq+R5ggW9w8KLr6f+G7+NUOq8zjrrBIKFVVZZpZQ7+RCAAAQgAAEIQAACEIAABCAAAQhAAAINSAChQgMOCk2CAAQg0IgEsgkVdjE7KtSi/fYHkRVlrd73fjWR16RyZe2oMOGEoFuu5sL+eBNkxhOus5sX/qITWI34wv+hx/Y3yLQJN15CDM+tUOEQLeZXYmMmnd0Cfr5ETeqvy7bydhe2Wap1m5FUt980cxJ+iT1L4VSq3ZF4KTHS1CTltDvSSbdDSXVqTCs6hawSeUcrdyM66TCGNUaLJZK0rt7ZLeDnSNSkcSrF2hR34yX2XUdPaFa0WIKD3zY5RcZUX7/75Fx159kT1eIvlzhe6Unp229+8xuzCC/dixwI1IYAQoXacCUqBBqZAEKFxhmdaoUK0hN3luLOl2zank2vfWexSTKSZxxCWyTf9xcXU8aJ4xeTHJP0pls6vr4UwcIkESw8+VwugoVzzz3X7LCw6qqrhtWSggAE2oQAQoU2wU6lEGhzAggV2nwIMjWgEqGCTN7MPM6bzCXOMd25o5u2zmKLzCGd1lp/N9/axM2kvemklw7KekavWV4brWDhpRdeq1qwsPbaa6tx48ap0047TSFYCKCTgAAEIAABCEAAAhCAAAQgAAEIQAACTUEAoUJTDBONhAAEIND2BPIWKtgfOMzi/BLds77ilsXfhitVriyhwt0npEok3Hps3W5b/d9ugiy7RNwtl9gvXdD72cgran0i8fwfpdz6JO362Pq8KN6rW7drl3RSPW4Mt6z1dWO4+WnxvF/UvFJujErbXSpGWpvS2p0WL6ndbptNf92gfjpev3Wx9aTFcMtZX1vWnHXBct4jUsbGcet0x9fGd+u2NnsuFcMta31tWTm7+XJtfdw2JbE2ZeXFP8ppt61Dirr1LHhpofrnGXerrxZ9ZcOWPF900UXqF7/4RUk/HCCQJwGECnnSJBYEmoMAQoXGGadchQr+wjDTu9S013eZ58l0Pz53klxrk7OZ24ij2J0X32SsYdpzsNc2jljNDgsTp6inplUvWBCRgggWfvCDHygEC0KXAwJtQwChQttwp1YItDUBhAptPQLZ6q9cqCATRK8O/ySTQ2sqkvbL+L7uPNC22NrcOaZbh/glzSP9yIl5c96dr+65+yH14vPVCxYGDhxoBAunn346ggU7aJwhAAEIQAACEIAABCAAAQhAAAIQgECDE0Co0OADRPMgAAEINAqBRhAqeE9OT1qanE7J/rjiLlK23rkJFSSg/YXGDx6vz/6gE299sfZ5Yf2SuvNuWRvPVOfX7dbp5rvl/OZ5xbwKQlOROtwYJrbUGfMPAwkOrwVpbfIaUBjDK+VFcutMih3YYu1Ii5HUpiCGn0jyceMF45xSZ2qbJX6DvUdMk/x+Z253Sr8ljBvDMGui98ii2R+r20+7S33+3uc+kdIn+TH56quvVl26dCntjAcEciDQUYUKCxYsULIAodgh+YccckgxF/Ig0JQEECo0zrBlESpccNFZqlfvXlHRgMyH/MlksHTMmpy5oZ07+a6mjPW381PH3YAJ7TGhQszRu9Q+QXDLNbTZWJIjbh9++LG6VwsWnnziWbVs2TJboKKziBTOOeccI1ro27dvRTEoBAEIVE6gIwsVRo0apWQumXYMGTJEXXjhhWnZ2CHQ1AQQKjTH8GURKlzyizF6fuZP5GRCZ/7zztLLMM9P+65enjgEHmFZY/Yc43NEOy+Us/FwzhLTHl457ePUJ3m2fEFaG+bMec8IFl547tXgoSXiV8khgoULLrjA/HtBS0tLJSEoA+lJ+YEAAEAASURBVAEIQAACEIAABCAAAQhAAAIQgAAEIFAnAggV6gSaaiAAAQg0O4HyhQryK4W7dDkvAnnF7aQeu/wJNf3aZ0s2bLUN+6qT9Y4K9neXSnoVKSsBrMGv3V4GsfWC8PgvPdZHiiSE8GgXKRfE9ussdYrXJ8KEtDalxU6K4f5gZfuSFjstbrG2F9QZc7b5Qewi/XLbl9juUrFj+cUuC9oVcy7Iz9BuW8aGCvpsDf7Z+qXlx9yDS1tODKZskTalxU6Kkcg6JXZa3KCRCYmCOrXP5wu+ULd/704looWsxzHHHKNuuukmJQvIOSBQawIdVagwe/ZstdFGGxXFe8UVV5hFsEWdyIRAExJAqNA4g1aWUMFMNPSL+c87S0+CJWJiiq/okny7CMxPSxk5XF+3mLWbck6GtXulpbyJ4p+t1Tu7vjYt7jb94QeL1KR7tGDh8eoFC3369DGf1eedd55CsBAdB64gUEsCHVmosPHGG6tZs2al4hU2d999d2o+GRBoZgIIFZpj9LIKFfTsLJjTlTPH9KaBwSw0mOMJHTvf89IhL2uXc5g2XqGTTlUzx5w7d4GaeNeD6vlnX6lasLDWWmsZwYKwRLAQGSIuIAABCEAAAhCAAAQgAAEIQAACEIBAwxBAqNAwQ0FDIAABCDQ2gfKECuZnEL9DlSwjLsbCxo7GtT+cuE/wT4/ixfB2VJiR7ubnxIUKYo7ULguo44ezWEiyIq22/o6PzRffSB9K+Nh+Zy4njvaw7bDXci5Rn3Et5VMq31QT9rhUfwvoVtLuDG3K0vdE3mmxDSz/pUSbxcsSMf21/mmxbb4paEuGMcRsuUba7GXIa/pYe7neq1uPtefQpopZSxsS6s/rPfLVx1+rf33/LrXgpYW2tyXP++23n7r99ttVz549S/riAIFqCCBUSKeHUCGdDTnNTQChQuOMX1ahQm+9o4I5/PmKmYf5UzXvpF+9/wrnNLqM7+r7+FfG30s70yA9JbI2v1xwLS3wy0rKT1p/0z5jd32ctDjoQoFFpz/SOyxMmjhZTXtsRtU7LPTu3TsQLKy22mq2OZwhAIEaEUCogFChRm8twjY4AYQKDT5AfvOyChWCmZlM7Mx/3lnCeHM2axeDZwnyIvM68ffzTREv7RRJnGMar/BFQgfVVDTH9GPNlR0WtGDhuRwEC2uuuWYgWOjevbtpIy8QgAAEIAABCEAAAhCAAAQgAAEIQAACjUEAoUJjjAOtgAAEINDwBCoTKhQsH86hn94PKDGpQPAjil2cXbwiL0ZmocIG3o4KElNKhr0KU+n1eXWFrY6XsTkSIZ6XHtXNkR+YVqSWDesPo4cpN0407ZZL8q9lu8O6pU1h7WEq2lb3KixbyMRtczSyG6FY2v6YVxhbSrl12yjltVlKFcZ2250lnq07PNe63YVtlrrzaXdybC++rSGkEqbC3sdT7jjF/TupxV8uUXedM1G9O21uvGDq9c4776wmTJig+vXrl+pDBgSqJYBQIZ0gQoV0NuQ0NwGECo0zflmECuMuGqV69XaEi7IoTKYd/sovO2+R69Jpr+/G03e2aVvWLgqTs7WZ2OGFrToA6ZaxRmsLriXhttnWr22eYGGKFiw8o5YuXWaLVHQWwcLo0aOV7LDAHKoihBSCQCYCCBUQKmR6o+DU7gggVGiOIc0iVLj0F2OjnZG5n8zV7BzN5oq9ZNpzsPNKuZK0hLOHnRvK2Zj1i+tvrhx/KeeWca9tTGPzMowpXt88s8PCQ+rZZ14KHrzili0nPWDAACNYOOOMMxSChXLI4QsBCEAAAhCAAAQgAAEIQAACEIAABGpHAKFC7dgSGQIQgEC7IpBNqDBMDR0xWPc7vvjXRSG/ZMTzk2xSJs3uxiuVTo/hCRWeLRVArWaECscX+EkvJLo5krpk82JnEVNEf+CJOcilE9xJJjhGTYFQw//FJ2if4xbEi7dZfHSBIN8pI0nTbveXpFh+MKx+DMlOqj9eTMqZxehO7KLl4u32nRPb7ce2P5gV1C0GG89vd9G63QB+bPtrXlK5SJtsPTZGUgGbZ31L+fj5kXpsjJRzU75HdF9Muyt9jwgLzSqRkzbK+899jyxbvEzdc8EDaub96Yta4ni33HJLde+996p11lknnsU1BHIhgFAhHSNChXQ25DQ3AYQKjTN+uQoV5E7AzvF0wibFGKbDvts5islzfFy7TZsYfpCk+w3rFz+HtXkpmy9Xtq2u7eNFn6h77p6snshBsNCrVy8jWBgzZgyChfhAcA2BHAggVEi/pxM2d999dw6UCQGBxiOAUKHxxiSpRZULFXQ0f5IWzh/DuaQ7b3PT4WRTinsl5dWmpY02LWcb29j8C5svvvawtvjZ5ttzmG8tYX1imT/vfTVR77Aw4+l8BAvnn3++OvPMM1WPHj3CCklBAAIQgAAEIAABCEAAAhCAAAQgAAEI1J0AQoW6I6dCCEAAAs1JIB+hgv15w67CFhbWJuksdvHLeqTF9spnFyqsqobfdbxuaRjPfcq7a3dbZn3i+Ul2a5Pyrr9rt7Htjzr22mJL8i0Wz63HxnJjuPnV2G3sSLudoXZjW98oBW8hebwvoW+YH/dxYyf1J8nmxjXx7OosuSjR7rR4rt2Nb9sXz0+yW5tpU8p70caOsBaj3243hvWVs1u/6+Parb8Xynt189PKZbHb2JF2l2Cd1m63TTaunLO0wy27fPly9eDPHlEv3faKG6ZoetCgQeq+++5Tm266aVE/MiFQCQGECunUECqksyGnuQkgVGic8atKqODP27wppb6f8P4z52AW5sw3zR2Hf9th5iZO2nErXETmZ1qfYF7jlxeaNp6dc9lznLQXwyto0zauieLHXPTRJ2rShCnq8anTq95hQQQLZ599thLBQv/+/eNN4hoCEKiQAEIFhAoVvnUo1uQEECo0xwCWLVQwczA9o/PP0ssgrW3WHM4DjcWfjYqzxyWYE5pLG8/P8yd9Mk/04tlztKx35ZYJ45SaY/pV6MJhGTctgoUJd4pg4cWqd1hYY401lAgWzjrrLAQL7qCRhgAEIAABCEAAAhCAAAQgAAEIQAACdSSAUKGOsKkKAhCAQDMTyC5U2L5IN/1fQ+yqaeNpbXLhrEwO8uI2k1HGi8RPjpGXUEEa4/9kE7TLqzGs1+a7i6VtubivGy3ubyuw8ey1nLP4uj6lY3gehe3zWhi323huHW77JG19XHuav/WN51u7jRFvh60lbrflovGsNZ1fOe0OoxXGc/MkZrb22d7E44XRov2xVMJyoSUeI8wJo0V9XLv1jtbnecT7Ir6SE7e78aJxbPTatDveDltL3G7bF9h14rErnlTTx88IG1giJT+ATpw4UQ0ZMqSEJ9kQKI8AQoV0XggV0tmQ09wEECo0zviVJVQIV17p2ZB/yEIvc6FfvP/M2cxJHH/xDt1Myvf30q6rXQDmLiIz5YNifsIPauc5fkOC9rgxxVWO0CbtdusuTIu/CBbunThFPfaoCBaWiqnio2fPnmrUqFFq7NixavXVV684DgUhAAGPAEIFhAr8LXRMAggVmmPcyxIqhBO0YL7ozSWlr3qOJv95UzWddC58FCZLO/gufhHvypYzkfwLM8e0ab8K7xRECOaJpgrrq7Pt/NHYnRfPReaXXiTzmpKWPLvDwjPTX6hasCDzSitYkPkmBwQgAAEIQAACEIAABCAAAQhAAAIQgED9CCBUqB9raoIABCDQ1ASyCRV2UUNHDE7vp7f61/wQEjqFP27YpdthXlLK+ttgST6OTdxsEccsybKECnfqHRX8H1ykrFlkXdCEeEW+gzHbPG2Ll4vke9GNj7bbn48K6nPCSQk5bPuCBeBSjxNDfAriiDECyGmc01/TaCcrLGYboi0rfAenzkh9jmvAoIhvat/Dyk3KewnrjvTHtsnx9H8N8y26nBSNt0Ny/ZCJeOL+tnqHWaTvfm2RthmbLSgXFpC22bptOZNl88Xo+6S0wxSz7k6sdvEe8bvvjpkxJY11wNQW0uc0luJij4jPCvXM9c+rR3/zeOG4WP/YuXfv3upf//qX2nvvvWM5XEKgcgIIFdLZIVRIZ0NOcxNAqNA445eLUEG6I3NF779gTmLnZ7a33jTEzoSliLGYbCcZ2CXfs3t+oU9yDN85KBP6ey2IXktsN25hOmi3zvp40adq0sTJaurD+QgW5Mm3sqAMwYKlzBkC5RNAqIBQofx3DSXaAwGECs0xilUJFaSLep5m52pmjulN1XRSJ6KTOrF4/nLWR1DOpI3JvFi7nMO0k+9Fivj6F85JyoZlJBVe2zzPwbMXpm1pyV/w3kJ19x0Pqqefej4XwYIIYkUYi2DBUuYMAQhAAAIQgAAEIAABCEAAAhCAAARqSwChQm35Eh0CEIBAuyGQWahwqhYqxH6ICCDYBdORfPfCOgQlEhJl+Lvh3GJ+1KqEComLoiWwW5HTAPtrTFo5my8hHB/7g5BnduKJIXak+abZo8Vtu506UtoUKZfiY+tc4fQlUs65sL5icv2t3bU5xXTSttmUDLNS2uQ4hEWd9tn6TDTHHpaLpqy/2z5rKx6jRLvT6k7pV7Y6vban+abZYz32LxvvPeLpNpx2BQ0vwVr8SvH281+54zX1wKUPq+XLlgfRiyVWWWUVdcstt6jDDz+8mBt5EMhMAKFCOiqECulsyGluAggVGmf8sggVLrjwLNW7Ty+v0Xre5s5CZGWWuZb5nPefPx917H53vSmfU94PJBYvz1bhZcg8zpaRnNDHz/eN5sqP5ZnC8nItR1jWXPk262cuxcvxi+bZOWUoWHhKLVlS3Q4LPXr0UFawIDtXcUAAAuURQKiAUKG8dwze7YUAQoXmGMksQoVLfj5Gz730nEv/35t5OX0Tm53AiYtkmbPvafPE7Gf6ORE/xy2I584x3Xy/Fr8uv01OUOsbtCuoWxonh51LeoWsf2j3fMyrH9fGem/+QjXhzge0YOEFtXx5tn+fkzhJR//+/c0OXiJY6NXLn8MnOWKDAAQgAAEIQAACEIAABCAAAQhAAAIQqJoAQoWqERIAAhCAQMcgkFmoUPaOCsJPfnVIWmScxrYMfwnr/6gRj1auUEHKy88vwY4F8YDBdVL7bCOK9TOpnK5T/2LjLoYPqklIpLUvzR6GSGtfcpvCcpIq9JH65CjNyrglcs0Wo7BuG7H4e8prX9ynXNZJfSzNWkoltTu5TV5/7GtSuY77HvFIlvqbTGaWPAaWsxfZuwr/ZmdNfkvd88P71dJ/L3MdU9Ndu3ZV11xzjTr11FNTfciAQFYCCBXSSSFUSGdDTnMTQKjQOONXrlDBLqYKeqDn82amJyuxvP+8LGuXK0kbJ3HxE8buu1of7zJhEZnnbGN4cx3/1YntFzcn2874OdkntFp/saSlJe+Tj2WHhSnq0SlP5iJYOPPMM80OCwMGDJDwHBCAQAYCCBUQKmR4m+DSDgkgVGiOQS1LqKC75M67TA/NHC+YQAYzyMDPzDvNi+ceeEgwYzKnwF/M/mRSzn4ysIUlxE+uQh8vL2rzYvgVhQ5BWePtZNu6PXuY4dolb8ECESw8pKZPe65qwUK/fv3UmDFj1OjRoxEsCFwOCEAAAhCAAAQgAAEIQAACEIAABCBQAwIIFWoAlZAQgAAE2iOBXIQK5YIpIjIwoez64fB3ixI1iKMtpFQlQoUSFYTh3TbpKm2txhzLszHFx82KXjhNjzjZ0lWeIw30Y7ntjtfp+ycVq3u7Y22zD8g3ZjfPNjYJpetnUYp/kt3mV3q27XBja1vEHMuzVRU0yfVLdbIZVZ4jDfRjue2Ot8X3TypWwDXRqcr22uJJsbVNzKbJbrutr86zySDbT8ydPl/dec49avEXi20NRc/yY6osbjz//POL+pEJgVIEECqkE0KokM6GnOYmgFChccYvF6GCnXjoczi/cCQJzmIw6XmQ4zt7xQNrsGAsvkgsXMjlFYznu1Stb/yc7BOx+gvMdDu9Ckymm7beYvvkk8/UpAmT1SOTp1UtWOjevbsSwcIPf/hDhWDBUuYMgXQCCBUQKqS/O8hpzwQQKjTH6FYlVPAmh+Gif33tzf503/X8y6bN/My/CK3i4zEyp7i/F8KZ5+mSNqBf0Lt27TaedrSx/ULxOaJ7HcaVZgeVpKa9WrRv507q/QUfqrvveEA99cSzuQgWzjvvPCNY6N27t62GMwQgAAEIQAACEIAABCAAAQhAAAIQgEAOBBAq5ACREBCAAAQ6AoG6CxXsKmGBG/5GEUVtfdLyI96uk1ewbKGCrS+tTW6+66PtweJ5aYZtiuNv800xmx+LIZfB8f/ZexNwy6rqanQJYgHVUVX0SCMitqiADfaJj0STiBowKsaoYPSXVgQDKgr6yTP/e/EzgZfE5PcTjT2N0lRDNVTRFoqo2EZF0SAqTVF93/LWbMZac+2z9+nurVvn3Du3xd5rzTnmmHONfaxa95w977EYGA1fykG+Jnu7OKoZsTEXp0NOw7fT6jY5uEzkRs2oDXP4m+qu8KFu8/lXvi9N3MhV9dPc5E8w2JJBB7YWYKhutXNNxo5w+Gk+KnUjBxHW1UR2HNZPNo3lmsgX52wCp8F3rNtgOR04eKIni4Hf2ggGexdxHEqnGMNhdKrwoe46rR/9+bJw/fvmhg0rNtpsbccXXXRR+Md//Mfig9a2Ae50BSoKeKNCRRAz9UYFI4YPx5UC3qgwOLez20aFqdOn6t5CHwNLG42458A4XmXIZ14k5nLN62YWhRWYCMGDXODFniXHSGDVT+xanRaSudgHIprEo8zDFraLT+aVkBQjmJiNAPEPNyzMkYaFLVu2Jp5+BtSwQA/3XXjhheHAAw/sh8JjXIEJoYA3KnijwoR4ofsiWxTwRoUWSQbS0G2jQtxMpf2j7AlpOeVej6biE3tCpNgsQd4v5hhElXs/2scJk144bzFGYPagtLQnBCcqsHPww0dXslkMfNZGjQqYP/LIsjDn+pvD3XeNvGFh5syZgRoWzj333OANC1Der66AK+AKuAKugCvgCrgCroAr4Aq4Aq6AK+AKjEwBb1QYmX4e7Qq4Aq7AhFFgxI0K9iFg8wFGWwER0w6vDxu35UlOIgJpj9+ocMOpiSUNSrpkbhp0KpUejJYPZ5oYRsneqW7j54e145xMTceY1d1UAOw91N1Ys+EA7YiuPfL1/RrpMU/HNXXiM/7x+hrhvypondVD177ygVXhuv81J6z549oqonH+7ne/O/znf/5n2H333Rsx7nAFmhTwRoUmZULwRoVmbdwz3Ap4o8Lg3L9+GhXkYbG4cdD9RNpWxA0/HqqyKyRbxmQPsOwzGNgJiTH9LJFYOI/wwM/YnCXVVuWwDsQSt7VLjNjER+N85DhdL8UzRwir6RsW5twablvy7TDShoW99torNSwcdNBBuQAfuQKuACvgjQreqOD/V5iYCnijwnDc934aFWg/xfs93VfpJRp1z2WWzj6yw5YGBJdJFZPs4uBIsmFa5FYOApksNElH5stG2DjOcCBITJExh8CV6zaNCshH37AwN37Dwnfu+kHYsX1HiulnMGPGjNSwMH369H4oPMYVcAVcAVfAFXAFXAFXwBVwBVwBV8AVcAVcAVdAFfBGBX8puAKugCvgCnSlQN+NCrkvILUI4IONrhITCBw1H07UcwCIQMNhApZe/p1wz+fvNZb64Yyn7BPecf1bo1N54wUZKOJxflJbP5Cxjho6qUjOxQc4NdiqSdOo2ayNLFyTSR7dj1eEq36403PdsQD7QVK1vqZ5u7oLvpqaeWlmWbQkrMt+MNaYWzXoWWsiTBKngaTpQmsCWr171rrfuotSi8mYvUZaXouiWttzu9dIwReXhPvPC1JWqzVJB8zOfI1Q6rWPrI/frDAnLL9/Rdv1WefJJ58cvva1r4VJkyZZs49dgY4KeKNCs0TeqNCsjXuGWwFvVBic+zf6jQq0trzJ5VHc0CSLDuxeBmNgsI9OV6ZUjggCXjKxgYZ8KCqVAI7k180V58K42HApjwCKfS95Eh+lrcZzjKRevXptbFi4Jdy6+DuxYWEL0vd1pYaF9773vfwNCwcffHBfHB7kCoxHBbxRwRsVxuPr2tfUWQFvVOis0SAgdlWjQnWfaLd51b0b9oO67Sv3mCYw7S9JWOz3jJ/N1X0hQSsYwfG54x7TriPljKGPPvJY/IaFxeHbd31/VBoWzjvvPP6GhX322YcK88MVcAVcAVfAFXAFXAFXwBVwBVwBV8AVcAVcAVegRwW8UaFHwRzuCrgCrsBEVWBUGhX0uWn+/EE/sOhKT/u8dcc4CzCBZoicPTUqXKeNCoae1sEPWOMp6zgvPiBBInPFA+tiimjDZ2AtQ6RgRzGJlsShfHGt/KA21mySAFr6O9QNPq2q0xpT8RyXZipWIkkO8BVaktfWTYWjDrMuA0l8GIhMAHdYI4Loauvm8MyRtabyYlGMtQHRBpEjFUMoHPeM3SWGUtpjIF4jscTifnSqGzqkhYzCazvmxDHIr5FNqzaHG86ZGx7+8SMot+P11a9+dbj++uvD1KlTO2Id4ApAAW9UgBKtV29UaNXELeNDAW9UGJz72E2jwkUXnxWmTpsiResmNe9VsTeSfWBhxzKjMW1/sPcinxnnON2LkluN6coxNVyJnACtcWKVcy2XTc7xJRbxiE11I69Zh/goQnRZvWpdmD93SbhlcfyGhc0ja1jYc889uWHhoosuCt6wgLvi14msgDcqeKPCRH79T+S1e6PCcNz9bhoVLr3sAlmM2YvJUDZZaUx7LTapHRJEo1iigTCYmbHEIY3GqxF7O7bWcQkc2Vr2pslB6Rs4S4zMgIUvzVG35k12ArIv51n2yPIwO37Dwrfv/F7YPsJvWKAmhfe///2Bmha8YQF3xa+ugCvgCrgCroAr4Aq4Aq6AK+AKuAKugCvgCnSngDcqdKeTo1wBV8AVmPAK9N2oQMrRg9p1R+WDjALST0wiIOIKQWVK0N4bFShKP/GgIR14AF1mcraf7lh78QS8OhqxRaBZTs1CCJq0jIOONUWOOpqmWjryVWq105QnDbI31UymLurutY4qnvMVSXMtdlSUWkwEZSlq3AyyWlbrIID1C6ueI2GVs+e6qwRK3anuoqaaOoimwCgvXXpao4njWMxr6rY1D/BrZOvGbWHO+QvC7779IBbT8fqCF7wgzJs3L+y3334dsQ5wBUgBb1Rofh14o0KzNu4ZbgW8UWFw7l9PjQpmv5S2MtEm5mihP9mRtvH2IavmcdYEGLpiTF6MTYqYQ/LmaIPLxSS35cDYFG2HKZ/NLemacwKL1JLjCWFN/IaFm+bEhoWb7wqbR6Fh4T3veU+ghoVDDjkkrc0HrsBEU8AbFbxRYaK95n29ooA3KgzHK6HvRgUsz+4DaeulG8DUjBBxaS/XdgzCjKc4xDKtkmuKCKQ/fMrBJgdirRM25oYDRXMsjLkOsiCO0xk80PCLi+rmqHTlb1iIDQt33UENC9sR1teVmhTOPfdcbliYMWNGXxwe5Aq4Aq6AK+AKuAKugCvgCrgCroAr4Aq4Aq7ARFPAGxUm2h339boCroAr0KcCXTcqnHYsf1DRNk3N88iMxycdeEaacNXPO4CpJgBnJz/FKWbpv3wn3PP5e6tMLfMZR+wT/i5+o0L1cxBOibw2qqkGwlTx7bCWsxqnvo41Rf5qimGou+O6oE11cbDTtapZO2y7OPV1U1M3GKZrV8tY1x1rqZbjrxH7gmgYV+7T9q07wqKPLQ73LWh+EKbK9IxnPCMsWLAgHHbYYVWXz12BFgW8UaFFkmTwRoUkhQ/GmQLeqDA4N7SfRoVifxU3iTynzSL9SU61x6XiASteNcMUZMZFHNzEnR3lmMgMjrn1hBhc4bNzDiV+cuaTqb9SdwRxKRHLURwD5hJLeXLZGHNUWLNmXWxYuCUsWXTnqDQsvPvd7w4f+tCHwpOf/ORcjI9cgQmigDcqNP98RtrMmTNngrwSfJkTTQFvVBiOO95Po0KxvUr7Kd58pb2V7KhEg7S308Dk4xAxtu7JZN+WYiNVMSZq8OVgTggcrmwkuMHR0NYBMgOp4JGs5KnnjswJzokoO5e77NH4DQvX3xyW3nHPiBsWpk+fzg0LH/jAB4I3LOBO+NUVcAVcAVfAFXAFXAFXwBVwBVwBV8AVcAVcgXoFvFGhXhe3ugKugCvgClQUGJpGBapbP4wolmAfKlZ/r40KTB1j6355fJFrjCf04UunmrrBjHHZ/KFRu7rxoVI7zK6omXK2q2kYtaY1DWPdg/YaeXzH4+HW/31H+Mk1/02SdnUceuih3KzwzGc+syu8gyauAt6o0HzvvVGhWRv3DLcC3qgwOPevm0aFCy8+M0ybNpV/FkkPXmEJcdPCP4LQicZpkn90SQ9vsU8COUrnGCuTchAd8ZkgSUHnhBE2wdIYHPi5CfG4JryAJcLWbNKVMeKgctiuuBIj7LChdK6J4lBUhK1di4aFpWHTps0S2Od50qRJAQ0LtP/ywxWYKAp4o4I3KkyU17qvs1TAGxVKPQZ11k2jwiWXnS/7o8o+idfE+0AasVP3fnY3Ve7JoAP2XRIZZ7xn41PaP9JeDfu1FKcbN73AnHCWl7kTXrgRgPiML3PbWInRGiMsx+jaQKpX1FzNwXGKWbZseZgTGxbuvH3kDQvTpk1LDQszZ86sVONTV8AVcAVcAVfAFXAFXAFXwBVwBVwBV8AVcAVcAVLAGxX8deAKuAKugCvQlQI9NSpYxvJziNbfcg9stzjCV7HgsM0I7XCK76dRQUIlkX1YHR+CoJSxv9rF1wmU/YNTd66pm5vaqW7y40Oonav/6Na9c2u17J3qzv5OWlvWnTvONQ3Ta+Tb//7dcM/nftC1NPvuu2+YN29eeOELX9h1jAMnngLeqNB8z71RoVkb9wy3At6oMDj3b+SNCrSTiXt02qbHDav92QE7d7ZhYpYOLOLxkBX2veQHxoSxDRjYqxz4uQrxuAJPV3CITwqETfy26OxnvLrqeRXLJCINnYUbgeQMYd2a9WH+3FvDzQvvGJWGhdNPPz18+MMfDt6wIPr6eXwr4I0K3qgwvl/hvromBbxRoUmZwbKPvFGB9mrYN+U9oVp4sXZPZlePuOr+MNNlvmocMLBXOeweE3mApauNF7/uC03hZVz2s11xJUYywMaQeNLI2j3m8mUrw+wbFoU7b/tu2LZtuy2x5zE1LJxzzjmBvmFh1qxZPcd7gCvgCrgCroAr4Aq4Aq6AK+AKuAKugCvgCrgC41kBb1QYz3fX1+YKuAKuwCgq0EujAj9aHE/8oYN+cMCl4Jlja2uqEVjyWzzs1mY5ov9xfmKdwiKoCRdjem9UeLztb9LnUs0nLXjY25hspVKnWvAhSgGIE15LvDb5CQ8MjXGU+PZ1l1jiE5adW3d9TbaWunVhfXQtsdnTqW4bl6NKHbvBILaK7afuppopB/iqeZC/k99yIIauJV/9/QC+xPprpFU/KJXv14++/tNw+6eXRkP2tRtNnTo1XHfddYEeJvDDFahTwBsV6lQRmzcqNGvjnuFWwBsVBuf+dduoMDV+owLt6/jnEJTPP4/Qg15qiAMxiQFmAogdgXLFPoy9EaCoxEd+YBApPK18wIEr4bU4+GGnq7goB8+SS0NacnOFVCcBOEbHKVIG5LeUAq3kQTytOuLXrl0fbppzS2xYuD1s2jiyb1igf1fRsHDYYYdVqvOpKzB+FPBGBW9UGD+vZl9JLwp4o0Ivau06bN+NCrpHwr6LN13RxmbdpGUI9lflOrHvox2ZhEiEhvPeCxhEgh+YZI8GjdYixIN4XDM+jYrcZAV3NYaIycd2SSZjUOmV/FKnGFBXwUc87CbOJ4THHlsRZsdvWLjj1u+MuGGB3t+jhoXzzz/fGxYq98anroAr4Aq4Aq6AK+AKuAKugCvgCrgCroArMHEV8EaFiXvvfeWugCvgCvSkQD+NCvSOP7/pTyf7sK58EtCc32IJBXyTHUzqj49cs4U/lkAsMObaU6PCt94aWasFGDId4kMPPOwPBD5kwZyoLF9drXgAHTHgxpyuVQx8ia+SB/7qFdw9192ysNaawG1zdqq7yW85yjVmD9/yyn23fCkuh/CoE8b6K6HxJSoJ7T2tYjCHHj1rTTnarIv4wY1cdG1bN90/f42wXFWdOmlZ9zqqcvxi7n1h8SduCzu27bC3pHE8adKk8NWvfjWccsopjRh3TFwFvFGh+d57o0KzNu4ZbgW8UWFw7l9XjQofOTNMnR4bFajsuMeSK094DyfbuHiWP7I43UsLFjtKihc3R4OLzIonAIZky3YTqgCLY76iAMlTxCNAXIm7NEuBYsu1aAjHMKdZB+c2JFI3Itgry46YFBYHmknrkNm6ddSwsCQsWhC/YWHjJkvS85j+fT3ttNP4GxYOP/zwnuM9wBUYdAW8UcEbFQb9Ner17RwFvFFh5+g62qxdNSp88nzaBOZ9Em+HZE9ERhnJQK2Mp1p5jthkqNrtXi6PZa+WGDUPkYpNL7pHI85oz3DKlnytY7bQCXQ04nm25VrgSDVlKLt43xlHbKb1Fn6ujBPBnP2EJWv8L/5Z/lj8hoXrF4Xbb/n2qDQsnHXWWeGCCy4I9E2qfrgCroAr4Aq4Aq6AK+AKuAKugCvgCrgCroArMJEV8EaFiXz3fe2ugCvgCvSgQC+NCpY2PgNtPmbQCRkbjhY84fApQpu4BrrCTA+R60cTbF96+XfCPZ+/t8DUTWYcsU94+7fe0uKyXHB286A6sPZa5eqXx3I2jau5CNdvvipXvzxNtVp7x1y1Lx7LIOO2PF1ytLLWW6q5CNWvRlWufnnqKy2t1VzDWneLRj3c31IDw9QDB+n2P3c8EG668OawbfO2UuSG2e677x4++9nPhve85z0NCDdPVAW8UaH5znujQrM27hluBbxRYXDuXz+NCvQzDO8n9GcZu7fID0fFNeqEH7zCklOM+PHjEB7CIhjGHGcIgc28jMY0xZHVHuAjG8bMleor0DwRV1xZSioYjo828CASc4LTGHH0UxodfCY7zwijA1KSJ2rQy/r4DQvz590aFt50W9g4Cg0L73rXu7hh4YgjjkBiv7oCQ6+ANyp4o8LQv4h9AX0p4I0Kfck25kH9NCrQRol3S2lbpINYfdo76YA9cZwQKUbAsGOPRgJgLHs1QQBHfiSRFLRHY2uKk1k+g48sGOMqtoyNCJ5UuYFINRUFWV5iyDX1u8dcsXxVmBMbFm6LDQtbt3b3fh5qrF6nTJkS0LCw3377Vd0+dwVcAVfAFXAFXAFXwBVwBVwBV8AVcAVcAVdgQijgjQoT4jb7Il0BV8AVGLkCPTUq4MOC+EAvPdNLJ/6AwdjrKgKWfPiQg3Emjh8XZj4Ya5jgYkLxp990Hn34eKanRoVvxkYF8FJ9dmJKMI8z6+IZbBBxiLoa+LriKBlbZ8hBnoY8Nqhjzi74OnLYhE1j5DE1E7RO79p8As7sNXyWqyuOzNY86pDHBtbmrKx3KF8jtMgOOnS1ditW3bgmB8HsfUVYbT4BA1Jbs0DyTUk8yF3lyGy1oz/+4KEw5wPzw+a1W2r9VSN98PqpT30qfOhDH6q6fD6BFfBGheab740Kzdq4Z7gV8EaFwbl/fTUqxPLxkBXtx+1epfxZRz3RmHYfOmALx4oW5UNdAuIHtsitpGzNp1QDcloOYW3DrbyGTkOQmwFIrT4qJfr5j1yFRmLsmC35JOuHDjk0hkQleAGZQ/gl17p1G8L8uUvCgnkjb1jYY489wjvf+c7wkY98JDzlKU9Ja/KBKzCsCnijgjcqDOtr1+semQLeqDAy/cYquq9GhVic7Otks2R2kHlPJoByb0WL0q1Ur3vMtAPjgcxQg6bSvVqrcnbviXG6mpokMnMDA8Y0jxDUz+EoIE6AySblE6DqkWSgCI0RXNZHuJYvl29YuG3J6DQsnHnmmeGDH/xg8IYFuiF+uAKugCvgCrgCroAr4Aq4Aq6AK+AKuAKuwERSwBsVJtLd9rW6Aq6AKzACBXpqVDB5+LneeEofEND7/vZhX4OlIVz68YB4MYlOPDBsP4QpKIC1ZMT7eGZGLT03KhCn4a/WgNoIlhbCk3hCHMqo2nlOIAMwQ8ATTzI0DGwsckeoDI0h2nquuwjHxCQ0w1QdYMlQM6jGmZiq1hTdWDfi2vBBiVHRu02eat2NNdOC+qm7mtvy0LjdUY3V/HJBMUIwsrrBZRKaYSoRsGSoGVTjTExVa4purBtxbfhqb0gVT0nAReOmI8Y9dt/ycMPZ88KG5RuaUC12+nr4f/qnf0oftLYA3DChFPBGhebb7Y0Kzdq4Z7gV8EaFwbl/fTcq0BJ4rxB3KvghhExm/5Ds0ZjMcZBmauSLwSCOrjmO8kC3ylhrYXTCAEs1ZSPGbAF/dtMKUh5gmd5wMHOMgb96RWbkkHg+Z26AOF9RABHzusFL0PXrqWHh1tiwcGvYsGFjiu5nQA0L73jHO7hh4cgjj+yHwmNcgYFQwBsVvFFhIF6IXsSYK+CNCmMueV8J+25UoGyyiUp7LTZhu4T9mxphphjZQSFeaOx+CmO6agqJMSTY8lkuHicMJZYDfDTDOHGzUXByjizKASxDYAQ0YoSDBhpZwbBZbXIx3OChlVXiqACKtXb6hoXZNywKty6mhoWtKbqfweTJkwMaFvbff/9+KDzGFXAFXAFXwBVwBVwBV8AVcAVcAVfAFehZgZ///Ofhve99b0vc6aefHk477bQWuxtcgdFWwBsVRltR53MFXAFXYJwq0GujgjwgLG/sd5SE3v2vewC4Y6AB8KcP3fGgZ+GuK74T7vn8vYakfjjjiH3C2+kbFfigQpFMTWN4IV27VLVS1a6ru/+aK0sY42n/de86rUmiYay7/5rH+EVRSddr3at/vybccObcsPoPaypMzdN3vetd4XOf+1x44hOf2Axyz4RQwBsVmm+zNyo0a+Oe4VbAGxUG5/6NqFGBlkEPPPGPEPJzRHoeKk7T3t6M7YNR+NFDwhM6PTxF9oQnDkOOYYpCDiYr9c1xmaPKjYg6LPms3WLZrjmbMBLP58gj0blM0i/PWrhhkPCwYf1GbliYP/eWUWlY+Lu/+7tw8cUXB29YsEL7eFgU8EYFb1QYlteq1zm6CnijwujqubPYRtSoQEXF/VHaI8WtEnZLycYQWCt7NTXzhXh0kYileRrTPkwBsBE8RbE7Y5RKEBrHeN3PCR0IDVr9FlsdM5pSRWxRi4kFI/ziIrx4ckklh41DrLWtXLEq3Hj9onDLzXeNSsPCGWecwd+wcMABByCNX10BV8AVcAVcAVfAFXAFXAFXwBVwBVyBnaLAd7/73fDiF7+4hfvjH/94uPTSS1vsbnAFRlsBb1QYbUWdzxVwBVyBcapAL40K9PAuGg+qb+q3yJM/GShd9Kx33QF81d9kr+FAo8LS2KjwvZ4aFWxSJKxJ0IepG2Z8K0RHTVvyd8PeEtSVoRMzaiay/useXa2pFtTdxNx/3WDmFdNp1I5umFPdcWHpw8KuKuiGvSuiFlAn5p7+vmhkb7qTLQFdG1B3E3PSOjL28tpe/9j6cMNZ88LyX6/oupY3vOEN4Rvf+EbYc889u45x4PhTwBsVmu+pNyo0a+Oe4VbAGxUG5/5126gwbfpUKVqfguJ9hJ7wgBQ95JXtumdjg4YqgPdyhT36IwlM2H/QHGMOxRNYikRejtPghJeUERkd6iMT/Igp/XGWsDLAHHFMG102zvrsWPLxWUqIZIkPRPHaGqNFIA9jCZjzbly/Kdw0d0n8LzYsxOaFkRzUNIqGhac+9akjofJYV2BMFfBGBW9UGNMXnCcbGAW8UWFgbkXbQrptVEj7IN0kyUX2QmnMe6CYDnshyiyQeEkDGes0QSIJTMhF8zSmJAAQgx0nkownEwUwLGGzH/GMSP6SlxnUhzqUVphrfAWOKmAMeHGlyphdziiGZ7lGAnF9aseccqxcsTrMvn5hWLxo6YgbFvbee+/wvve9L1x44YXBGxYgtl9dAVfAFXAFXAFXwBVwBVwBV8AVcAVGWwFvVBhtRZ2vVwW8UaFXxRzvCrgCrsAEVaCfRoXqhwON0ukHC+zH08FNYGCrOLJXbQ0cg96oQGVjmXYJ/T4YXQpTx2yz9Da2ktcx918z1QH2Oube6rRosMJWx95/3Za9jhlZe79aZoquYx/0uke3ZlLBqlLHTpj+jk7MI9F685rNYfZ588NDP3qk6+Je9apXhRtvvDFMmzat6xgHji8FvFGh+X56o0KzNu4ZbgW8UWFw7l83jQoXXXxWmDptSi46PsTEzz3pw09pp0J2Qqmh+jMTe6Ov1U4x+XEp+IkGY+JMY00g6bUWyqtHypMKgSdzcIl6Ag+h7BhRsPGV6uBi4JVrrg0cZEdtHMEOTkkeIeXgpnEun5MKNhuJnb9Vgb5dgRoW1q/bwJh+T9Sw8Pa3v52/YeGoo47ql8bjXIExU8AbFbxRYcxebJ5ooBTwRoWBuh2NxXTTqHDpZReU8XF/JPst2TFh30RGbJ14V5UcEo69FK4gZRjFqgF+mqcxEQOgA8mVcyY+LSIxpjjLl9Bas4DACS9dObVyUup2awNe4lGbVhI5OAs4BJTWKLFSB7t0aPMpA2tB45UrV4c5NywKixfeGbZs2aqM/V2oYYFeD9SwcOCBB/ZH4lGugCvgCrgCroAr4Aq4Aq6AK+AKuAKuQIMC3qjQIIybx0wBb1QYM6k9kSvgCrgCw61AL40KTSvlB3/T079xUPlggOLot6unN/0tET4nSPGCJUgVTw8Q44MUylE8y0xTLWTpFXd3/Y0Kf3vtmyt5+PfA5zxUiB72AWbY6q6pxuiUkuiMhdoIWXSBR7eFhbXEkpZ0WM76uvupmZib6+63ZmEt65aayWM1YGStDuQpDxuXayaM1Ybm/datcQVfvdacZUR1V2seWd2l1sJFq7Ga9VtzqozXW627X62FtVo3XiWjVne6R6NVd/ka2bZpW5h34cLwwF0P0oK6Oo477rhw0003hf33378rvIPGlwLeqNB8P71RoVkb9wy3At6oMDj3b6AbFeJWJf08RA9gpa2L2S0VdtGVY4pYtXOYxsqFHbLHsnbjjAjJq/mjC/zCCu4cY+tMsQSjWjXI7uuaxgDbfImhUsfGjZsCNSzMm71kVBoW3va2t4WPfvSj4WlPe5pW7BdXYPAU8EYFb1QYvFelVzQWCnijwlioPPIcI21UwJ6JK6E9lBrsvghVYi+Fa7LHgbVhTFzgwVViJInkyjkzHwdKLBlRE19trDjBwzODoTkd8PM1+lGfeOVsbYLnyBzLU14FB5R4qYnAOlJSvWTCYk1Wk9Wr1oQbr6OGhTtG3LCw1157ccPCZZddFiZPnixF+NkVcAVcAVfAFXAFXAFXwBVwBVwBV8AVGKEC3qgwQgE9fMQKeKPCiCV0AlfAFXAFJoYCfTcq4B3++Ixueu7XdA7YDwbsw/LWXnxKIM/6sujAWyxsFGM/MDApYx1CsvTy2Khw5b0db+CMI/YJ1UYFPBRNwbX5O7K2i4NoRJIXnPKQlsaeUzXEGQFtXGe+zGxHKY6qyzc1zpC/puYWbMFoJiZW+Wprbstn6MwQddfXTECT23wIVeINYd16k628R8jNWQrNLF/ruDkOWjNjCmzGA9IQtwvr7lwz1d593d3xQY/ymmKL/4815B6F18j2bdvDzR+/Ndw3/9dlIW1m9CDcwoULwxFHHNEG5a7xqIA3KjTfVW9UaNbGPcOtgDcqDM7966ZR4cKLz4zffDQ1Fc37iriNSPsL9pBBdzbxSkfxM0tlbmMJZ7YfiZdsmQMYJWc+OsEex3oghq9kQz18reLtvBxzaEqnvjiPo8SpKYuaYWMkcioZ6GS9OqM1aJDVhU3RgXwZFW1CkOoAZsOGjWHB3Fu5YWHduvW5lD5Gu+++e0DDwtFHH90Hg4e4AjtXAW9U8EaFnfsKc/ZBVcAbFQb1zpR1ddOocMll58s+R0N5f0N7H+xz2M6bIdkrYV9E9jjGgX0QzRGLfZOlSj7wmKsllJjIYHIwNyVFjBjorLgq3s7LcY7hkcQTbzUhc0sRpQt88apkgsq1kJmIq362sy+6ZTFytXj1yyUyxD+rYsPC7OsW8jcsbN68hVx9H/RLSj74wQ+GM8880xsW+lbRA10BV8AVcAVcAVfAFXAFXAFXwBVwBaCANypACb/uKgW8UWFXKe95XQFXwBUYMgX6blSgddK7/fzgr1m0Pqxd/XABD4VX7SYyDRNWPzAgh9DGZPz5ACWuPyj2rviNCvd8vvtGBfMcu6zJUNOHFvaBeuNqO2yOU9FMtH5s0pyHn7PXOLt0tiuRsXfkM7mrw/q6QW4TklQdtKmru6Qo9O7IVy02LV3qa71PZK8m7FB3qpnI46R+6dkeUSOpu7VmyjuSunW9dXXDRiniMbp1g7zUu2OOpPfO15rW3Kr3SLQWxqbXCP1ddMen7wo/vvpnBOzqOOSQQ8KCBQvCs5/97K7wDhofCnijQvN99EaFZm3cM9wKeKPC4Ny/bhsVpk6bwnsnqpx/nolbiPxzje6DyIal8dja85g5CGkw9uEr8JKN9lL0h0cGxCayCogAxQEOMmIs4ZERwUJs5hlr44RYgjhdTU7KgTyC1yhNJkvg1bBDzXEcPQbTwkFu+h8CdG5zMAWd9CDsxg3xGxZuig0LN94c1q4decPCqaeeyt+w8PSnPx1p/OoK7HIFvFHBGxV2+YvQC9glCnijwi6Rveek3TYqEDF2SLzf4a0R9jV6JZtWkPZEHIhIJmEEWxgvEdhCCTzbwCN4tTODcIEHJlzLOLFSDtjVwpe63ORowrJdShEaxZZ4ccHG8JgIYTknF8VgwsKfiUX3xJMDE4SCUqSO6RsWZl+/KCxacHsYacPCfvvtlxoWpkyZkvP6yBVwBVwBV8AVcAVcAVfAFXAFXAFXwBXoQQFvVOhBLIfuFAW8UWGnyOqkroAr4AqMPwV6alSIzxLTc8V17913qwyaEOitfnxK0PJhgZJpzwPPbE48bGw/LLDPoy+9/DvdNypc8+b2pVNx/DB1e9iIvBCgTR64AG2bDyAEtQWPwNlFHioBsI6ZAByLutvkgAvldFU3gjqC+wSgmDZ54AK0bSaAENQWPAJnF3moBMA6ZgJwLOpukwMulNOu7u9+7vvhu//n++0ghW/mzJlh7ty54YQTTijsPhm/CnijQvO99UaFZm3cM9wKeKPC4Ny/sWhUwANQvGrdPPDPMXGMn2fszzrAkw04HhkQ9iCMxURlzTExysYwLnoTXgZ5XsUnYGQ22BhgYygt5bG5tJRk42jCqCPHR4tOyFflwBxXCrdjpStsyR8JN22MDQvxGxbmjlLDwlvf+lZuWHjGM56B1H51BXaZAt6o4I0Ku+zF54l3qQLeqLBL5e86efeNCnZ/JPuiYp9EGcmsmdM+h8wZmADMxniJKCDYc5EfYyYHu9IgPps5O7hpgngZl3NliRgO41OJhwNXimfSIka4Y1ZLpJSwMUP0gylDo0UnhIVfwxMneFiGKoooYDNjouWGhRtuDgvnx4aFTZtB29d13333DRdccEE4++yzgzcs9CWhB7kCroAr4Aq4Aq6AK+AKuAKugCswoRXwRoUJffsHYvHeqDAQt8GLcAVcAVdg8BXopVGhqXEA79l380B/blQgbfLHBPmDhKxZU77EgQ8JQKNPD/faqJD4qKK6QnJJ3Y3wFDOhUVt3kbWojjpQmiGsmz/sGQV9itfdSPnivcPtYyrl89eIvjQhDk1HqnWk6Pzajq+SUciTbupo1G1eI0zXxWvkJ9f8LNwev13h8R1WQIquPyZPnhy++c1vhte85jX1ALeOKwW8UaH5dnqjQrM27hluBbxRYXDuX7eNCtOmTZWidWPCe++4Byi2KdHHczXiwaa0T6/YEUw4u98BnmzMoaSwQz0xV2KJlB3xYkljkExLPGdQfDlGfHLmGiNRstpccWw8XCZqoGuKMbUoKPmAZzvjkKDkTrjkTgOpIU+ZalN8gIwaFuZQw8KadaDv67r77ruHt7zlLdyw8MxnPrMvDg9yBUZDAW9U8EaF0XgdOcfwKeCNCsNxz7ppVLj0sgvyYrBXog2b/FGfmfMwnuAhLB3pkgZqKvd92D9JiojlP3TSOGGr3TPyTk5h4FF4LZ7IM23dOOdMuDhIVpsrjo2H01INqCPFkBQ8ScHCZ3nTGoEpucGJQlLeCOcxX7HyENbEfSV9w8KCm24blYaF888/nxsWpk7Vnz1yKh+5Aq6AK+AKuAKugCvgCrgCroAr4Aq4ArUKeKNCrSxuHEMFvFFhDMX2VK6AK+AKDLMCo9Ko0KMA+aFv/VAgxssHCSVR00PMhCKO4sMD8/xvT40KV79Zn2EmAv34IZclBRluNsBfZ6/aKAB4YevpbDVIVMQX80gqOvdQd1N9Tfaeqs3gburGBzw5Ko6a6ujWPgKts6ZSkaWS9HTuUmui0PskbHquswFbALufdKN113W3q6/pHnRfaoHsu+6mOnq1F9V0OYk5qmnwOhE7netfI/fN/3W4+RO3hh3bdnSVjB5e/9KXvsQPwnUV4KChVcAbFZpvnTcqNGvjnuFWwBsVBuf+ddOocNHFZ4Wp06bEf+L1X/14sftY7AVo75d+PolL1B2B2FJoQhOAD76YB6jAQXaMKXcaS5iEsx08mdDWp3C+gANLIaPYJDbbKR97NY4vejJYpCQwxhhENHGnnIYCNjJ1HCsvY8HN6WpyttglKXJQw8KCebeGG+MDZSNtWNhtt93Cm9/85vCxj30sPOtZz5JEfnYFxlABb1TwRoUxfLl5qgFSwBsVBuhmtCmlp0YFbMAa9jG0KcuQCNKD9zc65b1fcsiAXNgDkQVj4gJeODKn4PjcmhNxJVxxYkSdnIFN3dolZ8qvOerWmNeh3BSkB3w0TWPSr8afjITFJAJ5jPzWrosDl82xZs1aaViYd1ug/eZIjlmzZgU0LEybNm0kVB7rCrgCroAr4Aq4Aq6AK+AKuAKugCswARTwRoUJcJMHfIneqDDgN8jLcwVcAVdgUBToqlHhvBPC8acdmz6goNrRbJDe9NcFwU5v6+PIH1LAQvE0xiO/8SOADE8gi6nmSaCaQX+NCkJky3g81VeTpMWUI/NIQFWe9OGHcsDfZGeYPP8sH5akOB3Ei80JvuxtN5JIG0/oOo6m+prsnJXrLhH5rpd11eUsEZjlavNIfHUcNjv81kaRsDOLFmhfc6iZ/DZnEcfB7U45Mo8EX+Vpqq/JziystX6gpmXszLqrNVPKpvqa7LnuEjHyurPCeSSidFt3WVH9a4T+4gJ/U82UFTkfuOvBMP9DN4dtm7ZJMR3O9ADcv/7rv4YzzjijA9Ldw6yANyo03z1vVGjWxj3DrYA3KgzO/eupUYHKxgNKtAHAGMvBvkA3B2mXEOd2X2ntTEm7CflDpKDlGKbSk+WQOIJnfMmVCMmcDssh5SOek6TcXFCMasUTlXBrWczNOKGgFbCNkVyfzLO1yps9Zb5sB2Xiji4eK6TZLqVUeTdt1oaF6xaFNavXpnr7GdB+7W/+5m+4YeHZz352PxQe4wr0pYA3KnijQl8vHA8aegW8UWE4bmFfjQpxabw/k00atj9s5C0P9j+QgOaKJZPdD2Ge3dGLfVMcCF++gpLjxJnxqITy0Zj9NiLXgRyMVJ7MySPlzSQ2JtGTO/5n82m1ac1Ye2bKdUjO7AG2sGe35KGUKEZ9yGlrMWEFnrBoWKBv8hppw8LMmTO5YeGcc84J3rBAd84PV8AVcAVcAVfAFXAFXAFXwBVwBVyBOgW8UaFOFbeNpQLeqDCWansuV8AVcAWGWIHuGxWen998j+u1DQl4D982FvCnCaoL/FWZMof5IKACAiakpfYAAABAAElEQVR9UFDx1013SqNC01PIhV0+qrAfWOAB5Wqd6YOO6LAY2K0tAtJhdTBm+rwkHbWxJSBh401N4zwqa0qAOKirDzbC1eamOM1jayY8cjbFJQCBbXBN3QUH4fVoqq/JbvPU1Y2aib7IWdSH7AzKE627kSMjk9ZksnlQt7XV1SxxmbAxJ+ouASYwO/KorCmDR/4aaaq7ab3D9hp5+MePhDnnLwib13b/G9Y++clPho9+9KNWZh+PIwW8UaH5ZnqjQrM27hluBbxRYXDuX8+NClR63M/xnkhPsr2LE/kji+MxA9KGF/tKplAw9nWJQ+iZg/DMIE7dtgunMldq0dQcFxEJJHY6FzUUvOzVHMBrLsPD8akuwVlOWVYOgC9dlVpTxxlylNdUAYBKSYqAC5giZ8QplBabxjaGxwrazA0Lt4Ubr1sYVq8aecPCm970Jm5YeM5znpPK84ErsLMU8EYFb1TYWa8t5x1sBbxRYbDvD6rrqVEBQdi76P5HLrK54a0LD3UTQzE6LPY5sjGKZ3EmDoIbPA+jQa6ZTCF5vwUDxxM+GoyNIulADXX5KAC5Fa0xOoOzUg/MAmYWCYjnnE/XoB6JyQVaXAo28VgLr6xISCCT0ywbnMSXxsBq6rVr18X95aKwIDYsbNy4iaB9H9Sw8IEPfCBQw8L06dP75vFAV8AVcAVcAVfAFXAFXAFXwBVwBVyB8amANyqMz/s6TKvyRoVhulteqyvgCrgCu1CBbhsVXnD6sS1VSmMCvSkvLsyrQPirdppLI0L1A4sSSZj0xn/poqelyyPW0kujwtuufnMZH2e6nOLh8CIPABTZkl+cdC4erCZscQiiMOmEPhwpYis5SIuKiSNRVm0snISsBpsb1G/d+FioNreuK71QMNdrS05bX5d1ty7KJpHqitpSbklQ+Gx+whl9wIqyGuMAoIC2fFUnMtC1fd2NuSnSXyMiZHHv+teayNrp3etrZPn9K8Ls998U1i/bIHV2cX7/+98fPvOZzwT6rb1+jC8FvFGh+X56o0KzNu4ZbgW8UWFw7l9fjQqx/PSzSdxryHZDNn9p6xGn2B+nHy5MHPsMJvExRvQhW63dEFo/zLDhKmyZE3P4U83RAZuiAdU1qp/rUoQNVrTlwJjVobiESdRxIFbCAl94KQf/MVcLIAZThxkme+kXHqaIQzq2bIrfsHDT7eHGby0Mq1atEWOfZ9qrnXLKKdywcMwxx/TJ4mGuQGcFvFHBGxU6v0ocMR4V8EaF4birfTUqxKWlPYvdF9mtS7HRyVogrtc9ZkmnGyNbB6VQM+UAf84so5TfEJphXhfDbZ4czxwmV1MOsqd8MkGJ0Y6oNGAs8PC27C0jnNeWADKwceAubShY45FWr+vWrg+zY8PCTXNuGXHDwowZM8J5550X6P1Bb1io3CifugKugCvgCrgCroAr4Aq4Aq6AKzCBFfBGhQl88wdk6d6oMCA3wstwBVwBV2DQFeiqUeEDJ4QXnNbaqIC1oUEBb9jDjiv8NO+Eafbnh4zTBwLRxA8Pk4s/AJBPAahR4XtX3ov0jdcZR+wT3nbV3zT6kSflADIVyQXA2vma4iLUilITidzkwrdK1MBaTVECfLBS1G306ZS7ILVx9MQ9ad3m6LfuxrgeNCvK6qXuJs0KwvpJ57o7a1Yw97DextwFYc2kab1Wsw6vz4LVxpGjQ2y/dTfG9aBZc90d7lOTZgVh/aSp7jUPxd+uds7csPrB7h+Ge/vb3x6uvPLKsMcee9Qnc+tQKuCNCs23zRsVmrVxz3Ar4I0Kg3P/+mpUiHuPvP2J4zzJP+uYvYOAy4eXmMFioiTYM2BrQ3PYSLFkz4Rp3w+T4LigIpbtloT5gCMHHViLjNlEVoHxNNWkNltfxisvGTSYLbQeBWVOWAgaxwYj4eonl0a35DQ+gmgEJUd64dbcjMkFcADFEO/mzVvCwnm3heu/uWBUGhZOPvlkblh47nOfi+x+dQVGTQFvVPBGhVF7MTnRUCngjQrDcbv6alTAPog3M9jHyM4GW5diH6SbHt4jVcbYN8neqJUDPOyxsSRvnNt4KJ5iUIw6hENIgGEa5WU2M858mYDiinVUcgifViUJOViGqdq09+NFRESqh/k1X2HPa01YwCJ5YuaxOCzOjlk31M2FSRWEWRsbFuZcf3OYN3tJ2LBhIzL0daWGBWpWoP/22Wefvjg8yBVwBVwBV8AVcAVcAVfAFXAFXAFXYPwo4I0K4+deDutKvFFhWO+c1+0KuAKuwBgrMOJGBfN8L96Lry7BPrfcL8Y+rJ8+BODcrQWMeqOCXQAvTj+daLFXV16d9xaHddq1Vxnr5o1xJH6Uq2O3QZUUN62r9caPcChNH3l2St1d14G6OaCqQOO8sWb+dIqk7o2PP8KK+nUb15y/sWR2NMb5a6SNcP29RoiQ9G79//ETwoYVG/ibFR67b3mbvKXrda97Xbj66qvDXnvtVTp8NrQKeKNC863zRoVmbdwz3Ap4o8Lg3L9uGhUu/MiZYdr0qVK07ovlInt72rqpMz8cxS7xk698yEkj0kUHhIvEmkLHxidEwmVjM4QQfGCvl67ZgRHz0yStpTLOPhpJbbLFjQkrOZEHOHbnk8BpbcyEnIxmS4o3GCos4zESgozXOSEVIhc98yVrKslaOSgT6YCMm7dsCQvQsLBytQT0eaZa0bDwvOc9r08WD3MFWhXwRgVvVGh9VbhlIijgjQrDcZe7aVS45JPnp/2Ybsj0wpsSbG3igvNepnYPRJKYfQwCsa9hN+2reF8UoTyWiZpyPDBCSKHpSLmjBeMcr3xIwhgKhT2PeZQClSvOwUl+HLAx3Kwh8RKQ7BqQ02O96ikwQLfmRD4QMjMoataS81EdUoTloHjCME90r1u3Pnzx89eE25Z8O2zfvkOr7u9CTQrUrEDfsuANC/1p6FGugCvgCrgCroAr4Aq4Aq6AK+AKjAcFvFFhPNzF4V6DNyoM9/3z6l0BV8AVGDMFem5UqHnumkzFG/O2+ui0IfmjAArKwOrz3Owq/JnFfkggv+QfPgkYcaMC0ZncqBJZMMe1BgpXy7XgKCYZ2qilQuiB5/ShRw5rHDWkqVtidxwNhJ3qbiRvcNSl6UVroi04iokkHYuaKVMvdRdlFhOpmfl6IcxhjaOGNENZd6/SFGsvJiLXzn6NbFm3Jcy9YEF46IcPN96fquPlL395mD17tn8QWRVmSOfeqNB847xRoVkb9wy3At6oMDj3r9tGhamxUYH3GLQx4D9ypZWwXZeU9ujk1k0EHkxirN1YmEBgxB1nGg8Om4dtGmv9WgJfYGdYJEupTP6EqbFJrZkRWF67wQMBP+WhMSDxpxaGVOuAn9RDrAAVTxxKXvjVxnXIScOAZkagEnfOF12Axitn0SthUlbFbN2yNSy86bbwrWvnh5UrRt6w8MY3vjFccskl4fnPf36q0QeuQL8KeKOCNyr0+9rxuOFWwBsVhuP+dduoQJsm3nbIRiTtTWiVuh3hBWM/xFd1pH0LYe1mxwQCw/SKISzwBio2cFs+rkBONg5jLVAvmdH6y3EmTPYYlsbZnWxcP6mj9D3tMREUeSkHKqzLR05GKMhiEFnYQEY1Y2w4KAa187IU8+gjj4VrvzE33EINC9u2s6vf0/Tp01PDAn3bgh+ugCvgCrgCroAr4Aq4Aq6AK+AKuAITSwFvVJhY93sQV+uNCoN4V7wmV8AVcAUGUIFeGhVafiM4PdRLb/DjjfjK+oBPb+BH/OPSWcBv3id7jAOWKZi3/GCA/TX2lNJwL73i7vC9K+9NrqbBjMP3Cade9Sb+kAIYW0d9ffWLtRo0clASWgMfGNTzAUXXrri108PWTLG5lvo83XETE47u6ra8FIk6muprsvMLBanN1fI3c5uAJHy9DkBaXrLVccNGflt3ttfn6Iqbk9KJju60JqTlznXU12dr5iypS6hz3c3cxISju7ptzRQJ7qb6muzj4TWybfO2sPDiJeF/7nwAIna80m/knT9/fjjwwAM7Yh0w2Ap4o0Lz/fFGhWZt3DPcCnijwuDcv+4bFaboQ0uyX+J9SRwWu6e4ueG5nurHFKNReiE1YKP9EfY8dJX9kgD5rCexa6S4k6iIFy+Rl3WxPZOVOVrsoEUtxKf1at6iRo239XE+TaohmlM8uV4mFnXAo8HQh6Z8MFTwNBc4n5OWqU7yi4tDBUw2NcYL8dM05ckuZt+6NX7Dwk23h29dc9OoNCy84Q1v4IaFY489VmrysyvQhwLeqOCNCn28bDxkHCjgjQrDcRP7aVSQrQlvSLBdkcVGB29N9IQtTNq5pH1LGnCczPQcL9j70BW5NIKo4gF7dcx0KV68BC/rYrvydB4Tgg6Ts+BjevYziuqnIplf4tIZcYQ2fqwXRnYxhYLsmMjogC1DEqmuVukEkPNJLFPAqFw0RWxegqz7kYcfC9dcFRsWFt81Kg0L5557Ln/DwsyZM6kUP1wBV8AVcAVcAVfAFXAFXAFXwBVwBSaAAt6oMAFu8oAv0RsVBvwGeXmugCvgCgyKAiNqVOBFyBvr1fXgoWOypw8G4vPLRaNCfnc+PaTMPPqcM8fpBwP0zDbHEp+JYzyd4I/XXhsVmFHzFHVrHmuTfCgqZecBPoew+FQr12fx0ZCOer7kjgPmxhrVAV3lOfPMxzkjBnoJvD4HaiZMXd3pGXYhIZSO6vkSLA4YEU8t9WlSmy/dg8oalcXS8hh113IzRzWkx7pjeFW/nBNcXLWU2HPdmYMq5XvJHLZui+lCb4JU6mj7GuF7012Odmvfua8R0gM16t81lTX2/BqRV2ZizYrnPNlWP8LdkIgc106n6r2p1r0jfuX7LZfdHn5506/qk9ZYn/rUp4aFCxeGI488ssbrpmFRwBsVmu+UNyo0a+Oe4VbAGxUG5/511ahw8Zlh6jRtVIil42cU7LPSauJGgPcI2BAwlry6h0nA0ib7iowBL10zVTlmBknGrMAhFqlsPYKxPLYOrUIu0dGKYzT88Ypc+ZqzAoYF8JzWoxDUK3nIKp5kVyBHxHGOBIHaEg52QnIAG9SdaoURNdMcY+RGPGJtbVu2bInfsHBH/IaFm8KK5auYrt8T5X3961/PDQvHHXdcvzQeN4EV8EYFb1SYwC//Cb10b1QYjtvfVaPCZefzYrDP4T1J3B9gT5JWSjaaGIcMW7GM1E0MYrCnyXueHGfxds9Tjik1WKSqglsmtjwqVucSl8NhF57aPJoKOYtYCtN8ecirYMICy5MIlj/sl1iuTu2aTLzZpubkjVycxXLFGNQoyc2ccRKNmsp4ZVY+alj45tU3hcU33znihoVp06aFc845J5x//vnBGxZwY/3qCrgCroAr4Aq4Aq6AK+AKuAKuwPhVwBsVxu+9HZaVeaPCsNwpr9MVcAVcgV2sQC+NCqlUPJerhso0WukLmPMb7jbONirwu//qpDftqw88M4PS2KeK8QA53uBnilgE7Esv7+UbFf6G6001om6QZocZoShjKoatiti1FlCeEL6Gk81VLouzviY7slk/2epyWr6mONgjlimqvEQdHS1ma0CeOhv4cbUYsnFSOPUKPpirMbDTNWKZogbTUrfF2BxNdpvHYqwdY8sHW7sYLhrAyrXKZXmsr8kOOusnW11Oy9cUBzuwVV6ijr4WszUglrhgtzbksH7YCIcYa8OYrlW/9cV4pqjBtK3b1mdjrd3msRi1R+jSy78dfvSNn1pg2/FBBx0UFixYEI455pi2OHcOrgLeqNB8b7xRoVkb9wy3At6oMDj3b9QbFfAkklkiPcBUY04PNvGOgDAagweeKAZjcuUxkNkm/B3yVPhQovAKp60z5+PsgKe1kJ8xWk6OramPKewaQaccuvrMEf2Jl+IyJ0fGKduASXTgE0OKolrJVI0zCTEUnM2oLBwrJFu3xm/Dmh+/YeHqeWH58pWSrM8zaXjSSSdxw8Lxxx/fJ4uHTUQFvFHBGxUm4uve1xyCNyoMx6ug/0aFvL9LK6V9DDYqakz7Fd2mJGwcAEsujMmPMVGlsWyOyB2PTJb8bKL8grBni8G41S+BNr7EZmLGxCn5gbFxtfVRQsJr4owHR6V2BXIE5UqRIFBbwsEOPpnnfBkITkKgfhmbmFQrGLh8BTwhLHtkebg27i8XL7wzbNu2Tex9nqlh4eyzz+aGhVmzZvXJ4mGugCvgCrgCroAr4Aq4Aq6AK+AKuAKDroA3Kgz6HRr/9Xmjwvi/x75CV8AVcAVGRYG+GhVs5vhgbfEYrj7Ia9+cT3DGmoD86QF9psAHheNgU37fXsyWI/psHvyG/lFrVGgppqhMJyjYFgpbhJhhWiRocEUeiFC1Y07XAlOQZ1TiyyZSKh8NcbZYQIp8maHoKrEY5DZQSV2Xv2JLOVuC1QAATSuxCAHE1gQfXW19FmPtwFu/1cbmtnG2JItJsRaAQqkmJIzXIqexI0/VD7uBlhwFeUYhzpZUWzOFWJDhw5DdFoM0EZAwxo/cgOFarA2B5ESs5UOQ9dO4Lq5iB6TIRxg9bH0WY+3AFmsHMTlRcxzaOGMuMKluAXz/i/eGu//je8jS8Tpjxowwe/bs8LKXvawj1gGDp4A3KjTfE29UaNbGPcOtgDcqDM7967ZRYdq0qalofvAo/pNtH0BiZ9w38L/kZv+AuVwTRcIVfnWDl2jszzp5zFG65SvHJrWWJH6aiC+yZFMFU/pQB4MEmWKhAZmBA3/GG58A0w4p10A5qSC7DmXQOrFuvhryogbYIxeH5QRpLib4JQC1m3Aekl3Tx3kcpVpoCt8TwpatW8PN8++IvwF3bnjssZE3LLzuda/jhoUXvOAFKMmvrkCjAt6o4I0KjS8Od4xrBbxRYThub7eNCthV0Kqwt6nuT9Leo3F/kzXBPqi4qhu8RMN5ceXk6UTp4sGnNDapySm18ojGbNGrGhPG8ogPdRhkioUG5AMO/BlvfALEVi3xRITG09VGErHMSQPkSIjoI3vGEF4C+GzHFBTnYsJVmKq8Gsb5DBvnkblyae5HH10RvvmNOeHmUWhYmDp1ampY2HfffaVAP7sCroAr4Aq4Aq6AK+AKuAKugCvgCowbBbxRYdzcyqFdiDcqDO2t88JdAVfAFRhbBUbUqGCeG85Vy8O6/KY+GdO77XHMeBOEd+lbYRSZQ+s4GEGY6Ix/5Flgyd1To8I33qRMXVwqdXQRseshtmaqRiTa9XV1qsDWPSw105qGsW5bM61hWPS2dQ9LzT28Rn523c/D7Z++Kzy+o7vF7b333uGaa64Jf/mXf0lZ/BgiBbxRoflmeaNCszbuGW4FvFFhcO5fN40KF118Vpg6bUouGg8k0TVb4z7QzBvHEkAPL3EsroYHDzZFV8RoBowlSB+IoqCIUAg2ojK3duQUPJ9TDJWdJ01jYVBshJc44bW2Ah8nnCHmQaackupMVrMWZaBcFKWQzGBqaMEgVoL4TLkpj/xBeSZ3MnENqAmx8BZ2MhJv/N/WbdvDovm3hWuvig0Ly1YA3teVctB+7tJLLw0vfOEL++LwoImhgDcqeKPCxHil+yqrCnijQlWRwZx306hw6WUXlMXzfiWaeH9hXHbeOBY87SNo/4I9i2FJtgjh/Qv5Ek42PZRaD9o75TGNZG7t4oc9Y2BPBDkP82S7ILWOaE71GJy1FXjCkCEWAEZbM+JwRSxfKRdFaWBmILpkrGCUQf1yIT2ER6OEHhwmKcPUXuaOoGTPOQizLO4raX9584LbA32j10gOalg466yzwgUXXBC8YWEkSnqsK+AKuAKugCvgCrgCroAr4Aq4AoOlgDcqDNb9mIjVeKPCRLzrvmZXwBVwBfpQoKtGhfNOCMefdmwNOz1Aa9+Gz7PH9Wln+8Z70ajAYfRmfqSINPIorvCBMdvK1MypJsHAH2fxz9Ir7g7fu/JeGBuv+xy+Tzg1NSoQEzKbkNgBkT6gsOY0RgXVWNgjkKmr/kQQ/YrVDyWSB3YYqn62MzkQcqW4mM7qRA7NotiaOPYoCuDanKBQUBXTse5ErkSZr73WhKPYqpbgUzfBqjWRDQfrU+Go1kzYFg7kaY1tX3dDnL0jvKwKL+qlK+qr1gR7wkaOFhomTwgesAYELcGoVMA1cRKc3TSq1iRexShjFVOtu+pP2pT1kQ7ttaa0dXWblWHYktMUzvq05jYIGbZwJPIS2rHu+rj7F/8mLP7ErWH71h0lX8Nsjz32CF/84hfD2972tgaEmwdRAW9UaL4r3qjQrI17hlsBb1QYnPs30kYFWkneMejPNmw0u6y4X0gYHdB+hoZ1+xrYCn/BkfMASylRiWxPMkZ8cgaeyzC1AAM/ze3Y+tmusS12GPQKDsmXdZAaCUR1ZjI7BpXNlxlMfTGc7UqT2MCrfvAkP2UHBsnYVuEzGOAzh9avGHqAjB4kuyb+BtyRNixQSWhYeNGLXmQq9KErIAp4o4I3Kvj/FyamAt6oMBz3vf9GBd648CLTfiPuM+rG2JdYMNkIW/hUMtiAITNsFFTsp8z+hzyC5XOM4Wk68VSN1pe4I7JpDBKuiYKr3NFmYy2exsiNsJzfxBEHAnGNhmK9BpHytWA0WJPwhbgxB3e8wmZMbFNomRtGikMA8dJMfbSvpP3laDQsTJkyJTUs7LfffsjoV1fAFXAFXAFXwBVwBVwBV8AVcAVcgSFVwBsVhvTGjaOyvVFhHN1MX4or4Aq4AjtTga4bFd71/PTmONeDB435HfT0NjreP4/PE8cHb+nZW3pPXU485waGTnZ9E55TIA9EsHzRVrh10lOjwtdPAXPbq/2AgdfWFj0YzqJmKqkQazBqrKuiqHtIaqZ1DGPdRc20iCHRu6h7SGru9zXy4Hf/EBZ8eHHYunErUXQ8dtttt0APd5999tkdsQ4YDAW8UaH5PnijQrM27hluBbxRYXDuXzeNChdefGaYNm1qLpoeHKKfV/RHILnInMf6swwFYC4YGOTnI6YwWCTAPoeuiLdcGSfWkoJqEwR4Ep7hyimh8ZzxWBDiS1+cqYOvaUHCXvjExGeyYw02RKhSoYKhCOCVA7wEMJXrGiVey+JYpuBYDpCRAmzOFBMRKQeNKSI64U85JVXC6pQjEi+ConX7tm1h0YI7+IGyZY8uJ9YRHX/xF3/B37Dw4he/eEQ8Hjy+FPBGBW9UGF+vaF9Ntwp4o0K3Su1aXM+NCrqP4H0J9h28hDiRP7xHwaoYEmMUqpsYgpAt/i85ECE+mgmGByZeAoSXURWOzGn3ToI0XClvxqM41NQSTw7+I1fixAEsrmTnFLxOmtBq8yE51AKfGCs4YIgvM6T4aErWIj47UFOKkXKkGIYJA58jSK5lPjKyR6BFTrGrg7jjf48tj9+w8PW5YWH8Jq+RfsMCNSyceeaZ/A0L+++/v9TtZ1fAFXAFXAFXwBVwBVwBV8AVcAVcgaFTwBsVhu6WjbuCvVFh3N1SX5Ar4Aq4AjtHga4bFarfqGAfDrZv2Ov75301KugS8QEBvpUh/XJ18kd++wa+LYM7ISJk6eU9fKNCp0YFbaqQjwOoADI0HFVX/iwhB3TCwF+NJXvVlllbRwmPIBC3QluWhBALteFN/l7slhvjVDMZiMwmBchcq+5q/k5+oipyKjfiqnwmdTEsODrUDW4Q1OXohIG/GlvUgQRtrgkPIhDXxFRdCLHQTpiUzwbFcZO9AuNpgaUiqkkrQVV3te5OfqIrchr+JruBpGGB7VB3TU2P/GxZmPfBBWHT6s2JstPg0ksvDR//+Mc7wdw/AAp4o0LzTfBGhWZt3DPcCnijwuDcv24bFabGRoX0EFL8p9z+PIKfXWj7au20St564MEkNQCPh5vYzEAaxRj8bIU4MxeEnMUc2UysepINXGRvrUUCwSOxyiDgVp5or66RuU0RyEkUPI4+yZQzAMMWjZWUgkyxGmLxOVXN2lOuyMB/5Eo0xFkUYvxUIfGmShMPBelBfk3OXDCzTS2IU65t22PDwnxpWHj0kcfA1Pf1ta99LTcsnHDCCX1zeOD4UcAbFbxRYfy8mn0lvSjgjQq9qLXrsN00Klxy2fmxQOxnePMgexFsK+KMD3LpHgQrYg/2HcRi/Bgbk9CogfwJQ54KUKaoi0P1lG2I53CmyLXSmtguRfIYpyp34onYNAY4Xq0NY7oSNeYGXtp0XcBJVSaOclqNlQh4yxuJsSoKKvIwL8htXcpPZaRorSlxw6fxeiGWnCPlZjNzPfbYivDNq+eFBfNuDVu2dPeLTVLOymDy5MnhjDPOCP/wD/8QvGGhIo5PXQFXwBVwBVwBV8AVcAVcAVfAFRgCBbxRYQhu0jgv0RsVxvkN3lnL27Hj8fDg79eG+3+zMqxesyWsW78lrF+3la/r1m8N6+N/u+32hDBl8h5hypQn8XXy5HidskfYd9Ze4einzeTrzqpvGHm3bt0RHn5kfWPpBx80Oey++26Nfne4AjtbgW4bFV5AjQr6bjk3B5QdAuzjN90TJj5tqw/nJjubauy0SMLqgQYFvIlP5uZvYiBnDOa8ErH08u+Ee668V9maL/scvk84tV2jgpZKDPmDgupE+Q1WLSgJU16jWSbbtWzBGI46e2HLrOWoygFvsQAY49XgYS3y1PgJV4cpbATS2BY7+aqHycN4+IuJGiOWDr3IJJ6LPIYPgMJPRsUUdhNX2EFSvVbx8HMwJno1WHgSDIMmTI2fTRV7YUOS6tXkQDhDiokJMnhYizw1fsLVYQobgTS2xU6+6mHyMB7+YqLGiKVDLzKJ5yKP4QOg8JNRMYXdxBV2kFSvVTz8HIyJXg0WHsBW/s+qMOcD88O6R5v3FIjB9ayzzgpXXHFF3Lv5PgOaDOLVGxWa78p4b1TYsGFD+Pd///fw8MMPhzVr1gSab9q0KWzeLE1J9NrYc889w9577x1/3poSDjjggHDsscfyf/vuu6//f7v5pTPwHm9UGJxbtLMbFWileJiKV13zoJFg2KsQ+dc/xekDTdWHpsQcf/7BZiFT5Aebog1xDCvyIw8FliRVbnAQLP1s10U+XkNNgYmPU2sdlbHFpDHnl8TJZurg6pCPsDqWDArEhLn4xGsiKH7+RJylZqoWPugvpCkOXGKO37CwPdwcv2Hh6m/MDo88PPKGhde85jXhkksuCS996UttiT6eYAp4o8LEbVTYsWNH+Na3vhV+/vOfhxUrVsT369eHjRs38j5y+/btvEfEHpL2kbNmzQoHH3xw+LM/+zPeT06aNGmC/b9lfC3XGxWG434OQqMCKaVbFxYN+xS6pnEVlGKwx+HQIl5CdJNDePoPidgsPjFlnMTxOdVl43gfVsIzr8nB9Zs5MeJIfGTQmmADNeZUOOfMUKZJfp7piTTjlSotuAsMsMqr/ATNsaiiFUuW7I0RmoPtGINLgSseWxWuuWrOqDUsvO997+OGBXrvwQ9XwBVwBVwBV8AVcAVcAVfAFXAFXIHhUMAbFYbjPo3nKr1RYTzf3VFe2/IVG8N9v1oZfnnf8vCrX68MGzZuG1GGWTOpYWFGePrRM8PTnjojPlizx4j4hj34uhvvC7ff+fvGZXzswy8NM2fs2eh3hyuwsxXoqlHhAycEblRAMfQwbbVRIfr4DXR9o7ynb1QAL10Nd7983Kjw+RE2KuCB4XgtDvpAQNdo7dK8YS1xTFgy0akbPl47BWgOzZO4LZ/AWs+Gwzq5ZuVL9nY1EQh1R1z1SHyWw9bXZK8S6Tyt0fotn7UTd7uaIrYjX7U+aBPtD//00bDmD2tr7/N+z5gVqMGFD8th66O6wWfsPdVk4vh1BD7KGf+jI92DOE7clJuddGo4DIdFbFyxIaz47aqwceXG+N+m8rpqU9ixbUd4UmxSnDR1UpjE1/gA7T57hllHzggzj5wZJu8/2dJ1rs/q10XdaY02S1Oc5a7iWSCjWdVPc8JYDpvH6kd25bM0aWw5kjEOLJ+xd1rj2ofWhTnnzQ+rHlxtotoPTz311PBf//VfYY89JvZ+rL1Ku9brjQrN+o+nRoUHH3wwLF26NPz4xz8OP/nJT/i/3/3ud/Hv7/gXRR/HXnvtFZ73vOeF448/Prz4xS8OJ510UthnH/33qQ8+DxlbBbxRYWz1bpet20aFafEbFdIR//G3P6fIVkD+ceex2RxgLpjIoAN+WMmMTYhwE5TyUFJ1yiUxwUyIFGPHXCN75QSuxCAGw5M8aqN1gsCMo00rowEfyGVrZFc0FNdMZzgSG69VKQteIjGomvoIziDBKQlfUIPJzWgsznBnzevyKUHiM/mEkCpIB2tiDFT/tvgA8eKFd4SrvkYNC8sStt/Bn//5n3PDwste9rJ+KTxuiBXwRoWJ0ahATQh33nkn7x1/+tOf8pUaFKgxoZ+D/m466qijeA9J+0h66J0aYf0YHgW8UWE47lW3jQppf6P7Ert/kG0E9htx3di70JBkSHsSGHT/wiEaLRdCRzhsmhXxbM5Ak6aIYRLDk+Y0KLjYQCY90oBtqEOcsRa44zXroV51ykWAfI4GxnIM8sRrwaFs4LAwtVk8TFyFpNIISdKSj2uwpDLG+tKVzMDa+sQsQRbDRTXUjnhTHyFXrFgZrvnG3DCfvmFh85bM2ceIGtzQsHDggQf2weAhroAr4Aq4Aq6AK+AKuAKugCvgCrgCY6mANyqMpdqeq04Bb1SoU8VthQK/vn9lmL/ot/HbE1YV9tGc0LcvvOC4A8Of/V9HTNhvWvjW9feFO+7yRoXRfF051+gq0HOjAh68xVO8lTfGUR2+FYHm+tY6u5rsRZw+s8dv6Ct/beMDBXE9EoA8S6+I36jQbaPC105B6uLKjFpH4YiT/MFF9jQ+Z8gfIHCZesoxGCU+XotYYaurAz7E0/Wx2Gz2rf81O2zfst2aRzx+Qvx7/Il7PjHssdce8T+58jw2oU3Zb+8wgx5Sfwo9qB4b02btnbRpqVt1aCqok342roXbOKFNI1/EtmBMbdu37whffdPVYX3Db60/5LiDwuv/v7/kjO3qkA+6TGFx2FhTF6+RxBeTcl6zDspS5cYayVc9UPeO+I0/D/344fDgd/8QHrz792H5/SsyeTWoi/mkaZPCrKfODLOOmhkOOf7g+N9B4UnarGjrQ22oI1Gb+5BsZmA5jJn+gqE/xdHCbbwpP4Q0PgxbMCZHlRtYxNprFWt9tXU31aT5yb0xNpjOvWAB/3++4Gszee1rXxuuvfbaQF/n7sfgKeCNCs33ZNgbFei33c6bN4+/NWHBggWB5jvroMaFv/3bvw3nnHNOeO5zn7uz0jjvKCngjQqjJOQo0HTTqHDRxWeFqdOm5GzxH3/+9183AWkfQnagGscA0J5U0Hw2+GQ3Nkqo8Ehgx8JnY8iCuXgVIw6eSE61Z+IiruTQWuUiHBSnc8JmmgwCB1sIIylzHFmMHXjA2C0nyZkZ6mslugIvTAUvp9RKgE8JqRytk33RgXnC6FqjXbMxhtzKyshqTvEL6bb4DQtLbl4arvrqjeHhhx5l/EhOJ554Yrj00kvDy1/+8pHQeOyQKeCNCuO7UeFnP/tZ+OxnPxu+/OUv8zdv7cyXJzUsnHvuueEtb3lL8G9b2JlKjw63NyqMjo47m6WbRoVLL7ugLIP2HLS/0A1F2lfYvYgZ1+01iBB2ise4sIODU/GJ3AWWDcYGHlzhpyvXSXXTWC46zhMbZ8caneNiSLGXo1oTTRqkWtlCGM5IBciALCmP9RscRxk8uSSXGO2YeIHXEGZKOTiWQS12NqhfOIULY/gpueRozZ9ycgqdJSPVLZMVK1aFa2PDwk1zbxmVhgV6HV944YXBGxbSXfKBK+AKuAKugCvgCrgCroAr4Aq4AgOngDcqDNwtmXAFeaPChLvl3S+YGhNuWvibndqgUK1mIjcseKNC9dXg80FToOtGhXfJb1jLjQb53XCMsk/fvNfFdmNPupgHdflNdiVvbFSgQI1Bnrsuvzvcc2U336gwPbz1q9SoEJNQnpSbBlhVHLYcAFYweJK65ZOGGr6EteT8cQQbOIOtqQWvuRVz/+LfhEWX3mLJxnxMD6pTwwL9t/8z9wtHvuoIbm4opaxolkSv2m35Rj9dL98sNlfjWLkYXLHX6GcRiLr/lt+GRR9bYpO3jN/0hTeGfZ82szVHgQSjzRIBqY6KnXWo2BLWEvf/GiHNdsRGjF9Tk+KS34Q//OChsG3TyL5FyVZWHe+2x27h4OcdGA474cnh8Jccmr6JgpWhpUIiWmex9GJigFW7zUhk6qcLc8cTm6tx7Mx40LTonbUmCKIEDm4E0zXmSblpzslp0HCAsVJfqqNiN3xb1m8N8z+0KPzx3ocauFvNL33pS8OcOXPCjBkzWp1u2aUKeKNCs/zD3KiwZMmScN555/FvvW1e4eh7aO/0tre9LXz605/2hwlGX95RY/RGhVGTcsREw9ioIA8wlUvHw0nVa4mKWxXzcwqGpS3vP6wd+yzEyLYnYhVO2ORTI7vUiLHCc1zE2jx2zLXHALteHpMD9spY0rET4XJFcYiLVwASJ0wGw7AYCziCmE5O4lN+iyvWoo5ki3MaU5P0kkV3hm985Ybw0B9H3rBAD69Sw8IrXvEKXY1fxrMC3qgwPhsVHnjggXDRRReFq6++uu9v3ur3dX/44YeHf/mXfwlvfOMb+6XwuDFQwBsVxkDkUUjRf6NCTF7dV8Q59hhpL0E1GjsAjMS+IxqVileEWLoyhPYjNDJ4jDmAU4jTxsJnr9mfrbCRpWmM5KnOak1Uq9aXsELIidiF9bCdzbwu5MRVPHqu5sHCYVcuVUprYCeQTJS4ERevHJqLlrkYmUcgdl0MIZG4biw4cUe30goXuI0RWL5G+8oVq2PDwpwwd/aSETcs0C9FQMPCQQcdpMX6xRVwBVwBV8AVcAVcAVfAFXAFXAFXYFAU8EaFQbkTE7cOb1SYuPe+ceWPxN8Ofe119wX6JoVddVDDwguPPzC88aSnhT3jb+ieCMewNCose2xD+MG9j4T18eHH7TseD0ccPi0cf+yBge6ZH+NbgV4aFbgRID1bm18beH88NRNEyfDGOD1bm+JiCL/BT6HW3iBx4iA4PbxLuS2HjTN8S6+4O3yv20aFr8RGBSyA+PCQMI2tneY46jB1NsJ3YwdvvOKDBVpqOixHMsaBqe/+m2Ojwsdvsd5dPqZvXjjylYeHp//l08LBxx4U6NsZ+EDddl2wVatuwtTZ62zEZ+2GH1ozRO03nDU3PPSjhw2qdXj0a48Kr774leLopW5bh43rxm7KQN29vEYej3+v/2rR/eH7X7g3rP79GsM2dsPpT54WnvFXR4ej/+JpYfK+e0tiu3ZbCvSxftgsjsZNmDp7na3KYfihNUOMvcgJu62vKQ+wTGjuIGKb4mrs9O0pN8fmpN/e8YBlbTs+5phjwvz588PBBx/cFufOsVXAGxWa9R7GRgX61oQPf/jDgR5+3pXHfvvtF2644Ybwkpe8ZFeW4bkbFPBGhQZhdoG550YF/Tebd7V6ElOcyB++0kncfOaVyZyG8KWR3dannwdoH2I5sF1Qq+bJHApmLruHsbKmWqkKLQi8zJTKTYNWXHRxDRliai7XR0ixSMIUwhyKzQUkHg7ikBTBVMhrNUAGQxOxsAoT68GmGGkotTxej7iVOU4yrBqD7ALiWSUfZ1UC3AtcyYd66Er/274jfsPCwjvD175MDQuPSNEjOL/61a/mhoVXvlJ/ZhkBl4cOrgLeqDD+GhVmz57N35C1du3aXfrCO+OMM8IVV1wRnvjEifHe/S4Vu4/k3qjQh2i7IKTnRgXsJXj/IJsIMWG/ERfBQ/HZDQ1bCh9BBae0rAD2IrL/ID5FgVJj8gWOiEtDHVQ0Ra3AcQUJivhkSHwFLrq5ogyLOJkkfsrLJrXzXNehPnhyrFjIjQM+nkc3MbTayEt2RNHU5OIpB9fgJIZ5aYg4wGURhlsckorGyJssQshcXBWd+LB105jnRBH/t3KlfMPCnBsXh82bNmeOPkbUsPCe97yHm+n8fcU+BPQQV8AVcAVcAVfAFXAFXAFXwBVwBXaSAt6osJOEddquFfBGha6lmhjAH/1kWfj61f8dNm/ePhAL3i8+oHjaO44JBx04eSDq2ZlFDEOjwr0/eiR84+pfhC1by9fHoU+eGt777ueHKZP32JkSOfcuVqCrRoXzTgjHn/b8+ECwFstvhOu74dGEUWpIIFt8Y5wdMcbayUZvlDNV8fCtciOH5Yjj1KhAMOWgIQ6bo+dGBSKhem09ICa7Peow1o9xO742HKyNTdkGy6k0z/2L4zcBDFijAqSg65QDpoSnxwf8n/G6o8PUA6dECy3S3GwCdaN1k65NfB30o9cpqnjsvuXh2tOvp0raHvRNAW+/5s1h71n6sH03ddcxNq2lyW45bM42a6QGhd/c+j/xG0Z+EFY9sNoy7LIxNawc+uInx6aFp4UjXnpYID1rjzod7LopqG7tdXGErbPX2QhrDvsaYXNdTuCb+Mhuj1qOhv9P1GE1D31Dxu3/79Lwi3m/suxtx095ylPCwoULw1FHHdUW586xU8AbFZq1HrZGhc2bN4d3vOMd/Btwm1c1dh56kOCqq64KJ5100tgl9UxdKeCNCl3JNCagnhoVzL/n6V/2aBNztMgfvtKJfx4yq+AYwqvN+g11iiN/HSYzxCxlIDOLiWJN8pQTtswNPHnsOCGlcPHFMeevcKMOMkvdEv24rlYocuW5tlwHRYCnOmY2zZ0wWkOVm7FCUGpNSeVPggBAlYlbSHN9TMR4tqlDUNEc5/Q/DqYpI/WkE9Rbd4WNKWLY9u3bw+JFS8PXv3x9+OMfRt6w8Kd/+qfcsPCqV73KVubjcaKANyqMr0aF//iP/whnn302/z0wCC9R2j/SPpL2k34MlgLeqDBY96Opmp4aFczGI+0laI8Be95qFPsO5OYY3pOIJcXFKSjIAztd05gddKJ9TMqe/OIQO3Ehju3mhDziz3hipaMuTmKoFgLQHz4xHifEcW5CCF18L1cGfI5GNSc/sykYHMKZOVpzKIu9GO4qnsulHMgDAF0Th+RDhQq1gAglDgnWC3OKXSzJbrmptkyYxmSDHe6VK1eHa+I3LMy5YeQNC3vuuWdqWDjkkEOkcD+7Aq6AK+AKuAKugCvgCrgCroAr4ArsMgW8UWGXSe+JVQFvVPCXAitAD/bOnf+bsPiWBwZOkSc9affwljc9Ixz3/AMGrrbRLGjQGxWWLdsQPv0v97Q0KUCDY56zXzg9NpX4MX4V6LpR4V2xUQFHfHc8vYken/K2TQIJQu+E07vodX6123fhyUSH5eI31dVRNCoINIVrIKyhr0aFFD2cg0FvVICqu++xe3j+3x4Tjvu754Xd478Dg3Tc+v/cGX4x576uSqL6X/Te47vC7irQoz9fFm7933eGFb/Zdd+k1Gnte07fM/z1Z/8qTD90eieo+5sUiH/Hfuez94Qffv0nTYgW+wEHHMDfrPD855u/11tQbhgrBbxRoVnpYWpUoCaFk08+OcybN695QerZY489+JtNnvzkJwe6/7NmzQr0DQiTJ08Oe++9Nz8QRnsg4ty4cWP8xrP1YcWKFeHRRx9l7MMPPxweeOCB8Pvf/z5s3bq1bT7KRQ+Z/fVf/3VbnDvHVgFvVBhbvdtlG5VGBUqgP/vwjy56kgeD8FOO/ugSjckSB5gJVirNDxbRQ0ZMzo6MQZTktXzMqAbwCKuUKGMBwN+aIzGavFpLdHH2ElI8DFX6NRcxxUQIK9aSJ4lH4EBzGUkL1M3WCEEGQ5MCEgPlJoAasl2htCp2Z0DCmCDkLnzgjlTZnicUwysHNSUityRMPsSSnRoWlsSGha/FhoU//L79t70xWYfTn/zJn4RLLrkkUOOCH+NHAW9UGD+NCp/5zGfCBRdc0PHFSX8/7LvvvoEeDJ0+fTrvI/fff/8wbdo03j/SXpK+BYHeP9uwYQP/t27durBs2TK27bbbbryH/N3vfhdWr+78iwxOPPHEQN/yQA+l+jE4CnijwuDci3aV9NOogL0A88b/v/NegSbRwT6+0olnKb34eLehodlvoeCjq9hxBVUNh5ArL12qMbYc+CQ/cnCU4WEyYoo21CRrJAO8coWfsQJSgAD5HJ0Ik5wEoVpgNXnIY+yM1Hmya1iVm7B0ZJwAeR6HGqYgXEQTVJhTZzTimVvCKAmtgK+lHQCpQzBiQ110zeMSv2rlGm5YmH39orBphN+wQP82/P3f/3340Ic+xP8u5Uw+cgVcAVfAFXAFXAFXwBVwBVwBV8AVGEsFvFFhLNX2XHUKeKNCnSoTzLZ+w9bw5a/+LPzyVysGeuWvfPmh4fV/dVTYfff85txAF9xjcYPeqDBn3v1h8a0PtF3V//2JV4a99/Kv+24r0hA7R9qowL/su+Y3fqc32esaFZJe+v97et+dbPFUNCTwG+vR3pYjkaWBNyokKQZ2MO3gqeHl570kHPaSJw9EjZtWbwpfOeWqsK3Lbx7ac/qk8PZr3xKeuOdg/t3489hwcednvh22V74pZyDErhRx8v85Kez/zP0qVp/2qsC9X/1xuPs/v8d/X3YTSw+20EMnr3jFK7qBO2YnKuCNCs3iDkujAu1dTj31VG4IaFoNfYj/hje8Ibzzne8M9HAR3feRHtTAcM0114Qrr7wy3HnnnbKHqiGdNGlSWLRokf//vUabXWXyRoVdpXxr3m4aFS78yJlh2vSpHIyHfhITP0QUZ/HKzxKRQ3+wkQufYWKnWIAjOD1MRIFyIAdds70cExL8GaMEhs9ywYtr9iVLkY+s4AaWkTEx1SwFECYXj7HUxgwIYTIgJURmiGFgPGGOKwgUrTWBiWkpSmAwa02IYXeccN2cg+EcVrUVaxNWAVN8wUtmJuVr8lk9EkQq0TKFR/mQTxEpB4VSw8Iti+8KX/vS9eH3Dz5EphEdr3zlK/kbFl796lePiMeDB0MBb1QYH40KX/jCF8K73/3uxn0cvdpe8pKX8B7ylFNO4UaF0XgFfu973+M95Ne//vWwatWqRkrKefXVVwdqcvBjMBTwRoXBuA+dquimUeGST56v/+7H3QA2AiCOBuwtzHYj7WUQkON4RyHRadtR8oKPrhKHa0rKAw5PGPjMPignzTUqDLw0zTCbR4qDDzVxeHRFJG+vJF6x1saOdCIPJxIkcmockhAmHsiFqxg1XcQiG9sZT6NolT9iTrjsE38VR2HKKBeZJy41UgaqM2EkjSQVI/l5RDg9ZK45spm5wAct4bbr5oaFq+aE2deNvGGB3m9AwwL9MgY/XAFXwBVwBVwBV8AVcAVcAVfAFXAFxlYBb1QYW709W6sC3qjQqsmEsmyOD1pe/m/fDw89vK6vde+22xPC4YdNC08/embYb9beYcqUPeJ/T4q/QQm/lWlbWLduS1i3fmv440Prwi/vW9F3Lirw+GMPDG8/9Vl91TroQYPeqPC5K38U/vsXy9vKeM6Zx4Ujj9inLcadw6tAT40KeGc7Lpfe7I79A3LUNCrQO+gJU+fnyIIwWpQRxOYN+PiprSarXAwFwrtuVDhsenjrV06pEFamxN+QuoLsfdrEXbOmgrwm7v4lvw2LPn5LARuGyXPf/OzwkjNfFJ4Q/91pPGrW24htcjRxaNoffu0n/Fvpm8Lr7K+84KXhWW94Bn92NCivkR1bd4Q7L/92+O8bf1lX8kDaTv5P06jQdJ86Vd4U12Sv42vCkt0e/fx90MRtefsdG+6fz/lluP3Td4XHd3RX5F577cUPVp900kn9Zve4UVDAGxWaRRyWRoVPfepT4eKLL25cyJve9Kbwz//8z2Fnfmi/ZMkSfjjgt7/9bW0d9Nt2f/jDH4aDDjqo1u/GsVXAGxXGVu922Ua1USEmSj++4IEitsV/rHU/oY8ZSUnJJoE6NQ9REV+yZm4lYw/lAURY+Yy46tVAEreNB55wTWNwkJ8xmt/iLYa5+JRXb7F2bOOSHfwVjiRqtFssZ0kxaSDUcUp+rDnFMYdA6FzY881LdmWVACYjTrGma6ZLPjahJKMfxYAT8SY8/ii8I9xy87fDV790XXjwd3+0rr7G1Kh66aWXcuNcXwQeNBAKeKPC8Dcq3H333YEaiLZs2VL7mnr2s58d/u3f/i286lWvqvWPhpGaFM4///zwxS9+sbFZ4rLLLmu71x2NOpyjewW8UaF7rXYlsrdGhXLvwXVjn0CTuElo2SewLTvyTkLwGkbELbG871DCct8hxhjCJHKlcT6AFw4lye5iz2PjEUfQpjHTRMoqt8UjFWxSausaq3lsHGIhTJUjq21q1bqYl8k4KkGrmqUcEVunQ65Yc5R0FKXcERkJ2K1EClVIGch5KdTEAG9r4iXE05rV9A0Lc8ONsWFh48ZNMPd1pYYFaryjb1g49NBD++LwIFfAFXAFXAFXwBVwBVwBV8AVcAVcgd4V8EaF3jXziNFVwBsVRlfPoWLbER9O+9wXfhx+8cv2D59XF0Xvcz33OfuH4449IBx91AxuSqhi2s3XrNnC395w9z1/DPf/pvk3MTVx/PmJR4S/+PMjm9xDax/0RoUvfe1n4d4fPtJW33/4wIvCwQdNaYtx5/Aq0HWjwmnH6pvica3xGdjH5aQLx1veTQ/Hwk9wi2myKy0+MeCpjVN/DOe36uPVfhNDL40Kb0GjQrURwpaGcqiEOjv89lpTbnLXcXTiTn4bHI2ahxoVbv7ErSnFMA0OfdEh4cRP/El40mTz26XTeisraWevQHlq5YK/wkEPdX/9rdeGtT029+0TG13e8uWTy9dEhRspa6+EbTq6qLsaun7ZhrDwY0vCo/+9rOoa6Plf/8frwv7P2r9SYxTH6tOLHk33wPLZbL1w2zgeV4IH4O+R397xQFj8idu6/jaNJz7xieHzn/98eMc73tGyOjeMjQLeqNCs8zA0Ktx7773hRS96Udi2bVvLQug3z9Iazj777BbfzjCsXLkyvO51rwt33XVXLf3rX//6cMMNN9T63Di2Cnijwtjq3S5bt40KU+M3KtC/+sUDPrwNoIeHKEM8yR9Jh4eD2AWMuvADBcfpVtLgkQO8crW5JbDqF3biy4VkLk0GULxmnzFSNOrCQN3AA01zthGeU9blIDRXRAkJxoflsmP1Sg3AIyg6iSGXpY54kZEMeKyglFEAgiNezDGQxNlOSGDATvPESwEJwGOeMbfY1UvAGGaxeQ797LrAw4F6kvD4iwK4YeEublj43QMjb1h4+ctfzg0LJ554ok3n4yFRwBsVhrtRYePGjeF5z3te+NWvflX7iqNvMvjKV74S35/fs9Y/2kb6mfB973tf7Z6Wfmakb2Cgev3Y9Qp4o8KuvwfdVDCiRgXZDOi2I07kj6SlvQYK4H0HJgRTj70YPPYj2FeUV+KRwFa75GB+cAso73G0DORgNsWWvHGmsYJJIGWI/vjLbBImutO6EoI4OFoqjhOwpLjotmMJJV5j1yC5iA84vhIWzBinmDQQKE8zh82tLqWMM/7D1jzO04gTDF9phvXJolGR5i0CZc0UbmIUIXHKwcHMLdjVq9dyw8IN31wwKg0Lp59+OjcsHHbYYUjlV1fAFXAFXAFXwBVwBVwBV8AVcAVcgZ2kgDcq7CRhnbZrBbxRoWupxh/wmm/9Mtz1nT/0tLDnPHtfbhIYrYfRf/XrlWH+wt+G3/xPbw0Lp775meFFLxhfv+Vz0BsVbr/z9+G6G+9rfL1MmrR7+NQnXhm/4htvaTZC3TGkCvTdqFA8kIvXRzdPAltMv3EqdgznDwyIJtJys0Ic9tSo8GX6RgVbk3LjotyY8rWp7CZ7EayTJizsNqZaHn2oUOgfQreNCke/9qiw5/QuPuhW/h3bY0tKfJB/+9btYdumbfzfpjWbw6ZVm/jB/u1btttK+x7TQ/9/9ZnXhCn7Ty5vh9XD6gC7tTVlB5b8sDLMUQAAQABJREFUVXz0/fb2B8LCjy5pim5rf+0/nhgOf1n8LVE1vBzYrb0uC+pu4jAxj923PMz7h/jbr1ZuNNb/n73rALCqOtojVVRAUGyIKFhQo4IlihJbYo0Ne4ktJr/GGH9joiRi4h9LTDTRqEksUdGoqBTFRhMUpEixAkrvzYr0Xv4zM2fOmdte2X27+xbOzeadc7755ps5sw/v3bd39lZsWqduHWix/47QZNfGsPX2W0Mj838cG5onK61btQ7W4Pcf/79kDaxatAq+nvwNrPhmZcWCGS9qVNi/Bf5mjDVi7+2IcFpNBEOirpXgGouIxRZZfMGFHtcrNO+EnxUsFJf4epTcYhrzP1oIA7oOhnUr12l25hx/gfnAAw/ATTfdlMkJhqqrQGhUyK5tbWhUwJs8R4wYkdgENik8+eSTcPXVVydsVQmsWLECTj755Mxmhf79+8Mpp5xSlSkE7QIqEBoVCihSNVGKbVTA6xU6/cqLGWmK+TqbQ9wNQUKXbbmfYdBN+5IM+/Mlho/nfczMhdBz1LIGGTzR+DgnSkPWEodA+yJYzCWiQTdAIQFllbSfcm68ljztSglLHhxa7Kip5pKXDcQmY2eKDORjIe+PvqJl5xI+GpuDoE3XkeYSyhhZXwASTMZ3PNYUgsSLjDaey8m6RHO2OXFw+rn33cHmCQvPvgKzZxX3+Z/I6/GYY46hhoWTTjpJw2Fe5hUIjQq1u1Hhrrvugj/+8Y+p77KLL76YmhTq1q2baq8q8IUXXqAG9o0bNyZC4FMdhgwZksADUP0VCI0K1V/zikQstFEBz/d0encjRuPrDD7tq7lcLDCDrm/Y12co1y1WxXPQx/rzYJjW2WsI5rmibLM0BkZEi+LovCJzsooEjWjWvmLUWLxRIa4ie+RUMGeblCFmzSVxopoX8vBuZm3VxGBtjiI+yNM2wQnDXHhHOg+/R3Rlfxl5b96PxK0W28yrxCCAPHHGB8nFNC3GuXhtkkUvmyStkStJG9PSpcuhl3nCQh/TsLByZeU+Y8bPuvDzkN///vfQunVrzje8hgqECoQKhAqECoQKhAqECoQKhAqECoQKlLwCc+fOhUceeSShi5/3h8/8E2UJQBVUIDQqVEFRa4PkkPfmwGtvTis41RYttoGfXHwA7NGqScE+xRAnTvoWuveYCMuXpz/COq5Vt+5W8D/XtKcnOsRttXVd7o0K69dvhL8/NBa++HJFaokvPK8ddDxyt1RbADePChTcqHBVB/qs3N0JHLsxlo0JkIukPvDmG4mFhx+JyzyrnvZj9K0UT035w3UL2KG4RgXzF/Fr2YHbtFVxmRfaqHD+0+fADm2bOT+cpOlFCFkL47h47hJY8MkXsPCThTBn9HxYW+B/79Mkm7XeHs765+mwdZOGaeYqw964qT8s+HhhhfRbHrornPHgqRXyLZXTcvPf71d/8Sas/LbizQJNd28Cux/R0vx/N9it/a7m6Rb1i0pv+Vcr4MvPvqKnOXw5wYyTvqEGl0JEXKNCIeRaysEn0MR+lVjlO8EGEmxeWb2k8Ee3d+3aFe6+++4qzy0EiFYgNCpE66FX5d6ogE8nOOecc3TKbn7PPffAbbfd5tbVOVm0aBE95WH69OQNfB06dIAPP/wwcjNCdeYWYnEFCmlUuPDCC+F73/teKFkVV2D48OEwcODAnFFuve16kCcq0M8eeEOPvckIHd11ufmZR9/oI6KIeY6gxs/+jEQ2xRGctBVHcBqtoGDE9VFUUj6O1tNzrYE4HhwW98Nr/Sp8HGmOHMWTKY3IIWfRsislLHocQ9l5GslB1FCU5sJRCUb0bBzK1XJczmYd4YodR8kb44iG5hPGwW0K5C1cllAWO0V7GodxktCl9FzjH9mvzQkbyt99ZyQ8/8yrpmFhHgtU4hX/6u3xxx8Pe++9dyVUgmt1VQD/2v6UKVMyw+H3Meuv9Wc61RID7i3tOkfSxyaON998U5ZlN37zzTfQtm1bc0Po0kRuJ5xwAgwYMADq1y/uZ/KEUAWBXA18ffv2hdNOO62CysGtVBXI16iw//77wyWXXFKqcEGnghV4/fXX6UkkWe7169eDP951s7rmoJN99HwvzrHrBw+7KyO8UHCHXGsQhL7WIjguZU7XINpuyWInrlNAR0vGqb0eIY6dp2HeA32IbUdt8XppjQrsxXyWkH2Z0WoSJyUnnTTlZ/egqGZbAiLbzP3SJen2phwRIyq5KD/FEQHkiUY0D4ku/sh0KfBc6YmGJlEeliN2XhptlpMtRfUwpBAwpp0vxScsvGwaFnpVvmEBm+7wc4hjjz0Wtt9+e4ofXkIFQgVCBUIFQgVCBUIFQgVCBUIFQgVCBUpTgfbt28OZZ55ZGrGgEipQwQqERoUKFq42u82dtwwefOQD9xfF8+1l/3Y7wBWXHmgeIV0vH7VS9sXmLy53++94mDM3+cuXNOFtGtWD27p0hG23qZlfyKTlVBms3BsVcG9LzPfohZc/B3wShhwN6teFs87YG47p2FKgSo3YRGN+hw4nHhce91qpQlaBc1GNCoU2FVCeePs7H/QhN34obiBCnclNhCoedlR280E5fVZuIEKdyU2cRjGNChf+t7P5oN5+Yo8Kaoo3F1Mw/NBeG1yk6ET+ELz6fD9KKGAlT4WIxIvkZEQoUIQB09+dCYP+NCRvhHijgqsl7TGveypB6rR+zQaY+e4s+PyNyXTTeio5D7jTAS3gTHPjf70856ZS1XrRjO+g109fy5NVbvN5T50FO+zdvEbeI2tXrIU+v3wLvivyCUayo13b7wJHXN0BcMw6KvIewScsTH17OkwdMB0WzfTnlrQY0qiQ772Pvo5TwD+ykrxH5L8BJrb7F6f+PUZy0v+NUBz594Fmp4GOGUdJ8rYiS+YshbduGQDYzFLogX/171//+hdU91/vLDS/zZEXGhWyv6vl3KiAf2kWP/wZP358YgOnnnoq4I1c8kv+BKEaAHzM59FHHw0bNiSffNSzZ084//zzqyGLECKrAoU0KmT5Brz6K4CNCk2aNubA9hqEB76Adqd9Azrcpkk2xCVtOyEkNheO/LfDjegrGoaU5uvlnShBouHsnCDnI3M7CgdHhmQ/3uL0MI+4fzS0t2M0+rIE0k+f0+7IRA4UWJa4kEpKbN4IyRPX+zPbhjaw9bRibsuCO28MIlFwGs9DbILLOupHckQRHgdAPZ07eVsehsLDDpE8MCeyOY6ZOKK5RjYftgwdMgqe6/YKzJo5l7jhJVQgNCqUb6PCLbfcAn/7298Sb9IWLVrQteXOO++csFUXgD9zYzMCNkvEj0MPPZRuvHb/HYsTwrpaKpCvUWGfffbZbJuUqqXA1RREGhXcvyd7zWHP+HSej8xp4U/+vNTXIZy4XFvgCudyfUFrdz1hlWXNRr60sCFcXmgzh9altRZGu2jJyCR8jRxoFq42CEZjPAdZWwfHxYzpyxKMXWxI9XO2c2riI2I80v7Ex8txTYiiahnbo9Mlf9YzwZUvpYkJMUYpcB7Ixjx9SMEVFrGrfVkn2WdyJHUMS4eLofVk7jhm4ogAy5etgJ7mCQuv9OoHK1dU7gkLnEV4DRUIFQgVCBUIFQgVCBUIFQgVCBUIFQgVKGUFfvrTn8JTTz1VSsmgFSpQdAVCo0LRJav9Dv987COYPmNxQRv54fGt4centaEPwQpyqCQJ/2p/r1cnw+ixhf3F6mM77Q6dz9q3klHLw702NCpIpb5dtAq++GIFbGv+kvZuu24HDRqU5hHj7wyZDW/0nQ6Htt8ZLjfNMeEorwpUR6MCfsBNH5bb+/650wDrQLdApxREPhFXdvqcnHF34zR5Ko5VKlmjgtwxbHTlw/6UZDkLlQZlKVvIckjB5SZsNKlfRzDT6mVxKtSoYHJWafPvIUqUN/5V/ZH/GgNfTfw6Zae5oT2OagWn/eVHkV+MaA/1bSFYfuGiOYXMsZbDHngfJr4+uRB6JmffU9rC8b//QbW/Rzat3wR9bx0I8z8q7NyqN7DrIbvAYVe3N09P2KXK8/522iKYMmCa+f/01L/uj40KLdq1MOnJuzH27k9579O/kBzv1VK+R6RukaxcTmjlvCN2hB1H9mWgPG9WnTe559gjhkg74v+NwKddvPXbAbB4zpI0eirWsWNHuOGGG6BevaptZk0NvgWCl156aerN5FKK66+/nppHZL25jDNmzKC/JJtrP+XcqIA3++NfvI8fDRs2hIkTJ8Jee+0VN1X7+he/+AU89thjibj4V/o//fRTqFOnTsIWgOqpQGhUqJ46lypKl66/hMZNtsMTuZP052lzBSALM3qKujIwoPNEjqzU3PuhBrMzR8lC/JkuaMLfGczEaSIoeengDKPVcWmh1ylxRRe3hum4Ne6W8nO7Jjlv11w9Fz+JjqL4hTgJ0lqsjNhXGvQcfa2e+LIc4aiBbHbDCHzE44gdrcwxr/SFLw6x3o7k8hU9Gb0vytj8xE3rqZxRHJcuS5lzeOpnf+/dUfDfbr1g5ozQsID12pKP0KhQno0KX375JbRp0wZWrkw+ERF/qYi/XKzpY9q0aXDAAQfAunXrEqn06dMHzj777AQegOqrQGhUqL5aV2UkbFS44+7fcAh1rqdTun1hmE72cqlh+O4qgC4K7CUAwt6i5ko685pErk0SWg6QNBkQvq6PYDg6Nx0cM7cG4aK/ntMehETG+J48n6KQnooX0/PahuOTUnMMojSF5LgqvuJxrREgb95DxIfIaCQK03yeLi/rI2svYWb0hS+M8itJqri8dv7CxZG/yF98aRQOJScWJ2ncxBFdvV03LKxYnjx/2czCECoQKhAqECoQKhAqECoQKhAqECoQKhAqUM0VCI0K1VzwEC61AqFRIbUsmy844bNv4KlnxxW0wZN/uCecdkqbgrilJnV/eSKM/TD/DZV1624Fv/vtUbDjDo1KnUK169WmRoWqKM6gd2bBW/1nkHRoVKiKCldes/BGhfbRYPzpNmPuPlw3SeFaKIPCVvkAPIUkJiSmmK06DcU1KpyLH8FHDvoL6IRoSzyotkXcc+gJL803qu9/fcE+aTlplYIbFZ46B5q3bSaJWHET2/zyQeuhwcfEVdyKGB458jamKYOmwejHPoCV3xb3V5eOvvFI+N65+3MIes2Kn8wsf96c85pla+GFC3rA+tXrVZzip3Xq14FLX7oAtkmcsyqaM+aQ5hut9ZC/DIcp/acVlTA+qeLY3x4Ne/+orfKL6qbGxjvoK/kewTpPeGUijHv5s0jDwjmPngE77b9jZM/x3fP3VKPxnHE72i7bQ15F3ttJ/biKf59x3Hj0uJ0ziuvGvSTv5G68nnDSfKP6kvPqJauhb5e34etJ34hzGGtRBUKjwo1l993ChqAOHTrQzf7x5H71q1/Bww8/HIdrZI3XeHiT4qpVyXPwK6+8Ap07d66RvEJQgNCoULveBZmNCrgNuT7CG3nwy52e5SyMmANzzH1NhI+jzDkU6zg1M6EoDmAN8ZHRK/tc0MXZI/l5trNHuLljojf6iSRrcII6zVRtFUfbURMPwWTUl36+2p7HPuTKvnV0BgpHbfw/5s2wi0VLAS0HMQ/hXs3KbtjjniT5xkcU0Zj4CkZxpJC4sAfxJFelgWbx3WiesPAePWGhN8yYPkdcw7iFVSA0KpRno0KXLl3gvvvuS7wb999/f3qaQrk82S6r4fWII44AfHJXOGquAqFRoeZqX8rIORsVMBCe6+U6gM73HN1frfjzPtPlSiKOs5/moK5oy0h2oWI8ulARgEfhyihWvca5y0TyN0Q1dbHR3/nSHp2nSDs7WShv8rJ6zNdeTk9pp2EuQBpPCard+FzEbkbS1puzwhITqTh3LsIVQMVHVweTj1lZvsMViXTFLrqih67ETYktHLSrI5GnDSp7Qeoy84SFXi+9Cb179oPQsKCKF6ahAqECoQKhAqECoQKhAqECoQKhAqECNVSB0KhQQ4UPYSMVCI0KkXJs3osNGzbBXx8YDV9/nf8vWRz8vRZw1eUHyedb1V6YDRs2wqP/+aSgJz8cctBOJtfvVXuOpQ64JTcqDBg0E/oPnOlKGhoVXCnKalKhRgX6sJs/8aa/AO7ujXWTCuzRfvpNnpXRAahMo0L0ZuB8OWm7Sdz+OXT9AX5ET7ZFbtpXDL5s/tcI2Q0DWmHauzNg8J+GeoGM2flPnW0aFZp7q80Zgfx564joUVjeK83TWgb98V34wjxlodCjXsO6cN6TZ0PTVk2Ui4ovedMvbjwlvd7KT+U8rsdnMOrfY71zJWYdLj8EjrimQ4qCjm3MJXqP4FMg8GkQxRxNWjaBk+86AZq3wUYVnVfy+xixS63RS/3iK3+tMbuk9vpV6+GzVyfCpy9NgNVL10C+RgUfJ1/OGE9xJG8DZf57kvTUvtJyZmWv7XPyMb0VFUTY23GWrq09kcK+mbUWGXLTvjomkqL7XrtyLQy8/Z0KPYGD1cJrTVUgNCqUX6NC37594cc//nHiLdGoUSOYPn067LrrrglbTQG//vWv4R//+Eci/JFHHgmjRo1K4AGongqERoXqqXOpotxqnqjQhJ6ogIr6qgKXdo3XEvjlTs2e587p1uYs5MJgxE94qO0N0Tmngq8RXK+1r8ZpzgBfOVG8eB5xXczFOJn/U/5MRxU6dCyZc+rWz7DIz/KdDuIpe9SYuIiPs9kcePALF8dAFuUYtPCgLCUzTMP56ryIyFmwj7DIgX3Y4OL5id+f5C0jcmSOI0qQDIayNWFZh1ISzod46GPslpLgbwR4b+hoesLC9GmzyT+8bDkVCI0K5deosHjxYmjdujUsXbo08UZ86aWX4KKLLkrgNQXMmzePGl7XrFmTSGHQoEGAN8uHo2YqEBoVaqbupY6a1qhgT+ccCq8N+MRO53mZa45cE/jrAGs1g7tacQ6iZ2yk7QzuegQDE2pNTt9uXtYyWjjqbwW8Dotx/uwR9bd5GVoUT1+LDu2Ppd1eSR11eBdOT+vqueSPdPRxNqeLDL/wus6TfYhCImSQpWSCOYsvKfpNKD552WisRT6Wy1ZDtxO2kbvLW/KnkSW8janGnwV4cKosKzbkmjlZLUW0RWb5spXQu0df6PXyW7B8+QqBwxgqECoQKhAqECoQKhAqECoQKhAqECoQKlDNFQiNCtVc8BAutQKhUSG1LJsnOOL9+dDr1cl5N9dyt+3gxusPgwYN6ublViVhxcp18I9HPoBvCvjr2v/7y8Ngz9ZNqzKdKtfeUhsV+g2cAQMHzYrUNzQqRMpRNotKNSqYXdCtse7+WDepwP7kw/HKaHDYYhsV0MtH1/E9mr0hy5Gboi1RPsB3NyxrWQoo2riIG1lEfonhNBg2r+wrCmjHJyoU3qigblRXeSdyxnjx1OwvLZIGl5zJbivjFnXcuG4TjHhkFOAN9oUeOx3QAs7+5+mwlfvrpwXWGgNEw7tfxIgB/xr2y5e9AksXLCs0nZy8rZtuDZf2uACwwSJ5VDBvV2tU9Btau3wtvGRyx7+SX+ixR8dWcGLXH0CD7RpYF//uydZI5l3K9wjeOD9r+BzY+6Q29hdnkpO8w3HXft+cp3DiuOwimTNaSpF3vn+PFMemkZ53Vs7KU/17JNS+ByJ6WibjPWLToEHnvWHdBnjn7vdg5tDZmhLmZV6B0KhQfo0KWTcH3XjjjfDQQw+V1Ttq4cKF0KZNG1i9OnnOGDZsGHTq1Kms8t1SkgmNCrXrO31r1+tNo0JjukCR86rbgbn0IAwvQcx5mU/NfD3Cr/Y6RBbW0fmgm/kff1k/y8XrF7mGkXiiz6OgSQ3Uw0P8ZWSUwrkX0WS+MLwvIz430orpey/vJzlaz0htXH5monOTuYxOV+JZR8lZYtjN0CD1RF/r5mMQgDGtstIVjPzFjKBwRc9gBJGDYkdwFnCudoL7cnszmMwJF30bG5PkOAigH49iphVqMMvlSesYjpeYw4aMhme79YLpU2dpiTDfjCsQGhXKr1Hh/vvvh1tvvTXxrsOnKUyYMAHq1KmTsNUkkPVUhdNPPx3eeuutmkxti46d9bOIFGWfffaBqVOnyjKMZVoBbFT4490383lcn7clX7pmsAt1/UCXAw4mR/GgUa4DcIFzff3Ac4MrPXEWnnA8zhFJl0XJpK9hhEtml2B6bOY4klnyHhAhTWsSfeTLIZjkSDmRu3VCovjT3nkhfmQWZyfKE9mfcD3NCaKipCvenDMJ84vzc25SB3R1oNNyrjRBBsdQbDO1nlbcqlAu7MaIz501EEXM8ZGMB2IOlLkDmC9+Hna5OUXDwSYFbFaghgXztIVwhAqECoQKhAqECoQKhAqECoQKhAqECoQKVG8FQqNC9dY7REuvQGhUSK/LZok+8PBYmDsv942WdcxNnr/7zZHQosU2ZVGDmbOWwMP//jBvLocfugtcdvEBeXnlTNgSGxXe6jcdBr07O/FtCY0KiZKUBVChRgXMXD6o1jfNpoN2n+gQIVs83+D98AYL/0G69pNkGBvx8Cj44OmPNSF1vv0eTeHCZzun2gTEjKPqYinRSOISwUSrSIlMKtSocOfQvEnRExXoL+rnpWYT4jkjs8C8h/9jFHz+2qRs7Zjl2N8cDe3O2DeGVnCp8p7z/hzo//vBeYWOvPZwmDZ4Bnw7bVFe7g9u7gj7n7lfXl7RBJU3FnrUv8bCuJ6fFSyz17Gt4aT/OyHxRq7S93YsZ0q2wPdIro1Vac4YeAvIe9PGTTDswfdh0ptTcpU62MqoAqFRobwaFcaNGweHHHJI4h3SoEEDmDZtGrRq1Sphq2nguuuug8cffzyRxgUXXAA9evRI4AGo+gqERoWqr3EpI+RtVJAfUPCGHpmbBOiyAhMhPJmRcOlmH0OWm35Egm4skoVyZ1wBGAKjKQ2c4+FipOpoDjtomvhaFg1oJzymzxytR+nYnBDH2vBILPEn3C4cB+lSDXIlF3wRVLR4ZAuRjJTO2yl7YiR/IyhukZgSB+001zxEUM9qWpP3j+M6PbGRP7pwJHy1Jk7I+pCVAojdRXN5u/0qE+taQIRxaS6mh783Bp55qidMmzLTxwqzzbICoVGhvBoV1q9fD23btoU5c+Yk3m/PPPMMXHnllQm8poEZM2bAfvvtB5i7PvC/MZMmTYJ99y3RZzVaPMzzViA0KuQtUa0gVLRRATcnp3y6BpCF2rVcG/jrCya5SwIzEY64EYNwQXiUaxEaEbLx0D+uQWaXD9q9A89xzdc/PKMVTdFOekrfc3gm8USWqdE4Lj+6tnJiAkdztmbOwqrRIJpsoegGj8TnlByGAYwXvvBhRxzEDw3EEUxx0GaIVoMN1mxxthMNX/BwBKRgztaPislmwpntXw3N5+r9PMHqCWDjiA+NaLPxMI+VK1ZRs0LPF9+EZcuWi2cYQwVCBUIFQgVCBUIFQgVCBUIFQgVCBUIFqrgCoVGhigsc5AuqQGhUKKhMtZ+0eMka+NM9I/JupOORu8GF57XLy6tOwlPPjIMJn3+TM+S229aHu/7YyX3IlpNcpsaKNiqsXr0eFn232vxVkrWwctV6aGiehNGkSUNo2qQBbLttA/c5YLlt+423psE7Q5O/dMM8Q6NCuX23OJ8KNyqkbsd+ck02vKVYjixc7LlG9sW/gC+HfA7Oa63NSKkaFXxE/nBf4pd8dBsyEXXQIgJVa6MC5uVyNnP1vcmXMt4kPeD2d2DO+3PzUcm+3c7bwcXPnwt16pXoLwvavPv+dgDM+2BBzhzq1q8Ll/W8AOaMng9D7h2Wk4vG7c0TgC7sZhpfkm/JvL55CTbvJXOXQs+rX4WN6zfmdUHCTvu3gDMePDXxpAd5m1VFqi6xCr5HnH9sIjkjHPKOFYeKoqqS79+kKeaYJz+ET7qPTxEKULlVIDQqlFejQtZN/1dccQU8++yz5fb2oXzwL6q2a9cONm6Mnjvq1asHs2fPht12260s896ckwqNCrXru4uNCo3NExXwTCs3APmLEby5B/djXvgLSW6DbLK383iY7KKFVqeBSpZHNxbJwiqKHi61SWv53JDDYjJaGRrYJLFJUeG81jGMGsUkLbWXuDauOU+Ss+lIHOtoBp4hbjFEBBcNn5YxCc+AxBNNjiPOXk9imNHF8L5OLqbl4thwtHZz9EcEnRi0JkqC4sRx54s+nCvzcMkYKXqzJXm7OOp9kBT5xB0N2+UgNh4lHv78NnzYWHjmyR4wdfJMjhdeN7sKhEaF8mpU6NOnD3TunPxDGbvvvjtgQ0D9+vXL8j140UUXpTa23nTTTfDggw+WZc6be1KhUWHz+A5nNiqYU7Y/79u5O52TkQrANDqzC51w8qBrFfblSwL2s5cHdJ0g1wriJHrsLyhfU9gokTjiL6N4SAwk67nWjfsIl3C/RXc947Wj+7W7ivIMGMUdwLhJiu1G1U4UYnPWuVPmxJW8nT9K+E0yB0WRoLSF4uIQxRGEimJmjka2WYbFKRgmw3xnxDX6kInzoaVB1chW+2pxLaT3QVKUiwTz3sijeAhJnuhg5yuXr4RePd4CbFhYujQ0LPjKhVmoQKhAqECoQKhAqECoQKhAqECoQKhA1VQgNCpUTV2DanEVCI0KxdWr1rKHjZwHeCN8rqN+/TrQtUtHc4N7w1y0ard98eUKuP/BMeaGGX3rYTKNG68/DPbas2nSoJAZsxbDuPFfKyQ6PfrIlrDTThV7mgQ2DLz9zmzYsCF6Y49EOPKI3WDXXbaVZWIsplHhy69WwOixC2HqtO9g/oLl5nfH6bXZbrsGcNCBO8IhB+8E+7RtZh4NTh8fJmIXAqw3N7sONk8/WGX2mXbsaW68bW/iFHL0eWMqDB2WffPxTuaJHvu326EQKeKcfcY+8hlnwT6BWHwFqqdRAfPC92n6ezp31vL+3uTuh7effSs34TBUqkYFVJOMoxFU6JJNK1ofTqDaGxUorFRFqlRYMdab/968/r/94Jsp3xbkUOonFSyevQR6mJv93Tc3I4t9TmoLJ9z2A2oK6H5xT1j57aoMpodPvfdHsMdRu3ugpLOtoP9tgwpu8mi8y3ZwzqNnQKPtt05kob9j8l1MkEoCiLqOWHFhURHViivl88QIEi0fN79dlMot73E9PoNRj40t5VbzFyMwiq5AaFQon0aF5cuX0039y5Yln2b30UcfQYcOHYr+/laXw1lnnQVvvPFGItzdd98NXbt2TeABqNoKhEaFqq1vqdVvvc00KjTlRgV7xw/foGNP7P5mHXePkLtZhyh0Q4/NyvmYtcL9zUF8UxGy6UYg9YOPu46wmJjEl/JwJBvP6oieR1mf8QhKC9b2uQjD5RSL43MwTOMsubEfZRbbr1OkfRqjUGmkOJ7ib4hCzFF9Ei4exVa41ZD8aClm5JIej6hhEReDzD6gzdXybFCRYym7Ei23dBNKQbiUl+VaOYlGOVA+1lWSkr0QbH29E8sLhzK1RNY3iqJnRvzMaeR7Y6GbecLClEkzXG5hsnlUIDQqlFejwmmnnQb9+/dPvLnuvfde+N3vfpfAywUYNWoUdOzYMZFO8+bNYf78+bD11snPGxLkAJS0AqFRoaTlrDExalS462ZzqrZXHzjac7ac163FXhPYVO2JnKmOIZcJ7CqaxiV5TcCYx50rGiiI5GGXRtPgbHL1ivgLkeIhReuIi8Zkr2LD0Ihlx0HvqN3qoQT6WimfitVTuRNHcdlkPUUA5aya17IxLKConJONbd18PjYW7S3GkRicA+sjhfYo8cXH4TRhq0vbTYjN/qzD6WIdWMjlbSYUnwCHUmy3wtzdgv3xVfRJwfoTD/lCM5MVK1ZC75f7Qo/ub4SGBalLGEMFQgVCBUIFQgVCBUIFQgVCBUIFQgWqoAKhUaEKihoki65AaFQoumS10+HRJz6GKeam9lzH8cfuAWefsXcuSo3Znn/xc/jw4y9yxv/hCa3hjNPa5uQMNw0bvXM0bFx7zSHQbr/Cb5DXwUaNWQAv95qkocj8p1ceZJoGWkQwvSikUWHZsrXQf+AMmDx1kbsRW2vkmu+y87Zwwbn7QZu9ts9Fy7QtMU/l+L8cT+U4+qiWpJ8pYA2vvj4F3hs+Lx+tKPsDfz1BffhZlGsgF1GByjQqYC8Nf2gtH0XL7bjJBDw3bkNf9svmoE92jLjfiIdHwwdPfxwPlFhvv0dTuOCZc5x22gfw4kQZYqDIITkJiHaPpelFJSzfu0gprGBUT6IwyTthnEIbFc578mxo3qaZl6JZNE487+JyRsGong/mcbzpv+dVr8LaFWu9OWO27U7bmqcqnJfyVAWvh66F5j3ioVHweZ/s/65LGmf988ew8wE70vLj58eb99RHYsocWx66K5z+t5OV3X+fGMSc8WA8njNasur95Wdfwes39EVK3qPe1vWg86Nn0lMekJwWR0TSm+LS8vZYXC8rZ4mRvOc/+r1zvNh7Jx5HeFTFaFBj8vkJL/5ejOtFJWxOWka+XU4wLW8hsWM8hnM1E2JGgxpUB0R2fr2ohM1Jy4gEysX0CHL4VjCl/zQY9veRsDGjIdPzw6ymKhAaFcqnUeHpp5+Ga665JvFW6NSpEwwblv/JOwnHagQGDhwIp5xySiJi27ZtAZ+44G84SFACUAUVCI0KVVDUKpQsuFHB5BC5DrAL/PflTtN2QoPC9b9BmTs/0ZE9yppFXEzxE5qMGpe5xEeOlbN0TpCx5A1K5G8oohOPgd6OY+ab5JoXiUaU1XVMjEFeyDAGP+gYbi4CRPULtweJYQFhOH8Vw+VjfZAjfD/BlBglSdHlBSdLufDUxTEu5GcFRSOii/GUnp16SkxDisM8q5jgxPLALCiH+OiTRjNeOo4c9gF0M09YmDxxOouE11pfgdCoUD6NCnPnzoU999wz8XQrvMkfbTvuyJ87lOub7vDDD4cPP/wwkd6LL74IF198cQIPQNVWIDQqVG19q0s9rVEBLwLoDE/nbn8Ngjnx+dxPiGJAS5XLBF4rXK41WIPZdM1jBZ2/CsImuXbA2BEWMunQuMxlRELUTWKTJWbjGOQbCyV6qIW7xZE/8rJ6NpC4+ZjIRdRa1OA1xcvTbHY40OH0zMT5idGMgjHZGpCLUzsix0VyebgJ7sqmiTHIkYQsg+dsIJ7n49LriBNiFNNqKVeicDhjdAF4gjytF9kbe6r9YgwE7WgWMTnSWrnSNCz06Acvv/A6LFmS/IMPVjYMoQKhAqECoQKhAqECoQKhAqECoQKhAqECFaxAaFSoYOGCW0krEBoVSlrO8hRbtWo93P6nYXmfSHDzjUdAq90bl+Umxn/2NTz97PicueGN+F1+c2ROTm1uVMAGisnmr4pHbzrMud1U4/cP35UaCurVq5NqzwIr26iAeffuMxlGvD8/K0SF8dCoUOHSFeVY0UYF/Z71H1xH7o51eUS5DjYT9xE2/TVHscgH6LLm0XPlVxKIp2lXtFEB9dJjY5z0vfk9aLvPVetFJdL5mAMfWfZ0fMaQmTD4zqHinDme9+RZplGhubKn66Xnnc5VYmaaxUnin3YfB2OezH/zP+qffPeJ0ProPVSopF56zujiuWtXrIPuF/aEdavWKa3kdIe9m8O5T5zpDKuXroUXL+oB69dscFjW5Nz/nAk7tNU1lveDz8O/b6LvuVzvkZGPjIbPXp2YFTaCH3rFIXDYVe0NJrGjcTQ5/b3t/XT9svTS89YakYhqoTn56yOO6TmjtXC99JzjGhIRx/T8PO5j6/diRCEaVJnENz2G1otKpPO9cJY9is8eMQcG3zUUNqzN//722mFWXRUIjQrl06hwzDHHwMiRIxPf+ueffx4uu+yyBF5OwMaNG2GfffaBGTOSfzF70KBBgDc8haP6KhAaFaqv1qWIlGhUMKJ8bubzt/9ZSHAb1ZCIISPC9pRPFjdHP7sgbZ4jRjNr47kXYVg4KG0Y7Iokd6Rqo9XpOyqCtHDaSs/pUBh6sVxPEg4h/oVVVTzlEdm7BEe7aBGm18Zody0m3Aoy5AudycZwjM0mr2/zQhfHFI5VsXJelwBLIg6FJrtDUc86pn1v0EZ25OH/rKP3Jy9WJ1BzyMlG9nEQIK8I3yqSC/tZBMmOj354jT1yODcsTPp8mtMPk9pZgdCoUD6NCnfeeSfccccdiTfST37yE3juuecSeLkBTz75JPz85z9PpHXiiSfC4MGDE3gAqrYCoVGhautbXeqpjQomOF8P8JlariMwJ7lOkAkx8FpCErYTuQ4QPKrBKF2DWFHhsZDYyeggrSHh2N15m7TE144soehix714v4iOgSX/CG4W4kOe/sWWw3hZSTugh/NBLTpsvUTLw96Z4ovBjKxr7PxFgIth9RxdZGwyEgeXTlc4KBjTJxbBloR2YmFYO5NBYrjEhMixkM8UGa2W81PimJ3oxvRcXKIbEvGEz07ka16sBCdCVM9buXKVaVjoCy89/1poWLDfqjCECoQKhAqECoQKhAqECoQKhAqECoQKlKICoVGhFFUMGpWtQGhUqGwFa4H/rNlL4KF/Jf+akU59u+0awJ1/6OQ+aNK2cpivMTfEdb1jGGzI81d8773zWPMo6XqZKdfmRoXMTVXAsO8+zeGaqw6CBvXrFuxdmUYFvFmy5yuT4P3RCwqOVwwxNCoUU62KcyvbqMAfZMtH0frm12hO+H6RD72jFvTd5BoO0jnokR1DbtwV36IbFSht+gSdUpNItDAvJjuZpozCjnMET3HRehJbaM4tTS+Gia/xmfGuaVQwNxrnO7hRAZ+ogIFieuTsEkiRUnyJjSznouzOOxZH+a0354AeV7wCK75e4dhZk7Yn7gUn3n6sDRaP4xJIcY9yJ/SeCO//a0wKLwr94Oajod0Z+3jQyAz/xyiY+MZkj2XM9j2lLRzXpZOySn7RXFThFFemiotT8//uF/eEFd+sFELm2KhZI7jo+XOhfiNz3iQZE9+mIJmIc/73tspDnETMrfVE8SW2mCm4sgsefy9qv5S8c+eMougUjxPfuQue5KbEz9ZTccQvJWeMljtvyU/pUYqC0yL2orhuGg/uDNYX7TGMllvBwk+/gIG3D4a1K3M38cSSCMtqqEBoVCiPRoXx48fDwQcfnPiON2vWDPBaCv8ibrkf99xzD9x+++2JNC+88EJ4+eWXE3gAqq4CoVGh6mpbFcqpjQoSyPwAErmBR526HY4czXdznpBNccQPx4ifX7ifqxzD2GjuOBLE4EZHDpkjInMfRGHaHpuTlo1HGlbe6RGBXwTjFEyGwnUcxCzoMM4jjstaRkWPaDg5MxFuJIJZCG4mbvvOzwiLnfwUB/l4sD2iyjoRLlG9lg5gNUgH88H/WTkaJA5LIIE4OOIh+fGKXxFzu8E5C3lKXMNadA5CxoaF90d8SE9YmPjZVIHDWMsqEBoVyqNRYcOGDdCmTRuYM2dO4h00ZMgQOO644xJ4uQHLli2D3XbbDZYvXx5JDf/7MXnyZGqGjRjCokorEBoVqrS81Sae2aggGdC53J74DcbndZ4Iqq8H9NxdLxBd2P76AbmCkp9dEKrnmItZaxwhOXRMmWttF8Q4iB19s+aki/EoPwrMkNs8LVnWYjzIdQ/mKgdifmWFyB7HZS2jKODoMJ8OYxJfkYlrQzo/0mCSriPOXXp+YrFo3rhyesqEmMMlD2MXnKjIsTbNFQyNEdzlEs2ZVFgwwieW0nC6xiB52PA0rFqFDQv9qGFh8eKl2hTmoQKhAqECoQKhAqECoQKhAqECoQKhAqECFahAaFSoQNGCS8krEBoVSl7S8hP85NOv4NkXJuRM7PBDd4HLLj4gJ6emjY/+5xOYMnVRzjR+/9ujYKedtsnkhEYFX5q2bbaH/7nmkIKbFSraqIC/uH651yQYPXahD17iWWhUKHFBM+SKbVSINwVkyKbA+FF17AbZFFYSko+48/tKbviX5z94+uOkVAzZfo+mcEG3cwhFdYnkJ9Yhf+iYcnFLkXfxi3CXvGcMmVVYo8J/8IkK2KhQ+aOieWu/KQOmwdD7RuRNpp5pVrv8lYugXsPsprW8IiZwjytfhSXzc/8ipMG2DeCyHhcAxtTH4rlLoOfVffK+jeuaZrGLu58H2zRvpN0rNf/is6/gjRv7FaTR6aajYP8z93NceY8QEH+TyTfDsUs7Efl42HxREn5xASHkE6qgHeXjIQuRivjFBaohZ8wxHraYvL+Z+i30/90gWLV4dSFugVNNFQiNCuXRqPCrX/0K/vnPfya+6zfccAM88sgjCbwcgfnz58Oee+4J69evj6TXoEEDmDt3rvl5a6cIHhZVV4HQqFB1ta0K5fyNChjVnIH5i1OguXnBQ831jUBy0iZWyk1EiDs+argbh/yNTe7WI4lBYhSVXvxNRYyJRlxbPMSO66w5cVU84ckoWlqDU9d5CwuxWNLGhFgCtzGzcFIkjtVWGpEIhDNHa+k0BCc/5FtJk5QNY0Y2isUuNTcaQzStQGSPKKXtMudoaMQvemF3nSwh3s4880rOTiGpIX5IpC/FxZCImRdsWHjq8Zfg89CwYCtWe4bQqFAejQpvvfUWnHHGGYk3zr777guTJk2K/NtPkMoI+NnPfgZPPfVUIqNbbrkF7rvvvgQegKqrQGhUqLraVqdyzkYFOiWrczmdpzk7uUagFeFEjv63hCE8vdMJ3S4dB9eiQ6MQ8GrDzul6gvwNly8UcOWOOOb1LB+ZTtfHI1iCIEXN0UahDKb1Exzlx+6G7fImFRKK+8laRse0znGct+2FZTvEEx8nghOVhySEqDjSnBe0Q8EVgXMQA2pyjSKIXSA3njPnpnyQwzIRrmBuj0rT0t1AcZiI2UR0iGR8dR6iTX5qb8jl5VawetVqesJCd/OEhcXfLSGZ8BIqECoQKhAqECoQKhAqECoQKhAqECoQKlB8BUKjQvE1Cx6lr0BoVCh9TctOcch7c+C1N3M/ih2bFLBZoZyPwe/Ohjf7Tc+Z4g3XHQp4A37WERoVopU5+qiWcMG5/ibVqDW6qkijAjYpvNhjEoz9sOqaFDDL0KgQ/V5V1arwRoUO5qkH/k7b2OfMedKTj6iR5jXyOFmz+Ob3k/RGPmwaFboV3qggfhiwuH3l30Eh2oVw0iJpv5lDS9uooLXTapLPnpavYNoX3w/dL+oJK79dJebM8Yd/OA7aHL9npl3rpuU8d+x8ugk7U8AaDjynHRz9qyMjNNEe0HUwzB09L2JLW3T4ycFw+NUd0kwJTLTRkJY34u//eyxM6P05TnMeTVo2Ns03naFOXf53U4h2TsEcxnza+ew5pN0TVpCTVZNc/lm2QnIqhJOmX1G/NK04Voh2IZy4Lq7jfkvmLYV+Xd6GZV9E/1pmmm/AqqcCoVGh5hsVVq5cCS1btoTFixcnvunjxo2Dgw46KIGXK3DOOefAa6+9lkjvL3/5C3Tp0iWBB6BqKhAaFaqmrlWlemvX66FJk8Ze3lyc8PUJX2+5uVkSwjDexmMBdpW1jCLIPoQSJDf6IC5zknIXRRxA4rK/qHkfp8j0hDanZ4zObjzUXBQRc3kgSC70EtEkk/NnYjRHm5FzZXJEG+UlCeIpQbXWHBvJ7cN5GB3hOUySJC0K5rePNnPo/bKfqovNTXB2tquIDYXwi16sLvM4BuOYn0cxNq/cSGRyNy9i8zyxMM1qupiSt41AZuYwHyVtfLFZQZsGEqgeOGLDwtNPvASfTZhiWWEo9wqERoXyaFQ466yz4I033ki8XfDmfrzJv7YcY8aMgSOPjH5Ogrm3aNGCGl4bNmxYW7ZS6/MMjQq1/ltIG8BGhTvu/o3fDJ2u/XkXDXw+5nO3NeOZmX3sQDzE8MufwIlDFDnXkx474atwaWQYUfajQXIhyFgMaHmpOdjYkoLmoyPjVoDiW11xwCWFUHGUTU2JKHpudP52gqyok19LHE/FDHEV4bBZ5UMMy7Ha7IWOzOY94FoU2UlSkZzEyriOYRWtnuezDr0SXfmIOIW1tU7ER9xqIw+F3NL6WH806UP8KGfr6PJGosGEY5cIkHyEh1QVGOerVq6BV3r1he7P9YHvFoWGBaxfOEIFQgVCBUIFQgVCBUIFQgVCBUIFQgWKqUBoVCimWoFbVRUIjQpVVdky0n319anw3vC5OTO68frDYK89m+bk1LTxg4++gBdeyn3z5ZWXfQ/aH5L9Fz4310aFOnXokzvYuDH/Ddrx7+O15qkK7fbbIQ4n1hVpVJg46Vt44ulPE1qlBkKjQqkrmq5XeKNCexLAm1r5Q+V0vWwU38/Fv5dNtIL89M22xTQqnP/0OYmUK7a/hEzkBmCxxrV13siJ28UvPsb98IkK79w9NE5LrM8r4IkKcW0U0XnlsyeCKiDui7rD/j4SJvWdqljp0wPO2g+O+d+j0o0GTdPW5P63FdZkcP7TZ0Oz1r45Tusu+Hgh9L1loJZNnW/dtCFc8qJ5KkPDuql2AbW2YLrWiCHnpUt7wfKvVgglc+xwmWmQ+Ck3SBSinSmUx5BPO589l3zcF/8L4H95lsszvy2hTeLeL25HS/z74dl+VlE/r5A9K0S7EE5ahCy/Fd+spGaF72Ylb8pO0wlY1VYgNCrUfKNCt27dAD/oiR8dO3aEkSNHxuGyXvfr1w9OP/30RI5t27aFKVOmQJ06dRK2AJS+AqFRofQ1rUrFLl1/CY2bbOdDmIsDuj6wFwnucgJxZFlA37DDsDHgl/UTQfaxvuiudGUe9eMATLO5iBj6E9mOiDOdGKLHMQmy8aKabBE7jjaOoYl+lOOD+O1JbuRhHO2Iap6UOZe8dTynEMsjoieJYTwbx2dHwXETLK9yUm5IwnTpkJi0TujZGAk8uke3F+GZEaeSn4/NQQW3dGsWGy59fs4XgzBF6QqPbWaV4JCLh5Uvx6FXmy/OR4382Dxh4UWYMH4yLsNRxhUIjQo136iAT6zaa6+9YMOGDZF3Ct7Ujza8yb82HR06dIBPPvkkkfKLL74IF198cQIPQNVUIDQqVE1dq1s10aiACcj51l4A0Dla40hR53I04eGvG5wH42xED14r3YiPECyTaXINYZ3NILFpRNj56RyEL/5MknhiJXdjcjjOUZDpjubsBrHp48zObSbGIG5RvqDoa+ce8hgrckxj13k4P+JYCmpZPSdHE3LmXFRO7MUuoucyJhf2Qx7J0AQZiDPicORYzJMZExxHoaAUHtrGa4Lti41B4XQkNosv+4ldYqCT19ccZPo8hE8MfLE2xleZJyy82qs/PNett/kDEbmfhEzO4SVUIFQgVCBUIFQgVCBUIFQgVCBUIFQgVIAqEBoVwhuhHCoQGhXK4btQxTk889x4+HT81zmj3HbrUdBix21ycmraOHnKInjsyeQvOXRe5569L/zgmN01FJlvLo0K+KHfgQfsAO0P3gn2adscGjduYPa5CZYtWwdTpi2Cjz/9Ej6f+G1k71mLpk0awu/N979hg9w3yVakUeHbRatg/ITke2/duo3Qd8CMrJTMX6JtDId32DnTHjcc94M91IeZcWtYl6oCxTYqpMXNutlVc4XjP6BGq3y4HW1gSOf6G9EjGsY16g1QcKNCq6ZwfrdzdJp2LoqSH8KCpdATkPYT3zQMbVm4Fo1ztI3nM4bMNI0K7yUNMeTcJ86E5m2axVBcxmPIfovFRTruJ3h83ASzR8yFt+94N25IrFu02xHO/mf85sp4nPS8l8xbAj2v7pP327jrwTvDjx84NRFbA69c+wYsmr5IQ6nzTjcdBe3O2DfVVli9eS/Lv1wBL13WO0MnCp/1yOmw0/5ZNzuk1yZvUSIhdL3z6WkuighfBON2weOj+MX5gsf58XWWXyF4Woy4XzyerMVX8wUTTq5R+yFPfDWehmmu1td+Gtdzr7dm6RrAJ4h8NTF5vtceYV71FQiNCjXfqHDUUUfB6NGjE9/sZ555Bq688soEXs7Axo0bAZsSZs2alUhzwIABcPLJJyfwAJS+AqFRofQ1rUrFXI0KkbOr+SGF1hbUN/VgfmQ1tkzcbkLs+DOPVUQn9bMxB6DXCM4CLo5c3zPd+ltfi1EEFiJnjImYPgSj0ZhEP8rxPsxHq+RMHmZpR7R4UuZc0pB4HMHGieUhHI6Kr+aQeDIySjhqk1Lcxm4uJ47Gr+Rj87YIspmbwDGM9/OhrSLGxSmOYqSltyMsEkwRG0XFl8jh4pGfNzJu1vzlRIVPTLHRfkSWLDYHm68xTZs6C7r9pwe8M2iEEMNYphUIjQo136hwxx13wJ133pl4h+BN/Xhzf207HnvsMfjFL36RSPv444+Hd999N4EHoGoqEBoVqqau1a2ar1GBz8I2K7leoPO1O2m7lN05PXrhgGf1yLWE5/lrCboSccF4wjJRXwwmXBoZoByET5DSSuLOGPEjnjFJfmS0LxpjPYrir09o6TKKaDhf4xiJbBdi11bBxMGtTRzRIMwmIxgbzYq/cDOOb7dCOYuesxJfnHwM9kfc/F/FZn3GJABpEdVy1dzHFpuMzkITQlP80Cg5R+cmqnNK56CdKDENQcUfR/ycYvDAEfDvR/4LXyz8CkOFI1QgVCBUIFQgVCBUIFQgVCBUIFQgVCBUoIAKhEaFAooUKFVegdCoUOUlrvkAD//rQ5g5O/fjMO+981jYeut6NZ9sjgzmL1gOf/vHmBwMgJN+uCecfkqbTM7m0KhwQLsd4IzT94Zdd9k2c59omDb9O+jRezJ8bf7acb7jvHP2hU5HZzd4oH9FGhWy4q5ZswF+94ehWWY4tP3OcPmlB2bag6FmKlAdjQrSeIA75A+hZa/ycTWu5QZZM7NTzRUMmVk42vCoXKOCz0M+OGdVjTOS/Zq+r2w94WfFEHt2xMo3KqC2jqNzETwNQz+N41oO8ZN1fGS/davWw3OdX4KN6zfGCZF1XdN4deUbl0KdunFdWes8BEOJTTDq32NhwisTI3ppixP/cCy0OW6vNJPDpg6cBkPvy39jzvZ7mEaYp86OltWpRPNzcMr34ItxX8KbNw/wlIxZo+23hkt7Xhj5BVKUmlYfjUXZ6avC845uPCuO1kuLGPcTfhxP89WY+CEmvmkY2rNwtMmhOYLpUWIgprka1/ysufhqP8HQJw3XmNbVfhrXc+27FaxfvR7e/r93Yf4HCzQpzKu5AqFRoWYbFfCvxuJfj40fzZo1g/nz50OjRo3iprJf33PPPXD77bcn8jz33HOhd+/CGuMSzgEoqgKhUaGoctU4+dau10OTJo1dHnxzkjnD6x9K8HzPX+7ULzcNoaO+GYnW1ldwLSW6iHkNM6NTOb1gKD4MqH09LDwzWrL4e77lWDtFU3PUinCNDc2yf4nFPHaU3MXmYjJJUonpShWstjiTD8bkwMKKx2Azx7dU4yk+LBbxwaT4CwPi1B2yX+R7XMhIZ1TbGEKO8iEXevHaLqjVIRft4+fG5PVsTILsCzGJhAAeBrFryZFxG8vGZl3NtzGNgd1Fx4qhsnWaNmUmdHuyBwx5533z87q+ZpRIYSy3CoRGhZptVFi/fj3sueeedL0Yf2/gTf14c39tO5YuXWr+CE1LWL58eSR1/O/O559/Du3atYvgYVE1FQiNClVT1+pWxUaFP959M57BXWg6h5tl9FyOgD1P02he8HCDmzDMJ26na5dRm+ioUQRJzb5oXw5JDqzlkjKeCT4B7toEtb1Who2k6YX05UVqIWMCR8CIs6rPhXiCyyjO5ENZGVfxRF8/Z3/m+Dk7OprWJVfzwl8o5nIiLyuNMXgqRBtD7BRM4ggoPgYnN+3LXAlG+ujm4uCUdfjV2mjhEHY3S+GiKgXD1wTONpZFI3M83wDiRzO0M+Y5bMAnyQ8aOByeefJlmDVznmWHIVQgVCBUIFQgVCBUIFQgVCBUIFQgVCBUoNAKhEaFQisVeFVZgdCoUJXVLRPtBx/5AObMzX4MJn7488BfTyiTbLPT+ObbVXDPX9/PJhjL8cfuAWefsXcmpyc6GwYAAEAASURBVDY3KtSvXwfwiRFHfX+3zP3FDStWrIN/P/ExLFgY/cVQnNeixTbw+98eRR8mxm2yDo0KUoktd6x0o4K5RyF+m4L77FmVVe5lSNrwg+q4gkEMRB9h28+xxR8ltYbGJVzFGxWSeXAWabhEyxpt4pG9CYY+WhNxvU7T1L5x+yaYMWRWJZ+oIJoSR+dTKCYaehRfjeFc6wO8ZW7EX2huyM935H4ihNb0cdetXAsvXtIb1q5Ym1O+UfNGcEn386BOvTqG5/2jTpuooeLFS3vDKvN0mXzHKff8EFod2TKDJjHS85YaTXt7Bgz56/AMDQ/ve8recOwtx3ggMtMxIoYKLArL29cwX2zRi6eSzy/Oz7eWOKIra/QTDOeCawzx+CG8OJ7mh9w0PO6bto776rhaM85L00JM+2uO1vI4NhA9ferzHgizaq9AaFSo2UaF6667Dh5//PHE9/3GG2+Ehx56KIHXBmDhwoXQunVrWLduXSTdevXqwezZs2G33Qr/uSQiEBYFVyA0KhRcqrIgYqNC4ybbmTMon0PpRhszjd9wg8m6n1PQrvmyE3saJluEIwSvi1o6hsytBDlILt6bZ8LFlcyjemQhsstZccmqDW4vVk8nYf0kDonaF8GIbvTEzUsbxC7QJvy4huAyajvONR6dM1NjFA/DsmMipzgu+ek4xGFpG5sRF8cs5XtMfi6KWVln5BKfuH4P1owAU1V9KGRMWwSR5uLb3Cg2+XMQ0rYvLCsxnEpEAzlTJ8+Ep//zMrw3ZHRoUFB1rQ3T0KhQs40Kffr0gc6dOyfeKngzP97Un/bvNUEuQ+Daa6+FJ554IpHZTTfdBA8++GACD0DpKxAaFUpf05pQlEYFjG3PxvzfBTxl80maLJQbYjTRtuhcCKRFfPZwUqhmFzj4OfIs18bApegIJKP44VrmWk+02C5enqv92GpjY0wS8j7ClTjaIhh5Gz9WQQ1hkSAtkOtga3b+1kHW4i2jxmXuY6h9UQCMSV+UiMQUPlNsLgKaQKKLMcUHZ0xhxHHM0s2Jbz1kQCfLIcisrcmNKBzRxsB4WD+34AnFY74FaFAa5Cc2xDkiDjyTnD2OT1B4e8Aw06DQE2bPCg0KUr0whgqECoQKhAqECoQKhAqECoQKhAqEChRbgdCoUGzFAr8qKhAaFaqiqmWm+ai5UX3KtO9yZnXfPccD3ghfzsfcecvggYfH5kzxNPM0hZN/uGcmpzY3Ktxw3aHQts32mXvLMqxYuQ7uvW8U4JjruPZn7aHdvs0zKaFRIbM0W4yhkEaFY/73KDjsqvaZNZEPoAu5ETetsSD5YTeH0lzNieLykbe/yXbEw6Phg6c/zsxXDNu3Mn/xvts5tCzur0L6D9ZFC/eu8/K45IcI58h78XgxsX2tjZoKiI0K797zng+bMev8+FmwQ9tmzqo1HEgTn1963ln7jargSueM67SY+ISCaW9PR3PO4+S7ToQ9Ou5ecK1RbOIbU8xTNkbl1EVj+8sOjrzPc+X9Sffx8GG3/O+x3TrsCqfff7KNnVWzZK3RQeJ//MK4gmLhv9N2Z+zr/FAjrdaIZx+cS/Tfm/+3FfVL5h19b2ftN6qCK9mrWIrL2+fh884VW/h+Xzp+MbG1H+ZejK/ZNW3X50wKRb23dfxiYhfjN77nZzDmiQ8p1/BSMxUIjQo116iwbNky+quxOOoD/w1NmDABDjjgAA3Xqvn555+f+vSEO++8E/7whz/Uqr3UxmRDo0Lt+q5xo0Lj6I025jTuz6f22gIx2RrNeeV5xmgJdMtQhCOOXhevEYRHM3XRYGWQjF+Rw/t4LSQwT/PZUfvrXP3cByCueSHEw1wLs7YWl49ouNFafEx0YiF8FZ4IyFpGxPWceDpuYs5KER+Mx18U20zdYU0KFyK5EI5k9mGb3rOLQybtyx7WkfXRLHs3o2W4EetCmHAkS/RDizjYCdJET6iUK/kzn1zsC8tKDJEza2ufMnkGdDMNCsOGjinyGldHD/OarEBoVKjZRoVTTz0VBgxIPhnxgQcegF//+tc1+daoVOyPPvoIDjvssIRGbX7aWGIzZQ6ERoUy/wYVmJ40KtgzMXnRedyciPlcjBCdlGmws8i5PnLed1QzoS8GvJaB7QIHiutG5rqIDqe03Iv4E08J8zSZt6K42FFfG5fiGYtxIMTCwtVxEcNDMDcyjBIyU3pWV0xmdH7ewWGORnlZQTVXLt6HaESye/AxhU8IUzAD+sJYgvPcvpLZvNDSa7FbzNe6MJVtuD/ytqNVIjksktiUK6ckyRLT8Kyj1IsFzKvSYC2xoA874WBnVmcroAaF/qZB4akeMGf2fHEKY6hAqECoQKhAqECoQKhAqECoQKhAqECoQAUrEBoVKli44FbSCoRGhZKWszzFnuv+GXz0Se6/Pv2H3x8NzZttXZ4bsFl9NvEbeLLbuJw5XnDufnD0UVl/kRqgNjcqVOZ7NHTYXOjzxtSctTvuB63gnDP3yeSERoXM0mwxhnJoVMBiywffuvDqPnyChaNx+fCb/fjG42IbFYq5wZfj8MfsOPc5+ZuemSOvnis3/LMf48XHxphJ32IaFZq3aUZ5cx3z5R21p8WWneYa8/nhjdB4Q3S+47gunWDvH7U1tGhe3k/qbe1m6P2z12DxnCWekjLbqs5WcNHz58K2LbaNWLPyXrN0Dbx4aS/YsGZDhJ+2OPeJswBrnv29lpzR2+9LYg/7+0iY3C/3f+vR80f/dwK0PqYVTlPfI2TI++JzKfy97XOuTGzZb3adciUfzbvY9zb9is5KFBu/4nlHc8bdZcf23LT3CL5tTGtGrgIlbHnzNnJjn/oIxr08IeEbgOqtQGhUqLlGhUcffRSw/vHj2GOPhaFDh8bhWrUeNGgQnHTSSYmcW7VqBTNnzoS6desmbAEoXQVCo0LpalkdSl26/pKeqECx7AUSnUfN6VmfofECm9YWtCt3XSZkwSNrpSXnaAzlr1HMTC7O7KY5FuK+Cp7vrwfFyjwmex/xj+Pi78W1D+ZOFmuWemAsysEGRVzy9kqozUyiIUfx7dT5MSepKziOTsEI0dwKpulicI6Pjs6T5EjL2iMW0tV8B3DuVlDiiQ6JKtDVAvn4JX4YE+XJASc802s/R55ZOQCdDIKQ9RMZpqHNkmnguWACcQYA0qAw/L2xOa5NXYQwKeMKhEaFmmtUmD59Ouy77750Q6Z+izRq1AjmzZsHzZtn/0EZzS/X+ZFHHgljxoxJpNetWze46qqrEngASluB0KhQ2nrWlBo2Ktxx9298eHOu5tO1OTPzV9SGK8LpzE02Opf7JV4NsI8bRNPC9noAB+K60TowzeVh6RyLg/NcGwzCS9bwJomdG0dB7ePC2JRkj25vjo/6VhtF7BHNxYlIZYglfrywtXD+4sOAi2tgmtNoyWZwWuSGOVk/mVgqm9nuNNFGet7PAmQQH0vDwfFlzhCJuPxI08RHf8yPdMiBAJo5TNtRJp63XafiyKdgTpy1nY+1G3Tjxg3uCQpz5ywQhzCGCoQKhAqECoQKhAqECoQKhAqECoQKhApUsgKhUaGSBQzuJalAaFQoSRnLW+TV16fAe8NzPxbzphsOh9Z7NCnrjYwaswBe7jUpZ45XXX4QHHJQi0zOltqosH79Rrj3/lGw6LvVmbVptXtjuPnGIzLtoVEhszRbjKE0jQoFlotupk3nxj4HNzdFpPPiaNwP7cU0Kpz39Nlxyeg6Kw/3iX6UnrkSnYr6oXAO38IbFc6km+Yz89QGyTlPbO1C8wr4FfpX24+6/gg4sPP+iZARQMVf8PFC6Nfl7Yg5bdH66FZ0o7+z5ai1cEY8NAomvTlFlpnjPie3hWNvOSbT7gySdyx2/9+9DfM/XOhoWZMzHzoNdjog+1yZ8JN4cUMsftwcWWuNYvxQRHwr6hdJxCyK0ZHYqFHdfjrvYmKjn+RdUT/UKMB308ZNMOIfowpqkEHJcFRtBUKjQs01KhxyyCEwblyyobp79+5wySWXVO03vorVsTFqv/32g6lTk41wffr0gbPPznN9VMX5be7yoVGhdn2HXaOC/OBhzqX6phx3akVcOGaLclsQYZYkGFXAYUj2FtFAs8zJrrTRn9zRz+m4SSQ/5Mrh9Azg/GjCvoKhOs/jOCqpODJFssztRGK5UZKg2JacMRcfcvFUzIpVzEBzt3QTk7edozazo5jOVXEtlbjop3XQRm7Cp5HVNU/iMV+t7BS5jm8wWttYji0xEEche0T80KKNhhPRdk5x3DuJHiEm5pSJ06Hbkz1gxLDQoCDlq+1jaFSouUaFW2+9Fe6///7EW+iKK66AZ599NoHXNuDpp5+Ga665JpH297//fRg9enQCD0BpKxAaFUpbz5pSizQqyLnfnJSj1zc2O8Qtx10LGRNhdCK3frIZhxHJXTJ4DaWHuhJfwpE/XrMw4GIiFdUs7sLRmkHxIWZROKopDZ6m7tHtwwazVEpHbKQmdp8U6xHThWM/2ZQR03uM7F30xB8lRDvuJ3iMi3ydL5oJI5BEECEvp+0Qgn1MXFox1lB+VioST+Vk3UjQxUEfxSF5u07FI3yvKFwcN27YAAP7vQf/7dYT5s7J/9k2JRReQgVCBUIFQgVCBUIFQgVCBUIFQgVCBUIFCq5AaFQouFSBWIUVCI0KVVjccpEeOHgW9BswI2c6+W7wz+lcTcY3+02Hwe/OzhnthusOhbZtts/kbKmNCliQDz/+Ap5/8fPM2tQxfyX83juPhQYN0v8qamhUyCzdFmMoplFBPquONxEIjkWL2+KFzOJm4XH/+Fr7ia1kjQpyU7ARlr9WHv91glDS8qB8hCDJ4eg/u2dUOBm4xCbXjEAFNyo8xo0KGDJDKpoTr/g1I7/IfmQvxkPyll9QaKn4fNrb02HofSPicGJ96BXtocPlBydwB6j4iL19x7sw5/25zpw1OfXeH0HLw3Yjc6F5L567BHpf85q/eTxDvG79unDhc+fCNjs0SmfEciaSqvUr//MGfDfzu3RfhV7w387QeJftEr9UUhQ/VTHdfiPfSL+tzPeJ0nDCKm/ChKNxwQzBxc4M4pR5Yn3FD8G0f5M55VR8p67zQ1A4GheMzLwo5L3ttJRfPGuRzsxbCJibHDo3xISThRMlf94b1m2AIX8eBrOGz5FIYazhCoRGhZppVBg5ciQcc0yyyWynnXaCOXPmQMOGDWv4nVH58H//+9/ht7/9bULo1FNPhX79+iXwAJSuAqFRoXS1rA4l16iAwezJmgdz0uUvTsOAdBq252J3jUIcT9Q4SVoRdjNW8Xd61kKDNWIq5Oz5US1j9VQ00aGvXWQPMiJBYotzkk8sMnN8dMIvG0zPSQ/zY5tloICN4xHH8Qk4P3agVxdH+D6s1TIDzWIxHZ9iCwkXKncOQXHR3e3J4eRsQ4qGZem8Hd9w8LADTSUvDuD2iBTJkejCQyc8zNrJiM0BNlezJpbC0Qkx0nY4TyTeZNOg8IxpUBg5/IPwBAWu9mbzGhoVaqZRYc2aNbD77rvDN998k3gv4fVlx44dE3htA1auXAktW7aExYsXJ1L/8MMP4dBDD03gAShdBUKjQulqWZNKkUYFTCRyfqcTOJ7G+ZDrAIIdiid5d/2ARHe1YCl8DWA16HpA5CzT6SpN0sEXvH4QX6uN8Siox2Um1xXeR/xZROPoI3yeOxUM4OPG4tmsna9ocATW4Dg6psw9S/zIw8JxbcwDD8F52wbkLzaiXTZGuDLK2jGZi3SnaW2oITI+gGDGQXgyCtmaJAcZKUfUVHyZSyC9prl98XN2JhUDOm2lybVAowXtBLkbTIPC2/2GmgaF3jBvbmhQkAqFMVQgVCBUIFQgVCBUIFQgVCBUIFQgVKDUFQiNCqWuaNCrSAVCo0JFqlbLfN4fvQB69M79JIJjOraE8zvvV9Y7u//BMbBg4fKcOXbt0hF2zLrB03huyY0K+NdQf3f7e7DW3FiYdfz6V4fDHq3Sn6wRGhWyqrbl4KVsVMjXpIBVlc/Sca75WTjych3aT3glaVSQm36taNaN0ZqWyEUbJTk94gf5+ThE8ST5BYGWwXkxjQrN2jRz7vS7BPcLBQv7cI6Xd5Kyl0TN4nFE1MSbNmiGaVQYLkjmeNCFB8IRPzuMf/Wh9VJyXrpgGfS6uk/eG26a7NYYLujW2f1ipZi8B94+GOaOmZ+ZrxjaX3YwHHpl+4LyFh8azR6xGWLxnCUROG1x+WsXQ/1G9W0MXZwYO1Yr2a//FVb0bUlKcbmYRixC+hI1Yn4SGx2y3tskls+PSFH5RN4xDevih5T8yJiC14q8/c5opnNGIP5LRsTWrVwHg0xzz4JPvsBlOMqkAqFRoWYaFS6//HJ4/vnnE++CLl26wF/+8pcEXhuBb7/9lm6kW706+nS2OnXq0JMW2rRpUxu3VStyDo0KteLb5JKMNCogai76/XWGmcvCjDQljr22sXMePEGue6yS12B5pNO5mqVZ1f+sIV5MZg650Iuc42X0FtaUtdi9btSOO8AjYTeAx/SclUWXfUXDjkyJ+FuI9+uFrRhmYXzZneZan0hkdgShUuIWJW0dx5GcG08kvMRQleacLcGyKS/OTyK5tH18iSHihkL6BvdxrJ/WN3NyjWGyDxzZJDyzlo2pdDiWsyAJPWHyxGmmQaEnvD/iw7w/L6FHOGpfBUKjQs00Krzwwgvwk5/8JPGGad++PXz88ccJvLYCN910Ezz00EOJ9H/+85/DE088kcADULoKhEaF0tWyJpUSjQqYjDv308Kd5/HcLad2uXag3C2oMTrjE5+Ncq1g5dnNxfHXEGQwURJxBDAEjCP6zPevkkNaPMyeceHr3FCYGBjA8dLiSAxUkbkbrbSPIzGio6WpmDa20kxwEKAc2SIxCZaAbg/MQT7Z7YRpsf0JFY1KXxZcAyskXDO6+OQTcWQbQjYv9Mb/G0BS8nPFQbsczEc/i5mBcxGG0hNdS92wYSM9QeG5br1g/rzw2aKqWJiGCoQKhAqECoQKhAqECoQKhAqECoQKVEkFQqNClZQ1iBZZgdCoUGTBaiN94RfL4b4HxuRMvdn2W8Mfbzs6J6cmjd8tXg13/nlkzhSaNGkAf7q9U07OltyogIXB9wG+H7KOa685BNrtt0OqOTQqpJZliwILaVTodNNRcNhV7SONBRUtkvrcO1NPczCObmiQuMJJs418eDR80C3/L4CbtmoK5z11lkhGRvdhvL25Wd/k62yYG3ptlXUHtP2U3pjtjGN4mNexV8eNx3aGmINZzhw6C969Z1jSEEM6mycqNNsLGxXiSWkiB4psS8V2u8WJwzfxLy1Qpoi8kY71nPDK5zD6sQ9wmfM47OoOcMgl30vhuETct2PMEx/A+N7ZT5wRke//z+Fw0PkHRPP2ckJLjJj3go8XQr8ubydscWDrplvDRc+fC3Ubxp9uYwPFvx0O3gSvXf8WfDttUVwysb7kpQugUfOtE3gccO/f2PfJ4caBTfGktJJL0FTBHm4i/lbI4ZV7j1CUWM6IFZ63S8S9R0jTwvxv3C3yv7e9HMmkvbjcCsk78g9Oq/mcIiEdjOJu4aYRrqG4/4ZFDD7O6iVrYGDXwfDNlG89GGZlUYHQqFD9jQr4F3BbtWoFW8IN/FdccQU899xziff6rbfeCn/9618TeABKU4HQqFCaOlaXSqJRwQSWm3/cTT/2hxP5GQVPze46QJ17xY9siiM47kk0EEvF5byv8yBHfPG5aV+2eFuUJ9ao3aycIZGTNRUcgwM6RdHjACwW368EpxhSKxnFaEedh9fG+tkIMjFL0SOL2HFhOHYZrbugGNvqCA9rxHoeISmth36oEaWQn+SiTYjRWo0sp1mIsKTkRGubn47FduPLXzDxc9Og8FQPGDXiI9IIL5tvBUKjQs00KnTq1AlGjEg+LfKxxx6Da6+9drN5w02cOBEOPPDARKPTtttuC/Pnz4emTZtuNnstt42ERoVy+45ULJ/URgUj5c7reB0g53XCOY7Gkud7PN3LOZ+vGzRf5BATXDBUt1cgFEjsvKBX5cPajNIlBiae8Ito64VKXGCXk5WOxLeBNCZzohsRyUj0bMYuJ+FbKUo6Uisj4FUcy+0ZEdHWWm4u/i4R1qBlJD8muFgxP3HHYJyfQ0gQV5GYkhSHYxtqWly8aZQ8cGSANS3XSjjM+Wq7gJidaJgRn6Aw0DxB4TnzBIUF87/UUmEeKhAqECoQKhAqECoQKhAqECoQKhAqECpQhRUIjQpVWNwgXXAFQqNCwaWqvUS8OfeOu4bDsuVrc27i1pu/D7vusl1OTk0Z8zUYYF6HddgFfnKJuYE0x5FPJ9eN+jlkyTRqzAJ4uVf2kyt+euVBcNCBLTJlXukzBYaNnJdp/8Pvj4bmzfLfWJopYAzd/jsexk34OpNy+SUHwqEddk61h0aF1LJsUWBVNSrIZ9VYTN1MoD/b1rguuuYIrrnarnHhFtWo8GR6owJq0S8ErKi7yTcHbqmxwX2Cb/T8ofUwkj/4juas2J4XnVGjwp8LbVTYPuqcuuKcdGZI83lrC+eM9mLzRh88Puz2CXz60nhe5Hj9wW+Ohn1ObpvB8DltWL0eXrqsF6zJc46s26AuXNz9PNi6sf/vsN9jRhgF435fve4NWDTzO4WmT4/536Ngv9P3STH6vP3M17rfrW/Dwk/z/xWqcx47A5pTE0pKiBiU9n1Kw2JusaXP1s983mnvaxQoPg6HzfLLwmPJ2qXP1M90zkiLWkSnuDjilb3f4vR8Tn6WP+9CYyz/agUMuG0wLJmb/8kdfmdhVl0VCI0K1d+o8Le//Q1uueWWxLf4tNNOg759+ybw2gxk3TDfokULmDt3LjRs2LA2b69sc8+qe9kmvIUnlmhUMD+M0PnYvvDPJnyGdj+nmCWxGKYK6rXMrRLbrbNo4A1GcpMREhwu1yoSg4wkQS/iI6NYKBURMaDYPYTxImyrZzEbj/wcz+s4TyPCsRBhIq/9buNxJBdMQEm7HBEUi+O6gN7GPBXXikV8REsC0drvg+KIH8VgAkE2cWum/TGEHIUymfcic2/mfZk15qVgt192sbaIrmZzSKeAeipfroKAW5kGhanmCQo9YPT7+Rv6SSa81PoKhEaF6m9UGD9+PBx88MGJ906TJk3o5v3ttivPz+cTCRcInHDCCTBkyJAE+5FHHoEbbrghgQegNBUIjQqlqWNNq6Q2Ksh1gT3382DP7jy4awV9ARG9duFzv7s+MBuV6yC5pKDrD4mBhRBtPzEzB7pSeR1rsxZaiZ4EQVlHM2pqLoKCka6xR/YhRiGTns2KA5KFpy7bRBzJGQ0uBaslAmJxXDIgyeaEa5rzxKdmPCOihiaAxVHbQ04EURSzNo0TTAbiiDNyyQFH9sWBOdYHOYZPLjh6mHFZC0cxXN6WQzo4d6HchBgcdytYv34DDOg3BJ5/pjcsXPCV9Q5DqECoQKhAqECoQKhAqECoQKhAqECoQKhAdVUgNCpUV6VDnFwVCI0KuaqzGdme6/4ZfPRJ7r9QcfIP94TTTmlTdrvGm4sffGQszJ23LGduF1+wPxx5xK45OVt6o8KbfafD4CGzM2t03jn7Qqejd0+1h0aF1LJsUWChjQqHXtm+qLrQh+LWQzcTCK6xuLBwNB7nCyeOo0+pGhVQCz94j9+4Lh/1x3Hkpx/8Yb79SD+h5z71NxZ9FBOn9I0KmEnF8y68Nrzj4Q++D1P6T9PbT52fcs8PoeXhu6XaGOScJ/edAiMeGpWDx6Z9TmoLP/jt0fR9RqTYvNFn2sAZ8N7fk38xEW362H6PpnDuE6YxRt4I2pij1oPvHAqzR8yJsNMWp9z7I2h5aO7zpfhlvbeycPFLjhV/j6BWsfXOyg/xwrX8N0BmSV+0VPzfY7xOafll7SXu69eSLb+F0nNGdnF5L56zhJoUVny9wocKs7KqQGhUqN5GhY0bN8J+++0H06Ylz0mvvfYanHWW+e/4Zna0b98ePv3008Sunn/+ebjssssSeAAqX4HQqFD5Glanwq23XQ+NmzbmqzX7QwgP5tzMXzYdc3aX0zXh3ijnfeZbkhvsxKi4m4vcXNkwilmSlvb1FGTQITcbudEbZEaxcOH2Ept7G82YF4uPFjwicYygqwMmjHZ6cVWI2HV8MSBfNNmVdXBOh1lm1cFH8Ro+H+MtUkoDfZDjfC2HBmOwSxSU8JwHyhFmcCYLxWshU/wUh928dtp+rRsKoAodUR5aJLa127Uof/7ZFPMEhV4wZlRoULAl3GKG0KhQ/Y0Kv/zlL+Hf//534j22uV7P9+jRAy666KLEfvFJCxMmTEjgAShNBUKjQmnqWNMq2Kjwx7tupmsEvjzgc71cH2B+6uwvlxJ83eENfB1gyXLuF0e3Ri0jLNcVPLfx0BcPsyS+1dZzJvCrXIe4UYxWXHCEGbJxaNBz58g8Y9K+ziq6VlD2QAljDMGtg7br+BiEo6s4GNOhLOBysGRdB+FqXR9PkuFR/HBEjvhKOMFtVLsRN5CIz8V665zQkdasT0ubDMVTiYkO01nEm60oynmQ5mqJ8rwHQ8dssEGhf98h8MJ/XwkNClSd8BIqECoQKhAqECoQKhAqECoQKhAqECpQMxUIjQo1U/cQNVqB0KgQrcdmuxo9diG81HNizv01bFgXbu/SEbbbrkFOXnUbPzYNFv81jRb5jkKeOLClNyrk2/+ZP94bTjxuj9RSh0aF1LJsUWAhjQr4l+APuyp3o0L8w+u0BoJiClsZvco2KmwyydtfAURSxtt//cf3ypQCZmkoL7qxOi2O5qQGTEmk0EaFcx5Vf3W/gnlH8stapGjT/dMxXOo08A/vwLyx87PUHN75sTOh2V7JJ0Lg+01L41MOvpu12PllTU77y0nQot2O3qxFEE2pNcHqPbJh/UboeeUrsHbFOq+TMTv57hNh9yNaklX2nkFljklg+APvw9SB03PRyHZcl07Q9sS9mFdA3nkFkRCvh4EKybui2mn1zoqXsUUOnZp36nZcqnjjf95/j8iOa2ckUoq8szRc0mZSUN7xnFHA5P3N1G9h4O2DYfWSNVoyzMusApvrjU0zZsyAtm2znpDD34SHHnoIbryxehsVBg4cCKecckriXbDHHnsA5ly3bt2ErbYDjz32GPziF79IbKNTp04wbFj+pzUlHAOQtwKhUSFvicqKkGhUMOdVumaw51d9mnU3+JgfZvzPM/4Kw9lxh8pRGOgjHBxlHqErbW3XRROcQiBfjBjAHDzI3Fmj8TzscYORmrKxHgP4ynkjipcbHseg4mbTMAy9R2O1BLQLW/ZCgvIidse3E1ZklnAQ82YXA2PJXnDUMdGGBw3G4NytkFtbP2IaUPTY17MkAYohGsi3c7QL22EYX0AUdAzvh3bNJxoyjeHzCeYJCk/1hLGjPxE4jFtYBUKjQvU2KixfvhxatmwJS5cuTbzTxo0bBwcddFACr+3A2rVroXXr1vDFF8knQA4dOhSOPfbY2r7Fssw/NCqU5bel6KRSGxXwvI7ne3v+twOe2AXiubM7RvR6wMOsZ7LT1wx4nSDXD45qJpHY6JByaD+Zc3LMZzeZew3HtbmItMMNVceP2yl/ZFjJoq4xxYliUxSSd7ElGI6xPDRHPKN7VM6yXaWBPpI7MS1HcMbEkcJbQfazCUVqg75ei+eYp2wzPreC7nuOa+GyTTTIQpDWYA5mgg0K602DwlDToPAqfLEwPEFBahPGUIFQgVCBUIFQgVCBUIFQgVCBUIFQgZqqQGhUqKnKh7i6AqFRQVdjM54vW74W7vzzSPMB0cacuzymY0s4v/N+OTnVadywYSPce/9o+HbRqpxhW+/RBG664fCcHDTmu1H/2msOgXb77ZBXJ40waswCeLnXpDQTYT+98iA46MAWmfZX+kyBYSPnZdoLacTIdLaGAYNmQv+BMzNpF57XDjoemf4XyEOjQmbZthhDKRoVoh9uc+kq26iAKlq3GL2iGhX+E/0L93hjsBzug38DeJR+RSAUP/rfKdCN3GLQGoLhqP8aehbH8ZV2ViIzhsyCIffmv5kw0qiAAZR21t5dHmYieefNOaadlTfG3LRxE3S/sCesNee0fMelPS6ErZs0TM1bclo47kvod+vAfFI1Yt+tw65w6l9+VNR75KNnP4VPXxyfN98Olx8CHX5ycOabNev7K+9t9VaIxlKGLA3tUBXvEdSX7y/OJWfG8TXlSMlba2gPyRmxLI7m6383LpmUeHG9vHkXoKHzKCpvpY05L/jkCxj8pyGwblX+BhsdM8yrvwKhUaF6GxU6d+4Mffr0SXyj77rrLrj99tsT+OYALFu2jG6swzF+bK431sX3Wd3r0KhQ3RWvXDxuVNiOrxHsDyh005I5t+rTK/7wQmv1QwxPBec83LWGckZM3EjbUP0NQkxkbdSwawuIH6uzn5sTXcf3cZgj66imdRMZMwqPpriSNChPISb3a3WRYIy8oql1QV2HkiatLCRxvKdzi+Zg9WnQuREdY1g/JjAqoLGhPi5dHJqLT9xfWEySFUmzCOtjHgTyQOroYuPSYF6IJaOhytq5WhlrsXvxOZGC4wB8Nm4KPNutF3wwJvmkHMkkjFtGBUKjQvU2Kjz++ONw3XXXJd5cm3vjZ9euXeHPf/5zYt+XXHIJdO/ePYEHoPIVCI0Kla9hOSikNSq4awAzUad2vHiIXB9g/nQdYVD24R3ZlXNmDYNaMX8NIpjzsD52bUXFT+ol/hSfXrL4NrLVsVQzaBxRPCQXmvKOmGbythM0WS0PWS2S8PvQdvY3PCtjJTgm+VF0nPmD6HEfFqAo3mR8VO6owDSfN3GZ4zJ0/kx2+dqJRUkr6uMcIzXixG0M0cBR6GbOmjY94ah80WJh2gTPrZ91Xr/ONCi8ZZ6g8Fwf+PKLrzlseA0VCBUIFQgVCBUIFQgVCBUIFQgVCBUIFajxCoRGhRr/FoQETAVCo8IW9Dbo0XsSvD96Qc4d16mzFfzut0dCix23ycmrLuM7Q+fAG29Nyxvu6isOgoO/l90EIAJbeqPCc+bJFB+ZJ1RkHT81dTwoo46hUSGralsOXs6NCvhdkA/KVf9A3m9O0Y0KSpFvJOZX+kje3llsB5ePc0GD/sRf+DZh9+sA4VjHxA3GWkfE0zCxxcYZQ4tsVNDamFuRebvaxPZFaWntWJ56ySE3wVeffw1v3TxAm1LnderVgatevwygjjXbvKmWRkxq/c7dQ2HWiDmpGuUA0lMh9tzelNwkrfJ27yObpLxHZpu9vHPXe3lT38k8GeKMf5yWyRM9JLjvn5nT98HUMvGtRIOAttboK80KUm/HQaM5JI6LIRps5letrfGUeULPcChn5BrthLzWtnmThnWivBJOpc2bQ/Grq4PKW/67hltIHDZnxCXvrFo7jpm4OPG96XqggzlmDZ8DQ/86HDas28BAeC3rCoRGheprVJg3bx7stdde9FcC9Zuifv36MHv2bNh11101vFnN8X326KOPJva0ub7/EhutZiA0KlRzwSsZ7tau10PjJrZRwWjRTU/mfKtvnqIQ/8/edwBKWVxtH+kgVRERkKIUG50IGjVqjF2wl5jYk88ktqixxCjGzz+JUZOoMfmiscQSUUGpEhQQKQZElGIBpBdBOkrngv+cM3Nm5m2775bbz+t1Z+aU55x53uXu3N05O+oFnl6GvRd63VXy8Osz42CLzuzry1Fm/YJ9dMGLc9B2vo3WZ7dhHx3IxXPYGimkV0PliQ+hHCgiuZCHAeQ+tUrr4mB8lGqNlRtDG8PoCRgflJ51ZqhVCiBOzjyREfpyIMZBSBtTD8wQB9rNClQE7OsHoyWTKK71cXqOzRhkogZsyi16sC0qA/MiZ4NpPOfMmQsvPDsYZkzPXuCsPeWxqjMghQplW6jQo0cPmDUrWiD00ksvweWXq/cxquiFa2Q8JW3PnuDflnXq1IHly5dDixYtqujMy29aUqhQftwXMzIVKjx4K0HyKoBe93FN4C8G0ILWCbQYsClomxhbMtcA9Ei+2o3XFdhq/+D6Akd4MbbfZ3syQBunJHvGZj0hayMS+f5BWz+mBqb8MIJW2VxZoGGNn8nDmAZsdRyl0T86NWNInJPcCLTW2DoHq1UTcD5srMwDE/PGHjabBP0tssvZxtA6ZxGD6ysxMzXmXKjFcZgbTpvimAHZsbHDQG/03717tzpBQRUovDAU1ny1jhGkFQaEAWFAGBAGhAFhQBgQBoQBYUAYqCAMSKFCBbkR1TwNKVSoRk+Adeu3q9MJpsJe9Y3Uma7WrRrCjT/vDXXr1MxkVuq6LxZshH88M1N9gJE5XyyquPtXfe0bbJkSy1aocN1V3eDII5pngkjUVYYTFR55bDqsXBn9BlSe1I0/7wWHqE2xcZcUKsSxUr1kuRYq4BvfmYsG+N82vp3trqBfzM5ZZRq0cb7ZemG/nAsVVDo2ay9t3pDNb87bPNiG/LQnfxhANgymBoFN1uxngcgg3sbDZnP+QIPHmDSHWjJxCbyb9kSF9s0oZhweY2fLm7nRH1soL55birz5+YP3Da+PXpwFM1+erQcZHg88ogWc+eip+qMSjof2hgTMecuarTD46qF0SkMGqHJVdTr1UDj+l8faHLJxvWX1FnjtqjetfVIHn4OXvXIh1Gtaz5l4zxHmG/nimNme2+X9HMHnFd9qfs4l5oyzNnMrWt42uKbU8abH4X/35qlIv8u0hUqJn/D6mctib2LufoTx2JjjRublDOw9DdgE7rU2nv+fBfD+E9Mq9L8Rnpa0moGqulF80aJFtKkp031+7LHH4Kabyq5QYeDAgfDAAw9EUrrooovgtddei8irkgBPTujevXtkSo0bN1Z/Z6yEhg0bRnQiyJ8BKVTIn7vy8CykUAHzxdd3uw7zJsCv+7TcQBujs3Il8F/XWe4WERpbx6DHzHF0oIiNxtXR/TxdPI1N6VFOqmdyIxvt6uEaAZoZQJIE5khoBJQUnwlBDhiHvTi+szEajuHHRZWVY+qUPDn4uMZFQ7K9tqJH54b5aEyDpvUkMnOnEC4OG3A8alFtgmJrPG2LPqzXsR2elSubT2bNUycovA4fffgJh5FWGCAGpFCh7AoVkl7XDzjgANqsX7euOhWyCl/nnHMOjBwZ5fv3v/893HXXXVV45uUzNSlUKB/eix01uVDBe/3noLhOMGsGK8IOyVniWrbFtQX3Uct9hLJ9t8BBCzSjy+pJZNY+rFQt61Hk43kmxkZj+un7vhzT6k1utDIy6VhdXH4mAWNKuegcmLNo7gyDeVCcQNKYESbBKEaJti4RVtPkyZRcPD/f1seimIhphNjjLukQQwtYTNZshGr09ZWE4fKjPNmEMBEh6GLngnoPi+VUoDByAvxbnaCwZs16DSCPwoAwIAwIA8KAMCAMCAPCgDAgDAgDFY4BKVSocLekWiYkhQrV7La/8PKn8PGs5G/UZzqOPLw5XHtV18Cbaqwri3bNmm3wlyc/hO3bS7KGu/iCw+CYvq2y2qEBniiBJ0skXVdcfiT07H5gkjqjvKIXKuD+x7vufQ927Qp+c5U/qbt/1Q9aHBB/mkYxCxV27CiBu+9L/tbvXj0OhB//8Eg/NelXAAZyKVTw37i2e28Dc+Btuih073IH/dLYBEAzDoLY2jTXQgWaC6Zl38RXfTWmzcEmXfoQAOFxWjw1tDFE8IcAaIK+9D81FkC5cQA0MpeHQWozIcI1rmyq3Q0G+qECH5Qol0KFZli4ZPxsTgRm8KgxAgznk6x0eNn8KB0/J+XHWNqU8rMYqGZo5Ya5j7hlNKydm/1bmfpc2wu6XnBEBI/j4f2a8fzHMPu1TzlyhWxr1q4JF//rfKhvCgp4E3rg/vqZK75evvhV2PnNLl8a2z/h9mOh4/cPJY6QF6IaH8wtwpbkfBNIhULqaD/VTbq/ZEegCGM6iJ3pOYLQqOfYlAAhuQdSezYGmvJGP3XZnFQ/8O8RlWHsEB6niqact80JhXypuKTH+CEMK2dbbNHG/ptVY6YE88H/fTwSoZA6rkWbMvo9gv82ZvzrY5unTkIeKzoDUqhQNoUK+EF8+/btAddF4WvcuHFw8sknh8VVbnzcccfBlClTIvPCkxauv/76iFwE+TOQtKHRR7zkkkuga9euvkj6pcDApEmTYMyYzCd7YaFC48aNbHReQ/AawFPQy79aHDgR9tSYJE5s7bTcrmzIj3ERxq7VEQa9tIOxw4YEJqSy0EOj9wZoaXx9G0Kwgsz+lIGBZA58f8an4ObBzkUbmmw5FxKqvBBUA9tUjD+Ked7Ushw90Fi76cY4k8gD4rEWZZ4juyG2gda5heLooXqkH1aaVnsE8uO0LR8YCH9MQD+eQ3F6ZWjmqJHQfvbMz+GF5wbDxzMK/9tnv/32gxNPPBHwG+Fr1KjB6UpbwRl44YUXYP78+YlZSqFCdON8IlkFKn784x8DnpwQvu644w546KGHwuIqN37rrbfgrLPOisyrffv2sGDBAqhZs3y/NCmSWCUXZCtUOPzww6v0KR6V5fYNGzYMpk+fnpguFyoEVhy4LvDWB9bZrgPcKoF6Vm4tA2sLlDoPt67QYTAQ/hgLanQf9ezJfd2i3OHoEY5JalqW+nYqioYmJa9/PEutVzaUj7FlO8Z39g5bh7az8OJgTNQGY1sML5bzJvNgDuhgkudYjMFjzs+YkZpzt7ZkrPPWXRZghuZSAFbHfQ+UdOqBrKyT9uV41KKN58+m3OJ8qG+wdV/jlJSUwFsj3oVXXhoKa9ds4MzyajGHzp0703sprVu3zgtDnIQBYUAYEAaEAWFAGBAGhAFhQBgQBjIzgF9Cd/bZZ2c2Eq0wUMoMSKFCKRNc0eBXqW9bfuQv07OeqoB5n3DcwXBe/05lPoUtW3fDX574ENZv2J41dvP968Odt/WFWrXSfUD64Uer4eVBnyXiXnLhYdDv6HRFD2GQil6ogCdU/O0ptekw4apXrxb8v/uPVx8227ciA5bFLFTYqYol7vrNewF8fyCFCj4bFaefS6ECZo3vYXt7nGMmYnbqurfZySbohzbB56R5bzwLdjRcnF9OhQpP9Y/EpFwxlJ0of1Bg4pvUeXMxSZXMWhkKeEO08aIpWxsjJFMbB/nV4LGbotHHxNF+FhkWT1oCE9KcqPC3s6CZOlHBXiny5pysj+rEzT0xZ3RMyHvTsk0w9Gcjg3h+IK9/wdP9oXHrxloSk3fJrhJ49Yo3YOfXOz2vitntcVk36PXj7nbTvM3Sn5cR4r0ee/+7sHzaCmuW1Gl/fDs46dfH03Mx/BzR98DsUbfPOe8ZqWLzFXd/SUegiGE6xqE0nyPu3zjH9HLG+CbvyPPP5zJl3mRmudHYGC2CbeZN4fnfLKdndKl/jyCXnq/l0sjCXOv76N0sFY9MvbwZw+atDKY/MwM+eeNzL3PpVhYGpFChbAoVXn31Vbj00ksjT4vDDjsMPvvsM/v6HDGoQgLcYIcb7cLXkUceCXPmzKkWHITnXlrjNIUKgwYNAixWkKt0GfjjH/8Id955Z8Ygd97zC2jU2DtVRL3I08u/WQPYV2WUM1JiXxvgazXa8ms2u2HLMoS3iIG+iU9Owb72p0edI9noB8TjhZPus5wUNODYZOkbaVOdG+YS0uE4LPMxdGg7Gy8338+fCwc0HJgUHYKXA+aDbFob9jUCNbT5OTMyis/Z4RGCN1e2t8g4b4ptJRoXH0lHQ5ubFuskKCeTt+5rW4vE/iY+y2fPwgKFITDzo8ILFHAj+z333AM/+tGP1PtvtUyy0lQWBnBjOG4QT7qkUKFsChW++uoraNeuHezcGXwfAot+sJDk0EPVFwlU8Wvv3r2Az7fFixdHZjp06FAYMGBARC6C/BnIVqiAha54Wppc5cvA//zP/8BTTz2VmAQWKgx88LagHl/78QWf1wCs9cden9clZGYWCrymCOgMDsswBq1fKBQ7opGJT/bBPmnJ1JeToc4Z1zTqQmy+OB6Ok/oBW5xbjL/vG7BHXBSgn1E4f8TSUm6NiW6UiryMo0Pwco3YBIMQPMUmQ5sDWsXFRHuWB2OTA4GbdNDQ5GclWk+hjMxTWVwKouOQmnDI1eXHMrRVFz7u2rUb3ho5Hl799/CiFCjgJpn77rsP+vTpQzHkQRgQBoQBYUAYEAaEAWFAGBAGhAFhQBgQBqouA1KoUHXvbeLM3h67BEa/vShR7yvwpIILzu2svtEoXSGA75tP/8tVW+DZf81JVaSAG+pv+Fkv6NCuSepQM2etgX+9/Emi/anfbw9nnHZIoj6ToiIXKuzd+y0VqGChStJ11JHqFI0ruyWpoZiFCnv27IXb756QGKtHtxZw5Y+OStSLonwYyLVQwWVJW2PV0HtX3CmL2IuPY95Ld7UENuK38P7jH8CHzyUX8LBpk4Mbw/n/6K+HsWHc3Fwvukmb8RJbxPYBggOlVAYRmxCar0csHONl5IsnLoUJf5ikZRkez31SFSp08AoVkmwZP5y3ja0MTGyCsPIQoG/jq4x8/P+bCEunLPM1sf3AvYq1APji7YUw+S//TdBWLHG9JvXUqQrnQc065psFkQ+8LN+mY3hdOH4hTHzkfW2T4bFGzX3g3L+fA8hX+DkSdLOBXEhlENkUH3QKjiI5o9rhUgL+/TdzCYKokW/jKyNyh+162qEoedv8VGA/tpV7yaEer2giMXJn5Ho5co2okZgGDRvSqQdsOYiR792DvxOnwhfvLESUVFejRo3glFNOAWzlKn0GcHM4bu5JuqRQoWwKFY4//niYPHly5Db85S9/gZtvvjkir4oC3GB38MEHw9q1ayPTGz9+PJx00kkRuQjyY0AKFfLjrTS8Knahgrdlym4oQhaU3Lze86YkzY0Wap2zYd5Iaxx133gxGA2dXxDb2ZLcxLfYCiPJHm04Nru5kEG/CIZyUBZ2fUN9E9TaRmysge4YvZ+3EgV0PMQW7UgfwmUdtfhAl8nfTchIVcM4KDEBwzlzThiRIVxunIeWzP74M3jh+SEwS7WFXp06daIChcsvv1wKFAolsxz9pVAh+e8b5GbkyLIpVHjwwQfh3nvvjTwTTj/9dBg9enREXlUFf/jDH+Duu++OTA//rnznnXcichHkz4AUKuTPXVl65l+oQAsQSjWyJkCpt76w6wqSk4tdxwR0WkU6Mo3DoGDeeoQXJuSrM9EiZ2NgzbrJt9EaP4ekvsXAnDCAhmGxnk8glyA2mgex2dXg4RCxWcwthaIHo9MWOlSor4cOw+TD+RJ6xAanYoQmJtobV61jHxZiqjY/9FYjT4cqHFpca4xyPbA5qTFJuA1jG3ssUBg9YjwMUgUK69Zu4Oh5tRj7nHPOoQKF3r1754UhTsKAMCAMCAPCgDAgDAgDwoAwIAwIA8KAMFD5GJBChcp3zwrOGDetP/l/H8OiJZtSYbVr2xiuvqIrNGlcN5V9vkYfz/oKBr02F3bt3pMK4pST28NZp+dWVLBg4UZ48h/Jm5J79jgQrvjhkanih40qcqHC5PdXwJChyce841ywIOW4Y9uEp2XHxSxUQNBb7xwfs3Fch8Pik5t+IW9SWvIrSKfwQgWciPfOeFHnxTtzgzHMe+kUyfsScTXW9vpEhZlZM7Gb3/0wvpcXyJ9h+NvmdSKeY8DYk/tdDzvwj8b3ZXs/P1/vyalQ4aEUhQp/VYUKh3iFCh5G4Db6cs4DW87bJ97Pybf1MXwbI1+/cAMMv1l9A6Rv5/t7/a4XHgl9runpJL6PwR52wyjYsGijs6ngve/e1A86n94xef7MtZrH7q274JUfDoY9KV5L2x5zMHz/3u/p2fs8+Xx42HxrYp/X6ONjsHFYHoddhOeID2ufe0oYSCMpTlzevswH9/jI+u8R/XwcTsaXJWCzKUHE5R3GYIewnPGz5L1HnXQ04Q+TYdnU5eyRtcVvXxwzZgwcdNBBWW3FoDgM1KlTB3bv3p0IJoUKpV+oMHPmTOjZ03uNMXejYcOGsGLFCmjSpEni/alqCvxm7d/97neRaV1wwQUwePDgiFwE+TEghQr58VYaXmkKFe645+fQuLEp3jOvvbwJCHPSL9fqUf+49TLrlA+/pGsb40GN0lmlnqG/0UibGHsK5oy1X7K/Nvfsjb+VUMf3txqTk6/DaSk9/ehWZ6sf/ZxZTmg8d26NknOnoa/z+0rJuDYuOtjwwfxYQXGdkcXQMSkiPYSxg/kimkbSxtqPfZyGc1ASE4B1ZMsD5U54Zmxx0Id+GIeGHIwymKkKE15UBQqzZxZ+Mlbnzp3hN7/5DVx22WVSoKBZrtSPUqhQ/oUKJSUl0KFDB1ovhp9MWCiB96i6XOvWraOC1x07dgSmjL/v8HQyPKVMruIwIIUKxeGxtFHSFCrc9+Cten2AyfA6wqwNSERJ8lrB2VidsjVLC7ueIJ3FIgD74K8/yC/gb5FMKm5togHcmHEYOIBlYZy9t7oh7Ii/mXNYjvgs45ZkWuF0ODaXnrpJguenhY4rZWvxlCmzaMxQS3kyJg80KjmQijGcn/ZgOQZEbPKzubh4GsSMNbi2NQqHo5UaJ2iPphSB/TEZ+uE5cEti9aAN6QQFVaCAJyisX1fYe+mYZ//+/alAoVevXpS9PAgDwoAwIAwIA8KAMCAMCAPCgDAgDJQdA/h+3NKlSyMB999/f2jevHlELgJhoNgMSKFCsRmtJHgbNu6Ah//8AezYUZIq40aN6sDFFxwGRx1R/F9MW7fthjHvLIZJU1akygWN2rRuBLfc0Eed9KDfMEvruHbtNvjdw1MTzZs0qQv33/PdRH2SAvcQPvfCHJjzafRbRdnnmiu7QtcjD+BhpH1DFRJMUgUFSde9dx8L+zWrl6ROlCO/v/vjVNim2qQL3yS8585+sP9+9ZNMinqiAgb51a8nQElJ/LcCN1X3YWAe9yExeVEUhYH8CxUwPO6eze3fa+5Jx8fA99X9fb4aV+/mzelEhf/rnzklegNf45Kh183oiLRks42bRJjOOIwY7JwKFfBEhRgMmk+SnCcblzPq8sh77P3vwvLpKxk5Y3v2n06HA7qo16qE/L76bA289au3M2JUNGXTdk3hvCfPjnLnJ+rxPe5/30u94fysR06DFocnvzZRCP+5nfJ5pv3UY5y9zTvhJuXxHLGQ3KGccWASiMsjIXzSc4eh6cO66C+V6P0Jx0yKZ4FVx+ca5WEM39bvp8WOyXv39t0w9oEJsHr2Vz5ixv6xxx5L3zzarJlXzJTRQ5TFYEAKFZJZfOyxx+Cmm0q/UOGnP/0pPP3005FEfvazn8Hf/va3iLwqC5YvXw6HHHKIWs8H/56sVasWLF68GNq0SS6Arsq8FHtuUqhQbEbzx0tbqNBIFSroZYh6caYf3WJks/0oIues8O9yfEnHy244ivRJTQ9sQ3527RP0RUPOxzOxIIyh7XR0fPTlBsDiWGeyI082cX40bXrwzZ2efIPxAjGNV0BmJkBeXt/acEydUiyXLhnejKVztBiYFxtxh3FNi6H5Tvl+7IYALFdde2mZlrCebPUD2TFuRM7zVa3p2hgfz/gEXnr+DZgze66NlW+nS5cutkChZk1zolu+YOJXYRiQQoXyL1QYMmQIXHjhhZHnxKGHHgrz58+HGjVqRHRVWXDNNdfAc889F5nijTfeCI8//nhELoL8GJBChfx4K2uvtIUKtPqgZQQuNMxaRC8r1NB27PqA50EaXD8YgV2DqHGwzx5Ojnq2YRxnhXY4cmsTp3My9teWDlsnpLNiHOcfxbY4ysX2PQdfxn1sMQKPPfOgTCcQkPl+fn7GlKDicBUIMqJDebkaiZVrAJUb2tKP6pkWdRFs1qmW9LpRj9qPQHDECaI997WV9vDkrNdmjKP9du7cBW+ZAoUN69N94Z0OEH3EOAMGDKAChbgvfoh6iEQYEAaEAWFAGBAGhAFPPUVlAABAAElEQVRhQBgQBoQBYaA0GPjggw+gb9++Eej7778fBg4cGJGLQBgoNgNSqFBsRisR3szZa+CFlz9VG3jT7oIDaHtwYzj9Bx3g8MP2L3imWCQxYdJyeE/9n7ZgAoPuu29tuOnnvaHFAQ1yzgFPa7jrNxMzzvmXN/aheeYCPnzUAnj3vWUZXcqjUGH79hJ4+rlZsHjJ5oy5pTlJotgnKtxz/6TE4gl88/LXd/SD5vsnF05knJAoS4WBwgoV8k0Jfz+Zd+DzhQj48e87jalPVEg+ZYVdm7RpDOf/I0uhAhunaPn3Ln8gkMKlaCY5Fyp4kTHvss45bb6YZsuuB8IZf/iBl7Ha521e4zjvCX+YBIsnLQ3YxA3wBIMGzUr/d9CiiUvh65Vfx6UQkJ36wMnQunergCxpsPyDlTD2t+8mqQPyFocdAGc+cmrR7ivxjR96FfXfbSDlog++xWoA9cPPkaIHKCXA8HM7nzA7Nu2At+8bD3hqSdrrjDPOoG9Lb9Ag93VY2hhiF8+AFCrE84LSsihU2LRpE22+37p1ayAR/N0xZ84cOPLI/E5lC4BVsgGenvDGG29Esr733nvhgQceiMhFkDsDUqiQO2el5ZFToQImgTt+eE2kWhLx+igk1zr1qHyMqfM1StYgLF+8dsGWxEbJcmene1G5A/N1jGW1FhdxrJRAtUrFN+IADgqD5oH1FtuiCfWVfcg8YM9ByMYEtL6UjcGxfdNRqJwfS1BgoykQ6lNrLWzunCcmR15sj6Z+37jqWBpMPbLU5KAlYUzEwSsuJ5IjKP0oC2PLBQqfzJlHvoU84DeY4wkKl156qfpCEClQKITLiugrhQrlX6iQtGH80UcfhVtvvbUiPm1KNacZM2ZAnz59IjHwdDI8pQxPK5OrcAaSnneMjKckzp49m4fSlhMDRS9U0AsGOxtaNtC6x4jMeoJGXp/XFyjndQq2AX/fiOwIxdrrkfPHMWNRXwsMppWYtQ1FQiFdOpRb91gczjloHoxj8uT8rS+DqzYg8+zRhKGtDcc0/o4Gl59RIbDy1whkx9jWwAUI46Mp+2ocz4l06GuwWaXGsT6Mpc09G4SwQpLroUJRYi5QeO2VEVCMAoVzzz2XChR69OjBGUsrDAgDwoAwIAwIA8KAMCAMCAPCgDBQTgxIoUI5ES9hLQNSqGCpqJ6dDz5cBYNen2s3cqZloV3bxtCrx4HQpfN+cGCLfdO60TfoL1y0CT6ftx6mz1iduFE9CbB+/Vrwi5/2hNbqRIV8r4cenQarvwpuMPKxjlBFGD+5prsvSuzjJsExY5fQiRCJRkZR1oUKX67aAi+98hmsWr0lY2r4xuSdtx2d9T4Wu1Dhkb98ACu/TM7tO70Pgh9ecnjG3FGJp4NMUEUie9W9uPC8LlntxSB/Bsq+UIGLCjBn8wZ6/ukrzyheaRQq0KZnk6f9oMDLmzcXo4j0xZiah5+tm3bj/7l/PQua4YkK5grkzR9osLKU2g2LNsKo28dAyc7gtzXHhlM8nvOnM6B5Z6+Qjvafu/u+bf12GHzNm7B3j5PFYTVq2RAu+OcA98FNnFEBMv85sujdJTDxkSlZ0Vr1PAhOe/D7We3YYPhNb6XefH7kuYfD0T/pza6xrWaMeYt7ZruiEASwH3rFopWd0Oc6Nms1pYBNGT23szEQyCnm95//75F+k+Txe2TLV1tgzL3jUxXKcL4//OEP4fnnn4fatWuzSNoyZEAKFZLJLotCBfx215tvvjmSxIknngjvvvtuRF4dBOPHjwfcABW+DjroIDo6VH5XhJnJfSyFCrlzVloeaQoV7rznF9Cosbe5Uq0raE1kXqftyzXKOVGz9qBxQK4NyNL6Ix47uvUWxmB/1Gobbejbax3LHVB43RbAIif94LAYA+UuDzMyMj3CxAJzMCB+jmjpz8FlhgqNozHMPLUDq8jAzoHjabcELsgomJe196IzlhHZGMqWRGoSzAlnxmOTlMmRgLx4bK2DWlwTB6UsC7QEsw98PGMOnaDw6SfzNUABj4cffjgVKFxyySVSoFAAjxXdVQoVyrdQYe7cuXDEEUdE3nvHwm/clF9dT6k75phjYOrU6KnH//jHPwBPMZOrcAakUKFwDssCIU2hwsAHb3Op6EWIXiuYtYNuaKFg1yjoYNS4sPD6Gook1l+NrHFwHUJi9tcDAvDtKZYR8NrFl+mIJp8AFll5sXUSjO1joTfLeTKBOdj4GtM+2nhkzalQMlbi2Vg/Y2lzUKlZe6XT4YL5GlBtR/YWhFPWAtSZfFERh4tqK/exEIHyZaGxMnhKqq+QPwrJ0hhQfGODrjt37oZRw8fC64NGwcYNhZ+gcP755wN+gUH37uk+ZzVZSyMMCAPCgDAgDAgDwoAwIAwIA8KAMFCKDEihQimSK9CpGJBChVQ0VW2jadNXwauDP1cfmOQ3z6ZN60GXTs3ggOYN6LSDhg3rQM0a+6hjq/eB7erUhC1bdqn/d8PyFV/DgoWbAE81yOeqW7cm/OwnPQGLJAq5Xh08F6Z+8GVGiO5dW8ClFx0G9erVSrT75ptd8PKgz2DeF+m+hbjQQoUe3VpAp47NoH27JtDywH2J33ByeA+XLf8apk3/Uv2/CvbuzX5T+/RqCZdfekQYKjIudqHC8y/OgVlz1kbisACfP2ecdgh8/8S27o1bVqoWCzHGTVgKM2etoXniCRt3/6qfZyHdYjNQfoUK5h30okwI/004vJwKFf6vf9YM9L849YghaGA/UiBff/OxBgvqAwEsRkBa8ABPE5jw0KSsOFSo0F4XKsTmnW9+Kf12fL0TRtzyFmxZk1xY5k+iw/Ht4MQ7j/dFgQ3oqPj4pdkwa9CcgE3c4DvX9oajzgsVSqXMOw7Pl4WfI3tLvoUh1w2Freu2+Wax/XOfPBuatWvqdBlyWjZ1OYx78D1nm6V3zM+OhsPO6hxrpXNGFfcwsP8vKbjZn5T48VeG/LRNwmO+fiG4MNfmI7mAVexzO2BhBmlySmMThx2SZcs7dc6Im5DTpmWbqEhh2/rszztO74YbbqBvra9RowaLpC1jBqRQIZnw0i5UwOIgPDHh888/jyTx2muvwUUXXRSRVweB8FL6d1kKFUqf47QR8i9UUBHCG4d4nYTBlQ5frvGyG5ZoQCJ6YDnZxdijnG0IzwBamYOydqzj1jOJiam1vm1SX2Viocy0ScT22Fp5wFb70aM3RzYhljw549lgqkMynjs7stwYWj9lpzG1wrhZflAawHNJGyTUOwzy9/JjVI2h0TWE6VsUE4fHWk0jzhVb/P8jVaDw8vNvwmefFl6ggJum8QSFiy++WAoUmPsq3EqhQvkWKtxyyy30d1T4KXbNNdfAM888ExZXm/GLL74IV1xxRWS++K3bH3+c/eTTiKMIIgxIoUKEkgopyLlQAWdBawPd0hAf8EK57gX6vKbQNmzg1iDk4/myPa1BjDnJDDjrHZKHpXDwirXRCqOnxvRt1gG/IAbjhvy8nExoZRDFI4k3RzZBxmwcX89hlCOxynHYEaO4gK6P9kZuXAiJZegewPMwbEgfIzYnyhoDBbExJwbBPmN7QpZRq+S7dqkChWFjYTAWKGzMfCq7Bx3bxfcLuUChW7dusTYiFAaEAWFAGBAGhAFhQBgQBoQBYUAYKD8GpFCh/LiXyJoBKVSQZwIxgBv3XxuCJytUTEIaNKgN117VFQ5p723QzDPV+Qs2wt+fyv6BR/P968MpJ7enooADWzSgooVt20tgldogj4UAH6sN8iUle1NnUWihgh8IizaaNKkL+9avDXjKxFr1LeGNVIHI2rXb4BtVGJL2aqHm9csb+mQsyGCsYhcqTPnvShj85jyGT2zbqNMzDunQFJqq+W7avBO+UqdhrFYblzEf/5JCBZ+N0unnVqjAv0y8d8IjacXb8DeF8xvnYbdserRPY4N2uRQqnPf3c9Al80XT9ees5sjTjPPkDwxIZ2x9d/bxMSIxlFEOv7yxUOG9P05m5MR2wBPqRIW437mR+PnmbfxiMihRRW5jf/surP5kTYw2KqpRqwbg/cGTEJKuPSV74PWrh8KOTTuSTEheq24tuPj586CO+p1KV9J8M6JkUMbgfTLkM/jwueyvS51+cCh89yZVkEUYoRj+c8QkPvymUbBh8caQYfxwH1Uc9v17T4Q2fVolGKCYAyffO3KOmSP9O2B3P4Kfd5Kfscd/10m/F3xI28+CZ+24E2fPOr/1c0Z5nF/YxvfP1s8VL/B7RIHj7wPCCAUyOa2dt47+fe1UBZdpr/vvvx8GDhyY1lzsSokBKVRIJra0CxUmTJgAJ510UiQBOTkAIOmkiZNPPhnGjRsX4UwEuTEghQq58VWa1gUVKuALs/7RKarXbvtSndg3pp4jb2piX14XYUsy88BLA7b3efF9UM5j3yYst3jcUdFs18wkcaxy8vPgeNpez0SnHezrESaoM0MM9g3nRxbKLhDHOPo+KCIbhCVcErC7bnkibEt26OB80ZDEytYzJ1A2N2DWznobh6Cd1RpghNIW2M6YPhv+/eJQ+PzTLwi2kAcsuuMCBSk+LYTJyuUrhQrlV6iwbds2aNOmjdr8Gf27/MMPP4TevTOfbFi5nmm5Zbtjxw44+OCDYd26dRFHXP/06ydfRhMhJkeBFCrkSFg5mRdUqKAXKHq9gfmrdQOvMXgtQdPy5GwQXjeZpYcxd+sQ6qmHsD3jkAOFdj4oC8RnI0/u4rn1FEXRMGhJXr4dCuw4nJNSWJ3O1kAYHOMcgidLzpVbCswP4Tg2L4tk4po41JCTsdRAFptUWk8aHpt4akiTxLlQHzPUHWNh9KglOeqdgeshjBl5Qpbt3LkLRo0YB0NUgcKmTV877Dx6uKa84IIL6ASFrl275oEgLsKAMCAMCAPCgDAgDAgDwoAwIAwIA2XBgBQqlAXLEiMTA1KokImdaqabN38D/Pu1z+Drr9NvXCsLivAEgSsuPxKaqZMbinHh/r0/PT4dVqz8phhwqTGKWaiQOmgGQzwt4tYb+8AB6iSCNFexCxV2qI3IA/93St4nbIRzlkKFMCPFH+dXqIB5eO+G27TMjlkaOz0XGJAXv5lufXSHbfiN9ZCahmls0LDohQoIynmnKh5Qc+fp+/YsQzyfKhzzlVMcdgIouFABoTg29uPyzpZz2A/H5tq8fDO8+/tJsEm1aa/Dz+kCfX/aJ6P5wvGLYNKf/5vRBpWdT+sIx97QN2jH86V5JU0u6JJxFMLbtXUXvH7Vm7Bb/V7MdNWsUxMufOZcqI+vhymeI+sWbIC3fjUG9qYsqqutXhdOuOM4OPg7rePTsHmn4IBtESmX5wjas6/xw9MmPnphJmxYtBEG/PUstMjhSvg3loQQim3NmO+kqVs/9EgysmjZO4xHcCnw2D6Oa8LQIb/8eBWM/91EwGKgNBd+2IgbwPE0BbnKnwEpVEi+B6VdqHDppZfCq6++Gkng3nvvhQceeCAir06CTZs20Qa8rVuDJyDhOm3u3LnQuXP8aT3ViaNC5iqFCoWwV1zfnAsVzGszLSHMgxbptUlAjqnyazl2aYwt9UjAfc9MuWg9ttqHxwgQ9A+OfTvc3ETmgQcti7MLynwn9rF4ypQy8/BdziYjqzO4JObZqgFhsK01tnPX5k6OY+2D8/LkARyycg/Kji3Jhwbo70zYAC21mlsKZwyVRv+ocVwfZep/raXWH3C+3H74wWx45aWhMPezBc42z95RRx1Fm8cuvPBCdTqnnI6VJ42V1k0KFcqvUOH555+Hq6++OvLcOfroo2HatGkReXUT3HHHHfDwww9Hpn3VVVfBc889F5GLIDcGpFAhN77KyzrnQgV/LUHLCl6z4DqDfkzrDczkjLkyo56zU3p/3cNrEWy1D7cayPdHiRtrXMRiDO3hHnUc5aGBSZHUZy/W61ZJVcdzNxhebNTqIRprPT6yH/WdhnPllhzI3IKQiPXcaqGPw5669e2oT3A8d2NrQuCMtJpbh4uW/txpTO7Kg37wgbzNbEnp6fQYc9ixYyeMGj4O3njtraIUKODaEt8XwbWmXMKAMCAMCAPCgDAgDAgDwoAwIAwIAxWbASlUqNj3pzpkJ4UK1eEu5zDHrdt2w2uD58LsT9bm4FU6pvje2kkntIWzzjhUfZCq32grVqTV6lv5H31sek4nIhQauyIVKuCJDFdf0RW6dNov9bSKXaiAgV957XP44MNVqXPIZCiFCpnYKY4u90KFTP9ueeNtjA2qYsS5ziLNt6+XSqFCromWsX1RChVKKedFE5fAf5+YlnXDvh++catGcPajp7sTEHyl1x95639g3RfrPUl8N/EkiXjzokk/eHoGfDZ8bla87pd2hZ6Xpz8+e+6o+TD1/6ZnxbUG6t9e94uPgh4qhv+BmtWXYQcLN/C0iU/f/BxKdpbAvs0bwEXPnVeGGVStUPhvf9Kf3k9fuFK7NvzrX/+Cyy67rGoRUYlnI4UKyTevNAsV1qxZQ9/2umtXsJi7Zs2asHjxYtIlZ1Y9NNdddx0888wzkcnedttt8Mgjj0TkIkjPgBQqpOeqtC1zKlSwO4m8P2uUjP7EQR3+0ACzVnI3sNNAGZv4et+U5WTrKbjrEDAeo2FI3dcNxrdhbcfJXH4+ht9npwCewqT4IWz2QzH2OY46N4tg6BHlBpT1hOYG5KtNHIZxsTqOxWBhbLbHlm3xlDFOinMgOzPAzDANztBLCVHIFBuLpyWkI5lxMJbWHjvswwUK8z5P3lytHbM/4rfa4uYx/JZbKVDIzldVtZBCheR/S8jNyJEjS+3WH3PMMTB16tQI/rPPPhtbwBAxrOKCBQsWQJcuXWDv3uCJxQ0aNICVK1dC06aFn6xcxSnMOD0pVMhIT4VR5lSo4C087FpCyXgNodcgempaZq1ISCO0N7O3fmrsQVs81LNNQG8R3PpFB9DI2hZ9TSCvYZmfH8dAM7/PbgE8hRlv42LjDDlOLmtMH9fvuzw4hpmY12Sy1/dFGZukjJuGtRg6Z8wdL85f9bQdyVTf2huxMiSfTNhKZwsUXn8LNm8q7AvccE150UUX0RoTT+uSSxgQBoQBYUAYEAaEAWFAGBAGhAFhoHIwIIUKleM+VeUspVChKt/dAuaGm8eHj1wAWLhQHleH9k3gzNMOgY6HNiu18BMnL4c3h39RFPz9mtWDHt1awPj3liXiVZRCheb714drr+oGLQ/cNzHXOEVpFCpsU8+vx56cAWvWbosLmZNMChVyoisv43SFCn2h15U9Yj8wwKBpTzrIK8EYJ46HqrgPDAopVPC/uNyGdp8XWFFch33dhw5xVullueAtnrgU3nt4clbw8IZ9joEfiJjPRLJiZDKgUhVTr/Ltnr2AG/XnvjU/k0tEV6dhHTj7kdOgcevGER0LMO81c9fC6DveZlFi2/KoFnD673+QqEcF85Dm3rFtADCBvy1fbYEhPx0O3+41pASc3KBek3pw0bPnAp6ukPaa8NBkWDJ5aVpzsmvV4yA44fbvQt3GdWmc63zT2CclhP9uF4xdBB+9NAu2b9huzbIVKsTxnSYP9ktja5PJ0MkFj20DcAnPkYCNGrBvmrznjf4Cpv59uv0dHMYKj3FjyODBg+GMM84Iq2RcjgxIoUIy+aVZqJC0Obl///4wbNiw5KSqkWb69OmA3wwcvpo3bw4rVqyAunX1a0lYL+PsDEihQnaOysoi6XeBH//Oe34BjRo3xD88SKwfjYWS0Rh1+scsqpVcKywU21GLUrLXIwNNtvz3DbY+hrMxMQmD45MrgbId41iNHxgtjWE0hjUkV9ZTa1QU1TMLYxloygdByFQJ2cXXsy/ZOYXND+V4aZXC8Gws56rji9lBx1OP+EMD0ycDBNUdzAz12NKlzXTfl5kgxkrp0ZBjayk9GgNc/86YPgdeeXEozJ+3yODl33Tr1o02j51//vlSoJA/jVXGUwoVyqdQYfbs2dC9e/fI8wg33+MmfPybSy6AU089Fd55550IFY8//jjceOONEbkI0jMghQrpuSpPy3wKFczyQadN6wsjUQ31qPUGZoJ6eWJXMXp5YtYvZulClryGwtb6EDAz5TDYlpdBCMpYVheIjwO20aAcgzQkCgTTay8LSt4a0Zj5cShnHULb8PwMOCMHY7JUYXMcZe/3tbu2C8iVyEjtvHVgniN5kpH1sz4YxFrreTqBxdUWJh9rb6SUL8biLFiu253bd8KI4WPhzcH/ga83F16gcMkll8BvfvMbOOKIIzgtaYUBYUAYEAaEAWFAGBAGhAFhQBgQBioJA1KoUEluVBVOUwoVqvDNLXRqu3bvgWkfrIIJE5fBho07CoVL5d+hXRM47dQOOX3TfyrgBKOJk1fAsJFfqG9uyrwxNMGdxO1Vzlf/uCt8NncdvKpOo0i6KkKhQtcjD4DLLj4c6tevlZRmorw0ChUw2Hq1CfWJv38EiF/IJYUKhbCXzlcKFc4JEMWbhANCNfA+zwir7MZiX5HJ3rdL6ofzyISHtkvUt6rnWqiQS4ykPMNyxNxbshcWTVhM35q/eeXXYZOM4xo1a8Apvz0JWnVvmWjHeU96dAosem9Joh0rTrzreGj/3bY8jLSMx4pMXKNN2D6b34SHJqmCguSCN/Y/9sa+0PnUjjzM2u5SRWF4osTXOXLcYL/60PWio6DTqYdCzdo1c3puZ+MmLult67fBF+8spP+3rNkaMclUqJDENYJkyiXsl8k2klCMIFe8sD1DZssj7JfJfvarn1DRB2Nna5s1a0bfKnrsscdmMxV9GTMghQrJhJdWoQJuHMVvef3ii2hx86hRo+DMM89MTqqaaXr37g0fffRRZNb//ve/5WSWCCvpBVKokJ6r0rZMU6hwx69/Do2bNKJUeLOQzUu9WNP2IXzR1j9aZeU4DG5o0tuNSEy2hOD5cgxsEVZfwT7KSBWwMaZePB+Ltdw6nZUE4qGU47MtW9JcjZJ13JIfG7INCWmmpNFiPTnfT5vFyJXISE1OeqTBiOEgrlGzj3G2vjwvmgcjWx/VsX3KiLDJ1p+PC656eH9MNNXi68yHH8yiAoUv5i/W/gU84qZoPEEBCxQ4TgFw4lpFGJBChfIpVLjhhhvgySefjDyLcPM9bsKXSzMwZMgQuPDCCyN04IkwWOwhV/4MSKFC/tyVpWeaQoX7/vdW+7oeeX1X6wkrc0uTgEyvP/Ss3CpLje06BjHcrBkPW5azjFGwJRfPhhF8W+5z62wsgo3h58nJxcdXWlRw/sbIj6Fz82JQ180+YMtBTHKs45bEHE7Z6rAmuFJqdyOlRj3oH9RqVG6odbxqO63kNCgC27M/xVFCK9ewOhD7m9wU0PbtO2DUMFWgMKTwAgU8TZILFA4//HAOLK0wIAwIA8KAMCAMCAPCgDAgDAgDwkAlY0AKFSrZDauC6UqhQhW8qcWeEm7inzlrDUx+fwUsXf51QZv643KrV68WHNZ5P+jXt1WZFSj4eSxctAn+9dIn8M2WXb44a7/hvrXh7DM7wtF9DqI3I6d+8GVBhQp4usC06avo/69iNmhmTSiDwWFd9ofTTmkPWFSR71VahQqYz86de2DM2MWAp1zs2ZN70QieEnHiCW3hu8e0znd64peCgXSFCv2g91U9sqLhhozwFXjz3yjRLknO/nF61CX5sh+2uZyocO7fuFABczefCvhgefejXDiofOIk5aflaQsV+j9+FjRr31SlkgnPZep62XNev3ADLJ+6Qm1IXwDbvG/MdxjZe8f8Qm3WPw0362fKT30ws3E7DL5mKOxVpzZkuho0bwAXPn0u7FPTzz8JOxNSWl0Ue+28dfDWr8ZkBWjatgngiRf6aejnm+y6cckmGHX7f2DPrj3JRgkaLFg46oIjFN+dEk5yiM5FQ6E87nI54wkSK2d8CfPHfAErPvwy44kSWKhw4bPnxQFmkWXKz+XiQLLnHbSNw3AW+feS8k5CDOWthh/8cwZ8PmJekkNE3qpVK/jPf/4DuClErorHgBQqJN+T0ipUePfdd+Hkk0+OBG7Xrh0sXLgQ8AN7uTQD//jHP+D666+P0IH8jRs3LiIXQToGpFAhHU9lYVXUQgWVMG9Ewg6vJOjvGjNwUjTWM6QmbG+w/L+JXF876lgK0eBoNINphOzDbbyNk/p2SX22Rj3ZYHz1f2BuxogxKEW0D8lxyDZGRY3FJgOtCWNYApXaYnAeJpCNyIGNLXNm/Uiu4+BjQM5ZIzbz6kxRiB6k8wsUFnyxxLfKq9+jRw8qUDjvvPNs7LyAxKlKMiCFCmVfqLBt2zZo3bo1bNq0KfKcmjNnDhx11FEReXUV7N69G9q2bQurV6+OUIDroH79+kXkIkjHgBQqpOOpvK1KvVBBTZDWJeE1D07cysiIh3YtgUsXu6bhRRH6GUstwrUNCQMPvh/3fQNf5vsH5Q7YlzPOPjX0ugrHcXpfTkgqECP69n7fYqMtJ2acwhjMgx8HA1g/zIsjMoYGsZwFbI2Nj+f7U59xOFEKSB4UFwsURqoChaGqQOGbr7dYq3w6+H7HpZdeSicoHHbYYflAiI8wIAwIA8KAMCAMCAPCgDAgDAgDwkAFYkAKFSrQzaimqUihQjW98flOe8eOEliwcBPM/2IDzFP/r1m7LV8oOP7YNtC9Wwvo0L6JOoreexcub8T8HfH0iA9nrKZijFWro9/i7CO3ad0Ievc8EPp+p1XgZIJCCxX8GOvWb4fP566HxUs3w3JVHLJx0061gT/zJlvfH9/gbNO6IXTquB9073oAtD24sa/Oq79l624Y+L+TEwtVju3XGi46v0te2OyEz6dhI76AufM3JMZh25pqM/FRRxwAx/ZrRfPk941ZL23xGSjtQgXM2H9z3i9mSJLzLJP0vpxt/Tb3QgV/I3DS7614G55PMCffVn8Df/S57Mdhe1/mz4j1KPNtnHzJpGWpTlTQhQpN7KkASXlzzUkwbxcbvyV/84rN6tv8v4ENizfCCrUpfdu6/F87cGZHnnc49Lm6l+q5efnzdVwDzHrlE5j5SvZv4ev14+50egDi6ysem7VBGzffpJzi/VDqfDHv/9z1Dqz5fG3QPGZ0yv0nQeteBxmNw3DxfZk2+2LsQlWcMzUGLZ2oXpN60PaYNuoUi4OgZbcDoW6jusrx29yeI4rWjcs2wZrP1qn/18Cq2V9RMUmaDHShwrnK1J8b3ydf5qOxHmXOxn+O+HLHn+oZ16Tntm8bxIiL72JrLecVlrMv63HsbFzeThbE03ljYc5/n5gGC99dzIBZ244dO8Lbb78NHTp0yGorBuXDgBQqJPNeWoUKP/zhD+GVV16JBH7ggQdoQ2hEUY0F33zzDWCx05Ytwc0QuH6YP38+4O8YuXJnQAoVcuestDzSFio0Uicq4Ku0XTvbl2y1tYj66kH/6FSV0JmYvhFYjR0TsLXnGIyrW4TnANoxrGeOnJ3LlzHZBluWMT5NgOTaivV65Oz9MdlgOpSazov12NoczYAtfGy/r33VDAjTMMVOiIf/2bHpqEb3dIf6zoh8jIFulI7V4dhWjpYaVDVRXK1yNri+nD51Jgx6eRgsXLBUT6OAx549e8J9990HAwYMULnqaAXAiWsVZUAKFcq+UOGFF16AK6+8MvKMwlPrpkyZEpFXd8Gvf/1r+P3vfx+h4ZprroFnnnkmIhdBOgakUCEdT+VtlXehgn3Z5/WKXm9osd9XM/TWNDhfWrPoDj7qpQza0AjNDQo1Dt8tNeL0xpnwlF6beFhGEIqBw3hcl4dxsVh27BUqYDw3A7ZgbK3heaE2qa89zZyZE54LKZkPQmFzM11KQveZQ+NjDMxcHYafByHaWIxlBXp+WqzjIiip94Ft27bDqOHjYBgWKHyT+fNN45zYYIHCZZddRgUKeMKkXMKAMCAMCAPCgDAgDAgDwoAwIAwIA1WDASlUqBr3sTLPQgoVKvPdqwC5Y7HCa4PnwoaNO3LOpm7dmmoTfQvo06sldDy0aeDNwZzBiuiwUm2mxQ3z69W3fOO88M3CZk3rQrNm9eDgNo2hxQENihgtHRR+mL1Vnbjw9dc7AU82+PqbXbBZ9XFcUrIXGjSoDfuqEx72VW2TxnWhnTo5oUH9WunAK6AVzmmt2sj81Vfqf3W6xMZNO1RRSG3YT90D/B/vxf7qFIW6deRbbMvy9kmhAp6ooP4xBi7zYYGVJet5gzGaug8hnD1vitZ6C4jWZuBstYDlvm2cTVCWtlChTZ/WUKdhbR9c9TFmEA8N9pZ8CyU7S+jb+qlVp6SUqG/uxyKFElXgVqwLvymr91U94chz+ZhpPxfHB3O9V/0uGXLdsKwb4WvWrkHf1F+vCW68Z5x4bDcXX4/SOD9fzp5JfrjB/FtYNnU5TPj9JDZObFv1PAh+8NuTjD5tbLUxSn3D/mfD5ybiplXgc3i/Q5rBgUe2gAbqdbGeKlqoqwoZ6isOa6nf17u37YKd6rVqp3qd2rF5B+xQ7YZFG2Ht3HWwa2tuJxhxTtFChWQu2Sf4fGWeNNdsE/fvEZ/mjG4+W2Rz1TIOW6CKZZ6ZRWAZ2/h+cb7Jen5uk5dNzNnj7xE8NWPiHyfD8ukrOXDWFr+Fd/To0dCyZcustmJQfgxIoUIy96VRqLBhwwb6JtwdO4J/5+CH9kuWLIE2bdokJ1RNNT/5yU/gn//8Z2T2d999N/zud7+LyEWQnQEpVMjOUVlZ5FqogLuQ6JWfX6/VgFcCEZ2aBNs6GzczXquEbaxcKwwGYikBy6hFLLchyox0AKNnLNJxztrC/u2ixRaQtCwLuVgfxiN8dPXcXVfnpsecpxl5wH6ODERqY+OZ4mx19qqhvhsaubVQBiaWTpY9Sc6YwdgWIjYOoSlHi6o6uEab9t+P4dWXh8OihUs1QAGPvXr1ogKF/v37B7guAFJcqzADUqhQ9oUKJ5xwAkyaFP27/rnnnoOrrrqqCj/b8psanlTWqVMnek/ER2jYsCHge5GNGjXyxdJPyYAUKqQkqpzN0hYq4HrFrjF0h5dDwbULjkivJ2Z9eJ5GF1kfMb6y43WPXgd5cRFDA/LyydpqVTiwwyK9BsRu0M9gksI82NgeZMQvVKjA/uzCc9RjNfLi8BzDmGaC2tbk66Wtpm/QGEsPHeXK2IhwkpSSNjVyNaCeMfLzsPl7NgFb9DR+lKfqb9uqTlAYPhaGvzGm4AKFWrVq2QKFzp07czrSCgPCgDAgDAgDwoAwIAwIA8KAMCAMVBEGpFChitzISjwNKVSoxDevoqS+U22IG/XWQpj83xX224dzza2p2tjYu2dL6KVOKmh1UMNc3cVeGBAGyoCBXAsV/A214fT8N9nDurixjxX3Bn42PWP6dij77xMfwIfPfczqxLaJKlIa8OTZifo4hf7gwH56EPnANezj7N031IdtijFeMnkpTHy48n2DX11VhPW9Xx1H3+Qf5sFxpzV8nxdPXAqTHs0+10NP6gDfveWYMGypj+PyxtyHXj8Cvlkd/EbquGT6P34mNG3XNE6VUbZw/CKY9n8fUnFJRsMKpsRChQuewRMVcr/iuM6Gon/XlO6/x+w5oEX63yNYIDL+wYnw1adrskFb/fHHHw/Dhw+Hpk1zfy5ZEOmUCQNSqJBMc2kUKjzxxBNw0003RYKeffbZMGLEiIhcBGoT7rRp0K9fvwgVeNLC0qVLATc+yJUbA1KokBtfpWmdT6ECvoT7f/fYV3S1MIn7mwZlzsbNhm1J59mwHC2572OQzACynmxdFH+ZYTECeHqAjwE9CUhGGqVjiWnVmGdDOaEB25g2MLTzQm40Jj16wP4cGCw4R5cDx8aY1A/FDGKTETlTrqQM+Xl5cBSEtDkhhLHx5VSgMPVjdYLCcFi8cBm75t327t2bChTOOeccGy9vMHGsNgxIoULZFirMmzcPDj/88Mh7QE2aNKFN9w0alP0X4FSGJ/spp5wC48aNi6T69NNPw3XXXReRiyA7A1KokJ2jimCRT6FC4vpGrUV4PcJzw3WJEtplmOsE1y6+DWNwqyEMBq55dAIUImATACd11IbXS6ZlbGete1qN8wlqbDzMQyntmICMr3EJzp2xNKDv5/ouGMnM0M+B5m5iUZ9tTExih2E8R8QjsXoI+Hk2DIF6FgfzMBhKjycojBiGBQpvq1MNCztBAf9Ov/zyy+Gee+6hojHOQ1phQBgQBoQBYUAYEAaEAWFAGBAGhIGqxYAUKlSt+1kZZyOFCpXxrlXQnBct2QSvvj6XTiMoJMX996sPRx7RnP4/tENTqFmT39lLRt2hvrG7Xj3Z+JLMkGiEgcIZyKVQgTeKJ0V1HwAkWQTlPl6cbzY9ovk2jP7+E9NgxnMzeZjY5lOogGB+rnHx/YC52Pp+ufYrY6ECfnP/SXefAPu22DdxunH8jb7jbVg7b12iDyvOevR02L/jfjws0zYu77mj5sMHT32YNY+OpxwKx97YN6tdnMHGpZvgvT9Mgq+//CZOXSFlhRQq4ITiuM40UbbP9m83E0YxdJwHYmXKZbs6BWrcb9+FDYs3pg6LG65fe+01dWpR/dQ+Ylh+DEihQjL3pVGogCeNzJo1KxJ06NChMGDAgIhcBJqBbt26wZw5cyJ0YEEUbqyVKzcGpFAhN75K0zptoULjJuZbn83uIt3o9zRsHzcokci916GHvPlIzcSoSOL1DSxNldcIkRa1ytCiq46PQ2rUWgM09wbkrsf0yFghGxMGrc18UKIu5cTxuCWx7082ZG1jsy21WmV1EX8bUwNRnmRkMDEJddl5GQNrZ/3JyuRMDmYuylL/oAECGUQz9GVk54xVj87Vmva+OkHh36pAYdFy7VTAY58+fahAAddudk4F4Ilr9WJAChXKtlDhrrvugoceeijyJLv++uvh73//e0QuAs3AoEGD6Ju8w3wcc8wx8P7774fFMk7BgBQqpCCpApikLVSg139vLaW7ev2Baw9euFi5mRvp/HWMNsaVELuQrwdt1xq85rAthfHWRAShcUw4i2vHPjBGMmPbGky25xbN2MbJlBCvUNyAnZcOy91cjT9CeHm5vtZrlQayHqbDsycfq6SUdGKErR4Mv6aHAfHHyq0rylGsLt2yHboYDTdqvHXrNhg5dCyMUP8Xo0DhRz/6ERUodOzYUSchj8KAMCAMCAPCgDAgDAgDwoAwIAwIA1WWASlUqLK3ttJMTAoVKs2tqhyJlpTshf+8vRjenbgM9u5VZ9sXeNWpXRMOPrgRtG/bBNq0bgRN1MkL9evXgm3bd8PmTTthybKvYf4XG2CD2pz3mzuPUUdB1ykworgLA8JAEgOpCxWu7KE2ZmT+92/faE8K5snDG3PjfH2bbHoPGkqlUIGnzp8y+AG5n9YmjJHGj2MktJWqUEHNv+PJh0Df678DNevUjJ8RchLmSYnWfbEe3rp9TLyPJz2gS3M446FTtSSMk4DtuefXzXIfS1Tx3eBrh8KuLbsy4iMnF/xzANRrUs/ZZcF2hgC71Wvp+49Pg6XvF/7trj5uafXzLlTIdh/TcJZkkw07XzKS4vl4ng2ewDF24PhUJ3EwxI9//GN49tln5RvOmZBK0EqhQvJNKnahwkcffQT4rdXhq2XLlrB8+XL5dxMmxhvjvbjllls8ie6ed9558MYbb0TkIsjMgBQqZOanLLVpChXuvOcX0KixOiGSNxWpBO3yEjch0UA94I9TBG14UmRmjLy+80MMrU9sw1gGzopD/izH1mJ6fS9pMuVc2Nb3oznqB7LlB2tLc/LjGIHy8dO09gogvs+8cgQ0xB+UGyQP0Ee3esI2/sqH5J4PatgWxdi36kBfF5VOe/8jVaAwApYsXmFA82++853vUIECbjTnHPJHE8/qyoAUKpRdoUJJSQm0bdsWVq1aFXm6TZ8+HbDoSK54Bnbs2AGtW7eGDRs2RAw+++wzOqUiohBBRgakUCEjPRVGmaZQYeCDt+l8eW2jRrQWMQ9arAb4QzI0T1qv+HJn5fwQQ4PQmsdTWLnOBp11FBtTK6yd52tdfGwn5J6Xv8sDlYyZLabWO3uaLce0UZw+gI2zsXPx+9qRc+AWY/HlsRrKVVmQHeKpTsAHdVqAj6hntY2BAZTQL1DAfiEXnqCA7wniCQqHHnpoIVDiKwwIA8KAMCAMCAPCgDAgDAgDwoAwUIkYkEKFSnSzqmiqUqhQRW9seU9r1eqtMOKtBfD53PWlngoWM1x7dTfo3LFZqceSAMJAdWYgXaFCX+ilChXc2+qGMX6X3Qz9wgLmNPAGfEq7b3mjrlcYEcaJi4XwaIebtD987mNOIbGlExX+elaiPqzQe5dDk/Zy1Pqwl7PnQg8n0bY83bA8jJRpvGTyMpj4yJRMJuWvUxM8+Og20P3So2C/Dpl/tztOfFa+hSmPTYWF7y7OOpfjfnksdPheO/tBkO8Qf598i/z7GtvPGbF4NgAfvTQLPhn8WdYAyFH3S7sG7HLN+/MR82DG8zNh7569AZyKNKjToDYcMeAw6HbJUTmnxawGfy+xVMNFOQveG/w3GZQk+eWcXqIDZ5iUN+s3qdMxxt4/AbZv3J6IFVbgJuI//elP+kPSsFLGFZYBKVRIvjXFLlS44YYb4Mknn4wEvOOOO2K/ITdiWI0F69atgzZt2sDOnTsDLNSuXRtWrFgBLVq0CMhlkJkBKVTIzE9ZaotSqIAJmw1KZk8SCuwaw/87JrnvZs022HJfh3CrFuqpB4rixATCPtwysj9GFztmMJKxtacP2WaKid6IyzxoW52gn6aN7WN7fV+PmHQpAMSzOg+Q4rCZCx68Byj3fNCcsVCMfVazHP/m/O+UGfDaKyNh6ZLCCxSOPvpoGDhwIJx55pkmW2mEgfwZkEKFsitUGDlyZOwJUt27d4eZM7Of5pn/Xa4anjfddBM88cQTkcn86le/Anwdlis3BqRQITe+ysu6oEIFTBrXJbQwUQ/4YxYpbrWi1y48P167aFdjrGGMCeNpvzh764XxKCij65Z9uGWtP8Y8bY6ctDL0uqpvI7k++nnyeGyeg2vRzqEFMRiPW7LNEMPaeYBuLhhHKyyEzRk7nLFuGQvF2Gc1y7ds2QYjhr0DI4eNhW1b07/vF4yiR/g3ORcoHHLIIXEmIhMGhAFhQBgQBoQBYUAYEAaEAWFAGKjCDEihQhW+uZVkalKoUEluVGVNc/6CjTB81AJYufKbUplC3bo14afXdIdDOjQtFXwBFQaEAcdA3oUK/A67g4JMxQNsls7GWnMn8GFFNozSKFRwxRM2JerwhxO+nmVo4Mt9zyQbX+7bZ+tX6EIF9Vxp27cNbUbPVqCA80zibOfmHTDkJ8Ngz+7MG+/rNa0HFzw9AGrUqkG0+Zz62L48G79p9D62b89xUL99w3Z443+Gw151UlGmC09TuODp/vbECR+b8TL5s27tvHXwwVMzYP3C6LcXsk15tA32bwBH9O8CnU49FGrXr51zCj4fvrPPjW+TJGffJL0vZ9tCWj8nH8ePgzZr566D8f/vvaynb/gYDz74IH1rmi+TfuVgQAoVku9TMQsVcIN9q1atYr/Nde7cudClS5fkRERDDFx88cXw+uuvR9jAAqlf/vKXEbkIkhmQQoVkbspak6ZQ4Y57fg6NGzcyG5DcRiPKVb2I059F+GKOP3qgVWYyvCHJ7lBScvIiF3II+mmR3tTkLxLQz4y9MDqWZ2dtYmQmJZOzywN7eHkuNpb2URmjifqfc9dy9NG+4bEWMz/Gzxq5se/PfW7ZnFqOrQZWTzLUmhzYxg21KyZDMm7dUHvr+Zls6e9aLlBYtnQlYRTy0LdvXypQOOOMMwqBEV9hIMCAFCqUXaHCBRdcEHuCVDHXqoGbW8UGWMzRs2fPyKzkVLMIJakEUqiQiqZyN0pTqHDfg7eadRWvQLy01dqF11K4huE+LWeMmb8eQpFFoeWOtmQ/0htn9LO+ISwy8eyM2uSpR76v3w/EoKRJQk46j6g/ZY3x1P9RLJOIdrN6nhNj2nmjHeLgA3aNAbe+jAz4wfhYOxp7SnI0uAGdiUHhnIKHnAmmwTnhCT2DXx0FI4ePK0qBwhVXXAG//vWvQQoU+H5JKwwIA8KAMCAMCAPCgDAgDAgDwkD1Y0AKFarfPa9oM5ZChYp2R6pgPriRbsbHq2HMO4th3frCvvXDp6devVpw/XU9oF3bxr5Y+sKAMFBKDJR2oQK9EU/v0OsJ6I26/J3hblL2wwClCmr1iPVZ/RVk0QoVTCLBfFzO2OMPRXReTofysMxpdY98FbiPz3hBYdgzOq6IhQq11O/zg49uDUedfwQ0a5+l8CwF13MGfwozX54dnXxI0u1idRrBZcHTCGK5Rj9+bgZuQggw0zBF3nxP+fkw5fGpsCjFqRDH/OJo6PQDdVS3ihFIL4+cv/x4FcxRJzl89emaTLMpXZ3Ku3mn/aHL6Z2gwwntoEZNVUjCc0kTOQXXCIN8M9cMG74HLPfbivIcWfnRKpj4x8lQsrPETy+xX6NGDfqG+Ouvvz7RRhQVmwEpVEi+P8Xc/IUb7HGjffg69thjYcqUCn4iUTjpchqPHj069lvAu3XrBrNmzSqnrCpnWClUqDj3LddCBd5kZGeg1h327x21mNBrDr3A4WUO/R3DA+uIaxa2Uy39mLFuSM827EYqG4elLgebn4eBVvE4pAnmbPyiPlqBKfvzCeP6fuSB9ihEllighywN5MZ43JJRyJ6GBstQqEQ6iuXRDQnC4oX9fDsEU4vI/07WJygsX/Yl+Rby0K9fPypQOP300wuBEV9hIJYBKVQom0IFPFWqdevWsGvXrsB9wDX8ypUroXnz5gG5DOIZ6NWrF3z8cfTkUzytAp/LcqVnQAoV0nNVnpa5FSrQSimYrlqX2HUO9fWixSxdyJbWN75ASWktaGTY1xjGl+UeHgdlO92y1OERLoo9DBqGHNwwPnbUx+Xmz8eu3dDBXCwjD/VgPANrSZsfzZ2xdYswjEGQTozWWkQN504eJEc12VCrRaTlCXt60hKO9kGT3btLYPw7U+CN10fDurWFfZkMnqBw5ZVXUoFChw4dXDLSEwaEAWFAGBAGhAFhQBgQBoQBYUAYqJYMSKFCtbztFWrSUqhQoW5H1U4GNwPOnbceJk5ZAfPmr49sDsxl9g0a1KYihYPbqG8rlEsYEAbKhIF0hQr9oPeVPdRmab1TmN+85wStnN+cR0VgZzVbZtpAzA4hdPPGfvAUBSM0sH5YFKUuVGjdGPr/NdsHophXMJ4JW7TGR2cWNDiPfIv4sFioMOnR8t9oWbdRXTjwqBbQ/rttoXWf1lBLnZCT/kqe7949e+FNdRLBtiyFcbj5/fyn+kP9/erHhvWZ5GjakEe+RSxEjBB90/ttXLIJRv5ydAxOUNS0bRM457EzSeijc6bamke+RRDHH62ZuxYWv7cUVkxfkZVL3y/ffs3aNeGgbgdCG1Ww0uY7raF+M74vuXHm4uc2X+eXvuczydG0N498i7S46ea7eOJS9ftrKuDzPc2Fm2NefPHF2M3XafzFpmIwIIUKyfehmIUKZ599NowaNSoS7Omnn4brrrsuIhdBlIE9e/ZAu3btaFNeWPvRRx/FflNu2E7GmgEpVKg4z4TCCxW8jUzqjxJaJZg/TuyKAeV24ObOG6XIS+mNt7VFPduwF+OH8cIYvDRlf24ZB1uNgTFoZFWMHfTRE0AdyfUwkp/GNbYGlkeBOOyPs+aA1DdpKJkxCSyzWcpY1pWtlZPDc66+DE3tmIOoN7beVwUKrw8aCSuWrbJc5Ns55phjqEDhtNNOyxdC/ISBrAxIoULZFCo88cQTcNNNN0XuB56yMHjw4IhcBPEMPP7443DzzTdHlBdeeGHsiV0RQxFYBqRQwVJRoTsFFSrQ+oTXaGqauC5yix5e9WgZr2U8NtgW1028ZkI1Q6CebdhNh2R7lro1E2LZwISlA0dwbD6MxXZRTC1xesIy/mFctGUZmagH4xmYI+eI+bI9GhhYBPH6Xk5GqjlCX9aZjmoYz6q8nMjas+EgJbv3qAKFyfDm6/+BdesKK1DA946uuuoquPvuu6F9+/acoLTCgDAgDAgDwoAwIAwIA8KAMCAMCAPVnAEpVKjmT4AKMH0pVKgAN6E6prB27TaYOn0VzJq9BtZvyO2UhYb71oaf/bQntDqoYXWkTuYsDJQbA6kLFa5ShQre15R7b+u7Agb3Ln6qQoWAeRy2986/H5s/ikDSfAwmsWiFCl5OsYE4YIEtT5O3QRNcjrGXf7ACpv5teoGZhNzNByz74BffK6Jr1KoBNdTG85q1awCellCnQR2o26gOFQU0btUIDujSHLC1V9zNscpQJ8t8Ny3bDCNufivkFB22P64tHH/bd6MKI2GucVgI3zZAlrytXagz9v53YdWs1SFpdHj+0wNg3+YN+PMtMrB55xmbQPZ+C+sXbgB83qz5fB0gvzu/2RlNIAcJPkcatmwIWGCB/+/fcT9o1a0lPVdszoiXb975+uUwBzQtr+fIvLfmw/R/fhT4PZsp9YYNG8KQIUPg1FNPzWQmukrAgBQqJN+kYhUqrF69Gg4++GAoKQmeVNKgQQNYtWoVNG4sJ7kl34Wg5q677oKHHnooKFSjW265Bf785z9H5CKIZ0AKFeJ5KQ9pqkKFX/8cGjVppNcIar1DawX3YP5MUAL9E/gDRZv5Pm6WuHYivXp0y2bXJ71TkCPj4cCpgj4uAtqYCM7YqrXI+dIEjDaqQ4W2JUwNS9Ycw7hSTJ2nleh5KqFC0ELqYxcxURaSK5mReCpnYzyxCfCATn4+jOHLGBhle/fuhfenzIAhg0bBiuWFFyjgKT0DBw6U9RndGXkobQakUKFsChX69OkDM2bMiNzOESNGABbCypWOgaSTKerWrUvr8WbNmqUDEiuQQoXK8SRIVajwv7fSQsauu3BqtHjRKxiW0/qGdLyyYTOzXnJi487rKFxnWVC7ZsI1UGBtZMP6cd2aitC8GDoVtg0qdDwd0++jBC+UhWPjbKzcg/PtSKyMdKuxyI8wfSeU4sVzVCOjpoYxtAlakTU9WFMtw5z0pRWcjxUrJcvIzihQhicojFMFCkMH/wfWr9tocPJr8D2jq6++mgoU8IsD5BIGhAFhQBgQBoQBYUAYEAaEAWFAGBAGfAakUMFnQ/rlwYAUKpQH6xIzwMDKld/AzDlr4TO1AXLV6q0ZN941Uhtdf66KFFoeuG8AQwbCgDBQ+gykLlTwTlTArPw38iMnKgR2JZs5qDfr/X3GhOG9s+8XIvjY/HmBr7efMDC0h4OiUilUCCdsYherwSlY2sJE5Rrb93efqhQrVYsTyBmlfly2Shs/7JvWj+Pk0FbZvHPhzOfb+G3ftAM2q4KFzSuwaGEX7N62G3Zvx/9LqN2nxj5Qu34t9X9tqK1OQOK2TsM60KRNY2h6cBOoWSfLCRp+XL5nafMO+6b14zg5tGX9HJk1aA7MfvWT1Bnuv//+9M3wffv2Te0jhhWXASlUSL43xSpU+NOf/gS33XZbJNDll18OL730UkQugmQGPv/8czjiiCMiBi1atKCTFmrVqhXRiSDKgBQqRDkpL0k+hQr49wn9vYILBnX5f7vY5YntKL3qG1P7ZwyNPbm/yYn75Ofj6HAIqONqEB4GN0qxLeZn7W0Wxt/HYQdfpvIOuhAW4cXIEQHFOm+N962ZOZkrMHZzuBiDvLSDMSAMLSFQ68kAGMeiYUxjjDHsgFxJ4cvQjQoU1AkKQ14dBStXZC8e5lSS2uOOOw7uu+8++MEPfpBkInJhoOgMSKFC6RcqfPrpp3DUUUdF7l3Lli1h+fLlIOueCDUZBeeffz68+eabEZu///3vcP3110fkIohnQAoV4nmpaNKcChUweVy/0I9uScRrHSeyix4loj612hgftQeuh2iEJrZn10u0zrJy40PO2larcE2lQRyGAQ1h+3r29eDYmlrWcJ+U1gAAQABJREFUM7ZRUp6Ew+mylzFEsc5bK3JaY/I80FXhcQg/bytEE29g80Q/Lxedhc6J++i2e9duGDd2ChUobFi/yary6eB7Rddccw0VKLRt2zYfCPERBoQBYUAYEAaEAWFAGBAGhAFhQBioBgxIoUI1uMkVfIpSqFDBb1B1S2/HjhJYuvxrWLJkM3y5agts2rwTNqoNkVu27FLfYFoXfqGKFA44oEF1o0XmKwxUCAbSFSr0hV6qUMF/o56LE3AS/EZ9sJgg2/TwDX5nE/T1FGb7PsdAj6Ctw+De+09MgxnPzeRhYtu4dWPo/8SZ3scPyjSYVKwvFxT4WaJhrDwBL9Y2NlpUiL6B2H4MNA9v6DYQSTFzwUvCMCESm1g/P++EnBEwkp+RoS4tD3EY6J/tyjfvWD8VLFbu84AJGS5ibbMlbPQR34QYYbiIn4eXC9foFrAPB4oZx8b2866CzxH8XfahOkVh3ugvYhiJF7Vu3Rrefvvt2I3C8R4iregMSKFC8h0qVqFCz549YebM6LpgzJgx8q3XyfQnarBICt/0Cl8jR44E3DQpV3YGpFAhO0dlZVFqhQo4AbWOofUQtyTTMwvL/b91uI8t23muhEtjrbR/vrCfjuAefTn3A7g0YHs90Euw4N9rOqbS4482YCc7RjFlrWGUXnfo0c6HpYRofI2D1/gxbN/ojacX33RtDG3I5uyPBQpTJk2HIa+9BV+u/Mr659s5/vjj6QQF3DQqlzBQ1gxIoULpFyoknSR16623wqOPPlrWt7zSxxs2bBice+65kXngaTRTpkyJyEUQz4AUKsTzUtGkRS1UUJOzSy/ToTUOr3tw8mbRE5bzGohM2Jf9uEUlXlZPAx6atRpZBB6SsNnIwJmhTlDLKu4a06y+eQqWA+yEuUUj5gALFMaqExSGvTEGCi1QwJNmuEABT4aUSxgQBoQBYUAYEAaEAWFAGBAGhAFhQBjIxIAUKmRiR3RlwYAUKpQFyxKjYAb27NlL+zFr1apRMJYACAPCQH4MlF+hgnszHzMPFh+YT1fstu5MttF5F1SogB872PC8dToYg6VsRvl7Jr7cfaKhDLyN1oyBbgF7Dyeum+jHn/54McL+7OvHYxna+nKbt4eXaBsOFDNO9M2Sd5Jfkry08g5wI88RfYcT7h3fmyBnMU+KkIj9UBzwTYjD7kl+SfKK8hzBNRCe/rJk0lKeSta2c+fOVKQgR71npapSGUihQvLtKkahwpw5c6Bbt26RIFj0s3TpUqhZM8tJMBFPETz55JNwww03RIi45JJLYNCgQRG5CKIMSKFClJPykuRVqKCS5eUJrlp4gxLOwcn1gNY0SmjXNqpjR0aITRBDK1BGPfOQrU/W2hVTsVcsNmoD+GyuUAyG76fNWWHmwEN2IEgtpEf3YObhYXM4ZMPzJ7HJKyznMbcWguLiSAXUPzQ3I6H+t6pAYfJEXaCw6svCCxROOOEEKlA4+eSTMYxcwkC5MCCFCqVbqICFTfh314oVKyL3Fwtgu3fvHpGLIDMDu3fvhlatWsG6desChvh7ff78+dCxY8eAXAbxDEihQjwvFU2aV6GCmoReFtEiKrBGsssls06i+Qb6uAzSfn7jr5u4jy1ZcotgWmDXgRZNydmPYnoPvpz7trWY7OCtA1Vc/2IfzIEyM2orV8bcJ5V7MPl62BYYZQaIZWa+YTmPuWVzbDWEwtE/JLCoSkkFCmMmwbA334aNGwo7QQELFK699lrAIjkpUPDvgvSFAWFAGBAGhAFhQBgQBoQBYUAYEAYyMSCFCpnYEV1ZMCCFCmXBssQQBoQBYaAKMJBPoYJ/mgJSQB8iqDYsz06P+SBB7SgO+vJb/m6rsf2wIGIbjZK2UKGJOlHhnPCJCgSH8V3saISoxLfm7KNWTpKrvfN0maWJE/YL++SSRy62flzus384B9YntegX9mEs9Anrwji52IZ9cRwXX0f1keM8gzLfOlvOHJcR0tizre+bq5+Pwf18884nNsfK1Rf9wj6MhfMI63hu3OZiyz5+Gxc/03OkZOcemPjwZFj50SofJmO/V69eMHr0aGjRokVGO1FWPgakUCH5nhWjUOHOO+8E3Igcvu644w546KGHwmIZp2AAN5dhoceuXbsC1vXr14fVq1erE/MaB+QyiDIghQpRTspLknehAieMG570DiaSeF0rD+q9VYnpUoM4BpPtccx93CXF2GRpfW1H+au+GXJ62FoMr49mVu75WJmvD/XVkC60JXvj7/v6NtjXuftzsBYuDxaRvcEOyXCYKY7WGycVdO/eb2HKxA/gjdffglVfrjGK/Jvvfe97VKBw0kkn5Q8insJAkRiQQoXSLVQYP348xJ2WggUKcSd1Fem2VnmYG2+8Ef76179G5nn//ffT79eIQgQRBqRQIUJJhRTkXajAs+F1lhnrtZQaoNzKuBdaH/HaDO1i7GkN52OwvQ2i3DiK0lHfhTKewZi8PvOxGUKn4QDYNiwnYIyHOfu5eH0OznqtQnut8aIEMHw/9vVl2A/LwzIbQ3V27S6BsWMmwvA3VIHCxs0MlVdbr149uO666wDfu2jTpk1eGOIkDAgDwoAwIAwIA8KAMCAMCAPCgDBQfRmQQoXqe+8rysylUKGi3AnJQxgQBoSBCs5AukKFftD7yh6hYgI3Mf7wIlhsYD7IYDPzSYH3Bf1K47YHOwx0YLn7oME/cYFtfUvnA5BLoUJ/VahA0Wxi7iMNxEfcyAcVLj1tQlb4oBW+vcP2cFXXG4VOk9CQPoYNEuo4Tnw0NIrmQa5xedt5Bz+QyZa30weTKnrenDOG8aZp564+HPLEhktfgvNyOVo/J4reX0/H3eB8PUAy0EkG5s55e6Y+RsBWYei8PGMlK0re9v4GsXN7juAko3N08/GwVZdHTo/+7grP3Wlcz90nRmNdNA+TmjbwzC1G5DnCWK4tCtcIl4LvXVt2wfjfTYS1c4PfIumyifZOPPFEGDZsmGz+jVJTJSRSqJB8GwstVMBvwm3fvj0sX748EmT27NnQtWvXiFwE6Rg499xz6fdS2Pq5556Dq666KiyWcYgBKVQIEVKOw4IKFWjdwX+vqIH+0bOhPhkYeXwfjUnjrVd4rYRy7hO2XbBwTO2t/bHv2euhclNaMtACxtM+Zh1t9T4uodn1KPsZWMJkWbi1NqqjU2Zcbv2UUGYTIFcec2vxlJmyjtjrKRoMsgHAk6smT5oOQwePLkqBAq7FBg4cCNjKJQxUFAakUKF0CxXwW62fffbZyO1++OGH4fbbb4/IRZCOgaQPTjt16kSnKqRDqd5WUqhQOe5/2kIFu94x6yFa0ZgHXkfptY6et7XHIa17yNitj/SQjDUMrp70xb44tn0Mwgaqw8sy62V0bG+g0NLz8/FQzE6etRcDpTYOd4wpxSFohx+Orf01oHb38zZAmEUcNsW2yZAx23HLCHqKxtaks3PnLhj39mQYPvRt2LTxa2uaTwcLFH7yk59QgQJ+EYBcwoAwIAwIA8KAMCAMCAPCgDAgDAgDwkA+DCS93yZfDJIPm+KTDwNSqJAPa+IjDAgDwkA1ZCB1ocJVqlDBbsINEsUfQCQWKnjv/wch9KZjRIvHcB80+LHZFv0cghvlXKgQSMpL1kO3H1YEA2LidEXyi5FbY+XBn5X4fhrJPdqYTuR6Ko8g33nkHcKw8ULyXPKme+On4jKmXnS+bOyItRhO5FDQPJQf552ETRFi/Bwo3g/Ow5e6fhDbt3VJWgwn0gDGPIjhYgblDptTCupdTtizMYNiPQrx5N9H/1+OxYjLO4Th2yY9/7Llbe9vXM5KFp0vc+IStBhO5NDQPCHvJGyKYMJEbTS0jekiBXpBP84ZTVySOzbsgHEPvgcbl6Y/Dn7AgAEwaNAgwA8w5aqaDEihQvJ9LbRQYcKECRD3rdfyTbjJnKfVDB48GC666KKI+SmnnALvvPNORC6CIANSqBDkozxHaQoV7rznF9CocUOXplrs6PWOer3XP1qHcuyZZUB47cBju54yiNrH+KK7WUyhnPsUx8g5AOdgxYxn/W0iRuPwdEwUq7huEOizE+r9PIwXp+F0xsHl47B1CDNHxCNb8+gcglhajRmyg+4r36R8sEBhynsfwJtDRsPqVWtNRvk3+BqCBQp4koJcwkBFY0AKFUqvUGHHjh3QsmVL2Lw5+C3ZNWvWhGXLlkGrVq0q2tOhUuXTpUuX2KKEadOmwdFHH12p5lIeyUqhQnmwnnvMNIUKAx+8LQis1kR6WaTXPmYphAsfvXYisVsXsTOvlez6yCjIn32VjPUot30MSIbopDucg25Rri/rww7Wz8cztmhD+iAmY2FLoTkImWtbC886Y+t8HU86hM8PIZMp50sSD0unFoplglofq1Yd9UMFCmMmwYih78CmTYUVKOBJhFygIK8n7q5KTxgQBoQBYUAYEAaEAWFAGBAGhAFhID8GpFAhP97Eq3gMSKFC8bgUJGFAGBAGqjQDqQsVspyoENy07CgzHxWQwG3XZb2ToF0Uw3wqEPKOx3RYuRQqnPP4GZxMqMXYDhM/lfCz8Y2jefvacN9H8fHDdnqcFDU+JmP7uEkIODvfLj6+kzI2SjL7JUVMjofYPqaO5UfkPJIx2CLc+ih+jLBd8h1OjhnN24/mR0jG8K2476Nkzhk9cuObsX3cJITSe44k5Z3MU5RrjYGPwSsZI2jnRswJSnxenAX3kphKjuny/mb1Fhj32wmwZc1WhsvaXn311fDUU09BrVq1stqKQeVlQAoVku9doYUK+OH/P//5z0gA+SbcCCU5CzJt4MMTLA466KCcMauTgxQqVJy7XVChgtnwZFcSqmM3N6kp+n2eMcrCcvJHuTFiPY65j0rbN5Y6POIxum4JCe0Z0dMzBomMXMv0gPU+YiCOMmP8oI0BU0KXD+dmMlEKtvLjJPXZOKC3wmAeeILOpAnTYOiQMfDV6sILFHATKBYoHH/88f40pS8MVCgGpFCh9AoVhgwZAhdeeGHkfktBZoSSvAQPPPAA/Y4NO998883wl7/8JSyWcYgBKVQIEVJBhwUVKpjFFK+bcPnD6yFu/WmzjFvWkX/M+gvlbEutH4h0iMDrOOzri1ZymIu3HrM6ztnD0iIt4Hhsjy3qrdzve0ZWb+y1inMzmcTMEe3Y18+DU/f11GcF5oF99YPXrp27YezbE1WBwljYXGCBQo0aNeD888+Hxx9/XP5e1vTKozAgDAgDwoAwIAwIA8KAMCAMCAPCQBEYkEKFIpAoEAUxIIUKBdEnzsKAMCAMVB8G8i1UsB9KKKqSN+lm5pE/MMC9wfEY5lMBgnEbiLPFTluo0Lh1Y+j/mCpUiA+Dn2i4CQROXXDi2J7nFkjdl/N0fBkas5yBw3q2CcvZj+SeMm3enguFDuBxMqqNk7PMMwtwynK0S4zjK5RhHCbj+K3vhnL2i5PHyXws7CfZ+HKOQfYhha8LY/tj3w3l7Bcnj5NlwmK8JD+Se8q0zxHE9dwy5hy25Zyw5cvHYhnyEJZbbnyFErKcfZNa3w1t2C9OHicL4ybZ+HKOgb7q98jGxRthvDpJYfumHWG0xPHtt98OuHnS/p5MtBRFZWdAChWS72AhhQq7du2ib8LduHFjIABuDli6dCm0adMmIJdB7gxce+218Oyzz0Yc//znP8Mtt9wSkYvAMSCFCo6L8u4VWqjgv/zjaz6NjTD8Gs6bnhLlhgzW458i7EM9G0x36BFjWrkGYB9qUWT02s74Wh/29+VWSYDsR61SMb6Oph85Zxy5fBw2If5/9t4F3o6qvPtfUXghwEm4BgiCgIAXoNB4icZa66cVi3+qrRcQkKtAuUYMQrgJfoqv+tZqX1v1o9ZiamtF6uWVmyFAIIEkBAxE1IIWrbVa7oEQcpKQ2389a61nZs3smb1n7z3nnH35jnHPmmc9z7Oe9Z0NrJNZvzO2QzNrThedsauHJHK9yXhptIzhOzdv2ZwIFJ584mkf0MWnbEIWgcIf/MEfdJGFUAiMDwGECmMnVHjve99rvve97zXcSFn3iJicozsCjz76qDnkkEMa3qYob7H47W9/a+TNFRzlBBAqlLPppZ5OhApufSNLnGht5Oak17avcB0miyb5E9ZHykF8Y5P2i03z6NnH2A57+JhsrLPrOHL2Bn9yl3Gs79Q87irycUH2Q/vd2fZrfdrv40Jed6E9Wpur3iXyXmnOOFYG0n6XIVw4q23HvVrDBvv3CbfNX2xu+sHt5vnVa3Tgjs7ydxDy35WrrrrKHHbYYR3lIAgCEIAABCAAAQhAAAIQgAAEIFBGAKFCGRns40UAocJ4kWYcCEAAAn1OAKFCeKOCPKSINxfrfZWnJe1s5E7iyvK1ae8oX3jiUjghTVhyLuVQUHeZb5y6io/6O9ZyUXQj1KmNc9nYZfZWqcvi+vU74ubTAetSDgW3rsw3Zl3mU2Tv5jtSmK+gZqmtyDeuuaxdEPfkw0+ZOz91t9k4urEsKmOXh6Kf+tSnzNy5czN2LgaXAEKF8nvbjVDhhhtuMO9+97sbkr/tbW8zCxcubLBjaJ/AHXfcYWRTb/54wxveYJYvX543cx0RQKgQwZjgZhWhwiVXnGumTBlJKnUbmOx/83Ujk1842G6xqZdrh6tcW1w0VjdGyRJHj6RP41yf9Qxn8UvcrTGObcgRFaXxqb/PEl/HbTdOOpBLLf06fx3L+2muJCDxl2qd1QZrb2accCF9OvcktzVKVGyX9ubNm81i9waF+eapJ59J3DttvP3tb3cChTe/+c2dpiAOAuNOAKHC2AgVVq9e7cSu8vao+Nh+++3N448/bqZOnRqbaXdI4I1vfGPhevG2224rXF92OMxAhiFU6I/bWkWocNUn5rh1js5I11jpuiesnNx6yHqFdZH6Z67VNVlXeUO65krXWWJzq7Lo7JL7IdJxQk4dT2PkOtN2frJeSz2dT3TdrM/Nw/rGOZNMNjDloVbrGxL6oV2k68yMI7GhkKQUTRHG0zzebZJZv36DEyjcfOMdtQgU3v/+95uPfexj5tBDD9WROUMAAhCAAAQgAAEIQAACEIAABGolgFChVpwk64AAQoUOoBECAQhAYBgJVBMqzDQzTjmyFI/8tX/xGxEkJH4UUL4pOn2k4IfxnrG/zyOf8VgaF3v6Nyo86BM1+UzeqJDLKfvk4wcVSYp4kMSYa4TpSo1am+RTDBl7LjS5jMbZOim9KMuncZO22sHD+Gpz5zRFxpy5aFF3xrfoIhrD3Z+ojqTuKK7oHkbdThsSpYi70nZLh9Q1bmXuQVx3Ees40LaTum1c0XdkqxW1FM03k6aobqkj2DP1ZQKji1Z15/JpZM9/R8rqVjg6EXsW/VARysjFNys5ZaMy9yBm7f7loGmLE8ffkd+teMzc/bmlZvOLm7MDlFzJb4788pe/bM4444wSD8yDSAChQvld7UaocMIJJ5hvfetbDcm/+tWvmjPPPLPBjqF9ArJReN999zWPPfZYJlj++yi/KffAAw/M2LlICSBUSFlMdKuqUGFkyk7JGs+tAe0yIF0LpmuCZHOU9IeVSupnZxtcXV/GJyWh/pJL2y5bSB5SuADXHxtCmjQuzZHNJ44+MKlZLNFF3M74Wp/IzY0ovll/Z05sbiTx8eYo3lpCMukry6F2FSj84Hu31iJQOOqoo5xAYdasWaEyThDoHwIIFcZGqPBP//RP5tRTT234Ishvw/7Od77TYMfQGQFZ5xe9gUve2PW1r32ts6RDEoVQoT9udFWhgsxGV0huveOWRsmKyU9WbGHauiZycfGCLDi4XM7fGzIuuuaS/qQtfsE3jCGXmkdNetY4uda2pNK25vL9GhX3Z9vqn+TwpSSBkjfNnZgTm3MXn9AlefxhG+HC5VCz9kZ9YtqwQd6gsMjcfIMVKDz/Qs67vUt5g8Kxxx7rBAqvec1r2gvGGwIQgAAEIAABCEAAAhCAAAQg0CYBhAptAsO9dgIIFWpHSkIIQAACg0mgLqGC0Ek26AZU+pgg2ufrvEJ35qS+sTHOF/eX2310W0KF/3t0Q91aQ5Ux1Tc+l9cXSMizkuQRimy49vbYJvniPJo/9mnVH+eI4zRX/hzni/3Vnn8wVFS3+uZzF+WLfbL90lPMJI7Rto4Z5/AZQo70KVXCWvpjf82hOav0N/OJc8c5tR2PF/sm9jH8jmRnnn7P4jq0zvw5qc92xP5qH+bviLBSDtL+z8X/ZZZ96T6zdXP4516MTY7tttvOfPOb33Svg2/iRtcAEkCoUH5TOxUqjI6OmmnTppm1a9dmkgtr2VS/6667ZuxcdE5ANpjJfcofn/zkJ81ll12WN3MdCCBU6J2vQlWhQuMbFexKKNkIJfNxi7d0hR+t5ZL1UeTv1lEZn5SJ+kt+9XOtaMAklbVFZpckjbFRUadvxv4+S+oS98WxyWh+LBvgLKnZj2OvQ08yGR0/OYeeeExJqqnUTxPo9ebNW+wbFO41IlB4+qlV2t3x+R3veIcTKLzpTW/qOAeBEJhoAggVxkaocPTRR5v58+c33F4RKYhYgaMeArImF8GrCNDiY5dddnFvrpB1O0cxAYQKxVx6zVpVqJCugsLaS9ZFujByk3ILrMK1kq6Tkk7r7/JFa7I4l/qLLeMXObmho/6Yq8aLLdt2lqhulyVzHQ0Rxeb8rJOOr+O6cbQeNUbjS7/P4jv9OMGifXouiN9g36Cw4NbF5pYbFpo1a7oTKMgvH1GBwqtf/epoNJoQgAAEIAABCEAAAhCAAAQgAIGxI4BQYezYkrkaAYQK1TjhBQEIQGDoCfSLUEFulD56iDcDq036dTtw3UKFeLy4DmkXHVn/tMLYrtbYJrnK7PE4rXzK+tUe59K2Z6cEy+vQHO3WXRan48u5zEftsa+2s3WnnlXqU++8r+aWcyufsn61x7nidnbM1Du2qzW2Vampik+r3HGtcTuupVWO2LebmuLxW40Z+2o7+x0pv6dFuYtsmlfPRT6P3PwLs+KfVqb/UlLnkvPIyIj5/ve/b2TDAcfwEUCoUH7POxUqXH/99ea4445rSHzMMceYG2+8scGOoXMC9957ryna6HvEEUeYlSvtvwc5CgkgVCjEMiHGKkKFuVecZ+SNCu6Q3U+6Wco307p1E5TujRJHe+gGK3XUtUPo9uvNKJdu/PJDaYeNEkN0uCsZMzK73OG6wd8HuAxpjMb7oNZ2Cbe+/o87O4sE+hR+Pm4Ua7J2rSN0ux61JbGRf2i6uE2bNptFdy4zN/6/22oRKMgG5Kuuusq88Y1v1GE4Q6BvCSBUqF+o8PTTT5vp06ebjRs3Zr4XU6ZMcZvnJ0+enLFz0R2Bsg33sl6XdTtHMYEybup9+OGHm4ceekgvOU8QgSpChas/cVFaXVhL6VouXjfJYs9d24/QcnFuPRU5Jn3BJteSVg9df/mhXDKfL3ayzv4yjW3IW+Iv46RdGu8LaG130TJB+RM+JJ8axKS5cmfxD4fOUS6Tts3hI7yT2NevW+8ECj+88c5aBAry9w8f+9jHzKte9apQCScIQAACEIAABCAAAQhAAAIQgMD4EECoMD6cGaWcAEKFcjb0QAACEIBARKBdoYL81X6yAVl2ALu/6de/7k83ukdD5Jr+4UBjjpybXiZjqKHsnD50WPL3y82Krz9Y5pjYp+wzYv7MvlHBHWXjVJlSktE2MjykwybI51BcGqf9ZXb1y/eH9JmnLeqrOfW61bnTustqiscr88nb261ZxsjUbRPkc+THkBjxKbNLvxxl/WV2H1Xt0+WIE3VRd13zrVJ5J3VXYS1jxzi0lqLY/HzVt9k5X3d4g0kSUnVsCciPn4+1/T++7ifmp997OEnfqrH77rubW265xbz+9a9v5Ur/gBJAqFB+YzsVKrzvfe8z3/3udxsS/8u//Is58cQTG+wYOicgb1c68MADza9//euGJA8//DAbNRqoeANChRIwE2BuS6igO6zsf//dTx5hHZAsB8SuPnYuyU8nkT2xyVzj+GgDleaQbm3bRtqWWHu4cGfX6zRhXJ/vDT5xferubP4i7ZbxJCZvz9niHNrWiUm0TaJzCN2SILGVtTdt3GQW2TcoiEDhmaefdTHdfLzzne90AoWZM2d2k4ZYCPQUAYQK9QsV/uEf/sGcddZZDff5pJNOMt/4xjca7Bi6IwDvzvghVOiM23hHtSVU0AWYXSzFa7hk7eTWU34Grj9Mxq2xCtZfuhRzXRIb+9u2W5/FNh0/sUlD1nDekGSw166tCYO/8w7OGpPGe+fWdpfFZXS+OrZcaDs0krVlSBq6Q2x6pX5xfevtGxRum2/foHDTQvPCmuwbGF2CNj7kDQof+MAHnEDhla98ZRuRuEIAAhCAAAQgAAEIQAACEIAABOojgFChPpZk6owAQoXOuBEFAQhAYOgItCNUSB5MWEqyMS05kqcNkS3pzDbKc2T9kitNmT5nSLryDc0tb1T4UTtCBR1DEsbjxPb8YM2uEx7WKebULEb6qoxd5lNmbzVm3D/edddRs+OmiewNa+eeaZjkKIor6y+zxyxbtetg3a91F7GWuRRxLbK1YlvUXwfvorqj+rZu2Wru/9oD5j9uK98wky9t3333NQsWLGAjbx7MkF0jVCi/4Z0IFV544QUzbdo0s27dukxi+Q24TzzxhJE3mHDUS2Du3LlGNnvnj7/6q79ymzbydq6NQajQO9+CtoQKUnZYU/iTXwgkywzbcJawPtCfTcTo2gV2l1J6Q5/zVL8knzd4n8QxjFUwpnWJx4tpZzdshdGTlHEd2pd0pjUmdfnMcU4pKlTkOrVPzmkm6+MuUov6bbZvULjLvkHhpv93u3nmme4ECpJTBQpveMMbfLF8QmCACCBUKP+5S9jcdNNNbd/tt7/97eb2229viJNckpOjXgLPPPOM2XvvvRveYDF16lS3bt9uu+3qHXBAsiFU6I8b2ZZQQabkF0fpGsmtqVyHLK78Osqd0/WTt2un+IS+5BSv7dJ2si7T9ZnzD0FSSqgnlCRXPrftcGOkrq7P9WfqDxE+kfNJc/lgXfv5WOdik4cZhPyxjxQVekM+mU/IFcLTXCGBNaiPCBQW/HCRmX/zneaFF0ajiPabIlA44YQTzBVXXGEQKLTPjwgIQAACEIAABCAAAQhAAAIQqJcAQoV6eZKtfQIIFdpnRgQEIACBoSTQiVDBvQ1BN+26v/vXBwBqbIbSP1ZwnrqJX8OLwjRlM58Qpw8s2hIq/G14o0LR2NggAAEIVCCwZdMWI//e+a9l/13B27vI6+BFpCBiBY7hJoBQofz+dyJUuO6668zxxx/fkPQ973lP4VsWGhwxtE3ggQceMK997Wsb4g477DDzk5/8pMGOAaFCL30H2hYqSPG6iUrb+vOQPSc/srh2uEqM6WYp93NL5OP3WXnHsOfKbaxyFt2EleTRn3rSfI5p6NcNWXp2feEjtmlbx/PTSQaxl77d0G8NatMcLcfwyRM+Gq9jbNy40Sy+a7m56Qe3m1XPPBena7stNcmG4quvvtq87nWvazueAAj0CwGECvUKFZ566ikzffp0s2nTpsxXYJdddjGPP/64kTU7R/0Ejj76aDN//vyGxD/4wQ/Mu971rgY7BmMQKvTHt6BtoYJMS9ZY7uw//HrJWvwfMbr1oWu4C9/SdaU3qb/LlPHX9ZeslXQN57y8qw0P40tLnX1S+XS2eCxnDB/qn9Ts/FMP7fcWrS3X7+oKHvH4wS3OoW1ff1y35vRjrBtdb267dbG59Za7uhYobLPNNolA4ZBDDtGBOEMAAhCAAAQgAAEIQAACEIAABCaUwPr1681vfvObhhp22203I//ngMBYE0CoMNaEyQ8BCEBgQAhUEyq80bz2lCPtL51X1UC1yctjgsaY5OmHTVKcTx8vNMam42ZyS5oorWwYXvH1lalzSWvKPiPmGBUqONGETRLyROlKohvNyVsmwsOUVjnEXx+saDadszJQe3xOqLlGmPw41a1zLKq7Wc1Sf1p3aEUPnVqxiuevbVdLxRxFrH1N9h7oTdfE0Tmp2TmPL2s/JN8RvR29+h3ZuH6TufuzS81jP35cS215fv3rX29uueUWs/vuu7f0xWHwCSBUKL/HnQgV3vve95rvfe97DUlFwHDcccc12DHUQ+Dggw82jz76aEOyhx9+mLfGNFBBqFCAZMJMnQkV5EcGXXzblmv662Rpai9Tn3R6uoZ2fZGP2sVTc4it0K5jO18/rhshNDVGz65PfKWhyV3TB0SmzHghQqKSsKSm3FjOKXzE42pbxw5hSb6NGzeZRQvvNTfdcLt5dtXqOE3bbRnrmGOOcQKFIvFU2wkJgECPE0CoUK9Q4atf/aqRjcX547TTTjPXXntt3sx1TQSE7Yc+9KGGbCeddJL5xje+0WDHgFChX74DXQkVZJJl68DMwi2lka657GrL/fGrLrWHlC5AbGp3Xt41Xbu64YPRBbqwNCauQXydj/fXvJHJBcf2EJGsB71vqElryY2hPi6Z/dB8OnYIS3KuG91gbrVvUJC3KKxd290bFESgcOKJJ7o3KMjPvRwQgAAEIAABCEAAAhCAAAQgAAEIQAACKQGECikLWhCAAAQg0ITAWAkV3OabMK5uvveX+uhArjLbwIO3PK7wPtm4pDvpdxn0rQxyEVK3JVT4nLxRIa4jra/gmYiMUnjoBv58pz44ydtj/9hH7bEtjo2nO+51W0x6T+L6tGapM7a3rrsz1pI3HlPHKR87vb+xT5wjtmu+CWWdm2Ncn9Yd27RmOfdK3XF9WrPUF9vlWo9Wdbfzz6PkjMfUMdy/XdKvXWKOfeP6yuwauGHNi+bOT91tnnn0GTW1PMtvP/z+979vRkZGWvriMBwEECqU3+d2hQpr164106ZNM6Oj2Y0IO+ywg3niiSfMTjvtVD4YPV0RuOyyy8ynP/3phhzXXHONufLKKxvsw25YtmyZmTVrVlMMiGua4qmts4pQ4ZLLzzVTpkb/3baLEr8u8YuKxrYtz3a5n2midUd8rW13DrPRNYiueeRabeLiUmneYEji43FCgoZYF5M6ar+Ol10nxX4SaHvF0f3xZ28Ndr0Ifi46/Qi1J9W631h+18Jl5uYb7qhFoCC/dfuqq64yM2bMiCqhCYHBJoBQoV6hwlFHHWVuu+22hi+NCMzlt/5zjA2BVatWmb322svIm3XiY+edd3brd95kEVPxbd6o0MikFy1VhApXXTMnXesl6zeZjVtEFaw3o3WXd3FTdyuscK3tdNWVxuiaT9Z0yTpQ4dn4JCbXTlySGtPBk1ZRX9oZ5iKZvFFrcRa5kD+xUTyjaxdlr/05yuMThKzGrFu3zooT5A0Ki+zfC6yT3o4PESh88IMfdAKFgw46qOM8BEIAAhCAAAQgAAEIQAACEIAABCAAgUEmgFBhkO8uc4MABCBQI4GqQoUZpxzR1qj6cEM3tmeD5bFCunk82yfPJtxjh2RTfL5frsUnya2pfJipS6jgxgk5M+WqLSos3tAcmV0zfrAihryvm6/N2WCPHsj4OJcu+tCJiyktyrXkI+7OushV2NCed3Jd7qNl3ba+fM0S2BiX5vQtHTOt2ccFP+12xmCLTn5De+yUdjaO3egnPvm69R4kmWxYNjK+6rTuOEcykmu0qlvra6i7D74jAjL5ZzVMu3G+WR5Z+invZLoxyrQ7SdL0OyL/rEQxeaaSpOg7onYdZPTpdWbhJxeZ1b99Xk0tz/Kb3r/5zW+a7bbbrqUvDsNDAKFC+b1uV6jwb//2b+bYY49tSPie97zHfPe7322wY6iPwIoVK8zrXve6hoRHHnmkefDBBxvsw25AqNA734CqQoURK1Rwy4ewGHFrmbCeSJcVdsWmF/Ycr3fcWk6mLXafybW9SYMkRv7vr+Ws7RAqJ28LIS5XGu76Ex/x9Rc6oh8geGluP5yO6QKcRygjtJMBff25MZNcLlzqdmH2I+QN9o0vbjQiULjlxoXmuWe7f4PCu9/9bidQ+P3f/30dkDMEhoYAQoX6hAplm+V32WUX8/jjjxs2y4/tP1YiBJk/f37DIDfffLN55zvf2WAfdgNChf74BlQVKsiiya2WZPHk/vizzNLZ3XTTtZVbc6Ud1idcuLC07eNTR4nT9Zlv+77EwzZcrmCI266E8JGs+UKyNN63tN+N70xq9xWldp8w8bduSdt3uU+1SRZpy7D+rwRDXvGyxlH71oTb5i92IoVuBQrbbrttIlB4xSte4ergAwIQgAAEIAABCEAAAhCAAAQgAAEIQKCYAEKFYi5YIQABCEAgR6CaUGGmmXHKkT4y3iAsFvdcwD8cSC5tw21MVt+0W1z8E4Uim+9NP8NDD2+wycryaUToX/qF5WbF11eqtfQ8ZfqIOeZzf+oeaKROYZzM2NKrg6ee2VY8Ic2R9Wi4kpRxWIODGnJOsgvbmSK7/jr6jusO82tVU6t+LblhYjYwidW6i2yaQJybHbkc4qqmorBk7KLO2JZLUshV6875ujTN6o79NUc8dkG7m7rdcNGYhXORMZvVLP2aI/i1qknTaZikKDzyDjYwyR311VF3lZqSsQuLjYyTzJrH1piF/9u+Pv6p7G9tj5wammeccYb58pe/bF760pc29GEYbgIIFcrvf7tChQ984APm29/+dkPCf/3XfzXHH398gx1DvQRkE8evfvWrhqSPPvqoYYNHFgtChSyPibzqSKhglynx5q1k1WLX4Zl2ehHZQ6xMOulPbbKUTzZkST7n4x3Tptp9Eu+TpZjkcC6hrjRBNm9Tu8+r+aRml83FpGNqv6vfO4VO76gChR+KQOG56iLPdIS0JWP9+Z//uRMoiBiKAwLDSgChQn1Cha9//evm9NNPb/gqnXLKKWbevHkNdgz1Evja175mzjzzzIakck/+8R//scE+7AaECv3xDehWqJBZatm1T3It7XARWZP1o6OTODdbY3qnxNU10twuMun0zHW9J1fePVQQYp09004TZGJTc1q3tblsUZ/P5w0yZ+mXs/8rPm8fXbvOCxTmLzLrRtdLSMeHCBROPvlkc/nll5sDDzyw4zwEQgACEIAABCAAAQhAAAIQgAAEIACBYSKAUGGY7jZzhQAEINAFgbaECrrZNz9eeELiHxH4zsxvKc90RMFldnXRJy9yrZuVpR3HybUeoT73RoV5HQoVMuNEA2XsOmB8bsfXxsUso9A4Y9qOHDJ1tLBnfNNs2VZZjqyXu2qrZokoyx3smfrKfAvqcKY2/Dutu1J9bdQR153JXTLHtuouq6OF3Y0RBopcsxVFHa3qbqtmGaUsd7BnxivzzVabXrXh30bdq/7zWXPXp+4261dvSIdq0br00kvNJz/5yfQBbAt/uoeLAEKF8vvdjlBh/fr1Ztq0aWbNmjWZhNtvv7158sknzcjISMbORf0ELr74YvM3f/M3DYk/85nPmI9+9KMN9mE2IFTonbtfXaiwk2yNcoW7jVb255T4R5XQ4T2iDt8MkdHSxFnCdcia5NONXHLWeMnv/NKPbJ/misZOY+LxNaer2GXNjBHyyGjZVNG19XEZC8bUXK7Lfrwob1C4Y5n54U0Lzernsv9+1gqqnoXHX/zFXziBwhFHtPe2v6pj4AeBfiKAUKE+ocK73vUuc+ONNzbc/htuuMH82Z/9WYMdQ70Enn76abP33nubTZs2ZRLvvvvu5rHHHjPbbLNNxj7sFwgV+uMbUEmo8Ik5bjJ+XeU+7SIrWnPpVMUmbb/Q8jFhsaVrrsRVPJ1RT2m+ojVmcA3O/soPE7dl6MTTjy+fSV3uIi5POsN1Nk9qlxg51M815UpM7ojH1Jpcl/1Y+8I6+/aEReb2BXfXIlAQYZoIFA444AA/OJ8QgAAEIAABCEAAAhCAAAQgAAEIQAAClQggVKiECScIQAACEGhLqCC44g29cq1PCKRtD7ls+TYF5xmctS3n0tyhQ/vdmHFgaIf+toUKEi5PPOJN0Zq+1K4O8bksR+xj2zqP2Fw2p8SnLHcb9tIxynIkg/tGvu7SfHFcWe4Ce1usZYyiHPHYtp2vOYTlvAoui3IX2Fy+MntB2qKaXY6cb0d1l9XRht26Fh9lOXLe+bpL88VxZbkL7BP8HXniZ0+ZxZ9ZYjau2xhPoLQtD1VlAyQbdEsR0WEJIFQo/xq0I1S46aabCjeSyeYy2WTGMfYE7r33XvOmN72pYSCxLV26tME+zAaECr1z9ysJFa4414xMyQsV5MeH3ELHXjtLzi5+OZMDoPEao9kSuzVoW9a9aQ71TPt9X+yTMtYc4qPttFdtPmc6htrVM9cvuVxNrhHmk/q++OKLTqAw/+Y7uxYovOQlL0kECr/3e7+ng3CGwNATQKhQj1BBRK4idhXRa3yIyFXEriJ65Rh7AmWb7xcuXGje9ra3jX0BfTRCGSudwuGHH24eeughveQ8QQTaFirYOt06zS7G4vWYK9/Z/FpMp+N9Cnw1j5zFWWLlbA9dB8rZx4uP7VWHtBH5usjE3yUKH2m+NHfar2P45DqeyxZfhDETk5RjL+K6kj5rXfvCqBMo3LHgHrNuXfbf2+nY1VrydzEqUNh///2rBeEFAQhAAAIQgAAEIAABCEAAAhCAAAQgkCGAUCGDgwsIQAACECgj0I5QwT0ksImcEKEsoW5UTh5yeEeJzQgYxJzx0QtNUDaAtccuLkw+rDHYOxIqNBmOLghAAAK/vf93ZsnfLTebN26uBEN+6+NXv/pVc9ppp1Xyx2l4CSBUKL/37QgVPvShD5lrr722IdnXv/51c+qppzbYMdRPQN6mte+++5rf/e53meSyyfi3v/2t+025mY4hvkCo0Ds3f6yFCv5HFfuTkGtk551s7rJmbYuHtiUmu0lLk+g56+u80y43mObyed1nQy3exwfGdcaxktsnDC17qf3p2ZgNG1SgcJd5fnV3b1CQf3e85z3vcW9QkE2XHBCAQJYAQoV6hArXX3+9Oe6447Jw7ZXYrrvuugY7hrEh8IUvfMFccMEFDclnz55t5GcCjpQAQoWURS+3OhcqpGusZH52geZWYtFCTa8jU+Se+ocVnOuL12y6xtSzD/bePme2nR9Hc0mc+hf7xHnCKBnHXL+9lNxxXeL+gggUbllkRKCwfn31N5z6EbOf8ncw8ncEl112mdl///2znVxBAAIQgAAEIAABCEAAAhCAAAQgAAEItEUAoUJbuHCGAAQgMLwEOhEqCK1SsYKKCPxzBgfWPVwIiGUTW3JEPvYxhHok3aWNKEVmp03IjVChlBwdEIBABwR+tejXZvlXf2S2bo7/5VOeSH7rpmxqefe7313uRA8EAgGECuVfhapChc2bN7tN8E899VQmmQiGHn/8cbPbbrtl7FyMHYHzzjvPfOlLX2oY4Mtf/rKRzTocngBChd75JlQRKsy94jz3RoWkatk8JT+6yDkx5q6dQ/gJR/0iZ9cUe+wXciU26+RGCHFpO4zrk0Q/DnnHkDLJrSV6e9ZH+nQ8N1oYK2vXDMHX+qS1eJsXKCw1t95sBQrPv5AGdNASgcL73vc+87GPfcwcdthhHWQgBALDQQChQj1ChRNOOMF861vfavjSfPvb3zbHHntsgx3D2BAQUet+++1nX3Sa/ZlbbL/+9a+j/1aNzfj9lBWhQn/crSpChas/cVFmMm5NJmsxWSPGPXodFnlJX2JPnXVdl5zTruSfI0mja7lkJJfUXqXJM21Jo32aW1N7exzre1K/bF9qTzL43FFd0iN+L6xZa26bLwKFJbUIFOSXiYhA4eUvf7kOzhkCEIAABCAAAQhAAAIQgAAEIAABCECgCwIIFbqARygEIACBYSLQjlBBuMgDjFKRgjjoM8XkwYYYozjt90bXl35IUOyQ9mRa6uLG0IGsMdjbESr8f5/900zq/IU+hFF77pmpmhvOEtfKt5VPWX+ZPS5CfPQoqqMsR5ldc1U5l+Uos2tO6Y+PduqO44rarcaWmCIfKUm/bkV5NS7uK6o77td20Xjap+dWPmX1tYqT/OKjR1HNZTnK7JqryrksR5ldc0p/fLRVtw1sdi/Lxn7kpp+bB//1oebBUVFTpkwxP/jBD8wf/dEfRVaaECgnMKxChUceecS8+tWvLgdjey6++GJz/PHHN/WRzgcffNDIGxXyx+tf/3rzla98JW/megwJLF++3JxzzjkNI8yaNcvIb8qt65g2bZrZZ5996ko37nkQKow78tIBuxUqSOJ4eZJsvLILC7UntshZbNKf6ZN+e6gt028vNKPrD8nVN0SGeJcls9bz/VHuEO88owVWnC9uZ+KllhCzwf5G2zvvWOZ+w+2aNd0LFN7//vc7gcKhhx6qQ3KGAARKCAyzUEE2mP7mN78pIWPMH/7hH1Zad2zcuNG89a1vtb+pO/vvL1mfL1q0yOy4446lY9BRPwERjfz0pz9tSCyikVY/NzQENTHIf2NEFNevB0KF/rhznQgVZPHmllhhnZUs18Su047auh5zXcFBbNLM9IVYtUl6zag2CXK2KI8OKT1ySJzzCj5yJYfa07YzZ2pIxnH+uQTB5nxClwgUFvxwkVl4+1Ij681uju2228697VQECiJ+4oAABCAAAQhAAAIQgAAEIAABCEAAAhCojwBChfpYkgkCEIDAQBOoJFSYPdPMOOXIYg4NzxaCId5BHPvEO4WL7LFNRoz9tQLrow9UMqKJ4NueUOEdLmtcrhjihyw6bHouKirtlerSw1aYc48fzni/rE/R2PJb5bw9zSyt1rlj/1whoUtyNI7ZuiYZPM5YlqNV3Y1x2ZrT+mK7tmPWYmtVd7ZfIoruh9jzRyNr8ciPr1ExGbXF52xc/rcGFtUUj1/ErCe/IxXvx1h9R/x3J8u68nfE3sIfX/cT8/CNP49vXNO2bJz94Q9/aGbMmNHUj04IxASGVaggm78Q9MTfBNrtEJgzZ4757Gc/205IT/kiVOid21GrUMEuaJJVR2nbz108Zf3TuOZLbdLXkM8ZfGySKXESS9qXz+1DvXNI41Jk/crjXXapyf5/wwYrULAbx2QD2Rq7kaybQzaLym8tlzcovOY1r+kmFbEQGCoCwyxUaLV+HqovApNtm8DatWvNDjvs0HZcrwQgVOiVO9G8js6FCnaV5pdrepLFYYW2r0fXj9n1XdonLfXRtusNi0M7lL/Uhr+0n+VrRB/qA9Ow1D9klGm4o6E2a/c1TTJrXrAChVvuckLYOgQK8gsNLr30UrPvvvv6wfmEAAQgAAEIQAACEIAABCAAAQhAAAIQqJUAQoVacZIMAhCAwOAS6FqoIGjCgwZPKVxkdlVH/OL923FckT22RSniBxqZrfLBv12hQlxqNIx7SBJfS7txQ7n3iHO4x0cJhuJJ6Bzy+eLxinz0oY6vJfZO2xqXWrJ1l+WI48rqUp9W/b6+dO46Zswprk/amju2x+NoDlFHpJnTuNg3zhHnbeWT79cxy+qOcydjuvrSCstyaGx+TM3Tql/8inx0POlvp+58HZonzqHj+dzpHOVaD/XJ50v65V8YBf98FI2nMXrW3Hot53gczdHtd2Trlq3mR//4gPnlnf8ZD9W0Lb/Vc8GCBeaQQw5p6kcnBPIEWm20Ovfcc80Xv/jFfFjfXyNU6PtbOKETQKgwofgHavAqQoVLrjjXTJky4ucdFhtuTRLWM/7k1zeunSxIwpLHXgdXZ9ArXddE7m6M1B48dUzpjZx90/okyX2JMojaNJcLDfGJe3DSPBod3OwpzeNtk8x6K1C463b7BoX5i4z8pttujpe+9KWJQKHO35TdTU3EQqCfCCBU2NhPt4tae4gAQoUeuhkDXEoVocJVn5gjqy1PQRZk7o8/i9H3qF0M3pL02evE4tz8la7/IncJseFpv2tpfM7RX2bXgXF8Q9sbfC0+sVhCuX5MZwg2rSO1WYGCfTPXgh8uNnfdYd+gsOFF7eroLG9QOOOMM5xA4WUve1lHOQiCAAQgAAEIQAACEIAABCAAAQhAAAIQqEYAoUI1TnhBAAIQGHoCtQgVhGL2uUNuJ3mEOb+3WeKKbBKSt2saGyOPYopECuLSjlDhnX/j36igqfPn6JFPdry84zheywOjePN40dATWbc8cIo3jxfVV2abyLrLampldw/Ywnc1851sFTjB/RPJWsbulNVY171l4xaz9AvLzW/v/13lO3TooYeaW2+91eyzzz6VY3CEgBJAqKAkOEOgOgGECtVZ4dmcQFWhwogVKuimLfm5x61H5OcYeyRrE7F7J98RPsUWXDP9sW8cpnYXF3WoXZP7Lptbk2uHPce+2hY3bTvXEJixhRz53LJhzL1BwQoU1r4wGrw6O4lA4bjjjnNvUHjVq17VWRKiIAABg1ABoQL/GHRGAKFCZ9yIao9AVaGCW0m6tZz9cH/8WUZLVpBiKljwic12uSPuz7aDgz2p3cW1sQ5MM6Q5xJbki9rWmLhrf2JwfnKVrl9F+HqrfUPXooXLuhYobL/99olAgb+fi6nThgAEIAABCEAAAhCAAAQgAAEIQAACY0cAocLYsSUzBCAAgYEiUEmo8OGZZsYpR6bzbiIgSJxin/QZRVPxQUOsiwvB8c78snzB7oQKX1+ZpCtrTJk+YloJFTKxMqd47EynvdA5N/PJx+Sv68gR56ySr9W84nxFbR1D+rqZe5y7VU06Zjfj1ZEjrlna/Vh3FQ5VfPIs8td15IhzjgHrTes3mbs/t9Q88dMn45GatmfOnGluvvlms9tuuzX1oxMCZQQQKpSRwQ6BcgIIFcrZ0NMegapChbF4o4Ksm3V7WbSnK930pZvPSjaSaUx+E1h8nWkLGs0Z2ukpu6j2uSeZDevXm4W3LzW3L7i7FoHC8ccfb6688krzyle+UobmgAAEuiCAUAGhQhdfn6EORagw1Ld/3CZfVaiga0G3wV/XhmFZlvaFNWO0XHPNzLouXVe2s8bUPDGYrtaYPqFLp+vJfG5Znz7/vLxBwQsUXnyxu3+fi0DhzDPPNHPnzuUXiMSwaUMAAhCAAAQgAAEIQAACEIAABCAAgXEggFBhHCAzBAQgAIFBINBzQgXdzKxw9enIeAoV8hug8zVJbdHDIVdq3iffr/OJz63GqZKj23xx3VXGU3/11WutQ+163eqcZyD+rXK26i8aU2O0Pr1WX7XrdauzxOdjWuVs1V80Zn6cTnLEeTvJ1+6Y6q989FrrULtetzrnaxb/Vjlb9ReMueH5DWbRX99jVv3q2YLeYtNRRx1lvvvd75qddtqp2AErBCoQQKhQARIuEMgRQKiQA8JlxwSqCBXmXnGeGZkS/bfe/nzifkQJP6ckSxuxayWlbe/gPIOztjVWxQVydrbwEYazCaxdncN4cUxaQtbJp/E23xbPfC5/vX7dBnPnHUvM7bfeY9au7f4NCieccIITKBxyyCFaHmcIQKBLAggVutvY2iV+wvuYAEKFPr55fVR6FaHC1Z+4KDsjWfvJIs8v1/Rkr61dPUvb3sF5JvF+XZeG+o50jRnypsm7X2MW5tJxjXl+9RqzYP5is/jOe023AoXJkycnAoXp06frNDlDAAIQgAAEIAABCEAAAhCAAAQgAAEIjCMBhArjCJuhIAABCPQzgWpChTfaNyoc4aeZ3wCsk5dnDvk+fThh7dLlLiObhrZ91hxxoI5t+9p6o8Jn3hFnce2tVhShm30aOjsyJLPPRov4IplL0sj6JFc6QTUU+JcMoxGlZ1dHQb6ygI7rbmOMzNidTixN4u9peh2Bj41RO+bdWHdvfkek/OZ1p/8gRlOt0hzw78joM6Pmrk/fbZ7/nzVVaDifY4891vzzP/+zkU3mHBDohgBChW7oETusBBAqDOudr3/etQoVbHnJzxDRJrLEJuVHy0q1O1OBv9jVR3aN2T/uSGz+MmPTPj1HLhk/uSjKt379BvsGhSVm4YIlXQsUttlmGyMChSuuuMIgUMjfCa4h0MghyvgAAEAASURBVD0BhAoIFbr/Fg1nBoQKw3nfx3vWnQsVbKVhkZYuG4vXgZn1Xupsw/2F+7Rt7UrseVtw0P6Yldry59hH2ml/2qM2sbg3KNyyyCxetNxs7PINCiJQEL6XXHKJ2XvvvdMBaUEAAhCAAAQgAAEIQAACEIAABCAAAQiMOwGECuOOnAEhAAEI9CeB6kKFI+0e6HgTdDRffeIRd6vNusVh4VmJD479o3Qtm1HujG/I54QK81ZmuooupkwfMe/866OSB0DiIxvQdTN3/EAlE68TykzGBXu3jD3NZwfy/c7k7RnXzEU8YsgRm1yqonzWFsyxu2sX1a02cYjHV3vGJmhsLeLqPsNH7BPbNUdsi32Vg+13j80ySUOQ5nB9kUNij2wSUmDP3NOQ1k8gF6t9mkOv5RzVnckX2WP3ojpcv+bOxIX7G89R2Qhua08qzcTFI4YcsalZvrI8RfWpTXLHcWovGSd2zcTFNcr3SeYYH3Gg6/YOpd8RzRHXIfmS+hJ6fpScXcQJd316sRl9Zl1cRdP22Wefbb74xS+al7zkJU396IRAFQIIFapQwgcCWQIIFbI8uOqcQFdChbBIS1Yadg2TLkfSTWGyDkp9fK3xukbb6qM/g8g5ky84qH88a7XFsXG/tv0yyyfStpzXrVtvFt621IoU7jGja6uviTRvfBaBwoknnugECgcffHDcRRsCEKiRAEIFhAo1fp2GKhVChaG63RM22a6ECk3WmGF1mPz9XFgeJn9xqGtCmbi0/XrPY4jXiS7OfuT9Zej48DFpHs0R+0hb7el4Pma1vEHBChTuXnxf1wKFHXbYIREo7LXXXvkSuIYABCAAAQhAAAIQgAAEIAABCEAAAhCYAAIIFSYAOkNCAAIQ6EcClYUKJ4c3KhRNUh9ixBuO1Sb+brOxD0weWMS+RTlb2eL84hvla1uoIE9hJJ+rMxTrTMGutbgxooGcXQLlqGJXX/GOx/EZ/GeVMYO/wnSp4nytcqR1ZOtubleRgowee3Zad7LhPySMH465nA6p+/BDZEYtshfZAuuCDG4W8USS8KQRouRkHcXXdiX3TqxyDxpy5OPVoYo95IvHyQ2R1CJlyeHS5nP7ruSJZEO+XNKGHFpzMoAmTDiEgVN7aOn3JM7gu1qNGRLIKf5uJ8ICGbpVjnjUmEmRfZJZ9atnzaLP3GM2rNkQDd68eeWVV5prrrmmuRO9EGiDAEKFNmDhCoFAAKECX4W6CLQtVAhrFLeyCB/eZC/8H79WklVL6uTK1Uu3nhGL83fWZOnjzDqGPfuYrE8Sn8uhSXTckEa8kiO1SX2TzLrR9ebOO5aYO25bYtvdCxQ++MEPOoHCQQcdlIxJAwIQGBsCCBUQKozNN2vwsyJUGPx73AszbE+o4BaFrmy/9pOmrNX82a8ZnUmstst1SKc7UrdgFxfxs0fsmooJQq/t1FjnG2J8YJpDk0guzeF8og8/js0XEq5+7nmzYP4ic8/i+2sRKMgvDLn44osNAoUIOk0IQAACEIAABCAAAQhAAAIQgAAEINADBBAq9MBNoAQIQAAC/UCgilBh1uyZ5rWn2DcqtHP45yE+It4v3CyHxFT0Fbd4iDhtLUIFSVg2gNbo+tXJGnNF+R77mdh1C3f0sMd2unSJTzwTLcHmkGRhw7ac3IMf//TH5Y83zzet2xXlPsJANllubN9rPxN7vu7mNUviJIc0tG61h7ozQoU0SFrZI6nDZ/Wd2bqT8cRXjkn5msXYRt3+rqQIZEZuLiFLMo7kLTka6g41i3uYSqZud9F+3UkOaShrO5Q+HGyr7oaapdhQtx9IDKF8a0j883W3wTquW3PH3+0wp2hg18x8JHVERZbVvdX7PPHvT5i7/3aZ2bR+UyZV2YU8jP3c5z5nLrzwwjIX7BDoiMCwChUee+wxt5m1GbQDDzzQTJ8+vZlLpm/Lli3mV7/6ldlvv/2McOWYWAKrVq0yO++885i8feawww4zb3jDGyZ2gl2MvmzZMjNr1qymGa677jpz3HHHNfWhs3sCbQkVdH1ih01WHNbm2tInf9IO204uXKHuSv0lR9QfNRO79Bf5hBF9zmxgsMlJN4o5U/Kh7qNWoHDXHfIGBREorE/6O2lsu+22RgUKr3jFKzpJQQwEINABgWEWKsyePds8++yzpdR23XVXc+ihh5b2F3XI343Jv8/22GOPom5s40hgw4YN9k0/69w6ciyGPf300428/adfjz/+4z82CxcuLC3/8MMPNw899FBpPx3jQ6AtoYIu0GxpyeoxXgdao7q4daBehKl0s8aMU3W6xoxzrH7OvkFh/mKzRN6gsLHa37eV3ZEdd9zRqEBhzz33LHPDDgEIQAACEIAABCAAAQhAAAIQgAAEIDCBBBAqTCB8hoYABCDQTwSqChVmWKFC8rCkygRjZ9lE3OpQ/7xvgT120e44fTtChaP/+ijZxuOfBNnEbnt1PECcuLCtFRQHxQ95kq3cbrhozHgjdn6MvG+0+brzurVmGazNusPTpwaRQTt1V82Rz5n5BjbWXYm18mvIHQzCW5+w2fuit8bZBJsdlu+IZ1XKu+r9bfbdTu6B5a03oeyeZezNv9u+d5L57/t/Z5Z9abnZsmlLJrrsQjYxXHvtteakk04qc8EOgY4JDKtQoWNgBEJgAAggVOidm1hFqHDJFeeaKVNGfNF2jRKvNmTXmLuWtYv/43+usBeJPUzXL2+ieOfvvJLNZ+Kqa1E5a4y3h0SaOxj9OFGfT5nkSXqsfdS+NWHhbUudSGHduu4FCieffLK5/PLLjQjLOCAAgfElMMxChfElzWgQ6C0CCBV6636UVdOJUCEs4XxKtw7URV2yvExXgX6R6Hx1vZjE24auOCO3ZG0YrzHj/jTKprUdLl+UVH11rSqDq+25Z1dbgcLdZund9g0KNQgUzjnnHPcGhWnTprk58gEBCEAAAhCAAAQgAAEIQAACEIAABCDQmwQQKvTmfaEqCEAAAj1HoKpQoe03KshM9WFG457yRg5lviV2Sald+WRtCRX+z1E+XJM1q7VoUPXX+Hwxcq0+2ie+9v/yyCfZhF2UW/3lrPmLcuVtcZz2abz2tRpP49Q/xOvDqEp165gluRq46FhyLquvzK6xJWNJ3YnAoFWOuuvWmjSv1hqf1Udt4mv/39PfEak1rjvMr63viOSQuDiP2uSct4tND+kLY6rJncvswelXd/6n+dG8B83WLc2SpxknT55srr/+enPMMcekRloQqJEAQoUaYZIKAn1CAKFC79yoSkKFy61QYaoXKug6J5lBsonLLdzSpUliF0+7okvWLGHTlze7NK5L/cU7OMs5ExflSMIzPi6dZEjiNJe8QWHhbfeYRQuX2d9S3b1A4ZRTTnEChQMOOEAH5QwBCIwzAYQK4wyc4SDQIwQQKvTIjWhRRhWhwlXXzMms+zIp3RovLP7sSZeBurbzhmjNl3jYLElY2i+5NTZeY6rNj+0D/fozG6v9ujbVuNXPPW8W/HCRWXL3j8ymTd29QWGnnXYy5557rrnooosMAgVPnE8IQAACEIAABCAAAQhAAAIQgAAEINDrBBAq9Podoj4IQAACPUKgilDhzbNnGnmjQl1Hi33Eyd5kfQjTclxxjPYcVxYq7D1ijlahQstBZIit9llPtiodNmv1vpIy9ncb5dWmASFBUe4KJbV0yYwZeZfdg6I6Mrao7ow9yl1Hsyx3Ud3iK0fMWq6THFqzN6Z2ua75SMaM8oZbnPvmtPEdkVw2SVHuaJiOm+X8kmebmdxFdWRyKO8xrFkKKqrD2xvr1voeuekX5qF/+6njmZlUycXOO+9sbrjhBvOWt7ylxAMzBLongFChe4ZkgEC/EUCo0Dt3rBahglv7+AWQbt4SpYAuiVw7XETWZMHiw9Me3fiV3ySmdg3M98dU1de/QWGJWXTnMrN+3YbYpe22/PdKBQr7779/2/EEQAAC9RJAqFAvT7JBoF8IIFTojzs1VkKFeI3p1nsdrjF1rSjrSr+mFK4+WZU15nPPeoHCsiUrahEonHfeeU6gsMcee/THDaZKCEAAAhCAAAQgAAEIQAACEIAABCAAAUcAoQJfBAhAAAIQqERgvIUKumlbigvPUhrqVJ+y/kxA7BQC2xUqJG8HkJrSpzOZYcp81B7H6aZol0Ank8mWHUdzCJB0i1IakPRbU2acrWny2J5G2v3YwSfuV5v4ZeyyG16PqKmmjG8bY0t8UWxs0zHkXFpfyZiteMfjlOUuGr/TOMlVFJuxtWBdliNvl2s5yuZVZvdR/lN9MvV1yDr+Drv7Er5Hce6iscUW+xTV1E5cUb4fX/cT8/Mf/kecpml7r732MvPnzzdHHHFEUz86IdAtAYQK3RIkHgL9RwChQu/cs6pChRH7RgX3Y4f9WcGfZQ7+BxHdzOXXQWL29sQjEyNWibQ+wc2d1Ef6Qrw/pZvH0hgfmO93iUPutaOj9g0KS8ziO+8169d3L1A49dRT3RsUXv7yl+swnCEAgQkmgFBhgm8Aw0NgggggVJgg8G0O27FQwS8M3Wi61kuWjWGNKJ2Z9aNfGlpb0vDxzjGxlqwxQ3/BuNFwIfMk8+yzz9k3KCw29y59oGuBwsjIiFGBwu677+5q5gMCEIAABCAAAQhAAAIQgAAEIAABCECgvwggVOiv+0W1EIAABCaMwHgLFWSisnc5PDopnLfukW/mkwkURw2yzbaECp8+yoamwekGoHQE3TStFt08JGGZ2PAEJ7GlaTU0OSfj5HMoGZ18rl8SSGwyRsiY5EtGyG1el7yBU0OsrTtja1a3zjHayK41uaFD3Q3MQmc8Tquak7wFdWtsnE/uR9GhvtKf8bfOrk+CSuv2HXFcki8arGG++jQvN6Z+d5J8JTX7kuzYZXPXsZvUnYwRfFvVHfcXzSeTr1ndHX5HdM6ZcaxRmemU8/cxqTvH2uWztWzZvMXcf+0D5td3/1eSolXjgAMOMAsWLDAHHXRQK1f6IdA1AYQKXSMkAQT6jgBChd65ZZ0IFWR9lqw/7FTCckwWLb6t60DtU7tMO3EWd3/hPiOfxO47JEpS+zHDRQhNcjiz9XjhhVFz5+32DQp33Ws21CBQOO2008xll11mECgIYQ4I9BYBhAq9dT+oBgLjRQChwniR7m6cqkKFzPpR13tuDRgtG2WdqIu/UJZfJoa1p9hCjGsG37yP5vDd6brV+/kkOoz6BqtZtUoECovMvcseMJs3bRZzx4cIFM4//3wzZ84cg0ChY4wEQgACEIAABCAAAQhAAAIQgAAEIACBniCAUKEnbgNFQAACEOh9AvUIFXTXcvRUZBynrqPrkMv+frlZMW+lXpaeR/YeMUd/+u2Z/ugRj7PnN02LMfYp6s8kDP55v3Zz5HPmr1vla9Vflq+s7rw9H1/lOq5J/Ityxj5F/flx1D/2VVvZGPkcra7jfGU5Y5+4lrLc4p/3azdHWW61t8rXql/zxOdmdefnE8e1025VV7P+zRs3m3u/dJ/53QOPVR7y8MMPd29SmD59euUYHCHQDQGECt3QIxYC/UkAoULv3LfahQrpTi83yfwGsfY2kaU/W8lmMb1yG8fChW4iW2sFCu4NCiJQ2PBiV4C32247c/rpp5tLL73U7Lfffl3lIhgCEBg7AggVxo4tmSHQywQQKvTy3Ulrmyihglsx6jpR/gZbF5C2NF03JmcpV9eY1i8TGwJXPfOcuW2+fYNCDQKFKVOmJAKF3XbbLYVFCwIQgAAEIAABCEAAAhCAAAQgAAEIQKBvCSBU6NtbR+EQgAAExpdAvwsV8iIFodeWUOFTVqgQP7SJLso2Wus2obL++A6qr9hi/0J7PJmopjif/Db55Ih8CvMljuFhU7iO64hcMs2yfGrP5CipKZOwxKcwXxSo/WLKjBn5xE31j33V1pCjpKYkX0l/ab4ksD3eZfnK7Ml3ILr/0dACKj0in9J8wbtVf5rUt8r81R7fg7KaMjlb1J3JFwXqeGKKfTau22iW/N97zZOPPBV5N2/OmjXL3HTTTWaXXXZp7kgvBGokgFChRpikgkCfEECo0Ds3qqpQYcrUEV902LTlT36hlbTtZdIOU3Qe1pgsyULDWcQ/9Pg4HcI7JZvIQqez5nKpQOHuRctrESh86EMfcgKFfffdt3duEpVAAAKFBBAqFGLBCIGBJ4BQoT9ucRWhwtWfuMhPJloI+qauBaXbLRgrrTF1XelD4hw6jNpyZzdMEu2GXPW0FSjcutgsX/ag2by5uzcoiEDhggsucG9Q2HXXXX0xfEIAAhCAAAQgAAEIQAACEIAABCAAAQgMBAGECgNxG5kEBCAAgbEn0O9CBSEU72+W626EChIvj2biDc9iyx9VfDSmzLfBHk/EPzPSFP4c94sl59OQLxtdaV5xSKt8zrdFTa18qoxRxUfrLvNtsLdbd5uspZ6GMbXIgnOZb4M9rjtXk0sb94sh59OQL1dLq/6ce+kcM3la1ORyNvGRXHI0+2cyM5713fD8BrP4s0vMs79+zsVW+Tj66KPNd77zHbPDDjtUcccHArURQKhQG0oSQaBvCCBU6J1bVUWoMPeK88zIlJ3suipdWCUtEQ64C/shf9KOdBkmPmHKKj6Qy2w7ZaL20rN1XbNmrbnz9iXm7sX3mRdreIPCGWec4QQKL3vZy9JCaEEAAj1NAKFCT98eioPAmBFAqDBmaGtN3LFQQatwa8ywgixZY+paUULK25ow9RHfIn8Z7ZlnnjUL5i8y99/7464FClOnTjWzZ882F154oUGgkN4HWhCAAAQgAAEIQAACEIAABCAAAQhAYJAIIFQYpLvJXCAAAQiMIYF6hAplBeruY92a4/22bt2aeSBSFi324gzNIoxZ+vfLzYp5K5s72d6RvUfM0bk3KrggHbRlhvYdZLN1ulWpSXwWWQoiDol9xrhmGbbtustqGse6K9XsJ5eSLao7rlk8i3zSDF21+I5YfDHvNlmvfXrULP6be8yax1+ofB9OOOEEM2/ePLPttttWjsERAnURQKhQF0nyQKB/CCBU6J17VYtQQaYjCgX5k6xh0lVovBHM+ehCx4X4gExcyFG0iWzN8y84gcI9i+83L774Ylcgt99+e6MChX322aerXARDAALjTwChwvgzZ0QI9AIBhAq9cBda19CJUCFZRkp6JyZwjcwaM11hiksUYZtJX9ROXWxvcC9aYz7ztBco/Gh5PQKFD3/4w06gwBtLW39X8IAABCAAAQhAAAIQgAAEIAABCEAAAv1MAKFCP989aocABCAwjgTGTqgQ7y5OH5yISEGPzAMVNebO6p1myDkUXLYtVJAcOoAOWJC3W1P8G+GTh0fNkraqqVV/s9xt9LVVt9Yk+ctYqk9Zfxu1lbm2VbMkqVJTFZ+ygiraa697HGqWqbVVt9bkA4vJqE+b35HVv3veihSWmHXPrivOW2A9//zzzec//3nzkpe8pKAXEwTGngBChbFnzAgQ6DUCCBV6545UESpccsW5ZsqUEbdebFjDyyYymY7s/JI//sJN0DVdV2ipQWzO2bm5diZO3SW377BvUHjBLLxtiVl6twgUNvrADj9FoHDmmWeauXPnGgQKHUIkDAI9QAChQg/cBEqAwAQQQKgwAdA7GLKKUOGqT8wJa8KGFaZbVCbrQ7s21Ha0nEzWibKs1KPdNebTT68yt81fbESgsGXLFk3T0XnnnXc2KlCQNgcEIAABCEAAAhCAAAQgAAEIQAACEIDA4BNAqDD495gZQgACEKiFwNgJFaQ82WUcPS0JFffcGxVCXeNx0g3dBY+gxmP4jsfox7r7sWa5QdTd2df0mV+uMnf/7VLz4gvVf7vw1VdfbT7+8Y93NiBREKiJAEKFmkCSBgJ9RAChQu/crO6FCpHoIBIWyAz1pyAnNtCLaOoqQtANZfrzQdAmuM1nL6xZaxbeXo9AYfLkyeass84yl1xyiZk+fXpUCU0IQKAfCSBU6Me7Rs0Q6J4AQoXuGY5HhvaECmE9GRdm1466VhSVgrbjJWU3a0x5g4ITKNzXvUBB3pogAgX5PwKF+CbShgAEIAABCEAAAhCAAAQgAAEIQAACg08AocLg32NmCAEIQKAWAu0IFfRtCPpwpJYCQhJ90YJuzMnndr9YPTi1Gr+TNyro3PLjynV+PPXN2+PYxCfZoiSJUo+kv2zC1lV90qhsLW5De5PfOJ+vT/Pl7Zo/6Y8LjWsW4UkYrzRH5KN5877t1K01Sa58Hs2vPrq5y9nHom79kurA0Vk3mKkpqanC/S2tu8L3XcfRceUcc2qHtcRqvjiH2PVI+ku+I+KX+FSYu+bNj9dO3TLeEz990iz9wr1m04bNmrLpWd6eIG9RkLcpcEBgogkgVJjoO8D4EBh/AggVxp952YhVhQoj9o0KsrRpXLdZi647bcM1g0HN4pD4RIXo+sdFRbnF9/nnXzB3WoHCsntWmI0bu3uDgggUZLOcCBT23nvvqAKaEIBAPxNAqNDPd4/aIdA5AYQKnbMbz8iuhAp+QZmuH2UtKcWHBaVrh+tWa0zf7yOk/fRTq8ztt95tVtz/UNdvUBCBwoUXXugEClOnTh1PvIwFAQhAAAIQgAAEIAABCEAAAhCAAAQg0CMEECr0yI2gDAhAAAK9TqAToYLMSTfW1DW/eA940UMW3fxcZex2hQpx7rL56HzzvmqP42Kf8CjJd+uTJLffP1UYtMoR59aNTF4PkOaIfeK25m6oSWtR53xNBRvR4xwSprk1hZzzPtqnvmX96ifnsjlqjtg3zpdh7RM514xP4ZdL9BfFLHXMOEc8ftxW3/y9SeyRc5wvU7fel/z9KKg7zhGlLuUX+8RtrS/Ol9yD2DFfU498R35z32/Nff/wI7NlU7VX1G+77bZm3rx55oQTTohnRxsCE0YAocKEoWdgCEwYAYQKE4a+YeBKQoXLzzUjU61QQaLtmsyf3YUsXMOKyDdcX/ALHrkYsfpD1mDqr+ux559fawUK95h7l4hAYZO6dnTeYYcdEoHCXnvt1VEOgiAAgd4lgFChd+8NlUFgLAkgVBhLuvXlriRUuGZOtE6sZ43p1pbJGtPmDIvNp55cZe5YcLd54Ec/6VqgsOuuu5qPfOQj5oILLjAIFOr7zpAJAhCAAAQgAAEIQAACEIAABCAAAQj0IwGECv1416gZAhCAwAQQaEeoIOXpZmbdTFNXya2FCulI+pAltWRb7QgV/vSTf5INLrmSx0Wlm9mTLUaNG97T7Uc+cWmOaFLKuKQUO1p5LfmYZr5xbfm64j7Jme/XceLvQau6NabVWccuGlP7JEe+P+7TMfI+Yh+Lml3eJvclri1fU9xXV92SMz+O5s6fm/nGteXzxX2SM9+v44wFbx370Tt/ZR785x8n/17SMcvOsmHvO9/5jjn66KPLXLBDYNwJIFQYd+QMCIEJJ4BQYcJvQVJAJ0IFu8yyf9yHy6PrErlIl/RRvzWGPWISGGK8s9rX2DcoLLRvUFi+9IFaBApnn322ufjiiw0CBc+bTwgMIgGECoN4V5kTBFoTQKjQmlEveHQiVPDLy2gNqQtHO6FkjZk0xNZ6jenfoLDYPLjip1agUPxLWqryEoHCnDlznEBhypQpVcPwgwAEIAABCEAAAhCAAAQgAAEIQAACEBhgAggVBvjmMjUIQAACdRJoV6igY+um9HgTsvQV2dXmY3U7TvSQJYqT3TvRMxebL0SlYYnN96QPWbSWqkKFnabtaN7xv61QIcodPeLx6cOn24SdDhWKyrjITu0Ge5wvs5G7wDeXrTCf85HYqGaxxeM4n/CRZR+MuVhXd84W56ul7pL5xuNo3ZVYi3OOQz5XW3WX1NfqnmrNvhybRPNoR45r0h/Z47rbqtkP6keK8jlDjo3Y4nF8kP/sme+IlFOxbqn54Rt/bv79hkfiqTRtyyvpb7rpJjNr1qymfnRCYLwJtBIqyGbTv/u7vxvvshgPAhAYQwIiVHjrW9/adITrrrvOHHfccU196OyeQEdCBTus/3nFLsDcn3QhFv8cI06uR89SbnB1Pbb9/Oo19g0KVqCw7EGzqcs3KOy4445GBQp77rln93DIAAEI9DSBKkKFX/ziFz09B4qDAATaJ/Anf/InZuHChaWBhx9+uHnooYdK++kYHwKdCxWkPrtIdH/CwlEs2gwNd9lkjfnUE0/bNyjcY1Y+0L1AYbfddnMChfPPP98gUBif7w+jQAACEIAABCAAAQhAAAIQgAAEIACBfiGAUKFf7hR1QgACEJhgAp0IFbx4QHdk2202+rDEzkU3PatoQKanNj/V1LkwLjyMcb52iGSUNKw2oYKvh08IQGDQCUyfPt3Mnz/fyAN7Dgj0GoFWQoVeq5d6IACB8SGAUGF8OHcsVJDy/A4x+7NQ+oNK1Ezt1ph42IZcrX7ueXPnHUvNfffWI1A455xz3BsUpk2bNj7gGAUCEJhwAq2EChNeIAVAAAITQgChwoRgbxi0I6GCzRKWl65VuMbMrCsb15hPOoHC3ebHD/6s6zco7L777olAYWRkpGGOGCAAAQhAAAIQgAAEIAABCEAAAhCYeAL//d//XfhLD4866ijz9re/feILpIKBJ4BQYeBvMROEAAQgUA+BdoUKqegg2W6TESq0U5W+LUFikk09qkzQROkwaik9S23yEKfqGxVKE9EBAQgMDIGDDjrI3HrrrebAAw8cmDkxkcEigFBhsO4ns4FAXQQQKtRFsnmeroQKklo3i4UfZpKfaYIgwbukP9CsDm9QuF8ECps2Ny+uRe9OO+1kzj33XHPRRRcZBAotYNENgQEkgFBhAG8qU4JADQQQKtQAsYYUXQkVZHxZYyYLy/TvzbO2dI3pBQr3mIdW1iNQkPWlvEFB1pscEIAABCAAAQhAAAIQgAAEIAABCPQugfvuu8/MnDmzocCPf/zj5uqrr26wY4BA3QQQKtRNlHwQgAAEBpRAO0KFVKQgMNKHIdFzk7YoFQoVJIOKFdIhKuXV+pZ94T6zYt7KSjE4QQACg0vgiCOOcG9S2GuvvQZ3ksys7wkgVOj7W8gEIDAmBBAqjAnWhqRVhQpTpobfIht+8HE/poQPb7IX/k/yY1LyO26tffVza8ydty8xP1q+shaBwnnnnecECnvssUfDnDBAAALDQQChwnDcZ2YJgXYJIFRol9jY+FcVKiTCg4przHh9KZU/+fjT5o4FIlD499wbjdufl6wrRaAg60wECu3zIwICEIAABCAAAQhAAAIQgAAEIDARBBAqTAR1xowJIFSIadCGAAQgAIFSAp0JFdyunCRnt0IFl01TqkhBsqstGam84UUPPhihQjkneiAwLATe8pa3mBtuuMHsvPPOwzJl5tmnBBAq9OmNo2wIjDEBhApjDDikryJUmHvFeWZkSvTbZO0PPw3iBMkndnf2yWXj2XPPPh8ECj82mzd39waFkZERt3FMNpDtvvvufhA+IQCBoSWAUGFobz0Th0BTAggVmuIZt84qQoWrP3FRtp4Ka0y32rQLzicee8oKFO42P/nxI10LFOTNXB/96Efdm7p23HHHbE1cQQACEIAABCAAAQhAAAIQgAAEINDTBBAq9PTtGYriECoMxW1mkhCAAAS6J9COUKFstFgk4H2KFAZbM6+sbsgVCxS0M5dG3piQ/KYp9bHn9M0MCBUiLDQhMLQEjjnmGHP99debyZMnDy0DJt4/BBAq9M+9olIIjCcBhArjQ7sroYJXK6Taavuzi/6s8tyzq81ddyyzb1CoR6Bw/vnnu99wu9tuu40PGEaBAAR6ngBChZ6/RRQIgQkhgFBhQrA3DNqVUKFhjakiWWMetwKFhbfdY35ak0Dh4osvNuecc45BoNBwCzFAAAIQgAAEIAABCEAAAhCAAAT6ggBChb64TQNdJEKFgb69TA4CEIBAfQTqESq0Uhmk/bp5p2EGqYvZav8nR+wrIgU9sna1ytn78EaFmAltCAwXgZNOOslce+21ZpttthmuiTPbviWAUKFvbx2FQ2BMCSBUGFO8SfIqQoVLrjjXTJkyksTYH1LkT/oGBe2xxudWWYHCwqVmxX0Pdf0GhSlTphgRKMyZM8cgUFDInCEAASWAUEFJcIYABGICCBViGhPX7kSo4P6+u2GNKUpYeYPCk+YOK1D42UM/7/oNCnvuuadRgcIOO+wwcZAYGQIQgAAEIAABCEAAAhCAAAQgAIGuCSBU6BohCbokgFChS4CEQwACEBgWAuMjVBCajeKDDONUh4BQIQOGCwhAoCqBCy+80Hzuc5/LiJyqxuIHgYkigFBhosgzLgR6mwBChfG5P1WFCiNTdrJ7xGTnWBBTy56x8NtuZffYs6ues29QWGoe+JEIFLZ0VbwIFGbPnm0+8pGPmF133bWrXARDAAKDSwChwuDeW2YGgW4IIFTohl59sVWECld9Yo4bsNka87H/edLcebsVKPzkkeiNwp3VuddeezmBwtlnn20QKHTGkCgIQAACEIAABCAAAQhAAAIQgECvEUCo0Gt3ZPjqQagwfPecGUMAAhDoiEAVocKs2TPNjJOPDPm3Jpt0kgH9nh3VIiTmsJcnvbat+M0I2uEeyGgONeZ8041AcY7w20yjGGku/fvlZsW8lTkrlxCAwCATuOaaa8yVV145yFNkbgNKAKHCgN5YpgWBLgkgVOgSYMXwboUKq57xAoUHV/yka4HC1KlTnUBBhJcIFCreQNwgMMQEECoM8c1n6hBoQgChQhM449jVuVDB/133Y//zhFl42xLz7z+VNyh0V/jee+/tBApSEwKF7lgSDQEIQAACEIAABCAAAQhAAAIQ6DUCCBV67Y4MXz0IFYbvnjNjCEAAAh0RaE+okD4Z0d/25AZVkUHa7V5LXVRQkVBB/GIhgsbFvnF/mV3jqggV5LeUbrPNNhrCGQIQ6GMCM2bMMCeeeGIfz4DSh5nAxRdfbLZs6e63bw8zP+YOgUElcNJJJ5kjj1Sh8KDOcuLnVVWoMGXKSFKs/FyyatVqs2jhUlOXQOHDH/6wEYHCLrvskoxDAwIQgEAzAl/5ylfMz372s2Yu9EEAAkNIYPr06ebSSy8dwpn31pSrChWSv1+360v56/X/CW9QePhnv6hFoDB37lxz1llnmcmTJ/cWIKqBAAQgAAEIQAACEIAABCAAAQhAoBYCCBVqwUiSLgggVOgCHqEQgAAEhonAmAkVBKIKGCKg/rdAxYoG3xkLEdQ9I0iQZJLPhvpo+QyPc3LjVBEqjI6O8pBGQXOGAAQgAAEIQAACEIDAEBKoIlSYe8V5ZmTKTu5nkVXPrDZ3WYHCyhU/7VpktvPOOxsVKEibAwIQgAAEIAABCEBgMAhUESpc/YmL/GStSOF/fve4ufP2JeaRf/+PrgUKIlYRgcKZZ57J330PxteJWUAAAhCAAAQgAAEIQAACEIAABEoJIFQoRUPHOBFAqDBOoBkGAhCAQL8TqC5UOMJO1QoDErGAlws4qYAKBZyIwNtTLtrpLS7eNmMRgvQEyYFzSjOkreJ+t1/IxTgRg28ZhAoBBCcIQAACEIAABCAAAQhAoJRAVaHCixs32jcoLDMrH/hZ1wIFeWuCCBTk/wgUSm8NHRCAAAQgAAEIQKBvCVQVKohAYaEVKPz84Ue7Fijss88+iUBh++2371t2FA4BCEAAAhCAAAQgAAEIQAACEIBAdQIIFaqzwnNsCCBUGBuuZIUABCAwcATaESrEbz2IhQZqj21ZUKlYQYUK0h/7FwsR2hAqSMIwDEIFgcEBAQhAAAIQgAAEIAABCDQjUEWo8IqD9zf/+cvf1CJQ+MhHPmJmz55tpk6d2qws+iAAAQhAAAIQgAAE+phAK6GCTO1Vrz7I/PyR7gUKL3vZy5xA4YwzzjAIFPr4S0PpEIAABCAAAQhAAAIQgAAEIACBDgggVOgAGiG1EkCoUCtOkkEAAhAYXALVhQpH+rcpCAqrH/ASAv/ZllBB4kVQkMsRv1PBZxVHOcIYqkJILK4zsvprMSBUCCw4QQACEIAABCAAAQhAAAKlBKoIFUqDK3bsuuuuRgQKF1xwAQKFisxwgwAEIAABCEAAAv1MoIpQodv5iUDh0ksvNSJQ2G677bpNRzwEIAABCEAAAhCAAAQgAAEIQAACfUgAoUIf3rQBKxmhwoDdUKYDAQhAYKwIVBEqvHn2TDPjlCMzr6BO35EgUgKVFsRWKz0Il+mbE+L3JqgEQWeW5tC4JK11SccIkgbJbUN8lMb6XMu+cJ9ZMW+lJi48j46OmsmTJxf2YYQABCAAAQhAAAIQgAAEBp/AWAoVRKAwZ84cJ1CYMmXK4MNkhhCAAAQgAAEIQAACjsBYChX23Xdfc9lll5nTTz8dgQLfNwhAAAIQgAAEIAABCEAAAhCAwJATQKgw5F+AHpg+QoUeuAmUAAEIQKAfCIyVUCERG1gIqVAhfm+CigyUUio20Dc0lAoVouRxbs2EUEFJcIYABCAAAQhAAAIQgAAEygiMhVBht912SwQKIyMjZUNjhwAEIAABCEAAAhAYUAJjIVTYb7/9nEDhtNNOQ6AwoN8bpgUBCEAAAhCAAAQgAAEIQAACEGiXAEKFdonhXzcBhAp1EyUfBCAAgQElUFWo8PsnH9lAQN+f4N92oFfeLdESuLceRCIEk/qlVonJXmXfvSC9cb/t5Y0KDfcDAwQgAAEIQAACEIAABCBQnUCdQoXdd9/dCRTOP/98g0Ch+j3AEwIQgAAEIAABCAwagTqFCi9/+csTgcL/+l//a9BQMR8IQAACEIAABCAAAQhAAAIQgAAEuiCAUKELeITWQgChQi0YSQIBCEBg8AlUESrMmj3TzHBChVgskLLJiAqCDmGrc/X+cX8qOEit3qsxd+rRKFTQ0VX2kOY1hjcqKB3OEIAABCAAAQhAAAIQgEAZgTqECiJQuOiii4wIFHbaaaeyobBDAAIQgAAEIAABCAwJgTqECvvvv78TKJx66qkGgcKQfHGYJgQgAAEIQAACEIAABCAAAQhAoE0CCBXaBIZ77QQQKtSOlIQQgAAEBpPA2AkVUuFBmeCgzJ6STj1iIYKJ3sqgQgWJUR+ECilBWhCAAAQgAAEIQAACEIBAMYFuhAp77LGH+ehHP2rOPfdcBArFeLFCAAIQgAAEIACBoSTQjVBBBAqXX365EYHCtttuO5T8mDQEIAABCEAAAhCAAAQgAAEIQAAC1QggVKjGCa+xI4BQYezYkhkCEIDAQBFoT6ggU08FCAoilROoJRUN5PtUTKCe2p+3+34vQ5DPdFRppfKEtJWOiVBB6XKGAAQgAAEIQAACEIAABMoIdCJUmDZtWiJQ2HHHHctSY4cABCAAAQhAAAIQGFICnQgVDjjgACdQOOWUUxAoDOn3hmlDAAIQgAAEIAABCEAAAhCAAATaJYBQoV1i+NdNAKFC3UTJBwEIQGBACVQRKrx59kwz4+QjSwkUiQxUgJAPKvIVH/XP9qcyhLSVChLiOGlrLEIFocEBAQhAAAIQgAAEIAABCDQj0I5QQQQKF198sTnnnHMMAoVmVOmDAAQgAAEIQAACw02gHaHCgQceaK644gpz0kknIVAY7q8Ns4cABCAAAQhAAAIQgAAEIAABCLRNAKFC28gIqJkAQoWagZIOAhCAwKAS6FaooOKAPB8VHuTtrfz9mxP0/QmxPCF9j0KcIx5H7QgV8tS5hgAEIAABCEAAAhCAAATyBKoIFfbcc89EoLDDDjvkU3ANAQhAAAIQgAAEIACBDIEqQoVXvOIViUBhm222ycRzAQEIQAACEIAABCAAAQhAAAIQgAAEqhBAqFCFEj5jSQChwljSJTcEIACBASJQRagwy71R4YjKsxbxgIoGWgWp0CDrrwIFFSxks2iMWLNx3g+hQpYXVxCAAAQgAAEIQAACEIBAI4FmQoW99trLCRTOPvtsg0ChkR0WCEAAAhCAAAQgAIFiAs2ECgcddJATKHzwgx80CBSK+WGFAAQgAAEIQAACEIAABCAAAQhAoBoBhArVOOE1dgQQKowdWzJDAAIQGCgCHQsVVEOgmoJARUUERQKCPDj1FXvWX5PaQQrGKY/zIyBUyJPmGgIQgAAEIAABCEAAAhDIEygSKuy9997mkksuMbLBbPLkyfkQriEAAQhAAAIQgAAEINCUQJFQ4eCDD3YChRNPPBGBQlN6dEIAAhCAAAQgAAEIQAACEIAABCBQlQBChaqk8BsrAggVxooseSEAAQgMGIF6hQqphCArPCiGlnq3J1SQbBpbNA5ChWLeWCEAAQhAAAIQgAAEIACBlEAsVBCBwty5c81ZZ52FQCFFRAsCEIAABCAAAQhAoE0CsVDhkEMOcQKFE044AYFCmxxxhwAEIAABCEAAAhCAAAQgAAEIQKA5AYQKzfnQO/YEECqMPWNGgAAEIDAQBKoLFY5085V3HRSJAzwMfROCXOmrELRnUhonXbGru5R+PbSlTnqt/eVnETAs/cJys2LeynIn2zM6OsoGpKaE6IQABCAAAQhAAAIQgMBgExChwuc//3knUDjzzDP5+WCwbzezgwAEIAABCEAAAuNCQIQKixYtMldeeaU5/vjjzUtf+tJxGZdBIAABCEAAAhCAAAQgAAEIQAACEBguAggVhut+9+JsESr04l2hJghAAAI9SKAdoYLKBmQaxWKFrIdOV99+4OK2RqKDyF19fK/6qLVsPB3Bn9UboUKWC1cQgAAEIAABCEAAAhCAQCOBX/7yl2afffYx22+/fWMnFghAAAIQgAAEIAABCHRA4JFHHjEHH3wwAoUO2BECAQhAAAIQgAAEIAABCEAAAhCAQHUCCBWqs8JzbAggVBgbrmSFAAQgMHAEOhEqFIsUBE2kPIjej6ACAvHYqkKF2NVFekM2dxqZtUumxkO9ESo0ssECAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAv1PAKFC/9/Dfp8BQoV+v4PUDwEIQGCcCFQRKrx59kwz4+QjvfRAhAbNRAbyMgTXr7KB8DaE8JKESZOKBAlhsvoiBZ178PWXtjPJLUNMiqQQGuATLPvCfWbFvJVqLDyPjo6ayZMnF/ZhhAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEI9CIBhAq9eFeGqyaECsN1v5ktBCAAgY4JtCVU0LchyGiRWEElCcnbEqQ7EhmU2mOpQV6k4MaIBonGzuQWv+RAqJCgoAEBCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACA0cAocLA3dK+mxBChb67ZRQMAQhAYGIIVBUq/P7JR/g3GkiZkX7AX4a3JJSKCayAQIUI1tW/DUENYd65S2eNxA4ugfokOUKsO2mnMbxRIeZCGwIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQGhQBChUG5k/07D4QK/XvvqBwCEIDAuBKoIlSYdcFMM0OEChmBQnQRCRTUR9+yIJPZmqgU3IWfXxQuBvXP+CbWkhw+U0M+hAoxGNoQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgMCgEECoMyp3s33kgVOjfe0flEIAABMaVQK1ChUh8oMIDmUxGfJC++CAjfCjyL7I5OHGOmFYYH6FCDIU2BCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCAwKAYQKg3In+3ceCBX6995ROQQgAIFxJVBZqHCKfaNC5lBVglUNxMIBNVtfERpkRAoSX+IrXUX+RbZMDgnUA6GCkuAMAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAgNIAKHCAN7UPpsSQoU+u2GUCwEIQGCiCFQSKsyeaWacfIQTEkidXmsQKw5C9QUm1xOJFzIigzJ7SGcHzB6aP2dPxAyhf9kX7zMr5q3MxuauRkdHzeTJk3NWLiEAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAr1LAKFC796bYakMocKw3GnmCQEIQKBLAp0IFWTIhjcleGNxNbGwQMUG4llm1yxl/ZFdRAp6bN3qkyNUUCKcIQABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQGCQCDz88MPmL//yLxumdNpppxn5PwcExpoAQoWxJkx+CEAAAgNCoB2hgigLRBZQKFIQHrEIIeaTagm8Vf1iu9riOGmrj/brdeTn3qgQRApiRqgQwaEJAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAARqIoBQoSaQpIEABCAw6ASqCxWOtEIEVQuUUIlFBLGrteubD1KzbaUXqSDBpQ6J4vEyOaLAqKlVIVRQEpwhAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgEB9BBAq1MeSTBCAAAQGmsB4CBUmTUoVDBldQU6IkIJuFCpkc0RZoqbGI1RQEpwhAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgEB9BBAq1MeSTBCAAAQGmkBlocJJR1TjIBqDAvGACA0y5likIJlTLYO/aNovAfbIJPQm+USokLKgBQEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAE6iKAUKEukuSBAAQgMOAEKgkVLphpZpycFSroGw4yWoG8uKANdpl8RXliIUNm0MZBECo0MsECAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAS6JYBQoVuCxEMAAhAYEgI9J1QoEinIvUCoMCTfSKYJAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAQK8SQKjQq3eGuiAAAQj0GIFOhQql0xBBQYs3HpTGdtqREzHwRoVOQRIHAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAATKCSBUKGdDDwQgAAEIRARqFSrkBAPJMJOijrI3JiTOuYaGlokftN+F+YtlX1huVsxbmUuUvRwdHTWTJ0/OGrmCAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQKCWAUKEUDR0QgAAEIBATGBehggyoYgWECjF+2hCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAoG8IIFTom1tFoRCAAAQmlkBtQgV5mUHZWw/qmKK+OaHCGMu+eB9vVKiDOTkgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgEBEAKFCBIMmBCAAAQiUE6hFqNCGiKC8khY9Ooa4tRArIFRowZJuCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCDQAQGECh1AIwQCEIDAMBLoG6GC3BwVKyBUGMavKnOGAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAYIIJIFSY4BvA8BCAAAT6hUAtQoUemyxvVOixG0I5EIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCAwEAYQKA3EbmQQEIACBsSeAUGHsGTMCBCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhAYBAIIFQbhLjIHCEAAAuNAAKHCOEBmCAhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgMAAEECoMwE1kChCAAATGg0DdQoWtW33VkyZlqxdzzpR1qOlqqy3g3i/db1bMW9k04+joqJk8eXJTHzohAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEUgIIFVIWtCAAAQhAoAmBOoUKKlKQ4WKhQtAuuCrGUqwgIgU5ln3xfvPAPyFUcDD4gAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACNRFAqFATSNJAAAIQGHQCdQoVhJWKFWKhgrPbj7EUKcgYcvBGBc+BTwhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgUDcBhAp1EyUfBCAAgQElULdQoRcwLfvifWbFPN6o0Av3ghogAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQGBwCCBUG514yEwhAAAJjSgChwpjiJTkEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEBgYAggVBuZWMhEIQAACY0sAocLY8iU7BCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhAYFAIIFQblTjIPCEAAAmNMoIpQ4U0XzDSvPfmITCVbt25115MmTcrZ/WXOnPHRi7Ic2i/nKj6xv7SXffE+s2Leyrw5cz06OmomT56csXEBAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgUE4AoUI5G3ogAAEIQCAiUFWoMOOkI0wsPkgEBMYKFVSrYLULXr5gTWqLxso3NYfY84IH9VWfsn71i88IFWIatCEAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAQD0EECrUw5EsEIAABAaeQFWhQv6NCg5MokoImPLXFeiJEGFSLHYoipG8FYQPGopQQUlwhgAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAAC9RFAqFAfSzJBAAIQGGgCVYQKsy6YaWacfEQ5hw4ECg3JWuXQfgmMRAv6xgVnDq9xQKjQQBcDBCAAAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQhAAAIQgAAEIAABCEAAAhDomgBCha4RkgACEIDAcBDoOaGCYI+ECMldQKiQoKABAQhAAAIQgAAEIAABCEAAAhCAAAQgAAEIQAACEIAABCAAAQj8/+zdB5gUVbr/8XfIQxaJJgwYEAVBBVGMGDGhGFCCiKgoouvuuuH+3XXdvXfXvXd3zZiVIAaMqJhBEBUEQUQQFQUMSBQBYVAJ86+3Zs5Mddep7urumprpmW/ts3T3OadOnfrUTPX4POdXBwEEEEAAAQQQQAABBBBAAIHKECCoUBnqHBMBBBDIQ4FMgwrFnsBAWZ6g7E04AF0FoaB09YOyPZx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EEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEAglQFAhFBONEEAAAQTCBxU6O1jlwQITKvAK2gMG2qJ8P0lYiaG83NtfeT8mpJDch/eo/vcEFfwmlCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAK5ChBUyFWQ/RFAAIEaIpBtUEF5vOEC/VweMNBPuqVaUaE8pKAt3U/OP/Y+ylrom7QbQYW0RDRAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEMhYgqJAxGTsggAACNVMgfFChiwNkVjhIDBmEkdNQgz+E4N0zXd+mXvexH98tdf6ZcfdsmTt2nrdz3/uioiIpLCz0lVOAAAIIIFBzBXbs2C6bizbLL7/8LPXr1ZeGDRtJrVq1qx2Inuf27duldu3alXp+xc4fBps2/+j61qpVSxo1bFxtrLdv3yY7duyQunXrVZtzKtqyWerUriP1nN8NNgQQiE4gjvtFVbnvZ6Om3xWbizZJw0L9Tq6VTRdp99HvxB83bXDbNWva3AnkV8xx0g6EBggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAgjkiQBBhTy5UAwTAQQQqGyB7IIKOmp7WMB2Pt6VF4LDCumCCOnqy1d4mDHKCSqMIahguxaUIYBA9gJbfiqSyVNf9nWgk3Z7H9vHnfTtq4yoYN0Pa+W996f6ett/306y7z4dfeVakG/jNSfxyhvPO5Pot5mPZa9HHXG87NR857LPub5Zs3alfLl0sSxZ9rl8v26NOwny559/8nXboEGhOzmy5c6tZZ+99pO999xP9H0+bcXFO+TTzxfI3I9myWrnvH/8cYPz81rHDSs0a9Zcdmm7u/Q4rJfssdtesZ7WlGmvyPQZk91jttippYy88g85H19/T/T3xbvpxNZje50cWxBCf7aefHaMe08YNvjaLMIKxfLSq894T8F936hREzmu10mxTKBd+/0q52dmoaz9fnXJ/9etFvP70dgZx84tWkmLFi2lZYvWctCBXaVpk2a+8SYX5Os9Kfk8qv/nYnn1zYmyefOmSj/Vk3ufJU0aNy39ffD+t0D50PT+1e2QHuUFEb7Tn/nJzn1KJ/nbtiN7HCd678ply/1+YT96Vb3v20ebWLpq9Qr3u3n1mpXi/t+5p27bttX93tLv3zat2knrVm3d7+N2bXdN3DnUp2L5+ttl8vHCubJ8xdeyceMGN6RoQvka4tO/N/Ta6r1uvw4Hyp577BOqZ3+j+O/nU995XTZt2pgwlH322l867n9wQlnUH7Zt2+bcO573davfGccdfYqvnAIEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAIH8FiCokN/Xj9EjgAACsQlkFlTQYZlJQuGDCrpX+BUV3Nb6T9JmjqvFwcfW47CiQhIdHxFAIBKBDRvXy22j/tvaV9fO3eWsPhdY63It1Kf7Pzj2DlmzdpWvq13b7SHDLrnWV64F+TZecxL/+M//c1c0MJ/N62WDRspuu7Y3H7N6LXKeyPzerGkyf8Ec58nJiZP4MumwqfO05UMOOkx6dj9WNMhQlbclyxbLCy8/6f48pBunBhX6nT0w1KTzdH2lq1/46Ufy9PPjyppFFVQYPX6UfPXNkrJ+zZs+J58jh3c7ynyssNdFn82X5yc9WfYz3KnjIXKeY5rZViw333KDdZerh/1WWrVsa62LolAnZusk11lz3nFXhAjTp07q7eL8PvTqeULKMFG+3pPCGFSnNjrB/a///F2ln9Jee+4rgy68wvlviALRAJv+TNq3ArngnMGRT8LWp/g//vTDsvjLRdbDakhx2OCROf0+RnO/8A+vqt73/SNNLNG/d6a8/ap7rdU//Vbg3Nd7umHR+vUbpG/utPjQCey9/d6bsn7DulDtTaMD9jtITj7hzJT3ONM28TX++/ndD/yfEzBL/JtRV4cadOHlsmf7DonDi/CTfn/ccuuNvh41XDLi8sq/p/gGRgECCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggEBOAgQVcuJjZwQQQKDmCGQeVDA2ZvJIcmggXbnZP2g/rffW2fozZaavxH1m6ooKY1lRwavDewQQyF0g1SRb7f20k86R7odGPRG6WJ54ZrR8tnih9QSyDSpUxfGaE6yIoELRls3uihSz5rwrW7f+Yg6V86tOjOx+aC8nsHCMFDZomHN/UXcwwwllvPHWJNGJx2E3ffJx//MuFf3Zqqht1erv5KFxdyVci3wPKuik2ilvvyLvzJjiY9PJrRpqCb/FP7FVx6YBntenvOiuLhJ+rOUtCwpqyUEdu8jZp1/oPvm8vKbkXb7dQ5PHX1M+V4WgQsOGjeWqob+Wxs5qCrrt2LFDxk940H3Kvu061K1bTzTM1qZ1O1t1VmVvTp0k7858y7qvhif697vUfdK+tUGawmjvF4kHq6r3/cRR+j/p3zkvv/Gcs7rBen9lmpImzooup598rugqU+m2p54fK598Oj9dM2u9rkR0pHMvP+HY06z19sL47+e2oIKOTYOVQwde44Rr2tiHmmMpQYUcAdkdAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEMgzAYIKeXbBGC4CCCBQWQK5BxV05NkEC4L285Z7Awm2Y2hb71bShqCC14T3CCAQlUC6Sba1atWSQf2vlD332CeqQ8o058nm+nTzoC2XoEJVG685x6iDCp9/8Yk8++JjohPoKmorLGwo/c4aIPvstX9FHSLjfnWCrU60zWbTSb9XDLlOWu4c/WRGDY08MPp239Os8zmo8NNPW+SZF8bLF0s+tXLrBP7B/a/I4EnW8U9s/fTzBfLks6Ot48+08IbrbpaGhY18u+XbPdR3AjWkoPKDCgVy8flDZd99OiaI6++Zri70/bo1CeXmQ7NmO8kVl1wnGnLIdfv4kw/lWed3Omg78bjT5agjjg+qTlke/f2i/HBV9b5fPkL7u5mzp8trkyfaKzMo7X1sH3dll1S75BJUMP1mtkJP/PfzoKCCjl9/Ty4ffK00ckKJUW8EFaIWpT8EEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBFILrFu3Tt56y//grY4dO8qBBx6YemdqEYhAgKBCBIh0gQACCNQEgeyCCt4AgSp5QwRBasn7JO/nrTf9mTLz2du3qfOWlbQjqOA14T0CCEQlkG6SrR5HJ+deMeRX7kSwXI+rTxfW1RREbPe7kt5zCSpoD1VpvCVnJBJdUKFYpk5/Xaa9+6bTdbChOW6ur/qE7eOOPkWOObK305XteyvXI4Tff+lXX8i4J+7PaCWF5N71icuXO5N+NbQQ1aZPRR/35P2yzBlf8pavQQWdmDn28fvku5XfJJ9SwmcNsQy88PKEsuAP8U5s/WH993LfI7dGFubJNqigHlXxnhR8napnTWUHFY44/Bg5pfdZVlwNKWhYQSf727b2u+8tgy+6UmrVqm2rDlWmv8uPPDpKtm3bam3fudOhcs6ZF1nr0hVWzP2i5KhV9b6fzmT5iq/l4XF3O6tmbE/XNER9gfQ7e4CzssshgW2jCCrUqVNXrrz0eifM1zrwOOUV8d7P9bipggpav0vb3WXIgKud7/e6+jGyjaBCZJR0hAACCCCAAAIIIIAAAggggAACCCCAAAIIIIBAKIFZs2ZJjx49fG3/8pe/yE033eQrpwCBqAUIKkQtSn8IIIBANRXILKgQNNEz2wmZ3v68fZhyb1mYC1Cy38xRH8jcsfNS7lBUVCSFhYUp21CJAAIIeAXCBBW0fds2u8jQgSNzmgC2Zu0qdzLmL7/87B2C732uQYWqNF5zclEEFbZv3yYTnhsruppCJlv9+g2kkfM0bp2gqhMRNxdtynjy9v77dpLz+w6W2rWznyibyZiT227ZUiR3PfC/UuSMPWirU6eO+zTljRs3pAwzdOvSQ8487fygbjIuf/XN5+X9D96x7pePQQX9OXn0yQfkq2+WWM/JFO7X4UDpe3p/5++OhqYozWt8E1uLi4vlgTG3yYqVywPH1LRpc2ndsq00bdLM+d3YJht/XC/ffvd14ETuXIIKOoiqcg8NBKnmFRpU+Pedf62Qs9zuTEYPChnoAdu13U0uGzQy5f3zy6Wfy/gJDwbeuw495Ag549Tzshr/ps0/Oiu+3Ob8jG+w7r/rLnvIkIuvdr4f6ljrUxVW3P1CpCrf91OZ6M+ChqTWb1iXqpkTPKnl3D8bud9res9Ktel99tor/ygNGtj/O88WVGjcuKns3KKVG5TasPEHd9UOnXSfatOf1WGDR4YIxcR3PzfjTRdU0Hb6t8qF5w4RDVlGtVV0UGHJssW+obZp1bZCVofwHYgCBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQSqoABBhSp4UWrYkAgq1LALzukigAAC2QpUjaBC8gQJMwEluTzdWZqgwmwnqPBRysYEFVLyUIkAAhaBsEEF3bWT8zTf884eaOklfZFO3HtgzO2y7oe1aRtHEVTQg1SF8ZqTzT2oUCzPvPCYLPjkQ9Nl4KuGEvbfr5N0cJ52v1f7fa0TG/V6LP1qsXy5dLF8uniBbHYmsqbbOh/kPHH7jOyeuJ2u73T1b06dJO/OfMvarIkz0fyk489wnzatkxM1CDN9xmSn/VTrpF9tc/Ww3zpPjW5j7S+TwnnzZ8vEl58M3CXfggr69O/Hn35EvljyaeA5aVjlxONOF31CfGZbfBNbNaBw/+hbrcNr5YQTjut1snTc/2DfZNatW3+RxV8ukllz3vUFNXINKuhgqtI9yYpDYVYCU6a94t5zbDvXq1fffUq93gvSbRp40uBT0Nbn5HPk8G5HBVVby7dv3y6jHxsl3y7/ylqv988rnFVmdFJ7plvF3i9Equp9P53TpNeelQ8+fC+wmU6mP67XKaIr/Oj9dOvWrbJi1bfyxlsvBV4n7eyoI4537722jp96fpx88ulH7moIGmrR72tdycW7aRjio48/kMlvvyKbNm30ViW8v+Si4bJn+w4JZf4P8d3PzbHDBBW0bfdDe8lpJ/U1u+X8WtFBhZtv+a1vjP2cv7VTraDh24ECBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQSqkQBBhWp0MfP0VAgq5OmFY9gIIIBA3AKZBRV0dCZE4B1ppoEC77629+YYYfs17Uv6mjmKoIJNlTIEEMhNIJOggh6p93F9pNcRJ2R0UJ0c99hTD6Wc/OztMKqgQlUYrzmvXIMKb739qrz93pumO+urPnFZr41OZK1bt661ja1Qn4j9wYcz5B0nCJAusHCsM8FbJ3nHuenTwO+49+/uZM7k4+rT8C8dOEKaN2uRXCVzP3pfXnzlKV+5FuQyYdx0+O13X8no8feIrnQRtOVTUEF/T5+e+Kg72TXofJo3byEXOCtr6FO3M9/im9g6Y9Y0eX3Ki74htm7VTi4dcLU1vJPceNFn8+U1p48NG35wq6IIKmhHlX0PTT5PPucmsNR5Gvq4J+93QlGJf7ebXjXcpZPGw24vvvqUzJ33vrW5PoF/4IVXOAG0dJPIy3fXIJUGqmybrrAz1Ll/ZvP7XNH3i6p637c5Jpfd7nxfrV9vW02hwAl7DnC/f5L30c9qqiE7/b63bfp9d/2IP9mq3BDoj86KGe332Mda7y3UMJ+GV4JWnDn1xLOlx2FHe3exvI/vfm4OHjaooO1P6X22E6ZLdw6m59SvBBVS+1CLAAIIIIAAAggggAACCCCAAAIIIIAAAggggEDUAgQVohalv0wFCCpkKkZ7BBBAoIYKZB5UsEF5JhyZt96MgSnTXZ2nM6fdzASm5LbWck/npW9n3kNQIa0xDRBAIGOBTIMK+jT6i8+/TDrsfUDoY02e9rK8M2NK6PZRBhUqe7zmpHMJKuhTkvVpyak2fUKzToitX79BqmYp6/Rp8i+8PEEWLJqXst15fQdJpwO6pGwTZaU+Zfq996dauxw68BrZfbc9rXVa+OyLj8nHC+da6gvkmit+Jzu3aGWpS1/0o/M06gdG3yb6mmrLp6BC0OR+c35qdcnFV0mTLJ68XtJHfBNbNRilKyMkb7qShq6oEHbb8lORTHhurCz76guJKqhQVe5JYQ1oFyxQVLRJ7nn4P4FPp+9y0GHS94z+wR1YanSVgrGP3+db0cM01UDa5c4KCDs139kUBb6+/8F0Z4WGiYH1ukKShray2Sr6flEV7/thnFL9TdWz+7Fy8glnpu3m8acfls+/+MTabvjQX0ub1rtY6zIp1NWt7ne+w3QSfvLWtUt3Oeu0C5KLkz7Hdz83B84kqKD32QvOuUQO2O8gs3vWrwQVsqZjRwQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEshIgqJAVGztFKEBQIUJMukIAAQSqs0D+BBWcFILJJCQEGEyhc5UIKlTnH1XODYFKF0g1qS5ocDoZXidKhpnkvdCZZP90mkn2yceJMqigfVfmeM25ZRtU0NUO7rzvFtnoPCnZvhXIsUedKMcdraschAjN2TtJKNUJqG+8Ncl5uvOOhHLzQSeqj7zyjxmt2mD2zfy1WG4d9T+yceN6364HH9hVzj1rgK/cW6A/3+pnW/VAV4bQFSIy3bQvXUlBV1RIt+VLUGHN2lXOpNVbZds2++oQLXduLZdcNFwaZx1SUKn4Jrb+3x1/EZ1E7t0aNCiU3//qb96iUO937NjhBmV6HNbL+Zmv59sn3+6hvhOgIEuBYhk/IXilIP3dv/LS66VevfoZ91+0ZbM8MOb2gKfyixu2GTZ4ZMq+lzgrPTz65AOB9/FjjjxRjj/m1IzHpjtU/P2i6t33w0LNXzBHnnvpcV9zXeVI7z+1a9fx1SUX6Cout93zP8nF7ucLzhksHffvbK3LtPDl15+V2XPf8+22S7vd3b/xfBUJBfHdz81hMwkq6D66YsiQAVeJ/k2Zy0ZQIRc99kUAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAIHMBggqZm7FHtAIEFaL1pDcEEECg2gqEDyqUTvTQMIBvfqevINjLrIrgbZEQPPBWeEII3oOaPtzD+o89c5SuqJD6KddFRUVSWFjoPRjvEUAAgZQCqSbZNmu2k+iEOdumE5eHDb425RP8V61eIQ+Nu1P0Sf22rbBBQ9Enlidv2QYVquJ4zbllG1SY/t6bMuXtV003vtcTjj1Nju7Z21eea8EHH74nk157NrAbneCqE10relv+3dfy4Ng7rIcZ7Eyc36t9B2udt3D8hAfliyWfeovc961btZOrLvuNrzxdwcSXn5R582ena+bW50NQQZ/grsYrVi63nlOrlm3ckEKjRk2s9eEL45vY+vd//5fvvqMThf/46787i2D5/8YKfw7+lvl2D/WfASXZCKRaUaB27dpy2aCR0q7tbtl07e6zes1K9/vzl19+tvahq+hceO4Q68/zD+u/d1Z8ud36/aqd6VPmLzz3Eudd5r8LcdwvquJ933oRLIVBK0Hsusse7t9Mll2sRf+682bZvPlHX12fk8+Rw7sd5SvPpuDDj2bJC69M8O0aLtQV3/3cDDAoqKD39q1bt5pmCa+NGjZ23Zs3b5FQnskHggqZaNEWAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAIHcBQgq5G5ID7kJEFTIzY+9EUAAgRojkFFQISA3kNHkHRMySBa2ToYLOKC3D8t+BBWScfmMAAJRCKSaZKtPgx77+H2Bkx3363CgXHTepc4w/JMdt2wpkvvH3Bb4ROh99+koHfbeX15543nfaWQbVKiK4zUnl01QQZ8If/u9/5CgiaoHd+om5555sTlE5K+vvjlR3v9gurVffUr4tcP/KDoJsCK3oEmfOpHyhmtvllq1aqU9/Kw571h/znTHkVf+QTRMEHZL1Zetj3wIKrw1/TV5+903bMMXdb5q6G+kadPm1vrMCuOb2HqH83ujk7WTt/79LhWd4B3llm/30CjPvab29d3Kb+ThcXc5K7VstxKc0vssOeLwY6x1mRR+/sUn8sQzjzirInj/26G8h149T5Dex/YpL3De6feFBo901QPb1qZ1OzdEYVsdxNY+uSyO+0VVu+8nG6T6/M7MKTJ56su+Jh32PkAGXDDMVx5UYFsVRtueemJf0dVdotgWfPKhPPPCeF9Xer+//uobfeWJBfHdz81xg4IKF5031Pk9GR24eogGazU4pN9n2WwEFbJRYx8EEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBLIXIKiQvR17RiNAUCEaR3pBAAEEqr1AXgYVxJmEZOYhEVSo9j+jnCACVUUg1STbP1z/37J8xdfy6JMPBk4A06fq69P1vVtx8Q5nnwdkybLF3uKy9zp5+4ohv5L5C+fIy68/V1Zu3mQbVKiK4zXnlE1QYdacd50J9n4f7VOfDjxi2O+kTp065hCRv+p1vO+R22TV6u+sfZ98wpnSs/ux1rqoCh9+9C755ttlvu4O6niI9Dt7oK/cVrDuh7Vy53232Krk7D4XyiGdD7fWJRcu/eoL5+f6ftmxY0dSVYEzWfg0mTzNPzm1qgcVNm5c74Zh9Cnptq3fWQPkoAO72qqyKItvYmvQKhrNm7VwV9HQoE1UW77dQ6M675rajwYB7nvkVtH7im3TEN7F5w91qvwBPlv7dGXvznxL3pw6KbCZ3gf1fqibBhqefHa0fLZ4obV9QydYdsUl14muPpTNFtf9oird9zN1eu/9qaJBi+StaZNmcv2IPyUXWz/r/Vj/Zti2bZuvXifla0g0im3KtFdk+ozJvq5227W9O7HfV5FQEN/93Bw2KKhw0x/+JbPnvmv9e9Ls2373vWVQ/ytFVzvJdCOokKkY7RFAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQyE2AoEJufuyduwBBhdwN6QEBBBCoEQKhgwoDO5fOI9LJRN6ggDJ5JhglP8nUU1UCWlrga5fcsDSJoC9ulbe+tM7t0FtecgRWVChx4F8EEIhWIN0k2/r1G0jQxDszkgvOGSwd93fup6Xb61NelBmzppmPCa86QXjY4JHSqmXbwIlluQQVqtp4zclnE1QY+8R9sjQg7HHOmRdJ506Hmu4r7PWLJZ+KTvq2bXu27yCXXDTcVhVZ2S233ig6STB5y3QCvQYVbBOLNWihgYt02/oN6+SB0bdL0ZbNvqbHH32K85T+g+Teh//tq6vqQYVUq2Yc7AQUznWCCtFt8U1sfW3yRJk5274ayC5td5eBF14uhYUNIzm1fLuHRnLSNbiTZ198TD5eONcq0LhxU2cFkl+LBgKi3J576XGZv2COtcs6derK0IEjpF3b3WTK26/K9PfetLbTCdqDnfv1HrvtZa0PUxjX/aKq3PfDmCS3WbBonjwz8dHkYvfzkAFXi06YT7ct+my+THhurLXZiMt/J7pCQK6bhiHud77TbEFEDafpd2zqLb77uRlHqqCCtkn1t6fWZ7sKFUEF1WNDAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQCA+AYIK8VlzJLsAQQW7C6UIIIAAAkkCmQUVPKEAb9DAu6qBt9wcy7NbYKjB20fZcglOByaTEFTvDUmUHo+ggoHnFQEEohQIM8lWj/fMC+NlwScfWg9dt249N3zQulU7d5WE51583NpOC8/vO1gOPKAk1BD0BNxcgwp6nKoyXh2LbpkGFX76aYv83x03WZ7eL27I46rLfiMFCd8hJcepiH8fGX+3fP3NUl/XtWrVkhuuvVkaNCj01UVRoE/vvnXUf1u7+u21f5FGGUwGnvTaM/LBhzN8fe29537OU5av8JV7C7Zu/UUeGneXdULn/vt2kv79hjh1K/MuqKChi9sc361bt3pP132vT/++etgNosGf6Lb4JrauWbtS7nno3+4T5m3j14m+5555sTu521afSVm+3UMzOTfaJgrM+3i2TJz0ZGJh6Se9Hw+68ArZa899rfW5FG7fvk1Gj79Hvv3uK2s3+vt6ZI/jRIMEQdtZp10gXbt0D6pOWx7X/aKq3PfTggQ02LRpo/zn7v+2rkLVrGlzGT70Nym/Mzdt/lHuefBf1lCchqt+O/ImqVUr81UBkoerqzXpqk227YJzLnHCpwfbqjxl8d3PzUHTBRV0RZGnnh8nGvQI2o52VgE7IWkVsKC2ppyggpHgFQEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQACBeAQIKsTjzFGCBQgqBNtQgwACCCDgEQgdVBikk2U9iQNvIMFMAPWWeY7h3S1tH+5+Jp3gfDBvzTGS6xM7d2sJKrgM/IMAAhELhJ1kq5OZH370Tlm56jvrCJo3byFnnHKePPHMI7Jtm3/is+501BHHy4nHnV62f0UGFarKeM3JZhpUSPVE5ROOPU2O7tnbdF3hrx98+J5Meu1Z63HO7zvICZ50sdblWhi0mkNBQS358+//6XTv+f5Oc7C3naeMv+U8bTx5a+I8Af3X1/w5uTjhs058/OTTjxLK9INOdh82+Fp3Mv+q1SvyLqjw1vTX5O133/CdlxacemJf6XFYL2td9oXxTmx92rluCy3XzYxfgzZH9Theju11ktSuXccUZ/yab/fQjE+QHVyB79etkfseudUJ9vxiFenV8wTpfWwfa10UhTqB/YExt4tO5M9063HY0c7v9NmZ7pbQPq77RVW57yecfIYfdBUiPQ/bpitf9D39QtFgZ/K2YuVyeX7SE7J6zYrkKvfzScef4QZSrJUhC3VloenvTRYN3di2xo2ayPUj/uSEIWrZqj1l8d7P9cDpggraRv/+HPPYvYGhHm1zVh8ntNM5fGiHoIKqsSGAAAIIIIAAAggggAACCCCAAAIIIIAAAgggEJ8AQYX4rDmSXYCggt2FUgQQQACBJIHwQQWdXGlSA9qJZ9KjN6DgKS5p4+xjdnPrvA1MhadrXxs9lrOZY/jqPf2XtJSZ98yWuWP9EyVLq92XoqIiKSysmCdbe4/DewQQqD4CYSfZ6hmv37BOHhh9u/VJv+lE9tlrPxlwweUJqwBUZFChqozXuGQaVHjv/anyxlsvmd0TXq+89NfSts0uCWUV+WHDhh/ktnv+x3oInZirE3QrYpu/YI4895J/dQ5dSUFXVMhkCwpb1K5dW268QUMP9m36jMkyZdorvkpdaUBDChpW0C3fggr6hPZ/3Xmz6ModyZuukHH91TdKvXr13art27eLTpKuW6eONGzYyCnz/s2TvHeqz/FObP1h/ffy0Ng7ZXPRplSDkhY7tXQnce+7T8eU7YIq8+0eGnQelAcL6O/Lg2PvCAzq7bZre7l0wIgQk7uDjxGmZuWq5U5g8C7rKihB+5d89w5zvnvTTTwP6kEkzvtFVbjvB0uEq1n+3dfuddqxY4d1B10RoVuXHrK783OjqyzoPeTrb5fKh/NnWVdR0k6aOKtmXHvlH6WOcx/OZFv02cey8cf17jHWfr/aDVDoygO2TVcF6d/vUtmvw4G26qSyeO/nevAwQQVtV+Tc8x907v36HWDbNIQx4IJhoisqhdmyCSps2VIkul+Y7fZ7/+5rdtpJfWW/fcJcB3H+279hxKsf+YZDAQIIIIAAAggggAACCCCAAAIIIIAAAggggAACsQoQVIiVm4NZBAgqWFAoQgABBBDwC0QaVEiYj+f54J3kEbQygnceSEKb0jEH9eEtL21KUMF/nSlBAIHcBTKZZKtHW/rVFzLuifudnJV9Ap5tRLrawhVDfiWFDRomVFd0UKEqjNeccKZBhVfffF7e/+Ads3vZa0Nnkv4N197kfPZ8H5XVVtybO++7RfRJzMlbFE/qTu7TfJ499z15+XX/Sg6tWraRq4fdYJqFel24aJ48PfFRa9sbb7jFxMe3/gAAQABJREFU+kT9z7/4xF0hxD+pUydzDpH99+1U1l++BRWWLFvs/B7fVzZ+75tDD+npBGHaOatIzJfvnWv+448bnN/3kj9odILnzi1auRNZuxx0qLRq2da7a5r38U9s1esy+rFR1kBG8mB1cq4+dX6n5jsnV6X8nG/30JQnQ6VV4JU3npdZc/z3Y22swZ4rL71emjdrYd036kL9vdRVXsoT08FH0N9VDVTpGHPZ4rxfVPZ9Pxcn7766Wo2uQhHFpgGCfmcPlE4Zrl6kf6f99Z+/Cz2EzFZsiP9+HjaooCesK6BoUG3LT0XW89ew4dCBI6wrWyTvkGlQQY95+z1/Dx1USD5epp97H+cERo+omMBopmOhPQIIIIAAAggggAACCCCAAAIIIIAAAggggAACUQgQVIhCkT5yESCokIse+yKAAAI1SCB8UKGzRaV08qcJCyTMBTUfnAl7CSEE7cZTZ3pNaGPqTaXzao5hikyYIbncqSeoYJB4RQCBKAUynWSrx545e7q8NnliqGHUrVtXLhs0Utq09q8AEEdQobLHa5AyDSo8+exo+fTzBWb3std2bXdzQx9lBTG9GfPYPbLs6y99Rzuo4yHuBEpfRQQF78ycIpOnvuzrqf3ue8uQAVf7ylMVpJpoe8N1N0vDQl0poHzTJ0/rE9RtT0Q+5qiT5PijTylv7LzLt6DC61NelBmzpiWcQ6YfdPLsIQcfLjq5VZ/onH6Lf2Krjmn5iq/lsQkPhVoJpnbtOnJkj+PkmCNPDP3k8ny7h6a/TrTwCny2eKEbWPKWed+f33eQHJjhBHLv/tm8n+ZMgp+aZhK8hhM0pKBhhVy3OO8XlXnfz9XJu7+Gu154ZYLMmz/bW5zxe1194dyzLs44pKAH0jH89Z/pQ306ab/v6f3lgP0OymB88d/PMwkq6Il8/c1SGesE8nRFENvW1FnNQn9HmjRuaqsuK8s0qJBqFaqyTiN8Q1AhQky6QgABBBBAAAEEEEAAAQQQQAABBBBAAAEEEKgSAgQVqsRlqNGDIKhQoy8/J48AAgiEFwgdVBhoCyqUHseEBhIO6wkoeHMHJpDglpkKT1tvH95+LYEEt6lp46knqOBF5D0CCEQlkM0kWz32cy8+LvMXzkk7jHPPGiAHH9jV2i6uoEJljteceKZBhYfG3SnfLv/K7F722mHvA2TABcPKPsf15mnnCd4LP/3Id7g923eQSy4a7iuPomDKtFdk+ozJvq50MuWF5w7xlacqWLlqudz3yK3WJtcO/2PCU/R1UuIDY253n8icvMO++3SUi88f6hSb7/qSFvkWVLjnoX/J6jUrk08vq88tdmrpmFwWYkJ0/BNbzQlt2rRRnp/0hHy59HNTlPK15c5t5KLzLhU9t3Rbvt1D050P9eUCG53VRO59+N+yZYv9qezdDukhZ556fvkOsb0rln/e9ueUK4XoE9Z1AnMUW5z3i8q670fh5O+jWB576mFZ/OUif1XIkv79Lk1YvSfkbm6zsEGFOnXqyOkn95NDOh/m7Jf43RZ8vPjv55kGFXTsCz75UJ554THnnfmP9cQzattmV7nUCT7Wq1c/scLziaCCB4O3CCCAAAIIIIAAAggggAACCCCAAAIIIIAAAgjEIEBQIQZkDpFSgKBCSh4qEUAAAQSMQIUFFTzBgYR5HN65DyZkoIPxtjeD01fTJl29ti1tQ1BBMdgQQCBqgWwn2W7btlUefvQuWbFyeeCQjjj8GDml91mB9XEGFSprvObkMw0q6NP8l3/3tdm97FWf3K1P8I57Cwqm7LH7Xs4kvxEVMpw3p06Sd2e+5eu7k2NwXoYGa79fJTrJ0baNvPIPZRPSdWLn40/bJ5bqpPUrhvxK9OnTyVs+BRV08vWtd/8t+RRy+tyoURMZcfkNUtgg1coK8U9sTTypYnn/g3dEf662bbM/YdvbXp9If97ZA2Wfvfb3Fvve59s91HcCFFgFiot3yJjH7pWvvllirW/Vsq1zP7jOWXmjrrW+IguDVh3wHlNXObn8kusSQlje+rDv475fVMZ9P6xFpu10VSQNSNlW5gnbV9s2uzj3oUEhgmD+HsMGFcyeukJS3zP6i64sk36L/36eTVBBz+OdGc7qTNP8qzOZc9QAogbTCgpqmaKEV4IKCRx8QAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEECgwgUIKlQ4MQdII0BQIQ0Q1QgggAACJQIVElRIDhV4HzjpDSroEMIGEZL7NBfQ7K+fCSoYFV4RQKACBLKdZKtD0X3vH32bFBVt8o1Mn7Q/6MIrpFYt+8Qv3SHOoIIerzLGq8fVLdOgwvgJD8oXSz4t2dnz71577iuD+1/pKYnnbdB4slndIOyIp737hkyd/pqv+d577ieD+l/hK09VoKtT6CoVtu03I2+Sxs5Ee910MqNOarRtZ/W5QFo7k5NtmwYVXnz1KV9V0ybN5IJzLkkob92qrdStWy+hLN2H0eNHWSdM9zn5HDm821Hpdk+oX/TZfJnw3NiEsig+dD7oUDnnjItSdBX/xFbbYL5ft0Ymvf6sLF222FadUFbg/D2mq8LoBN6gLd/uoUHnQXmiwLR3Xpepzv9tmz6BXkMArVu1s1VXaNlnixfKE8+Mdo6R/B8f/sNqmGLY4JEpnxbv3yuxJO77RWXc9xPPOJpPb739qrz93puRdKZP+7/k4uGyS9vdM+ov06CCdt6rp7MSx7FhVuKI/36ebVBBz+vFV56SuR+9r2+t22Fde8rpp/Sz1hFUsLJQiAACCCCAAAIIIIAAAggggAACCCCAAAIIIIBAhQkQVKgwWjoOKUBQISQUzRBAAIGaLhA6qDCoSzBVUIjA7OEGFUrTCkFtTeAgXb326W1j9vOUs6KCgecVAQSiFMhlkq2OY9nXX8q4J+6THTt2lA2rWdPm7pPnGzZsXFZmexN3UEHHEPd4zXlnGlR47qXHZf6COWb3sled5H7VZb8t+xzXm/se+Y+sXPWd73DdDukhZ556vq88ioKZs9+W1ya/4OuqXdtdnZ+v633lqQo+/+ITd6UEW5v/+s0/nOBAXVm4aJ48PfFRW5NIyy53nsKe6YTTKIMKs+a8K6+88Vzac1KTlju3kUbO7/H6Detk3Q/fO7/n21PuN+CCYdJh7wMC2sQ/sTVgIG6xXm/9+fpx08ZUzdyfjcsGXSttWtsnpefbPTTlyVLpCugqCrqagq6qYNtOP+VcOazrkbaqCi3TQJSuZPTLLz+HPs5+HQ6U/v30afHehHXo3SXu+0Xc9/3wEuFbVkS4o2np31V6Pw6/FTthmzdEw1lrv1/t/l9Xl0q1aYjuuuF/FF0lJ/UW//08l6CC/o362FMPypdLPw88rZOOP0OO7HGcrz7ToIJ+T677Ya2vn6AC22pPJ59wpuy7T9B3aWJPjRo2EV1BhQ0BBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAgeoiQFChulzJ/D0Pggr5e+0YOQIIIBCrQM5BBW9oIGjk3gk/Qe1Nm3T1egxvG7Ofp5ygQtCFoBwBBHIRyHWSrR571px3nInPz7vD0CdNDx14jbRru1vaYVVGUCHu8RqETIMKr095UWbMmmZ2L3utU6eu/P5XfxV9jWvTSbH/e/ufZft2/yT1o3v2lhOOPa1ChqJPP9anICdvzZrtJL+66v8lF6f8PO/j2TJx0pO+NgUFteTPv/9fN4Tx8KN3ytatqSdx+jrIoqCygwrpnvStQYNjjjxRdt+tvXN25ZObt23bJu/NmirT35ssQZNdNaQ04vLfu5P7/TTxT2z1jyGxRH+2pzhPPn//g3eciuAn1O/UfGcZPvTX1ifT59s9NFGAT8kCW7YUyb0P/1s2/rghucr93HH/g32rpFgbRly42Vm56IExt8uGDT9k3HOvI5yn5B8X5in5/q7jvl/Eed/3n23uJRp8uufBf8mWn4qsndWuXVuOOPwY2b9DJycI1lrq16/vhsBWr1kh78ycIitWLrfup4X779vJDZ0ENkhTsX37NndlHv37QkMvQVv3Q3vJaSf1DaouLY//fp5LUEEHrYGDR8bfneLcC+T8vgPlwAMSH2SQaVAhDZyv+uZb/OHTfmcPTLmSj68TChBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQqEYCBBWq0cXM01MhqJCnF45hI4AAAnEL5BRU8AYG0g1cAwWp2qer1/5NKMHbj6WMoEK6i0E9AghkIxDFJFs97ptTJ7kT7A7pfLgcfGDXUEOprKBCnOM1EJkGFYIma2p/F59/mfOk3Y6m6wp/XfTZxzLhuTHW45zXd5B08kzqK3a+y269+2+ik2oz3U445jQ56ojjy3YLWuGgXr368sdf/09ZuzBv3nt/qrzx1ku+pg0aFDrBj7/JMy+MlwWffOirr4iCyg4qaPhDf76St8aNmzqrY5wn+gT2VNsP6793nup+t2wKWIlgyICrpf3ue1u6iH9iq2UQ1qIlyxaLrmISdE6606kn9pUeh/Xy7Z9v91DfCVCQIPDEM4/IZ4sXJpSZDxrEGT70N6L3jTg3nWCuKzx8s3yZ9bD16zdw78O232uzw7lnDQj93Wz20de47xdx3vf1/KL8zkrlpXW77dJezjnzImmxU0v96Nt0LB9+NEsmvf5MwipV5Q0L3NUOmjdvUV6UxTsNmr3gfA98vHCudW9dTee/fvN3p648qOZvGP/9PNeggp6DBpAeHHuH/BgQRNKw7eCLhsvuu+5ZdsoEFcooeIMAAggggAACCCCAAAIIIIAAAggggAACCCCAQCwCBBViYeYgKQQIKqTAoQoBBBBAoFwgdFBhYOfynVK9swQHApubttrAGz4I3KG0Is1+BBXSAVKPAALZCEQ1yTabY1dmUCGu8ZrjZBpUWL9+ndx+r04U9G+HHtJTzji1n7+igkp0Avf8BXMsvRfIDdfeJA0bNi6rKy7eIX/95+/KPmfyRp/4rU/+Ntt3K75xnyBuPntfb7zhn6JPpg67aZDm3Zlv+ZrvusseMmzwtfL0xEdFJ8jGsVV2UOHxpx+Wz7/4xHeqh3U9Uk4/5Vxfua3giyWfyvgJD9qqnCdxnyPdDz3KUhf/xFbLIAKLipxwzbgn73dX17A10snFI6/8vVOVOHk33+6htnOjrETAuzpQsomuvjJkwFWyx257JVdV+OfnJz0hH338gfU4Oq4BF1wm++y1v6RqpxOwLx0wQnZpt7u1n6DCuO8Xcd739Zyj/M7asWO7/OuOm62rKTQsbCRXXfYb0UBYuk2/q/Q7y7blsjqGtz8dq078X/fDWm9x2ftfXX2jaDAneIv/fh5FUEHPZ+Wq79yVFXRFHdum1+qywSPLAiUEFWxKlCGAAAIIIIAAAggggAACCCCAAAIIIIAAAgggUHECBBUqzpaewwkQVAjnRCsEEECgxgtUiaBCJiEFvWIEFWr8zy0ACFSGQL5Nss238ZprmmlQQfe7495/iD69PnmrW7eeXDv8j9K4UZPkqsg/6yRGnRyokxqTt9at2rkTL73lUU761EmE//jPjU73xd5DuO+vGPIradd2N195UMFjTz0ki79c5Kvu2qW7nHXaBTUqqPCoMxn/y6Wf+yyOOeokOf7oU3zlQQVBT57vdkgPZ2WG8y27xT+x1TKIlEUaVhj92D2yZu0qa7uhg65JeNK2NsrXe5L1BGtwoU5e1iet6+oFtk1/N/R3JO4t1aR1HcupJ57trPRxtDssHfvo8ffIt999ZR1mE2eS/OXOvVNfw25x3y/ivO+rQZTfWd98u8xZbeYuK+15Zw+UTh0Psdb5C4vlobF3Wa9j+z32kSEXX+XfJYuSRZ/Nd1ZLGmvdc1D/K2XvPfe11pUUxn8/jyqooOPXsN1jTz3sXn/bSWowTUOMhYUNhaCCTYgyBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQqToCgQsXZ0nM4AYIK4ZxohQACCNR4gciDClVAlBUVqsBFYAgIVEOBfJtkm2/jNT8y2QQVXpv8gsyc/bbpIuE1rlUVJjw3RhZ99nHCsc2H43qdLMc6//duUU761H5vv+fvsn7DOu8h3Pe2Y/salRZs3bpV/vf2P8m2bf4JyKf0PluOOPxo0Qnqv/zyS1AXacvXrlttXWGgXr36ctXQ3yTs36RJs4xWg9CdR48fJV99syShH/3Q5+Rz5PButtULfE3LCp5+fpws/PSjss/mTaYTsafPmCxTpr1idi97NatUlBWUvYl/YmvZoTN4s3LVcrl/9G3OBFZ/QObsPhfKIZ0PT+gtX+9JCSdRwz9s3fqL3PfIrfL9ujVWiT2dyeGDLxruZIoTV9OwNo6wUFc+0UCQ7WdRD2MLBW3atFHuH3O7/PjjButIdm23h7MyxNWiKyyE2SrjfhHXfV/PP8rvLF2VR1fnsW2//9XfpEGDQluVteyt6a/J2+++4atr3ryFXDf8v3zl2RT89NMW+edtf7Lu2ufkc53vliOtdSWF8d/Powwq6DnMmTdDXnr1mcBz3H23PWVw/+FueOmWWzU0mbi13Lm1jLg8uxWkvD3dfMtvvR/d9/2cYMtBoYMtvt0pQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAgrwUIKuT15asWgyeoUC0uIyeBAAIIVLxAlQ8qmIlOlklwQToEFYJkKEcAgVwE8m2Sbb6N11ybbIIKGzeul9udVRVsqxnUqlXLnWy6+657mkNE/vrJp/PlqeftT1uuU6euXD/iRmlY2CjhuFFO+tSOg57av0u73eXyS65LOHbQh88WL3T7sdXrhN32u+9tq8qobNXqFXLvw//27aNPZR555R985ZkWRBlUmPTaM/LBhzN8Q+hy8GHS9/T+vvKgAg076CTm5E2f1v7ra/6cXOx8jn9iq2UQoYqeeWG8LPjkQ19b26oT+XpP8p1cDS6YOOlJmffxbKuAPlFdw0YaMIpzW71mpTw07k4nQPWz9bD6ZP3B/a+QWrVq++q/W/mNPPLoKCectdVXpwUHd+om5555sbUuubAy7hdx3vej/M6aOXu6vDZ5YjKhu/rRb0be5CtPVfDp5wvkyWdH+5ro9f7T725xyqMJzQT9baIhRA0EBm/x38+jDiroub05dZLoqiVBW6cDusgZp55nDXQQVAhSoxwBBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAgdwECCrk5sfeuQsQVMjdkB4QQACBGiFAUKFGXGZOEgEEIhDIt0m2+TZec4mCJgNeNmik7LZre9PM95pqAm3Dho3l8sHXij5hOept+Yqvnaf43xM40VWf4q9P80/eopz0qX3rhHqdKOvfCuS3I/8sjRo18VcllbzwygT58KNZSaUiOgH5hmv/4jwlvZavLtOCfAoqTHOe0j3VeVp38ha8EkJyy5LPs+a8K6+88ZyvslXLNnL1sBt85XEGFV589Snpefgx0nLnNpZxpC+aO+990T6St25desiZp52fUJyv96SEk6jBHz5eOFeeffGxQIGLzhsq+3U4MLC+Iip0hZcHxtxhXU1Gj7dT853doJbew4I2Ddpo4CZoO/G40+WoI44Pqi4rr4z7RZz3/Si/s97/4B159c3ny+zMG1294o+//rsTKgn/XRMUBNM+b/rD/zn/5h5U+Pnnn8S2UoAe49QTz5Yehx2tbwO26hFU0O+lp59/1LrKkDnxw7r2tIb7CCoYIV4RQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEIhWgKBCtJ70lrkAQYXMzdgDAQQQqJECVT6okMVVYUWFLNDYBQEE0grk2yTbfBuvuQDZBhXW/bBW7nno34GBAZ2IPfiiK0WfYh/Vtmr1dzLuyQdk8+YfrV3Wr99Arr7st9K0aXNrvU5+zGbTyZy1a9dJ2HXTpo3y77v+5pQVJ5TrB50wrhPHU207duyQW+/+m2yynEvXzt3lrD4XpNo9dF0+BRWWLPtcxj1xv+/c1H7kFb+XZs128tXZCnQiv07oT972at/B+ZkcnlzsfI5vYusDY26XH52fnaEDR0jzZpkHeYKCCranjOfrPclygWpckd5f73vk1sBVC7of2ktOO6lvrC7bt2+XsY/fK19/u9R6XL3/asBNA0HptsnTXpZ3ZkyxNitwVnfr3+/StCGMyrhfxH3fj+o7K1W4YLizKkeb1u2s18JW+PqUF2XGrGm+Kg3n/TbD1Rl8nZQWfPXNEieQOMpafV7fQaKrCQRv8d3PzRgqYkUF7Xvbtm0y9ol75Ztvl5lDhXolqBCKiUYIIIAAAggggAACCCCAAAIIIIAAAggggAACCGQsQFAhYzJ2iFiAoELEoHSHAAIIVFeB0EGFQc4EjGL/5Meq6EJQoSpeFcaEQP4L5Nsk23wbr/kJyTaooPvPnvuevPz6s6Yr36tOXLzgnMGyx257+eoyLVi4aJ5MfPlJ2bp1a+Cufc/oL10OOiywPuqKh8bdKd8u/8rXra4kMWLY70QDDkHbzNnT5bXJE63VF59/mey7T0drXaaF+RRU+OWXn52naP/J+fNnh+80O+5/sPOzdImvPLlgw4Yf5O4H/8/5Ofklucp5Cncv52nctsnd8U1s1aDCdyu+cZ88P+TiqwJDNb7Blxa8+IoTwvjIH8K48NwhcsB+ByXslq/3pISTqIEfNBDw8Li75LuV31jPvm2bXWSYs2JNcnjK2jjCQr3/zps/29qjhgt0hYew961i579xnnjmEfn8i0+s/dWrV989x1Shh8q6X+TDfT8ZVVcietBZCcO26TW7+PyhTlX6lRC2/FTkBmj0Ppu8HXxgVzn3rAEJxcu+/lKaOcFBXWkj/FbsrpqkYQXblj5YEd/93IyvooIK2v+WLUXy4Ng7RMNLYTeCCmGlaIcAAggggAACCCCAAAIIIIAAAggggAACCCCAQGYCBBUy86J19AIEFaI3pUcEEECgWgqEDioM7Jw3509QIW8uFQNFIK8E8m2Sbb6N1/ww5BJU0D4ef/rhwMmmWl+rVm3p1fMEObL7saJP3M50+/HHDTL1ndetk7O9fXXcv7MbivCWVfT7+QvnyHMvPm49TE/nfE8+4Uxr3ffr1ohOWLc9LVtXorh62G9FJ/5GseVTUEHPd/yEB+WLJZ9aTz3Mk7THT3gocP9B/a+Uvffc19J3fBNbTVBBB9GgQaGceep5cmDKp4OXD/eb5cvcCbw7dmwvLyx9d93w/xINyHi3fL0nec+hJr4PemK9WtStW0+uvPR62blFq1hp9An6Oq6gTe91es/LZNOggU7AXrN2lXU3ndx++ZDrpLBBQ2u9FlbG/SIf7vvJYBoM+fedN8vmok3JVe7nk44/Q47scZy1zhRqH489FXx/PbvPhXJI58NNc/f12RfGy4JFH0mnjl3kaOfvgNat0q/c8O7Mt+TNqZMS+jEfmjZpJteP+JP5GPAa3/3cDKAigwp6DA0pPDT2TinastkcMuVrVEGFv/7zd77g4PnOihZhv7NSDpJKBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQTyUICgQh5etGo2ZIIK1eyCcjoIIIBARQmECSocMaK7dKtiQQWdnBI0aZKgQkX9tNAvAjVbIN8m2ebbeM1PV65BBZ04N3r8qMDJpuY4Oim75+HHyEHOU5db7NTSFAe+rlr9ncz7eLZ88OEM2bZtW2A7rdAnjF9y0VXuxO+UDSOu1O/GUc7T+9d+v9ra87G9TpZjjjzRCWvUKqvX4MBjTz0oG50Ahm1LPxnftldwWb4FFZYs+1zGPXF/wAkVOJOhj5Hex/ZxniZfO6GNek6c9IQsWbY4odx8aOo81fu64X90gzOmrPw1vomt3qCCOf7BnbpJryN0Em9bU+R7/frbpfLU8+Nk06aNvjoNAP3h+r855Ynhlny9J/lOsAYVLP5ykXN/eNg5Y/uqarbJ4BXNo2PSQJre72xb187d5aw+F9iq0pb9sP57eWD07aJP6rdte7XvIAMvvCLhHuptVxn3i3y473uNzPuXX3/OWQXpXfPR97pfhwPllN5nWb+fl331hbz+1kuyYuW3vv1MgQYINEjg3TSo8PEnH5YWFch+HTrKYV17uoGFZk21bfk9S1dpmOSs0KQ/b0FbqgBg+T7x3c/NMSs6qKDH0aDa2MfvTfv3kLaNKqigK54kh1s6OcE6XfGEDQEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQACBmihAUKEmXvWqdc4EFarW9WA0CCCAQJUVCBVUuPpw6eoEFYKCAXGfnHdikm1MBBXiviIcD4GaIZBvk2zzbbzmpyjXoIL2s3nzjzLGmUAX9GRscyzzqk9+1yfbN2+6kzRq2ETq1a/vrC6wxelnk6xzJq5+ufRz64Rss7/3tVXLtjJkwFXSsLCRtzi29wsXzZOnJz4aeDydMKhPH67nPAl9xarl8smnHwVO+G3TehcZPvR6p6/yyZuBHYesyLeggp6WbTK/93T1Set77L6XtHW8duzYIXqOn3/5ifz00xZvs4T3fU/vL10OPiyhrPxD8MRWfQJ4i512Lm+axbtd2u4mRzuBFd1Sndtuu7aXgzp2dZ6W31KaOcGKbdu2y/c/rHF/ZhZ99nHgkbsfepScdtI5vvp8vSf5TqSGFGgI5Z6H/yNFAU+9V4Yeh/WqMI3GjZvKUT2OT/jvjzVrV8pD4+6yrv6iA9Hfw8H9h/uCQ5kMcqkTLnp0wgPu77Jtv8O7HSl9Tj7XVuWWpfqd0gbR3y9Eqvp934a1yfmevuv+fwZeS91HV0DS4F/LFq2lYcNGbqBOg3ir16ywdVlWpgHEfmcNKPts3iQGFUxpyatOdtfvR33VFQM2blyf2CDpk7bTsFnDho2TapI/xnc/N0eOI6igx9K/H556Xv/esIeGzHiiCiqY/nhFAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQACBEgGCCvwkVLYAQYXKvgIcHwEEEMgTgbBBhW6DulSpM9Kwgi2koIMkqFClLhWDQaDaCOTbJNt8G6/5QYkiqKB9aVhhrPMk/HQTGs1xo3jdtd0e0v+8S6VxoyZRdJd1H08+O1o+/XxB1vvrjnXr1pVhg691nzSdU0dJO+djUEEnxt4/+lbZunVr0tlk91Gfyj6o/5WBf8fopM+bb7khu85D7LXvPh3l4vMvc1umm1QdoruEJju3aOWEW34tderUTSjXD/l6T/KdSA0o0L+zxz15v+ik/crcRlz+O3fyuI5BV8t5cMwdoqse2LbmzVrI5ZdcG2LiuG3vxLJZc96VV954LrHQ8+n0U/q5T+L3FJW9jf9+UXLoqnzfL8NJeqMrFE167Zmk0tw+tmrZxvk5uM75Dqvn6yhVUMHXOE3BqSf2DRnUie9+boYcV1BBj/fe+1PlDWd1i1QbQYVUOtQhgAACCCCAAAIIIIAAAggggAACCCCAAAIIIJC9AEGF7O3YMxoBggrRONILAgggUO0FwgQVeo7o7q6oEBVGqpCBHsOsmBAUREg3DoIK6YSoRwCBbATybZJtvo3XXJOoggra37Zt29wJdDrpNN0Tf83xs3094vCj5aTjz3CfAJ1tH1Ht9/PPP7lPyv9+3ZqsuzznjIuk80GHZr1/0I75GFTQc5n38WyZOGmC8y71k6ODztuUt9ippTuJtkGDQlNkeY1vYuuDY++Q5d99bRlD5kW1atWSywaPlF3a7m7dOV/vSdaTqeaF02dMlinTXqn0szRBhR07tsvYx++Tr75ZYh2TPt3+skEjnWBVW2t9NoUvvvqUzJ33vnVXfdL/4P5XSPs99rHWx3u/KBlCVb7vW5FKCydPfVnemTklVZPQdfpzoCEFnRhv26IKKnTt0l3OOu0C2yEsZfHdz83B4wwq6DE1bKKhk6CNoEKQDOUIIIAAAggggAACCCCAAAIIIIAAAggggAACCOQmQFAhNz/2zl2AoELuhvSAAAII1AiBuIMKJoSguEFBBNMmqD7dhSGokE6IegQQyEYg3ybZ5tt4zTWJMqhg+vxy6WfORLpnA5/Ebdpl89qu7a7S+9g+ss9e+2eze4XtoyGF8RMezOKcC5zzOU169TyhQsaWr0EFxfhowQfywssTZMeOHVnZ6M9K/35DpWmTZmn2j29i6/r16+QlZ5Kp/o7kstWuXUdOPfHswKfMa9/5ek/KxSUf9/1m+TIZPX5U1j/nUZ6zCSq8+IoTGvjIHhrQ/17o3+9S2a/DgVEe2jn/7TLm8Xvl62+WWvttWNjInRTfvHkLa31894vyw1fV+375CO3v3n7vTZk6/XUnrJ7dvVV71RDYmaedL3sGhEe0TRRBhUMP6Sl9Tu6bQSgxvvu5nqNucQcV9Lo9/vQjsvjLRSUDSPqXoEISCB8RQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEIhIYPbs2dKrVy9fb3/605/kxhtv9JVTgEDUAgQVohalPwQQQKCaCsQdVFDGdEGEdPXpLgVBhXRC1COAQDYC+TbJNt/Ga65JRQQVtG/9bln02Xx5d+ZU+W7lN+ZwWb/qpPNjjzpZ9t+3U9Z9VPSOP/20RZ6e+GjoSej6NOpzz7y4Qs8pn4MKer2WfvWFvPz6s7L2+9WhL19BQS3p2uVwOe3EvlKnTt0Q+8U/sXXBJx/K9BlTZPWaFSHGl9hEQzp9Tj7HnSicWJP4KV/vSYlnUb0/6T3j3kf+Ixs2/FAlTlSDCl8s+UxemzwxcDwnHne6HHXE8YH1uVQUFW2S+8fcHuihKzjoSg5677Rt8dwvEo9cFe/7iSO0f9LVMl569emM7q3aU926deXonr3lyB7HiQamUm1Lln3urN7wlixd9oXTLLPVcQoLG8pJx53h3Mu7pzqEpS7++3ncQQU96V9++VkecQJOK1ct9xkQVPCRUIAAAggggAACCCCAAAIIIIAAAggggAACCPx/9u4EXorqTvT4X/bLvqjgihh3BUFF3GNiVjVq3BLUGGOMayZjzGJWMZ/kJfMy72WeyeSpmZlMFie+bG6ICzFqTCaKG4ILi4CAiguggnBB4cI751T9q09XV3VXd1dfuvv+euBW9Tn/8z+nvnUv3RnP/zYCCCCAQFsIUKjQFreRi0AAAQQaL1BroYIWE/grrPYTEDRHteP8Oe255tH2WTc8Lk/+ao4+TTx2dnZKR0dHYh+NCCC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PuYKFo446qtZLYBwCCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCLSIAIUKLXKj2niZFCq08c3l0hBAAIE8BRpSqOAXGOhitdAg1lf2ExX8T0/Q8TZfLIdO4Y4mjkKFIhGeIIAAAggggAACCDRYoNpCBX0/u6XLFCw88bQ8aAsW3nir7lV+8IMfdAULRx99dN25SIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAs0pQKFCc96XnrQqChV60t3mWhFAAIE6BDIXKpwzvjBLuUKBQlTymV9woBFp+fxYPyZqN2UOwR/xP5Fh1g32ExXmaPbEI5+okMhCIwIIILBNBVatfk02bdqUuobtR42Wvn37pvbHOyrli8fn8XzIkGEyeNCQPFKRAwEEWkig1kIF/YSxri1b5aknTcHCn/8ub6yuv2DhAx/4gCtYOOaYY1pIkaUigAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggEAWAQoVsigR00gBChUaqUtuBBBAoI0EaipUsNfvFw5U4xEVGcQGJeXzY/1+r307r12LFShUiNnyFAEEEGgBgVdefUl+9ov/U3alF1/wRdlpzC5lY7QzSz6NzfN4wvEnyjFHvD/PlORCwAlsNe9/Xn3t5Zo0evXqLR0DOmSA+duvX/+acuQxqJ2Lh7IWKowcNTykLBTc6vtq+7a2qyssWLjv77J69Zt1s59wwgmuYOHYY4+tOxcJEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEECgOQQoVGiO+9CTV0GhQk+++1w7AgggUIVA0xYqeMUI7nK8ggTx+0y7/U20WqRgYylUcGJ8QQABBFpKYMUrL8q//fK6smuuplAhS76yk9XYSaFCjXAMqyjw7rvvyA9+9M2KcZUCevXqJcOGjpBddxkru+48VnbfdZyMGb1zpWF197d78VCWQoUvXX2pjBg5rGBp38faN7Lh+1x76h7m+dYtW8wnLDwr9//pv2X1qje0p+bj+9//frnmmmvkve99b805GIgAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAs0hQKFCc9yHnrwKChV68t3n2hFAAIEqBKoqVAg3Ubn0Wizgt9kObU9bg8bH47Q9LUdav98ezpmlUMFe94ABA9JWSTsCCLSQwMCBA6V//233G8JbiKqpl5qlsIBChaa+hSyuwQJ5FSokLdMWKkw+5GgZf8Ah0rdv36SQutuy/IzXPUlCgu4qHsq7UMEVLZgvW7RgYebfTMFC/Z+wcPzxx7tPWLBHHggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggg0JoCFCq05n1rp1VTqNBOd5NrQQABBBooUHehgl2bFgvEiw+S1q2xts+PT2vXHGn9fnsYm6VQQdNyRACB1hfYf//95d5775Xddtut9S+mB19Blk3MFCr04G8QLl0aWaigvB0dA+XED35cDjpgkjbldszyM57bZF6iZipUuOrqS2TkyOHR6raz72Ptn6L3s2GbjTKnwWE72bLVfMLCE/YTFv4mq1bW/wkL9pMVpk2bJu973/uCSfiKAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAItI7B06VL54Q9/WLLek046SexfHgg0WoBChUYLkx8BBBBoE4GaChW22ot3XwIFu7nKLzooZ+NvxIqPcXliuaNcwaYt99Qf5+cLYylUiNA4QaDHCOy+++6uWGG//fbrMdfcbheaZRMzhQrtdte5nmoEuqNQQddzwH4T5OQPnym2cCGvR5af8bzm8vM0W6HCiJHDTP1BUIFQWqgQtNv1R29x3VvgsN0cTL2CzHnyGfmzKVhY+fpq/1JrOj/uuONcwcL73//+msYzCAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEECg5wlQqNDz7jlXjAACCNQkkLlQ4dwJxcUI0e4pM61fOOCvQmP8fm2zcX570ji/zY+tkGPWjY/L7Jvm+qM5RwCBHiCwww47yF133SWHHXZYD7ja9rvELJuYKVRov/vOFWUX6M5CBbuqHbYfLRece7kM7BiUfZFlIrP8jJcZXnNX8xUqDNcPSgg+ScEWIkTvbQsFCeGZ+1SFosKGUGKLeW/sChZm5lOwcOyxx7qChRNOOKFmawYigAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCPQMAQoVesZ95ioRQACBugUaVqgQbbgyS6yiyMBdkD9Wr7CKHBQqKBpHBHqewJAhQ+S2224TfjN06937LJuYKVRovfvKivMT6O5CBbvyncbsIp+eepn07z+g7gvJ8jNe9yQJCZqtUGHkyOHBKsP3u9GnKvhrN32uUCGqWwhOooIGr33LFlOwMNt8woIpWHj9tVV+lprOjznmGFew8IEPfKCm8QxCAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEGh/AQoV2v8ec4UIIIBALgKZCxXOGZ8+X6XCgrSRdpxfgODHxXNWivP6KVTwITlHoOcJ9O/fX37zm9/I6aef3vMuvoWvOMsm5rwLFd5/3Edk+LCRuaqNGb2z+U30Y3LNSTIErMC2KFSw8+6/73g5++Oftqd1PbL8jNc1QcrgZipU+NLVl8qIkcPsRygEqzUHV5JQeJrSHgRoUYMN0k9ZcANMty1YmPvUc/Lnex6S13IoWDj66KPlmmuukQ996EPBmviKAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIBAKEChAt8KCCCAAAKZBLZ5oYKu0is00KZoE5dtSOq37brRy4uhUMFi8ECgZwv07t1bbrjhBrnooot6NkQLXX2WTcx5FypUk6+FKFlqmwpkKVQ49cRPyIH7HyybN2+2O9llS1eXbHxno2zY2Clr166RN95cJS+tWCYvLFvkCh+yUn3qk5fInnvsnTU8MS7Lz3grFw9dd911cuWVVyZeuzZGhQq2IXwPGxzMzQr+BKGm0Tx1bcHBPQtiwnHxdn2+VUzBwuzn5E+2YOHVlba5rseRRx7pPmHhwx/+cF15GIwAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggg0D4CFCq0z73kShBAAIGGCjR1oYK9ct2MRaFCQ78PSI5AOwrY3zz9gx/8QK6++up2vLy2u6Ysm5irKSzIO1/bgXNBLSeQpVDh9FPOlfEHTKp4bRs3bpC/PXK/zHr8b6aoYVPF+B22Hy2XffbL5m1ZuGG+4ojSgHb/may6UMESGc9CQYI51yfmGEm78/CZHrz74DJ4MZpjq3nvbD9hwRYsvPrK66U3pMqWI444whUsfOQjH6lyJOEIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAu0mQKFCu91RrgcBBBBokEDVhQp291Na0UC5NVYapxuuqs2t4+zc4Vg+UaHcjaAPgZ4n8OUvf1l++MMf1rXBtuepdf8V572JOe983S/CjAgUC+RZqKCZV656Vf7zpv/rPnFB29KOn/3UP8iuu4xN667Y3u4/kzUVKhi1qPjDvKd1dQjhe1v/LW4hpsCsbaWFCmE1g8tt3x7bgoV5pmDhL/LKivoLFqZMmeIKFj760Y8WFsMZAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggECPEqBQoUfdbi4WAQQQqF2gqkIFf8dUNQUFWcZpTDV57WXrOHteQ6HCEZdPtiN5IIBACwm8tXyNzL9zYVUr/sxnPiM/+9nPpE+fPlWNI7j7BPLexJx3vu6TYCYEkgUaUahgZ3p5xXL55c3Xy6ZN5T9Z4egj3icfOP6k5MVlaG33n8maChXM+9igOMECmvPCk8JbXNMWRtkT99DihHCUa49ibKbw/bG+Tdbnc2Y/JzPvtgULrwWJ6vh6+OGHu4KFE088sY4sDEUAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQaEUBChVa8a6xZgQQQGAbCNRUqFBtMYG9LrtTqtw43UlVLibNJ5Y76ycqjNxzhHzmrnNlq5c32P8V7QIr9JQGFfrMmf1ttWkP3Rym/fFY3WxW0q4mhYF65o7+jInr9gPsiPCyoiRmzfGQqM+Gx+ZPWl+8zY6Pj4vfd52zaM1uoP1iHhpgz+Nrdv3p647Pnba+tHabPnp497R0SeHC/PWVBkWp7EnSnBpQad099XvE+vgbL6PvB2O97vX18sfP3i6rnl+tjBWPp512mtx8880yYMCAirEEdL9A3puY887X/SLMiECxQKMKFewsf3rgTvn7rAeLJ4w922H7MXL5RV+OtWZ/2u4/k1kKFa766iUyctTwAC18nxUczBuK4E8Ial799D2Gay90Rq+L2m5HhLFRn20yCTRHcB4E2fcjT8+ZJ/fe9aCseLn+goXJkyfLNddcIyeddFLpe8DwajgggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCLSXAIUK7XU/uRoEEECgYQJVFSo0bBX5Jq6mUOECU6gQ7u1yi/D3mlezqpIcNpHfmJQsS0xCGl2jn17bkqYp16Y5ovGV1qSBOjAlebxbh9lw7fPbUtKkNhfl0ETamDTKxpTrD8fEQ5JSa1vSNOXa/NwuR5Y1ZYlJuDRdY8mc5RaY0qc5NKcrJNHGpDEaWC6mzJptSn+opkuaauPad+TWi6fLK0+9mtSd2Hb88cfL7bffLkOHDk3sp3HbCeS9iTnvfNtOhpkRCAQaWajw9ttr5Lobvi9dXV2p3L1795FvfeWfUvsrdbT7z2TWQoURplDBvc7ZKgL3JzhaP9ceQkZFjLY7rDiIFyJE5t5AjQmGBMUKfqGCzuMKFubOdwULL7+U/XU0mjN2cthhh7mChZNPPjlabyyEpwgggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACbSJAoUKb3EguAwEEEGi0AIUKsUIFf1e0t+mr0m/5LwpNy+HfzCwxYXxRbi9HUXtSvqQ2b7w9rZjDj8+Qzw8vyu11aLv3gQWxhSQEe032VHPY89Q8ttM+alx32rDU+dIGBKtwX3XdqTm82GrWrXnt8LRlJM7pB9vBfiL73Dz8psQcQVjhq5/TH1yIiM787qRhqfN5wZs2bpLpX7hblv51eZS30skhhxwid999t+y4446VQunvRoG8NzHnna8bKZgKgUSBRhYq2An/879+KstffCFxbm28+srvmk+l6dCnVR3b/Wcye6HCMPPaal4BtfggKljwOE2be40MvySf29do11P0Yq1tLq03R3AaxPv57Bupp03Bwj0zHpSXX3rFW0Rtp4ceeqgrWPjYxz5GwUJthIxCAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEml6AQoWmv0UsEAEEEGgOAQoVznU3wm7YKtoUrbfHdegT7xjs8/Iagj1iqTmKIs0Tb6O160rI5w8pt4zUOTPO4XLHY+3k8TXFY+L9/oLD86rWXS44LXeWNWWJieVPWopri+ey45KCtT0pb1qOWGxLfo/Ya/Cvz9pUeJTjK/neTgne0rVF7rn6Ppk/Y2GF2Qrd++yzj8ycOVPGjh1baORsmwrkvYk573zbFIfJETACjS5UuP2u38pTcx8ra33F574q24+qrcir3X8mMxUqXH2JjBgZFioYafdJCea1TT8xIcKPChUKL6RaaBDWHkSh9kTHB9GmVCEcFrXbfFGq4vNgfPA++BlXsPCAvPRi/QULtijwmmuukVNOOSVaX9GieYIAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggg0LICFCq07K1j4QgggED3ClCoEBQqFG2ubtQtiDaImQn8zdzVzJdHju6ez1+znbvWa2fd2QR87+62rvX++muuMcfWLVvlgf/xkDz1m6ezOZmoXXfdVe6991454IADMo8hsHECeW9izjtf466czAhkE2h0ocI9990msx7/W9nFXPKZL8qY0buUjUnrbPefydwLFQqVBRGpLTxIaI4KAdzLqY0JRxQKFQrFDLZL281ZUe7gyVZ5Zu4C8wkLD8iLy1dE/bWeTJo0yRUsnHrqqd68tWZjHAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIBAMwhQqNAMd4E1IIAAAi0gQKGCKVTojs3c9ntB94LVO5/NU2+Oar4381h3HjmqWbONzWPOPHLUsu567293rzuP+fLIYawf/tdH5eGfPppZfdSoUTJjxgyZMmVK5jEENkYg703MeedrzFWTFYHsAo0uVPjdrb+SeQvmll3QV75wrQwcOLhsTFpnu/9MZi1UGDlyeETkCgbM61+hcCDs0mIDryrBvUxG7VGK4O1O1F4oUrARmtemcT3ha23hPGgIpomfBwULd8+4X15cVn/BwsSJE+Xb3/62fPzjH4/WVbgKzhBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEWkmAQoVWulusFQEEENiGAj2+UGFG+IkK2/AeMDUCCOQrMPumufLgD/4q9lMWsjwGDx4st9xyi3zwgx/MEk5MgwTy3sScd74GXTZpEcgs0OhChX/92f+U1W+sTF1Pv3795etX/Y/U/kod7f4zmaVQ4UtXXyojRg4rUNkCA1sfYI+F1uLnfl/ReTDAFiO4sXr08pQUKtg+E+wXKphh4SNci3sWNNq+real9LlnFshd0++X5cte1uCajwcffLArWDj99NMpWKhZkYEIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIDAthWgUGHb+jM7Aggg0DIC1RQqbLU7lcxDNz0lXWRajG2vZZw/R1puP8aez7rxcbEblSs9Ru45Qi648xwXlrSdOW290TpiE2gOf5zG+qF+v23XmGifmG0s7BqzzxJjdD4XEH6J5/b7kubxc/hjNdYf7/fbdo1JW3divx3nJw3P47k1RHPY5/48miM+zo93Ocwgf+uf3x/ly2Btc+mcLm/4JT6/9uk80Rxhh+aIj9N4HR9tItRx+rMXBZiTDOvW+YqHxVdV6NV1+BF+Dn/dGlsYbZfkj9y23yPz7lwo937jz7Jl8xZ/iann/fr1k1//+tdy9tlnp8bQ0ViBvDcx552vsVdPdgQqCzSyUGHZ8sXyi99cX3YRo3fcWS698KqyMeU62/1nst5CBWtXeBX1igbMa2vUXnQeaNvXXtsffw12+cLX5aL+ohyFeYrHBzMGw4MY+7r/7DML5W5TsLBs6UvB5HV8nTBhQlSw0KtXrzoyMRQBBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAoLsFKFQIxe1/TH/p5XU1+ffuvZ0M7OgjHR19pX//3jXlYFDrC7zy6jrZvNnfplm4phHD+8vgwf0KDZwh0IICtRQq2Mss3swUXLi/cdnvT2v3uTTGH5fUb9vSYjS+2kKF5J/wcLNYuMFLc+s69bluHPNzuLZwXDw+Gqd5zetUydhCkDvzc+h8tsMfp0PsMcknSw5/nB+flNvv99dkJo/C02Iyr7uMjZ9D1+3PFy3CetgnCfejsNJCv/21wUW57Vjz8NuCluCrnztqz5ij4rrVMiWfm6/CdaWuW3NHiy4UFdgm38bPoWu2ManeFdZkx1a6H/6cLj784s+v7f464ut+4aFlcueV98jmjZs1vOyxd+/e8tOf/lQuueSSsnF0NkYg703MeedrzFWTFYHsAo0sVLj5Dz+XhYueK7uY/fY5SD5x+gVlY8p1tvvPZJZChauuvkRGjhxeYDKvme61LXwBCw7ma/Aner20A1yfjdfR4YltCV569agBdngQZI863s+lkcnjC/k0j8Y/97T5hIU775elL9RfsDB+/HhXsHDGGWcIBQsqzBEBBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBobgEKFcL78847XfK1b/+l7rvVq9d2MnLEABm7+zAZO3ao7LnHcNll58F15yVBcwvMm79afvbzOamLPPXkveT443ZP7acDgVYQqKVQIb5ZSa9TNwwn9du+pHYda4+VYsrl9/PkVahgc4Z7wFz6pM3T2p/Wl9Sua00aq20aY49JOWxcUruO8/PE40r6bEDYqH3xMZrXHm2M369johi72y22uV7H2aM/NhoTnvi54nGV+uLxSbn9GD+fH+vH2HYbF2/z4/08SXHan9aX1K75k8Zqm8bYY1IOG5fUruP8PPG4LH3xMZrXHuNz+/n8uHgOjYu3+2M0xrbF45L6Vjz5itx++QzZuPYdP03Z8+9973vyzW9+s2wMnfkL5L2JOe98+V8xGRGoTqBRhQoPP/oXmXn/9IqL+dhHzpJDJk6pGJcW0O4/k1kLFUaYQgUtDLAvmK6EIHwBC8sJ3Aup325NXYgWHIQNGu+/xw5yB3dB2+1Rx7uhfpDNHXSGx2BsmKGoLcoXJJHnzCcs3GU+YeGFJcv9QTWdH3TQQa5g4cwzz6RgoSZBBiGAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAALdJ0ChQmidV6FC0q2zhQrHHLWrHDJptPTryycuJBm1ettz81bLv/0nhQqtfh9Zf3mBLIUKUy49TCaeM95sVAp3UcVSZi0giA2r+anOZxMkramaQoVP33lOsHErXE1847PdcF/0iBmoiIvSWC9G+22OaN1ev21PivGvK1Num0gfug59bo/enEnzuVV4HXqaaW5vvqJ1e+1J88dkLZC/4qI1u0vwepMsdc02rJp1+2t2Y3UdaWbeOtypxmu7N8426bqqWZPv5eew53rt/roz5baD9RFfs2331q1rts06nz1Pisk8dzhn0br9dSTM73K7icMvfnxsPe6pFxut2+RdtWC13HLxdFm/cr0XUf70yiuvlB/96Efmkn2N8mPorU8g703MWfLVt+Lk0Sccf6Icc8T7kztpRaAOgfwLFbbK47Mflrtm3mb+rd9SdmWDBw+VKy/7hvTu3adsXLnOLD+TF1/wRdlpzC7l0jRtX6MLFeyF29ek6FXJnETPvHP/ZUtfw6JxYae2K6aOKW2PZnOh2u9avbU89+zzpmDhz7Jkcf0FCwceeKArWDjrrLMoWNAbxBEBBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBoMgEKFcIb0shCBb3ngwb2ldNP28f8dsnR2sSxTQQoVGiTG8lllBWgUOEc56PbsKKN0fEN0XFF3ehl282grfHf7a47vky3zR1tmrbx+qgQ4zaDZcmt+eyx3Lpj89W2bnM1IVbSdbkNc6aj3PWGwwti5dZsr8m3dpcY3SXbax4mY5jUHsrNHUaXxDR83VnuY5JD7J7Fr43vEXtHzaOCk/0GWfPSWrnlojvkrRfXBGMyfD3//PPlP/7jP6RPn9o35maYhpBQIO9NzFnyNQKfQoVGqJLTCuRXqLBVXlqxXP784F2ydPniTLgffN/JctSU4zPFpgW1+89k1kKFkeYTFaKHef1yr+Xe+xh9X+OaYq9v9vUuDPXe+5iWaLzNF2UPcpundg7XHHYGh0Jg8hibJ4hxayykjXJFGYLkMv+55+XOO0zBwqJlXnRtpwcccIB861vfkk984hMULNRGyCgEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEECgYQIUKoS03VGooHfx4PE7ylln7Cu2cIFHewhQqNAe95GrKC+QtVBh0rkTyiayG6jdFqhox1LZ8Lo6dbN2fNOUJs38iQrjRsin75yqw6Kj3QYfXUbCnvgosJYTL7l3WjmTCd4aLcpbX9pIf93euKRwd+/8HWpJQTW2uXulm+Iq5fDXbGPDdVfl5M/hDfRO/YjUc38pSXxF+fxgmzFpQOpMCR1ecu80ITDWZIIrfY8U5bNP9FFhzU3zPWLXm7DuouvSa9JY79rWr+qUWy++U1YuWOVHlT3/2Mc+Jr/97W+lo6OjbByd9Qtk2cRczW9bz5Kv/lWXZqBQodSElnwEshQqHLDfBBl/wCGuIG+L+ZSErq7NsnnzZuncsF7Wr39bVq1eKa++vkLWrVubeVEdAwbKlZd/U/r16595TFJgu/9MZilU+NLVl8qIkcMKPOY9knubVPJeySs4sDE6ouhcG81bD3+8F+O367mdMAw3CfzzIJ/GxY+F2WJx9mm4QB0zzxQszDAFC4ufXxYfVvXz/fffPypY6N2bT7KsGpABCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAQAMEKFQIUbuzUMFOOWb0IPn8pYfIoEEUKzTg+7rbU1Ko0O3kTLgNBLIUKhxx2WSZeM74iqvTAoJ4oG5asu1+TFq7jvf7/bHxdo3XY/ZCheFy/vSpdouWDg33QAc7of32KMCc6KcnxPuT2oNMpfk01s9bcl3BMBdSGl88u/YXt/rZk9et42ykP1bb/TYbo+32XB9F6y675uI57HjNF59Hc2t/fKS2x8cltfv3QPPaY63r9vPF59f8SeuwfdW0a6zmtMeiNduGst7FqyvkK263afShMX6EttmYpHa/zcb48fa5fRStu+yai+ewYzVffB7bZx/aHx+p7fFxG9/eKHdccbe8/OQrQYIMX4899liZPn26DBvmbS7NMI6Q6gSybGKmUKE6U6LbSyBLoULeV9y3b1857+yLZffdxtWdOsvPeN2TJCToruKhXAsVvGIDW1UQvVMtOteLNf1hgDt4Mfr6a49FOaJ4cxJ1BPn8MbZFn+tsevTbo/n1JBw377lFMuP2+2TR80t1WM3H/fbbzxUsfPKTnxQKFmpmZCACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCQiwCFCiFjdxcq2Gl33WWIXHHJJBkwoE8uN5Mk206AQoVtZ8/M3SfQKoUKaQUOSVL1FSoUdlF7W7qiafxN6rZRY3RTtAYmtWubjYnHx8fp86yxfj5/Hs3j9xdWXbwOHZf1GjW3PepYv614zkKPxsb7tb0QWc/6Ctni82j+QoS2BMekeD/W7/fbNUtWPx2bls9v19z2qOP8tiyxfkzlHIWIpHFp12jX5Mf7ayxkLLRmifVjKuXQ/rT1afvmdzbLjC/OlBceWlZYTIWziRMnyj333COjR4+uEEl3rQJZNjFTqFCrLuPaQaC7CxV69+4jU8+8UN4zbp9c+LL8jOcyUSxJ0xYqhJv6XZ1A+CVoMk+CP+4YvfL7RQD2GnVMeK6vgV5YVGQQFSronG5slDnMFX9uMtp1+Ak926A5SKTnhdBgrCaebwoW7rzDFCwsfMHLUNvpvvvu6woWpk6dSsFCbYSMQgABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBOoWoFAhJNwWhQp26gkH7SCfOb/ybx+v+06ToKECFCo0lJfkTSJQbaGCXzAQvwS3QcrsV9oa7AaOugublqImd+LnStoEVdQf7dgqzmGfFcWZyeouVIitXzdZFWYOA9zerGCDlt2ebf8UPYr6bU8YY9p1M1m0CduO1VSaJGxLi9X2IHOYW8e6o5/QJjOPtDUFvcHXtBjTbucsu2abIeO6XZ5wWYXp/TVrMnNMW1NhoInxx4Ye4ZqDTOFk4fr8odG9C+Pj11iddTCby1+07nBN/sRF/eG4cH06Z3wt/vCs1kHmhPkD2DClndg80tYU9AZf02JMe8n3SJTTS1DhGvXa7Qj/5zvI4CaPJTNP09bkRfoxWzZ3ycxvPSDz71zoR5Q932uvvWTmzJkybty4snF01iaQZRMzhQq12TKqPQS6s1ChV6/ecvbHz5d99z4wN7wsP+O5TeYlaspCBe89S/SqZtqClzLzNfgTvbbF3ydrnDuaa/X7vdRRu+1PivFfb/1+fU8V5LJjPdDwtNBWyK3xNqQoXzhmwbzFrmDh+QVLwpbaD/vss09UsNCnD78konZJRiKAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAALVC1CoEJplKVSYevb+MnHCjrJp8xa3MaBry1bZuGGzdJq/b63ZKCtXbZBly9bI84vfFJsv6+Oyz02UffYemTWcuCYUoFChCW8KS8pdoJpChdINw8XL8Tck+cUKhY1MxfF+Pn+sRlXqt3F+jI6bdeMT8tR/zdWnqceR44bL+XdMLdpIlZQvSODv0ErY0O1fsD+jf/FejH+96XOGM3s5/NjKORLWbFN6+UqqSnTtSTEmnW5o89ehQ+LHtPVpe3Khgs1S47qT1myzee3VrNtfX7YcldadVCjgFmgvOnjwPeIcKntXsjZpPMtQN/zWCsea/q3mPd9D//x3mX1T5X8vNMfOO+/sPllh/HgKUtUkr2OWTcwUKuSlTZ5WFOiuQoUD9psgJ7z3RBk5YvtcmbL8jOc6YZismQsV/Fcz+/7MPbfvW4I/0etW8FamEK1xUYuLD555b3ui90D2ddXPUYjRd3YGy8boDXAnOsZ2RT0uovBU59Sj7S49j9K6ru1k4QJTsHDbfbJg/mLtqvm49957yze/+U0599xzhYKFmhkZiAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCFQlQKFCyJWlUOFTUw+UQyaNrghsCxfuf2CZPPTfL8qmTVsqxo8ZPUi+etXhJf9Rv+JAAppGgEKFprkVLKSBApkLFaaOL/wm/ZT1+JuY/D3C4Z6kolHxDeP+WA30Y5L6bZwfo+OqLVSw43RrVvTb6zVZdAw2XZkZo5bgJK3dD7MxxePcfKY5af3+SD1PW59tT1+zHZ22vtI16VzBMXmc3odq1h1fX9q1lM5fbFZYV1K7jk5fdzVrttmqX3fy3On3QNdsj6X3ozm+R+za0ryTr7d7v0eS1ldqaaMKj9J1238zHv7XRwshFc5GjBghd955pxx11FEVIumuRiDLJua8CxXGjd1LRu+4czXLLBtrv/+PnnK8DBo0pGwcnQjUItDoQoW+ffvJ+VMvkV13HlvL8iqOyfIzXjFJDQHNVKhw1VcvkZGjhrur0NfL6JK0UMBWAQR/wrcQ4Tsn9/KVcG4ThC9t+t4hfBr9/yLsXDZt8Cg+t21Bar89DDU9Ok7Xq0eNcOPDII21Gf3zICYY4Y9faD5ZYfptfxL7SQv1PuynHtmChfPOO4+ChXoxGY8AAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAghUEKBQIQTKs1BBzV99bb385PonpbNzkzalHv/xikNlj7HDUvvpaG4BChWa+/6wunwEshQqTLn0MJl4zni75ah40tjT5I3gJaNKNoDbpP6mJfs8nqtSvx1jHzZu1o2PZ/oN6fqJCsHIDF/tfu2Saw7GFTZjhXm8vd0lw2I53IiSoDBPvQddhz+naYum89vtXBofnkbd0Ym3oCiJ15bXaVJu0xY1++uxjeFDT6Pu6EQjzDFK4rXldZqQW4t22v57xBrGvRM88qJOvI9mvmhKfy22MXzoadQdnsz97bPywPf/6j5lQWPLHQcNGiR/+MMf5CMf+Ui5MPqqEMiyiTnvQoVq8lVxKYQi0BCBRhcq9OnTVz72kTNlwkGHNmT9WX7GW7l46LrrrpMrr7yyrF3mQgWTJXrfYE70Ncu9Hw6fFFptcDCtO8Tjw1yF99JmpCbUgS7Gbw/y2a86Ln4sRPgxhVaN93PEzzX6+YUvuIKF+c8t0qaaj+95z3tcwcKnPvUpChZqVmQgAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAgggUF6AQoXQpxGFCjb1suVr5f/eOFve3dRV9k6ccPxYOfnE95SNobN5BShUaN57w8ryE6i5UCHa4FRYS7y4QHv8jVTx31IfxRR2TJUUKdgYf7NT6jxhjqoLFXTnsptIVxQ7JsWYtqJN6GrixWq/S6398Xm8eG+/WGEBaf1p7YWRwa7t2HxuTXasWY9bkq7Ly5e4bo2z+bzYxDWXi9Gxfj4brw/tt881xrS5ZvvFtHnfLtFaon4bouP8HPbcBdkT8/Bjgpbgq8b4/dqWZZwfY8appVuT5vTyab8bpv1+DnvuxSeuO60/rd3m1IfGeHPX/D1ic2oezeu36Zx6TItJay83zoxxw+wXswa3jIS1qHfS98jCexbJvd/4s3Rl+OQsu5S+ffvKL3/5S5k6daqujGMdAlk2MVdTWJB3vjoujaEI5CLQ6EIFXeQRk4+TD59wij7N7djuP5NZCxVGmE9UsC9P/ntbfdEKXpuCFzF9CbNvakrOw4aoJ3ruEkfxOofm1dc+bdcX7Xi/3nSXX3OHgwtjNapwLZo/6DGjY2N1RDyHfW7/2oKFO26dKfOefV5Daz7uueeeUcGCfb3mgQACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCQnwCFCqFlowoVbPo7ZiySB/6yvOxdGzN6kFz9pSllY+hsXgEKFZr33qSt7MGHlssWs0n1/e/dPS2E9phA0xUquM3Gbrtx0Ur9DU1JhQp+f1WFCrcnbDC2m6pKl1BYj9evYeE+rEKMd2Y3RutGLa852BumCYo6anzirSsxg9fvNmub51Wv28uROEe1jbqAcg7enJXWnbgJ3a7Jy1HtEhPjq8jnLi3teyBMzvdIonKhsZK311/v98iyv78od37xXtm0ofInZ9kF9urVS3784x/LFVdcUVgvZzUJ5L2JOe98NV0UgxDIUSBLocJ7j/6g7LnHPqag/h3ZsHGDbNzYKa+vfFUWLHpO3n57TebVHDXlePng+07OHJ8lsN1/JqstVIgKEOxrmH2jEvwJKO3Gfdfsvro2fR61hCdFxQThGI3R98fB+1DNaacyES7InGmwbY3OwxiXz01v+gqd/nkwZdCn8wQjdJyLKMrtj9FzlzOcwn3Cwq1/kueeWRgkqeOrLVj4xje+Ieeff74rMKwjFUMRQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBEIBChVCiEYWKqxZ8458958elq6uLanfeH369JJ//v7xqf10NLcAhQrNfX/iq7v/wWUy/a7FcsjE0fKpcw6Md/M8RSBLocIRl02WiVPHm737wW7ycJtTlDFq1w1MSZvO7cYj066xOlg3OvnFB0X5ww1Lfn+4s0pTlGx8ylqoMGLccDn/tk+aPP7mqihttF63nnAdXm/RaXDJyT5FgQlP3KhgqOmNTnRZdttYYZTpDgwLbcquQWpVzbqL5tBEFY5aFBCEFa87nk/XFF2UGZS67nhHwjr0+yg+T0JoSVPmdUfWNkXobQ4FedMcxlRjHWQrymKbyj6cbkQcnUSLKXII1xR1msxxUr0f1ay7aI6yqy10ZrY2Q3RNmdYdv6DClNFZPd8jr8x5TW7//F2ycc3GKF+lk2uvvVamTZtWKYz+MgJ5b2LOO1+ZpdOFQLcIZClUOP2Uc2X8AZMS17Pg+Wflznv/KOvWrU3sjzcef8yH5L3mb16Pdv+ZrKVQwb6p8F+Lo3cH5nVO3yP7/ratEFPo0VjX58Vou43Ucz+HawsTar+LLczivyxHOfx8/rmfw7bbR/CSba8neO5/1Xh7dOcaEx4XL1zqPmHh2afrL1gYN26cK1j49Kc/TcGCfxM4RwABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBGoQoFAhRGtkoYKd4ifXPylLXnir7C36/neOk46OPmVj6GxOAQoVmvO+JK3qvvuXyox7lrguChWShNLbMhcqnGMKFbxdx942qaj4QDcbudm8vdT+XqeiHN6OpaJ2HaCblUxCv9/fMeWliC6yqkKFW02hgpckOtXN3vY6zDrc9XrriSYLT/z1VYr1x3qk9iL9rugyo3z+mmxktNjCqUuheey6vZji5MGzonVXiPXH6xSuzX/iGUVz23UXxRSC3JSx6yraqOZPqucaHz6P5tH+Mkd/GUXehSVFZm7NZi738GyiU12HjbHWwZdwQOmhyMBGe3OWRnstbp7wuVuP+xI0hDmiuV2sN8CbJDq13Qph1x11eHN6p1GsaasU6w0r4i164l13lM9fk03irUlP/fvhxnl5/HnduTqEHdE8JYGlDUqzevEbctuld8q619eXBqW0fP7znxe7UdV+ygKP6gXy3sScd77qr4gRCOQrUG+hgl3NBvMJC7+79VeydNmiTIs75cSzZdKEwzPFVgpq95/JrIUKI0cND6jCF7jgYF+Q3Z+oL2oPYd3LnmmMXv7Ck+g9gInTc43R17+So81pgqJseq4DNVcY5w7heu25fUQ5gydFbe5J+EWvIzY8Gu/WEXZqziCZW6I7Xfz8Mlew8MzcBX7qms732GMP+frXvy4XXHCB9OvXr6YcDEIAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQR6ugCFCuF3QKMLFW7+3Tx59PFXyn6/ff3LR8iOOw4sG0NncwpQqNCc9yW+qnvve0HumflC1EyhQkSR6SRzoYL3iQo2cbSxyZxHv7nc34FkNgoXPczGJ3/Ds+3zNyP5fX5uu3nJPvz+wraloM+f1rZUXahgB8WT6G5l22cfbh3hYoIW76vbFV14Xja2EBadRVbRSdSl1+8WEF+Tjaq47rQ128F1rDtaanRiEwaPoinNk4rrjq3DZolfV5g6OMTiq/GOlhudFDJXWnd8TRWvq5C6ZN3VrNkOjpYbnRSSR+s2J1nWFI+JX1chczCxP2VN6/YThMmjNdvnWdZtcsTTNGrd0TxbZe2Kt+VWU6zw1vI14cIrH8455xz5xS9+wW9rrkxVEpH3Jua885UsmAYEulkgj0IFu+Suri65dfpv5Nn5cypeQZ8+feTC8z4vO43ZtWJspYB2/5nMUqjwpasvlREjhxW9zym8tJp3wPrEHAsvc947Y9PoQiy2jdFn3nlhnM0RRKce9abp+CBcW0vGRx12es1tG3Vd/uRBs+2NYt0T/7mdt2RMuAi3Jr9/O1myeJnc/sd75ek58zVVzcexY8e6goXPfOYzFCzUrMhABBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBDoqQIUKoR3vtGFCrfesVAe+ttLZb/PvvyPk2WXXYaUjaGzOQUoVGjO++Kv6u6ZS2TmfUv9JqFQoYij4pMshQpTLj1MJppPVIg2Q5msWpxgJ9ANRsXFBBWnjsbZyEpjC3O46LLJZ934hDz1X3PLxtjOEXsMl0+ZT1SI7Y9y49xe5WjDsmkKN0u5ztgXP8zvCrdZ+U1F50Xjip5Y06JQ98SFhHGp/TZSc4U5ElIV8rmzwpe02EJEIX1JEjM4aXymdeuabdKUPLoGP1TbkubVPj0WjfOeZLFMjfHylFu3H6brscdK6y4aV/Sk8vdI0nqiFNFJsIi0dfhhuu60WO23x6Jx/hMzOGm8CwnjslrbeZJylcxvG8wjLTboDb76S9WL2PDGBrn9ihny+vxVfmjZ8xNPPFF+//vfy8CBFKqWhYp15r2JOe98seXyNGeBLVu2yPr162Xt2rXu79tvv+2OnZ2d7mdp6NChMmTIELFH+3fQoEE97tNL8ipUsLfOvu/6w+2/lufmV36/NHLE9nLphVeZAqz6fvt8u/9M1lWoYG+KeQF0r1X2hdD+iV64Cu/A9f1wEB4FmFj/3PYGD223Rz23PXoejTInbpaooXR80FL46ufQc2/R/mk0nx1diC0/p8bqpQXjggUuWWQKFm65V+Y+Na+woBrPdt99d1ewcOGFF1KwUKMhwxBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAoOcJUKgQ3vNGFyr84tdPy5ynV5b9DvvutGNl8KC+ZWPobE4BChWa877oqmbcvVjue2CZPo2OFCpEFJlOWq1QwV5UpaKGagsVbE7dBBX/ZfO2b1s9Kq2pUv+2WHeWNWWJ6e61Z1lTlphmW3czr9lapf28Ndu63133rky/8h55+YkVmW/x0UcfLdOnT5cRI0ZkHtPTA/PexJx3vp5+f/K4fvub/J999lmZN2+evPDCC7JkyZLo+OKLL8qmTZsyT9O3b1/ZbbfdZM8995Rx48ZFx/33318OPPBA6d27d+ZcrRKYZ6GCveaurs1y02//TZYuX1yR4JCDp8jHPnpWxbhyAe3+M5mlUOGqqy+RkSOH2x365lEoQHBu5sUvaDZf7R/3pDjO3+Rf1OOGBAOKxoU57LhorJvM5g/jg0SuVdvCkEJMIWlJnMtivrjV6xMT5Q8pzmvXYgP8MTqjHeeSFM0TNIXj3NAgZsni5XLbH+/JpWDB/nvy9a9/XWzBQv/+/QsL4gwBBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQACBJhR499135fXXXy9Zmf7yv5IOGhDIWYBChRC00YUK3//nR2Tlys7U29e/f2/5p+++N7W/ER0bN26WtW+/K+vMpjr7H/+HDOpnfvtoPxkwoE8jpivJ2dW11fw21E2ybv270tm5STo6+sr223dI/37NsVno3Xe75G1js26dWaM5bjbrHTKkrwwb2l+GDulvflNor+iaKFSIKJruZPqMRXL/X5YnrotChUSW1MZaChX8T1OwiXVDUaUCgtJFhBuOzK8xj+eMx+oc9recV4qtpVAhPh/PEUAAAV+gy7x/uPvqP8mSB5f6zWXPx48fL/fee6/stNNOZePoDATy3sScdz7uU/UCGzZskEcffVT++te/ur8PP/yw2E9KaPTDfvLCkUceKccee6z7e/jhh5v/TdLR6Gkbnj/vQgW74Hfe2Sj//qsfy6rVpf8PrPgFTT3zQtlnrwPizZmft/vPZLWFCm5jv6/nb9w3O/N1c74N0a377v2wPgnHujxhm55rbt3zb8dF76V1nBtj28MGbQ8qCMzXKKnr0fF61FFhGvNUcwXj/LzFYwr9rl2n8QfoWsI2nSMcWWRjl/mCK1gIPmGh+v89olcSHG3Bwte+9jX57Gc/S8FCMQ3PEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEmkjA/rf4KVOmlKzo2muvlWnTppW004BA3gIUKoSijSxUWLzkLfnXG54se+923mmwfOWLh5eNqbdz1eoN8uxzq+QZ83fpsjWyefOWxJS2aGLv94yQgw7cQQ48YPvcPuXhHbNx7/nn35R5C1a7v2++uTFx/qFD+8kO2w90f/fea4RMOnh0yaaIxIF1Nm7ZslVeWLomWN/81bLilXVlM44YPkD223ek+TvK/FbXLrnp5udS4089eS85/rjdU/tr6bC/XfqVV9fJq6+ud8Ue60zRhy38GGDun7kUGTy4r7l3/WTE8P6yxx7DpF/ffAtAlix9S+aW+ZSQo6bsIjvuOLCWSxNbRPOn+5eZ396a/D06ZfLOstOYQRVz3zb9efnLX19Mjdtxh4Gy/36jUvvjHaeevHe3fC/G522W51kKFY64bLJMnDo+tUBANzLFCwi0Xa/VfAvHHoUWjS3JEW5Q8jcdpcVq8loKFfz8mkePxZurCr8FPmE/lQ6JPvUhPlYDdL60fhunMTrGHovjjVaB0A9z58Wxldet88XH+Ykrx5SuqTRfaYw/hx/vX1+ad+U1FSz93P6cJqLEMh6r8xSPKzzz43XdaWu2ozSfP66QrXK/n8MfV5yv9LrSY+2cQW/auiut2V9T8Tr8WUvXVBpbGuNn8ON1zba/0evuMu+x7v/uQzLvjgX+csqe29/2PnPmTHnPe95TNo5OMe/RXpR/++V1ZSkuvuCL5r3CLmVjtDPvfJqXY3kB+ykJM2bMkLvuuksefPBB8/4v+X8blM+Sb++AAQPk+OOPlxNPPFFOOukk9+kL+c7QPdkaUahgV75y1avmZ+/H5n/7mEL3Mo8hg4fKFZ/7qtm8PaBMVHpXu/9M5lKooC9k5hhsztet+aGrbQ+aiqD1ddGNMv36Xlljbb/G+AODdr8lHOvlCBZSeA+anCfIEfSFa/bWWTzG6/eupzjGz2fXZB7mSzgyNAieReszJ0tfeNF8wsK98tSTz0bvs4JM1X/ddddd5eqrr5aLLrrI/NKH2r7nq5+VEQgggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAghkE6BQIZsTUY0ToFAhtG1kocK//2KuKxAodxvHH7SDXHj++HIhNfe9+tp6ucP8Vvl5ZvN9tY/evbeT447ZTT78gXFmo0ltG91tQcRf//sls/F8qWzYsLnaJchuuw4Ru0H8PXsOr3pslgF24+Kcua/LXfcuMZtv0j/1IkuutJi8ChXsxv05c1e6YooFC99wn/iQNqff3qdPL9lz3HDZb5+RcuikMWKLQep9/O3vL8kfb1uYmuaSzx7sijhSA8p0PPLoCvntH+anRlz46fEy3hTSlHvcesdCeehvL5ULqbrvR//zfYkbd6pO1KIDMhcqnGMKFfwdwd716mYos7U4atW2qCE8KUTYhsIzjfdz2O1IusHKn1tjgwyFHOEUUm2hgp9bc8SPunkqTqDr8+P9fDrO77eX7V9nUoyfwx/rrt3uy4rl8GP8c83tr9tt6wr3dkWxsXw6Luqtq0iBAABAAElEQVQ3J/E1ZYnR8Robz6H9/lFjbVvRuuNrdv2F+x/Z+MniMUk3LBbjD9e1VLVuZ1nIkjSln0/nKIywC7J/vGtLSOLn8MdGDrEcfox/rvP71ra/ZMpYPh3n54qvKUuMjtfYeA7t948aa9v8dZes2fUXHG28P9Y+tw9/zqT+ohiT7m//8rDMvmmuG5vly5gxY+See+6Rgw8+OEt4j43JexNz3vl67I3JcOFvvvmm3HzzzfKLX/xCHnvssQwjtm3I5MmT5YILLpCpU6fKiBEjtu1iqpi9UYUKdglzn31Cbp1+c8XVTJpwuJxy4tkV45IC2v1nMlOhwlcvkRGjhru99dHrTfT+xryC65s0cwxOo87ouYb4xprLvgeIcpgAfV20/Rqj4/z8Gmf7NM7mCiYNRkTtfnCYLGjSuV2WsEfX4PcF/W6M+eKn0zl0sH3uX687D9cV9rg1answ3hQsLDEFC7fcI7OfeKboNV7zVnPcZZddXMHC5z73OQoWqoEjFgEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAoKECFCo0lJfkGQQoVAiRGlWo8OBDy+X2OxdVvBVnn7GfHDll54px1QRs2rTFzP28PDxrhdhPC6jnMWRIPznr9H0rbg6Pz7Fo8Zvy/34/X1a/sSHeVfVzuzH9tFP2lpEj8vsthS++9Lb8/pb5Yo+NfNRbqNDVtVUeffwVV+yR9kkUWdfft28vOfrIXeWE942t69MymrVQwW5E/eNtC+S/H345K0nmOAoVVojdgFPukeUTFfxN1Zor2kAUNpT+i1Vo0djiPKbV7DwKNiKXxtq0xfHBRNUUKpx3yyfC1ZU/2PUVVlAcG2yOCtri69Hr0o1e/oZoP4u/MSstRuODtaStRqOCY13r9i4sbU3VrLt4ZenP1CzpCr0lldx7HafWdoakdTdizXauuqyDBPZr4ppdt7eTL+m63OAavtS1bu+GpK2pEd56r6v9HnGO9hukwrqzrPnxn8+Wh3/6qP1HKNNj+PDhMn36dDnmmGMyxffEoLw3Meedryfek0rXvGjRIvmXf/kXV6DQ2dmYwuBKa6inf+DAga5g4Ytf/KLstdde9aTqlrGNLFSwF3D7jN/KU09XLjQ5f+qlMm5s9V7t/jNZbaGCe5PrXpIKr0v6+lb0UhW+/ruXLt24b29Y+FoWb/dfw/TcHvXcG2pyBEnCQxTj1hHmt/H60Bx6LG3XFnv0c9v5/T47tWkwfxPbdXTYb4cGL7duZcG4MF1hvM1lI8OJzMF+wsLt5hMWnnz86dT3V2Gaioedd945Kljo6OioGE8AAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAo0UoFChkbrkziJAoUKolHehgt0s+/dHXpZbbl9YsUjA/nb7b3/tKLG/9T6vR2fnJvn3/5wrLyxbk1dK9x/zP3HmfjJl8k6Zcj7z7Cr55X89I/YTFfJ6bD+qQ774hckysKNP3SnnPP26/Ob/zZN3N3XVnatSgnoKFRYveUt+89vn5I03N1aapqr+fv16y0c/NE6OP273qsZpcDMWKtifO1t4YotzGvGgUCFDocKlk2Wi/UQFb0duuE3I3RK/vZp7FG1yMvc4OUe40SicRXNXmruqQoU/mkIFbxo/t85nj0XrC3ZKFY1zsQntfr5MOfxJ087tPN6abZg/jz8s05wV8mXK4U+adJ5gY8OS1p15vti647ky50lar7YlrDs+TyFUg02LnsbuU1K7ny+XNdsFxWxskz+Pfa6PTHNWyJcph06YdkwxS1p30Xw2X8rYSg5FedJypK3XtD97yzx54Pt/la0ZC0ftxsbf/e53cvLJJ5fJ2nO78t7EnHe+nntnSq/8qaeekh/84Afyxz/+Ubq6Gv+eu3QF+bb07t1bzjzzTPna174mEydOzDd5jtkaXaiwYUOn/ORn/2Q+La980cnIEdvL5Rd9WXr3ru5/u7X7z2SuhQrm+6awAb/wxL53jt5ahCfu4LVH76/dsCAoGhcmLeTQfvuNanKHHX4O26MPv13P3RDNGyW2I5JzF+UyIZqnqD0c7fpsjHm+VfPZwKLrtQ32YddvI+3f4sOypS/LrX+4O5eChZ122skVLFx88cVCwUJAzVcEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAIHuF6BQofvNmbFYgEKF0COvQgW7UXr5i2vlzrsXi/00gSyPU07aS9733to2iyflf+utjXLDv8+R115fn9RdV5v97/mnn7qPHHPUrmXzPDdvtfzHL+dWLNIomySlc799RsrnLjxYevUKNxakxJVrvu+BZXLXPYvD375eLjKfvloLFf7y1xfljhmLGuKoV3bIxNHyybP2F/tJC9U8mq1Qwf6G7t/+Yb7MeuyVai6jqlgKFZqgUMHcseTfxu7/e6C7iN02pOgeF200DlurLlSw44r2NPnz2o1Rhbn9UzedhnohRe1205RpCLrDoHisHaB53OAyX/yx3hhv21o0uOp1e/lUOVOOaMaUE3/NNsSbp6p167gK+YJuL8g7dSvUPCnLjZrLjCu77rRxae2ORD+xwwvyTmtet3etZddsJ0ibz2/38vE9Epgtum+JzPz2/dL1brbN2n379pWf//znct5557nbypeCQN6bmPPOV1hpzz2bPXu2fOc735E77rgj5XW7tW3sJudTTjlFpk2bJpMmTWq6i2l0oYK94NlzHpU77v5dxWs/7ugPyvuO/XDFOD+g3X8maypUMEBub3345sjftB+0h4LmiXsJ1qNtDl+TXU90bvMVXqz13B51fDQ0aHATBEM0JnyFL6RxMW5cUu6gI8wfhZqTIEGU28un67IhRetPze8mccldGhOnoYW0tq3wLAgOrknbly19yRQs3CNPPDa37n/DbMHCV7/6VbnkkksoWHDYfEEAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEOhOAQoVulObuZIEKFQIVbIUKhw8fkc5dNJotz9vS9dW2dy1xX1awPr1m+Ttde/K6ys75eUVb8vate8mWSe2DRzYV675+lHSv3/vxP5qG+2nF/yfnz4hL7/8drVDM8fbAoEvXH6ojN19aOqYmfctlbtnLkntr7fjYye+R95//Nia0jz6+Cty8+/m1TS21kHVFipsMb9x+b/Mpyg8Ofu1WqesatwuOw92xR/DhvbPPK6ZChXsxvWbfzdfHnuicUUKFoZChWyFCgefc1DJ91Gw9Se2kb8kqnxD+Rz+ZqPCbmkdYzMXbaQPp6qpUMG9CvjzlV83va0rYL9n/O+h1r2SrCu3Pzt8b2fVsnHVfo+8OOtlmfHle2WT+eSrLI9evXrJj370I/nHf/zHLOE9JibvTcx55+sxNyLhQhcsWCDf+ta33CcoJBcWJgxq4Sa7qfmMM86Q733ve7Lvvvs2zZV0R6GC/Rfw5zf9VF58aWnZ67afQnHphVfJ9qNGl43zO9v9Z7LmQgVFijbfB6/Z/p573Whvd+dHr+hF50ES1+e16zjbrucuRyGJfeoeUWbz3J1HMUG//Rrl8M5tWNTujYna/P7YuXlqJ3PzufhwvD/WxdiwcKHBwaxQYzXAZtHGqC0YF29fvuxlue2P98hjs+bUXbAwZswY+cpXviKXXnqpDBw40JuZUwQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQaJ0ChQuNsyZxNgEKF0ClLoUI20uxR/fr2lksuOlj2HDc8+6AKkbfesVAe+ttLFaKC7j59esnoHQfKjjsOsvtM3Ccw2GILW+xQ6bHDDgPly1dOFnsNSY9GFypsP6pDvnn1kUlTl22zn3bxk+ufzHSNmmjnnQbLrrsMkSFD+klvU6Tx1pp35I03N8qrr62XdaZAJcuj2kIF+8kAjzy6Ikvq3GLsNf7D5Yek3tP4RM1UqDBv/mr52c/nxJeY+3MKFSoXKky59DCZeM74VHvd2BQvGii0+0MLBQd+q8b6bcX5ChF+e6G1ULRQfaGCvyZvh5W/mDrONXtaZt30Gd9EVXlKzWwj07JXzpIUoZnLZa1/3eWyJ62qcluldeuadVNc5YwaoZnt8223br5H9H7UftQ7mXYXa/0eee3ZlTL9C3fJBvMJWFkfduP3d7/73azhbR+X9ybmvPO1/Q1IuMCVK1fKtddeKz/72c/M++zNCRH1NQ0dOlS23357GTVqVOpx2LBhsmbNGlm9erWsWrUq9bh27dr6FpMwuk+fPnLxxRc7gx122CEhonubuqdQQUyh/ity43/+i/n0t/L/+3H33cbJZ8693CCk/Yta7NPuP5O5FioY0kjVnYfPypxbbRdlNuuH0dHGffs8eg9hc0Qb+k2sBptR7jR8XogJ7qPrjWILOWxTFJvQb0dH/bFz22cn1dwap0fXH37RtmC9hXUXprRthWc61raVtIdzvrh8hfmEhbvl0UeeqrtgYfTo0a5g4bLLLqNgQfE5IoAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIINEyAQoWG0ZI4owCFCiFUdxcq2CKBiy6YIPvuMzLjraoclnWz9qiRHXLGafvIfvuOLPkP8fY3+c95+nW55fbnK27Ct59oYD/ZIOlRqVBh3NhhctihY2TMmEFi19O7dy+zmWiDvPLqOvnzA8tklTmv9PjCFYeKzZP1Ye/xP/2vR1yhQaUx9hMu7PUdfthOMnxY8qcMWKuFz78hs8wnNDzz7KqyxQ/VFCrcZ65/xt2LKy0x6h88uJ/ss/cI2d44miVJx4DeYj/lwxZSLFr8lry7qSuKrXQy4aAd5IJPjTffF5UiRZqpUGH1Gxvk6WdWlix606Ytcte96Z/ssYspzjjMfEpK1sd7j909k03WfK0Wt2JFqxQqhJuYDHArFSropmj7fZH2IxhtjLYxWX5QbTL3yJJdY6s7Vspc+5rtOjR7mkh1a9VozarP/z971wFgRZG0S5aw5GXJGRGUIAIKCmYPFD1FEVHOwBlOBcPhASqoeOpvwvPUO887xJxQQASUJDmIAgoSRJIEUZCcM7vg39Xd1dMzb2bevLdv2UDNwZvuCl9VfzMvcFZN+6Enn7eN7odMURM/R0EuiHknnzNyGIWVxLmOgpx83r/DjrW74PP7xsG+zfsiJ4cFja+99hrgLgsn+pHqIuZU451I1+fo0aMwcOBAePzxx2HXrl0pWTp+vzVq1AjOPfdc+fcPf/gD1KtXLyXYCPLzzz/D1KlT4ZtvvpF/ly9fnuPCY0ouIyNDNhXh+xV3Esir43g1KuD6Jk4dDbO/nRF3qR2vuB7ObH5OXDs0KOzvyUiNCn27Q2am9UAD8b4Qf8ShfluoMU6F3BGbQn4U4SG1woDOSqpRyBftNCBi0RiBzRgnUidf1UyJtFzrtR2dlA/pEAD/yBfpJ2dSrWy0EJdlxY71c/JCO/LCs0DXeOoko6EY/0i9fHU7ObGknbLUDoioPIUPNiyMwIaF2Qty/LmBDQsPPvgg4OdF6dLi4RF8MAPMADPADDADzAAzwAwwA8wAM8AMMAPMADPADDADzAAzwAwwA8wAM8AMMAO5wAA3KuQCqQyZEAPcqKDpOp6NCmlpJ8FttzSD05tWSuhixTN+6d/fwfoNewPN8D/mt7u4DlzW/mQoViy8yG3/gSz4bNRKWLBwcyBeenpReLL/eVCieGwRTlCjQmvRnIANANWqBv+HeNzRYfzEtTB1+rrA2Ki44Nxa0Fk0XEQ9Jk35ObRonXBOb1IJunZpBNgAEPX4QTwd+Z33fwg0j9qosEI0Pgx6C5/SGAhlFNjk0kFcy3qiWcNTZ2Fsjh49BsuW74CJU9bCr+uD7w3jIAZXdKgPl7WrZ4t8x/mpUcE3QSGM974+s0VV6HZT0yB3lnsYSEWjApUIuYuLPYHMVJUF2c0GRpXDASIjbkI7Kgy/QUTVhUsyvsrMLpSitOwCZpJ5z14/+baXb347BnmpDwXjI6axvPj7KamtC8jbF5PiO2eTgxYF5+3JWdj782LnRnF+p5IwEwXRvLFR6Y+p3ayT7Rucs0SUXi573w9lb97enBVWTvK2czCZRb1HhEMsN96cFaqS2rqAe8QXEzHcR6J52/axOSO2nRvF8ufb7wvRH5NwnLOdB0p9L7s0T/bedue8VzRnfn7/WNj5c/Ti7q5du8IHH3wAxYtH/43irLDwjFJdxJxqvMLDdPhKFi5cCHfeeSfMnz8/3DCCFgt2L7vsMujQoQNceumlYse3KhG8UmOyZcsWmDRpEkyYMAEmTpwImzcH//snasSzzjoL3nrrLWjRokVUl5TaHc9GBYz12pv/gL17d4euIT29JNx/18OiILtsqB0qC/t7MkqjQp++PaBCptWUL/7BJ//Np//hZ74ZxUD+YtYC73cZ6WLlgmjE1FeD9DinMSrNWFuq8DoX7YsnE4cQCdjCkyItV7hq4sRwAF1xhBnhOxZ2bjgmDeUmPaSCVHacoLFJ3wFUsRHeykPtsPAlzP3me5/fW5RLtDN+3mHDwr333ssNC9EoYytmgBlgBpgBZoAZYAaYAWaAGWAGmAFmgBlgBpgBZoAZYAaYAWaAGWAGmIEEGOBGhQTIYtNcYYAbFTSt8QqaU8V+82ZV4CqxC0GliiVTBSlx8Mn+A99cGIrZ7pK6cNUV/jsg+DliYd+/XpsPv/y6x08tZV2uPQ3Oa1szRu9tVCgvdiXoel0jaNyoYoytnwCLA/8zcD6s/Tm44AWx7r6juZ97jOzQoWx4+vlv4MDB7BidLTi3TU2520SRIlTOYGuDx0uXbYc3310UaBClUQF3aHjxlW/lTgiBQEJRsmRR6HZj08hcEtb8BZtg2Gcr4MiR8B0WihdLg8f6toVy5cKLILlRgZg9cc6JNCro0iBJjikSlm8rem+JN7mq9ZVFP34s+mKgIUF4neLg2eaEPXfQPFgweLGt8h1XqJcBN4tGBfJDI7tRwC52Muv1RXILg/3sRdLCsNbKkfvHcfQOwUiZIz/eecfPGTlx8vPP28k6Gp6bZ5qRr2TUVKEHxI7LtX/eecm1zChu3gHrta6Bw3aUe47YdZ+Ja5S679XY+MG2NmasH2r9+I6GZ2M7Y3/fgNhxuVYZOujqvWznfGDnQRj9wHjYsjR2VyDHzz3CYu4RI0ac0MWMqS5iTjWe+4oVvll2djY8++yz8m9WVlbSCyxTpgx06dIF/vznP8NFF12UL3YLOXbsGMyYMUM2BA0fPlzsMBd91xMvEcWKFYPHHntM/i1atKhXnavz49mogAv5cfkiGD7qw7hratq4BXS55pa4doX9PZnTRgX7Wwkr9OVcC+3vMSRaaoUuUK6vBunxq818TyG2xkWpwkNQW64ATBxtZ07STftaWArXlhuliiOnOo4YE76KpmM6ybnyJGwFIT01phOD1osKe2zyxgHFVeGcuYZB5PXrN8KIYeNgTgoaFipXrmwaFvDzkQ9mgBlgBpgBZoAZYAaYAWaAGWAGmAFmgBlgBpgBZoAZYAaYAWaAGWAGmAFmIBUMcKNCKlhkjJwwwI0Kmr3cblQoLnYduPfullC3TrmcXK9A39fFU/hXrNwRqK9Tuxz0vPcswN0cEjl+27gPcKcGLKL3O2pULwMP9To7RmU3KmBDARbWY4F9IgfuAPDyq98FutSuVRZ692wdqLcVU6atgzHjV9uimDHi9fpra6vIIcYkUJCKRoWvZ2+A4SNXBMZARcXMknD3X5pDlcqlQu2ClBs37Ye3REPFjp2HgkykHBs2ru98WqgNNyqE0lMolck0KsiCZ/r4kB8/9BkkhC55LGVUViTNqKic3GPN4+LZLoSdaKOCxAjIGzHtAm87XtiYcon1xcVSMIUQbGtF+F2TdJLbV0J5+IuEZ0HbQ//1UgB37EhxMG+/nDEoweoEIuHZycb1owCxecdeFws4jGs0I1grfiieBW0Pg9eLAWJzRt/QOGF5++QcFw8NfA6+RwQpYVwjZ4LvI2IXq3F9JsD6737zYdFf1KZNGxg7dixkZmb6GxRyaaqLmFONV5jpX7duHdx4440we/bspJdZs2ZN6NmzJ3Tv3h3Kl7eeGJ80Yu447t69GwYNGgSvvvoqbNiwIekgbdu2hU8++QTq1q2bNEaijse7UQHz+2jom7B6bfi/ZdDu+k7doEmj8Gbzwv6ejNKo0Ltvd/EZn4GUyUMW04vvDFdRPX6JqD/mNwf9ZlByocSDTrqwn2ysOn+DizKplz5ipM8WjDAguUQ3L5Sb4y9NZQJOLJWMPbfHMo4ykX60Plq/CYZa7Uhn0imxzELlqhWuOGJCYbz+KqbQyj/KKtAGsYXJhl83wsjhX8I3s+Z5GjQpq+jnSpUqyYaF++67T+zyyA0L0ZljS2aAGWAGmAFmgBlgBpgBZoAZYAaYAWaAGWAGmAFmgBlgBpgBZoAZYAaYAT8GuFHBjxWWHU8GuFFBs53bjQrFihWBG8SOAq3OrJby64u5P/rEzMBmAmxO6Pdgm6R3cRj5xU8wc9avgXk/88QF4qm+xVx6alTAHSS63dQ04QYJBMO65L79p0NW1jEXNk2qVCkFj4h1RTle+c+80J0hEKPnfWfByXWTK5bKaaMCPm36iWe+hr17jwQup0SJNPjb/a2gWtXSgTZRFFu2HoB/vzYvdHcJ3FHi0YfbyMaIIExuVAhipvDKozQqtOnRGlrc1Cy8SNqHIiwVii2sVoVBytxdjO0DEShyYSOMBTt30HxYGHVHhU9vCIxhY3rqxoN9EtVYeUvXAEo8SwyOEhEvGCCixo4TkDMiJZV3CF7E7ILNIuRN4W3TQEDbiBwDjZNU2DEQIiAOir2mvhG9RgF4vr6JCCPGydd5B3BDYu8SvfQcFbsdTXx8KqyeutarCpw3bdoUJkyYAFj0faIdqS5iTjVeYb0eU6ZMga5du8L27duTWuIpp5wC/fr1kzsoFC8evnNXUgFyyenIkSNyh4UBAwbA6tXhjc9BKVSsWBGGDh0K7dq1CzJJqTwvGhX27tsDA9/6Jxw8dCB0LSVLloJ773wIypQuG2hX2N+TURsVKmSWF9/X6htEFsqLoVMw73yzmAJ81Nv2xLA2lTqXDRk4uIhlx6CxhpAOlIvjrUZkizMau/GkRhqbnC1bqbUVZi3SSGBKV/OCMSiOEUpTZShf0UYrHX8h0RPUBWGQnM52DBzbchpvWL9JNCyMEw0L88X/P+P//2N4cYLm2LDQu3dvuP/++6Fs2eD3S5A/y5kBZoAZYAaYAWaAGWAGmAFmgBlgBpgBZoAZYAaYAWaAGWAGmAFmgBlgBpgBZIAbFfg+yGsGuFFBX4HcblSgC33RBbWhU8eGNE3JefmK7TDo7UWBWKc2zIR77moRqI+nwJ0acMeGoOPO286Apk0qudQ/LNkKS5Zug65dGgEWvSd7vPDSXNi0eb+ve6WKJeGxvm19dbbwwMFs6P/kV6FPNjyzZVW564Ptl8g4p40Kq9fsgtde/z40JDZ8nNmiaqhNVGW8a4o4V1/ZAC65qE4gJDcqBFJTaBW51ajglA9hXTWV9SKN9meHLXcoJl+3X6weJdgQZA4NnWijgo1BBUkGM5mBlZJruclgCR/XEi36CnreKeEaOSW+LW6SpFq6Ed9O4Zv7PktJ3pQzRkxB3pSzhLPwCvo9gtzQ54G8OMm+EN8WN8lCoR/xHeUe+V3sXjXtua9g6efLI4esV68eTJw4ERo2TO1vy8gJ5JFhqouYU42XR7Tkati33noL7rnnHsjOzk44zsknnwyPP/44dOvWDYoWTWyHtYSD5aIDrv3DDz+Ep59+GtauXZtwJFz7wIED4c4770zYN1GHvGhUwByXrVgMw0Z+EDfdhqc0hpuu/0ugXWF/T0ZvVMgwX/3yNwV+15kvFP1FhTJiUo7VzLETSm0gvyddNuTo4CI82cmRiWdg0Bj/uA7HB9WOUg1te6WzTDz25EtnGU7FxIiOWPmJuYxtZUPxzVnrnJjopIDwlewIguZ0Rrk9lnZ23Jix2GFhg2hY+HQ8fP3VvBw3LGCjEzYs/PWvf+WGBbpIfGYGmAFmgBlgBpgBZoAZYAaYAWaAGWAGmAFmgBlgBpgBZoAZYAaYAWaAGYjMADcqRKaKDXOJAW5U0MRGaVTo0P5kOLVhBTginnp74EC2eCJ9FmzctB9+XLYNdu8+HPkSYfE3FoGn6hgzfjVMmbYuEK5zp1PhgnNrBerjKfYfyJKF/kF27S+pC1decUqQOkfyN99dBNgE4HdUqJAOf3/kXD+VS7bohy3w3odLXDJ7UrxYGjwidg/IKF/CFic0zmmjQrxdK2rXKgu9e7ZOKKd4xm+/vxiW/Lgt0KzBKRXgvu4tA/XcqBBITaFVRG1UaH7T6QlxYBcXxTYcYPkQVQ7HwpJvrJ9jizZSb8MgrDgSb1RALwTSkTUOSs3hEydmCeRn2yIAyQ1YAgOBZcNJKHwxctQG5B3jqOP6yW0ZpZeDvKmQ2wVl8lbBZNZ+MexcbL2f3JZhMNuegidwtvOWUBpPyTFYANcYw86F8rBlaBNPjjaJHiKGHcbkbeSoDcjbdsS4fvn5yShH0tE8gbPNNbq586bERN5+MUhtHHVgP7kt89prt0ROMXnr/ELvEZHDN6/Nhe8/CG5A9eZQpUoVGD9+PJx55pleVaGdp7qIOdV4hY34f/7zn/DQQw8lvCx8Gnj//v1lg0NB2kEh3kJxhwVsOHjmmWdg27bg39JBOC+++CI8+OCDQeqUyPOqUQGTHzV2CCz6YV7cdXRodzW0aX2hr11hf09GaVTo07cH4I4K8qCiejyrPw5vQia/XvR3jJ45hfUeOX1/SzsLiwrxVQhS4HerBtAR5QxjWmLCQpMYe+UgvR0f8lcgjpz8HXBHJ2TqjzybWNpU5iCjKAzKw0FCufRSVmJCOrI1mBpHxSMrhStVWmQQxFyOjZxCnAS/bdgMIz4dB7NmfpeShoVevXrJhoVy5cpRlnxmBpgBZoAZYAaYAWaAGWAGmAFmgBlgBpgBZoAZYAaYAWaAGWAGmAFmgBlgBkIZ4EaFUHpYeRwY4EYFTXKURoVuN4on2osn7/sdWPD96cjlsGfPET91jOzyS0+GDuJvKo6BbyyAlat2BkLd1u10qJCRHqiPonjlP8HFJqeL3RT+InZVSPVxTDxZGHdy+ClgbRUzS0L/fvF3VBg/YQ1MnPJzYHpNGleEu25vHqiPoshpo8IzA2bD9h0HA0Pd/udmcMbplQP1ySg2btoH/3j520DXtLST4JknLoD0dP8n33KjQiB1hVYRpVHhnB6toMVNzRQHcYp+qbjHNBHo4h4XgYgRJLcNTRWTDhrkRz7abO4b82Hh4MUkDTxXqJcBNw+7IbbI2/IIa5awzMTQWZAzUhZeDOKI/EkfJJd2cu1uC71cqbZjEh7hB58dL2ekrP0w3NGxOF5lECSXSCF5R4npn7vj6YwSyztuzgLOLnAL4hqjEg8qg7BXJ1tnpOy9GEH5BcklSgjXqLdjeuOpLPxeHS9npOz8MILyC5JLpHyad2jOmLgn7yj3yIIPF8uGBf3WUUSGvGLB4hdffAEXXXRRiFXhUaW6iDnVeIWHaYBXX30VHnjggYSWhDsH4O4LTz31FFSoUCEh34JkvHPnTnjiiSdk00KiO01goXrPnj1zbbl52ahw6NBB+N9bL8LefXtC15eWlgZ3dLsfalSrHWNX2N+TCTUq0G9c8eUqv2/0l6z5rkU52Qgm6TtJyoytsTZf8lLiU6yPcoOHegubLhTKSEzx8MeDHFuhbHtnrEYKVxkTlkSQIq8cfTSwOBl7Oda2pEdLmR/JVTyJYByVDWnsNZqxcpcmQWsMlitkgyWmmzZugeHDxsHXM7+Fo0ePUeikzpmZmUANC+XL62aWpJDYiRlgBpgBZoAZYAaYAWaAGWAGmAFmgBlgBpgBZoAZYAaYAWaAGWAGmAFm4ERggBsVToSrnL/XyI0K+vrktFEBYQ6InQfeFU/uX7U6uGnAvh3+dH1jOKd1dVuU1PjFV76F3zbuS8o3FU71RQHvX+9NzVN8fxePGV6zdjd8v3CzeBLnFti/PyswxWpVS0PfPucE6knx6YgV8M2cDTSNOV90QW3o1LFhjDwRQU4aFY4e/R0eenQ64Nr9jqJFi8CzT10AuPNDqo/nXpwDW7ceCITFHRVwZwW/gxsV/Fgp3LKEGhX8b2dTY4RMUXGP6963ioJcBbpBcqLcKjwSbyaSuuI5QjHSJqlqVHAVYlvhrZopE9OprnKn58KwkiWeUGTbkNyW0brQ1i6OCk7J0tAwiGuLY7cJOWJU5/DLj2RolWzeQX6+XGMgn7xdGGijj6D8guR+fNtsBPIUbESpmLwDMRxL815Ckb02ytuW+eWs/BzAwJiUt9vAcnQUzsidk2OM97+ysvMjmcqJAoqZNYx3b9t4tl9Bu0eWjV4B05+fBcciFjSmp6fDkCFD4JprrrFpLpTjrds2iULol9w3hrVSvEceuOcxKF8uw5IGD1ONFxypYGneeOMN6NGjR+BvVL/VtGrVCt58801o0aKFn7pQyhYuXAh33XUXzJsX3NjtXTjeo6+//jrcfffdXlVK5nnZqIALWLlqKXwy/J24a6mQURG6394LSpRwN9VzowKA/44KSKn47lR/FL/iXpLfpuorVYzNQI3N1Aykn7QTIiUVM1IbPK2RJ61U0YWTY49gDpawc0xlHKkncLTVeI7IjSXRHKXJSwITPGLIsQRzj2UMxFQ6bYFpmNhyIufaxhXP8tBDuT7LntZIcpWLCUBqkwPGk/kIvI2/bYHPho2FWTNy3rCAjWDYsIBNT9ywgCzzwQwwA8wAM8AMMAPMADPADDADzAAzwAwwA8wAM8AMMAPMADPADDADzAAz4McANyr4scKy48kANypotlPRqIBQ+HS8j4YshYWLtsS9jliA3vPes6B2rbJxbcMMnnz2a9i9+3CYSa7qojYMhCWx7pc9sGDRZsnb7j3R1lK+XAl4sv95YbBS9+4HP8DiJVsD7bpcexqc17ZmoD6KIieNCriTAu6oEHRgowA2DOTGMWr0TzDjq18Dof98c1No2dx/FxFuVAikrdAqEmpUQBaswmJDiqv2R01S06iAEQhcBKbYJDIJ6IHWJ9KocJPYUcF7EHxOC6Nd/t4gYl0Yx2tDxVEuOa1bY2BRlEckNaF5kxItvc52IZdUew0kvHzB/Fy5aVWyeVNaLkw7PBlgHFuO88h5+3MtIfT9FRQ/Ka4VML6qw847cs7o6p93slwrRErJSoqGKeGask7dvU1pBV0jfQlpYepMr5H59ucaYeLxncw9smbGzzCx/1Q4euQoZRp6xifZY5H4bbfdFmrHSmYgHgMffvihvI+OHYv25O/ixYvD3//+d+jXrx/gk/JPtOPo0aMwYMAAuYtEVlZwo7XNS5EiReC9996Dbt262eKUjDGfF199Ag4fPhSI1/nqm6FZk9z5NwYGHTnmE/FvsPmB8UnRod010Kb1BTSV58LePJTQjgrEjPiekt9z+kV9bYmJ+qOs5FgaSDkKpZcRKWP6vjIYaEc2Jo4SkFwj6TiEIANImSzElzgaSFm6dDhx7BwDkimJN672wbwoR9eitRcp7RioQj9lYvxxLXRgbHd89ME/8kWa4TjQBi0cUzGWnsrPmxOFFWfcYWHEsPEwc9qcHO+wgA0LuPMN/s3IiNagJxPkF2aAGWAGmAFmgBlgBpgBZoAZYAaYAWaAGWAGmAFmgBlgBpgBZoAZYAaYgROCAW5UOCEuc75eJDcq6MuTqkYFhMOi2/c/+lHuCBDv6leqWBIe6nU2FC+efEEPPo0/OztaEVG8fJLRR20Y8GLjLhC4cwI2dWCxfqJH1Lj/HbQgdJeLe+5uCac28N81IGpOOWlUwB04MMeg49w2NeH6zqcFqXMk/3r2Bhg+ckUgxrVXnwoXnl/LV8+NCr60FGphoo0KWKbjKhhGdqjQ2WaKina0zPjZti4bPUlg5wQsIFIHDgSwxk6oUWHo9QTiPgtIKkmS63XlTYGdmG5nn5l0IT+ht9fpZ24VQbmaPnxsXaKgvO34cWJ78WSllhTGXy8VfMVw5gKNnZAfalzrNXnHj+1CNX4S0dwbLhuaBHFG+pAz5R2zXnP9cpB3nOtEsTE9F2ch+UpV0HptzuLEdoWw/VARx5fyjuHMBRo7IT8VQvBKh4mfA66tzw+CdZ2DOHMZ+U8ob+96N3y/EcY9OBGO7D/i7+iRIs6LL74Iffr08Wh4ygxEY2D06NHQuXNn8e+L7EgONWrUgJEjR8LZZ58dyb4wG+H/wXPttdcC/maKcmBz0YgRI6Bjx45RzNmmkDCQVKOCWDt9T5hieP0bwvyUsL6DnN++jp/8vWrZGDyJrchFma/cArT1JCYZne1LZctobHK21yWd5Je1Gukh+kg/a27j45hw7bE0R19tbMek36wGW9vQieJ5OSM9nt0xSYO5qrFbL4QmEa0Xp02btsGIoeNgxrTZOW5YwCYFbFb429/+xg0LdDn4zAwwA8wAM8AMMAPMADPADDADzAAzwAwwA8wAM8AMMAPMADPADDADzAAzANyowDdBXjPAjQr6CqSyUQEhsXFg0NuLQgvk6eK3ObsGdO3SiKYJnY8d+x369JuWkE+qjdPTi8Lz/3dhJFjMd9EPW2DmrPXw87rdkXyCjKI2KgwdvhzmfBtcLPT3R8+FChnpQWEiyXPSqIB8vPfhksA4l7arB3/sUD9QnxNFTmJzo0JOmC+Yvok0KjglQVj3bRUKW0PDAhXtCIHLzy5itmycKh/hQDYuvUHG4M5BVUMo0X4paVQQcHYhkqsQnGJSnk424SPjh2b2IvzdKL4rtr+pSxroZ+LHj+0BVNMI66XCL3RISd4mZ4mo8oj0Km4eun+i5K3jJJuzzM6OY/JOluto6w281nE4CvTLcd5R1usU+yXLt9svsWvtoiaB9TqcRbs2FIf8pJfnHtm6fBuMfmAcHNwZ/HR0wqEzPtn+ueeec30+kY7PzEAQA7Nnz4Z27drBwYPRm4gzMzNhwoQJ0KpVqyDYE0Y+b9486NChA+zYsSPymkuWLAlTpkyBtm3bRvZhw4LNQJRGhd59u0NmpvV0fPE9JH+u6Bf1taR+wNBXFBrYv6+QJXtOY40kSaTvHsLAOcmUvwRROFpg/FV4D44lVK74Q1naSHc9dkQYj9Rm4MiECOPJnBy1mpObOMu8ZQDzIrykQp3VECXiUEBmnSIBC9rBFkLSGFsFICFIh84aUaFrMJcPYWkd+ZDNFtGwMHzYOJg+VTQsZEfbRYlS8Z7Lly9vGhZwtwU+mAFmgBlgBpgBZoAZYAaYAWaAGWAGmAFmgBlgBpgBZoAZYAaYAWaAGWAGTmwGuFHhxL7++WH13Kigr0KqGxUQ9tChbHjltXmwZcuBuNf6ztvPgKaNK8W18zPo9/gMwPyDjjNbVg1SpUReMbNkpEL6BYs2w+djVsHu3Ycjxa1/cgasWbsr0DZqo8Kb7yyCpcu3B+I88dh5kFG+RKA+iiInjQo//LgV3nn/h8Aw7f9QD668PHcaFXA3i/cHBzdJXHRBbejUsaFvbtyo4EtLoRYm0qiARGDxTtwmBWXo4k362UW6PjaqHEgUOtu1zlT4Y6O59NrAwk5Vo4JMURQ5uYui7USSGWO+9gLCMBKxDcM53rpU550sXrJ+ifGFxWh5d48klmv+sU71tUkWL1G/RO0V48H3yEmwa90u+KLnONi7aV/ky3PXXXfBwIEDIS0t+Z27IgdjwwLPwJo1a6BNmzawdevWhNdSrlw5GDt2LJx//vkJ+xYWh1mzZsGVV14Je/bsSXhJlStXhjlz5kD9+rnzmz/hhNghVxmI1KjwcHeoUDFDFcDrSn55orHJUPxyxq8cPMRZFs/ruRzbcj1WJ3ISPgKAMNTY0tn+Nq5jghbyQF88zFnOpIBGjk6akj2qHUDKRa4GxeKvvS4CozjS21oDYUlElGuHGFzSaIUM5RiZXCmeNw87JyeKiE54FFgmSEk4a0EfNDW+Yrx501b4bNh4mDblm5Q0LPTs2VPusIANZXwwA8wAM8AMMAPMADPADDADzAAzwAwwA8wAM8AMMAPMADPADDADzAAzwAycmAxwo8KJed3z06q5UUFfjdxoVEDoTZv3wyv/mQdHjgQ3EqAdFt33e/AcwN0JEj2e/+ecwGaIokWLwICnLxQFakUShU2Z/d59R2D4iBWweEn8oqeyZYvD2WdVh3NaV4fKlUvB2+8vhiU/bvPNJWqjwuAhS2He95t8MVB4f48z4ZT61tMqAy2DFTlpVFj782549X/zA8HbnlMDbrguuR03AkG1Il6zQbtL6sJVV5ziCxPPt/tfmkOj0yr6+sYT4g4YuBNG0HHHrc2gWdPKQWojj/e+PrNFVeh2U1Njz4NwBiI3KtzYLByItFS8E6UWn2zR17YnuS0jfDwLPRb/SLXVoEAmkRsV6mbAjUO7mMIj6S9AsRGDipEI0ylEp+RIo85W/ZOC0XnZOCpf8qPF+eORVRAu6l3YPvHQJpG8ydbGlRjmxR4kl3cMdmje/jGCOInFxnzpyBnfsdj59x7BFftdSz+ZbSvfWESXdbb5DsSQQOSUeq4R2e8aqIix94mdM9oE5k2pSiCaxOKpOOo1OnbsPYIIKhd3jH1b9sOYB8bDjrU77VCh4+uuuw4GDx4MJUrkrCkzNAgrCzwDWFyPT/RfunRp0mspXbo0jBw5Ei699NKkMQqq46RJk+Daa6+F/fv3J72EJk2aAO5ogU0ffBRuBpJqVBBfB7KgXX8t2N8O5ntPfPE43z2m/N39vWg5kgX6EAaeFYYyNOZGjteGbNzXyWBIE0JHc40lT35jE4VMJTDhiXCutVNU0qO3k7f4/kQHlMkXJw+dhtSQr7RS5tKe5DYHCCMPYSfRyN4BVHI0IhscajvypTNh4Blt5ByVhCuGmzdvh8+GjoWpKWhYwM8UbFjo1auX2KWDGxbkdeAXZoAZYAaYAWaAGWAGmAFmgBlgBpgBZoAZYAaYAWaAGWAGmAFmgBlgBk4gBrhR4QS62Pl0qdyooC9MvIJmNOt2Y1NIZncCLJLHYvl4Bxbn/+n6xvHMYvQD31gAK1cFF6z1+msrqFM7bwpetm0/CP8btAB27joUk7ctqF6tDLS7pA60bF4VihRx/ot+KhoVRo3+CWZ89asdzjVGzpH7nBw5aVRAjp59YXZgeNxZ4q/3nBmoz4li+MgV8PXsDYEQXa49Dc5rW9NXH69R4c7bxC4hTZLbJYQbFXwpz3NhShsVnLc5VhPFP4LsSR6AQcVGGIAKkO1gCTcqqOojCWHjUcERrsW1iwRVHNlBxZgKl4IxbAd7cbRgW++MpVabuLApoDD1k9syUyXlwMqRBRGA4XEwFzY8Z/QyeXv4o+vnzY9y8cq9GUhswwfOHC4dbNvL0QfxYFsH5eEnzy/3CObvmx8Jhd7m1eEpPjcWRACGzR6OCTMV94gbj3Kx1xJ0TR1bGwN5Unm5e5woZ7SNkLfv/acKE2U0CzzqPXJo9yEY23sCbP5xC0JEOtq1aycLyMuWLRvJno1OLAbwfdK5c2cYNWpUjheenp4OQ4cOhauvvjrHWAUF4IsvvoCuXbuK3fTC/70TZT2dOnWCESNGmM+fKD5sU/AYiN6oUF5804gvEv19JL+XcGovWejknL7MhE4NSU7G3jniiP9pMPrOwzP5o6fCNiO3zkqE/I0l4jgTEwdFMrKjDMR07KSLzFeBCg0ljiqN5UDKkY6v8zB2YoBI0knZoaEeyYH0kDIjRSeXTk+FTNmQj5HLGDjTh4YyeWt8dDcZyrHjgLotm7fB8GHjYOqkbyA7O5uUSZ2xYeH++++H3r17Q8WKyT1QIKnA7MQMMAPMADPADDADzAAzwAwwA8wAM8AMMAPMADPADDADzAAzwAwwA8wAM5CnDHCjQp7Sz8EFA9yooG+D3GxUwBCfDFsG387bqKMFn+69uyU0bFAh2MBH8/HQZfDd/GDsztecChecV8vHM3dFyOkLL80NbVKoXKkUdOrYEJo09v8P5aloVJg6fR2MHrc6cLHtxa4BVwbsGhDo5FHkpFEh3r2HjRvPPnlBUrtteNKMmT4zYDZs33EwRk6CHne1gNMa+j91cfbc32DYZ8G7Hvz55qay8YSwEjmnqlHh0KFseOTvMwND844KgdT4KvK0UQEzEsU68vCrE7Zl2oxOWBDkLlYmDUCijQpOEohhB8Xk7DnFoKRp7j27fbBQyS0he5LGwyN7PJMPjm0/r9yee21x7hxYMKXqqqP6oJ0d28EKHtnY5BtPhmhkG4zs5iTMJ9G8/fJDfLccM3Q3soTlgDo8bAwl8V8r2UXhgXDIB+e2n1duz722hKXOao04juqDdnZshRP+amOTbzwZIpJtGLqNE+aTaN42rp2HW46aKPdI1sEs+LLvJPj12+BmQ+8qW7duDePGjYNKlZJrIvTi8bzwMPDCCy9Av379UragYsWKwYcffiiL91MGmk+BsCmjW7dukJWVlbIMBwwYAH379k0ZHgPlPwYiNSr07Q4VMnWjgliCLHAXXxKm0J2WJX6cyW8V/JGmD5pbIlIZf2NDPtoY8R0/95hAKAdlZ9uQhZOnvw35qJydeI6fQvLoxVR44ouzDmUizNVAvmpAGpOJEwfjo1RpHLkSmRhar3Jx61BGuEgY+dhy4gllaGzmONbeFFtiSRxprRzwVQfZumWHbFiYMnFWjhsWsGkRGxb69OnDDQtEN5+ZAWaAGWAGmAFmgBlgBpgBZoAZYAaYAWaAGWAGmAFmgBlgBpgBZoAZKMQMcKNCIb64BWRp3KigL1S8YnE0S3ZHBfTdfyALnv/HHHnGedCBhfsP9z4bihYtEmQSIx/75RqYPPXnGDkJmjerArd1O52mx+08YtRK+Oqb9YHxzm5VHa7rdCoUL54WaJOKRoW1P++GV/83PzAGPvUfn/6fkyMnjQoY9/+e+ya0oeOmrk2g9VnVcpJijO+v6/fCy69+FyO3Bf37tYWKmSVtkRnH2ymka5dG0ObsGsY+kUGqGhUOHzkK/frPCAzNjQqB1PgqEmpU0EU1MbXKhEx6nNt1ujgnnVeOOjxIj2OykTKtsJ5Qjia+hzadO2g+LBy82NfEFlaomwE3Dr1eiCggaj2JoMoWoYlLQL62EcmksYKXattG6/BEa6OqJVKRnOYxGHYcC5v8LJE7ZxlUo9pGFh4NvTlRLsiZnw3FNnZiEJi3J7bBi3HWAl8DoSO5NQzK287PtrHlFN7W2zG81x/D20uR/raA8vOT6WAGw7ahRMSZ8nPlZMnJVLrbGBQbDSy5wSNHj16Kydfyc/EgjGTett7GE0oDYdlQbNtUqi0b44hGJLfxYpy1gALafji25DT0cqkRDNcSgmIjBDmSoTi78rb1lh/GRpUtkhC2gHxPgmNZx2Dyk9Ng1ZQ1VqDwYePGjWHChAlQu3btcEPWnjAMzJ49Gy688MJIha/FixeHI0eOROImLS0N3nzzTbj99tsj2RdEo3fffRfuuusuOHr0aKT0o/JXtGhRmDlzJrRt2zYSLhsVPAZyu1EBGcGieL+vLyqWl98saKPpM3IhcBXdGxCyVNgqhnwNj6MCxdioeArThNB565RwpobipGFMbna+xkg7Gh3OXWvUBogig8bGd0KSDfkgFv6hZHROqKYYeiEK1ZZ7/LSddsWTCks4jkQqdJaSw61bRcPC0HEwecJXkT63JVTACzYs3HfffbJhgZsYA0hiMTPADDADzAAzwAwwA8wAM8AMMAPMADPADDADzAAzwAwwA8wAM8AMMAOFgAFuVCgEF7GAL4EbFfQFzO1GBQwTr/ia7qXL2teDKy6rT9O45xUrd8Drby0MtMP/Do47NTQ4JbGdGgIBIyh+XofNAd+LWj0qqHM7RS0QT0WjwtGjx+RT9bNEQZ/fgUUKfR5oDTVrlPFTR5LltFFh+MgV8PXs4KciV6pYEvo92AbS0kzZQ6S8wowGvb0Ilq/YHmiSkZEOf3/kXFkQ4We0cNEWeH/wEj+VlF3WTtzHHaLfxzZQvPfKHbc2g2ZNK9suvmO89g8+Mt1Xh8IWZ1SBW285/k08gQnlc0VSjQq4Jr+PAftWtvVBcpsbsrH9UE9FPwGfOzaEqgYSOyok1KjQxQWhJiIZbzzKz1ijICZZt8yrRl9aD47x8MZR0vBXieELHovnytsvZwzlkftCW0B+OWNOfnJ7Jb55B/hZ4WLyM5hopJONlzP6+OUXL2/fnBHMJ29XztqG8sOpPKyccZ5s3gos+DXpvD35mQgeeby8k+EaYwXl7RvPJIeO4m+QkSW3htJbxrNwkspbxD7JC4yYQu7FwzRdh1/eYgeWY8dg5otfw48jg3c4csGISZ06dWSzQqNGjbwqnp9gDOzduxdatGgBa9bEb3Zp0KABDBkyBG644YZI9kgl/sZ+9dVX5ZO7Cxu1r732GvTs2VO8df3e07GrrV+/PgwbNgz+9Kc/wapVq2INPBK0X7hwIWAhMR+Fj4GojQqZmRnO4sX7SX4V4dmR4htNzaVSKaTeyB1jt9yNY4r7hZHU6CDOWAlUmKCxet87EWV6YipQNB7pKJ5X58iNpV63tMQXeZCdnY/x0MGkqRhTaCcHzAelSuPINYIQ07odb6WjuOgqvbWzPUZLmis1xtPYqLMnxlbJHTMx0hN5Ej5qquTbt+6ET4eOkQ0LWVnZDngSozJlypiGhcqV4/8bO4kQ7MIMMAPMADPADDADzAAzwAwwA8wAM8AMMAPMADPADDADzAAzwAwwA8wAM5CHDHCjQh6Sz6ElA9yooG+E49GogHUs/xk4H/AJ/2FHWloReKhXa6hapXSYmdFhgcxTz34Du/ccNjLvoEKFdHi419mQnl7Uq8rRHNfk+e/sEm/wkKWAT9z3O0qWLAr9+50LpcQ53pGKRgWM8b83FsBPq3YGhmvYoIJs5gg0iKPIaaPCsuXb4Y13FoVGueqKU6DdJXVDbaIql/y4DZDbsOPiC+vANVc1CDRZtXon/HfQgkB9yxZV4c83NQ3UhylS1aiAMXr3nRpT/0mxT65bHnredxZN+RyHgYQbFeLV7uniG1fNMMkwl3j+cfKNqxaxojYqZOCOCkOoUQETsxPVkcQHorfwCDXxl2FZSGgfbB0i9IQfyHT4fTDLTGKxYyUKxEGTSRGydXYsfPmwLAOHds5o5Ju3v7df3nZGivl4Vn56K17Ql5yddwI544dRcvcI5qRXJy9HnLytJbiGcfOW4C4XnARFc/j29zM5S8QglJhwboGdM2oS4NsvopMzgqUgb8zPLyc7bz89hvc7hF8y98jc1+fB9+8HN616Q2Eh4rhx46BVq1ZeFc9PIAZ69OgBgwYNirviChUqAO68cNppp8GGDRugffv2sHx59OaYAQMGQN++fePGKSgGL7zwAvTr1y9yutgUNHnyZKhZsyasWLFC7pSwc2fwv0sIuHv37vD666/TlM+FiIEojQp9+vaACpnlnVWL7xL5daK/U+zvOPO9gTbk4RorIdqh3tiTrSVz6cXEIKKvA+4aI4zS2TYa3MJw/N052PnYY42g8kUcG0DGxHgmKTI3MqkRerJwTG2/kJy1o4Ng5SB0Um5saL0UTdnK/KStSc/k50jQ1oPnJGvsLWQlEzbb5A4LY2HSlzMgFQ0L9957Lzz44IPADQv21eExM8AMMAPMADPADDADzAAzwAwwA8wAM8AMMAPMADPADDADzAAzwAwwAwWbAW5UKNjXrzBkz40K+ioej0YFDLVx0z7457++g2PH3KVy3pup/skZcH+PM+V/sPbq/Oajx62GqdPX+amM7OxW1eHGGxqbeU4HS5Zug1Ff/AS3dTsdatV0P+3zHy/PFWvd7xui0amZ0P3OFr46SA8qUQAAQABJREFUrzBVjQrxCt8x7p23nQFNm1TyphBpntNGhezsY/DE07PgwMHgpyFikcNfbmsGTRsnlyMtBK/Lv/87D/CeDzt692wNtWu5r6ttv3XrAXjuxTm2yDUuX74EPPnYeS5ZlAnWdr77wQ/ww49bA82j7qiAAA89Oh2QX78jQ+T4RBI5+mGdCLLIjQo3NXPXJ9vkUIWN/RFIMmEXWNtr29t4UcaE74Mx9435sHBweNMOhpCNCp9cFyWaKSZC46hPWo4EnItG3iKvgpj371h07nONc5G2pKFtvgsi17jwgpi3vD3sD5mkr2DuOyZzjywe+iN8/ar4Xo74PsAntY8aNQr+8Ic/5P6COEK+Y2DGjBlwySWXxH0vp6WlwZgxY+Dyyy83a9iyZQtcdtllsGhReJOtcRCDxx9/HP7v//7PFhXI8d///nd4+umnI+fevHlzmDhxIlSpUsX4fPnll3DVVVfB0aPhv8Xxc2DatGlw0UUXGV8eFA4GUtqoIO4T+qmL/+eB/1jxhvcU6u3vGGKUZGQj5V48B9zz/1MIXK0jHIOLA62UJr52wf7KHfXCUfsabMyPApNQhlOG8hVttM4xdfvFYAgH6aUdCUH5G6HHxhNEY9h5a0+5DsKktNFO6rWfSdq7HukgbDEZZ0GwbdsO+GwoNizMhCNHsgg2qXPp0qWBGhbsz66kwNiJGWAGmAFmgBlgBpgBZoAZYAaYAWaAGWAGmAFmgBlgBpgBZoAZYAaYAWYgzxngRoU8vwQnfALcqKBvgePVqIDhPh+zCqbP/CXuzde1SyNoc3aNuHZosGnzfnjhpblxbduLJ/J3uPRkKFq0SFzbIINduw7BSNGgsHiJKiT3Fo1jUXjf/jMCmzFanVkNbv5TkyB4lzxVjQqY0zMDZofvOpGRDvd2bwmVKpZ05RBlktNGBYyB9wTeG2FH8eJpstmkxRlOsVOYvVe37pc98M4Hi2HPniNelWtev14G/PXeM10y7+RI1lHo139maIFbr7+2gjq1y3ldQ+dfjF0F02aEvz+891wY4GNPfgUHDvgXa2CBx6MPt0nqmofFLKy6AtmoYCqCxFXxKd7NjUYFp4rKJ2C+vjmILM479y8Tc537HNsRCiLfqmBRNuDYS4kzXjFe/MZ87is4dtS/Qc/rXqJECfj444+hc+fOXhXPCzEDWVlZgAX0y5Yti7vKp556CrA433vgjgBXXHEFzJ0b/98f5NurVy946aWXfAuLySa/nrE5q0+fPvDKK69ETvGcc86B8ePHA+5I4T2waeOJJ57wimPmTZo0gYULF0KxYsVidCwouAxEaVTo3bc7ZGZmqEXqgvTYonfx/ab+uIrW5bee8KFvP2WjZgoKC93d/ElsIcIz+aOFPZZzJYjxR0vCJCzb34SL8Tca7e/gqHhCL/+oM8rooDh0RrlEs9Yg59pB5aclZCOd9JqNHdnIVUkprc1epzYXIvIXfuSqHRw/ZW1ylabaj/y1zMF1+2hoISSO0EFJSbdj+y4YPmwsTBg3PSUNC7jzzkMPPQRVq1Y1afGAGWAGmAFmgBlgBpgBZoAZYAaYAWaAGWAGmAFmgBlgBpgBZoAZYAaYAWagYDHAjQoF63oVxmy5UUFf1ePZqICxnv/nHNi9+3DoPVWqZFHo91AbKFumeKgdKV97/XtYvWYXTQPPWIh/fefT4NSGmYE2fgoscp8561dY9MMW8QRQp5DVWzS+dZt40v4/gp+0f3Ld8tDzvrP8QsTIUtWogMBTRfH7aFEEH3aUKV0M7rj1DDi5XvkwsxhdKhoVsJniebFDwY6dh2LwvYKLLqgNHdqfDCXFPRLlOCoKFmd9swHGjF8duLsA4WDxRJ8HWkPNGmVIFHjG5hhskgk6mjSqCHfd0TxI7ZJjAdiEyT/DhElrXXK/ifee87Mh2T//9S1s+G0fTWPOrc+qDjd1jb/TCF6X6eIeOiby7HLtaTE4J4IgcqPCjWJHhUQOqqxBH+ejJRGEpG1T1qgg8sbU7aW4J1aK2taSKFPbOZ4NBrMP8tV+ckoy284eaww8uUxdE8tBY1sSd94WHtkYKBpoDDklGRoHyQnIPtu2ttzGs+XankTGjAYePdpJFelRYMckuZC5DpK7hNbExiBxkE8COREUniUcYQblZ+dBtjaIPdYYeHKZuiaWg8a2JL45aVhpZqBooDHklGRoGSS3g9HYtiUZnm08W67tbZErfjw9OtoxKY6QaZWbByWOfbUxSEtYNKezhU0iyvnnWb/ApMenQfbh4F2ayAfP+MT8119/He68805bzONCzAAW2/fu3TvuCnHHhcmTJ0ORIv4Nznv37oWOHTsC7s4Q9bj77rth4MCBgZhRcY6n3bFjx+TTxQcNGhQ5LO6CMHr0aMCdS/wOxGzfvr3cMcFPb8tefvllwCYPPgoPA1EbFSqIRgVVhy4+4eUfdUYmqDTeKyeW8N90wloepjhezNxjbWDJpZ8ufketba/m8pXq43FiDtuWxpgDjaWhxjbrMt5ohxMqwrf85LLli2Vt6dGLcPWY5raDS2bZ02JcuVJMieeguDCMmHJWOdo2iCkPGhCuPmMadKVsP3KT19fOleCkTIEaP8ISZ9mwMHQMfDk25w0LpUqVAmpYqFatmkmNB8wAM8AMMAPMADPADDADzAAzwAwwA8wAM8AMMAPMADPADDADzAAzwAwwAwWDAW5UKBjXqTBnyY0K+uoez0YFDLlw0RZ4f/CSuPdWy+ZV4c83N41rhwbbth+EF1/5Vjw572gk+zNbVoXTm1SCalXLQJXKJUWhmrsI6dChbFizdrdoftgJK37aEVjs7S0aj/ek/SJFToLePeMXwv+2cR+89d5i2BlQuF++XAl4sv95kdaKRocFLy/96zvARop4R7OmleG8tjWhZs2ygM0L8Y5UNCpgjKj3BdqmpxeF88+tBWecXhlq1SxjijNQRweuFXOb8dWvsFPshBHlwHVHLcQfOnw5zPn2t1DY5s2qwJ+ubyTzDTLcu/cIDB6yVN5nQTa23HvP2Trv+L0PfxDNNWr3D68O53g/XtGhPrS7uI4vh3gfTpm+Tl6bY8d+F++VUvCIaCA6EY+ojQrNRaOCKpuJZUnX1rr1tjEZxLo6ErKPYGubkJsDBJCSRgURRMaxg4kgVv2QHVLsQiKmHltZhIRWmKTQSbWfDS0CbbTejmOwhZ00JXvE9h6IgTKNI9VBfn626ID2FCPAJm5+tp+NJxOKfTFrtFUJ5u2bUxBeUH5CvmnJFtizYa/DgYVRWTRqZdTVT0K2MSwbF3+2HO3FX9dhrzEKnoXhu14bzxXImvjFEX4Htx+AHWt3wcGdB8XfQ+6z+K45JhrviosmyxJlS0AJeS4O6WLXoor1K0DmKZlQunJpK4i+hwQuHub62vnZedhy5RLzajBsTZCfjW3Z+3Jm6eW1wznmbWNgHJThYcltPKX0vFq2Lo2NZyvQXvx1HWiLAvHy24JNML7vJDiyL3wHJfLHIsfnn38e+vbtSyI+F1IGcCeEBg0awI4dO0JXmJGRAT/88APUqlUr1O7AgQNyR44JEyaE2tnKW265Bd59912xw1u0hlvb93iPs7Oz4fbbb4ePPvoocugOHTrAiBEjAIt7w47169dDs2bNYNeu8EbzzMxMWLVqle/ODGH4rMu/DCTUqIDL0F8ssiBdftDjR70ZqLGeSnPtY0RiEGPvwKK1CKGs8SxH1lwa6BctNvakI3+cu8ZKQNmiUrqokxpLgfSTxmTiwkEhxfbaSy/CVRPp60Z350VgrrUKX1fuVkBnGJsHYmnWBAD+kS/46hx6YvC1nRRLfwyufR0vnaZUWHiUg/R2ciZ/JRb2J4mGhZ1ih4VxMH7sNDhyONpvAiu8a4ifad27d4eHH34YuGHBRQ1PmAFmgBlgBpgBZoAZYAaYAWaAGWAGmAFmgBlgBpgBZoAZYAaYAWaAGcjXDHCjQr6+PCdEctyooC/z8W5UwLCD3loIy1eGFwmh3a23nA4tzqiCw7jH17M3wPCRK+LaeQ2wWLtSpZJQulQxOHgwG/aJwrb9B7JFEZy3Cs7rCWIHgmaAhf328ZzYGWDr1uCGgBrVy8B93VuKAp7YJgCMOU08uX7chLVi54ZjNqxrXLRoERjw9IWmwWLe95uk3z13twxsLsCi81f+My/urgJ2INzRokyZYlCsWBoULy7+FisCJwm+7ANxgxoq0O6aqxrAxRfWsV0Cx7jrA+7+kMiBPGIBfWnRVIHX8sCBLFGAdihycwLFqlO7HNzXo6VYYxqJQs8rV+2EgW8sCLVBJe7i0f4P9URTTGmoWqWUbFo4IO6zjYK3ud/9BgtE4w7uKBH18LvngnyjvidqiaaU+idnQEb5ErBL7HayWewUsWnL/pidT7hRoWYQ1VJ+To9WkHCjAnrSWyr+R05itgKaICmETFS/JNSo8PF1tqsZS3wKYqRq4BQ1OYpAe5Eg5hioFzobjz6e/WQymsZzIqvRtpXbYUT30XA0YlOb1z9ojp+LRUUDVbGS4vNS7PaCZzkXn09lxOdTBSxSP1n8FedSFUuZtXjXa6/HL5bX3tj4rDeKbSQbaSQiWTHw+2lwl2GwX3xO+B01z6wOV//nj1IVGAMh8aJ7jkB7HT9QL3BsvGTvEUqH4hzLOgYbF2+CX7/dAL/OXQ/bV4vfLlJJlomdS4hGw4qiYaFig0yoeVYN8bc6FNe/ByhnRKS1UB4UheQ095699kZvXT+SRbGNZCONBKoVw+sXN2/CoOT02c/Pi21crHsE3+tj+0yAgzsOGnW8wYMPPgj/+Mc/BPcCiI9CyUD//v3h2Wefjbu2d955RxboxzUUBocPH4Ybb7wRRo4cGcVc2nTu3Bk++eQT8ds62s5xkYFTaHjkyBG5Lmw6iHp06tQJhgwZAiVKlIjkgg0bd9xxR1zbxx57DJ555pm4dmxQMBiI0qjQp28PqJBp7fInPpflR7P+fDaf0iinZds6l1wZSEttTGPypc99PEsZYZGBkGoRRTPfFeSLCnss50qIrxpXjRwsFYDmbn+3DgEob4ki1ZSXslVyZw2OlBIgDG2jgWw7k4MQWlZ6/cqS8pWrIjsNok9uLrw2DoDmhdbhxLRMhJAyQSA9loFIjgtBlY6uTyTbsWMXfDZ0LIwbk/OGhZIlS5qGherVq8u4/MIMMAPMADPADDADzAAzwAwwA8wAM8AMMAPMADPADDADzAAzwAwwA8wAM5B/GeBGhfx7bU6UzLhRQV/pvGhU2L3nMPzj5W9lUXnYDYfNA337nANly0Yr5InaABEWMxGdX9H4ex8uEU+x3xIKU0Y0AHT84ylwSv0M2SCxXjyV+pdf98DiJVth3S97Qn1J2eHSkyGzQroodt8odn9QTyNFrrAgPujAHQBwJ4DjeSTSqIBFmrgLAPJwPI/KlUrBA/edJZsdosbFXF9+9TvAa3c8D797Lig+7gzyxNNfA+70kYqDGxXiNyq0EDsqpOrAYlyrziZVsAYneqNCefjT4C7KjxIylcIkMLDWQBqJubBBM5rKgZ9fwIrxzeYyd4qSJKSN7WNrfIXx6ilrYNIT06wcj/8QC9WxYQH/VmlcGepfVE82N5g8ZUpiUbRmuUj5IjQk9Msbbbx+QiQ58foF4PnwZ3v+rierp66FSY9P9UvCyLq82wkqNcxUORmp38DKm9LCewSD2cGlq7b1woTkLSERh7B9bE0cbXPs6FFYNWktrJ66BjZ8vxGyxWdpbh1FRANgjebVoE6b2lC3bS2zE0XiedMCY0izUkcbi1dykZx4/UjpkfvwZ1vQPaL4Fhg6pJOEN36MgWNqRtqGAuFU3iPiREWJXlsx371+D4zt9SXs2Rj9exqfHv/GG28UiKfdmyXzIBID+OT+unXrwp494b+zL7nkEpgyZYpT8BoBHXceuPXWW+Hjjz+OYK1MrrjiCvjss88Ai17z23Hw4EG47rrrYPz48ZFTu+mmm+D9999P6L2DDdrt2rWDadOmhcYpV64crFu3DnCnCz4KPgMpbVQQdJjidPH9Rl8JjgwNHM5ILkVU8G5hoJxsEMwXT8ORnffsRFMjo8epzoVkUkRBUG2NjbGUo6U4hD/ZoCmN3bYqiHwVRmqmfBWEdDRyBwO16pAy7WghWPGs2AgnE9O+NoY9JjzXGikenhXf0szO22CIHTC1rzopQA0rrVxrsRQk37VzDwzHhoXRU0STWc52WMDP7rvvvlvusFCjRg2dJZ+YAWaAGWAGmAFmgBlgBpgBZoAZYAaYAWaAGWAGmAFmgBlgBpgBZoAZYAbyGwPcqJDfrsiJlw83KuhrnheNChh60Q9bZVF6vFuvSaOKcNcdzeOZST3uhjDo7UXHrXjcr2j8+wWb4cNPfoyUb6qN4jUqYLyvvlkPo774CY4dk5V+qU4hBi+RRgV0zhJPr37n/cWRdtyICZaEAHc86HFXC6iYmXih2Cax88BL//4uoR0RkkjR5eJ3z7kMPJNPhi2Db+dt9EiTm3KjwvFrVLDfnVadjevCkU2Q3mXsM0moUeEjsaOCXViExcp02HKS4ZlsZII6S5Kh3vaLIkcfPAQUFU1ZWTjxlJXzasVZPVk0Kjw5zdHlgxHuvFD/wrpw2h8bQo2W1Z1da6y8HS4DrnYU/gyeYI2IMzJBhI1h8ULFXSgit8/vGwsbF22yrGKHp17eAP7w2IVKYcexTe2YxiZCfsZWgNkYFjblTTlLVYAt3Yu/i+/FnyathvnvLpBF7hbccRuWr1UOGl15Kpx6RUMoLZroouTtsrG5sbO2127bxJMH2VrYxDWK4vIdhGfLLWzX9bVtKG8/Gfpr+f5tB2Bs7y9hx5qdNmroGJ8Kj0+7T09PD7VjZcFi4IUXXoB+/fqFJl20aFFYuHAhNG3aNNTOT3ns2DH5lO233nrLT+0ru/jii2H06NFi97Iyvvq8EO7btw+uvvrquM0Ddm533nknDBo0SOxsJgqJEzx+/PFHaNGihfgtHd4QNmDAAOjbt2+C6GyeHxnIUaOCLog3v4bEZ338sWLBXUwvf0waX/oew7PE0y/0FWP7Eqcks31JZ59JjzKDRwMRzQx1NoFzmbLK28Eif5mNCqsB1BJsuVabmNJCxFdnpRWvMoR8kSJCcNmRDZpLd9teIRl7spV2Fr4yU6sWIJSGgqOoZERzBNNj7UCw0hLVClGuA2WUhzxL95Ng187dsmFhzOeT4fChnDUs4G+Fu+66S34+1awZ/m9FvRo+MQPMADPADDADzAAzwAwwA8wAM8AMMAPMADPADDADzAAzwAwwA8wAM8AMHEcGuFHhOJLNoXwZ4EYFTUteNSpg+I+HLoPv5scvou7UsSFcdEFt3wvpFR45chTe/2gJLF2+3atK6bxcueLQ/S8toEb12OKit95dDD8u25bSeFHAojQqIM7SZdvhg4+XiCcJpuZJ+2G5JdqogFj4hNVxX66BKdPXuWoUw+Ikozvj9Mpw4w2NRTFi0WTcpc/MWb/CSNH4kYoDd8hocUYVmDrjl0C4RBsVDhzIgn//dz5s2XogEDOqghsVwotPzunRCo7njgpUEOwq0Il6MYVdwo0KiI1FQVQgbMei6iKSeW1I7yf3ysLiaHwqOiIOVHW0mVEWzlnnvXqK2AkgnzUqOEkClKlaBk4TBf6NrjoVylYvq1RefohLcvTqUa7XSybyTH5eez9bl6Mq8iJ2t63cDsPvGOWxiJ3iTgG3fHoDlKqoi+0pPpn65YE6P7lXhnZx8o65R/ywUSYObFBYM/1n+O6d72HXut1KmMevJxU5CWqfU0s0LTSEeufWAeQz5iBOvfyQnBy8epT78Ud+Xntpi050F+DYfSDfLq0XwzYPwqP4ZOvFIL2f3CtDDBnndzgsdvEa13cSbF4SvtsVhcUzPlV/1KhRgE9y56PgM3BU7JJSv359+OWX4N9XuMru3bvD66+/nvSC8fdrr169AAuxox5t2rSROxfkh90CcNcJ3Olhzpw5UdOHBx54AF555RXxdkv21whAjx49ZKNDWNA6derIXRXCbFhXMBhIuFFB31vyDtMvSiQm6o8844tSy1dJhpobjbZXevuWpfsXzzYG2Zjid0QVBmauDdRJSBW060KQTroqcG2njG09OZLM4FFMC99tY8fWuDqgcZEYUuiJbyxi38fSB7EdG7V+G4eyFmdhR5bSR07s3NBG2aOlUtPZqIwRrRENlZsaSA+dk5IrTG1k8rXzltcWfeQfdZYNC0PGAjYsHDp0WIMkd8KGBWzawoY4blhIjkP2YgaYAWaAGWAGmAFmgBlgBpgBZoAZYAaYAWaAGWAGmAFmgBlgBpgBZiA3GNi/fz+sWLEiBrp69eqAf/lgBnKbAW5U0AznZaPCwYPZ8MJLc2G3KCILO9LSisAD950FtWvpws0wY6HD3QI+G7USvpmzIY5l4uqiRYvAxaJpon27elCieJovwJ49R8S65sABsb5kDixYx+L53zbuS8i934PnQNUqpSP5YOH62PGrYfGSrZHskzVKplGBYmFun362HPbtzyJRSs7Fi6XBFR1OhosvrJMSvJmz1sPnY3K2S0W9uuXh9m7NRIPNNhg6fHlgXok2KiDQ9h0H4T8Dv4fdu8PfZ4FBtYIbFXLYqCCqeH8X/7OLZuJxnkq9q4hYAH/7xnxYOHhx3BAZ4t78E+6oUAiO/N6oQBSnic+oFjc3gzO7NYe0gO8Zsj3e5+kvzILlY1ZGCov5n333WZFs88poy7KtMH3ArISeuH+8c00vnw7XDrwSytcuf7xDF5p42YeyYWL/qfDL3PWR13TWWWfBuHHjoEqVKpF92DB/MoC7FuAuAWEHFpmuWrUqJQWmjz32GDz33HNh4Vy6li1bwoQJE6By5cou+fGcbN26FTp06AALFiyIHPbRRx+FZ599NrJ9kOGGDRugQYMGolD4UJCJlK9fvz4l1yc0CCtznYGEGhV0MTomZQrShUyOqejcUfj+xpYF6npV9m9wC9r4mWJ2Y68GOqKc2BjCUcvwJKxMLlJs6UhP9o6hC0+7KRyNJ0xlfMdFWWk5ilXeSiz+pSEH8lUAqRnaKL2Tp7ZzFBKHrPDs5KGd7ZOF7fbRRqLhktamJcrMYKj1UYZWGhjZ2MZiaFzt4ItNOp+zwbMcd+/aC58OHQOjR07KccNCiRIlTMNCrVq1bGp4zAwwA8wAM8AMMAPMADPADDADzAAzwAwwA8wAM8AMMAPMADPADDADzAAzwAwwAycgA9yooC96XjYqYAq48wDuQBDvqJhZEh78W+uEnn6/YuUOmCGeeL98xfaYhzTHi+fVlypVDM5qWVXu7IC5xDuwyeDjoUthw2/Rmw2KiScmn9umpiiirw+7dh2Cl/79HWRlHYsXCjLKl4BOVzeE5s0SL6b75dc9MGHyWlixciccPRo/VtxkPAY5aVRAKNwh46tv1sO06b/AfrE7QE6OEiXS4Pxza8kGhTKli+UEKsZ39ZpdciePvfuOxOjCBJjHVX9sAGe3qi6LQeZ8+1vKGxUwPr7P8TrjDhBHj3pL1sMyVLpKFUtK3s5rG16sHx+pYFr89ttvcYvj4u2ogE9axoMKZI4nE35XnBsVjucVSC5WuRpl4fy/tYU6bfNHodOh3Yfgo+uGQnbE3XjSxXfTLcO7QtEc7FqTHHPRvJaJhotZL8+Go1m5v7tQtIyCrTq/0RGqNM67IubgzAqO5pj4PTX12ZmwasqayEmfeuqpMHHiRKhbt25kHzbMfwx07NgRxowZE5oYPtV/4MCBoTaJKJ9//nnAQv6oR5MmTWDSpElQo0aNqC4ps8PfOJdeeiksXbo0MiY2YjzyyCOR7eMZ3nPPPXF3s3j66aehf//+8aBYn88ZSKhRAdciis2tmnJnjkXo6o8844u008Xp2hUBlFwKnJllZn6b4290JVcRHRsbg+IgIB7kI0aOg9IoGGkjLbU+NoYxtPw0rlbJqDS24hCWI1JG8lUItYtel8zClaedsz1W+cbaIyBFcGLKtJEAo5N2KgnpQHloA3ES/5NYWiPHGscxMrkaf9TJP/iipPJVDSWAvI7aziBibiqg0KCv/GPscbB71x74VOywMHrUJDh4MLxxinCDztiw8Je//EXusFC7drSdQYOwWM4MMAPMADPADDADzAAzwAwwA8wAM8AMMAPMADPADDADzAAzwAwwA8wAM8AMMAMFlwFuVNDXDovT+z81Szw9Lvjp/91ubApniiL93DoGD1kK877fFBe+U8eGslEgrqHHAHcPwALt+Qs2h67T4wa4s0HtWuVEA0BlaHZ6ZcDdFBI5sCB88rSfYfLUdZCdHdwEgE+qb9m8Kpx/Xi2wC+iXi0aLjwU3QcXvaHuR2BXgQuFXPIdP3caGgJ9W7xRb3eyAzVv2y10MMO5+sZsB7lCR7HHLjU1Eg0e1ZN2NHxbaz1+wSTSd7JB5ht2vxkkMcGeKU+pnwGkNM2WjCTac5NZxRBS7zpu/CWaJxoqNm/aHhqlVs6zM55zWNaBkyaLGNrcaFSgAvhc+H/0T4L0V77qmpZ0EpzepLJpnakDDBplUC0JQJ9S5oDcq4MXyvosTblTwAth3ABYHefVUMBRVbuPROB4G2eHZL45HtnrqWpj05DTbq0CMz7ihKbS992w4STydFgur5OFZm5T7ydDYK1cIsa+I7bWleEK18OMfYM7A72L9QiQX9jkXmlzTSOUdhB1V7heH8gvCsH20DRasz/r3bFj6xQpbm6/HnQfpRoWg9drZB9mgPIgnr9zGs8dh2LadFy/Iz/ZJJL8oeIRt2f4ufs98/e85sGTkMtLGPeMTkfFp91hIzkfBY2DTpk2ARaLZ2cH/zilSpAgsW7YMsDEllcerr74Kf/vb30SztPcN4R/llFNOgcmTJ0O9evX8DXJB+vPPP0P79u1h9erVkdCx0Pdf//oX9OzZM5J9VKOVK1dC48aNxW/T4H8vIT8//fSTKVyOis12+YuBKI0KvR/uDpkVM2Ti3uJ5/AeJ/FgXZ7vY3JGjmyqCVyvX9kosRUGF6rLAnb4zPBjGHeMbGxXBjkf50pkspL92dPy9WM48xh+Xa/xVAjSnGFJKNiqg4kqMlTjAj3z0WeJhPD2wfR0dYaHEGCNr0sSc5NRZlzK1fdHb9td4BEu5KVSNjf6ISTjqrF2kDekQWsrRFv+IsxTRWSiNrTKVDQvDh46FL8QOC6loWLjjjjtkw0KdOnV0BD4xA8wAM8AMMAPMADPADDADzAAzwAwwA8wAM8AMMAPMADPADDADzAAzwAwwA8zAicIANyqcKFfas84DB7PlbgU7xY4Fu3Ydhl27DwMWrqWLYvF08cR9LGwvV7a4eHp6WSidoqJ2LAjHAnHcZWHz5v2yTrBM6eIyTr265SAjI92TpTPFBocflmyFTaJ5APNNT0+D6tXKQE3xpO3q1Uon3DzhIBfcEfK5TuwEsX37Qdgnmin27cuSuy1g/UFpwSs2cJQWfytXKiUaTcpCESzuPc7Hhg175TXfvuMg7Nh5SBZAVMgoARV08ws2p+TlgffV1m0HxP0o/op7C98PJUsWk8052KCDeVYUuyiUyGEDTF6uMZWxU9GoEJQPFjB6C2TQNkjuh0MlkInc6XPfmA8LB8ffzSajTnno+tF1OixF8ssiP8lsJpycsVFh8pPT81OikXOpfXZNaP/UxVBcfMblxYHfk5/8aTjs3RR9lyDMU94/H3aWxWF5kbc35n7xXTzx8amwZelWrypfz68ddJXYUcG7a5Jzb+fr5KlK0CSZ93nPe2cBzH9vocko3qBixYowduxYOOecc+KZsj6fMYBF9b169QrN6rLLLpPNKKFGSSrffvtt6N69u9jNKtrOLdhUgc0KqW6a8EsfmwOwSeHXX3/1U8fI0tLSYNCgQfIp4THKFAg6dOggdzAJg/r666/h3HPPDTNhXT5nIKWNCmKt+O8/eXgLz7Vcl6VrG+vktRcqxLJ/kztjBaZiYYG8wrFfydZ79rdxpGSPkqAxWaNe2tDafBIhDGmC9tqZ5N44MdjSgKQqJ8IQM6MweEIko2iVieiYypwpVeMnkEgmQ1oTG4PsHTgZEL0NX7E2iO14UNook3IJgWO1HJetEknd7t374LNhY+HzzybCgQMHtSa5U/HixYEaFniXpuQ4ZC9mgBlgBpgBZoAZYAaYAWaAGWAGmAFmgBlgBpgBZoAZYAaYAWaAGWAGmAFmoCAywI0KBfGqcc7MADPADOQBA7nVqGA/ZdkukgmS+y3dLvm1SnL8TF2yhBsVgp4IbQf1S8aWYQZk75W7stMTssWpbW/Lyc+ltwysvGWjwlPTySPwfOrlDSC9fHADmXHU2MfE7jlYyH9U7KqSLXYnwr+H9hyGQ6IBCAv7j4oda1JxYNH/lS93gDJVSgfz4eJBR7VlQYlYlPlxvXbmOpjYf2qQd6j88gHtoe65tZWNnQvFtGVoFST3i0K2qLNxbLn227ZyO4x7SDwdd2fOis0QrkhaEajcuBKUq14W0kWzYUnxF88lyhSHrINZcBivP/4VzZAHRcPa1hXbYL9oDkv2uPZ1bFSojJV3CsK6r2Mwae1BfPjJbVkMoBYQLk5te1tOvrYeZfHytjFsX5LbMomnA3nlWuw6EQYKLfslI5bBN/+ZK9+7LvuASZkyZWDEiBFw6aWXBliwOD8y0LZtW5gzZ05oasOHD4frrqOGvFDTpJSffPIJ3HrrrZCVlRXJv1q1ajBp0iQ4/fTTI9knY7RkyRJ5L+OOE1GOokWLwgcffAA33nhjFPOkbD777DPo0qVLqC/u5ICF7nwUXAaiNipUEDsq4Me3+X1sPsupwFwI1B9Fhv6ekWZirM5aRT8spFC6ye8lPTUxFATho52wsIC8eroKjh3CKlQ6kw2eSaZNUCLV9twZO/bSSPtLDOUm3fVKyUTEwKGWiokxtYApD+OE9mhI9uSkkRxXrRAnNVIDOXaMVHRloOwQl+Y00MFpKjMlG/RSf2ROaKpUJFQSKZPYRqtRlYMLUwci/lDnxEZ7hUEAaqps9oiGheGiYWHU8AkpaVi47bbb4NFHHwVuWCC2+cwMMAPMADPADDADzAAzwAwwA8wAM8AMMAPMADPADDADzAAzwAwwA8wAM8AMFF4GuFGh8F5bXhkzwAwwAyllILcaFTBJbEqILRgKlvstjGpv3SU2fpaOLKFGBXwifl4duChaYA5ziNqo0OWdTlDxlAo5jKbdRe67ft0Nvy3cBBsXboRf5m6AI2InmGSPCnUz4OrX/gjp5Uq4IVLBUwjG6L99Cb8t2OiOGXFW88zqcNUrl0e0TsIsJG9C2yd2Mxp5zxg4sD35ZoHytcpBrdY1xd8aUKNFdbG7RTGCj3TeJ3av2fzjFrmbw+Yl4rx8W+QiedOoEClSgFEEngI8HXEqMBy0aKNUxAzA+GnSapg+YBYcE7sMRTnwicgfffQRXH/99VHM2SaPGdiwYQPgDgV28583pUqVKgHa4bXNzePzzz+Hrl27wuHDhyOFwV08vvzyS2jVqlUk+0SM5s2bB5dffrnYmWx7JLcSJUrAkCFDoFOnTpHskzU6cuSI2NGuJmzbti0QAq/nunXrfH83BTqxIl8xkGijAhWQU4E5LgY/0uUhqsnl2Coyp7ljQ8ZYi66kXhsjVwqCxlJ2HUwVrOuglJKyo2wUtPZVE8JVflZ8K46jw5EdR2lsDBzLOcXSZ5pKBOLEYCmtF0ehSw85lNQQPxag5ECbyXFMTCtn7S/NTR5ihmPyo4GMql6USEcSdhRHuqCvNJMKBKOZOlt49hq1meILvbQd8Yeo5KoQJZzKFYcyHMVU/nt27xUNC+Ng5PAv4cD+nDW94ncONrBhw0K9evV0cD4xA8wAM8AMMAPMADPADDADzAAzwAwwA8wAM8AMMAPMADPADDADzAAzwAwwA8xAYWOAGxUK2xXl9TADzAAzkEsMJNKoQAWRVBCTypTiYct6fv2k9XjxE2lUuOGDzlTvo5ZjVfSIvQRkI0G8eMSDTM+p+yFxQmcTk7Ky8kEghwcqbhJCYZNso4LCUxieUBgu8oHXL/vwUVg77WdYOnqFLFqP7GwZVmlSGTqKwv+i6UUtaeyQ8qZCrFiL+BLkesfqnTD8js/jG4dYXPf21VCpQcUQC0cl8xbTHHFN96VAObL/CIy6fyzsXLvLCZLAqHqLatD69paA57Aj0Xsbd1jAQvmfJqyGHWt3hkEDNSrQvW3d2TFEyc8JQZ7LJgA9VfcI0u2K57l4Jo6dh2VD72m86C4c294aSzwxtyAsbbQhxfx1zgaY9OQ0uRNKFM+0tDT473//C927d49izjZ5yMCgQYOgR48eoRncc8898L///S/UJlXKiRMnwrXXXiueyB2tYap8+fIwZswYOP/881OVAnz99ddw5ZVXwu7duyNhlipVCkaOHAmXXXZZJPucGt17770wcODAUJh3330XTj311FAbVuZfBoYNGxZ3V4zeD3cH2lFBVpPTd4P+0Def/eIHjt/vT5Q5Ng4XZCt1lg3J0ZLGNoaUUWzrR5UVxfWFRBguPDXBVxNDTvSLgsX12FI0xj9KKHNCA7LRZ9dU6NWcsPTMArbzIzDXGjEFg20GQiTGzlQnSnG0E+kpDzm3bEiuvbWXwwmG0LmiK41lYEtO7o7etkVHZYF6Y4PYWqHk2obA0E3HQDNpa+GQ2d49YoeFoeNgxPDxOW5YwHiZmZmAO+nkdsMc5c9nZoAZYAaYAWaAGWAGmAFmgBlgBpgBZoAZYAaYAWaAGWAGmAFmgBlgBk4kBk4//XT44IMPTqQl81rzGQPcqJDPLginwwwwA8xAfmUgmUYFXIspdknRwqhRIQg7nt5OI7FGhWtNYY/E0EU7OE4kpu6hcCAsHCmM8OKKp4uNHEAFEGSzetpamPzU9LhRvDsquPJOImcM6JcTPlX/m/9+C1uWbY2bk9egTtvacMXz7bGKyv8QldxUzI0GVHflbxwsxby/enk2LPtiRbBRBM2pHU6Bix+5IO57wsU14gatLySmzfXv2b/DuIcnwobvE98NonrzanDW7S3E7gnVEss7iZy3r9oBKyesEn9Xw6Hdh2JWZxoVDEFUaqdNdUx77XE/f1J4j1DCrqxMTqhVd6OfXmrNuuJ/blqm6vZIgm8XTwJlk3gvfvnIJDi8N/puJ7169QIscucj/zKARe+TJ08OTXDatGlw8cUXh9qkUjlz5kzo2LEj7NmzJxJs6dKlYdSoUdC+vfi8z+GBXOCuCPv374+EVK5cORg9ejRceOGFkexTYTR9+nS45JJLUgHFGAWYAWxUyKyYoVagf8Cok/rAN2MxNWO9XmkhhMpSCPVASqyx8qMQSkHfm+aMag+WjSPVTgAJRr5yIt01tjTWednBtaESCb3OUYrFmOLRWcFYRtJGgVBsspVng+/4kJ32cji0sKROzpWf8dEwWqrM5MRRqKmITnJHRReMWFNnYeiYipHHXk0doVkX+ek1op/Ukakm086d9HjWagonc9OuTp6EpcApkvA9Cfbu3S8aFsbCiE/Hw/590RrQDAAPmAFmgBlgBpgBZoAZYAaYAWaAGWAGmAFmgBlgBpgBZoAZYAaYAWaAGWAGjgsDZ599NsydO/e4xOIgzIAfA9yo4McKy5gBZoAZYAZiGEikUQGdqQjWFMbEICYnIFz09sN29E7xTVCkxBoVPDsqyARwnThwlcOboh9vXLu4WLsrE1MR5IEiAEvvrI9cLaW2V9lQTrIciZAgmUYF37ztsBTKRNEDyyY0b+G/cvJqmPv6PDiwPbEip3N7toFm1zX2RtbXxS2W6Vg5uS6bbWrZYN5YuD34+mGRnzZvQ9njIsWKwE1DrodSFUsd13tk+oBZsPLLVXYqcce4U8WFD54HDdqfbNkGv6dSeY9kH8qGJSOWweKhP7oaFjoNvAqqNK4s8sEbTl0k61LJPNWtaN+Q2s5riCi2mfTWqLatj400tWxC722MIx0IyP1+1GE9NihNkGvlQnAU1Jl79EE5bxc7h2BTS6LvQ3cgnhUkBipWrAibN28G3CXjeB7ffvstXHHFFbBjx45IYdPT0wGfQo8NDske2HBwww03wKFDsY1Qfpj4hO/x48cD/p82x/M4evQoVK1aFbZv3348w3KsfMZAn749oEJmefyxazIzIyFTYiHBP45CfzsKF7QhT2mmZ9bY8UNzpQ88e7E0nBF7/EmOZ4Npja2kpSnlQra2n1yjepG29GJs5ZrsOCjQ6yFjcTb2gWPi1XYSfvg/k6Cjsxh29BJb2wgf6RfElbS1UNCe4PVAnrxrkXZC45WjL/mRznNGvYyiz1qt3MhW4mggnY9S6fwsDGVqNSwMGw/79kVrBNPQfGIGmAFmgBlgBpgBZoAZYAaYAWaAGWAGmAFmgBlgBpgBZoAZYAaYAWaAGchlBrhRIZcJZvi4DHCjQlyK2IAZYAaYAWYAGUi0UYFYo4JYU+CjFfHkVGlDBTRePJzbmH547kJkVShs++SkUeF3V5W7XcxDBcmUsczUnpgKaTsXN54wRxgJG45tlTTJGA6O4+eMAFZNWwNTnprhzsdn1uXtayDzlExLIxLSOdkxnXjClJbuvWhG4cD5YRzYcRAm/32afLK7Yxk+KloiDa576xooX7ucZWitmG4CkZMlFRlRssJNr4vuOQXk6BcP+xHm/O87Cz/5YctuzaH1X1r6ANjZCbXOO6f3CO4CgbtBJHKUq1kOLnv6EsisX0G42Xk5nDh4Hr02iZ+37YdosdjZB7Phx5HLYNGQJXBoz2FQjQqVXDnZKM41dUudXO2RZZOCe8SN7GA7OaGFkjta5eXY2JpYPsjfxErRPaIyc2Lv+W0vjH1wAuCZj8LPwE033QSDBw/Ok4UuXrwYLr30UtiyZUuk+MWKFYOPPvpINhtEcrCMsMnhlltugaysLEsaPKxSpQpMnDgRmjdvHmyUi5qbb74ZPv7441yMwND5nYG4jQq4APy9hX/MR7jzW8f+HpY29H0uXZSD44cYJBMYlsI1ljEVc7ZcpeL4K4tYO7QwftKcfBwPo/fYypUpc2PstaW0la3GNtZWbBvbNca1Ww44FHPEM7EsvYyjzW09mUgZApLAY4titCG1wUA7Emobl0j6CAOdrGVq/AjLe0ZcW0a+8kx4aoIhzUF6Usms5cTBQ2NsUvhs6Hi5ywI3LBj6eMAMMAPMADPADDADzAAzwAwwA8wAM8AMMAPMADPADDADzAAzwAwwA8xAnjLAjQp5Sj8HFwxwowLfBswAM8AMMAORGMhpowJWzuj6FxnPv7HALs7V1S/C2tdPVtro1IUbFftS8Q1qqP5YWTnYZJNoowLiUFYUT2GTFGdOHKWjV23jTsoUC7nwbAh78QHYVOLkwjCZunPGHRWiNypYhepW3sSfK56dMy7Z5O1VKD4oZ5zZOMeyfoev/zMHsMA+6lGlSWW45rU/wklF6DokyTUG9OSN9+nQm0ekrGg7vXw63DTsesAGi9gjybxNzojo8H1k3xEYInI/tDva08PRu27b2nDJYxdA8TLFcSoO4tTBVXL7NTZvukfQylxfL4TJ26tQ2HSPZB3IgrWz1kGDS+vr9wvlZGfnxSAbr5zyjs0ZNZS3yRmFXoiIebswEMdw6YzcNpQz2nqDogyPJPM2OSOGPzbxjTlh09D4hybB9tXRnnaPqHwUTAbeffdduO222/Is+eXLl8tmhfXr10fKAXd+eOuttxLK+b333oM777wTcKeCKEetWrVg0qRJ0KhRoyjmuWKDOd9+++25gs2gBYOB3n27Q2Zmhv7Yp09onbv4TJffBvjZjn/URCrlUIzo+4y+NlApvbQBjl1+JEdspZB40k/PrTBSZ9vRmM62HwGRv5OHCmqHs/1lxlZerrXYTiIA+SmxjIDuas1WAlpj7N154trJWJ8tDHcM6amMyEb7EoS0lxNpIG1pqrydeDF5EYgwVD7Gwr0ukbAx1cm7YpCMFiaUzjqUr/GXSWk8C4TsVc4qIWllObptToL9+w/A8GHjYPiQMbB3L++wgNzxwQwwA8wAM8AMMAPMADPADDADzAAzwAwwA8wAM8AMMAPMADPADDADzEBeMcCNCnnFPMclBrhRgZjgMzPADDADzEAoA8k0KqjadiyKVZUsVCMTFkg1MFiVL+htTRHTTGlAdbc0twJY9fVCqgypmCahRoX3r7VQY4fOKmN1OZaYdeGAFuseRo0hGxX+b0Zcc7mjgnyiflzT/2fvOgCmqo710IvKD7+CBXtBjQq2F7tRg9gQKTY0aoxJMDGWZ4xGny2xRZ/xGVvsxgYKIihKlyoWbNiVXqyA9M4PvDNzzpwz9+69u3f/AvvD3Id7zpn55ps53+6/u++9OXvTAVQ3F+/qFuWnBwK8ee878MUrX+WDRHxH//lw2Ktjm4it0gtR98y3Z8Lga98oSHVIj4Nh8htT4afJhRu7j7ryMNj71D0LchYN8HVbkfEuEHg3iKzXLkfvBMfffKz4A8saWQWcrxk5inuNVCFr1UNrqG5UgKirXmEyg69b/CGKqQzCgy6Dr3sDfvj0R2nW+UamwNSpU2GXXXbZoLuaNm0a/PKXvwQcs1x169aF++67Dy655JKC8AcffBAuu+wyWLt2bUEsAlCLN954oyQ02XXXXTPVrKCNUwF5UIGawuU2zXs52fA93XxJtt+T6Q3ef4bQd11rkpEGyzgz0j+3tgP5GSMD0eZCvZlroBGtgoOWsQByRzB2IWHR3MFP9kisL4MmHEcQ8+AiI9r4+syE8dE6Y3vkfMzmyEO9HoCMnNShzZKB8bgQhiBm93FExbGmQAt3tZGdY9Dp5g7vqEkTJsQ6ZC08J7vntyGU2z6Qx9JGWImWOTgHRls+3pwdly5ZBn37DIQ+vfDAwhKXRAdVQBVQBVQBVUAVUAVUAVVAFVAFVAFVQBVQBVQBVUAVUAVUAVVAFVAFVIH1qYAeVFifamuuJAX0oEKSKmpTBVQBVUAVyFGgmIMKfLcESxKaW1wPTQ53IYM8bBDh4AbbkKIQFfm5vvGPfQgTnv+kYEzzHcvgzDwHFbgMJCqylIK5IwC/eZNRJo2A8i/W60EFLMXXbObyicxfJqxbuw6GXD8CZr49qwDSujffenM4+7muULd+3Uz4giBX98CrhsA373+XF16vQT04t88ZMPPdb2HUHWPzYtHZfCfzenrKHHypiReLq3vhrIXQ58L+sLYiW3Nuq71bQsf/OzHnTg/8MquJUr1QlXyN+PiESW2sm2vG7awfvU1GmTRBx4qVFTD85lEw851sv3afQKGmElZgm222ge+//74kKsQ7Khx//PGAd1jIet15551w9dVXp8Lvuusu+Otf/2o+egq80B0D3kEB76SAd1QohWvbbbeFH374oRRK0Ro2gAJ4UKGFuaMCfkSKtnRbiTH6j06co9UZ/OeHxIj6ucGcogQ381GzOS9icXFznIM/vHyOeIAvk+v31XL5Zgw2/jQkk3lgVxRji2QbRdO+0M4xjtMPaHcLj5F4CkUDXQZtRxqYE02eUPB5a8SGUJ/Th6FR4CWfcFi4q9nV7ShcXUjCKDLZBwfivDQi1HHjiGEO5mPYT0hyRhAuxtmEC/kpFpk4zoxoW7rMHFh4EQ8sDIBFi/TAghVbH1UBVUAVUAVUAVVAFVAFVAFVQBVQBVQBVUAVUAVUAVVAFVAFVAFVQBVYPwroQYX1o7NmSVdADyqka6MeVUAVUAVUAaFA5Q4qiO4Vw+V6aARrtin3GHLPC0XJvsNomoKk3LQ4/tEPYELPTwviS+aggu36MfXKzRcsPwJY7wcVKDs/QcXVXbGiAl69fBDMnfhTZA9pi+q+U8GCmQuh96/7FZR7j+N3g2OvO4oOBfQ8uw8s+2l5WonefuId7WHHQ2uiGdZqPfi64ZkPeWyxzebQ+d8doUnzxr4+nshnjJ9F9lXvyOwyY+UzMAuzVp6pQCS+qVEyzlgAX8DNLDVbN7NztvxF4WGX0XeNg0nDpuQHqrfWKdCxY0cYMGBAydQ9e/Zs6NChA3z88ceZa7rxxhvhb3/7Ww7+pptugr///e859jRDu3btYOjQodCqVas0yHq3n3rqqfDaa6+t97yasDQUuPJqc1BhS3NQAcuhBnAcaYEP7ju1Mdh/bLA+BxBwsluzbyU3HIQwZmNzU2o254WLsjwWEFzRGJ8A2QIoMkeMdYVYzM1Xro8ibIxxCtoEXuO3cEcX1m5GqdwuXLzLbYZg9+E0kbGW3iFdKJNG9swUkYKt0eMop2F3owvhQvAZEXPjxf2TzSa2j3FOQvg49EZ4XD1Ug8tr81seenR2TGUvO+G6aZWDcUjmpzrRRkCqwbnsgYXeg6B3T3NgYeFiG6iPqoAqoAqoAqqAKqAKqAKqgCqgCqgCqoAqoAqoAqqAKqAKqAKqgCqgCqgCNaqAHlSoUXmVPIMCelAhg0gKUQVUAVVAFQAo5qBCol6mJ9a2xcrmWNv8EsdzM0vcntqfn0yTG+5T20kxBxXO+I/5BXx3pdZn/MTMJys4IHT7OAuiQtFJfJkoPH+Uz5upmmierAcVuj1+GpTv2iJQ0SyaZ33UvXzecuh9QT9YtXRVrJbc5WatNjN3VeiWcFeFUHfhmg3Wgcb96x34on/hX/fu9MApsPXPtjIF1YGPnvsE3n/yw9ziYpbWB24LJ9/dQVjD82SNoWZcF1P3j5/Phlf/NFBwp0/rN64PXf59Kt3lIS0PR2NF0btixGsmgHkI9sJ1R+BIwG8Udh57DTujA+XPg9jcmtEa4nBlr/x6R/8eDTZxY8yFY5RPenieRMG+7HVzREpJRMSYhLojfsbFx3X0tL/z4Hj47OUv405d12IFrr32Wrj99ttLagfz5s2Dk046CcaPH5+5riuvvBLuvvtu82dZh+6ecNVVV8E999yTOR7/jzKDBg2C8vLyzDHrA3jdddfBHXfcsT5SaY4SVCB+UAE/uiJN5+KzzH+e+Al+Jrimddyb+9ijQdi5+ZwgLpbiJA9r4/2WkCGSg6GSL23O8TbGFmhtpm5XL/NRDmNMtBsQwm3dNmKd23Dufj0j4aPC4ErkMMG4pssNOPc2nLOdauMFYuwV0SYYrR9jiEMwMgbtzGJszEM2l1RAvR9DLMblZw5cugCrk11IzTxfjIMDye9qjuex2UKdVIUNcBqZqjiBG5cvWw59+wyCF597FRbqgQWWUEdVQBVQBVQBVUAVUAVUAVVAFVAFVAFVQBVQBVQBVUAVUAVUAVVAFVAFakQBPahQI7IqaREK6EGFIsRSqCqgCqgCm7ICVT6oYMTjOxlEdeTOFbSGrlluyoliIxCDtvg4lvNIe06jsaEq7qBCZxMRavUNN7ECOXfUHOLkHtP4kmqV2Ch30CyKSbZPHTUN3vj76ChFwqrb453MQQXZtJnMJ3Woqbo/7vkJjH+8cPM/bqPDrcfBTofvKHaUW3fhmsEcjFgNPc/sA6uXrxZcudMtdy+Hro92Mg6bZ8WiVdDrrN5QsXJNLjhm6frYqbDlblLjpNdJsGWpG18Db93/LnzeL1tD+YHnt4ODfr2/qSw5jyy5lF/bUpvCNSMi7JefOxtn7ZIv+XUd57DR9jH3NRe1h9wyT4QhmlS4QmyoO9gkX5QirSZB7d9/A1/Igbg68OGzH8MHT30kg3ReixV4+umn4fzzzy+5HSxatAjwbgJjxozJXFuPHj3ggQcegEsvvRQefvjhzHFHH3003VWiWbNmmWPWF/CZZ56BCy64YH2l0zwlpkDOQQVTH32vdW/RvpGd7KJ480FAEB7R5WMsmN/l5fdknuPI8SIUk+Myp/Gc48gpHqSd5xFeLoJikrmZjuINhHkidrOwpYlmeLdhzmdHg+NAM7NcziIGmUPOOdipQ0xOEirA5rBEji5aL+fgIDOiCZeekzGWPT/MPrcAAEAASURBVORwMZGaMZYQyBEJ9Os4L8IRS3iXNxZKpBTH5C4L4iRfFGML8XUgkuIpiOI4DyGtGYsBPLDwcu/B0Ov5V2DhgkWWSB9VAVVAFVAFVAFVQBVQBVQBVUAVUAVUAVVAFVAFVAFVQBVQBVQBVUAVUAWqVQE9qFCtcipZJRTQgwqVEE1DVAFVQBXYFBVYPwcVUFnbUBuaXWJqi37bpIMKsplaciQ17Y5/9EOYYJrgC13NdyyDM/6DBxXMtY67a6iXx9rcI9cTMfoFdeyYldgA+djugWISw2JuvCIhMYx3xuyu7qkjzUGFW0ZbnjyP9qAC3lGBk8X4vD2JJIYVmgW0xKTkcHHY9N/7/Jdh6ZylITxltttxu8Bx1//CeWUONHGelGDx3OAvx7/9QOFf9D7qysNhr457RAjf/L934MsBX0dsSYs2J+wGv7jmSOHi+oqpO4ZdWwd6nt0bls5dJniTp01aNIGznusKDZrUtwDxPHElHFk6r+3YfvPUjLUXrjvGV8RrhLQR+a1WaXwxu4grXa2tgnZf7tHU/cWAr+Ctf72bcvAsgtZFiSvw5ptvwhFHHFGSVS5btgy6du0KQ4YMyVzfrrvuClOnTs2M79ChA/Tr1w+aNm2aOWZ9AvH5Oeqoo9ZnSs1VQgokH1TgArERPHx6iKn5quPayXnEEAN1Vv9ViKIFhvlwtD4bWGhOaAJxbXZkPmIxnDTaheAns3kwLI5Dxll4ICdfAo5jyBUeXB7BzekoX+Als9s3czGU1zyyHUdbs+Gx/9gQ8kbAtEvC2lib3+/bkzAk1M3i2BqiddPK1U7pnBux+D+2mFAI2TEp/Qs5KMwVQ3Mq0j44cw6f5A9z5nQsLk+8FNoL+0ya5ctWwMsvDYRez70CC+brgYXwjOlMFVAFVAFVQBVQBVQBVUAVUAVUAVVAFVAFVAFVQBVQBVQBVUAVUAVUgaoroAcVqq6hMlRNAT2oUDX9NFoVUAVUgU1GgUwHFXocDO267+c0WWcbWqRC2LMS69clt+tlkVB54IDtoQmGLXaUWNvEE7dz00w07t1HP4AJz2c8qPCUPaiA5fty/UTwJu1PuKs6jeQvgozjpo6anu2gwmN4RwU8qFD1i3MXyyTjJg6ZDKPvGleQon7j+nDey2dB/Uau+b5gRALAJO59QT9Y+G3+RqmGmzWEc3ufAZhTXgtmLYQ+F/ZPfq0LYL0G9eDsnt2gaXkTYa3a9MfPZ8Orlw3KRHLkFYfC3qfu6bFS7/Ai9+6C+xHIoqeR3EVHu4Ckv0d0IXkNXZWtOxKXVHcN1oxSRPIXoQ3H4fvIyDvGwtqKtUVEK7TUFJg+fTrstNNOpVaWr2flypVw9tlnQ//+5v20mq/TTjsNXnzxRWjUqFE1M1cf3YwZM2DnnXeuPkJlqlUKJB5U4B2YznH66DAjXm5wc7bZ0frDnD/fycI8xOHixByJmVt+B3fZfbM7c1IB7kF+H+c5ZuC5jPE26Y/NHS3FE95tScZKDM5t7XIPHhHqYBPhEeuInZ3XPAp4BOvDzISxkolsCTX7OJcf+QmGPJzMgSyvt5I3F2uDfA0yAXIjL9roH86jeFw5k8ewgTlthIszTm9n7igAEZ6UuTmGRw5ZsRwPLAyGns/20wMLLIqOqoAqoAqoAqqAKqAKqAKqgCqgCqgCqoAqoAqoAqqAKqAKqAKqgCqgClRRAT2oUEUBNbzKCuhBhSpLqASqgCqgCmwaChR3UCF02VJzCkvE3SnB7RtXGMKjPHzANhzjDS1ok1jpT7NjDF7FHlSQd2Xgxh7LVPXHLNweE/p9MiX2cQY9bXT1HlSQ3EmaFPLn2wDHIi8+lz3P6gPLflqeL4R8v7zhF7DrMTvnxUnuOHDWe9/C4L8Oj5tz1vt03gsOv/SQiJ15h/zPGzDr3W8ivqTFAb9qCwdfeECSK8fG3OhI0hrtbz/0HnzW9wuc5r2atd4CzniqC9StZ8Q1VxbuvIR5nIW4C/nzUPu60/TIF1vIx3WlcbMfedIwSTkqG5fEFbdl4c6CifPiOh73zXvfwbCbR0LFiookuNpqgQLLly+Hxo0bl3SlFRUVcP7550OvXr2qrc7u3bvDM888A/XrRw+ZVVuCaiJasWIFNGlSfQfZqqkspVlPCqQeVKCPbW4wNwv7z1ZFcwI4e/IcweQxH14O4b9f49p/lzYLPzfI8Fnn4lxwwHAZGGjn+Mh+MnFO74/yWryN5Ti7QiLB5YrJwSDMJoqNFO6oMKcvgGx+jTkixdu19zsGqoVxFMPUgTuSAffNBpwzjxnZzjnIJzEOQFHW6aNzsdbluZic8hg0/hPcjMMonhMnGewDU7AfrXxxTXZ0++IABFFKm9ctKZS42EcW+2BD6wC+/73cxx5YmD9voUDoVBVQBVQBVUAVUAVUAVVAFVAFVAFVQBVQBVQBVUAVUAVUAVVAFVAFVAFVoFgF9KBCsYopvroV0IMK1a2o8qkCqoAqsJEqUGMHFVAv3xETxLNNsfJEg/UlNclEDiTYjhgCSw5upAkZqnZQAXlkH47kLXYuG4A5Ns4dx8T9HBcf43H4S+gjbh0dh+Wsu2W4o0KcO6mmLJic5MaQFDf2n2/BVwMnJcEjtp912hOOuPzQiE0ukrilf/B12Q4ZnP7kadBip+Yy1Nf93Uffw8C/DI34khaNyxpB917mrgyN6iW5vS1eMzrieiPmhXNegiWzl/q4tMkB55oDEr+xBySycKfxFLLHueM1Y3wWTFKeysYlccVthbjjfoxP2lucF9fx2KxxSVzSFudFX5w7jon7JZ+cx+OYe/YXcwD/XlYuXinhOq8FCmAD/LJly2pBpQBr1qyBHj16wBNPPFHlei+66CJ45JFHoF69/O+5VU5UTQRNmzYFPFCi16anwJ+vuRhalJeFjZs3bPuebZu+/VdntCPKGeLfd3kd//5sY1wshrsPBLTznL5SOzsn4Bq8GXObi2M8o6sn6kMgWcJeKNba8JGvSB7HxXsJmJAk1GNQnAOBZuGWTiIbw/VaSOBxIDMYmzM7Br/HiN1jXFWYzxUjWKkOT8k1uRBbA0JshH80E5on2NFjzR5t2SjG2nydHG9GmuIYye04GEcFMYB9oT72WJjx0z87uopDbRGf83J+DvF7Yeawt+XmDgv9+w6G55/pB/N+WsAAHVUBVUAVUAVUAVVAFVAFVAFVQBVQBVQBVUAVUAVUAVVAFVAFVAFVQBVQBYpQQA8qFCGWQmtEAT2oUCOyKqkqoAqoAhufAtkPKuxrNu8aTEzj9DrzP3hFW2KCnZwOEeYGb5pX8JKHEHAteZgb7XxF/WzFOHf5SREHFXYog9Of6swMYsS9CULvsXv2y9RJPDaJj7mSsHHiOCbuB5g6apo5qDAm1xGzdH30VCjftUXMist4jkL1peGZOu5ne3xcBzPGzYJhN42MO3LWLffaCk574OSYPZ4nue6F3yyEPhf2xxdo3mvbtlvDKfecmBfzco8BMG/KvLwYdB55xaGwV8c2KbikuuM2DF0HS35cCi+c2zeFJ2rudP/J0GrvllFjZIUCxPMUEMXHx+PQkY8vjo/nift9otiE4+J4tsfgOcu0uCR73IZk8TxJmJykLi4JG+dLikVbPBbj4jbEJdmTciTFYnz8snzzpy8wdyAZBkvn1o6m9/guNtX1VlttBXPmzKk128fvAldccQXcd999la75sssug3vvvdd8v8j6Gq90qmoLbNmyJcydO7fa+JSo9iiQelBBNpPjdszLWb6m5Zx3i7a4nf4K0O5A7Mc1z6PcjLT++J8RMRmIZwzwwEfcNqHNYUE+n6sFB8uPdePC8QpOhnKsrIe5CW4cHMZYy89WzBXmDJY2z2BgNHfwKMZVhPkcn2DFJBhs6RHDGwhhZoax1uARGJPD53Lk2AOWWJgL8zFW8LnUFhrDBJ8lseGhvuAPOTkH+uwck+E/OwY7mZ3PMslY5yUOVzasXLkKnnv6ZXj84eq7u47NrI+qgCqgCqgCqoAqoAqoAqqAKqAKqAKqgCqgCqgCqoAqoAqoAqqAKqAKbPwK6EGFjf85LvUd6kGFUn+GtD5VQBVQBUpEgWIOKshmE3nQgBpV3H6SDhlwYwpCuDEF58VwRHNgtL1sm0108e6jH8CE5z9hSOrYPPGggmzwlezSnkoZLYRWMi6Nj+0SK3OwX9qi86ofVEA+mUfWwvYkG8ZJO6754jhex0cbt3p5BTzb5QVYW7E2Dois6zWsBxcMOAfq1ovz8lrWwTakWAfvPPQefPbylxG+pMVxNxwNu/5ilySXt00aOhlG3zXOr9MmzXc0B2GeOC0qqwdH6/PmhOfgh09+hNeuHBIgKbMmzRvDOX3O9E1rubB0fXKxaZbsdUc3LnNLbskn7TyXcRIr7YzNNybFJtmQI80u+SVG2nku65NYaWds2pgWV6yd+WUc2+KjrK8OLP5hCQy+Zhgs/HZRHKjrElVgu+22g2+//bZEq0sv67rrroM77rgjHZDiufbaa+H2229P8ZauuXXr1oDfv/Ta9BTId1Ah8i6NDeYojzPKpnBrNg78J79YE9zZEWQu9iMscJiZWdvLTugRc3o7e42B/jkHDzTaRYjheGl3AZzNxVGMmYeaHMAMXDNakrgtBUVSkMW4PGbhZhEeNnK+gBL5mMJu2HLToy0kntcnN45Enw3zdVh6Boe81o5spipc2AcuGR2eQxpZJxw5LnCFGI8jIv+AE4pjTcjgHjjGYgKrtZu1/WcJiMdi6JF9vB/idH4GGBve/eelF16HXs+9AgsXLiaUPqgCqoAqoAqoAqqAKqAKqAKqgCqgCqgCqoAqoAqoAqqAKqAKqAKqgCqgCmRXQA8qZNdKkTWjgB5UqBldlVUVUAVUgY1OgewHFfazTTCogOlllQcSuNlH2qJC2eYUtPn+FOJAi22MZQ5rkc2yaMG4wCG9wWpxCKv8QQXJ7Pgob5Kd/WkjVyZj2YYxSXZpi/PK2LhvnbmjwvQq3lGBOTmPrCWrjTnkyLHSxvOQ43XTiP+9acgvdCXfEYJzBD73SiO61ctWQa/ufWHV0lV56ZuUN4HuPbtB3fr18uDW0YGKXuf0heXzlufBWdcJt/0SdjikdQouf938Gpk8bCqMuvPNFI5gbnPC7nD0X44IhshMasMOzJ9kZ3/amK3u8BwUysF8SfnisZWtGbk5D3PyGn1sS8KhLemS8dIvudhe2bo5h+RkG3In2aWN8/MoY9nGY1JcHVg+fzk8f0ZvBulY4gpgA/w333xT4lXmlvf999/D/vvvD7Nnz851plhatWoFEyZMgG233TYFUbrm7bffvlYeKCldRWtPZVde0wNalJeZTyT7fkyN32YaGsPd+zTaeFs0l/YwRwhxCQw1rbtY5kUb42hGFJbHPiKRQfiFIyAz48zo/BYn8Q7j/CEH8yRjef+MwjHU7MnI7XNaEJciajZ4twGMZB4KphiqKmJPw1AM0nEWmlumSAzmY5+Zm6m/XCmUz9vZaFDM433eZi3st/zGJoCUya2JEnPjfy67j0VOtLGPwBZk7eg3Mw50EwtDTovlR8tr8eRyDx6PQOumCdvJTFiApUuXQx9zQOGF5/vDooVL0KWXKqAKqAKqgCqgCqgCqoAqoAqoAqqAKqAKqAKqgCqgCqgCqoAqoAqoAqpAJRTQgwqVEE1DqlUBPahQrXIqmSqgCqgCG68CmQ4qXHww7N99P3MHhKCD6zUhQzigIK2258WGcGBooMFAtlrWsPLNNcFksLxwHJjKmKyVfZZpPN5RoeendpHnUd5RQd7dIU+Ic9l9Rpt3TIXRMiJYu7AA2bSD9mJye21icXhQYeRtY2yaPI9dHukEW+7WQiAqW3danKB2U1kzmpL2i3comDxsSm5wzNLhluNgx8O2z6w1hn85YCK8dd87Mabc5f7ntoWDfr2/d+SrG19fHzz1kcemTbY7YFs4+X87OHeaZvLvJvc18pG5O0iWXEdcfijs1bGNb3yjpIbOZE0rL8Fena/ttP3mps2ndS46yRJvpsuXm/UOukTz54uN5o7GJb+2oxFyVZ1aF5e7mLq/ee9bGHLdG7JwnZewAttssw1g039tumbMmAHt27eHyZMnF1327rvvDsOHD4eddtqp6NgNGYCHK3744YcNWYLm3kAKZD6oYOrz3zPNxwV/g468f7uPM/JFMGFzjEcunhObI3cUFEB+aXA0IS5wRPkQaAN9zWgRCzmPYA1GwCgjYqN4MnsbZUKMNYt4Y3Fk6EvjYDuPjsYP0h6dW4i0UT5Mi66EmuJ2rs/Cyev3gSy2fGd3e0EA7daa7dyW4hJjaqcZYmUdHuf0cpyOiuIlNxMiLLJPx2Nt6HRIIsLctCM0Bx9W6vKheelSvIPCa+aAwquwaJEeUEBN9FIFVAFVQBVQBVQBVUAVUAVUAVVAFVAFVAFVQBVQBVQBVUAVUAVUAVWgKgroQYWqqKex1aGAHlSoDhWVQxVQBVSBTUCBmjqoQI0qTj/ZKO3aZMgT2oRxGVa+qSWYIs3W3o9RCacDij2okMRBBaY+hN1x/006R8Cm7VHqk5rSOdL2XsxBhfJdW7iGomT9bKr8dafvN3kHvm7znCbtF5+zT/t8nhwsrL+45kjYvf1uxiJeHMLv2qaC38D6/vYVWDBzYQQVX9SpWwfOeq4rbNZys4iL647vd+WildDrnJdgzco1EXzSouujnQA1j3MEbH6tx/7zLfh60KQAT5m1v/lY2OmIHSJNYek5U0hsixk5q/raLjY3a43Ji4sN+nHN+TkYH15Dlc9tXnEuaXE1Y4VcB3LgOt++A1a+9jl3/liijjxkjZsychqMMYeI1lasjcTronQVaN68OcyfP790C4xVNmnSJDqkMHPmzJgn+3LHHXekwwp77LFH9qANjGzRogUsWLBgA1eh6TeEAnhQoby8uU9N78fmLV6+L9PnA9oYRXO78jjvRBwB7Ghi+DMFwxmPNsbRTIA8lbEJM2UPMYHL8tKjwFuWEB/l4jowN1+ExZyWis22ZmN0nqjdrJiLmWROLCjYeWYpOA4BjPI2ziJ8EmfnMR5cYnL7j+Zm6i9bl8nEfgTixWsLcFZr5LrkPigkkDgKJsG0Lpb5zGgsnI3wno8x1upqCVwObGt2WIbiaHO5KjEJXXaPSEYmT2ftS5aYOyj0GgAvmv8W6wEFFk1HVUAVUAVUAVVAFVAFVAFVQBVQBVQBVUAVUAVUAVVAFVAFVAFVQBVQBaqsgB5UqLKESlBFBfSgQhUF1HBVQBVQBTYVBbIeVGh39n45knB/Smg8Z0u0OSb4fQsLcYU2YVyGlW8aCqac5nbCGL/k5gKLOajQ7cnTOKzIMexV1p5MglixGQfCdp6k+pM5ghX3Hm+KLvaggmXLrSlkwVly3VFM9lVS3RyNhxTweSt0HfrHn8M+XfYqBPP+7z78HgZdM8yv0yY7Hb4DtP/bsWnuRPu4f70DX702MdEnjXt02B2O/svh0pQwT9YaXyOD/joUvv2g8C+kn3rfSdBq75bEnU/rhOQxE9bCV+m8Rrii5FHWjIhCdeeyVE2zXL5sFll3oZpTXiMJ7wdZchfa7xevfg3vPDA+570mC7diNpwC9erVg9WrV9tm0g1XRqbMn332GRx//PHVcmcBvJPEsGHDYN99982Ue0OC8PO7QYMGsGZN4YNuG7JOzV0zCvz5mouhRXmZJeemcRztv5DU2OgTgh7C92d877YOR8ELjzN2jqWpddgwBmEDuZu7jLTCOGGmCnyIcNgU+EjRIYbjs9ox3GDtP6aztVkK43ITRFJ9dh2s1k6FOEyhOVN6bkMW2WsAxOyWOaKd0Cxid0VQzbG60EWaYSzhqAC02jU5cRUuzy2MbKMRKTjO8Xoo2wOdx2ISuXeGIBfzsY2xnM/abRbG0srlX7J4KfQxd1Dobf7TAwpeRZ2oAqqAKqAKqAKqgCqgCqgCqoAqoAqoAqqAKqAKqAKqgCqgCqgCqoAqUG0K6EGFapNSiSqpgB5UqKRwGqYKqAKqwKamQKaDCj0Ohnbd8aBCciMtt9mQdq4rxt7owOKlPzTmB6tF5XIHBGbO9WM+xkh/tR1UECmZn/PRXvnB7ZmXkVFweHscz5g0uwnE/NwE5HnEJPNBhYdPtb/ub2Jd35JgEVOuSZiwQSlyMUba2WaAXrO8iSzj5GFTYLT55fZC14Hn7w8HnNc2HSbyI2jYTSNh5tuz0vHOc+Id7aH1QdvRKmvdC2YthL4XvZL2Z+Fz1mtQj+7W0KS8ibflTGJ1S61f/v0AmD+t8C+kn/FMF9him83zvk58XpHP71cmNUCE5H3qBIfnla8FNDImxe5z503k2QMfUVOFsaprsG7ei8+N+sQ3JmrlaVJcTtUGXIhK8BB1HM/+NLsJyqr3R899Ah8+PYF3oGMtU2DevHmAv9hfytcHH3wAJ554IsydO7faytxqq61g8ODBcNBBB1UbZ00Q4R0vysvLa4JaOWuBAv6gAn9+mPds+m7p3rv9W3iOPQDkZ4//Xhrc9OHNPIzFNc/xw93PnWaEJ7s1SF5Zn5RYcvjt0MRmZxvt0Cag8GDHpcDaqa2N5+LDEfNxTud2fGHFfmIWibw9QK3urgS5x7S9c6jnwuoxh3NIOxXm/OiO+yjM14cclsQObs4k8Xjr9pxcA+dAN84dLHAn8RmQ3DtDKN7X56yIRV5v9xm8DS1LliyjOyjgAQU8rKCXKqAKqAKqgCqgCqgCqoAqoAqoAqqAKqAKqAKqgCqgCqgCqoAqoAqoAqpAzSigBxVqRldlza6AHlTIrpUiVQFVQBXYpBWouYMK3DXrGmCcytwoi0vRQuMbaKNPRkDIOIkJiNCEWy0HFUL5lE7mj+YM1fi+HTbFONhMI/f2xDEJ9pzcjBGExRxUaLFraGAlqjhfvCaRx3c9xTHIEbNF6s4RR5ICTB421RxUeDNqTFjtd+Y+8F+/Pcg0RCU4Y/kXfbcYXrqwf8FfhG+23RZwxlNd8AVJV+a6Tb6h178Bs8Z/m1BM1LT/uW3hwAv2z1R3JNLUhIchFsxcGDEnLc575Wxo0KRBYsNZBB/Tifeb+rrG4LjeMY4IP2PjGLTHbJybUiQ+qYJZxEbiRHECUimt4/VR9qrULQui7QdDqt6sn9h6Yl3sT6jPSxLSGYqwoNwJefCX3t956D34ov9XzK5jLVQA71Swzz77lGzl48aNg1NOOQUWLiz8vlbsJsrKyuD111+HI444otjQ9Yb//PPPa8WdH9abIJtYIn9QAfftPvfsYN+U/UehmZDFvVf7zwxee6D7Ps12ExVcYe4b153TDi4IS3H12BEXgZdyB6h1oj8kcjlDPoqOxKAvGPzUTCI5vYMKwN3k5GMe9tgQXoW6GMcEfu2gzJ1mx9QEdTVxBo9nDbyDds3paEQshnMudhIl+izKmhlHTm+yCLa5XEk1sA0hBPP8aOBcuXNMwPQ0x2j6Z0e08UU5mMsmIRfaFy9eYg4ovEZ3UVhqDivopQqoAqqAKqAKqAKqgCqgCqgCqoAqoAqoAqqAKqAKqAKqgCqgCqgCqoAqULMK6EGFmtVX2QsroAcVCmukCFVAFVAFVAGjQNaDCvvTHRWSJZMNsIwQ7TBsojEJiw7E5/qoA4bieBbHyDzsy3pQoWyHMuj2RCfijz94Xtfby9yI8z4z93YuMELkjIYj4vZmJDcL7h8mu7lzAqPjuSMkkUQwbfR0GHnb2KgxYdXF3FGhxS54UCFelASHmiIpyexqRng11I00uN/PXv4C3n34fVzmvQ668ABzd499UzC2bq55/KPvw6d9v0jBBvPPf38w7NftZ96Q/zn1MKr7u4++h0HXDAvGlFnjssZ0V4V6jerFEK7a+NPhzevglT++Dj9NnheLy112f+EMaFLeONcRs9Dri5874+P9+tcd2TAoXhTa+PIF8qvVOoLZrjkP2Sv32kYiX5vj45ojPrOw7gJ1J7lNfZZTbMBN0ZOmWXTzWE30qp66Q02+JEzjzbhrs7Cb9/Z43VIzjpXVLvxmEQy5djgs+VF//VjqUhvnvXv3hjPOOKPkSseDMP/93/8N//rXvzLXdthhh0GvXr2ge/fu8Pbbb2eOu+yyy+Dee++NNEZnDq5hYJ8+feDMM8+s4SxKX6oKRA4quCK5wdw3k7uucd88bt7i/eeJ+CDgOPIJDNuRnjnQlmQXzBE/f05wDI9SV2njOeezuUWxTBirifbsYMxRMIcl94wyJ38IIlcqn8jndRVJZZzkZjuPtgwS3kYzb059zmHsPh+GOfKIF20yKcXgg4tEN+48BGE24iI+4SKIj+N4G8i5Kdg9RPEuD5EHlI2zSRC/dt1aGDn8bXj6iT4wY/o3AagzVUAVUAVUAVVAFVAFVAFVQBVQBVQBVUAVUAVUAVVAFVAFVAFVQBVQBVSBGldADyrUuMSaoIACelChgEDqVgVUAVVAFbAKlNJBBawo0kwrunBsW42tWWJ8w4+ILeqgwuPJBxUwUxJ3Pjv6cq9QeZil75O7jdNy5/JbCx1UuD3rQYXmaTTCHqoNM1l31MqBxdbNcR88NQE+fuFTXqaOR/35cNijw24p/lDTmhUV8MK5L8HKJatSsNZcr2E9OLtnN2i8RWjwl6+vvMHGifvtd/EAmDdtfiEoHHH5obDnyXsk4ELdYRa0HnT1MPj+4x8S4qKmzg93hHI6hBK1J62SnqckW1JssIVqwyzUjeqEi7vo0/+uAjZ5llZfmj2Nhe3R6kJ9G1PdWbWZO+knGPo/I2DFwhUsj461WIFbbrkFrr/++pLawdq1a6FHjx7w+OOPZ67r2GOPhVdffRU233xzWLJkCXTq1AlGjhyZOf63v/0tPPLII1C3bt3MMesDeOutt8INN9ywPlJpjhJUIOeggm8kx2LNuzZ9ONlPKDsnM33foO24Dy96f4/N5Xs+N6IzB67ZRplkLBmin8/8Ec4xPFIN5oHCmRzXbh5MvJdIhNuftWEMxXEtIZiDAi9aOIebuzA2IwA9dFleqYgxGzdZeERTPKfwWbzlo0hHH4lBPHOwH0OMDZecj0z4QFZyuwe2WJ+tO+D8zPHZmjApetyFS/JbO7to9HFOC7Pmy9fNNBTu/LG5hRgOctehAwojho2DZ556CWZOL3xnMc6poyqgCqgCqoAqoAqoAqqAKqAKqAKqgCqgCqgCqoAqoAqoAqqAKqAKqAKqQPUpoAcVqk9LZaqcAnpQoXK6aZQqoAqoApucAlU9qJDW1O3aYXL0LIS37cLcNOyaZRwLryQH55G26jqogGmRX3LbUmzWXLsrNGfgym1fUXIcYnjfMots/M4h9obqP6iA1LZurj637uDxhVBUkmYSkTt/8//ehomDJ+c6YpYTbvsltD54u5hVLm1NXw+cCOP+9Y50JM73OH43OOqqw+l5RkDuHhPDIsbJQ6fCmH+Oi9iSFs13LIOuj5qDMSxbBBSMOJN1vPH30TBj3MwIOmlxwh3tofWB2ya5Em1Jr+2kv6fEYG+0dXP1sm4LCR4fYiZJuaU/bW7j0Jv7t5KbO52FPXGt2c5/qWFta8Z19jwhOnm/Vu3sfKwlVxfVwGazOwqZC9eNh2CG3zwKVi9bLcN0XosVOOuss+CFF14omR1UVFTABRdcAD179sxc08knnwwvvfQSNGnSxMcsX74cTj/9dBg4cKC3FZqcc8458PTTT0P9+vULQdebH58fvOuFXpumAlde3QPKt3QHRl3TODd/4/cD+U7ve8rJHpz208Pox3aU0gV6H5oMAXPYuQMxPBZPsQGCrHRxQ7sfg4NnlAsXfi+xefDhzNbm64/l5DyMI3d4sFvFvRET5yQ0WXy8wGBhAc8zSxDwbm0Ls1zy0dVg92ixTCo5EIZrn9Gls4OxujVPeImMlsdYHIixnsuC8JEhFEM48+C5xJxrI194cBw+gviIIZjsHtwafXgHhTeGmgMK/3kJZs34jjj0QRVQBVQBVUAVUAVUAVVAFVAFVAFVQBVQBVQBVUAVUAVUAVVAFVAFVAFVYMMooAcVNozumjUooAcVghY6UwVUAVVAFcijQNaDCu2675vLgn2yopmFAdjIkrX5lltqongmNQkScnAM5ovGkQHGP/YBTOhZ+Nf5y3Yog26P5TaOr1u3zjbm8IbcmFBKQHDJjE3hCAG2drkX6fPzGC/ZEwrJelCh87/Fr+4ncKft3ddjJgnppdvOE7iTAjnf0BtGwDfvFf5F1i4PnwotdoneEQI58IUoU+JdDuZPX5BbV8xy0j+Oh5Z7bRWskgStSI1XzM51o2tNxVroc8HLsGpp4UbvDrceB9v/V2sMA8lBhoQHfH2/ec/bMGnolARv1PSLa46E3Y7bxRpTnqQsOSOssX2jLwtHSvoIdVxTciYEpuVLgAb+WN3IgVf0VRLgOEOt8/k9Osad5TXiYylPzsspuGPcaXsPAVWre8bbs2DUHWNhzao1klLntVyB3XffHSZNmlQSu1i5ciWcffbZ0L9//8z1dOvWjQ41NGzYMCdm1apVgIcP+vbtm+NLM3Tu3JkObjRq1CgNsl7te+yxB0yeXPhg3notSpOtNwXwoEILc1CB3u6xu5z+2RGLILurhhvMCUOd6NHPMe+PBfJnmQ0xK6Q3DxLPecjmFtLvSqCB7QRDHnbaBFFMgg0BwhzqMETE5gktscyHc47FT2nioodQB/uJjSCO0Dlw5TkDmLjowQBkHYylNGG3giOEerfgQC5M4yvEAsxFg3G4JRYV7DRDE9rMf/TPjugSUQgiNA5cq5wT3mMs1toozD1Iey5fBGm41q1dB8OHvgnP/qcvzJqpBxSkPjpXBVQBVUAVUAVUAVVAFVAFVAFVQBVQBVQBVUAVUAVUAVVAFVAFVAFVYEMpoAcVNpTympcV0IMKrISOqoAqoAqoAnkVqPRBBdv3a7lDr4tvpMk5QJBQhWy6ieKZ0CThPGwyPKlxDluVgwrc0IzlRvOEDYhSEo1pHAFsm4t5LfOwLTLKhKwHAoR96qjp1HAciUtYRA4qxDiKqbtgzTFu/zwKO+fD5qeeZ/aBVUtWJVQcNZ3T+0xo3Mw0m4q9Mw/X9P0nP8Kgq4dGA0tktd0B28KJ/2hPzf5cEtfNax75b+LDpz+Gj3sVPnhzwHnt4IBftQ1/M0iUoJM1Bwe/pIKFK3CjcLDWcQ4ZwXWn7UtiZX1JrxHEck7JxzWjX5SHy3AJB3OgU/IwmGtO8zPOj4Lb1y1safmKqTuNw9dgJkXVLerDmicOmQxv3fcOrF0jq5LsOq+tCmDj6uzZs2GrrcQhrA2wmWXLlkHXrl1hyJAhmbOfd9558OSTT+a9AwLeoeE3v/kNPPvss5l5TzjhBHj55ZehadOmmWNqAjh37lxo1aqVf1+riRzKWdoK2IMKZfazSDaTm/do+TaNzeh+zXMySLv4TPPgYEP60Mhu4lw8KhSmbLdWiwkacnyIcfkDQZQ3r515Rc7I3qyfc3K9oSYid7W7OkyI9HMs7dDAbYQFcWkh0tVDuAC2OHo08XbEgechH/JaDp/X4RDDeI9BqHG4EBtMOHLgQ0xL78zhInZ0u2JoYG4ekS+Qujka8CJPLB+xsotQa9eYOygMwwMKL8M3s74nmz6oAqqAKqAKqAKqgCqgCqgCqoAqoAqoAqqAKqAKqAKqgCqgCqgCqoAqoAqUhgJ6UKE0nodNuQo9qLApP/u6d1VAFVAFilCgygcVbJ+Lyxiab2QDbVo5AR1tuA0dMqaBlntoI3lsI01ODoct+qCCKNBS2Eeqz3G6wTX0xAJitaGXm4z9HpMwbnN11jlnHOOTinwp06mjizyogNycD0feZ/yX5xnj8rLmUhvPw7VJbrYljDblOpj9xRx4/crCjax169eFX796LkBdR+bqppoMGWs94tbRMH3czISMpWGiu0Ls3Dzza2SG2cuIW8YULL6VuTNEx3tPSsWx3gjwrzkzt3Zjiz3X5GCb0xpjC722q/M1Qvn47wRfaK5YXzMCuEac44VOtrm6+TWCbn6deAwazZVTN3NYt88dj2O3HG199lH+rfi6k7jjNqypwN8j5vR1F/E+8ulLn8N7T3wY9iSL1/lGoQA25Xfp0mWD7WXx4sXQsWNHGDOm8HsXF9mjRw946KGHoG5dfpNnT+64du1a+OMf/wiPPPJIrjPFcvTRR8Nrr70GW2yxRQqi5s39+vWjwxs1n0kzlKoCV15j7qhQ7g4qmCKp0dy8/3PDua+bm83Fh7Odmk+V2OcFfc44mx0ChnlxDHHROeZk7jDPrYm4HQnjAydFJvIYJpHb4mQe/FyVdUZ8GIsGvDi3m7M91IB50Go9wW5NxGRcghGZCM4+tyQz5kuyc60EQj6RiOds4nhbUWBnv83h7LHamAu3wzy2MPuIfsYQH66Jyo1m7vOyj/z2gWJwiuwOyJFr1q6BN4aOg+ee1gMKJJE+qAKqgCqgCqgCqoAqoAqoAqqAKqAKqAKqgCqgCqgCqoAqoAqoAqqAKlCCCuy7776A/7/z+IX/v/RLLrkkbta1KlDtCuhBhWqXVAlVAVVAFdg4FSj2oAI2sHBjbK4ivh3GuLgl16IiceiSUFpag43iWNsuk57PcvtUhgIj3n30fZjQs/Av0JftUAbdHutEpfqMoi5uErasLhcOjDFBXBs3ChGKyczC+zGI4wjkHiSHxAg7w0kNyUEY650+ZjqMvGMsQ1NHuqPCzi2oriQ+DixUd9DGqcN1Zajb9V5bOUzch89+DBOe/4RTp45b/6wVnPzPDibOBHE+RJucdlgHS2YvhZcu7A94l4ZSvfbosBsc9d+H+/IKab3khyXQ+9f9PD5tgq/Bs3t1gybNmwSIeI1wExrqxTndsxfwrKvAVPa1XR2vESyM687hC1WH14OrO+01giG89xyM4+M8Eb/QI5pWvBYJY71cM66YL5PW8rVt+PgqVLN8TvPWbTjff+oj+LTP50yt40aqAP4fHR544IENsrv58+fDiSeeCOPHj8+c/8orr4S7777bN91mCcS/rauuugruueeeLHDC4C9KDBo0CMrLyzPHVCfwT3/6Ezz44IPVSalctUyBog4qyA8Tt0/8TE4w+78d+hhHjMDjFGPk53mYMzL4LX+BPDE+l87lsJyyzpCPqmE41UUWrJmKtK4Qm1CfDRB7ZDrH4TyBw/gdDebA/4lcZkk2xrCTsBhrHT6K7eSiYIqQe3QhNpPA+0ICraE3h7PiOZgbmSlFyIMmvGgvIhHnt3t0GDvQI/vjfN5uUHgHhWFDxsLzz/SDb7/5QUTrVBVQBVQBVUAVUAVUAVVAFVAFVAFVQBVQBVQBVUAVUAVUAVVAFVAFVAFVoNQU2GeffeDzz3P7P26++Wa46aabSq1crWcjVEAPKmyET6puSRVQBVSBmlCgmIMKsrGHG2ejNfkWHmMOXbaROO5Sx0ABj2BcbJItmi+Shhp20P/uox+YgwqFG9/poMKjnWw2Vy71+2BdZk17ZDsXyzWbkRqQ2Y+BLg5rcFuwHLgmt8Pgmi/Mw5qg2zUcSW6GRjioPuPB/CYu80GFhzpCi12a+zjS2MRzvTz655dKpgdfBk5kfVSz45Ca+QDJQft1HrSb/wZcPgjmfD3Xw9MmB190IOzX7WdRLXH/+B8N6+CD/3wEn/TO/RJuEaXxWK9BPTjz6a7mQEFjKqiQ1ri/5898EVYuXlVwA0dfdTjs/svdSCOMI2nwgZ4DO5KdX3PGYVz2wgn+R3EumOLowetsSXFJ7NHnw1HhUJ2vkRw+rhrrxatQ3a5UXzOG8N8sEbiHPHv3f6cSj9L4v1njYEmwnnhNZEIjTcKIOfn5YD7Hw3y+bvQjsaOxJOYxiQPNyOu48PDOW/e/CxOHTPZhOtl4Fdh1111hypQp632Ds2fPhg4dOsDHH3+cOfcNN9wAf//73zPj48Abb7wRbrnllrg5dd2uXTsYOnQotGrVKhVTU47ddtsNpk6dWlP0ylsLFMCDCuXl5nuYu/iziD9L2I5fkOit3n3GoJ3XdvRImmB8xO/czIs08vMjzCmKvo/xh4tNaRDW5RMxFxoKY6LxMtYSCj/W5pKFkdOGIrzPFcCeUCdyotV6gt2bvAYGyQlopDhn8h5DQHNHlGvHTMbqHFwfE3N+tPtYnnGY91mDR8qc5OIAZo9phm6O8Zy+tLBHnLHfxNhlHaioWGMOKIyBns/0h+++/dE6qvC4+eabQ8uWLWGzzTarAouGqgKqgCqgCqgCqoAqoAqoAqqAKqAKqAKqgCqgCqgCqoAqoAqoAqqAKqAK5FNg2223hWHDhuVA9KBCjiRqqCEF9KBCDQmrtKqAKqAKbGwKVOaggm+azRHDdbyQnTttsUkm2GVDrgxnTJSbrdhrG/hkXCSVa7wp5qBCV3NQIU6NfT6UjZuHIzswGd12/F5cQdwgxHxJNXuMi4nmwd4hcceKpC2b3KiKjXMkZpg2djqMynJHhYdOgRbmjgr+cny0dvly6pYYA4zXjHrYmozHcXh+njAm5l8wcwH0/8NroVGb8Qkj3v2iWetm1sM1Cb6KVRXw4vkvw8pFKxOiS8u0f/e2cOB57YxcYgOuxKTXyPCbR8Ksd78puImdj9oJjr3uqMTXCAbTa5tSct7wN0bkRleqid0UZJ9f8jt7Tt38fBCoiq8R5BD5M/89YpCI49eltMXrTtLavBjdLszAr9s4d0C4v9lozejOXLfMR3EmKV6ujHjN6Cq27jWr18Dou8bBjHEzMVyvTUSBTz75BPbbb7/1tttvv/0W2rdvD1999VXmnHfeeSdcffXVmfFpwLvuuguuueaaNHeOfa+99oLhw4dD69atc3w1Zfj000+hbdu2eemPP/546Nq1a16MOktXgREjRkCfPn3yFvjnay6GFuVlAWM+LPDzAh/cu7/1yXXq3EEpHD+wYhxsp9G4OQNCcU4JzYxG5IrOyeJ88c8dG2OdId4wiEXaHHnxIr+hiOLI42ryhQU8xhHE78ZhOY5j5F4onAIpykECg6jB+KIYjrVB9Gj2SNvE0bkpu9g7m9HE++PY4LPRnoP4KIAhNHKcHYOLebEInHPddm5xFONCCO9qZHvFmjUw3N1B4fvvZgfySs7wMwB/nefII4+sJIOGqQKqgCqgCqgCqoAqoAqoAqqAKqAKqAKqgCqgCqgCqoAqoAqoAqqAKqAKZFVg/PjxcMghh+TA9aBCjiRqqCEF9KBCDQmrtKqAKqAKbGwKZD2osH/3/UzfrGsE5u4WJwa36Xg/2qlhxgKknZtqcppvRW+woyUOP4/lxpw5Ia7hd/xjeEeFT0Noyqxsh2bQ9RFzUAEvJovsLSzCDKEMtqEFHxnuSfzEhRoAYuJmSZzmd9zTxs6AUf8YKyMS550fNAcVdhEHFRJRxuh4ye3r8hMLSKuJOZlDhqFP2EfcNiZT83TkuWL+2Dhp6BR48963Y9bSXDYua2zuqtAF6jWsZwsUmlhDVLQpI6bAmLvfKriZuvXqQOd/nwpl27sDHRiRw43GwB9mCGUwYgpcEupJ/MQEGwBipClOyRxJmBxfAIWZJaxU3RESuahC3Tk1Y32BO8yK1BppcrglmwMgJmZevXw1vPH30fD9xz8gKNO1ww47wK9+9Sto0qRJJryC1r8CY8eOTfxlBFlJVe9UILkKzadNm0aHFLLeLQC/C9x///1wySWXFKLO7H/wwQfh0ksvzXTwDUnxrhN4WGGXXXbJnKMqwCx3fnjjjTfguOOOq0oajd2ACvzrX/+CK664Im8F+Q4qYGB4CzffdHkhvlPL79cM5sZ0/o4tC2AbUvE8yhHyeD8R2OS2hoBJ45a1MEbyybn0k5336RxoS8MjhOBCE1uj9cg4OXfUltflM1nYHPIZE9k9hiHkoIWvL5i8ndE8Ym0RvlCsz+lSmRC3b4FBHvIbm8f5ifE5bLQm5LEVeCjHO8cacweFoYPNHRSe7Q8/fF/1Awp4yAoPKBxxxBE2sT6qAqqAKqAKqAKqgCqgCqgCqoAqoAqoAqqAKqAKqAKqgCqgCqgCqoAqoArUuAJ6UKHGJdYEBRQomYMK+GvT33y7pEC5ye56ptmuaZP6pkmqATRq5Br5kqFqVQVUAVVAFaikAkUdVJC//O07X1wDjskv7zDAjTNYVqrdd94iCJGxi7ts0CxyR7hlSGUPKiTlRl6Rn7dLDdESHxyyEtdVZEwSKxGCW+4tdCEJsOTgfOgW9mljzEGFOzMcVHjAHFTYVRxUEByR3NIuSvGaiOcjEiexkoPrFrafpsyDVy8fGNmHDJfz/U7fBw7+zQHWJDjI4Lhf+dPrMG/qfBlW0vMjLjsU2py4e/r+xWtk9dJV0OuclwB/Gb/QteNhO8Avb/iFhcW14mDB7Z+atOdUcjAYeaSdeXFk7jQ+iZUcxXBjGscj31+8EX1J3NLm4mngmilOgDiJxAq3jXXOuJ1jBDfTra/3kRULV8CwG0fC3Ek/cTUFxxNOOAH69u0Lm222WUGsAjacAp999lnBuyXsvvvuMHHiRPMnya+8mqn366+/pkMK33xT+K4vWEG9evXgsccegwsvvLDaC3rqqafgd7/7HawxvxKe5dp+++3psMKee+6ZBV5pDL5PtWnTBiZPnpzKUVZWBrNnz4aGDRumYtRR2gpkOahw5TU9oLy8ediI+fukP1H3d+r/WtHOKOmL2C0AkQhJ+ltnG47EF+NCBmu3M+e2xI6XPFFHAlc83lYfwmyNjpiS2rqxcG+liaxZeuQeZIjMgUJ4n5wbIuZFgECRdlyE53ITy0UBsdpw6bx2iPi9F2twfp+T15EcNsKaDICDOItZU5iLJTTHyxFD8X8czsNdfIU4oPDjD3OQpkpXhw4d6IDC4YcfXiUeDVYFVAFVQBVQBVQBVUAVUAVUAVVAFVAFVAFVQBVQBVQBVUAVUAVUAVVAFSheAT2oULxmGlG9CpTMQYWVK9fAX28YXeXd1a1bB8pbNIaddiyDnXZqBrvu3Bxab7d5lXmVQBVQBVSBTV2BrAcV2p29b1Qq3/liG2LQKRuGfTMQ2rFjmJt4TRw20CT+AjpjOBN32dA6iYOBOAZ/5jsqmF+d93dUkFRyTjWIwsRUwio3RxETCIW2SW4jX05YUQcV8I4KCRy0hzR7oQ3KmhGbsK04xfCbR8Ks976NmxPXHe85EVruuVWiD40/fj4bBl49NNVfio7mOzWHLg92tM9FWoH4+nMN/2/cMhpmvjMrDRmxn3L3CdBq75YRW85CPmdJz1faayHNnpMgZpD50FVMTkkleSrLIfl4LrRmE42F8kXAKYuafB9JqXvp3KUw5Po3YOGsRSlF5ZrPOusseOaZZ7RROleakrRg4/ukSZPy1jZmzBg46qij8mKq4vzkk08AG1V//PHHTDQNGjSAZ599FvC1VlPXiy++COeddx6sXr06U4qtt94ahg4dCm3bts2ErwwI74Bx9NFH5w0999xz4bnnnsuLUWdpK5D1oEILc1CBPlrw/Zv+2RF359rRc+zWhwCPCBgyEyPCfJO6nVu7bPKXdpzjRR9TmD3QWIewye/2BIvUwnmIzcXaIc7teUwI7SaW0/tNOM8RQnOZ02VhDC3dBohSzCUmOnckYp9sQTFsaeaR/tkR/WSnB4cWfozC1BztYz2xJeA6IjRUs7NwfuZis82eW5NNSnmJxtdZBypWV9AdFHo91x9+/GGurKRSczzUiHdQOOywwyoVr0GqgCqgCqgCqoAqoAqoAqqAKqAKqAKqgCqgCqgCqoAqoAqoAqqAKqAKqAJVV0APKlRdQ2WomgIb3UGFJDnwoMKRh28PBx6wNTRsoHdcSNJIbaqAKqAKFFKg8gcVRFsN/3K6MPnmHFNA5FACNxYLLNbI+AjWW1M44ptznOMf/QAm9Pw07s1Zl2U5qCCisDauU5j9lA9qcOORd6yHSdEHFVxNpDc+J0a7fHur7i1krRfzbrPf1nDSP46PlBDXetQ/xsK0sTMimKQF3sGgaYsmSa5qsTkpYaq5w8Wibws3iHf4+3HQ+qDtMuWeNf5bGP63kZmwrfZqCSff3cE3+GUKygMivdfzayRPOeQq5b/HfLWvj7oXzFoIQ294A5bOWZavlIjvD3/4AzzwwANQt27diF0XpavA9ddfD7fddlveArFhHw+f1MSF/0ePk046CebNm5eJvnHjxtC7d2849dRTM+GrAhowYACceeaZsGLFikw05eXlMGjQIPj5z3+eCV8s6Pzzz6cDGvniXnnlFejUqVM+iPpKXIGiDirQd1b6YLXfv2gtvovxZ66z89bxOyab5PfN6JzRhs91rPs4sQ4oxOHKcDO5cDIHITjeLnwtHMg8IjyH2/OZXLSbWE7JwViE0B4SCmQM5YzVR2W6WPLLOeW31ggHA0kPVxxiJTdjnBuF4L3giFBay3wcQzZ+QBxfNo4tnA8BxOWAzJtj5/rM6KbmTlwVMHjQaHix56vVckAB3/NvvPFGOPTQQ7loHVUBVUAVUAVUAVVAFVAFVAFVQBVQBVQBVUAVUAVUAVVAFVAFVAFVQBVQBTaQAnpQYQMJr2m9ApvEQQXe7WZNG0DXzm3gwP23ZpOOqoAqoAqoAhkVqPpBBdOajd3ZeIVOG9tQY63JBxVS8NQ47+IsxJJG7JxP4Gjq8tfEQQWZ3zcIifzcOO9rFloIWI1Nszb+d37gFGiBd1TAi566IKZviLLeGnucN3U+vH7VEKhYWVE4h9Hx1HtOgq3abBmwsbqX/bQcXvpNP1i7JuwlgMNsi202h26Pn+YbzYKnembyNTJ15HQYc/e4gsTbHbAtnHDrLwviGPDqZQPhpynZmoL36bw3/Px3B3Fo4mgVY90SXtkxrdfXaySxWGGUWidUvcFe26LExGmhuuX7CLUlVuJ9ZO7En2DYTSNgxaKViTUkGbHh/ZZbbklyqa2EFfjiiy9gn332yVshHg6YNWsWbLVV+h1p8hKkOPEOAR07doRFiwofyEKKzTbbDPr37w/t27dPYax+8/Dhw6Fz586wdOnSTOTNmjUDPOBQ6M4HmcgEaO7cubDDDjvkPTSx5ZZbAn4fa9iwoYjUaW1TIOtBhXJzRwW6RGM5f4e2b/vm0f4zY/ggoBk2obMwbkIWM2ePCPHfefDzm+Mx3GI8k0zjYyxOYsTckXgLTUyOqAFRPpf0+bnBc928Ma6NR+JwRDaNj0ArEggO4TMEvhyEcVKJJ7slYTeuHKnldSQ0xDg5QZw7gk3MZ7OgOJaeQDYfpWe7xRG/BZKBvG7NuRmDvoqK1TBkoD2gMPvHn1yyyg8nn3wyHVA45JBDKk+ikaqAKqAKqAKqgCqgCqgCqoAqoAqoAqqAKqAKqAKqgCqgCqgCqoAqoAqoAtWqgB5UqFY5lawSCmxSBxVYn3b7tYIzuu0JeHBBL1VAFVAFVIFsClT5oALfTYHTxZpoZGMuQbgnGhcCa5d1oocaCJJr8wcjMEhejq+ogwoP5//14lBumIl2KMqes8fQciSrq9E53k1g1J1jC+aggwo724MKvm7cGmkXbYoqSFYJADZPD7hiICyZna1xdJejdoJjrjnKZ/I1ewvAR899Ah+/UPgOGv910UGwb5e9RWT1TMMrI8zWVqyDvr/tD0vnFv5F+84PdoQWO7mmxQIlzXxnFrxx6+gCqOA+7A8/h71OaRMMYmarDTVbV/Q1kKt31C/o1ts0t277h+/+/HPeQ5L2td6KFYmS6uaaEZakNdolBtf5rm8nfA8jbxsNq5dnOARkiPDuCffccw9cfvnl+WjVV8IKYNMo/h8f8l14CAUPo1TXNXToUOjSpQssW1b4/Q1zlpWVwWuvvQZHHnlkdZWQmefNN9+kAxULFy7MFNO0aVPo168fdOjQIRM+C+jWW2+FG264IS/0T3/6E9x///15MeosfQWyHFT48zUXQ4vysrAZbFTHN3pLkIo9AABAAElEQVR6EO/5voHd+vxnQcQuaSyCHgVGNrFHOMKCU3syGYNGXnsA2qyDTHZuvVGs2xvi3f4cysZxDWakbxdujdCAZ1CwkUXskT8oLQc9Ov4Qaw2xPBxonCGfmGMdiHE0zCax5Oa9MZ6S2QfEUhz7aBQA46Vw++CwFGHnDhrPieZIbZjH/LfaHFAYSgcUBsCc2VU7oIB8fEChpu42I5XQuSqgCqgCqoAqoAqoAqqAKqAKqAKqgCqgCqgCqoAqoAqoAqqAKqAKqAKqQHEK6EGF4vRSdPUrsEkeVEAZt9l6M/jTxQeaX+3UwwrV/7JSRlVAFdgYFch8UKH7vrYhxohADbfygILtp3GOBJXYjy7ZF51mZwrpl7HC7tp/bJOv4x7/2AcwoWfhxvWy7ZtBl3+fytnSR8onksq9J0VRsxE7TFFYlwhnT0QLNEbizLpQHk8EgAcVRt/1prAkT0+739xRYeeUpvhI/pS6ncaePa4NbiqOceCKFRUw/G8j4YfPZvvwfJO69evS84N3Qki71lSsgT4X9ocVC1akQchev1F9OPM/XaDh5u7XqouoOy8xOxP4Puv7Bbz/1EeMSB33OH43OOKyQ7O9RswL6dXLXod50+an8klHnbp14Jc3HAPbH7ydNId5pO70584H1MBrBO8iEGnA88lSJpGaEVOg7jie/67ILnLEX7fxuEJ5BFXitFi+LFpjIlf39HEzYew/x8Ga1WsT08eNDRo0gCeffBJ+9atfxV26rkUKPPbYY/D73/8+b8UtW7aEadOm0V0N8gIzOF955RU466yzYOXKbHfswDsFDB48GA4++OAM7DUDef/99+HEE0+En37K1rTbqFEjePHFF+G0006rckF4N4dddtkF5syZk5drwoQJ0K5du7wYdZa+ArXxoIJsdmeF+TM5PrKfR/bjmj+yorbwQSvt/IWHY2y8wTo42gM+l4MsBuQ9boIWy2kNgYMrdrwCzx6PNT7PzHOPt+gcrPNjQT7WEdNerAMfsQA7Oj9FoIMKdz67iQjO5yQOGyxtq1dXwNBBo6F3rwEwd062O2/5EmIT5D3llFPgpptu2qDv3bGydKkKqAKqgCqgCqgCqoAqoAqoAqqAKqAKqAKqgCqgCqgCqoAqoAqoAqqAKhBTQA8qxATR5XpXYJM9qIBKb996C7ikxwHQuHH99S68JlQFVAFVoLYpUJmDCrhHbC72FzfoCJP34YT9OJeYNDvi8ErzC7ts9+Gaqv2gAtXiksp9U5EpD67JKHLYgOuWGsTDk+LimIR1tRxUQMGxxvges9ZN+0re3MJZC2HkHWNhgRmzXnufuicc8vv8za1TRkyFsf/3dkHKNifsDof/6ZAorpJaR0nEKsa3aukq6PPrfrDaHNDId9VrWA9Of6IzNGneOLzmk2UkmrmT58HAvwyBtRUZG9LN96Gjrz4Sdviv1sllxOpOBrG1iq8RpHGvL7zbxIfPTIB5U+fDaQ+cwgmyj8XUnYYt9NpOi8teZQyZol8M5ZdJ+blmBLnXyaShU+CtB9+FdWvzvHA8KUCTJk2gd+/e9EvzwqzTWqjAkiVLoHXr1rBo0aK81d9+++1w7bXX5sUUcr7wwgtw/vnnw+rVqwtByb/NNtsA3n1hv/32y4SvSdCnn35Kd0n44YcfMqXBgzxPP/00dO/ePRM+DXTHHXfAddddl+Yme7NmzSDrHR/yEqlzgytQ/EEF+5lAb+vu/d4O0o7bijawWwuZcWq97rMBkfzRQT7PG+VgjLOG7x8RPsslG+KRky9fqzHwnHmpKleTJM/B0VZ98UQdxXDd6LI4ejQgF0Vm9nAsoe2COHPWJoAZ/P7IRsiIhrzgfISnhdUnJLAz5LVuHrnyZG7Lax7pHz54i6e2hOhyPjeuWmXuoOAOKPw0N9sh1kAanSF3x44d6YDCQQcdFHXqShVQBVQBVUAVUAVUAVVAFVAFVAFVQBVQBVQBVUAVUAVUAVVAFVAFVAFVoOQU0IMKJfeUbHIFbdIHFfDZbrtvS7jw/A3fFLPJvfJ0w6qAKlDrFCjmoAJtLq0PFvtm8vmkMozLF8N4248TuHnNfjNiGxAfUkBzVQ8q5PTpJ+QU6UtiWpWDCrhf1+9ULXuJ800dMx3evv/dgg37Mnmz7baAjv88MdwBQTrF/LUrB8PcSYV/JTvvnSQEX9Zp1tcIvha/ePWrgrTtzt4PDji3bUEcA756fSK88/B7vCw8mtdwuzP3hXbntBVNboXDGBF/TtlemREPbnz20hfwef8voWJlBWy2VVM446kueamk3tX5Ws2btIpOWTNS1VTdn/T5HD58dkJ4jyxQd/PmzWHAgAFw5JFHFkCqu7YocPnll8N9992Xt9yysjKYNGkS4N0VKnM98cQT0KNHD1izZk2m8B122AGGDx8Obdq0yYRfH6CJEydC+/btYdasWZnS1atXDx555BG46KKLMuHjILyLwh577FHwEMJll10G2OCuV+1XoKiDCuJDwX/NNDZrNhb7j0Z84AZ1VoliEO8M0i+ofRz6OQZDGBMY0MZsAWBNmN8lEkOwod8CGI8wOecwttFoQih/jNtjiINAVLu5/xLR0KMBcZjFo4vrdLjg8PURgYUiOtgdWZw74GU+g0Ju+89DcI2X5bUjrZ2dnA5Epbn6vNusKUvcbkkpnHXGOygMGTgK+rzwGlTHAYVOnTrBjTfeCAceeKAtUx9VAVVAFVAFVAFVQBVQBVQBVUAVUAVUAVVAFVAFVAFVQBVQBVQBVUAVUAVKXgE9qFDyT9FGX2CtOqjQ/cy9Yf+2rWC1+WVg/H/SrjG/BrtieQUsM/8tWLgC5sxdDjNmLIRJU+bDypXZmmPwGf7D7/aHNnuUb/RPtm5QFVAFVIGqKFDUQQU+YJCW0HfaGIDAclMNhq2TDoGJULoGHf7ldfIZbm4RKsRRlYMK8eZirotL4nXSyLFZsEnxcVsxfNPGzIDR//tmnCJnHW/Y5xwIrI66Jd+6NWvp0MhXAyfm1JHP0HDzhtDx7hOgWetmqTDMM/urOTDo6qGpGHZss28rOPGO43mZOHLdWTRgbJwoKXbJj0ug7+9fLfhL943LGsMZT3YGvLtC1mvUnW/C9DdnZIUTbrv9t4WjrzoCGjVrROukmuOEcr9Z8PF4XuNhosnDp5qm+o9h+fzlbC54UEHm56Asdfg4eu/gyMqPzFdU7li6YmILYs3fwHtPfkgHPmJpUpf4C/eDBw+Gdu3apWLUUfsUmDZtGh0IqKjIf/eW3/72t/DYY48VvcH7778f8DCEPBCYj2S33XajQwo777xzPtgG8U2fPp0OK0yZMiVTfvz+gs3nl156aSa8BP3ud7+Dxx9/XJpy5vXr1wc8QLHLLrvk+NRQ+xSoloMKuG38AODPLjPiwn4m0AIN6Cact5gJf0+2WAQgxCJwlBwBw1EEtrwUaB8YxzxoxYvtbiXykJfMMp/FcZyrhWv2m3BsjpzjQy63F0oR6pZ+WWfa3IWbAetwySODq8+WYx8NzpeJc4yLxBAdYRFp3QHgY0UQ5474mDvQufx2WG3uoDDYHFB46cWBMO+nqt9B4bTTTqMDCgcccIBNoI+qgCqgCqgCqoAqoAqoAqqAKqAKqAKqgCqgCqgCqoAqoAqoAqqAKqAKqAK1RgE9qFBrnqqNttBadVDhvO77wIEHbF3wycCDCyNGzoAx42bB6tVrC+K32XozuPrKn4f/53PBCAWoAqqAKrDpKVBrDiqYp4YbekrtoAI3MMtXDzYoVeWKc+bjQ+z0scUfVCgmR9a9IOdac/Bw6qhp8FnfL2Dht4uyhhKubr260P5vx8J27bZJjJM1j/3nOJg6enoiThqP+etRsPMRO0pTZC450ZFPa/TH8WjDKy1u1J1jzYGCmRaU5/HwSw+BNh12z4OIulYtWw14R4lFRWrctLwJ7HfGvrBHh92gXoN6qXVjtvhe0/YYrSy6WvbTMpg0bAr9t2T20qjTrPLdUSGeXwan1ZIUk4aVfPnmcc5CfHE8c+eLS4pJw69bsw7G3f8OTH5jKlMXHHfddVcYOnQoYBO5XhufAhdccAE888wzeTdWt25dGDVqFBx11FF5cdL5j3/8A6699lppyjvfe++96ZDCdtttlxe3IZ34vQfvrPDll19mLuP2228vSoexY8fCMcccA2vX5v/fWc8//3x4+umnM9ehwNJWIMtBhSuv7gHlWzanjfD3Wr8r86ZPXx/xzd/+oxEfvN2B7eeDs6ONABYpPzs4B44cQ3CH50Dmt6NLQgPHGaQj5jGC8j62hjifg2t0WEdvd5fg4zyhJguy67D36L4ckSvDc+TkRADXGGKiXJ6EJj47Tsx/XIGnTrARxgZiiA10g6+N7Gy0o/c58lUrV8Hg10dC397mgMK8BT6iMhPk7ty5Mx1Q2H///StDoTGqgCqgCqgCqoAqoAqoAqqAKqAKqAKqgCqgCqgCqoAqoAqoAqqAKqAKqAIloIAeVCiBJ2ETL2GjPKjAz+kPPy6F+//9ISwzDXqFrssvOQh23qmsEEz9qoAqoApssgpkPqhw9r65GrnGG+8wTepVurAZhziqRlTMHRU6P3SqKxlzxjcU300WDMfk20NSnkLcaX5rz3pQodN9p0CLnbFBLh8f7yE+xuuOcvw0ZR7Meucb05A+GZbNC7+YH2fJtz7sEtOsfwI260e5Q4y14y/yv/Sb/rDW3LUh39V0q6Zw+mOdoU49WXsadz4m9GWJy8XM+XouDPzLkELk0HzHMsA7XtiXoayXQ3O5509fAK9fNRjWrMp+xylmwwML+3b7mdF7j5Q7OeTms7FoT7ts3evM3bG+/eA7mDhkEnzz/nd57yiBBxVOf7JLAmFafoam+fPZOVaO2bSWEXaelCfJFo9MwyTZ0Ra98Lkefdc4mDX+m6gjz2q//faDIUOGwLbbbpsHpa7arADeIQAPCaxenf9/P2rTpg189NFH0LRp04Lbvf766+G2224riGMANrziYZiWLVuyqWTHOXPmQIcOHWDChAmZa/yf//kfuPXWWwvily1bBvjr5HinhHxXgwYN6LCEHh7Kp1Lt8lXrQQWz9dAAzy3x1sh2YfVfYekTzQD4ky00vCOftwZu2T6PcQwR0nNcfBQQzy3jGY+4tDlzoJ8wLr/ESwxx0UPuHq05dwOe2wc7uTAn2ugSM96EMRHCuTyaoc7v4TwxfGIa3TtnxFgHYjpbBq5MJudbhXdQoAMKr8P8eQsJUtkH5OzSpQsdUNA7K1VWRY1TBVQBVUAVUAVUAVVAFVAFVAFVQBVQBVQBVUAVUAVUAVVAFVAFVAFVoHQU0IMKpfNcbKqVbNQHFfBJnTFzETz0yEewanX+xrxfHrMTdDxZfzl2U/1D0H2rAqpAYQUqe1CBG2gK3d2gcAUWEfjMOumnxbMSGVzxBxVkM3CkXUhkTcasc7Vy/TYgYOVWZNMSNiGFi/HSFry2QZ7XEsNxeEeFmTD6f99kUOqIBxWaiwN8hepOq3nZT0th4TeLzK/5L4Z50+bDN6YpfdncZal5szj26bI3HHzhgQYa9iV1Yq2R65MXPoMJvT4pSHvgee3o7gEBmMwd/DhjTLLWsqbkOLSGWKx78F+Hwewv50ThCav2Nx8LrQ/kZvLAkVyTJZg0fAq8dd87CWzZTI3LGsOOh21v7mKxLWzTdmtotEUjE2j+sp0MmV4jBjt/5gKY/cVc899s+P6THwEPk2S57EGFzgaabb+Wk58jXIU4+RrJVLcli3AEraPcHkoTzh9yFxcX5ea6C9WMd9EYedto+PGz2dFy8qyOOOIIGDBgALRo0SIPSl0bgwKXXXYZ3H///QW38oc//AEeeuihVBy+Hq+88kq49957UzFxx6GHHgoDBw6sVa+z+fPnw8knnwzvvJP9/fOKK66Ae+65xzcRx3XA9R//+Ef497//neSK2C699FK47777IjZd1G4Fsh5UaGHuqICfHpH3fPo4wQZ11MA82H9WEGMkM7kY41zscQAaBJ5zMK8dZW4bGPdbdizD+JnbBTMnY2xZkoc9oVYZI+ceabjJHsvFfpuDHm05iHdOySfn1u1qYDwHGScyuC3RivDG75lpji4bJO2IJSvyWretn0jsg7cjkjFuQj4HcC7LSIs6gHdQGGQOKPR7aVCVDyjg3XT4gELbtm1FhTpVBVQBVUAVUAVUAVVAFVAFVAFVQBVQBVQBVUAVUAVUAVVAFVAFVAFVQBWozQroQYXa/OxtHLVv9AcV8Gl69fXJMHL0zLzP2DZbbwbX/PmQvBh1qgKqQH4FRo2ZCebHseG4X+yYH6jeWqlAyR1U4O7oKqhZtYMKmDi0DNkyuCmZiwp+bjCmKO5I8o3upnVZhHo30TCHAETsnAvHJEzUlvWgwvYHt4aGmzeQ5GaOtUT5ELC2Yh1UrKygX+unceUaqDC/5r7sp2VQsaICIdVy1albBw769QGwT+e9HZ+shXVCLa19bcVa6PvbVwo2wtdrUJd+qb9xGTbeJ+0xcIeNyNxoZUyanSPT/Vj3zHdmwag7xjI4ddzugG3h+L8d6/xZcwO89/gH8MWrX6XyZnVgg1/5ri1g631aQdOWTaGxObTQyBxkaGI0rN+kPqw2jfIrF6+ClYtWwoqFK2CFGedNnQ9zvpoLq5auypomgss9qJCuZQiUGNYpvEYQF5oVBdZMeRX9e6QI88BeXPMV+K0ljmF/mp150v382kZkUt340ke9h988yug9jwkLjtiE3adPn0y/nl+QTAElr8C8efNgzz33hLlz5+atFV9j+Lro1q1bDm7t2rVw8cUXw2OPPZbjSzMcc8wx8Oqrr8IWW2yRBilZ++LFi6FTp04watSozDX+7ne/g4cffhiw+Td+9e3bF04//fS4OWe91VZbwddffw3l5eU5PjXUXgWKPaiAHe70CcIPZuRPlODzFoeVMVYrsjgYDcxr3PyZYj/zRFM9slkwD4jGtP5ymXxRzIUAOZdrzuNJCEuICLeM4Tlxcn4uD5102dqsm+t0K1F0vC6/J4MhtA1hRjuyw/k8hGMQ5XJYqEXwnNPn5rZhUkeam0Af6yqxBvNZv2IVDDEHFF42BxQWzF9E3so+4HtU165d6Q4KeGclvVQBVUAVUAVUAVVAFVAFVAFVQBVQBVQBVUAVUAVUAVVAFVAFVAFVQBVQBTYuBfSgwsb1fNbG3WwSBxUWLlwJt/zjbVizZm3qc1S/fl3439uPSfWrQxVQBfIrMGLUDBgwcAocuP/WcN45++QHq7dWKlDZgwpFbxa7eGTXftEEeQKo24f9dWD8o+/DhJ6fsiF1LNu+GZz2YMdUf5LDNiOFhLLBOD8+/EJ9Eq6qtulvzoAx/zuuqjTrPb5Rs0bwi78cSb/kH0+epvW0MTNg7D8L73W3Y3eBI644LE5b4+ukuvF10v/iAbD4hyUF83e672Rz14vmBXFxwJQRU+Hdh9+nwyVxXymv8aBCtyfwjgrFX0laF2LhRsJCf7uFeKriL7bupXOWwrAbR8Ci7xZnTnvOOefAf/7zH2jQIH4wKTOFAmuhAk8++SRcdNFFBSsvKysD/D9atGnTxmMrKirg17/+NTz//PPeVmhy0kknATbnN2nSpBC0ZP3Lly+nQxuDBg3KXOO5555Lf1/169f3MRMnToSf//znsHDhQm9LmzzxxBPwm9/8Js2t9lqqQGUOKmCDOjev47b9N0zzQcGfV1IOtAVM8DCWfALDduK2Hz7Uc88s5HeEEWzIIooyU8ch+eRc+rk6G4L7YUsYGY8jzRnDNQUo+a2ZudxKEDOfDWO/WTmMgFrdEWhgpIeFy53bmiyZ4CA0WWXN0dw2iChxb7gUeXAd8HVgBd5B4bUR5g4Kg2HhgqofUMADUzfccAPsu+++thB9VAVUAVVAFVAFVAFVQBVQBVQBVUAVUAVUAVVAFVAFVAFVQBVQBVQBVUAV2OgU0IMKG91TWus2tEkcVMBn5f5/fwhTpy3I+wTd/rejTfNMaCLJC1anKqAKeAWGj5gOrw+eSms9qOBl2egm6+WgguwKqu7DCtT5w0+LXYx/9ANzUOETNqaOlTmogGShsSj6C+5JiYrBJsVntdXGgwr4y/3HXns0bNZqs9RtJuk36OqhMOfr/L8YjoSn/PNE2HL3DfNr1Ul1f/X6RDpEk7pZ59i9/W5w+KWVuxvU/BkLYPQ/xhbV0F6onpr2V+WgAtaWpHW+mhm/IQ8qFFP3gpkLzZ0URtKdTPLtS/ouvfRSuPfeexN/8V3idL7xKYCv6/bt28OIESMKbm7vvfeGt99+G/DQwsqVK6F79+7Qr1+/gnEMwF/q7tWrFzRs2JBNtXZctWoV7f/ll1/OvIcuXbrQ/hs1akSHEw477DD48ssvC8Yfd9xxMHz48Mh7V8EgBdQKBbIeVCjf0h1GjDTPUxd7aJLH5nb6Whu+6NplaJJnMFkcjOccxZ95fkQlkZtGM8VZLJbFdqjgd/V6v1tbLkvCeRhDaSzA7Sd4PNb4ec5jqMni2c71+tqMm302l63DRVHtHEN+/4CuWM0uNDAYhF+Yif2HCW0k+QSG7Ta5w3AWDGMCoiKelctXwsDXRkL/vuaAwsLshxFdisiAd1A444wz6IDCPvvoDwxExNGFKqAKqAKqgCqgCqgCqoAqoAqoAqqAKqAKqAKqgCqgCqgCqoAqoAqoAhuhAnpQYSN8UmvZljaZgwq9en8J49//Pu/Tc+1Vh0KrVk3zYtSpCqgCUQWGDJ8Gg4dO80Y9qOCl2Ogm6+WgAqqGzTnVfUiBnw1qFKIkZKmROyqsc8l8Lk7uRvbjMg2DPsZJDNsKxaI/5apVBxXM3nc/blc45OL/gnoN6+XuiPWQGjnU3Ek/wcCrhuTGxCwt99wKTrqzg7VKHuZGj7TH4iu1ZO4U3orlFfDSb/vDqiWr8tKjJt0eOw0aN28ccMyNlhR+Bq9evhreuu9dmPHWTDaV9FipgwpZ9CgGIzXNEldZRZlb5pNc7He2ORPnwohbRsHKxflfM5Li5ptvhptuukmadL6JKTB9+nRo27YtLF5cuOm1Q4cO0KdPHzjrrLNg8ODBmZX61a9+BU899RTIOwpkDi5RIN5R4sILL4Tnnnsuc4UnnngivPjii9QcPHTo0IJxzZo1g48//hh23nnnglgF1D4FshxU+PM1F0OL8jKzOfNB4D4LaHAP+HWZfXZu1w5qXKHx3VI4jxnYE+IQbv05I9FyBKckEvT4Kx7nHWbifWjkumRya0avx9JCrrluWya5mddLxNy4Q8KJuiVX6pzjiN4+uLwyF3ttKe7R5UOf3xrWw3YLw1I9AOe8du6wf2egAwqv4wGFIbCoGg4onHnmmXRA4Wc/+xlWotf/s3ceAFZU1/8/sktZYBdYehVUsFCVIlYsiYqx/UyMLRpjwxYSRQMaYxI1xmjUxJhYUNQYJcZOVf/SQZDelCJSpHcW2KXu8r/nzpyZO/Nm3sx7+3bZZb8TeHPntHvmM7M7z3DOXBAAARAAARAAARAAARAAARAAARAAARAAARAAARAAARAAARAAgSpAAI0KVeAiV/BTrDKNCh8NW0oTJ69Jejnu/1VPatkyN6kNlCAAAi6B0Z8vp8+/WOkK1AiNCh4cR9RBxhoVuPDGV2R7uEBNH8wrKiyInF6vqPDCjyLt2MA8Nbc8ypS6NlKUZAV2jw7ZUVyJZSFR/HJLG+9z5eTvaeJfp8QzPlxW6gRb92pFXa/pRPntGiTNwmViUjlEU/4+jb4btyKpLyvPvPc0atenrbYzI7CAY/tl2jADH4l5i8QKPvs/82jh+99EzsSMul7T2bGTKKnkvWj4Epr1xlwqKS5x4lS0QY3a1emky0+gLld3Sjk1l4lJRaRhP488jWUvP4+uxE2Bo5hRXU3pR5Jh1O+R9XPW0/i/TKaDew/GmpTfpPz888/T3XffHcseRkc2gTfffJNuuummWCfZrFkz2rBhQyxbNrr99tvpxRdfPCJX7CgpKaE777yTXnnlldg8UuH3xhtv0M9//vPYsWFYuQik1KjgVL0bzxsugOdTZh3/MR5E8sxwCuu1mWvglbvcRM57GVtTWL5uBJ5PHZkCYw7TV6KLjF1kbCbtyd84cG15usQ5LZGVCNuKq+VnyyUJc+7QsRtD3KyYBhMrrFbrnGxDJ1cd2xIeVY1zNhx8tqzRefvkfLhn714aPXwcffKhalDYudu2SG+XlZVF0qDAK+RgAwEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQqFoE0KhQta53RTzbKtOo8MZbC2jegs1Jr8Fjvz+L6tapntQGShAAAYvAyNHf0RfjViXgQKNCApIjRpCRRgWp1ZEK3MNMp0waFULOTeqUzMUiRMYYTLmJJczGlJv2UeMK3aig7o82p7bSxehRDQp8nmHM9hXspQ9u+4SKDyQvvOeVCHhFgmrZ1TQ2k6kZ25RH8Y2jN2Ob9jIP6/ds20Mf9htGJQcjzqEen8NlzooTZmyJZ84RNt68ZAtNf2UWbf1uW5jJYZHXblibTrrseGp/wbFUPSf172gmD/METDamjchNWSp+pm1pxlHzi55/nqf8fWrkfSK5VK9enbgw/dprrxUR9iBAN954I7311lsZJXHvvffSM888o4twMxq4AgU7pH4QBwwYQM8991xGs7rhhhvo3//+d0ZjIljFIpBaowLnbpbE86F9zA8t/iPfrw07p3De1jkRtIsl9PiJHcd2Fd6xlQp/euTmselryvXYEnDKOm/7w8jfH5dzsWx1/naO7M6bOZeMrdRtP7axZtP2PJRjsffGcf0sBx1A+zj2dg7Wzj2QuNYc9nScjDaRvXsomVgmdhzltnfvPho1fCx98tHntCsDDQq8Cs7vfvc7OuGEE5xTwgAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQKBqEUCjQtW63hXxbKtMo8ITT0+jzZuLQq9BzZpZ9ORjfUL1mVbsVW+93blrP+3evV//a3VunRqUm1uDatXKzvRUSePx/Fu27tFvjW7YIIfy8moktYcymECxegv1joJ9VLBzH1VT1QYN83P09Qy2zqy0uPgQFRYeoN2F+6mo6ADlqELORo1yqGaNrMxOZEQbPnIZjZ3wvSFxh2hUcFmkOuLC0y1bivR9lJdXk/Ib1KJsu4A61VhlYY9GhZAVFYzGBGOYcAm4EEmKi01lmNxvw7+ozfjspzdTyAKRW9qEz4rYqJCtnn2te7WkTleeRA3a1k/I2SOwz9d/2qbNgve/prlvzzdFgeMuP1WrEVzrrkbARpqrCm7G10j5wxRqY/6IsRl+xjDQ0ZxmyvPTaHmMVSFOu7sXtf/hsTo/M346ea9Tb+dfoFZy2Pj1psD8ykWoEm/UviEdf1F7anf20VQty2okibq3ndxsCCYLR2cMwn72wuTietjvEcWHf5cs/fRb3VzCxdJxtjp16tD7779PF110URxz2FQhAoWFhdS7d29auHBhRs764YcfpsceeywjsSpDEC4CfvzxxzOSaqdOnWjatGnEP6/YjlwCcRoV7hvYj/Lz1Xci9TvfKYIXJCJTe/7iop9L9kOSRbzpwno5sERWHFumY6qxxLZiWH5OUb74aR+ZxxbyHDynEYPHvIm/7C2pNnU+PDnbfqav5WMp2NY8H39c0885DzsZcx4nPzUwY7hj3znK+fhiyRz2yeidsNC5WMm7c+g4RmwjrsTaU7RXNygM//gL2rWr9CsocEMi/y4+/vjj7WywAwEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQqKoE0KhQVa98xTnvKtGo8N3yHfTCS7OTUm/RvC49cG+vpDalUXIzwNffbKGF6u/KVQV0MOQNydww0f7YBtSpY2PqeFKjjK/wsHjpNpo+Yz1tVsXQnBM3TJhbDVXc3qhhDjVUf5s0rk1cdM5synrjGrv1G3bThg2FuuB+tyq85+L7WopHidLVrVtdsahBDerXpLZt61GN6pktwl++cgfNT7LiRmd1PY49xls8ywxnzdlIc+Zu1Dz9dYLMslnTOnTaqS2oxynNMlZwvm9/MX377XZatGSr/rt9+97Ay8NNJ40b1dZ/2x/XgE7u2lQVSwSapiT8ePi3NGHS6lAfvm9OPKFhqN6vuPyS9hnJ63DfQ3xezGX7juDr0UC9ub3PWa39p6+P16v7fsToZbR8RYHnZ7JataPohOPzqVeP5tSlU5OMcApMIKYwI40KMecqL7PYKyq0zKPLXghpVNDJSqFwBn7Ikpy8GV1mtMzlyLQIDsSNCpOemRKsLEdpzdya1FTd123PaEMte7SkbPX7Pv4Wfr4lqnHsI7USQZF6xiXbuPj9ylcuoxzVWBa0mSRlNstOjkyLoAhBMvaN77ddPZtG3Ds6KJBHVr9NPbr07xdrmRldMrWM5ci08ITxHGxavJlWTFhFa2asiWTpcUzzIEs915t3aUqtVMNKq54tKUc1T1pbaszc6VM7X9cv/sgkKbO5OfPItIgbN975zv/fQpo3dEHcoNSgQQMaMWIEnX766bF9YFi1CCxbtox69epF27dvL9WJP/nkkzRw4MBSxaiMzn/5y19o0KBBpUqdf075/yA67rjjShUHzhWfQOYbFdznjYzMwn6TiBTlS2G93isD+e9E1ouN309sRO6PIY898Ze92PNeYlg6K1uRWXo5A33EH5aPzksfhuanbe0PO7I9nx3T2XnP0c2T5dYcci5WODua3hk2YqTkbgw1lhBOMFvvKCwDPtyzR62gMGwMDf/kC9q9q9D2TG+XlZVF1113nW5Q6NChQ3pB4AUCIAACIAACIAACIAACIAACIAACIAACIAACIAACIAACIAACIHDEEUCjwhF3SSvdCVWJRoVX35ivmwSSXZ3OnRrTzTd636qczD6ubsPGQhqm3j6/aPHWuC6OXVbWUXT2ma3pwh+0I25gKM32/eqdNHzUd7Tsu9SLj9odXY9OP60ldevSJGPF9nwuvArBvPmbdbH9EtVAsYtXl4ix8Rvmj2lXn07okE/dT26WkVUgJn+5hj74eGno7Fdc2t4pMudVEz76ZCnNS9LY4A9Up051OufsNnT+OW08RQx+u2TH3Nwyacoa+n9jV6qCBm+DSTI/0bVulUvcFOBvuBB9nP1Hw5bSxMlr4pjGtnn2L+emzaQi3UN8ws8+P4NWr9kVeO5Bq7bsP1BMoz9boZiuphLuyEmytWmdRz/5v+OJr+Ph2tCokKRRwexUMoqSMn2tpL7Jc7ekOPfq6Wto2r9mZDY1lRgXaB2lXnzP+2rq93Q1VXieVb0a8WoJNWrXoJpq1SBuCshrkUuNj2+k904SqTCLON8d3xfQ8F+NckKHDdqe2YbOGnBGmNopMmOD0vB2JojI27HzDb74wzhaP2+DT5p4eOXgy6mOak7LxD3iia5+N239bhvxfbNp0RZivvt27fOYpHrA90jdZnWJGyz4b8Pj8qlFF9XQp+6Vw8k65fMwHMorb149YdaQObRoxBJj9uTDFi1a0KeffkqdO2f+e27ymaGtbATGjBlDffv2pQMHDqScOv9cP//883TPPfek7HukOLzwwgvUv39/teKJ5zdCrNOrXr06jR49ms4///xY9jCq3ATiNio0UCsq8HOdf770Jg95JbVESmD9YSMHih6pY2vviK0Qtp3Wal/LT9x5Lmc+21Xi8aHYWWPb10nCchB/2VtS0WlPI453fj4hcw7nWOflRvLH5mMrT3sevVMS/ceawzLQEY1zFBtfXo6LPbDUnF1CfnoOI2nx8OSop9EfOrOioj00evg4GjGs9A0K2dnZukHht7/9LaFBQePFBwiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAgEEAjQoGDAwPC4EjvlFh/MTv6ZMRyyLh/vTHJ+g330caxjQ4cKBEzfstTf1qXWQBclTIXFXcedWVxxO/1T/VjQtl/vveYpo+c32qrgn2tWtX129273tBO+LVAtLdiosP6Xy44D5sNYC4saurItgzTmtF5597dKlWn4jbqPDltLW64cO/EkXcfDue2Ih+du1JVEsVY6aycYMJX8et25K/ITxOTL6PrrisPeU3qBXHXNtwvdUHHy+hKVPXxvaJa5hOo0JFvIf4fFNpVOAmhcFD5qfUPMTFLpdcfCyd16dNXLwZtUOjQsxGBaZuFCtl9CL4gwUVQ6Yyt98/FV9/Lqkc++dl37hz+33j+qWSn23LhWaeclP/3GwXd36/b1w/O5e0d/55U8mZbf3+Ku89auWYAtWwULCGmxb204GiA3RgD/89qPdHqdVgqudkq7/Vqbr67iD7GnVrUL1WeVS/dT3Kivoe4Z83lbz9vmXIujzvEV4tZOo/vqLlE1YyjVgbv5n9888/p3bt2sWyhxEIvPbaa3TrrbemBILf4v3KK6/QzTffnJLfkWg8ZMgQuv3221VDdnFKp/fqq6/SLbfckpIPjCsvgViNCr/pRw0aWo0K+ruGrnHXH/rE+fmjvoTIH30k30m0Tj37LBvLzDLgry2u3C2kd4vvtd54broxrJGoxFdHc4xkFmsePhI70cixxLHkZmw3F48P5+2bx4nFhgl6nZkltwO5/hyLg9kB1c4aGXNoma3X8a0gdlRvLnpu11ZGkp/2tIVFe/bSaLWCwgj1t3B3kRU0zU9uULj++uuJGxTat2+fZhS4gQAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIHOkE0KhwpF/hin9+R2yjAteocVH5h+rN91FvKs/Lq0G/G3R6xlYLKFIFe6++Pp9WrCrI2B3A/8h99U9OoFN7Nk8pZlm8Af+3A0+jRg1zUspDjL9bvoPeefcb2rZ9r4gysufGCW6g4FUL0tniNCrsVCspjJ3wfTrhPT5NmtSme+44hXJVwWacbeHXW+jNtxcSr6iQqY2v3739e1JtVUgatfHP0nsfLtZNN1G26ehTbVSoqPcQn3vcRgVuZHr19Xm0dFnqK5zwPD1OaUbXXX2St0CGFWW8ZbpRQd447CniUefA95xbSJT8pKSIXAqCklu7Wpl7xquzae47C1xFyCivZR5d9o+LpZzJsjKT9BdG23HC8guUh8QLtA3J0xSLH8scPuYcrEgh71Tjib0zN88XYwv0M/OOyJmnMOeMjMcORky2N/1ZHWeLnMeYw4wX6KcMAuUhHAJtzUmSjBN8zTnYr7R5J4mXMHeSPE1VoJ85T0TOHMu8xpHx2MGIGWjPNhFboF/MvA/uK6ZJf51Ca2eti5jFVXfr1k2vpNC0aVNXiBEIxCDw6KOP0u9///sYlpZJ165diVdjaNiwYWyfI9Vw69atelWEefPmxT7FP/7xj/TII4/Etodh5SeQmUYF90lmPkrkSzR/v3Ys7IHeGXLzO7iMHT87qBvDGllit6Bf/PxXxZTLWOZnWzu87RYcW2Jqf2UicTxyjsV/OaD1R32HYokl54msI7bRYq2xYtkCY2fO4YwdP47pHjjxZA5bIBaOv5qxsKiIRg0fS6OGjaXCwtI3KPzsZz/TDQrckIgNBEAABEAABEAABEAABEAABEAABEAABEAABEAABEAABEAABEAABJIRQKNCMjrQlQeBI65RgevIvl+9k0aM/i72m8ov+9FxdG6G3lC+Q71l+KVX59HGTYUZv378795XXt6Bzjy9VazYk6as0Y0asYxTMEq3UWHCpNU0bOSyyMaRFFJJMD2lW1O65qoTiVdaSGWLalRIJVYc244nNaJbb+oSafrNoq302pvzy4TZCR3y6babu1I19ebrsI2Lud99fzF9NaP0K3KEzZFKo0JFvof4/OI0KvDvKG5S+Gbx1jAkkfK6qsnljw+fkfTaRQZJw6A8GhWMWmCjmCg82cDC33BzR+M0KgxWjQpD02xU4Gj8i1knIZk4U+iBSM2fMpFpd6+5Hc+0cAvWA+39/saxGcWcn0usdI2VCdvw46H4mn4iY70pdy6UES/Ulp0jtlBfu/jLLBg3Q4X5hcnLKm8PG04Q94jFgFkY94g+5A+1JTCzxKGfqVxTM0iYX5i8otwj+wr30/gnJtGmRZvN00k6Pvvss2nYsGFUr169pHZQgkAYgf79+9M//vGPMHWCvFWrVvTmm2/Seeedl6CrKoKxY8fSz3/+c1qzZk3sU/7lL39Jzz//fGx7GB4ZBNJqVFCnbn0Vsp6aZhG8fEXSdNSBtpA9C+0HrdaosX2o4smIY1tj3uuRHDv+orcElg3HUiNLxQpnk3gskLHlI/EdU7bQB9aUSm/EE19rGqWwdY48IT6HsuPpoTufG5bn4CNXYsVXEnNytpBjZWpH4qh6s1RaYUWybXVUNeY9r5owaoRqUFBNCqVtUKhevTrdcMMN9NBDD9Gxxx5rZ4EdCIAACIAACIAACIAACIAACIAACIAACIAACIAACIAACIAACIAACCQngEaF5HygLXsClapRoWvnJtT95Ka6gLKk+BAdLC7Rb5kvLDxAu3bvp02bi2jtul20c+f+2ORq165Ojzx4OtWsmRXbJ8yQ33j/t3/OorVrd4WZlFrOReX97+pOR7fJSxqLV5H4w+NTNJekhmkoU21U4FzeVqsozJ6zMY3ZUndp2aKuLsCvl1cztnN5NypwYtf+9ETq1SP5Chmff7GSRn++PPZ5pGp46cXH0nnnHB3oxoXcQ/+3mGbMKrsmBZ44TqNCZbiH9Lk8P4NWrwn++effMU8+1ofGT/yePhmxLJB5XGGceydurFTsyqJRwSn+MRKRWmapCzJUGR3yPR53RYV6akWFS/0rKqSZTWhRdEi8VO3NMOKrC6ZMRRpjicWuUfFSsQ1KRfyj5vH7sp/fR2KxrV8X5C+yKFuxM/dB85v6uONUcuaYqdr78zgceZs5cz6p8hb/dPz8PhIrTh6p2Po58zH7++cPshPZHtUAO+bR8bR95Q4RRe4vvfRSevfddyknJ73VryIngEGVIMDPyFtvvZWGDBkS+3yrVatGd9xxBz355JOUm5sb26+yG+7atYsGDRpEL730kmoujr8C2s0330yvvvqqWwhd2UEg/9gE0m5UkBm4CN74omwMXTnbOPb87LGPzJ1hI/F47/rxPG4QGTsWSqfHjo3YKrkYK5GM2UzG7iTs487j6E1bNuHNmE/sZG8ZaBOexDLXOyO2GOn5LBtHpAYcKyGeEyvYXvyd0+UYSlhYuIdGDhtDo1WTQlHRHjFLa88NCjfeeKNuUDjmmGPSigEnEAABEAABEAABEAABEAABEAABEAABEAABEAABEAABEAABEACBqksAjQpV99pXlDOvVI0KmYZWo3oW9bu1Kx3Trn5GQn80bClNnBzvDZrZ2dWoaZPa1KRJHV21xiswcKMFNztEbY0b16b7f92TOP+wbcnSbWplh7lhakeel1eDjmlbn+rUqa7+Af2gyqGQ1q3f7X/psWPPg1QbFfiN/NOmr/PEKOuDVi1z6Zd3nZKUkZlDOo0KfA27dGpMzZvXpbzcGrRz135ar9itXbc71ooaOTnZ9Af1Vvxk17GsGxUaNczR19NkIeNF6o3/rwyZJ4dlto/TqFAZ7iEGFLWiAjcZPfePmbF+zsOAtz26nm5WcophwgzLQJ7pRoWoFMujYWH64Fk0953oFRW4UeEy1aigi5QlMV2GJGfhli97CpxEbNQ2mTFMW1duGKvw5rWWlSBkVt6bMUy5OXb9vLGlxD0hRlDeznl75wyMraaRmdzzMjPyxvBq3KPA2FptJejJW3JmvUyuhk4Mu3BMu5tywziSNdsasSWWufeer2nsJhiYt2FqxjBtXblhrCaPzNs0MJM1xg6nhBO08jbz0G5yOkYqbgzv9bVuHXYwjNVQjtzzMhJi60znLTnzNDK5Gjp5q/kMsSs3pGZKjh/HM7aovL3na87IQawkOcbujbvpiz+Op10bdhvRkw+5kPG1116j7Ozs5IbQgkAMAlx0zysE/Oc//4lh7Zq0bNmSnnnmGbr66qtd4RE64qagAQMGqEb1tSmd4c9+9jO9AgU3d2CregQy06jA3NQzxPpjQdRj+7lijD3PJVfND1rnCSc2rJaxju08+LiIX6ZxBspEje1DS2vbiLERj83M2GLvyEy9b6xt9VTWfOIje4nFe5FZKZh5ixXLEpNmWYLcnjNM7kS0w+0uVCsoqNUTPh0xLiMNCvw7mFdQaNeunUyFPQiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAikRACNCinhgnEZEKiyjQpcZH7rTV3o+A75GcEat6i7YX4O/fiKDnTC8fkJ/wjOb42ft2ATffjJt7RbrRCRbOO34PPb8MO2qMJu/nf5yy9pT2ee3pKysrwFMrtUwf3Xi7bo5oJV3+9MmCKVRoUvxq2ikaO/S4gRJqhbtwZ1aN+AGilOCgfl1MpSbyM8QBs2FtKy73bQ/gPFYa4Jcm4iuOmGzopzgipBkEqjAvO64Py2dMZpLXWDR0IwJeC35g8f9Z16q6pZFZloef01J1GPU5olKmxJVKNCO1W03qN7M2rWrA7xvcW5bd26h9arosYxiv0WNY7a+t/dnTiOf9u6bQ8tWLjZL6YDB0po1Gfhqzy0VE0iPdTKJ3G3Pme1SXqNKss9xOebrFGBV0NpopqM+F42N5b17tWCWrfK1b8TuGlp+sz1FPSzxwUyA/r3IGZ8OLbD1ajA5xrn5zgdJik1KjzPjQrmz7T5y8WVqxInlbDKxhV5UvPGcIupvEXPbmw9Uh9evSekvne8EuNI5eGd041tJqkLsIJyZnNfDDnHxJzc2Pqa+fyMrBQiZeuamyo9Do9tJqmi2PklBFByfwwpMvPLzUQknpeZGz1p3oHnKyfp5u3EcEXuBGrknzs4b4lrZx9wvmZQiWHKnHFC3m7s0t4j/nsnY6yZk9E8Y52L5G2CrZz3yI5VBTTmsQm0Z3v0c1yu469//Wt69tlnk/8+EGPsQSAmgYMHD9J1111H7733XkwP1+yss87SDQs9e/Z0hUfIaMaMGbpBYdKkSSmf0VVXXUXvvPMOGopSJnfkOMRtVMhvaLxQQX1B0d9R7C9Pzlg9+vTTz34EOt8xbFxyLHuhaPloqRbJ9wSWy1h/VbMmYqltxzvbz55TS2w7J2KgTrta3o5eeRhjjsUby5w8tMCe1bY1da6/ZWgdS46yZ387kNqZ/loqQXhe21LM5djxkRzYzh7v3lWoGhTG0KejxtOeor3aNd2PGjVq6CYxblBo27ZtumHgBwIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAKaABoVcCMcbgJVslEhK+souulnnalTx0YZ4//M32fQmrW7QuPxP2qff04buuAH7ah6dW9jgN+psOgAffDxUpozd6Nf5RzXqmW9jb9mjeBVFf71yhz6dtl2x94/OOfsNqpR4Ti/OOGYi6XHTVhF81XButQDxm1UWPLtNnpZreogfgnBDQE3jFyo2PDb4hWqwK24uIQWLd5Gn49ZQavXhLM2nfteeIxuKjBlQeO4jQoN6tdSzQ+dqE3rvKAwHtmy77bTy6/NS/r2/JO7NqUbr+/o8TMPwhoVeqrmBG5WadZUrcgRsvHqHKM/X0Fjx68KsbDEZ53eiq5UzTNxt337imnQ7yaEmp/SrSndcF34OYU6Bigq0z3E6SdrVPCfHv8e6nvBMeo6cqNG4k2/VP38vv/hEtq8pchxPVNdK250OlxbeTcq8HnK748ARBnBELdRIY9XVHi+b+KcXA+tL595Dc0i6USXpBInXlKrDCpTzDsT+ZU6RpKcSx07Cdp0Yzt+SfJOMm2CyomXoMmswJknxbwdv1KkU+oYSXIudewk55VubMfPynvz4i007s8TaX9E06qZyeOPP06//e1vTRHGIJAxAtys0K9fPxoyZEjKMfk7zo9//GN69NFH6cQTT0zZv6I5LFq0iB555BH64IMPApqlorO9+eab6eWXX0aTQjSqI9oiTqPCgIF3UIN8o5lc/Szp78P2l2LnScdypmUL/P9dobVKlyhnHynBd/UcxrH1+FkTWNPbufC89ubM4yQiGjeejmCFsefwxnQ9dGrq0J5HmUl8r40djC2doeSmPbRCVM55aXuRsok7dtNXMltsR9LHZh7sxw0KI4eNoc+4QWFP6RsUbrrpJr2CwtFHH22eKsYgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgkDYBNCqkjQ6OGSJQ5RoVunZuQpeolQgaNczJEEKipaog/8XBc5PGO//co+mSvuErIPid+S3Bf3thFn2/OnFFA7H9yf8dr9/qL8fm/m8vzAx8I7vY3KgKyU9WBeVxN25YGDZiGa1YtYMeefB0qq8K9pNtvJLA089NT3h7vN8nJyebbri2I514QkO/KunxrDkb6H8fLKH9+5OvsFCjehZxY0VeXo2k8eI0KnCTwr3qbfa5atWHuNtbQ7+m2XPCG07yG9Si3ymeYZu/UaFevZp09Y9PiM2Li7z/8eIsWrGyIGwKHev2m7uG6v2K8mpUqGz3EHOK26jARS3c8MKrfiTbuNlk6P8W0WzVtFS3TnV66DenEf/MHK4tTqNCr9t7UNdrOhnFQu5bzz1FQOok3Lehu8VBZp2QeZ5i64+Rqo1pz+OUGhX+rhoV3FTVCRjRzMSlu8JQhw5D4xkeMo9py2qRG6ae/Ewb09f0y2Te5hxx5pa84/h54pkO6mTM85GYQXvTzRPPZyzxTHuRmaamPiye6ZdJ1jyfOb/MY8rMnHgsW5iNKZd47FPeeZtzp5Iz24qvmTMLRS7xwvYmA088n4PEM+1FZpqa+rB4pp/Ke+3sdTTpr1PooGoKjLNlZWXRP//5T11EHsceNiCQLgF+Dj/55JP08MMPqxXDSlIOw/fqT3/6U91Q07FjZhpaU06iFA5ff/01/elPf6L//e9/VFwc7+fTnK5atWrEDUWDBg3yFkWbRhhXGQKlbVTwPF7Us0Mf20L/d2UprE+UK9ziq4dWAH6EuoX5amTHlS8e+pD9HLl12Zx55AuKrbfsrAPXR/xNuTeg+Om9Ukl88yYxzykoto6oFBLZay9SxuCOxdicz4mgzES+a+dutYLCWPp8tFr9KAMNCr/4xS/owQcfJDQomFcYYxAAARAAARAAARAAARAAARAAARAAARAAARAAARAAARAAARAAgUwQQKNCJigiRmkIVJlGhRpq5YG7bj+Zjm4T/Sb8VIG+pFYNWLJ0W6gbv32//13did+gnsq2bv1u4pUauGA7aGvRvC49cG+vIBW99Y4qkE+yIkPP7s3puqtTf6vpho2FSd/iL8lMmbqW3v9oiRwG7hvm59Dtt3SlJo1rB+qjhOs3FNKrr8+jbduTv7nw9N4t6aorj08aLqpRoWbNLPrV3d2pebO6SeP4ld8t30EvvDTbL/YcP/lYH+L4QZvZqMDNHNzUkWqhOq8+wQX0YVvrVrl0X/+eYeoEeXk1KlS2e4hBxW1UuPRHx9F5fdoksA0TjJvwvW6u6hzR2BDmnyl5aRsVdGmP/WvQquWX323u70azTsjMWxoVzBimnsdi4yk28hv5jlNuVPD5ew/5POScvJqKeyTskXfgNcr0JeUbPJVGlsCkDGHG81OxE24F3CMG8cRhBq/BikmraOoL06lErSAVZ6tRowb95z//oauuuiqOOWxAICMEPv30U7rhhhtoy5YtacXjgv1LL72UHnjgATrjjDPSilGeTlOmTKGnn36ahg8fnlaDBufaqFEj/bN64YUXlmfqmKsCE4jTqHDfwH6Un1/fOQv9/VY9c7zfc1mg/9gfvBOB5Woei68U3pvfux2ddpcYylINneAyUkLT15pJWdlC75yW2tA4UQAAQABJREFUv9fe9PeOtbWe0+unYztya0ZnPm9wJ2crdZ2NdrDM7CDqQMJJHCuq+lQKrZU9i+w5du3aTSM+GUP/79MJtHfvPsclnUHNmjWJV1nhBqY2beL/t2E6c8EHBEAABEAABEAABEAABEAABEAABEAABEAABEAABEAABEAABECg6hJYv349/fvf/04AwP9mf+aZZybIIQCBTBOoMo0K1atXo5+qN9H3OKVZRhly0fZDv58Y2kzAzQmD7u+d9goOHw37liZOXh2a8+O/P4vqqDet+7cvxq6kkZ8u94s9x1y8z0X8md64WPj3j0+hXbv2h4bmwvxf39MjVtNDaBCl2LS5iP6uVo8o2nMw1KxataPUm+h7EzdGhG1RjQoXX3gM/fD8tmHuSeVPPDWNNm8pCrUZdP+p1LRJnUC9NCrwSiA3qFUwUm124aBcEzvw4fF04EBw4WOTJrXpQXWPxt3Ko1GhMt5DzC9OowKvosH3Y1ZWtbjIK4xdnEaFU/tZKyoEJq3uRamB1oVBUh1kGEsNt6/eyLWwY4TqlWWyGFYzgzvxjMGzaO7QBW78kFFeyzy67G/WigqHnLPgydzCJdOV53HLn0yNb6xS4XiOLQOy0/PIDTdHLjCVTufknlZoPCfMITWjYa/lRjzHLmgQlF9E3k7OHM+YJ6W8lZ8UjZlppcLa9HPyUOfjyc8w8shD8vZcO/a14zlhOO8E2GrOw3GP2PlZO+dCeu65pHkbDBy7oIETOv69HYd1ZN4ZukecXOR8S3mPOHn74jnolHzp6GU08/U5+r5w5EkGdevWpQ8//JB++MMfJrGCCgTKhgB/H+Di2s8++6xUE/Tu3Ztuu+02vdIC39MVZdu9e7deOWHw4ME0bdq0UqXFzQlDhgyhFi1alCoOnI8sAnEbFRrk13O+0+nvEup55H6nsB+2Co3zNYP1/EWEN9/YEmmhY+P4sbl9wDsZ62iGkR3Z0ssBB7Y318+N4Y3HhpajEdaYz/WzQrq2OrZvTpaZc9ppODJtzja2wp1TSewD1oXFEDnvd6oVFEYO+0I1KEzMSIPCLbfcohsUWrduLWljDwIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAJHJIEq06ggV6/PWa3pikvby2Gp94uXbKWXX5sXGqdD+3y687ZuofooBa/UwCs2hG233tSFOp7UKEH99aItarWB+Qlyv+CM01pqHtnZmSuajrOKABfdn9KtqT+dtI6jGHHQy9Qb7M9N8gb7qEYFvmf43klne+OthTRvwaZQV74/+D4J2hYs3EwLv9lCV//kBOKGi3S3vzzzFfFqGEFbo4Y59NuBpwWpAmXl0ahQGe8hhhWnUYFXMuEVTSrjVupGBXXSyZoImInoeewWE/GRu4lNlJ49TBurSUHiWD9PqTYqcAFz0OaWQFlF72JjykVm7s14pq1HbpyEnEOYrRk7XRvTz4xnjj35OeVf7rlLYRf7aFsbmxnbjGHGjrIJ05tyM545ljlNW5GxnSdvudFYHnCOZtwovY4dEsP0NWPK2JNfWIyIe4RjmXEktjl3kJ7tgmxMmcTy7814pr3IPaz556oK3yPz311IC97/xo8w9Lhhw4Y0cuRIOvXUU0NtoACBsibAz6NXX31Vr4xQUFBQqulycnLovPPOo0suuYR+9KMf0eEo3F29erX+uRoxYgSNHTuW9uzZU6pzqlevnl6J4dZbb/U8W0oVFM5HDIH4jQr1nSe/fm7q+nr5b0J7zzIho8fWkfmcFQP9PPbYiKP7HYi/UoidHhnfMazIykfJDLEO4vq4sVhh2Zn2kp92s3yNYG7ezmxWjKA52U//cW2tOa1j/cl+9lTuNEpiH7DOndMylGPe7yzYpRoU1AoKn02kffvCX8RgT5F0xyso8O8EXkGhVatWSW2hBAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAIEjhUClalS48AftVEF3A9q/v5iKig6qt+gfoPUbComL8gsK9sW+JlywzoXrmdhGjP6OxoxbFRrqyis60Fmnp/+P0IVFB+jhP0wKjf+Dc4+mH/U9NkFfUnKIuDidVxyI2nilgSsv70AnndgwyjSWPmoViNatcum+/j1jxYpr9Nqb82nh11tCzY87tgHd3e/kUH1ZNip88PFS4vhh2y9u7ExdOjUOU2dEPvj1efTNoq2BsRqoN/w/8uDpgbogYXk0KlTGe4hZRTUqNGtah35zX6+EYpggzhVRVtEaFZiRW3DkEjPqyz16KfK3LK2SpUw1KuhcVBmUFGFLNm5plEi8e6+9Ze2Vcf2VlWtcuTkD+/r9/Ho+9tvInKatjK16cruqXAnFNixGkNwvk9i8D4sXx0Z8TVsZe/N2Lf25sCZIxnH8conNe4kYZePXi58Zyxx77S1rryx8bonttzfjs02Unu39NhLbjCVjL+vU85PY/jklfpSe7cJsRC6xzH0m8g7LOSgn/p00c8gcWvrpMjONpGMubOS32J900klJ7aAEgfIiwEtEDhgwgIYOHZqxKdu3b0+yxCTvjz/++Ix+d+KfvSVLltCUKVNo8uTJev/tt99mLP9rr72WnnnmGWrevHI2pmYMBAKFEojbqJCfX9+KIUX1vLf+uLGVTH9TtL4uOs8/Kba3lO5z0XNsxBJ7awpRqNj23DKhNRfLRWLHto8T7C0Hbez6mP7mWMXSRm5w04dzN8JZtlrm2vNEHEPyMDVWLFvCNvYpiK348r5ANSiMGj6GvvhsUqkbFGrVquU0KLRsmfkVLe3TwA4EQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEKiSBStWocMO16i38Jwe/hZ+L1N/7aDHt3BnvLXcX/bAdXaj+lnZ78RVVYLZse2iYm27oRA3q1wrVx1E894+ZoWad1GoKt6hVFYK2r9Wb+F99I3pVBfHllRkuv+Q4atyotojS2j/+5FTaui38LaRlUZi/fsNueurZ6aH5ZmUdRY///iyqVSs70KYsGxU+/2Iljf58eeC8LEx2X4c6paDgphVelePbkPuUG1UeHlSxVlSojPcQX5KoRgX+ncO/eyrrlmqjgtkwYL0u3VuIZHKwmgi8esv/kFNoJPbeuFyMJBprL35cyuTXsYWrJ5oxeDbNHbrAGyDgKK9lLl36t76WhquZfXNqhVXlHOAdItIxzEAqQFAMn4mOZspY4Pfz68XGL/f76eARHzqGGSggb1MdNrfIzemC/FgfJjd9o8Y6hgQKyNk/j7ARFzO+6ETmt2G9X8a2fj/xT7b33MQqQFAMcy7Rm7Kguf16sfHLJV6yHP06HcMMFJC3qQ6bW+Rm/CA/1ofJTd+osY5hBPL/svHPI2wMF2cK0YnAZ1NyoISm/ms6rZz8vVhE7jt06ECff/45HX300ZG2MACB8iYwYcIEuvfee2nOnDkZnzo3N1cX/Tdr1oyaNm2q/waNGzRoQNu3b6eNGzfShg0b9D5ozM0Vu3btynieJ598Mj333HPUp0+fjMdGwCOLQJxGhQED76AG+fXU881+gKidLq13Dy0oLBcbJdE2vGeZY2sP2MORaSM5dGKw2omnYjhj9lWbdtdyOXYDmvlZWtvGzs/eaaEV1/J15Twfq/1yV8YqsQ87R5ZL3lYkPaUj09EkCM9mjHfu3K1WUPiCvvh8Mu0v5QoK3KBw22230cCBAwkNCtY1wCcIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgEDVI3DENCrwpStSqw+8/tZCWvZdeOOAeYmvuepEOrVn6d50+fRz02nd+t1m2HIdH9O2Pv3yrlNC53xlyDxatDj4TfpBTlzQf9YZrenCH7QNLeoP8hNZcfEheuCh8aoQ2F+hZ1lkZ1ejP/3xLKpRPUtcMrZ/4ulptDnJChK8ogKvrBC0lWWjwpfT1tJ7Hy4JmlbLrv3pidSrR+nuQ39w5r98RQHNnruR5i3YRIWFB/wmzjG/5X/ggFOd46hBWa+oUFnvIeYW1ahQ1k0pUdeutPpUGhW8vwLk94EUH3kzMX9fmIVC4XLT34odx8/jZSeYcqOCnAoHMyufTLk5UdTYKIyyOyiiPFy9zB82t+jZw7QJk7uRo0fp5h1n7iCbIFl0lokWkrf3Bk2080ui5g/Th8n98ZMdS85sk27e5vU35wrLL0xu+kaN0807ztxhNiIPO9+onFlfDnkf3HuQJj3zJa2buyFORtqme/fuNGrUKGrSpElsHxiCQHkTKCkpobfffpseeeQRWrlyZXlPf9jma9u2LT366KN0/fXXU7Vq1Q5bHpi48hBIqVGBT8t+Nlk79bCz/lgnrIT68ac/WOUMrLFz6Ay0n7ZTIkvqfkfn79RaZn84c1qz2TrXnsVuLCegbW3tzO/pEk/22t9Kwvbh2K7AHVqxtYY/9KE+8o5ZpZwkhm2hYyfOaWnZtmDHThqpVlAY8/+mlLpBIScnh26//Xb6zW9+Qy1atLDPCzsQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQqJoEjqhGBb6ExcUl9J//fkNz522KvKJcNN//ru7UulVupG2YwR/+NIUKCvaFqctcHlVkvm9/Mb08eC6tWFWQUi718mrS/13enrp2Tq0gjldS4Lfhh23cKMANA2WxfTz8W5owaXVo6Buv70gndw1ekaMsGxXmL9xMr/87/I3tV//kBOrdKzMFDKu+30lz5m3U93/Bznj3JV/rPzx8Rig3v6KsGxUq6z3EnKIaFe7r37NUv2/816K8jytyo4IukbIrkaxabqtSWYqU/KykCSKlRoXn7BUV/MFwDAIgAAIxCezfvZ/GPTmJtiyN30R6zjnn0CeffEJ5eXkxZ4EZCBxeAvv27aPXXnuNnnjiCVq7du3hTaYMZ+c3pD/00EN0yy23UM2aNctwJoQ+0gik3KjAALj4Xu+tD6foXgntr8B6YFs5Qn1sG8hYbJwYVngObBX5WwP7WO9YY8xjj52JLT/LzRDarub3cRlbc1sGIrOP9C5BrwQ6sv1h6tnBjCFjZ28FZoQy0nvW71ANCqOGjaGxX6gGhf3hzf3imWzPDQr9+vXTDQrNm2f2RQTJ5oUOBEAABEAABEAABEAABEAABEAABEAABEAABEAABEAABEAABEAABEAABCoygSOuUYFhcwHqm//5Wr9JPgp+o4Y59MC9vahGjfTe8M+rBxw8WBI1TZnp4xSZ71Vv7n1r6Nf0zaL4RXGScOeOjYnf+J+Tky2ipHtezeKfL88JtTm9d0u66srjQ/WlUUyZupbe/2hJaIj/u6wDnX1mq0B9WTYqLPx6C7325vzAeVlY2kYFXtGDV07g5hwu8k91i3MPmTHLulGhst5DzCiqUeHJx/qoQrb0fteY1+BwjVNpVAjL0ftC+HjNBFYsp7LIKTLyxnJndIuQrOcBa6RQSazEd8bgWTR3aHgjkdjntcylS7hRQafMHyofOyU3M7GO3kujhLZUCSeLIbYJ52Avk5DM2yKsZsl03jbkdPNOLWempGayJ0s2p+bp+xB+Whwzbz9r9j2k/pdu3qnmrOeTm5QPovJW11fnZ9uxC28s4y21vNNnzXM5vKNyNmz9vEvDmnNIlbeTs3a2vJPFYHt/zuwalXfR9j007vGJtGN1/ObRK664goYOHapWuarFU2ADgUpFYO/evfT666/TU089dUStsNC2bVtdiPyLX/wCP5uV6o6sOMmm1aig0neePeoZq59T8qw1HlqujXu+ItNeyla+F4icLe1Qeo5AufF0NfUiFpns3dmNvPU8VrIynzW3cQIS0JcTiyW27CPnsII7Ec05d+zYRSNVg8L4MV+WukGhdu3aToNCs2bNzLQwBgEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAIEqT+CIbFTgq8rNAy+/No+46Dlq47fZc7F4qltJySEaMGhcqm4Zta9VK5v+/OjZkTG53nHMuJU0+vMVxHmnsjXMz6Ff3NiZWraoG+k2b8EmeuOthaF2Pzy/LV184TGh+tIoSjN3ZWtU4GvI5ztx8hpameJqGX7GFa1RoTTX0X9uqR6Xdu5kjQrcoMCNCpV5q2iNCszSrOUWtmYRklmAbBY1iV9KjQrP8ooK5u9Pt6jKnFPyCNubOZk2Zn6m3LQXmyCZ6cNjOUdLXr55h+UXJjdzD847PdYWB/Pc3ZmEpSthZq6tqQ+Ti6/hpkRuDC4FlK287xFOw9Oo4KYiKVWce0RXH1ppRbFmqyje+lQDztc5cd/AnNNUmfeAyE1bUx8mF7+dqqlw3J8m0O5NhSKK3HMR9CuvvELZ2fGaRSMDwgAEDhOBgwcP0rvvvkt//etfae7cuYcpi9JP261bN7r//vvp6quvxs9l6XFW6QhpNSqoLxLu802N3QOnycB6nNoPQGenBr6xNCrwRZBnmXxP4WORWXrrUjk+OpwT0FJ64tg6W6OPJLjHTlzlXPjY9TVcdD46J5nWVNphdN5OCMtQ5pao7LZjewGNGDaWJoydmpEGhTvuuIMeeOABQoOCfSGwAwEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEfgSO2UYHPk1cSeO6FmbRpU5HvtBMPb/1FF+p4YqNERYRk0O8mEL9hPmw75eSmYaqMyLmJIJXC/xUrC+i/7y2iTZujmZgJcpH1Hbd2o7ZH1zPFCeMFX2+mIW+Gv538B+e1pR9dVDaNCryiwJtvhzdJ9DmrNV1xafuEnFlQmRoV5szbSJ+MWEYFBfsCz8UvPKZdfVq+Yodf7BxXtEaFynoPMVA0KhCd2q8Hdb2mk3N/mQNvcTFrrIJusxhK7C3b5AXfifHEm4uurLEbxy2CMv0y1ajAs+k5zZS10MrD+TSKxx2ZMfCzMIufxYxt/PJEP7GWvZmYlGtZujh5uxwlnnfvmT/gHINy5ggeP3VsXhtrBsk7IGc2ELVlbNa3aUmyvHXBnRHWz5QDxMpbn68kwHszKWMCHc+nZnOvCUsSrq8W2h+JzMz5LKOgvBP9zKg8NuN4kyqXe0SBkMYKM7N089ZnwB/maXFg76nZ95zfyMogU/fINvUMHvfERNpbsNcKHOOTi6H5LfT+84/hChMQqLAE+PfsuHHjdAPOxx9/rP4bKt532cN5QjVr1iRe2eT222+nc889Fz+Th/NiHEFzx2lUuO83/ahBw/rWY0s/iPl7CUNQH9Yfm4j7HdeSu0r9HHNctLPzHHR0HFEFtqewx7atNZs9ny+ua2LnYcXR00m+opHgHE902t8KYoncgIa5Za9UOl/XREeWWDKn62fHtRSMhbZvK6BRw9UKCqpB4cCBg9o/3Y86deqQNCg0bVq2/39PujnCDwRAAARAAARAAARAAARAAARAAARAAARAAARAAARAAARAAARAAARAAAQqCoEjulGBIW/YWEjP/WOmelteeDMB23Gx9qD7TyVeoSCV7c9/nRbaCJGdXU29Qf1sysqqlkrIMrfl1SY+H7OSxo7/noqLS2LPx2zuvK0btWmdF+rDjRDP/2tWqP60U1vQT3+c+uoVoQENRVSzwfnnHk2X9D3W8HCHUb7c4MCNDulsC7/eQq+9OT/UlVfz4FU9orZdu/fT+x8uofkLN0eZUm5uDerVvTmd2rM5NW5cW8/PeQRtFa1RobLeQ8wWjQpEvW7vrhoVOvtuNSkC9lYXSTGRWyDu1XsrjN0Cqmh7N47MwQkFFcHPGDyb5g4Nb66SE8lrkUuXPHsRV1eJiCNaKXpkrJbzNUw9w6AYHoPEAw5puiVa2BKfEZ+0FhlyAZF23vZ584xG2ISUBEMyG+3kN7Dja7HozDlFJjPKRHLs34u9GcNvYxxzOHExxIlDn1EgV3tObWrax82ZZzVjJGbhSDKZd+C52Lk4EwYN5BztnNlEREHmgiGZjfbzG5hMDF155m1MG3Rqluwo2rRoM014ajIdKDoQbmZouOjyz3/+Mw0cONCQYggCRx6BggJVNDxqFH3yySf06aefqgbcggpzkvXq1aO+ffvSZZddRhdffDHxMTYQyCSBtBoV1HPHLNY3H0NOwb56hsjXO21rJ+3o+dhwFBvLx/JlW9NezLXMPjD1JheRazOOI0o7KZlHp2HLEsfipFIVGxVIR3MCWjaiZzGPxfyQPTPLt6sVFEbxCgrjpqkGhXjPYjcD74gbFO688069gkKTJk28ShyBAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAgEEjjiGxX4rGfO3kBv//ebQACmkIu6r7nqRFMUOX7xlTm0dNn2ULt7f9kjaWF/qGM5KLZs3UMfD/+Wvv4muIA9KIX69WvRwPt6hTZ0cMw//WVqkKuW8dv9f3nnKaH60ije/2gJTZm6NjTET/7veDrjtJaB+oreqMBc//XyHNq+I/nbmJs3q0vnn9uGTu7alKpVcys5uFGisjQqVNZ7iG8sNCpIowKvqODef97CfUsuhUTMzW084KNgPylECreXimdvDO88rJPNsi9Vo4IURXPIsInM05Gp9d5WeGJ4DNyD4FNz9Z6RMaEndoTctOV4hrkb3hCa9obYsTVzDo3nWKuBEcQT25YHydjdIzfjmeOAGKw2pnSszbyD9I6hDAJih94LRsB08zZCSAZ6n1LeRhBPHhFy05YnNczdXAyhaW+IHVsz59B4jrUaGEE8sW25KdPxAuRGCDNyeGyvlT4y8w6NZ/mtnbWOJv9tGhVHNMvKLFlZWfTSSy/RrbfeKiLsQaBKEODi4ZkzZ9KECRP03ylTptCuXbvK7dxzc3PpjDPOoD59+ui/PXr0oOrVq5fb/Jio6hGI36hQTz391MPG/m6hvw/zoYlM6fSx+2Gbm3L2sb0MZ5FxePmu7Rb8W4b60/7wjC21k4n4s8CyM+e3jN2vSErnBgsYS1ixs4LqiPa8Qf5uyKNo29YdegWFieO/ooOlXEGhbt26dNddd9GAAQMIDQpybbAHARAAARAAARAAARAAARAAARAAARAAARAAARAAARAAARAAARAAARAAgXgEqkSjAqMY+r9FNH3m+kgqd91+MrU/rkGknRi88+4imjErPO6Vl3egs85oJeYVcr9o8Vb68JOlxAXicTZ++z+vAhC07dtXTIN+NyFIpWVcPP+nP5wV2ugQ6hhD8fiTU2nrtvBzuEOtBnF8+/zASBW5UYGZ/uWZr5I2KTRuVJt41YeTTmwYeH6ZbFTYu/cgPfjIxMB5WHhKt6Z0w3UdQ/VRisp6D/F5oVFBGhXCVlRgSnZ1EY/U0K0t5upfV8eW/gaHePb+GP55rMgSO+VGBXb3JiIBk8hdE8/ILHgWhT/9ODbi6+w9YB1paN6uhXfkz0Vrw2IbrmnlzP4hsY3QzjD0GjgW3sEhPpmAxMxzDFAn3JLeqNZRoF/IuaScd8CEZs6sDpw/wM8jSjE/j69x4M9Fq8JiG35BObM6MJ7hl8o9YrqZ49A50sw7JN6KCato2ssz6FBx2MmaSRHVrFmT3nnnHbryyiu9ChyBQBUkcPDgQVq4cCFNmzaNZs2aRXPnztXHe/cmb9iNg6pWrVrUqVMn6tatG3Xv3p169+6tj7OzU1tVL85csAGBMAKxGhUG9qMG+XajggrkNCnwdwlzU8daYsitoVHkb9hLQ4H4SDRHzvFEqCKbYwnj2loSORY970UWnIvEtSZy53D97Mh65+iVufLkD198PaO23a4aFEYOH0OTJkzPSIPC3XffrRsUGjdubKWETxAAARAAARAAARAAARAAARAAARAAARAAARAAARAAARAAARAAARAAARAAgZQIVJlGhcKiA/Tnp6YR75NtXPD9G7ViQHZ2tWRmjm7kp8vpi7ErnWP/oGvnJnTTDfx28Yq9HTxYQl+MW0Vj1F8eJ9u46OCRh06n+vVqBpo9+sSXSYvqr7v6JOrZvVmgb7rC1Wt26SLxZP4PDzqNGubnBJpU5EaFDz9eSpO+XBOYNwt79WhOP76iA9WokRVqk8lGhX3qzdCDHp4QOldpGxU4cGW8hzhvNCpwo0IP6npNJ6eoyWpECCrUVRVGkZvpF20vRUxu80PQBFZMKZ6a/ooqgBy6IMjQI8trkUuXPHuRR4YDEAABEAgisHjUUpr91rzgJpIAB36b+8cff0znnXdegBYiEAABJsCrL+3cuZMKCgpox44d+q9/vHv3buI3n9erV4/q16+v//rHeXl5ToEzyILA4SJQ1o0KfF78XVe+G5vnKd+B9TdrtrGVjlwJpBlA4lgmYulvEoiYx5ooIRdrPiummafkkTinLdHnpZPUAvHlFRRGDhtLkyeoFRQOFlvGaX7yc1kaFBo1apRmFLiBAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAgwgSrTqMAnO236Onr3/cU8TLpd8IO21PeCY5LaiHLJ0m300qtz5TBhz/9wzqs0HHds/FUaEoKUo2DN2l30xlsLk65MwOkwH+YUtL3/0RKaMnVtkErLGjXMoUH396asLKswIdQwBcXLr82jxUu2hnrUr1+LHnnw9IQCCXGoqI0KK1cV0PP/mq2LsyRXcx+3KSCTjQrFxSV0/4PjzTQ8425dmtDPf1a65pzKeA8xBDQqJDYqMBcuLkzc4vz8m37R9lKoFDidTsCNJ0VQ0werRoV30KiQeH0gAQEQSIfA/P8upIUfL4rtym9oHjVqFPXo0SO2DwxBAASCCaxZs4ZatarYK9kFZw5pVSMQt1EhP7++g0Z/d1Vfh+U7rKGwmg3ki7BS6G/N6tjaO5Y+udukwBYSl8N4GhXYywhkTaMF9n9bJzYqSCwrrv5M+O9w18br78rZjzdXr3XW1E6+27Zu1w0KUyaqFRQy0KBwzz336BUUGjYMXqnQygmfIAACIAACIAACIAACIAACIAACIAACIAACIAACIAACIAACIAACIAACIAACcQlUqUYFLl79x4uzaMXKgqR8srKq0QP39qSmTeoktWMlF+D+8U9fUsHOfaG2DRrUot/c24tq1coOtUlHwedj1COkEyLQZ3fhAXrq2a9o1679gXoWnnB8Q+p3S9dA/aLFW+mVIepNwkm2S/oeS+efe3QSi/iqhV9vIS7ET7adc3YbuvyS40JNKmqjwtv//YZmzt4QmHdOTjY9POh0qq32UVsmGxV4rvsGjlX3fvCs7Y6uR/3v7h6sjCmtjPcQnxoaFRIbFaz7JOhmsauMkt4Tpl+0Pf8+DLsv3WkkplX0lEqjwo+eSb6igvn7ODoPN6OyHMVhcjjzjpNfGJ/DmXdYTlHyypgzn9PhzJt/8uWnNoqvX1+eeR8qOUQzh8ymZWOW+9MIPW7Tpg199tlndMIJJ4TaQAECIBCPADf8vPbaa/TBBx/Ec4AVCBxGAnEaFQYMvIMa5Ndzs1QPNf1csx9uzjdjlotV6Ngy4EJ/tk1sBnBlHN6J6Bnb8+tQ3jGL2E976j2PrU3kfGSNRe4amvmYY8uS/XQinry3btlOo4aPpS8nzSh1gwKvtMINCvfddx+hQUGoYw8CIAACIAACIAACIAACIAACIAACIAACIAACIAACIAACIAACIAACIAACmSFQpRoVGNn6Dbvpr3+bQSWqoCzZdky7+nTPHad4/jE9zH74qO9o7PhVYWot79WjOV370xOT2qSiXPjNFvp42Ld00w2dqFXLXI8rn9vz/5pFF190LHU4Lr2VHHhFBH6rfdjWpEltelCtihC0HTxYQr9/bDIV7TkYpNYyLja45abO1PHERqE2cRTrNxTS3/85k/btK05qfl//ntS6lZeT6VBRGxW4YYTPMWg7oUM+9bu1W5AqQZbpRoUHHhqvCkJKEuZhQf16Nen3vz0jUBdXWBnvIT43NCoQndqvB3W9ppNvFQWzEMm6C7yrLLh6W6t3UqgU3uxgWVufwTG4YCp4s54BMwbPprlD462o8KNnLtSh/E0IZgFW4lyHdPOEWZjFNhwj0c+yNWPEs/GeI7P1zydzemN7/Uxdshjp5mTGD4vhz9vPmmPIfWHGs8bBrFln8faer/cejHs9gmNE5Z14vmb2wXnjHmFGJu9gTmzlv0/K+x4pUc/Dqf+cTqu/WsPpxNpOPPFE3aTQunXrWPYwAgEQSE7g1FNPpRkzZtCcOXOoa9fgZurkEaAFgfIjkNFGBW4rkMelGsiQhe7YOjd+PrIs6DkpMrHRHp4Y7jxia0cVU47s5mIprRxUHN70p52UP4ZtEpqbtle+WzZvsxsUZlJxcfL/D8BOIXTHDQr9+/ene++9l/Lz80PtoAABEAABEAABEAABEAABEAABEAABEAABEAABEAABEAABEAABEAABEAABEEifQJVrVGBUn4xYRuMnfh9J7eqfnEC9e7WItNuwsZD+8sxXkXY/UCsIXPjDdpSdXS3SNsxgx4699JFqUJi/cLM2ufnnnalzx8Ye8+LiQ3T/g+O0rMcpzeiKS9tTnTrVPTZRB9wI8dob4asURBWjM1/mnGyrUSNLN29069IkmVmobtX3O2nIv+fTzp3hKz+w8zFt69Mv7zolNA4rKmKjAhfrD3x4QmhTDV/b6685Kel5iTLTjQq//cMkKio6IOE9ey4ieeg3valRwxyPPNWDynYP8fmhUSETjQpuE5lZwOQvKk+8n+yqJ61wY3gLnU0vyybVRgV/QbRENHMVmT9nKcDyxxBfv73EidKzXZCNzMd6/5ws4038rCP1qbCocnDnkAcSx4whfmE5W37WNQmz0aVy9mUzbYLm8ySkczKvtxL48g6LkZG87eBmztb5WlmanCyJ9Slzm7K4McTXby+xovRsF2QjnFif6bzDri/PJVtQTqLjfVgMyTssZ+0rRhKwjO6Rg3sP0uTnptKGBRtlpsh9z549id/+3qhR6Zo1IyeCAQhUEQKjR4+miy++WJ/tlVdeiVUVqsh1r8ynGadR4b6B/VTxfH33NNVzTT837a9A1k59Wn/cL2zKQ+vYXrztAUusx6PsxYDdLSPeiz9rzbE+tgR2nGB/V+r6W9GdgIa/ownMTfLassVqUJg6eVapGxTq1VMrAKoGhV//+tdoUDAvFsYgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgUAYEqmSjAr99/89/nUYFBfuSIq2dk02DHuhNuXVrJLVj5Qsvzabvlu+ItOPi7auuPJ46tE/tjX1clD9x8mqat2CT+od5t4g0qlGBE8pR53H2ma31Xz6nONt7Hy6hL6etDTVt1rQODRxwaqiei+z//PQ02rZ9b6iNKPqc1Zou/EE7nafIku2Li0tUY8FaGjH6u9C3+os/FzYM+FVPatmirogC9xWxUWHzliJ64qlpgfmysN3RqsDi7u6helOR6UaFv/5tOq1dt9ucwjPu2b05XXd19AoifH+Mn/A9lahq05/83/GeGJXtHuLk0ahgNSp0ubqj51raJUo+mfwec4uTXANXxzVTVjGyyFwrdxQUg7Xsk0xHlEqjwsV/tVZUcOetgqNkSOPiyESMuHPBrvwJZOL6ZiJGOZz5vt37aeJTk2nrsm2xZzv//PPpo48+otzc8FWeYgeDIQiAgCbQu3dv+uorq2mcv/tjVQXcGBWdQNxGhQaqUYG/C+vvs2qvWwjsr7Z2O4Gt0krPaTsNB9rdsVbx7AAc1R06csfPVpr2dij29PiynDfTVsZ6ChXLmcqJqz20n3xYKjc2x9isV1AYQ9OmzM5Ig8KvfvUr3aDQoEF6K09KrtiDAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAjEI1AlGxUYzdx5m+jNtxdGUjq5a1O68Xp/0W2i25ate+jp56bT/v3FicoAySknN6VOJzWiZk3rUpPGOZSV5V1lYa96Q+/yFQWq+WE7Lfl2W2hReJxGBZm+Zs0sOuO0VnRqj+bUpEltEXv2/LbmMeNW0chPl3vk/oM4b/OPy5hj16qVTWee3oq6dGpMrVrW9RQ5yNxcuP/Noq00YdJq2q5WloiznXFay4QC+CC/itiosP9AMQ16eKIq0uaKzcStWrWj6L7+0U0Y69bvplfV6hjbQ5pG6uXVpD88fEbiBEkkb7y1QDXNWKt6BJlxbn0vPIbOP6dN4LXknMaMX6V/DktKDqmfgdr0oGoK8m+V6R7i3NGoQNTr9u7U9ZpOvkvplCYpudzPpswtlPLe7mLL4bz2vgmSHJoxTDMr3ozBs2ju0AWmInCc1yKXYjcqyJTJUo5jE5iJIcxEDCNcyKVxLWQ+liQ7N9cjcZSJGP6oEjMspyi9P17QcSZimHHjxItjY8YMGmcihhk3Kp7o2SfsepjxgsaZiOGPKzHDcorS++Op46Jte2j8nyfRzrU7A7TBoh//+Mf09ttvU82aNYMNIAUBEEiZgLmagjhjVQUhgX1FJZBSowKfBFfw6z/WXovkQeuTWzrLR6msTWz4yBjbPQPaxmksUELtZytFbgWyUtFhTGcOaxx7xpaxZOsEsMydDHV4kfF+86atNHrEWJr65WwqUS8qKM1Wv359kgYFHmMDARAAARAAARAAARAAARAAARAAARAAARAAARAAARAAARAAARAAARAAARAoPwJVtlGBEb/86lxavDT6Lbg//1kn6talSeRVmTJ1Lb3/0ZJIO78BF3U3apRDdWpXpz17DtJu9YbewqKDoQXqpn8qjQqmX4vmdalL58bUolldql+/Fu3bd5DWrS+kyVPXqLcWFpmmgePbb+5KJ57QMFBnCoePXEZj1RvzU9lqKw5cuF6nTnViNkVFB2jbtr2xmxNkrjat8+juO06mGtWzRBS6r4iNCpzsE2pVimTXg6/j3f1OJmbm37jBYZxiP+qzFertk+HFHdnZ1ejJx852mmVmzt6g/e68/WSqq65B0Bb3Xm/VMpeOaVef6terSTvUCiYbNxbShk2FCauZhDUq8NyV5R7iXNGoUMUaFaS4mS++1FmZMpbzJjrryO3VkGO/XuSyD4opOtlHxRA73pvxxM+Uia3o/D5BepGZ+6CYpp7H5hx+nf9Y4pk+IhNbU8eyKL34yT7IPkgm9lF701dyM2XiLzo59tv49WIne7+9yM19VAzT1ownfqZMbEXHx1F68TH3QT6mnsfmHH6d/1jimT4iE1tTx7IovfjJXtnvWr+Lxj85iQpVA2Xc7bbbbqMXX3xRPWujv5PEjQk7EAABInM1BeHBRdJz586lLl26iAh7EKhQBOI2KuSrFRWcTd3XugHAfo5ZO/Vp/VF7W6Ec9IjtxdkeaIkxNlycRgOeQ/zZ3bJxIpnTeHycqcyg7G8HcSJYAiOOpRG3zZu26QaFadygUBL+37AyX7I9r5rADQr8Fw0KyUhBBwIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAJlR6BKNyoU7NxHTz07XRfCJ0PMDQQDB5xKubk1kplpXdzmh8hAMQ3SbVSIGT7QjBsIHv3dmbqJINDAEPLb0fnt+/MXhr993zDP2LBxo9r0q7u762aHOEEraqPCG28tVCsXbEp6CnXr1qBLLz6Wjj2mvm52WbN2F32/eqdmvur7eG96vvCH7Si/QS36asZ6tZLHDj0f3/PNmtYJnJtX/Pj9Y1OIV33IxJasUaGy3EPMAY0K3KjQI2BFBbMSWMqUTJncRaKTY9MmFZ3p7/czdUQzBs+Ov6LC0xeKs7PnhiDzrbGOwjPg8/DnESRjp2C5nofVThhnwFLfZnJjVaJtdN7BeagOOhUuMV5g3joNtpf0nIEIfHvtYMh89qL2iQ0HNWSjIIMgeZBMReBrykGdMM6ApQGbJMaqRNto1uwXlEuQLMw21bzNnDlmOnmH5HdE3SPMxrttW7GdJj41mfaq75Bxt0GDBtETTzwR43dF3IiwAwEQYAJBqykIGV7B5P3335dD7EGgQhGI06gwYOAd1CC/npu3+v6lv4LZ38PcJ7ctZ0u2EQ/PWIRsYlnoT8PGlMtYx3MDWvO7odxYEtPeGyZ6KPGsOS2tyPiIx5s2blENCuPoq6lzMtKgcO+991L//v2pXj2DoTU1PkEABEAABEAABEAABEAABEAABEAABEAABEAABEAABEAABEAABEAABEAABMqRQJVuVGDO8xZs1oX0UcxPUqsH3KZWEYjaeDWEl1+bR1wsXh7b4WhUuPKKDnTW6a1in96BAyU05M35sVaviB00iWGjhjl0x23dqGF+ThIrr6qiNirMnrOR3hr6tTfZcjpK1qjAKQz93yKaPnN9RrJJ1qjAE1SGe4jzRKNCaRsVmKJTDaXGZjF1mJx9eDP1fCy+fjnreLP0KTUqPHUBV1JZ7hyBC7I5jBLpsjBX5djown4+Mvy0k5Oe4cTxZBN7PYX+sOexDUQv9s7etnWOffb+eIFxjBimPig/Di9yfSr2+XAIW26G8HIwkpQYhsi6pL546jCSNccwJ5XYZn5s48jtObTIPXczhCce+8omMeSY94ZjaveIdnYjSWwjnpOzOY//mkoE009keu+eo0cs9v54IvcYq4O4+bGfY8sHvmvKEvcS+A7Y3t4khhzz3rymnDfbKFlZ3SObvtlMk579kg7sOWBmETrmwsunn36aBgwYEGoDBQiAQPoEglZTkGj884dVFYQG9hWNQKkaFawHnfUI5BNT97rzGA0dWwTM56OMxVcaB3gvMh3bPhB7k6XITF9TL2PR87EKrzeRbbQbFGZMm1vqBoX8/HziBoVf/vKXaFCwMOMTBEAABEAABEAABEAABEAABEAABEAABEAABEAABEAABEAABEAABEAABA47gSrfqMBX4J13F9GMWdEF11dc2p76nNU68qLt319Mb/5nIX2zeGukbWkM8vJqUL9bulGL5nU9YUpKDtEDD41X/9CvCvYyvJ19Ziv6v8s6pByViwdHfbqcxoxf5dQrphwkhkOXTo3p2p+eSLVqZcewdk0qaqMCZ/jq6/Pp60Vb3GTLaRTVqFBUdID+/s9ZtGlzUakzimpU4Akq+j3EOaJRIahRwf97SEqf/HImyJvoeWzahMnZjrcwvSm3LM24KTcq8DwcUqV2yPqwgmqxfy4zfzYTfRy52NrzWLM4EZxJbbm788cWRzuembcSGaVobojY3CVHc05LptnI1EZkayh+psKMYcjtajan4J9VgXn7/c05TJ3Ig2SpsuZkzDh8zJtOUKtwj8TjLVYWP5uhe2CPglgrlVQ8KrW+T2z39O9tMxuZ8yhaM2sdTX3hKyqOuZJQdnY2DR48mG666SY7f+xAAAQySeDTTz+lvn37Jg2JVRWS4oHyMBJIuVHBftbpJ5T9YYnUgfVH7/nDUutPfYbWsaOx7S29PELZUBoHeG/GEBvnuWqH9h6rI3sisTfxis6aR3+qFRQ20yi1gsLMr+ZlpEHhvvvu0w0KeXl55tQYgwAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIHGYCaFRQF2DPnoP0l2e+ooKd+5JejqysavSru7tT61a5Se1YyU0CH3y8lL6ctjbSNlWD7OxqdI5qmPjB+W2pZo2sQPf3P1pCU79al9FmhW5dmtCN13d0ihgCJ44Qzl+4md77YDHtLoz3NuKIcI66RvUs6nthOzrn7DaOLJVBRW5U2Llzv7o/p1GRuk/T2fIb1NKNG+vW707JfdD9p1LTJnWS+mzdtof+8eJsKihI/rOTNIhSxmlUkBgV9R7i/NCo4G9UkCJfuXrm3q5ySij0Frlpy2MzVpBNlN6O53sr+4xXZ9PcoQv8kyUc57XIpYt5RQWpBlPTeYrQ2SNZWlonBtrZmsMW6d0h0XMst9TfKQSzZrRQGKZWIJleKVhnn6d+wby2Fbkvb62TCMZecJrVZiY720/vJG914GbNaVhGHk62nzGTbaUUrJO81VCb2vN7GhXYOSCO9xYxDCRvQ6Rzc87RzVpyds7EseFJvZsVToL6YrBYX2b94TqKuSvRdvpQ68TA8LNFeies2aGS3iMOWz4F+0KmdY8oRPr2kHuUkcm11nz4w7cpG2cTPxaIn+BXIpP38okraMaQ2XSo2AzgREoY1KpVi/773//S5ZdfnqCDAARAIDMETjvtNJo2bVrSYFxwjVUVkiKC8jARSKlRwXheOY8pJdNj1vEfVxH43+pO84E6X2lI4FN3/Vy5tjUUMpRntuXnTOgEseyUlaFiW95c2VHEKyh8OmIszZw+v9QNCg0bNiRpUMjNjf7/aKxs8AkCIAACIAACIAACIAACIAACIAACIAACIAACIAACIAACIAACIAACIAACIFCeBNCoYNPmN9bzm+ujtob5OXT/r3vGfmP/kqXbaMLk1bR4yVanDi5qjjB97drVqfvJTfWqDpxH1LZ9x16aOHkNTZu+jvbuTa/Inedo3qwO/ajvsdTxxEZRU8bS84oTk75cQ+PGf0+F6q38pdlq1syiM09vpRsU6tapnnaoityowCfFTQbvvPsNrV0Xv9mgevVqdHrvlqqB4xjaoe6FZ/4+gw4cKIlkVL9eTbrisvbUtXOTSFs22LevmD77YoW611ZTccwiTjNwo4Y5+vqdcVpLU5x0XBHvIU4YjQpmo0JIQa+I3YolRU6ETDGguonFkTYxYkgxso5nfaTSqND3LxdYxV2coprOU1xtxAwfyrmZubrWZgGYU/auXLRc5gw4BzcCF4JpB29+/hhW8qZbkjFPLFuKedvXOKHJQMLJ3p+fnCPL48aQWM4+ed6xWEdxCskv8Bo4eUUNJO8UWesqRRWb70vhFzJVYH58LmaMqHP3xJacWZhi3nGvb1h+LLdjxDl3T9p8vs4WnvfikUto7ruqmSnYxIkgA36T87Bhw6hPnz4iwh4EQCDDBOKspiBTYlUFIYF9RSKQTqOC+dRSDz/rKcbPQOuP3uunuTZ0ra1D45uPtrf08ghlNvI85b0l99uYMWR+oSo+bhxHY4WhDes306cjx9GsGQtK3aDQqFEj3aBwzz33EBoUhDT2IAACIAACIAACIAACIAACIAACIAACIAACIAACIAACIAACIAACIAACIFAxCVSYRoXi4hJ6+I+TkxbU33BtRzpFFeqX1fb2f7+hmbM3RIa/4tL2ulkg0tAw2LS5SBdyz5qzMek5Gi56yG/Db90qTxWNN6bOnRoTr6aQ6sbF6dyIMWfuRtUwsY32HyiOFYKbIS74QVvq2b2ZU7gQyzGmERe4z5qzQef07XfbY3OpVSubjj2mPh3fPl83bnADR2m3eQs20RtvLQwNc8N16t7rlt69t+r7nfS3F2aGxr71pi7U8aToJhBuAvhi3Er6YuwqOngwvOGAVyc4uWtTOvOMVmQ2byxWTTPvqHt81+79gbmwbR+1IsXZyq9GyEodgY62kO/xT4Z/SzwPryiSbMvKOoo6ndRYNVK0oPbH5dvFMMk8gnUV6R7iDAe/Po++WbQ1MFluqnnyscpduLpu3Tpq2TJ5Q0mv23tQ12s6BjLQQrk1zMqohApgu6LJiSJOIvDrWW7aBOnZxLSxYqXaqKC9OHxiKCsgf5o6SSVI5npYI9NGdOyv/nI5mFOALnYSW2xlz3KxERnvw+SsM+3NuGFy9pHNtGGZ7c+Fbk4zh9iYscVf9snyExv/XuKy3IwdJhd/Uy8yM2+5V8TOjC32yfZR5yJxOYYZO0wuc5l6kbG/+lvm9wjPJ/OnkrPpx2PexF/2Epf3ItOGvg/Wia2pCpOzjWlvxg6TS1z1mJ3/3kJaNGKJSCL3TZo0odGjR9Mpp5wSaQsDEACB9AnEWU1BovOzCKsqCA3sKwqBOI0K9/2mH+U3rK9TliYCJ391X+tHGn+ftv5YKkfOh2JjjK0hf1paw1fm4D2HtTbvmGVa5bGxTTmi7WfGWr9uk92gMN/9LisuKe65QWHAgAHEDQp169ZN0RvmIAACIAACIAACIAACIAACIAACIAACIAACIAACIAACIAACIAACIAACIAACh4NAhWlUOBwnf7jmLNpzUL/hnlc82LFjH+0o2EeHVGF3rZxsqqWKmbkQPy+3hioIzqU6GSjCN8+Tay93q0L1bdv3qr979H67GnMRfIP6tahRoxxq3Ki2+psTe9UIM366Yy5sX7V6J23dukfnt3v3Ab3aAhc71KlTQxfc11GF9Jxb61a5VK2aUz2R7pSV1o9ZcVMAr7KwcWOhrsGsqxjxPdP26Dyqr65j2MYNDgsWbqYNmwr1vVerVpZaMaMutWyRq1fOSKcRxj8Xz7F5S5HKTf1V8/B9npNTnbjphv82UH8bqlUUaqbRDOGfyzzGPWTSKJtxvEaF7qpRoVNAAv6fWbNKWJnzod+EowTKTUMjjmNr6iUI7/3bUTRj8CyaO1S9LT1iy2ueS7yiQpxNVkOwy8McF8k0MTtLY9p7YoiDHYB1pq0zQSkHnjmNWA5WQ8ZDv70cs07nZ+QturLKOyhuUN6Sh5NjwHk496EKwPZBsdm/tFtQbPsSOynIHJK3mYtHZrBmn6DYEqs0e8+cRqAg1qz228sx6/S5GHmLzjxHtsvExrGD4gblzbb8nWzm63NoxYSVsadv27YtffbZZ9ShQ4fYPjAEARBInUAqqylI9J/85Cf03nvvySH2IHDYCWS0UUGdjTQI8ImZTQLyhcLzDLSfvXqnHOVR7Pq5Mcx4/OSWzdvMIFLXj/XSoDB75oJSNyg0btyY7r//frrrrrvQoODixggEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEKgUBNCpUisuEJEEABEDg8BOI3ahwtWpUcGuZVOKeA/tEpCRbHRpDj2mYPMjIY2vOZypMhpZNqo0KzqoGfFZmVZgROtBGpeEUYht+ItPuIama8wTGjppb6TPtl0reUXNz+mE2ItdldOZltc9Z9HwYh5OTdwZY85xB8wfJ2NbcwmyC5E7OHCADeQfNoUPLKhLqwGTJOr2F3cMhfqnkHZaTTM37MJswufiG6cPkxQeLadq/ptOameskROS+Y8eOukkhasWZyEAwKDMCmzavV0254SuKNWncnLKyssps/vIKfOhQCa1dt1o1/y5XK2gVqKbfQioq2q32/LdQNQPvVKtm1VSN0HWpdu06nn3D/MZ0bNsOlJdnvcG9vHJOdZ5UVlOQ2NWqVdOrKnTu3FlE2IPAYSUQt1GhgVpRgb/+eJ7L+vuQ+mZk79lAD/mMlDBhbAscjXPstZc5JK58XXW/g1mOfj1Py5vYrV+3Ua2gMJ7mzFroeXZbVql98kpF0qBQp06d1JxhDQIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgUCEIoFGhQlwGJAECIAACFZ9AmTUq8KlLAbZTXWXzYLlf5gjEybDloVRWabHPRsvcgKk0Klz05A+1t3xIQZYc894sfuZjx0alYRZuczGYeeycPzv5ttAYDgfloE7JPzeHYV/PPLbMdGU70zdsPrZLKW++Dr7z1jHMyWPm7eTEAezNzJlFjk3QnDF5J40hedu3T9D8qbJOlndKrDk3zst37vp8eBLeYrK2TO142tH6MM83KaeYrPU8GbxHnHghOWt9CCfxPbD3AE3+21Ta9M1mI0ryYe/evWnkyJGUn5+f3BDaw0bguxVL6D/vDk46/6/vepjqVfAC/bAT2L5jKy1fuZS+W7GUVqxaRnv37gkzjSVv1LAJHaMaFo5t14HatjlWNzbEciwHI1615KKLLkprJqyqkBY2OJURgVQbFZwGBH7W288yPdSH9tOen6n2ZpkZ3wJclRE/+9IAADARSURBVP4up930h2uT0KhgGznPfDWvO4U5tr6DrVurGhRGjaO5s7/2fK+0U0ppxw0KDzzwAN15551qdUU0KKQED8YgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgUMEIoFGhgl0QpAMCIAACFZVAvEaFHtT1mo66YFqfh1EY5T0vU6Gqqz0b6/wyNrB95A3uZgjtH6U3Ymh7oriNCrnNc6lvUKOCHcdfoG6LuaRLhgkNA47CGLC9P1aqMYxwgcOoeFF6f1CxD8vbL/f7xzmWOcQ2KKZpE6QXX9mLvWkrMrYx5eKT6t6MFxbTtIkzJ9v77VKNEXUeUfGi9P74Yh+Wt1/u9497LPOwfVDMZPp9u/bRpGe+pG0rtsedji644AL68MMPUUQZm9jhMVy2fDG9/b9Xk05eGRsVVqqmhHGTP6PvV69Iem6lUWZnZ1P3br3pzN7nUd26eaUJlRHfdFZTkImxqoKQwL4iEEinUYG/UurnmP3V0vmGqboHpMnAPDeWuTauRmy1zrAROVvK2IyhZTK327FAukFh5DiaN+ebUjcoNG3a1GlQqF27tps0RiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAApWWABoVKu2lQ+IgAAIgUL4E4jcqdFJVwkajgVMlZeZrCg1bt6RKGYfIA2Mb8QL1PLdhY6eSUqPCn9WKCkYIo/wrsCjamtFyCCqatlNwdmHxAuUhaJxgPAixCYz3/9m78zgpqrvf479h2HqQsIiyKbIIimwKohEiypMo4vqAxsFdfBQwEpMb84hrMK9cvfdJbp68JN4YFxRXJirXuAbcFXcIgmzKOggiIqJRaRmUmVunuk/36Zru6qpeq7s//ZLp6nN+Z6l3Dc78UV8qYWD0Rjh7CnMSR1H0o57PeY5J283pDMuEmVPUJJ3PGKj7VZNzL0ZZ7FDXm7W6rdkcKfYUmyxFf8r5YgMzs3buL+k6KfZkLM33SBQj/HlYXvvDG/LVJ18n8Lh9qK2tlfvvv9/61+Zbu5XRFwCBcgsqbNq8QV5ZuEDqP1pfMN1IYOEYK7AwtmiBhWyepqCheKqCluC92AJegwqd9+0Y2Wo0GBB5i/wCFTu2PsaOoydmV1iNsV+1ogd2i+NY15jhBDVN7HPkQ8Jcap6PP94mC555RZYtzT6g0K1bNzugMG3aNCGgEL2IvCGAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAJlIkBQoUwuJKeBAAII5FugMEEFdRbqlinzLmvdpt6tV7ogQsp+NVjfjqWOfT5RwRFUUOPVjVrmje6qLZtXqvkS2l1oYmunqUmYLzYofpCuP17p4yjNnuyZvNS4LJmLfTebI92e0vQ3m89l/166Us2X0J5mT16sE+bzsrFc1ORg3+m24Tyvr7Z+bYUUXpfwzm/TDY31X3755XLbbbeJ+hfaeQVfoFyCCp/v/EyeWTBPNlpPUijWSwUWRg4fLf82Zryo40K+Ro0aJW+99VZWS/JUhaz4GJxDAS9BhatmTJNOnTuoxEBsZfso+iUWTrA+x0vUT7noyxFUiPWo+mhVfJyaIzIy5Xt0WhVQmG8FFJYvW531ExS6d+8uV199tUydOlVCoZDeOe8IIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAmUkQFChjC4mp4IAAgjkU8BbUGGEDKu1nqgQu/PJuvNY33xs3/+kb58y2tNtOmGcVZwqiBBbR6/hqNXrGN2L7loiS+cu1z0p39t3by/jnUEFvV7KUdl1qACEvpHMdSbjfOy6ZPsya5L1uy7gvVOHNnzvO9WeSnHf5p4VXapz886aspLvEYvG9PZpvXPjF7Lwv9+Qhq/3pDR2dtxwww3yu9/9ztnM5wALlENQ4cO1K+Xxp+dKQ8PuQEh373aA1E64SDp06FSQ/eTiaQp6ozxVQUvwXkyBrIIKauM6hKB+31b/xX4Wxn8D04GDSHmsIBZIiE6j3uyXrlfv+lh16OMtmz+RBc++Iive/yAnAYUZM2bIlClTCChE+PmKAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIlK0AQYWyvbScGAIIIJBbgcyCCtYeEoIF0RulzDYv24zfgeWYLzrYvEE5Va25TnQbvoMKag411lzPnDdHx/qGfzVd/JYzl8n1/Wep9pWu32VqP10Z7TvVntXCBd53TqwLtO+MrNXe0nm79avxWb4y2rfbnjL8Hvl05XZ5489vy/e7v/d0RupGzT/96U/yi1/8wlM9RcERKO2gQpO8svA5efWNFyxQt78IhfcOhWrkzNPPl359BuR98Vw8TUFvkqcqaAneiyngJajwqxlTpXPnjtHfhRy/oagwgToB9Tuv+i/ywT4l+9Duih7pBv0bpfVZzxYZZ08UnUPNZfXGO0QFFJ5TAYXlH2YdUOjRo4eogMJll11GQMG+WnxBAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAIP8C33zzjbz//vvNFjrwwANF/eGFQL4FCCrkW5j5EUAAgTIRyCio4Awk6Jul/N5vaY+LDjbnTDZf7OYqa5FU60THZRRUKND11Dd065vJCrRs1suU8r6xzvrye5qg2N8jWxZ9LG/fsUgav2/0tN9WrVrJ7Nmz5YILLvBUT1GwBEo1qKCenjDvyYdk7frVwQI1dqNuZh475iQ59ph/s1r1D2SjIAeHzz33nIwbNy4HM8Wn+OlPfyqPPPJIvIEjBAos4Deo0Oz3E+uvm92m/trZwQJ1ApG/g/pvoh020B+M89MhBD1ez61/fVb96s/mj7bKc/94RVYuX5N1QKFnz56xgELbtm2N3XCIAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAL5Fnj33Xfl6KOPbrbMTTfdJDNnzmzWTgMCuRYgqJBrUeZDAAEEylTAW1DhSBk2abAVEEiRENA3TDm79d1RCXZGkXGobsiKvKxG3W43RdvNtXVpwrzWh+i4RXcvkaVzlzt7m31u3729jP9fJ9jtTeb8zSrV/WLxRXWt2eYcEqsxb/KMTxG7OczLHObcZr19Y7i2Mouix2ataortyTgXc5juV236Bjdz++Z6zrn1PGaNbtM3zenP5jq6zXw35zZrzXazXtfE9qw6k1jbzR7OXc/tXE+vo/ud72a9rjXbnPWxGnOzSfbtZQ5zbrM+2fVIVavaY3vy4BTzNvbsaQ71FzXJ923Cvn3+fdzwar0suX+pNDUmmdg84ehxKBSyb2g+9dRTk/TSVAoCpRhU+O6772TOQ3+Rrds2Z0Ss/o5069rTftrBfvt2lZqadtKuZh/rXzCvsefbvXu37Ap/Lbt2fSPbd2yTdRs+lE+3b81oLTXohyPHyLgfn57xeLeBuXyagl5HPVVh2bJlMniw9fsKLwSKIJB9UMH6yap/ploH9mG0QTergliNcY76Z6g9yiqOjo7V2k9Q+MersmpF9gGFAw44wA4oXHrppUJAwbgIHCKAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCBQQAGCCgXEZqmkAgQVkrLQiAACCCDgFMhfUMG+S8q5nPXZuJHYOIzdSeW8QVnfjWW2x+7Wckwfnc9XUOGWE6wdmRtxzBn9qG/80jdy6yp9Y5j+rKYy59M3itn9et/WuZgrNpvDKnauo+fX+3Cuo/ud7/bcjj2pmmZrOmqS7du5p2ZzWPM6a/R+9L5T9es69a5rneeYbr2EPUcmsqc114zNbfdEvpj9RrN9mMrPWac+67md8zXbtwdrv+du7kfvwzmHWWMepzrHTPad9tythZ01ei9636n6dZ1617XqHFc/86Esn7dS/cXz9OrYsaM8+eSTcuyxx3qqpyiYAqUWVFDf1488fp98sGaFb9ABBx8mQwePkL4H9Y+FErxO8vU3X8l6K7Dwz6Vvy5atm7wOi9WdfOIEGTl8dOxzLg7y8TQFvS+eqqAleC+GgKegwtVTpdO+Ha2fY9ZLhQ7s99iX6K/DVmvkP7tG9apX8zGRdrsv+vuymjFyaFfLFvUEhfmvyuqVa1P+/I3P4n6kAgrXXHONqIBCmzZt3IvpRQABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQACBvAoQVMgrL5N7ECCo4AGJEgQQQAABkZwFFVLdJBy9cSpi7SgyP6o6M4zgdnEi914lVhhz+QkqnHTLTxLnsT5FbxtLaE+MFiR0uX5wzpXpPK6LRDtzuVZWc6lrkewapTiJtGt5nM85j1ouX965XMs5V772rDyca2Vj5JzL1749XlO1P/VKupY1x7JHVsia+WsjRR6+duvWTebPny/Dhg3zUE1JkAVKLajw/MtPy5vvvOKLVAUUjv/RidK92wG+xqUqXrNulby8cL5s+9T7UxaqqlrIOWdNlv79Bqaa1nf76NGj5c033/Q9zssAnqrgRYmafAlkElRQvy/ZP+OivzeZP+9iv0LHDqxa6zj2K1ZsjHVGRruq+WjTx/L8P16T1au8/4xM5XLggQfKtddeK5dccgkBhVRItCOAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCBQYAGCCgUGZ7lmAgQVmpHQgAACCCCQTCDjoELspinrbmF103Emr9gc1mCvIQW1TppxXoMKaqpx/9MKKsTu+Eo4VN2xV9LtGePsQu1gtBuHiUxJamOL6YNUNUnazXX0cPVe8H3rvanFzU3pdrPNUaKGqJddqusjTZGv5ljdb7QZh3a9Lkn44CzS8+tiZ3+SdmdJbApdqxvUu7NY1xjtxiHfI0nMTB9N27i3URbf+57s3PiFbkr73rdvX1H/knu/fv3S1lIQfIFSCiosWfqOPDX/Uc+onTt1kYmnnys9u/fyPMZ7YZMsX/mePL1gnuzZ0+BpWOvWbWTyeT+Tbl17eqp3K8rn0xT0ujxVQUvwXmiBvAUV1IlYv/vaPw/1u90WOUOz3Q4ozH9NPli1LtKZxddevXrZAYXJkycTUMjCkaEIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAII5EOAoEI+VJnTjwBBBT9a1CKAAAIVLJB9UMHCS3o3vAfUWODAuntb38DtYVgugwpelqMGAQRKW2DIkCGyYMEC6d69e2mfCLuPCZRKUGHH55/K7bP/KI2NjbG9ux2oJxdMPO1cads25FaWdZ/a19zH7pWdX+zwNNcP2neQ6VNmSKtWrT3VpyrK59MU9Jo8VUFL8F5ogYyCCtYmY78OW1EE9TQE/TIOUwYV9PMVIgGFV+XD1ev18IzfDzrooFhAoXXr7P7OZ7wJBiKAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAgKsAQQVXHjoLIEBQoQDILIEAAgiUg4C3oMIIGVY72OV01U1VfpIGKaaK35vlY7rma/t5okKKndCMAAJlIqBujH7qqaekU6dOZXJGnIYSKJWgwtzH7pE161Z5umhjRp8gx//oxIQblT0NzLCooWG3zHvyIVm7frWnGdTejrP+ZPratm2b3HLLLZkO9zVu7NixMmHCBF9jKEYgW4GMgwp6YSuZEAknRH4hNoMKsQCDqonWq7ZN9VvkeesJCms+yD6g0Lt3bzugcPHFFwsBBX1ReEcAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAgmAIEFYJ5XSppVwQVKulqc64IIIBAFgI5CSroO6mcT1ZI1Z5sv/quK7sv+sE5X9JxxsBoPUGFZFC0IVB5AuPHj5fHHntMampqKu/ky/yMSyGoUP/Rernv4ds9XQkVAFBBgEK/mpoa5eFH77GDH+nWbt26jfx86jWyT7v26Uoz7t+1a5fMmjXLdfxxxx0no0aNcq2hE4FiCGQVVLB/nTWCCtbn2G+49nH0U/S4fuNmefG5hVZAYUPWp9qnT59YQKFVq1ZZz8cECCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCQfwGCCvk3ZgV3AYIK7j70IoAAAghEBcomqGCEGggq8O2NAALnnnuuzJkzR7jpsjy/F4IfVGiSu+bMkq3bNqe9AIMGHi5nnXGeVRe7LTntmFwWqCcr3PPgbbL9s21ppx1x+A/l1JPOSluXacH27dula9eursNvvvlmue6661xr6ESgGAJeggpXzZgmnTp3iG/PCvVGcr12AiH+fwHVrqqi/1uwP1nH9Rs2ywsLFsq6NRvjc2R4pAIK119/vVx44YX8rMzQkGEIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIFEuAoEKx5FlXCxBU0BK8I4AAAgi4CvgOKqi7qYxQgOvkqTpzMUequa12ggouOHQhUAEC06dPF3XDaIsWLSrgbCvzFIMeVFixeqnMe+LBtBenZ49ecvG5P5OWLVumrc1nwb+++lLuuu9W2bXra9dlqqpayOX/cZXs18U9TOA6iUsnQQUXHLoCL5BVUCGSVtC5BDugUBVtUydev3GLvLjgNSugUJ+1Q9++fe2AwgUXXEBAIWtNJkAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEECgOAIEFYrjzqpxAYIKcQuOEEAAAQRcBHwFFYwbpjIOK+RiDpfzUV0EFdIA0Y1AGQvcdNNNMnPmzDI+Q05NCQQ9qPBA3Z2yoX6N68Vq0aJapk+5Wjp13Ne1rlCda9atkrmP3ZN2uSOPOEZOGXdm2rpMCggqZKLGmKAIZBtUiD48IXI61u/L6vPGDR/Ji8+9LuvX1md9mv369YsFFIodjsr6ZJgAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAgQoXIKhQ4d8AATh9ggoBuAhsAQEEECgFgYyCCjxRoRQuLXtEoKIE1NMTZs2aJVdccUVFnXelnmyQgwoNDbvl97fOlMbGva6X58gjRlk3/E90rSl0530P3y71H613XfYH7TvI/7jiRteaTDsJKmQqx7ggCHgJKvxqxlTp3LljbLv2UxOsRIL59AT1OIVIQGGhbFi3KVab6cHBBx9sBxTOP//8oj+9JdNzYBwCCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCQKEFRI9OBT4QUIKhTenBURQACBkhTwFlQ4UobVDrbOr6lw56ievOAaiFD/zmzy/fBEhcJdJlZCIAgCrVq1kvvuu0/OOeecIGyHPRRAIMhBhRWr3pN5Tz7kqqC+Z6+cdp3s0669a12hO7du2yx3zZllLZv856vez9TJv5JuXXvojzl7J6iQM0omKoKA16BCp84drCiC+j02GlCwDnVQYcP6j+Ql6wkKG9ZvyvoM+vfvbwcUzjvvPAIKWWsyAQIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAALBEiCoEKzrUYm7IahQiVedc0YAAQQyEAhkUEGFFNQrZVAh2h8psr+aX7wEFdTNZOpGUV4IIFD6AkOHDpXRo0eX/olwBp4FghxUeOyJB2Xl6qWu5zLq6OPlhLGnutYUq/PRv98vqz5433X5sWNOkjGjfuJak0knQYVM1BgTFAGvQYVkT1SwAwrPvy4braBCtq8BAwbIDTfcYIf3WrZsme10jEcAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAgQAKEFQI4EWpsC0RVKiwC87pIoAAApkKeA8qDMp0Cf/j0gYV1JQqrJD8X3z2ElQIh8MSCoX8740RCCCAAAJFFwhqUKGxca/8/taZ0tCw29Xo0guvlJ49ernWFKtThRRUWMHt1bN7L7n0oivdSjLqI6iQERuDAiLgJahw1Yxpop6oYL+s33fXr6uXl59/Q+o3bs76LA455JBYQKG6ujrr+ZgAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQSCK0BQIbjXplJ2RlChUq4054kAAghkKeAtqDBChtUO9riSftpB8hCBx0myKiOokBUfgxFAAIHACwQ1qPD5zs/ktjv/y9WvJtROfn3lTVKlQ3mu1YXv3LOnwQpb/Eb27t3rsniVXHfVzdaTiVq71PjvIqjg34wRwRHwE1RYv26TvGQ9QWFT/ZasT+DQQw+1AwqTJk0SAgpZczIBAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAiUhQFChJC5TWW+SoEJZX15ODgEEEMidQG6DCjqkoPZHUCF3V4mZEEAAAQRMgaAGFTbWr5X76+4wt9rseMig4TLxtHObtQep4QHrHDZY5+L2+vnUa6Rzpy5uJb77CCr4JmNAgAS8BBXOmDhOli5ZmZOAwsCBA+2AQm1tLQGFAH0fsBUEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEECiFAUKEQyqzhJkBQwU2HPgQQQACBmEBugwpqWh1WIKgQQ+YAAQQQQCCnAkENKixbvlj+/kyd67mecUqtHD5kpGtNsTtff/slefGVZ123ccn50+XAA3q71vjtJKjgV4z6IAl4CSrkYr+HHXaYHVA4++yzCSjkApQ5EEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEChBAYIKJXjRymzLBBXK7IJyOggggEC+BHIdVGiK5hOqdF4hycZVjVt/kiG+mhbdvUSWzl3uOiYcDksoFHKtoRMBBBBAIJgCQQ0qLHzzBXnptfmuaBdOmip9evd3rSl25/sr/ymPPzXXdRtnT7hIBh4yxLXGbydBBb9i1AdJIN9BhUGDBsUCCi1atAjSqbMXBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBAosABBhQKDs1wzAYIKzUhoQAABBBBIJlDooIIOMqi95CusQFAh2ZWmDQEEECgfgaAGFZ5ZME8Wv/eWK/Tl/3GV7L9fd9eaYnduqF8rD9Td4bqNk0+cKCOHj3Kt8dtJUMGvGPVBEshXUGHw4MFy4403yllnnSUEFIJ0xdkLAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAsUTIKhQPHtWjggQVOA7AQEEEEDAk0A+ggrpAgg8UcHTpaEIAQQQQCCFQFCDCnXz7pUP165MsetI869/PlPatWvvWlPszu2ffSK3z/6j6zaOG32CHH/sONcav50EFfyKUR8kgVwHFYYMGWIHFM4880wCCkG60OwFAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAgQAIEFQIwEWo8C0QVKjwbwBOHwEEEPAqkGlQoSn6aISqdKkEjxvRT1pwTudnHT3H4tlLZOnc5a4rh8NhCYVCrjV0IoAAAggEUyCoQYWHH50ta9evdkW78er/sm46rnatKXbnzi92yJ/v+N+u2/jhyDEy7senu9b47SSo4FeM+iAJ5CqoMHToUDugMHHiRAIKQbrA7AUBBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQACBAAkQVAjQxajQrRBUqNALz2kjgAACfgWyDSqIVIkzXOB3D6pehwycc2USVFh09xJZVkdQIZPrwBgEEECgFASCGlSY98SDsmL1UlfC//zFb6Um1M61ptidH2/9SO6+f5brNsZaT1MYYz1VIZcvggq51GSuQgtkG1QYNmxYLKCQqyBwoQ1YDwEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEECiNAUKEwzqySWoCgQmobehBAAAEEDIHMgwrGJNahM2CQ2FuYTzrswBMVCuPNKggggECxBIIaVJj/whPyzuKFriw/u/TXsl+Xbq41xe78cO1KqZt3r+s2TjvppzL88KNda/x2ElTwK0Z9kAQyDSocfvjhdkBhwoQJ1u/TVUE6JfaCAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIBFSCoENALU0HbIqhQQRebU0UAAQSyEchVUEHtwcu9VTpM4LU+3bklm089UWHpXJ6okM6OfgQQQKBUBYIaVHj9rZfkxVefdWW98Jxp0uegg11rit25ZOk78tT8R123MenMyXJI/0GuNX47CSr4FaM+SAJ+gwpHHHGE/OY3v5EzzjiDgEKQLiR7QQABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQKAEBAgqlMBFKvMtElQo8wvM6SGAAAK5EiCokCtJ5kEAAQQQKJRAUIMK773/rjz57COuDP9+yiQZNuRI15pidz7/8tPy5juvuG7j0ouulJ7de7nW+O0kqOBXjPogCXgNKgwfPtwOKJx++ukEFIJ0AdkLAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAiUkQFChhC5WmW6VoEKZXlhOCwEEEMi1gN+ggn6CQZXaiP0luqMmEes/+5XqyQpqbGycUR8dlvCWao6EIvNDdD41jicqmDAcI4AAAuUnENSgwtr1q+XhR2e7gg8ZNFwmnnaua02xO/9y9x/ksx2fum7jl5dfLx06dHKt8dtJUMGvGPVBEkgXVBgxYoQdUDjttNMIKATpwrEXBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBEpQgKBCCV60MtsyQYUyu6CcDgIIIJAvAT9BBR1SUHtJFiRI1d9kdFQZA41ma8ZYzCF2qkap3abrne16gO5fPHuJLJ27XDcnfQ+HwxIKhZL20YgAAgggEGyBoAYVPt2+Vf56z3+74oVCNfKfV/42sDcqf/mvnXLr7be4nkN1dbVc+6ubpbq6pWud306CCn7FqA+SQKqgwpFHHmkHFE499dTA/r0PkiN7QQABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQACB9AIEFdIbUZFfAYIK+fVldgQQQKBsBAoTVFBckSBCpkEFHULQ8MnCCrpGPVFhWR1BBW3FOwIIIFBuAkENKqhg3v/5828lHP7GlfySC6bLgT17u9YUq3PRkjfk2eced12+b+8BcsGkKa41mXQSVMhEjTFBEXAGFUaOHGkHFE455RQCCkG5SOwDAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAgTIRIKhQJheyhE+DoEIJXzy2jgACCBRSwFNQ4bLhMrR2SMK2nEEBFRKoUhX2l4RS0QGCxNbmT2Vw1plrOPsiwYfExXS9CirwRAWnNp8RQACB8hEIalBBCf/96TpZtmKxK/ZRI34k40/4d9ea4nQ2yZ1zbpVPtm1xXX78CRPkqBGjXWsy6SSokIkaY4IioIMKRx11lMycOVNOPvnkoGyNfSCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAQJkJEFQoswtagqdDUKEELxpbRgABBIoh4D2oMNjaXjwYoEMBas/qX5BWL/NpCXZD9EvzkEGkw5xD15u1Zr/Zrp/OEJ1FD7XWjxwSVIiRcIAAAgiUpUCQgwqrPlgmj/79AVf36upqmT5lhnTs0Nm1rtCdK1cvlceeeDDtsr+8/Hrp0KFT2jq/BQQV/IpRHySBBQsWSGNjo4wfPz5I22IvCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCBQhgIEFcrwopbYKRFUKLELxnYRQACBYgl4DyqkfqJC4YMKSisSjkgWniCoUKzvJtZFAAEECiMQ5KBCQ8Nu+f2tM60blve6YgwZNFwmnnaua00hO9V+/+9df5CdX+xwXbbr/t1l2iVXudZk2klQIVM5xiGAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIVJIAQYVKutrBPFeCCsG8LuwKAQQQCJyAp6DClBEyrFY9USH+Mp9woJ9kYLbFK9WTFiKf4v0qZFAVa9e18X7V0pTwhIbEPj0i8u6cXwUVltUtTyxyfAqHwxIKhRytfEQAAQQQKAWBIAcVlN/9dXfIxvq1aSirZOrkX0q3rj3T1BWm+53FC2X+C0+kXWzM6BNk7LHj0tZlUkBQIRM1xiCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIVJoAQYVKu+LBO1+CCsG7JuwIAQQQCKRAIYMKCkA/fUEdV+mEgd2uWvQr8rSE1P26Lh6CUC06zEBQIe7DEQIIIFCOAkEPKmyoXyMP1N2Zlr5zpy5y6UVXSqhtTdrafBZs3lIv9839q+zd+73rMm3atJUrp10rNaF2rnWZdhJUyFSOcQgggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAAClSRAUKGSrnYwz5WgQjCvC7tCAAEEAieQSVBBBwL0yei8gbPd2a8/67CCDiI0H+c/qGDOQVBBS/OOAAIIlKdA0IMKSv3Bv90p6zeuSXsBevfqJxdMmiItWlSnrc1HwZdf7pS77p8l4fA3aaf/yfGnyOgfjk1bl2kBQYVM5RiHAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIFBJAt9//718+eWXzU65pqZG1B9eCORbgKBCvoWZHwEEECgTAb9BBTMQYD3DwKFQ5fgc+aiDDM5OHViwnouQ0KXrzbV0W0Kh9SFSk7iPRXe/J8vqljtLEz6Hw2EJhUIJbXxAAAEEECgNgVIIKmz7dKvcOedPCU8SSqV7+NCRcsbJtam689be0LBbZj/wZ/lsx6dp1+jYobNMn3K1VFe3TFubaQFBhUzlGIcAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCBROgKBC4axZCQEEEChpAT9BBTM40DykoBgSAwcaJnXIwAwYxMfqenM93abn1O/xsINuEYk8UWFFvCHJEUGFJCg0IYAAAiUiUApBBUX5+NNz5f0V//SkOuSwI+T0k8+Wli1bearPtujznZ9J3bx7Zcfn2z1NddYZ58uggYd7qs20iKBCpnKMQwABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEECidAUKFw1qyEAAIIlLSA16DC0LMHJzlPM2iguuNhA2exM2iQ+CSExHG61gwq2LMnlkWfpqB6EvdBUMGpz2cEEECgvARKJajwr6++lL/e80fZvftbTxegW9ceUjvxYlFPL8jna+361TLvyYdEPVHBy6tP7/5y4aSpXkqzqiGokBUfgxFAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAgYIIEFQoCDOLIIAAAqUv4CmocNlwGVo7JOFkdZjAbEz2dINIvyNhEAsWxNvN+RIDCjqEEK8110x2HAkqLE/WFWvjiQoxCg4QQACBkhMolaCCgq3ftE4e+Ntd0ti415NzKFQjp4w7UwYdOtSq9/6zz8vkKpjwxtsvy+tvv2SF/fTPV/eR+3XpKpecP13atg25F+agl6BCDhCZAgEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQyLMAQYU8AzM9AgggUC4C3oMK6okK8RsmzWCBtkh8SoJuVe/xcYlPP4i3x+az7ptMvHVSf4rXmjMnOyaokEyFNgQQQKB8BEopqKDUl76/SJ549m++LkDX/XvI2GPHySH9B/kal6z4u+++k3f/+bq88c7L8u234WQlSdv22ecHcumFV0qHH3RM2p/rRoIKuRZlPgQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAIPcCBBVyb8qMCCCAQFkKZBpUUBixcIF1HP+HmXWwQHMlCxiomubtar74PHq8nq95va5wvhNUcIrwGQEEECgvgVILKij9F199Vl5/6yXfF6J7t54y5LDhcnDfQ2S/Lt08j9+7d69s3rJR1m38UJYuXyy7dn3teawqbN26jUw+7wrp1rWHr3HZFBNUyEaPsQgggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAQGEECCoUxplVEEAAgZIX8BZUGCFDa9UTFfyHBjSQDjU0DyLoinRz635Vnzy0oNd4964lsqxuuZ446Xs4HJZQKJS0j0YEEEAAgWALeAkq9O7VT1q2bJW3E+l1YB859pgf+5i/SeY9+bCsWPWejzGJpe3bd5B+vQfIvp33k5qadtKuZh+prq62goMtpKFht+wKf2P/+WTbFqn/aL3s2dOQOIHHT8pt0pmTpV+fAR5H5KaMoEJuHJkFAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBDIpwBBhXzqMjcCCCBQRgKZBRUUQPKwQDIaHSBQfemDCqoq2dzegwrqiQpL5xJUUJK8EEAAgXIU8BJUyPd5DzxkqJw94UKfyzTJq68/L69Yf+LhP59T5Lm8c6cu9nl13b9wT1LQp0RQQUvwjgACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIBFeAoEJwrw07QwABBAIl4C+ooLauAwPJwgSpT02FFVKHFMx51XGyufW6qfpVuzXSGsoTFSIWfEUAAQTKVaB0gwqRK7Jm3Sr5f089bD8FIUjXaOAhQ+SMk2ulTZu2RdkWQYWisLMoAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCDgS4Cggi8uihFAAIHKFfAfVNBWOjjgDBXodl3n9m6ONccla0/W5pw7UqOeqLCsjicqOHX4jAACCJSLQKkHFdR12PnFDqmbN0c+27Gt6JelRYsW8pPjT5FjjjquqHshqFBUfhZHAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQ8CRBU8MREEQIIIIBAZkEFM1SgDL2ECJJZpxqn2811dJuax2w3543UEFQwTThGAAEEyk+gHIIK6qp8990eeevdV+WtRa/J7t3fFuFCVcmhAwbJcaNPlG5dexRh/cQlCSokevAJAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBAIogBBhSBeFfaEAAIIBFDAf1AhWUjADBGok0xWk83JO+fXcyVbp0oIKmgf3hFAAIHyFCiXoIK+Og0Nu+3AwtuLF4o6zverqqpKDjt0mIwZ9WPZf7/u+V7O8/wEFTxTUYgAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCBRNgKBC0ehZGAEEECgtAT9BhaamSDDAjg0kZAcSPvgAMIMG5hy63WzzMm1k3KK735NldctdB4TDYQmFQq41dCKAAAIIBFOg3IIKWlk9VUE9XWHFqvdk5xc7dHPO3vfZ5wcyoN9AOeao46TLvvvnbN5cTURQIVeSzIMAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCORPgKBC/myZGQEEECgrgYyCCs3yA80aPBqlCiSkak83rQ4qLLGCCitciwkquPLQiQACCARaYNPmDTLnob8UdY8jh4+Wk0+ckLc9fPmvnbJ+4xrrz4eycdM6USEGv682bdpK7179pM9B/aVv7/6yX5eufqcoaD1BhYJysxgCCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIJCRAEGFjNgYhAACCFSegJ+gQmodHSxwqbBKqqq8Bhr0fIn16okOyefQ9SLqoQ+LZxNUSH0l6EEAAQQQKDWBpqZG+XznDtkV/kbC1h/1viu8yz7e890eadsmJDU17aQm1E7a1exjv6vP+3buYv3cbFEyp0tQoWQuFRtFAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAgQoWIKhQwRefU0cAAQT8COQ6qKCCAuplZhJ0W6Q9MXxgFzu+qECCs1a3OdutaEJstF6HoEKMhAMEEEAAAQRKRoCgQslcKjaKAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAhUsQFChgi8+p44AAgj4EShEUEHtR4cIkj8RIXHHOpRg1uo2VWm2E1RItOMTAggggAACpSpAUKFUrxz7RgABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAIFKEiCoUElXm3NFAAEEshDwFlQYLkNrB9urqMCB+bSEyNLpn5Kgt2gGDnRbYvBAt6pwQ/xpCWaNbo/so/nai+5eIsvqlscnSnIUDoclFAol6aEJAQQQQAABBIohQFChGOqsiQACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAII+BMgqODPi2oEEECgYgX8BBWM3IAjrNA8LJAKVIcMnP1mEEH3mbVmf6p2PY6ggpbgHQEEEEAAgdIRIKhQOteKnSKAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIBA5Qr8fwAAAP//bAAF/gAAQABJREFU7N0HnBNl/sfx3xbKUpbeXFBBBRVYAWkiBycqineWs4AioiDYBQGxnF1PxYL8RcVOEeWAA++wUhRRQAHpzYJ0UKQuLbuU3f3Pk2V2J5lJMsmmTJLP3AuTedo8836y3PJ6zTdPSqF2CAcCCCCAAAIBBH7//XfJysry26pt/1aS3aOZGP+fJSXF2MXjxFhh8b7QYxy9QYrngO5i4/+VFVXr1ykaw7NMH0nkx/eWyoqJq0oKLN65XC7JyMiwqKEIAQQQQAABBGIhsHPnTqlTp47fSz/77LPyz3/+028bKhFAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQiJ5BCUCFyuIyMAAIIJJKAnaBCm35FQYWSYEBJ2KCkrEjFGC5QJUX1RrGisIG5nR5CEC3IYM7amcfRxyzpp5cQVNAleEUAAQQQQCB+BAgqxM9aMVMEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQSF4BggrJu/bcOQIIIBCUQHBBhZJQgDFMoO+GYCwzTsIzZOB/DNXPahzPMTxGN5643xNUMJFQgAACCCCAgOMFCCo4fomYIAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAgggIAQV+BAggAACCNgSiGVQQYskaKGEomkWBRGKQgwEFWwtHY0QQAABBBBIKAGCCgm1nNwMAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCSoAEGFBF1YbgsBBBAIt4CdoELb/udKdo9mHjsd6LsoqPlYBQtUud5GrzeGEVS9Cirohx5YUOd6P71OvepjqPee45SEHVSdOha/v1RWTFxddOLjvy6XSzIyMnzUUowAAggggAAC0RYgqBBtca6HAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggEL0BQIXgzeiCAAAJJKRCpoIIxbOAZMijaNaEIO9SgQskYxrH1BSSooEvwigACCCCAQPwIEFSIn7VipggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCQvAIEFZJ37blzBBBAICgBu0GF5t2bmsbVwwhWYQE7db52VFAX0vvrF/W+hl7vXa7aE1TQ1XhFAAEEEEAgfgQIKsTPWjFTBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEheAYIKybv23DkCCCAQlICdoEKbfq0ku0czn+PqoQFjA6sAgbE+xb0pgr4zQqEUlmyuUNzMOK6v8fQ2xnqCCsWEvEEAAQQQQCBuBAgqxM1SMVEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQSGIBggpJvPjcOgIIIBCMQKyCCmqOeshAvTcGDdS5fuhtAtWr9nobggq6Hq8IIIAAAgjEjwBBhfhZK2aKAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAskrQFAhedeeO0cAAQSCEohEUEEPDNiZSKAgghpDtfE1pt5ftdPbEFRQGhwIIIAAAgjElwBBhfhaL2aLAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAskpQFAhOdedu0YAAQSCFggmqGAMBRgvpAcEjGXe7/W+vtrarVfjGsfQ+xnLCSp463OOAAIIIICA8wUIKjh/jZghAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCBAUIHPAAIIIICALYHSBhWMoQFfF7QKE3i31dv4G8+qjV6mxtP7ElTw1uUcAQQQQAAB5wsQVHD+GjFDBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEECAoAKfAQQQQAABWwLBBBXUgCna//SjUAr1t6V+VePaGc+7nfe5mghBhVIvBwMggAACCCAQdQGCClEn54IIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggEDQAgQVgiajAwIIIJCcAsEGFQIp6Tsc6Lsb+Guvt1Vt7LTXxwrUj6CCLsUrAggggAAC8SNAUCF+1oqZIoAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggEDyChBUSN61584RQACBoAScEFQodG/MENzuDHpYwSrgQFAhqI8AjRFAAAEEEHCEAEEFRywDk0AAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQcLjAxo0b5ZlnnjHN8sorrxT1hwOBSAsQVIi0MOMjgAACCSIQbFAhRVKkUPtf+I8UbchwjJsii99fIismrvY7RZfLJRkZGX7bUIkAAggggAAC0RMgqBA9a66EAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIBC/AosWLZJ27dqZbuDJJ5+UJ554wlROAQLhFiCoEG5RxkMAAQQSVCCYoIIKKehH+MMK+tieYQV/Oyfocyl5LRqjaEeFVSXFFu8IKligUIQAAggggEAMBQgqxBCfSyOAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIxI0AQYW4WaqEnShBhYRdWm4MAQQQCK9AKEGF8IcU1D0RVAjvyjIaAggggAAC8SVAUCG+1ovZIoAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAgjERoCgQmzcuWqJAEGFEgveIYAAAgj4EbATVGjb71zJ7tFMwhVQUDszlHYsf2MU7aiw2s9di7Cjgl8eKhFAAAEEEIi6AEGFqJNzQQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQACBOBQgqBCHi5ZgUyaokGALyu0ggAACkRIIR1BBhQbUYSd8oLe12949sNd/Ao1BUMELjFMEEEAAAQTiQICgQhwsElNEAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEIi5AEGFmC9B0k+AoELSfwQAQAABBOwJ2A0qNO/R1OeAenDATlBBDaLa223r66L+xiCo4EuNcgQQQAABBJwrQFDBuWvDzBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEnCNAUME5a5GsMyGokKwrz30jgAACQQrYCSq06ddKsns08z1y4Ymqoo0Vitv5CxMUNzK8Caq9uqbX9fShCCroErwigAACCCAQPwIEFeJnrZgpAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggEDsBAgqxM6eKxcJEFTgk4AAAgggYEvAdlChuxZU8BEM0LZHKDoM9Sp0oB92dk8Iqr1+PXWBksvolxOCCsUUvEEAAQQQQCBuBAgqxM1SMVEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAgRgKEFSIIT6XdgsQVOCDgAACCCBgS8B2UCHCOyroQQU7oQb3jbGjgq31pRECCCCAAALxIkBQIV5WinkigAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCMRSgKBCLPW5thIgqMDnAAEEEEDAlkBYggq2rmRo5Cdk4G6l75hgsVuCYRTDW9VQ7yTsqGCQ4S0CCCCAAALxIkBQIV5WinkigAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCMRSgKBCLPW5thIgqMDnAAEEEEDAlkDUgwoleQLt/618TFFv46veo5uxUVHHxe8vlRUTV3u08j5xuVySkZHhXcw5AggggAACCMRIgKBCjOC5LAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIBAXAkQVIir5UrIyRJUSMhl5aYQQACB8AtEPaigbsFOEEG1MWYQ/N66aqgPyo4KfqmoRAABBBBAwKECBBUcujBMCwEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEDAUQIEFRy1HEk5GYIKSbns3DQCCCAQvEDIQYWSXEDJRW0HC0500cew3U9vqHfUxjG81SeyeDQ7KugWvCKAAAIIIBAvAgQV4mWlmCcCIq7cw5Keli5ly5ZzBEdBQb7k5rokNTVNypUrr72mOmJediaRm+eSgoICqZBRQVJS4mfedu4tkm3Umufn50taWpp73SN5rWDGLiws0H4+XJKmfRbLl2cHv2DsaIsAAggggAACCCCAAAIIIIAAAggggAACCCCAAAL2BQgq2LeiZWQECCpExpVREUAAgYQTcERQQanqGQSfwsYGhnSC4a3elaCCLsErAggggAAC8SNAUCF+1ipxZ1oo07+aJocPH4r5LXa98AqpXCnTYx5fzvqf9mD2cY+y0p40O7ulnHryaX6H2b3nT/n51zWye8/Ooj97d8qRI3nuPpUqVpYa1WtJ9eo1pWb12qLGy6xcxe94palUD6Zv3bZRftv4i2zbvlkOHT4oh12HJC8v12NYFaBQc6tTu57UqVVP6tbJct+nCjHE8lAP169b/7P8un6tbNz0mxw4mON+2L5oTilSoUJFqX/SyXLGaWdK07NaSEb5CrGcbsBrf79wjuzdt9ujnQqJdO7YVSpWqORRXtoTFQD4+dfVsnTFItm5e4ccPLhfCymku/2qVKkqJ9VtIO1ad5ST6zcs7aVs9VdruVX7DK7f8Iv2uqn4s5ibqz6LRf9ILVOmrPvnoUpmNamSWVUytT/Vq9WQ0xo2CbuPrUnTCAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBJGgKBCwixl3N4IQYW4XTomjgACCERXIOSggpqmRUggcODgxP159zXmEHwSqEZeHb1OVVeCCj4BqUAAAQRiKjBt2jQZMGBATOfAxZ0roB5A3r59u98JVq2qHvT0fHjbbwcqHS8wY8YMOfPMMx0xT/Ug9NMvPBDzuTQ89Qy5qcdt2rfre/6C/Pwrj8jRo0fCOr9uF/9D2p57vuWYKowwZ95MWbRknvsb/y0beRWqb7c/p1lr6XheF6lWtYZXbeinW7dtkvkLv5ENm9bJsWNHQxpIPUDfQHuI/YxGZ8pZTZprD4zXDGmcUDqpv9+Wr1okc3+YLfv377M1hApVnN/+AunQtrP7gXxbnaLcaOxHo2Tz1g2mq17W9R/SppX158rU2EaBWvdPvpgk+w/kBGytggrXXNkrYoGZbb9vFhXQWL/x15B/HtXPdla9k6XJGU2luRbuqVKlWsD7ogECCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAgggYBQgqGDU4H0sBAgqxEKdayKAAAJxKGA7qNC9WeBdDyxCA24SwzNWhYY2hmLfY+vtPRoboPV6VXSizeL3l8qKiasNjcxvXS6XZGRkmCsoQQABBBCImMC///1v6dmzZ8TGZ2AEEIg/gRUrVkh2drYjJu6EoEIF7Vvo7+w7WCp57aaggKIZVFi5eonMnP2pe7eCUBYnJSVVmp11jlz5tx6lesh++x9b5JvvZmgPhf8SyjT89jlF20miZXYbObvJOVKmTBm/bUtTuXPXHzL1k49k564dIQ3TIOtUuf6aW7TdFsK7Q0FIk/HqFI2gwg+LvpVZ33wu6ufT7qF207j+2j7uMIDdPoHa/b5jq8yZO1PbEeOnQE2DrE+RRlo4qdU5beXMxs1K9fMS5IVpjgACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAnEsQFAhjhcvQaZOUCFBFpLbQAABBCItQFAh0sKMjwACCCCgCxBU0CV4RQABXYCggi6hXlOk53V95YzTzjIWFr+PVlDh519Xy6SPxxZftzRvhg58SipkVAx6iOPHj8vnM6ZquxD8GHTfYDuoh8Rvuv72YLvZar/25xXy8af/lvz847ba+2qkdqfo1/tex4UVIh1UmL/gG/lqzue+WPyWlylTVm67ZaDUrFHHb7tAlWrtvpj1X1m6fGGgpqWur5JZVe6769FSj8MACCCAAAIIIIAAAggggAACCCCAAAIIIIAAAgggkPgCBBUSf42dfocEFZy+QswPAQQQcIhAxIMK3jshaDsgqE0QvIvNBQYgfdcEUydDG8NbdlQwYPAWAQQQcJAAQQUHLQZTQcAhAgQVShaifZtOcsmFV5QUeL2LRlBhX84eeXvMCDlyJM/r6qGdhhJU2L9/n0z671j5Y8f20C4aZK9TtZ0Vbu55Z5C97DWf/tX/ZOHiefYaB2h16imnS+/rbxO1W4VTjkgGFTZu/k3GT3wnqJ0UvF1q1awj/W8eqO2YUda7ytb5wYP7tdDOOFE7e0TjKFeuvDw06F/RuBTXQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAgTgXIKgQ5wuYANMnqJAAi8gtIIAAAtEQsB1U6NFMe0ikaEYp3oGBYIIEels1lHEcvdxYZgTQ6gvdEQetm2kCxoYiBBU8PThDAAEEnCJAUMEpK8E8EHCOgNOCCsNfezoiOPkF+ZKXl+tz7Hp168utN90raWlpPtv4CyqkpaX77OerIjU1VW7s3k9OadDI3aRQ+2X/3XH/5zcgkKl943vtmnUls3IVUbseHDiYI9t+36K9P2Z5mWCDCpu2rJfJ/x0nubkuy/F8FZYpU8a920Cq9hC/cs51W+v/wPDVq6g8XoIKarYqyKICLU45IhVUUOv/+rsvist1yOetpqenS8WKleXAgf1+wwytzmknl3e7zuc4viq2bd8sE7WdRQ4fPuiriUd5Ze1nol6dLG1OlaRiRiUpKCzQPocu92d5956dsnvPLq29/89kOIMKGzat85ifOqlTq67bzFRBAQIIIIAAAggggAACCCCAAAIIIIAAAggggAACCMSdAEGFuFuyhJswQYWEW1JuCAEEEIiMQEhBBTUVY6BAf97CWOZrunpbX2N4l+vjaP0IKugYvCKAAALxKUBQIT7XjVkjEEkBJwUVInmfs7/9Uub+8LXlJcqWLSe39xkk1avVtKzXC30FFVTAoX7WKXqzkF/VDgbvjB1h2b+WFk74a8euclaT5qbQ8LFjR2Xd+p9k0ZL5snnrBo/+wQQVdvz5u4z56A05evSIxxhWJ/XqZslpDZu4/2TVa2D6xnwVulC7Q2z7fbNs275FVABi1+4dVkNJLIIK9U86Rc5t0V5qaw+OV8ioKHtzdsufO/+QRUvnS07OXst5qkL1YP7AO/6p3W8Zn22iWRGpoMJXcz6X+Qu+sbwVFQi4+IK/S7OzWrg/i+rzon625i+YYxlYUCH3u/rdLzVr1LEcz6pwz95d8t4HI/2Gi1S/SpUypW2rDtL49LOlTu2TrIYqLlMBGvV53Lxlg6z6aZmonUO8j3AGFZ4adr/38HLNlb3cbqYKChBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQCDuBAgqxN2SJdyECSok3JJyQwgggEBkBGwHFbo3sw4nqGnpAQVjCMFruqpKb1ZcZSzw09fd3k9bFWBIMYy+ePRSWTFxdfFlrN64XC7JyMiwqqIMAQQQQCBCAgQVIgTLsAjEsUAyBBU2at9sPn7SO9pD1Na/8P7j7zdIdrNzA65ipIMKPyz6VmbO/tQ0j9q16kmfG++S8uUD/+780y8rZYY2hv4Qtt2gwoEDOe4Hww8eOmC6vrHg1FNOdwcm9F0gjHWB3qsgwMo1S2TVmqVivE40gwrqYfnLu10rJ9dvaDld9dD99K+nybIViyzrVeFVf7tezmne2md9NCsiEVQ4pO1gMPKt5+TYMfMuHWonjz697paqVaqbbnPpioXy6Zf/MZWrgqZaqOFa7SF9O4cr97C8N26kO+jiq70KFHRs30Xatf5LiKGRQndgYcWJz6PanUQdBBV8iVOOAAIIIIAAAggggAACCCCAAAIIIIAAAggggAAC3gIEFbxFOI+2AEGFaItzPQQQQCBOBaIRVDA+kmXMGxiyBcUPbhkDBx6kxo6GAfVdFlRbvS9BBQ85ThBAAAHHCBBUcMxSMBEEHCOQ6EEFl+uQvDn6FTnk4wH8c5q1lqv+fr2t9Yh0UGHCf95374zgPRn1bfRqRwW7R26eSyb/9wPZtPk3sRNUOH78mLyrPRi+c9cfPi+hQhIq0KG+ub60R0FBgTuw8N38r9wPo0crqKB2ALjisu6m3R+s7ueTLybLspXWYYXmZ7eUq6+40apb1MsiEVSY9c1n8v3COZb30rfXPdKg/qmWdarw408nuIMo5gYpcs9tD0iN6rXMVYYS9dkYO2GUbN22yVDq+VbtgnHDNX2lalVzWMKzpb0zFZqZp+0IsWT5QklPT5eHBv3LXscArdhRIQAQ1QgggAACCCCAAAIIIIAAAggggAACCCCAAAIIxLkAQYU4X8AEmD5BhQRYRG4BAQQQiIZASEEFQ1DAPUc9ROBdbrgBvUpv6tFPO9G/YVYPGxi6Fr01dtQHU/20/6nD2I+ggpuE/yCAAAKOE7ATVOjUqZNUrx6eh/8cB8CEbAvMmTNHcnJyPNqrBzj//ve/e5Rx4myBTZs2yfLly/1OMrGDCoXy0eT35bcNP1saVK9WU27vM0jKli1nWe9dGOmgwksjnxQVrDAeKiDw4H3PGItsvVcPfKuHzdu17hjwwfxv582UOdofX0ed2vWkx9W3SLWqNXw1CalczXHF6sXu+akQQSSO6V/9TxYunietW3aQv11yte1LqG/1f+3tYZKXl2vqo3YVGHT3Y6byWBSEP6hQKCNGPStqhw3vw05AY7/WT7nl5xftUGAc468du0pn7Y+/Y/GyH+TzGVN9NlFBmWu0kIjdn1mfA1lUqHte/dNy6dDurxa1wRcRVAjejB4IIIAAAggggAACCCCAAAIIIIAAAggggAACCMSTAEGFeFqtxJwrQYXEXFfuCgEEEAi7gO2gQo9mKhXgDgYYQwF+J2QMF6iGhoCBqZ/e1ruNr3LTACUFBBVKLHiHAAIIOEnATlBh/vz50qFDBydNm7nEQOCqq66SadOmma68f/9+yczMNJVT4EyBd999V2677Ta/k0vkoMIPi76VmbM/tbz/tLQ0ufWme6Ve3fqW9VaFkQ4qPDf8n3Ls2FGPS5cpU0YeHvycpKTov5R7VJf65MDB/fL6O8O06x6zHKt2rXqa0z0ReTDc8oJhLlRBhb379sgN1/bRDFODGn3O3Bny7fxZpj5qnMcffEErj8yamC7opyDcQYXtv2+R9z4YaXnF3jfcIQ1POd2yzlj40eT3LMNB6rN0561DjE093h89ekRGvvW8HPYK6+iNTm7QUHpff4eon914OAgqxMMqMUcEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBEIXIKgQuh09wyNAUCE8joyCAAIIJLxAMEEFfdcDhRIwrODruRnvIIIurLf3rvdVrvezeCWoYIFCEQIIIOAAAYIKDliEOJmCerhdPeTufaxfv14aNWrkXcy5QwWSOajw+46tMnr869o3u+dbrs4lF14h7dt0sqzzVRjpoIJ6SHtfzh7T5a+/po80OaOpqTwcBR9/OkFWrVlqOVSlSpnSv/cALZxU1bI+Hgp37d4hVTKrhRS0+OmXVTL5v+Msb/OB+56WjPIVLOuiWRjuoMKsbz5z78ThfQ9qZ4+hA56S1NTAYY9FS+bJl7P+5z2E+/ze2x8StZOJ1TH7u+ky9/uvrKqkatXq0v/mgVIho6JlvRMLCSo4cVWYEwIIIIAAAggggAACCCCAAAIIIIAAAggggAAC4RMgqBA+S0YKTYCgQmhu9EIAAQSSTsB2UKF7M/duCgooYEhBV9RDBvq5dwhBL1evelvvNr7KjX293hNU8ALhFAEEEHCIAEEFhyxEHExj6NCh8vLLL5tmunz5cjnnnHNM5RQ4UyBZgwrqm9nfHjNC+yb93ZYLc8ZpZ0nP6/pqdfovupbNTIWRDir4+ib6qlWqu7+JvmzZcqY5labAlXtYXh75lBQWFlgO0+fGu0V9i32yHirkMOo989+DymPwPY9LZS3IEesj3EGF0R++Llu3bTLdVrOzWsg1V/YylVsVqJ+7194eZlUlV17WQ1pktzHVFRTky0sjn5S8vFxTnSro00v7LNaPr88iQQXLpaQQAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAIGEESCokDBLGbc3QlAhbpeOiSOAAALRFQgmqGCamXq2SgsWeGYLis68wwyFWivvMvd4+vNZhkFUW3V4t/cY48S13Q0N/1FtloxeJismrjaUmt+6XC7JyMgwV1CCAAIIIBAxAYIKEaNNuIEff/xxeeaZZ0z3tWDBAmnXrp2pnAJnCiRrUCHQLgF39h0sFSpUCnrRIh1UmPH1NFnw41zLeZ1Ut4H06tFf+/05fN/iv3TFQvn0y/9YXu+sJtnS/R+9LeuSpTBn/1559c3nLG/3kfuHSXp6umVdNAvDHVQYNuJROXIkz3QL11xxozQ7u6Wp3FeBCipYBYXOa9tZuna53NRtw6Z1Mn7i26ZyVaB2E1G7isTbQVAh3laM+SKAAAIIIIAAAggggAACCCCAAAIIIIAAAgggEJwAQYXgvGgdfgGCCuE3ZUQEEEAgIQVCDiroAQNNpbA4ZFD8xiNkoAcPFKBH+MAwhjHtoLc3ttXL3GOkGDqWXFIbouhksRZUWElQQVFxIIAAAo4SIKjgqOVw9GSefPJJeeqpp0xznD9/vnTo0MFUToEzBZIxqLB81Y8y7fNJlguSov0Oe1OP26ThqWdY1gcqjHRQQX2D/5vvD9d+tzf8gm2YVM0ateXqy3tKvbr1DaWhv/1w0ruyfuMvpgFSUlLlntsekOrVaprqkqlg2/bN8v7410y3rHa2eHjws6byWBSEM6hw4ECOjBj1L8vbuH/Ak1IxiHDP5zOmyuJlP5jGanRqY7np+ttM5V/M/K/8uHS+qVwV3Hnr/VK7Vl3LOicXElRw8uowNwQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEESi9AUKH0hoxQOgGCCqXzozcCCCCQNAIhBxWU0Im8gOezTEUPNhlDBqqpHiLwLneP4fUslK+2HuV6VsGiLzsqKHEOBBBAwHkCBBWctyZOndEjjzwizz1n/ibxhQsXStu2bZ06beblJZBsQYU9e3fJ22NGyLFjR70kik47ntdFLux8mWWdncJIBxXUHKb8b7ys+XmFz+mkpqbK+e0ukM4dL5a0tNC/0f/48WPy/CuPSkFBvulapzRoJLfceJepPNkK1IP26oF77yPrpJOlX+8B3sUxOQ9nUOG3DT/LR5PfM92HCq48/uALWrn+D0BTE1PBd99/Jd98N91UXrlSpgy+53FTuQpIqKCE91G7Vj0tqDDEuzguzgkqxMUyMUkEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBEIWIKgQMh0dwyRAUCFMkAyDAAIIJLpAsEEFlQswPSKiF3iFBqzs9LCBcRS9u1V7qzJ9DHfoQe9suPbi0UtlBTsqWNFRhgACCMRUgKBCTPnj6uL33XefvPrqq6Y5r1q1Spo1a2Yqp8CZAskUVMjPPy7vfTBSdvz5u+Vi1M86RfrceLeoB/1DPXwFFerVzZJy5TJCGrbduR3lzMYlP1P7cvbI+x+8Joddh/yOp3Y7uPSiK+WM087y285X5e49O+WNd1+0rL74gr9Lh3Z/taxLpkL10L56eN/7UDbKyAlHOIMKK1cvkf9+9m/TbamdFNSOCsEci5d9r4U8PjZ1SUtLk0eHqtBDyXHs2DF5bvjDJQWGdx3ba+Giv4YeLjIMFZa3ubkuOXIkz9ZYr75lDvt1u/gqaXza2bb6Z2RU0P5eKW+rLY0QQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAg+gIEFaJvzhU9BQgqeHpwhgACCCDgQyCYoIIhC+AZVrAIC/i4XPHOCkX1ekdjbMFXz5JyPaigSlJSSsbQBncfBBWKHPgvAggg4DQBggpOWxHnzqd3794yfvx40wS3bNkiDRo0MJVT4EyBZAoqfDnrf7JoyTzLhShfPkNu7zNIqlapbllvt9BXUMFuf6t23S7+h7Q993yPqj93/iFjJ4ySvLxcj3Krk8ann+0OLFSrWsOq2mfZ+o2/yIeT3rWsV99gr77JPpkP9UD68NefFhWA8T56XndryAER77FKex7OoMKPS7+XL2aawwW1ataRu/oNDWqqa35aLlOmfWjZ59Ghwzx2A1E7obz+jmd4Qe/Y+/rbpeGpZ+inMX3NzXPJq28+ZzuoUNrJqoCGCmpwIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAgDMFCCo4c12SaVYEFZJptblXBBBAoBQCYQkqqOurvIAxyeBnTiVBg5KQQck7Px0NVWoM944Kqszr2gQVDFC8RQABBBwkQFDBQYvh8KlcfPHF8tVXX5lmmZubK+XL8w3PJhiHFiRLUOGXdWtk4tQxPlfhuqtukrPPPMdnvd2KaAUV1Hy2/7FFJkx+X1y5hwNOLy0t3b0DQqcOF0l6enrA9qrBkuU/yGfTp1q2fXjws1K2bDnLumQp/GrO5zJ/wTem261UKVMG3fVoqXbmMA1aioJwBhXmLZgtX8/5wjSbUxo0kltuvMtU7q9gw6Z1Mn7i25ZNhg58SipkVCyu26i1/cBH23tue1BqVK9V3DaWb/bv3yf/9+azUZsCQYWoUXMhBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQRCEiCoEBIbncIoQFAhjJgMhQACCCSygN2gQvPuzTx2UdDDBsVhgRNIerlxjwSrEEJRpkFPNniPUiKuj+e7RUlb/R1BBV2CVwQQQMBZAgQVnLUeTp5N48aNZd26dR5TrFGjhuzevdujjBNnCyRDUOHAwf3y1ujhor4B3+po1aKdXH7pdVZVQZdFM6igJnfo0AH53+cTZf3GX23NtWaNOnLDtX2kerWaAdt/O2+mzNH+eB/p6WXkkfuf9y5OqvNDhw/KyLeek2PHjpnu+y/nXShdOnczlceqIJxBhdnffilzf/jadCtnNm4mPa6+xVTur2DHn9vl7TEjLJsMuONhMe4AsmL1YvnfZxMt2z543zNaOC7Dsi7ahQQVoi3O9RBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQcLYAQQVnr08yzI6gQjKsMveIAAIIhEHAflChackOBtp19QCBCiToQQTv8IE+Pb1eP9dfS8YwjqLXFr3qbUqu4llvdUZQwUqFMgQQQCD2AgQVYr8G8TAD9XBuxYoVTQ/ptm7dWn788cd4uAXmeEIg0YMKhYUFMm7CW7J56wbLNa9Vs67cdstAbZeBMpb1wRZGO6hQNL9CWbh4nqhv+D9+/HjAKauHuq+9spec1rCJ37YqpKDCClbHEw+9bFWcNGVfzPxYflz6vel+U1PTZMDtD0mVKtVMdbEqCGdQwdcuEk213Uiu1XYlCebYvedPeePdlyy73KsZGsM0S5Yv0Hb3mGLZ9tGhL0haWpplnZ3CSR+PlRxtJ4RgjgZZp8hlXa82dSGoYCKhAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQACBpBZQX/z3wAMPmAyuv/566dGjh6mcAgTCLUBQIdyijIcAAggkqIDdoEK2tqOC91GyH0JRjX5ubOcrpKC3KQoi+I8hqDb+W+ijFb0SVPD04AwBBBBwigBBBaeshLPnsWrVKsnOzjZNsmfPnvLRRx+ZyilwrkCiBxV87QqgViQ9PV363zxQateqF7YF8hVUUN8OX6ZMaGEI9Q39zc5uGXCOe/buks+1B+g3bvLc6cSqY0pKilx9xY3S7KwWVtXuMl8Ph6empspjD7ygtQn0rwifQ8d1xbbfN8vo8a9LYaH5X1Ztz+0o3S6+ylH3F86gwrfzZ8mcuTNM99fo1MZy0/W3mcr9FWzbvlneH/+aZZMh9z4hlSpWLq5b89NymTLtw+Jz45vBdz8mlStXMRYF9f654f/UQndHg+qjQj69evQ39SGoYCKhAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAIIYCBBViiM+lEUAAgXgSKE1QQb9P/TGa0jxOFGgMfWcFdU1jaKHkIR7t6icmoIIKKyeu1qdn+epyuSQjI8OyjkIEEEAAgcgIEFSIjGuijTp27Fjp06eP6baef/55eeihh0zlFDhXIJGDCmoXBbWbgtpVwer42yVXS+uWHayqQi7zFVS49aZ7pb72LezRONRD3TO+/kQOHjrg93IqOHHrTQOkTm3roMaGTb/K+InvWI4xdOBTUiGjomVdIhfm5+fL22NGyK7dO0y3WbZsORl4x8NSoUIlU10sC8IZVFjw43fuz5b3/dSrm6XtTDLIu9jv+a+/rZV/Txlt2eafQ573CPZs2rJe+1l+07Lt7X0GSd06WZZ1dgrDGVQoKMiXvft227msu43VjhJdu1wuZ5x2pq0xKlaorP17uYKttjRCAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBIPgGCCsm35twxAgggEJKA04IK6iasAg+BgwqqY1FPggohfRTohAACCERcgKBCxIkT4gK33367vPOO+QHmGTNmSNeuXRPiHpPlJhI1qJCb65K3Rg+XAwf3Wy7lWU2aS/d/3GxZV5pCJwQV1PyPHj0is7+bLgsXz9PO9Lix+c7UTg939B0s6iF770M9cP3a28O8i93nN/e8U049+TTLukQunDNvpqhdOqyOLp0ulb90uMiqKqZl4QwqLF2xUD798j+m+6lSpZrcd+cjpnJ/BctX/SjTPp9kapKSkiqPP/iiR/nuPTvljXc9y/QG//j7DZLd7Fz9NOjXcAYVgr34U8PuN3W55spefnc6MXWgAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEfAgQVfMBQjAACCCDgKRCuoIJVuMDzSv7PvB9x8h7PV1BBjeq9qwJBBf/W1CKAAAKxEiCoECv5+LpukyZN5Ndff/WYdGpqquzZs0eqVq3qUc6JswUSNagwceoY+WXdGkv8KplVtYfzh0j58uHfucspQQX9xjdsWif//ezfcsjP7gqXXnSVtGvdUe9S/Kp2D3j25YcMv8cXV0mHdn+Viy/4e0lBlN+pf1uMeOMZOew6FPSVu3TqJue3vyDofjt37ZB3xo4Q5eJ91K1zkvS/eaCkpqZ5V5nOoz33cAYV1G4dU6Z9aLonFXR5ePCzpnJ/Bd8vnCOzvvnM1ET9XD543zMe5Xl5ufLC/z3mUaafNDu7pVxzxY36adCvBBWCJqMDAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIBAnAgQVIiThWKaCCCAQKwFggkqGMMCxV+equ1i4B0q0O9Jb29sURIqUBsglPTU27r7nkgtmOotyvVrqVd97MVjlsnKiauNVab3LpdLMjLC/wCZ6UIUIIAAAggUCxBUKKbgjQ+BjRs3SqNGjUy1LVq0kGXLlpnKKXC2QCIGFRYtmSdfzvqfJbz6tvZbbrxTTq7f0LK+tIVOCyqo+3FpD/OPn/SO7Pjzd8vbq16tptx7+4NaXcnv/XrD/xv1L9l/IEc/LX6tWaOO3N1/aPF5tN8UFhbI0y88ENJlL/zrZdKxfZeg+h4/flzeHfeq7Nz1h6lfWlq63HbLfVK7Vl1TnVVBtOcezqDC739sdTtY3dejQ1+QtLTAQQ2971dzPpf5C77RT4tfs046Wfr1HlB8rr95492XZPeeP/XT4teMjAoydMBTHv9uLa608Wb8xHfk+PFjli0PHNovOTl7TXWnNWwivXr0N5UHW8COCsGK0R4BBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQCAYAYIKwWjRFgEEEEhigUgFFYzBg3AEFdQS6UEEY4DBuHR6PUEFowrvEUAAAecIEFRwzlo4dSYjR46UgQMHmqY3ZMgQefnll03lFDhbINGCCuph/Pc+GKl96/1xS/gL/nKJdDr/Ysu6cBQ6Maig7kuFFcZOeFN27TY/6K3q+950jzTIOlW99ThmfD1NFvw416NMP7mxez85vdGZ+mlUX6P9sP+Xs/4ri5bMt7xHtbOE2mHC7hHtuYczqHD06BF5/pVHtVv13mtP3GGNenXr22WQCf95X9at/8nUvuU5beWKbt1N5Wr3BbULg9Vx9eU9pXnTVlZVpSrztesDQYVSsdIZAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAgSgIEFaIEzWUQQACBeBcIJqjg617Nj5IUat+Zav7WVNVfDxOo996BA+9xrEcoGcPcv2iExaPZUUH5ciCAAAJOEyCo4LQVcd58OnXqJHPnmh9c/vrrr6VLl+C+pdx5d5d8M0qkoMKxY0fl7TEjZM/eXZYLeerJp0nvG+4w/X5r2TjEQqcGFdTt7Phzu7wz9v88ftfXb/PKy3pIi+w2+mnxq7J8/Z0XtXPvfwWItoNAPbmj7+CIehZPxOtNNB/2//W3tfLvKaO9ZlB0enKDhnJLz7uCMojm3NUswxlUUOO9+uZzkrPfvMvAXzt2lc7aHzvHsWPH5MVXH9N2MjAHii658Epp3+YvpmE2b93gvhdThVZQtWp1uaf/g0Ht6GA1jncZQQVvEc4RQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQTiSYCgQjytFnNFAAEEYigQ9qBCYdGDRt4hAv0W/QUVVBvjY0qBggqqvfE6+i4OBBWUDAcCCCDgPAGCCs5bEyfNaPPmzdKoUSMpKCjwmFb16tVlx44dUqZMGY9yTpwvkEhBhWmfT5Llq360RM/IqCB39h0ilStXsawPV6GTgwrqHqd+8pGsXrvMdLtqlwm124TVMX7iO7Jh069WVeLroXLLxmEsjNbD/gcPHZC33h8urtzDptlXqlhZbuszSCpXyjTV+SuI1tz1OYQ7qDBx6hj5Zd0affji15PqNZD+N5t32yluYHij+qtxrI5bbrxLTmnQyFSl/n9nxKh/ySFtTayOi/76Nzm//QVWVSGXEVQImY6OCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACDhAgqOCARWAKCCCAQDwIOC2ooMz0sAJBhXj4BDFHBBBAwL4AQQX7VsnY8qmnnpInn3zSdOt9+/aV999/31ROgfMFEiWosGrNUvn40wk+wW+4tq80Pv1sn/Xhqoh0UOHT6f+R89p0kpo16oQ05aXLF4oaw/todU47ubzbdd7F7vOff10tkz4ea1mXkpIqN1zbR8447SzL+kgVRuNhfxXeHj/xbdm4+TfTbaSmpmk7KdwpDeqfaqoLVBCNuRvnEO6gwuJlP8jnM6YaL3HifYrcf+/jUlELcAQ6PvlysixbscjUTAWKhg54Ugu6p5rqVMGS5Qvks+lTLOtUn57X9ZXTG51pWR9KIUGFUNTogwACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggg4BQBggpOWQnmgQACCDhcwFZQ4dZW0rxHM/OdqN0TUlLEKlCg75xg3PFADaCXq/eWdYbx3IGFEzs0qPb64d1PL3fvqKB1cu+oMGm1Xmz56nK5JCMjw7KOQgQQQACByAgQVIiMayKMevz4cWnYsKFs27bNdDtff/21dOnSxVROgfMFEiGosHffbnl7zAg5evSIJXjbcztKt4uvsqwLd2GkgwrvjntV1Lf89+11t1StUj3o6fsKKnTu2FX+qv2xOtSD9a+/86IoZ6ujbNly0qtHf2mQdapVdanLDh0+KCtWLZbz2nYSFRDQjyNH8vS3Qb2mp6dLWlp6wD5z5s6Qb+fPsmz3t0uultYtO1jW2SmM9NyNcwh3UEHtaDD89We0S+jR9ZKrqbCLCr34O9w7I7zxjKh19T5aZreVKy7r7l1cfK4+i6Pee1l279lZXGZ8U65ceelz491Sp3Y9Y3HI7wkqhExHRwQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQcIEFRwwCIwBQQQQCAeBGwHFbo3dYcSiu/JECCwCg74CiQELteCDyeSD0EHFU7MiaBC8SrxBgEEEHCUAEEFRy2HoyYzefJk6dGjh2lOKrzw22+/aQ8QW38DtqkDBY4SiPegQn5+vowe/7r8vmOrpWvdOidJv94DbD2YbjlAkIXRCCr8/sdWqVa1hvsb/TMzqwY1w0+//I8sXbHQ1KfH1bfImY0tQs8nWv6xY5u8rznn5x839VUFaWlpcsmFV0ibVudb1odSePz4Mfl+0bcyf8E37hDKXf2GSq2aoe0kEez1163/SSb8Z7TWzfwwfstztIfpu/l+mD7Ya0W6fbiDCmq+749/TbZt32yaetWq1eXufg+ICoP4Ohb8OFdmfD3NsrrndbcG3J3jl3VrZOLUMZb9VaEKzlz1tx5yVpNsn23sVhBUsCtFOwQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAScKEFRw4qowJwQQQMCBAraDCt47KkQsqFCy04Ix1GCkswpGqHq9PUEFoxbvEUAAAecIEFRwzlo4bSZt2rSRxYsXm6b13HPPycMPP2wqpyA+BOI9qDBz9qfyg/Ywu9VRpkxZub3PIKlRvZZVdUTKohVUUJMvXz5DLr/0Wjn7zHNs3cvW7Ztk7EdvSkFBvqn9wDv+Keohc3/H4mXfy+czPvbXxP1w+IWdu5XKXH3T/vKVP8qPS+fLgYP7i68XraDCvpw98s7Y/5O8vNzia+tvsuqdLH163RW14It+3dK8RiKosHLNEvnvp/+2nNZ5bTtL1y6XW9bt2btL1K4gVjtK1KxRR+7qd79pRz+rgWZ8/Yks+PE7q6riMjUPtUuICi6EekQ6qPD0Cw9o/z4u8JjedVfdZPtn2qMjJwgggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAgh4CRBU8ALhFAEEEEDAWsBWUKFfK8nuXvItqHZ2OtBDA+qqxmCBr3Lj7PQ22t4KWueSAILexjieKituf2IrhsWjl8qKiav15pavLpdLMjIyLOsoRAABBBCIjABBhci4xvuo06dPl27dupluo3z58rJlyxapVSt6D4KbJkFBqQTiOajg71vvFcqVl/WQFtltSuUTbOdoBhX0uTVv2ko6tu8itWvV1YtMr1u2bZT//G+8HDp0wFRXrlx5eWjQM1q59kt9gGPqtA9l9U/L/bZS/w5oelYLadOyg9TPOlnbbSXNb3tVeVgLJ2zeulFWrV0qv/62VgtTeD68rdpEI6hw7NgxbbeAkfLnzj/UJT2OypUypf/NA6Vy5Soe5U4/iURQQf3bbtR7L8nuPTstb7+zFhDo1OEij512lOmE/7znET4xdr5We0C/qc3Qjbq+2lVBfVb8HRnlK0j7tp2k3bkdRX3O7R579+2WDZvWuXcfUbuJeB+nNWwivXr09y4O+lzN/7DrkEc/ZVCacIXHYJwggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggktQBBhaRefm4eAQQQsC8QSlBBja6HA4xXMgYIjPV2yo3j6H3t9NPbqv56e4IKRk3eI4AAAs4RIKjgnLVwykzU/4+3b99eFi1aZJpS//795Z133jGVUxA/AvEaVFAP3L85+hVxeT3ka5Rv17qj8TSs7ytpD62f3+6C4t9t9cFjEVTQr10/6xRpdlZLbTeDmlIls6ocP54ve/btkrU/r5CfflmlNzO9tj33fOl28T9M5VYFR48e0R7kf1127jI/yG/VXj1wfUqDRlK3TpZUrFBRCyFX0MxSJTf3sLhyXbJ//z5RIQr1YHigIxpBBbVLgNotwNeh5h7sUblSZRl092PBdgtb+0gEFdTk1miBlSlacMXXUbNGbffOAGW1nU3++HO7+3No/HehsV+d2ifJHX0HaUWBwzJ6P/VZHPPRKNmhjR3oUGEZFZppdGpjaaD9nFSsUNn9eUxLSxe1g8fBQ/tl/4EcUbuOqICC+lz6O8IVVPB3DeoQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQKK0AQYXSCtIfAQQQSBKBsAYVTuyAoOiMD4roAQJ/5Tp3KP30Pvp1CCromrwigAACzhIgqOCs9XDCbKZOnSrXXnutaSppaWny008/yRlnnGGqoyB+BOIxqKB+rxw/6R3ZqD1QHMvj7v4PiHoY23jEMqhgnIfd9zWq19IeEB8s6ell7HYR9YD4p9OnyOq1y2z3CUfDSAcVFi2ZL1/O+m84puoxhgq1DLnncY+yaJ5EKqig7mHSx2Pl51/975IX6F7LlCkj/XoP0HYEqReoqalefRanfTFJC0GsNNVFsoCgQiR1GRsBBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQCBcAgQVwiXJOAgggECCCwQbVPAOBRh59DpVpocG1Hs75aqd92FnDGMf/TpLxiyTFRP9P9Ticrm0b13NMHbnPQIIIIBAhAUIKkQYOM6GP3LkiDRt2lTWr19vmnmvXr1k/PjxpnIK4ksgHoMKc3/4WmZ/+2XMoWMRVHjvg5Gy/fctYbn31NRUubX3vXJS3QYhjffj0vky4+tPJD8/P6T+wXaKZFBh85b18sHEd6SgIPz3kshBhSNH8uTdca/Knr27gl3O4vb/+PsNkt3s3OLzUN7MX/CNfK39nVBYWBBK96D7EFQImowOCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACMRAgqBADdC6JAAIIxKNAMEEFPQig7tMYItDv21e9nXJ9DOOr8Rq+xjC219ssHr1MVk4iqGC04T0CCCDgBAGCCk5YBefMYdiwYfLwww+bJqS+AXvt2rVy+umnm+ooiC+BeAsqbN2+SdQ3xBcUROeBZH+rGYugQk7OXvlsxlRZv/EXf1MLWJeWli6XXnSltG55XsC2/hps/2OLfPzJBNm7b7e/ZqWqq16tpnRo11laZreV1NS0Uo1l1VnN/b1xIyU3z2VVXeqyRA4qKBwVUvho8nuyL2dPkFYpcmHnbtLxvC5B9rNurv5umP3ddNm0+TfrBmEoVZ+/hqec7v65ObNxszCMyBAIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIRE6AoELkbBkZAQQQSCgBu0GF5tc19bhvY4hAr9CDAurcWG8s1+sKC9U793/UG8sj0BjGTsZrEFQwyvAeAQQQcI4AQQXnrEWsZ7Jlyxb3bgqHDh0yTeWuu+6SN954w1ROQfwJxFNQIS8vV94a84rs37/PEdCxCCroN7567TKZ+8Ns2bnrD73I9qv6NvjLuv5DVAAgHIf6HX/Dpl9l6YqF8su6NWHZYUEFKRqdeoY7nKAeCDf+myMcc9bHUJ8ptUtFaXYE0Mfy9ZroQQV138pxyrQPbQdoypYtJ1df3lOanOH571dfhsGUb922Sb6dP8v2XAKNrT6LpzVsLGc3yXbPt3x5dvwLZEY9AggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIICAMwQIKjhjHZgFAggg4HgBW0GFW1tJ8+6eD3oYH+gxhgT0Gw5UX9QuRW+uPSBU9NY4lr0xiocofkNQoZiCNwgggICjBAgqOGo5YjqZyy+/XD777DPTHDIzM2XdunVSu3ZtUx0F8ScQT0GF7xfOkVnfmD+TsVK3CioMf+0pOXT4oNeUUuTe2x8MWzDAOLj69vjlqxe7v0V+/4EcY5XHe/Vwda0adaR9m05y9pnZHnXhPHG5DsmK1UtkzU8rJGf/XjnsOqwN7z/4rK5fpkxZqVWzjtStfZKc3uhM7U8Td1k452Y11kbN74N/v2VVFbayunVOktv7DA7beMEOpHY7+G3Dz6ZuKqzSptX5pvJQC9S/EdV1Fi2Zr4BQZQEAAEAASURBVL2qHT/M616pYmVp3aqDe0eCihUqhXopW/1UoGnD5nWi1lj9nBw8dCBgv5SUVKlUqbJkVq4i1arWkMannSWNTz9bypUrH7AvDRBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBwmgBBBaetCPNBAAEEHCpQ2qCCr50R7IUM/AcVtH0ZLAMMgSgJKgQSoh4BBBCIjQBBhdi4O+2q48aNk1tuucVyWi+++KIMHTrUso7C+BOIp6BC/OlGd8YqGLB3325xaeEAV+5hSU1Nk5rVa0lNLQCgHhCPxZGfny8HD+6XA+4/OVpw4ZA2r1QpV7a8++Fv9c36VatU0x4Kr65Nr+TfHbGYK9cMn0Bunkv25eyRnJx9cvToEcnMLHrwv0pmNff6h+9K9kdSn0MVnFE/G7naH/VaUFAolStluueXWbmq9r6y9m/bVPuD0hIBBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBwsQVHDw4jA1BBBAwEkCpQkqFIUU1N2Yv9FSlaqwgq8gg6o3PjCkHh0qNI1jfKDI+hruYbz+Q1DBC4TToAUKCgpi9qBT0JOlAwJxJEBQIY4WK0JT3bBhg7Rs2VIOHDB/+3TTpk1l2bJl2jedl4nQ1Rk22gIEFaItzvUQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBCIvABBhcgbcwUEEEAgIQTsBhWyuzcz5gq0AIIxOKAHCoxlRh69XpWVtNH2SyhuZA4pqKqSemO/4k6qhRaGUIdxPgQV3CT8x0vA5XLJn3/+KTt37nS/qvdW56osJydH+ybeclKnTh2pXbu2+1W91/94l1WvXr34s+h1WU4RQMAgQFDBgJGEb48ePSp/+ctfZNGiRaa7V9+CPnfuXOnQoYOpjoL4FSCoEL9rx8wRQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBDwJUBQwZcM5QgggAACHgIhBRW0rIFnsEAPFJSEEDwu4iNwEM6ggrqeHlYgqOCpn4xn6rOwbt06+eGHH+T77793/1mzZk3xZyTcJjVq1HA/XKsesFV/WrduLRUqVAj3ZRgPgbgXIKgQ90tYqhu466675M0337QcY8iQIfLyyy9b1lEYvwIEFeJ37Zg5AggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACvgQIKviSoRwBBBBAwEMgqKCC1tMzoGAcSoUV7AQVVJ+idiqo4Hs8fWz/IQirMQgq6HbJ9ap2Spg1a5bMnDnT/frHH3/EDKBs2bJy/vnnS9euXeXiiy+Wli1bivq2cA4Ekl2AoELyfgL8PbCenZ0tCxculPLlyycvUILeub911295xYoVoj4DHAgggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCAQHwIEFeJjnZglAgggEHOBYIIKdkIFJbGCktBCSopeqt1uSbHPkIK+04Ln9bRSfZgAYxBUiPnHKmoT2L17t0yZMkXUw8/z5s2TgoKCqF07mAtlZWVJjx495IYbbnDvthBMX9oikEgCBBUSaTXt38vs2bPl0ksvlWPHjpk6VaxYURYtWiRnn322qY6C+BcgqBD/a8gdIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggg4C1AUMFbhHMEEEAAAUuBcAYV9ICBupAxZOAutxkyUH31cYxjuMv1pAJBBcWR1MeyZcvklVdekcmTJ8vRo0fjyqJ58+YyaNAg6dmzp5QrVy6u5s5kESitAEGF0grGX/9Vq1ZJp06dJCcnx3LyH374odx4442WdRTGvwBBhfhfQ+4AAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABbwGCCt4inCOAAAIIWArYDSo0797U1F8PFOgV3sECvdzuqz5eacdhRwW74vHXTn0r97Bhw2TWrFnxN3mvGderV88dWLj99tslMzPTq5ZTBBJTgKBCYq6rr7vauHGjdOzYUdTvGlbHfffdJyNGjLCqoixBBAgqJMhCchsIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggYBAgqGDB4iwACCCDgWyDUoEKKzd0NfF/Zs0YPKahSggqeNpyJfPnll/L000/LggULEo6jWrVqoh7WHTBggFStWjXh7o8bQsAoQFDBqJHY77dt2yadO3eWDRs2WN7oJZdcIp999pmkp6db1lOYGAIEFRJjHbkLBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEjAIEFYwavEcAAQQQ8CngtKBCaUMK6kbZUcHncsddhdpB4dFHH5Uffvgh7uYe7IRVYOH+++93BxYqVaoUbHfaIxAXAgQV4mKZSj3J7du3S5cuXeTXX3+1HCs7O1vmzp3LbjKWOolVSFAhsdaTu0EAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQEAJEFTgc4AAAgggYEsg1KCC9eApJ4oLTdVqx4TQQghqzBPjqRf9EoYrGHdjUMU/jl4qKyetNrQwv3W5XJKRkWGuoMQRAqtWrZKhQ4fKjBkzIjYf9S3emZmZUqVKFfdOBupVf6/K8/LyZP/+/e4/OTk5Hu9zc3MjNq+6devKU089JX379uWbxiOmzMCxEiCoECv56F13y5YtcuGFF8pvv/1medFTTjlF5s+fL1lZWZb1FCaWAEGFxFpP7gYBBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAElQFCBzwECCCCAgC2ByAQV1KVLwgrGIEHwYYUTyYTCkvGMYQXj2PoNL9aCCisIKugccfW6Z88e9w4K6sHG/Pz8sM29atWq0rZtW2nXrp20aNFCmjdvLqeddpqkpqaGdI29e/eKClOsXLlSFi9eLAsWLJB169ZJofFzGtLIJZ3UHF999VW54IILSgp5h0CcCxBUiPMFDDB99ffgxRdfLJs3b7ZsWbt2bfnuu++kSZMmlvUUJp4AQYXEW1PuCAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAYIKfAYQQAABBGwJRCOooCZSuh0V1AhaUEHPKnjtquAdVmBHBeUVX4d6wH/cuHHuXRR2795d6slXqlRJOnXq5H7Iv0uXLu5wQqihBLuT+fPPP+Wbb76R2bNnu/+sX7/eble/7Xr16iXDhw8X9YAvBwLxLkBQId5X0Pf8lyxZIpdddpns3LnTslGNGjXcfzdmZ2db1lOYmAIEFRJzXbkrBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAIHkFiCokNzrz90jgAACtgVKFVRQwQEtNKAHBfzulnCirXliKnVwIoHgs43qVXQVy2t49Vs8epmsZEcFM7VDS7Zu3Sr9+vWTmTNnlmqGmZmZcsUVV0j37t3lkksukbJly5ZqvNJ2/vnnn2Xy5MkyadIkWbt2bamGq1mzprz++uvSo0ePUo1DZwRiLUBQIdYrEJnrT58+3f1378GDBy0vUL16dZk1a5a0atXKsp7CxBUgqJC4a8udIYAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggkrwBBheRde+4cAQQQCEog5KDCiWyBulhKStEWB5YhAtXA0FYFG0oOw4n2jfrFh6FYL9PDEOrc4zqGbvrYBBV0Nee/qgf5b7/9dsnJyQl5sk2aNJFBgwbJTTfdJBUqVAh5nEh2XLBggYwYMUI+/vhjOX78eMiXuvHGG2XUqFGiQhkcCMSjAEGFeFw1/3N+++235Z577vH5d1utWrXcQbQWLVr4H4jahBQgqJCQy8pNIYAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIICAAwQKCgpMs1DP8enP8pkqKUAgjAIEFcKIyVAIIIBAIguUOqighQr0EIFHgMAbTQUKLAIIRYVapR44sGwT4BpefQkqeOM77/zo0aMyZMgQ9y4Boc6uTZs28tBDD8lVV10lqampoQ4T1X4bNmyQl156ScaOHSt5eXkhXbtx48YydepUadasWUj96YRALAUIKsRSP7zXVqGr+++/X1599VWfA2dlZbl3UjjrrLN8tqEisQUIKiT2+nJ3CCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCAQG4FFixZJu3btTBd/8skn5YknnjCVU4BAuAUIKoRblPEQQACBBBUIOqjgFQqwz6ISCHrnYHoVJRf8hiD04U4Mv3jMMlk5abVeavnqcrkkIyPDso7CyArs27dPrr76apkzZ05IF1K/ZKtfqi+99NKQ+juhk/q5GzZsmKgHOEMJLFSuXFkmTpwol112mRNuhzkgYFuAoIJtKkc33LNnj1x//fXy1Vdf+Zyn2u1m+vTpcuqpp/psQ0XiCxBUSPw15g4RQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQCD6AgQVom/OFT0FCCp4enCGAAIIIOBDwG5QIbt7MyksNAQNfOx8YH0ZY2PDGNaNi0v1nRpUAUGFYpa4fvPHH39I165dZfVq/0ESq5s8++yz5bnnnpMrr7zSqjouy7Zu3epOMX/wwQeSn58f1D2kp6fL6NGj5aabbgqqH40RiKUAQYVY6ofn2kuXLpVrr71WNm7c6HPA9u3by6effio1a9b02YaK5BAgqJAc68xdIoAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIBAdAUIKkTXm6uZBQgqmE0oQQABBBCwELAbVGjevWlRb5UzMOYOLMa0LlKd7IcU9DFUWCGYkILqx44Kup6zXnfu3CmdO3eWn3/+OaiJqQddn376abntttskLS0tqL7x0njlypVy3333yTfffBPUlFNTU2XcuHHSq1evoPrRGIFYCRBUiJV8eK6rHjofMGCA351g1I4548ePlwoVKoTnoowS1wIEFeJ6+Zg8AggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAgg4VICggkMXJommRVAhiRabW0UAAQRKIxB0UMHqYlb5A+8wg97GUK7vmGAKIli0dV82UPmJuRFUsFqk2Jbt2bNHLrzwQlmxYoXtiaSkpMitt94qL7zwglSvXt12v3huOHHiRBk0aJDs2LHD9m2onRXUw9/qG845EHC6AEEFp6+Q9fwOHjwod955p3z00UfWDU6UPvTQQ/Lss8+KClFxIKAECCrwOUAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQTCL0BQIfymjBicAEGF4LxojQACCCStQFSCCnrAQClbBBVUsUdYQW9vaOuxGYOvcjWQdhBUKHJwyn/379/vDiksWbLE9pQaNmwo77//vlxwwQW2+yRKw3379snAgQPd30hu957KlCkjU6ZMkSuuuMJuF9ohEBMBggoxYS/VRRcvXiw9e/aUdevW+RynfPny7gfS2d3FJ1HSVhBUSNql58YRQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQCCCAgQVIojL0LYECCrYYqIRAggggEBEggrGIIFObBU+0OrUrgoeIQVf7fX+qt44vrH8RF+CCjpi7F9zc3Ola9euMm/ePNuTueGGG+Stt96SzMxM230SseHkyZPltttuExX0sHOoB4W/+OKLpAx32PGhjTMECCo4Yx3szKKgoEBefPFFeeKJJ+To0aM+u5x88skydepUad26tc82VCSvAEGF5F177hwBBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBCInQFAhcraMbE+AoII9J1ohgAACSS9gO6hwXVPfVil6csAiNeDdy6qJ3t1fW2MbwxgpJ65tDDssHr1MVk5a7T2ax7nL5ZKMjAyPMk7CK5Cfny9XX321fPLJJ7YGVrsCvPLKK3LPPffYap8MjdQ3mF911VWydu1aW7erwh3ffvuttGjRwlZ7GiEQbQGCCtEWD+16mzdvlt69e8t3333nd4CLLrpIJkyYILVq1fLbjsrkFSCokLxrz50jgAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggEDkBAgqRM6Wke0JEFSw50QrBBBAIOkFHBFUUKtgDCLoq2IIJLiL9DaGcj2ooOr1sAJBBR0wtq933323jBo1ytYkKlWqJFOmTJFLLrnEVvtkaqR2VFBhhTlz5ti67aysLFmwYIHUr1/fVnsaIRBNAYIK0dQO7Vrjxo2TgQMH+t3NJTU1VR599FF5/PHHJS0tLbQL0SspBAgqJMUyc5MIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIBBlAYIKUQbnciYBggomEgoQQAABBKwEwhNUsBrZR5khZODRQg8h6IW+2un1+qvWL0X7nx5SUMUEFXSc2L2+9tprMmDAAFsTUCGFL7/8Ujp27GirfTI2ysvLkyuuuEJmzZpl6/Zbtmwpc+fOlYoVK9pqTyMEoiVAUCFa0sFfZ9u2bXLnnXfKZ5995rdz3bp1Zfz48aJ2U+BAIJAAQYVAQtQjgAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACwQsQVAjejB7hFSCoEF5PRkMAAQQSViCooIIeJvAOEejlSsm7zlvO0LbwRFt3kaE84BjGMY39TpQTVDACRf/97Nmz3TsjHD9+PODFMzIy5PPPP5cLLrggYNtkb+ByuaRbt27y3Xff2aLo3r27TJw4UYy7jtjqSCMEIihAUCGCuCEOnZ+fL2+88YY89thjcuDAAb+jqL+DxowZI3Xq1PHbjkoEdAGCCroErwgggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggED4BAgqhM+SkUITIKgQmhu9EEAAgaQTCGtQIVBIQekaggUEFRLv46a+kbtVq1aya9eugDdXrlw5mTZtmjvUELAxDdwCBw8elK5du8qCBQtsiQwfPlwGDx5sqy2NEIiGAEGFaCjbv8b8+fPl3nvvlWXLlvntpP6+HjZsmAwcOJDwk18pKr0FCCp4i3COAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIlF6AoELpDRmhdAIEFUrnR28EEEAgaQRsBxW6Nw28W4IdNUNQwefOCcY2akyrAITeRqtT1fqpar54zDJZOWm1euvzUN9Or77NnyN8AmoHhS5dusjcuXMDDpqWliaTJk2Sa665JmBbGngK7Nu3Tzp37iyrVq3yrLA4K1OmjHsHhvbt21vUUoRA9AUIKkTf3OqKmzdvlocffti960qhnhq0aqiVNW3aVD788ENp0aKFjxYUI+BbgKCCbxtqEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAgVAFCCqEKke/cAkQVAiXJOMggAACCS4Q0aCCnh4wBg30MuVqLDc6G9vo5ca2hnrj85V6MUEFHS26r08//bQ88cQTti76xhtvyF133WWrLY3MAtu3b5fzzjtPtm7daq70KmnUqJEsX75cKleu7FXDKQLRFyCoEH1z4xVV0On555+X1157TfLy8oxVpvcqUDZkyBB56qmnpHz58qZ6ChCwI0BQwY4SbRBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAIHgBAgqBOdF6/ALEFQIvykjIoAAAgkpYDuocJ22o0Iwh54aUH2sQgbGMu9xjX31Ou/2J9roQQVjF4IKOlr0XpcsWSLqW/vVrgqBjsGDB8vw4cMDNaM+gMDKlSulY8eOcvDgwQAtRfr16yfqYVEOBGItQFAhNitw6NAhGTlypLz88suiwgqBjnPOOcf9d0abNm0CNaUeAb8CBBX88lCJAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIhCRAUCEkNjqFUYCgQhgxGQoBBBBIZIGwBRWMSQEF5h0sCBaxFOMRVAgWu3Ttjx07Jq1btxb14Hygo1u3bvLpp5+K+qZujtILTJs2Ta6++mopKCjwO1hKSorMnDlTLrroIr/tqEQg0gIEFSIt7Dn+4cOHZdSoUe6Aws6dOz0rLc4qVark3hln4MCBUqZMGYsWFCEQnABBheC8aI0AAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAgjYESCoYEeJNpEUIKgQSV3GRgABBBJIICxBBe9QgfIpRVBB76o9W11y6IUlJT7fEVTwSRORihdffFEefPDBgGM3bNhQ1M4L1apVC9iWBvYFHnvsMfnXv/4VsMPpp58uq1atkvLlywdsSwMEIiVAUCFSsp7j7t+/3x1QGDFihOzatcuz0uJMhZl69uwpL7zwgmRlZVm0oAiB0AQIKoTmRi8EEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEDAnwBBBX861EVDgKBCNJS5BgIIIJAAAo4OKihfPaxAUMGRn7bt27fLmWeeKYcOHfI7v7Jly8q8efOkTZs2fttRGbxAfn6+e6eEOXPmBOysAg2PPPJIwHY0QCBSAgQVIiVbNO6OHTvk1VdflbfeektycnJsXey8886T4cOHi3rlQCDcAgQVwi3KeAgggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggIAIQQU+BbEWIKgQ6xXg+ggggECcCAQdVFDBAT+hgUKtMqU4XWBAMPSz08bQM/Bbw9iqMTsqBCYLV4u+ffvKmDFjAg43bNgwW7suBByIBpYC27Ztk+zsbNm3b59lvV5YqVIlWbdundStW1cv4hWBqAoQVIgM95o1a0TtnvDRRx9JXl6erYs0btxYnn32WbnmmmtE7ajAgUAkBAgqREKVMRFAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAINkFCCok+ycg9vdPUCH2a8AMEEAAgbgQCCqoYHyO0SKsoAII+uERVjD0KywM3MYwjD6c71fD2Ho/ggq+ucJZs3btWvfD8eob/f0d6lu6586dK2lpaf6aUVdKgfHjx0vv3r0DjnLPPffIa6+9FrAdDRCIhABBhfCpFhQUyPTp02XkyJEyc+ZMMf7/q7+rnHzyyfLYY4/JLbfcIunp6f6aUodAqQUIKpSakAEQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABkwBBBRMJBVEWIKgQZXAuhwACCMSrQFBBBXWTKhhQkjUw3bYeVvAIKnj1s9xRQQ8c+BnbdDF9XPVq6EdQwVIq7IU9e/YU9dCxv6Ns2bKydOlSadq0qb9m1IVJ4NJLL5UZM2b4Ha1cuXKyfv16ycrK8tuOSgQiIUBQofSqOTk5MnbsWBk1apR7hxS7I9avX18efvhhufXWW0X9PcCBQDQECCpEQ5lrIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIBAsgkQVEi2FXfe/RJUcN6aMCMEEEDAkQJBBxVO3IXPQEKId6nnDPS8gj6Mz+voDfWOhnktGbNcVk5arQ9h+epyuSQjI8OyjsLAAhs2bJDGjRtLoN0Uhg4dKi+++GLgAWkRFoF169ZJ8+bN5ciRI37Hu//+++Wll17y24ZKBCIhQFAhdNXFixfLW2+9JRMnTpTDhw/bHqhhw4by4IMPundQIKBgm42GYRIgqBAmSIZBAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEDAIEFQwYvI2JAEGFmLBzUQQQQCD+BEobVFB3bNo9IQQGY96gJINQUupxDb2Buk5JE+1t0cmSMcu0oMIav7MgqOCXJ2Dl4MGDZcSIEX7b1apVS3777TfJzMz0247K8AqoEMLw4cP9Dlq1alXZtm2bVKxY0W87KhEItwBBheBEDxw4IBMmTBD1sLfanSaYIzs7Wx544AHp0aOHpKenB9OVtgiETYCgQtgoGQgBBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBAoFiCoUEzBmxgJEFSIETyXRQABBOJNIPSggrpTFQzwiBCU6vaLRvMcQoUPLK+gwgqGkILqVRJUYEcFT8XwnuXm5kpWVpbs27fP78AqyHDffff5bUNl+AX27t0r6hvU1QPO/g718Gi/fv38NaEOgbALEFQITFpYWCjfffedjBkzRqZMmRLU7glq9IsuukiGDBkil1xyiaSkGJN9ga9NCwTCLUBQIdyijIcAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAgiIEFTgUxBrAYIKsV4Bro8AAgjEiUDpggpFNxnsY5A+wwchmukBBT3QsNi9o8Jqv6Oxo4JfHr+VH3zwgdx8881+29SpU0c2btwoGRkZfttRGRmBRx55RJ577jm/g7dp08b9jxa/jahEIMwCBBV8g27atEnU36/qz/r16303tKgpX7689OzZUwYOHChqJwUOBJwiQFDBKSvBPBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAIJEECCok0mrG570QVIjPdWPWCCCAQNQFShtUCCWkoN+kHizQz0N51UMKqq8+HkGFUCTt9+ncubP727799XjmmWfk0Ucf9deEuggK/Pnnn3LKKafIkSNH/F5lxYoVPNTsV4jKcAsQVPAUzcnJce+aMH78eJk7d66o3RSCORo0aCB33HGH9O/fX2rVqhVMV9oiEBUBggpRYeYiCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCQZAIEFZJswR14uwQVHLgoTAkBBBBwokBUggqG5y4LU4pO9FBBsYnexl/ywUeborBCyYgEFYpVw/5GfeN3o0aN/D5MW7ZsWdm6davUrl077NdnQPsCN910k3z44Yd+O9x///3y0ksv+W1DJQLhFCCoIJKXlyeff/65TJgwQb744gv3eTDGKSkpctFFF8mdd94pl19+uaSnpwfTnbYIRFWAoEJUubkYAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggkiQBBhSRZaAffJkEFBy8OU0MAAQScJBBMUKFk94KSUID3vehtPFpoAQP3t0RrIQR3uXcYQdX/P3v3ASdFla99/D9EW1CCAgZYXUUUBoliXDAg5jUgZpFgglVETIthRVFEZVcEWbx6Jcm6VwmrrrqgIquYlQwjoqKi+BIUA2FAGZi3T3Wf6equ0NU9Haq6f7Xv0NUn1/cMg/fz9jMn/L/IZTQybuOamdrYjhHuoUdYMGmRLH1ueXQ8+5fy8nIJhUL2lZQ6Cjz00EMydOhQx3pVcdFFF8mzzz7r2obK7Au888470rVrV9eJ1G9jX716tagPPnMhkAuBYg0qqH9zZs2aJTNnzjRCCps2bUqZW4W/+vbta5ye0LJly5T70wGBfAgQVMiHOnMigAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggEChCxBUKPQd9v/zEVTw/x6xQgQQQMAXAukFFaKBg4QniIUN4uuNkIJKERgZhFgQoaq7DiEYbWL1cR+dVm0qw384jREeTHVXF0GFiEM2/uzSpYvMnz/fdejXXntNevTo4dqGytwItG7dWj799FPXyd5//305+uijXdtQiUCmBIopqLBu3Tp5+eWX5aWXXpI5c+aICiuketWsWdP4eXrllVfK2WefLerEGi4EgiRAUCFIu8VaEUAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAgKAIEFYKyU4W7ToIKhbu3PBkCCCCQUQFPQYX+neTwC0qlsqQyciJC4gqiCQFVr6640xRUQbhYhRicTkJQTSJtjLtoGCF6r1/0HHocXR6XZoiEFQgqaJzMvq5Zs0Z+97vfRQIjDkPvv//+8s0330iNGjUcWuS+uKKiQtTav/vuO2nYsKHst99+0qhRo9wvJA8zjhgxQu666y7XmdUJGSNHjnRtQ2XxCnz55ZeybNky40PymTh5o5CDCupnzQcffCCzZ882vhYtWiS7du1K65tHnZigTk+44oorRJ18woVAUAUIKgR151g3AggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAgj4WYCggp93pzjWRlChOPaZp0QAAQSqLeAlqHBE/45GUMH2Q6rREIJaiGsQodorjQ6g51PBBYfTFeZPXCRLpy13nVH9ZutQKOTahsp4AS8fNrzxxhtl9OjR8R1z/E6dvKE+WK1OdlBf77zzjmzbti1uFSqscOqpp8pVV10lxx57bFxdIb1ZtWqVqA88u13t2rWTJUuWuDWhrogFPvzwQ+PEjU6dOsmwYcPkj3/8o9j+W+DRqNCCCitWrJA33njDODHhzTfflF9++cWjhLWZClJdeOGFRjhB/VyqjrN1dEoQyI+Al/92UP8GqX+LuBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEvAkQVPDmRKvsCRBUyJ4tIyOAAAIFJZDxoILSSTjlIKNgBBUyypnKYOoDtNOnT3ftMm/ePOnatatrm2xWvv/++3LzzTeLevV6nXTSSTJq1ChRH8QuxKtDhw6uQQT1Yei1a9dKs2bNCvHxeaZqCuiggh6muoGFoAcVVq5cKSqQ8NZbbxlf6t/Q6lx16tSR008/XS6//HI566yzZLfddqvOcPRFwHcCBBV8tyUsCAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEECkCAoEIBbGLAH4GgQsA3kOUjgAACuRLwElTo0r+TcaKCYwBBnW4QvirD/0u8LKcsRIMGTuW6v1Gv3ujQg2mOqjpzve4Yfp0/KXyiwnOcqGAiqfatOqVgn332kQ0bNjiO1bhxY6O+Zs2ajm2yVbF582a59dZb5cknnxS11lSvGjVqyH333Sd33HFHql193/6uu+6SESNGuK7z2WeflYsuusi1DZXFKZAYVNAKnTt3lrvvvjvlExaCFFSoqKiQxYsXG6eyqJNZ3n33XVm3bp0mSPu1du3a0r17d7ngggvk3HPPFfWzkwuBQhUgqFCoO8tzIYAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIBAPgUIKuRTn7mVAEEFvg8QQAABBDwJeAoqXBkNKiQZ0fiAeOJnxMNBg6pQQjSkYOQZnMr1HOb6cFnV2Anlurn5laCCWSMz95999pkceuihroOpD91OmzbNtU02Kr/88kvjN5GvWLGi2sOrsMPDDz9c7XH8NIA65eL44493XdKgQYNk7Nixrm2oLE4Bp6CC1lCBhWHDhhl/B9XpHMkuPwcVNm7caJzGok5kUV8ff/yxbNmyJdkjeaqvX7++nHbaaXLOOefImWeeKY0aNfLUj0YIBF2AoELQd5D1I4AAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIICAHwUIKvhxV4prTQQVimu/eVoEEEAgbYGMBRV0CEGtxBxWSAgWWAIH0ZUbpzHY9TPXR++rgg/R94kvBBUSRar/furUqXLFFVe4DjR+/HgZOHCga5tMV65evVqOPfZYUd/HmbpGjRolt9xyS6aGy/s4v/32mzRs2FC2bdvmuJYjjzxS1AfSuRBIFEgWVNDtvQYW/BJUUAGEhQsXyvz5840vFUpYtWpVWieyaIPE15YtW8oZZ5xhBBNUWKhu3bqJTXiPQMELEFQo+C3mARFAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAIA8CP//8s7z77ruWmQ855BBp1aqVpZwCBDItQFAh06KMhwACCBSoQEpBBXMYwcbDCBDYlIePVIhdpjCCEU6I1tj1daxPGM/cTg23YNJiWTpteWxOm7vy8nIJhUI2NRTZCdx0000yevRou6qqsiVLlki7du2q3mf7Zvv27XLccccZHzZ2mqtWrVpy8MEHS2lpqRx00EGyZs0aKSsrM7527dpl261mzZoyd+5c6datm219EAvVh6TVyQpOl/q7sGnTJlFeXAiYBbwGFXSfZIGFXAcVKioq5PPPP5dly5bJ8uXLjS91r05icfoZoJ8l1dc999xTTjrpJOnRo4eccsopooIKXAgUuwBBhWL/DuD5EUAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQKUYCgQiHuKs+EAAIIZEHAc1ChV2n4oAQjqeC4ipIS4/gEx/q4Ch16UMGFhFMXdDvL6QvmgIJqZB5Ddwq/Lpi8KBxUKDOVWG8JKlhN3ErUB2/nzJnj2GT33Xc3PuiuPuSfq2vQoEEybtw42+nU92Lv3r3lwQcflH333dfSZvHixXLrrbc6PpNKFqsPM9epU8fSN4gF6oSIv/3tb65LX7FihRx22GGubagsPoFUgwpa6IgjjpBhw4YZpwkY/zZEK7IVVPj+++9l5cqV8tlnn8W9qlMS1Kki2bhUwEed6KLCCepLPTNhn2xIM2aQBQgqBHn3WDsCCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAL2AgQV7F0oRQABBBBIEPAUVOjfSQ6/IBxUqFSpAtOVEBywOxUh7jQF3TUxYKCCCirkYL4S2lhCEAn1VV3DwyyYRFChyiNDNy1atDBOI3Aa7sgjjxT1geZcXW+++abxwWDL92R4AU2bNpWpU6cav9E82Xpuv/12I8xg127SpEnSt29fu6rAlSmPK664wnXdzz//vJx77rmubagsPoF0gwpaKjGwkG5QYceOHbJ69WrjJAR1GkLi1y+//KKnzNpr/fr1jWCCOm1FnVLSpUsXqVu3btbmY2AECkGAoEIh7CLPgAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAQLwAQYV4D94hgAACCDgIeAkqHNG/oxwePlGhKoiQkCnQQxsnLug30Vejj7m9XcAgXF8VVDDqo51NwYi4oIIeQzUL31ddapzw/+YbQYXlVcV2N5yoYKdiX7Z9+3ZRJybYhQJ0D/WBfvXB/lxcO3fulA4dOsjy5dY93meffeSdd96Rgw8+2PNSLrjgApkxY4alvZpj0aJFlvIgFixYsMD4be9uaz/nnHPkxBNPdGtCXZEJ7LXXXnLIIYfI0UcfXe0n14GFTZs2yWWXXeY63o033mgEAL777jsjnKACCupe/d3P5bX//vvLcccdV/XVvn17TkzI5QYwV0EIEFQoiG3kIRBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEIgTIKgQx8EbBBBAAAEngWoFFcwBhPAExgfZzcEBNWk0PKBeVajACDPYtdEnKqg2VfVVN5EgQ7IxIpPJ/InqRAXrh9jVcvRFUEFLJH/9/PPPpVWrVq4N77//frnzzjtd22Sq0ul0gJo1a8qcOXPkhBNOSGmqH374QVq2bCl2v5FdhR7UB5WDfqlna9iwYdAfg/XnWKC0tFQmTJiQkaCCXvpBBx1knIag3/vltU6dOtKxY0fjWY855hhRX7/73e/8sjzWgUBgBQgqBHbrWDgCCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAKOAgQVHGmoQAABBBAwC1QrqGAeKHwfd6JCNGNQdVKCU8hAlYevqtMawvexoIKqiAwUVx9JPKhukSs8hvnkBoIKGiYzr2+99VbSD/8//fTT0rt378xMmGQUddLBkiVLLK1uuOEGGTNmjKXcS8Ftt90mo0aNsjTt16+fTJw40VIexAIVVLALYwTxWVhzbgSyEVTIzcrdZ6lfv76o0xFUMEH9PFGv6lnr1q3r3pFaBBBIWYCgQspkdEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQMD3AgQVfL9FLBABBBDwh4CXoEKX/p3k8AtKIycmhJddFRqIhgx0QKGqXD+ayhhE2xiv4fdxJyrogEG4mR5DKk2j6L5x9ab51Ty6jX4NF82fFD5R4TlOVFA8mbhmzpwpvXr1ch3q9ddfl5NPPtm1TSYqFy5cKJ07d7YM1ahRI+O3tKd7asBXX31lnKqwa9euuLH32GMPWb9+vYRCobjyIL5p3bq1fPrpp0FcOmvOk0DQgwrq76/6vm/Tpk3c1wEHHCA1atTIkyrTIlBcAgQVimu/eVoEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAgeIQIKhQHPvMUyKAAALVFvAUVLgyHFToFQ4qmE4yMMUJqkIGxukJOjCgQgpuQYVwO2MM1V4FGEzHKFSNreqi4xn1ajyjKFoYfdFtIrUEFbRDpl4nTJggV111letwCxYskE6dOrm2yUTlsGHDZPjw4Zah/vznP8uDDz5oKU+l4JRTThEVuEi8VFCjZ8+eicWBe3/cccfJe++9F7h1s+D8CQQlqFCzZk3Zc889Zd999zUCR+q0hGOPPVaOOeYYadCgQf4AmRkBBISgAt8ECCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIFJ4AQYXC21OeCAEEEMiKgKegQsKJCmohVWGC8H1lSSRBYC4zFhsNFugggTnooMo8BRWMgVSWQQ8W7hc+daHqMt3qMuNEhWmcqKA9qvs6duxYGTx4sOswn3/+ufEBYddGGajs3r27zJ071zLS8uXLRX2oujrX008/LX369LEMccUVV8iUKVMs5UErOP3002X27NlBWzbrzaNAUIIKbkTNmzc3fja0bdvWeFXPpE5YqF+/vls36hBAIEMCBBUyBMkwCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAII+EiAoIKPNoOlIIAAAn4W8BJUOKJ/R+NEBXMQoSo4oAMH4YesKotlCmKPrgIF5nLdL1puPlGh6hgFo3e4k24bHS0u8KDK1Bima8GkRbJ0WpmpxHpbXl4uoVDIWkGJReCvf/2r3HrrrZZyc8E333wjLVq0MBdl5V79xvR169bFjd2sWTNLWVwDj29++eUXadq0qfz2229xPfbee29jfPVb24N8nXvuufLiiy8G+RFYe44FCiGoYEdWo0YNI1ilToHp3LmzcRqMum/YsKFdc8oQQKAaAgQVqoFHVwQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBHwqQFDBpxvDshBAAAG/CWQsqBAOCxhhA3MYwe1hdfhAhQzCfeyDCtHBEtsaHZwHXzCZoIKzTuo1Dz/8sPz5z3927bhmzRrZf//9XdtUt1J9j9SqVUt27doVN9Txxx8vb775ZlxZum969Oghc+bMsXR//fXX5eSTT7aUB6mgZ8+e8vzzzwdpyaw1zwKFGlSwYy0pKZFDDz1Ujj32WDnmmGOM18MOO0xUqIELAQTSFyCokL4dPRFAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEPCrAEEFv+4M60IAAQR8JuA5qHBBqZRUqlSByhWY0gg6RKDLTVVGY/VHpFvkralefTBUX45BhWiTuNMcwh9Yd7sIKrjppF7n5USFb7/9Vpo3b5764Cn0qKiokN13390IKqjvF/111llnyUsvvZTCSM5Nx44dK4MHD7Y06NOnj0yePNlSnkqBCnOooMCWLVuqvrZu3Srnn3++nH766akMlVbb8847T1544YW0+tKpOAUyHVRo0KCBdO/eXf71r3+5gqqfOart6tWr5euvv656Vf9e7dy507VvJisbNWpkBBaOO+44+cMf/iBdunSR3XbbLZNTMBYCBS9AUKHgt5gHRAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBAoQgGCCkW46TwyAgggkI6Al6BClys7yeG9ShNOPYjNpkMEcQGGcLUujwsqqG7RnIG5vW4bqYo2CAcZdJShqm24KlZaNVRs0PAdQQWFnLlrzJgxcuONN7oO+MUXX8jBBx/s2iYblTrgYg69VGceFSY44IADLKc21KtXT7777jvjw9Ppjv/aa6/Jqaeeaun+4IMPJj2xwtIpjYIzzjhDZs2a5dhTPbfdaRKOHagoeIE6derI2rVr5eijj67Ws6rQgQoAqZ8js2fPlksvvdR1vHfffdcICCQ2+u2334zgwqpVqyTx66uvvpJt27Yldsno+7p168qRRx4p6hQX9aVOXlA/G7gQQMBZgKCCsw01CCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIBFWAoEJQd451I4AAAjkWSCmooBIG0QyBeZk6OFAVJohW6nIjbaASB7pv9NXcXrc1l4kKKkT7GeXRfrqtmkYPGZky8o6gQkQjU396+ZDh4sWLpX379pmaMq/jnHTSSfLf//7XsobRo0cnDWxYOpkKnnrqKbn66qtNJZHbcePGyXXXXWcpz3RBt27d5O2333Yctl27drJkyRLHeiqKU+DDDz9MO6igAgo33HCDDBkyRNTpBOr6v//7v7SDCm47sGvXLlEnu3z66afG18qVK6te1b9z2bhUkOOoo44yTolQPzfUvSrjQgCBmICX/4ZQ//aof4O4EEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQCAYAgQVgrFPrBIBBBDIu4CnoEL/8IkKF7ifqBAXMDA9lREq0MciqHJTsqCyJPampLIkXBV7bwxhpBSig1XG6uyDCrF6ggpRswy9TJs2TS666CLX0ebOnSsnnniia5ugVD7zzDNy+eWXW5Z74IEHyueffy61atWy1Hkp6NWrl8ycOdPS9NVXX5VTTjnFUp7pgrZt20pZWZnjsF27dpV58+Y51lNRnALpBBXsAgpaL1tBBT2+3etPP/0ky5Ytk6VLl1Z9LV++XLZu3WrXPO2y+vXrGz8H1d9ndXrKIYcckvZYdESgUAQIKhTKTvIcCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIxAQIKsQsuEMAAQQQcBHwHFToFQ4qmIIE8WGBWEjAZar4qnB4oSrEEO5eaQoixBraJxySzU1QISaYibs33nhDTj75ZNeh1IePL774Ytc2Qan89ddf5YADDpD169dbljx58mTp06ePpTxZwapVq6R169ayY8eOuKa1a9eWH374Qfbcc8+48my8adKkiTGX09jnnXee/Otf/3KqprxIBVIJKrgFFDRfPoIKem7zqzqBYcWKFaKe76OPPjK+VJihoqLC3Kxa9y1btpQzzzzT+Dr++OM5baFamnQOqgBBhaDuHOtGAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEDAWYCggrMNNQgggAACJgGCCiYMbm0FPvnkEyktLbWt04UPPfSQ3Hbbbfpt4F/vu+8+ufvuuy3P0bx5c+M3szds2NBS51SgQjhnnHGGzJ4929LkrLPOkpdeeslSnumC8vJyUb/t3T4QFJlt4MCBMn78+ExPzXgBF/ASVFBBmxtuuEFuuukmadSokesT+yWoYLdI9ffk448/lvfee8/4+uCDD1zDPXZjOJUpI/VzQAWCTj/9dNljjz2cmlKOQEEJEFQoqO3kYRBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEDAECCrwjYAAAggg4EnAS1DhiP4d5fDwiQpOlzrhwHzaQnw7+1MRjDamqpJK05twZeSMBvNJDZF69ad5Ln26grll5ESF5fHLSHinPpAaCoUSSnlrJ7B58+akv/H/mmuukSeeeMKueyDLfvrpJznwwANl06ZNlvV369ZNXn75Zc8fNB4xYoTcddddlnFUwWuvvSY9evSwrctkofpN8e3atXMdcuTIkTJ06FDXNlQWn4BbUEEHFIYMGSKNGzf2hOPnoELiA6hgz6effipvv/22vPPOO8br119/ndgs5fe77babnHbaaXLhhRfK2WefLfXq1Ut5DDogEBQBggpB2SnWiQACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAgHcBggrerWiJAAIIFLVApoIKCtEcIFDv7UIEOoKg6s2Xbmsuix8v1sJcHiuNjUxQwayYmftmzZrJhg0bHAfr2rWrzJs3z7E+iBXDhg2T4cOH2y69bdu28uyzz7qeNKECHuoD3BMmTLAd48QTT5S5c+fa1mW6cNq0aXLRRRe5Dvvcc88ZH5x2bURl0QnYBRXSCShouCAFFfSaza+rV6+WN998U/773/8ar+p9dS510ok6ZeHyyy+X7t27S82aNaszHH0R8J0AQQXfbQkLQgABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAoNoCBBWqTcgACCCAQHEIBCeoYA4+xM5PIKiQm+9TdYqA+q3iTlfDhg3lxx9/lJKSyMkXTu2CVK5OU2jVqpWsX7/edtl169aV448/Xk499VTjq7S01DiB4YMPPjB++/pTTz0la9eute2rfqP6woULpXXr1rb1mS5UJzqokx3crsWLF0v79u3dmlBXhALmoIIKKAwaNEhuuukmzycoJJIFPaiQ+DyrVq2S119/XebMmWMEj9RpLOle++23n1x22WXSp08f1xBUuuPTD4F8CBBUyIc6cyKAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIJBdAYIK2fVldAQQQKBgBFINKqhgQNWJBiovYHwuXX84PRYgcAaKRAusYzj0qJrDob6qOBZZmD95kSydtryqxu6mvLxcQqGQXRVlNgJ/+tOf5PHHH7epiRV99tlncsghh8QKCuDu5ZdflnPOOUd27dqV9Gl233132bZtm1RWJv97MH78eBk4cGDSMTPV4LTTTpNXX33VcbhatWrJli1bRIUvuBAwC6igwimnnFLtgIIes9CCCvq51OvOnTtFec2aNcv4UmEkLz8PzGPo+y5duki/fv3k4osvlkaNGuliXhEInABBhcBtGQtGAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAgqQBBhaRENEAAAQQQUAKpBBViUQCJ//Bl1W/RT/4BbecxHPZDD6mzEA7NVLEem6CCC1KaVV4+aDh58mTjN4GnOYVvu6mTEa699lpPYQUvD3HVVVeJ8szVpT48vddee8kvv/ziOGW7du1kyZIljvVUFK+AOilFXY0bN84IQiEHFRKB1L+vL730kvz73/82TlvYvn17YpOk71WgrmfPnqJ+bqgTXArp1JqkD0+DghDw8t8P6t8f9e8QFwIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggEQ4CgQjD2iVUigAACeRdIJ6hgnIYQFyDQKQJd6PZYkTiB0VL/5nnd3a6bHtKtTbQfQQU7wMyULV68WDp27Og6WN++fWXSpEmubYJaqU5W6N27t/z888/VeoQhQ4bIqFGjpGbNmtUaJ5XOCxYskCOOOMK1y5VXXikqkMGFQLYFiimoYLbcvHmzqJ8jM2bMME5bUKevpHq1atVKrrnmGiMQtvfee6fanfYI5EWAoEJe2JkUAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQACBrAoQVMgqL4MjgAAChSPgJajQpX8nObxXqRgBhRQeXQUHrH3MiQOdQogfVAcOrH1j7eLGVsOYhl0weZEsnVYWa2xzV15eLuo3VXN5E1C/lV/9RvVNmzY5dth///3l22+/Ldjf+L169Wq5+uqr5fXXX3c0cKo48MADZdy4cXLmmWc6Ncla+YMPPii333676/gTJ06Ufv36ubahEoFMCBRrUMFsp36OPv/88/LMM8+XbnUoAABAAElEQVQYJy2on6+pXLvttptccMEF8qc//UmOPvroVLrSFoGcCxBUyDk5EyKAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIJB1AYIKWSdmAgQQQKAwBLIVVNBhA6UUHzgwJQrCNXaX7hvfL9ZS16uSSn0qg3oTHZqggsLI/KU+ZP+f//zHdeBFixZJhw4dXNsEuVJ9v82aNUtGjx4tb7zxRvz3n82DNWjQQIYNGyYDBgzIWzCma9eu8s4779isLla0atUqOeigg2IF3CGQJQGCCvGwa9eulX/+858ydepUWbJkSXylh3edO3eWQYMGyUUXXSQqwMCFgN8ECCr4bUdYDwIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAtUXIKhQfUNGQAABBIpCwGtQoW2vNil56DCBfdhAJQrsQwpqEve+kWWoNlVj66EIKkRwsvTno48+KkOGDHEd/e6775Z7773XtU2hVH799dfG6QrqQ/7qtIU1a9bIfvvtJ61bt676atWqVV4/PLxu3Tpp3ry5uP3G9oMPPli++OKLQtkWnsPnAgQVnDdIBRWmTJlinLSwYcMG54Y2NU2bNpWBAwcaX82aNbNpQREC+REgqJAfd2ZFAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAgmwIEFbKpy9gIIIBAAQl4CSoc0b+jHN6rNPLUOhSgDYxwQDQhEC7Td0aIQLfVhbqPKrcr0/X6tcTcKNzJrp9uq16j8y2YskiWTisz11juy8vL8/Yb7i2LCUjBypUr5bDDDnNdrapfsWKFaxsqcycwbtw447etu814/fXXy2OPPebWhDoEMiZAUCE55Y4dO+Tll1+WiRMnyuzZs6WioiJ5p2iLunXrSu/eveWmm24yAlOeO9IQgSwJEFTIEizDIoAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAgggkEcBggp5xGdqBBBAIEgCKQUVokEAy/NFAwVxsYJKU+O4ClNvp3LdxBxUcBpPt1WvOqgwORxUmE5QwUyTqXsVRFCBBbfro48+ki5durg1oS5HAkcffbR8+OGHrrO99tpr0qNHD9c2VCKQKQGCCqlJfvfdd0ZgYcKECcbJLV5716hRQ/74xz/K0KFDRf0c4EIgXwIEFfIlz7wIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAghkT4CgQvZsGRkBBBAoKIGUggrqyU35AwPCCBvEEgfqLulpCkbH8B+xbpESx7GjFbo+sZ8eL1q/gKCCFsn46x133CEjR450HXfAgAHy+OOPu7ahMvsCZWVl0rZtW9eJGjduLOvWrZPatWu7tqMSgUwJEFRIT3LXrl0ya9Ys+Z//+R/jdefOnZ4H6t69u9x1111ywgkneO5DQwQyJUBQIVOSjIMAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggIB/BAgq+GcvWAkCCCDga4FUggol0WSBEURweiqHMIHqGxdgUP1NgQNPY+s5LXNE4hE6REFQQUNl/nXp0qXSvn1714H33HNPUb8FvH79+q7tqMyuwODBg2Xs2LGuk1x99dXy5JNPurahEoFMChBUqL7m119/LePHjzdOWti4caPnAbt16yb33nsvgQXPYjTMhABBhUwoMgYCCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAL+EiCo4K/9YDUIIICAbwXSCSqoh3EMK1hCBCqPEEskVFbqBuFBYsVVbRzHNQuahpAS0yDRsQkqmLEyf9+hQwdZsmSJ68DqQ7QDBw50bUNl9gS2bNkizZs3l19++cV1knnz5knXrl1d21CJQCYFCCpkTnPbtm0ydepUI5CkTlDxeqkTFkaMGCFHHXWU1y60QyBtAYIKadPREQEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAd8KEFTw7dawMAQQQMBfAqkEFdTKq05GcHoMHSIw5Qfi+un6SGHcKEnH1q31GMYceqJwYbScoIKGys7rmDFj5MYbb3Qd/JBDDpEVK1ZIzZo1XdtRmR2B0aNHy0033eQ6uNqjlStXhrM++u+Qa3MqEciIAEGFjDDGDaICgK+++qr89a9/lTfeeCOuzumN+nt/3nnnyQMPPCCHHnqoUzPKEai2AEGFahMyAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAr4TIKjguy1hQQgggIA/BTwFFfp1lMN7ldo/gOUzztECh5MTdJjAGMzcNy58YJpKl5uK1EkM+pSGuBMYCCqYlbJ2/+OPPxq/rV/9Nm+365lnnpFLL73UrQl1WRBQ+9KyZUtRf7fdrocfflhuvfVWtybUIZBxAYIKGSeNG3DhwoXy0EMPycyZM2Xnzp1xdXZvateuLddee63cc889stdee9k1oQyBagkQVKgWH50RQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBDwpQBBBV9uC4tCAAEE/CdQ7aCCeiRz4EC/STeoYB7PLqSgpjP9BniCCgos91ffvn1lypQprhOrD8t/8sknoj4Iy5U7AfVb1ZMFEOrWrSvffvutNGnSJHcLYyYEwgIEFXLzbfDZZ5/JyJEjRQXGduzYkXTSxo0by/Dhw2XAgAGchJNUiwapCBBUSEWLtggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggIA3gQ0bNsgLL7xgady5c2dRX1wIZFuAoEK2hRkfAQQQKBCBjAQVlEVcWCH83hwyMNeZy3U/uzJVl1iuytQVHk+dqBAXUlDl0fYLJi+SpdPLVInjVV5eLqFQyLGeCncB9Vu7vfxH7SOPPCJDhgxxH4zajAl8//330qpVK/n5559dx+zXr59MnDjRtQ2VCGRDgKBCNlSdx/zyyy/l/vvvl6lTp0pFRYVzw2hNx44d5fHHH5ejjjoqaVsaIOBFgKCCFyXaIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAqkJfPTRR7b/f/v33HOPDBs2LLXBaI1AGgIEFdJAowsCCCBQjAKeggr9O8rhvUpjPC4BgqpG5jZuQQXdwa6NURatSOGEBiOoMI2ggqbN1muPHj1kzpw5rsM3aNBAVqxYIfvuu69rOyozI9C/f3+ZNGmS62A1atSQZcuWSZs2bVzbUYlANgQIKmRDNfmYn3/+udx9990ybdo02bVrl2sH9TPiuuuukwceeEDq16/v2pZKBJIJEFRIJkQ9AggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAgggkLoAQYXUzeiRWQGCCpn1ZDQEEECgYAV8F1QwBxyUeglBBb9+87399tvSrVu3pMvr2bOnzJw5M2k7GlRPYO7cuXLyySdLpTnUYzPkhRdeKM8995xNDUUIZF+AoEL2jd1mUKfh3HbbbfLGG2+4NTPqDjzwQOPklRNPPDFpWxog4CRAUMFJhnIEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAgfQGCCunb0TMzAgQVMuPIKAgggEDBC3gLKnQKn6gQ/e3riUECLaTyBIl10YyBbXliWz2Ol1c9rrmtHi9cx4kKZpjs3p9xxhkya9aspJM888wzcumllyZtR4P0BDZt2iTt27eXr7/+2nWAWrVqyfLly+XQQw91bUclAtkSIKiQLdnUxn3llVfk5ptvlpUrV7p2VKcr3HjjjcbpCnXr1nVtSyUCdgIEFexUKEMAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQSqJ0BQoXp+9K6+AEGF6hsyAgIIIFAUAt6DCqXhIIJOAyTQ6OCAuVqXqaZeyhOGdH1rHtvcMDqPEVSYXmausdyXl5dLKBSylFOQmkBZWZl06NBBKioqXDs2bNhQFi1aJOo3dHNlXqB3797yj3/8I+nA119/vTz22GNJ29EAgWwJEFTIlmzq4+7YsUMeffRRue+++2Tz5s2uA3Ts2FHU3hFycmWi0kaAoIINCkUIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIBANQUIKlQTkO7VFiCoUG1CBkAAAQSKQ8BzUOH86IkKdiw6OOAlkGDX1m7MZGV6HN3ONDdBBY2Sm1f127bHjBmTdLKjjjpK5s2bJ3Xq1EnalgbeBSZOnChXXnll0g5NmjSRTz/9VBo3bpy0LQ0QyJYAQYVsyaY/7po1a2TQoEHywgsvuA5Sr14942e9l583rgNRWVQCBBWKart5WAQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQyJEAQYUcQTONowBBBUcaKhBAAAEEzAKeggr9OsrhvcInKqRymYMEphBBKkOk25agQrpy6fXbtGmTlJaWivqwa7JrwIAB8vjjjydrRr1Hgfnz50u3bt1k27ZtSXtMmTJFrrjiiqTtaIBANgUIKmRTt3pjz5w5U6677jpZv36960AXX3yxPPHEE7Lnnnu6tqMSASVAUIHvAwQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQCDzAgQVMm/KiKkJEFRIzYvWCCCAQNEK+CaooIMNiaEGp3KXHSOo4IKTpapXXnlFzjrrLE+jjx8/XgYOHOipLY2cBdauXStHHnmkp4DI6aefLmqPSkr0XyjncalBIJsCBBWyqVv9sX/44QdRgTIVWnC7DjnkEJk+fbq0b9/erRl1CBBU4HsAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQyIIAQYUsoDJkSgIEFVLiojECCCBQvAJZCyooUv2Z6MTwgR23U1uncrsxomUEFVxwslh11VVXyYQJE5LOUKtWLfn3v/8t6sPzXOkJbNmyRU444QRZsGBB0gEaN24sS5culf333z9pWxogkG0BggrZFs7M+JMnT5bBgweLOjHH6QqFQsYJOX369HFqQjkCBBX4HkAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQSyIEBQIQuoDJmSAEGFlLhojAACCBSvQFaDCmmy6lyDzigkHUY11J3CtwQVkoplpYH68Hznzp3ls88+Szp+/fr15Y033jBOBEjamAZxAjt27JCzzz5bZs+eHVfu9Eb9ZvSePXs6VVOOQE4FCCrklLtak3355ZfSu3dvee+991zH+dOf/iSPPvqo1K5d27UdlcUp8L//+79yzTXXuD78kiVLpF27dq5tqEQAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQiAkQVIhZcJcfAYIK+XFnVgQQQCBwAoEPKpjTDNGwAkGF/H0bqg8bHnPMMbJt27aki9h7773lzTfflNLS0qRtaRAR2Llzp1x22WXy3HPPeSK5/vrr5bHHHvPUlkYI5EKAoEIulDM3R0VFhQwfPlweeOABUT9/nK5u3brJjBkzpEmTJk5NKC9SAYIKRbrxPDYCCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCGRVgKBCVnkZ3IMAQQUPSDRBAAEEEBAJfFBBbSInKvjqW3ny5MnSr18/T2vaZ599jLDCoYce6ql9MTfatWuX9O/fX6ZMmeKJ4dhjj5X//ve/UqdOHU/taYRALgQIKuRCOfNzqJ8lKiS1du1ax8F///vfy0svvUT4zFGoOCsIKhTnvvPUCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCQXQGCCtn1ZfTkAgQVkhvRAgEEEEAgLJCJoEKlRI4yKDESA7lnVbObD1bgRIXc70HijDfeeKOMGTMmsdj2ffPmzeWtt96Sgw46yLaeQpHKykoZOHCgPPHEE544lKn6P0j23XdfT+1phECuBAgq5Eo68/OsX79eLr30Upk7d67j4A0aNJDp06dLjx49HNtQUVwCBBWKa795WgQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQyI0AQYXcODOLswBBBWcbahBAAAEETAJBDypEIhKRB9JhBYIKpg3O021FRYWcffbZMmvWLE8raNGihbz66qvSunVrT+2LqdHOnTvl2muvlQkTJnh67Hr16sm8efOkU6dOntrTCIFcChBUyKV25udSP4/uvPNOefjhh40Ald0MtWvXlqeeekquuOIKu2rKikyAoEKRbTiPiwACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACOREgqJATZiZxESCo4IJDFQIIIIBATCDoQQX1JJyoENtPP91t3rxZTjjhBFm4cKGnZTVq1Eiee+45fhO3Sevnn3+WSy65RGbPnm0qdb6tVauWvPDCC3LmmWc6N6IGgTwKEFTII34Gp1anJvTr10+2bt1qO2pJSYk89NBDcuutt9rWU1g8AgQVimeveVIEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEMidAEGF3Fkzk70AQQV7F0oRQAABBBIEMhFUSBiy6m2lESEQKQn/z3xVVlaK+hCjl0ufmOCtdWRETlTwIpubNuvWrZOuXbvKF1984WnCmjVryr333iu333671KhRw1OfQm2kAh4XXXSRZzv1d0qduqA+PMyFgF8FCCr4dWdSX9fixYvlnHPOkW+++cax89ChQ2XkyJGO9VQUvgBBhcLfY54QAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQRyL0BQIffmzBgvQFAh3oN3CCCAAAIOAtkKKuiQgprWHFRQIQV9eQkr6NYEFbRa8F6/+uor6datm6xZs8bz4o8//niZNGmS/P73v/fcp1Aa7ty5U0aNGiX33HOP/Prrr54f65FHHpEhQ4Z4bk9DBPIhQFAhH+rZm1OF0c4++2z5+OOPHSe54YYb5NFHH/UcUHQciIpAChBUCOS2sWgEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEPC5AEEFn29QESyPoEIRbDKPiAACCGRCIFtBBbU2FVYwhxT0ejlRQUsUz+vKlSvlxBNPlLVr13p+6Pr168vw4cNFfchVnbRQDNeiRYvk2muvdf3Qr53DiBEj5I477rCrogwBXwkQVPDVdmRkMVu3bpVLLrlEXnrpJcfxrrvuOnnssccIKzgKFW4FQYXC3VueDAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEE8idAUCF/9swcESCowHcCAggggIAngVSCCvo0BC8nIXia3NRIH7RQ4nB0gnGyQrRRsvkXTF4kS6eXmUa33paXl0soFLJWUJI1gbKyMlEnJWzcuDGlOdq3by9jxowx+qbUMUCNf/zxR7n77rvliSeekIqKipRWftddd8l9992XUh8aI5AvAYIK+ZLP7rzq59aAAQNkwoQJjhMNHjzYOFnBsQEVBSlAUKEgt5WHQgABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQACBPAsQVMjzBjC9EFTgmwABBBBAwJNAOkEFNXCysICnyU2NdFAhMrapInqrQxKReoc0Q7QtQQWrn19KlixZIj169JDvv/8+5SWdd9558sADD8hhhx2Wcl+/dti+fbuMGzdORo4cKSqskOp1++23Gyap9qM9AvkSIKiQL/nsz6v+nb7tttvkr3/9q+Nkf/nLX4yTchwbUFFwAgQVCm5LeSAEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEPCBAEEFH2xCkS+BoEKRfwPw+AgggIBXgVSCCmpMHRjIfVAh9kROpy7oFgQVtIQ/Xz/77DM544wzZNWqVSkvsFatWnL55ZeL+rDrQQcdlHJ/v3T47bffZOLEiUbI4Ntvv015WTVq1DA+DDxkyJCU+9IBgXwKEFTIp35u5h42bJhrGGHs2LEyaNCg3CyGWfIuQFAh71vAAhBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAoAAFCCoU4KYG7JEIKgRsw1guAgggkC+BVIMKep1OgQW7cl0W6Rs7DcEcOIi1KQmf1qBnUcGIaC+bskhNtEH4jQ5PEFSI+fn1buPGjXLxxRfLnDlz0lpi7dq15dJLL5WhQ4cG6oSFbdu2yVNPPWWEDL755pu0nr1hw4byj3/8Q84888y0+tMJgXwKEFTIp37u5h4+fLiowILdpYJWM2bMEHVKDlfhCxBUKPw95gkRQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQCD3AgQVcm/OjPECBBXiPXiHAAIIIOAgkE5QIRIe0AGBxGBBpFyHBtS0sRCCehdLHMQHEqzj6ZCC0SvWrSq8oMrDo0dewn/qOQkqVJH4+mbnzp1y3333yf333y/qPp1LfeD1j3/8o9x8883StWvXdIbISZ/vv/9exo8fL3//+99F3ad7denSRZ599tlAnyaR7rPTrzAECCoUxj56eYo777zTODXGru3uu+8u8+bNk86dO9tVU1ZAAgQVCmgzeRQEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEPCNAEEF32xF0S6EoELRbj0PjgACCKQmkGpQIRY6iCUHzIGDVGa3DSKEcwc6emDMEJsm6dBqbSqsQFAhKZWvGrz77rvSt29f+eKLL6q1rtLSUrnsssuMkxYOOOCAao2Vic7bt2+XV155RZ555hn5z3/+I7/++mvaw9aqVUvuuOMOueuuu0SdJsGFQFAFCCoEdefSW/f1119vBLTsejdv3lzmz58vzZo1s6umrEAECCoUyEbyGAgggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggg4CsBggq+2o6iXAxBhaLcdh4aAQQQSF0glaBCLKSg5oklCDIaVAiPrAMMqY6r17dgymJZNr3MFaO8vFxCoZBrGypzJ6D245577pHRo0dLRUVFtSZWYZXDDz9cevToISeffLJ069ZN1G/vzsVVVlYmc+bMkddff13eeust2bJlS7WnPeKII+TJJ5+Ujh07VnssBkAg3wIEFfK9A7mdf9euXXLxxRfL9OnTbSc+/vjjjZ+ZKozFVZgCBBUKc195KgQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQyK8AQYX8+jN7+NOj4Q9r6l9IjQcCCCCAAAKOAukFFWIhBTVwqoECvRjzv1R6DLsy3d7tNdIv8k8fQQU3KX/XLV26VAYNGiTz5s3L2ELr1KkjHTp0kGOOOUaOPfZYOemkk2Tvvfeu9vgqUPHhhx/K22+/Le+//7588MEHsmHDhmqPqwdo3Lix3HfffXLttddKzZo1dTGvCARagKBCoLcvrcWr02XUz131c9Luuv322+WBBx6wq6KsAAQIKhTAJvIICCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCDgOwGCCr7bkqJbEEGFottyHhgBBBBITyCVoILTDOaQQKRNfJAhUlYZDjTYlUdrbeJ1ic1VBs9ujFi4gaCC0x4FqVzt84wZM0R9eHXVqlVZWfoee+whjRo1EhUGUK/me1XWsGFD2bZtm/z000/y448/xr3qsp9//rnapz/YPVzt2rVl4MCBcvfdd8tee+1l14QyBAIrQFAhsFtXrYWvX79ejjzySPnmm28s49SoUcM4hUaFGbgKT4CgQuHtKU+EAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAL5FyCokP89KPYVEFQo9u8Anh8BBBDwKJCZoIJNykDMoYRYvV3QQC01FjYw3hmrN7c1HxQUX240jf5BUMGsEfT73377TZ588kkZMWKErFu3LuiPk3T96sO6F198sQwfPlwOPvjgpO1pgEAQBQgqBHHXMrPm+fPnS9euXUWdsJB4/e53vxN1ok6DBg0Sq3gfcAGCCgHfQJaPAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAK+FCCo4MttKapFEVQoqu3mYRFAAIH0BXITVFDri4QIzCED86oJKpg1uDcLlJeXy+OPPy6jRo0S9Vu5C+1SAYVevXrJX/7yF2nbtm2hPR7Pg0CcAEGFOI6ie/PEE0/IgAEDbJ/76quvNsJptpUUBlaAoEJgt46FI4AAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIICAjwUIKvh4c4pkaQQVimSjeUwEEECgugJegwptzy+NTqUCB+bTEsLvom/jwwaxcvMazScjxMpLqsaIlalTFuxPYoiV2/dbMHmRLJ1eZh7Kcq8+/B4KhSzlFPhXQO3ZhAkT5G9/+5usXr3avwv1uLLatWvLpZdeKn/+85+ldevWHnvRDIFgCxBUCPb+ZWL1Kpg1c+ZMy1AqyDhv3jz5wx/+YKmjILgCBBWCu3esHAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEE/CtAUMG/e1MsKyOoUCw7zXMigAAC1RRILagQCw6Ywwp2QQVdlri8WMggvsbupAVzW3O9U7kekaCClijM1x07dsi0adPkkUcekYULFwbuIRs0aCDqN4ffcMMN0qJFi8CtnwUjUB0BggrV0SuMvhs3bjROj1m3bp3lgdq3by8LFiyQmjVrWuooCKYAQYVg7hurRgABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABfwsQVPD3/hTD6ggqFMMu84wIIIBABgSyFVRQS7MLK0QOSTAHHiIPYQ4i6McyBxJUMEKNFztkIXayQ+I8BBW0YOG/fvzxxzJ16lR59tln5fvvv/ftA6sP3Xbv3l169+4t5513ntSrV8+3a2VhCGRTgKBCNnWDM/bzzz8vPXv2tF3wk08+aYS5bCspDJwAQYXAbRkLRgABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQACBAAgQVAjAJhX4EgkqFPgG83gIIIBApgS8BxXahKc0hwV02CBSptZjH0IIpwtMlw4VxIcQVIP4dpEueg6n+kgro9bUnaBCzKVY7ioqKuSDDz6QWbNmyezZs2XRokXh70fz90/uJZo0aSKnnnqqnHbaaXLKKaeIes+FQLELEFQo9u+A2POfe+658uKLL8YKonf77ruvfP755wS6LDLBLCCoEMx9Y9UIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIOBvAYIK/t6fYlgdQYVi2GWeEQEEEMiAQCpBBfOpB+YPgetyc1n80mIpAh1UUPXx7WNtYn3NHzS3q4+1VHd6bIIK8S7F+O6HH36Q9957T959913ja/78+fLrr79mleKggw6S4447ruqrTZs2UqNGjazOyeAIBE2AoELQdix76/3qq69E/Zzcvn27ZZL7779f7rzzTks5BcETIKgQvD1jxQgggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggg4H8B9UtczzjjDMtCb7nlFrn55pst5RQgkGkBggqZFmU8BBBAoEAFvAcVSquCALFfVB8JEqQSVFCMKlCQOIb9iQqqtQ4rJA8q6LEJKigJLrOACil88cUXsmbNGvn222+N18T7TZs2mbvE3deqVUv2228/ad68ubRo0cJ4Nd///ve/l6ZNm8b14Q0CCFgFCCpYTYq5RIURHnjgAQtBo0aNRAUZGjRoYKmjIFgCBBWCtV+sFgEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAS8CBBW8KNEGAQQQQEC8BhUO71VqChckwtmHCfQJB7GTE9zCBrExYv3M8+h6VVbiEHaItF8wZbEsm15m7my5Ly8vl1AoZCmnoHgFVJhhy5YtsnnzZuO1Tp06ssceexhf9erVC3/PuX3/Fq8bT45AKgIEFVLRKvy26udty5YtZcOGDZaH5VQFC0kgCwgqBHLbWDQCCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAKuAgQVXHmoRAABBBDQAtkKKpg/0x0LKqhZnT7sHQsi6A+Ex05dUP2s9UZpfCNVJAQVDAb+QAABBHwnQFDBd1uS9wWNHTtWBg8ebFmHOqXm66+/JlRokQlWAUGFYO0Xq0UAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQMCLAEEFL0q0QQABBBDwfKJC2/NLXbRUiCA+gKCDCpEcQSxkkNguNqi5jSqNH88cVFB1avxYRiG+L0GFmCp3CCCAgJ8ECCr4aTf8sZbt27fLwQcfbPz3SOKKnnrqKbnyyisTi3kfIAGCCgHaLJaKAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIICARwGCCh6haIYAAggUu4DXExUiQYX4QEDMLhYqsA8oxOpjgQNzmRrJbmxzG3O9uVyvIlZPUEGb8IoAAgj4S4Cggr/2wy+r+dvf/ia33HKLZTkdOnSQRYsWWcopCI4AQYXg7BUrRQABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAwKsAQQWvUrRDAAEEilwge0GFWHAg/nQEL+V6U8yBBKd+uq16jbQhqGA24R4BBBDwjwBBBf/shZ9WsmnTJmnRooWo18Tro48+ki5duiQW8z4gAgQVArJRLBMBBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAIEUBAgqpIBFUwQQQKCYBVILKigpc2BAy5kDBbpMt0us0+W6na5PLFf1uk63Va+qnV25rhMhqKAsuBBAAAH/CRBU8N+e+GVFgwcPlrFjx1qWc91118m4ceMs5RQEQ4CgQjD2iVUigAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCQigBBhVS0aIsAAggUsUDqQQU7LK8hA9XXrq0q1+EDc70uU/Xmy6lNpJyggtmKewQQQMA/AgQV/LMXfltJWVmZtG3b1rKsJk2aiPpvlVq1alnqKPC/AEEF/+8RK0QAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQCBVAYIKqYrRHgEEEChSgeoHFcyhATOil5CBU3s9ppcxzG0IKphFuUcAAQT8JkBQwW874q/1HHnkkfLxxx9bFjVnzhzp3r27pZwC/wsQVPD/HrFCBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEUhUgqJCqGO0RQACBIhXwHlRok4KQCg/osEGybjpoYG5vV2YeR9erMnO/SBtOVDBbcY8AAgj4R4Cggn/2wo8rGT16tNx0002Wpd1www0yZswYSzkF/hcgqOD/PWKFCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIpCpAUCFVMdojgAACRSqQdlBB5wPMmQHDUBfoBm6wuq1qY26vy8NlulgXxc2R2M+oFIIKEQf+RAABBPwmQFDBbzvir/WsXr1aDjzwQMuiWrVqJStXrrSUU+B/AYIK/t8jVogAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggECqAgQVUhWjPQIIIFCkApkNKpjTBDph4Abr1F6XOwUV1JimNglTEFRIAOEtAggg4BMBggo+2QgfL6Ndu3aybNkyywq/+eYbadGihaWcAn8LEFTw9/6wOgQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBNIRIKiQjhp9EEAAgSIU8B5UKDXpOIUQdHhANU1so+qiZerF3FQ1jyvQfXUj/d5omOSPkvCJCotk2fQy13bl5eUSCoVc21CJAAIIIJBZAYIKmfUsxNFuvvlmeeSRRyyP9s9//lMuueQSSzkF/hYgqODv/WF1CCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIpCNAUCEdNfoggAACRSiQXlBBQdmFB3SwILHeVF5p6mcqdg8qJI6n3ttdkQEJKtjZUIYAAgjkX4CgQv73wO8r+Pe//y3nnHOOZZmDBw+WRx991FJOgb8FCCr4e39YHQIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAukIEFRIR40+CCCAQBEKpBdUMIUN4szMyQNzG1O5DiqYiiJD6AKHfrbBiLjJw28iYxBUSHThPQIIIOAPAYIK/tgHP69iw4YN0qxZM8sSu3XrJm+99ZalnAJ/CxBU8Pf+sDoEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQTSESCokI4afRBAAIEiFEg5qKCCBjpTEOelCsN1Kmdg1JsbRctV+xJdrhomXIlFVW1Vu+gYurvtIiIDLJiyWJZNL0sYPP5teXm5hEKh+ELeIYAAAghkVYCgQlZ5C2bwFi1ayJo1a+KeZ6+99pIffvghrow3/hcgqOD/PWKFCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIpCpAUCFVMdojgAACRSqQUlBBn4agrKoCA6Y3cfWmBk7l5lMSEkMKxrBexlAN9UVQQUvwigACCPhRgKCCH3fFf2s67bTT5NVXX7UsbOPGjdK4cWNLOQX+FSCo4N+9YWUIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAgikK0BQIV05+iGAAAJFJuA9qNAmclqC8jHlByJc0QK3QIIOIhhN1R+6IDJC4luj1O5EBVVRNUa0r/ESG48TFcwu3COAAAL+ESCo4J+98PNKrr/+evn73/9uWeKCBQukU6dOlnIK/CtAUMG/e8PKEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQSFeAoEK6cvRDAAEEikzAU1Chb0dpe344qBDNI0SITG/iAgoa0FRvTiHoPIG52uiiC3QDVajL1L2p3HSraozL1JSggkbhFQEEEPCXAEEFf+2HX1fz0EMPydChQy3Le/nll+XMM8+0lFPgXwGCCv7dG1aGAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIBAugIEFdKVox8CCCBQZAIZDSqYwgKeQgZJ25sbmNIJptu47Yo2J6gQp8IbBBBAwDcCBBV8sxW+XsjkyZOlX79+ljWq8j59+ljKKfCvAEEF/+4NK0MAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQCBdAYIK6crRDwEEECgyAc9BhV7hExXiLh0iCKcGzMEBXWy0VW/MlQlv49qqDjbt7coShlQ9jSs6HkEFDcIrAggg4C8Bggr+2g+/rubFF1+Uc88917K8sWPHyqBBgyzlFPhXgKCCf/eGlSGAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIJCuAEGFdOXohwACCBSZgKegQr+O0vZ8FVQwJwts0gI2RQanUzencr0H5npVpsdPLNdhhmi9EVSYUaZHsX0tLy+XUChkW0chAggggEB2BAgqZMe10EZ9/fXX5ZRTTrE81sMPPyy33nqrpZwC/woQVPDv3rAyBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEE0hUgqJCuHP0QQACBIhMITFBBhxTU/sQFFUxvKiONCCoU2Tcxj4sAAoERIKgQmK3K60Lnzp0r3bt3t6xh5MiRMnToUEs5Bf4VIKjg371hZQgggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCKQrQFAhXTn6IYAAAkUmkF5QwZwaMIE5FMcHC8LtdTtTxqCqzDSccavb2PWpahtuFA0pqCKCClUw3CCAAAK+EiCo4Kvt8O1inE5UGDVqlNxyyy2+XTcLswoQVLCaUIIAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggEDQBQgqBH0HWT8CCCCQIwHvQYXSuDCA7fJ0qEBV6mCBujfKzZXRBpY2qlxd0bam8EH8GKaOpttIX4IK2oFXBBBAwG8CBBX8tiP+XM+LL74o5557rmVx48aNk+uuu85SToF/BQgq+HdvWBkCCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAALpChBUSFeOfggggECRCeQmqJAYUogiW4IIGt8uqGAew5ROMN3q3pyooCV4RQABBPwlQFDBX/vh19VMnjxZ+vXrZ1ne1KlT5fLLL7eUU+BfAYIK/t0bVoYAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggEC6AgQV0pWjHwIIIFBkAp6DCj3beJNReQKb8ICUmIMGqk1Co7jq8BvX+uhSEobQCySooCV4RQABBPwlQFDBX/vh19U89NBDMnToUMvyZs+eLaeeeqqlnAL/ChBU8O/esDIEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQTSFSCokK4c/RBAAIEiE/AUVOjbUdqenxBUSAweKLfEcEEqlubx7MYxBxkcAgp6OoIKWoJXBBBAwF8CXoIKZ511ljRt2tRfC2c1ORV4//33ZcWKFZY5zzvvPGnUqJGlnAL/CqxcuVLeffdd1wUuWbJE2rVr59qGSgQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBDwjwBBBf/sBStBAAEEfC3gu6CCXUhBC+qwAkEFLcIrAgggECgBL0GFQD0Qi0UAgWoLEFSoNiEDIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAgggkFMBggo55WYyBBBAILgCaQcVfPzInKjg481haQggUNQCBBWKevt5eARsBQgq2LJQiAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAgG8FCCr4dmtYGAIIIOAvgZwEFUr0UQjhZ3c7MaG6NNF5FkxeJMtmlLmOVl5eLqFQyLUNlQgggAACmRUgqJBZT0ZDoBAECCoUwi7yDAgggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACxSRAUKGYdptnRQABBKohkJOgglqfDisQVKjGbtEVAQQQCLYAQYVg7x+rRyAbAgQVsqHKmAgggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCGRPgKBC9mwZGQEEECgogZwFFXKotmDKYk5UyKE3UyGAAAJeBQgqeJWiHQLFI0BQoXj2midFAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEECgMAYIKhbGPPAUCCCCQdQGCClknZgIEEEAAgagAQQW+FRBAIFGAoEKiCO8RQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBDwtwBBBX/vD6tDAAEEfCNAUME3W8FCEEAAgYIXIKhQ8FvMAyKQsgBBhZTJ6IAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAkUuUFZWJv369bMoXH311aK+uBDItgBBhWwLMz4CCCBQIAIEFQpkI3kMBBBAIAAC06dPl/79+wdgpSwxHwKVlZWydetW16nr1Kkj6ourcAQ++OADKS0tLZwH4kkQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQACBLAt89NFHctRRR1lmueeee2TYsGGWcgoQyLQAQYVMizIeAgggUKACBBUKdGN5LAQQQAABBAImsGHDBmnWrJnrqkeMGCF33HGHaxsqEUAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQKGQBggqFvLvBeDaCCsHYJ1aJAAII5F2AoELet4AFIIAAAggggEBYgKAC3wYIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggkFyCokNyIFtkVIKiQXV9GRwABBApGINNBhcrKSsOmpKQkzkgVJxTF1ZvfRIewtPcyhpp/4dNLZNmMMvOQlvvy8nIJhUKWcgoQQAABBBBAID8CBBXy486sCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAALBEiCoEKz9KsTVElQoxF3lmRBAAIEsCGQyqKBDCmqZ5qCCDh5EypM/hG5vDjboMrcx9PwLn14cDip84joRQQVXHioRQAABBBDIuQBBhZyTMyECCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAQAAFCCoEcNMKbMkEFQpsQ3kcBBBAIFsCmQwqqDXqsIA5qBApjzyBOXwQKbH+qUMJiW2dys0jcKKCWYN7BBBAAAEEgiNAUCE4e8VKEUAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQTyJ0BQIX/2zBwRIKjAdwICCCCAgCeBTAcVkk3qJWxQ3TEWTFEnKpS5DsOJCq48VCKAAAIIIJBzAYIKOSdnQgQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQACBAAoQVAjgphXYkgkqFNiG8jgIIIBAtgTyFVRQz5N4YoLXZ9RhB6cxCCp4laQdAggggAAC/hEgqOCfvWAlCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAL+FSCo4N+9KZaVEVQolp3mORFAAIFqCuQ6qKCWq4MG6QYV9BhO/QkqVPObgu4IIIAAAgjkQYCgQh7QmRIBBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAIHACBBUCt2UFt2CCCgW3pTwQAgggkB0BL0GFzn07yuHnt4lbQGU0bVCSkBbQ5eHzEqraJzSpKtdtE8eoahC+8dLG3F7dE1RIFOE9AggggAAC/hcgqOD/PWKFCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAL5FyCokP89KPYVEFQo9u8Anh8BBBDwKOA1qNC2ZxsxBw50gEAFEnR5JLtQGZ3Ze1BBdXAKK+h5nOrtHpOggp0KZQgggAACCPhbgKCCv/eH1SGAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAII+EOAoII/9qGYV0FQoZh3n2dHAAEEUhDwGlRIPFFBTRE9VCEhqGCdXAcZrDX6xIRY2MG+jQoy2NXYlxFUsHehFAEEEEAAAT8LEFTw8+6wNgQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABvwgQVPDLThTvOggqFO/e8+QIIIBASgJeggpH9O0obc9v4zhuYmAhsaGuV+VOgQPdJll94hj6xIXInJE0w8KnF8uyGWWRIoc/y8vLJRQKOdRSjAACCCCAAAK5FiCokGtx5kMAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQCKIAQYUg7lphrZmgQmHtJ0+DAAIIZE3Ab0EF9aB2YQUdZEisJ6iQtW8NBkYAAQQQQCCnAgQVcsrNZAgggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACARUgqBDQjSugZRNUKKDN5FEQQACBbAqkGlQwBwb0uoxzDCKHGeiiqlfVvqo+fB/+fy5BBFUbuUoS0gp286qWauxYL2N04USFiCF/IoAAAgggECQBggpB2i3WigACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCQLwGCCvmSZ14tQFBBS/CKAAIIIOAqkEpQIT4soOMBJbbBAzWpPu3AHDrQZareqVzVqSu+XpXE5lTv1GXOM+ixFz69RJbNKIs0cPizvLxcQqGQQy3FCCCAAAIIIJBrAYIKuRZnPgQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQACBIAoQVAjirhXWmgkqFNZ+8jQIIIBA1gSyFVTQoQG18PjAgQ4bOJfHHjYWgoiEJHTf2PENBBViWtwhgAACCCAQZAGCCkHePdaOAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIJArAYIKuZJmHicBggpOMpQjgAACCMQJpBJUiOtoehN/0oKqqIwLJ5iaVp2yECmLDxxYx4n11IGExMCCLlctdf+FTy/mRIUYHXcIIIAAAggEQoCgQiC2iUUigAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCORZgKBCnjeA6YWgAt8ECCCAAAKeBDIfVIicemA+RcG8EPNJC+EzFaqqdOBAhw2qKqI3ul69NY9hnkf3JaiQqMd7BBBAAAEE/C9AUMH/e8QKEUAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQTyL0BQIf97UOwrIKhQ7N8BPD8CCCDgUaC6QQUdDohNl52gghpfhxXsggrmdRBUiO0GdwgggAACCARFgKBCUHaKdSKAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAII5FOAoEI+9ZlbCRBU4PsAAQQQQMCTgJegQue+HaRtz1Kb8VQoIXYqgmpgDRPE14fPQzCNU2Jqr4qt48W3j3S1O0UhNmilRIIKn8SKbO7Ky8slFArZ1FCEAAIIIIAAAvkQIKiQD3XmRAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBAImgBBhaDtWOGtl6BC4e0pT4QAAghkRcB7UKFNeH5z6CA+cKAXZw0qqBr7fvGBA/vxUgsqRMYgqKB3g1cEEEAAAQSCI0BQITh7xUoRQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBPInQFAhf/bMHBEgqMB3AgIIIICAJwHvQYXEExXsgwWxoIKaXrexDyqoAINqX2k0021VP93eXKbK9WXup8vUa6Q9QQWzCfcIIIAAAggEQ4CgQjD2iVUigAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCORXgKBCfv2ZPfwJz8rwBQQCCCCAAALJBLwFFTpK257qRIXwPzC2wQI9iw4Y6Pd2r+Z/npza6zaRQIIaxf1ftVh71TYSVChTt45XeXm5hEIhx3oqEEAAAQQQQCC3AgQVcuvNbAgggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACwRQgqBDMfSukVRNUKKTd5FkQQACBLAqkElTQpyWo5djn4ZyCB+YH0KECVebUPtKmxDShc1DBOh5BBbM39wgggAACCARDgKBCMPaJVSKAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAII5FeAoEJ+/ZmdExX4HkAAAQQQ8CiQTlAhEhowBwT0ZE7BA12vXs397NrH1+usgnNQwTxmZDyCCmZv7hFAAAEEEAiGAEGFYOwTq0QAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQyK8AQYX8+jM7QQW+BxBAAAEEPAp4CSoc0bejtD2/TcIpCrGQQSxMEB8yiF+Crov1iw8txLeOvDO3VSV2Y5j7ReoXPr1Els0oM1dY7svLyyUUClnKKUAAAQQQQACB/AgQVMiPO7MigAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCARLgKBCsParEFdbUhm+CvHBeCYEEEAAgcwK5CaoYP4nyRw+MJfbPZdTW3O5uZ8OKiwOBxU+MVdY7gkqWEgoQAABBBBAIK8CBBXyys/kCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIBESCoEJCNKuBlElQo4M3l0RBAAIFMCngNKpT2bJ0wrV1Y+l4AGgAAQABJREFUQAcPvNbp9glDG2+9jmHuS1DBrME9AggggAACQRIgqBCk3WKtCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAL5EiCokC955tUCBBW0BK8IIIAAAq4CXoIKnft2kLY92ySMYw4S6MCBuSyhedVb3VYVeGlf1dF0Yx7DVBwdb+HT6kSFMnOF5Z4TFSwkFCCAAAIIIJBXAYIKeeVncgQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQACBgAgQVAjIRhXwMgkqFPDm8mgIIIBAJgUIKmRSk7EQQAABBBBAIF0BggrpytEPAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQKCYBAgqFNNu+/NZCSr4c19YFQIIIOA7AYIKvtsSFoQAAggggEBRChBUKMpt56ERQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBFIUIKiQIhjNMy5AUCHjpAyIAAIIFKaAt6BCR2nbs00CQKXpfUn03lxmqhZdL1JZGWtTUhIrD9dUddBN4utVtW5j7lfVrap+4dOLZdmMT8wVlvvy8nIJhUKW8lQKfvzpB/n11+2OXfbeq5nUrl3bsT7dis2bf5EtWzcn7V6jRk1p1nTfpO1ogEA2BCord8n6DWvj/s6b52ncaG+pW3c3cxH3aQhsLd8imzb97Niz3u71Zc89GzrW57pi3frvHL8nJPxvxb777O+4pHXr/1+47y7HelVRp05d2atxE9c2uahU3/u7du1MOtXeezUN/ztRJ2m7TDRQdt+t/Vb+39o1or5vtm7dIuXbwq/R+19/+1Vq16od/ntZV+rW2c34+1mvXn1puve+0rTJPtIs/FWv3h6ZWIrjGAQVHGmoQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAoEqAoEIVBTd5EiCokCd4pkUAAQSCJpBeUEEHBvTT6uBAYnlifXWCCuax9Xx6fP0aaZOLoMLGH7+X8U+NCn8Q1flDs9f0HeL6oVu96lRev/9hnUz6x3jZtr08abcDD2gpfS4ZkLQdDRDIhsD8Re/JK6/+y3Hoyy68Sv4/e/cBJkWV7338PwmYIQx5hpyRJEkQERUQI4gKiCCSEVSUVXe97q5uuPfddd1kzoJIVkAQUBAUEAwIguScc85hCBN46zTUUN1dqcPMdM9867ljd59Upz7VM9zn3vOrU7tmPct6KtwJLF76vcyZN8OycWKRJBnc/xkpVbKMZZvcqvj5l4XyzfwvLU+nwlV/fuFfpvW79+7Q/va9a1pnLIyNjZU+PYaI+vuXV8evKxfLV7M/dzy9Cig8NfgFSc7BIMkpLcSybccmz8/2nVvkwoXzjvOya1CsWAmpo/3e1q3dQGrVqBv2kAVBBTt96hBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEELgisHfvXvnwww/9OG6//XZp3769XzkFCIRbgKBCuEUZDwEEEMinAoEHFa4FBvSdDxSN1+YIflbewQLvXRX8GjsUeI+lGvuOlxtBhf3aU6mHj37Tdq7hDiqcOnVCPh73jqgdFZyOcmVTZWDvp6RIkdB2jXA6D/UIWAksXf6TzPrmC6tqIahgSRNQhVNQQQ1WvlwFeazvsLAvKg9komqR/LiJw213RLALKqhzqZCDCjs4HYmJSTKk37NSsmRpp6Zhr1eBitETPnCxm0KM9OjaT+rVbRT2OagBN21ZJwt/+lYOHNybI+OrQePi4qWGFghpUK+xNKzXxLObRagnI6gQqiD9EUAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQACBnBcgqJDzxpwBAQQQyBcCgQUVzEMKOkSMV1rhWlstxqA38XrVAwaeWq++ejP3Y+g91OuKsStlzefrjUV+79PS0iQxMfhF/LkdVEhLOysjtaeJq50cnI7k5FIyqPfTUrx4slNT6hHIMQGCCjlG6zWwm6CC6lD/usbycJc+2jvzv8deg4b5w4mTx2T4qDcdd4JxCipcvpwlEyaPlK3bNzrOsHy5VBnUZ1hYFs87nuxqA7V7wfBRb8g57e+109H+tnvktpvvcGoWcP2WbRtkwQ/fyP6DewLuG0qHQoUKS8P6TaR541ZSuVK1oIciqBA0HR0RQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAIFcEyCokGvUnAgBBBCIboHcCSooI//FsdlBhStJBRPI4IIKakeFtVPyT1Dh0qWLMmrC+66ejJ2UVMyzk0KZ0uVMPCmKBoHjJ47KmnXLJe38Oe2p7FlSuWI1adyoubZrSWw0TD97jgQVsily9I3boIKaRE4tjre7wPT0S/Lx2Lfl0OEDds08dU5BBdXo4sULMmLM23L02CHH8a6r01B6duuvtfP/98exc4AN0tPTtTDZO3Lw0D7Hng3rN5WHHujt2C6QBmonh2/nfyV79+8KpFuOtC1XNkWaNb5RWt/YNuDxCSoETEYHBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAg1wUIKuQ6OSdEAAEEolPATVCheb+mcn23BiYX6L34Uw8eGBuabZRw+Wr+wLvOeywRY0hBjWher4+ln1Pt6qCCCms+X6cXmb5Gy44KmZkZMm7SCNm5a6vpdRgL1ROt+/V6QiqmVjEW8z6KBNZtWCnTZ00UtejZeKh7+ujDg0QFUaLlIKiQO3cqkKCC+jv6yEMDpG5ts7/nOTPfydPGyvqNq1wN7iaooAZSYZ4Ro99y3KFBtb1V27Xgdm33gpw+Pteuc52L66yQWtkTJouPTwjblNR34BstpKB2nIik469/+G/A0yGoEDAZHRBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAgVwXIKiQ6+ScEAEEEIhOAbdBhUZdG2hPdDdeo9cHT4VZUEFVGPsZgwXGcu8gwrWQgt5eBRCuHf71V85zpU1+CSqoRadqke+GTWuuXbrFu7i4OOnV/TGpWb2ORQuKI13g2PEj8uEnr/mFFPR516vbSHp07a9/jPhXggq5c4sCCyqIFC5cRB7rO0zKlknJ8Qn++PN8mbdwluvzuA0qqAF3aOGtcRM/8uw64nQCtXuB2sUgp44fFs2V+d/Pdhy+WLESMqTfM1K8eLJjWzcNMjLSZcbXkz07sLhpn9ttCCrktjjnQwABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEckeAoELuOHMWBBBAIOoFwhlUULsg6MECI4wxY6DXG8uutNWDCNdCCKr8Wnu93lN6pYtFfX4JKnypLUBdvmpJ9rVavVEhjm5qIW69JlZNKI8CgbkLZspPi7+znenvn/2bFCmSaNsmUioJKuTOnQg0qKBmVbpUWRmsLZjPye/Slm0b5NPPR2p/w73/ptupBBJUUOMsW7FIZs6Zajekp07tXjCw99NSIbWSY9tAG2zask4+mzJK62Z/nfHx8dK/11CpVLFqoKcwbX/y1HGZOHWUHDy037TebaH6DhQrWlyKaru1qF15Ll66IOfPp0ma9qNes7Iy3Q7l146ggh8JBQgggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAQL4QIKiQL24jF4EAAgjkvICboMIN/ZtJo671DaEBq3npYQKzBZuqzqpcjXcl5GAVYNAXu/rXq776edV7kfwQVJi3YJb8uHj+lQty+G/Hu7pKy+Y3O7SiOtIFJkz+WNTibrtjQO+npGrlGnZNIqaOoELu3IpgggpqZrVr1tN2YRmk7Xjj/fczHLNWu4OMGPOWXLhwPqDhAg0qqMFnfTNVli5f5HieEiVKenYzKKotyg/XceToQe0635ZLly46Dtml8yPSuOENju3cNFC+I8e+o4UJzrlp7tVGhVTq1Kqn/dSXalVqigpxWB+X5djxo7J3/y7Zu0/70V4PHT6o/e8CWdZdDDUEFQwYvEUAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBPKRAEGFfHQzuRQEEEAgJwXcBxUaeD0Z23xtq3HBqzGU4FyuBxHUtXqPfaWvU73RKNqDCj//slC+mf+l8ZIs37e95S5pp/1wRL/AlOnjZO2GlbYX8sTA30lK+Qq2bSKlkqBC7tyJYIMKanZtbmovd7TrFNaJqkX7w0e/JUePHQp43GCCCllZWTJu0nDZsXOL4/mqVKou/Xo9KXFxcY5tnRqcv5Amw0e9KSdOHnNqGlZntcuBCoEcP3HU8bzXGsRIo/pN5LY2d0i5sqnXioN4p+7vhs1rZNXaX2Xnrq1e/3uB73AEFXxF+IwAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCOQPAYIK+eM+chUIIIBAjgvkTlBBXYYKHBjDC3qZetVqLl+rCyyooHobgxDRvaPCqjXLZNrMiUpEXZjtoXZRULspcOQPgSXLfpTZc6dZXkyhQoXl98/+TWJjYy3bRFIFQYXcuRuhBBXUDLs90FtbxN40TJO9LJ9NGSWbtqwLarxgggrqRCo0MEILR7hZvN+0cUt5oGOPoOand1LhiPFaOGK7i3BE3doNpGe3AWHZuSIzM1PGfvah7NqzXZ+K46vaOaND23slNaWSY9tAG5w+c0rWrFsuK9cs1YIph/26E1TwI6EAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBDIFwIEFfLFbeQiEEAAgZwXcBNUaN6vqTTq2sCw0PKyFiy4MrcroQI9KHCt3Gnm3v28gwpmfWOy0wvO51A7Kqydst5smOyytLQ0SUxMzP4c6Jv9B/ZoTw1/07bbkP7PSYVU94tDN29dLxOnjhK1CNbpaFiviWeB8TUXpx7UR7pAZmaGfPjJG3Lk6EHTqd53z0NyQ9ObTOsisZCgQu7clVCDCgkJCTKw9zBtIXvFkCe84MdvZKH2E+wRbFBBnU/t4DBizNty8eIFx9Pf3eF+uanlbY7trBrMnjtdliz7wao6u1ztXvBY32GiQkbhOKbN/ExUmM3NER+fIA926iENwxZCsTvrZVm3cbXn3h85em0nDYIKdmbUIYAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAAC0StAUCF67x0zRwABBHJVILiggnewQF8sb9wVwc1F6P1UW6e+gbSNxqDC7j07ZOzEjyQjI92Rrmb1OtKr+2MSFxfn2JYG0SVwRntC+RdffSo7dm3NnrhaSH5n+86idtCIpiPagwo//7LQ83fp5lbtIpo91KCCurjk5FIypN8zkpRULOhr3bh5rRa0Gq31d94NxuokoQQV1Jhbt2+UCZNHavfNPuwVExMrjz78mNSqUddqKpblK1b/IjNmTbKs1ysSE5NksGZaqmQZvSikV/V9/Gb+l67GKFE8WdvFYWBAQTlXAzs0Uv+Or92w0hNYOHb8iBBUcACjGgEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQiFIBggpReuOYNgIIIJDbAsEEFXxDBXqIwLfc6Vqu7argvEuCfg61CFbfzcFq/GgLKhw6vF8+Gf+eqyeBV0ytIv16PRG2J3RbGVKetwInTh7TdlY4JEmJRSWlfAVJSCiUtxMK4uzRHFT4afF3MnfBTGnUoJl0u//RIK4+97qEI6igZlutai3p2/NxiY2NDXjy6rs6YsxbcunSxYD7GjuEGlRQY7n1KFIk0RMkKF2qrHEKtu/37Nspoye8L5mZmbbtlGGfHkOkerXatu3cVp5LOytvffCKK9+KFarIIw8NlGJFi7sdPuztVFBk+84tWhDkuoDHPnz4sKSkpNj2e/nll+XFF1+0bUMlAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAQM4JEFTIOVtGRgABBPKVgJugwg39m0mjrg0sdz24EjhQuyJ401wLF+jl3g2M7Z3GMIYgrNrqZ4mmoIJakD5y7Dty9twZffqWr2VKl5OBvZ8K6annloNTgUCYBaI1qPDDz/Nk/sKvPRr5JaiQmlJJDh7a53iHWzZvIx3v6uLYztjgwoXzMnz0m3L8xFFjsel7Fbo5dPiAaZ0qDEdQQY2jdjxQOx84HWXLlJfH+v5GChcu4tRUTmu7nQwf9Yarv9Wd7u4mLZq1dhzTbYNZ33wh6vfJ6VC7N6hdHNRuDtF6EFSI1jvHvBFAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEECgIAkQVChId5trRQABBEIQyKmggn9IQZ/ktbCCWVBB2zBB/U/2oY9jFlRQjYxj6J2iJaigwgkqpKDCCk5H8eLJMqj305KcXMqpKfUIRIRANAYVFv70rSz4YU62X34IKsTHJ8jTg1+Qj7RF9mnnz2Vfm9Wb++99WJo1udGq2qtc/V2eMPlj2bp9o1e52YfWN7aVoknFPDtVmNWrsnAFFdSOB2M++0B279lhdars8to160mv7oNE/7cmu8LwJiMjXUaOe1cOHNxrKDV/27L5zVrYo6t5ZRClKgDy7vD/SFaW/S4OKmwxqM8wKVfWfjeCIKaQq10IKuQqNydDAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQSCEiCoEBQbnRBAAIGCJ+A+qFDfNBSgxDw7HPgEDK6Ux/iAGiMI3iEDq10S1OJRY0gh+3xXR47WoIJ6CvmoCe/ZPl1cxytSJNGzk0K5sql6Ea8IRLxAtAUVvtMCCt9rQQXjkV+CCi89/4rs2LVVxk38SFvwnmW8RL/3cXFx0r/XUKlcqZpfnW/BvAWz5MfF832L/T5Xr1Zb+vYcIouWLMyVoIKaQFraWW2nh7fk5KnjfvPxLbi5VTu5s/19vsXZn6fOGC9r1q/I/mz1poZ2nb17DNECF7FWTQIunzxtrKzfuMq2n/p38pGHBkqdWvVt20VDJUGFaLhLzBEBBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEECroAQYWC/g3g+hFAAAGXAu6CCk2lUdcGXkGFa0+fvuxV7vK0nmbBjnEl1HAlBOEbYlADR/qOCurp3GM/+0h273V+2ndCQoL06fm4VKlU3WPGfxCIFoFoCirMW6gtuP/Zf8F9fgoqqO/N4qU/yJx50x2/QsWKlZAh/Z+V4tqr1bFOWzz/ubaI3ulILlFShgx4TpISi8pPi7/LtaCCmtehwwe0nRDekUuXLjpNU7rc94g0bnSDXzunOesdSpUsI4P7PyOJRZL0opBfjx475NlNwWmg5k1bSed7ujs1i4p6ggpRcZuYJAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggUcAGCCgX8C8DlI4AAAm4FQg8qqJ0RvHdKcHvua0GFwMZw6hfJQQX1NPOJU0fJ5q3rHZnUU7l7dhuQ50/Jvnjxgpw9d0bOnTurbZ8hUjSpmBQrWlwKFy7ieA35scE57UntJ04cEy2iI6WSS4ta1M3hLxBqUCEzM1POnD0lZ86c9gxeMrmUFC+urH13avE/dyAl3373lfak/wWmXfJbUEFd5BdffSqr1/5qer3GwkoVqsqA3kMlLi7eWOx5f+jwfvl47NuSnp7uV2csiI+P13aDeVoqpFb2FDst+o+NjZM/v/Av4xAhv9+0ZZ18NmWUNo79v1PqOgc8OlQqVayafc4t2zbIp5+PdPw3Tv0tHNRnmJQrm5LdNxxv1G4VatcKuyM+PkF+88QfbUMldv0jrY6gQqTdEeaDAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAgj4CxBU8DehBAEEEEDARMBtUKFhlwZ+vT2BAW3tp1qwHeyhxggm6KCHFcz6Rm5Q4bJM+2qirFq7zAVXjPaE756mT/h20TmkJidOHpNNW9bLpq3rZO++nZKRkWE6XqFChaVGtdpyXZ2Gcl3tBpKkBRicDjXWD4vmyqX0S5ZNa9WoK7Vr1rOsd1uxZ+9OWb9ptW3zZo1vlPLlUm3bbNuxSVasXirHTxzRfo6JCm4Yj4SEQlK6VBlRT1QvW7q8qMXtKeUrGJu4eq9sftIWJl/wGV/vXKVSNWlQr4n+MaRXtavHQW2x+bHjR+TChQvaOc97rsvs98nNieK1Rd4d2nX0ahpMUOHgoX2yZv0KWb9xtZw8dUIbz/tvi1r4XqpkWWncsLnc0OymkJ9eP2feDG2Xge+95m38UKZ0uYCCQnd36Kx1D2+Qwjgfs/dq/uo6rA61kP2l51/JrlbfM7XLwIGDe7PLrN40vb6lPNCph1f1+fNp8tHoN+TkyeNe5WYfHuzUU5pc3yK7Ki+CCurkarcMtWuG0+HZSaLfM1ogJlmOHjssI8a85ff77juG+rfokYcGBvQ98R3D6rO6T+rvmN1xy023+/3u2bWP9DqCCpF+h5gfAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCgrZDSFpp5r+xCBQEEEEAAARMBN0GF5v2aSqOu/kEFfTir0IBVud7P6jWQfnpbtZ5ZD0xEalDBaVG00eOu2ztL6xvbGoty/P2Ro4fkm/lfytbtGwM+l3oS+k0tb5W2be4UFWCwOs6cPS1vvv8Pycw0Dz+ofiVLlpZhQ/4gakeJUI6RY7VFvlrQwupQc1ZPIk8uUdK0yb4Du2Wu9jTznbu2mtbbFVapVF1aNGvtCRaoxfVujjNnTslr7/7NsukNTVvLffd0s6x3qjilLfxfsWapFkJZK4ePHBS1u0e4DnXP//jbl72GCySocOToQZnx9WQtGLPLawy7DwkJCdKscSu5o10nUe8DPWbPnSZLlv0YaDfb9n/5/X8k+2+SbcvwVQYaVFBnPnX6pHw06g1J03YHcTruueNBadXiFk+zy5ezZOzE4bJj5xanbtKyeRvpeFcXr3Z5FVRQk5j65QRZs26513zMPlSsUEUe0Xay+WT8e1ow6ahZE6+yO9vfJze3audVFo4P5y+kyX/e/F8tyGf9e6pCUr996s9SpEhiOE4ZEWMQVIiI28AkEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABWwGCCrY8VCKAAAII6AL5JqigXZCe0YvEoILbJ3qr+9Lmpvaexdf6PcrpV/V0fRVQ+HXl4pAXrxcrWlw63d1N6tVtZDntWd9MlaXLF1nWq4ou9z0S0m4SKqCgggp2R5NGLeRBbdcK30N9j2Z8PUlWarsohHokFkmSpo1bSvtb79YW0xeyHS6nggpqsfXsudM9ART9d8R2IkFUBhtUULtnLPxprvbE+3laeCUziDOLVEzVFpZ3Hyjqu+fuuCyzvvnC8TvobizvVtESVFCz3rV7m4z57EPH33kVGOrdY4hn9xS3YauqVWpIv0ee0MJGcV5AeRlUUDtJjJrwnuzbv9trTqF8sPobEsqYel+1s8jUGeP1j6avajebnlqoIj8dBBXy093kWhBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAgvwoQVMivd5brQgABBMIsEI6gQpinFPJwkRZUWL5yiXw5e7Kr62rW5Ea5/96HXbUNRyP11O5PJ4+03Xkg0POoJ8p3vre79rT7G027ntae5v7Wh6/YLkwvVzZFhj72vNY/xnQMp8KJU0fJxs1rbZrFeMZX5/E9cuJJ+8Me/4OULlXW91Ren8MfVLgsPy7+Thb++I2oRdo5eQQTVOjVfZDnCfdqQXaoR3JyKenb83FHY7Xvylezp3hCOaGe06x/NAUV1Px/+fVH+frbaWaX4lWWmJik7apwqyz4YY5XudmH4sWT5fH+z0pRk+BIXgYV1FzPaju6fDT6TVG/a6EelStVk/69npS4OHc7pgR6Pjc7QHS+p7s0b9oq0KEjuj1BhYi+PUwOAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBDwCBBU4IuAAAIIIOBKILeDCmoRu37k1NPdIymocPLUMZk8bZy220OWftmWr+rp2D269pOYmFjLNuGsUIGBsROHy9Fjh8I57NWxYqTjXQ9Ky+ZtTMf+avbnjovFe3Ttb7szg+nAWqHaQeCdj/6VvcOGWTurJ5G7XbhtNqZdWV4EFeYumClqYXhuHMEEFdTi9/Pn08I2PfUU/wGPDtXGu/Y3xji4+nvz5deTZcXqX4zFYX0fbUEFdfHTZ06UlWtC3z1EjRUXFyf9tXtQuWI19dHvyOuggprQgYN7ZeS4d7XwTrrf/NwWlNDCGIO1MIb7XTzcjnyt3YjRb8m+A/a7P/z2qT+LCobkp4OgQn66m1wLAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCORXAYIK+fXOcl0IIIBAmAUIKgQHuv/AHhmuPZnb7riz/X0y//vZ2s4Bzk+zr1alpvTuMUTi43Pm6dy+81RzGjHmbTl4aJ9vVdg+q8DFoD5PS6WKVf3GPHnquLz94T8lK8s6wFGxQhUZ3O8Zv75OBVeemP+zbbNBfYaJeiK68VBhklff+ZucO3fGWByW97kdVFi2YpHMnDM1LHN3M0gwQQU34wba5v6OD5vu5KFCCtNnTZRVa5YFOmRA7aMxqKB22/hk/Lui/qaFejg94T8SggrqGtdtXCWfawEytcNGoEdCQoIWiHlaKqRWCrRrQO3ffP8fov5OWh1ly5SXpwa/YFUdteUEFaL21jFxBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEChAAgQVCtDN5lIRQACBUARyO6gQylzd9o2UHRXczjelfEXPk+ALFy7itkvI7WbPnSZLlv3oahwVnlCLYsuWLu9Z1qt2YDh67IirAEaZ0uXk8QG/FbW41/eYMWuS49Pt+/QcIjWr1/Xtavk5Le2svP7e37WnpVuHQ648ef8pvzG27dgs4yZ+5FfuW1CsWAmpWrmGJCUWlfMX0uTY8cNa4OOA1sx60XNuBhW2bNsgn37+iatdPHyvzemzCnekat9X30N9R+7u8IBX8dLlP8msb77wKnP6UDSpmDRvepPUrnGdJCeX8uy4sP/gHtm6fZNs2LTaqbuoXRrUU+bj472/b1u3b5Txk0Y49g+1QTQGFdQ1nz5zSj4a9UZIIZ0btPt23z0P2RJGSlBBTXLBD3Nk4U/f2s7XrPKhB/tIw3pNzKrCWvbyf/9ou+uD+ruo/j7mt4OgQn67o1wPAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCORHAYIK+fGuck0IIIBADghEYlAh5up1Wi/7toeIpqCCWuz+5GPPS7Gixe0vKoy1aiH7hMkfO45YqmQZuffOB6V2zXoSE6PflSvd1O4D6zeulq+/nSbntHCA3dHmpvZyR7tOfk1OnDym7arwL9sF9dWr1pJ+vZ7062tV4Gbxca/ug6ROrfp+Q8z4WgtOrPrFr/xaQYy2GL+ztGzeRuLi4q4Va+/OarswbNm6QX5dtVj27d/tVac+5GZQ4YORr8qhwyo4YX2o+deve72kplSSUiVLe+Z/+Mgh2bhlre1i9eLFk2Vw39+IenU6AgkqqN032t96l9zcqp1ma76ryK8rF2vfty+0gEym7anNwi3qu7Zx81q/fhkZ6Z5dT/wqrhYon8YNm1tV+5W3vvE2rcz7d8WvUZgLFi/9XubMm2E5qgptvPT8K5b1esXuPTtk9KcfaLuc2Pvq7Y2vlStWk/6PDvX7vTC2Ue8jKaiggkWTp431/B3znafV57Zt7pR2t95tVR228kuXLsorr71kO17jhjdIl86P2LaJxkqCCtF415gzAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCBQ0AYIKBe2Oc70IIIBAkAIEFYKD239gjwwf/WZwnQ29ChUqLAN7Py0p5SsYSnP27UejXpcDB/dZnkSFElS4QC3K9X0yvW+n8+fTtKfmT5W1G1b6VmV/VjtFqKfcq2v1PaZ99ZmsWrvMt9jr86A+w0Q9yd/pSE9P13ZT+JvnKfxWbZXzEwN/Z1o9RlukvWPXVtM6Vdj6xrZy1+2dLev1ir37d8miJQu1HQDWaEVX4ja5FVQ4cvSgvDfiv/pUTF8rVqgiD3TsIeXLpfrVX7hwXlu4/7UsW/GzFiAxjwpV08Ij/V2ER9wGFVToofsDfaRK5ep+8/Et2LFzi4z5TO16YT431d4qGOM7lvrstCC8UYNm0u3+R826RkxZuIIK6oKWrVgkM+dMDejaVMhqyIDnpLi204jTEVlBBZFTp0/KG9oOLG4OFaZRgQ/fkJKbvoG2OX7iqBbi+qdtN7d/j2wHicBKggoReFOYEgIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggg4CNAUMEHhI8IIIAAAuYC4Q4qqGeJWy8hNp+DaakaJMgHk0fTjgrq2hOLJIl6CnyF1MqmFOEs3K4t9B772Ye2Q95y0+3SoV1H2zbGSrWg/eMxb8u+A/47CejtOt3dVVo0u1n/mP167PgReXf4vy0XxauGavcDtQuC0+FmYXxXbdH59dric7NDXYMKGVgd3R7oLY3qN7Wq9itXOyt8M/9L2b13pzw39CUpUaKkXxtjwZkzp+S1d/9mLPJ6f0PT1nLfPd28ynw/zFs4S378eb5vcfbnurUbSM9u/bUdMmKzy8zerFj9i8yYNcmsylP24H09pUmjFpb1qsLN/UjWTPr3GioltV0d3B6Tvhh9NQRi3kP9Hg3p/6x5pU8pQQUfEO2j884i1/rExsZpO548IVUr17hWaPMukoIKaucIFXrZtXubzYy9q25oepP2O/iQd2EOfNq7b5d8PPZt25Hb3XKXtNV+cuLYtGWdtivL/rAMrQIVCQmFXI9FUME1FQ0RQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAIE8EyCokGf0nBgBBBCILoGcCCoogZDCCvqT3LUn+wdzRFtQQV1jkSKJ0vvhwVKpYtVgLtl1n3ETP5JtOzZbtldP2x/U52lRC5ADOQ4dPiBqp4asrCzTbnY7GUyZMV7Wrl9h2k8vfGLgb7VdJyrqH/1eL1/O0p5A/i85cfKYX51eoBbD/+bxP1gu0neaR5PrW8iDnXrqw7l+PXL0kJQrm+LYPhxBhbc+eMXSoKj25Puhg34nSUnFHOeiGnw+bays27jKtG1qSkV5fMBvTev0QqegggpuqJ0ZSpUso3dx9ap2jXj/41ctwy1qR5A//vYf2uLoBMfxCCr4E2VmZsio8e/bhnb0Xh3v6iItm7fRPzq+RlJQ4cuvJ8vyVUsc5+zb4N47u8iNN7i/Zt/+bj672bHnppa3yt0dHnAzXMBtPhj5qhZUOBBwP7MOzw/7q6i/PW4PggpupWiHAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAgjknQBBhbyz58wIIIBAVAkQVAjudrlZSNq7xxCZu+ArOXjI3ZOpCxUq7AkrVKlcPbhJOfRSi7L/+fqftQXe5mECFU54esgLAS8c1087e+50WbLsB/2j3+v/PPN/kpRY1K9cLeR//+P/Wi48Vx0aajsZPKTtaGB1rN+4WiZPG2NV7Sl3WlT9w8/zZP7Cr23HUDsaqJ0NcuIIPahwWf7fv35veX/Vk+DVE+HdHmfOnpbX3vl/ls1/88Qfbb8rTkGFHl37S726jSzHt6v4ZPy7snvPDssmzw39k+MOFqozQQVzQnXvP/rkdTl77ox5A6206fUt5YFOPSzrzSoiJaiweOkPMmfedLMpOpbFxsZ6/k7XqF7HsW2wDU6dPilvvPd32+5qZxi1Q0xOHAQVckKVMRFAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAgfwjQFAh/9xLrgQBBBDIUYFwBxW0VdJX5mu3G4JqY1cf4hVHyo4KQ/o/py3kLi3jJg6XfQd2u7qqhIRC0qv7IKletZar9oE02rp9o4yfNMKyS01t4W2fno9b1jtVqJ0a1I4NVscjDw2UurUbmFZP1p7ev97i6f2qg3pK/tNDfi+lS5U17T9i9Fu2xkW1XQSeHfqSxMdbP2V/89b18unnI03HNxa2bH6z3HX7/dpY8cbikN+HGlS4ePGCFkT5k+U8nhz0vJQvl2pZb1ahggpq0brZYXc/VXunoMKjDz8mtWvWMxvasWz6rImycvVSy3ZPajtHlC9XwbJeryCooEv4v+7Zt1NGT3hfMjMz/SorpFaWgb2fDvh3IBKCCurv4ITJIy0DPX4Xa1KQWCRJBvd/xjaoY9LNdVFGRoa8/N8/2LYP9e+13eAEFex0qEMAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBAgqMB3AAEEEEDAlUBYgwp6SEGd2SqI4KaNq5lbN4qkoEKF1EqiFpCPnzxC9uzdaT1pQ41aTP/IQwOkZvW6htLQ385bMEt+XDzfcqB77+wiN97QxrLeqeL8+TT595t/sWx2S+vbpUPbjqb1hw4fkA9GvqbVXQ26mLRq1uRGuf/eh/1qdu3ZLqPGv+dXbiy4/bZ75Nab7zAW+b3PysqS90b8R44dP+JX51tQqmQZuffOB6VOrfq+VUF/DjWokJGR7vFPT083ncOfX/iXqF0zAjlGjn1H1IJ1s6Pzvd2leZNWZlWespwMKvywaK7M/3625bkHPPqUVK1Sw7JeryCooEuYv/668mf5avYUr8okLfQzpP+zklyipFe5mw95HVQ4euyQjBjztudvspv52rUpVzZFBvUZJoULF7FrFnSdCh2pfzusjrJlUuSpwf9jVR1SOUGFkPjojAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAII5HsBggr5/hZzgQgggEB4BMIaVFBT0oMIVkEFvY1dfYiXFmlBBXU56emXZIL2tP6du7a6ujr1tP4eXfsH/cR5s5OM+exD2bFzi1mVp6z7g30lOTnwxcfGAdXOBlbHdXUaSs9uA6yqZeLUUbJx81rL+ri4OPnNEy9KieLJXm3ULghqNwSro1ChwvLc0D9JkSKJVk2yy93uqqB3UDtE3N3hfsudHvR2bl5DDSqoc/zj1T9q3zXzoMKwx/8Q8Dxfffv/5Oy5M6bT73hXF2nZ3DrYkpNBhTXrV8jUGeNN56UKnXZ70DsSVNAlrF+/mv25/LpysadBTEys9O05RKpXq23dwaYmL4MK5y+kyfBRb8qJk8dsZhhYlQoqqe+a2vEl3Mc7H/3LITQVI78b9hcpVrR4uE+thcZeFRUeC8fx/LC/StEA5nj48GFJSUmxPfXLL78sL774om0bKhFAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQRyToCgQs7ZMjICCCCQrwSCDio4BRL0eqXlZhGn3t63rVW52V242nb52FWydor1wnXVNS0tTRITnReum51Gle0/sEeGj37TqtpTPqT/c6J2VNAP9cT7z6Z8Itt2bNaLbF/VwnwVHlAL/MNxhHPxaTDzqVq5hgzo/ZRl14OH9smHn7xuWa8qWrW4Ve6544HsNuoJ6e8O/6/22XonhptbtZM729+X3cfpzfhJI2Tr9o1OzbLr1S4FrVrcIm3b3BnS09XDEVR4/+P/yuEjB7PnZnzT9f5H5foGzYxFtu9PnTohb7z/smWbXt0H2e4okZNBhU1b1nl+l6wm1+W+R6RxoxusqrPLCSpkU1i+yczMlG+/+8rzdP/q1WpJk0YtLNs6VeRVUCErK1PGThzuKiiWmlLJE6gaNeE9OXnyuNMlSZub2ssd7To5tgu0wagJ78uu3dtsuz3QsYc0bdzStk0wleH8t4KgQjB3gD4IIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggEBkCxBUiOz7w+wQQACBiBFwHVToUt87cKAHCNSV+IYLVJlTvWpjPMzam5UZ+/i+v9o+UoMKarqZmRky6YsxtjsAGC9LLYLvpi0wb1CvsbE4qPevvfs3UYvh8+ooVzZVhj72vO3pnXZHSEhIkGeffEmSkop5xpnx9SRZseoXyzFV2OMZrX3xYiUs2/hWqMXr47RFzXv27fStsv2sznHPHQ8Gfa/CEVRQQRi1iN/sKF2qrDw+4DlRO0y4OZzuxdNDfi9lSpezHCovgwqd7+0uzZu0spybXkFQQZfInde8Cip8NXuKtivEz44XqXYnGNz/Wc+uLYePHJCPx74j6jvidHTprAVjGjoHY5zGMdZ/9/1s+X7RXGOR3/sG9ZpoYbY+fuWhFnwy7l3ZvXdHqMN4+hNUCAsjgyCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIOAloB7Su3XrVq8y9SElJcXz41dBAQJhFiCoEGZQhkMAAQTyq4DroELXBt4ExhCBqrEKK5iVe4907ZM+pt7H9/O1lubvoiCooCaunu79+fTxsmHTavPr8CmNiYmVrtpC2EYBPA3fZwjPx5f/+wfJyMgwq8qVMrWQ/7dP/8X2XG52qri1dQe5ve29cvbcGXnjvZc94Q+rQZs1uVHuv/dhq2rL8osXL8iUGeNly7YNlm2sKurVbSTqSedFigS2Y0c4ggpO4YDrGzb3fJe0X1ir6XvKFy/9XubMm2HZJimxqPxu2F9EBWmsDqe5PPrwY1K7Zj2r7rblTjsqEFS4xhcfnyAvPf/KtYI8fJcXQYVffv1Rvv52muNVx8fHS/9eQ6VSxarZbTduXisTp47WPlvv2KIam/XNHiTIN/v275YRY96y7a3+xvxO+5uq7nE4j6ysLFcBjc3b1ssXX35qe2qCCrY8VCKAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIBCUwC+//CKtWvk/xPN///d/5a9//WtQY9IJgUAECCoEokVbBBBAoAALhC2ooAz1gIGTpwoU2LUNJKDgWT96dRHp1TGXj1kpa6est52FSpUmJga2kNw4oJsF9UP6PycVUisZu2W/VwtBp331qaxZvyK7zO5NjHZtavF7k+tb2DWzrFPn+9u/X7Csz42KwoWLyB+e+7vjqcZPGiFbt2+0bKfGeW7on0Qtev7h53mW7ZTZU4NfsH3qv2VnT8Vlbfz58t33c7QNQrLsm/rUlipZRh7u0k9SUyr61Fh/DEdQISMjXV7XwhtpaWctT1SlUnXpeFdX07mdOXta5sydLus2rrLsrypuvfkOuf22e2zbEFSw5QlbpVOopCAHFbbt2Czq74mb39+unXuJCvL4HmpXA7W7gdNRTAtiDen3jBQvnuzU1FX9Ze3fwVff/j85Z/O7rAa6o10naXNTe1djhrvRlSDHKNthCSrY8lCJAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIBAUAIEFYJio1MYBQgqhBGToRBAAIH8LJDrQQU9hKBQzcIKTvW+N8OkfTQEFdRlqIWoM2ZNkpVrlvpelcXnGOl870PSvIl/Gtaig1fxK6+9ZPuU7OtD3LHB62QmH0pqi/edFrerbnv37ZKPx75tMsK1IrWrwtIVi+TChfPXCn3e1b+usRYW6OtTGvjHPXt3yvRZE+XY8SMBdS5UqLD06TFEKleq5qpfOIIK6kQqvDF/4de251S7dNSoVlvKl0uRksmlPbtTHDl6SHbs2mr7HVGDql0Unhv6kqiF2XYHQQU7nfDVEVQwt1S/r2pHAru/EXrPW1rfLh3adtQ/+r1+Pm2sY3hHdaqYWkUG9B4ath0Ops+c6Pjvg9pV4ZknXgx4Bxe/iwyigKBCEGh0QQABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAIAwCBBXCgMgQIQkQVAiJj84IIIBAwREIa1BBYrTwgYOdSbAgu4exThWaBRmyGxve6P2uto+WoMKVK7gsM+dMlWUrfjZckN3bGO1p+F2kZfOb7RqZ1r07/N9y9Nhh07q4uHj5429flri4ONP63C4c+9mHsn3nlpBOO7j/M56FwyENcrVzZmaGLPxprixa8p1kZma6HlLt/tC35+NSsUIVxz7hCipcunRRRk14Tw4c3Od4zmAatLvlLmmr/TgdBBWchMJTT1DB31GFE4aPflOOnzjqX+lTUq9uI+nRtZ9Wav2PV3p6unwy/h1Xv1ONtMBXt/sf9TlLcB83bFotk74Y49hZ7aigdlbI7YOgQm6Lcz4EEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQSuCBBU4JuQ1wIEFfL6DnB+BBBAIEoEAgoq6IEAdW1mIQK7er3O2E8vs7IytlVt9Pa+5Xr/q/XLx66StVPW66Wmr2lpaZKYmGha56Zw/4E9noWwdm2H9H9OKqRWsmuSXTd77nRZsuyH7M9Ob+7u8IDc1PJWp2Ze9WO0xf87bBb/P9bvN1KpQlWvPnn1YfeeHdrC4HeDPn2N6nU8AYGgB7DoqBY+z5k3QzZvtf9+GbuXKFFShg56XlRowe4IV1BBnSPt/DkZNf49UbskhPOoVaOuPPrwYO3X33pRt34+ggq6RM6+ElTw9s3KypJxk4bb/q3Te6SUryiD+jwtCQmF9CLL19OnT8pHWvjh3Lkzlm30itvb3itq15dQj6ysTHl3+H8cAxfx8fHS/9Ghuf73m6BCqHeY/ggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCAQnQFAhODd6hU+AoEL4LBkJAQQQyNcCuRJU0AMGStK4wNlYbqZs1dZYbuwXxUEFdRlzF8yUnxZ/Z7wi2/fqCdrqSdpuj2kzP5NVa5ZZNr/3zgflxhtusazP7YrRE96Xnbu3BXXaPj2HSM3qdYPq66bT1u0bZdY3X8iJk8fcNJdmTW6U++992LZtOIMK6kRnz56W0Z9+qO2iEZ6wQmpKRemj7Q6RlFjU9jr0ymgIKly8eEH++fqf9Cn7vYbz6fh+g4epgKCCN+Ssb6bK0uWLvAtNPhVNKiaD+z8ryVqQyO2xZ+9O7XfqfRe7qsRIz2795bo6Dd0Obdlu/cbVMnma864KxYoWl8f6PRPQ9Vie1GUFQQWXUDRDAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAgzAIEFcIMynABCxBUCJiMDggggEDBFHAdVOhS3xvINyzgGzow1pvVXVbDef7jPa7xk90Yqp1e7zN+NO6ooF/2gh/myMKfvtU/Or62v/Vuua3NnY7tVIP5C7+WH36eZ9m2Qb3G0v3Bvpb1uV2xc9dWbVHwBwGftkJqZRmiLUDO6SMjI0N+XDxffvx5vrZwOcP2dGoHgmeH/klKFE+2bBfuoII6kZrXoiULPPc9PT3d8txOFc0a3ygd7+oq6sntbo9oCCpcunRRXnntJctLIqhgSRNUhQpiqUCW1REbGyd/fuFfVtWO5SqgoIIKTkdcXLz06/WEVKlU3ampX/2K1b/IjFmT/Mp9CwoVKqzt1jBMypdL9a0K+POIMW/Jvv27HfullK8gA3s/LercuXEQVMgNZc6BAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIICAvwBBBX8TSnJXgKBC7npzNgQQQCBqBcISVPAJCngw9BCB+mBWr8qNbdRndRjbGuuN5VdaWv43moMK6qLUwvd5C2dZXp9vxW033yHtb7vHt9jv87Ydm2XcxI/8yq8VxEi/Rx6X6tVqXyvK43efjHtXdu/dEdAsuj/YRxrUaxJQn1AaHzi4TyZNGy0nTx63HcYpVJITQQV9QmvWr5CpM8brH12/qu9C65a3Sd3aDVz30RtGQ1AhMzNT/v6f3+tT9ntV3yP1fYrkgx0VrtydHTu3yLhJwyUrK8vxdj3Yqac0ub6FYzurBnPmTZfFS3+wqs4uL1mytAzWdjlwuwtJdkefN7v2bJdR49/zKTX/qH5nH+7SVxKLJJk3CGMpQYUwYjIUAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACAQgQVAgAi6Y5IkBQIUdYGRQBBBDIfwIhBxXsAgR60MCqjV5vZPVtq7fxLTf28Xkf7UEFdTlOi499LllubtVO7mx/n2+x1+fLmuHr7/5Nzpw97VVu/JCcXEqeHPg7KVy4iLE4DO/V7hkxAY/jHK7wHrJ0qbLy9JDfaxmYwM/lPVJgn9LSzsr7H78qZ8+dsexYu2Y9efThxyzrcyKosGXbBvlm/pdy9Nhhy/MaK9ST2KtVqSk1tMXOdWrVk7JlUozVAb2PhqCCuqD/++f/aP81391FPXF/YJ+nA7ru3G7s9LciPj5BXnr+ldyelun5cmpHheMnjsrw0W/KhQvnTc9rLGxzU3u5o10nY1HA7y9fztJCXyNk+87Njn2rV60lfXoOEbVbRCjH59PGyrqNq1wNUTK5tPTo2k9SUyq5ah9sI4IKwcrRDwEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAgdAECCqE5kfv0AUIKoRuyAgIIIBAgRAIOKigLwAPIDhgCamPpTcIdkw1jqFvfggqKJKlyxfJrG++0N6ZL6LW2fTXVi1ulXvueED/aPo6d8FMUYuF7Y6mjVvKAx172DUJqG7TlnUyZ94M7cn0faVCauALZz8e87bs3b/L1Tk739Ndmjdt5aqtsZF6CvvIce9Ih9vulRrV6xirXL+/cr+mWrYvW6a8PDX4Bcv6cAcVFi1ZIN9+N1M7n/n3JyEhQSpXrCaVKlaV1PIVpXy5ClKmdDltQXWs5RwDqYiWoMLf//MHyczMML20EsWT5bmn/mxaFymFBT2ooMIJI8a8JceOH3G8JWpnkJ7dBoQlyKTOq8IRKiThdLRo1lo63d3NqZltfXr6Jc/fqIOH9tu20yvj4+M952x6fUu9KOyvBBXCTsqACCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIuBIgqOCKiUY5KEBQIQdxGRoBBBDITwIBBRWMwQJDMCBoj3CMZzJGfgkqKNcVq3+RL7+erOUwzBeb+9q3aHaztji1i1ZsvqPAkaMH5b0R//Xt5vf5lta3S9s2d4la7Brscfr0SZk9b7ps2LTGM0SPrv2lXt1GAQ+ndgWYMPljx37FipWQZ598UeLiAp9zVlam/O3fv/eco3GjG+TuDvdLUmJRx3MaG6hAxmdTPjEWeb13WvQezqDC9p1btCe+f2T5vVE7cNzauoMUKZLoNcdwfoiWoMK/3/iLnL+QZnrpamcOtUOH2qkjUo+CHFQIZGeD8uVSZVCfYaJ2DQnXoXYqUSGJixcvOA7Z8a6u0rL5zY7t7BqcPnPKE444a7Mrjm//ypWqSbtb7pJaNa7zrQr585p1y2XqlxNsx3l+2F+laNHitm2MlYcPH5aUlBRjkd/7l19+WV588UW/cgoQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBAoKAIEFQrKnY7c6ySoELn3hpkhgAACESUQVFDB5aJ5xwvVQwahjGcyRn4KKihDtRj0i68+0xadZzmSqgbNmtwoamcBtcja7Bg1/j3ZtWe7WZVXmbPMZFoAAEAASURBVFqcrZ4CXjPAHQbU7gdLlv0o6zeuFhUA0I9ggwqq/wcjX5VDhw/oQ5m+3tGuk7S5qb1pnVOhMaig2qoF/GqHipu0H7eL+WfOmSLLVvxseapyZVNl6GPPW9aHM6gwedoYj7/Zya6r09DzVHmzunCWRUtQ4cNPXhO7p9Q3ub6FPNippyPNyVPH5edfFmrf+cva701Xx/bhalCQgwpffztNfvn1R0fKpKRiMrjfb6RkcmnHtoE2UEGqTz8faRkK0sdTO5X07jFEalSrrRcF9br/4B5Rf8PT09MD6q92TlHhpFo16moBtISA+uqNMzLStX87dsj2nZu1ny1Xf2/sQ3QEFXQ9XhFAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEAifAEGF8FkyUnACBBWCc6MXAgggUOAEXAcVujYQbSVm8D5mi+YDHU+N4aJPfgsqKPT1G1fJlBkTvBb+292MJo1ayAOdHtbCCrF+zY6fOKot/H9NW+h6ya/OrOD6Bs1ELW5XC+3LlC6n7VgQ59VMPU18994dsnP3Ns8CVqtF36EEFT4a9bocOLjP67zGD4ULF5Hnhv5J1Gswh29QQR9DPX1dPQW96fUtpWyZ8nqx16va7eLHxfNl/sKvvcp9PzRueIN06fyIb3H253AGFd784B9y8uTx7LGNb2pWryt9eg4xFuXI+2gJKkz6Yoy268dqSwP1O3T7bfd4QjBm4R8VoPlJu//rtN/RrKwsz++I2oUht46CGlRQoSAVDnI61N+rvj2fkKpVajg1Dbp+0ZIF8u13Xzn2TyySJIP7PyOlSpZxbGvXQO1S8/n0ca7/PTCOpXacqVq5uhZAqys1qteWUlp4I1HbPcb3u33hwnk5c/aUnD5zWlQ4QgUT9uzdKZmZGcbhHN8TVHAkogECCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIBCxBUCJiMDmEWIKgQZlCGQwABBPKrQK4EFcxCCgrUKnSgtzfW62V2/a7epPwYVFCXtmnLOlFPys/MvLZLwdVLNn1pVL+ptjC+l6gnefsey1Ys0hb5TvUtdvysxlI7LSQmJolayHou7ZycP3/O8WniauBggwoqADF6wvu2c7ul9e3SoW1H2zZ2lVZBBWOflPIVpP51jSWlXAUpUSJZLl28KIeOHBS1IP/Y8SPGpqbve3UfJHVq1TetU4XhDCp8Mv5d2a09+dzqaN6kldzZ/j7Xu0VYjWNXHi1BhaXLF8msb5x/FyqkVtIWeNeUEsWTtcXbp+TI0UNy5Nghz30zOqgwD0EFo8i19z8t/k7mLph5rcDnXWxsnPz5hX/5lPp/3Llrq4yd+JEnGOJf611yf8eHpVnjG70Lc+DTF199KqvX/uo4crmyKfJY39+ICkGFcqhw2GQtZHP23JlQhvH0VSEFtXNMkhZYUGGbs+dOB7xjg9UkCCpYyVCOAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIBA8AIEFYK3o2d4BAgqhMeRURBAAIF8L+A6qNDFeoG1KyRj0EB1MIYQfAfQ2/q2sSr36Z9fgwrqMrdu3ygTp46SjAx3T7VWC+sfeuBRLazgvQuCGmvcxOGybccm9TZXjmCDCk7zjI+Pl2effEmKFi0e9HW4CSoEPbjWUS0A/t2wv5qGRvRxwxlUcHrKvjqncqtf93ppUK+JVKtaU9TT3sN5REtQQe0I8uo7/xe2hdkEFay/ReEIKqgdYUaMfkvOX0izPtHVmtY3tpW7bu/s2C4cDdTf5FHj35N9B3Y7Dle3dgPp2W2A3y4Gjh19Gpw9e1rUjiB79u30qYmcjwQVIudeMBMEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAgfwjQFAh/9zLaL0SggrReueYNwIIIJDLAiEFFVRwwDdMEMr8XQYRnE6Rn4MK6tp3aE8T//TzkdrC6ktOFJ766+o0lO4P9pW4OO+wwrm0szJ+0nA5cHCfq3FCbRRMUOHgoX3y4Sev2566RbObpdPdXW3bOFXmdFDh3ju7yI03tLGdRjiDCpe138sxn30o6snz7o4YSU2pINWq1JIqlatLlUrVPTsHuOtr3ipaggpq9tNnTZSVq5eaX0iApQQVrMFCDSqoUMmIMW/J0WOHrU9ytUbtXvLIQwNDDgM4nsjQ4IwWHBg+6g1Rr05Hm5vayx3tOjk1c6xXf7tmz52u7eyyyLFtXjQgqJAX6pwTAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQCC/CxBUyO93OPKvj6BC5N8jZogAAghEhEDQQQU9VKCuIhxhhTCOl9+DCop8994dWshghFy6dFF9dDxq16wnKiignqJvPFTYYfK0sbJl2wZjcdjfFytWQno/PFhSylcIaOzPp4+TdRtWWvaJiYmVYY//XkqVLGPZxk1FVlaW/P0/f9C+yllumgfUplWLW+SeOx507BPOoII6mbq302dNsvWzm1TJ5NJacKGm1KhWW2pWryPFiyfbNferi6aggno6/8dj3pZjx4/4XUegBQQVrMVCCSqo380Jk0d6dpWxPsOVmnJlU2RQn2FSuHARp6Zhr1c7KqidFdzsetO1cy+5vmHzsMxB7baz4MdvZN9+5x0dwnJCh0FKlyorzRrfKGpXC9+QnF3Xw4cPS0pKil0Tefnll+XFF1+0bUMlAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAAC+VmAoEJ+vrvRcW0EFaLjPjFLBBBAIM8Fgg4qiLabgvY/YQkpKAU9qBCG0ENBCCooMrUgdZy2I8KFC+fVR8dDLTbv2W2gJCQkeLVVC4BnzvlCfl35s1d5OD7ExcVrC1Vvk1tbd5BChQoHNOTxE0flnY/+bRseaFS/qXR7oHdA41o1njlnqixftVhUaCFcR4N6TeQhbX4x+vfbZuBwBxX2H9gja9Yvl8VLf7A5q/uqCqmVpGG9ptrOELf4fYfMRommoIKa/4mTx+QTbYG5ug+hHAQVrPVCCSqoXQOWLHP+LicmJsngfs+EHF6yvgrnmtXrfpUvvvzUsaEKjvV/dKhUqlDVsa3bBtt3bpaFP30ru/fscNslbO3U3/iG2t+8po1bStXKNYIal6BCUGx0QgABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBAoYAIEFQrYDY/AyyWoEIE3hSkhgAACkSgQfFAhEq/mypwKSlBBXe2Bg/tk7MQP5fz5NFc3pFrVWtLroYGmoYFtOzZri9q/155Yvkkb67Kr8awaJRZJ8jwpvHXL26RkydJWzWzLv5o9xTE88fiA30pqSkXbcQKpPHX6pGcx9PJVS+TixQuBdPVqW75cqnRo21Hq1m7gVW73IVxBhV9XLpZFSxaICnrkxKGelN6l8yNSuWI12+GjLaigLkbtUKIWeatwR1ZWpu31mVUqGxXMadHsZrPqHClTv7Nz5s2wHDs+PkFeev4Vy/rcrAg2qLB85RL5cvZkx6nGxsZJ355DRP2dy+tj7oKZoq7X6Siu7TYzuP+zol7DeezavU0Wa8GOHbu2hvS3zGlOajebWjXqaj/XeV4TEgo5dbGtJ6hgy0MlAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACHgGCCnwR8lqAoEJe3wHOjwACCESJAEGF4G6Uelr98NFvWnZWT9B/5smXJLlEScs24ao4fOSAjPn0QzmXdtbVkK1vbCt33d7Zsu2x40c8i/VXr1se0ALXksmlpWKFylL/usZSv24jUbspBHucPXdG3njvZcnMzLAconbNevLow49Z1odSkZGRLpu3rpe1G1ZqwY2Nkp6e7mo4tWj3tjZ3SJNGLVztomAcNE27f6++8/8sd3S4oWlrue+ebsYuXu9VWGXG15Nk4+a1XuU58SEmJlZuuam9tLv1LlGLw82OlWuWyvSZE82qPGWPD3hOC5lUsqy3q9i7f5d8POZtyyaPaGGcQEIivgOp3wG1+F+FdtSOI3aHuv56dRuKuj81q9fWmqqtZnLvWLN+hUydMd7yhOr38pknX7Ssz80Kp6BCieLJ8txTf/aaUkZGhvz7zb9ov4OXvMrNPnS+p7s0b9rKrCrXyy5ruwN9+vlI2bJtg+O5VbCl091dHdsF00B9f1WgTQUWduzaIrv37nD998z3fGrHhHJlUqRc2RSpVLGKJ5yg/uaF8yCoEE5NxkIAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQyK8CBBXy652NnusiqBA994qZIoAAAnkqQFAhT/kj/uQXLpyXU6dPaD8n5fQZ7ef0KcnSFr4WKZwohQsX1n6KSLGiJaSCtuA8MTEpbNfj5mnk/Xs9mUtPTr8sZ8+dlVOnTsjJU8e1H/V6QjKzMqRkiVKinqJfunRZKVOqnMcjbAgBDHTy5HEZOf5dUbsy5ObRvEkr6Xxv99w8Za6eSwVlVGjhyLHDcvToIc/vQZEiiVIyuZT2U1oLIpWSUtqOIWoBNwcC0SCQmZkpJ04elbS0NEk7fy77RwWd1E9MbIwULlTE87fsymthz24P5cqmat/3ZO0SczaIQ1AhGr5FzBEBBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAIK8FCCrk9R3g/AQV+A4ggAACCLgSiJSggvbwac+hbUQQ8rF87CpZO2W97ThqkWZiYqJtGyrzRuDixQvy+nt/t93NoXLFajKo77C8mWAEnnXcxOGybccmVzOLjY2V4tqT6xPiE0QtuldhlHNaEOO89ipy9RfR1UhXGvXuMUR7snrdAHrQFAEEEDAXIKhg7kIpAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACRgGCCkYN3ueFAEGFvFDnnAgggEAUChBUiMKbls+n/OPP82Xewlm2V9mja3+pV7eRbZuCUrlm/QqZOmO87eXGxMRqXg2lVYtbpWrlGhJjkgjKysrSnrR+TDZtWScbNq+Rvft2a2M6BxeSS5SUoY/9D7sK2N4BKhFAwI0AQQU3SrRBAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEECjoAgQVCvo3IO+vn6BC3t8DZoAAAghEhUCkBBU8WGpNNDsqRMX3JqcmmZGRIW+8/7L2hP8zlqcoWyZFnhr8fHi+LJZniZ6Kj0a9LgcO7rOcsAoS9On5uJQpXc6yjVnF2bOnZfGyH2Tx0u8lMzPTrEl22cNd+kr96xpnf+YNAgggEIwAQYVg1OiDAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIFDQBAgqFLQ7HnnXS1Ah8u4JM0IAAQQiUiCQoMLlqw9XN3kYe0Rd2/Kxq2TtlPW2c0pLS5PExETbNlTmvsCyFYtk5pyptid+oFMPaXp9S9s2BaXysvZL+Y9XX5SMjHTTSy5RPFn6PzpUSpUsY1rvplCFIMZNGi5paWctm9/W5k5pf+vdlvVUIIAAAm4ECCq4UaINAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggEBBFyCoUNC/AXl//QQV8v4eMAMEEEAgKgSCCSqoC4vksAJBhaj46vlN8vLlLHn7w3/JiZPH/Or0ghLa7gDPPPFHiY2N04sK9OvxE0c1s39aGtzd4QG5qeWtlvVuK3bs2ipjPv3Asvl1dRpKz24DLOupQAABBNwIEFRwo0QbBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAIGCLkBQoaB/A/L++gkq5P09YAYIIIBAVAgEElSIigvSJklQIVrulPc8165fIVNmjPcu9Pl0d4f7tYX3t/mUFtyPW7dvlPGTRlgCDO7/jFRMrWJZH0jFu8P/I0ePHTLtUqZ0OXl6yO9N6yhEAAEE3AoQVHArRTsEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAgYIsQFChIN/9yLh2ggqRcR+YBQIIIBDxAuEIKly+7H+Zxh0XjPXGcv9eV0r09r5trcr1cfT6FeNWydop6/Vi09e0tDRJTEw0raMwbwQ+GPmaHDq83/LkiUWS5Lmn/iQJCYUs2xS0il17tsuo8e9ZXnafno9Lzep1LOsDqXj17f+Ts+fOmHZJTakojw/4rWkdhQgggIBbAYIKbqVohwACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCBQkAUIKhTkux8Z105QITLuA7NAAAEEIl4gWoIKeghBgfoGGHRkvQ1BBV0kel6ddgZQV9K2zZ3S7ta7o+eicmGmJ08dlzff/4flmW5pfbt0aNvRst5txaHDB+SDka9aNm9Uv6l0e6C3ZT0VCCCAgBsBggpulGiDAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIFDQBQgqFPRvQN5fP0GFvL8HzAABBBCICoFAgwoqDGAVFHBzwXqYwNjWajxj2xjVwfMfEb3cqt/yseyoYPSNhvefjH9Xdu/ZYTnVhIQEeXbonyQpsahlm4JYkZWVKf98/c+Snn7J9PKV28Nd+kntmvVM690Unjl7WiZM/lgOHtpn2bzdLXdJW+2HAwEEEAhFgKBCKHr0RQABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBAoKAIEFQrKnY7c6ySoELn3hpkhgAACESUQSFBBDwioC7AKCThdnHEMY1uz8YxtjfVW5fp4BBV0ieh43bNvp4wc+47tZFu1uEXuueNB2zYFtXLGrEmyYvUvlpcfGxsn9975oDRp1EJUcMHtcVn7Rduxa6tMn/mZnD5zyrbbwN5PS5XK1W3bUIkAAgg4CRBUcBKiHgEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAARGCCnwL8lqAoEJe3wHOjwACCESJAEGFKLlR+Xian34+UjZvXW95hbGxsfKbJ16U5BIlLdsU5Ir9B/bI8NFvaQTadic2R0JCIalbq77Uu+56KZVcWpKSinp2qChcuIhkZmbIubRzkpZ2VtQOClu2bZANm9bI2XNnbEa8UnVdnYbSs9sAx3Y0QAABBJwECCo4CVGPAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAQQW+A3kvQFAh7+8BM0AAAQSiQsBVUKFvU2nYpb7XLgr6rgbGnQ7UBevlVhevt/dtp5fr/ezqjXW+/VR/dlTQFSP/9fCRg/L+x69qE7VeZN+40Q3S5b5HIv9i8nCGcxfMlJ8WfxfUDGK0XyK1e0IwhwqRPDnoeSlbpnww3emDAAIIeAkQVPDi4AMCCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAKmAuyoYMpCYS4KEFTIRWxOhQACCESzQKhBBXXtxrCA03pnq7ZW5bqtVb2xXG9LUEGXiPzXL776VFav/dVmojEy9LHfSbmyqTZtqMrKypJxk4bLjp1bcg0jLi5eunR+RBrWa5Jr5+RECCCQvwUIKuTv+8vVIYAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAgiER4CgQngcGSV4AYIKwdvREwEEEChQAuEMKjiFFBSsMVhgbG9Vrt8Mq3pjud6WoIIuEdmvp06dkLc+fEXUInuro27tBvLIQwOtqik3CGRlZcrMOVNl+aolhtKceVu4cBHp2W2AVK9aK2dOwKgIIFAgBQgqFMjbzkUjgAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCAQocPHiRTl48KBfr+TkZClZsqRfOQUIhFuAoEK4RRkPAQQQyKcCroIK/ZpKoy71JZBggeJSIQJjH71Mp/St08vNwgfGtsZ6Y7nef8XYVbJ26nr9o+lrWlqaJCYmmtZRmDsCX387TX759Ufbkw3s87RUqVTdtg2V3gLrNq6Sn5cslH0HdntXhOFTXFycNKzfVG5t3UHKlikfhhEZAgEEELgmQFDhmgXvEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQACBSBUgqBCpd4Z5IYAAAhEmkFNBBaswgVW5kcXYRi83BhKM9cZyvS1BBV0icl/T0s7KG++/LOnp6ZaTrFqlhgx49CnLeirsBfbt3y2Ll/0g6zeu1natyLRv7FBbrGhxadGsteenqPaeAwEEEMgJAYIKOaHKmAgggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAQHgFCCqE15PREEAAgXwr4Dao0PDB+l4G2mYJ2pYJV4rMwgJ6mCDQOs+wV8e9Mrr5OezGJ6hglIvM9wt/+lYW/DDHdnK9ug+SOrW8v3e2Hag0FTh79rSsWP2LHD56SE6dPiGnT5+UM1pZVlaWafuEhAQpUbyklCih/RRPllrV62q7KDSR2Ng40/YUIoAAAuESIKgQLknGQQABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEck6AoELO2TIyAgggkK8EXAUV+jaVhl2sF4zroQEjjFlAwViv3uv9rNrq9aqtUxtjPUEFJRbZx/6De+TkyROWk4yNjZV6dRtZ1lMRmsDly1laWOGMJ7hwVnuNj4+/Gk5IlsQiSaENTm8EEEAgSAGCCkHC0Q0BBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEMhFAYIKuYjNqRBAAIFoFoiEoILyMwYNdE+nXRtUO7MwA0EFXZBXBBBAAAEEokeAoEL03CtmigACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIFV4CgQsG991w5AgggEJBAOIIK6oRmgQE3E9H7mQUVsse9rAUZLAbT+6tqfQyCChZYFCOAAAIIIBDBAgQVIvjmMDUEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQOCqAEEFvgoIIIAAAq4EAgkq6KEAPRDg6gRXG3n6uggcWI3t2V3h6ljG0II+J1Wl9yWocBWKFwQQQAABBKJIgKBCFN0spooAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACBVaAoEKBvfVcOAIIIBCYQDBBBXUGPRTg5mxmYQLffnobq3EJKviK8RkBBBBAAIH8JUBQIX/dT64GAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBPKnAEGF/HlfuSoEEEAg7AKBBBXUyVWgwCpMYDc5p34qiGDcKcFsLD2sYGxnFnBgRwUzPcoQQAABBBCIbAGCCpF9f5gdAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCgBAgq8D1AAAEEEHAlEGhQwWlQs+CAVR89eKDqjeEDq/Z6uaff1c5moQmCCroUrwgggAACCESPAEGF6LlXzBQBBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEECq4AQYWCe++5cgQQQCAggagMKhgSDgQVArrdNEYAAQQQQCBiBQgqROytYWIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggEC2AEGFbAreIIAAAgjYCYQ7qGB3rnDWqayC1S4M7KgQTmnGQgABBBBAIHcECCrkjjNnQQABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEQhEgqBCKHn0RQACBAiQQSFBB38jAKiCQE2zBnJOgQk7cCcZEAAEEEEAgZwUIKuSsL6MjgAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAALhECCoEA5FxkAAAQQKgABBhQJwk7lEBBBAAAEEokCAoEIU3CSmiAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIFXoCgQoH/CgCAAAIIuBNwG1Ro1KW+hLSTwmWtd8yV/RHUf0MaS+tvNwY7Kri797RCAAEEEEAgkgQIKkTS3WAuCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIICAuQBBBXMXShFAAAEEfATCEVS4Ej+wCR+okMLVI+ZqWEF9vFaq17p71c9nNQZBBXeOtEIAAQQQQCCSBAgqRNLdYC4IIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggIC5AEEFcxdKEUAAAQR8BNwGFRpqOypYHXpwwDZ4cDWsoAcVbNtanchQbndOggoGKN4igAACCCAQJQIEFaLkRjFNBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEECjQAgQVCvTt5+IRQAAB9wKuggp9mkjDrg3cD3q1pQoTBBJICKi9Cj4YdmcwTo6gglGD9wgggAACCESHAEGF6LhPzBIBBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEECrYAQYWCff+5egQQQMC1gOuggtpRwSIYIFd3SzDW6zseqIm4CSvo7d20zT6fGtxkTgQVFAwHAggggAAC0SVAUCG67hezRQABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAIGCKUBQoWDed64aAQQQCFjAdVDBbkcFk6CCmkgg4YNA2mYHFUxCCuq8BBWUAgcCCCCAAALRJUBQIbruF7NFAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAgYIpQFChYN53rhoBBBAIWMBVUKFvU2modlQI9FABBrMwgVW5Pr5F8MEpoKB3J6igS/CKAAIIIIBA9AgQVIiee8VMEUAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQKDgChBUKLj3nitHAAEEAhLIsaCCHjZQszGGFazKjbPW2wTa7+oYBBWMmLxHAAEEEEAgOgQIKkTHfWKWCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIFCwBQgqFOz7z9UjgAACrgVyLKigZqACB8awgT4rsyCCXqf3U6/Gvk59DP0JKhgweIsAAggggECUCBBUiJIbxTQRQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAoEALEFQo0Lefi0cAAQTcCwQdVNCDA8ZTGYMFxnKr9/oYVv30etXfqo2qM7bTPq4Yt1rWTl2vaiyPtLQ0SUxMtKynAgEEEEAAAQRyV4CgQu56czYEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQCAYAYIKwajRBwEEECiAAhERVFDuZkEEYwDBrF71M7ZRn7VjxbhVWlBhw5UPFv8lqGABQzECCCCAAAJ5JEBQIY/gOS0CCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIBCAAEGFALBoigACCBRkgaCDCgrNNyRgFSYwA3bT19jGbGxjveEcBBUMGLxFAAEEEEAgSgQIKkTJjWKaCCCAAAIIhCCQlZUp59LOyaVLF6VwocKSlFRUYmPjQhgx8rqqa8zMzJS4uLgcv7bzF9IkKytLkhKTtOc/xEYeRhhndFn7vwGdSzurXav6zuTvaw0jG0MhgAACCCCAAAIIIIAAAggggAACCCCAAAIIIJAjAgQVcoSVQRFAAIH8J+AqqNCniTTs2sD54i2CA767Jaj/53KM72jGIILZOMZ61demzYqxakeF9b5n8PrMjgpeHHxAAAEEEEAgzwUIKuT5LWACCCCAQNQLqEXb8xbM8ruOQtqC+A5tO3oWjvtVhqng+ImjsmjJAr/RrqvTUOrUqu9Xfq3gsnw1e8q1j1ffFS1aXNrdcmeOLD7/+ttp2kL6DL9ztrmpvZQqWcavPNiCI0cP/n/27gMwijL94/hDChB671VESlCKBVEEREWxUOzSUURFwYqe//MsV73iWc+KjWKnqagUKVJEFCnSpKPSkc5Sk/znXTLJ7M47u7PZ2bC7+c6d7uzzvvPOO58JEMP89pV1G9bI+o2r5ffdO/0PmR89esQ2XMmSGf6Hz6tUriaNGp4hpzU4Q9R+omw5OdmyavUy+XHJAtlhXPOBA/uMr7U0f1ihfPkKUqtGXWl7TnupV6dhVJekAhBr1q2S1etWyIaNa2X/gb3+c5wctJg/9FGnVj3j662pZDZrJRklS0V1PqeD1de5+nq3bio40LF9Fyldqoy1HNX+9h1b/V87O3ZuE/8/hu2JE8f9turro3rVmlKtag3/10vNGrUjPFfh/7qLcIJ0RwABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAgrgUIKsT17WFyCCCAQPwIuA4q9DQerAgOCwRfhi48oPpYjlMhBXMLCCtY+oQKIfiPtYxhjuV/zR2DoEKACm8QQAABBBBICAGCCglxm5gkAgggENcC+/bvlede/qt2jq3POk+6XXmjti3aolodYMTIF2Tnru22oWrXrCeD+g+z1fMLOfLU08Pz31r2hgx6SKpWqWGpeLP7j//+0b+iQfBot/UdKnVq1w8uR/TeZ3zi/bwFs2TpsoVy4OD+iI61di5XroK0anGOtDuvo6ggQ7xu6zeukU+/+FDU1164TQUVruveR8qVLR+ua0C7Wp1h8U8LZPa302Xfvj0BbU5vSpQoKSp4coHhp0ITXm7vjHlZNv263jbklV16yrltLrTVIy2oX0/Tv/lKFiycY/x4KP9nSM7jFDPO284fRlLX7W4r/F937uZFLwQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEkOAoEJi3CdmiQACCJxygZgHFawBBHW1xl8yq79mDggpqLq1n+4vos12XVvQ8QQVFAgbAggggAACiSVAUCGx7hezRQABBOJRIFRQQc2362U95byzo3+QOvDac+SDse/Iz2uWB5Zz3xWVoILv8CH/ihILFs6V48ePaS0KUlQPnp93dnsjsNAhZisEFGRe6phvjUDG1BmTjB9zZLseooyxUsbN1w8U9XXhZtuxc6uM/XSMf0UBN/2D+9St3UBuvm6AsdqCdysdxDKooH4dfTF1vOx3EfwIvtayRgDkqi7XilrFJPxGUCG8ET0QQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEHAWIKjgbEMLAggggIBFwFVQoV8ryTRWVDA/ya6YGRowxzHDA8F1s936avZVNWt/p7p5rNFufo5eQMjBOkZuX4IKJhqvCCCAAAIIJI4AQYXEuVfMFAEEEIhXgXBBhZSUFOl78x3SoF4jzy5h1pwpMtP4x2krCkGF1WtXyLjP3pOjR484MURdz8goJdd16y2NGjaJeiwvBpg7f4ZMmzmpQEOlpxeXwQPulSqVq4c8fsWqJYbr+5KVdSJkv3CNFStUlkH9hnoWVohVUGH+97Nl8tcTw11O2PZLOl4p7dt1DtOPoEIYIJoRQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEAgpQFAhJA+NCCCAAAKmQEGCCurYgLCCGTLQhAbM8+S9mn1PDpJXVist5G26cQgq5PGwgwACCCCAQDIKEFRIxrvKNSGAAAKFKxAuqKBmUyqjtPGQ+H1SvnzFqCenPv1draZgLB3oOFZyBxVyZObsKTJr7rSQBo44ETaon0N0uuhy6XDBJcaRAR9hEOFI0XXfsGmtjPrg9YhWUgg+Y9Uq1eX2/veKCi04bV9NmyDf/TDHqTmieoP6p0u/mwcbP8tJieg4XedYBBU2b/1F3hr1P8nOztKdMsJaMbmue29p0axViOMIKoTAoQkBBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAgbACBBXCEtEBAQQQQEAJRBJU0IYJ/M9jmA9lGA8KhHpWwBpGUCe3BhJCtam+we2qZm7WcYwaKyqYMLwigAACCCCQOAIEFRLnXjFTBBBAIF4F3AQV1NxrVK8lt/YZajwknl7gS9m5a7uMGPmCHDt2NOQYyRpUUJ/y/9H4kaJWU4hkK1GipJQuVUZOnDguaWnpcsh3MOKVGJo0zpQbevST1NTUSE7tSd/Dh33y0hv/Ep8xb6ctLS1NSpcuK/v37wsZZmjTsq1c0/UGp2HEy6CCOsnll3ST88/t4Hg+tw1eBxWOHDksr739rOzdtzvkFNSKKBlG0EjZmyt+Oh2gVuAYdsejUrJkhkMXggoOMJQRQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEHAlQFDBFROdEEAAAQRcBRX6tpTMns2cgwVmUMAhTGDGGJR2QI7BPM6om3/JHNBuvT2WvtbQgm7sRaOXyLJxK61H2/Z9Pp/xF9xOf2Ft604BAQQQQAABBGIsQFAhxsAMjwACCBQBAbdBBUWRaXza+vXd+xRIRT1Y/ca7z8vuPbvCHp+cQYUcGfvpe7JsxaKw169CCU3OyJTTGzaRhvUbax8cV54bNq2RdRvWyKo1y+TQoQNhxz2rxdnS8+pbwvbzusO0mZNk7vwZ2mHLli0vl118tf+T/NXqDyrEMvvbr43+M7WBBdVnyKCHpErl6trxnIIKdWrVl7NbnS/VqtbwrxCye+8u2b5jqyz4ca7s3ev8sL8KT9x75/9FFdBRE/U6qDBp8jj5YdE8rYEqqmBKp/aXi1qFQoVTjh8/Llu3/yZTZ3wuv23e5HjchedfLJd2usqhnaCCAwxlBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQRcCRBUcMVEJwQQQACBAgUVggMJZogguJ7LqwsT+Jssx5l9CCrwNYkAAggggEDRFCCoUDTvO1eNAAIIeCkQSVBBnfeSTldK+/M7RzQFFbJ/7+M3Ze36Va6OS8agwoxvvpJv5k0Lef3qE+2V7bltLozowXi10sIPi76VOUYYIFxgoWP7LsYD7F1CzsPLxoNGgOKFV//uf1A+eNxyRkhhYJ+7pUL5SsFN8uOS7+SzLz+21VUhVGAmOKigAg3XdL1e6tVpqB1LBSO++nqiLFqyQNuuij2uullannmOY7ubBq+DCs8bpvqARTEjTNTbb6Sbl/q1qIIg6utRt6l7cv/df9I1GTWCCg4wlBFAAAEEEEAAAQQQQAABBBBAAAEEEEAgQQQ2bdokzzzzjG22Xbt2FfUPGwKxFiCoEGthxkcAAQSSRMBVUKFfq5MrKjgEEUJSmGEE1akgx6vj1BgRHMuKCgqNDQEEEEAAgcQSIKiQWPeL2SKAAALxKBBpUEF9on2vG26T009r6vpyvp71hcz5drrr/skWVFixaol8PGFUyOtXn4CvVjsoUaJkyH6hGo8fPyaffvGRLFu5OFQ3ub5HX8ls2jJkH68a1Sf4z/tupna4W/vcI3XrNNC2qeK4z96Tn5b/qGkvJvcMflgqV6pqa7MGFVoYK4B0u/JGI/RR3NYvuKDcFi3VhxXObN5aru3WO/iQiN57GVQI9Wu23XkdpUvna8LO7f1P3pLVa1do+9156wNSvVotTRtBBQ0KJQQQQAABBBBAAAEEEEAAAQQQQAABBBBIIIEFCxZI27ZtbTN+8skn5YknnrDVKSDgtQBBBa9FGQ8BBBBIUoFIggrq0+rMzXHlA7ODerWGFMy6ZQyzFPLVHCOC4wgqhBSlEQEEEEAAgbgUIKgQl7eFSSGAAAIJJRDqoWenC1EP09/e/17tg+LBxyw3HtL/JMxD+sHHJFNQQa128OJrT8v+A/uCLzP3fTHpeOGl0ukitcqBq58aOIyTX/52wSyZOmOS8dkF2flFy17ZMuVk6B2PRrRqg+XwCHZz5NmX/yb79++1HePm4X/1tanssrJO2I5Xq0Ko1SGCNzOocE7rC+Sqy68NbnZ87zt8yH+uI0cO2/qEXmXA1l1b8DKosHTZQhn/+fu286Snp8sj9/1FUlPTbG3BhX379shzr/wtuOx/f2PPftKsyVmaNoIKGhRKCCCAAAIIIIAAAggggAACCCCAAAIIIJBAAgQVEuhmJelUCSok6Y3lshBAAAGvBVwHFXo0FTOm4PpxAzNkYJ10BIED/2HmGBEcR1DBCs4+AggggAACiSFAUCEx7hOzRAABBOJZIFRQoXz5iqIeaNZtVSpXk0H9hoVcAWD7jq3y5qgXRX3Sv27LKFlKDh/x2ZqSKagwe940mf7NV7ZrNAudO3aVi9pdYr717PWHRfNk0uRxjuNd3OEK6XDBpY7tXjRs3vKLjBj5gnaofrfcKQ3rn65tsxbHfDRC1q5fZS3596tVrSl33fagra6CCrv3/C63XD/Q+ByIFFt7qMLM2ZNl1typti5qnMcf+adRd/2THdsYXgYVnFapqF2rnv/XpO3kDoX/vPiUHDp0wNZ6ZZeecm6bC211Y9lOeerp4Zq6yJBBD0nVKjW0bRQRQAABBBBAAAEEEEAAAQQQQAABBBBAAIF4ESCoEC93oujOg6BC0b33XDkCCCAQkYCroELflpLZs1nIcc0Qg+qk++tu1a6r+1ddcBlCcBzDMjPVZ/HoJbJs3EpL1b7r8/kkIyPD3kAFAQQQQAABBE6JAEGFU8LOSRFAAIGkEggVVLhj4P0y8v3XtGEChXDG6c39D4Tr/sv18GGfvP7uc7J3726tV+NGzeT005rIl1Mn2NqTJajg8x2U51/9hxw7dtR2japwZmYbufaaXto2L4pfTZso3/0wWztU8eIlZNidj0rpUmW07V4UnR6oL1kyQ4YPe0pSUsIHCRYsnKP9GlHzG3rHH6RSxSoBU925a5uUL1dR1PVFuq38+Sf5aPy72sMevu/PooI1Bd28DCrMmT9dvp75hW0qp5/WVHrfOMhWdyr8+4UnRX2NBm9XXNpD2p7TPrhsvCeooEGhhAACCCCAAAIIIIAAAggggAACCCCAAAIJJEBQIYFuVpJOlaBCkt5YLgsBBBDwWsCLoII1pGDOzxpKsLZb6/6QgnmAJaxg9rf2NWuqu7VuHq5ezT5qRYXlBBWsNOwjgAACCCAQ9wIEFeL+FjFBBBBAIO4FQgUV/nD/X2Xz1l9k9IcjJCcnW3st6lP51afzWzfVd/SHb8j6jWus5bx99XD54AH3ydLlC+WLKePz6uZOsgQVFiycazxkb78+dZ0VKlSSuwc9LGlpaeZle/6q7sNrbz8n23ds0Y7dpfM10u68jto2L4pvjX5Jfv1to22oFs1ayXXd+9jqusLuPbvkxdee1jVJ9ytvklZnnattK0hRhRxeHvEf7aEP3PO4lC1TTtvmpuhlUGHedzNFhUCCt3Jly8v9d/8puKx9n52dJf/47x/lxIkTtvZbrr/VH0KyNRBUsJNQQQABBBBAAAEEEEAAAQQQQAABBBBAAIGEEiCokFC3KyknS1AhKW8rF4UAAgh4L1AYQQU1azNEEBAyKJb7zhJScOzrNIY6IHczz8GKCqYIrwgggAACCCSOAEGFxLlXzBQBBBCIV4FwQYUSJUqK04PR5jXd2LOfNGtylvlWpkz/TL5dMCvvvXVHfdL9oH5DpWqVGvL9j3OTOqgw8oPXZINDWKPnNbfIWZlnW2lisr92/SoZ89EI7dgN6p8u/W+5U9vmRfHpZx+To0eP2Ia6rltvadG8ta3uVFBBBRVYCN5UyEKFLbza9u7bLc+/8nftcH986OmoQiVeBhWWrVwsYyeO1s5zQO8hUr/uado2a3Hlz0uN1SNGWkt5+3ff/rBUqVwt733+Disq5FuwhwACCCCAAAIIIIAAAggggAACCCCAAAKJKEBQIRHvWnLNmaBCct1PrgYBBBCImUCkQQUVBggIG6iZOQQOdJM2wwTWNtt41kbNvjlG3nHq/Jawg1pRYRkrKmjkKCGAAAIIIBC/AgQV4vfeMDMEEEAgUQTcBBXUtYz9dIwsW7FIe1np6cX94YNqVWv6V0kY/9n72n6qeEOPftK86clQQzIHFY4cOSz/fuEJyc62r0ShQhp33fag8WOBvP9Cd/TyouHtMf+TX37dYBsqJSVFhg97SkqWzLC1RVvYv3+vPPvyX7XDPDTsSSldqoy2TVecNHms/LDoW1vTaQ3OkL43D7bVC1r4bfMmeXPUi7bDVbjm0Qf+ZqtHUvAyqHDw4H757//+ql3lpHy5CnLnrQ+GvKcHDx2QV4yVI3yHD9kuISOjlDw09AlJSUm1tamP03jq6eGausiQQQ/5w0faRooIIIAAAggggAACCCCAAAIIIIAAAggggECcCBBUiJMbUYSnQVChCN98Lh0BBBCIRCCSoIIZEFDjBzyCYD6QYAkLOM3BOoa1T8B41gbNvnWMgIchcs9PUEGDRgkBBBBAAIE4FyCoEOc3iOkhgAACCSDgNqhw/PhxeWv0i7Jt+xbtVVWoUEmuvvx6+WDs23LixHFtnwvPv1gu7XRVXlsyBxVCfWJ9545d5aJ2l+Q5xHrnh0XzZNLkcdrT3NCjrxEcaalti6botJJDsWIp8vgj/zSGdv8TjW/mTZMZ33xlm07ZMuXkgXset9ULWlBhCBWKCN5q16pnBHGGBZcjeu9lUEGdWK2SoYx1W80adaTHVTeJCg4Fb1u3bZYJkz6QHTu3Bjf531928dVyQdtO2jaCCg4slBFAAAEEEEAAAQQQQAABBBBAAAEEEEAgYQQIKiTMrUraiRJUSNpby4UhgAAC3goUdlBBzd4aNDCvxv1f6588Qo2RdwwrKpiMvCKAAAIIIJCwAgQVEvbWMXEEEEAgbgTcBhXUhPfu2y1vvPO89pPYw11Qo4ZnSO8bbw9YRSCZgwrzvpspU2d8rmW5Y+ADUqN6LW1bLIr79u2R517RrwhwSccrpX27zp6fdumyhTL+c/vKGmolBbWiQiSbU9AiNTVVHhuuQg/ebE4P/6sH99UD/NFsXgcVNm/5xQgOvaRdsUPNU62I0KZlW6lbu76oVRbUr/Nfftsgi5YucDymbNnyMuyORyUtLc3hUllRwQGGMgIIIIAAAggggAACCCCAAAIIIIAAAggkiABBhQS5UUk8TYIKSXxzuTQEEEDASwE3QYXWfVtKZs9m+cEAYwJm2CAvLJA7KbNuzjG43azn9VOrIBhBg3D9nNrN8ayvrKhg1WAfAQQQQACBxBAgqJAY94lZIoAAAvEsEElQQV3Hhk1rZdQHr0tOTrbry1KrLQwecJ9klCwVcEwyBxW+mjZBvvthTsD1qjeljAf1hw97wtiL5L/YbcNEXHjxtadl955dtuPannORXHFpd1s92sL3P86TL6bYV3GoWqW6DBk0PKLhl69cLJ9MHK095rHhT0tqqtOD9dpDtMXDh33yzEt/lqysE7b2XjfcJo0bNbPVIyl4HVRQ5/5m7lSZMXtyJNNw7KtW3ryuex/JDLm6BkEFR0AaEEAAAQQQQAABBBBAAAEEEEAAAQQQQCAhBAgqJMRtSupJElRI6tvLxSGAAALeCUQbVFAzMR9JyAsfBE3PbA8qGw+D5B+h/iI5eMtvzT9HcB/de4IKOhVqCCCAAAIIxLcAQYX4vj/MDgEEEEgEgUiDCuqa5n8/WyZ/PdHV5aWnp8ttfYdK9Wr2FQSSOajw4bh3ZNXqZTajmjXq+EMbtoYYF9597xXZ+Ms621laNGvlf0Dd1hBlYc786fL1zC9so9Sve5oM6D3EVg9VWL9xjRGOeU3bZfi9T0mpjNLatkiK02ZOkrnzZ9gOKVOmnNw/5DFjhYIUW1skhVgEFdTPhz798iNZvPT7SKZi66tWX7i2W68wIQV1GEEFGx4FBBBAAAEEEEAAAQQQQAABBBBAAAEEEEgoAYIKCXW7knKyBBWS8rZyUQgggID3Am6DCi2MFRWCNzNIYEYMzPfWfmabtWbd94cVWFHBSsI+AggggAACRVKAoEKRvO1cNAIIIOCpQEGCCmoC4z97X5YuXxh2Ltd26y1nNm+t7ZfMQYU3R70ov23eZLvu009rKr1vHGSrx7rwyYRRsnzVEttpGtQ/XfrfcqetHm1h+qwvZfa3X9uGaXpGC7np2gG2eqjCtu2b5bW3n9V2GXbno1KxQmVtm9viwUMH5IVX/y7Hjx+3HXJRu0ukc8eutnqkhVgEFU7OIUfe+/gtWbNuZaRTyut/83UDpUnjzLz3zjsEFZxtaEEAAQQQQAABBBBAAAEEEEAAAQQQQACBRBAgqJAIdym550hQIbnvL1eHAAIIeCbgJqjQpm9LydQEFcxJmAGFcKEEs7/uNdwYZrs6Nvg8ZtjBHFetqLB8XOi/2Pb5fJKRkWEewisCCCCAAAIInGIBggqn+AZwegQQQCAJBAoaVDhx4ri8Nfol2bpts6PC+ed2kMsv6ebYnsxBhREjX5DNW36xXXvzpi3lhh59bfVYF5yCJfXqNpSBve/2/PROKxRkGtd/fYTXv+v37fK/N/6tnePQO/4glSpW0ba5LX4xZZx8/+M8W3e10sAwY/zy5Sva2iItxCqooFbtmDDpAzl69EikU8rrX6N6Lbm+e1+pXKlqXk2/Q1BB70IVAQQQQAABBBBAAAEEEEAAAQQQQAABBBJFgKBCotyp5J0nQYXkvbdcGQIIIOCpQLwFFdTFBQcRVM0pqOAPKagOajNWZlAbQQU/A/9CAAEEEEAgoQQIKiTU7WKyCCCAQFwKFDSooC5GHfv6O8+Jz3fQdm3qk/r73jRYUlJSbG1mIZmDCmM+GiFr168yLzXvtWGDxtLv5jvy3hfWjtN8CrLCgZs5z5o7VWbOnmzrelqDM6TvzYNt9VAFtTKFWqFCtz049AkpU7qsrslV7bctm+StUS9JwM9Jco887+z20vWyHq7GCdcpFkGFGd98Jd/Mmxbu1K7aixcvIf173Sm1atQN0Z+gQggcmhBAAAEEEEAAAQQQQAABBBBAAAEEEEAgAQQIKiTATUryKRJUSPIbzOUhgAACXgl4FVTQhQsimaM1iKCOCx7P2m5ry8ltJagQCTl9EUAAAQQQiCsBggpxdTuYDAIIIJCQAtEEFdQFb/xlnYz64DXJzs7Ou/7y5SrI4AH3SalSZfJqup1kDiqM//x9Wbpsoe2yq1WtIXfd9pCtHuvCa2//V7Zt32I7TZtWbeWaK26w1aMtzP/+G5n89ae2YWrWqG18bdxvq4cqrF67Qt7/5C1tl/978B+Snp6ubQtXzMrKktfeflZ27tpm66oe3L/3zkfDfg3bDnQoeB1UWPnzUvlo/EiHsxWsXC73121px1+3BBUKJstRCCCAAAIIIIAAAggggAACCCCAAAIIIBAvAgQV4uVOFN15EFQouveeK0cAAQQiEogkqGANCxgf0XfyPEY4IDg4YE7A/BS/YrkBAlXX1fx186CTnfzvAo5zqJuH+WeTO6dFY5bK8nErzSbtq8/nk4yMDG0bRQQQQAABBBAofAE3QYWqVatK5cqVC39ynBEBBBBAoEACY8aMkTZt2hTo2IIcFG1QQZ1zwcI58uXUCf7Tp6Wlya197pGaNeqEnU4yBxWmTP9Mvl0wy2aQlpYuj9z3Z1GvhbUdO3ZU/vX846IezA/eLmp3iXTu2DW4HPX7H5d8J599+bFtnPLlK8p9d/3RVg9VWPzT9zJx0oe2LsWKpcjjj/zLVndbmDlniswy/tFtnTtcIRddcKmuqUA1L4MKBw7ul1dG/EcOH/Fp55Kamirnn9tBmpyeKVUqV5MSJUrI7j2/y46dW2XO/Omyddtm7XGq2KRxptx83UCHdoIKDjCUEUAAAQQQQAABBBBAAAEEEEAAAQQQQCBBBAgqJMiNSuJpElRI4pvLpSGAAAJeCsQqqGAGEtRcAwIHZsAhuG69qNw+1uPESCLgrJ1LAABAAElEQVTkqH8FHRd42Mn2RaONoMJ4ggpWG/YRQAABBBCIdwE3QYV4vwbmhwACCCAQKDB79mxp3759YDGG77wIKqjpTZs5yf8AdKuzzpUzm7d2NeNkDio4PaivYHrdcJs0btTMlZEXnVb+/JPx6fvvaoe6vkdfyWzaMq9N/Vzi2f/9RQ75DubV3O507tBVLjz/Yn/35SsXyycTR9sOVSsVPPrA32z1UIV5382UqTM+t3UpWTLDCH38xVZ3U9ixc5u8/s6z2vBGjeq15Pb+90pKSqqboVz18TKooAIg6utLt9WpVV96XnOLVKpYRdfs/yCMRUsWyKQpYwNWQcnvXMy/kkSFCpXyS3l7BBXyKNhBAAEEEEAAAQQQQAABBBBAAAEEEEAAgYQUIKiQkLctqSZNUCGpbicXgwACCMROIJKggprFyShA4HyKBb71vzODCgFhA3W8Q1BBHRQ8ttO4/jUcNI3m8YtGL2FFBf9d4F8IIIAAAggkjgBBhcS5V8wUAQQQcCuQqEEFt9dn7ZfMQYW9e3fL86/+3Xq5eftnt2onV19xXd77WO+M//x9WbpsoeY0xWT4sCekVKkyeW05Odny538+nPc+kp1LOl0p7c/v7D9ky9Zf5Y13n9ce/tjwf4r61H+3mwrBzJ0/w9a9dq16MqjfMFs9XOHEiRP+uakVBoK31NQ0GTzgPqlWtUZwU1TvvQoqZGdnyX9eeEq7mkKpjNJy120PSpky5cLOVXkqV92m7qG6l/aNoILdhAoCCCCAAAIIIIAAAggggAACCCCAAAIIJJIAQYVEulvJOVeCCsl5X7kqBBBAwHOBSIMKugmYAQF/m241BMtBoYIKqpt1LE0WIfcU+b2sQQizSlDBAs4uAggggAACCSJAUCFBbhTTRAABBCIQIKggUrum8QB6/1APoBf+A9P/+O8f5dixo7Y7eVvfoVKndn1bXRVeePUfsmfv77a29PTiMuzOR6VM6bK2Nq8Lu/fskv+98W/j0/OzbENXq1rT/2C7tcGroIKy+sd/HzOGNn/qkH8WFQSoWaNOfiHM3nsfvylr1tlXgGzd8jzp1vXGMEfbm7+cOl4WLJxrbzAql118tVzQtpO2LZqiV0GFX3/bKG+Nfkk7leu795HMZq20bfZijrw58iX5bcsmW1P9eo1kQK+7bHV1L596erimLjJk0ENStYq34Q7tiSgigAACCCCAAAIIIIAAAggggAACCCCAAAJRCBBUiAKPQz0RIKjgCSODIIAAAskvEG9BBSVu/tU/QYXk//rjChFAAAEEEDAFCCqYErwigAACySNAUCF5ggqTv/5U5n//jfaLs7BWVfho/Luy8ueftHPo1L6LdDT+sW5eBRXUmM+/8nfZu2+3dXj/vu68tk65hePHj8u/nv+TqFUQgrfLL+ku5597UXA55PvVa1fI+5+8pe1Tr25D4wH9IWL9cAdtxwIUvQoqLF+5WD6ZOFo7g0fu+4uULJmhbdMVZ8yeLN/MnWprqlChktx75//Z6gQVNCSUEEAAAQQQQAABBBBAAAEEEEAAAQQQQCChBAgqJNTtSsrJElRIytvKRSGAAALeC7gJKrTu21IyezZzPLkuUGCunBD8l+JmXQ1ma8s9gzmeGViQ3FUazAkUE6OH2cksGq/+/kbfRaOXyvLx9k8otHQVn88nGRnu/9Lbeiz7CCCAAAIIIOC9AEEF700ZEQEEEDjVAgQVkieosH//XnneWFVBt5pBSkqKDOg9ROrWbhCzL7kVq5bKxxNGasdPS0uX++9+TEpllA5o9zKo8MHYt+XnNcsDxldvatWsK7f3v9dW1xXU8Woc3ab86tc9TdekrR04uF9effMZ8R0+ZGtXq1sMHni/lC1TztbmRcGroML872fL5K8n2qak5v/g0Cds9VCFVauXyYfj3rF1SUlJlT89/LRRD/4hEisq2LAoIIAAAggggAACCCCAAAIIIIAAAggggEBCCRBUSKjblZSTJaiQlLeVi0IAAQS8F3AdVOjRVCUL8idghgeMmqWa1+4USAhbt4xnBg/yBs3dCQ44mO3m2AQVTBFeEUAAAQQQSBwBggqJc6+YKQIIIOBWgKBC8gQV1D2fOOlDWfzT99rbX6pUGbm93zBRn2Dv9bZ56y/yzphXjJUIjmuHPrfNhXJll562Ni+DCj8s+lYmTR5rO4d6AP6hoY9LaePh+nDbp19+JIuWLLB1y8goJcOHPWn8yCXF1qYrqJ99jPrgNdmwaa2tWT2YP6DXXVK3TgNbm1cFr4IK3/0wR76aNsE2rbS0NHn0gb+LCsC43ZavWiKfTBil7f7EH/5t1IN/ckVQQYtFEQEEEEAAAQQQQAABBBBAAAEEEEAAAQQSRoCgQsLcqqSdKEGFpL21XBgCCCDgrYDroELwigpmUMGYji44YIYG1Gyt7ZHUrX2tV20dz1o3+xNUsKqwjwACCCCAQGIIEFRIjPvELBFAAIFIBAgqJFdQYfeeXfKK8Sn+ToGBKpWrS79b7vD0k/y379gioz58Qw4dOqD90itRoqQMue0hKVeugrb96NEj2nq4onpYPjU1La/bQWMFg2de+ovx3v+RCnl1tXNN1xukTcu2AbXgN9nZ2fLs//4iBzXX0fqs86TblTcGH+L4fubsyTJr7lRt+1WXXyvntL5A2+ZV0augQqhwwZ23PijVq9V0PeUp0z+TbxfMsvVXAZKHtKszEFSwYVFAAAEEEEAAAQQQQAABBBBAAAEEEEAAgYQSIKiQULcrKSdLUCEpbysXhQACCHgv4Cao0KZvS8m0BBV0Kx0EhwfM0ICasbXNqZ53ZcbgObl/8e9fq8H40DvrMcHjqfdmu3meRaOXyLJxK/OG1O34fD7JyMjQNVFDAAEEEEAAgVMgsHfvXunTp4/s379fVq7U/zles2ZNqV69+imYHadEAAEEELAKHD9+XGbNsj8UbO1z2mmnycSJE6VFixbWckz39+3fK8+9/FftOf5w/19FPdQeq+37H+fKF1PG24avXbOeDOo/zFbPLxT+A9P/+O8f5dixo/lTyN27re9QqVO7vq1uLXz/4zzjOsdZSwH76sHwG3v2k3p1GgbUC/Jm+crFMvGLD0V9vTltPa6+WVq2OMep2dP6m6NelN82b7KNqVaRuHvQw6LCDU7b/O9ny+SvJ2qbe91wmzRu1EzbFlxcs26lvPfxW0bZHpho3dIIPHR1H3gIHtvte6+CCmqljBHvvqA9rfLodcOtRpvxQ6Ew2+EjPnnt7Wdl3749tp5nNm8t13brbasrv6eeHq6piwwZ9JBUrVJD20YRAQQQQAABBBBAAAEEEEAAAQQQQAABBBCIFwGCCvFyJ4ruPAgqFN17z5UjgAACEQkUJKigTmCGA6wnM4MCwe1u6tZxzLHdHGf2Vceb/QkqWDXZRwABBBBAAAEEEEAAAQS8FdizZ49UqlQp5KBPPPGEPPnkkyH7eN1IUMGdaDRBBXWG9z95S1avXeF4spSUVGnfrrNccF7HAoVDDhzYJzPnTJEfl3zneA7V0KzJWf5QRMhOHjYuXb5Qxn/2vnbEdsa1dul8jbbt99075Y13nxfd6g5qFQr1YLz58wztALnFPXt/l9ffeU6OHDls66YCMQP7DAlYBcLWyaOCV0EF9fOcZ158Sg75DmpndtnFV8sFbTtp28yiGuO9j9+UtetXmaWA1+5X3iStzjo3oHbyDUEFDQolBBBAAAEEEEAAAQQQQAABBBBAAAEEEEggAYIKCXSzknSqBBWS9MZyWQgggIDXAgUKKlhWPbDOx1wBQdV0AYJQdXOcghxnHmP+xT5BBVOTVwQQQAABBBBAAAEEEEDAewGCCnbTorKigrpy3+FDoh5W37lrux3CUilZMkPandtBWhifal+pYhVLi353+44tsvin7+WHRd/KiRMn9J1yqzWq15L+t9wl6hyFtamfPbw84t+y6/cd2lN2bN9FOlxwqaSkpOS1b9+x1XiQfoTsN8IXuu36Hn0ls2lLXVNATa0q8eaoF0SNF7yVLVNObu9/r5QtWz64KSbvvQoqqMmpVUjUrx2n7YzTm8vll3TTfv1s3LRWpsz4XLZu+83pcLn/7j9JOa0LQQVHNBoQQAABBBBAAAEEEEAAAQQQQAABBBBAICEECCokxG1K6kkSVEjq28vFIYAAAt4JRBpUyAsFSLH8SeTumm2qwQwNqH03ddUveHMzhvUY8zyLxyyVZeNWWpts+z6fTzIyCu+BBtsEKCCAAAIIIIAAAggggAACCSpAUMF+42IRVKhWtabxgHZl+8kiqNSqUUcuMh6et27Rrqigxjp06IC8+/6rYcMK5nkrVKgkpzVoLBXKVZTSpcpK8RIljBUGDhvjHJTdxkoB6zasloMH95vdQ75WrVJDBvS+S0pllA7ZLxaNy1culk8mjnYcukrlatLcCB4UTy8uW7dvlhWrlgT8TMR6YPVqteTOW+83Spafr1g7WPbVSg5qRQenrVix/HCEU5/getkyZf0P8gfXw733Mqhw0Pg6eun1f2pXmzDnoVboUMGUKpWqSalSpf2hDxUW2bHTHtowj1GvKiBzXbfe1pJl3zmoEKtfd5aTs4sAAggggAACCCCAAAIIIIAAAggggAACCEQtQFAhakIGiFKAoEKUgByOAAIIFBWBSIIKZhBA2fhXTzCR4iyosGj0Ulk+nqCCeXt4RQABBBBAAAEEEEAAAQS8FCCoYNeMRVDBfpbIK40bNZNeN9wWcKAXQQU1oAorjPzg9bAPjAecPMo3tWvWk5uvHyhlSpeNcqSCH/7huHdk1eplBR/AODI9PV0G9Rsm6qH4cNuChXPly6njw3WLuL2MsRLDg/c8HvFxXgYV1MnVChqTJo+NeB6hDqhapbp/lYl0IzCi35yDCvr+kVV1v+4iG4HeCCCAAAIIIIAAAggggAACCCCAAAIIIIBAaAGCCqF9aI29AEGF2BtzBgQQQCApBNwGFZr3aBpwvQUNKqhB1EoJOTlqz/8vtaPdnFZUUJ2tbeq9NURBUEGJsCGAAAIIIIAAAggggAACsREgqGB3LYpBBaVw4sQJmTrjc1EP04f7b3y7WmSV88+9SC67+GpRn7B/KrejR4/IG+8+L7/v3lngafS8+hY5q8XZYY/f9Ms6fxgkOzsrbN9IO8RLUEHN++uZX8ic+dMjvQRt/+LFS/hDCmp1C+eNoIKzDS0IIIAAAggggAACCCCAAAIIIIAAAgggkAgCBBUS4S4l9xwJKiT3/eXqEEAAAc8E3AQVWvdtKZnBQQUjbGBu1pCAWbMGCXTtJ/vlj2EOZ+3rbgzzjPmvBBXyLdhDAAEEEEAAAQQQQAABBLwWIKhgFy2qQQVTYt2Gn41PxR8ne/b+bpY8e61Zo7Zc0vFKadSwiWdjRjuQCimM+WhEAa63mHEtXaV9u85hp7B7zy4Z8e4LcviIL2zfgnSIp6CCmv8386bJzNlTjA+iyC7I5fiPqVSxilzT9QZpUK9RmDEIKoQBohkBBBBAAAEEEEAAAQQQQAABBBBAAAEE4lyAoEKc36AiMD2CCkXgJnOJCCCAgBcC8RZUUNdkhhUIKnhxhxkDAQQQQAABBBBAAAEEEPBWgKCC3bOoBxWUiPpv+ZU/L5W582fKlm2/2pEirKiAQscLu0iTxpkRHlk43Y8cOSyfTBwtKqThZlOf9H/tNb1cXY8ae8TIF6JatSHcnOItqKDmu+nX9fL5V5/Irt93hJt+QHt6erpc1O4SuaBtJ0lNTQto078hqKB3oYoAAggggAACCCCAAAIIIIAAAggggAACiSJAUCFR7lTyzpOgQvLeW64MAQQQ8FQg2qCCGSrQTUoFDYznFIzN/y9NF8uKCqrVeBs4XjFRKy2EHsM+LCsq2E2oIIAAAggggAACCCCAAAJeCSRaUKFEiZIyfNhTxgPMqV4R2MZZsWqpfDxhpK1eu2Y9GdR/mK2eX8iRvz/zRzl+/Fh+ycO9VmedK92vvClgxGdefEoOHjoQUFP/QT70jkdEfSK9F9v2HVuMB/hXy/qNa+SX39Yb13fc1bApKSlyaaer5IzTm0vlSlVdHXMqO6mfYaxdv0oWLJxrvKrAgv3nH2VKl5Vz2lwg57RuJ6VLlXE13Q2b1srI91911begnWpUryV3DHwg4sPVShLqmoO3K7v0lHPbXBhcjvi9Ml21+idZuHi+EVzYICdO6L92VCBBfY3UrlXXH2gpX65CBOcq/F93EUyOrggggAACCCCAAAIIIIAAAggggAACCCCAQFgBggphiegQYwGCCjEGZngEEEAgWQTcBBXa9G0pmT2a+YME5nUHBgrMqtOrGUgI/At7I4aQd0CO5i/zA06obT95+MlARP7YBBXyWNlBAAEEEEAAAQQQQAABBDwXiNeggucXyoCeCKjVASZ//aks/ul7V+NVKF9JzsxsIy1bnJ0QYQXzog4f8cmevb/L3r175Nixo1KuXHmpWKGylC9XUVQAgy1ygaysLNm67Tc5cHCf+A4fMkILJ0R9fVStUt2wrWR8uAWukatyBAIIIIAAAggggAACCCCAAAIIIIAAAggkgwBBhWS4i4l9DQQVEvv+MXsEEECg0AQKN6igLis/UOBFUEGFFMzNDE8QVDBFeEUAAQQQQAABBBBAAAEEvBcgqOC9aVEYUa2w8NlXH8u+fXtcX26N6rWlSeNMaXJ6ptSsUcs4Lv9nAOYg2dlZoh5oT08vbpZ4RQABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAgqQV+/vlnueeee2zX2K9fP+nbt6+tTgEBrwUIKngtyngIIIBAkgpEFFRQBsYzAWYgwD1J8IMEJ8MKZlBBv5pC7snyTpIfcMgrGTv+MYLmRFDBKsQ+AggggAACCCCAAAIIIOCtAEEFbz2L0mhqpYFpM7+QHxbNi/hnCyVLZkidWvWlerWacvDgAUlNTZWt2zfLjp3b5MzmraX7VTcVJUquFQEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBA4ZQIEFU4ZPSdGAAEEEksgkqCCc6Ag/5r14QOzmt9P7TmNZ/YObDeqZt7BklkI7HNyfIIKgc68QwABBBBAAAEEEEAAAQS8FCCo4KVm0Rxr+44tMmX657J+4+qoAerXPU163XCbFC9eIuqxGAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQCC8AEGF8Eb0QAABBBAwBLwMKpgBAwVrDRBY61Z0ax9r3ewf3F7MTCoQVLBysY8AAggggAACCCCAAAIIFKoAQYVC5U7qk63b8LN8PetL2brttwJdZ8MGjeWW626V9PT0Ah3PQQgggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAApELEFSI3IwjEEAAgSIp4Dao0LxH07A+TgEDdaDZZg4SHEIw62Zfp3brOE59WFHBqsk+AggggAACCCCAAAIIIOCtAEEFbz0ZTWTb9i2y+KcF8tPyReI7fMgVyemnNZWbrh0gaWlprvrTCQEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAwBsBggreODIKAgggkPQCboIKrfu2lMygoII1MGAiOQUHzPZQr9bxohlHnYOgQihp2hBAAAEEEEAAAQQQQACB6AQIKkTnx9HOAllZWbJ67QojtPC9rF2/SrKzs7WdmzTOlBt69JPU1FRtO0UEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAIHYCRBUiJ0tIyOAAAJJJRBvQYVoQwrq5hBUSKovUS4GAQQQQAABBBBAAAEE4kyAoEKc3ZAknU5W1gnZuWuH8c822bHT+Md43blru9SpVU96XH2zpKQQUkjSW89lIYAAAggggAACCCCAAAIIIIAAAggggAACCCCAQJwLEFSI8xvE9BBAAIF4EShoUEE//2K55Rxbs1oxwYsQgm1goxC8GgNBBZ0SNQQQQAABBBBAAAEEEEDAGwGCCt44MgoCCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACiShAUCER7xpzRgABBE6BQERBBWv+wMwkBMzZWszvHBwkCDgk7BtzTGM8c0izZBxrHdscatHoJbJs/ErzrfbV5/NJRkaGto0iAggggAACCCCAAAIIIICAswBBBWcbWhBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBIdgGCCsl+h7k+BBBAwCOBwggqqKmagYLIV1UwUwnugwo/GkGF5QQVPPoKYRgEEEAAAQQQQAABBBBAIFCAoEKgB+8QQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQKEoCBBWK0t3mWhFAAIEoBCIKKljPY1vdQAUKzKK1Y+6+ajIzBwHNluMc+6gDTkYdtEGHoOMWjV5KUCHAmDcIIIAAAggggAACCCCAgHcCBBW8s2QkBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBJNgKBCot0x5osAAgicIgEvggoBqyWYWQVrKMGsqWu01q1vcnI7BbTno5jnUJWAsIJmbIIK+W7sIYAAAggggAACCCCAAAJeCxBU8FqU8RBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBIHAGCColzr5gpAgggcEoFCiWooK5QBQpsIQSzYDSagQOzFKTiGFQwx1avuccSVAjC4y0CCCCAAAIIIIAAAggg4KEAQQUPMRkKAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAgQQTIKiQYDeM6SKAAAKnSsBNUKFN35bSvEfTk1MMEyjw+jrMgELAKgpOJ8md26IxS2X5+JVOvfx1n88nGRkZIfvQiAACCCCAAAIIIIAAAgggYBcgqGA3oYIAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIBAUREgqFBU7jTXiQACCEQp4DaokNmjmeTkmCkF46QOKx9EOZ2Aw82QgioSVAig4Q0CCCCAAAIIIIAAAgggcMoECCqcMnpOjAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggMApFyCocMpvARNAAAEEEkPAbVAhYEWFQggpmHpmWCFsUMGSoWBFBVOPVwQQQAABBBBAAAEEEEDAewGCCt6bMiICCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACiSJAUCFR7hTzRAABBE6xgJugQuu+LSWzR1PnmVpCAs6djBZNwEEFEWwhBHO84P6qHlxTJzT7q31jI6hw0oF/I4AAAggggAACCCCAAAKxECCoEAtVxkQAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAgMQQIKiTGfWKWCCCAwCkXKNSggrpaS9DAXC1BlQPCCmbwwNI3IIzgVFcDGRtBhZMO/BsBBBBAAAEEEEAAAQQQiIUAQYVYqDImAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAokhQFAhMe4Ts0QAAQROucCpDCqoi3e9ooIZXjh5UL6btZ5bJaiQz8MeAggggAACCCCAAAIIIOC1AEEFr0UZDwEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAIHEESCokDj3ipkigAACp1TAVVChT0vJ7NHUeZ7FzCUONKmB4KN0XczDQ/W19rGOYdSDww6LRi+V5eNXBo8W8N7n80lGRkZAjTcIIIAAAggggAACCCCAAALhBQgqhDeiBwIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAALJKkBQIVnvLNeFAAIIeCwQF0EFdU3WIIJ5jUGBBLMslnqxvJCEGOWTDQQV8qTYQQABBBBAAAEEEEAAAQQ8FyCo4DkpAyKAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCQMAIEFRLmVjFRBBBA4NQKeBNUiOAaLCGDgKOCgwq6fqqPpq7CCmZIQY1JUCFAljcIIIAAAggggAACCCCAgKcCBBU85WQwBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBJKgKBCQt0uJosAAgicOoGIggpmmCA4LGDW1WUEtwVfmtnX6Gd29ZfMupsxgsdU7y3HE1TQAVFDAAEEEEAAAQQQQAABBLwRIKjgjSOjIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIJCIAgQVEvGuMWcEEEDgFAgUKKig5mmmDNS+GRKw1lRdt5l9jbYcS39jUYT8zVLPL7rYyx2DoIILK7oggAACCCCAAAIIIIAAAgUUIKhQQDgOQwABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQCAJBAgqJMFN5BIQQACBwhCIOKhQ0BCBeTGhAgmqzYPxCSqY2LwigAACCCCAAAIIIIAAAt4LEFTw3pQREUAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEgUAYIKiXKnmCcCCCBwigVcBRX6tpTMHk0jDxGYoQRr+MCsqeu21q0OZp9w7WoISx/zsEVjlsry8SutI9r2fT6fZGRk2OoUEEAAAQQQQAABBBBAAAEEQgsQVAjtQysCCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACySxAUCGZ7y7XhgACCHgoELOggpkaUHO1hAnEqW69JrOP9Thduxra0sc8jKCCFYt9BBBAAAEEEEAAAQQQQMBbAYIK3noyGgIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAKJJEBQIZHuFnNFAAEETqGAq6BCn9wVFdzOUyUGLAECt4dp+0Uwljql6k5QQStJEQEEEEAAAQQQQAABBBDwRICggieMDIIAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIBAQgoQVEjI28akEUAAgcIX8DyoYC5rEEVQwTy0mDmWYjGLIYjMLovHLJXl41eG6Cni8/kkIyMjZB8aEUAAAQQQQAABBBBAAAEE7AIEFewmVBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBAoKgIEFYrKneY6EUAAgSgF4jqooK7NDCuYKYQQ12t2IagQAokmBBBAAAEEEEAAAQQQQCBKAYIKUQJyOAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIJLEBQIYFvHlNHAAEEClMg4qCCCg6YiYBIJmo5Th1u5g8iGcJt30WsqOCWin4IIIAAAggggAACCCCAQMQCBBUiJuMABBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBJJGgKBC0txKLgQBBBCIrUBEQQVrusAhrGCWrV2tqYQcs4NxWQF9PLxMggoeYjIUAggggAACCCCAAAIIIBAkQFAhCIS3CCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCBQhAYIKRehmc6kIIIBANAIFCipYwgbB5zabbCEEVchtVC+29uCBonhPUCEKPA5FAAEEEEAAAQQQQAABBMIIEFQIA0QzAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAkksQFAhiW8ul4YAAgh4KRBRUCHoxF4HDnTj6WpB0wh4q/ovHrNUlo9fGVAPfuPz+SQjIyO4zHsEEEAAAQQQQAABBBBAAIEwAgQVwgDRjAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggEASCxBUSOKby6UhgAACXgoUNKigAgHm5sXqCLrxdDXznLpXsz9BBZ0ONQQQQAABBBBAAAEEEEDAGwGCCt44MgoCCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACiShAUCER7xpzRgABBE6BQLwFFYJDD2b4ILiuozL7ElTQ6VBDAAEEEEAAAQQQQAABBLwRIKjgjSOjIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIFEfjhhx+kQ4cOtkP/+Mc/ivqHDYFYCxBUiLUw4yOAAAJJInAqggoqUOAmeOCW2AwomGMuGrNUlo9fGfJwn88nGRkZIfvQiAACCCCAAAIIIIAAAgggYBcgqGA3oYIAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIFJbAggULpG3btrbTPfnkk/LEE0/Y6hQQ8FqAoILXooyHAAIIJKlAYQcVzFCB4jSDBdHQ6sYjqBCNKMcigAACCCCAAAIIIIAAAqEFCCqE9qEVAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEIilAEGFWOoythsBggpulOiDAAIIICDRBhUiDRuYwYJIjwt1q4LHJKgQSos2BBBAAAEEEEAAAQQQQCA6AYIK0flxNAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCAQjQBBhWj0ONYLAYIKXigyBgIIIFAEBCIJKuTk5EYCihVzXA3B7FPM6GPd/HUXx4nluMARRJzGNs9jBhYWj1kqy8evNMvaV5/PJxkZGdo2iggggAACCCCAAAIIIIAAAs4CBBWcbWhBAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBGItQFAh1sKMH06AoEI4IdoRQAABBPwCBQoqGEcGBxHUYGaQQO1b253qqp+55fcx4gm5CQVrUCG/PXBs83j1SlDBqsE+AggggAACCCCAAAIIIBAbgWQIKuzYuVWysrIcgapVrSmpqamO7YnQkJOTLZu3/Cqbfl0vBw7uk0O+Q+LzHTRe1T+H5ODB/VK8eAkpXaqMlCpVOuC1cqWq0qjBGVKuXIVEuFTmiAACCCCAAAIIIIAAAggggAACCCCAAAIIIIBAkRIgqFCkbndcXixBhbi8LUwKAQQQiD+BggQVrCEE6xWZYQJdu2rT1W3H566oYA0pmH1CjZ/Xx9hhRQVTg1cEEEAAAQQQQAABBBBAwHuBRA8qrNvws4z+8I2QMPcNeUzKJ+BD+nv2/i7rN66WdRtWy4ZNa+XIkcMhrzNcY5XK1eQ0I7DQqOEZ0qBeI3+wIdwxtCOAAAIIIIAAAggggAACCCCAAAIIIIAAAggggEBsBQgqxNaX0cMLEFQIb0QPBBBAAAFDwF1Q4Sxp3r2pY9DATYDAS2zzfGpMXfhh0Zilsnz8ypCn9Pl8kpGREbIPjQgggAACCCCAAAIIIIAAAnaBRA8qrF2/SsZ8NMJ+YZZKogUVNhqhhBlzJssvv26wXIW3u2lpaXJ2q/Ol/fmdpUyZct4OzmgIIIAAAggggAACCCCAAAIIIIAAAggggAACCCDgWoCggmsqOsZIgKBCjGAZFgEEEEg2AYIKyXZHuR4EEEAAAQQQQAABBBBAILYCBBVi6xvJ6Jt+XS8zZ0+Wjb+si+SwqPqeDCy0MwILFxNYiEqSgxFAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQKJgAQYWCuXGUdwIEFbyzZCQEEEAgqQXcBhUyezQL6aBWOShm/E/9P9abuaKCbjUFdW5WVIj1HWB8BBBAIL4EsrJOSHZ2tqSnF4/JxLKzsyQrK0tSU1MlJSU1Judg0OgECuMeqa+BAwf3+SdavlwFY1WnlOgmzdEIIIBAAgsQVDj1N+/33Ttl0uSxssFYSeFUbSqwcG6bC6Vzh66i9tkQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEECgcAQIKhSOM2dxFiCo4GxDCwIIIICARcBdUKGlZPZoajlKv2sGCIJbrYECax+nunm8tV3VzGOD62Z/85WgginBKwIIFL5Ajnw1baIcOnSw8E8ddMYul3STsmXKyedfjTVacoJaT76tVaOutGnVVtsWbfHo0SPy9awvjQBBlnaoC9p2kkoVq2jbIinu3LVNPhz3rj9EMKjfME/CCjk52bJq9TL5cckC2WGMf+DAPmP8NH9YoXz5CqLc2p7TXurVaRjJVD3te+TIYZky/TM5fvyY63HVn5/ly1eUypWq+v+pUqmaZGSUcn18uI7zvpspu/fsCuiWkpIiHdt3kdKlygTUo30T+3uUI7/8tlF+Wv6jbN76i+zfv08O+Q4Z0z75a0mFVipWqOz/GlaeZ5zeXBrUa1TAy8rJ/XUaeHjp0mWlU/vLYhKImDlnihw8uD/ghI0aNpFmTc4MqHn95sSJE8bvkRNsw5ZR13rR5bY6BQQQiF8Bggqn9t78vGa5jP/8fVHfb8XDVrNGHbmpZ3//9xnxMB/mgAACCCCAAAIIIIAAAggggAACCCCAAAIIIIBAsgsQVEj2Oxz/10dQIf7vETNEAAEE4kIgUYIKZkhBoRFUiIsvHSaBAAIaAfXw9J//+bCmpXBLDRs0lr43Dfb/fvnl1AmyYOEchwkUkxt79vP84WT1e/b7n7wla9at1J63ePESMqjfUKlapYa23W1x5c9LZcKkD+XYsaP+QzKbtZLru/dxe7i23/qNa+TTLz6Uffv3atutRRVUuM44X7my5a3lQtlXQYoPx70T9bnKGGGWjhdeJmcbgZVoVwh4Z8zLsunX9bY5Xdmlp//Tlm0NBSzE+h4tMgIq38ybJnv37Y5ohk3PaCFdOl/jDzBEdKARfnjq6eHaQ4YMeijqXye6gf/3xr9l1+/bA5rUaiF9b7pdGtQ/PaDu5Rv1QO3Tzz5mG7JK5Wpy9+2n/vdO28QoIICAowBBBUeaGDfkyMzZU2TW3GnGefRB1BhPwHF4FX68rlsfadTwDMc+NCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggIA3AgQVvHFklIILEFQouB1HIoAAAkVKINKggjUwoIPyhwiCn5copulp9MmxPFihCx9Yz1VMjEF04xhDB/QzPi2aFRU03pQQQKBQBOIhqFDK+OT6u259QNQD6GrLzs6WMR+NkPUbV2sN0tOLy219h0r1ajW17QUpTps5SebOn6E9VP1+f/N1A/2fQK/t4KKoft+f/s2XMufb6bbe6kHxdud1tNXdFL5dMEumzphk/LmS7aa7v4/6JPibrx8otWvWc32MFx29CiqYc6lerZZ0vayH1K97mlmK+LUwggqFcY8+njBSVqxaGvH1qwPUyhsXGF9/nTt2jeD4+AgqqAmXLJkht/a5xwhHVI9g/u67ElRwb0VPBOJdgKBC4d8h9Xvo2E/HOAZBC39G9jOq7/Mu7nCFXNSus9Ho8B/w9sOoIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAQIQCBBUiBKO75wIEFTwnZUAEEEAgOQUiCSpYAwE6jYCwgTWs4PB8gnW8gGNzBw/XrrpZ+5hzWjxmqSyfsMp8q331+XySkZGhbaOIAAIIFFTg1AcVikmvG26Vxo2aBVzCkSOHZcTIF+T33TsD6uab8uUryuD+94oKOUS7/bRikYwzHqJz2i7tdJVceP7FTs1h6+pa1EN6a9frf59XqwL0u3lwxJ8Kr4IVKmBRkE2FPQYPuFeqVI7Nw926OXkdVDDPcXar8+XqK64z3jr84W121LzGOqhQWPcomqCCyRLZKhLxE1RQ81e/H9zeb5iUNkI4Xm8EFbwWZTwETp0AQYXCtT9+/LioP2e3bPu1QCdW/71do3pt/2oHVY3vV0qVKi2lje/71CoIajty5Igc8h2QQ4cOyo5d24zvs36W7Tu2FOhc6qDzz+0gl1/SrcDHcyACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAgiEFiCoENqH1tgLEFSIvTFnQAABBJJCwHVQoXvTgBUQdBcfEDawBhVU56DnHYMDBgHH5g5u7aNrV92sfXIPE4IKpgSvCCBQ2AKnOqgQ6qEwFVJQYQX1oL9uU5+k3++WOyQlJVXX7KqmHp57e/TLcuLEcW3/szLPlp7X3KJtc1NUDzmPfP+1sA/pNWrYRPrcdLubIf19NmxaK6M+eD2ilRSCB1efQH+7EfZQoYXC2GIVVFBzv6BtJ7ns4qsjvoxYBhUK8x55EVRIS0uXOwbeb4RXqrlwjK+ggppwrRp1ZUDvIcbXc7qL+bvvQlDBvRU9EYh3AYIKhXeH1H/zfjT+XVF/9ke6nXF6czmrxdlyWv3GeaEEt2McOLhf1hmBhYWL58tvWza5PSyvX2ShvbzD2EEAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEXAgQVXCDRJaYCBBViysvgCCCAQPIIuAsqnCXNjaBCseC0QZjwgVKyHWPUcoz/BW/BQYTgAEK4dnM81W+RWlFh/EqzpH1lRQUtC0UEEIhSQAUVnnnxz1GOoj88KzvLMWSgjqhZo47c1neopKY6Bw3WbVgtYz4a4fhA/slP079eP4Ew1YOHDsgb7zwn+w/s0/asXaueDOg1RNLS0rTt4Yoq/DD6wzdk06/rQ3ZVD+T1uOpm1w/jHT7sk5fe+Jf4fAcdx1VzVp8uv3//Pkc7dXCblm3lmq43OI7jZUOooIL6hOTg7eixo44BkuC+6n2/W+6UhvVP1zU51mIVVCjse6QLKpQpU04qV6oqpTJKy779e/yrk6iH7kNt6tfkoH5DXYR/4i+ooK6rSeNMuenaARL8PVioaw7XFuugwvqNa2xTqF61RkxWh7CdiAICRUyAoELh3fCpMz6Xed/NjOiE6vuhTu27+L8/jOhAh86r166QGbO/km3b3a+yoFa5uuX6gbaVvhxOQRkBBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQiECCoEAEWXWMiQFAhJqwMigACCCSfQIGDCkEhBSUTHC4wtaxhBV1IQfWzPgSnGydcu3UMggqmPK8IIJBMAtNnfSmzv/1ae0nFi5fwf3p7pYpVtO3W4nc/zJGvpk2wlgL2C/Lpt1lZWfLOey/Lb5v1n7Zbtmx5GWysNqAe9i7Ilm2ENN7/5G1Zu36V4+EqoHFpp6tErSoRyTZt5iSZO3+G9hA1b7WyQItmrfx/Th0zHvZX92Du/JnawIL6s2rIoIeMT9Gvrh3Py6JTUEHN+YG7/6Q9le/wISNssVc2b/3V/8Dj7j27tP1UsWaN2jJ4wH3GnuYPfIejYhVUKOx79PGEUbJi1RL/aggqvKM+iVoFFKyb+l5lyU8/yNfffCkHjU+cdtr6G4GPBmEDH/EZVFDXdN7Z7aXrZT2cLi/ieqyDCk89/ZBtTtd17+P/NWxroIAAAlEJEFSIis/1wT8u/k4+++pj1/3V94LXdusltWvWc32M+4458tPyRfL55LGividys6nvUQcaK/TUqF7bTXf6IIAAAggggAACCCCAAAIIIIAAAggggAACCCCAgEsBggouoegWMwGCCjGjZWAEEEAguQTiLqhgLLagCzOECypY2wkqJNfXKFeDAAIiG4xPCR/14euOgbCeV9/if5jarZV64E09+KbbUlJSpM9NgyP6NP2JX3woi5d+rxvOWEEhXW7tc3eBP9FXPRD+ycTR/gfHtScwihUqVJIbe/SL+BxqFYgXXv27HD9+3DZ0OeOB/4HGvCuUr2Rr+3GJ8dDgl/qHBjONUMP1xoPRsd4KElSwzkmt/rFw8XyZNHmctRywP3jA/f7AQkAxxJtYBBVOxT1SAY4Dxsog9es1CnG1J5vUg5oqpLN122Zt3ysu7S5tz7lI25ZfjN+ggprj5Zd0NwJA4a4h/2pC7RFUCKVDGwKJJUBQIfb3a9fv2+WVN5+R7OxsVydr3KiZXHtNLylZMsNV/4J2UvNSAdJQgUfr2Op7qnsGPyLp6cWtZfYRQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAgCgGCClHgcagnAgQVPGFkEAQQQCD5BdwFFVpKZvemeQEC6woJppAKF/jr6oOXjbCBbcutB4cQzICBdRWFgPFzP8jZsV2dKOjDngkq2PQpIIBAAgv4fAfllbf+6/ip7S1bnCM9rr45oitUKxSMfP812fTreu1xGRml5HZjBYSKFSpr263F736YbazQMNFaCthXD+2rh/cLun27YJZMmf6Z4+GVK1WV/r3ukrIFWK1h6ozP/SsL6Aa/tc89UrdOA12Tvzbus/eMTxX+UdNezHgY72FR84rlFm1QwZybWl1DrbKh2y7ucIV0uOBSXZO2FougQiLcI/Wg5uvvPCfqIfzgrXXL86Rb1xuDy0Hv4zuooL5Xu7Fnf2l6RougeUf+lqBC5GYcgUC8ChBUiP2def+Tt2T12hWuTtThwsukU/suASsVujqwgJ3U7+djPx0ja9atdDWCmltH4x82BBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQ8EaAoII3joxScAGCCgW340gEEECgSAm4Dir0MIIKxqdam5s1TGCGD8zQgb9PfteAIEHAGMaDb+YWULcmD8IFFfKHMIcSggp5FOwggEDCC+TImI/elLXrV2mvpFLFKnLHwPulePES2vZQRd/hQ/LGu8/L3r27td2qVqkhg/oNDTn2emOlh9EfvmH8+aD/pF/1kLt62L2g285d240HwJ+VEydOaIeoUrma9L/lTilTgJCCStU9+/LfZP/+vbaxz2zeWq7t1ttWtxb2Gce9+NrTkpVln1thPIznVVAhKytL/v3CE9qH7NWD6TddO8B62SH3vQ8qJM49+mLKOPn+x3k2n1o16/pDP7aGgEJ8BxXUVNXKKAN63yW1a9YLmHmkbwgqRCpGfwTiV4CgQmzvzcZf1sm7773i6iQqAKC+9yjsTX3/997Hbzl+n2qdj/pedegdf5Aypctay+wjgAACCCCAAAIIIIAAAggggAACCCCAAAIIIIBAAQUIKhQQjsM8EyCo4BklAyGAAALJLeA6qGBZUUGJaIMKKmBgBgesQYWTBwQEHfwlL4IKuWOrF3MjqGBK8IoAAokuEGo1gdTUVLmt71CpWaNOgS9zx85t8uaoF+XYsaPaMZo0zvQ/qB4QRMvtuWfv7/LGO8/L4SM+7bEnH3Lvb7SZfzBouzkW1aoPI0a+IFu3bdb2qVqluj+kULqAD7xt3vKLf3zd4P2M8EPD+qfrmgJqYz4aoX04r1rVmnLXbQ8G9PX6jVdBBTWvt0a9JL9u3mibolpRQq0s4XbzOqiQSPdo0ZIF8umXH9moSpbMkEfu+4utHliIn6BCenq6HD9+PHB6ue9KlypjhJeGSYUKlbTtbooEFdwo0QeBxBAgqBDL+5RjfI/1gmzZ9mvYk6hVq67vrsKVBft+K+wJwnRQv6+/NfolUd9ThtvObnW+XH3F9eG60Y4AAggggAACCCCAAAIIIIAAAggggAACCCCAAAIuBAgquECiS0wFCCrElJfBEUAAgeQRcBdUOEuaG0EFXThBSZgPsFpXRXAjZB6n+oY7Nq+vEYAwV3BwOsfiMUtl+QT9p4+bx/h8PsnIyDDf8ooAAgjEnYB6OE09QK4+8V63XX5JNzn/3A66pohqq9eukA/Gvu34+3D7dp3lko5XBoypgg0qRKBWPNBt1avV9Ico0tOL65pd1WbMnizfzJ2q7ase/r7r1gelXLkK2nY3xakzPpd53820dVVjDx/2lKSkpNjaggsLFs6RL6dOCC7736tPDVYrXsRq8zKoMP7z92XpsoW2qaoVK+6+/WFb3angdVAhke7RshWLZOynY2w06mv0/iGP2eqBhfgJKtxy/a3G7wfvOK6Sor4mVEBK/TopyEZQoSBqHINAfAoQVIjdfVm2crGMnTg67Alq16onA3oNMVa9SQvbN5Yd1CpTapWuQ4cOhDxNsWIp/iCnCpuyIYAAAggggAACCCCAAAIIIIAAAggggAACCCCAQHQCBBWi8+Po6AUIKkRvyAgIIIBAkRBIuKCCcVfChRoIKhSJL10uEoGkFlBBgNfeflZ279mlvc7GjZpJrxtuNdq8+fTcufNnyLSZk7TnUsXruveRFsYn9qpN/R784bh35Oc1y/3vg/9VyvjU9cH975Xy5SsGN7l+v9944O35V/8halUF3XZdt97SonlrXZPrmvr0319/22jrr65TXa+bTd2fF197Wtu1+5U3SauzztW2eVH0Mqgw6oPXZf3G1bZp1apZV2437qXbzeugQiLdo+mzvpTZ335to6pTu77/wX5bQ0AhfoIKT/zhP/L9j3PliynjA2ZofVO/7mnS9+Y7RK3qEulGUCFSMfojEL8CBBVid2+c/ly2njElJVXuGfywVKxQ2Vo+Zfsq+Pr+J2+FPf85rdvJVZdfF7YfHRBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQCC0AEGF0D60xl6AoELsjTkDAgggkBQCBQkqBK9oYK52EC5AEAzmX6FBPWPrYpUE8xxu+hJUCJbmPQIIJJrAuM/ek5+W/6iddpky5YzVBB4QFQjwcnP6VH11jrS0dLm1z91Ss0Ydmf7NVzJ73jTtqdWDy/1uuVPq1WmobXdb/GraRPnuh9na7mcaAYVrjaBCtNvTzz4m6qHp4C3SEIQKKugCJe3O6yhdOl8TPLxn770MKjzz0p/l4MH9trllGqGN612GNtTBXgcVEuUeqUDN6+88L9t3bLEZqkCN+poKvcVXUEHNdcr0z+TbBbMcp31mZhu59ppeju1ODQQVnGSoI5B4AgQVYnPP1O+T/3r+CcewpnnWc1pfYDzwf635Ni5e333vFdn4y7qQcylXtrzcf/efQvahEQEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBMILEFQIb0SP2AoQVIitL6MjgAACSSPgLqjQUjK7NzUyAkaiQLP5AwdGPbjdrGsO8Zes/c2+1prqZAYUrCEIp77meQgqmBK8IoBAIgos/ul7mTjpQ+3U1e+JfW8aLA0bNNa2R1PMyjphPGj+ivy2ZZN2GPVg2QVtO4kKETht3breKK1bnufU7KruO3xInnv5r3L8+HFbfzWHIYOGS4kSJW1tkRTUig3PGufQbQ8Ne1JKRxACmTR5rPyw6FvbUKc1OMP41PnBtrpXBa+CCkuXLRQVUtFt7c/vLJd0ulLXpK15GVRIpHv05dTxsmDhXK3JjT37S7MmZ2rb8ovxF1RQ33d9PGGUrPx5af40g/YuuuBS6dzhiqBq6LcEFUL70IpAIgkQVIjN3Vq2YpGM/XRMyMHT09Nl2J3/J2VKlw3Zr7Abt2z7Vd545wXjtPqfG5jzuWPgA1Kjei3zLa8IIIAAAggggAACCCCAAAIIIIAAAggggAACCCBQAAGCCgVA4xBPBQgqeMrJYAgggEDyCrgOKvQwggrGQ2u6TRccMGu6/mbNGkow+1trRkzBCCqc7G09t9lXtQT2P9mXoMJJB/6NAAKJJ/D77p3y2tvPGg/pH9NOvn0748Hxju4fHNcOEqJ48NABeePd50U9JB7p1vaci+SKS7tHepit/4zZk+WbuVNtdVW44tIe0vac9tq2SIpr16+SMR+NsB1SrFiKPP7IP4167h8+th72wjfG6hIzjFUmgreyxsoXD9zzeHDZs/deBBX27P3d//WmW1lCTfTm6wZKk8aZrufsZVAhEe6RWklj9ryvRYWLdJt6gFR9anRKSoqu2VKLv6CCmtyJE8fl3fdedQwvqT7drjTCSWe5DycRVFBqbAgkhwBBhdjcx08mjpblKxeHHFwFRy+7+OqQfU5V48cTRsqKVc4hNzWvi42QWwcj7MaGAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACBRcgqFBwO470RoCggjeOjIIAAggkvYDroEKYFRV0gQFroEAHaT3G7GutmUGFk/mI/JCE2VeNGdj/5FkIKui0qSGAQLwLqBUNRox8QbZt36Kdap3a9WVg77tdPPSsPdx1cdv2zfLW6Je0Kxo4DdKo4RnS+8ZBRrgs3APZTiOcrCuD/7z4lBw5ctjWsWTJDLl/yGNSvHgJf1tWVpaoYEV6WpqUKlXaqLkPFzitIqBWUlArKkSy/bBonkyaPM52SGpqqjw2XIUeYrNFE1RQq1XM/+EbmTt/hjiFFCpVrCL3DH4kb2UjN1fhZVAhHu/RJu2dswAAQABJREFUyp9/kv0H9so+I8iz6/cdosIU1iCl1UitfqKCHmec3txadtiPz6CCmqzPd9D4felFUaEW3aZCGOrXvlpBxM1WkKDC4cM+x6/T4HM+/+rfg0vS9bIeckYjN/dBJCOjVNQrttgmQAGBJBUgqOD9jc3OzpJ/Pf9E2N/zBvUbJrVr1fN+Ah6MqEIKKqwQaqtds54M6j8sVBfaEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAIIwAQYUwQDTHXICgQsyJOQECCCCQHAIFDSqECwu40VEP8fk3I4OgCxwEPnRKUMGNKX0QQCBxBb6cOkEWLJyjvQD1kP4dA++XCuUradu9Lp58yGyUMWz+771O56hcqaqoB+bUHKPd1m9cI6M+eE07zNmt2kmN6jX9n9L7u/FJ9gcO7Mt7SFw9LK3moR4Kb9nibKlapYZ2DLP4/Y/z5Isp9nBB1SrVZcig4WY3V6/qU4/Vpx/rtseGPy2pqWm6pqhrTkGFEiVKivqk5eBt67bf/CEP9cD5zl3btWEQ6zFXdrlWzm1zgbUUdt/LoEK83aOcnGz58z8fDmtgdlCfdK27D2Z74Gv8BhXUPNVKL28aYYXDR3yB0859p77mbu1zt1SrWlPbbi1GGlRQ53z+lb+HfWjXeo5o9i/pdKW0P79zNENwLAJFRoCggve3Wv1++9LroUOOpTJK+0OVef8t7f00ohrx2LGjRtjicVGBUuetmPzfg3+T9PTizl1oQQABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAgZACBBVC8tBYCAIEFQoBmVMggAACySAQF0EFA1L/icTWT8fOf1g2XEiCFRWS4SuTa0CgaAn8vGa5fDD2bceLvqFHX2netKVjeywaZs2dKjNnTw45tAonqJCCCgl4sU2Z/pl8u2BWVEOpB/danXmuqAfF1aej67Y586fL1zO/sDXVr3uaDOg9xFYPVQgVrhh+71OiHiiMxeYUVPDiXOqTjpVDmrFaRSSbl0GFeLtH6vuUP/8zfIhFPbTf46qbpekZLSKgi++ggrqQX37dICONEJFa9US3lStXwf97Qdky5XTNebVIgwr79u2R5175W97xsd4hqBBrYcZPJgGCCt7fzQ1GYFP9XhtqOzOzjVx7Ta9QXU55mwqdqu+PQm1D7/iDqNWb2BBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQKBgAgQVCubGUd4JEFTwzpKREEAAgaQWcBtUaN69ic3BDAzoV0OwddcWQo9BUEGLRhEBBJJKYL+xMsCrbz0jhw/rP628Tau2cs0VN5yCa86Rfz73eMhP3lefPK4e7PVqe+XN/8iOnds8GU49/Nbrhtu0IYrps76U2d9+bTuPerj8pmsH2OqhCtu2b5bX3n5W22XYnY9KxQqVtW3RFmMVVKhWtYY/pJBRUh/yCDVvL4MK8XaP3AYVVLjjqi7XSauzzjGorN/HhJKL/6CCmv2yFYtk7KfvGXv54VHrVdWoXlsGGgGX4sVLWMsB+wQVAjh4g0BCCxBU8P72Lfl/9s4D4Iriav+H3ptUO9hFQZqggoqCqBh7YjRGYxJ9k6hJNMmX/L8vmgSMGpNoYhe7ohQRBQEVu2JBpbwgICLYsKGAonQQ/nNm5uzO7t295b172/s+G7k7e+bMmTO/vWGHvfvsvDWLJk0blzbwySf8UAsy0zqVuDJObOim9bMfX0y77tLVNaEMAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiCQAwEIFXKABdeCEIBQoSBYERQEQAAEah+B7IQKPan7yfvFDj5ObODb3abRD7eJb9DT9fU9XGGEb+XH5ow/VlRwKaIMAiBQzgS2b99G9425jT5c/l5kmh07dKGq836r3mzfKLK+kMZsHjLjFQsu+MlvE3kYnwUb/7n5ikSH1KJFK7rogv+h8EP3z7wwjV6Z+XxKXweoVSu+r1avyGVbuWoF3XzHvyKbFPJtwYUQKnTdfS86Xb2luWWGt+JHDlYZkxQqlNs5ylaoIGwO3L8XnfK9M6lBg2xWpagMoQKP7eXX1GokL6auRiLj3nvP/ems7/+U6tWrL6bAHkKFAA4cgEBFE4BQIfnTN+PVZ+i5l55MG/jcM39B3brundan1JXzF86mR6eMTZvGGaf+hPbft0daH1SCAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAjEE4BQIZ4NaopDAEKF4nBGLyAAAiBQ8QQqR6jA7yU2byYWQQLDFxuXxQ6hAtPABgIgUAkEXnz5KXpB/Yna+M3sLALo1HHHqOqC2t55dyGNm3iv6sMVjEV3yWKK88/9ddq3qEe3DFrffmc+PfTo/UFjAkc9D+xLp37vrECkF195ml6YMT1g44M9uu5D55xZlWJPZ/j4kw/prtE3Rrr8/td/pZZKLFGILUmhAq8+ccxR3yNeUSKfLUmhQrmdo1yFCsxx0KFqxZEjs1lxpHKECjyuKU9MoDnzXudi5Nav96F0wrGnR9ZBqBCJBUYQqEgCECokf9qmTZ9Is+a+ljbwr37++5LMDdMmFap874N3afS4USFr8HD4sNPo4D6HBY04AgEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQyJoAhApZo4JjgQhAqFAgsAgLAiAAArWNQBJCBZYLmC3zA60iLRBRQZI8WbTAcSFUSJIqYoEACBSKAK+iwKsp8KoKUdsJx55G/XoX/wGuFV98Rnc/cBNt3rwpKq1I2z57daczT+e3qMv1INItrfGN2a/QE08/mtaHKxs1akQd2nemFs1b0tdrVtPqr1bRtm3fpW139hnn0157+CsDzXzzJZr+7GMpbXbssrNaweLSFHs6w5Kli2jsw3dHuvzf76/W+UZW5mnMVajAb7hv0qQJNW3ajJo2aUqdOuxIXXfbk3bfbQ9ioUISW5JChfI7R9uVqOhpWrX6S1q56gv9Z+vWLWmxNWrUmH77y/8lXtkj/VZZQoVt27bRmAl30rL3l8QOi4Uvhw0YnFKfq1CB/7+9+quVKXHiDFGrmww7+kTae0////9xbdneonkr4pVisIEACGQmAKFCZka5eoybeA+xWDTd9gclgsx8XUkXofB1X3z5Gd1617VpOzpy4DE0+PBj0/qgEgRAAARAAARAAARAAARAAARAAARAAARAAARAAARAAARAIJ4AhArxbFBTHAIQKhSHM3oBARAAgYonkItQIbB6wXYrStDPpMqDqcomWgUxhQhFxmCfGP9M8dzwEnvug/No4aTFblVKef369epBtGYpdhhAAARAoBgENmxYT7fdfS198+2ayO7237cHnXHqTyLrCmlct34t3XHf9bRmzVc5dzPoEPX2+MHZvD0+OvTzLz1JL736THSlsrLQ4IjDhtKuu+yujvyLxtatW+nVN16gGa8+S3EPjrdp3ZYuuuBPnmiA3wbPb4UPb23atKNLfvXnsDntcfVbb9LkaeNTfFgY8Jc//TPFnpQhTqjQuHET/XC820/Dho3UiheNlcnn5tYnVU5SqFDu5+i777YSi42eem4KsbgnbuvfdxAdf8wpcdXWXllCBU6aBQf3PHhzmrHXox+c8mPqvt9BgbHnKlQINM7iYMQ//pDidfrJP6YD9++VYocBBEAgPwIQKuTHL6r1mAl30bvL3o6q8myX//Eaql+/gXdcjgUWmN046h9pUzvk4CPo2CEnpfVBJQiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAQDwBCBXi2aCmOAQgVCgOZ/QCAiAAAhVPoCZCBb0aQkCQIA8+KmPAnopHxATaLSB2SPXVlgzx3FYSe+6D85VQIf0DHhAquORQBgEQKDaBdG/M5Yfqf/mz3+s33xczL37wmld4WP7JB5HdNlFv4T9APXTMD5DHbaeddDb16N47rjqtnYUDUbFbtmxNJx73feJVG9JtX329Sq0EcTOtXftNpNt5Z19Iu++6h65b+HY1PTz5gRQ/fsj/f393ZYo9neHV11+gp5+fmuLCKxf86ZIrPPt2dc37z81XEItBct2OPuJ4GnjIUYFmcUKFVq3a0O8uujzgW6yDJIUKpThHNeHE4pjH1Hf3rYVzIpvzCiD/9/urVJ3MlaLcKk+owKNgodWd999A38YIrho2bEjnnvVL2nXnrt6gIVTwUKAAAhVPAEKF5E/hRDU3WaDmKOm2//ntCGrerEU6l5LXffLpR/r6kC6Ro9RqCkeoVRWwgQAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAI1IzA6tWr6emnn05pfOCBB9IBBxyQYocBBJImAKFC0kQRDwRAAARqKYHshAoH0QEn76c0CKIayA4GCwdS27gP6uUWz+01EJvDOGGrtVABKyq4vFAGARAoHwJvzH6Znnh6UmRC/Bb+887+Fe22S7fI+kIaJ00bR/PemhXZBed19hk/pz277Uvp/PjB5J+efRHttOOukXHSGcc+fDctWbooxaVf78PohGNPS7FHGZa+t5gefOjOqCr1VvtTqX/fgbru08+W65Ujohwv+59rqEGD7N9U/MwL0+iVmc+nhNp5p93o/HN/49m3b99GI6/5o3ecS4FXquAVK9yttgsVSnGOXL65lLdt+45uvuNfxG+QjtouufAyYgFS/FaZQgUez+crPtUrK2zevClyePww7c/P/TXt0K6DrodQIRITjCBQkQQgVEj+tD35zGR6fdaMtIEvPP8P1LFDl7Q+pa58592FxKLcdNuJx/2A+vQakM4FdSAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAmVMAEKFMj45SA0EQAAEyolAoYQKsroBjzUoVnAUBTHCB2kbbOdTk3odW1Zl4AMbGkIFnxVKIAAC5UWAH+rlN5Dz6gVRW6neLssP2vMD93HbcUNPpgH9DtfVnPu9D95KH3/6YaR7K7UCwgXnXUK8z2V7YPzttOz9JSlN+G27zCXbLW61Cn4Yjh+K440fqr76ustUKVUwV6Vy37HLLtovm48xE+6id5elruLT+6D+dNLxZ3ghIFQwIhEPSIZCKc5RhpTSVr/9znx66NH7I33OOfMXtEfXvSPrjLFyhQqcPwuExky4m/g7HrWxSIFFO82aNScIFaIIwQYClUkAQoXkz9vLrz1Hz774eNrAvFJNt933SutT6so51a/TlCcnpE3jzNN/Svvujbc5pYWEShAAARAAARAAARAAARAAARAAARAAARAAARAAARAAARAAARAoYwIQKpTxyUFqIAACIFBOBLIVKnQ/ed+c0g6ICVIeBGVFQerDodKBtI0TKrBfwEdCQaggCLEHARAoQwJbtmymUff8h1at/jIyu6677Un88Fm9evYvs0iv5I28igE/3L/dFX453bgP+It57dpv6Pb7rqdvv10jpsB+5x13UytDXEi8wkK228OTRtPCxfNS3HMVb8x47Vl67sUnUuKEVzi4/tar6Os1q1P8Bg8aRkeqP9lsW7ZsoX9efzlt3ZoqPDl2yMl0yMFG3MGxIFTITajAzIp9jrjPmm4bN26ga/57eWTz4cNOo4P7HBZZZ4yVLVTgMcyufo2mPjkxdoy77tKVzj3zl1qk9Y//sEgouHVo34kuuqBmK464kUb84w/uoS6ffvKP6cD9e6XYYQABEMiPAIQK+fGLaj13/hv02OMPRVV5tlNOOJMO6tHPOy7HwtPPT6VXX38hbWrn/+Q3xPNFbCAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAAiAAApVJAEKFyjxvyBoEQAAEik4gO6FCT+p+8n4mNxEFSKah52lTBAShet2MY8TZJS7vvYd1badx7aSNdaseM58WTlos1sj9+vXr1Zt9m0XWwQgCIAAChSAwedp4qn7rzcjQ/KbxX/3s99SqVZvI+kIZv/jyc7pr9I16hYGoPnZn8cSZVVS/foOU6k8/X073PHCLekh/S0odG3oc0IdOO/FHkXVRxmnTJ9Ksua+lVPHDePxQXrYbix1Y9BDeeIWH3138F88ct/LCTjvuShf85LeeX7rCO+8u1CKPKB8Wauy+6x5eFYQKuQsVin2OvJNVw8LV1/058v9LLHxhAUz8VvlCBR4br8rCq7PEbQfsdxB977jvRwo6IFSIowY7CJQvAQgVkj83vEITr9SUbst1fpUuVqHqbrnzX/TlyhVpw1/yqz9Tmzbt0vqgEgRAAARAAARAAARAAARAAARAAARAAARAAARAAARAAARAAARAoHwJQKhQvucGmYEACIBAWRHISahghQApA3BEB55QwX0zt1MfWEghzi4deEIFZYiLJ768h1DBpYEyCIBAGRF4a+EcemTKmNiMzvr+z2ifvbrH1heiYv36tXTHfTdErirA/bVr214/sM8iirhtwaK5NPGxB+OqaejgE2jgIUfF1rsVL77yNL0wY7pr0uXwSggpDiHDG7NfoSeefjRkJerYoTNdeP7/eHYWRbA4InWrR3/49V+oRYtWqVUhy2NPPERz570RspISwjWn//nN35Terr5XB6FC7kKFYp8j72TVoLBp00aKWimAQx039GQa0M9fXSM1fO0QKvBE7OFJD0SujCJj7tf70EhBEoQKQgh7EKgcAhAqJH+uVnzxKd1293VpA5s5xoiir8CVNimnkler4hWR0m0NGjSg//3dldSgQfYrb6WLhzoQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAIHiE4BQofjM0SMIgAAIVCSBnIQKPMIosYIjOEhWqMAdSnDVsfQtJq52NwgVXBoogwAIlAmB1V+tpFH3/CfyTeucYv++g+j4Y04parbfffcd3T/2Nvro4/cj+23SpCn9/Jxf64f7Ix0c47MvPk4vv/acY/GL9ZTg7MzTf5qVCOO9D5bQ6HG3+41tiR9i+3XVn7J+6+6UJyfQnOrXU+J0230vOvesX3r2tWu/oWtvukIdy8XFq6ITj/8B9TlogG+IKG3bto3+c/MVtHbdtym1vXv2p5OGn5Fi54fZa7I1bNgw5WG+xUsW0PhH7k0Jx6ty/O6iy1PsxTDc++At9OHy91K6Gj7sVDq4T+5ChVKco5TkszTwuHn8Udv3TzmHeDWB+K22CBVIrbCyle4fdxst//iD+OFG1ECoEAEFJhAocwIQKiR/grYrcf6/bxxBLCZNt/3snItp1527pnMpWd2bc16hx59KFYy6Ce3RdR86R63YhQ0EQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQAAEQKByCUCoULnnDpmDAAiAQFEJ5CpUYCHC9vBDnanPePr6Ajsar53r6wgOMgocXCoSw2vPBWW09uox82nhpMVui5Ty+vXr1Ruvm6XYYQABEACBJAmwIODu0TfRp58vjwzbpfNOdP65v0l5CD3SOUHj5MfHU/X8NyMjsriAV3jYe8/9I+vDRn6obtzEe2jJ0kXhKn3cuHETPUZe0SDdtnnzJvVG+svVAjrbUtz237cHnXHqT1LsYcOaNV/RzXf+i7Zs2RyuUm+0H6TebB8UhNw1+kb6+JMPU3zbtt2BLjr/j8QCgbht5pszaPqzkyOrf/SDn2fNLzJAFsa6IFRgDMU+Rx98tIzatG6rVxTJ4jRYl+1KpHBrpEiDHX75s99T5047pglXe4QKPMgNG9bTnfffQCzSynaDUCFbUvADgfIhAKFCYc7FpKnjaN6CWWmDl0LkmjYhr3I73X7v9fTZ5x97lqjC8cecqoS6uQsYo2LBBgIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgAAIgUBoCECqUhjt6BQEQAIGKI5CLUEHEBDzIgFhBhAPu6D0RAWsW/AN+oNXbfHO0j1PvteGCE4LUA7XeZmNDqOARQQEEQKDEBJ56bgq99saLkVk0atSYfvHTS6n9Dh0j6wtl5Hw4r7ht2NEn0qH9j4yrjrSzyIAfTP5y5YrI+nZt29MF5/2WmjVtHlkvxgcfupOWvhctNMvmrfQPPnRXbPtzzvwF7dF1b+lK7+cvnE2PThkbsMkBM2AWUduq1V/SHfddT1ErJHRo35kuPP8P6vLkXJ+iguRpqytChWKfo0cee5AWvD2PDtj/IDr80KOpU8d0AgNzEl+Z+Tw988K0yDPaWq1wcWnGFS5ql1CBQbBI4a77b6T1G9ZFcgkbkxIqjLzmjylipx+oFS26p13RIpwNjkEABLIhAKFCNpRy91m0eB5NmDQ6bcMGDRrQxWq1qbZtdkjrV+zKhW9X08OTH8jY7SW/+nPWK2VlDAYHEAABEAABEAABEAABEAABEAABEAABEAABEAABEAABEAABEACBkhCAUKEk2NEpCIAACFQegVyECjw6b2UEGaorGhCbcXSPTDtXpBDn46yM4OgbArEihQpObAgVgrhwBAIgUBoC7y57m8ZMuFt1Hv0X5cnDf0i9eh5c1OQ4p7EP360e5I3OqXfP/nTS8DNqlNNXX6+iO9RbdDdsXB/Zvtvue9GPf1hF9evXj6xn43sfLKHR426Pqa+nBBRH0JAjh6sVKBoEfL75dg1NnjZOtX83YJeD1uoN+b/95f+qvoPtmMMtagWGlau+ENfA/shBw+iIw4YGcl7xxWfqvN5J3GfUlllQEdUqd1tdESoU+xyxUOGtRXPtCalH++y1P/XrfagWLLRp3UbZfQEKr+Ax7alHiP9/FbelE7z4bWqfUIHHtvyTD+j+sbfR1q1b/aHGlJISKvDKLuvWrw30coASKfDKLthAAASSJQChQrI8JRqLIP95/V9p27bvxBS573FAHzrtxB9F1pXCyPnefMe/Mq6mwysM8UpD2EAABEAABEAABEAABEAABEAABEAABEAABEAABEAABEAABEAABCqbAIQKlX3+kD0IgAAIFI1AVkKFs3tS95P3yy4neX4v+hnYYAzxZavrL3bX5rZU9UYwwe1SnSBUcGGhDAIgUAoCa9d+Q7fefR2tDz0w6+YyoN8g9zDRcsuWrWnggKMCb/X/cuXndNfomyJXAeDOd9u1G5175i9TRAC5JPa+Ego88NAd6uG6bZHNDu5zGA0fdlpknRh5pYJPP1suhyl7Xp2Bc+3SaSfdDwsHlixbRBs3bkjxFcMpJ5xJB/XoJ4eBfaa3//ID1Pw29sZqBYzPVnxC/KbjOKFHZ5XTL392qYovF7JAV4ke1BWhAkMr5jkKChWCp4wfdufvA+95xYBvvvk66BA6Yj8WyDRv3jJUEz6MFyrwig47tGsfbpDT8U5ddqHDleDG3fhh0pWrUldA+ev/+7frlnfZvBmc366dOl9zgyclVHBj1ubyRx99pL5XzalDhw61eZgYW5kTgFChcCfo/nGjiOdU6bd6amWuS6hL553TuxWp9vVZM+jJZyZn7O2IgcfQUYcfm9EPDiAAAsUjsHz5cmratCl17Fjclf6KN0L0BAIgAAIgAAIgAAJ1g8CWLVto8eLF1KNHj7oxYIwSBEAABEAABEAABEAABECg5AQgVCj5KUACIAACIFAZBBIVKrjPZaZ/Hs3AifMXe0yMevXEgXUKqU4QKlTGdw9ZgkBtJcB/L40ef3sWD5gVlsBFF/xRP1TNvazfsI7uvO8G4lUPora2bXagC37ymyweqI5qHbS9MfsVeuLpR4NG5+iEY0/Xb6h3TIEir25w+73/If5hJYmNV3I458xfBEQb4bjjH7mX+MH/fLZGjRrR+ef+Rr95P5842batS0IFZlKsc5ROqJDtuRG/44aeQtkJkuKFChIrn/3ee+5PP/rBzwMhiiVU4E5fff0Fevr5qYH+wwcQKoSJRB9/+OGHdPXVV9M999xDr776KvXt2zfaEVYQKAIBCBUKBzn9ClN+vzu060Dnq/lbs6bNfWMJSss//oDuUyvofPdd+hV0mjRpSr9hAV+zFiXIEl2CAAiECbBAgecVd999N7344os0YMCAsAuOQQAEQAAEQAAEQAAEKoDA5s2b6b777qOrrrqKhg0bRqNGjaqArJEiCIAACIAACIAACIAACIBAbSAAoUJtOIsYAwiAAAgUgUBJhQo8PtEcuHqDKFuIBYsVokQK7AahQggWDkEABIpKYMZrz9JzLz5R1D6jOhOhwrZt39H9Y0fRh8vfi3LTb4f/+Tm/Vg/Yd4msr4lxypMTaE7165FN69dvoFZuqKLdd9szsp6N1W+9SZOnPaRK7sUh1j22gh/gu+Anv1VvCG0W68MVmzZtJF7JYdXqL9P6pas89XtnUc8Di/fQcF0TKhTrHCUlVOh9UH866fgz0n1lnLraLVTggU6bPpFmzX3NGXOwCKFCkEf46IMPPtAPEt57773EPz7zNmvWrLIWKvCKHekEZx3adyYWeGW7ZYqXbZxc/Fq1akMtW7TKpUmd8oVQobCn+wElel32/pKMnXRV86lz1LyK51el2L7+ejXdcf8NaVcRk7yGDj6BBh5ylBxiDwIgUCICvDKTCBRkXjFz5kwIFUp0PtAtCIAACIAACIAACNSUAM/l+F4Rz+343hFvVVVVECpoEvgAARAAARAAARAAARAAARAoBgEIFYpBGX2AAAiAQC0gkJNQIZOAQOqZS/jZUqkL24Wh1Ltttc1WRKycIE29vXWtfnA+LZy02DNHFdavX0/NmqV/cDWqHWwgAAIgkI7A8k8+oHsfvIW2bduWzq0odSJUmPKEEg3MixYNsOjrzNN/Svvs1T3RnFgcwW/W/Wj5+5Fx+U26LCBo23aHyHo2zlswix57/KEas9yxy85qbD+j1upB02w2Fik8+NCdsatOxMeoR0OOPJ4GHXp0vEsBauqaUIERFuMcJSFU6NvrUBo+7JQcHhqt/UKF7du30diH76F3l70d+f8GCBUisegfmfltePxWPHmQUDzLWajw2ecfq5Vx/iupRu6rzruU+O/pbLZs4mUTJ1efIYOH06BDivt3e645ltIfQoXC0v98xad6hak4cb7be6+eB9PJw3/omopSZhHhXaNvpC9XrsjYH6/edXHVH6lBg4YZfeEAAiBQGALuykzheQWECoVhjqggAAIgAAIgAAIgUAgCPJfj1TZZoMBzPHeDUMGlgTIIgAAIgAAIgAAIgAAIgEChCUCoUGjCiA8CIAACtYRAjYQKPPYowYEVCmg0bn2c3WUoPm47rlcP0eoNQgXDAZ8gAAJlS2Djxg102z3X0Zo1X5VFjixUWPreOzT92cmx+RTyzbbr16+l29UqBXE8eAUHXsmhceMmsfm9/+FSevypR2jlqi9ifcIV9erVp94HHUzHDz2FGjbM/m3dHIfP4cOTH1BvMH4nHDbymHM/7cQf0b57HxBZX0hjXRQqMM9Cn6P3PlhCL898nt7/YKnqLTwpSX9GmzVrTscM/p76/vVP75hSW/uFCjzkzZs30T1KyPX5ik9SCECoEETy/vvvkwgU4lYlKGehwqefLder1ARHFTzKRaiQTbxg9GSOIFRIzxFChfR8kqh9dOpYmr9gdlahenTvTScNPyPnuU9WwSOcWDw4buI9Wc/Rvn/yj+mA/XtFRIIJBECg0AT47br8EBu/bTcsUJC+IVQQEtiDAAiAAAiAAAiAQPkS2LRJ3VuzAgVeJStqg1AhigpsIAACIAACIAACIAACIAAChSIAoUKhyCIuCIAACNQyAjUSKqR7bi9KcCA2ZpeubRJsVV9YUSEJkIgBAiCQK4FXX3+Bnn5+aq7NCuZ/wU8uobsfuJG+++67yD4OOrAfnfK9MyPrkjKu+OJT9abdm2jLls2RIbMRSvDqDLOrX6e3Fs2hjz/5kOLeLNysaXO9MsTAQ46ijh06R/aXjZHjL31vMb0x+xUt9Ii6cLVs0Yr69TmM+vU+lFo0b5lN2MR94oQK/IZyfgC4FBuvSMHswtvwYafSwX0Ghs01Pi7GOfp6zWqqnv8mzV84R62ysVrlGj+B6dRxRzqwey8a0HdQWuFN/IC301XX/jn2/yfx7bKriXrT9n1jbqUPPlqWEuCv/+/fKbYkDd+u/YbuvP8G+uabrwNhd99tTzrvR78K2OriwXvvvUdXXnkljR49Wn0ftqRFAKFCWjyJVEKokB4jhArp+SRRu0b9XXnb3ddqkV428bp03ol+eNp5xKsXFHLj1XEmPvYg8YoK2Wzduu5N5575i2xc4QMCIJAggWyEj9IdhApCAnsQAAEQAAEQAAEQKD8CLFC466676B//+ActX748bYIQKqTFg0oQAAEQAAEQAAEQAAEQAIGECUCokDBQhAMBEACB2kogK6HCj3tS95P3i39GT4QI7jN8YmNw2dhzBSzx3dg2RvWY+bRwUuqDkm4X69evp2bNmrkmlEEABEAABMqcAK/SsOLLz2ndum9p3fp11KBBfSUUaEVtWrclfkCfV1NIctuwcb16SH0Vff31V/pt8K1bt6F2bdur/tpR/frJ9pVk3nUpVjHO0XffbaWv1Uopa775Sn8XtmzdTCyMadGiJXVWIoWWLVvXJeQYawEILFu2TAsUHnjggYwCBekeQgUhUbg9hArp2UKokJ5PUrUfqNWlRo+/g1i4mc3Gq/uccOzpdMB+PZW7/KM5m5aZfViY8Ipadejlmc/FCkfDUVg8+rMfX0xNm+Lf3mE2OAaBQhFg4SOvzHT//fdnPa+AUKFQZwNxQQAEQAAEQAAEQKDmBFigcOedd2qBwscff5xVIAgVssIEJxAAARAAARAAARAAARAAgYQIQKiQEEiEAQEQAIHaTqAihQru8xYQKtT2ryjGBwIgAAIgAAIgAAK1ksDSpUs9gcLWrVtzGiOECjnhqpEzhArpsUGokJ5PkrW8ws/kx8fnFLJzp53oqMOPpX33PiCndlHOvMLLG7Nfpldef542bFgf5RJpYyHf+ef+RgtKIx1gBAEQSJRALiszhTuGUCFMBMcgAAIgAAIgAAIgUDoCGzdu1AKFa665hrIVKEi2ECoICexBAARAAARAAARAAARAAASKQQBChWJQRh8gAAIgUAsIZCVUONuuqJDLeDOICXIJlasvVlTIlRj8QQAEQAAEQAAEQAAEikXg3Xff1QKFBx98kHIVKEiOECoIicLtIVRIzxZChfR8kq599sXH6eXXnss5LK841aN7H9prj32pY4cuWbf/7rvvaPnH79PS99+h6rdm6dWssm6sHBs3bkI/Pfsi6tJ5p1yawRcEQKAGBGRlptGjR9d4XgGhQg3AowkIgAAIgAAIgAAIJEyABQp33HEHsUDhk08+qVF0CBVqhA2NQAAEQAAEQAAEQAAEQAAEakgAQoUagkMzEAABEKhrBMpGqCDChogVEsLnxHWRZq4PhAouDZRBAARAAARAAARAAATKgcCSJUu0QGHMmDE1fpBQxgGhgpAo3B5ChfRs64JQoetue1LDho3Sg8ijdrddu9Hhhw7JMsJ2mvjYGFqwaG6W/qlurVq1oT277kPtd+hIzZu3oBbNW1KDBg2oXr36tGnTRlq3fq3+89nnH9MHHy2jzZs3pQbJwsLMzjz9p7Rnt32y8IYLCIBATQnkszJTuE8IFcJEcAwCIAACIAACIAACxSOwYcMGT6DAv9nms0GokA89tAUBEAABEAABEAABEAABEMiVAIQKuRKDPwiAAAjUUQIFEyowT1ERuMqCOM65+KoYElKauWEhVHBpoAwCIAACIAACIAACIFBKAu+8844nUOC3lCexQagQpHj0EcdR2zY7BI15HvGb4HN5A32e3VVc87ogVCj0Sdl/3550xqnn5tDNdnrx5afpBfXH/xdxDs2L4LpDuw56TJ07YSWFIuBGF3WUAK/M9Pe//52SED4KQggVhAT2IAACIAACIAACIFA8AixQGDVqFP3zn/+kzz77LJGOIVRIBCOCgAAIgAAIgAAIgAAIgAAIZEkAQoUsQcENBEAABOo6gYIKFUoEF0KFEoFHtyAAAiAAAiAAAiAAAh6BxYsX6wcJx40bR0kJFCQ4hApCwuyrzruUduyyc9CIo4ISgFAhf7y5CxVMn0uWLqJHpozRqyDkn0VyEfbftwedPPyH1KRJ0+SCIhIIgIBHgFdmEoFC0vMKCBU8zCiAAAiAAAiAAAiAQMEJrF+/3hMofP7554n2B6FCojgRDARAAARAAARAAARAAARAIAMBCBUyAEI1CIAACICAIVCOQoV0qyVkc94gVMiGEnxAAARAAARAAARAAAQKQeDtt9/WDxKOHz8+cYGC5AuhgpAwewgVgjyKcQShQv6UaypU4J5Xf7WSxk28l75cmexDLTUZVf369Wno4BPo0P5H1qQ52oAACGQgwCszsUBh7NixBZtXQKiQ4SSgGgRAAARAAARAAAQSIMAChdtuu43+9a9/UdICBUkPQgUhgT0IgAAIgAAIgAAIgAAIgEAxCECoUAzK6AMEQAAEagEBCBVqwUnEEEAABEAABEAABEAABEpOgAUKV1xxBT300EMFe5BQBgmhgpAwewgVgjyKcQShQv6U8xEqcO9btmym1954kV578yXauHFD/gnlHKEe7bfPAXTkwGHUpfNOObdGAxAAgfQECrkyU7hnCBXCRHAMAiAAAiAAAiAAAskRWLdunSdQWLFiRXKBIyJBqBABBSYQAAEQAAEQAAEQAAEQAIGCEYBQoWBoERgEQAAEaheBpIQK27dvp3r16pUEDq/A4PaMFRVKchrQKQiAAAiAAAiAAAjUSQKLFi3yBArbtm3Li0GLFs2pRcvm9MWKlWnjQKgQxAOhQpBHMY4gVMifcr5CBclg06aNWrAwc9YM4nKhN/53f/f9DqIjDhtCnTruWOjuEB8E6hyBJFdmat6iGbVq1ZJWfP5lWo4QKqTFg0oQAAEQAAEQAAEQqBEBFijceuutegWFL774okYxpBH/O+yAA/ehBW+9I6bIPYQKkVhgBAEQAAEQAAEQAAEQAAEQKBABCBUKBBZhQQAEQKC2EUhCqMAiBd5KIVQwPZuzImIFCBUMD3yCAAiAAAiAAAiAAAgUjsDChQu1QGHChAmUt0BBiRMGHdGf+h/SixYteJcmPjQtbeIQKgTxQKgQ5FGMIwgV8qeclFBBMuFVFXh1hQWL5tLqr9KLnaRNLvuWLVvTPnvuT4f2P5I6tO+US1P4ggAIZEEgSeEjCxR4XnHIYX3o7UVLacLYKWkzgFAhLR5UggAIgAAIgAAIgEBOBNauXasFCv/+978pCYHCgT33o8FDDqNOndrTyMuvU6vrbY3NB0KFWDSoAAEQAAEQAAEQAAEQAAEQKAABCBUKABUhQQAEQKA2Eqh0oQKfE6yoUBu/mRgTCIAACIAACIAACJQngQULFtDIkSNp4sSJiQgUDj9yAPU/tA81btSQWABcPWchhArOqf/0s+V0x33XO5bUIoQKqUwKbal0ocKHy9+jex+8pdCY0sY/uM9AGj7s1LQ+Na38es1qWvb+EvXnHXr/w6XEIoZctyZNmlLX3fakbrvvTXt03Zs6duicawj4gwAIZEEgUeGjWplp0JH9aYASKDRu1Ej3Pq96EYQKWZwHuIAACIAACIAACIBAvgRYoHDzzTfTtddeS19+mX5Fq0x98YvhehzEAoWBWqCgX9qm7hlBqJCJHOpBAARAAARAAARAAARAAASKSQBChWLSRl8gAAIgUMEEkhAqxA2fH7SKWmUhzh4VR1ZMkNUSonzCNqyoECaCYxAAARAAARAAARAAgXwJvPXWW1qg8Mgjj+QtUGjZqgVpgcIhvalRY/MgoVIpQKgQcZIgVIiAUgamShcqlAHCoqWwffs2WrV6Ja1bv5bWqz+8X7d+nS5v3rKZmjZpRs2bt6DmzVpQi+Yt9Z6P2+/QQf17vn7R8kRHIFDXCLDw8YorrqCHH344/3kFr8w0eAANUMLHRixQUHMK2eZVL1RChalyGLnHigqRWGAEARAAARAAARAAgawIfPvtt55AYeXK/Fa3q1+fBQr70+CjD6OOnTuY/vl+EZfUHkKFrE4JnEAABEAABEAABEAABEAABIpEAEKFIoFGNyAAAiBQ6QQKJVRgMYJsrlghzi6+7t6PQAShgksGZRAAARAAARAAARAAgWIRmD9/vhYoPProo3k/SNiKBQqDD1ErKCiBQsOGegjenJd/eFZ/sKJC8MxCqBDkUS5HECqUy5lAHiAAApVGgIWPLFBIYmUmI3w8RK2g0JsaK+EjzyP07Tj9wSuQbqf5ekUFCBUq7XuCfEEABEAABEAABMqfAAsUbrrpJrruuusoGYFCdzpq6EDq2HEHPfjA/SK2qDkehArl/71AhiAAAiAAAiAAAiAAAiBQlwhAqFCXzjbGCgIgAAJ5ECiUUIFT4h9IXZGCpBlnl3p3LzfikhYqLFu2jJo2bep2hTIIgEAFE2jTpg21aNGigkeA1EEABEAABMqNwLx58zyBAs9f89lYoHDEUYcagUKjhuYhQn4fnvlP/9gs8efOXkATH5omh5H7WbNmUd++fSPrSm1MWliQdLxS86kt/UOoUFvOJMYBAiBQLAIsfGSBQlIrMx2hhI8DDuMVFIzwkccBoUKxzib6AQEQAAEQAAEQqMsEvvnmG0+gsGrVqrxQ8AoKPXsdYAQKnXaw94tUSHUfyrsTZe9J8VwPQoW8cKMxCIAACIAACIAACIAACIBAwgQgVEgYKMKBAAiAQG0lkItQQR7QihIf5MsnU2x9Q87ejMvUf/WY+bRw0uJ8U0J7EACBCiKw22670fTp02m//faroKyRKgiAAAiAQDkSqK6u1gKFSZMm6Qf+8smxVeuWdOTRagWFQ/pQQ36QUH5c5qBmgmtM1s5mXlHh4fHp33wMoQKT8req8y6lHbvs7BtQKjgBCBUKjhgdgAAI1BICLHwUgYLc+6rp0Fq1aklHqHnFgEN6U0O1goLMKzie3DfTUwpnXjGveiFNGJt+XjFz5kwaMGBATdNCOxAAARAAARAAARCoEwRYoHDjjTfqFRRWr16d15hZoHBQbyNQ6NCpvTevc8UJ4Xkddzjismtpy5atsX1XVVXRqFGjYutRAQIgAAIgAAIgAAIgAAIgAAJJEoBQIUmaiAUCIAACtZhATYQKjCOTWCBXZO6PtVGxM9W7/UGo4NJAGQTqDoEOHTrQE088Qf369as7g8ZIQQAEQAAEEiMwd+5cGjFiBD322GN5CxRat2mlBAqH0sGH9DJvOla/NOt34dlfnIM/POtKbxwQKngodAErKgR5lMsRhArlciaQBwiAQLkSSF746K/MxKqE+HmFIhIQKixSQoUpaTFBqJAWDypBAARAAARAAATqOIE1a9bQDTfcQP/9738pf4FCferV9wA6euggat+xnSbrChKC94tUtTOvY2cIFTQyfIAACIAACIAACIAACIAACJQJAQgVyuREIA0QAAEQKHcCuQgVeCwiGIgSE+QzVonLMaJi+/X1VH36niBUSM8HtSBQmwm0atWK+A3YRx99dG0eJsYGAiAAAiCQIIHZs2frFRSmTJnizXVrGp4FCoOHmAcJGzZoaB4i5GCiRXB+YNY/PqtjPc/1fokmmjtnAU0cPy1tClhRIYgHKyoEeRTjiB/U2HPPPdN29cc//pH4DzYQAAEQqEsEWPg4cuRImjx5ct7zCl6Zycwr+lCjhvHzCjOnYMo8r+CdP7GYVw2hQjl9/1544QVatmxZOaWEXEAABMqAQNeuXWnIkCFlkAlSAAEQcAnwv3uvv/56LVBgsX4+W/369al33wPpqGMGUocOO+hQIjx153LSh9wr8n8bNTUQKggh7EEABEAABEAABEAABEAABMqBAIQK5XAWkAMIgAAIVACBXIUKMiS5ORYWFWSyKxmCDhEWG0g7rnRjij1okyx4b358deshVHD5oAwCdY9AkyZNaMyYMXTaaafVvcFjxCAAAiAAAlkT4If9+UHCqVOn5v0gYRslUDhq6EC9gkKDhg1kimqECvZZQeeZQZWjMfJcV893xUfZeUUFCBX804gVFXwWxSpt3LiRVqxYUZTumjVrRp06dSpKX+gEBEAABApJYM6cOXpekdTKTIOPPoz6H9qbGjbKNK+w4gSeW5j/zDB5jqFK8+cupAnjpqYdOlZUSIsn0cqzzz5b369INCiCgQAIVDyB008/nR5++OGKHwcGAAK1hcDXX3/tCRS4nM/GAoU+/XrQ0ccMoh06tJXbQTqk/P6pbwnpDzabgtwr8n2MfeRl19GWLVtjU6qqqqJRo0bF1qMCBEAABEAABEAABEAABEAABJIkAKFCkjQRCwRAAARqMYF8hQosPHBFB3LTzBUOiM1g9JdDiGrnxjMPc5mbb8F47gnx7t55AgcIFVw+KINA3STQoEEDuu222+j888+vmwAwahAAARAAgVgCb775pn6QcNq0afkLFNq2VgKFw5RAQT1IqK49vMkb8XTZUSc4Re0l9dpuK7kthApMxt8gVPBZFKv07bffUrdu3WjVqlUF7/KWW26hX/3qVwXvBx2AAAiAQKEIJLkyEwsfBw8ZaAQKLHxUm3tPLVi2I1JzCH1nzJtLOHZlm88rKkCoYKGUfgehQunPATIAgXIkAKFCOZ4V5FQXCbAo4b///a8WKSQiUDjYCBTat2/n4QzO58zvm2YuJy7Wxjue53lzPGOHUEE4YQ8CIAACIAACIAACIMAE+Hec6dOnp8Do0aMH8R9sIFBoAhAqFJow4oMACIBALSFQE6GCuS/GN8WiV0eIQmNupvkiBfYJChX8VmK3998CfuIldebY3KATMQOECkIJexCo2wT474Srr76a/vSnP9VtEBg9CIAACICAJvDGG29ogcLjjz/u/dBbUzRtWaBwjFpBYUBvatCwvh9GTUsDQgXz6CAbAw8RcgM9g1WTWj2vdSa3c+cswIoKPlHKRqjguCdWHDJ4OA065OjE4lVaoKuuuor+/Oc/FzTtXXfdld59913i1bCwgQAIgEClEUh0ZSYrfOyv5hUNGzVUcwSZOKj5gp0jyLxBOPlTBzuXsG20HzspB24LoYIQK489hArlcR6QBQiUGwEIFcrtjCCfukbgq6++8gQKa9asyWv4DRqoFRQO7klDeAUFJVDQ8zqOaCdpMrczJjPnM/M8x4nd2cjzOW3WnzoWhAoMBBsIgAAIgAAIgAAIgIAQ4N8+BwwYIIfe/m9/+xv99a9/9Y5RAIFCEYBQoVBkERcEQAAEahmBXIQK7g00ESkwDhEW5IpG32izjdwYYndt2cSW/OaNfYsWTlqcTRP4gAAI1AECf/jDH+if//ynt+pKHRgyhggCIAACIOAQeP311z2BgmOuUbFtuzZ0tPqxud+Ag6ghv+nY/FasfyzWAdWx/hk5o912z/4y+bV7XlHh4fFT0+bHD0f27ds3rU+pKrMRFlSddynt2GXnrFLMJl5WgXJ0qutChWKsqoDVFHL8UsIdBECgLAjwykwjRoygJIWP/dXKTA30vMJ7lM2fY6j5gZ1W8KTBY+AUnbmH8hUXbqf+QKjgISuLAoQKZXEakAQIlB0BCBXK7pQgoTpCYPXq1fSf//yHbrzxRkpCoNCv/0HqpRYsUGjrzeUYpTebc+8BOXY9f/MmcbYp+/Is0JnbcawRl11LW7Zs5WLkVlVVRaNGjYqsgxEEQAAEQAAEQAAEQKD2EYBQofad00obEYQKlXbGkC8IgAAIlIhAzYQK8Ssj5DIM576bJ3aIsmUbUx7yqlZChUUQKmSLDX4gUCcI/PSnP6Xbb79dPVTasE6MF4MEARAAARAgmjlzpn6Q8Mknn8wbR7sdjEDh4EN6UYP69b3fiaUQ+NHZ+SE53q5S0j82K4/Qj84QKgRPF4QKQR7FPCrkqgpYTaGYZxJ9gQAIJEGAf/QTgUK+8dq2a62Fj1qgoN66yxtPB+S+lmewNpkq+JMG9tVe1tUeqJ0XQzlAqOAzKpcShArlciaQBwiUFwEIFcrrfCCb2k+ABQrXXXedFih88803eQ2YV1DoN6AXDRk2iNq1a6vmdP68jAN7x1zmCZyt9urEZCd3XjXbAxM+UwOhApPDBgIgAAIgAAIgAAIgIAQgVBAS2JeKAIQKpSKPfkEABECgwgjkIlTQQ/PukpmB+od+yV1twcURuUKCbea2ljaR/lLp7P17dSZKrkKFQb871ImGIgiAQCUQWPfFOpr7wPycUj3llFNo7Nix1LRp05zawRkEQAAEQKCyCLz22mv6QcLp06fnnfgOO7TVPzbzj84NGjQwPzCrKaf3Q7NbVr15PyLbya3288rswCkpq93zsSnqT64kCBU0Bu8DQgUPRdELhVxV4eabb6YLL7yw6GNChyAAAiCQKwFemYkFCk888USuTVP82/HKTOohNhEoyBxAZgHePIJbWqPMJcTHTiJkpx0D98WUo/ZVRv7f/LmLaMK49Cs1sbgzaon4lAHAkDcBCBXyRogAIFArCUCoUCtPKwZVhgRWrVqlBQo33XQT5S9QaED8MgtedZPvHfn3enRJT8j0PM5y8OZ53qTO9dPNAzG8eP5ET0eCUMECxQ4EQAAEQAAEQAAEQEATgFABX4RSE4BQodRnAP2DAAiAQIUQyFmoEDEu7wZboM5ddcG/81YvRn0QvNdm/MO+0o9rj2qXi1ChVZeWVPXCefL7rx6BydzmHz2MSC2G5BfAYA/cnNkU5cs+YXu4nfNLtI7sk5WUQnm7DtzCHQ8f6x+uuRC9hfuPyi9s40jhdunzdpKSopu32NwU0+RdjwfptInLL87uduPmnZqS7cTpK+KLFArnRglUpTCLyy9sz4019xnKO5ySOx52T8NaRwv9fzouvzg7x9Bb8P/MIZROUlJUeW/8ZhM9+osp9OnczyRKxv3gwYNp8uTJ1Lp164y+cAABEAABEKgsAq+++qp+kPCpp57KO/Ed2relocMOV2/FO8gIFJzrpVzT9ON/zvVL7O5FzLOpjDxXubZag+vDiUOoEDx9ECoEeRT7qBCrKmA1hWKfRfQHAiBQEwLJrszE84pB+mE2LXy08wr98JrMC1SS4TkBzymMjxmBNx2RNjyXMP9xa/2fjJVj8f/mVyuhwlgIFYRLqfcQKpT6DKB/EChPAhAqlOd5QVa1h8DKlSs9gQIL8vPZGjRsoEWnQ5RAgVff5OmYbDKXk/mb3qtKsWu/SH92MlG0rw0qcUyN+YRQwaWBMgiAAAiAAAiAAAiAAIQK+A6UmgCECqU+A+gfBEAABCqEQHGECgzD3GVLeajacnJv5kX5ujfy3BhR7XIVKlyghAry7LOfqU0sh11KDB6ya4yKlY1PRBh7zzIQXmxR3aSzSYpe+0w5iaM0jAkerpZm7O7WufaYUJFmiaHbSxAxRrVgn3T1tk3YJSq02KK6yWST+DpGNjll4xMxNMlR+uO8xJYpx3C9xPDaZ8pJHKVhOKA9DldLM65261x7ONSWDVtoym+eoA9mfBSuij3u06ePfhtmp06dYn1QAQIgAAIgUDkEXnnlFS1QePrpp/NOun37djT0OCVQ6C8CBXMVkjmnOyeVH4wDe8nAXrwC/nJBU8F00QZ1y9x87pwFNHH8NIkUuZ81axb17ds3sq7UxmyEBVXnXUo7dtk5q1SziZdVoBydhgweToMOOTrHVrXPnd8yucceexC/eTKpDaspJEUScUAABApBgIWPI0eOpERWZrLCR37brhEomMmAN6/gGYH+T+xm747LPKxmLF6tO5eQ9l6l+Kr5hvKDUMGlWfoyhAqlPwfIAATKkQCECuV4VpBTbSDAAoVrr72WeAWFtWvX5jWkhg0bUv9De+uXWrRt19oTH4TnddxJyn0ima+ZSi8PuWckMXRLPafTDQL3jqQRhApCAnsQAAEQAAEQAAEQAAEmAKECvgelJgChQqnPAPoHARAAgQohkI1QodfZPan7SfvZEfFdMvcRYnWkDu/EKYYAAEAASURBVP0baf7AtVfQ1bt553txSb0DP+THVrlJpz0cB98e3a56zHxaOGkxN8u48YoKKUIFfSPQNnXzirM7vYh7gIcYHT9dzCKeNHFDxDWL7NN15mBuIBvcNUXGkCRk78Z0G0u9s3ero5oF+uN20iDK2YnrunI5EEdiuP5ZxHPdJURcs9j+4ho4wb3YWfiaO9G2sTR0YrlFtzoudE3zDsSOC+4mk41PxLCimgVy5jaSjOO87btt9OSfnqHF05a4WaQt77PPPsRv3N59993T+qESBEAABECgfAnMmDFDP0j4zDPP5J1k+w7t6Jhjj3BWUDAXGp53yrXIn4Pqn45Nn8pNfoBmgy5LNuE6HVLi+k46vnSizHNnK6HCQxAqCCEIFYRE6fZXXnklXXbZZYkksMsuu9DSpUupSZMmicRDEBAAARBIigALH1mgkMTKTCJ8PHhAWKAQnAfIHMKbP8jcQQYlx6aZf4uA5yfsw/OHkI826/ambl71QqyooHmUx0cmoUK7du3oueeeK49kkQUIgEBiBH7/+9+n/f82hAqJoUYgENAEvvzySy1QYJF8EgKFQw7ro1fHatOujY5v7hXp2Zi9Z6TmZubQvy/kHrtljiDHtpHZGaP+tB8SU4JzvyMvv462bNmq84j6qKqqolGjRkVVwQYCIAACIAACIAACIFALCUCoUAtPaoUNCUKFCjthSBcEQAAESkUgN6GCvXumk5WnhdVzw7bo3TRT9WILj8t9wMutc1dJELvr69bH2aVdTYQK3JaH4Y5B4pkK78gv+Ag8W9oYnpctuDjZFBHPbaJjuwZbTttnln2kjRHu042ZIWdumlPe6ZzDeUhsNx/xCecV9gnXSztnH5WKtoVjcZsoZ7E7McUU+z0L+coNa8+cIe90acT2GR5PTB86dthXBuQlaAuuX0w8t0lOecc4898Lz1/5ElU/+JYbOm2ZH5Tjt2R27949rR8qQQAEQAAEyovASy+9pFdQSOIhrg4dd6BjjlMChYN7mjcd26HKfJP35hoqe/492bnQ2aL4c3OvXtXpcqSPdMTzT89Bl6vnLIRQweLhXTZChW6770WdO+3ktMqvyP/2GDhgMLVo0Sq/QLWkNa+q0K1bN1q9enXeI8JqCnkjRAAQAIGECbz88st6XpGY8PG4I+ngAeGVmcy1Xq75sueheNMAnl/IlCC2rFtoP+3KHzxXcQLZEFyh/5tXvUgJFaawR+w2c+ZMGjBgQGw9KpIjkEmo0KFDB+KHK7GBAAjULgIsRHjkkUdiBwWhQiwaVIBATgS++OIL+ve//0233HILrVu3Lqe2YWdeQeGQgSxQOJzatm2tq2WexXM5mc+Zsmnt3Q/iQ3Hmokz4tNlW8FTN2s3O2L1mXG/nc+58D0IFhosNBEAABEAABEAABEBACECoICSwLxUBCBVKRR79ggAIgECFESiUUIExRIkV3BtuLipXiCB2uUlnjv3VE9wYymoeEpdGal9ToYJ749AJl2zRfWjbu+OYYxdJxMilS7c/bleTvJOIkUvO7Ov2WZOcwzH4uKZxuG22W9J5FztnHmdN+nTHXdMYqt1rN71Br938BkfIamvfvj1NmzYND2VkRQtOIAACIFBaAi+++KJ+kPD555/POxEWKAw7Xj1I2P8gqldfXYTstUsuYTIP5b3MPc2eXcVLpeG1UwW3zBmKyTaUmJK8dvfisz9H3k7VsyFUEEa8z0aoUHXepbRjl53dZignTCCJVRWwmkLCJwXhQAAE8iLAKzONGDGCnn322bzicGNemWmYFSjUb9DAiyfX/rg9OwbmF+5cQsriwL48ueBN7XSJP/T8wextFe+0nXcQKjCF8tkgVCifc4FMQKCYBCBUKCZt9FUXCbBA4V//+hfdeuuteQsUGjVigUJfLVBoowUKMvGy8y+ekbHJztF4b4sKvTdbE2ff4oXhCRy315/azxSN3Vptexub+7CNIFRgENhAAARAAARAAARAAASEAIQKQgL7UhGAUKFU5NEvCIAACFQYgeyFCvuqkRmxgHcDTY8109PFwXoRL8hNPB9X0M+7i+c5hOu9CpOFU10joYJ/DzAYuBBHnGu+/SURI5exCd988k4iRi45s28SfSYRoyZ558Naxp5vjFzyToJTEjFUznMfmE8vXD2Dtm/LDkDLli31W82OOeaYXEYMXxAAARAAgSIReOGFF/SDhLzPd+vYqb0WKPRjgYJMTGVipi4b5sohPzLLXtntr868sz8P61TE7uUl9V4sW+P8qOz5qoL3g7bEV9H1igrjp7luKeVZs2ZR3759U+zlYEhaWJB0vHJgVIk5JLGqwk033UQXXXRRJQ4fOYMACNQiAkmvzMTCx/4DennCRzOXUMDk2q+LxirzBm/PXGXuEFHWJm+OwEd2k9g6rMxXpA/fh0vz5i6kCeOmWmP0DisqRHMphBVChUJQRUwQKH8CECqU/zlChpVJYMWKFZ5AYf369XkNggUKhw7qZwUKrayQgEOaOZY7Z+PpmTefk7mazMskC/aRttZmXGXu5htNU/0prU3/POeT+DbWyMuuoy1btnp+4UJVVRWNGjUqbMYxCIAACIAACIAACIBALSUAoUItPbEVNCwIFSroZCFVEAABECglgVyECv7DXP5NOJO7PF3MR8GbaeF673kw9rQ32MI+mWIY/9RPiZ2zUOH581KDwQICIFDRBBZPXUJP/u8ztG3rtqzG0bhxYxo9ejSdccYZWfnDCQRAAARAoPAEeOUEftMxr6SQ79apcwctUOh7cE+qX7++DufPRf35q9jCPx57dm7JPxTbhMRuD/WObYFpLlulTajC+KpoNiBHhlDBpYkVFYI0SnuUz6oKWE2htOcOvYMACJCeT/C8IomVmTp2VMLH4WplpgEHmXmFvpSbi7m+1NvrPVtkriB7PhdS1i1kjuDY2cebGzj12q7r7FzE6UfXcR7WJnOP+RAqeNjKoQChQjmcBeQAAsUnAKFC8Zmjx9pN4PPPP9cChdtuu43yFyg0osMOVwKFYw+n1q1baXDefMoceTDFznt/ymXngOzFdustvl5jU+3P1ZwK7SsB3fbO3E4iQ6jggEMRBEAABEAABEAABECAIFTAl6DUBCBUKPUZQP8gAAIgUCEEshcq7KfeOmsGZe6Xye02tolQwbW5AKTe2DhOfAz2iYoTjOFGl7L2UB85CxWe+4kOEdmrDFo6sXu5yRjOSmK4og4ejtxE9MKohmp9Cu8wMl6o7ygf6c8LpAqBvt0KVc4Uw20rvm4It57t4uOPRBmdvCPruR03Dm3h2FItMfjY7UdihNu5/jpGDOtAPCdntksMtz9t54/QFu5fqjPFCLcTf2nPgy2X7wjnFMU7JWflFzeuAEuHtxvD9ZH+PB4RsaUuLsZ7L31IUy95krZujH/DkMTgfYMGDejmm2+mX/ziF64ZZRAAARAAgSITeO6557RAgd94nO/GAoVjhw+mfv17qmsUCxT8H5P9sr3qqJ3M2WSuKr8Ty7XGuz6pCi6L3ctTYui9Z2VHcy2VgLaK2+sYNjB7QajgcFNFrKgQ5FHKo3xWVcBqCqU8c+gbBOo2gaRXZjr2+MFaoFCvvv8vWHN5Nxfz8HVdLv3unEHKugXPBewpErs+dOYGEsM7k9LGVkh7Pd+QA/ZRf+ZXL8KKCh640hcgVCj9OUAGIFAKAhAqlII6+qyNBD777DMtUOAVA5IQKAw8oh8dc+wR1EoLFHjuJNSCZW1VdXrWZvfi687fdHOeg3ED2UtIY0q1i58EtP46Lvfl2DkyhAoOUBRBAARAAARAAARAAAQgVMB3oOQEIFQo+SlAAiAAAiBQGQSyESr0PrsndT95P+cmXXhs+rabMvo/0gY9MtWzt/j4Dzo799+cetMHP+fs1/ttOVL12Ldo0aTFXMy4terSki5QQoVgBL+Z7s15qJpr3BuDfCyjDseQB7bD/tyGN6nngbhtJZ510js3hlvvttOO9sOL7RizieG2c/2dMF7ebr2bk/a1zOJ8ss47DRs3hpd3yF/y1vllyEkNzLiHYsjY3P4kLu/d2J49yxiSt8vJi8GxvZz4/yF+BpKT9s0wLr+VG9mJ7ZjdPNw+3BheTqqd6++E8fJ269142jepvFVycWw470/nfEaTL5xGG7/Z5KaYtvz3v/+d/vznP6f1QSUIgAAIgEDyBJ555hkaOXIkzZgxI+/gnbt0oONOOJr69DtQv+lYXZrtZgrmWF9EzHXE1utrijHzhc67+rrXNA7E7mwL2EMxxI/j6LLde3ZjNDFsWzbNnbOAJo6fxsXYbdasWdS3b9/Y+lJWJC0sSDpeKdnUhr55nnT55ZfnNBSsppATLjiDAAgkRKBQwsf6SvjozxBMsuYSz/MCPvYmBJ6f2GUqIPMH4+5EUwbnSIfSx9puwdggpq3pT+JrD/FVRu4HQgXLrUx2ECqUyYlAGiBQZAIQKhQZOLqrdQRYoHDNNdfQ7bffThs2bMhrfI0bN6KBR/SnocPUCgptWsotGxVTz64C8zlvjmWq9NyKO+f5malTZSnYrMwcTc/g/DpprxvbfmLK2mzrdOhQ/BGXXUtbtsS/mKmqqopYyIENBEAABEAABEAABECgbhDAigp14zyX8yghVCjns4PcQAAEQKCMCBRXqMADT3lc2dKwd+rYw3uA2VbpXWo9m8M3AdmWi1ChpRUqSFZ+Lxwpuy1T20z13Iv4cJlzcI/Fxvvwxn755MzxdPuITjPFdnOUHFybF5sLoS1T7JC7d+jGlz69SlvIFDscwz2WWFGxxS+qTtrF7TO1Tannm88iUnDGJfE5B2nj2qTs7sUv17ylHceKa8s+cXXcLiqGa2Mf3Z4/QhWZYnPbqM0NI7mtfGcVPVL1GK37cn1Uk0jbJZdcQtddd53391GkE4wgAAIgAAKJEHj66af1CgqvvPJK3vE6d+lIx3/vKCVQ6OEJFILzRXN1ML/zSlnt7UVDfPWhcrLmyDkn++o/nLU4ctEE12OJLeta7az8zV5MvKLCw+OnymHkHkKFIJaq8y6lHbvsHDTiqCAEarKqAlZTKMipQFAQAIEYAs8++6yeVyQmfBx+FPXVKzOZf22613ZJga/lvt2fFIjNTA1SH2jTnqrSa2ELjsXEFbsJpLv1itLeM5isuG/+A6GCnKXy2EOoUB7nAVmAQLEJQKhQbOLor7YQ4N8vWaBwxx13JCJQGHSkEigcqwQKagUFM3Xy52fujR2Zw/EkTc/LQnMxPhQf2bvM2eb6+JM9px03MEmYards67TJ2iU+hApCAnsQAAEQAAEQAAEQAAEmAKECvgelJgChQqnPAPoHARAAgQohkK1QYf+T9kszInuXLvyksddC6tngPkbsOaiC75NJqKCjqIe4zf05v51Ey0eowDFSIoZuBMY9QK7bia/zkLk7Yu+mpVOvxyPJc/82hnDgqqxiOzHkBqdrcvOOzImdnbzEJ6u+jZPuLpC38EgXW7eyH66/2CNy4irh5ObM9tzy1onrcUu7uNiBenZyt3DeTs7sJm2zY2lz0g2lpR+DzTL2AGtTwZ96PKYQaidG3odzZpuTt9+z3x+7ZPSJi8FtbZ+BvN08Ito6NDiCF8Mc2M+IdsbVP79rln9Dj5z/GH29fE2gabqDc889l+666y5q2LBhOjfUgQAIgAAI1JDAU089pR8kfPXVV2sYwW/WZcdOdPwJR1Fvu4KC1PA107/U+FcVYwvVqWrtwW04gOx10W9rq9iqY2tvp1qu057JJiB96vb8wRv3wY7Wh01YUYEp+BtWVPBZlEspl1UVsJpCuZw15AECtZ8Ar8w0YsQIevnll/MerAgf+x7cU/0T2Pzr2Lu+O9ds6Uiu5eba780A7OXdXuvtvIHbeLHMgZl36DJ/8AzDfqqCLts+A2XjpOcQrl035Ri2zby5C2nCuPQCyJkzZ9KAAQOkKfYFJAChQgHhIjQIlDEBCBXK+OQgtbIk8Mknn3gChY0bN+aVI6+gcPiRA7RAoVXrll4smSuZKZNMrPTUSvmYYzudEqM3L+Nav73fVoJzO75XJD42nNee/bxWylmX7Ydvt314SZjoECoIZexBAARAAARAAARAAASYAIQK+B6UmgCECqU+A+gfBEAABCqEQDZChV5n96TuWqjg3SILjc5/pFmeFzb3zsTfr/dvv7k2Die+bmjXJ6qefcXHr89JqNC5JV3w/E90pymRQjcA3cxMA9NCf6ru7e1E301gKAv7eDclfY+Uh77DPvoH8WxiuzHT5q0yMWmbXTaxo+I5Y1MDc3tXcU0f4bFoJ9vOpuCf9VCMQEA+cPrjtqmxTZ9eu6h4GWIUMm893gRYR41d581MfJoGQ3i8Hhx2Dp4zt0p/QXTC9quSQN5R/fF3O/U8qkxs3jYFf1Rpc/bb8ViiOLF13ar19OgFU+jLd1ayW1bbiSeeSOPHj6dmzZpl5Q8nEAABEACBzASmT5+uHyR87bXXMjtn8NhxJyVQ+N7RegUF/fe/9XevMW5ZwpnLCv9oLBazF9+4PXv5bfz24m/qU67KupHuyn543aqC11YFZnv1nAU0cfw0DhW7YUWFIBqsqBDkUeijXFZVwGoKhT4biA8CIJDkykwsfDxOCR/7HnygtzKTS5iv2e48QNfxtZwL9jpuj0yVrvCv9XLN9/a6nXZVMSSQRHD7CsUXV44v/fqJeflwZAgVmEL5bHVZqHDWWWfRokWLYk9G79696d57742tRwUIVDIBCBUq+ewh92IS+Pjjj7VA4c4776R8BQpNmjSmwwdbgULLFmZ+ZAfjzcX0XE1/eMM0U6rQPIxrnTmXmYKZdhJLAsiUTOwpczyJ4zXguZ+KZdPQZd2fa5d8ttPIy66jLVu2SuuUfVVVFY0aNSrFDgMIgAAIgAAIgAAIgEDtJAChQu08r5U0KggVKulsIVcQAAEQKCGBwgkV7F01PTZ55JgPsrELkLh2Us/7VJ+chQrPnesG1GXO0ovspsy1XoV2DX4EGgarvCPHxyl61bEF5bzd6dspek0C8fhAtihnqVN7vmkqbwl0zMFiIHiwKt2RviEbevg81t/NmZ1s3nFd801f53n81LBOQ6eY6hdhYX/ZovAF4rnO3CiqgQTLZu8Ed4qZWypnfEeCmMLfkU3fbqLJFz5On8z5LOiY5ujwww+nKVOmUJs2bdJ4oQoEQAAEQCATgSeffFILFPitvfluO+7UmYafqAQKfQ/Ucxh9KXZ+7JUfhLkftyz9so2vEeFNfOP27C/tAj8ki1HXez8r++H5Gh33w7O0VXv+X/WchRAq+OQIKyo4MMqomM2qCjvvvDMtXbqUmjZtWkaZIxUQAIHaQiDJlZkCwke5DxE5T2B66motdbagD72yVDpzBqkL7XU0392bs7BJ5iLsYzbpV9Wa//Sek9EhJLa4817Z5lUvogljp7jWlDJWVEhBUjBDXRYq9OvXj2bPnh3LdtCgQTRjxozYelSAQCUTgFChks8eci8GARYo/OMf/yAWKGzatCmvLhsrgcKRRx2iVlAYRK1amhUU9D0gG9VMmfTsSVlkfuV3KfV2ahWo8FqpSpmryZ4d3TZBu2kpczaJI8G1rzXamZ2e5+myaWRjQ6ggzLAHARAAARAAARAAARAwBCBUwDeh1AQgVCj1GUD/IAACIFAhBHITKvCgwrfQ2OY/lc0PjcuNPK5x68xxuL20DduzaRv2MTFyFSqc/+w5agSSh4zQxHLtJn8ZRXS93ER02xnPVH/xdeOmiAVMM+0S6R/IW5zd3t3oPLb0ebgto3w5mtjdyIG8JY04XydnN57btxvb7c/18e2u1c/PtZqUnMRsBzXN243n9hOVd7he8s7GLr5u3EDOXOEMK9Lf4e3Xh3v3exAf10Ns7BVld23s4/rzMW+BvHPImdtKvHA/XMeb1HPZ9fHtrpVoy6YtNO3Sp+j9lz7kJlltvXr1In7AtnPnzln5wwkEQAAEQMAn8Pjjj9PIkSPp9ddf9401LO20c2d/BQWevtlrit7xD8VO3Kgfhbk6aHca8BVF4tmC+Hp7HcC59ih/3avTccBXwktu2s/Jk+1ss/2x+1ysqCDU9B5ChQCOsjnIZlWFG2+8kS6++OKyyRmJgAAI1A4C/O8ynlckszKTFT7266FfgmAux+ai7lyaPXBSL3uZeLhzAecq713evbmBDeodc2Q7h0iJoey2yvSv2trMdIUu80eUXcc13hAqGHzl8gmhAoQK5fJdRB7FJQChQnF5o7fKIbB8+XItULjrrrvyFijwCgpHHn0oDR12OLVs1dxAUNMhM2eSeZTPRuZj7GGnaLpS7K5NJl9uLN/PzLm4sbSJmtfpeuvktzCNTFzj4dWpgvQhgTkuVlRgTthAAARAAARAAARAAASEAIQKQgL7UhGAUKFU5NEvCIAACFQYgdyFClED9G6dOZX+g/+OURWjfNlD/N16sQUjBGO4PqZt/kIFN4fgg8+cian1feQR6PCtzmi7WDmOH8Mdoe/hW7PxdX0yx/A9otrFjdGMv3R5S9Zx+QXt4p0b67gx+tFS47l1pr3/ySWpd1nH28U7tR9uw5vvYY75Mxxbalxf18e1i69b7/YStJuaIGvXO7tcovsUa3y8bPOOy0/s27Zuo6cue54WT13id5qhtNdeexG/tbNbt24ZPFENAiAAAiDABKZNm6YfJOSbZPluO+/SRa2gMIR69z1AheL5n/kbnXe25P+A63Tm/ajLLewvxrIXN2O2VwjeKYM+kr3blhtF2L0kHF/tav39ne2HDbxxLNunMZBeUeHh8VPlMHI/a9Ys6tu3b2RdqY1JCwuSjldqPrWp/yuuuIL+8pe/RA4JqylEYoERBEAgDwJPPPGEnlcksTITCx95XtGn34EqI39eoa/JOkd7fQ7la+rVhVv/5+wdP3eeIdd4vtRHzR+MncPpkh9X+5ug0tYz2SS9XExo48yRuIH1YSOEChZNmewgVIBQoUy+ikijyAQgVCgycHRX9gQ++ugjuvrqq+mee+5JRKBw1JDDaIhaQaFlyxZqGmTnVYqCV1QF3+rjEd/wXjxMe9tS7XQUvefYxi57bsMmr6dQ2Y9p20kDbhcu62Pbh+2HTbyNuOxa2rJlqzmI+KyqqqJRo0ZF1MAEAiAAAiAAAiAAAiBQGwlAqFAbz2pljQlChco6X8gWBEAABEpGIH+hgrmpljoAV0Dg1mbjLz7ZxHB9TLtEhAqSgpe62w8brYM2S52yhdsF6m079lF2eeDavXGpfx9nN9ky+EoMdpebpNLU7CU346FtcTm5DeN8bN6BnLmd2w0f55J36EZrdDDpw+1IdcL9uFsgb1tvc2a3QN5uKFNpIoX9Q2Px4oT7joSgvKNyMj15/QXHXIO8wzmbJHXYUn1HTAp2LHwQxTvbvAv0Hdm+bRu99M9Xae4D8znDrLaddtpJr6zQo0ePrPzhBAIgAAJ1jQD/QCsChTfffDPv4e+86470vZOGUK8+LFAwm7ksmAuxe4lwfxwWX96LnfduW/GRes9XLl/sb53ERx9H2D1H7s8E0i11BBtEYuhqXas+JCeTmLZWz1lIECoIICIIFXwW5VZas2aNFnB+9dVXKalhNYUUJDCAAAjUkACvzDRixAhKUvhoBAomocD1WS78qsq1u6mLnfdSjqpnm65XMWVuIOGlXZxdx7PO4uvF05XB/CRu1LwCQgULrEx2ECpAqFAmX0WkUWQCECoUGTi6K1sCH374oSdQ2Lx5c155Nm3ahAYrgcJQJVBo0cKuoKAiBudOpgvX5nYq9vA+yocndHKPh+deUW3YJvMyqdexrFHvnPs/4uPapX3UvI5jQaigieIDBEAABEAABEAABEDAEoBQAV+FUhOAUKHUZwD9gwAIgECFEMhPqODdMosYbfipZHbJ1l/8omKE44iPtFFvoR37Fi2atDgip1RTy84t6fxnzqF69SSOf4Mx1dv3CYzFa6ty8NPwm3v1yuTchMyuTxMmzjfO7nfOJcnbSS4mp0C7GB/pU26iBtqEDsSXza5/nN1vLjnrlo7ZsTssPQddbX2c+sz9eRF0QfzlxjMbxcZldyx87G9Ofu6XwWNZx74jzMD52vmc/FIc1zi709Ivup14rFW18x1wnPlkmkNb/8ao2fTqTdm/7btdu3Y0depUOuywwwJhcQACIAACdZkAXxv578aRI0cSv+0/320XJVA44aShWqAQ/GubHwqU6HFlqZdLgfiZ65K+vouLNnkBvdhyrU/Zczu3jZRtCD8S+0lP2slcrbRDOB/jy6F5g1DBcJBPCBWERHnuo1ZVwGoK5XmukBUIVBIBvv6KQCEJ4SPPK2RlJv63pplLmKu2WzbXeENK5gAuN9cmZdmLnxtPl9WHufzLvICnCLZvbqSKXk2orKtdX2Pgz+AYtMUYpU8xQaggJMpjD6EChArl8U1EFsUmAKFCsYmjv3Ij8MEHH2iBwr333kt5CxSaNSVeQWHosMOpRUsWKDj3WPjITLw0Ainb6VQKFm9OZtuIv2ls3IPzNGVTTuzut9WNTRNb1B6qbA5NwVbZoFLj1GmTjIXdnLIzAAgVDEJ8ggAIgAAIgAAIgAAIGAIQKuCbUGoCECqU+gygfxAAARCoEALZCxX2DY5I7qq5z2VrDzGIQ7BZ8Eh82er6i13ZxCwmHcA9EAc/RPW43IUKHFbePG9uM+qOIj64b6dP7SH5hO1u86h25uF3uaHpekeV4/Jje+acOWI4v0x5R9fLA+S55B3OL24swXFHM+MzlToWt2V83rnkzBGTyzs6JzfruHGZhyjC5y7YUo7iuBbuO8I9p56P4n5HOIcwn9Sc2MvfUs/H/PEL6fmrZtD2beFYfiu31KJFC3r44YfpuOOOc80ogwAIgECdI8DX1ilTpmiBwuzZ8Q8eZQtm19120gKFg3p3D4gE9VXZ/hXtX8/VlVrbTIXzu63XndTLXi4Z+hov8cSoWkkM6SO858CeD7eTGMpoi17ffs7GT9fzh/jaQF47ewyhgoNQFSFUCPIot6OoVRWwmkK5nSXkAwKVQ4Cvu7wyE6+gkJzwcQj17nuggmD+nWgvtxaKzCXk0FyVzTU7eG2XOQF7BsvaogPExRb/lL3fVM0jVK92UhAoq6DWrPuQjkyOJoBXz75yYNvNr15IE8ZO9dtGlGbOnEkDBgyIqIEpaQIQKsT/e2HQoEE0Y8aMpJEjHgiUBQEIFcriNCCJEhBggcJVV11FLFDYsmVLXhk0Y4HC0IE0ZFhwBQUOKnMsnkx5cyFdNhMj3xZMgdt5dV7BjacjmkYqlD/N4nYSW6zczo/v1bNJVThVNh7bJAb7aEcTQ2IbT8+fCxAquFBQBgEQAAEQAAEQAAEQgFAB34FSE4BQodRnAP2DAAiAQIUQSFaoIA//8uBTbrtFEInzF7uKIWHEpKO4B+Lgd1lToUJEgqkm7s7tnru1Kcjbfr1GodQCzQIHtkVEbC9WPgXJw+1T2bzuXDv3I/62GKgOHDi+YTvHyXfzEnQCxeUdyplbeCl5hWAc38GxJ1GMyBvfEfeEJAHZxohgzd9fz+yeezY6zbjoVdvCkieX0vT/e46+2/KduKbdN2rUiO677z4666yz0vqhEgRAAARqIwH+wfWxxx7TAoU5c+bkPcTddt+ZvnfyUOrZiwUK/vzKD8w/Apsj+bGXj0zZVEi938bU+3blJzFMY+0qPww7JhtX4vv7gI9cdJSRw7p5sR9bTd+mX921cTRp2MS0XbubEoQKGp73AaGCh6JsC+6qClhNoWxPExIDgbImwNfQpIWPPK/o1ecAb9x82U29Vods7rVZleUa7bZzyxI8U2xpE95ze9ulDuXVc8+2c7ZJHtKfqXZ8xINNXkCeh2yn+dWLIFTwwJW+AKEChAql/xYig1IQgFChFNTRZykJvP/++1qgwPfOkxAoHH3MQBp67OHUvHmzwNzJjFHuvfBRVNnMpLwpkgVjjh1/x0HmU7albeHP2/T8zPqLr+7dNND+Ytcm5etUmXjapqzmP703Mdjge3sla4NQweDDJwiAAAiAAAiAAAiAgCEAoQK+CaUmAKFCqc8A+gcBEACBCiFQY6FC5Pi8x35VrXf7LNIzUaPblUqhemwNVlQIxYjML8pH2eSeoRYqCALHV+o5ZkDMIL5c4fj7T09zhd3i6uPs0o734uP0p3Niu7Jps9SJLzdzypF5O/WRObt9c1n6SGfnOt6iYiubNvNHFnlH5hwXm+3uFtO/5+KOxTOqQkw7jyXnLW0dX69ehfDqOa74ctnxD9i5jre4+ji7aWU+xcfpr65+Rz58ZTlNvXQ6bdmQ3Rue6tevTzfccANddNFFLlGUQQAEQKDWEuAfWidNmqQFCtXV1XmPc7euO9OJpxxDPQ/aX10D1SpR+ppkLkz+9dE9dn5EVr3LD79uImLz91wrFztTNN3ID8V+nfQvffsxbA42lLSUsFIr7diNByP92GYmjZDdrzNR5s5eQBMfmsbm2I3fMt23b9/Y+lJWJC0sSDpeKdnU1r7dVRV4XvTrX/+6tg4V4wIBEEiYAF9nCyF8lJWZ5DrOaZtrdHAewRdmY9ce5jrNvraBuTLzAbc3RxLHWM2n2PxYuoFME5y2EsONzLE5jp+LnkFYF69f05X5VA1sE9NO6tguFbb9PKyoIHTKYg+hAoQKZfFFRBJFJwChQtGRo8MSEXjvvffoyiuvpNGjR+cvUGjeVK+eMPQYJVBo0UyPyJsX2XmOnbX58x/lZeZC7C7zIt1Uf0h7XWsdXZuxq0+eU+kW2uKX7DyLm0o72WtPqXeamTjcQP9nYknf1mib6Todz9YbZ9uOc1J/Rl5+nWK7VapS9lVVVTRq1KgUOwwgAAIgAAIgAAIgAAK1kwCECrXzvFbSqCBUqKSzhVxBAARAoIQEchMqyFPM5tZaatpSzzWuj2N3b7A55ugnsl0HN57Ts2u2T3hXj51PiyYtdpziiy07t6Tznz4n1YG7dmOnengWcXOz9SptgYcdeABdHHLoR5qk3WeK59TrU6GO2RS3RebtxIhrl7M9U0ynPlPeul4lkMLbiZFzflENsolnffR3hD/UMZuitkjW7JhNP1EB42yZ4jn1mVhzF5F5OzHi0sjZnimmU58pb12vEoj7jnw2fwVNvmgabVyzKes0//a3v9Ff//rXrP3hCAIgAAKVRoB/DH300Ue1QGHevHl5p797t13UCgosUNhPCxTcgMEfefVVVFeLXf4eZ6PYotpLneyDPm7buD78H7UlhvZUCXgtbMHs7CfvbJLSjvv28pb2nsFkxr78h1dUgFDBMOFPCBV8FuVcGjlyJN1+++20dOlSatq0aTmnitxAAATKgABf7yZPnqznFXPnzs07IxE+skBBb+pa7F6D2WYuu8612l7NXTubjEdqexPDnxv4nk5saW+CmliqrGPKXucivXBUG4nrdXtbJzs22k2X7LHZmTrPQxm13fpwMwgVhF557CFUgFChPL6JyKLYBCBUKDZx9FdsAsuWLfMEClu3xj9En01evGoCr55w9LCB1LyZEShIO3d+F18W73TzOTuHcuZM0sqY4uZ80s6PHc7Dn5dJRJ7rWava6bIc2v71oWsL5SV98B5CBZ8rSiAAAiAAAiAAAiAAAkQQKuBbUGoCECqU+gygfxAAARCoEALlJ1Swd+M0P37yWDbXLja1d801Eiq0oJ8/xUIF25faub1yfL5xWI+tgQonB1s0qZhP7Z/qEmvRrUxT5eMVjL/u2ulcVZsbm74t/MC13LjMJe9cc+bkgvdLnbzDOWtfqc8i7/CADInAp9zcLWjeHmvu2uatx+akYn1yYW2i+RycaLFFTU8Q4juS8lBrFLh8viMrl66mSb+cSmu/WBcVOtJ28cUX0/XXX0+8ygI2EAABEKgtBLZt2+YJFObPn5/3sLrusSudpFZQOJAFCup/MmeRwO6xmWeYi19q2bRw/cMxpE72Us97iSd7XWev6an17G/zsJXhS7Jcc/gSrcvWQe+krTRSx65d960+uA/+A6GCEDF7CBWCPMr1iFdV4Lein3NOhAi8XJNGXiAAAkUnwNe5JFdmYuHjiScPpZ5KoMArM/Gmr9nqQqv3oRG6NinL3rT1G7h2sar01cbXa8+iC2LXtXxg6yWGaWav/xzBDyCBtI3todABX7ddoCxRuD0HcOLPq15EE8ZOEY/I/cyZM2nAgAGRdTAmSwBCBQgVkv1GIVqlEIBQoVLOFPLMlQAL1XkFhQceeIASESgcd7gWKTRr1pS2b/NmRV5agfmPne+Yne/rTIMC8ygOIu1lzxMvZ/al+5F4fhwTO2i3cy43pukgdS7nWwLzNB3VdmLKOoCdxunEdD4mrOQAoYIHBQUQAAEQAAEQAAEQAAFNAEIFfBFKTQBChVKfAfQPAiAAAhVCIHuhwn5qRPbmWOTz1Ww0N8vM0F0n56aa9wC662thuSbdPCKGZ/IKtjF3bwJUj3srhxUVlFBhunqYxsvLPo7O4XXa+kMbMz2I7t3c1Bkp74gU/WT9kn/Dk/t0IahjG8Pr282JQzidSFGHkDiqvfxYz+5Rm5t3Jl+3vXShbe6BM24vHucd8PGddN4R45LxuH16ZfG3Bq8fzyG+4KYR4O2n5DHTOau+zMYwvZIpSx7so6t9H9sosAswUA3SjtFtqfuxBp2P/jAGmxMnEMdSQnn9cTwBkWPehWKt//8mOXHCXrJ+MXA+VL3jIkP095qZz6kmeX/z6bf06C+m0NcfrfHjZij96Ec/onvvvZcaNWqUwRPVIAACIFDeBFig8Mgjj+g3Hb/11lt5J9ttz93oxFOPoR49zQoK8ne6dz1SPbhl7tBcFvwff00SwePUNubv/oDdXg7cH5+DsT0HdTny47sxpKw9VWPbQiXJ//ntdd7GKFabtvWy1zq741HKf2rPfUOoYID5nxAq+CxQAgEQAIFKJcDXtyRXZuraTQkfeV7Ra3/170JH+MiXVb6eMii1D29yPfer+dqrjzxXv5nUeVU6tt/WtEv1t/2qnc5E74O+gTxsQG7l2tlspgkmANfrzXaoj/3OvTFrk2PHigoCrjz2ECpAqFAe30RkUWwCECoUmzj6KzSBd999VwsUHnzwwfwFCi2a0THHHeEJFDh3PZ9zhAopcyTx8SZIMuLg/M1tF1m27fWcTULY2HxoplTKyfzHFs8m0y2Jq0Mpow1p23hHfgzXx3Zi2uoDO6czZa9faaP2WFGB2WADARAAARAAARAAARAQAhAqCAnsS0UAQoVSkUe/IAACIFBhBHISKqibYN7mPRzNFjlQ9eLiPkEcaCe+3E6cg0Wu0VtWMcRZ7W0/1WOVUGHyYqcivtiysxUqsIvbHx+7efMxb2EfY1Wfzti1n/fheaQteCi8gu/uIVOFbHIK++j2XhA/ri7lkbeXqlfwYwe6yybvUB4cKZY1V4b8046R/Z3NS9cr+JUZ81YOrk+YNUdKl7frn0vOHNdL1yuw1WxeTqrg9uHVew7GEvZJm4vqz+0yra90aPdeO6/gOwRSUgfhnNgzwDKUR0q9H9qUQv41zHv96g006cJp9OXileEOYo+HDx9OEyZMoObNm8f6oAIEQAAEypUACxQmTpyoBQoLFizIO809RKCgHiTUm70k6B9y+a9q+/e/7N0OuSraboMoZ7c+ruxex+QnY9OtiaPb2ZBcluhR8XRdjI80dGN445E2pmNxVQNwxsA+6g9WVPCo6QKECkEeOAIBEACBSiKQ9MpM3dTKTCeeOox69hLho6Ghr9nONdVeblWlXNUdPwvQ+PC1lw1hP2OTOO6cwDb32qX6+LGknfQR9jVdR889dD/KgWulnfTNBmnr2VSB+9O+tgF7zdcrKkx13VLKWFEhBUnBDBAqQKhQsC8XApc1AQgVyvr0ILkcCCxZskQLFMaMGZO3QKFFy+ZKoHA4DRl2ODVr3tRkYadRek5jhQoyn3LTNFOdiDmScnL9o8quzUyopGvbuRvDzsXYj2v9tn7fYtOteS5mwjm+3NAYwz7W1fh68zcJwM1UC24kcdUeQgWhhj0IgAAIgAAIgAAIgAATgFAB34NSE4BQodRnAP2DAAiAQIUQyFqocOK+wRGFHzLmWnsjTTvGPWDs2e2dOYkaOkwfg2sDCahje8NOlXIVKvzsyXOCz0NzeLXplNy8wl0at+Q+3b5UVA+V00MgJ5VPOCUvhFfgQE6AuCL7Z+MX1T7UVziMV20LGcfFfYSDRPWbj81LygTJJqdsfMoub8UxjNIbulfIkjf7h4Nlew5CfYXDeNW2UG6sN6/dTFMueZI+mf1ptiOmgQMH0pQpU6hdu3ZZt4EjCIAACJSSAD9IyCKrK664ghYuXJh3KnvutTuddNowOrCnmUPqv+K9v/B52qgO9H9mzx3Kj7vSuZla+j/+it37gdY0MnO2yPa2Q29nC7odd2/61lY7j+Wy5CF7041pK77miJ39OOzHG7fz6o2Jjcbm9GMNXGU261M9ewFNfGiatIzcz5o1i/r27RtZV2pj0sKCpOOVmg/6BwEQAIG6QECEjzyvSGplppO0QIGFj3Lh1JdXjVNfs/maLNdZ3yXk71fI9de08e0c0NT5cxCJqzuzH2yTGKaNxJB9OB/fX+Kxp5SDMWwntt7tR9dw36aB7+j6/n/23gTOrqLYA26yECDsm+xhD1tAEyAsAQQEVFYRBRH91J/G956gPH2foICfAQQX4KlPxaDiggrIvhPComwCQhYg7Lv4BETgARIgC1/X8u+uc+45c+/MvTNzJ6nD5HR31b/+VV33zu3m3FNz1IBQXqhQSNGgD7xQwQsVBv1N6AEMSga8UGFQ0u5OO5iBhx9+OJx88snh3HPPDQsWLGiLmQoU9vnAbmGPvXcOSy+9VN7Z6RYq7Y3iGH20cCxbnby3gpxai0UfLXCFMfnJUTAk6aHjlskTEhi0ZEhxJa5Sn/UKiipz6DxYqNYK4BH1sbeLrRcqmNR51zPgGfAMeAY8A54Bz4BnwAsV/D0w6BnwQoVBfwk8AM+AZ8AzMDQy0FKhwuFbhy0OqCpUwO3G8UqZXjjLNzJDR3mA0nStOqWKhAabyYpyC0m2saOcXKhwaetPVKBCBTpwc7Re82PZYJ+axdRMP1jxU1w95bEb424lplYwA53zZjE10w90vPDHccXf5dpfZ/197ul9BK6BaBe8vSBcc8z08MQfn2rZ3bhx48K0adPCmmuu2bKNAz0DngHPwEBngG4k/MMf/sAFCg888EDb7jfeZP1w4If3DluO0wIF/qDXL12V3X6JSwtB+uI16q1O1gBZKQrrgQ6EWr/ELdliIswHHxBSCxm3qoi8zElq+Ci3aitNNgae5bChAR+CY249CcTICad2M2fEQoXzvVBBcheCFyogE956BjwDnoHuzwDtKy688ELeV3TkyUyx8PHAWPg4bhstUOClkxdTLJucFKzDWPdJqMsq9RiTZUV72FbhwJExQmXHwJC99NVfbOAZeGqBgV3efUiodWPgOQLiyRMSkY4Zp2BC3TvzgXDBef5EBU5SF5y8UMELFbrgbeghDEIGvFBhEJLuLjuSgYceeogLFM4777y2CxSWXXZ02Gff3cKee00KSy09iuPjvRH10vbJbqB4d5V1hc1QFGO/gw0XZhzlEGUMJABZ+5IuDplBxdCWucpjnkayYRJ21sCFuFWb7Ng2orVNcsbFk9pNOf70MG/efEgb2smTJ4epU6c2yF3gGfAMeAY8A54Bz4BnwDOwaGbAn6iwaL6uQ2lWXqgwlF4tj9Uz4BnwDAxiBvpeqKB3EVPseoEMhQIyHaNPlwUJK1o+W0jBGCALgKzEYehA0ddCBUvlfc+AZ8AzUM7AwgULww0n/ik8ePnDZVXteMMNNwzXXXdd2GijjWoxrvAMeAY8A4ORAfoLeChQePDBB9sOYeNNNwgHHbxP2FKfoMBf6+LL19hiu4gvcgsO4zav8MUtwBFk8UmcOqLHLtFiwQ8Z2ixnch7CngbA1bWCYTM+ZRxrCjKRKDvPMUpoGONnqc5DEWxLulkz5oQLz+/5hkJ/ooKkC+fJn/rPsOYaa2PobQczMH/+/PDSSy/xv3/+8589tm+++WZYeeWVwyqrrNK0HT16dAejdCrPgGdgsDPQH09mOvDD709PZqL5LSG7BV6rzVYgrd3IAesMAGs16bO4bm+S5QBjzcZ6bfkKPmV1l3gUXLYhW4kBLW0NgKIAhZFltk/iOGaRTsLGoVDBYJLkK/7nhQqS0245e6GCFyp0y3vR4xjYDHihwsDm2721nwG6TkRPUDj//PPbLlBYbrlYoPDB94Y999klLLUUFSjEHYpsakpt1GAfY6bAMt3sWH2xXzDgAZkAg9ag6nXRsLgXy1bgodb2gbDhQ0+62n70JHoCcVewSqQiKLj1QgVJh589A54Bz4BnwDPgGfAMeAYkA16o4O+Ewc6AFyoM9ivg/j0DngHPwBDJQPuFCnzVTmZr6wpYAoG5nGa6KCwoGlsAaZpwiHGBoq+FCvZioaVFfwn8afoowAVHIwIsteCzdknJHDLXOj1hwWHtinhc1LWI3C9im8dt/ZVtwQpMnZ6uqCI/sGnENmKApdbiLVddvpvHlHNpua3PVuKGn6JdHlluxF0XM1mBz9pltuZ6y2Htinyt51r4hKkubsRMqKIfsaMzMHV6i8lWZb7W40auiatZ3K3EVI+JMS0M4bbv3xFmnDPbht5jf4011gjXXntt2GabbXrEudIz4BnwDAxEBqhAgb5opi+cO1GgsMlYLVDAExTsl6xpT1D8TMc6keYbt0SQyWd63g9CTtj0ea+dyBqF/JOpEkhEbM+YzCk2Ojb2RV+ihwxxsTSZZmPEwnGaoJQlx0mCSGbxYqPnqPcnKlAu8uFPVMi5GIjeq6++yo8KvuOOO8Ktt94abrzxxvjXGud13PXGG28c9t5777DjjjuGHXbYIdDYD8+AZ2DoZaB/nsy0Txi39Wa0mqb9AWWGCxWikFdRUuqBtRpjWYYZWLAvbhEii3JYe9sHgGG8douHAgZO2Z0Qsh7cpRhJJ37RynxAw5OOA5pjoU8A+AA3JiAqQkRM5uV+FN07c44/UYGT0x0nL1TwQoXueCd6FAOdAS9UGOiMu7++ZoCetEnXi+gPW9D1o3YOKlB4/767hz33jk9QiAUKsoWRPQ7vdSI5bWfs3sr24Rt7K+yhCnId5G0R+Elh9kU0yiC2whgtCy1OqCAu2JMN7GxccMHzi/Z0YK6agGRndWzHeI0ZRGxPyHiozAsVJB1+9gx4BjwDngHPgGfAM+AZkAx4oYK/EwY7A16oMNivgPv3DHgGPANDJAMtFSp8fOuwxQFjdUZaOGAulFXVEqTpo84AAr04x0Ors3JgrZ5kwJTlHEBUqp4LFS57CCw9tsu+a3T4zLWfKFwcrDPAzct26oStujEaFylF3xAwx5ouUDJHI8ZyEA+OJWi+BOcpIynQNrYtx13ig51lLMfUCgb2wJY5oLdtmmMU2nw3yzVxwI/lsz4tdx3GysFnOaze9oGV1yZrmsWd7LJJw+tbhamLKc2x9JpaetsHt8016RviLvHBznKVY2oFA3vEXeaA3rbAkszG3RAz64u/J81istzWp43r7rNnhj//+C5+nSymrr/iiiuGK664IkyaNKkO4nLPgGfAM9CvGaAvmM877zz+wvmhh1rbJ/UU0KabbRgOpCcojNvUfBbqF6rRkPc5vG4QS5aD036m8ud4POXP8/y53YBjOmJXTPIB5uhNidBmqICTLXNJ+AmrNBjnVhRsyzTiH/rkHTpRwzUFJX2KrYSBLbiHeqHCP158Lvzk56fHaWkSMEFtaR3+0r8fF1ZYfsWSpnrYab5qL4uvdO7cueG2224LN9xwAxcl3HPPPW3fkNKXbK655pphjz32CHvuuSe3Y8aM6QuN23gGPAMDlIFOP5kJhY9bxSczYT9Aq0hxneUFNK4u8b/SEmNx3CeoAZkusXKWRFbksjbkxLqBDm1KtYIYTX5hxX1BwYZaxAI8IYo2iTDLBSRjqLVla+7Hk/zENinDbC9UkBehS85eqOCFCl3yVvQwBjgDXqgwwAl3d73OABUonHTSSVygQIWo7RzLLb9sLFCIT1CgAoVR9AQFObD3wb4H2xXsk4CjNsl4bxMtaGvD25u8x0kYxpMVHYoVsN0SiVadWlvZPwlvQU5s6hOxMgnLyQ9skpTxmJ/lBYJlhkwZxI/lMxiyZc4IpvbE48+If0xgfqIsdyZPnhymTp1aFvvYM+AZ8Ax4BjwDngHPgGdgEc2AFyosoi/sEJqWFyoMoRfLQ/UMeAY8A4OZgd4VKpib6e2FMojlqlrjdKAnjcXUycFQp7fyVCVB3ELe20KFT19zBDwWWr5Z2UjSBUYja6XbKZ6B9uVxN894p3LUKZ7mEVONS+EXKJr09Z3dyNV3puaRl+Nux1enuOZc/GC46ZRb4lMW7Adb/VyWXnpp/rJnv/32qwe5xjPgGfAMdDgDdCPhueeeywUKDz/8cNvsYzffKBz04X3CFltumleQ9DEYP53xxWr0lLaLsZMgJoKEJSVhEih1Ml8WqUwE2SYTZ141Sk2OL6PJtfUtmjIH/PBMCK8EwJX5AACOJsd9IuIfaQt2UUF8s2bMCRedf5VVNfTvvvvuMGHChAa5CzwDrWSAnppw1VVXhQsvvDBcc801gYoVuu0YN25cOOSQQ/jfFlts0W3heTyegcU2Ax0vfBy7YdxXvD8WPm6SckpLJR3U2HU292m9ZEjhBD23tMwqqIjNhlV6yIjY9uGIZAV5pktyXfHZBL5hk1thZKxyUB960to+J6MkA3cEiloFBbtoM3vWA+GCc68gytqDnqIzceLEWr0rOpcBL1TwQoXOvZucaShlwAsVhtKrtXjFOmfOHC5QuOCCC0K7BQrLL79c+OD+u4c99poUlhw1UhKZ9kq0zyER9i3UU0ja1KiAUJBFEPUxzFYGw3jYAivs2Q568Kn31JAj+lGBwtme/Gdz7klMIoUPRhmONAdrS3oYRDl4WaZy6VsjjUu5vVChmBsfeQY8A54Bz4BnwDPgGVjcM0B/fGr33XdvSMPXvva1QP/88Az0dwa8UKG/M+z8ngHPgGdgEclA7woVaNLxJmdzIY3TgPuecVWtnBvoIQcOcoyhRws9jYGxMuBKMfW6UOHqWKhgeMs3McNN4XJkXTwVcsvXEgcc9tSSHxMzQa0fa9qSzyZ8LXFYp1X9itwQrCrugj8C1diyvIc8FHjqOIi/p6PCripmomjJXxO+ljh6ihc68tNDbgCjtiWfTfha4rBOq/oVuSFYVb4L/ghUY9vf75HHpj8RrjvhxrDg7dYehT1y5Mhw9tlnhyOOqC6Qoqn44RnwDHgGOpGB+fPnh9///vfhW9/6VnjkkUfaptxsi43Dhz78gbD5lhvLR27cD6bPYv0M5nHsW7moogSf0xpJ4YtZ0hEfYzLQjrM9cERk+0rMVCTPPKyJwyiVrtElH6wvctAIPDBhjjgAO/TJEn5KfDw/IWSo9cti1RGzFypwivzUDxmYNWtW+OEPfxjOP//88MYbb/SDh/6hpKKcL3zhC+Hwww8Po8xf5Owfb87qGfAMVGWg44WPm8XCx0PeHwsfc4ECrdR05DVXBuU1V9ZihqZTWlfZRBZhrNHgEzDYGtd40sOm3BfbrE84peNGHYlIz9BDl9rEaOYbwfwDWzXmYARv557mFTuMBLeQwIEXKqRMdEfHCxW8UKE73okexUBnwAsVBjrj7q9ZBu6///5w4oknhosuuqj9AoUVqEBhz7DnXjvH/19bUvdT2J/kSGT/pHIS874n768y0sgIQ3sd2exYiPohvRUXsUVd5k17OTJVe4qsICcV6eKp4IJFGZt9kIzoBF3mIjFr1EBQhl+U4lM5ciPGxO2FCjFnfngdqQlxAABAAElEQVQGPAOeAc+AZ8Az4BnwDHgGPANdkwEvVOial8ID8Qx4BjwD3Z2BXhUqpCtnNXOyN0VbLMvpZIWNw8S6hBLlK3x6wzUc9MzTp0IFcg567pqBBoYLjOVpJLtSWEmufKJWUBlLPhpdqudSY22NTdObua2d9Wflhg+3h6d5k43FWg7q93T0YNeruBFfD3w5kQZkuhwmeHqKmXQ92PUYd51dnTy6Ij5RG5Dpcqh9idvY9BhzT/O1cRg+f4/Ie+Svd/4tXPVf08K8N+bxy9TsNGzYsHDGGWeEL33pS82grvcMeAY8A73OABUo/O53v+MChUcffbTX9mWDzeMNhHQj4eZbxBsJ03oQdwe8T9Ndgsp5FPsyTMI4JnxmLn9Zy2Oys6AIl6G1VeZmXGxrQOra8lM/uyPnAoIVsOWWUElm+mydOCw3g0QNcs4IyUlssBRT/G/WPfGJCn/wJypw0vzUkQzccMMN4Tvf+U6YPn16R/gGi2TNNdfk/dO//du/hRVWWGGwwnC/noHFKgNUoECFjyeffHJnCh83j4WPVKCwVXwyky7EaCWxeV3Esgl9amUBzWs3FvRooEtrpBJrqPJ6C9YoUXAjRiPJivSaIwaipzWbD+7HXsSrRPGYC1qCCEIaxbO9Wto+U2Y5kSYPjGMAiXUu3Mt99eVPVOAUdc3JCxW8UKFr3oweyIBmwAsVBjTd7qyHDNx3331coHDxxRe3XaCwAhUoHPC++AQFKVCQjRDte2j/InsY3Y6oCjsZ3d9QnLSniSBIsFdKU4AeRKqQIfkCMnUKsqwXPwltFSQkPxoFYkgQ7WQPGjPkrBBtsmVOMAq/uiHjNF8EayhSHALSOcImtieecEaYN28+0VUekydPDlOnTq3UudAz4BnwDHgGPAOeAc+AZ8Az4BnwDHQ6A16o0OmMOp9nwDPgGVhEMzAwhQr2zmZzOc90C+mtLFRonaPPhQp85c/6KUTVxQNK5FCMe/BSSpeCq27aH7yI+tuzv0d6m+Hevkeen/OPcMUXrw5zX3mzZVfHH388P1q7ZQMHegY8A56BHjJABQq//e1vuUDhscce6wHZmor+wvGHPvLBsNnmG8l3o2SW9m70RSkNRMBdHeFLWYJTCR6j4snKbZ9wPC5hRF60gz8iJV7BoFfEln0oPMVBMWdMJgQbdOXW+iQs9CkglYEnAuDadiNc5bHJHJJXfqKCFyqkvHmnbxmg99WVV17JNxffddddfSPpUisqUjjqqKPC0UcfHVZZZZUujdLD8gwM7QzgyUxUoNCRwsdY8Pihj8QnM8UnNOFI618U1PYVTHpgCmsoradYUqnVvumY9TdzEC2WaOEVQ8hEn8hoKEcUsX9VIRayQ3yAMpJwFDsJ0XJXCMpyxA9eMYsogYtvFjK7kZMwHgQtTsKfqCCZ6ZqzFyp4oULXvBk9kAHNgBcqDGi63VlFBu69914uULjkkkvaL1BYcfmw3wF7xgKFSWHkkiPFm+5VeIfCexERYFvCI7MXSn+yifYu9J/aF/YxxEx6sgNA5ybDbMfAgk4GsENLUttXE24gb+A2vjXMQkyws9yMi3bAo9MoF4RxQdmQsGLDfRqCK7ZeqCDp8bNnwDPgGfAMeAY8A54Bz4BnwDPQHRnwQoXueB08Cs+AZ8Az0PUZaLlQYf+xrc2F7pfX62gFAy4+MArTLeBoQFh7ZQ6AFjn6VqhgA+r8Tf9gr2PGxcwlUKSBOTdtwUzAOvamJJUAMPfE2n7cPbFXhtVU2CxuxEzp6n2xQjP2puHVApoxI25/j9SmsGVFq7kmwt7k+6UnXw6XfeHq8Przr7ccy7//+7+HH/3oR4GesuCHZ8Az4BnoSwboRsJzzjmHCxQef/zxvlAUbOgvHB8cbyTcLP7FYzpo/eHPTXx4ipTl2PRBTy3WK4aRpfyIldnfJRzrFWf0ZCDD6D+q5dCObaIS6sTJtpDCloT0wye1AbdiRcUG4GpoSWt8Wk42ZLXw8TkHX5hHFiMG5Y0KL1RAJr3tawauueaacMIJJ4R77qm/GbCv3N1kt9xyy/ETFr7yla+EFVdcsZtC81g8A0M2A3gyExUodKLwkZ7MdPAhsUAhtnRgXbX94nqZ10VZTbNNwVZXcl6HsahGA+FidjqZtVdkBQ4Fizm8ZRuLZTLmgxPyVbKJRFkiFswBOVrwUEswIwdBYmJ3fCJkVKsHiKKtyLkRLoVg8rNnzQkXnHulAqqbO+64I0ycOLFa6dKOZsALFer3JpMmTQq33HJLR/PtZJ6BbsmAFyp0yyux+MUxe/bsVKBQtbfpTUZWjAUK+x74vrDn+3YOS45akvd1vO3A3oPJ4m6F9ydmjxK7GOnWJSJFKHLawqBn+gwRHFFbDMbZLNsrNUGSjbW1fQbpCXLhpHlAa2IgUVSQKuMTMMsYFzGMJDAJtFF7EYgi+8q8bA1q2MTWCxU4c37yDHgGPAOeAc+AZ8Az4BnwDHgGuiQDXqjQJS+Eh+EZ8Ax4Bro9Ay0VKhy+ddjigFKhQrqhHlfK4kxNt9fzTnzE0w5RCN1WqFCeTdWt+bioSXnrzY3RxaRXMff6lUgGNu4q5r7HTC6asacwet1pxtz3uJsx9zrUZGCZSdjZfFv2KuYURq87zZj7nmsKpRl7r8NNBs2Y+x73O+G1517nYoWXn3ol+WvWOfTQQ8NvfvObsOSSSzaDut4z4BnwDKQMzJs3LxUoPPHEE0ne186W48byjYRj4xMU7EGfifZzUXT4wlY+UfG5Sls4i7V9cELGbQlPGOilz2c66fZQPdmG4mNE2RZSVTJJxBBafoiVlckn5OBES0iaHLV8yj6VIulFLdjGPkniAV7LCXmUeaECZ8lPfcjAnXfeGb761a+Gm2++uQ/WvTehvQsVC+DfyJEjw+uvvx5ee+01/vevf/2r8LvRew+tWay88srh61//ejjyyCPDqFGjWjNylGfAM1DIAAofTznllI4UKGwZCx/pCQqb0RMUdFnEWgrHNE6rqyywrNLlEWbpc6TBnhD0AwOyFhEJ6cccMrBY9DMuG4isyAG8+MhYdktDJbIasQEP2hwzY9UgajX+JOD4IWc/aYLJHTlmHOtjDByGieVeL1RI+emGjhcqeKFCN7wPPYaBz4AXKgx8zhd3j7NmzeIChUsvvTTuDfJeoS95WXGlFcL+sUBhdypQwBMUIhHxMnOJH/sf8gXPAtF9CivUlvp6pDijEWl5DIIyJo4TvtSHUzIFBi3R2D6N+VCf2VYcI+4ypidusYwWqVP0Cf+s1tzZFIo+auVH49N8RaAXKkhK/OwZ8Ax4BjwDngHPgGfAM+AZ8Ax0Rwa8UKE7XgePwjPgGfAMdH0Guq5QwV6R62P2elWosPro8OmrPx492Ru45aJfVcEALiL2FFrZLl9wtD7AwNpCcUKjj2o7kVpdTdx8QVP8wGtV23rcrcRMHmxs8PiOSrOOoi77JnRjHsBRbMu2Ypf5M7qvcTfGTFeJia3sm3y1EnfZjiPj935f4662E6nVDWzcdp7VebGx4ZVqPd/VnODJrY2DpJLvrM+9vr5H6N3O7wimmvvym+HyL10dXnjgH5m6SW/vvfcOF198cRg9enQTpKs9A56BxT0DVKDw61//OtCNhE8++WTb6Ri3zWbxCQofDJuO3bBhDeNVI368NX7eRg1/ZPJJPldjJCTLWGCKIULPbQGfcRlDMvHBPewTVcRNlAEBuwKWBnrAJw3FRs/gJTlPQvUV3GWfcI5cCXdECXVsTF9llCjuql+IWR5lXqhAWfSjNxl49tlnwzHHHBPOPfdc8zvYG4ZqLO2hxo4dG7beeuuw3nrrhTFjxhTalVZaqdpQpW+//Xag2J5++unwzDPP8D/qP/roo2HGjBlc1NAjQS+VG2ywQTjttNPCwQcf3EtLh3sGFt8MoPCR9hWdeDLTVlT4+NEPhrH0ZCasc7TuaR+Zxjooa2A8i4DVgJLI2tl+4qniFkO4JxbAK/ngT0CCFRnFrVJ0iM30QcwilWdvwIIHLeTg1jbGWeBu4rsYBuJWHymWd8K9sx7wJyrgheqC1gsVvFChC96GHsIgZMALFQYh6YupS/r/rBNPPDFcfvnlxX1FH/Kx0sqxQOGgvcPue+7EBQqFfUrkwxgtXMhY9yYqlK1J9V6oaEfE9KP7It0PNWAIZjZDtk/2dAiH9g2W9KQrHJAZW+gTN2Gwx4otGJKMDIw8AVgsaLaCYUFOg/gvntgF/JCIDvDG1gsVJCV+9gx4BjwDngHPgGfAM+AZ8Ax4BrojA16o0B2vg0fhGfAMeAa6PgN9LlSgmdl7jM3FtcGedG8LFT4VCxWWMJPJlxiLN6LjgmMr87M3RhftqpNWj4e3GrtBjLt5zBR763G3xod8FNtq2xrf5ukdxdfGcjba+ntE8lOda9JV5KyPuRa2zIffyXrfEltP52rb7EO/CWCKamyZvdHWvkfeeuPtcPVXpoVn//K/ZcPa8Q477BCuuuqqQH8V2A/PgGfAM1DOAN1I+Ktf/YoLFJ566qmyutfjrbfZnG8ktAUKDV+Y0rekuscrrpn6xakq9btUHmVcEUMB6vesHGvCsQvrh5EFLIIQe4PV+Ng/86NHA/rJ4+RP6FVTFSMbih5fBBtuZjRyoiMw+0LLQiNPGJIxgzZskHzBbOY994eL/nAVhpXt3XffHSZMmFCpc+HikwH6C+jf//73w5QpUzpy0//w4cPDNttsE3bbbbew6667hl122SWsssoq/ZJQip3+yuef/vQn/nfrrbeGl19+uSO+9tlnn/DjH/84bLRR8QkxHSF3Es/AIpIB2lfQU92oQKETT2baauvNwoepQGEz+b3DultYH2UJTBkkjK6KvJbqCUsl68DDK22FPZFljFDzUkvcCa9euEnCZJdxzMYkIjMc0SxFWzTIeJUbDxoDeNDmmG1IzG/8aHLEr5ICw5EmR6nDc+IwUixeqMAvUBedvFDBCxW66O3ooQxgBrxQYQCTvZi6uueee7hA4Yorrkh7nL6mYuWVV4wFCnuFPfbaOYwYOYI2QYX9CPEW9yR5L8K6tFdiFIchojhmaG5ZSXyGIu3tqvwq0OI5GuUVZxqf4U2cBFBfOTryn4SqRowFg4QjvFpkGUOznIYEYglaFopc1KwQLiYs+kVYSBD59UIFJNFbz4BnwDPgGfAMeAY8A54Bz4BnoBsy4IUK3fAqeAyeAc+AZ2AIZKCtQoXezA83LKcra70x7gFr7xXWG6Vn/f7e8MBlD/VglFXLxicqUKECH3whMPYKnDSkv5UOZbZt1sNNy4225KDIV481Xt7RwJYwtuhWxEyWjb4NX023er5wAIdi3DRuhkdbGzOZgga0GktTPsWVm3o7OIBDsayeo2GtyjWpQQNaNWnKZ6htt+e44Uws6rGGsSpuS2PibonPUNtu9XxBbh3K7w/Z1r4XGR5tF8H3yIK3F4Trjr8xPH7jkzZ9Pfa33HLLMG3atLD22mv3iHOlZ8AzsPhkgP4iORUonHrqqaEjBQrv3oJvJNxk7Aa8rvHns350p8/qOLZ9ZDt9cRsFVX2iyfLIYPZ9pluQMzf8UUsk5J1b1urJyKKS/qPD4qw/VQuOeCEAG8mScXbGMsYLOTTA8pj9K1Hio/iAzrokY04+sTIhiYsGxpaeqHDh+VdmkoqeFypUJGUxE82ePTt8+tOfDjNnzmxr5ksvvXTYa6+9wkEHHRT233//sOqqq7bF11fjBQsWhNtuuy1ceuml4ZJLLmn7847mddJJJ4Wjjz46UAGGH54Bz4BkoPNPZtqc9xWbbrYhLbZp3SVvae2FXIQSCOl17eM1Ma2Dui6yfcYwmwDZPsENDyvoRP7ArTYWLzj4yS3sgQUHy5mHo0jcwFPLNvGkMJKwuiA3enBLeNYux87zMIyFcTSELTuCR/JBCj6JZvasOf5EBSSpC1ovVPBChS54G3oIg5ABL1QYhKQvJi7p2gA9QeHKK6+s3KP0Jg0rr7JiOOBD8QkK79spjBwxMu41sOGgfQfvPJgO+xgjKvhO+ohGH/sWYdH9ihKYbUvCp7g5BD4l3xYPHPxwpOJM8YLI+jiWIGIjvHZuhBZ+xMgSOrEdeKhVmhSzuM1yMSI+QaKFXNxDR/zaB4B8kEjlEE85/vQwb958DBvayZMnh6lTpzbIXeAZ8Ax4BjwDngHPgGfAM+AZ8Ax4BvojA16o0B9ZdU7PgGfAM7AIZmBAChVQpED5K11UazuluDeaiWTQ60KFq7RQoSoYyy/XCatQ7cta8EPuLaxHpxbYX3G36KPluFvk63HerShb8IOUWWgttQXBsBbchqIFPy3nmsJoga+NaMW0RR8tx90i30DEjZfahlTl952F74SbTrml5eIp4lh//fXDddddFzbZZJMqSpd5BjwDi0kGqEDhl7/8JRcoPP30023Pepv3xAKFQ/eNny0byJexxBg/zPgrVP1QS1+nQq4YOLdfqua+fnEqdHGrh09IyGUMcdaDVQwhFxxsDYYiZarcQlvJrWFEtIkJFrIlhU+RIs7Yyg+DlCZx8Dg6hByMxFXkU9YUXDnXagk7Q+iFCsiqt1UZWLhwYTjttNPCCSecEOhzoq/HpptuGr74xS+GI444Iqywwgp9pekXO/pduuWWW/ipCBdffHGgpy/09aCnQpxzzjlhzJgxfaVwO8/AIpEB+rz49a9/3bknM72bChT2DVSgkNa/uJalfswaVksrswuolVf1aWnM8rzOYmmlFybraaQHxUGOOB6SkS2UaLNMOARgcQVutU+8RG4Ossv4rGMZ6QgbQdAAW5aDkvTAQCYUyhAbxMJygNguDiggPWbPeiAWKlyBYWV7xx13hIkTJ1bqXNjZDHihghcqdPYd5WxDJQNeqDBUXqmhE+df/vIXLlCgp/NW7Rl6MxMqUDjw4H1igUJ8gsIILfIu7TWIDzuZ5C9vN9Jeh3FmHwIsQ2mfwoHRPkcYBc9C0RhbSJkj4mHTCAEfsyUcj8Rh7BqMyjga4tWosj/LI33WAast4sAcGQkMG8gJerRJZbDMBcIIiCqecFlOYi9UoCz44RnwDHgGPAOeAc+AZ8Az4BnwDHRLBrxQoVteCY/DM+AZ8Ax0eQYGpFChv3Ng7xSOV/BmnXtfyzcF8xMVYqGCvUi4hC2s6GvsfCVRjW18feQz1yiDDc/j1oQOQL491wOXa/I0FPNdG3N8f97+ozvDjN/M1iQ2b1ZfffVwzTXXhPHjxzcHO8Iz4BlYpDLw1ltvpQKFZ555pu25vXv8luGQeCPhRpuur990UhM/mMzaaT+/oENrAyCcmMFeR8pFTeaKWJWDAzq0Wc6GBq9+kr10hM/yJoDaGl1UKYuJCR4pTvWZRSQo8WCc58UeDTeZp/mU5JQsjoGNqM8ucNIx+WAgafmYOeP+cNH5V2FY2foTFSrTssgLX3zxRS4soKcv9fXYfvvtw7HHHhsOPPDAMGzYsL7SDJjdk08+yYUZVLg1d+7cPvldaaWV+AZtemKEH56BxS0DeDLTKaecEjpW+PjRD4ZNxsYnKNCBtU773OgGgNfAJhhS05HWUlk5lbckzwuprtdlWyKin7yuNu4d2BsbQpfhYsduiErnIWA+C3eFTmxoTSccGJQjDkWcMpK4y3L2wngxyhZCm8aiJgdiIg2PuWti9ycqcIq65uSFCl6o0DVvRg9kQDPghQoDmu5F2tldd92VChTanegqq67EBQrv3TM+QWHkCN6w2L0G+LEnYh3vQfgENbfYf6AVZbRgQXkvlOUgST5gkBRkK/5EJYQZZseNfaKBXbJhOsEKtfbVJ/DqFtKcH7UHH2LPvjRm9p39sJ5IpaMNk4mUVaqPWuYlNRyRLP534vFn+BMVOHt+8gx4BjwDngHPgGfAM+AZ8Ax4BrohA16o0A2vgsfgGfAMeAaGQAY6UqiAG/HzNbRBnXnfChUoZJrAEvKH5jEnOxM7P+itjLDN5Jav1X70Yd2wCzolOWlr4raG5K8qvioZYemATka9Opvrp2zHVHTiuBFYjLvKB9RkafVVcisr42ncy6MubpGTs5pckx8bC+K2MsI0kxOmt0f0Yd2wCzolOWlr4raG5LcqvioZYemATka9OtfluiHuKh82bquvkltZmzGTeV3czd4jM86ZHW7/nzuLL1YPGVt++eXD5ZdfHnbbbbceUK7yDHgGFpUMUIHCL37xi/Dtb387/PWvf217WuMnjAsHxxsJN95kfeYqfLFZ/iCLiLLejomAP0qjnXykxrMIlJsbFmW71r945nCIW8jhTbmTMMWYcQQRvcgyR46jODcmJSsyUyLjQUXgQVvkgP+oTTExrxKRXMMq6GEnMQiY4uRYjS09UcELFSRLfs4ZmDNnTqAb7enG/b4ckyZNCt/4xjfCXnvt1RfzQbd5/vnnw/e+971w5plnhjfeeKPX8VAx+sknnxy+9rWvxf//sJvHXlO5gWdgSGSAChTOPvtsfjJTpwof5clM6/P8edkyaxfWPSSH1zezHpIc66NdowVPa6Eg8lmW6YwFRiwYZxZWrKXwkVF5Dbc+CvZpHlFK67IaZ9+Zo4o3T1MsG+yimDUV3GU5nNt51PbFnYlZHEGMudw7c0644LwrbegNfX+iQkNK+k3ghQpeqNBvby4n7uoMeKFCV788QyK4O++8M0yZMoX/sE27Aa+62spSoLCHFCjU7TWsH+xvqLV4YGj/AYxs7GRHIvuv+r0Q7KllbhhAQdsb8pk3ONCwHIPkm3mSFJ0CRxGbiBNW9nbkWEQJQXGo0MZU5ION2AMPLtIW8cLO5+yISRhHNDp5cHmhguTYz54Bz4BnwDPgGfAMeAY8A54Bz0B3ZMALFbrjdfAoPAOeAc9A12fACxVGh09dGZ+oYF6p8m0ruABoIDXdbJl7Ai1z6C3jiQf6OjkDKchIbDF1cYMvOeixI9E2i5korG8aw0+dnDCc3HgzkOVvP+7MlnvsLcUkIzkXvUvcVbJkgwBN3BARphWfiavQyZa5JwDkEvC6+OrkbEdBRmKLqYu77A9+q1uJtlnMZGt90xh+6uSEGZLvkYq463ItUNE+ePnD4Y+n3hoWLlhI4qbHUkstFc477zz+q8dNwQ7wDHgGhmQGqEDh5z//ORcoPPvss23NgW6+fc+ErcIhh8YnKGw8hj9e5RQ/avO3uoU+HELPn9vxIwtj6KklmXyaEYAlrAa1iIBp5KjjZnviFnLyxLzsIQtTTEaUsCLLHIX4I12OSqgZr0TZG2IGD1rINTI1YE7LXZJz/DQXyLVNAoo+xlCM5Z3ghQryGvk5Z+CWW24JBxxwQHjllVeysMUePZ2J/pL6Pvvs06JFd8Oee+658K1vfSucddZZgW7E7u0xefLk8JOf/CQMHz68t6aO9wwMiQzQvoIKFKjwsRMFCthXUOEjL2NYO9OaJmtZOTmyvhmQAqrlWG8FDytyZddz24c/yLgt4csYGmc8jwSiDrmhdVmkCctInbeqkl3iY4lYQiZbgCiTH3LewM0WRg4AI4WuNo4UEuxVoGbiL8runfWAFyoUXrjBHXihghcqDO470L0PVga8UGGwMj/0/VIxIRUoXHvttW1PZrVYoHDQh98f3rvnjmHEiBG0NeGjsO9IG5fsLu1togh9tEAV9jRMLOTZhyBhhxb21JKsLBcqkheQPLDYYh9YG0ORI+EjhOcPE2oh49YoKD7ND/eEvhAz4rQ4ZlAs0wNErrTP6oSRDqviqYCJ/r1Qwbwm3vUMeAY8A54Bz4BnwDPgGfAMeAYGPQNeqDDoL4EH4BnwDHgGhkYGOlKo0GVT7fUTFXooVOALiphfulAYBfaO7YK88YbuAge4mCKTWAxu6LYyuv6Jw/4FUCMuhWQ06GZ3fLEVfPaRBkUIDBOSO1XxQUaAvsZdZ1eaWA7G/CVUxF3gyMjCzfMW05u4bTbgr6f5Nou7lqMXcdu5+HtEE1d4oXKWc6/0HlWzuvdCnbwq3wXX5nUsv05P/OmpcN3xN4YFby8wqPoufXH0s5/9LHzqU5+qB7nGM+AZGHIZoC8aL7300vDFL34xdKJAYfy247hAYcON1ku5SJ9LscOfRSpIn0sY6xejZFjAGTnrdMxmSRctwKOe05eoUICXSaIPyKOdcKmCcMqlmoxNuuwvY8iebJOxCCBTcZo3y+VUtmCOyMNytOChNv6jU+JSAjvmfqWciYiBD+GKaOkoeQgzZ9zvT1RAkrwNN998c/jABz7Q66cIrLPOOvyX1OmGSPv/D4tKSh977LHw1a9+NVxyySW9ntInP/nJ8Mtf/jIMGzas17Zu4Bno1gx08slMKHz8SCx83FCfzESLFdYtyoGsXdwzfclOYR3MQFbSOmt5xIL4SMoa1cuouLZHvfwkroI96wyAGI1/6WLdJcuILTeIj7QFW8WKhZyNP9GCO/Nyr4IT3GW9zC/bc3gaB7AIIYdX9Jvk5Df+80IFZKw7Wi9U8EKF7ngnehQDnQEvVBjojA99f3/+85+5QGHatGltT2a11VcJHzokFijssWOhYFv2FrQjir20/Ugd9os9Cw0sjsdp06HmtPcQBZ3jQXsR6clI+sRpeUUXgfQDAxnCgFuoVKjc4iDr4FPkzM1dyMVa5IqJTdQmhXA14skh4xQPnynmyECyxKWUacxOzRwJT37lhxQ5BsUygsRGN+X408O8efMTttyh4vypU6eWxT72DHgGPAOeAc+AZ8Az4BnwDHgGPAP9kgEvVOiXtDqpZ8Az4BlY9DLghQqjw/8TCxXKB25qLl9ETDgASJCvH8YChqygXsE+GaMjt0BXYUhTkFsf0ZxuHCiJmBTeK22hJGTZuJdxNxLkv6Rf6Zuj6znuWruOxN1zriUlJimmy6+FjQFz0bbXcfcy1+S64CP59/eIpoLefPkwrx0LW853398jZT8IBmEVXj+N72/3/G+4+v+dHt7+V2t/CZh+57/3ve+Fr3zlK6D31jPgGRiiGaAvMOnG2hNPPDHMnj27rVnQZ8OE7bYOhxwWbyTcUAoUCl+Qgj1+9vBnkX4Gpc8lkpsvO608mVp9K301JF5wJ96oYxnFwTFJKyYaHGNEwlEXfCqSZYI36uQP1tySHwNCLCSycthIfIqKIEQFLI+NHICMVF41THLylyZNfT1InuJjED9R4cLzrwSisr377rvDhAkTKnUuXHQycOedd4a99torvPbaay1PauTIkeHLX/5yOOGEE8Lo0aNbthuqwOnTp4cjjzwyPPLII72awuc///lw5plnLpJFHL1KhIOHfAbefPPN8Itf/KJjT2Yav218MtNh+4WNNhrDueH1Stcp7pMU6yDkSaFrHWPYnE95nZM1L8FNRzAiwLJII2tL7GkpRQwNGLUhKIg0FBnG1VjckKVohJb71qaur3Qai3AwZzzpyFIXeMGJlpTos23iIAWbsl67BBYh26VuhEY5q8z8iCv+80KFnKdu6HmhghcqdMP70GMY+Ax4ocLA53yoerz99tu5QOG6665rewpUoHDwRz4Qdtt9B36CAhFi38F99cAy3WJgNyNbC+wvaJuhAGto+GQbIpiCD7t3sf4Ktsodm2TLfTUwvjMd9jzwmbGCqZMDRwHovASa5gj77EttogDxUT6gzzLiJA3w6KgfGpJPGPJQ0CxSubVnNghU74UKOa/e8wx4BjwDngHPgGfAM+AZ8Ax4BgY/A16oMPivgUfgGfAMeAaGRAa8UCEWKlxxeO1rRTcA0lG4IEiCdPMzXVkkQYtHsot4c0Gyyhq+SWcvXlZhC7IYstxyXYqbp6K3TjfxXeYr3AnexLavcdfapbh7m2uahc6XrwAXZlUcRFhlzoqoyhHi7tx7hNy09jrBN1n4e6S1nFGu0sEmajcA7xHya1+nfzz8z3DFl64Oc19+M4XUrHPssceGU045xW+qa5Yo13sGujADCxcuTAUK9957b1sR0uf/tttTgcJ+gZ6gwJ8tuh+xnzNpixLXbu4Dg81LHNv1S1EkTEeBT/cAVsYMiVfMoE8tCIHDXoL9RxuWixIqYhJ7NeIxS6NcWj5ndeEzlnR0IAbyYecnFEkiYEKQIp7KevgUeZGL/YgFKYiF20a5cIuc+orgNutmzZgTvFCBcrN4HzNmzAh77rlneOWVV1pOBBWv0JMCxo0b17LNogCkG7WnTJkSTjvttDB/fv1flizPlZ5o84Mf/KAs9rFnYEhkgN73P//5z7lA4W9/+1tbMdO+YsJ28clMuq9gMl2b0joahViu7DpJWFkj2UrWQBbKmLsGQHyZBxhaf0kqGsB5lPDv8P8lM4pkAlU78EjLXFFvYyeN2GTbsj/BKDHjq/uE44N8pJhLvGoKBsRSboknyUwf/KwnL5mIVSyHLA4QB4UDPjKi/+6d+UC44LyeCyDvuOOOMHHixMTtnf7LgBcqeKFC/727nLmbM+CFCt386nRHbLfddhv/Pw0VYrd7rP6uVblA4b17xicoDBsu+wTdN6R9QnTCIto7UA/63OEwgLd7DcQHHY1b6qshsKk1PlMsCInjkuDSfqjgr6yLDBU28KUhSBNx8Jfmx9ykBo9A+cx7K1IJGpxlf4lLQhMfSsM2KicRYzkO4RUZK0QLrDghdfBCBU6DnzwDngHPgGfAM+AZ8Ax4BjwDnoEuyYAXKnTJC+FheAY8A56Bbs9ApwsV6EKbvXka86fraPYefcg73ZL/2efdHx647KGWqJddvbVCBSLDhUcmxmTMBcKWHCY7ZmxqglwWfDe1olzLzdcNdsk/rnC2QEaQXtnFW/7TPeO981MddyQjPqbqHZ8JpOlEq303NUu5JmQh3zkJzUksItkxo9VU9tuNuxAzeUj++y/X9IJmN73zUz1ffY9Q/H3+nWweR/bNjujU0gE7AhfyHZPwytOvhMuPujq89tzrLXER6HOf+xz/BeDhw4e3bONAz4BnYPAyQAUKF110UTjppJPCfffd11Yg9Hmy/Q7vDh+OT1DYYMN1dW3Uzxb9GLOfMyzSz0X78YgvQhEMxvbLVMiAoZa4LT8CADf84RMV2Dou5o5g6IEXX6wlr+gk3/DHllmd9MmArBWMFnRsBh0bCBG4gc+tsCJWGqHPrQhEpn2L4X6KNVpIADw9GwvhvFCBsrB4Hw8++GDYddddw4svvthSImhPQMWM3/zmN9NfymzJcBED/fnPfw5HHHFEeOKJJ1qe2XHHHRdOPvnklvEO9AwMdgaoQOGss84K3/nOdwJdz2nnoH3FtttvEw75WMWTmXTNwjpIfswypmtgkui6ltdGxIW1Mo3t2pvMaV2kga6oKoetSoUi6miM9brMS2PmIlwJJMOyrR3bvrpTjjJXDAHRFvzAh+gRXY4FPMDxVOOAW8SezciJ+OFWFWIkNuhrywhgmdcLFWw6u6HvhQpeqNAN70OPYeAz4IUKA5/zoeLxlltu4SduXn/99W2H/K41VgsHf1SeoJCuG/O+AJuDvCchZ2lfwgNxz7sS3lfImFWycUl7EisDKnEpljcxUZmG1OexkANP9mWfYgMcG+m+x8jIUKTSY1WjHv6tPzZQc/Jd0AlFkulQfMUBjyMptbCDD56JGmBOghSPwJuwM4fGkznEGfwJg5y9UMFmw/ueAc+AZ8Az4BnwDHgGPAOeAc/AYGfACxUG+xVw/54Bz4BnYIhkoD8KFWjqxRtzczJwc3KWdK6HC32dLFSg6Ggu4O5MtOmu+87QdSVLp+fYab7OJs3fI33JZ6df007z1c2pb37q3yNLhNdfeD1c8cVrwktPvlzntEFOX3D+7ne/C6NGjWrQucAz4BnojgxQgcKFF17IBQr3339/W0HRZ8jEHd8T/9LxvmHMButkLnwBSt+K2r4i7P4lf3Gav0zNRPxVaNrvsJ3yAQMutMlhBICbTLI+960MfNRCzi1NQYnAJ9gcSJUeMssndmqdOJUn02V/SF40gW/w5jazJlm0Q58o0hfQFT7IGtzUYUg5NnXhhQo514tj79lnnw077bRT+Otf/9ry9L/xjW/wX99s2WARBj755JNh/PjxvXoSBT1VgZ6u4IdnoJszMHfuXC5Q+O53v9uRAoXtJm4TPvKx/cL6VPhIR3nt0nFa5ywk6nglSzbSoWXNypuvi2pHzmFrYslcyiQwjiStqYTXA7GyLp4yRv1wY/tiKHaN8kZewVCsdCA+jQ5ClmffKlZBIcbEkRmgFysGJD8kU9exozbEyz/SJjvCMiYWKsyKT1Q415+oYHMzmH0vVPBChcF8/7nvwcuAFyoMXu671fPNN9/M/w934403th3iGmuuFj586AfDrrtNDMNG6B+2waahtE+wew30dZvCcUBmgyrseUp8wPG+IxHBOW9ZhJfOvDcRC+vH9kVL2xt2RB3Z0yh3csFA68f2wSK2NKr0kTjVNlMU8HmnRjzCbecLmfWD+GFb8F/hp4GjHJu45bMXKphkeNcz4BnwDHgGPAOeAc+AZ8Az4BkY9Ax4ocKgvwQegGfAM+AZGBoZGIhCBcoELrR1Y6HCJy//WKGwQuJtfDJEvphINyo3HuW5AU83F+Lga5DpQiQ6WQ+cbY05i8FLgwK3JtnKCJPx1X4sP7Dx793TH71PRyfjrouvTl4IRCOyMZMoxV1S4H0nZu3luy4+K0ccVTFTDKXwKuPuRK7JF2Kpis/KLLaVuMFLdpanE3GD2/La+OrkvYm7kYM84Oj/9wh5knmaX7Aoe/P/3gxXfXlaeH7OCwimabvnnnuGSy65JCy33HJNsQ7wDHgGBi4DVKBwwQUXcIHCnDlz2nJMn1k77PSe8JHD9uMCBfms1a858ZEVW3wBSs5k7RNloc9KCcfiRcwkrIQOrViQj3hEQnxWq0RsxB1jsl7xgtC4eKA2asQw8W9t8xpucWRKMTAFn6wNx5dVSV/EZADmyC2JJYxkxyJ1Bp+Wq2CvMVkuocyk4MhzEB2bZmWYec/94aI/XMVx1J3uvvvuMGHChDq1y4doBl599dUwadKkXj99ZcSIEeFXv/pVoJsfF+fjhRdeCHvttVe49957e5WGYcOG8ef2wQcf3Cs7B3sGBiIDVKAwderUQAUKf//739tySfsKejITFSjQk5lo/bHrGgtYRm6wRkmrEmpUleUsIDERRjssaeU1kbVQMp4NyCJzCgWd4wEuYcqmkAsKZ8yFcfFk8WUMjZOesBSDlfFITplXMAoVGw5d5WpDvLABDca5VW4iMxzQwy7p1IU2HDz32RlRMEkyow5ks2fN8UKFQmYGd+CFCl6oMLjvQPc+WBnwQoXBynz3+f3Tn/7EBQo33XRT28Gtudbq4cMf3TfsuvvEMHz4MN5/5L2C0PPeIglpC5EH0tVdkIqxf7DBwcbqICMcmypvlgsh3AGjbsQqDmicbYhNjiRjjAAhA6ciucFcaGD1sCEh+bIHdGhZp6DCXGEpYQiM+NQR/GFMANgnr2xrIoCfEgdbso4NxDMcsOcQvFBBE+GNZ8Az4BnwDHgGPAOeAc+AZ8Az0BUZ8EKFrngZPAjPgGfAM9D9Geh0oUKzGeOaWvmG7WZ2vdHPOve+8MBlD7VksuzqowMVKtCNzojJXlBMN+zzdUG9esjMxZuM4aw5B5DUNuez6EpuCIkNyY193IxtZb25mZv8Zg4a2QNxV+fAIhlBp1L+ityZD9PpTdwybXDUxZ31dXkoxK1TK3L7e4RyZF8b/H6Yt56mEfkeSu8Rnp3G30Lc/fAemTd3Xrj2mOnhr3f9TeNo3my33Xbh6quvDquuumpzsCM8A56Bfs0AFSj84Q9/4AKFBx54oC1ftE7uuPP4VKAg6yhRyheh/CkbT/jik53pR2/+TCYswkhfjRbX5DKHwvFZz+aRJNNID3omo6gUQE3WEVmU8I+NpYxRmJJYe/ASExFhXMSoc4ZIHxLg0DINThoX4qOWjirbSr9Awg4g5oCQo06kAhEdn/WUTGOHRLO8UIFeisXuWLBgQdhvv/3Ctdde26e50832P/3pT8PnPve5PtkPdSN6EgUVKTz0UGv/H1ie7zLLLBPopqFtt922rPKxZ2BQMvDGG2+kAoXnnnuurRhoX0FPZjr08P3DmPXlyUy04mAt0h6vVywjb3aN0oUKeFanxUvAVTrmTYSEi7TGrqpftsFYaOJIHRmaBl6KHdzAM6jBv0qVrOhLdOChUeoTvySIQUnOINLJYeXo51bAOp3MV+ImMsSl9CAXP0QQ47eYjGPj4IUKkrJuOXuhghcqdMt70eMY2Ax4ocLA5rsbvf3xj3/kAgVq2z3WXOtd8Ymb8QkK790hDI//H0gH7wbK+wZsmGi/oAdEbKFy3keQHvba5yYb0DDvh0yfaRIusolA8dzoviV5IuusjwYyKvKLpcoioIoX7Ml9ZMp9w6fCKj/Yn8EfBZMiQl8NrT3siBp94rC2aZzswcDAZCfhiY7PekpzQfyxPfGEM8K8efOJuvKYPHky/39EpdKFngHPgGfAM+AZ8Ax4BjwDngHPgGegwxnwQoUOJ9TpPAOeAc/AopqBwSpUoHzipvRO57ZvhQq9jaLZjczmgmOirrKxuCo9GVtMIutDp47fUpV91dlYXCsY66O3/Tp+y2PjIXmdjeKoqXwDlnmsj97262IAT5WvKhuLq9ITn8WAvy9tHb/lKvuqs7G4VjDWR2/7dfyWx8ZD8jobi6vCWL3l70u/kX/hvIVh+jdvCo/f8ETLhJtvvnmYNm1aWHfddVu2caBnwDPQuQzQzcUoUHjwwQfbIqYbCXeaNIH/0vGYMWvnT3f96KEvO+nLTx7GU/oi1Hw0pS8xYyRJT/3MluWWw0ResIM/0idyioMFbAUxiaztEuqVZAmDDlvqieKg+JizyJHh1RzWH5wwDfkEfSZJXkUkCOaA75JNjt34T8wRnOxix/aJh0VGbuJQqGAgjy35mzVjjj9RQV+Hxan5yle+Es4444y2pkyfIcRx9NFHt8Uz1IyfeOKJ8L73vS88+eSTbYW+9tprB3payRprrNEWjxt7BtrJABUoUNHR9773vdCJAoUddhofPhoLFNbXAgWKDWsnrZS0BMmalNe5FD+vS2zAIsLiAAeNiScd2pX108gVULAzhLXygp3wCbcorJ2NgWMysUBn8cm9dhge+4jaYgv2EZBRJg74Azi24KhrCYo4CjFTFImv1GcjVRMGMdt5EEY5Zs96ID5R4QqW1J3uuOOOMHHixDq1yzuYAS9U8EKFDr6dnGoIZcALFYbQi9XhUOnJCVOmTOGi6Hap11r7XfEPWuwbdtltYhgWn6DAh9kv0FYA+wm0FkN97DsYaWwZx/okTFzQoU37GosnJfYi3AoP/PEoDpQ9XpnPepImHDpwBh9qCN/GHSOLcnihkNCPreFI0qQ3DuGTnXCmsq3CiBfc0hdFniGRKJi6xk/CUEgqZ6jtkynp5URAoYutFyrkvHrPM+AZ8Ax4BjwDngHPgGfAM+AZGPwMeKHC4L8GHoFnwDPgGRgSGRjoQgVKil5vq75PvANZ632hwuEUlfFsbx7mq4EV9zSXMGxdJVNaome1xRiXdUmB3ECLiauJG3YFd4VBZIStlUNm1VZvA4lYwO1N//BtoUxheWBIIMgtX4OxCqrsSGXk6NqYLJ2Nz2KsHPhC3CAmJWKmfpSTyopIXBDA1oIgY7DhsBjVUYP4bMxWbqD+HkEybC5NvtEt5xJmyDWNLcbKgWUX8ANiNgQitlFOKsCSxgpgG7+mWfhOuPl7t4U5l7R+w/N6663HxQqbbbZZYveOZ8Az0L8ZoAKF8847L5x88sl9/gveiFAKFLaNf+l4v7AeFSjwR0L66jJ9jFCHdOmLykiALzX5c4bHYMWXmDJObJEAnzjUSfYwYw5BwI/Fk3c6xA59FrGmyBf1/FPC2c9T6AXC84MP8SPcJINZ9lHkBYCkGaOxwZh1ZU44z55hT62YouVIQJAMkCtScJ9apUUHnDBmNfgVTLaz7vFCBeRocWnPP//8cNhhh3VsuvS5dNxxx3WMr5uJ6AkK9CQFeqJCJ45ddtkl3HjjjWHEiBGdoHMOz0DLGfjXv/6VChSef/75lu2qgIXCRxQoYKlL6020pDWIGiUpr1OsZ4Ag1JQtCn21T0SEIO4MAqIgs/raPlsSF3XKrdBaW0YRWEIu+RMOwYgtnzVOcSE5EYySFKDCnVGqZDF02QCx1bXiR/DMqS4LfZNHURs/JIh6ltt5GGIvVJD8dsvZCxW8UKFb3osex8BmwAsVBjbf3eCN/p+CChRuvvnmtsNZe501uEBh1/dOjJeqqUAh7QjQpV0S75cq9xAC5zjytkLwJGQb7qQe81ouNgY28qUIUp+UKuUWfbHkUZSLlGRWH+VZEfs6iI2NQcQZCBijkthyiTDZMZ/EmeA8tCNMo9HWRC251gAQL/wkNu2kWcexsnIn4xSRJyQ4Buh8ok6GXqhAr4MfngHPgGfAM+AZ8Ax4BjwDngHPQPdkwAsVuue18Eg8A54Bz0BXZ6CvhQq4+EZfgNsDcntHbgmS4MCWORIgdlrBWDz1e1+o8LEyRRzHeZkLgwwoTlUwemmxgkBE6WqjQZQTUvZjoLVd5qgkbxI3TaLGzsorISYBVTFTTFVyO4m6uCv9FQybx13JYWImuqr4WorbxoJ+zXwLLmlQFRg4atScJ4tpwmGgqVuX66bv7bqYS/KqkGzcfc51yQ8mVOkPSmpr7Ky8ioP0ZIqjz3GDwLaRuJKvhKl5j9z507vDPb+aZcE99ldbbbVw9dVXh2233bZHnCs9A56B9jJABQrnnnsuFyg8/PDD7ZFF613iF80fOXTfWKCwFnPljw350OJzFOIjDHrskUjBWgWIXgawoc8i7qtxltPHVBqluZAseTTqDI1aHogSchoV+JiHaDNJwlKHf6RlVIKlToGvYGs4sy3FRaNSHCJKXI0Y64+tlaeRT8K2+NxnN3FIuYMPdU0BScQlBeeaKFROKH6iwvlXJdOqDv3V9wkTJlSpXDbEMvDII4/w2v3aa691NPJjjz02nHrqqR3l7Day2bNnh7333ju88MILHQ3tmGOOCd/+9rc7yulknoG6DFCBwk9+8pNw2mmntf1epmsrO++ybfjox/YP662/tll7xDvWaF65sC5FVVrJIBMAKwpYyMnG9jE5lpFOOrzyQZYwWA9JoErqqQ1LbZ8w/CNY4HgkIjIRe+BUDiwDGMNIjR1SUSSq6Bv9RnsQi21GEgf98EntTb+CE9zMCFuiLfVZpPlgLAnoACd0SRmjQF87s2fOCRecd6XY1Zz9iQo1iekHsRcqeKFCP7ytnHIIZMALFYbAi9ShEK+//nouULj11lvbZlxn3TVjgcJ+8QkK24Vhw4blNT7vNgp7B+wBsCehAHjPgb0BxhoZi+NJ8AJK0CRXcLJhhdiQTA240ZPsc0SRYyIsexIm28d8lIuGhLSxgyc5FLoUgNVLH2QCET5xXYgjixjYyEMA5dK4WEJ9BadWFcmzwZOKDsSW/YiQbQpCxUZZ5hfmE48/I8ybN5/5qk6TJ08OU6dOrVK5zDPgGfAMeAY8A54Bz4BnwDPgGfAMdDwDXqjQ8ZQ6oWfAM+AZWDQz0Gqhwub7jy39YfF0uS3K5S5fXGSTTOU7f+29yzaLuMBGMnBYPS5I1uoL4DzobaHCJy5DoQLNKcedGOPEquLLGUjIUscgmLqCu2RRObQXKCuTWR13nbccVbVduvBKwTSLu5Yie+E5VcZdMduWcl3r1BDWzV4hlNOqmPqYa7rCPCDvkQ7HXZel/Oq1kGuG1DGZl6TctbkmXdXrUbbRcZW3HDOBWoi76nfd+utzri2J6ffxPTL7vPvC7T+8s/BraVgbusstt1y49NJLwx577NGgc4FnwDPQXgaoQOH3v/89FyjQjcXtHluOGxsO+/gBYdw28Uko+plY/GiUTzY62z2TxUDOMnDIBorDS5+NUcf9hNHooxAcdj4kU4vC54+aU0RqJx4gp5Hls30QJSx1jH/IJQ7hpb7lAEZkGSM4Pkc8tUU7kZCsKM/cmQsy4aF5inWSC7nks9ZPtoNvImIqEKqCeJkbfiLKCxVS1hb5zttvvx123HHHMGPGjKZzXX755cMGG2wQ6Ob8Vo+jjjoq/OAHP6jcp7bK0a24u+66K3zgAx8IL730UkshLrXUUmH8+PHh9ttvb4qnm4CmTZsW3ve+9zXFOsAz0NcMvP7666lA4R//+EdfadiO/l900q7bhY8eHgsU1osFCnEtwZojrUrioCA3XiEnES9Vul7xOgWcWcOwLjI+6bMfkTMrO9VeYc3TaNi6wJf8YD2V+RQwxif7Ihv6MXEDgpYhiRvS2EZZIT5VgYuGtp/AJMeA3QsLY5WQ+j1xs64GA0PLoaHlmHU+8EE2KVbijf/unfWAFyqkxA1+xwsVvFBh8N+FHsFgZMALFQYj6wPrc/r06VygcNttt7XtmAoUDj38AN7fyXcOstLrsh/5dUyeaL1Xj1lv9wOEpg2CgLBPgI1QkF4kSU4iY6cuWAYOliUDUMj+Aw4RE8MKsRpDBBcJE56wNJAf0BECoYheR7AjfSG+pCe5DKr1pKvDwJARTEIcVXwsFzc1cZCbaKsYNBwTCK19BCJeWHmhArLmrWfAM+AZ8Ax4BjwDngHPgGfAM9ANGfBChW54FTwGz4BnwDMwBDLQaqHCFgeMbZiNXCBbIt1fLNfR6BJb8Tbinu4/LnOUnTTTl/E07nWhwqWHVdE0yOyN6Lg42ADqMoGNmUIbinHzBdjyldsuyzPCsfkeirkeuu8RfnPjZejqti/vkUeufSzc9K1bwsIFC1ua26hRo/hm6oMPPrglvIM8A56BnjMwf/78VKDw6KOP9gxuQbtVLFD42BEHhq24QCF/yZm+qExrnnRof4UvI0vfWaZ1Pcljh63QIh6MFSgYUZbXK6y7aEFBrZpTT33nGFnPGJHxOBvQMB5kpz3q8A9aVuMkIBrBgPskBocSkSgeAoMOsozJNBaDvuI4FOmX+QpxqENCWjl7BQe3EofIoy/q5EDSmDlYKfiZM+4PF/kTFSQZi/j5uOOOC6ecckrTWY4YMYKfmkRFDQceeGC48cYbm9oA8JnPfCacddZZYfjw4RAN+fbmm28O+++/f3j11Vdbmsvo0aO5kHPnnXcOu+++e7jzzlgE2uRYZ511wn333RdWXHHFJkhXewZ6lwEqUPjxj38cTj/99NCRAoXdtucb2dZdj57MhMUnrzmy9pBGdLLcYP0rxo41DetSwRZQXcewTpJYOKUDPyJXTWwyxvpO0sJ6muLQmDX6IoYc0AEXFBD9pPgytwBJJwYKgTjZsLakrORTap6rsoBbQqZAREEYUILL+pGQMpPFVHGoO54MbJnPnOCPHBOfFyqkrHVFxwsVvFChK96IHsSAZ8ALFQY85QPm8LrrruMChVYKopsFRfs5KlDYeddtw7AlhkW47hF0cZe1n1hko0Fn7B3S+k/qeEAufT7T1oAU2GKQsDi2uohlpLgSKFlWyFkpVHRW32KIuHhk+G18Yk922kudHIOIFCAw9QMbauGzjBMdaHlkB2TJJjkGmQch6YhKpUROqAWFnYvQMIpJ1axIEw2L8owXoMLJAf3AEUfyTvBCBZsl73sGPAOeAc+AZ8Az4BnwDHgGPAODnQEvVBjsV8D9ewY8A56BIZKBdgoVMEVcJ6srSICe8M0wzfQNHHytji7r5eII+gvkD1z2EEGbHsuuPjp8osVCheyD/PVwWHUOKxs002dkh3oIwjquoIYa8DIEepLXYco2bY3hxDouEVoV4CVI4apvHaZs09sxxcHccGADqyCzaphYWDO9xXakjyCs4wpiq4aJhTXTW2xH+gjCOi4RWxXgJciAvEeSTwRhA0vK3LHqaPLUrc+E6SfcGOa/tSBjeujRzYg//elPw2c/+9keUK7yDHgGesoAFSj87ne/C9/61rdCbr4/CgAAQABJREFUJwoU6MkJhx1xUBi3tTxBgb+GjJsk++te+PJRN1DSRJwFauDAJxXxxQHk1qiAIXsVJCyLIDQc6otNUhCIR/AQ06jAB0XiKMWncraJxtYWJlaGvtBqrOxT0NDDllrIcig2ZnJKP9IyXvuMikbcGh7C0EFy5jYYgIt8DCSTFAv3WcJC5YEgFt3OmBMuPP/KLKjo3X333WHChAkVGhcNlQzcc889YYcddgj0WdPs+NGPfhS+8IUvMOzNN98MhxxySLjqqquamSX9YYcdFn7zm9+EkSNHJtlQ7dCTDqgY84033mhpCiussALniooU6HjuuefCdtttF5599tmm9p/+9KfD2Wef3RTnAM9AKxl47bXXUoHCiy++2IpJLYae+jGJChQ+tn9Yp1CgQCZ57YoLDP3wAamMRQidIPI6JesbMcWjZC9kyqYAi0v+oxA+MwfxUUxKymRysjL02d7wlM2gJ4YUcwkELsHwmU6aF4nDmlg8AxkLnMZtYsoY6tHcpGW5wUEOX/AjcJ4Jm+RcsYYoiVVbgagTNFFo/GazKCa5Fypo1rqm8UIFL1TomjejBzKgGfBChQFN94A4o/8vmTJlSvjzn//ctr91x6wdDqMnKMT9HV05lrVfFnVd2mVdhyda47VPa338aTiw1yAFq+NJZAavhsmcMIRWQZEDwiLGOgYefth3NqMAQK2xWGtSCxit2EcZ/VRM0srq+/Bh5q0iobRy+GfPjAIGgcMPzQQhQQZPbB2VxJZ0Qq2c6keAIjN97uqYfcARI0OYcvzpYd68+usIkydPDlOnTlW0N54Bz4BnwDPgGfAMeAY8A54Bz4BnoH8z4IUK/ZtfZ/cMeAY8A4tMBrqtUIESW1WsYK/FWX260MeviNwA3NFChXjNkC4b4tZi44a7hZNirYztrHEzDDmzB2zVroHPYtFXDmpgzqrCAODYKreRVN5zr7RFKnAqR0N8dXLrDH0TB2iLzgDU1uChKfhvpiejqviiTFXFPIi48Ww5oC1MAMLY9iImY1WMoy4+G0edf0tq8ZDX2TWL28TUQAVO6w8yAtfJQWRbE4elKL7RjYHBQ8p2MG6mJ6Oq+KJMVcXXRsSNZ8sBLWLAGK3hhgjQ/539XLjmq9PD26+/DVWPLT294dRTTw3HHHNMjzhXegY8A8UM0E3Dv/3tb7lA4bHHHisq+zDa+t2bh8M+Hp+gQAUKOOgLS/m2kT5m0mH3NejLHih/AQow9DROHMwbx2KkCtFmDInjSAUJyzwQGg44JD14iYGhgodYRMzOVhkvJBijBTWPo3GjnBDWR12/yA9eto7BIT5wiZzPDGW9ggpzIFtGNMYmHMLNKACjws6jtq+8FJz1T2IvVEByFt12wYIFYfvttw8zZsxoOsmqm+XffvvtQDc6XnjhhU3tAaAnMZx//vmBnrw0VI9LL700UNHFW2+91dIUVllllUA3EJWLeu66666w6667NuWhvdQNN9zAT2FoyaGDPAMVGaACBSo2oico/POf/6xAtC6iAoVd3juR9xVrr7NGXm9kIWGitBzFjl2fuK+uimtT9g85tUxJqkSofCorcCdwNiAz8BU4mNuQkkk8Etb0Cxw0m0azZMf2UW95mNjw0Rh64RJCyws9bIs2wDcGQhzZNushgz/4SnJxkFOkpg2vF+Qg4LlolFHGaqND3OTHn6igeeqSxgsVvFChS96KHsYAZ8ALFQY44f3o7tprr+UChTvuuKNtL+vFAoVDPx4LFHaNBQr40ovWdV7TZfHXLUDcaNCPjkyfoNhX2ICsjK1gY/Hsh6nF1GAgUEijbybNHnkIPm4FkO0jNg5gZuMDC8ka5NGgUs50YCvmwHLAv/Wd/VGPfCYJOjkO8k9RKwbcNEz9TFCwtxjYEyDZyYBtmF551BX7ZGyJ3wsVOGV+8gx4BjwDngHPgGfAM+AZ8Ax4BrokA16o0CUvhIfhGfAMeAa6PQNtFyrEq2Z04QzXUavma6+j1eEshjjKOKtv1OHSndzO27FCBZ2bvYjI84tuyjGwnPAIhQU0Ef6RUyt8hoN96B3KzEvclg8+ym2NH8uXTAz2+TkvhFf/9pqo4EeBq45dJay43orJjDqWrzI+w91K3InDekEcmoekstxJWBOT0RfisBzkBz5IHv/RYecoktLZcliV5bNyw53EhKUBnVrhMxw2vpQ/y5eclDo1fiwfWbzxzzfCS4+/Et54eW6Y+/Kb8d/c8OYr0s6N7cL5C8OoZZcMo5YbFZaMLf1besWlwsobrhRW2WjlsOy7RuvkNKfRb4+vATnlZFCn4jBzT9q6+dbMkf3DRzM+y2H9GHk5ZykudAwWIm6JD3FYRZOYXnzkn+HKL08Lc1+aa6167P/Xf/1X+O53vxv9VTns0dSVnoHFKgPz5s0L55xzTjjllFPC448/3vbct3nPFuFj8QkKW261aXEroR/YstbkL2nJIb6shAG+DI0fDfxByi1104JhbAgTD6xhRS71A6XBMRuISV7DjRjYR8KIoaElDQdBbYqBZPHAGK1IVR4NGuVsleYk+BihuCVG/hEUDXWeAkx8gk9GrIUscxXtEUu5VWqNQWKxOSN9sgFYhCk3PISOYqbQTCAzZ9wfLjq/57+W709UQAKHZvvjH/84HHnkkU2DHzduXLjzzjvD0ksv3YClYofPfOYz/KSEBmWNYO+99w6XXHJJWGaZZWoQ3Ss+99xzwyc/+cmWnkBBs1hjjTXC9OnTw1ZbbVU5Kbpx/KijjqrUWeEWW2wRZs2atUg8jcLOy/v9n4FXX301/M///E/47//+744UKOy2+w58I9va66zJwae1RhaRtI6k1Y6XSD7pZM0aCV3UYPmxa5nIdH0iaya19iyotFUw65KFwDkOihuxs0BPWZb9klmW80BCabBRXDRgnwV/BBYB5qXmiRs5YKQdKBAx5JaRoGF69kBzY2kOAD6LrcYbsUU7CFLEBW6iBp77cAO/4oRUfCDe2TPnhAvO6/lJTXSz5cSJE2HqbT9mwAsVvFChH99eTt3FGfBChS5+cVoM7eqrrw4nnngi//9Ziya1sDHrrxOvFx0Ydtpl23ipegndP0S4ruWyhstCj+WeQA37HBGKPfYDTKO2DXsDCQl7BDWUhlQGL13wqJ36E2iKrGDP0sST93VsoyeZB/ZNyq02KTYR85llkbiso3FyJUjFU6PxkR0Pi/5EJBjhUDxZikGRWx1ZLsSDljhxEJw8Jp3SW3tgyZHISWLiJA71i2BIe+LxZ/gTFVLyvOMZ8Ax4BjwDngHPgGfAM+AZ8AwMdga8UGGwXwH37xnwDHgGhkgGelOogGtiMjW9skaXUmvufcVFNHtzLGTEUZTbhAl3o75RDiuJTfSzz7s/PHDZQ1D12C67+ujwiUsOq8Qwm1A26KvmXIunG5IjQ60+6iwf8lwl40CUryEoFdT6qbEjfwsXLAy/+8gfwr9e+Fcl7drj1wz7//CDDTrEiJgJkGQ04GCok+Uyajy3EjfdpH3x568IC95e0EjQhmSJYUuEEUuNCCOXHhn/ScvjZUaGZVdbJqxEN97Hf3QD/jKr5Bu7amOOsSAPNqxafJe8R6jw4Ll7nwt/vfNv4Zk7nw3/fPylwmto59JKf9Tyo7hgYdVNVg5rjV8rrD1hTc4xclPOB+R13GV8wlW8t1vBtoRhUPRkfJTtmsYNjhSwdKrsytzJxPh/5a+vhiv/89rw2t+1sCiB6jv015jPOuusMGLEiHqQazwDi2kGqEDhN7/5DRcoPPHEE21n4d3jtwyHf+KgsEUsUKB1kL9i1M+BvA+KUl0800dECYtAYM+4aENtktkFWIm0Kfkmf8SYtExvZQUqHYiJ+IRBYjAGmAtj1AvJrBx9tMAKb54TjYERF4g9W0AvthJROVaLsX2wEHe1XPl0fsCgJXtVUS/1i3qTs+SQ0XTiIyFsHJGY/qMnKnihAhK36LWvvPJK2HjjjZveuEzFCX/5y1/ClltuWZuEhQsXcsHDmWeeWYspK3bZZZdw5ZVXhuWXX76s6trxL37xi/D5z38+UHFGK8e6664brr/++rDppvFzuIfjgAMOCFdccUUPCFHRzeatFJY0JXLAYpEBKlD44Q9/yAUKL70U/3+qjYOeoPDePXYMhx5+QFhrnXcJU1pHlFjXDixIqub1htcaK4gmPEwcERH7jCO6JEdf9AXuvAiSRaU9M4JXORnMeBHYdRN4BAAXhCzjKEZm4HkLawHDeoDInjA6D4HrOcusvfTZiHGIBaakzzLjhwCqiAjAIYqtyBpathM426kpN+QrMcVOGkep/HCb5PABGx3PnhULFc71QgWkZbBbL1TwQoXBfg+6/8HJgBcqDE7e2/VK6zYKFOipbO0e62+wbqlAAQs6LfNY9bHXkDGkvPYnTI4EdrRrIDXvHkybkCxLI/Gn5GKjgwwxMVF8ogA/jbJv1SVQ5gJGEBlHCOjQktb2Ba0y+Fcf0sicgZPWyqKRsdMuw+AHPJYDMnWVVVEADrLPHJBSrBaeBwlLasMDNOsVnrzEMfdZTv7Y2AsVkDRvPQOeAc+AZ8Az4BnwDHgGPAOega7IgBcqdMXL4EF4BjwDnoHuz0B/FSrgwhtloFhwoFfbGuQ2V8DkIghchCvzFaz0KmBvChVGU6HCxYdSNPzDfHrBLwusF9snoNohZLpUyeIoLxyKLcjigGIuQOlv6MhBFjzgTuxXYBlJBsCIcxZXnwCMRsbu8RufCNO/cVO1iUoP+eVBYdVNVpE4SIZAYyd1o5g9GO7KuGHAYBOT+mpsCLNEePyGGOf/d1OjegAldPM9FSysvMFKYfUtVgsb7rZ+GBkLGqoPiZsThGlShliMJMBSsRiirXjdYcmUzXJNPBZTeo9Qkcpj058I9B7424y/h/lvzofnjrfDRg4La22zRlhvh3XDejutk5/SUTHH9KbiSfJJJ1IXlsmfnS9zI2OwreGriMNavoMBYjIuhTkCypgkgO9yqyRlOxZDCJvs8F8vvhGu+vK14aUnXoayaXvQQQcF+mvESy21VFOsAzwDi0MGqEDh17/+NRcoPPnkk21P+T0TtooFCh8KW2y5Sfykpd/XeMQmf6kY+/Q5w0f+ghGSMlaByZ5x0Z5acKJVStuUfGd/4KVWwpEIUmgsV5mCZCQGts9qCZy66SAMzbVxviJPQO2wbw1AGvXPDWLPVpmXHbFCoJwRGSsfDQp41iI+HZgG2LqWoKBmbxJqwQfZqjgzQwY8EHEMX0RM6ln+RIWct0Ww9/Wvfz2ceuqpTWd2+umnhy9/+ctNcfT++epXvxpOO+20plgAtttuu3DttdeGlVdeGaKubemG76OPPjr/njSJdKONNgo33HBDGDNmTBNkCM8//zw/ceHFF1/sEbv66qvzk3aWXXbZHnGuXLwz8H//93+pQOHll1vfo1dlbfjw4VygcNgRB4Q115IChbxWZAtdUuLvx8K0OEEmy3McWYGaxo8NPmjVKaxZSQ6grlFqkGJQNTVsousXi8FBMjiyeCPLesImNu0Ld8bQ/2pRxBITaKw+uYkgRlKrvMAnDCFYJ3yQC58ooIeO2gY+BcEfYzhKsQIH4iy3mRN49W3iEw0jk39ywUg6RSfS57P0YRR1s2c9EAsVei7K8icqIGH933qhwuJZqED/7/nCCy9wgfzMmTMDrRlz584Nb731Fv+j4lMqTltyyfjU0lGj+LrNCiusEFZbbbVw6KGHhrXXXjustdZaYfTo+ORSP4ZkBrxQYWi9bLReX3XVVfwEBSoeb/fYYEMqUDgo7DRp28K148L+AZuG6KywH4FzWu9lqYeE27S3iDsA0ldyGrvUNXxikzSJP3NHkaqr+GEJvA00yRKrzI9soENLENtnkwis9MlOowbOGcwMRsbGQkPzTZiin7JP4azgNhxkAzu07F2dsDfjEBgWGR6ExHpry2R27ojHn6iAnHnrGfAMeAY8A54Bz4BnwDPgGfAMdEcGvFChO14Hj8Iz4BnwDHR9BnpTqECTkYt0xWnxrbT2ftp4QY0vxEWYLVIQe3N1Ln7NDDMrLbLLtdusf0esYGjAiG32efe1/ESF0atpoYL90+YgIm4rN74KiQCmzq4VueFGzvKco9JyGGwhPotBTBZbp4/yy468Kvx99vMW3dDf9P0bhz2O360yFsRMRn2OuypmJsyMj9/45KAXKpQTQ09eoGKFsR/cJKz1njUDPZ2Bj6p881R0Pna+VdjS3K1f5DtnJmotRxGcRwZD3UenPx7u+WX8gvTZVzNmAHsrrLN82CzmbdMPbBJGr5qfVMEhVOXHymycZl4t/U4Ab/kgs7yxj1yTuGm+6/is3PJbnxYDeZWM7FX+1qtvhau/el14/v4XLGuP/d133z1ceumlQ+qvKPc4IVd6BvqQgbfffjsVKDz11FN9YCiajN9WChQ2jwUK9EGBPRA+NPBlJFnx54j+juNLy4zPnzL4GMgYMk5I8aHwxI8xO5JBYoydhNPA4IMjTkAe0YmPbKOi2tgFz675JLFmeyEU86iDv9hijmqmRDV41hp7ClR+xC4Si2Uaxg64sibHFbVZzFiMgWloiTraJE/oG55kQ1g6lJQhtq86FsFxlM30QgXKzCJ50A3xG2ywQXj99dd7nN/EiRPDbbfdFuhm5VaPb37zm2HKlCmtwsPWW28drrvuuvCud+lfaW/ZcuCAVNBBhR2tHltssUWYPn0638jXqs1vf/vb8IlPfKIpnGI59thjm+IcsPhlgG42/cEPfhC+//3vh04UKOy+507h0I/vH9Zaew1OJq8pWGtIYtcbTbesOwwy65MA8/JSHNMor1eiAzeP9GTXKBEpNvkurokkLvAaOORqmnDMAH9MIAgSFW2ihH8YHHUCznMkA2bjlrVVGJ1ooz32GJafWPJRtGFnrOR9gZhFdu1EDWLDPBpasrZ2iVI6mUnIZGx0LDBxi4pYk3MvVJB0dMvZCxUWj0KFZ555hp9gdffddwf69+CDD4b589v/wyAbbrhhmDRpUthnn30C/TGKZZYpXUvrlje6x9GQAS9UaEhJVwponaanz5144on8u9tukBtstB4/cXPHnSfwd1ppjyALuuwZUp+8yUKe9xVqgQ0FIRQvaOBFAVWyZ7VgCE8HY5RE+iQDhiXGR9SISG2BoziyIvWijPuJP+Otb2CSHUWgg8SLcYoNczdW8JNE0hFxIkgxJRjPpjSHxFVEIS7KUgolCgmFWNHyHNkceSAT5bON2msYRCQoa8tk2UdKUJRPOf70MG9e/ZoyefLkMHXq1ETvHc+AZ8Az4BnwDHgGPAOeAc+AZ8Az0J8Z8EKF/syuc3sGPAOegUUoA70tVKiaer5YR1q54mZv7rU29qJdvNs2qXA/bpErqXFfLgssh/UD2z4VKhAzBQGS7DrdFJxEZUxd8D3xlTkSObmTvOi1S9H0gK+MGzEZ3oa5aXwvPvrPcOFnLrPIyj79NfwjLvhoWGaV6i/BKO5exUxeyvMqx13SP35DLFT45k2V8XWDcNl3LRvGxoKOzfbbNCy3hvmLq5hXaT6Vrx1NRF+bujm18x55Z+E74Ymbngp/+eWM8MrT/1fnYkDlVNyx7sS1w2b7bhrW32m9QO+1mAT+6e17hAOvzF8PfPzGLbx7C/Pv9Xu7ig/vATBXvRdIVyUvywinc6QnYEw7/sbw1zufJWlLx4QJE/ix5fTXgf3wDCxOGaAChV/96lf8BIWnn3667alP2G5cOPyTB4fNNt9IuOLvfvkLSFLYfUv6pIm/19KPLf2Ol37PWacYURGuGHKBl5SqL8hhwuoajCFGVMRleRKNYhkHTlLGfmoiRoeGQyRirnOBPWxhlJmkB5+sFxB42Kexq4pZMLAj38aAPSD9wERhxPAILYtUL4SNczS01kdtX32zL7I1cc2aMSdceP6VQFS2dMMTfZ77MbQy8I1vfCOcdNJJPQZNxQn0Vzvf85739IirUtJTFejpCvZ9V4WDbOzYseH6668P66yzDkRd0x533HH8ed1qQJSvadOm8V8ebtUGuD322CPcdNNNGFa2tG+i4rall166Uu/CxS8Dr7zySipQoH47B/3e77HXzuHQw+kJCnmPnn6XdY3h1cmuN+o04wgRAWZNIYgMsbbFMf1neBjDdkIIfBIpOJlgrALxCduEYj/EQUeKUYYFGey5ZbCAyLRgF/0KnZ65iTIZ0sRKPoWHFcxFY4BjrzAPkScuxmcsWdIhemBjyz9FHHgTPhoxAi3ziE2dnGwRKjBJpEEWYslKiVExJPZCBcpC9xxeqLDoFirQ7z7tq+hpUFdffXWgpyT057HiiisGuhn1qKOO6sq9XH/OfShye6FCd79q9Pt7xRVXcIHCPffUf061OosNNx7DBQo77DyeCxTILu0PZAvAVElGepbQye5tqE+arGVEHOrugtd9y0N6OpIMWKVIcsIwUrFVerOfgD8y4j6MwUGt4smHxbNK9TCzcSASMk9y28/U1CMmPhI2jur7CWwsVWbsYI82Iwy3iYmiABYt2VAfEVp5Elo7MaCzqJE/loiQOVQOsRcqIBPeegY8A54Bz4BnwDPgGfAMeAY8A92QAS9U6IZXwWPwDHgGPANDIAPtFiqUrpHFGctlONxIXU5B4eJcLwoViAf3+VoO6wex9LlQoRzsYjL+43duDQ9d+UhLsx3/iW3C9pMH76a4bi9UQBKHjxwe3v3xcYHyNXzJ1v8SLuz7q33hwX+EP3771vDSEy/3l4u2eZdaYanwoTP3DSusu0LbXIsLwcJ5C8NNp9wSHr3+8ZanvOmmm/JfUR4zZkzLNg70DAzVDFCBwtlnnx3or2HTX7Zs99hu4jbh45/8UBi7+cb6BWTc++i3kGmPgjEptE9+UzduWqQfW9rAYBOjwbEOGFLTf2KQwmcGlYmOgcKr4GTCKtFLHKZviIucyTr7TLxiz3ghZAxZpBywHAjhQpzJJdMIl8KZB5kCXoWJ28oTVwQVfMPIyCXXkk+jLtgxXzxxxGgtBxlWyMVAWGHLUMXnhrXKLwj4pBEdXqggeVjUznPnzg3rrbdeoKcq9HR87nOfC2eddVZPkB51Z555ZjjyyCNbvjlugw024Jvq6C/0dsNBv6f/+Z//yTeAtxrPjjvuyDcE0g17fTnuvffeMH78+LBgwYIezX/2s5+Fz372sz1iXLnoZ4CemkBPT6AbUdstUBgxYnjYc69J4dAjDghrrBkLFGhJ5EUht5xRWTqkq3oaQAwbkshaBw2b6Joja5uYE050OGcO9a36gjyB2VMKoIAxxLqaMs5iEo1iGRf9WTxhOISIQaiZQyRiHvU0jP/Aw7YwokFiiD34ZL2AwFO2A5YpzAlyatE36oKM9RxbRBBegbCTMBrlDFMwsCSr7Ssv+yA7nSeJvVAByemO1gsV6m8ApicF3HLLLd3xQvUyitmzZ4f/+I//CLfffnsvLduHjxo1KlCB5zHHHBOWXHLJ9gmdoV8y4IUK/ZLWtklpXb3sssu4QGHmzJlt8220yfp8vYgKFPiIazLWbrT/P3vfAWhXUa09JAECkW5QCBAgtIAEkF4EQToEQgiEXi3v6XsW/ieKYkGeCijqU5+KD1QEaZFepAiIIEUEQoBQJCBNLAjSSwL88621vpm199nn3HNvbpKb62xu9sx861vfWrPuuWcO5+w5mzhaj9myD9SWcTjLCERxEx85+dcOcMlj5agv+llDRq0xRZox1cGFS/wUIeWkev7M+aD1fFWNZ5+n7yNJNad4rXkLBSx2IJfG1X6dg9AZSwLwNrzeJk5083ORvmCtvvCBXAtfDKooWbhcUlw6Q0OpIiZUx4epbFRggUpbKlAqUCpQKlAqUCpQKlAqUCpQKjAQKlA2KgyE30LJoVSgVKBUYD6oQHcbFdYNY8ev1fVs9Iu++Xaa3h0gOxMHsoBuPoiQRzO3uccNC7DW3qMDEu4+594w/eIHmp1r6IiRI8LBF0yuof86w9eefy2cufe5YdbrnS/KYUWGL7FwOOiXk8Ow4cMIzdV2ftmowKIsvvxiYatPbh5W2nzef0vt/XEzyk3fuiW8ObO73zXnMC/aiT8eH5YdO3JehJ5vY+JOGb/7n1vDvRfc3/Uc8O3J+Obhtddeu2ufQiwVmJ8q8Prrr8sGhRNOOKFfNihsstn64cBDdYMCXrikDyfjixF+sIj6sM/Wv8hJr3fgoyLaqqOUN7+2UTbHGFFTfMVHXDSE0JGLEMWgkJyVaKYWfwvCnEhmvNaxxWH2FkJD+3ixLz+KaRj6IhlV9nFbOEJp44/4YvJ2ZmvaZk88pWrmvm9uynO1NoC1MDn1h08EFFMxPWexhMaO9O3k81EOtLRXNipY/QZZc/rpp4fDDjus46zwbf0PP/xwWH755TvyejIi1pFHHtnjhffUGTVqlGxWWGut7v+fj7792eKbhz/ykY+EU089tWvZbbfdNlxyySXhHe9wdzPr2jsT8btB3ToduGvDnXfe2YlSbIO4Atig8O1vf1s2KDz//OzdmQ4bFLbf6X1hvwP3jBsURqb1AWtNWhPjkiB91tQWC65HgAUSHxt5H1tTxEJfeOiPrDkGaxxy6MexEyBfNeJIAEXpBjD3ZWS82DiDupqvCsIT0RI/daMfLNnf/KRx8eJYmGp2ebThIwA8jC+BRUMMCMiMDABEreSUMFFLMHmCphh1f2HFU4pU66umaTEL5uACKiMCyBkD44By99T7wpSzO9+p6dZbbw2bbrop6OWYwxUoGxUG30YFbIr/t3/7tzBz5sw5/OjpLP++970vXHjhhWGZZZbpTCzWeVKBslFhnpS9bVCsxxdddJFsUJg6dWpbXreG1dZYORx06N5h0y02kDsoyLqONV3W5bRKyxiafD3gX2gkFnxgEEB6jX3RsZNSlWse5gMC4slZsBRbcDHAKAd5pGccqhGt0vM8kr8SNIZlYj7SyNySajUmeZqEkiLm46b8jEslYSUsekhfAfa9bPaLntGQbNaxzNN8/VilFWEt2UKXWsKwnNi3oYb3saJBdUUhaaCTfCgcKWWjgpawnEsFSgVKBUoFSgVKBUoFSgVKBUoFBkYFykaFgfF7KFmUCpQKlAoM+Ap0v1FhzTgXv+mAb5F5rPmuB81+4Gbf/GZexrR4rXGcW37TTsjK7dNGBYZp+o0hpbqdaXaLN+kC66TtfZri1DHP7zK/qWfdE2790e3es8f+1v9vi7D2hHgRUz0+Y1KhbgfeNF/yaUdb9zW/Gdc9Gq758vXeY77oj9t3nbD5RzcJCwyJE2Gd6nNsN5OmmlHD+9T1zA/ftn/T/9wSpl/yoGcP6P7EUzpsVODc28y3ZWJN9WshGdCOy5j0a4oNWx0nH20n7bof49Vxr+f7Tvv2n9wZ7vhZ9x+w4QPsyy+/vFyU4utZ+vN9BbBB4bTTTgvYoPDEE0/M1nzwWkU2KMgdFMaIlvxp2t8nXr/wNUy71j83pD/r5Oc/dMTTSGRkUsqdn0fCLjFpYR5uLHmYA3OiGa24ID5BaqScaNDWa+Q+8oBdnS2cjDIHT30aB1jisOPDRBlhojXdVlqTBrFqHhXpup4JM57OQv2lb13Oo95WOJix42cVZuDyIxWkmINwUy7kq61sVHD1GETdLbfcssdv2f3kJz8pF0L3x7SnTJkScDFktxfNLbvssnK3pfXWW68/wvdaY9asWeHQQw8NZ511Vte+u+yySzj//PMDNnjM7jFjxoyAjRrIo9Px+9//Pmy88cadKMU2yCrw7LPPpg0KL7zwwmzNDhsUdth567RBAWJNayTXHl1m3OqCtcQtkOznNc3WFxHWk6MDiJIQkR+IoeswGgQEXezs0Fc84JitSnGYj5vzhIvPsdpXRZeDqGoUaFAnxzcPiWvk2EhsS0AbJbBvpuSQdemsMX2unuP7FAFW14WN3HatclRFqmFzqfShrZR8Jub5IpZjMv9pZaNCrtsA6JWNCoNro8JXvvKV8KUvfWkAPLI0hbFjx8rrOXwxRTkGVgXKRoWB8fvAeowNPfjbxZ1QZvdYY81V4xdaTAybbr5++qyLrwf0tYEu1HwdgAUdq7ofMwdb0rGQCwctjgqeB3QjzXRVv+pY14gippPyMDWBJb4HIp25WJuCxw5twNjXVoPQpa6N94vUB+mgJjJMGjpyWLQrJ3NbOAYwD1E2Yep7H/TBTbbUUZxc5MeDFPXjHFrt4DMPsSIORdgKRg04qEH8LFDFx7CyUYEFLG2pQKlAqUCpQKlAqUCpQKlAqUCpwECoQNmoMBB+CyWHUoFSgVKB+aAC3W9UqH+7pn+LjFfVxgvSrKvvmZGT7endtlgbblRoz0UBmzTqcVho5fZ2o8JB5/OOCoxFvYHaNtezt9niG9jP3u+X4cW/vNQr1yVXWiJMPmMirj7sxVEn963WM657NPz6y7/pRdyBQ11xk1Fh++PeHxYaMTduw671fvnvr4Srv3Bt+Nv0vw+cQnSRyV6yUeGdXTAHAqV/Htv9OZN7z78/3Py92wL+xrs58A3EF1xwQdhhhx26oRdOqcCArcBrr72WNig8+eSTs5WnbFCIHzQffNjeAR8846h+wIhXKPFvDD94ISM/8eR5+gJHMKNqPw7oYyqOo1oJiB1RVWl4Rl/nlfBMlLAWW32NpKKN/qJI3SpdcxVfja0y7CuZU8WIdSIPExBWJCm7xhE7SbDBk/qqQq0Uhx0wpU9l+mc/2DPdxQHFDDmzBJku9V0rfqovfhZa0/ZKqq9mjasch6f4qsd87rrz3nD+uZcb2Nz84Q9/CBtuuGGzsaADrgLTp08P66yzTse8FlxwwYCL5VdcccWOvN4YL7vssrDPPvsEPD92cyy11FLhV7/61VzfwIgNZvvtt598q2k3eYKDi72wqWGhhfrvtTVyOPfcczum8OEPfziccsopHTnFODgq8I9//EM2KHzve98Ls71BYcFhYcedtg77H7xneNe74x0U8sIkfQ4TLsuGrh2oZlpdAPm1I/XFIIWPPT3EXU5EpBW780OX6xm1MxE2OxxPPFSIVnVxmIUwXFXUnGaT5uKcK3wZxBP8kJvPj3225EobHTgnjMnRnKBTYSe7+qpRzohpVGpg6PtmFs1m3PQsKDlsVY8qWbueP/NIzAhUOMwUOCco+b8dpk2dXu6okAo37ztlo8Lg2ajw+c9/Pnzta1/r8UGFDZUrrbRSGD16dHjXu94VFl98cRnjiyPwfgz+4fUM7iz18ssvh5deeingzj1PPfVUePHFF0X/kUceCY8++qj8e+ONNzrGHDNmTPjtb38723fo6hikGHtdgbJRodcl61cH/H1xg8K0adNmW3vNtcbEOyhMDJvYBgWuvbJeuzU64Wlt1vWbuCQiTsD1EJvwFSEOQvZzNiPgdQHc5PUBpAxPXdhSHmpMYw0t/knB+5tfKz+TvE37jKHiMoo6ziMZmLvmGhmZJH3xMgzanIalHRuPNfXVue7HnBVnAEvLyOaZQpGLNvubLzJJMiCYFppoyCzFFVOe2MhXcSMlmSReNiqk0pROqUCpQKlAqUCpQKlAqUCpQKzAAw88ED760Y+21AJfDIV/5SgVmNMVKBsV5nSFi36pQKlAqcAgqUB3GxXGhbHjcUcF3SCgb7bZu2apDvWLdZOh1vF+Pftg4wPf3KsJuSE1F5CNElPPvidMv/gBZ2/fHTFyRJCNCu2C+BQZBnLEPdYJb0qBGrB5HY/Tz9sRnJye8q74RbHkF8KjNz4Wrj72OkboVbvzCduH0ZvXLqKitlfy8au7WDwr96lR8cvmGdfGjQrH/SYDbXpr7LRaGL7k8DZWD8dA8eeteEH322++Hd6c+WaY9dos+ffa86+H155/TTZyvPnGm96pz31s8tjtWzuFdyw7ovo7b6fIesDepibJ1dsj+MzDz4YrPn11ePXZVxOlr50hQ4eEkWPfGRZfbjGp6yKxtqjvwu9YKMx8dWZ4/YVYK/yLNUO8vz/4THj5mVf6Gi7s9aPdw7JjRzb7syZ+vsTg0YR7rFk1/2200/B+db2eHts95dcuZj2Oz4H9Ntp//PWM8Juv3xTemvUWmR1bfCh+5plnysWMHYnFWCowACuAC3BPPfVUuYMCLuaYnQMbFDbdfAPZoLD6mqtUpNIHkEDj+oslWD5mRMv12P5uOfZ/xgkTrjiJfuIAwpOYA1xXbRra/DJXw2tOWVTUZMgXUznN7MuAsCWPFDhi0cDcVYySJOW4QCpcC5iYTIC8aJCYJAgOfQWUno0cO5lqPLjGgznkVlCxyUniCpGRkq0aw83Ngko24m95VRoxqGaFr6SUd+wIkgANz3zvuiNuVDivbFRIv5RB0PnsZz8bTjzxxI4z2XfffXu8SL6jQBvjtddeG/bcc0+58K0NpQIvtthi4dJLLw3bbLNNBZ9Tg1deeSVMnDgxXHXVVV2HOOigg8JPf/rTMGzYsK59uiHefPPNAXe+6HQsueSS4emnnw7Dh3fz/xqdlIptoFYAGxS+9a1vBWxQ4AWifc11WNygsNMu24T9D5oQL05dJj3366qgqnju1zWhdf2CwayyNCovIRRQjq0pdW0hOTDHyzrSMw7XIs6ZS1XCNQnLOQuTJxln2HJjqtmgMjmHuHhbyIixGxHPSzmQacQ6DidibOGi9Kp+NV84qriPa+GcpqgRlrZRO4Im53wV8XmJmgaUHJOXOZNLLQY0lzhMHjJJyUUTEurd5Y4KUoeBciobFQbHRoXvfOc74VOf+lTbhxU2oI4fPz4ceeSRYaeddgpDhw5ty+2N4bnnngtnnHGGbJrERth2B+6QddNNN8kmiHacgs/dCpSNCnO33oyGDQr4chbcQeGee+4h3Od2rbFj5A4KuPMmv4QLYpW12tZ/weJiTRtfFMiqDdxlQY62NCoj8QCn9d2v/dAyrpEZQ3PTQAlzgtK1U5KGWuKIgqrbvCyUiDIfthqplqdpaRhmqrrQ8qGow1btVRJtOUdV0LHvW+4+QISyfzYQy/kL0eXWykU8+rGViMDpmd0SlvK2Dn8vQjW+6CWiZsUYaL/yhW/FOye2vxNg2VzP32RpSwVKBUoFSgVKBUoFSgX+NSqAu0BvuummLZP98pe/PKDuAtmSYAEGTQXKRoVB86ssEykVKBUoFZizFejNRgVei4uM+MZYNTt/xWzVkkfu3bl01Xy21nuMWXtfztGyHt8c7vVGhV/u6/Tmchcly1OYq8Ev/eSV4c93Pd2nmKPeu1zY/ds798m3T05WpxnXdbdRYdJPJoRlxixVDdXXWsffzz+feD78eepfwtNTnw6P3/ZUeOOlzt9eVg1cHS01esmwx/d3DcMXX7hqaDfqQ94v/fXlcOG/XxZe+UffNwssscLiYYWNR8V/y4fl118u3gliwXYZNuIv/e3l8Nf7/iZ3c/jrvbF94Jmuv+G/40aFxmgR7EOdWqT6Q6NFtAegP2K20Xj81ifDNV+6Xjbe9JCFmPHB+f/+7/+Gj3zkI93QC6dUYJ5XABsUfvzjH4eTTjpJvm1ydhLCa4jNt9wwHHTYxLD6GivXPpRVZb72wbIt/dhBS9yv5wkD1xIjpq04i4V2EPkBJQzpg0303Qsh10047AlPgk6jrp3IGonnFMdriLYDQI5H4ro+WE04+DxolxZ5VXJRlsea+t7F2xtjRLCZ4/E8P3I1Rq5rwhEENUnBtKNjO8PZCPQzNyObv59ItICLf1PvvK9sVNBKDYozfqerrLJKeOyxxzrO57rrrgvbbrttR05fjb/73e/CbrvtJt/O243GoosuKhf04MK6OXngInBcxHfDDTd0HQavU37wgx+EIUOGdO3TGyIu7OvpW1bPP/982VzRG93CHfgVeOaZZ2SDwve///1+2aCwy67vD5MPxB0U7E5xeI5HGdhaSeS5X/C8DohJlhIuJkpu8seCAw3omoyS41lwG6U+qOKTaNJJdvjRhFxF2hBptG+IkGVmpFgekBBcO5VcsjxVNA4jU0KsyMEcfI4ia8RGPDq14pZMbNRVlX0fwdrFY0wLCxVAcngN6RtJGLFfaaNHPTeIAINbmrHJey51lC9nnHImpmETFNvdckeFS6Xf7nTrrbc2fqDZjl/wvlegbFSY/zcq4HXLBz7wgfDmm81farLVVlvJnf7WWGONvj9QevDE88KPfvSj8F//9V8Bmz6bjv3331/uPtVkK9jcr0DZqDB3a44NCnjNjg0K995772wHH7v2avH9or3DJput55fYpMu1Gut06suaLAu7W6izHc621Fd8BNUFX/TJATlpJ8+MiV4iZxyvLaCprXQByMHXHKJrvoxBBlqVIJuAxqjyzSsFc3mIUNZo8lOKJgJ7092CvV/7vubh9TJSzdtrkNNSs4Z6S361mrWrk+RBjUjyMdl3JVO7B6JA5pWNCvw9lbZUoFSgVKBUoFSgVKBUoFRAK1A2KpRHwryuQNmoMK9/AyV+qUCpQKnAfFKBvmxU4Bt1rVPE1bI9HfbundB65ve8UQFCqtnXjQoHTtm3umXCpSVvnUI+YvF+DZJ1p5PURridWJ1tjJniNYTVNyYTQwUdL2mwgLWQzz7yXJhy+EU1tHfDSaftGZZZbenkxDdLU1YuH5DktxQLlOwA6xwUMGIVDnh2zLhuNjYqUMS1qU4+kaacXEazXn8zPPKbR8P0Sx6UC/GdXNfdZdceGcbHjR7DhvftW2Bb8nY5v/HyG+Gij10ennv0n13n44nLrf/usPHhGwS0/pjdxzbusPDHq2fIv2cffc5Lt/T3+qG7o4KbG4jyOOvwGPFi+piLj6eahuf01G+pNRxqeimOF3McasCv3WPbu4peaxhP6bHPmH+99+/hymOuCa+/2P3mmv/+7/8On//853uMUQilAvOqAq+++mraoIDXMbNz4LXDFlttFA4+fGJYbfWV43MM1OJfEP8QKR4BQrDxb4xrH1uQaEuu1hFO0hEiLUkbgaGPgxF1rCBtyogcA1QbPuIoZvrrwEZG8LwUKYLJRwjUi2g9MMI4jH3xFx1EhZ9ETyfaxQojfmokP1aTirT2VdbzGYgYW4mDkzuox1ZMklI1ntpznmKNYFKzTkLimPPMHO1RSxgCCZmhEUTqUTYquF/UIOjedtttYbPNNus4k9VWWy089NBDlW/l7OjQB+Mdd9wRdt5554CLsbs5Fl544XDOOeeECRMmdEPvNQffCLzLLrsE1Kfb46ijjgrf/OY352id8C36H//4xzumVC7861ie+c7497//PZx88smyYfell16arfzxDdq77Pb+sN9Be4Rll9UNCn4t4LqUsBgNWFoSbB1AEuRKQuagvLTiiCmtKbLIVG1eg32hYaXySVDJwGSKY0D09U6ZIxngpKk64ZSN17BYaJJuykdFKIFR5lT7KlPLT0H16TFm1tN4GhsSKT47ppttvn4+Z/YRXJ2kBhxGPYMr8xLdeJK5Og7J1CCPCVZqo+EkeUnb5V42KrA4A6MtGxXm740KL7/8clhnnXXabkD90Ic+FH74wx/22x0UenrU3nLLLbIZFa+rmg58k/xee+3VZCrYXK5A2agwdwqODQpTpkwJxx9/fLjvvvtmO+ja66we3y/aO2y86XqytmNNdkus6ru1Gzau26mlg7wIqPrXXxfktV2Eor6oWJyaNlDGQ5diytbXFQl3cY2XlJm/4IYmLe2odvKwuCpOm4WVJs8DeSUx6ZtiS75wlAhGh199o4LXEr5p5xA+X0mlEr/qw0AWV+lyVr0Y3ygy4Wip4tnOvIQeSTU3/1tUDRMmX/JyJ8bRZOSc5oFYPd1RYfvtty9fRKRlK+dSgVKBUoFSgVKBUoFSgX+JCjz88MPhmGOOaZlruaNCS0kKMIcqUDYqzKHCFtlSgVKBUoHBVoFuNyqsvcea6Y04rUG+CpcXAfMNubpdx3x7Ll6mG10rb7a1LWqOkTXqmHfWGHefc2+YfvED3tC2P2LkiHDglH2qFw+7EH5O3AjRTszeXxSzSDiddj51vBKvfjW06bXlJDtUWW9cpN2ayI0n3ywX2tfj92a8xk6rhW0/9z5x6SknkDKndql2ytvlrFd0t6Qz47p+3qjgfmmVrFJOkrnk0WTHnQJu/v5t4W/3d3fBl5/QSputGHY5YfuWi949p6mf69h60ftbb74Vrjj66vDUHU83uXbEsDFho7hBYfnaBgU4uTLJ329HoTZGn/ezDz8XHrr64fDQVTPCa8+/1uIxIW5UeNfYkRlPv4/8GJHZtz60s0+kVtiduNmrpefzbnoMaG00UsUOpYa8m/4efdBKrZ2G5/TU9zmD++yMf8rjojd32PjUpz4lF2z1lG9PuRR7qUB/VgAbFE455RS5g8LTT/f+ec7ngsf2lltvHA6Od1DQDQr2jCHPHXLS5xD3R2kMeU6Ujx1BM3u99U9A4hd5bJEHtaSnhmS3YRzHnv6Ih0slTaUSl1xp44lHyhGA4slKrgHp41TBTQC5i91ICc7jlEfKWW3Ec+SUgtYu0iqc2iQZtwb34NMa26YdG5+zZYUcgJsJfcZryk1okWD0Si4EvYaVCxNVs4mrjubAeMKJg7JRIVVtUHTwBvEJJ5zQcS7HHXdc+OIXv9iR0x9GfJvoDjvsEP7yl790JTds2LBw+umnhwMOOKArfrekv/3tb2HHHXcMd999d7cu4Qtf+IJ8I2rXDn0kYiPH8ssvH2bOnNlWYYkllgiYw0ILLdSWUwwDvwLYoICNL7hDR39sUNh1923D/gfvGUaOXAYriVtXYi343M/WlQdrDdcErjv1VuiUJJ8aaawEU8vrDngWIMVBhjKgiLY5LnHjpRiGc2wi1IWVGk5B4ktetZg5B8SBUQnEBeGgQRt8mhlX2ugoSjQymZqGmqmhsUmt2hRlDIyyNP0FNdy0JA/t1/UqWiYIpscBYyIxgrWC6CkKinJOJI0FcvjdU+8LU86+zDm3dssdFVprMqeQslFh/t6o8KUvfant65F///d/l01vc/t9lD/84Q9yh4cXXnih5WG76qqrhvvvv7+8ZmmpzNwHykaFOVtzbFA477zzZIPC9OnTZzvY2u9ZIxxiGxTS2ty0Jtt6K2tyjIphXrdlkNZ2r8MExY8abGm09d8U7bWAaSabWs01eaLDeGqjnxj0NYOScNZxPb4mJ3NSjgDKZzf65NgEc2zxSwRy+RpGc1dtkdWTySB/v1GB8yFTZalJFG0V836NfcbLVRExchkHZqEiL2WkuSeuhKddUolcCyC2uoYIRdBYGsDimA0KwBOn540K9CxtqUCpQKlAqUCpQKlAqUCpwL92BcpGhX/t3//cnH3ZqDA3q11ilQqUCpQKzMcV6N1GBfemGq/AjXPndfB8Q07L4a8Kzn7+w5oqv6mIzRrp6t8WF43T+40KtTsqmK6q5dw7XRgtbxa6fFLmqRONXopcZ6/Xo+Wi5yRBoVYGLdVgkefi4JvVz5x0bpj12ixm0ad2yIJDwoHn7hMWWXqRin89q2pOmohLR3yVk5n8Hfu8QZxxXZcbFU6bEJYZs1QlLxm4wD3Vu5pTfVYqLZz4y//jr2eE2370h/DKP15tjdkB2fLjm4X37D02M3wJiPYi5+tPuDE8dOXD9OyqxV0dtv6vLcPqO6zayG98bLucGh/XUHKcdrXGY/DeC+4Pd597b2XDQstGhShX/X3kAPXHCCz1nBPb5TQ7eUMPRzWnDo+RSrDq36Mq6bmed0o3dVJQ79ax1iAisxf+/GK4/L+ukrbq3H50yCGHhNNOOy3gIsVylArMywq88soraYNCtxfXtssXr0O2wgaF+IHzmNVGJ1p6nop/2PLxoP6Bx+cT60Qme4CIs4UQ+mlMsuGw40h29AURUEYyhgbweGIeFRw2O4hjKLoCaN+6GJDeJrb5Jk3lO7eKdmQ36yUH1AAUnQfnm73EJBrMOXGShpiNU82PFvpg3E3fpW2ZwZFZmoYlCT3m26QttiYOnSwnN0SaCKK6Ns9kj50UB5z4r2xU0JINlvO4cePCPffc03E6uJvC6quv3pHTX8Y//vGPAd+w+Pjjj3clOWTIEHkO/uAHP9gVvyfSU089JfEfeKC7jeXQO/HEE8PRRx/dk3S/2XfbbbdwxRVXdNTbcMMNw9JL57vLdSQX44CqwBtvvCHfhP3EE0+EN998c7Zywx0Udhu/Xdj/oD3DO5fNj4f8vG5rjT3pE09rQIwOTMZYD9DDD9cKa1OS3gaQPBJES0iCxJ7oqVlGEov6YlZYKMRFNmlDzyvEvsTRFpYkAar5AecBzGbpyCJjlGgVP1WiBEZez/cplLjouPjENYDqou81yPGxlQ+esK2t+nlOVY9x2Ga/dnoaJlWnkp/EiQSpXpbU8FGQvswHLfKRWBpQfKdNnd7jRoVdd901vPOdehcQr1f6/V+BG2+8MTz66KNthfF7wEaqwXhstNFGAXd4andstdVWAfUZqAc2KY4ZM6Zxc9vuu+8eLr744oDXTfPiuPzyy8Mee+wRcLF2/cDdov7jP/6jDpfxXK5ATxsVtttuu7DCCivM5azm/3BY9/70pz+FadOmheeff362J7TOutigMClstMm4pJXWeluTdQHOazyIXKax/CY+cK7HsWU/kZ1dNIwrfZzkEEH2koZoWVD0Gd+clE89SIChP0nDSK5RFT1HWPjmJMNkiRrippw0AKaGNFcgyW6vUSJHWBF3MiaYJMSP82T+mQRdjKjpLT5m7uc8MiZeTELVklDiRzvjg5pw1yemKbl5pbmLuGjXOQJSy/jCgSF2GBsTpm9Pd1SgZmlLBUoFSgVKBUoFSgVKBUoF/rUrUDYq/Gv//ufm7MtGhblZ7RKrVKBUoFRgPq5AtxsVxo5fozbLfOUsLxTmG3JKzHYd8+01vUiXbyTWRGvD9ho1og01xuxuVMhvJULW58A5+OjeHnF7M7GyIUPfQsxOkBE379uqXb/sOeeV/XLP3rRMUaqWBMfOtPPuC7f+4HYP9bm/wcHjwsZHvrfi7/POOYOSc8o9n3cVrYjaYMb1fwrXHvebJlMFm3TanmFpbFTostZw7invanb+96WWV559Nfz6i9eFv8S7LHR7DFt4aJh06oSw+IqLVV26zNvnPP2SB8ON37q5qtPDaPFRi4cdj98uLL3qkg3M6oz5MO75se39IOtrpWF83niMzHx1ZrjvwgfCtHg3lNdeeD3UNyrkx5HXbtWlurYIbZz4JFX1dL7s8olMnAkmJel4lZwTTKruYwDNHG9p0vZ2OCrH17qqJ+JdPY/Aj3njMXrFp68O/5jxLOCujlGjRgVcLDB06NCu+IVUKtCfFZg1a1bA7SrxbXivvdZ695XexFpgyALhfVtvIh84r7raSvHPzP0txi7/XhNsHWH5fgyKofBdi1ygmXTFMfOYa1UvkeAd/xMRa9WDehWbsNWOZNSGcezpT2xrOKyZqD7mIo0aI04BkYKpUUthETQK+zmu9VJNXPjsI+HklDHp6Yk5W3rZEgFGTHONVtaLxDQ2svOSCco4hdcOqPRjCz32RUqo0qvo1OMaQ2HmbJPJc4pZkGidu+64N5x/3uWUa2x33nnncpF0Y2UGFog7wVx44YUdk8JGht7cWaCjWJfGxx57TDYL4Dm2mwOvSb797W+HT3ziE93Q23JwYSY2STzyyCNtOd6AuLi47mMf+5iH53j/Jz/5STjyyCPneJwSYP6twEILYYPCB+QOCu98p25Q4BqjT+X6xJ76XDLseZ5P+6gA1hcZx1Nal8izNlXKcegrLQmiBZIoCpq7islZeOpEO9c5fSkADW93voDpb85GFZ+ko+5y1jlSMBsYG47qZ3EctaLHuExOU0kxJPcs6sqQMrQ4mgOpPjazUxvyIjdrZI5irZzMreq06sEuv3cTrcwXmNkZg7GRmESpGeAvkOFgdbNRIemWzjyvQNmoMHA3Khx11FHyeqj+IFluuXLtKWUAAEAASURBVOUC7lo1rzcw4nXad7/73Xp6AfnhNd+iiy7aYivA3KtATxsVNttss4C725Rj3lTgPePWDIceMSlsuPG4ymsFrsPIKi25aY3NIFd+mGSFNoDrer1NunSElAuicDwrqI2EU4v3V4q9LoBGPIjlvvYk9XgylUjUnjXimWzmnHKnlxGksZP3F7cMVOrJ2jCDrA2veFCb/nFc8TG7kpF+tNYw1WEE5Yh0jcjYyrc4FI5tsksOAjC9ZCOHLdwRJkWv9cVupGraNg8BzZt9Ei1/xCobFVDEcpQKlAqUCpQKlAqUCpQKlAr0VIGyUaGnChV7f1WgbFTor0oWnVKBUoFSgUFege42Kqwbxo5fs1YJf2Et3y3zWLw41obV9wDJhVyVXwvQYeg1PE317j7nnjD94u6+oXPEyBHhwCn7igizSW8kVlAMOsetvyvKi4wrel6CBZI43iCAnHiBcUXD1Y05g9zMqerijcxzD7ygV9+qnrNp7Q1fYng44Lx9Ai6458GcMW7OKf/mq3Z4cEbVvGHB0auNCqvW7qiQ6t2szbzb5+Sz8xrMOYS3Zr4Zfve928L9cdNAt8e71h4Z9vj+rgEX0cpRkc7a7R5/yPuNl94IZx94fuWuBD3FX2nzFcN2n986LPSOBTtQmVNOio9rOKVaZbNq9VBrkJrqPfOVWeFPNz0eVot3dxhiGimGKoundutBSWDOGGcO867oZbM695B3U87mqE088zdWiZNQ0OpB6cq8q/Ye8045t9f2eeOxcuUx14a/3PNXBi5tqcCgrsAQbFDYZtNwSPzAedUxboNC/FOTv1NpUYI4qv75Rcj9Jbs+eNk3CUS6CtRb/2efQogefM3Hfgv0laGRiclQ/BBfD9psqDnDSF0SK/Pz80qekj/nlVFIJZHu+uIclcSt3qqy18RkfFxvowa8XBppoCHEW6NWSC4WYyhkhhxXdIBGf/aZR0srPEqIsAzIE7PLQ/WUJ32cGMd4ylEc/lPvvDf88tzOGxXAK8fgqMCxxx4bjj/++Lk+maefflo2DWAzWLfHV7/61fC5z32uW3qF9+CDD0q8J598soK3G2CT5P/93/+Fww8/vB1ljuH4xmRc1Nf0rcRzLGgRni8qgA0Ku++xvdxBYZmR7v835Wmeax6mUu1zcdF1IK81wuRaoEZZ7xSihq0SqYkd9umbAImstTSbxpAzWeLPLECTfk2T5CxjHuQ5gkGqmx00j3jmGlmJoynBKjzlsC+QWOibkEjxuQOvcGhXKaknYyhXzjiZzftX44uf6HmOuFZi5inHzESCwUXBYlE7c+jH+SgRPuYPIHY5Jp+JCyuBFiuOBTIcvtPuindUOOcykS+ngV+BslFhYG5UwJ39Vl111YBNqPXj9NNPD7gj5bw+XnjhBbnjwzPPPNOSCjacfvKTn2zBCzD3KlA2Ksy9Wvcm0rrrrRU3KOwTNyism9d2rr22HGMtdcutymO9ZSDXBy9Z0DfHdm0WsXUcmqInzhIhxRGTjXzDGGZPfNERCT1Fg+aBjsUzMvMDMeWvA/Glna2A4Iq/ilT7Jiwc11c1i08/i2i0egzNNRob7ORaCZgWExOXzDGBzGr5/SSThHMxzVDXqo9BYy4yK+askxAVgYykZjujUWOuaxyrVVyT+HHHnhxmzpy9u6WbYmlKBUoFSgVKBUoFSgVKBUoFBnEFykaFQfzLHWBTKxsVBtgvpKRTKlAqUCowUCswpzYq+Gtn+eac1sC/tcZLentbHa/hfVWv1xsV4oX2nQ5E62umnXSTTcRxcvNy3cTrh87jtzwRrvzctT0qbfqRjcLD1z4S/vFwz9+8/r6jNg9j94gbWeZQzj7ZGdc/Gq79yg0eauzLHRXqGxXATLXGwBLuh7whIdKQjcdN37m1680y4G/9/7YIa+1ev2sJLHakvF2yros7ZEybch/ZPbarbD067PDlbatJ9+jVS0LKGX6WrMu5l2pzjz6H8sbURXpOzSTl7Yrsuj7srNdnhV9/+Tfh8Vu7u1DQ+5Z+qcD8UgFsUNh6283jHRT2DqusumJKmx8i4mmJHxrKn0p8sdL0J5P4YBsBDXFpifODxlrrhVMMxBNeNS51JeFEdvEsDzXlnNwENc+UQ7KknIFUorr8K/HN1WNd9St+lqnMVw1ew6hISHNyudDm+TYtFETMcoa2kT234h8JmaUW4Zoj/WGhRrtWOaahictA9KmXEnVxJQcEwD/Lxs9DJcU29c774kaFckEhSzLY2xtvvFHuXjQv5okL2Xbaaadw5513dh3+mGOOCV/72te65oM4bdq0sOOOO4a//rW7jZILLrhgOOOMM8LkyZN7Fac/yRtttFG44447+lOyaM3HFVh44YXC+Ak7hP0O3DMss8ySDWsKJhef2xvWAX3iF7MsAcIkETDXAvFVDYWyXhLWKJAQ2eQLZeqoVc8ei31Lz6WEGIaLRGJkjodMT8NnA/PQNDLOVJI9AimeiJDLueqYYTDyvgvEAMQShx0GE12kH5kqV9HIdMasxvDxoqOoyjn2Ta6ix7BKNT4GRq77yPwFdPFJtty18RpZrO28UiJuPsg5/pM7KpSNCqzQgG/LRoWBuVHh05/+dPjmN7/Z8vhZZ5115HXOkCFDWmzzAvjGN74Rjj766JbQuFvmjBkzwsILL9xiK8DcqUDZqDB36txtlHHrrx0OO3JS2GDD9yQX/xpA+lyKsZ4mVu608KMJvITDH68JHFYfe+EUQ+KJs/rKWUQyPZFdDItDE2PRXVpoIycjWXpx6DAa4ZB42mnS9Bj7bEWCQbKc9BRGPnkOdT7GOESvlkvChQGOddQgA8zL4z4vpbWZF3LC5E3TGs3DwkCLemxdaI3vglc5VLQ4kS1UxsPAfDOTpBDKRgUpbzmVCpQKlAqUCpQKlAqUCpQK9FCBslGhhwIVc79VoGxU6LdSFqFSgVKBUoHBXYE5tVEBVcNmBfdenBXSv7XW18t2vYb//ahef25U8JH6mq3PsG0/7eyIEX3Qtg6dDZSo53zFp68OT/7hzx2dhy44NN5lYp/w+G1Phd98vecPCJccvWTY96cT+uUq7HZ5M+HZ3qgAoVTr2G99gDJU1y1zhgPr/fZbb4erjr0uYGNIN8c73vWOsN+ZE8OQYR0+2Ex5x4gu6PNPvhCmHH5ReGvWW92ECsuOHRl2//bOYajdBYM5d+XcW1LKOTr2Q60RnlOfn/Jmzsh/oOSNx8sNJ/0u/PGaGUirHKUCg6YC2KDw/u22kA0KK6+yYnzOyH+B/kNBwPzQkYyKHRWJz1tqE7LUCGP5Z89p4qOkSNdOvU2O5svnwxw/CVg88UhPeElPMxacmcHBvK0TLQCYC6SSfGIKKKOajTnBjQfjY9zUr/twrNKWD3J34b2OxIk2YsrLZOIaX9hufnCUHzNkncwnp1nT+1djKZ8Y8xJUJE3P9yUo8hFQclKWjqWPUxTzHHODQX7uindUOL/cUUHqN9hPI0aMCM8991zAhfnz6vjnP/8Zdt1113DLLbd0ncLHP/7x8J3vfCe+rO75lc3tt98edt555/Dssz1vgEYCw4cPD+edd14YP3581/nMCSIu8sPFfuX4166AblDYMd5BYY+4QWGp9Nwtz+GuNGmNkCd6PM1bJ3H0+Z2ot7PvNapYFDE99bezNPEkPzgJgGE+iAnosjaSrEaRY+Y0PxEgx1oEMrlormqlUeRKP/loKmk+GDKe9bWhg7aMgxF9wYO6/vhc6hyjmYj3p65IIVMLW+UYKOG0L+dIpsXzVctiuvxIrvvAV+OyTdmwI61EM+cUOY4ruNiVlLtO13Kedtd95Y4KWt354lw2KvT8PuTc/kXitdJKK60UXnzxxZbQeM2yzz6dvwCnxWkOAq+88orc+aFpc+ipp54ajjzyyDkYvUh3qkDZqNCpOnPPtt4G2KCwT9jgve/RNdVCV9Z2t97qKhtJ7nWAulTXW2Dg6npsKzd0dNFvaUE0ljmlBk5qU7GkyRhoFQRVSAZpTopIANKMb1jFR7UklySVMqvEqXIkpMb1etZnXnUfKistjiwm+VRtHCN94adEq/NPMIj4UYAxmrQZh20LR6Va5gkAPvTzeTGexNcUUi6WUvITHVWPGEQV0b45ExaTYmWjAopRjlKBUoFSgVKBUoFSgVKBUoGeKlA2KvRUoWLvrwqUjQr9VcmiUypQKlAqMMgr0N1GhXFh7Pj4jfmVI79Rli+99Zgn+wtYPKcdTl9vB0bfOk6+2u8+596uv81+xMgR4cAOd1RgRERoF5XRZ6+luo/Yd0WvQuV/PvZ8OO/wC3MZ28ivvsOYsO3n3icXvp+135Twyj9ab2ted93569uHlTZboQ73esy8mXNdoF82KogoIjBaPUrvx1Tyec96bVa45BO/Cs889I+uBOXOFC1/Z96V6oymNtwho9sNEYu9+x1hwg93D4ssObwyeyr7aP3Xp3o1777qU4WqfdXp2Y8RGLFnj04MqlC1E3f2bIjAaJ2VsKHmlv/9fbj3gvs7E4u1VGA+qIBsUPgANijsE1ZeBetR/DuwPwV8OMgPD2UqxOMnf61/LeCCFU/yo634KSo+1JNW+JEOPXVOsU1J3RnPOOpmPhVMA0l21LZMMUwxnLi6R6v+gCQx9dyqxwTpZ/Tobh7JsRqPsZlbKz8i4muW2Fcp4pJWOiU9kKIj86AXiORoH+d4gEtlDaC4nenDNk9LE6Kv0BWqxAFO39yquPiKjwamXa1wxI+J6tAcLSomWePQl35lowIrMvjb7bbbLlx7bc93O5vTlXjppZfCHnvsEa6//vquQ+FCt1NOOSUMHTq0rQ/uFrH77ruHF154oS3HG7Bx46KLLgrbb7+9h+dJ/9JLL5WazJPgJeg8r8Dw4QuHPfbCHRQmhKXjHRR03UFa/vk99j0ka5NCPOc1Qv3Ew/FoVxxh4kqAdcIdMjRMLeBUCbp+0FqzGVc4NEUMYzFFMW3NaDYFZerRIAyLa33QtRsbcTIB1a7bhOoS5zjP18Qga1002a4GNcWImS5xPU/60V7FhGYnU5GmquV9EKQWRjQrHCgaiXVIXhGnP31yq6lwrDLqUPVP4uLAGMKneIyi9aB/tLoC3V02Kkjt5pdT2agw8DYqnHTSSeEzn/lMy0No7bXXDvfcc08YKHdTYILt8sXdH5BvNxtNqVXa/qtA2ajQf7Xsi9L6710nHPbBfcP6G6yj7rZOcl31ay8IGLul1EISa15v1Q9LsKmBxjjAvKCt4dbIui198iUiBPCDk1jR00OgNFJOtIBm0dGRQ13FYGPvByfzSbB26GehW3RVPfqSACnro63nAb7ak0XyzTh6+aCW5Ae9Wn5gJo706Uuunwdt2Sf5mq5kFfs5O/XRuNSs6lDD54Z+0vB9ugLLDpieHIIZLo3jgODz+8qx3wozZ85Sx3IuFSgVKBUoFSgVKBUoFSgVKBVoU4GyUaFNYQrc7xUoGxX6vaRFsFSgVKBUYHBWYP7ZqMC37PB7aHepr3J6t1Fh0XDAufumX26nLwUV9dobhK25gJXza9KrSkR+naTTsJyqeilReQuzcxxyRS4G/d13bwvTL3qAcNt2j+/vFt69zkix33XmtHD7aXe25dIw6r3LhV2/uROHsZ29vJmzE4zdBcIj1z8arj3+hircMJp02p5h6VXjN16KEAlxUK81THWO+/2pJwi9q7X6BdnkMeWwi8IbL79BqG37jmVHhP1+sbfcVaHHvC3nv973t3DJf17RVtMbhg0fFib+aHxYcvQSHpa+yFWC5vlmcs91qEjAsS5jeatmVa83ccBtzRloPSCZGa8/BKo5R9U6gRJo5WiXN+3NErR2nzc9mvV6zFsCZY3mns7lzjPuDnf89K5mSkFLBQZ4BXBRyLbbbxEOjd+IN3r0CvG5IT6u9Q8tPb8D8x8Cqj2a4x9S658KuJi06gjDkdCFnXhq7Y8yxan5SBkRz3gWweB4Rxz6CxJPLoZyVRDnpOFjwN/Gya4ycG/RI1ndnG8SUTdx9TmnPNVH5m/62lDLLByiYrFfP5ir2OIpc5SsY99XBfVrxamfdS1oamJHfgyAg41zbB8jms1Au8wsDqhAO2NTjwTyMDnpQ0h+tE1+SEU4b4epd95X7qjgCzOI+8ccc0z42te+NiBm+Oqrr4ZJkyaFK67o7rUlkt5///3Dz3/+8zBs2LCWOVx99dVhr732Cvhm326OJZZYIlx22WVhq6226oY+xzn4JuJ3v/vdczxOCTCwKiAbFCbiDgrx/yeXXjKvS/b8LNnKk7nmzTVAID7P16ZEjqwDWAPigTPxJAf/OCAuRCPr2lP1S/aoJj5OW2zQ0gXHhilSigGkEs8oqqcRvL3aVzvOHieK2AlHLpZfsjPfhPv8lFXPjxpsqcWWuLQuZgohRB9H+95ODVB9vzGGkGjJfKm7wdSmVm6b/WgX6eTcylW74ZEnMzG+1wDj7qnTw5SzLzVyaQZ6BcpGhYG1UeHNN9+UOxQ8/vjjLQ+d008/PRxyyCEt+LwGsEF09OjRAXeCqB/XXHPNgNgQWs/rX2FcNirMm9/yBhu+J21QkNWSLwO4ZvrXK0jR7OByGc6ZE4sk+dE229Ud6zBkZD1Gx/qV9Zm4mkHW0CkvMwiOOOpgblVt9RQH0EwJHT2AmT+ASp8UdeRIWnXhnJ0urKYtjWlX+hFryQOIktQ99mUIOdOQwHZKGHjQIzl5Vf28XfvqkHEVpi5bykm+iEUg5RE7USSFTzhyqscAljVoNxdtYKefMwhGHLLWJ0UyMO2yUYFVKW2pQKlAqUCpQKlAqUCpQKlApwqUjQqdqlNs/VmBslGhP6tZtEoFSgVKBQZxBfq2UQHvlNUPXAjchIOXLxJWL/I8TkwZem6ye8xzs3/vNyrgFt1Zt+k6ZUTiG4g+qvazb65Bxrxe9f3FnLOPX9UnJ+vlGGBm3MfxGsgbF8qfte+UMPPVzt+0ssxqS4eJP95D3KH32guvR7/zwqzX3/SSjf2J/7dHWGbM0tHGnEHL+TXhnXJuCvLI9X/qeqPCUqss5STa5eQoPead59KbvKeedU+4/dSeN3sgk52++oGw0uYruqQ6533z924L913Y3bfhv/eQ9cJGh2/gtHO3+bGd59v0u4O3r0PzY9tr5Hjt9NrhPg5VmnOWrEiJbWv9JCOXVs67leuErNuOQzwLN+UMkd7l3ayXcxZFyw1N5jswdlvzy5j6Tb/kgXDz/9zWIb+qYhmVCszrCmCDwnY7bBkOixsUVho9Sh/l8aHOD+7kMc5xTLblb482afNslBdBHI6jgEBRC606Updt8jH/1NgfbuKpvMimmJFjkdvENruLL/p8UjDnphgpL3IRn3ybiyQDvD42otDtpA2YSUTc6ZtwoJEiTKMKETATYB88h4Gnw+hd8fVj34eHHtCpazEPMLyNMdRuAo5DLnmSCvSNSnvyxDxMjByx0UeF0tzUBp94CCduVLgjblQ473IxldPgrsB5550X9tkH/y8yMI433ngjHHDAAeH888/vOqE999wznHvuuWHhhRdOPhdffHGYPHlyeP311xPWqbPMMsuEK6+8Mmy00UadaHPdNmrUqID/Xy7H4K/A8EWGhz3jBoUDDt4zLLlUvIOCfx7XJ+jK2qFP2v75Xp/x7Sk+F4zP/UDYr7caTUPCFv/5Q8YGaSp5DSJPfaLVfJWX80s8S5wxlO70GAcG3zcB1VWDT5PrXiWOSFCkNRdwkQdzUd+qtozAMWFy6/GoJbRIpp18tZtIUtP4VVvGFGdk+mZ70jaKNFYUhexMO22pVU3mKvGQm/zQ15zVKA4VfjJHVPrxpD9IVAPEc9mokEoxX3TKRoWBtVEBr2kmTJjQ8thZYYUVwiOPPBIWXHDBFttAAHAHCNxZoX5gE+kFF1xQh8t4LlSgbFSYC0V2Id670brh8A/tG9Zbf21BsSzmNZTrpa6VaU2nv+MqQw2Z5/wdAV2uxz5e8hO3qkMaRYfEg07KBVnDURE5Y0iGwsIWptgw1E7S9DzTMpb6asLqJwhDWiTzr8cVGLmbj3biWGJUfUFhPskjOrZoOJ7IgoMYShSIp6QnNqDa8Vzt08Pl0GKAN+IkMYsJ2ZRxEtKcfDyYcp5iqftFsBk3fTXmuGALJsqKR82vfKHcUSH9IkqnVKBUoFSgVKBUoFSgVKBUoG0FykaFtqUphn6uQNmo0M8FLXKlAqUCpQKDtQK926hg74rVisH37qq3jvbcni6ehWATp2cN/8Yh05p27r1h+sU93zkA/BEjcUcFuzjo7ZiDpVHPpvWtSEZDS7bP1+Oey36Ni9g4KCWDGicZa3gXed97wf3hlu//XlQ7nd531OZhrd3XrFBu+vYt4f5LH6xgTYM1dlotbPMZfANqLT/Ju4Z1yBna7erd7UaFvU/VOyrkPNvHV07NPhu1zjG1h00e5x1yYXj57y/XTS3jMdutErY7dhvDaznVHyPRfNbk88LLz/T8LbWLLLVImHzmxLDgIgummTF4u1qrnQ/IWi4tKlRDW+PW8xZqjdOPjxHNBHk3xVBr87nGd49R5dfsqQY13Pmxeow3cGqNjFrzfuQ3j4brv35jeGtW/Hb3cpQKDNAKYIPC9ju9Lxx6xKSw4ujlNUt7OOP1iPydyTj2rAWp5fWC4yrN/4UKIn8mWS//1Ugce/HjP5j0f1ZJzcWp52FRLDchuvxtLjrDFBy6Ok+ZVHVeTNtyk3jJ3zJKedPg4jAhkc4DmSPpCUYeGCjAkBIlQoamZ3etk4qQQ0m0ogU/CplRh4hFtimncdXH+/t+8s5CEisPEVxZlKZ/vQUrYa4v3knD5ZyDVObBOIhLPRDwX9moINX8lzjdd999Ye219eKZgTLhWbNmhSOOOCKcccYZXae04447hgsvvDAsuuii4ZxzzpFvF545c2ZX/rhrAe6+sO6663bFn5skzAvfPFyOwVsBbFDYa9LOYb94B4WllsKd59zztzxB2/KA52f3fC4VwfO38NMzusIcGl+Gvg8W9ISNrvUjID205FtLcqOWyCU1iABBCNeir4fGo51ojg1E4pskcxGcdJez4iTXdCqJq3NFrz5PoeTcTLWlHlInDawerk427YirN01ClwFVMU8VYascnPXwubZg0dfnoVIJoYLGiAHqdsa0FCpacE5KjCPEOg6iGqgjDOPSVjYq2K9jPmnKRoWBtVFht912a7zb1Ne//vXw2c9+dsA+qp544gm5EwRe1/kDd8HC3SGWW245D5f+XKhA2agwF4ocQ2y0yTi5g8K49cdqQK6ftlCm9TcvnHG55MKZcxQswrRkjiFiy4TMs7Uapqgr63kyMiUDwEEEDl0eBkFEOXBFn1w6CU5dUETR/NRHrElQOeoR+9bR+XIk7uaWsUSOFtZDrIwJDwXMrr45Z3FMMgtYD/aUt9OGnBy0U4hwimVAUs75IyHvxrzh4ftJwcjaOF/iJJo/NciHOWE6yFlpOXQcHWyYkrXpwAtZS4tG+hjSJ7Zlo4KWp5xLBUoFSgVKBUoFSgVKBUoFOlegbFToXJ9i7b8KlI0K/VfLolQqUCpQKjCoKzAYNyrgjgr3x28H7+aQjQrn6EYFvN+XLixOHadi7w86pF+7lfi9UK74NeUdrzk+79ALw/NPvdBRdaERC4UDz9snDBs+rMJ7/onnw3mHX4R3RTseQxccGvY7a++w6NKLdOTBSClJtylnEmpKj/ymuzsq7B3v7rD0qv6OClWhSs2qpo6jil8v8n7oqofDDSf9rqM2jKj9wRdMDsMWrv4O6Ojj//W+v4VLPv4rmjq2W35ys7D2eNuA0ou8O4p2aeSvsilsTxJpvu2cKd6TUB/sKXYvfSt+TXnPwZyRaiV+L3Kn35O3/zlc8+Xrw6zXqh9m90KqUEsF5kgFsEFhh523jndQmBRWWCluUOAHdIhmf1cRil05CYgxjfygEIgcjis0eGonmq3jOPChWeIYGboV7eSaOlBOzuRSS3RFSxGxJ1fHcpjEV0fNyXJhgkI1LCnEcQVPBqRmA49RE/Omr8TECQfnrU6kY8Q5goUPnhWr4p4DHufdios12tHisE5sCHmfdn31VXfOF5qZnwXruuSwlSwsIeHGvrYpiuhSxyXvu9HHGPAnWfpxo8Kd5Y4KuZqDt4fntVdeeaVyJ4KBMtu33norfOxjHws/+tGPuk5p6623Dvvuu2/4xCc+Ed58s+e7sUF4xRVXDL/+9a/DGmus0XWcuUlEDX7wgx/MzZAl1lyqwCKLDg8TJ+0S9j9oQlhiqcWxIPBZOXb5pIxkYh8/9vzs0yOPbbKJi/qJgtOLqB6GYSzaQJ0fNdmm5IwPOg7qJZ6AooopCcOFB5DiVXzEojZyKO55jOdzFX4iZ406biEkfq/6RkYezCX/tiyeTlmz8Ekm3xQxaQBhbVRXHYmpPYlRIDrhR06CMRf4Mb9MNgy5q6C2sU9uHSeBuurWGk9T8LhFBVSdRLmjgpVmfmnKRoWBs1HhqaeeCqNHj255XTN8+PCAjQD4XQ3ko92F8SeeeGI4+uijB3LqgzK3dr8PTnazzTYLt956K4el7WUFNt50vXDEhyaHdddbS9b3tI7KQou1EYIRrbWC+nXT4spaSt/kpxpCiTaJkTjqCCni0KiuycaJjEYNy8OsypHYjp9ylShJBx2wJKYM1CfFd6IJMx8URcyM77nMVTRx0hjac/HEkFCbt+VgNsbI8m/rl1tEABlwaj4/cYUBPyRYGB1mPyFVbDqgH9ukaVzfkNOi7WIzf3Azn2jOUxBwGMA6rbgaXAiph7hFkyiAQq3Ylo0KLGppSwVKBUoFSgVKBUoFSgVKBTpVoGxU6FSdYuvPCpSNCv1ZzaJVKlAqUCowiCvQ/UaFbi8ewZW5+uZaa9n8Vbt1jrfBsyd75vg38YD2ZaOC11igngpEZ+PoRrsbTlMK3fg9cftT4crP/rrJvYKtM2GtsMV/bpowr331sdeGx299MtnadTY4aFzY6PAN2pkT7rV7U+9uNypM/PEeYZkxzRsV+hq7r36YNN60PmvylPDKP15NNWjX+cAXtgmrvn/lFnM9/q0/vD3c88vpLbw6sPioxcKkn+wVhgxdIPSm1nWdpnE9pzqnJ3ud78ez4+t1mvrUblcP2uHbjtNJt7d+TVp1rJucuuHUdTGu+/1t+t/DlZ+7Nrz+4utN9IKVCszVCgwdOjTsGDcoHII7KGCDQjz4IR0/EFRMDMkGTJjyciKe5Ce/tvC+3qZ/D8pXBcioH70x9DlUtMwJ9oSbozTRmTqg4lAeSdoyj8SNHXpqfHF0/hjLkA2Eta9inIYQDVIHRbJ/zYj8RLoBp5PadZTmLeqSeMrJ26QvZuUwmSoHaIwvAbQvPBtLw/zAzMRKX3zMXWaTQlI7C2qPeNakdj0mJkdNxqlzM556NieLpg2CSd5lowLrNLjbUaNGhSef7Pn19byqAh7Hn/70p8PJJ588R1IYM2aMbFJYeeWV54h+f4h+4xvfKBfy9UchB5AGNijsvc+ucYPCnmGJJeMGhXjwOdyeke35WS36HA+SPj8D5aFLTiteXxdEV8kw6eHG+FtTjsuFdmvFyZy5xgCjtpri2TimFBvkpyF51ngNuAiaEpzMryWe8CwCOYmsUao+zVoaTgXknBLNuZl8nIPxEifNUPKkHWmoliUZm+zSoGHkVk7rPBSBHoMglmpKNHSjLSNOgzhboSpTzvGUPE3Aj6XfiGtMjQQNHSNFOaxz99T7wpSzLzOwNAO9AmWjwsDZqHD88ceHL37xiy0PmQMPPDCceeaZLfhAA3DHqp122qklrdVXXz08+OCD8f2ufn4DvCVSAXwFykYFX43+62+y2frhcGxQGLeWicZVM66D1bUzmmqYMHThzDYqpIXU+aHr+KDKUDpp1a7ExmuG9BoFPBzMA13GEUyArAmuHE7D4jOPHB+yOnKSCJDjJbJAaov6AkeetgiIeBK4cmKubGnEmBrE0CpPhSinul4/WvRHXL126os9kxJuwTimtsGNuuSC4/vJh3gKp514hkV+rAcBmTd12Ipdk7G6AIFrs78aLYI2BnHg6mUxEbtsVJAylVOpQKlAqUCpQKlAqUCpQKlADxUoGxV6KFAx91sFykaFfitlESoVKBUoFRjcFehmo8J6+68bxsZvY69+ftH0YQbfQNOa2XtyFT9iYLTXyzrkVz88yfbqb0dzuvuce8L0i3t3RwXGoV41N6K9b+u6UKhr1zl1e7uodb8mbWC44PiJ23q+CGrST/YMS41eUsLVtZ+e+nS4/L+uFlun0/AlFg77nx3vyrDw0La0una384VgbzYq4I4Kde16bGjWOcCajrpvt37UuvHkm8MDV/yRw7Yt/ta2indA8EdT7LP3/2V46W8ve1pjf/0Dq5tHept3o2gEW3ICsfa00MKp2bvW7tKvnZ7He8qpbodvtzWr+3br5/Nr7MenvPqzXl27r7Hrfpzvc3/6Z/jVZ64JLz/zSmNKBSwVmNMVwAaFnXbZRjYorLDicpVw/AAwtbTK30rrH4zw7MGODwfpRze0CatppL+96M8+pGSEFrhpU49jtnQUf6dT5Zu6adW5SUtyVc8qhmQMz8IKUdPsMHvfTG+dC7mtfHDFKu6UBua5vu/jUBcJduIkXuz4eJW5RkOOz16zro+nTDureHTCj5xwlqDKyHp1XInZ7nNu7QOJB3O2uIwheMTKRgUt02A/b7TRRuH2228f8NP80pe+FL7yla/0a55jx46VTQrLL68b0PpVvB/FfvGLX4SDDjqoHxWL1LyqwKKLLhL23tdvUMjrmD6vx6dmSS7jthyYAXh6tlamOSrsbLHLtQTEZIlEdVGEOHQVj1z0VTA5mlVigpjs0DaucCjiYtLukpAucYaCuLozFwQCmmNIP51quBcCJx4pBoTw04ajYZQjRPEViWpOTlOtYDdoJ6loVXF40qWSB3PKPNCUq1jW4FiEJEbWFC8MTchbNAZ12IKqLDmbQ7RKeGlFVKJFVHGFXN/8mLPYo65IJ/23w7Sp08tGBS3lfHEuGxUGxkYF3B0Kmyofe+yxlsfNddddF7bddtsWfKABuEPWqquu2jiHa6+9Nmy33XYDLeVBnU/ZqNC/v95NN99A7qCwzrp2B+Ekr+tgZZ2FTZbPvIaSLjy3ZtKPdnE1e10jLcOQTxquHzHVd2qWB/nQxCEN+Dp0Z9PIJLHBn9ykFS2WRuJoB/qRbQ70A5m+gtHuRUQAumpka7DgXtvjDMh4KoGYyqprAfUY+jKmgInXOQZXfP1cyWdbj0N/LVEMxvxyJ/YSmOIAoSZbahs7aRFnLPKFl2pLq+kSJ4x6qFDZqMCalLZUoFSgVKBUoFSgVKBUoFSgYwXKRoWO5SnGfqxA2ajQj8UsUqUCpQKlAoO5AgNvo0J6G0/Kbu/HxQuF/ZXKVU7+/SintxsVcGF964EYPiYZ7WLTzrbu26RHrSYuddjWOcR926r3/JMvhCmHX1h5U9R7sL/cuHeF3b61M4fWVvUu+Mil4dkZz9Y4rUNcZL/W7rgDRzc5w78aJysSzwg2Klz337/NQJvexB+PD0uvunTNCr2mnOpxmjg1KRl2q6e+j/3uiXDNl65vEqpgI9d6Z9jz+7s5rDXOS399KZxz4PmO0767x/d2DcuOHekIrXr5d+Bojd2m2nTSq/PB9Ufd7m2+T786n7jnNvXb+fUWp3bdj3i9ZX51PvE6vz5u8qtj8IFeHW+KUefU43Gsei/+5aVwZdys8PxTL9BQ2lKBOV4BbFDYedf3h0OPnBRGrYANCvlDTAaXj+biw7TywR6MwPREqoDyWkI+0BOCchwD3aSFh7/TkKGzizV9OKh+9ZhZy7x9Q18IycH5kaStnB03a9JPskQCqoJWu2zERh2QjKp8N0cBxI5cTMRAzq2OI5hSlU8vSSNpkMMI2lJL2ujIGJ6VOUCpjjlY3zcRIyPZ4UWuE05YdFAfOzuucGhv0BYPhzO4n0fbvoZDcupmcQkTn3rHveH88y53mZfuYKzALrvsEq644or5YmonnXRS+OxnP9v4d9XbCay//voB3/A7cqR/fdpblbnDv+qqq8LOO9f/H2nuxC5R+qcC2KAwafJuYf+D4x0UllgMT7N2xOdhfUK35+O8LhCHgXxdP5KzaJBHDhXET0/KSyERUzW8EjAZo40dchRUZ2NIiGSPJvbF3kab4UUcPs4PNnOr4pIIrDmG9gWSE2Mr7meknLrdj8VHHW2amHhCm3OKBOaqEXJuLdo6ScfP+Xku+1Vd5SqWY5KraWe9nEvsmVC20r/e5txVT1UiK0pkbytOBfN2T7UCClfwlEvZqMDf0fzSlo0KA2OjAl6j7babf29OH0GrrbZaeOihh2rvUw/cRxc2m2LTaf2YPHlyOOecc+pwGc/BCpSNCv1T3M22eG848sOTAzYo6FLHNZb6OuZ6mVbV2ME6y7VV2ebr1kz6UQ1twmoaSdtxyIVN+vAxfa+VMBORJvJsCGo84IwfQ6WxkeMmLXgYVbxtoI0IAaaakOlr0mbPXAHgk7RcgB5x5dKDeZhU0mQMtIzDecuYAkZMHOGLl1iorwM5S+0a40XNVFelAlDM4tFe12V8tEwtYdByeCIIrGzxomMFxyD+QxbWYpyo1I1tuaMC6lSOUoFSgVKBUoFSgVKBUoFSgZ4qUDYq9FShYu+vCpSNCv1VyaJTKlAqUCowyCvQzUaF9Q8YF++osIa9QRYvh217rSsN6e0zVz3Y2uGgNdnovkB6k7I5NuMqf/Y3KvhcvLbHmVu7tp1fb3Hqez9i9dbnp/xbf/D7cO8F99eJLePtvrB1WHWblSPu41T1/nj1jHDDSTe1+NaBJVdaIkw6bU+T8np1JsbVGJnh8Yz2faOC1/M5eTzHqdbB4+x7v270Qpj56qxwxl7nhLdmvUWRxnboQkPDoZceGIYMhW5znL9M+0u47KirGv09uMiSw8MBU/Z1H6A261XjeIWmfrv5NuFNWF3Tc+o2jpvy9hh5nVofh75NGDTa4V7fczzOPmNg7LkeJ7dd286vtzj1vR+xeuvzWyC8+tyr4cpjfh3+8XDPm5TqSmVcKtCbCgwbFjco7LZtOPSIfeIGhXdHV/fBHEbpoWkfBMaxQPygDsEESwYgtQ/31GYKYudJPmAUQfFSmFJxlD50zInk+OAZzlaNSCmLZHlmoDaOJCjmY0TiOs64JgdtSSy12jG8bgMVGA4JKycdA2L+ahSc8elIDp3y2JgmWcElqJzSvOCfORjgx5zFJowKX0jOlunqpxFadU0JTUNMs4ozFYynshgglBzMWekZV2OkWlIVi+iYgvQjm7U2OMUwHHp3lY0KUtbBfprfLhD7wQ9+EP7zP/8z4Nt5+3psttlmsjljqaWW6qvEXPW75ZZbwhZbbDFXY5Zg/VOBESMWDZP22y3sdyA2KLxDRN3TbBzHZ2t5HrZnbT5HO1ye1u25WtcAPnFrjmldMB1mTl1bFgzWAErNKwU1QIIfxmIFUciSqWpwrAEEEyj5KMFoaidXiYZlTZphACXlA4MJqasOtK/s3Dc9pcCY5+D6aV7C0JPOF/3o7ASZF6CUE1RdDPEyIHOAwkdPma+OzWOvmwMo19miSeYg0pmHeDhSTB3amf71Ns9LlJy2apm+xxMkoOgLlE+KxUSYiyUR7p56X7mjAosxH7Rlo8LA2Kiw5557hksuuaTlEXPiiSeGo48+ugUfqMBTTz0VVl555TBr1qxKigsttFB44oknwrLLLlvBy2DOVaBsVJi92m6+5YbhyI/sF9ZeB1+OxHUVmtW+IFwqsSYCwCEYDQrIeqkGqChNQenzxNcZia/u5uHWdOcranEMiP7iRo6kIieGqenRxswireKTcepT2tJDYNWMfuaMToojdnMSihmTsoFJn57ENSHRFFeXAH0QrRKeOQGnwRSce65Z5DTl47nqTj3JxKariZKbc4ocNSXtig1my42+ziHlBh+TyZiEzziGOEQ/kisWn4PYhKh8cdKT5JATEftxx54cZs6sPq+LoZxKBUoFSgVKBUoFSgVKBUoFSgVcBcpGBVeM0p2jFSgbFeZoeYt4qUCpQKnA4KlA9xsV8C01fOstXnbbeL2rBzO3/UW6mU/tVl3l0I7KVzlZg7+V2duo4POmImI04bS3a5mb9yUGnybcY3Vd71u3tfrNfGVWOHv/X4Y3Xn6jTq6MF1l6kbD/WXuHIcOGGM44XnMBucD+7AN+GV599tWKf9Ngp69+IKy46aiaXhPTx4AdsetY9uvfjQrt42hE1iHH116TX+e8qXB53Fzw9LS/cti2nfjjPeIdIXABl4/FfN4OD1/zSPjNiT1vGlljp9XC1p/e0uJ4LYbuLm+yc5tzacWAMFYTL3vkHnkZyT1qEelrzvBnHGpyDBuxJh6wpsP7e7vXIt7XvBnDaxKDdhPuMcZn632JsW3yWyA+h7wefjFpSnhz5psklrZUoF8rMH7C9vEOCvuGUaPeJbp4uZHX/fy4JCYIOJYFcQDyoZ8R9GWLsshh6ydAXn6ZQ2XkoUz4NfsCz/kmTpao+CU46bmPKaGjk9A6oB8PzUHjCGAnWHM8cRaLeolRFVTA1NQ5+zkNuKSYSQVgOpIfuKYLI/ugsg9H9h01YfBLR3Tk3NvNV/XUQ3U1sbbalnfS9ROJMvBjftDmIRhsACKJFnLruPcjh5hKmEJsmIvgJCEGKHJScOqd94VfnnsZGaUdpBU47LDDwk9/+tP5anY/+9nPwgc/+MHw5pu9f03w/ve/Xy74W2yxxeabOU+dOjVssMEG802+JVGtwOEfmhz2O2CPsHjcoKBPrfY8mwqkz8t8zpZRPBman475/Bz9lKsMyCRfOidtPp37mOYXGyrAnxp09bnSxjY5utjw0/BRCz0V8FSNYUGFI/7qaXQM5AAtx4NexpVgCvU4Qs1kzYW+NRywQdJ1SaTYkUAY1FZcBcip62CMGPRTXtYUu5GqtpwYtalhdHol7ayFeHEUT05F+R53dmoL3+HUhJ0cYmgTFh3pKzhJ4idEInGjwvS4UeHSNC6dgV2BslFh3m9UePLJJ8Mqq6wyaC7unzBhQrj44otbHvgnnHBC+MxnPtOCF2DOVKBsVOhbXTfdfIPwkY8eGMaus7oIxGUur4WKJNxWRizHaT2urps08HWBrKQVvcR36QKDph6pkzD6sE1M56ca5pslqrGzY8w/kixoogukI7EzIxcnSaADXFo7mZA1aq/HELdM1Dzgj5omz0rehP38m/rizZygpoBqZ+mqtliRaiQYR2tpBtfkmM3a2R6dqIWO/BiQ4qFDHe2LCVzWLM3FYUL1lRKvio8idnaxRZbaJCEGUjOccNmowEqUtlSgVKBUoFSgVKBUoFSgVKBTBcpGhU7VKbb+rEDZqNCf1SxapQKlAqUCg7gCc2ejAgrIi2P9m37E8pt5wsxw8uMbgO3swHn0daOCj0Gt9q0mWd004d+89J5+Qjp/9ct4b2Iv4IJ28rv/kgfDzd+7zSfS2N/gwHHhvYet32DL+cXfkNjvPuue8Ief3tXArULLb7Bc2OWkHRLocwbYKe/kVOksIBtUdKPCDRVL02CvU3Ch/5LJVI3f7veU6KlT9ett3lo/9+sKN8TNBX+8ZkbSb9fZ4fjtwujNV4jm/DvwNZv6i2nhjp9Nbeee8K0+uXlYa3fcDcX/3SVzm05r3vj9N0vk/PgYqT622/m1hp69WkOvnnen2Mw716Uav5NvNfeq3+w/Rvpe697F7k3eT93x53DV564Nb7+V61WtQhmVCsxeBdZ+zxrhyA/vF7bYakMR0ucb/3eoj72EgxUhPiLTc1wkCGanhIPunsR8XwNCy8fLAeoxvK+GUT/ibKkrSj42DciVeQqmJ/FnUMkq4nHcmp/AeV4QM7/sDi/4K5Jx1ZOIERSWGc1DtHxfuCLltExXFJJ/HLXg5mMcaGWOKUcbMXWP0R1fWcRya96JSw3BzR/zqOAMCXsMksNoT+ISZytUs8Pf4To0ldh4RYinsfTVV3xwwgGt+M8lEu66895w/rmXq72cB20FjjzyyHDqqafOd/M7++yzw0EHHdSrOytstdVW4eqrrw6LLLLIfDXfe+65J4wbN26+yrkkG8LW7980HPHhyWHNtcZIOfAci6dZPVJHn3sjKIh7Gk5rBrDkaM/VEBGueDm7qotZTA0xxU95mpNq0FNDqR/jsvVrBLHsbbFEIPaTIFLNQWnxcUhFCz9qx44ChsMOTLRVQPti8H5w877iIVqM7x1TPJE3rusDyZyoYLER1nUrOGyaguahPPiKxZ0cFo34D4fn+XjMW3giXRWEX+Znm2DCV3FayJWxxJfw6QQ7OQkUCVMQTTmJ2VCZgMxBTupZNir4Cg78ftmoMO83KuCD/OOOO67lwTK/3Q2LE7jiiivCbrvtxmFqx4wZEx566KEwZAi/uCaZSmcOVKBsVOhbUXHHzcOO3EfuwIk7ceryhjWSetohDhR9mtNaGkHB7FTlk+3XcuorpnxiyifGGGwlBzlpnsTZioqF9FjKArmKuMVxYWUWAtt8og1c5uKoMFTmzKKYOzzNL2uBk0YaXvSzrhBaOLCrrjpV5mXJ0W6MFFt8FZQw3lcAaEMDP8Jj3rSi9Rj7Kmrhqxw16TygC3F3tMZJDhUfavucgbXqCdiCI6xw1RwHsWOH9OJYIIfDXDYqsEqlLRUoFSgVKBUoFSgVKBUoFehUgbJRoVN1iq0/K1A2KvRnNYtWqUCpQKnAIK5ANxsV1tt/3TB2/JrxQvF8cS/fG0uQXCRsb5x1Ua/qxcx4Dy6/CZc183tzTbF9GO9z9zn3hukXP+DNbfsjRi4a9j97n0r8tuSKgbWIl0db18+hQnUXm+OtRx5pThGqv3lJTlOb/KKxbcyoef4HLw7/fPz5JomELTBkgTD5zIlhxMgRCcudPEfm/foLr4dz4l0VZr3e87eo7nXKeLsrgCp2lXcO7no5j0dv+FO47r9vcLbmbstGBfwOTKZtzZql0uO+t34pYNTlY+S2U/4Q7plyX5tIGd7m6C3DajuMSbHTm9ZGuelbt4QHf/XH7NCmt8Nx24aVtlixjbUdnOvNvNvPPXP5GIEqf9ft/Zpj0w/W3vnmPJhzZw3y3d/jAHmMtJ83c5aZ4SRH32vW3e8Jf3O/OeEmuaMKY5a2VGBOVQDfkIcNC5tvuWF63swvD/gaw1ZMWTuRScb1uVIgw/PfuDBNTBtnEy0VdCieiCCZW1HVscGIjhTyc5YMxQuUqk2HogcD/94dO2HQFGecnaZNAUahUMNICZexcajlJBGd8uKDE7VoY5sIxhGd5G8jbSQUdRDA51uJUTPIMJ4y7HVNXOKLSgtPtWu26CZzEL+sARYOxpS+INrTHJgLW18fOKuD6Ls4ddwUMz+lkToxD8QQERGFJu6oUDYqaI0H8/mII44Ip5122nw1xddffz3sv//+4cILL+xV3ksvvXT41a9+FTbZZJNe+c1r8rRp08J66603r9Mo8ftQAbxG3mrrjcPhH9ovrDV2VVHg8zsG2pde6nP9Ss/QeGpOREWThjxtyymtNRIkaef1QxYBdecykXSzvubEcb2Fo6w5mrKEMsmkxTiJJ1wbOX/OIU1N1MRbkhBdGC2ANVVb9Mk4+pmvYdXagjse52jhK/MQb5PMvKhGA3PWMDJKPPEz52ihT3W+6kgbJ8N8KZs0EYG6Eg26ZNGmpKTpeeILnkQQC/1FxeFqRDh1yh7wNxwkpylDFWrBYbv7rvvClHPKnZpQi/nhKBsV5u1GhVmzZsndFHBXhfpx3XXXhW233bYOD/jxW2+9FbAp4U9/+lNLrldddVXYcccdW/AC9H8FykaF2avp8vEOnIcesU/YZfftwjC7K3ReiuNqyXUwhkFfhtJHTwHB7OT5yIxjbQXBSQ5Zs1WCkDioVGWljjqCSvzkR1HRULsKIzMBObREavNhVO9fjxM5DAO6RImAtobIADzrOJ9qHtGeKXCu+YDdwFGixaRAZFpXGuZU0/QxfH7ANZTGUy0VpC6T7caWfEROdZK+BLMT7dLSoAPOXapAiSSMWilfeLGb5lPDtVDInrogu1j0hZmiQnk7fOXYb4WZM2eRXNpSgVKBUoFSgVKBUoFSgVKBUoHGCpSNCo1lKeAcqEDZqDAHilokSwVKBUoFBmMF+rZRofrmWL5QNr6tlt5M67la2a+ul32p146bmfli8N5uVNjvrElephf95guHmwXAbS1OvE+AvhnZ7NQWRT38G5R14p/vfDr86jPX1OGW8eh4Efv28WL29kdr3r/7n1vDA5c91N7FLKvvOCZs/ektK7ye8q6QKwOtNe6ocP1Xb6hYmgb1TRLg9LXWTfrdY5q38t+WTQq///EdPbpv9tGNwzp7jRVeU95Xfvaa8NQdT/eoM/67u4Rlx47skddKqObdavcIuK2Pbc/oTX92HyM5Vu9zaqp11ptTvdmvdd9r1nlO+Du/+bu3dXyu6axQrKUCfavAWmuv5u6wkP9GdN2zj/rin7j+lfO1hwKC2alpnQTG1xZUgJCoil9CY4ex1GBm8Sdf9eqOpofpRxO5MkzBI2p96lbt8FWLnJlLhiGdNCwpSGRM+gLJifEw8P3MyHhlXkao5hFHCoiV06rk1CZOo7Y6yjQ0nIibdmuf8TxXMdTVUHbisGm+YjaOi2D+1GFb1aB0tFa1e4hNv2repkHfqFk2KmiFBvv54IMPDj//+c/nm2m++uqrYeLEieHKK6/sU86LL754uPTSS8PWW2/dJ/954XTHHXeEjTbaaF6ELjH7qQJ4nbzl+zYKR3wo3mFh7GpRNT+vMwTXiNQmQ/W5X+D4RC5P19LGnvzYEzj9Ypu0lCw8mMlMdgGpqX60wYSDY7YUUWnzVSrYaR0TyBaeOpdafl0iB35it2StAaihqZkMOUeJaSdoMA5xUYh+dTwikI+HilIaWOaSQzVtaZe2ws+8zAFGdadtkDTI21zpJ16aoFm0SfbooD52dtyUl4q0aIuHi0kCayVuAFU6Nq5vGIonXYtLmPi0slGh8nsb6IOyUWHeblS4+OKLw4QJE1oeJmuuuWa4//770xdztBAGOPDVr341HHvssS1Z7rXXXuGCCy5owQvQ/xUoGxX6p6bYsHDI4XuHXcd/IG5Y4B0WuKbrCojl0Hr59QUxMcR101qflfjZWkoF2LmWS58OkacScrZ46sXXB2iTr9LE2zyFLH2z0Q8GTaOqLfGZH9sIShzLi7B4xoG24qnJGd/oFkc1MmYJEbCW+dVb0uBFmwqrTmNOnksBw5IG8SgDjDppIjUN75e5EGEeWaPKVTvDSYuY8DNTZkBDRz4nYhIt+cSO/CQghajy1d4uZ9FgTEuobFRIpSydUoFSgVKBUoFSgVKBUoFSgQ4VKBsVOhSnmPq1AmWjQr+Ws4iVCpQKlAoM3gr0ZaOCfyMNlcGH/zjquIAdTvSr+5qce/Mxx6hzvTz9+nWjgr2PKHHtjUBczNxyNEAVjtMRvM6nvR0eneTN0dj6ulViuME1X7w+PH7LEw5p7u58wvZh1IbLNxuZk7fG/P75xPPh/CMvTm/UerPvD11waNj3jL3CIksv0lXO4utipvm6ej8Sv939+q/+1odp7O/1o+rdHJyE8hnH15tYZKTYfFA1RjGwya8lYOTGWA9fMyPccNLvOqmJ7b2HrB82OHhclcc4UeeCD18annv0uaq9YbTvGRPDYu9+R4MlQtSTrg7qj22gHUvgNFIQX1OA5LTBe1VrryfSczlvzsXH7lggJByPJr+GxwhoHeWcjui2qWmLtPPrtt5TfzEt3PGzqRKmnEoF5lUF1ho7Jn4T8uR4geHG8rehn8vZozg+rvWhHcfSSYDiEWx6XQIs8Tkxca35wwautdLgFA9gou38UixiwlSrINW9AABAAElEQVRyspmvJRB1hCwoNOVIMRMgdMuErkrFOfGpZbmZu+iaeDWPzDdqlFIi82JLO1pwyNKOjbQxiJxqLuJvc2Ys0Y6+4g5t0xFc0ZSX+DPHxEsd861qpDiRlrMydbhSTyE5qw912Oa5SEQLK5peu4ZDkBzpmx0oD6kphi6XqXfeW+6owAIN4hYX/Z9//vnzxQxffPHFMH78+HDDDTfMVr6LLrqo3I1hfvnm3t/+9rdhm222ma05F+eBUQH8PzTu2HTEhyfHOyxgw0I+uFaklqb43EyMEJ6r5RlcWhDwI0iieEyf2pUHApleF33ggoGqTkmPY7YUES3zTWTqJJJGrHOTlvDVu4ohEcO1QWIKWX4+Te+b6ZHvSWYA1ooDA0GDWmjBPNf3fRzxhAB+2sRUjpzF1cerzDUacnz2mnUlnp7MR/kpB+RjgSttxMip4yYUGzpnrkqJh5uDiKU4whGr4XE+06ZOL3dUYE3mg7ZsVJi3GxV22WWXxk2ZJ598cjjqqKPmg0dQc4pPP/10GD16dPwG7pkVwrBhw+ROC6NGjargZdD/FSgbFfq3psstv2w4+LBJccPCdmHB+BlEXv71NQVXS11vbcSlFWu9QGRpbuB6HWYsGlmC5MraCxAUlZVVXNf6CHDNVyM4WUz6eQiy6Gc8sUU8jYRmo9hHL+cuVNEymmam0jkfoMSQU0NfkhGeGV0/zctIwoiCbBVuzYt+bM0dM5AcKrhCtbnAQ6I0zIV4VhW2wLVcOHmoub54Slw5WSTTk/kRz3ren1JpPl5B8qjGo6+YzJ7nJ8lV8oNu2ahgv4/SlAqUCpQKlAqUCpQKlAqUCnSsQNmo0LE8xdiPFSgbFfqxmEWqVKBUoFRgMFegm40K6x8wLowdv2blDTFfE15YyzfhaGu9oD690yYUz8/c/Aaf6uqVuHzDDo6MxzhsqYeNCvdf8gDhju2IkYuGtndUqKYb3wLMgL+gO6MNuXljUyaYXp3Di48d3hKbnAbNF556Mfzy8Iva/r7osvjyi4VJP91L61nXc7HJT23kXv35a8MTv38qQe066x84Lrz30PXELDWrx/GOLmbLfI3X540K8EdsF+P/s/cdgFYV19ojKCCKKHaxYTcKiA27xgKoSLGgaMQWS14S8+dpevJeNJYkJhqjsb0YaxJRolGxd7EXigJWsMdYsQap/vOtMrN2O+fcAlyus73umVnrW99as845ezb77HW2UJbKM/6r3nAgyPFl7Mzd4gp7+e7p7sHfPhRcV3X6jNjMbfPNrVhdEvc/vnmj++j1j6vMg3zUjSPdUl2XCuPQ0YBEoHFXvq+By792OY7AbbF5TMlc1DebeUDejyU2fAU7wRkIU+X5LMBycwCF15Qg9eJuxfcIhZGPGcKmxq0cxq6QM8XQJGXn8Y9d9KSbcv1zVpr6KQOLNAMbb7KeKViQJxH596q+veM5gkig8ycF9J5XkMyA5HrCoLMCHmyCpUYwIgIhobGn/3WMFn92bHjRVR31g04/kWwPEvDCj1ApkuyhLcgFz43yVPkTD+QkeEOHPZfINYBM/DpP45sYgj1bqY22BOcZsk+dDPn3WrJnElUJE82f+x4mOG2zcuiZQ+VoSSZiyTKpCep3eQvGi9zolZtDMHZ5bj8mbamcAiL/2AUuwcoE3YRUqBBy1J47u+++u7vnnnva/BRnzJjhcNPe448/3iqxdu7c2V1zzTWlv1bcKg5akeSmm25yQ4cObUXGRNUWMkAFC74QctPNNvTh+CM2H4z1EEwhiojXkCgJWBzAzUoQcSSHgfJyH3jpeZW1xJDHul7peqMGig7yGlzkgyakILGmuEQmgUReROs3TkRmLgJFk40bMbORqqjVHXGLuxC3KDE2pioVv2ykerRZey/hP7KzutAnveBkTuIkxBzFHofNNhofxBGY6ZON2OlcmSKbl7JYlTO0xCM5sZzSZ7Wy+1EmJmixZf0GCObi/0+FCpylxWWfChUWXaHC9OnT3YYbbujmz5+febt06dLFvfnmm27FFVfMyBe3wUEHHeTGjBlTCDvduFBIyQIRpEKFBZJWt9rqK7vD8YSFwXv4goUlyQnWPlnazfodF/ugDwsmx0Zygql1lCshq1kfUMKjY+VHS+cCqrf+BEwYSY3aY63nPtvTOg8MDVUmsXkhubHcyicybqJdwWeOV71LECaHEonH61bkYmVGbmJTU9WHNjjzPhRPcXlPZKSW0Afv0mdB43K1z/sKxIE3coqNF1B+PJR6YhJiRriiIwvV6/wghN4QRz4xJkOChR3Bjc0pP/+9LzybK8jUpAykDKQMpAykDKQMpAykDKQMlGcg/Xu/PC9J2voZSIUKrZ/TxJgykDKQMtAuM7CgChVi4UE+bXJ1zovNtTV/s3y8Y1Yv1JXJwGagGXLla1Khwko1ChUy7LguGGOvuqGb4svZtcbQ+lY+G4PK0D5xyVPu2TFTrai0v+1xW7vND/xa0MVXIIgqO/+a8La77Ud3VepV0aV7F3fw1fu7jp07kqgqZsVra+drbVpUqKDkDbTWP+A2hlrm1s7a6DtnyvVT3eMXPVWLgnRbH93P9T2kdyXun/811n3w8oeVelUcOnqEW3qFLjqsbDXuspitUVPeI9auVl99K8bGoLKy1tpZG8212iyImMFt/WNsY8C4arN21mZhxG19a3w2hvnzvnTjfv+wQ0FN2lIG2mIGNtq4lzvqm/4JC7tuS4VI+rnR8waOmaWQkVxBMqEgtxP0GPp8CNbyZczB6e2Iw/BBqDbaEtBitC8tmoglVj8mqbQRqP4CXlSFmMne8MKH0vhOBq8ayPUEivBKooY5vcVW9cWU4hYMZ44V5A9uKCZuRcMNRBIGQJn4NDwC8CBis7FGMmLBjjaNBXaWO2iB80qCa0siJsjL87zgCXNEPwK4zzQqBSAbh/c5cfwUN2b0WFClrR1nYLPNNnOTJ09u0zN899133cCBA93Eia37lCX8eu+VV17pRo4c2abn/+c//9kde+yxbTrGFFzzM7DdDlu6o48d4TbdfCMciDPHZbB6kTk+ez0vAF6IPxpE5yqjlo0jQnrQMUnGGjLyxcQBY0HBX56jgo+CpDBgwGEGDgyDjGOiIcUhCosRH0YEI6ZQ/xkzQw4jv+m8tR/gpsMYFqhLjKytlKvCfUZuMeoDARblpCV79DwiNNLL2Fh722cjMTU5iBg4D9TUUV2+hTLITJ+NaE96jc8Eb7veXXSofACgnwoVOI+Lyz4VKiy6QoUf/ehH7re//W3hrXL44YfTeUtBsZgJUCC75557FqJec8013SuvvOJwfpa2BZeBVKiw4HIL5lVXW4mesLCvf8LCkr5gQdfNsCaSe5aSzHezOh7nZTBTfOgTl5dLS42eD/gB8NDl7QK3MQwy4ImId1HupcpNXYuCDdZ68WXs0Q0c0INdTIMcGLEhmepVSia0IxTPSg2k9Y3yaQtNZV/MVB9a61PmC5F2Y6RZGes5cIstk6svCYGbijmqfeQMgYe5watyhhYwb8QRoQ8Bb0EKn4ZY5SQSeTADlhKhJKxJhQqa1dSmDKQMpAykDKQMpAykDKQM1MpAKlSolZ2ka80MpEKF1sxm4koZSBlIGWjHGVhQhQpImS004BSGS2w0NNfjAtZepLMcVl5WqGC5mlqocPBfD+DwSvb2Jl69aEhx8W+1k4WVl1B4UbxVOvbkIiMZWCkEnKcq32RSsZv7xVw3+rB/uFmfza5AsLhjp47+SRIHuM7dOtfAcVzF6Di+f54w1n34yowa9qza8XvbuY33wa9V1t6q5mvl0x94xd13Rv0vLYddtJ9bsdcKwWH2NbIziu9J6yeLDzSlnSq7MvnTl01weH/W23Y5aUe34YD1+UJ0AMe4b/vhne7tSf8OmqrOsIsGux4mD4qzsUGm87VyzkzMj9pm29rvEfveZzvmy/qp5yN6rLKrkkdL24t5jD2NTmOxGpVlixE0Z5a5ql8VX5W8nCfGFHvxtWObrAayRn3MmzXP3Xv6g+6Nx98sd5+kKQNtKAMbbtTLHfnNEW4nFCz4k4J4juA/r/znW/8ptScHiJ90ivGtbAEmHdLYPnB+rBbgtX3iVby0AUCmjFYbchs4vJQUiJccSUsogcKf6o0chmSD8HJ9gYk6xq/4YMhAzRX80KaNzkf5ZKx4BStM/ak+tFW83oBs4s7MX+esrDQN71Ll8G770Ecsx2ZkXmXnxy6DRODC53nyeqZWeZ4r+g0xiCh48GPlpMiDifg0wlSooK9e+267d+/uPvroozY7ybfeesvttdde7rnnGn/KEub08cf1n/qFSXfs2NFdfPHF7phjjmmzOcCF/FNOOaXNxpcCa50M9N++nzvSFyxshoIFbHr8xnFb1xVaF1Rh1gC2IBs63sOGOMLR3xAaviglH9EN1oToh6g0IB74kTqJfGIBhNgzJoNVHgOGHu5IpHNUvbQhHnCTB3ISbCDSkKmvqADWmKDlflCZDvuhiIMjjZ9hX3Khqh9o3MyY5VcfCMPGznLam3iFmRuiszZVfQL6XV4f80BBMp+AFZtvoQ4y0ycziSs/X52A9UdQ2QW57+C/ZyZMddddkwogKaeLwS4VKtS/5rcgXsZZs2a5tdZay7333nsF+ocfftjtsMMOBfniJsCxZpNNNnEvvvhiIfTrr7/eDR8+vCBPgtbLQCpUaL1c1mJaZVUULOzv9tnPP2Gh01JhjfWrLf3BFp8FXjJpz3SkZoxoSW7XVLKlHdsFa+XzusAtfXIbSFgPCg4gjgMX6TQCjgdg0mNouJjG66A0MahcfaAlBiLJcpBIbVWvhjoWnxqVqjlUAVEI3M/GKPEB7DdFU56El+Veo0rgVKdijaEMI4ZqAiLuM1jlgRMOdSN+dhLm53Vk43fGHaT6RwDolDPvL1gKQRirjSEmHVMTr4ewX8J4rWJDx7lUqIAspS1lIGUgZSBlIGUgZSBlIGWgXgZSoUK9DCV9a2UgFSq0ViYTT8pAykDKQDvPQHMLFWIRgrlY1sRcccEB31irF/UaoYh2fJXOXKMj89YsVAAhbvQVTyE8vfnXXmQMytIOz1NvIy7aRY01b6qfF259yT187mOWorS/4V7ru51Prvclm8YUbze3cb905zT/6+uPlPJb4fJrd3f7XzIkklhlrl8+X5U615RCBdygrzOwcbPLqNEQ1EsRq4jqFraNvEceOudR9+LtL1cTiWbg6Xu6nluvnsPFmO859QH32sOv5/TF4cAzPc+WeR7GVc23Sl5kh0Rjir1i/hSjV9Vr+y/3E6Xl8akUF/KzfqKl7WlMTYtbvTTmw/qDn8beI1mr/Ijj1uiLcUSNtawX92xf2HTX/97n3pn8rjVL/ZSBNp+BDTZc1xcsHOQLFvrz05b8x5+OALLLnFvIoYE+N4rDEUPkYbJeEETaz7ceTBjiAQd1AgWUGT9qHxEeAASA/n+/0d7YsYx11FecAINGOjYGO2+GM0goQMcxUy/uYEcxEaAGxhJx5DoNmUdgCX54rtEXueDgaPKqz8Quc5PskLHqbQgqY85gFJypXlsJOcRKdszOe6FQfGyZUmNlOw+mPzZSrKHzasYQnmFIbtG/mVQqVOBcfxX2H3zwgevRo0ebm+qrr77q9thjDzd9emNPWcK/Df/4xz+6wYMH0y/1Tps2raE5we4Pf/iDO/HEExvCL2zQqFGj3FVXXbWw3SZ/iygD2263BRVCbt57YzlG43AtB25p9ZguR3GONEAyUq/zY9IpwPDJHKGBD4Wpv3xL8EgDIxZpK3wZn8oLnYeTF+FgkfHLAGJR3xwUXEWj0MvwsVRhZX6Ui/zamMlU40ArHkLjO/QnAg6ccOqPgva7TJyAewBjoq2Os7aKY/KsjtnBbflJauKyOvXBcbM9MQuxYhVH0YFfoKoPluqH2iDl+TExCZWPB5Q2waRCBZO1xaKbChUWTaHC3/72N3fYYYcV3iN9+/Zt9SdLFZwsRMHZZ5/tTjrppILHAQMGuDvuuKMgT4LWy0AqVGi9XDbCtPIqK7pvHHmAwxMWluokTwvBWkoLrq79NJBFEw0vtixVjPFm1ms6z4DKyHQNF1Y+dwAlO2UickE7GkOneAYoJxkyRhUkimi1ZHoZAaOMClWZjG082ieV6iUP6hZtxBEZ+xC84gImzJcBOlR4ERf5lSvjE4bIkxLxUKDKmuWIUNgx1NqLsTfCX5YbMmyK56EKyQRKggWMqIktQH2H/oIAnoScm4IfUiMe0oi97+skxCwVKkgiUpMykDKQMpAykDKQMpAykDJQMwOpUKFmepKyFTOQChVaMZmJKmUgZSBloD1noOWFCrhOJhfYmpioWOzQNI56dq1RqIA56c29DU1L7w+24AbSAkiZqaUpBVQY3nD8zW7Gq/V/mXXvX+/lVt5kpVLnjc593tz57rojrnezP5+TCbdsMOC03d2a2/QsU7GsgVwB+MoDr7r7zqz/peWwC8ufJFAdgGjqvhiRodE8BQvPfecv7nVvPvFWEFV1hvsnQqyw7vKkLnupx539iEOhSL1t1x/t5NbfvVcW1mCug1FJTpo890CW65Rw0/X6KnnOvOawNTiqHJRxl2Cr8lT2mpJ5FW+d1wxfctQ9XpVxe96ZH810d/z0Hvfh9PpPRymZYhKlDLSJDKy/wTpu1DEHul123c4t0cG/2ekzgy/2zIdHuvSloPa93iDCXIKd6qUNco8kO7+DzMqJBHIg+A8gxgcPIFA7ozN2gBpN8OEhoW9JKQYorb7QJzXtCjELNvhELD5Gu+lYW0Som0IhiXrTL8uBwZKN8al8zG/9cN/qS/1pYOLDYkzYIdYwb8KLV3GitmU+Yad68AaeGHLUG24v5DByPtizc6lQQTPR/tu2+Au9L7zwAj1J4Y033mjoBcCTES655BJ39NFHEx7/vsSTGKZOndqQPUBnnHGG+8lPftIwfmEBt912W/fkk08uLHfJTxvJwDb9+7ojjhnhevfZJB7DzSKA437+eE+HfT22Z+bhkWqLdUL7goEd86Ej64jBBTyAsoUu/AlfkCEyyPJyiNgBsVDf92CnHDRQH8TBg6AXPElzfMwELsNHeHigDrfoSmwkDnESIcdICoVjPixAE01VrjhulZtwfmfxisxgRMgyjjXaqEWMWW01V8hjkEU4yfI8iostG4ADgbL36MvQsQ8BKC7YwBH9cZuxk/iemeifqPD39EQFm5u23E+FCvWv+S2I12/nnXd2Dz30UIH6wgsvdCeccEJBvrgKPvzwQ7fmmmu6mTNnZqbQoUMHh3PADTbYICNPg9bLQCpUaL1cNoUJBQuHjhrmBg/Zk56wwAsu1m+w0M40cS3Fypxfy8lChb5lilwbWWn9pnVf3MAeRmShrpSHlLIjGQBsyHuxFZmwkEE4t8DI8qkhqNhxBs9w40PwFksGoBX7fKt65dJYYKGbhkwSE1/EIuyIj3YhoJhLr8xCo53lsJggN77zPiJGNdmYaN5QeXfqETZqV+YvkyuYZkBFPxk1BiJQnmiRnqhgc5H6KQMpAykDKQMpAykDKQMpA9UZSIUK1blJmtbNQCpUaN18JraUgZSBlIF2m4FGCxU2GbxRIQdaMJC5yFZA1RYwBy7q1cbltbV8N7lQ4eoDMjfs2/nYm381xLL7fSk+o6jisPOgi4xiaEwtJPYtQAOB1sjfnvRvd9sP74o2bai3Rr/V3SD/6/5hM3FrrmyugdNpGmiLChU033k/ISbtWIcVgWjMUFu+spiV9sv5X7q/jrjW4dfr622HXjvCdVmus89BZLRhjb9iopv492fr0bh+3+jr+h3eJ+A0bhszlNFLgGY7xrlyAJDnUSONu0qvOGoNdwgECiNXn3m+5sSd57CxtDjukph5KlGhMeemGMOIUJJVzV0NNGbmyxkrSFur9oF8+vZn7o6f3e0++denikhtysBinYH11l/bjTr6ILfrbihY8FPx7/PwGbF9zFLG+fMP/cxRIrzSwzw2sGS+WISO8OAyRNwlB2yPKIiIWInP70QWuUkLX4LNaIhOJMAArLhooBRBySoGZmxgLPZEpRxkGXWZeTHQzDUSqDkk1oacEF2cF2iwWRz1gVMi0hNMduxL52NgGRs/sNMKOstLhEznsRQct1DwkCHiRG3VZxgDjI1somGIIKiNTmQwYj7WkVgdeMoJT092/7j2FqJPu/adgYsuusgdf/zxbWaSzz77LBUZvPPOOw3FtNRSS7krr7zSHXLIIRn8e++95wYOHOgmTJiQkdca/PSnP3Wnn356LchC1c2bN891797dff755wvVb3LWdjKw1TZ93JEoWOi7CRYoCkyP8boWiJBXBI8Jh3mZRsTp8Z5bnSXwwJAdqVivdtoqMeGCsdoZv8QFDkYGvHQCH/zSfxSA0kNIG5v7Af+V8pFXwauh2ol79aBq4Q5GNHcIlSvMJEC8hPqi8X1WqZwow07nRzZ+p3GoFfmKwqgHVpjRsI9AG+NUWwGQDeGNBY09h2KFRsexZUWeQ/XBu/KLi+CJYvYo+Mlh1Fa5J02ckgoVNCmLQZsKFRZ+ocLkyZNd7969C++Obt26ubfeesuhbU/bkUce6a644orClE4++WR31llnFeRJ0DoZSIUKrZPH5rKstHIPKVjYy3XCExZ07QSh7ZtxbinPru1mHfbmtNk1HDIag9sQcZccso13btSw4j8SgoWG1EKFkXKwlgG05qNL5qJBo2MReUmwt31SC0a52B9QsGEl6RQnMtIzCPuAJec0JrGEH9ih0T9jI1jDbecQ4pAYDHPJvHJcYQ4sxz7yGUKdn8RHuEyf7WEb7aOMe5iazi8QsiwCqJfnIMsQDnx4mM2HH6YnKmgSU5sykDKQMpAykDKQMpAykDJQKwOpUKFWdpKuNTOQChVaM5uJK2UgZSBloB1noJFChb4je7tN99u4MgtVRQNV8jKiJewNtHKHsl6kK8OrrMxHswoVlNC3fB2Q9/amZr0+mAnV2FEXSgHqZVfLYeGqh6wKY/H1+vf86gH32sOv14MtMr19SoANQvNgc6C5Bs7muyVPVCjzY+NoSp/j431Z3DZm5X136ntu7H/frsPKtsOSHdyRN/vHzXsSjRlg6+dV/zrf61/vetsq/qkZg/+wd4BV8Wm+y+IOxlB6YBVHwBGsmBurb2pffdocaMzgaotxc3zFPGjcdWPGxDy4bO5Q6aZ6jG1+VF/V4skrKFL4zwfZX9Grwid5ysDilIFe66Fg4QC3227b0xMW8DkpnFPI50u/6yvo8QH0W5lesYTwAGAYx/2MITgyXOSYpULOnshKidgC3CLWDiTwT3Kioh2jBCy0JNNYMQhsasdClostGQFrY1N/hFcg4hACwqMPH9GWBJDQn+JFaoOECBj1aXSmSyAdK5ZMVcgD7CkOBIh4sFk8SyDEH+1CS1gBqA1adqGt2CmROFE8c6gw+iC5iZUQsgti+PLAialQQbPb7ttjjz2WnkbQFiaKJwcMGjTI4Zd2G9k6d+7srr32WjdkyJBS+EcffeT23ntv99hjj5Xqy4Tf+9733DnnnOP033hlmIUlmzJlitt8880Xlrvkpw1nYMute/uChYN8wcKmPko5vqMXDt4sjmsKTyajh0iO8aQ1fVpnSF++ZhCPd8srBFljwDRkpxoCRZzxEcEIg411j6HtM7Pfk9Bzo7U2DA48jJcYcjqSikx51T/GZf28jY6Zxo+oo614l/jUB2JXbsWrTuUYBzPpZH2xhcWzDcjxR4EIyIxZTXJrq/3YEhuzCJX6D5pSOWs5Bt8HxsdvbQXBSq9PhQrIyOKzpUKFhV+o8O1vf9tdcMEFhTfJt771rVJ5AbiYCXButv322xeixnsPT9Tq0qVLQZcELc9AKlRoeQ5bg2GllXq4kYfjCQt7uM6dO4X1s2xdD+cJ3rGu3xwDL9BBT+uwaIKQbXQIe+3T4m3XeJj6cVzLFSt+mJowgvKNidhwwYfyaEvmgiFXoa9+AitDNVDDpSGQPQebwRKl2iECFgiGrRVDLWuCgvLDo1yuBcITY6vgh9KgVpn8GkjkE6H619dUWyEShyYn3sDm0tqrLYVnnBIeTALO2isD6y2HGgSE76geEyS5b0/9xdluzpy5HGvapwykDKQMpAykDKQMpAykDKQMVGQgFSpUJCaJWz0DqVCh1VOaCFMGUgZSBtpnBhZUoYK9uSRcTKuRwpYWKoBa/TS3UEGvJdpYlLNwC7DeZRyuGvoAVKbzFJ1emKSbiPMYChyXIBmcwXiRypUyow+2zn323uduzJE3OPxqf1vdNhywvtv5v3fg8GhuvuvzoSmpm2sPb7hQ4YLBrkevFSK5SYr6Kc9lNn/2fQyKlrxHxl/ln4Lwt/pPQVh1s1Xcvr8faCLmro37s3c/c9cecUMBkxcg/pF/P9B17u6/ZDS5Bk75oNDXgOx1IO+/sjypH31/FjACUB/BQ45bedDmc42PBL0aJm7lq4wZRA3GXYgJtrKpn8K8hFtxaPNxt+Q9gnzm+TgJmBZlg18tzaMNxPdL42azYA+T96a+7+7633vdrAae7pFzkYYpA4tVBnqtt5YbdeSBbpfd/RMW8p8b+TzrZ5Y+Y/J5kaOPHE9kyh6oamp1jFYU+AxqP3bi5xcE+jklKRMFXvIkBBkfUKgP3wGEokEbHBqMYMnM6MkGQr8FuzwHq4OeqDxHoAx8HIcGpmLgArfvL8GRkkwxsIl9dZi1sxwRG+2y+hAdSIiQ9r6vGosXjwIVPOwEnLeBLdNqSzNQGmNnOSIZRaFDJooxogczlZOvL93E8VPSExVihtt1D7/e+8wzzyzyOY4bN84NHjzYffLJJw3F0rVrV/fPf/6Tnr5Qy+Czzz6jQob77ruvFiyj++Y3v+kuvvhi16EDHo2z6LZLL73UIZa0pQxoBvpttTkVLPTZAgULvMXjt6wNOKZDheO5YGyjeG0ZKliyVYK4NihWW0vMPrA+wU5H0WOwIUdFOSyAYcvoMyCJlnYkEhfSVytvFxhAyNbEaw1YzLE2pS9YzE/9MHf0o5DQImQEYmJRnc1JCC90vAn5qeZWe20zvOpPhb5VXFULqHEf8VXxh0nJ9OBTYxYiCQPUpJs0cap/osLNPE77Np+BVKiwcAsVcK7Ss2fP0nOgSZMmuT594lNK2/ybpwkBbrnllqVPvrrqqqvcN77xjSYwJWijGUiFCo1mauHgVlxxBS5YGOoLFjpJwYJxjXU7rs/ZvsKiHsttXH21D1Hs5zgETucrIAQ2rP2KZZBAQaauiTeMpAN78ik8kY/51TjSqB/xLQCNmWk8eXCkDAiFheozaFROrWDEnhovl6E38dfBsfcCy6PckZP1amj14o6gWbl6iXMEi/z5NsZh7YJPiks4JL7gX0CwU1vusyIyg0TA6JpgFUMikRM0g2F7wkLpdYpJhQoxr6mXMpAykDKQMpAykDKQMpAyUJ2BVKhQnZukad0MpEKF1s1nYksZSBlIGWi3GWiNQoWq5OCGW3sBrgqncnsTobkmp+rKNu+nOYUK5A9X+vSmaLpKimuJXkhXAM2t0dDhf2xQS7B0g7GRq51eeGRuD1AMMzCH+MlzKLdCMxwamm+fvnyCe+bayQHWFjsdl+roRly5v1t6+S6cGuQV6ZB80FwhI7EINVdovW76g6+6+8+s/6XlsD/t63qs16Nmrou59A7EPwWBOBCcxNDS98jY79/u3nvhfaWubLc5ZkvX+6DNsnoKTeJDSD6uvx50rZv16awsrmS0y8k7uvV3X4/mQVPBzvL5Yeam/TBf44+TFfPjVdgy7219IVnFeiQNWMRsOOznKsALGK9R23xMRClCaUCfmZcf0+sHBxKvthq3fX0Bo41Cpl1DcVuOJr9H4DAXt+WjeCV2jZnTiMlxuGGfj1tfD8jlGAXsm0/9y913+oNu7qz0q0shd6nT7jOwTq81fcGCf8LC7vyEBZqwfmb8gD8i8imjzxwpFaYAPYRw640Y6lvq8GdNuaKxlwNpMKSDX5ELEwhUlY0JUqJgPWBqSyq1E3MdCoo5g41wsJR5o4FKvX/FkSHJSRJ3ghEcNwgz2DKZl9AfA6wr9RH0wDEMLGxOfOhm7YNtGQ48ZBc5iCGSZ/ywWLBia/HwpRilCK8ZAeHP+CIOHiseMJCQ1Ah1TCKRAzXx6VSoQDn7CuxwM/67777rVlxxxUU227vuussNHz7cff755w3FsNxyy7mxY8e6nXfeuSH8zJkzHW7Muu222xrCA3TooYe6K664wi255JIN27Q2cNSoUQ4366UtZSCfgX5bbuaO8E9YqC5YgIU/mvNSEM29QEVxHcPyoOuDrCcCUgy1XhaslYS8YKf2ULBSIcpBQYhQZTQU22q854Yy+CAm8kNyIVZ7nSBF5IXaRiuYMpqbYOnFFX31QWqJB8wRnrFFDNZvlhdkbGjtlYxdkDV7zYBIxL7UB4tEEf2yBy/29trXOAotrAWUiRtClZs4WMQ66suOIUZOvKRMT1RALhajLRUq1L/m15ov5yWXXOKOP/74AuWOO+7oHnrooYK8vQiq5r3DDju4hx9+uL1Ms03NIxUqtKmXIwSDgoVDDhviBg/bk56wQApaTnkNDeurV9h+WKZljWa0LN1eRmPwqB4yFap36MNiH7FQx3MC5SJjsrQ8lhJIcZfxy0a0r7QXLwhCI0IQJg5jzwrWQUw40UtAPG8axJgIa/gDD5No7AxjW4ZEB3buQofGb3HusS8c0FKXebhr4yACkzMeRx6M2VZ6NAanfX1Jx+RA8xbMRGLGdr4IkBAZocRtdIpJhQqa4NSmDKQMpAykDKQMpAykDKQM1MpAKlSolZ2ka80MpEKF1sxm4koZSBlIGWjHGWhKoYLe9KsX4JqTltbgqOe3yYUKVx0gFyuFWe4B1gt/LA23cuuQWrqESEA/JDu5e1hlXpy57GkxzJS9CGn0GW7BUiMYjs+5ebPnudGj/uFmfVL/pnVLsyj6Wxzax/U7vC9d21X/8X5qPyPJWybbIaVf+icqvObu/3X9Ly1RqLCCf6KCvt/UF9rM+zfkMvq2WPuaZq4Tk52EGxSZqMON5HgdP3r1I/fP/7ol6zvjKA4O+PMQ171n9yjwPX6tJTl+jHnd/cv73OuPv5nBlQ3W3Xkd9/Wf7EKqmGs/LItbcg1wWZ6IRMLIvK+9ojTXiFzDllwTt5UTKe+Ug0zUjrhZbz8TmWxL3FYPC+Uja+FrKO6QG5DgT34T3MREnNhl5uXHiiE5o2IuM1GTLRCZuA0fWZfFnccQB3bq3FPLi225p9//qht39iNu/tz5RJ12KQNftQyss25P940j9ndf32MH+qVuezwIn1P/MbKfmyD3ydJPGNog9587/ehBFuSa3Lp8YiMk5EMdiUeWUVTEav0FNxCKHet5ICIEzGoxjnIzFyXzLc0lEEaFmAMhcxU/QojG5iD2g0eEQhvpfF8xJA6w0Al6GGVsNT6mEx3iYoHyipoalRUxRX+MKfIBqTwgtX124mWUHxrFnSckL+pcNLAnkciBoicqjL4l2qZeu87A6NGj3YgRIxbJHG+66SbyPWtWY/+O6NGjh7v99tvdNtts06R4Z8+e7UaOHOmuv/76hu2GDRvmrrnmGn/DUOeGbVoLiM/lmmuu6fBv5bSlDFRlYIt+X3OjfMFCX/OEBcL6g70c8WVNIoGqsHDweiDEYR3wY9IArmuCtGqgejGNuMgOEmWKvkhmeAmSi0NkseG4YarxKHcGAz0E2MiE7XgomigCGf5kC53oAzQBoNgYq+rIMpqzjR8TUuSKDd7EKNAbRaBCfBpdDhj4lD8gEXT0TWqxRV/ttAW99hkrtqTI9gtYCLBpnMYPh6M5i5hnJkxx110zlszSru1nIBUq1L/m15qvYr9+/dzEiRMLlO39yQJf1SdJFF7ohShIhQoLMdnNcNVjxeXdwYfu54YM3ct17tLZL6m0QhOTrtl2rYciyNEnpLRhjY4YYC2e4N6I/Iix1bOIAIIRiWDVIw0JltdH3xS3nC/Ab9GPyOw5BQHhhcgpXN2pjFrBhUYCYh/ZmFgVrOAU7LJlsezW6xGTgOIUjFUUgi5wcT8ISA6ugEFf4WpFgoixeYpBSE68DbgUE1pwGW6ViwtqOIboR3WEZaWKOF7wiVyjPvXnZ7s5c6p/hGiDDTZw/fv3DzypkzKQMpAykDKQMpAykDKQMtC+M/DBBx/Q9zb5WaZChXxG0nhBZSAVKiyozCbelIGUgZSBdpaB5hQqIAV6cayp6dCbZ1vCUc9nUwsV8Cv/tOFipL8BOLtFQewxQi8MZvEVowI33WmsRL6lK6HRGM5yIhprEEb/0h3T3EPnPhpt23CvS/cubsQVw13HTh15fjofijkOYo8no7l+5cEGCxXO94UK660gmRA2NJRTv0OrToJc4Giq9FYe4EoUKVWlcd/rf8H+tYdfV3Fl232t5dz+Fw8RvedVavhFUMb/tHunuwd/90gllyo6dFzCDbtgPwfu7Kbk0Q30GnMWW2NkYmKUxK0xW1N1STqjsBzAqN7KCa4E2ZihalLcyh/opBN8e4D1HeQUBO+s3ojLu8FReEkV1+S4I5Wn8AMd05yq437u5hfc4xc91exjt8ab2pSB9pCBtdeRgoU9t6eCBcwpnNfQx0g+S1aOPoB+Q6t4agHXLw1zXyoCTJ9zaskQFLSBh7SwUXsWkQY6HUZ+USlC7QgKHmJUU2HwYI9jCO2NHCqWKXOMV+RGHaEeRQPhM1DLZ/salHKQztspRuWKC/FEBaaByYRWMSTN6CJvYxiZANjFX9aXkYsztVB88OMVyKEJm1VewCGqpYqBJSMSAJUKFUI2vxKdI444wl1++eULfa4okDj88MP9DQ5zGvK96qqrujvvvNP16dOnIXweNHfuXHfUUUe5q6++Oq+qHA8cOJCKG7p27VqJWRAK3LCIGxfTljLQSAbwZIVRRx3o+m0Vn4oX1gYc3s2CoH27EkCmkKAXgY55AeFogswPtW/5mCyuOaRDHCDhPxhayjDNwAf//g8bZNIlO5ayPPRNRzkgUkuZDqFIHwnVMsyF7IKBZ5A+TGw/GnJPeQMmcASkt48cUZqVqT30Vf2YEI+RAbvjiWksyqHTLeMjnTcuw6gQdqoPcauMHUe9BwY/wPj/n5k4NRUqhMS1/U4qVFh4hQqPPfaY23777QtvCrwGb7zxhuvSpUtB154E3/nOd9yf/vSnwpROOOEEd+GFFxbkSdCyDKRChZblb2FZr9Cjuy9YGOKG4AkLvmABW1xXZd2XRTnIgSEktyqn1qzLKhcogWmFr+SDMf6IhMxk2Q8eyRTrvfrXDhAKhjlxEB0UzCU2aDjWnNzYGShxWe6Mjii8N/IhfNxwjJlYRUEEWSyHKzxqH+ChE+dIc9BI1L+OuUVMMnUShDkIjHURk9VrEJJLb2P5LBZIHWsrLqghP4jFCtXGBhhkhk+s6hUqHHfcce7iiy/OeUjDlIGUgZSBlIGUgZSBlIGUgfaagddff92dc845hekNGjTI4TuWtKUMLOgMpEKFBZ3hxJ8ykDKQMtBOMtCkQgV/R2zxElrTE4FihbKLdE1nKrdoVqFC/sqgUutP0Pux3g8MVSZ+VVgOlREYu5LNcHvCCLC2KjXqbCDO3fjdW9yH02coss23O564ndto4AbFOE0+bApsrl8Z14RCBf9EhbAZ7rq5hpHmOxNIYMt2DHcGLq/pB9M+dDd979bImbXOjHofuJnb+ihzU5Thzsc95z9z3N9HjnHz5szLcJQN1t5+LbfHz3fNqgy3xm1znX+fBWMFQ6B5CkrpKHe993Weox638nq7DLTKj40vY5APGIQGUMVnzcq4rcxiDbfxUn4cgZ3yZMCW0PQNd/49oqgJf33GTfT/py1lIGUgm4G11l7DP2FhuNt9rx35KSTy2aNGjgP2uKgfTbQqp9YLMmN1Azn6novaIOcRSQkjWosjkdgJxh6aIhXbChzO+FCQ4TIYGKqOxSH2wIlo6Y9blYspCEjEc9Y+ozDSXEBi+4rQeQQd3ISYmI+xYqEGxAeZzFHiIEkwUx2k4KW96fM4UipeCHzjJQaveo6RFH7HtIwM8zBK0hCXCMWh2hkoBUkc7JZUE8ZPdv9IT1TQNLX7FjfDvf32227JJZdcaHO97LLL3LHHHuvmzat/Homg8HSBu+++22288cYtinH+/Pnuv/7rv5p008Suu+7qbr75ZtetW7cW+W6KMX5p6JRTTqlpcuKJJ7oDDzywJiYp23YG8H7E+/rKK690+DKnpVvvvpu4UUcf6LbcavOw/tHhv2QNMId8swbGtUbXFm3NkpdZg2Sh05VLFijMRFYz75vXHpH4Afv2chuETF796bqUsdUE6XxUSd6UAG3kFu/kNLhDTMZWLCkP+T7Ze6zyWLvIx1YhZokPUp1P5CVpYe4WZ/uWIyMX5xoX45gbCda4xVvwZzm0T1TICcB+UzkPaB/4FMM6sZH5xmlTAMwHXv9/I4UKp512msOv76ZtwWfgvPPOcw8//HClo1SosPAKFUaNGuXw5IT89oMf/MD99re/zYvb3Xjy5Mmud+/ehXnhnAuFGt27Z5/2WgAmQZMyUK9QYZ999nF4T6at+RnA+Rye4Pb4449n19NmUC6/wnJcsDDcP2Ghcydm4CVW+rzGKrWu0Wh1LacWNmGtVhRAQoNV3ohJARsASE4932eQiAIBxpGfOXWvcozZXHz5AbMJ0o4zfYTgkQasY23Vl7bRD0VGYpYJjeG38bG9ZxVfQUfuaRfmoL7QBhz1SYJdRs5j2gd+jLBV25OWguaQOAaWSjzIDiuzPAD5Tbm1ZSFRQmnTGsdKSGDhgLuc/JSf/77mExVSoYIkMDUpAykDKQMpAykDKQMpAykDKQMpAwslA6lQYaGkOTlJGUgZSBlY/DPQSKHCFiP7uE332xiX3hbKhPWpC/kLcOp8CXOLcllMrVqoAKfhRmC98qiRSIubictSUyW35uDOXWg004vIPL9wvzPlXXfrD++MuMWgt/w6y7vhfxqcvdNc466Ta3qiwm/qf2k5DE9UsIUK4C/LNcnVubRluYYqL7dmNeK++5f3uTeefMuiK/uDzx7kVt54pay+LG68/n6759QH3OuPvcGDOvt9zxroVvnayllUjbgJWPUerpIru/LWe2+X5bRRbn1BmsLRCHc+ZswJdnbL+1R9Xm5tNCdVcVdx1IsZPireIziG4ikKeJpCo1uPHj3c//zP/7i11lqrUZOESxlYJBl49tln3bXXXuumTp3aYv9rrrW6O8wXLOyx5470hIXwUfafIXsuonK0JPcdtIrRlgISMDXA5KMMdlmd5dC+h8Kj95MnkThIKzrijXJrFMx9h7yKQP2AIUQDTInDKNN4mEShGEVMts8Rsp3FkF8Q1PUZ+dhf1nfgYUdhr1iNkRx5rcqDHdOF3NDQg0ScmZeSYx70fxBwx86vsh9smCM48nI8UWHM6LGKKG1x89T6669fqkvCtpWB008/3Y0fP75mUHhSwV577VUT01rK888/3+Eme/verMW93nrr0c3cvXr1qgVrWAe/J510Uukv/FSR9O/f3912221uhRVMIXIVuBXkm222Wd315fnnn29x4UYrhJooWiEDKNi55pprHG7Uxuva0m3zPr5g4aj93ZZb9+a1xqwlym0/f+jzmsPrXNDl1qVgKx3CqS0YlMTrxZQ/55YHtgRloTfPbOqbYlKdtt4wdmPMIMzyRF2wEENqEHPWgGKwMu2TvTdic9hlws3YkQ2wOZAds0rYqLF95rZ49aayfKt6tMqtLekQj0Yv/jS8wCXGHAmIyDLYYax5IKjgTUPO2YzATOD38IH/GylUwC/L41ibtgWfgcMOO8z97W9/q3SUChXqX/OrTF4TFO+++65be+213axZszJWHTp0cC+++OJX5jx7l112cePGFXN+7rnn0vliJjlp0KIM1CtUgH7MmDEt8pGMOQMowvnVr35F+URhaks2FCyMGDnYP2FhgH/KSmddpuPaKwu7LN+kD2u8rMNqpPIwRmDA5AMkGdZ01gS9xZo+r/d5Ej4PUKlyUAywjQKC6BDBZM47AlDkQOcw6oNUgue5MqtS0MgPWJqNTzl4LooQqR+Wyr2a/TCuuh/Y47yVmoMy8ug78ME/T5qsVA5ZmJt21JVvgQOb4mkgepWxe/ZZ6AMLDiYRS25SoUImHWmQMpAykDKQMpAykDKQMpAykDKQMrCIM5AKFRbxC5DcpwykDKQMLC4ZSIUKXd2IK/ZvtZeLLjL6G4ttMUWrkZcQ3f/rcQ5PGai3bTRoA9d1haUrYbjgGe6jrkTVV0x/8DX3yVuf1AUOOHV313OrNeri8oAWFSrkyRbCuNF4EcpqvVd1e/+6aTeovfHEW+7uU+5raCarbLKy2+d3A/zrjDvfm77hvd1c26Z7ax0L+jqA3tvNm3PrRNF0Fv2yoiX5nj93vht3ziNu+v2vNhzARhtt5O644w637rrrNmyTgCkDizoD9913H/3q9QMPPNDiUHquuZo7bBQ/YaFjx478hSBY6VtB34gHDPX4gs+r9gGgvkZCY7ZXW1axgj/rGYv4BSaZiZXw6LEh0EtcGAd+xAO86kjB2gzGGAUs8QjKN1Ye4MqLmRKU8SpmUZxTgUOApfIynwUf1h/3Oe+IsBizyjQ+k6kYP/wyEPvQV5l4KeSDTSTfNghwRIeBj/G0x47l1JFcGptGnqjw1FNPua222oq40q5tZ+CCCy5w3/72t2sGecQRR7jLL7+8JqY1lL/5zW/cj3/844apNt10U3fXXXe5nj17NmzTKBCFkbiBqNGtb9++DgUdq6yySqMmzcJNmDDBbbnlljVtcc70wguNF4LWJEvKNpMBFCyMHj2aChaee+65Fse1ee+N3TeOOoCesJAny6wT/vjPaw6vH0GnC5A3DjL0hQyyKPdSWUdUDyAxi0C8kHW0C2ZZLNEFQ/EofBjluc0aRkpAFCN4NNiycbNM5TrS+BCB9vOYApYdZvB5TJ5DuW34KlNba6M6bbMYG6vkzgMUyz7wmrFVkLMDpFQUtmEpYXN2QCkXOqQOAuGA3P+fChU4H21lnwoVnq58KXbaaafSm+YrDVqgQCHpz3/+8wLDoEGDqDiyoGinAhTqjRw5sjA7nOugeK8l16UKpF9xQSpUWPhvgClTptC/N6677jrX0oKF7sv7goVDBrv9/BMWll66Cy3Cdu2VZZrWZlqVvSC0sj7r2k+ZEAPI1DZkSNZvMGALet8JaNMn+hyP+i61hy0ZgZzZea/OvLURZPpCaPkhwkYmyketcAcuxqhvbdma95SP6FCEHG+pz+AP0OjIcgc634kI9cd2AWMQysE6bynGQQ6PYqgtsyo3+ws6tSeXPKC9cuTlNBYfMUAiT4UKlIa0SxlIGUgZSBlIGUgZSBlIGUgZSBloIxlIhQpt5IVIYaQMpAykDLT1DDRSqNB3ZG96okJbn4vG1+QnKjRYqGAvZZYVIoSLjj6QhfFFzufv/8eNOfoGN3+eXOXUBOTabqst6/b/8xDXYYkOOQ0PWzPuafe94h783cOlfqxwjX6ru4Gn7WFFmX5Vrhu98b/0iQoZDwtmYOOeMf0jd8vJd7i5s+bWd+bvo9/v7L3dShutWB+bQ9x04q3ug2kf5qTlw82Gbeq2PbZ4U2OMu+ydHS+6g3VhvLfLo89KY8zVhUGt+d7Oem/+qF7cmZjxKAf/19QN77n7znjQvfnUvxo2xQ15+KXiBX3zX8MBJWDKQBMzcP/997tTTz3VoXChpdsaPX3BAj1hYQfXAQUL2PyXgrra4vtBGqHVLxT1S0PVsRWAERNkXggGtVU5pExuJNYeNqxS/xgpjxoFTOgQiuNXmYB5SGwIibYyblHBmcKoHywCQGgEZ2Or6ovTMI8sDlrv0/Bnx14hOmpsfLAUQ24yJMKZ4zb20ZbtdEzxEjd6bK++o05sVEBQyR2DNWwEGWJRYSpUsIlb/Pv49xaeVFTr5phll13WAdetW7cFNuFf/OIXdAN2ow622GILKmBckOcGTS2c2GSTTejpDguicELzgqdNnHfeeTosbVHsceaZZ5bqknDxzwA+q1qw0BpPbvra5hu5w4/c3221TZ+QHLum6BqFFnJaLXgZwTKTGauY1g5hYy4yJknEZG1lxFbK60fsP4u1MUVSWccgEKMyW8IjavURAhJNsM0qYk7YltyQK4sjUqSFtmiDkFQnWm2o5YHGi9li43H0xzIxJATv1E9sCRkR3oSsPKEwB13eR+QwSLLnsU5OtZmYCeepRRh0vkP4IIjxIJBJE6a4666p/aSm9ESF8JIt8E4qVFj0hQpz5851eGLUG2+8UXi9x44d6/bdd9+CvL0K5syZ49ZZZx339ttvF6aIH7IYMGBAQZ4EzctAKlRoXt5awwrnc3hyFs7vav2brBFf3bt3cwcesq8buv9AesIC2eg67AdYimlVtq2uzypTRzqmVoSE1XMTr/Ab77mj3KQgERsTRuKwGD3vCHglE6ycQGjDTgTMYbMB91mhnOoTUqVFAqycshGUEUccig3+GKj8IqaG8d7eBgK/4DD8bGNlXsl/AMc4xZbxZbzQWB4yIDi5Ey6NR1sCRGiIlzxLnNZe8SE2VsY4/TjYykQxPvXnZ7s5c6q/czruuOPcxRdfHOhTJ2UgZSBlIGUgZSBlIGUgZSBlIGUgZWBBZiAVKizI7CbulIGUgZSBdpSB1i5U0Nuc6QLaIspTkwsVLq//RAW+juj3uGmYBjrTOMnsnL1ebzBm4wgMHFGU6VXZZUDOjb96kpt0zbM5aXG4zTFbus3239THXS9m2ErcZTFDnZdDppuPe/6c+W7MN//pUERRbxv2p8FuhXWWL8DYhd+HPMW48fSI+38zrmCTF1ChwrorxJu868Rdc1558oqxjfuLj2e5sf/vNvfZu59XoLPiXjuv43b70c5RGOYeRZmeeY+8/tgb7p7THsioaw22/9a2bpN9NwoQinsJSdBCeI+Q41qvR4isumNzzXzxPaJW2c8jpC17b7f2e6Th4wiHXvzsVbxHZn82293ln7Lx7nPvaSrqtrvttpu78cYb3XLLLVcXmwApA209Aw8++CA9YeHee+9tcahr9FzVjTx8mNtzwE4OT1jQLx7x3WDs6/ETH1Mo2G04BpHIyOWLRUKHLxkl1BzWTiD4gxdvR26AD3weTcLQUCfGBDswCsiQK0eGSgZsIv5gnQUFloxcvECmcm1hYPuRAJF5bxKeYuBO+wGb52gg1nKO2txqk28RRzYNHLTiWB9zhjFtND3ayZDtaNqBkHM2cfwU94/Rt4hheZOeqFCel7YqxVpb78kvF154oTvhhBNafQp4b5500knunHPOaZi7f//+VMC4wgr+fHoBb+eff75DcYD9DNVyiRsL7777bterV69asGbpZs6cSU+PmDFjRk378ePHu379+tXEJOXinwHcyIZf4MWTP/CLvC3dvrbZhu4wX7CwzbZ9M+93XQL0M0CtrhneaUaOIOLywSF5Al5DWSFqwrGcYWpI+sCBdQeaICCwjLyC9QRS1xqw0JbZQ4W4iTeQsYHORzEiFRcMVhcYWTwilT8oNOocBkZQWy6ZBzuTfZQpFgrusy2PBS4N9BofO2IFWajPEBn4RK+6XAttwITJETMpYiSEFKyX8h8DPQHhlJtdkj26kyZOddf9/WaVlrapUKE0LQtEmAoVFn2hwvXXX+9w03h+W3/99d2LL77oOnQo/6GXPL69jE855RT3y1/+sjCdIUOG0LWigiIJmpWBVKjQrLS1qhGemKUFC3iSVks2FCwcMGIfKlhYumsXvz7zio0m9MNiLTKGeGnocF+HwoHFnbusEDXEgdvGbv2RfwISC9kQNpAYEYNZTQ4NSBwoN4YcEytUOtEwhwAAQABJREFUDgvtM0Y4DNjq2ZptrK3F2L7FY1rYVM8uNFes071iaCyxQCYUgQP6DFYIKrlzHGqrLfMJSY5bMRSD4VE06XWOGqkfU9Rs5GMlD6lQQZOW2pSBlIGUgZSBlIGUgZSBlIGUgZSBNpGBVKjQJl6GFETKQMpAykDbz0AqVOjqDrp8eIMvlN4dDrhcNVTL3DBWKVQBVJ5vrQ/o8sSMnzdnnrvuqH+6Lz76Ik+QGS/ZeUk3wj8xotOyncq5LD25tv6tMkNbMoh2k/8x1T112fgSTFa04V7rux2/t11WGEaRz+YAhQoP/OahgKrqDD1/X7fCusUiiCze+oCmKfPNMsXREm7uF3Pd3b+8z/178jtRXKPXYckObviF+7luqy9bA2VVubj9FWo8VeHDV2rfUKUMS3RYwu3xP7u5NbdeQ0W+Vc6SHFgRwRQLc6s0dKVda1fbFhfm6z+5wfKVxGFFzY7b+qgdc+mUS4WW0wbpwblhU48j//lwprvrf+51M179qNRzmXDo0KHummuu8b8C5h9bnraUgXaUgXHjxlHBwj333NPiWa2xhi9Y+MZQt7svWFhySRQs4ONKu/CFpn7hyGLzYTZYBBJwoR+/KOVjgB8bc7JRX0xAsOBfdFCxfWioozgMmDdLbmXWr8ZJaK8IVrk+u/XaAKBIaJ4QKU/0LxYWT+a0I+NiTBo7cxNDNli2Y0UmlOjfxoI+gdnOxhLyFPHKEdpoCjSmJjyRCNg4Yj2ckkx2QQ+5DgQzcfzkVKggaWsvzf/93/85/Kphra1Pnz5u0qRJtSBN1uFG629961vukksuadh21113dTfffPMCfbpDPpjLLrvMHXvssa7RG4bWXHNNKlbYeOON81QtGv/lL39xxxxzTE2OzTbbzE2ePLkmJinbVwbwORozZgwVLLTGa7/p1zbwT27yBQv9+1KidA0I64wIqsZ2gYnLh++RnVl/IAJYQdKhocigh1mwCnJ5Db2SaVmhMdlXmDTAQSj21CVbIxAjyxH74kcIyKfQRQz+1cp+IAsY7Qg/Nd6t2rE64iMsyhRLmTATKaUWfdBJhyKT6VJfHClOfeRbwAIG8zccKi/GzDiCYueB3Ke9UgTiVKgQM9gWeqlQYdEXKuy5556u7N+Jv/vd76i4sy28TxZmDHiaAp6qgKcr2A3F+tOmTSOdlad+8zKQChWal7cFYfX8889TwQKuhzb674+qOJZbbtlcwQKWcr8e0x+3mb4nCucJFkNy7LyQ+mIb0aQjLUNyOOaFufonHj2ZyNiQaYaPbQwIMdCQZUqT4SSM6AOlcBgDPfcRCNIRfKtOW1YJhzEo02t8xpVY+NkECt/hv+Az0EaQxwcDUus4J44cXgGLiIv2apN5HUIQFE7kCcFAroFKHzoSiVyIgUtPVNDEpTZlIGUgZSBlIGUgZSBlIGUgZSBloC1kIBUqtIVXIcWQMpAykDKwGGSgtQsVcPEs3PNcNf9GMFW2Dcib+kSFgy5rsFAhPCLBB6FXHCvj8Tcj6/3IFqsy2CEPZZv6sXY53LR7p7tx5zyakxaHGw3cwO3wXSkGqMEXLNU3BBavcdeL2ZvN/myWu+7IG9wcf8N+ra1jp47uwEuHuaWXL7tBujx/VKjw2wYKFc6TQoUmxJ2Zb63Aa+g+fvMTd9+ZD7qPXv+4Biqr2nS/jV3/47aOQo0Zknr5ltfo/Zc+cLf+8E43f+78yFOjt1SXJd0uP9zJrbVNT0bp625f8yp7xUJv8Rp3vZjzdsYPnsQx/sqJ7sPpMxyKTWpv5e+RShuN28YMcCvEXemzTKFxQJePpRbeYjVm4mCjT97+1N35i3vdZ+98VsZSKjvyyCMdbpxccsklS/VJmDLQHjLw0EMPUcECfn27pdvqa6ziDjlsqNtjwM6uoy8ywzE6/6WkjsmXHA+tLBwi/Wea+tSCCBZBGw4P+kVlxMZZBF4yp110K8eMwJjBsDQeVrwXA6RuBs8+Wc7AGBePNXTFiDTkR+fGfow/D1QueLFxxDGzqW1eDt9Ff0DxFvLkh9rXNmLQM368Mxppa20FKggys3MgtUxE49KJZeYAIDb4AFBsIJqQChWQhna1ffzxx26NNdZw//lP7aeO4Vi1xx57tMrc586d64466ih39dVXN8w3aNAg949//MN17dq1YZvWAo4ePdodfvjhhZvkqvhXXXVVd+eddzoUeLTGhuNC37593bPP1n5i3VlnneVOPvnk1nCZOBazDKBgAZ8PPGGh3vukkaltvOn67htUsLAFwfEe1PVJWyio79cJu+4ov64zjCeQwbE2Li9xTD34E6LQEwHryXtmjVK7jH8vJHuxJStxWiUP9iE4jxSn0hAEfZsLeOI/QkUbHpKO/CtO5Ygw9BlBe5JZXVUfaN5CnGJr4yGEl3sWhQe/Oo9CC6S1KfQDlccpM4HYC7nSuK2cFGScChVMDttANxUqLNpChRdeeMFtuumm/uMUPyN4Wyy99NLuzTffdD169GgD75KFH8LBBx/srr322oLjn/70p+70008vyJOg6RlIhQpNz9mCtsDxAE9Y+Pvf/97igoVuKFg4aG83ZP+BDk9YCGs7lmY53mhL85JDkJWFo1JmvZe13xyzCCc7NKQKNpw1shJC8iF9aAs+vS7iGRjd6TlGBS+L+ZyEyeX8ROLmRAgKfvymsWpL2ugnxJeJi8yEh2NkqmK8LKc94cNcMv5Ilc2FAIN/hnB+mYkmYOegWG0BA43Onqcv8dpGfakB7PJ9GoMPhGIMmd9O+fnv/b+bq797w48kXHzxxQxO+5SBlIGUgZSBlIGUgZSBlIGUgZSBlIEFnIFUqLCAE5zoUwZSBlIG2ksGFkihApJjb6S1ybLX1KowFt+M/gIrVEAsuMk4d2GwOkRM0E5YkBXiap6iZux/3+5wc3q9bajesF8PaPVNmqMxNHZP/N/TbupNzxtlebfvIb1dv8Oqbi4qJqrJhQrlbrNSE3dW0bTR9AdfdY+e93jdAg3Lutwa3dzg3w+SJ14YTXHqRlneff6WF91jFz1ZriyTeh99R2zutvD5r//0ghxBc3NWYYeiFjyJY8oNz7m5s+a6ZVbyTzppqICoGYnKTaWhYUXcDdmWgVqDz0wdhR13+ad4zJwxs8xbqeykk05yuNGuya99KVsSpgy0/Qw8/PDDVLBw1113tTjY1VZf2R3sCxb2RMFCxw78paFntV9M2uXfyu1Zgcq//NIXmeXOLQjnZWhZFb+0tROIHB4p5CoDTkTUIbYyjPGtX6YSRzCOHpVbuRSvjmCiGPIfuCMZ9CT2IuVhbPRjIg98TMU8WR/RzsqjNMbEvmMsirF21KfYvBaxCkgxNC6RByCZqVX0DRrloD522MAFOO1I4iaOn+LGjB7Lg4r9U0895bbaaqsKbRK3xQygaODyyy+vGdrXv/51d++999bENKKcPXu2GzlypLv++usbgRNm+PDhdJNO586dG7ZpbSCe5DBixAj3xRe1nxqnfnEz4e233+622WYbFTW7vfHGG92wYcNq2nfq1Mm98cYbbpVVVqmJS8r2nQEULOCzhYKFZ555psWT3WiT9fgJC9vqExZK1hAR2XUTjhUZ1hdan7zUrCkBRzo2Ak8OAkkgZB2PyYeAqS+EWXzQeF7T1wi9yMpBgU1lykUtKUhN1oqxeA1U41SXhI3uzRxZqHhmN/5JbTHiX4nVQFqNSf2FuHN6DInC79hFRAYOAbH3GBNRiVBtCZp5ndRKM8IO1Sdx+F0qVNBMtI02FSos2kKF73//++4Pf/hD4c1w9NFHu0svvbQg/6oIHnjgAbfbbrsVpovC0Ndff93hHChtLctAKlRoWf4WpPWLL74YChZQ7N2SDQULww8c5AsWBvji76X5XMcv17ruE3dcvjNyI45ynEPwwp4JCzLFU18HBhV8eh2hBRPkHqtmJCvTk28mDR5zfOqSzAVPMSm78gKYi1ttNRKYh/hM34QBkmAWsERdJRe48R0IjJ1yaVuGgWvVU6wSS5DByPhROXHF8AIHw1lhsQEKLgxoRyy0S4UKMReplzKQMpAykDKQMpAykDKQMpAykDKw6DOQChUW/WuQIkgZSBlIGVgsMtCiQgVcJMPNsnbTq2h5eR5TS2+xzei3RqFC7tofzbORkNUO9yG3xlbG9+5z79Gv59fjX3XzVdzeZ+5VD0Z68uNjbqWw3af//sxdf/xN7sv5+oYoD6NL9y70VAU8XcFuVflbIIUK4rgs1zamfF/xeIrBE39+2r1w64t5SM1xp2U7ucG/G+iW67lcTVw9pcaBnN3/m4fcqw+9Vs8ko19ji9XdLj/Y0XVZrvZNaa39HgEfLsBPu2e6G3/1JDfzw3iTfb5QQedoA696j1iM2jWCtXZV/abyKT7wNfgZU7tG4n5nyrvunl894GZ/Pju4qdVBYcIZZ5zhfvzjH9eCJV3KQLvNwCOPPEIFC/gV7pZuq66GgoX9pGCB17HwxaIsf/bLYPgLq6L/oFOfWjogZsLh44BixE5tBGm5FU9fmpIj9mT9GbGHwScTVfaZVLwJVmRqQy0RKxcf24NRiFniocZbiW8Oww9kHOQi4LGCI7eVW5vYDxGIL+ag14fcRU4K3xhS1+8Ioa0H6WvLcoQsHL6hvgyJj0mxDzxRxEDay059koHfpUIFzUT7ah9//HG33XbypLMaU2vpUxVmzpzpcCPUbbfdVsNLVnXooYe6K664ok08ZQkFZSia+Pzzz7NBVoyWW245N3bsWLfzzjtXIOqLceN5v3796t50fsghh1AxR33GhPgqZADrghYsTJo0qcVT3nDjXu6wUcPd1r5ggYqJzRqkSw6c6HpEffEaZGTjFxdaWEQJGwLzysUq3yehwRgB8YlebYlC4V5o177g3+szfQ0ceMMfaESmXBwhSBihvmVoOFjC5nEuxbiDJ+ooHoOqPnwX/SlPdh46J20VVeD2AuLUlvzLHGBUIicuCcTyF7glWo2ZuDBgINGkQgVKQ5vZpUKFRVeogHOknj17uhkzZhTeD08++aTbemvztNMCov0LNt98czdlypTCRPHUKxSSpq1lGUiFCi3L38Kwfumll+gJIn/9619dSwsWlu22DBcsDOeCBcRv13M+3/ALdljATTecF0AfzyE0B2SicuLlnaHytLAVi9Dljo2DILKLpw7x3AoMipdIAq/KxQs1KuNWY2cEuwksYNa/TF85WM0YMNj4qsfkRbC2D3sew9ZuKs+3AUMhiK32qY2cagsbuAmzzPVJryC0fiOs8Okk/RAK1qLNxZ4KFZCbtKUMpAykDKQMpAykDKQMpAykDKQMtJUMpEKFtvJKpDhSBlIGUgbaeAaaVahAF8kwMXQavPO2kTwIXYCSHyP0rupuHj5p9GT3XAO/5g+u/A3RkOWu+0FEW72bhvN29fDKW9VW8T34u4fd9AderTIL8t1+tLNbZ8e16SEQQVjSsX5aGjPole+B34xzrz78eonHrGiH7/R3Gw7YICOsimNhFCogkCr/GiTmiAKF6fe/Qk8C+PitT1TVUNvB/wL3nqd83a3Rd7WG8FUgzbXq534xx938/dvdJ02Mp2uPpV0f/3SFDQes7zoulS0aAbf1Uy83Gkut9vP3/+Neunuae/muae6zd4s3odnPpfWd56wVS96uFjbPWzW2nPX4LNbyNdWuFv7NJ//l7vv1g27e7HnWRWW/Y8eO7sILL3THHntsJSYpUga+Khl49NFH3amnnkq/xN3SOa+y6kpuxMj93F6DdqabfPULSm35y0X2Qqc26PqDBH8ZGb6+DAfbePxgNO39jlvGByuGiI6I+ZgtJGrD3nkPVdGehBKTRSMsceLFse8ZmNz45hgjBjxZXmZSW/FDEMaRBYFyGIKqTFtChziiLYHDLsQpvBwwIjM+VeitdLo6j0JLjpheOZia9oaJyYJU3TE4xq1y4mV0KlTg/LbH/bbbbutwI1ytDTfM44kZHTp0qAUr1X366aduyJAh7v777y/VlwlxXnDRRRc1y18ZX2vIHnroIbfvvvu6Tz5p7By7a9eu7oYbbnADBgxolvvLLrvM4ZeU6214Os8OO+xQD5b0X7EMYJ3A+w9PWJg4cWKLZ7/BRr3cod8Y6rbdvp+/2rIEr1dg5SXCrx/SUZEfs8Tv6U/0gqORihjA+GCXWxOVP9jIlAyeaAgnIMQSunadruA2sYOdTIk/79Tq4EOdcMtD4y+Y+w7+ZCwsMjZ4OPfADC5wQOV1hOFd9A9V1GT7xsBwK6bQAu6pgqdcn9TiK3qEjViQMFizHDIT36SJU9x1f6/9pKbHHnvM9e/fH+7StoAzkAoVFl2hAooyjzzyyMIrjCczPfHEEwX5V01w/vnnu+9+97uFae++++7unnvuKciToGkZSIUKTcvXokS//PLLVLBw9dVXt0rBwtD9B7qhvmBhmWW7hvMHPR+wJxphnac13o/K1ngkRuS2yyI+HwhnBSTkTAaTDDdOFwwI1AIMeDYPuCI+b89jxmnfxhCig7eggFRDyfjwEEKJMsQnphIecak9LIp9K4tW6MFfwEvHSxgUmtAJ8UCisWrLfGrqEcGM+zJkgIDJl0IJoPHkbEKQzqVChZjC1EsZSBlIGUgZSBlIGUgZSBlIGUgZWPQZSIUKi/41SBGkDKQMpAwsFhlodqGCXhhD8UCtO2kbzYK9SqcFCfChcvhQeRWnYFtSqKDTqnJhp1oP2whHFaaK+4sZM911x/yTbpKvsoW860pd3YH/N8wt0ZGTtijifu+F992tP7ijVpikW37t7m7oeYNLX9983K+Oe809cNZDdTmH/HFft8K6yxPOcpQZVuW6yu79lz90bzz2pnvprpfdf8xTAMq4q2Tbf7u/22hgtjjDYqt8W0xV3B+99pEbe9LtDd+8bjlRsLD5AV/zsW3o8k+5sDjEV+a/Vtx4usabT//LvXj7S+7Np/5V82kbWqhQ5sPGgb712Qg+b5/nKNNX8Vrf1q4KrxhrVw+rNvkWRTIPn/uomz9PD5J5RHbcuXNnh18EwxejaUsZSBmIGcBNWShYaMovj0frbG/lVVYsLVgI5zIeHj6x/sPPX2SGrz9JqV9QMnNAh2Mu9PQlqroWSED6DvHKwcV+WZoxgf+MgO1K8eZAFfWIAwTMohCMIgZLO/uBLGC0o/6FhpCegNURH2FRZn1wPxtHtCnhE/9kEfpsT6FIV33kW4vhvvj2A8VCzpvG7DH8Ry0mSVbBv+J962WpUMHko511r732WnfwwQfXnRUKC0844YS6OAvArwPvs88+Dse1Rrfvfe977pxzzvHnU/X+odUoY+vhUKwxaNAg98EHHzREinMd/OLv0KFDG8Ir6KOPPnKbbLKJe+edd1RU2qJAAYUKaUsZqMoA1oAbb7yRzismTJhQBWtYvv6G6/qChWGuvy9YCNdCsJbI2gEi7dOqwguLrMxQ4o92GZ9WBnuYqUz5yID4iIbtM3zegvQCEg9WZsI0ccIZ+2Qf2b7QBHwYkxl8qj/1DzqVKRrgrFwxDI22aqF6Ggsfsfq+sluM7VuO0lCUr6KFvdqRN3GY6XuAxqH+aI68I1FAeGCIj+y+dM9MnJoKFULiFn0nFSosukIFrOUoWM9vl156aUMFi3m79jb++OOP6YkT+ada4Tzx+eefdxtttFF7m/JCnU8qVFio6W4VZ9OmTaOChauuuqrFBQsoUkDBwjD/f9dlljZrdQw1rPWyfusJQpSbNd6cGdjzCPTtOYGyRw6vZRCpwjmDAAlH/q0g+s3jgVKZtlHGXmN8BA6R43oRYznmgNMOaXlH3DIJ9EsgIQ7mFDCyYcCmS8Q8NnwGkLELUWO+MSbFaMu+Wc99maMoNKqA8GT4T9RIhPR9RxxlbESWChU4T2mfMpAykDKQMpAykDKQMpAykDKQMtA2MpAKFdrG65CiSBlIGUgZaPMZaHahAq6a4SqZ3tTS0ntb9Iqb5SGZUVhdWWYF2pRCBdzQf9Bfhgub8VXGr1cKw10CDNILkcUbfJSPrytqqiK1nZBirSwixZOb9Pdn3UT/f71ty8P7ut4HbS6wcm7EzTFZn4oVj36YjdtigVF8Xs72t/3oTvfuc+/xoMZ+z19+3fXcco0cosj96rhXfaFC/RuE9jt3H9ejFxcqMKmNT3mhsXLrnjH/+WCm+/jNT+gJBR++MoNutP+PfxpAS7bNhm/qtj5qS6GIseA6czbXgNj4FGtl+UgY89Ld090jf2z8JrU8S5fuXdza26/lVu+7qlut96quy3JdDETjYFExbonPw2a8/pF7d+q7/v/33NvPvONm+kKbRjYUKhz4l2ECrT/ffJ5iTNY2xg09tmy+y7FZbrbjvfJZO2iq5GqreoyNrQ8KmkaOI1P9E2OevHR8dKXUFW23bt3oV1732GOPCkQSpwykDOAXNE855RR36623tjgZKFg46JDBbs+BO7ulllqS+fwHPHz66fOuAv1K0sNIpHKYsQXtg9jjqc86JY0YAcqBjuWC5UhK7eEr8GbhXs4CbZmG8SFGsUGTx/G8YKU2OYw38hrsaGN3ESvSSh37E2OPknDZjMaWS52IOw9mSdFe51FowRxofCf0yZkOgaJgWM046mOnfk2wrKO9mzB+svvH6FuIomqHm7i32mqrKnWSt9EMzJs3z/Xu3ds999xzNSNcfvnl3dSpU93qq69eE6fK9957zw0cONA15ebon/3sZ+60005TijbZPvvss26vvfaqW0SgwS+11FLuyiuvdIcccoiK6rbHH3+8u+SSS+riUNCGwom0pQzUywDWjZtuuokKFsaP9+fsLdzW32AdN9I/YaH/Dvg3pP/3g6wddt3gdZTXEN6zU1rDrMCLGYsWA14Ho8xLLd4Oqa8Cb0E42rEzpsOexhKm9EWGkfhUUGAIBspNCIaRGeQBXdlXA8VqCzmbl/AbXgFl8sO25b7Jn3BbX1EucxcfitGWuQNa3Xv/3k5cAhu9C1ZlilEEzHQ+gnkmPVFBE9wm2lSosGgKFXBO0adPn8J7AOdcb731lsPTmdLm6Amcf/7znwupOPnkk91ZZ51VkCdB4xlIhQqN56qtIadPnx4KFubMmdOi8JZZpqsb4p+uMGT/AW5ZX7xAW1jLZYh1nNZyVoiazgvCGi/rPukEgLMFMjXnBGDMYBigUjnvCB7C2NoQh8RDDQSyxXjM+YfXRTnHBDhz2nMa9quc0cbYe0iwYDhxq42EQexRFn2SNTsmaMSwpfpkuTrI6diShX6vWLTRXmyDXuLOUNq4QAeCiCOo4pkcINpE7MHcS4UKmpnUpgykDKQMpAykDKQMpAykDKQMpAy0hQykQoW28CqkGFIGUgZSBhaDDDS/UKFkcuae2xJtFOF6WlOwsKyF1yt1gpl0zWT3nL+Rt5EtFiooiVqVObSYqNcLkrCMNxlHrFw/JOLyG6Mjlr1Hbh5j/yU9RWGMf5rCzBlfRHFJr+NSHfxN3sMdbjanq50BE3nLYwYwxtIacb/+6OvuvjPHhQiqOmv0W93tdcruRh3jsC/+K75Q4cEGChXW3HoN12nZToYPXZ1/lnv+vPlu3qy5bu6sef7/ub7v29lzHYoU5n4xN8fR/OESHZZwWx2xhdts+NeEJMbRGrm2rx0cPPnn8Q43tLd0w3t6hfVWcKttvopbZqVlXOflOtF7q8tynd2SXZZ0s/8zx836dLab/eks98UnX7gvPp7lZviijnefe9/N/nx2s9xnCxVAoa+dpYv5s/ry97bF+kzJMPt5tH4svp7vKjsrb3ncGvPEvz3jnhk92RLW7K+00kp04/U222xTE5eUKQMpA5yBJ598MhQs2ONJc/Kz0so9qGBhr0G7UsGC8nHrjzPywQ5HHIj4W0pxF76OJazi9HhgsZDZMS/nJfZCksEymMIJFurMR4J4NXabhyiDnjVoopwGwi6WHqA+CKdjsRdU4GDeqFRu9Qe8ytTWylSX50FQxOoVzG59EIPMycxNnGbtEAB7Djy+oxhmAka03NDYYpgBYgZMeNoXKlybChU0L+2tHTNmjDvooIPqTmu//fajm53rAfHvOdzMj8KGRrczzjjD/eQnP2kUvkhxL774ottzzz3dG2+80VAcHTt2pMKDo48+ui7+rrvuogIP/exVGey0005u3Lj6/6apsk/yr2YG8L66+eabqWDh6aerb8xtNDvrrb+2O8Q/YWE7esKC+TeK90Orma41hjC8t2X9YVxcp8KyhJVLMSoknuI6GNY09aN+g120AUR9Ul+wLIeSjSJGxoErG2uYDwj8pmNtWSpyz1GUk5W6FbiNF0b0xzofnwmFZOCM04haluV0ymV4NCZtJQjhZPvgVegVG7xJADS2fZDBFxQih2hSKlRAGtrMlgoVqo+HC3K9/e53v+vOP//8wvvgO9/5jjvvvPMK8q+qAP8e3nbbbQvTX3nlld2bb77pOnXKX2stQJOgIgOpUKEiMYuRGAUL+HcUCqNbXrCwtNtvGAoWBrpu3Zbxyzav8tz6Pi/ylB3W+C7EYX0PZwsslzMWVZNWDFkm5wdgNITUlZ3aAhD7bMAQ8RnsYzwxLuCj3PYzHKyIoWDst8DjwfBGY+MvgyE8SbCTmBkc48/PJfpQX5ofIpGdyiyP6q1d7McgYSOZQidsKlNu1QUOIAVPsuicOALOy0/9xdn+PVj9vdVxxx3nLr744uA7dVIGUgZSBlIGUgZSBlIGUgZSBlIGUgYWZAZSocKCzG7iThlIGUgZaEcZaFahAuZvLrKFdJjvyoMs37F2jeDz9vlxCV+TChVWtL/cnicvH/PNzTF4vUhYjva3UBMUu+KF0SqbMvkrD77mxv2+/tME1v96L7fj/9s+QxFjYHG9mIEKN3H7HNs0Z4jrDODnnyfc7D7992d1kM4N+eM+bvl17FMQNIaY60YLFeo6W8iAzv6m/l1/sJNbrc+qpZ7j69Oy90iefNq9093jFz1FBRh5XVseo1DhgEv1iQq1I425Y1xT3tu56/21HbWytslx+2Afv/gp98JtLzUcyVprreXuvPNOt8kmmzRsk4ApAykDnAH8Wj2esHDLLbfEL0qbmRwULBx48L7+CQu7uE7+CQu8puriql9VenISqZzOGoJHe2yzxy6Vow1ydkC2gT3PHcCAsQFEFh80xG1IidljDYf2CQU8YUxMYkOcYkc28Gl4FGZl2meYMHPDXmrYR1tjIE5gpnrMXDeVqT+lD3IAvTBYSMdImFflSsBm7EbtjY5pkbMv3cTxU1KhAmeqXe7xGu+4447u0UcfrTs/3FyAmwyqtldffZVu4p82bVoVJCNHAeof/vAHd+KJJ2bkbX3QnHmee+65DjclVm0ffPCB22KLLeimuyoM5MjZI4884rbbbrtasKRLGajMAD7zY8eOpYIFnF+0dOu13lpcsOCfsMA/lMBrB9YmbGF9Ql9kJFc9AWADadwyWBV7DORBZ4yCOTDwKoKA9RwkBxfUxjbQB5nGwyQqppEfCHWBQzm1zfDW8ck+rD/bZ6Y8L6Swy8qtnfYBynLQsMZcmBt5iPPNcyiGmbNxiDsKkOZGO0ZOmjjVXff3m9WstH3sscdc//79S3VJ2LoZSIUKC79QYebMma5nz55uxowZhRfzmWeeoaddFRRfYQGe2lb2RKDRo0e7ESNGfIUz07Kpp0KFluWvLVm/8sorVLBwxRVXtLhgoWtXFCzslStY0PMIXt3jGh/XfnO2kDkvMct/kLMM5xiSRWkLHCoPQOBZSHsvF4iK+bwlg2cf9lxJ+3kOlUtUoVE52i/nB48FPQSKLfYDPINRKXFL3JYj6okx5kxn7sPRLDAHWyhHfo5qJmwCjnErnvV+L9Mlvlxegw8vT4UKnMq0TxlIGUgZSBlIGUgZSBlIGUgZSBloGxlIhQpt43VIUaQMpAykDLT5DLRqoQJmG+8pz85dLrJlhIrN61SeAdcYqL3YLehCBUTCNwRwTHqRsCrCpmCrOCC/7Yd3uvdeeL8WhHT7/n6QW3GDHgVcU+NoKr7gUATP3/Kie+KS+jdkbLDn+m6H7xa/GLdxLI6FCj380wi+/pNd3DKrLFOVoia9nypJKhQzXvvIPfDrce6Tf31agWh74qYUKiB6+x6p93m0+EawCzI7jcY9f+5899A5j7pXH3qt4XBQnHDHHXe4tddeu2GbBEwZSBkoZgC/gHzqqafSLyK39Jix4koruAMO2sfttfeu/pcol2RndA6jX3N6Eb6IlfMalfKYharTSDUmaj1E6Eit9jyIvEBZHI2ZXjVCpHxqKyBxrr4x1D4xe5h4CHMRE5arL0wGf7lJ2bHOPQvReJjV4oMfb5CRm5giBj3l0qDysas+xklI8AeiaEMi9UWtgGQCbAuZ8gqLYiXuVKggeWvHDX6tFje+z58/v+Ysu3bt6nDzaO/evQu45jxpAIUPxxxzTIFrcRDg3614ssJzzz3XcLhnnnmm+/GPf1zA4/gwdOhQOrYXlDnB4YcfTr+amhOnYcpAkzOA9x0KIHFegWNAS7d1e6FgYajb3hcs+H8QYaHylBXrkyxA0hCK4LkgdO0kHHQeBJzKCS6GGQxhSZvBhmjyHAwlbsRM5sSrfeHyjfVt+4ooxgdGOMzaMj4rUz6eEvsGTqaY8Z23Vww5CjbiV/wTl8ZCg5CRAje8UzyeOEQiHZ0P8xEQ3QxHtPFoJiMMdqlQIaSiTXRSocLCL1S46qqr3KhRowqv//bbb0/FiAXFV1xw0UUXuW9961uFLOA8DE+jSlvzMpAKFZqXt7ZshWJq/Hvj8ssvd7NnN++pwjo/FCzsO2QPNxRPWFhuWS/2izkt7rzCa1fPCcLZAsEEw41ShvMEPmeR8wNojQ2B9dyD7IU5cHEHHMFn4ACX8gYDoYxjPd8iM/UFtgghG9JzcIEjX6hguZSPWzLxOya13NU2EoBvMnMDC6lsjARS9oJefbCZYSOB4WcaciAqDlzzwgQmN2oAE7ZAmwoV9PVObcpAykDKQMpAykDKQMpAykDKQMpAW8hAKlRoC69CiiFlIGUgZWAxyECTChXs1bOyYoIqPclV6Q3VVkWUJx2o0gtNtwqSSbFQTBo92T130/MZVdWgazOeqFDFVUuOqegMa+GqdO+/9IG79eQ7qtRBvvLGK7m9fzsgjNtCZ+4Xc92YY/7pZn9W+4J9x04d3QF/Huq6dO9SCHsJ/2bAJV7cqP3gWfWfKlEgWBQC/6JvsPt6rv8J2zjMbVFuc2bOcY/88XH32iOvL8owGvbd1EIFEOt7pGEniwkQn5/7faHJvya83XDEW2+9tbvtttvcSiut1LBNAqYMpAzUzgB+URI3Ft50003hy8HaFtXaHisu7w4YsY8bsPduXLBAJwjyRab5cpIkXsdq80WnobZfVAIoVL6lHiPDl5kYsjxofUf9sFY0JGdzfEMqFMGesFEYchK5OAKNj7mVj1vSwU+IT3wLjGxIZP0bW8GpPeMjh5VrOjgq5SALSkmMm/OhU7Mc2ueQIpPKiVXcQ6sc7M3vvUBtxTP5Jo8aNjD+/1SoELLWrjvf/va33QUXXFB3jhtuuKF74okn3PLLxyePPfvss27AgAHu3//+d117AJZaaimHX/wcOXJkQ/i2Cnrvvfdo3hMnTmw4xJ/97GfutNNOy+DPOOMMB3m9rUePHm7q1Klu1VXLn4pWzz7pUwaqMnDrrbfSk5vw2W7pts66a7qDDxvidthpq/hvIl5wZN1RD7zYYH2SFamwVumaBgwtUoRFVy2ES8cMzPhRDkGyL/VJvKohWiWk9Y98eonQEq/ls/0CFkbGD7mKu+DUcrAfrL1Q087gWKax0MgOYCF2UZzj8nrNXB6biYPJC/OFuDAnEkIuzNE5acBLIiOfNHGKf6LCWLUsbdMTFUrTskCEqVBh4Rcq7Lbbbu6BBx4ovJ5/+ctf3FFHHVWQf9UFn3zyiVtjjTXc559/nklFhw4d3Msvv+x69eqVkadBYxlIhQqN5WlxRL322mtUsHDZZZe1uGBh6aW7UMHCsAMG+YIF/6NH5hwFSzut/qZFviAzy35IYTjXMHimIxbGiaHKmU8ojB3LCUXK4M93Qp+DFb3Fal+x4l/5vYUi2Jj2ntfjzBMVwnxYLX6VU4RCEGPy3GZQ2jfOJTJmETtuKFiO0wvYJPpWXpIHfda3TjKPkZC9Gj6UWebDYBYrr29ToYLkJzUpAykDKQMpAykDKQMpAykDKQMpA20iA6lQoU28DCmIlIGUgZSBtp+BBV6oIBfT6EKcv3Gbqg+o9V2+7sZJkotw9EuALMkWKlis2itOW8E0uVDh0qHKULeFC9wQnd1icKy32jwW0/6ywACLom3kefjcx9y0+16JgoreTt/f3q2367oFLXPnY4GUt6LvPLY87qKdMmbbCVdPcs+OmZoVloz6HrK563sI/2JsWcxUqPC7Nl6o4FO31rZr0jx69FpBZhlzXZx2Y7mGXaP5LvpgyXM3v+Cevnyimz+v9q/3VtkvDHmnrku5rw3dxPU5ePO67sreI2wU813MWTbfzfk81g2sDqCRuEEx69NZ7p5fPeDef/GDOoxRvccee7gbbrjBdevWLQpTL2UgZaDVMjBhwgQqWLjxxhszX3Y2xwEKFvY/aG83eMie/EPIIAlfPPK6iwM/HdFUbhypXMzIlvreQk+rYgdqsiCG0PMd/jKUianPJOyX+oYvSrN8gVuxzFTlk2nJeeCxWI5Gp6ScKvWtyYe1q+pr2ByV8Ojcme7/s/ce8HYV1f74kJ5AGjWEJuojgkTRCJFOIBBIJQEV3l9saNSnn8/j6fNnwwKIShcVJBQLPRCQKlUQAhggQAKhKUoLDwKEDgkkgf9815o1s3a795x7zs0992ZtLntmVvmuNd9zODPss9fZEoxMBUdaeEifuCuLTwrGhq0aipBlgauo9x3BlnktuGeRu+Siq9mv4jx//nw3ZsyYCq2JuwMDuAls2223dU8//XS76e6333706/+9e/d2eO333Xdft3RpbfuD/v37u9mzZ9MTBNoN1A0MXn75ZTdx4kR60kSt6R522GHuxBNPpKdwXXnllW7//fdv92kWwMbNRl/4whdqDWN2xkDdDKC4+IgjjnB33nln3b55hy3et4n79H9KwQJrw5ITTHnlobNap7SNrEfUhoVKZAAJIlozBScrV2taiEp6iieASZFiY62Hnm1EThIZQBv7AYtkjCc5i000JbW2133lm2bHHmSW9iCCyx7ip3PSfR2D+5xPEY/DpH1DeZzkF+N7QPGNMt+BP8XigN7mPXf/goesUEGT1MV9K1S4p/IV2GWXXdzcuXMr9R1R/POf/3SjRo1Snx+MMmTIEIdr4muvXf30047E6yk+X/rSl2gflJ/Pj370I/r/4bzcxu0zYIUK7XPU3S2eeuopKlhAEVSjT1hAwcJE/4SF/f0TFoagYMEfWPfjPsEPpJ+RkyWfRA9H2jVQSyCERVayXwBIkFI3DMWPh1HDe40Sm4gRcMkk9sMehbPBBGIeEVk6voWW5hBkcT4A9QfDCibL5KxtpS9twUZiAjNmBHwJHOSUk5LDPthIC2z0BVLLRUg6ZQMfHGQreCzyQvzFwAzhbaxQQQiy1hgwBowBY8AYMAaMAWPAGDAGWoEBK1RohVfBcjAGjAFjoBswUHOhwuRR2dnoe33lyptYaB1k0OMi21pBIfq8HxmK0vuoLl+FA1jJIXYBr7MKFcJ1wkwCMiURio2WU1qFuSY64FvmJ5jLX1nuLvnK5W7VirZvLh8wbIA70D+RoFefXuJKrWBrYSY/lVuVXHy1HjLBzsvFXtq3XlrmLp15hXt3ZTtz8E9TOOCMqa4XnkCg8hKcJ29/yt3aqoUK/n24+dhN3ehPb+tSgUL2dcY8yjir5z2C/y7kLS+81NO+8OiL7q7T73FL//VSPW6dbounm2wzdZT7j30+4PoO7NtuvEY4k9dAB9HvYa3Xcm3f0b7GFox8DNi8tXSZ++uRN7tXnnpVzNptZ8yY4c4//3yHGxLtMAaMgc5lAL/mjScsXHbZZf5zvWTBqiM8/RLyf05xO9IvIavlz8MKNn/mqS87Bd/HZl0U8DqTkXN+nGboJ3PqpThezyYsxznMT/uzOBmKP8kBQH+sFx2NWASzODeyjTGUAdmQpaSAAR9ij5Hvi5fEClbZGNEqaL2TfOEr/mVYghlbihl8dT+CpLkpUcpTciclWwQR2QDyPitUAA1rxHHDDTe4CRMmpPdqG7P+5je/6T7zmc+4yZMnu1dfrW1/MGjQICpgxNMXetLx+uuvu6lTp7q//e1vNU/rK1/5ivva177m8KvK8G/vmDJlCj1Fpz070xsDzWDg2muvpYIF/Kp9o8fmW/iChYMnu513/QQV58Q1JqyDsvzI6il6WedgJusjcmF9WK8kOS9knLwc9iwTU8YQO98GNTWhTxHJjwUCgVEGT+IGELGLMbxDMXfS4kSHxhP/JIsJxXkXbQQp5Va0qcLx2QWVxMQ4sFnIjwWsF78Y3QsIKqcALomCHFZWqBBZa4mOFSqs3kKFH/zgB3TjcP7F/+pXv+pOO+20vNjGgYE77rjD7bzzzgU+NttsM/f44487FM/aUR8DVqhQH1/d2RqF6L/4xS8cChbefvvthqYyYGB/N2nynm7aAb5gYejgtC/K7ycQBXuAEE32CDIOm4a4RyiVk2/CCMMYkzTREfsTf4RT2HaIIPqQSVJ6c+9Af+QY7QIMzOmQfVK0ZfNor+0UvIizXASDiJmsEp7KiRNAmiSUYZuYGlvyEX9qgSJzoH6UEj5Fg55svC7YRnmwggKxrFBBCLHWGDAGjAFjwBgwBowBY8AYMAZagQErVGiFV8FyMAaMAWOgGzBQU6GC/4X7radUFCqEi2c81Yo7qOOFtRwh+but83Zan9fhah3plVHoLrxwkXv4ikdywcqHuDn6wPaeqOBD5cNrNLnJOF1AZG2VXHxFr655kirKMfKBH5jzoLvvvPvFrbLFL9Bvd/Bo1oeEO5p3fi46qOSnbfIvBRGmXhr41/pUiJ2+sYP7wPgP6JCx/8RtT7m5J7TWExX6DOjjn6Cwifvw9G3c8PcNi7nqThln0FfJxTfy6l9I/VqKH9mJIse3YFS1/3fvs+6BSx5ySx58vsqk8+U+5/X/Yz03at//cFvuvoXr1TtbZFOaQJivTLvMBvzo9ydshLO8XPuX2cTXQAwRuE6uydX7tZcz7JDfa//3urvxpze7N194k1xrOX35y1+mL9nty+Ja2DIbY6B5DCxcuJAKFvAkE/3FZEcibI5fQvY3Fu60C99YKB8agkufIf5DAq18noguxoOeDNiC+kGpbRlFAaFLvoIcETPzymAo8IycXEMePlNCJOxyTEjJX4UWPA5RnAtPMvAA7AAtfilSwk5WYhx0iK8cBKOqhalMnTCDs9izPiFyz5/5j4NJzgEoWofxgnsfdHNmX6WyKnbtiQpFTrqr5Fvf+pY76aSTakq/X79+Nf86J34pGE8P2G233WrC7m5Gy5YtcyjSxA3etR4DBw508GvvGDFihMPn+4YbbtieqemNgaYycN1111HBwt///veGcTfbfCTtK3bZbXuPhf+BUSthWHggwdJTup6JTVqksJTxOqbRZE0LOr0eQoRDZOyfz4MDsI30g5/yjRJvIvmydcInG6XHmJdWsZQxadJ6HtZf8g+cUD/IyVvPk3ATJqGxEZKL+ZGcgBCX7dFyV9pgH+zgj0PmGPuQBZ10BBM2OEgd8SEAii9UuM8/UeHCtvcVKJIZO3Ys4dipcxmwQoXVV6iwatUqt/nmm9OTE/Kv6l133eW23x6fj3ZUMbDNNtu4hx9+uKDG3guFtnbUx4AVKtTHV0+wRsHCL3/5S3fWWWc1pWBhPxQsTN/HDR02OCz6zJLsB7APoH1GIE/kkUtvwPsL6oR9QxYDI7IRJ9pcMC7p4maEDXjIRtl+cASe8olSL5M4UHNeghmtgqBan8HWbiEmRGIjLYNmYxV0+ZyCk7ZDX8bSwiyEJo+sPCUocpaEMxrqAjcBsZbgIvgRh5/gVqxYGYTFZubMmW7WrFlFhUmMAWPAGDAGjAFjwBgwBowBY8AY6AQGrFChE0g1SGPAGDAGeiIDtRcqbOWnr+7OlW64eMbceKHINVmZq2lKUYut2GgMfbVP7iwGbLCtt1DhAP8UgrYPBJdE2rbsqFaj66m+679U+/NXr6RfV28LGzd4zzh9qhu47kBl1rl5V+XMCRRjv/zEK+6q/7lG5VfeHbb5UDfl5ImlylYpVOg/uL/baNsN3ft23txt8olNXJ/+uMFeM1KafkNCja7fI+EKdgfjv+eef+RF9/gtT7rFdy9u933W0ASCc+++vd2Ij2xExR2bbr+JGzhcv2driVB8b9XiVY9NNddA6Wj82vxe+vfL/kkKf3PLX11ec8rf/e536Ze61tKfhzV7m6ExYAw0g4H7778/Fiy8+27bTw9qL97mW4x0nzoIv4S8Pf8SMj538BHiD3x5i20QD8OXl6zis1dmvtAMfuSr9k/AoSOnly9LWRlMtF9Jn7A0TgBmU8lR2iJmMPd5M4j4saWfayZmkIothr4v4bVtxt8bJCvWkG1wFH+G45Fg5Vu2CRiIHDGq+uRBdmSKk+Ss50GQjGGFCszvmnLGr2zuuuuu7u67727alNddd113zTXXuB122KFpmK0I9M4777iDDz7YXXrppU1LD0WfuAFv/PjxTcM0IGOgXgauv/562lfcfnvjRfqbbraxL1iY4vcVY9xavUJhOC1IvDZinZP1SdY8WduQd1iqaApRD7kyinIsY9qBvLIy6EN4Be5lkoSKCZHGWytEJYwAovUhnHfCH51IpG10eiKXFsa6H5ICEhTc5m2gwyEx0UUQcopNxIWOc5AWNsE44HCjMRIY2cqQgWCeEOAmcooVnqhghQrEUyucrFBh9RUq/OUvf3GTJk0qvOyjR492+P83O9pm4Pjjj3ff+c53CkZ4wteFF15YkJugbQasUKFtfnqydvHixe6YY45xZ555plu+vPbrvWWcDBjQ3+07aQ+3/4x9uWDBG8m6j+0B7TOCo8gjDhvwviPuJVir9xfYVQQ1unQIlrQR03e0TPrSwi7TF0fsUQI4ti0ZG9nHiK1g5HKBOuuXcaABRYmTydprf40THDk/iRmgtR36MuaU2VinL3odq9BXPHAXuN4qAKn0o8wKFcILYo0xYAwYA8aAMWAMGAPGgDFgDLQEA1ao0BIvgyVhDBgDxkDrM1BToYL/lf6tJ5c8USFzlUzNVd/lC3EjdoKVx8CFuvxNubD14oWz63uiQpuFCvrKYj6emnKjXZkmcOJUfexXnnrVXXlY+zf3v2+Xzd2u31aP5F4NeZfmTBOIMyi8RviV+GcXPtcuXTPOmObWXn9Qwe7puxa7eac27yYuCuAnghu88fKu1Wst16tPL9fL30zfu28vh6cl9BvUz/Ub3M8N8kUgQ0YOdhuMWt8N2WRIym01cI1g7fJd7/szn7d/2Zb+6yX39J2L3fMPv0Dvvbdfb+zx1OB1nRHrOBSf4N/1Priu2/gjI3xhh3pEfF15+yTl7VWXX3q5aum1yzW9INqqHdQ81xXmSxY9727+xa1uxVsrKiyyYvB77LHHuv/93//NKmxkDBgDXcbAAw884I466ih3ySWXuEYLFvBLyAd+ZpK/sfATrpe/sZC+YMXM6KMwfBjKx6J8NvrPG+qGzx0Rk4/+LCI0xiLIaC+AkPJR9sUqRSHTECEGQnqMETIJ3636kbIBchaXBMomGRfs2BlnFYuG8SQ+0nJK5ZghXfKN9sAWTmILkzArmmLA0302iXmFIRoAIhS1HJMcIaGD0Vh2372L3CWzrxZVaWtPVCilpdsKn3jiCfeJT3zCLV26tOE5bLTRRg43OX/kIx9pGKs7AKxcudJ94QtfcOedd15T0sVn+OGHH94ULAMxBhpl4MYbb6QnLNx2222NQrlNNhvhPvWZyW6X3bd3vdbCvgIH1mdZn8IqxwoM2ELGZMuyYBkM1Cj6RCd4KSyWR21cY0US9GGIRtZjFYwwgyuJszZwSn5ap31gJOOsTQgOZMmPopRjkirmi8CETC1BlPiWxoVjcAiviMLI6WRILQ8Ek6IHPfJH9/77HrQnKjC7LXG2QoXVV6jwqU99ys2ZM6fwuuNJVocddlhBboIsA0uWLHGbbbaZ/9Xu7DWqAQMG0FMqhg8fnnWwUZsMWKFCm/SsEcpnnnmGChbOOOOMphQsTJi4u5s2Y4IbNoy/p8Cqj/1AcR/h6aW9ASm9DQ2I8yRmHb8QrI+6YJ/HlRctgye20iIww4V4PGYR5wuFxiiMySX4kSN75+3StIJtCJzk8MjGinHJhXGjjIxT+hl5wBFZiqHmFOYeeQt41CQHyZJeOx4EDGUTXb0M/xx5+In2RAWQYocxYAwYA8aAMWAMGAPGgDFgDLQEA1ao0BIvgyVhDBgDxkDrM1BzocKUXKFCuh6Y7qDWMj11uZ+X9P6ElmT+lNEFJ7kIhxuRy/QaG/2cTacVKlAsCZZPovExkDMUCg8CXc+N2dq3Hj+JVWMrbMS8dVzBqDV+3rdWP4lTR9tpXCOH7ph3Rc7LXlnuXvXFMq8uftW9/fo7dAP9imUr3IplK/2/K6iwo+/APq7vwL6u7yD/b2j7rdPPDd10iBu22VDXpx8XJdh7RL1BS/hGEc7c4+9wq1asUobV3T59+rjTTz/dffGLX6w2Mo0xYAx0GQOLFi2iggXcGNNowQJ+CZkKFnb7BP0SsnwRSpMLH660hIZ1lL4EFbkw4MdaLjsOdvGaaB874pn5wlhiCxa1sAxuFIX6rBHcJI+w1Il48PHG2l4sxQbjqIdtCBpl4kB2nFD0DfmRV4kDRNE24Mg4tayguLCP8QN4Pn6MGQHZg4IF/5yr5IcnKlihgiJ0Den+9a9/dfvuu6/DjfcdPTbddFOHG5tHjcr9v1tHAbuJHz5nv/71r9PeqJGUZ8yYQTc02lOqGmHRfDuDAXw+HHHEEW7u3LkNw2+y6Qi/r5joCxZ24Ccs+HWJliNZk3wrax2C8bLJykyflJyOtmcJ/IIP0PEXxlFP/t4zytk+iMkMkqSnAeeKDJM52eIkttTmYib75JjsI0TEIIl3StZsAx/xY5uir/aSuOKT2oQnCOSHvGWW4gyDkIjYkEiSi3mSM5sq34VWqCAUt0RrhQqrp1DhpZdeciNHjnR4cpU++vXr5/Dr5htssIEWW7+CgWnTprkrrriioD311FNp71VQmKCSAStUqKRmjVPg+zg8YQEFC8uWLWto/v3793MT9vMFCwf4goXhQ2iPItsD2Tugze4fokUywb4hirnDWwnvGeSyP6GEo613EwOvkD7aaB9tBStovFxU4qfJiDLYAU+Mo1eKBz+t5z47JHlCZ7wAGBvfob8gCOaClcfRGEnHeYYZRj5SZCSayzvGIQWNaO7ZNLwb9PizQoUMnzYwBowBY8AYMAaMAWPAGDAGjIEuZ8AKFbr8JbAEjAFjwBjoHgx0qFAhd5GMZlq481vNP3M3O19QyxQq5PFwZY98/CnjqzB1FzYKo95ChRlnTI1hCFbfRJyuMuqIMZykJ0pJIyPXeDBUmLDP2ApQO23Br40YGqo0P29QD14Vho5T1i/103krXvL+hfxCzrDL8KfxoFSYZRgwae/oaN6lfj5YqbyT8q6VG81BaX4h71rxqjB0nKo+fCvjqNcz71/wCwYFeSdxjXD15i08/fumx93ff3eXe2+VSPKzy47x63UXXHCB23///bMKGxkDxkDLMfDggw9SwcLFF1/ccMEC3Vh40CS3U3jCQlxQ/EeHfGEJAugLzcBE/FTJ2EQpLZMZXwFNJlk8ksODALmloBxQ5CEjWvQYymsUZkgvYpPOn9gmGeox9zlYuVxQE1umhDwAAEAASURBVAeRiwAp+VEbzAUr4bNCfFMb5DT3hCD6GN3HkjiQxdn4ANRHIP5DotGNbMnmPWeFChla1qgBbvr6xje+0aE5v//976cihS233LJD/t3dCf8tfutb33K/+tWvOjSVj33sY3QT+Nprr90hf3MyBlYHAzfddBMVLNx6660Nhxu5yUbugFCwgCc30RGWJVrbdD9E02ueXsK0XBKDLK6WWPe0gzeSsbS0OMY43EEKSZ/6WhZcqBE5tSpmNnSYmMLWesEAoO5TACWLugBHTQCK8yZ79hT71ApiikOMqWTENm0mki28o6nvZOJHBcdYuOAhd/EFV6aAJb158+a5sWPHlmhM1GwGrFBh9RQqnHLKKe6b3/xm4eWbPn26u/TSSwtyE5QzcNlllzlwlj/weYHPDTtqZ8AKFWrnak2xfPbZZ6lgAT9E04yChX32280/YWFfN3T4YKZQ9ijYF4Q+FHF/gT5bskwGQcrbCb/HCHK9vxFHUgWDTN/Lor3CjZiUSC5+yEWamKf3Rz+E8eoIyHlDkkSklzjAyuoYi+XKCTECbowLI3+Qvz8p6yBHTixNMThPsRY9OYST4GEYMSV+Bo+E0ZUwg509USHSYh1jwBgwBowBY8AYMAaMAWPAGGgBBqxQoQVeBEvBGDAGjIHuwEDdhQrx6hlmpweZW3SzU9cq7UL+Wpl1K4zyphErdrzLWm51FiogR0krm4XKXt8Yna5a1sqeAuJuvXEEoMqvSp55MkBJ3jJvwW+vbTeOiqGxqvyq5DFvhVdpqwNV9MU3M9+K11RDiB9k4lsmI58KvEp7HaikX+lXEUdDiK/kDJ3I0NfyyDUZJSvpZWxh084hfjDL+Ere6jXVUFV+VfKYt8KrtNWBKvriW5ozfFQcDQG/hy5/xN179oIsydoo1x8yZIi7/PLL3R577JHT2NAYMAZamYGHHnqIChYuuuiihgsWRm4ygm8s3G17hxsL4xef4cMojj0h8vmEzyHqq88j6coXqGIsX34Kn4LH/lEa4gouy8WX44bovoFc4sFSMCMalPjTRmRH1hlfQgvQ2T6jCYa0EoPwcfKH1nHIED8aJxuxFTtC8ANJQfQMzABZHiggq8XJe6epqtiE6wsV7vFPVLjoagarOM+fP9+NGTOmQmvi7szAt7/9bXfiiSfWNYUPfehDVKSwySab1OXXE41/9KMfuZ/97Gd1TW3zzTd3d9xxhzP+6qLNjLuQgZtvvpkKFm655ZaGs9h45IZ+XzGJnrDQOxQs0NoW1iy9zpEoLGBpHaPVGKd4pHVQQIo2MAa2xhcQwRZIsYktgokyRBUdq1gfZRQrGCpHjpNdkyU2rLV/9A4GGZ2k43UpLe4JntinlhEruaIEMM2AGBvfkX5oyYr6rONuVDorVJBXrzVaK1RYPYUKuJH+rrvuKrzouJ4yderUgtwE5QysWLGC9kcvvPBCweDhhx922IPaURsDVqhQG09rohUKFo499lg3a9ashgsW+vXr6/bGExZm7OOGDx+a9jJpW5BknmwR0/6ENxD0Esj+Je5ExJB8/CCM2SXuVoLcjwkgyLVv3CslIZsqDMRICRAmxixKfkg0yTHCwfrkLn5BmxTZGMFVspD40Tx0dHSOreNl+zTyftoHg3J5sGNlsIlJZX085pE/OtGtWFH9JMaZM2fS+4lnbWdjwBgwBowBY8AYMAaMAWPAGDAGOpcBK1ToXH4N3RgwBoyBHsNAXYUK+qpavEqnqJCbiZWIupm7d4MyXHSjq2ykV0bS1fFEprE1hpIvvGiRe/iKR5WkujtovUGu8EQFMkdAnUARA1qdlrbW8qInS+q11zjiW4zTdt75nIEpWOgX8SDNHmJfi23WM8Wq17fRvCVn5NOR2OV+QNLIsMoe+by1dS151Guvo4tvMU7beedzBqZgoV/EgzR7iH0ttlnPFKte30bzlpyRT0dil/sBSSPDKhxefN95C92iSx8WSbvthhtu6K655hr38Y9/vF1bMzAGjIHWZAA3cxx11FEOBQurVq1qKMmN/S8hz/jUfm6X3XZwvXv7X0IOHzfyhSrA4yeQfDka9m96Gxe/No3G3k8Z0Jevkmm08V5kwwIxxyj5vkefpyKLNtIRTPHxhsmXlTDNyoAGGeu5nwbaVvejNfACK9BHnNiBng/xz7c6JmxFT17BmbAZJpOsChPzQMCIQTmFJypYoYIwuMa17777rvvsZz9LT0+qdfIHHnig++Mf/+jsaQCOCjoPOuggt3z58proW3fddelJCttss01N9mZkDLQSA3/729+oYAFto8eIjVGwMNHtuvtYXwjp/z9GrWmCHUSko/VUbKIxVFjY2EPWXBlDGte8TF+tyUCI/owjfuKbxxV5DE3+DCJYghGTo/gkDfGq7GGjDm9G8aUNKoqDdVyZkiUEIpeWRGxJZyUXgIjkDSQeoLNyxmY5KdmCoSkudFaoABZa57BChc4vVHjkkUfc1ltvXXjRcU1l8eLFrm/fvgWdCaoZOOyww9zJJ59cMPjBD37gjj766ILcBOUMWKFCOS8mTQw899xz7rjjjnOnnXaae+utt5KiAz0ULIyfgCcs+IKFdYdiAxGPuG/yEhGTzO9HcISG+9ECChKxXGwhzjqQIcuyeDTytgKzVujBHfYiz+Ahmuh1HIrLyiQWBOBBx4fGk760YiOtyNnf5yQ4sUPpkDlsk70Y8lxgQBLYRHDuFOVswXKxCV6+IQQMBcu3VqggpFprDBgDxoAxYAwYA8aAMWAMGAOtwIAVKrTCq2A5GAPGgDHQDRiouVBh8qjcbOgqWZLRnb1t3N6bV9G1toCRL3AQW7JJIQp3D2sMZVZvocIBZ0yNFw7jLcrIIcb3N9rlcxSd5Crm/kIhjry9pEpKMoiRSCQXNaPed/IYWid9Dgf0kEjMuzyPOKfSvNeKPzQPfEbQHQ4jrjynaAUXOmrLW/wETbxZXsCAOGcaOfOvjVYRgsAHWP3ysT5rUIgn6ag2+YVoaCJMC79HMAd6ozQ/bzX9xJQPEyIxPeG/iWRQ63tb0AVNEFheeM1KzLvuPYJcAxGSl2dDcn7v3ffcvNPmu8du/JdMqt12iy22cNdff73baqut2rU1A2PAGGh9BnDzDH7x+8ILL2y8YMH/EjIXLIylggX62AmfvekjKHw5KvKowFIWBlqmPrvxWRpVqsOfsSwQc4ziZy+9DF7Cf7QWsXXOhvTBToDCS8hDH18cJRM2ZyuvFLWOrfsBLuTC1lnsBJjHEpzYAiwkRLYSXxxJnXISW+WGrs9ZYqr5Acv/u+Bee6ICkbQGn9555x03ffp095e//KVmFkaNGuXOOecct/3229fs05MMcTPPd77zHfe73/2O/juqZW6DBw92N9xwg8OvLtthDHRnBvBkhSOPPNLddNNNDU8DBQvYV6BgAYWQsv4BOC51tITJOhbWtGCQ1resXBLL4IX1lFyr+sERfhnfkA3JkJikgz4dseP9kiyDEeQs40Gy9ZB6IKgwC3Kaq5KX23sHb0/o0hJEiAd/JReSs9jA4EBRTiItZz3xEPKTPK1QIXDTIo0VKnR+ocIPf/hD9/Of/7zwiuOG+5NOOqkgN0HbDNx7772lT3LDE6kef/xxespf2wimBQNWqGDvg1oZWLJkCRUs4P9rGi1Y6IuChX12cdOmT3DrrjeMUtD7FdpeyD4k7B9kGyH56r0HZBl/8SWF8iAQ3rxwjLCV0fZpc+N7/h82z+DHeF5HeQQblnNQ8YubJS9OMvTZSdqIiU7uEBt2STkRtuQHH2+AYbJPiUUZ2cFTOxJS9IeJJJvJGT7RLfRDTNhboQIxZydjwBgwBowBY8AYMAaMAWPAGGgRBqxQoUVeCEvDGDAGjIFWZ6DjhQplM4tXz5JS3yEepcEu3s4cFLgfWVQZ2/yNylFZ2lk4G09UeKRUlxfiiQpUqKCvBGbySgnJTcaFHEN6chESMejW+RJ5uoUbN2uHbHyIeMEyl2CMmZPLUMfU2JrIiJGmwu4l+UVbb1GFLXln9ZJRdu5JqnqF+SoigpnmL8O3MtWcSd7FnNiBzsG3aMNBBUNlmulm/SQRmCRiI0YSMUZJbD3HKmzhGiH0fHViMaYWqn4VdofzjknZe0TRTN1auH535Xvutl/93T3196fz7pVj/MLvdddd5zbddNNKG1MYA8ZA92Tg0UcfdV//+tfdzTff3PAERmy8gb+xcKLbJdxYiC8vaTkKe5y01fHy3DpFlkGW/Szjz/q8DMmyjJ04Dq8sGVuJHWanddT3jjp2wmUHdg8xJAgZBT078Dx9v4DPZums4gVUSjowFfoEFLlju4TNaUQP8kGAsthiKwkk3r0/K1NMBiEcK1QQxtbsdtmyZW7KlCnur3/9a81E9OnTx3372992P/nJT9zAgQNr9uvuhrg5+6tf/ap77LHHap7KoEGDqBBk9913r9nHDI2BVmdg7ty59ISFej43qua00Qi/rzjQFyzsgSc39SYzWrrQ853MukeChFSl03KC0fuEuEjKGklhCFT8pJVItBrrXNAn4HgK660ekwVByFocQ7N3xifpMOeAQ3ESDkkx9AZZKUSkiL6CJ3Mhe3+Knrofw5EQo5wdBIQQdDzmkEm+cMGD7uILriKbqtO8efOsaKuKnCbLrVChcwsV8GSq97///e7JJ58svHK44f5jH/tYQW6C9hkYPXq0W7RoUcEQ/x+7xx57FOQmKDJghQpFTkzSNgMoWDj++OOpEPvNN99s27gdLQoW9tp7Z7f/jH3dcBQshP0D7RZ8n1uA+H7aQkTUuG/JKSEXjGgMFLJjIIFjV43vNfwXXQtxSJ+MRC8OMhZskWvcZONxwiEyGUtL8mAWZhb4UDkEcJgJjrTAQT9G0lixT0YwZTtOPsQhccSFRVADONpboQLzZGdjwBgwBowBY8AYMAaMAWPAGGgNBqxQoTVeB8vCGDAGjIGWZ6CmQoWDRrutJ/tf8VY3KGfu5ZdZ4qpZvAonQt9qv3hlLScvv++bLsARksZQ0GXdegsVZpw+pQRGEtITyv5yv3ZSlx+jGNZlcl1QgCjlNhGGix4wZOOoKPdrQt6ea31xNQbMvOial2QhvQxTNeetMTMIAhvb8rlHteoIH0KfjqHMQrcqank8wdaYVQjlrzOs28auM++aucaEG8i7R71HwAW/lkyf5gW67JF5hRXfbb+OjLli2Up3yzG3ueceWJIFbWOEX/i9+uqr3XrrrdeGlamMAWOguzNw66230o2FzfglZLqxMPwSci//S8jyrabegpWt8/RlqjYKpJbL/acefbTx55t8ckKmsXVfXiORUZuzz9tgnOxpxCYSMOhlKLZkWTIXLH1iwz7hLLbQkxFaAuc2xCFRTi4Ggstqxi32IfGHjyf4NCRhkHudFSoIIdbiFzQnTJjgbrvttrrIwA16J554ops2bVpdft3NGP8v+//+3/9z559/fvxvu5Y59O/f31111VVu/PjxtZibjTHQ7RjAZ8YRRxzhbrzxxoZz32ij9d3+B+7rdh/3Sf+r2VywANCqdU8C5vV6rG14xfRnXhhJpZbltGbmYsIwrtniQN7kwn4MTpZBVZp31j1kFPIRnc5f9xMuwgRfEZIIsrRvKsdjhzgfJgNudIgcg0w/6MWK9D4AxYi5vOfuX/CQFSowSS1xtkKFzi1UwBNmym6c33bbbd0DDzzQEu+B7pjEscce67773e8WUj/00EPdmWeeWZCboMiAFSoUOTFJbQw8//zzVLBw6qmnuoYLFvr2cXvu7Z+wcMAEt966w+K+SPYnyKh8nxP2ONow2FbbB58wTXYN+5SKODAVPLR4KnH+EL22zffTHiqLJ1gaQ2TwyeyzBMQbRHvYBA7QkL3SU7bIW0BjJ/lBJRi6H2DJk/QShyTkxLheboUKQoq1xoAxYAwYA8aAMWAMGAPGgDHQCgxYoUIrvAqWgzFgDBgD3YCBDhcqYG58by/PUi666Stq0UYbeiFsai08ELxa7T18UwoVZD6ZuF4ocp519Tk35ehXJi+TaeS8HjrkkZdLbiTXyhrz1i4SA21eDlnZIfFFV+bXZt7aocacEUu7YSx5lMnLZPCRI68XeVkb42inFsob+enUMIeYMwZaWWPe2qWAB0E7h8QXszwe5G3mrR1qzBmY2k1iVMmrbGEvR95G5PlW5us/R95+7W1309G3uKWPvZS3qhzvs88+7pJLLnHrrLNOpY0pjAFjoGcx0NRfQsaNhb5gYbfd+ZeQ6SMpfC7pL1/BoHxJWpDjQxl/sh+LdHtLBRhgSZZsxSY6ZXD4i1fAcwyxyuCqGNBH7BCQ1YRA7lFPxgGbNHyK+hiSgaLcm1Ff9D4ZtkixaazkYqDnUdkXMMyagZCkQCAI9Rfcs8hdctHVKvNid/78+W7MmDFFhUl6HAOvvfaa23fffd3f//73uueGG/FxY1lP+/Vg3KBzwgknuOOOO8698cYbdfGCIgXsryZNmlSXnxkbA92Rgdtvv50KFm644YaG09/Q7yumH7Cv280XLOAJC4W1Mxchr9djmGbXU1kMSRrWSLZJfrJ2pkCik1Y0tMZiTWU4iRbGURjnkOyAoHNIGDqG7udjJgTuMbbgSIslX+fBKF5L4alVQCIPiJKiml8yBi5BB3z4WqEC89sqZytU6NxChZkzZ7ozzjij8HIfc8wxVNxYUJigJgYWL17stthiC4cnVuhj2LBh7tlnn3UDBgzQYuuXMGCFCiWkmKguBl544YVYsFDv/wPlA/X1BQvjxu/spk3fx623/vCwL2Mrve8QP9m3SFurHJsW2fHw1iTsUzxAHguYIpMWzvl8RBe2OvCCa9gXhWjkR9IgT9hsHHBpwCfBlYQlc8k7+skey7chWsobRkouPiwOecJLHGEexiQKpxhTm6q4VqhAzNrJGDAGjAFjwBgwBowBY8AYMAZahAErVGiRF8LSMAaMAWOg1RmoqVDhYDxRYRRdZKP5ZG7er3GGuLFXXYAr94JBxR3A4UJcuwUO3n3hhYvcw1c8Uh4iJx203iA3Y1Z4ooKEzuTphZCTLKPIIZUMo19OVyaHDEdbIcr84FMml9dIeINdrUcpXnDO59fRvKv8Opp3JV4beefnovmpC88bw57w2gLVAUK/rTh5qCpbDVtlE/NTxh3lGhCleAG7o3nX6tfRvNviBqmXxc/LwhSpqQPvrRffcjcedYt77ZnXNEKb/U9/+tPunHPOcf369WvTzpTGgDHQMxnALyEfeeSRrjk3Fq7nbyzcz+06bizdWIjPu/h1qvTD511BDnpFl9tTxC9xgSY2MJdBlLMyijM2jC9fzPpRwEqYkPEhMo9Hfylo6KnY3iOqyRjZCFDwx1BhBi3lzy5enbxkXoSi5ORG9uyUPAg+xVWY8GEc7hE3iqD77vWFCrOtUAHs2MEM4EaUT33qU+7aa6+tm5JevXo57Ct++tOfulGj/P/TdePj7bffdrNmzXK/+MUv3HPPPVf3TIYOHeouvfRSt+eee9btaw7GQHdm4I477qCCheuvv77haWyw4XpufypYGOv69O5DeLT20cLG8LJmYiQ6adkia8drIs4MIksiSWQAJDaMEKLS8Ujp7SATPWXB0MGXB4Kn7QS8oANmzC8DxiEh8k5ZjeSQbzk/OJK9P2nPOJ+cHMbRjvocEzg4vMifQqw0KbdwwYP2RAVw0yKHFSp0XqEC9gkbb7yxe/nllzOvNvZCTz75pNt0000zchvUx8Bee+3lyp4AOGfOHIeb8O1omwErVGibH9PWzsCLL75IBQunnHJK3UXb+SgoWNhjr53c1Bn7uPXXX5c2E3qvAXvZl2i57gum2Gkf6vMGJu1TyCHsV1iq9myMprHYXTY+nI/a5rCDN0oy6dPOKMrzmDE338noaBy0DAEJBNSILVpRRxnZJDn5wA3J0Z94BI3IWA1DUtA5nEgU5IJ3xOEnuBUrVsqw0KJoD//fbIcxYAwYA8aAMWAMGAPGgDFgDBgDq4MBK1RYHSxbDGPAGDAGegADHSpUwLzlZuFaOJAbemHL19qKXvpiWxl2e3oghjgdLlQoZmUSY6BGBvDmq3pz1whhZj2SARQnoEgBxQq1Hl/72tccvmzCl+l2GAPGwJrNQDNvLMQvIU+bMcHtvucn0+eLX7rkC1UwLV+naple3rS8rI+VMMnx5TCvjXobJ7LMK4s8EAh/5ALfjAVnF2SMwQNtl8EW2wCah4Nfsk9akkGH8N5INGKbl0uW0IuNyBgiIPhG5khyMRI/CeTlC+590M2ZfZVYlLb2RIVSWnq0cOXKle5b3/qW+81vftOheeIX0A866CD3/e9/3334wx/uEEZXOb311lv068jHH3+8wy/6duT44Ac/6C6//HK3zTbbdMTdfIyBHsEAnsxyxBFHuOuuu67h+ay/wbpUsLA7nrDQpzfjFda63BoIK7Xe6XWzrA/TJM+us1jHcSQ9j1mY1ly2g6/SByORMQYbiAwmGWyJh9VcGwVYiLJywYOC/mAQpy+2ZKXkAY6wxEZkaKOMMAU44LMBwlAsDHEsXPCQL1S4kgcV53nz5rmxY8dWaE3cTAasUKHzChUuu+wyN3369MLLNW7cuNIb7AuGJmiTgT/84Q/uS1/6UsFmxowZ9LSqgsIEGQasUCFDhw2awAAKFk488UT329/+1r3++usNIfbp08dfK9rR7+0m0BMWCKyw18AGg4+4H8EwiKmhTYjar0AtMrKVvZDszdg5mMAi2tMgnAjDm7Kd+GoL7Sf6PLbIEYR9vYT61Cq4YpzoEPODj+RdPscEGPXikFQJDyGCPkSjMYlyflaooAi0rjFgDBgDxoAxYAwYA8aAMWAMdDkDVqjQ5S+BJWAMGAPGQPdgYLUUKtRChb7Y1tFCBcTx94vXXahwGj9RIX9BkuFSlYXo15KKiHbmVWYvMkBoHLlYqWWAj/YqlrZpT68xtJ+Cy3Q1nrYX+Vq516Ysb7HNAPtBGZ620XrIBScv1z7Sr7KNcpU3ycLVXo0ttoKJVusxbs9G6/O+8M8fYq9tRWbvkXhJPtKmeYJQuMrLo4PqVNlGeSe8R5Y+9pK7+edz3duvv60yabv7wx/+0P3sZz9r28i0xoAxsMYx0MwbC/FLyNP8r+Xt5m8sjL+ErPZh9LnoP4Kl1WTLuk+f0NHHW4aPbDRiQwhsSBBig0GyIRVMo4ztEiZbcICiTssTBvmwiuZRiEc58CmYYcBuaHwgGklLoqCHle8GC4xi7nl5Zkw+ZEw+5EcnzFWUrLInKkSKrFPCwHnnnee+/vWvd/hmFBRCTp482X3nO99xu+yyS0mE1hHh5ptTTz2Vbr554YUXOpwYbqA766yz3LBhwzqMYY7GQE9iADel48lN11xzTcPTwq/vTvM3taEQEvsKWh95yUxrpV43gw6B9fqc+lgXOS00RTkrxSaPQ57eRPJgu4TJyOQV4pBxzLUSl8MmXN/TB/x0rqIjGYeAQfQSW0JRcu0nNiJDG2WEKcCYL5R8ojnQCWMrVGAWWudshQqdV6iAJ0hdfPHFhRf7zDPPdIceemhBboL6GHj11VfdiBEj3PLlyzOOAwYMoCdd4clVdlQzYIUK1dyYpjEGli5dSgULKGhvRsECrhWhYIGesOBTi3sP9LHZoD/adIS9B+fP25Cw14n7kLQHy+iBxII4eXHR8URJMm8vPmIresqM8CDJYidbkZMJuXoJzYFakvCpPI6ypW7C0znDt4infFUcDi86r0jJQsVjqJUcYitUAAt2GAPGgDFgDBgDxoAxYAwYA8ZAqzBghQqt8kpYHsaAMWAMtDgDNRUqHDTabT15K3/XdrppP1400zLMNXfRjKav3PgKm5e25ad1glcmI/BwUvqFsxe5h694RGsr+4PWG+Rm+EKF/MVDcdA3QGsbLRdb3VbZFuSem/yFRsHWthpb9JC1Z5PXa1+NKX1tL7ZaBrt65YJd5Sf6Kmzx03a6Txdt4xurjfzwHqHrvuxRFU9j12Kj89NcaXkeE2Ntm7LOygmjA++RevLO5qEzKcu6JL/CXBJGFXZeLpGEsyp91bzET3DybTPeI8Csykvia/1zDyxxtx53u1uxrPoxzDpPFAHhV7AOO+wwLba+MWAMGAMZBnBjIX4J+dprr83IOzLALyHTExZQsOB/PU/2I/RZhvVS9mAKHLL4mUqdMOKGdMnP2wa5QIhO2iT3PWBHe40bhTGnZAeErK3odAzdz8dMCNxjf8lF2sQHRQspeS2Fp1YBiTwgSoqF+ZHeB6T8FCaeqHDJ7KuhrjzsiQqV1KwRiscee8x97nOfcyhiauQYM2aM++IXv+gOPvhgt+666zYC1TTfd999191yyy3uj3/8o5szZ47D0xQ6eqyzzjq0v/rKV77SUQjzMwZ6NAN33nknFSz85S9/aXieuJlt6vR96Nd4+4QnLOj1EAH0OLs2Yy1ki3jmJTau/eQd1krY4NAYspZSDFKSSRY3+nMnxgxyyU/MND4v+aJB8DCfEIs12XmQCkH4DwmjS4dg01jJWRmwyS94xIaEYkbYZE161nGXzmS38L4H3cUXtv2kJnuiAlG1Wk5WqNA5hQq4OXejjTZyy5Yty7yO/fv3p5vorVgxQ0uHBwceeGDp0xPwtIUvfOELHcZdExytUGFNeJW7do4oWDjppJPoCXyvvfZaQ8ngGtFue4yla0b4sQvZtwAUfdkz6SCy/5A2bFLCXky2LMW9UAYD2P7fzOGHFBFiBo9qNmX7Yh9mWV2E9uKYiReyVYQlN5KSnZZTJlEveDrnKIuxA3pssqDiS+pgk/JmW7HhGb3njjz8RLdiRfV3DjNnznSzZs1SiVvXGDAGjAFjwBgwBowBY8AYMAaMgc5jwAoVOo9bQzYGjAFjoEcx0HChAtiQIgG5ClcrQ+IHe+0r8jJZ3lbHCn71FSoMdNPDExU0VKYfLxBmpNUDKsygU7DhC4oZB63OKEoGOn6ZH/RV8hK4ShFhaKBc3lpVCRIUOmeIGvFtK1bElU4IrOOLSuNAXyUXuzK96PKtjpfXlY0JWwfwAHkMrS7D0DLtW+YHfZVc47TXJwwNlMtbq9rD0jnDthHftmJF3Njx1jXkXQtnGlLl8NS8xe72X89z7654V0mru/jy5/e//7075JBDqo1MYwwYA8aAYgA3FqJgoVm/hDwVT1jY45Oub98+FAVfguovQiGkj23I2UIEwZ4a0mk/3YdF/KJX7/EgByjFhBUOjkI9ZSt4ShRtWYa84QW4cgzWpphkK8LoJzjS5vHYAfPRcSRtLcv2VaBgDD2lGvIFphUqaJ6sX8XAqlWr3Mknn+x+/OMfuzfffLPKrCZ537596ekK++67r9tvv/3c6NGja/JrltHLL7/sbrjhBvpMu+6669yzzz7bMPQ+++zjTjvtNLfllls2jGUAxkBPZ+Duu++mfQUKFvS61ZF5r7f+cC5YGLejL4TsnYGglZnWvbRGs0FYC2VtDF5YGlM+YpOBjHqyy9gnu4Sh8VQ/pEMN8ovxpadsE6wXJjlbhnNY02Ea8+JBAZs8VEwxoCwYzot8R/oZ7JCM+AddMEVwin//goesUCFQ1QqNFSp0TqHCueeeW3pNZf/993d//vOfW+Gl7xE5XHrppQ433OePCRMmNKWYPo/bk8ZWqNCTXs3WnstLL70UCxbwJJRGjt69e1PBwv4H7OvwYxc4ZF8lreBj/xFltCfhHUnYnvBWBnuT4BBtBSD4F+TeATLB8aPooW2z/WgCVBpojKxtwoteiAm/oEoWvLeCXTUeo4g/teTAcuqmyUTOKEYMxB3K03clX8GyQoXEpfWMAWPAGDAGjAFjwBgwBpx7++233eLFiwtU4Mephg8fXpCbwBhoNgNWqNBsRg3PGDAGjIEeykBdhQrxTuJ4xYxZkcICjNRFtnYpq/ITuWDJWAOKTsuCXYcLFWRa+uZjkek4tfR1zmW5VmHo2LApi69ttL5KXhWrTN6MvHVOOkZZfloG2ypfjZPvE4YC6ijfZbEVLIUVGy0XWT6v9sbN4BoxyuJX5Vclby9XrW9G3mU5I0ZZfloGmypf6No6OivvXH6P3fhvd9cZ97j33q0t0YEDB7rZs2e7KVOmtJW96YwBY8AYKGXgrrvuijcWlhrUIVxvPX9jIQoW/BMW+voCKhzyZajA0BexrAmfx/xZJ0uvfPKJn7TRHx/i+Ms5kJ+XiZjtGS3aeiHrtR3bwL6oy8aRL3QZO9gjpghCy/EkhrQJi3P1Y/H0gtgHhowDMOlin/VkFLshhpr8ffcusicqgEs7amLgiSeeoCcyXX755TXZ12KEXyTeaaed4r877LADPXmlFt9abJ566ik3d+5cd8cdd9C/DzzwgEPhRTOOkSNHuuOPP56eEtEMPMMwBtYkBvC0HhRCXn311Wmt7iAB6643zE3Zf2+3x547+kLIvhEF66xe20Uh6y/GYdmktT1jW7luex+so/THbRaXR7zUMrruS0DSqBg6tu4Lto4XUEkVbSUVwZTWW4lNPmbKRZyTLcDFj/s4+0NwfUtDOge5l1mhghDSGq0VKnROoQKuqVx1VfHJIbje8ulPf7o1XvwekMXy5cvpyRX5X2vHD3DgO4YNNtigB8yyc6ZghQqdw6uhVjOAYnA8YeHXv/61a0bBwq677xCfsICoek9CYxbyVibsSbwVtinxQFf8pBWlXDvJyGU7JHuciMUdFlf1gZzVZXJRg0xMyjH4endGwNgf3ifmqeam/QVW27Ez/LmXsYdQ4pA+GHG4TEx4A9cKFZhHOxsDxoAxYAwYA8aAMWAMMAP4rnjs2LEFOn7605+6n/zkJwW5CYyBZjNghQrNZtTwjAFjwBjooQzUVKhw8Gi39aRRdBEMNOTuy/WCgqQ2tuSqHYEqDJHXixv8qFDhykdrymHQev6JCr8ruUEY6aRrgjVhrVajzswPvMtrsFon1UXBOpPLLpoShe3Medl7pPSVfejyR9x9599f82fH0KFD3ZVXXul23XXXUjwTGgPGgDFQKwP4JeQjjzyyyTcW7kRPWMh8gar2B0nuvyYNeya9dYI+2fCXqZgPycQebXTijmDx3HMYZCLxomOKn3UmiEy8FIx8dH4cT/LzMSDAHIJCbPNyMYiW3oD6wbFaLsAhZoiHBk9UmDO7eKNV8KAGN5OOGTNGi6y/hjNw/fXXu29/+9tu0aJFTWeif//+dOMZbj7DvxtuuGFpO2DAAPfiiy+6559/3r3wwgv0r/R1i5vb5L+pZiWL4s//+Z//cd/73vfc4MGDmwVrOMbAGsnAPffcQwULuOm30f9Wh687zE1FwcJeXLAAPF5LNbVeRms4L56iR5uN7yX8B43XMUbGhvTBTgxCKB4mPwKDLmKiH/KjbgiQ6/shHzoWSQQ7AQqC5Fho4adici7BS5owDxqGfnCjqNyPkSIvhOvtrVAh0tQSHStUaH6hAm7GHTFihHvnnXcyr/E666zjlixZ4gYNGpSR26AxBj7/+c+7s88+uwDyu9/9zn3ta18ryE3ADFihgr0TuooBfEbiSXz495VXXmkoDTxhYZfdt/dPz5rgi5bW91sN2X+EXZXsWbRc90N08YstNkA4fCOyuD8jlYoTu2rfBdea5RSJT96Hdn7BV3aBjCX42h4W5EStxIw5hzwEB6Y4uEmDjH3Eg2GwER8/lHiEEtRHHH6CW7FiJaBLj5kzZ7pZs2aV6kxoDBgDxoAxYAwYA8aAMdDzGLBChZ73mna3GVmhQnd7xSxfY8AYMAa6iIG6CxVwMczfAI17oONRb0GBOKoLb7HYgS62hStuhUDiWNEGvHoLFfaXQgX4q7lk5lgRMi+mi4x1YMB+LWWfx6saC0Ok74K8y/LCRdO1su+MgllV3h3hGuD18F3FdV15N4HrcO05/kfU3tyr8i6QmxNUcQ2z9mLmoGhYD9dl/pDVxTU5pP8mO5IzQyQMjNvCqeK63bx9iHvPXegerrFACnngS/RrrrnGbbfddhjaYQwYA8ZAUxjAzesoWGjGjYX0S8jT9na77+mfsBB+CZnWgpBpZV/pxQafo3T4hvoyRBv60sFSKwf7J4HotFxk8JF44k+td5eYMQ+yLbP3FgjnTxRVWhJxHnm55B+xvQH12Zz7SKQgh9AfiBFspWOFCkyNnetnAE8l+NOf/uTwSzlPP/10/QDd0AM3y+CGOcx5s80264YzsJSNgdZl4N5776V9xRVXXOGXKFmsOpYvChYmTxvvxvmChT7yhIUIibUQAxZIKJLIwGvXCqsqbEVclhfJvHNeB5+sLBsPM9P6qj7s5BCbDLYk5404QsJN9qJROtgrX3GGLForveoGZjhgxICf/9cKFeTVao3WChWaX6jw+9//3h166KGFF/jggw92559/fkFugsYYwLWsiRMnFkDGjRvnbrrppoLcBMyAFSrYO6GrGUCRAooVfvWrXzWhYKGX23lXFCzs4zYawU9SifsPP9HKfiBB9LGVnY7f8IgMItr/pBN5p/2P7AfJwPsJw+XyiCtmaL0P7bKCL/UhprHgKAevEByYxH6whyV8BYcnwP5aJn5kH4woJgdOboJF+AHcN1aowJza2RgwBowBY8AYMAaMAWOAGbBCBXsndDUDVqjQ1a+AxTcGjAFjoJswUHOhwuRRuMLm/3Azeu6QG+3lgpmoYVgmEz1aXHwTfxrHk+94AB1MsLQM5jjCRTx06y5UOBVPVBBwIKQAOjVo2jv0RUaxrSpE0LbaRuRaJlho1VQxUqqO5S3xFBB1q+NzTK3XGFquMcvz7ljOwNUxJU517MSTttEYWi54HEdGCcPeI8xJNWcl7xG8VwOF1X7CNTEfBq39Hnlv1Xtu3qz57t9/e1wn32Z/yy23dPjV4w9+8INt2pnSGDAGjIGOMoBfQkbBAp7aote6juANX3eov7Fwb76xsE8fgkiY/MEua3z4mI8xxU5/ISs5RB2cAoDgwEb0cfGIZh5NAvmFJfW1DxD4EBxpSer9CcI7R6igEDyxTy0Mgj35B0/dh0UEIEDxoIDkEfTckHPMhT3siQrCg7UdZ2D58uXujDPOcL/85S8d/n+vJx4oUPjMZz7jfvzjH7tRo/z/q9phDBgDncbAfffdR/uKyy+/PK1zHYw2fPhQN3HqXm7c+J1dPylYwGpJC2NaZwFPI14qaUQhw7oryy3Z6QEsMcZfQU7WXk5IsKROGpf5iE10EueIz/5iB7XvB3PxklxSy3akDwmgL3poEwb4IQmfxD7KNG/K1tvhn/vve8hdfGHbT2qaN29e6SPiVVTrNokBK1RofqHCfvvt56699trCK3TZZZe5adOmFeQmaIyBFStWuI033tgtXbo0A4S92TPPPON/ZX2jjNwGzIAVKtg7oVUYePXVV2PBAp620MjRu3cvt9Mun+AnLIxYn6AyexnsROJ+JW5taL+j7bBfwZ8cUSfiwt5H75nYkU2q+tpeoviW8DkI5RBUhOVPjCb2Ygc/1kmeHBt2Xh6cyEL3yS0KYEyH2JEmnARD40Vg72WFCoE8a4wBY8AYMAaMAWPAGDAGiAErVLA3QlczYIUKXf0KWHxjwBgwBroJA3UVKlTNKV05ixfv0q3F7EQmXki/uJ9Xalx/MY4v8+VsK+V09Y4QJI37L1pU8y+bD1pvoNu/jUIFAGeKFRCuIn+5MEnJ5E75G7PztsJLQZ4J7kGJBw2e5q8ToxQlTzGRsXYHpBCXk0tOWpy3lXlVycW3GEKSgkVKLDNdmCSVQFHLeBojqSWnKPFm8p4SGWzayxm22bx1vGxiteetMSQbbvN5F/IDGf6vIM8ER9L0p8B1zJQ39WQoJjJW3ujmY4p6TX+PrFqxyt32q3lu8d3PCCXttqNHj6Yv0EeOHNmurRkYA8aAMdAoA039JWR/Y+GkaXu53cft6Pr16+tTk8UD6wRnSo0fiEbWD/niNTMfbySWZIdxABI8hUrdMr3IYKD77JtkUReSo0biMTqfRS+62EZENV8/AwYKvsEZoxwOiUTtndiNBTE3QrFChUCDNU1gAAULf/jDH9yxxx7rnnjiiSYgdj0EnvCCmzy/973vWYFC178clsEaxsCCBQuoYAE3/+bXrnqpGDZ8iJs0xT9hYfxOri/2FbQ2yuLJaGn/IOumLK+y/qaoOh9am4HHi2000mPuQ5W1S/LoFueqY2AhD1lFPaGFmHkc8U0t4xOGNw4zz2CRhcShNuWEyXEo9uR4yUh0sKInKlxghQqKvS7tWqFCcwsVXnrpJXpiJW6e18fQoUPdkiVLXP/+/bXY+k1i4Ctf+Yo788wzC2innHKK+6//+q+C3ATOWaGCvQtajQEULPz617+mJyzgs7SRAwULO+48xk3Zfx83YmN+wkLctfFWJe5bwjCz55H9kc4hyrC9wb6HNztkkrqCxjbir/XS1/5ih6SwV4q6BBdlLAoKsmdvnZPEgEawgCv4Wk7eAU7LSRROhBdAWaQcvJMVKhCLdjIGjAFjwBgwBowBY8AYCAxYoYK9FbqaAStU6OpXwOIbA8aAMdBNGGh6oUK4ZqbvnQ7X1+gm67IbmzNUeWO5iEc3buPGaSXje7W9UG6oVlcBpVt3ocIpkz2eACIbCpiTSZY0GxnkWsEINmhElLOMw1psykAwWcLWAbyM8LQMkSBs6xD7YEcYbdnXqhNcZV+Wd5mMXOrIu5aca7GhuPm8vSP5anmZTOYJ47YOwRGMtmy9jmK3Y0NqwQ22pbxKzJztmvAeAS3tcdmePlCL//hWLFvhbj32drfkoeejtL3OTjvt5K666io3fPjw9kxNbwwYA8ZAUxlo5i8hDxvmbyz0v4S8x15SsOA/XvH56Q808qUsjUXhNbELRTjEllrvnMZigTaAoxdANJbIyFIrIPAH9NpGwUU57T3Z3Mu4Iz6pzcoxkj1rpmWzmLb4k71MBTkpgbaBeMG9D7o5s9u+oXD+/PluzJgxMLfDGGiXgZUrV7qLLrrIHX/88Q6fB93xGDJkiPvyl7/sDjvsMLfZZpt1xylYzsZAj2Fg4cKFVLDw5z//Oa6lHZ3cUNpX7OnG7ekLFvqjENIfsl5ipQ0LM0T5NZps1SnaBmOxV4ARD26iZz8OKjIFG30EX/LDah5lygGyPI7YpZYdgMF/Ep9bBccxgjhqEQNGCER/3Gb8vALxrFBBs9L1fStUaG6hwu9//3t36KGHFl7YQw45xJ199tkFuQmawwCeEjphwoQC2Lhx49xNN91UkJvAChXsPdC6DLz22mtUsHDSSSe5RgsWevXigoWp01GwIE9Y4LnLvoVaiGQvQ90oZWMtwxYHttjzhCN1tUz3xZJ9aaTiiVYwpeXNFWujzA/DrgudaAK92KR8UjzyIXvOS2w5F8lA2cf0gQs9OXM8HcBrrFAh8Wc9Y8AYMAaMAWPAGDAGjAHnrFDB3gVdzYAVKnT1K2DxjQFjwBjoJgzUXKgwaVRxRrjXWS6aFbUZiVxno0KFjCYM9H3TdA3uPX8rcBLGi4HeXMtDAhnEhbPreKLCuniiQq5QQV/40wUMGXkmZHES7dp6FyEF3mmqASvfKIMMdh1yZZpFV4oMdtYqjiRv5RZ1hY4yymCXyOviGoHKMAoJsEByzrlVWHtxGXaJjPCq5FXowT7DR4VtXXlX5VGHXJlmM1KKevJWblk8PVJGGewSeTPeIwitoGMmdXC9/NW33d9+Mde99Hjtj8feb7/93Jw5c9ygQYNiSOsYA8aAMbC6GcAvIR911FGuGTcWomBh4lR/Y+Fe/sZC/wvnOPBRmvnyFRL6ky9aycyLWM4jduQveSEBCnCoCScty2Fpw9AXV8lF2ogYDCQPaqH08jJfCaFxsj7JMcojntIROEdgTNaxmOVwu++eRe6Si65Gt/KwQoVKakzRDgNz5851uKnv4osvdm+++WY71l2v3n777d2XvvQld/DBBzv8OrIdxoAx0DoM3H///bFg4d13320oMRQs7Dd5nNvTP2GhX79+AcuvqmF5lPVV1k+RS9DMGg0fb5Bs0hpbsAMAbAnIn/mPRnISH2lls0BeZM/eCkJhMor4pjbIQ0DJgId5vJRU1EjOmCT9JZuYd8BeuOBBd7E9UUFo6fLWChWaW6gwceJEd8011xRe1yuuuMJNmTKlIDdBcxhAEeyIESPc0qVLM4C9e/d2+K5hww03zMhtYIUK9h5ofQZQsPCb3/zGoWAh/992vdmjYOGTO33cTZ2+ty9Y4M8D2sPI/oUAZQ/jBxk5hmQdw9IY5kquugAABLV0Vu7RJzgoVcSLNnDGgVhhH8VDEoiKW48nfpKLjIs+7M+x+Qx4spO8wjjNJaCIPNq954780YluxYqVDFBynjlzpps1a1aJxkTGgDFgDBgDxoAxYAwYAz2RAStU6ImvaveakxUqdK/Xy7I1BowBY6DLGKipUOGg0W7ryVvxtTN/YUzfK0yJFwQV0/G++gKfWMUnJ4gArdgGWXwSg8h9i5uNozzYoVl4IQoVHlGS6u4gKVSACeYhVxW1S5m87EZn8gmKPE7eHvnrI6/Xutj3Rnlc6ErzqzGPdrGjAXealbe8Z/LzqZTn8ojDEk7KuKw77yr+2pDn54Icy3IRYd4+b1t3ziFgHpfEHjwvbwbXZXNsVt6V+VW9Bkim7Cibe4ldjXm/+cJb7qajb3WvP/t6CUi5CDfW/elPf4o38pZbmdQYMAaMgdXHAH4JGQULl156afxitaPRhw4b7G8s3NPtiYKF/v0yeGvxzo9ksgzpL25jTP8ZLHtEtuMPZfFhO3wJHHrS8cMMXpCTme8H86yNBPVKsSAMwQ56wUXLsNImPzIVvxAbMsFFAtQvtYmB4rzQQTw8UcEKFQI/1nQaA2+99Za78cYb6WlPeOLTs88+22mx6gHGDcq77ror3Vw4efJk94EPfKAed7M1BoyBLmDggQceoH3FJZdc4hotWBgydLCb6PcV43zBQn/sK2g+sgbnW56srNlx6lh/w7rMTViIvYHIYRtMYoesvDBZZ+3ZB+D401bKjtUwpUPiFVuoA0qAolG7ffbjHAgCwTmbMKGUGSdjhQrgrHUOK1RoXqHCK6+84jbaaCP3zjvvZF5gFDYuWbLEf4b0z8ht0FwG8KSrs846qwCKm2Nxk6wdWQYOOOAA+v/vrDSNoMcPnNhhDHQ1A6+//rr77W9/60444YSmFCzssON2btr0CW7ESF+wIHsWP0lcL8KB7Qv2SbJ/kT0TKcOJZMFA68PWh6yyckFj7GAQIaEVe2mjMnSi3Btn92hsAL3YyBwEI84mpRFtYaP1GgMa1lNDwxhbOPKtFSoEfqwxBowBY8AYMAaMAWPAGCAGrFDB3ghdzYAVKnT1K2DxjQFjwBjoJgzUVaggF9b8fb/hVmGepdxQ3N6ccxf1ojnw8hg5W1LjpOWUB50iFDr0RIUrOlCokEGxgTFgDBgDWQZeXfyau/nnt7q3XlqWVbQx+sY3vkGPz8YvSdlhDBgDxkCrMYBfQpaChWbcWIiChXHjd8z8ErLs3fDFrRzyRWwa+14w4CYZJz98CcweWf8kFwMy88aCkrUXDLTegv64DRIyEB+0HFdauAgyQ7Cfxgh6EYXEBVPHofhBj0D4Z8E9VqhAL4KdVhsDeG8+/PDD7tZbb43/PvPMM6sl/oABA9wOO+zgdtttN/p3xx13dOuss85qiW1BjAFjoLkMLFq0iPYVuNGy4X3FkHXcvnjCwt67cMECrZW8vqa1GduHsObqqdD6K4tw1kbsM25hQEi+L4him4EW2wyAt0A40SmHKBNdroWpQFHkEDzTFwMKEw04Twy9nqSCDVA5vGzhgof8ExWuFElpO2/ePDd27NhSnQmby4AVKjSvUOHcc891hxxySOEFAsfQ2dG5DFx77bUOTw/NHxMmTHDQ2ZFlwAoVsnzYqPUZQMHCKaecQgULL774YkMJ47r49p/czk3df2+38SYbBSy9p/F7GRlKRyJ6eeW+KPiQRexjaySDhAub8AcD3jtJJtGeBTxkjNgPkEFK+UoctAKRQY4+vhP7iBFQqGEdd1keLUjF+pizD2SFCvw62dkYMAaMAWPAGDAGjAFjgBmwQgV7J3Q1A1ao0NWvgMU3BowBY6CbMFBrocKH/BMVfElAPHDJLI6lyCBcR9MX46JN9GQJ2QR7AGUKFejaG52SVxGIdRI7WjbwRAWFYV1jwBgwBjQDSx97yf3tmLnu7dezv9SnbfL9n/zkJ+6nP/1pXmxjY8AYMAZajoGm/hJyuLFw3Pid/Y2FfcMXwbzpky9uQQB9oZvb8yU927MdnXFKX/xGw6KdqOQLY3KMvvk85MvkgOObYFGIJXjA13tdOFSNJRfKwQ8IWwllTKIgh5UVKsirZm1XMvDkk0+6u+++mwoYHn30UfePf/yD/n311Vc7lFafPn3c+973Pjdq1Ci31VZbUbvddts5/Gu/eNwhSs3JGGhZBh588EEqWLj44osbLlgYjH3FpD3cnnjCwoD+vH/wM+c1lCmQNZpGsi6TgbfT665yUmIYiSv1g2vGlyMFPG+QWfuhFBm1wdrj5rEkn9hq39DnJgFlbAmadYQdTjwFJScQUvpChQd9ocJV5Fl1skKFKmaaL7dCheYVKsyYMcP9+c9/LrxIeGrc9OnTC3ITNJcBPMkCT7TAky300bdvX/f888+7YcOGafEa37dChTX+LdBtCXjjjTdiwcILL7zQ0DzwHeAOvmBhyvR93MhN8IQF+vOYfs/E2xbCl72P3l9BEfc7ZJUdJ3/BSoDRT+J5QdIymMQs4lDkYJTNN/kwmsSJ2BQvjggj2mix5JOCJ1vSERBYIvmRh5/oVqxYyTmVnPFUGzzdxg5jwBgwBowBY8AYMAaMgTWDAStUWDNe51aepRUqtPKrY7kZA8aAMdBCDNRXqICKAp88XRfji2NUJ0CnIM9dTMNURY1+HMBdbAErRgqb7MNJ1FpG/RLFwgsXuYevrO+JCpJKAd8L8iHytqKvVS4xqvxEj7bKBvJ8vDI/LcvbN4qdx9OxyvKripf302N+r2UkxEk+ds3Y/LbNAoZRFUaVXIOIjchqzU/88vaCg//c8N9clZ7UZFS0AXYtfhILbd6+Kr9asfN4OlYZRlW8vJ8eo5+P0yh2Hu+5+5e4uSfd4VYur/4CQOeEX4k6+eST3Te/+U0ttr4xYAwYAy3PQLN/CXmCv7EwFiyE2ctnLO0D1X5Q5GzmFdFe94OWjJMcUvaXL6QxzurFRstTP9mKrAoPlmLDmMkXYxzQF8JDxkqykVO0DQ6wWnCvf6LC7KvFpLSdP3++GzNmTKnOhMZAZzKwbNkyh2KF1157jf6VPtoVK1a4wYMHu6FDh7ohQ4ZkWsjtCVOd+coYtjHQegw89NBDVLBw0UUXNaVgYcJ+u/snLISCBZluWIZpbfZ9Wm21TOx8y0ttG2s0bGW9pm4AyvV5QQ+x4INDxSavuK4DknGkJXOR8UAgoy3EIqS9AgnUSfLM4LBTECEwQdx/ny9UuNAKFRR7Xdq1QoXmFCq89dZbboMNNnBo9bH22mvTTfKDBg3SYut3EgOf+9zn3DnnnFNAh+yzn/1sQb4mC6xQYU1+9XvG3FGwcOqpp7rjjz/eNaNgYfuxH3VT/BMWRm46whMke6XEFe1/sKlhFbY14YidzL5J67mf7ODIeAyh92QBNOCnfWLWJmGJnFILQaOMA0nKmfyq4iS5j5EmQWLCJTHH552dc1aoIKxZawwYA8aAMWAMGAPGgDEABqxQwd4HXc2AFSp09Stg8Y0BY8AY6CYM1F2oEOYlF8UwXIuqF3DNEFfNchP3N0uH+6hZEe9EVvZkk6wKOHmMTIic0sdfOLu+QoVpp0zKIGYHKa+sPD/RrDY3a6/M2+dx83rg1WKTj1vmp23K4oi+lnjNspGYus1ja11n552P3VY8nRf6eV/Rt4eR98vbt6emmmnzAABAAElEQVQvi53HkFzybR5b69vD0L5ltloP3I7a6Jykn8cWOdqyOKLP+5XZlts8NW+x+/spd7l3V74rYG22+OW4P/7xj+4///M/27QzpTFgDBgDrcxAs38JecJE/BLyjuGXkHnm8QtXfH7jL340xw4Zyhe+GLCN3ymSSd6OLCKO9iOggj/wBCO0vpE9rsQQE7ElSy+MnmIQgzBGXozExFdM0QKXsAMgrKxQQTNkfWPAGDAGjIHuzsDDDz8cCxZWrVrV0HTWGby2w75inC9YGOCfsCALsqylcb0uLMRYcxEa6242BfEhrVJWyWNM6QA1YEcMta4LZBkeu4U9AuGo5EowgE+HBxVfjKOX78Q4sPH/3r/gIStUYNZa4myFCs0pVMCTFPBEhfyBm8HnzJmTF9u4kxi47LLLSp9egdfmkksu6aSo3RPWChW65+tmWRcZePPNN2PBAp6e0siBHy/7xA6+YGH6eLeJL1iQPRM2NrTTUfuaqEu7nrTn8UlofdwLheRYh31RyrZ9G20fHHVeyFDE0kEeCOHHmTaFZR/Ri1zGCodhKKD3CYEA7f+xQgUhzlpjwBgwBowBY8AYMAaMATBghQr2PuhqBqxQoatfAYtvDBgDxkA3YaDWQoWtJ4+ii2AyLSlOwDhcdgtX4YKFv+eXbeSinB/TfcCkCLb6Apsgi18axwjeXOoc+Gf1YROjR4f7qVDh0ThuqzNo3YEOhQrqWl/GPD7pQUvp+mDKXXLSGDT3cN+zvpCoYTR2ezZaL/GApWNWYYu8FoyO5iQx0FZhrI689RxryakWG8m7Hq792zLzzizDsPcIs69fM+EJmnr4rgVD3pfatr3X/19//beb//v7Ml8GaJ98H7/Yhy/E99tvv7zKxsaAMWAMdEsG8EvIP/vZzxx+Cbk5Nxb6X0Iev7Pr179f4kPWTLQlH/5aJn02S3sxcRN9Ak+YYkMrdHSl4LxmBxntLFlMi5GYamySeUC0Wk4CyNDhP04lBM/Ykh0BMAaBsvl99y6yJyowFXY2BowBY8AY6EEMPPLII1SwMHv27Mb3Feus7faZiCcs7EwFC7TGYu1NC36mDxpZ5VdptebSqq3G2p99WJmRIw4WenVksYNO2WX1KU+y9MqIpnwIXsbUZgOST5hMaLwBG4oOeVuhguKtBbpWqNCcQoXPf/7z7uyzzy68oueee64Dx3asHgbwRIsNN9zQ4cZlfeDJFvjF9YEDB2rxGt23QoU1+uXvkZPHf/ennXaaO+6449ySJUsamiOu24/ZfrSb7J+wsOlmG6c9HG1rwt4mbXZiLL0/YzXtgJK/t0xu+T2g2o+xG6wJO4sFEefAPe5j9ybYOo9gTYGBltEJTHCEXkB0X2NQaAkEhT+OOPwE/zTD6ic/z5w5082aNYuN7WwMGAPGgDFgDBgDxoAx0OMZsEKFHv8St/wErVCh5V8iS9AYMAaMgdZgoKZChYNHu60nhUIFXDGTIgTciI+La7kLZZgZ3RQsermQp/1gpPxiFzb6bmWyQxgEAjD+6ETjKIddOO6/CE9UqL1QYepv23qiQsgHscNBMWXQRos827PFXMv4awOWVKAoclZhTDyGvMvyqMLoaE46jSqMqpjiq3OGrJ68BaOqrcpJ29dio+2lX0veYqtbe4+o/7ACMe29R2BGnwHBvrPeIw9d9rC7/6IHQ5T2m+HDh7urrrrK7bTTTu0bm4UxYAwYA92MAfwSMgoWmnJjof8l5L333S3eWAgqaC/kl4SyPZGWSV9a9k1karlIeb/kV4u45HBH5IyB4OwhGDT0RkFcmRvsxUY6ghGxQzIZeZAhMZJHEEdPVJgz+yqxKG3nz5/vxowZU6ozoTFgDBgDxoAx0MoMPProo7SvuOCCC5pQsDCI9hXjfMHCwAEDCut1Zu3lxZ2oye4DElvaXqQiy7eiRws80cdNBcl5gZd43CZbTqlkLxE3FUADOEcTe4lJUg+q5WzJMZCTFSoII63RrsmFCqNGjXL/+Mc/Kl+Irbfe2h199NGVelGggPqLX/yie+ONN0REbZ8+fdwf/vAHh5vk7Vh9DBxzzDHuzjvvLAT8/ve/77bffvuCvKMC/CjIAP85310PK1Torq+c5d0eAyhYkoKF5557rj3zNvX4juVjn9jWTQkFC2SMbRD2OrKJUghaVt0XB2BIn1sea3kyiHghvniKHK1Yi0xs0Io+6sQ46MRW9NKSb1JyzrnErVBBCLLWGDAGjAFjwBgwBowBYwAMWKGCvQ+6mgErVOjqV8DiGwPGgDHQTRioqVDhoNHuQ5O3il+Mcp2Av1M+HOmSnEhKbiSWC3FSaECmQegbUUfsBM+WuBgnRgpDX8CT6M0uVBDcmHIut4IegrZsMg4lAzXPEm3niBCzkZyRVbPzbi+nZsRrBkb+FemueefnkR+3N6+8fdm42Xy3l1NH4nmf+85d6B695p9lMyiVbbzxxu66665zo0ePLtWb0BgwBoyBnsIAfgkZBQsXXnhh024s3HOfXVx/PGHBf/7m93XypTH4q+qTXyA4789+VV86k5bjsiGh0NLhg2Var8ljSz5oyZocCCLaRhEbZ+fApjQxUgcbiO2JCkKOtcaAMWAMGAM9mQHcsIx9xfnnn9/wvmLttVGwsCs9uWnAwOyNrLKG81IbV+e0XidRlGnekz8byjhro/cKCVBsJbYs91EOEC+MHqETIlEI8gmOes8hWNE/CjgzxADO/fc96C6+sO0CyHnz5rmxY8eyo507lYE1uVABBQS4odUOY6AjDDzzzDNu5MiRHXFtCR8rVGiJl8GS6EQG8PmOX/E/9thjXVMKFsZs65+wMN5tttnIeM1F9k8yDRmnLVDYQVGj+94j7IvEF23Wn+1FX9AFNUPzHivZZH0FG1Kxkc2e+JMNG+LM6jCRiOY75J8mSLZWqEA02MkYMAaMAWPAGDAGjAFjIDBghQr2VuhqBqxQoatfAYtvDBgDxkA3YaDmQoVJvlBBH+qmdv3r5mKivmYNV9lE41vvS+7vCUjGOt4wT7jBhC/IZTEwWitgaIROK1SIVwh5Diob7mo9JDK9gmEbgmZgaPha8LRNR3JGvGZg1JO3jge/juTdDAydM/oasywnrYd9mQ3kbR3NwND4teBpm47kjHjNwKgnbx0PfjXk/d6q99ydp893T8x9Ukdqs/+BD3zAXX/99e79739/m3amNAaMAWOgJzHQzF9C5hsL/RMWxu/kcGNh/BLXE8bfxfpdXuYzPTfWX+T6vjYVLMHRr4HIgjurlH/yZUQZwzD5pFyy+mweBC7YBKf0kEvSwWbBvYvcJbOv5pwqzvZEhQpiTGwMGAPGgDHQ7Rj45z//GQsWVq5c2VD+g9Ye6Pae4AsW9t7FDaR9BeDUWkvosrYXdWk91zbk5NdrLZPFm+B5/xHWcf0/v7LGJ1/BCC2ngAxDEN3k8tb43pw8cBK5BIMIMGG80AoVwEbLHFaoYIUKLfNm7GaJWKFCN3vBLN01loFly5bFgoVnn322IR7whIXtPv7hWLAAsLSnopFsd1QcvX/iDZPsi6gNloJDKGoPxWM6F7HVngtYgiEtvHAInMhpnxeCl+WCjVvWJhlHeQDF+MjDT3QrVlTvmWfOnEmvAWdjZ2PAGDAGjAFjwBgwBoyBns6AFSr09Fe49ednhQqt/xpZhsaAMWAMtAQDHS5UkOz9zb+4YJg/6CJcuJ6W18lYFzjQBTdRhJZwA3QVXhlG3YUKv5mUi5wbIod25pLzsOGaxlmz57um4bXAfzGr3lnlbv/1PPd/99X+BcpHP/pRd+2117oRI0a0wAwsBWPAGDAGVj8D8kvIF1xwgWv0xkIULIynGwt3dgMG9KfJ4HtY+WJXzy4ji1/Wegvfly2bttF9wYEsuIqIWrGtamGk/fJ2rE95ECgJsZ3EhFgSLTJzRE7vuQX3PmiFCpE46xgDxgA+F55b8kyHiOjVq7cbOGCg/1wd6Pr148/WDgE1wenFpUv8DTUrmoBUO8TgwUPdOmsPrt3BLLuUARQsHH300e68885reF+BgoXx+0jBQv/M2s2TxJobetLxQ17XWaHEkRfokxyLuKCRMw3iGp9EAVfwUwsHwSM/hce5EGQ4SWyOS6Y4ISdYBCDqq/HCBQ+5iy+4EpLKw56oUElN0xVWqGCFCk1/U60hgFaosIa80DbNHsMAChZOP/10esICvoNs5MD3hB/92DZu8jT/hIXN+ckqvO2RvVEWPbOHkv2R7Je8qdbrvqDUgg0/8ZUW/iEcQWXlvEOTPVvcr4WgZBuEYWfnwfBHJyAHbCtUCJRZYwwYA8aAMWAMGAPGgDEQGLBCBXsrdDUDVqjQ1a+AxTcGjAFjoJswUHehQv4Gaj/WxQIy7XQBLUjyflEMRbjglrdR2AU87R/8yMbL6y9UmOi9OA/A6guIZUUYsIlXHPNFGnIlMiMPFxMpRDFOknjcjB9FSifBFkklnldkQMXBt8DI+YF9/NGRiS95KzASsbGStpF3wAjwhRgZPI+YARWngEE6ZSB8ZHL2PmXyTJyAm8eTcNTWkXc+vuCU5QFdqbx8jvJeVLNug2uFLTnk5pjwvCIDKg4BI+fX098j77y1ws09/nb3wqMvKiLa7u66667uiiuucMOGDWvb0LTGgDFgDKwBDDT7xsK9/K8g77XPLv7G2gGePfkyVojU47Re+x6tsdQGU1n3WJU0vBTzWJZldknY4ltoCSxa0xJZxA/YbBaMw06VVKHPjmFr4BX85wsV7IkKmjrrGwNrOgPvvPO2+8WJP2yYhl69ermhQ4a7TTfZwm06cgu3+aZbuhEb8Y0+DYO3A/Dsc4vd6X/8VTtWzVfvtcdEt8sn92w+sCF2KgOPPfYYFSyce+65jRcsDBpIe4px43d2g3w/HcU1P+05wjrOTXLxPdlDSCvXUmhlD/ZqlY//+1/YT6gNiHTzGCJPCUjOvGGgcDh5Q+7TWVKSZJ0VKiQGW6FnhQpWqNAK78PumIMVKnTHV81yNgacW758uTvjjDPcMccc4/DfcSMHvqv7yHZbU8HC5lts4rdAsjfSqFrm90b8l/ZLwVT2Zhjqvh4X9mJqz4Vdl/hJy744I6wEzvehDHs3slRjgLInawgi4IRk4GlPVGB67GwMGAPGgDFgDBgDxoAxwAxYoYK9E7qaAStU6OpXwOIbA8aAMdBNGKirUIHubV4Ll9hwvSwda+lBEGtR9PNCLReEoMdQX8AjNW6Y9j5SDJG7hJd5moNcEKy7UOHXoVAhxIo5SF6Q66NwhVIMcpPDDewk0nICJXk2jg4QbLSoEDMo5SZ5HyKLl8NoI4+QpADyDexl9sFC4kjomGZeUMCIlulme+Qtc6OUm5l3wEIMvBCUTwrN2eTiQUh2wVilTMR4cxyUc8Qrw8j7Sy45eSu9R3hiND8+Sc6kqE0erITv/FuiUIhDdOQ4kUji7NWd+R5Z/upyd8uxt7mXn3xFIrfbTp482V100UVu4EB9o0u7bmZgDBgDxkCPZ6CpNxb6X0Lec/wubs+9d6IbC3m7wGuG7qslPq0Xium4hniZ9KUVM41HfX/iJSq02hdOoldy2WewOq1tghPc4IFuMgcWRHQiFT1RYc7sq3hQcZ4/f74bM2ZMhdbExoAx0JMYaFahQhknKFTY/uM7u9HbfNz17du3zKQpsv979ml3xp9ObgpWPSBWqFAPW61n+69//cv9/Oc/d+ecc07DT+NAkcKee+9Me4tBa6MQUpbesA6zRC3HWk5KtuCFPdj5Af2RkI1yY17eE5bsQWILL+1T6DMsnbFnIHs6Z/ssoklpG5hboQKx1zInK1SwQoWWeTN2s0SsUKGbvWCWrjGQYwAFC2eeeab75S9/2ZSChdEf/ZCbPHW82/x9KFhAMNkM0XYojuOlFtlHqbxkP0bewVDLWE5n9vIhaDdGLeJwTGnFPuzYKCXdj0jiJw6+JSQtD8aEHeQQ4Tji8BP83nglD0rOM2fOdLNmzSrRmMgYMAaMAWPAGDAGjAFjoCcyYIUKPfFV7V5zskKF7vV6WbbGgDFgDHQZAzUXKkzeiosFcKM2LsTxNbiQd2aQnQvd65xueJYLeRmjvE0WnEylUAGDeHEv70eJdeCJClWFCgjmY7R/iFGRB9b4M1Q0iNmH4gv2KXqmqBGDRMHeN3Qft76ZO8yfzNgpgRR62sCDAVaJYswoL+YNVVtHxCCjnLXOW7/eKocMdsxDG2Qxk0Z6rGfXJCMpCzMhMBAr7rF/MvLaYMAXiIMmOSXTQk+M8pgC6fUxpzzXAEuyArQXMHo2RoSDFiovIBRJQczLAEmmDchZAimtt4mBUo7832saV4XgCP6Mjn4fwKFZ75GYn06fI7/5whvu5l/e5t5Y8kZVigX5IYcc4s4666xOvZGrENQExoAxYAx0MwZwY+HRRx9NNxauXFn95Wkt04o3FvqbCwcOzN5YCH+9fOgvhzW2yNFKv0zPeLzmYfkAOLXU5V6VPBoqW4YQBMCpPpQ4KCduaexPC+590FmhgrBhrTFgDHRmoYKwO3DgIDdx7+lu220+JqKmtlao0FQ61ziwf//731SwcPbZZzdcsIC9xJ7+6Qp4ctPAQS28r8CrHLYNsvcgkd5L6L68K0r2FVaoIOS0RmuFClao0BrvxO6XhRUqdL/XzDI2BsoYQMECrq2jYGHx4sVlJjXL8ISFbT/iCxam7eXwhAU5MtdeZD+l9k1ih1Zs822ZDfZm0a7MlwFlCxdtCSvkwSZpoPFwfYj0dPankn0dVFaoIARZawwYA8aAMWAMGAPGgDEABqxQwd4HXc2AFSp09Stg8Y0BY8AY6CYM1FyoMGkrussXNyDT5bJ4LS12qmdM9yHDz9uWmQc9ACptvE6KFciG7zPOygJ2vU9UmOILFQgbmJRiRZ5IsPQIyZROLuUN13i7m8xZYlZcKKVweVtOMr4ePvkO5A0nOcpelHby9q5tvVaEXJE33X9edRO6pFTZtp03a8UmsF2RR1WIbH4eI9CDC9/EtXekC8jltFXAppzKDOS9DV3le0Re93KA8vdwnXPPQkvOnFVWx6M28/YmHX2PgGfiO4SWC/ZlORRlbefN2rXcK0+/6m45bq5b9vLyIkSF5L//+7/dSSedlHKrsDOxMWAMGAPGADOAGwulYGHFihUN0UI3FuKXkKlgQZ5ok9ZpWnVK1mZex8XOG9CfMsyNs/bePGwEYotZaB/pB8jQwJHmS2fp84DlYuh12gZKK1QgiuxkDBgDgYHVUaggZG/zoY+4yRMO9IVhg0TUlNYKFZpC4xoP8vjjj1PBwp/+9KemFCyMG78T7SsGDcL7PSzMvklLtPQS9bIfgET60ooVL/vsS3211gui+NBY9AqTsIKx2EIm9tTngTZFUrwFocCksicqMA0tc7ZCBStUaJk3YzdLxAoVutkLZukaA+0w8Pbbb8eChaeffrod67bV+B7hw6NHuUlT93Tv23KzcDmGN1K8JZJrQkUc2Wclu7ABE1M/DFdtaCPG2y+WJN/kA5ysfdBlG9qzIQTZkg8NREKxSAs/ta/zIytUAAl2GAPGgDFgDBgDxoAxYAxEBqxQIVJhnS5iwAoVuoh4C2sMGAPGQHdjoK5CBUwOd/mGi2plc5Ubl+PFODEq8RNbmBTsxa+kjTcwaz+VU92FCidP5Chyf7PCKgnfIRHmWpijjxfl7cWU3BBd29aD0aHMi07Cv1yILVooSVV+Mh89F+XWdhfOdTpW5VEVqCq/KnkVTh3y+F7QPs3Iu14MHb+D/VZ/j7z4z6Vu7gl3uHfefKfmGR511FHu8MMPr9neDI0BY8AYMAYSA7ixEAULzfol5HF77eTG+YKFtdceWPIFdIqLXvqymUZxCyFfBrM07Svk+1/Z5+TbhAko7xdcYZdQYIXDy0jIdtKFkPt0Tn4huBUqMHt2NgaMAWZgdRYqIOIG62/kvvD//ZcbNHDtpr0EVqjQNCoNyDPwxBNPxIKF/5+9+4CXorr///+BS7sCggiKvSGggg0VFFQERcUWTRSNJWoUjSnfmPbN9//1+0s0RRN7D2LU2AWNGMHeK1YQBUGNiS2iYKF4QWn/+ZyZM3t2d2Z39u7svbt7X/OI7Ow5Z86cec7CnuzOe+ebb5L/f7oovC6NnWXkqD1k9H4jpGs3LwjpvzWH79PBU7OpnRPok+x1UxK0MQ/BH3YekGlvtwsfM5t6+/T2Fu7fWQ/mB+5YMnMJv4OwTucY5klm+9dmzpbJt011B5a3Pn36dBk6dGheOQXpCxBUIKiQ/quqbfRIUKFtnGeOsu0JaGDhuuuuM3dYeP/998sGGLT9ABl78GjZfMtNvL4y86JgOpXXv87JwrpgxZ9KhbMrf46mW9rplW6jT237sAMt83dhWoTrprHZxq8N/jT9+J2apsEffh9Oud0o6Jw7KlgQHhFAAAEEEEAAAQRUgKACr4PWFiCo0NpngP0jgAACNSJQclChyHHZ8IH/UV3hxrattkrS3vZmLoLWC8bNZ3X+B3a2Th9LDipc4gUV7AXotiPzoaB9knnUcbrjztTkr8W1DcvdfQbHEtu321Z3peOLKssfRmxJVBfaOBxf1Jal7DOubVx5zv7ixlHKuMM+3H02x1rH5vahz3UgEUu4z4i63KK4tmG5u8/mjNvdXnceM+bccdnn2jy3C60Lx2cbuo+5GxTaZ1zbuHJ3PwXGUWjc82d9Is9eNl1WfbMqp7fop+3bt5crr7xSTj/99OgGlCKAAAIIJBbQwMK5554rN9xwQ9m/hKwXFu4zerjss68GFrqYMdgvhN0BZX3prG+EwfuSeQg20Pc1u9g+cr9wts+1Xdgmpz+3jd+f17O/I7Nfu6qF2fsP9h50TFAh8OABAQSMQEsHFXSnG/TdSL53zA+kc2f/39dyTwVBhXIF2T5K4L333jOBBZ1XlB1Y6OIFFrwg5GidV3RbK3yftjME9z3eXbfj0rLgbdwWmUfbNu5RG7nbhe3cOYb2ndWrbqT/M3+YmrCFFoUd6pjWyKyZcwgq5Pq14vO2HFTQu6EsXLgwVr9bt26y9dZbx9ZHVSxfvlz0v549e0ZVU9aCAqtXrxb9r0OHDhXZ6/Dhw715SeeK9N0SnX7729+Wv//977G70vo777wztp4KBOpdQOdyNrCgc7xyF73DwthD9A4LG4ddhVOkoMR/rvOlrALzJDOfCuZcOU203raxj9ok7Mus+x2bP7V90Ef4YMqCNvoQNDD9BR1lbROUEVQIBVlBAAEEEEAAAQQQ8AQIKvAyaG0BggqtfQbYPwIIIFAjAmkHFUo9bL0wP+IjusLdeBcxh9tlfVLnb9asoIK3qf1A0f4afO4gbL1eue0GCmy5u13WMUWMMUkfcfvP24/2nzMmd9vo8Xktgg828/qzG0eM222rzaL6tpubevvFec74Em/ndeLu026nfWeV209x/Z3qn1lLXtvg2NxydwO7n9z6uHK7ra3PPR+23O0v6zWiHeR6x5jl9m33bbqIO6e8Rsy/M+8//4G8eM0rsnrVapctdr1Tp07m17/HjRsX24YKBBBAAIHSBfSXkG1goewLC73Awt777O79EnJwYaHzfmrff/23R7cieNv1KvzSTF3wVhrOcTJ9OC29Vbulff+2tXZ7o+L2b7bxSrWhLXcam+2D5zNeeUPumjStIOzLL78sQ4YMKdiGSgQQqA+B1ggqqNw2AwbLUYd/LxVEggqpMNJJjIBezKbziuuvvz6VwMLeo3aXUd68olvXILAQ7DczJ9AC884djsh/C/dmB26x98Q+zWzrl9jnpifbyGtttzdbBuXaNmxi92jLTIVTr+W2cdBmFndUsGpV8diWgwpVcQIYBAKtJEBQoZXg2W3NCehnRBpC/eMf/yhpBBa22W5rOcgLLGyx1abGIpwnec/sfMwvsxOvYJYXzKN8QDu5Mh/n6JZmvpXZPrfetAg6sg/OHE07DQZiZnHe5qaHoBvTrzPQsPdgTOecdaH34x8r/aFF/Dl+/HiZMGFCRA1FCCCAAAIIIIAAAvUoQFChHs9qbR0TQYXaOl+MFgEEEGg1gdKCCt6V02YJPxqr+LhtIMB8YJdwbyUHFS4eqx8thr2bfdpDDUrth462UXjBubdZ1rbt/A3dMqdru7l5jO1Dr0TXxRlD3v69yqx9aPNg32bb4A93O/e43HJtqttm9ZfhcLsz63Y/eX34V9CH7SPrvdqs/XjPbX/hhtrG+SA2HHc51s7Y8vrWHRex1ibuuMMxaUWwuP1qUXhc5YzbntPcPuyAi4zbHXPWmIIx64M7bve43HK7bVZ/NfYaeefhf8qMm2dlHa/DkLfatWtX80tnY8aMyaujAAEEEEAgHYFKXVjY1buwUBf7XmYf3VHrVCNTnnlT86cg3jueKbKPmbZ+sfOOGGzqP3h/+v/TDfwxhAVhkVkxtUEbOy4dj5bPJKhgSXhEAAFPIElQ4bCx42S7bXaQlSu9C1a8/4+wetUqWf71clm2vEkWL14kn3+xUD78z3vyr/feMf0lhT3+6NNky81L+3XrqL6TBBVG7XWA9OzRK2rzZpf1XX9D6dO7b7O3Z8PaEnj//fflvPPOM7/G+/XXX5c1+M6dO8le+wzzgpAjpFv3rmFf5r3af4v3ysKVcN4Qvu2H8wBtFswb7KMpymyrnfvN/XlHOMsImtj5SriF7dsU+KVunakO2mjfrxFUUIaqWQgqVM2pYCAItKgAQYUW5WZndSCggQW9E48GFvTHLspdNLAw9pDRssWWm5iuwvmVM5+y+3DnZX5ZONPy5mzB3Mt7yKxn14fPwhWdNfpPbN92Ghn2oTsK2psyZy5nqsL9rpFz/u8iggr+ieFPBBBAAAEEEEAAAU+AoAIvg9YWIKjQ2meA/SOAAAI1ItC8oIIenPMpWwWP1Vw4bfaWfH+lBBUaezXKIRcfmHUEdp+20H6IaJ/ro9smqt5ta9vntiu1j9w+c5+7/WldGvvTPuP6yS3PHU/S5+64o/osVp+7H9ve7cuWaVu3PHfbpM/d/uL6dNsk2ae2z21Xah/Fxu/2FzVutz53LHF9Fxp30j7i+rblxcZVrH72lDdl9t1v2u6KPvbq1UumTZsmw4YNK9qWBggggAAC5QvohYX2l5DLvbCwS5fOstfIYTJqzAjp2rXRDM5+8euOVL/jzZRn5pm2zH55bL8bDsu1E68w3CJYCUu0X60Ny/32wWb6kNnedu6XmvHofma+Ops7KgQmPCCAQLKgwhGHHiuDt92pKNfy5cvkmemPyQsvP+OFGlYUbd+n9/ryg+//IhPCLrpFdIMkQYXxJ54pG/TdKLoDShEoQeCDDz4wgYW//vWvUu68QgMLe3rzin29eYUGFvy3bu+dPnifD9/wvfGFcwWttPOAoKF56q3bzWxb97C0zPxnC3P60GJ3u6z1cJtgbMF+tfi1mXNk8m332haRj9OnT5ehQ4dG1lGYrgBBhXQ96Q2BWhEgqFArZ4pxVpvAihUrwsDCv/71r7KHN3DbfjL24MwdFnRSZ+dntnN/GhXMqUyh38KWa5E/b/O3sHMy08rtz+k43ItXltve9Of8Ee7H3d4vNNsSVPDd+RMBBBBAAAEEEEDAFyCowCuhtQUIKrT2GWD/CCCAQI0IlB5UcD4dq9JjLDmocJEXVHB+mb7YRc962EnaWJ64tnHl4SejzphsX+bRPQVOm9j+go2L1Wftw3sS196Whx+u6oYxY8rqM6ZNZH/Ohrbe343bidPIWbXt3fHZsrw+3O4cS6e7zLE59bH9ORsmaWObx7WNKw+9nTHZvsxjzHHF9hdsXKw+ax/ek7j2ttw9B+GYtZNmjjurP2cwdn9a5LbRD/31LgrvPPJPp3Xh1Y022kgefPBB2W677Qo3pBYBBBBAIHUBvbBQAwvXXXddKhcWmsDCfsOlWzfvwsKsNyL9YliH75UGj+ZgvHXbzpb7j9ref3P1m9tWpotwm6w+TF+mxP/D295uqwW2X91j8D9TqPshqOC4sYoAAonuqJA0qGA5FyycL9fffJW544Iti3v8/vE/lo032iyuOlE5QYVETDRKWeDDDz80gYVrr7227HlFJ73DwsihMsq7w0L3MLCgAzbv7pn5hHlb99/b/Vp/3bSycwHdKjMRCOcH2sYtD7r2Hpw+TKemt+y2um1QZ7p2+ueOCgpTPQtBheo5F4wEgZYUIKjQktrsqx4FNLBw4403mjssvPvuu2Uf4oBttpIDvcDCVlttZvpyPuUJ53WZ6ZQ7F/Na+pOu4DEzfwvnYnZ0ZjNT6peY596q14FTmnluCm3/uom/gV8cbONtS1DB5+RPBBBAAAEEEEAAAV+AoAKvhNYWIKjQ2meA/SOAAAI1IpA0qLDNQQO8j8WyPj4Lj9BeJBxX727Wrl3mCuWs9rbrTHXYf/6K28humGlVblBBe9JjyhpfpnuzVvSYI9pH9Ze3H/dw3MO0/bn1WpbTJq8/u13wmMa4I/twx5UzJrNrt14LnDaR/QXjtQ/Fjsu208e4tnnlBcYU9ue2ccZcaD922yTHZdsW6q/guHPGZPpzx+x37O4m1sc2qsZxJxlTrtPqVavlxYmvyPvPf2APrehj//79TUhh8803L9qWBggggAAClRNI/ZeQ9/YvLOzWfa1w0PaLZS0wFwUG7586X/PrgvJgC3vhoGnmfKlsy02ziD6CzZ0vnv1GQVP/e+fMDs1YCCqEaqwggIAn8M03X8u5F/1vQYtSgwra2Uf/eV/+dtvVohf9FFqGD9tH9h15UKEmResIKhQlokEFBT766KMwsLB8+fKy9qSBhT333k1Ge4GFbt27eX1FzRvCCUH4uZKdd2Te8p35QNy8QkfqNXPnJuHg7Ta2w6BC5yWmKCjXbWeZOypMDTeNWuGOClEqlSkjqFAZV3pFoNoFCCpU+xlifLUioP/f5aabbjKBhX/+M/mPE8Ud34CBGljYR7bqt3k4b9O24Wc9wVzMn5M55draTvnCeZfZUJuaJexDn9m2Zl1naNmLaev2Y9rpZl5LbezVmW28R4IK2XY8QwABBBBAAAEE2roAQYW2/gpo/eMnqND654ARIIAAAjUhQFChUQ7JuaOCOXG5nxSmeDb1I0V74XXBbnMvQo8aU5I2BXeSvLJi4446ruTDKtgy8Zi1F9cyakxuvbaPaqPlKSyJx51kTEnapDBm7aJi4y7RetU3q+S5K6bLx7M+SXxkO++8s9x///2y3nrrJd6GhggggAAClRXQX0L+05/+JPpLyGlcWDhiL+/CwjH+LyHr+7i+bwX/8x79Nxv9036ZbB/1KO26aWW/IHbKtR+7aFvnqV9sy5z9+I28trZx0GbmK2/IXZOm2e4iH19++WUZMmRIZB2FCCBQXwKVCiqo0sOPT5XnXniiIFif3n3ljFN+UbBNsUqCCsWEqG8JAQ0s6Lxi4sSJ5c8rOnWUERqE3He4dF9bAwuZuYK3Fh5OOH8wRZn3/LA8azu3j7ALMwcJ5wq2OJgzZCYRfoWZg+i+gg10RkJQwaJVxyNBheo4D4wCgZYWIKjQ0uLsr94FVq5cKTfffLP84Q9/kHfeeafsw916wJZy4EH7SL/+m5u+7FxNp3XmEx7z6FXZOZhZNRM8M1czG/nVfnstsNsG6+GD04eW6WL2F87f/LJwe92N3cZ7JKgQ+PCAAAIIIIAAAgggYAQIKvBCaG0BggqtfQbYPwIIIFAjAomCCuMGy8CD+1fXEemHc7kXYAcjLPuOCv7nixU5XvOhZtBzSWGFuDG5BnFtUjiSksadZEy2TbWMWY3smHQ9alzF6nW7FJaSrHV/dlxRY3brdT2ujdaVuZQ0bjtm3WfcmGybuPqY8X7z1Qp55uLnZOE7n8W0yC8eOXKk3HPPPbL22mvnV1KCAAIIINDqAqleWOj9EvKIvXaV0ft6v4S8dlfzPhS+1dgvfr0jtl9K5z2qhrdB+L5n18NOnG1DOdPIf8sz7bytg0fTnd3WL5QZBBVCOVYQQKByd1RQ2yVLFsmlf/mjrFq1Kpa6oaGDnPXL82Lrk1QQVEiiRJuWEtDPwf785z/LNddcI8uWLStrt528wMIee3rzijF7ev9/smvW+7s/X9Du7fu+M0cI3vP1IZxT+E1jnweb+OP1nvhTCTuJsMXBvmz/XiuCCr5NtfxJUKFazgTjQKBlBQgqtKw3e2s7AhpYuOWWW0xg4e233y77wLfuv4UcYAMLwTTLzrnsrCvvcyJnkmZXzUwt3N5bCde9IYbzNDtcO3/T58G6qXLXtcrv5OyzLvTuirfStIj6Y/z48TJhwoSoKsoQQAABBBBAAAEE6lCAoEIdntQaOySCCjV2whguAggg0FoCiYMKB3lBBXvhcO5ggw/ZcuvthfjmQ7ncbXKel9LWfqhnuogYU7OCCjnjqeRT62GPuZL7SrPvWhx3LY5Zzxnjbt4rd/mXy+XJC56RRR8uTtzBYYcdJrfffrt06dIl8TY0RAABBBBoHQGdt9pfQk7jwsLh3oWFo/bz7rAQ/BKyHlXcF8623G/jH795v7ZfNttvo50+TFs7cfXamab6h9fWXzd/2hZBp2tk5quz5c47pvrPY/7kjgoxMBQjUIcClbyjgnJdf8uV8v4H/yoo998//Z03X24s2KZQJUGFQjrUtZbAxx9/bAILeiFXufOKjh07yvA9d5HROq/o4d1hwX+Ltw9Z8wt/yuDNBcI2wYpCuGXuelBnioINs+YmFtFrEJab+YYXVJgxRybfXnheMX36dBk6dKjthccKChBUqCAuXSNQxQIEFar45DC0uhDQwMKtt94qv//97yWNwEK/rTc3gQUNLgRTssxnOZ6YzrfsnMs+KqSd3/nr4ZZhW7fcrw3+1IeguenPzvd0A7sEZQQVLAiPCCCAAAIIIIAAAipAUIHXQWsLEFRo7TPA/hFAAIEaEUgcVCh0R4XgA7RaDyq4F5vlnr527bITEfbDx9xyd7uwjQvjdBPW5/Sd1Yd+Oml9g4rcfaY6brO7Nd6InYE6qzqE5ow7csyms+Cgch7y2nsfwuaWuZuEY4oZt2sU149pkzOm3LZuP+7+dT2vbfDBcW65u13RcSfpo6VfI94B6Lir7TWy5JOl8tQFz8pXC75yiQuun3jiiTJx4kTp0KFDwXZUIoAAAghUl4BeWKiBhdR+CXmEF1gYM8L7JeRu4TzHvkfnPSpFMDdz5wXx68EGdkqn23rvo6aL4H0+6M7v2Hsy49U35K47pumGsQtBhVgaKhCoO4FKBxXuue8OmTnrpYJuPzz1V9J73fUKtilUSVChkA51rS0wf/78MLDQ1NRU1nA0sLDHCA0sDJe1e3S3U4as+YX/9u/NBYIJQDAr8PfrlrnrWus9z5pv2A78qmD7TL9mvuG1MXdUIKjg+1TBnwQVquAkMAQEWkGAoEIroLPLNimgd4qzgYW33nqrbIOt+mlgYaRsPWDLcD6nnepnRZnPi0yJ2ZednmXN2fxJnKk3LW0j74lpp4867zNzv2Aul9VGt/KWoIyggs/BnwgggAACCCCAAAK+AEEFXgmtLUBQobXPAPtHAAEEakQgUVDh6MEyUO+oUOqiH6zlXORuuihUbvcRt53WR9XZ7bzH5txRwX6o6HSTtxpecO6N336AqI3CcmcLt7+4C7qz2kSEFdx6p+us/cW1iWrvtjVjinDMa2M7Ctq69VpV7Njt5lltc/zcNnbdHZ+7z6j9+Z/z6ovKX6K8i/bhbeq2sX3po91nXH1U27wxFTm/UWPWft192nG4+3Pr3XK3bVybqPZuW/ccuG3z2tjKVnyNfPH+l/L0hc/J8kXL7WiKPv785z+X888/Pzy/RTegAQIIIIBA1Qmk/UvIemHhKHthYfAFsH3fs98R2y+bw7lg7rzGPg+mJuEMxevArGtH5n/+o0U1dX4FQQWLwiMCCBiBSgcVHnhkirzw8jMFtU876Uzpu/5GBdsUqiSoUEiHumoR0MCC/n/Ev/zlL5JGYGH34UNMELKHBhaceUU4p7ArHkDkvMLOFyyQfe5PGoJr1YIZhHkwDTLzjWC712bM5o4K1rAKHgkqVMFJYAgItIIAQYVWQGeXbVpAAwu33XabucPCvHnzyrbYst9msv/YkdLfCyzoonO7zPzOdq9lMfO6TJNwO9OPKfe3CyZxpg//D7tR0GfQ9zlnXSQrVqzMVOasjR8/XvSOYSwIIIAAAggggAACbUOAoELbOM/VfJQEFar57DA2BBBAoIoEKhZUMF+SBgfqXhCfpNz6JNnOtnUeSwoqrNMoB190gLN1/Kq9mDz8Atlpauu0KLferTObeMdlP8R0usi6YDqqPqutl9bI3Y9b767r/qPa5o4rt02xet2HaeOcp7TGbfedOyazT73o33kd5bax2xqDBNbarti4TV8J/rD7zh2TbmrCA8G4c+vtduEuEoy72Ji1z9z9hP3nrMS1zR1Xbn+59dptbhstKyU4ETcW7cdd7L4XvLVQnrn0eVnRtMKtjl3Xsfzxj3+UX//617FtqEAAAQQQqC2BilxYmBdY8E3M+5z3fm7f76Lej01Z+J4fWOqX2Lrqf2vtbx+0CVqYMt125quzuaOCReERAQSk0kGFSXffKG/Om1VQ+pc/+a2stVa3gm0KVRJUKKRDXbUJfPLJJ2Fg4auvkt+xL+o4OnTsICawsO9w6dFz7fCzB50O6OLOIwrOMaLa23mEO8fI6VP38drMOTL5tnt1NXaZPn26DB06NLaeivQECCqkZ0lPCNSSAEGFWjpbjLWeBDSwcPvtt5vAwty5c8s+tC232lTGBIEFO48L53X6qY/5nz9Js/VZO9V6u4FX4bcMyoJyU28rgo3deSJBhSxRniCAAAIIIIAAAm1egKBCm38JtDoAQYVWPwUMAAEEEKgNgYoFFfTw7YdpzoXsRiWq3Ja5bO52br1b7rYP1tMIKtiLoN3u7YeBbpl3LXjRxe0ruEQts40eV6E+7HHntonYzt1PZgd6GrzGth9bUWJ/WeO2feX2YfvWx7g2Wp6zXdS4E43Z7qdAf3njzmmrXYRL3JjDBtkrZY07uyuPJDOwrDFruwizrM3jxh2xnbsft49E3kX6yxp33Jiyd+o/yxy6/7zIfmwXur+PZ86X569+UVZ9s8oWF3xsaGiQq6++Wk499dSC7ahEAAEEEKhNAXthof5bX+4vIZsLC/cYIvuYCwv1l5B9E/89M/Ou537BbFp47fw2memQXx5sE37xrKWmsd3Me6ptCCoYEP5AAIFQoNJBhSuu+ZN89vmCcH+5K506dZb/+dkfcotLek5QoSQuGleJwKeffioXXHCBXHXVVZJGYGHYHjvLqDCwYA/Se+d35hj+ul+QNcewbWxjb/Nw1Vsx1UFB1nZeO4IK1ro6HgkqVMd5YBQItLQAQYWWFmd/CGQLaGBh0qRJ8rvf/U7efPPN7MpmPNt8y01kzIF7y4CBW2XmZPqJjjcpC2Zm3nowgXP6N0V2zmbLvef+XE4L/D700S/0G5kWQd8EFSwcjwgggAACCCCAAAIqsGzZMnn33XfzMNZbbz3p06dPXjkFCKQtQFAhbVH6QwABBOpUoOSgQv5naxmZ3AuOMzXRa25fUdsWq7e9uu28slmT35A3701+O9du63W1PfGIAAI1IrD009J+2bJz585yyy23iH4xyIIAAgggUN8CGljQCws1sJDKhYW77yz77DdCevToFnx57E8+9c+sL56DOal+gZz1fbT9Ejqcs5qvmIMvnZ225stpL6jwindHhUnTCp6kl19+WYYMGVKwDZUIIFAfApUMKrz3/j/lhluvLgi1/nobyukn/6xgm2KVBBWKCVFfzQILFiwIAwtLly4ta6gdOjTIUJ1X7DtCeq7jBSG1N++PYGaQva5VdkLhzDHMAMw2poH/NNNR0GewgVdLUMEQVc0fBBWq5lQwEARaVICgQotyszMEYgVWr14dBhbmzJkT2y5pxeZbbCz7HTBSBmyzpdnEn7rZz3zCGZ7fnTN/C2dq9vMibRHM54IHW+B/vmQ+L9KiNXLO/10kK1as1C0il/Hjx8uECRMi6yhEAAEEEEAAAQQQQAABBNIWIKiQtij9IYAAAnUqUFJQIfz0LAYjKmwQ09QUu/1FbVusXjtx2wT7MndUmJo8qBBsxgMCCNSpQPfu3eXuu++W0aNH1+kRclgIIIAAAlECqf4ScnBh4aj9hsvaPbqb3ek0NPcCQq3QsnCKGnzp7Jfrn/4StvAaZvrwSr32M18lqGCdeEQAAZFKBhVuu/M6eeudwhfoDOw/SMYdcWJZp4KgQll8bFwlAhpYuPDCC+XKK6+UNAILuw3byQQhe/YMAgt6nMEEImueoIVFywMknYMEbe0KQYUqeQEFwyCoUF3ng9Eg0FICBBVaSpr9IJBMQAMLkydPNndYmD17drKNCrTabHMvsHDgXuYOC9rMTMd0Xma3CedyzmdApqFfEc7fzLaZxqYHfWr78h4JKlhUHhFAAAEEEEAAAQQQQKAaBAgqVMNZYAwIIIBADQi0WlAh+KwtJGpOUCG3j6AzggqhKisItHmB3r17y3333Se77rprm7cAAAEEEGirAmn/ErJeWDjSCyz07Lm2+fY5/OI4ALbBAzNVdb5tdlZNIMFvnn1BIUGFtvoq5bgRiBeoVFDh+ReflIceuzd+x0HNIQccKTvvOLRou0INCCoU0qGu1gQWLlwYBhaWLFlS1vAbGhpkt9139O6w4M0r1ukRXNWmD8EHXt6DO8+ILw+Goe3thCN4JKhQ1ilKfeNiQYV11llHXnjhhdT3S4cIINC6Aj/60Y/koYceih2EBhnuvPPO2HoqEECgMgIaWNC/e7/73e/kjTfeKHsnm262kXeHBS+wsG0/M69z527auf2cKJjp6cTN7NNO3/w2OqEL1mxDr4FfRFDBgPEHAggggAACCCCAAAIIVI0AQYWqORUMBAEEEKhugURBhXGDZeBB/UWiwgTu4dkPzdyyiG30S9N2uZ257ZL0E9VG9+v1Y4IK93JHBfc0sI5AWxTYZJNN5MEHH5RtttmmLR4+x4wAAgggkCNgLyy84oorUvkl5F2HeRcWjvYvLAwvCvT2Gb8eDMh+waxfM/v/8yu03PuPOyrknDieItDGBdIPKqyRl2c8L/c9NMX7N2d1Qd1u3daWn/7g/5OGhg4F2xWrJKhQTIj6WhT47LPPTGBB5xVpBBZ2HbaDN68YIT17eUFIu5h5QmayYC5R857qYh4yf4QXr3lTCZ2MmDb6x2szZ8vk26aGz6NWpk+fLkOHlhdIiuqXsnyBYkGF/C0oQQCBtiBAUKEtnGWOsZoFNLBw1113mcDC66+/XvZQN9lsQ9lv/71loBdYyJ+/+fM0fxoXrGembsFnSl6B/z9/LPp5ka55j9xRoezTQwcIIIAAAggggAACCCCQogBBhRQx6QoBBBCoZ4GKBxUUzwkhuBduZYUVnDb+J2456sXqnf0QVMix4ykCbVBg4MCBJqSw6aabtsGj55ARQAABBAoJaGDhoosuktQuLBy6g4z0fgl5Hf0lZG9x57vZ68GonC+YTfugWL9wJqhgMXhEAAErkF5QYY18+J/35dEn7pN/v/9P233Bx/32OVj2GDqyYJsklUmCCkn6KbXN6JFjZcSwUaVuRnsEShLQwIKdVyxevLikbXMb6x0WdvHmFfvsu4c3r+hpqrPnEpmr2Lxpg7P4T7StKQ8q9ZK2WTPnEFRwpFp7laBCa58B9o9AdQoQVKjO88Ko2p6ABhbuvvtuOeecc2TWrFllA2yy6Yay7/7eHRa26Sftgu84o+Z2fgjB352pD+dywRB0jqer3iNBhcCEBwQQQAABBBBAAAEEEKgKAYIKVXEaGAQCCCBQ/QIVDyq4AQPl8D5N04/UskIKWu62879f1dLMYuuj6rSVrfdWCSpk2FhDoC0K7LLLLnLfffdJnz592uLhc8wIIIAAAgkF7IWFl19+eSq/hLzLbl5gYT+9sNALLARzVvNVsl0P57FeqVn3/vD/5z2GlTLjlTfkrknTCh7Fyy+/LEOGDCnYhkoEEKgPgSRBhW0Hbi+Dt93Z+6dkjaz27pKwatVKWblypTQt+0q++mqJLPxsgcz/9D/e3WSSX0Td2GUt+ekZ/yudOnUuG5KgQtmEdFADAp9//rlcfPHFctlll0n5gYX2MmRXDSx4Qch1i88rLA9BBStRvY8EFar33DAyBFpTgKBCa+qzbwTyBXROZQMLr732Wn6DEks23mQDP7Dg3WHBBBaCj4DsZ0bmafBH5uMh+9mRt7OgUMdFUKFEfJojgAACCCCAAAIIIIBARQUIKlSUl84RQACB+hFIFFQ4erAMPKi/uehBjzwvZGA5nLCALcp7zFyDlRUusBdzmfZR/XjbmQ/tvAZ5+89pT1AhT50CBNqMwKhRo2TKlCnSvXv3NnPMHCgCCCCAQHkCemGh/hKyBhbKv7CwQYbstr1/YWGvHuH82Q8kmAmtGWzw/bO3HnzxnPkmWma+OlvuvGNqwYMiqFCQh0oE6kogSVAh7QPu2LGjHHfUeNl0ky1S6ZqgQiqMdFIjAjqvuOSSS0xgYdGiRWWNuqGhvey8qz+v6NWrZ/i5mD+v8Lp25g/+3CJ/XvHazNncUaGss5DuxgQV0vWkNwTqRYCgQr2cSY6j3gQ0GKDfNegdFmbOnFn24W3kBRZGjxkh22zX3/z2mvnO035UFMzrzJxO9+Q9N0VBud352WddKCtWrLRP8x7Hjx8vEyZMyCunAAEEEEAAAQQQQAABBBCohABBhUqo0icCCCBQhwLNCSooQ15YwC8sLhR+ymY6ybSPKw9a6AeCdsnad05IQdsQVLBSPCLQtgSOOOIIufXWW6Vz5/J/9bVtyXG0CCCAAAIqYH8JWQML6V1Y6N1hwbuwMDKooDs1Xzx789zMVJeggrqwIIBAKNDSQYWGhg5yzHdOlq226B+OodwVggrlCrJ9LQp88cUXJrBw6aWXpjKv2GmXwSYI2WvdYvMKT8v5DO21mXO8oMK9BQmnT58uQ4cOLdiGynQECCqk40gvCNSbAEGFejujHE+9Cej3k/fcc48JLMyYMaPsw9to474yasyeXmBha3OHBTN1c+Zv5iMi73luue6YoELZ/HSAAAIIIIAAAggggAACKQoQVEgRk64QQACBehYoJahgL7DKCgrk4kQEB8ImzgVYpsxtW6hOG3v1+usikft2+/GaJgkqjBkzRhoaGsww+AMBBGpfYNCgQXLuuefy97r2TyVHgAACCLS6gF5YePHFF6f2S8jmwsLRw2Udc2FhZtJr1swXz2aiGx73jFffkLvumBY+j1rhjgpRKpQhUJ8CLRlUaN++QY46/AQZsPV2qWISVEiVk85qTODLL78MAwu6Xs7Svn172WmXQUFgYZ0wkODPKbTn/AvauKNCOeLpb0tQIX1TekSgHgQIKtTDWeQY2oKABhb+8Y9/mMDCq6++WvYhb7jR+t4dFvaUgcEdFswXoUGv5sfb9OMik1bwC3XOdw53VCjbnQ4QQAABBBBAAAEEEEAgPQGCCulZ0hMCCCBQ1wKJggrjBsvAg7xfU7SBAPMNqMMSV+40sZvYpqbKeWI/bIsMImhjp62GFuyi4QVd3O1MUGHqPNsk8rGpqUkaGxsj6yhEAAEEEEAAAQQQQEADC/oryPpfuRcWNjS0lx13di4sDOawOge2Xz6ruM5tZ746m6ACLz8EEAgFWiqosO3A7WX03mOl1zq9w32ntUJQIS1J+qllAZ1L2HmFzjHKWTSwsOMQb17hBSHX7d0zuIGC9/mY/z+/a51jeGuzZsyWybdPLbg77qhQkCfVSoIKqXLSGQJ1I0BQoW5OJQfSRgT0c5ypU6fK2WefLa+88krZR72BF1gYte8I2XbQAO8OC/53nvazIvPo7cF+F3rOWRfJihUrLNDEtwAAQABJREFUY/c5fvx4mTBhQmw9FQgggAACCCCAAAIIIIBAmgIEFdLUpC8EEECgjgWaFVRQD/+zMl/GhgjcMsfMLbZNTbXzxH7Y5gYOnC6KBhW0rd2WoEKWHE8QQAABBBBAAAEEyhCwFxZecsklZQcWMhcW7uFdWLiOCSmYH8czfxBUKOM0sSkCdStQ6aBCx46d5IRjTpONN9ysYoYEFSpGS8c1KLBo0SJz1ya9e1MagYUddtrOu8OCN69Y17vDgreEn8FpUMH7b9bMOQQVquh1QlChik4GQ0GgigQIKlTRyWAoCJQgoHOtadOmmcCC3vmy3GWDDdfz5nUjZLvBA/yugvmcPvHneGu8OyoQVCjXme0RQAABBBBAAAEEEEAgPQGCCulZ0hMCCCBQ1wIlBxXCbzxLY9HNnFxCaRtra7txxP71l0RsSEGbElRQBRYEEEAAAQQQQACBNAX0wkL9JWQNLKRxYeGOO28nI0fvIb30wkLvy2e7zHj1De6oYDF4RAABqXRQoUOHjnLIAd+R7QcNqZh2kqDCFpv1k/XX2zC1MbRr106GDx0pXbt2T61POkIgTQGdV1x++eWigYXPP/+8rK41CLnDTtvKyFFeYKFPL7+v4MI2ggpl0aa+8YMPPijz5hW+C2zqO6VDBBCoeoF+/frJ2LFjq36cDBABBKIFNLBw3333mcDCSy+9FN2ohNK+G2hgYbhsN0jvdO99ORp8ZqSfHJ1z1oXcUaEES5oigAACCCCAAAIIIIBAZQUIKlTWl94RQACBuhFIFFQ4erAMPKi/+SU2PXA3FJAIwoYMtHHmGqxEmxYKKMR1QFAhToZyBBBAAAEEEEAAgXIF7C8ha2AhrQsL9/YuLOzt3WFBl5mvzpY775hacJj6S31DhlTuouKCO6cSAQRaVKDSQQV7MMN23Uv2H32ofZrqY5KgwvgTz5QN+m6U6n7pDIFaEFi8eLEJLFx00UUpzCvayfY7eoGF0cPNvII7KtTCK4AxIoAAAggggEA9CWhg4ZxzzpEXXnih7MNaf4M+so83r9M7LNivWc8mqFC2Kx0ggAACCCCAAAIIIIBAegIEFdKzpCcEEECgrgUIKtT16eXgEEAAAQQQQAABBCokoBcWXnbZZSn9ErK9sHAP+fD9jwkqVOic0S0CtSiQJKiw9/D9ZMvN+8s3K76WZcuXyfLlTfLpgvky7505smTJosSHvYd3B4L99jk4cfukDQkqJJWiXVsWWLJkSRhY+Oyzz8qiaN++nQzeYVvZe9Qw+fijT2Ty7YUDkNOnT5ehQ4eWtU82RgABBBBAAAEEEMgI3H///SawoPOscpf1+/Yxd+Qc5AUWzvm/i7ijQrmgbI8AAggggAACCCCAAAKpCRBUSI2SjhBAAIH6FkgUVBjn31GhkIR7owT7yx5u+zXerRRKvhOD20EJ69xRoQQsmiKAAAIIIIAAAgiUJaCBhSuuuEL0l5DTuLBw9Wp3Zh09NO6oEO1CKQL1KJAkqHDEocfK4G13ijz8eW/PlqkP3iVLly6OrM8tHDlijOzt/ZfmQlAhTU36qncBDSzYecXChQvLOlwNLCSZVxBUKIuZjRFAAAEEEEAAgViBBx54wAQWnn/++dg2SSvWW7+3fPpJ4fnh+PHjZcKECUm7pB0CCCCAAAIIIIAAAgggUJYAQYWy+NgYAQQQaDsCaQQVsi+l8p+5oQQNKdjFLQ/vVaqVmSbean4ffpPoctu33W7WpNkyd+o8Wxz52NTUJI2NjZF1FCKAAAIIIIAAAgggUKqAvbDwwgsvLDuwUGzfBBWKCVGPQP0IlBtUUIll3h0WJt19o/z7vXcSwRw69ijZafvdErVN0oigQhIl2iCQLbB06VITWNB5RbmBheye858RVMg3oQQBBBBAAAEEEEhT4KGHHpKzzz5bnnvuuTS7zeuLoEIeCQUIIIAAAggggAACCCBQQQGCChXEpWsEEECgngRaIqigXjZEEBlUcEIKsW3j+tANgsXu43UvqPAmQQXLwiMCCCCAAAIIIIBACwpoYOHKK6+USl5YSFChBU8ou0KglQXSCCroIaxatUruvvdWmT33taJH1KFDBzn5uB/JBn03Lto2SQOCCkmUaINAtIAGFq666iq54IILZMGCBdGNyiwlqFAmIJsjgAACCCCAAAIJBR5++GETWHj22WcTblFaM4IKpXnRGgEEEEAAAQQQQAABBMoTIKhQnh9bI4AAAm1GoNSggmYK2pWhY8MEbhdZ4QW3Imbd9hG33axJbxBUiLGjGAEEEEAAAQQQQKBlBPTCQhtYSPvCQoIKLXMO2QsC1SCQVlBBj2XNmjVy5z03yZy5s4oeWq91esvpJ/9MOnbsVLRtsQYEFYoJUY9AcYGvvvoqDCx8+umnxTcooQVBhRKwaIoAAggggAACCKQg8Mgjj5jAwjPPPJNCb5kuCCpkLFhDAAEEEEAAAQQQQACBygsQVKi8MXtAAAEE6kKglKCCe+OD5oYVbMggFy8udJDbTp+7fURtR1AhSo0yBBBAAAEEEEAAgdYQqMQvIRNUaI0zyT4RaB2BNIMKegSrVq2Um++YKP9+/59FD2jnHYbKIQceWbRdsQYEFYoJUY9AcgENLFx99dXmDguffPJJ8g0LtCSoUACHKgQQQAABBBBAoIICjz76qAksPP3006nshaBCKox0ggACCCCAAAIIIIAAAgkFCCokhKIZAggg0NYFWjqooN5u0MD6RwUObF3Uo/YRtw1BhSgxyhBAAAEEEEAAAQRaUyDNX0ImqNCaZ5J9I9CyAmkHFXT0X3+9XK698TJZ+FnxX2U/5jsnS/9+25Z10AQVyuJjYwQiBZqamkxg4fzzz5dyAwsEFSKJKUQAAQQQQAABBFpM4LHHHjOBhaeeeqqsfRJUKIuPjRFAAAEEEEAAAQQQQKBEAYIKJYLRHAEEEGirAkmCCtuPGyQDDxrgBQMyi7m7whovLNDOLc0PIcSFCcKwgnbkdRHbLmIfmVFErxFUiHahFAEEEEAAAQQQQKD1BTSw8Je//EXKubCQoELrn0dGgEBLCVQiqKBjX7Bwvkz822WyYsU3BQ+le7e15Yen/ko6d+5SsF2hSoIKhXSoQ6A8AQ0s2HnF/Pnzm9UZQYVmsbERAggggAACCCCQusATTzxhAgv62JyFoEJz1NgGAQQQQAABBBBAAAEEmitAUKG5cmyHAAIItDGB5EGF/llhgjVegMAuNqwQhg9sRfBYKIRgm9o+7HN9jNqHWx+3TlAhToZyBBBAAAEEEEAAgWoRKOfCQoIK1XIWGQcClReoVFBBRz5r9ity9723FT2InbbfTQ4de1TRdnENCCrEyVCOQHoCy5YtkwkTJsif//xn+fjjj0vqmKBCSVw0RgABBBBAAAEEKi7w5JNPmsDC448/XtK+CCqUxEVjBBBAAAEEEEAAAQQQKFOAoEKZgGyOAAIItBWBpEGFbbw7KrhLGCJw7oZQalBB+zP9OH24+wjrvZWoIENuW/ucoIKV4BEBBBBAAAEEEECg2gU0sGAvLEz6S8gEFar9rDI+BNITqGRQQUd5z7Q7ZObrLxUd8AnHnC5bbNavaLuoBgQVolQoQ6AyAhpYuOaaa+RPf/pT4sACQYXKnAt6RQABBBBAAAEEyhV46qmnTGDhscceS9QVQYVETDRCAAEEEEAAAQQQQACBlAQIKqQESTcIIIBAvQskCSrsMG6wDDyofyyFDSjE3TkhdkOnolgfhept2MF2N2vSbJk7dZ59GvmoF4Q1NjZG1lGIAAIIIIAAAggggEBLC5TyS8gEFVr67LA/BFpPoNJBhWXLmuTya84TfSy09Fqnt5xxyi+koaFDoWaRdQQVIlkoRKCiAjqvmDhxogks6Gd/hRaCCoV0qEMAAQQQQAABBFpf4OmnnzaBhUcffbTgYAgqFOShEgEEEEAAAQQQQAABBFIWIKiQMijdIYAAAvUqUG1BBXWOCjzYoEJufXhnB79C/xSCCoaBPxBAAAEEEEAAAQRqUMD+EvKf//xnibuwkKBCDZ5YhoxAMwUqHVTQYc147UX5x/2Tio5wr+H7yT577l+0XW4Dggq5IjxHoOUEli9fHgYWPvroo8gdE1SIZKEQAQQQQAABBBCoOoFnnnnGBBYeeeSRyLERVIhkoRABBBBAAAEEEEAAAQQqJEBQoUKwdIsAAgjUm0CtBxX0fIRhhXb+2SGoUG+vUo4HAQQQQAABBBBoewKFLiwkqND2Xg8ccdsVaImggvf/quW6m6+UDz78d0HohoYGOf3kn0nvddcv2C63kqBCrgjPEWh5AZ1XXHvtteYOCx9++GHWAAgqZHHwBAEEEEAAAQQQqHqBZ599Vs455xx56KGHssZKUCGLgycIIIAAAggggAACCCBQYQGCChUGpnsEEECgXgRKCSqEgQD34L1wQNQdELSJbd+uXZAgCLbT8qgyt1tdd9uYOyqs8Vu45XYbt37W5Nkyd+o8WxX52NTUJI2NjZF1FCKAAAIIIIAAAgggUC0C9sLC8847T+wvIRNUqJazwzgQqLxAywQVRD5d8LFMuP5iWb16dcGD2nSTLeSkY8/w2mT///xCGxFUKKRDHQItK/D111/LX//6V9F5xQcffGB2TlChZc8Be0MAAQQQQAABBNISeP75580dFh588EHTJUGFtGTpBwEEEEAAAQQQQAABBJIIEFRIokQbBBBAAAEpO6jgGUYGB7wwgl3cehte0Lq48lK2s2310fZNUMFVYR0BBBBAAAEEEECgHgT0wkL9JWS9sHDKlCkyZMiQejgsjgEBBIoItFRQQYfx0GP3yvMvPllkRCKHHHik7LzD0KLtbAOCClaCRwSqR0DnFdddd52ce+65MnnyZBk6NPnf6eo5CkaCAAIIIIAAAgggoAIaPD377LNl0003lQkTJoCCAAIIIIAAAggggAACCLSIAEGFFmFmJwgggEDtC5QSVNCjtWGA8Mhj7qhg27lhhNztC9XpjzPm3qkhrk87FntXBYIKVoRHBBBAAAEEEEAAgXoT0AsLV65cKV27dq23Q+N4EEAgQqAlgwq6rysm/lmWLFkUMZJMUZcujfKjU3/l/TvUPVNYYI2gQgEcqhBoZQGdV6xYsUK6devWyiNh9wgggAACCCCAAALlCnz++efSq1evcrthewQQQAABBBBAAAEEEEAgkQBBhURMNEIAAQQQKDWoECVmAgK2IriRQm4IIayOudNCWC/OnRg0rRCx2MCCVrn7seOYNWm2zJ06L2LLTFFTU5M0NjZmClhDAAEEEEAAAQQQQAABBBBAoMoEWjKooIc+e+5rcueUm4oqbLfNjvKdw44r2k4bEFRIxEQjBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQKBmBAgq1MypYqAIIIBA6wpUW1BBNWzgIPeOClaKoIKV4BEBBBBAAAEEEEAAAQQQQKCeBVo6qKCWN98xUf75r8Lhf2135LeOl20H7qCrBReCCgV5qEQAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEak6AoELNnTIGjAACCLSOQOpBBT0M76YIJmQQcUOEuJCBe/RJgwru3RT83fp3Y+COCq4m6wgggAACCCCAAAIIIIAAArUq0BpBhSVLF8vV114gy5Y3FWRrbFxLzjjll9Kta/eC7QgqFOShEgEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBCoOQGCCjV3yhgwAggg0DoCSYIK248bJAPH9o8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CCCCAAAIIIIAAAggggAACCCCAAAII1JEAQYU6Opk1eigEFWr0xDFsBBBAoKUFqiaooAeeyRz4DE4gwRRofW6ZbuaFFWxIQdsRVFAFFgQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAgXoTIKhQb2e09o6HoELtnTNGjAACCLSKQMlBhaiwgBswiAgSZB2Ybeu1s+GCdnkJhawtkj2x/XqtCSokI6MVAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIBAbQkQVKit81WPoyWoUI9nlWNCAAEEKiBQUlDBCQNk3dnAlhcLKej4bVtvdc2azAZphhUIKlTghUKXCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACrS4wZ84cOeWUU/LG8f3vf1/0PxYEKi1AUKHSwvSPAAII1IlAs4IKmXxB6QpOUEHDDnpXhVRCCnYkXv8EFSwGjwgggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggEB6AgQV0rOkJwQQQKCuBRIFFcYNkoFj+2uqoLTFhhLc7WyZ9uSWuz3bNnH12jZoY+/K4IYdTFBh2jy3x7z1pqYmaWxszCunAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAgWoCgQrQLpQgggAACOQIVCyrYsIHuzw0cxJW747Jt3O2i6rXrNZlGNqxAUMHFYh0BBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBIR4CgQjqO9IIAAgjUvUDioMKB3h0VSlkKhQ20LpMvKKXXTFunjzWmMxtTECGokGFiDQEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEAAAQQQQAABBBBAAAEEEEhLgKBCWpL0gwACCNS5QKKgwlGDZODYhEGFQgGFhJZ+8EAkEz1ItqHNPrw+ebbMnTav4EZNTU3S2NhYsA2VCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIZAYIKGQvWEEAAAQQKCBBUKIBDFQIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIAAAggggAACCCCAAAIIIIBAKEBQIaRgBQEEEECgkEDqQYVCOwvq9I4Jpd4tIUG3YZNZ3FEhtGAFAQQQQAABBBBAAAEEEEAAAQQQQKB8gVWrVsrq1aulY8dO5XcW0cPq1atk1apV0tDQIO3bN0S0qN6iNWvWyFdNS2Wtxq7e2NtXbKDqs2TpItN/j7V7Srt2ldtXxQ6CjhFAAIEqFajl96GkpG3hGJNa0K5tCTCPjT/fzGPjbahBAAEEEEAAAQQQQKCYAEGFYkLUI4AAAggYgbSDChpC0CUriNDOFJk/9AMfu2S1sYUpPBJUSAGRLhBAAAEEEEAAAQQQQAABBBBAoEoF1sgDj9wjX321tNXHN2b0odK929oy9YG7vLFkPvNxB7Zh301k5x2HukWprX/99XJ59Mn7vQDBqsg+9xg6Unqt0zuyrpTCBQvnyx1//5sJEZxywk9SCSusWbNa5r71hrz62ovyqdf/kiWLvP47mLBCjx49Rd2G7jJCNt14i1KG2iJtP/n0Y3n332/Jpwvm+/9541+5coUZf+9115P1+2wg6/XpK1tu3l826LtRM8e0Rt7/8N/y+uxX5aOP35fFixd5YYivvL7815kGOtbpua45v+v26iP9+20rm2+6VTP2tSZ4/WZv2rVrdxk5Yr+KhCGeeOYhWbp0cdYOt9pigGwzYHBWWdpPVq5c6f3bMSWv2256rHvun1dOQXoCy5Y3yaNP3JfXYadOnWX03mPNvy15lSkVfP7FQnnuhSfyehuw9Xay9Vbb5JX7BS3/9+L+h6d4//6tjBlP84oHbbtT5L8LcfsaPmwf8+9K8/aW3lZ6vvS8uYuGwPYeMUa6rtXNLS5rvTXfh9rCMZZycqr9NVnKsRRvyzzWGjGPtRIt+8g8tjxv5rHl+bE1AggggAACCCBQbwIEFertjHI8CCCAQIUEWiSooGMPwgoEFSp0IukWAQQQQAABBBBAAAEEEEAAAQTahIBeWHjOn37V6se6xeZby/HjxnsXcrcTvcDuxVeeiRlTOznq8BNSvwhbP2O67c7r5O1/vhm5X70A+JQTfix9eveNrE9a+Oa8WTJl2h3yzTdfm02222ZH+c5hxyXdPLLdu/9+W/5x3x2yaPGXkfVuoQYVvu3tb+3uPdziVllXg8eeesCca/czvvjBtJNdd97dXIjduXOX+GY5NTO88MZTzz0iXy76PKem8NOB/QfJmFGHlHih8Ro5+7xfRnZ8xim/KPv1E9XxlRPPl4WffZJVpXfROH7cqbL5Zv2yytN8ohdEnnfxWXldarjkh6e2/r8peQOrowL9u37JVb+PPKKdtt9NDh17VGRduYX6d/baGy+TBQuzX2/a70YbbCqnfO8nMbto+b8X5170v+G/szGDKrn4wP0Ol92GDM/bLm5f3z/+x7LxRpvltW/pghtuuUre++DdvN2OHXO4929q/vHkNUxQ0NrvQ23hGBOchrBJtb8mw4GmsMI81kdkHpvCi6nELpjHlggW05x5bAwMxQgggAACCCCAQBsVIKjQRk88h40AAgiUKpB2UKHU/afdXu/o8PrkOTJ32ryCXTc1NUljY2PBNlQigAACCCCAAAIIIIAAAggggAAC1SZQDRd4reX9ovMPTv6ZdPPupqDL6tWr5ZZJ15pf2Y/y6tixk+gFoOuvt0FUdbPKHnlimjw7/fHIbTU8cfS3TzK/sh/ZIEGhXkD22FP3yzPPP5bXWi+G3323vfPKkxQ8/+KT8vDj00TPY9JFf/H+6O+cZC4sTrpN2u3mvT1b7nv4bu/OBsXDFbn77u6FLA4ac4ToL7gnWSZPuVHmzJ2VpGleG70rxR7euRm194F5ddEFLX9BdtQFXjq2Ll0a5eTjfuSFI9aPHmqZpQQVygQsY/NCQQXtNu6C+jJ26W26Rm6/6wbRv7tRC0EFP3zm2rSVoEI1vA9VOqhQDcfovraKrRNUKCaUbj3zWOaxpbyimMdmazGPzfbgGQIIIIAAAggg0NYFCCq09VcAx48AAggkFGhuUMH+app+8ZvGogEDXdrZWy8EnZayH9vH65Nne0GFt4Ieoh8IKkS7UIoAAggggAACCCCAAAIIIIAAAtUt0PpBhXby3SNPlq232iYLavnyZeaXuz/7fEFWuX3So8c6Mv57/yV6cVi5y+tzZsjf/3FLbDf7jjxIhg/bJ7a+WIUey11e/++8Ozeyabt27eWEo8eX/Ov3GqzQgEVzFg17jD/xv6T3upW5iL3QmKa/9LQ8+Og9hZokqhu991gZsfuoom3LCSrYzpP/8nj1BBV07Pr35NQTfiJdvXBK2gtBhbRFk/dXLKjQvn17Of7o02TzTbdK3mmRlk8+85A84f0XtxBUaJtBhWp5H6pkUKFajjHu715UOUGFKJVKlTGPZR7bvNcW81jfLS6ooLXMY5v32mIrBBBAAAEEEECglgUIKtTy2WPsCCCAQAsKlBtU0FxBbrigOcO3IYPcvpoXVOCOCs05B2yDAAIIIIAAAggggAACCCCAAALVL9DaQYVhu+4l+48+NBJKQwrX3niZ6IX+Uctmm2wpJxxzmrRv3xBVnajsP/M/kOtvvkpWrlwR2X777YbI4YccE1mXpFAv5r7xtgmi+ym0bLXFADlu3KmFmmTV/eu9d+Sm268p6U4KWR14T/SX9k/1wh4aWmip5aOP35frbrrSu2vGqhR22U6+fdixMmibHQv2lUZQoUOHjnLaSWd6wY71Cu5Lf3X+7PN+GdnmjFN+4Zn3jawrp7DQBV7a74Z9N5ETjz3DO88dy9lN3rYEFfJIWqygWFBBB7JWY1cvjPRTc5FfuQPTuyjo3RT09R23EFRoe0GFanofqlRQoZqOMe7vXlQ5QYUolcqUMY/1XZnHNuf1xTxW1ZjHNue1wzYIIIAAAggggED9ChBUqN9zy5EhgAACqQo0O6jgfMmRGy4oNkANJZS6TaE+c0MOs8wdFeYV2kS4o0JBHioRQAABBBBAAAEEEEAAAQQQQKBKBTSocOHl51RkdKu8i9HjQga6ww36bizfP/7H0tAQHzT457/eklsmXRt7Qf6QHYfJwQd8p1njX/rVEpl4wyWyeMmiyO032nBTOfG7Z0iHDh0i64sVavjh5jsmynsfvFuwaf9+28q3DjpaGhvXKtjOVi5b1iRXTPyz93nUUluU96hj1l/RX7x4UaydbrTzDkPlkAOPzNu+EgX6Wphw/cXy5aLPC3avvwbf6F1krcdnf3QkbgM1+8lp/yNdujTGNZGooEK3bmvLur36mIu5Fy3+QjQUoxfeF1r09XrKCT8uEoypvqCCHtOArbeTcUecKGndzVb7bImgwrv/flt3lbWs36dvRe4QkbWTKn+SJKigh9B3/Q3l5ON+XFZIZcHCT0xg7Jtv8i/Ed5lqKajQ0FD6v+n679KxR50iGpDLXar9ovBKXMRfbe9DbeEYc193hZ5X+2uy0NhLrWMeyzyWeSzz2FL/3dD2zGObo8Y2CCCAAAIIIIBA5QUIKlTemD0ggAACdSHQ0kEFGypQvDTCClH9EVSoi5cmB4EAAggggAACCCCAAAIIIIAAAi0s8NiT98vTzz8auddOnTqbX6jvtU7vyHq38IWXn5EHHpniFmWtjx1zuOy68/CssmJPVq1aJTfcepV8+NF7kU27d+8h4727DegF7c1Z9I4Bt915vbzz7tzYzTWgse/Ig0R/jbeU5ZEnpsmz0x+P3ETHvd8+B5u7DOhF6XpxsZ6DZ6c/ERlY0Db6S/+9110/sr80C6c9+Hd5ecZzsV3qxfQjR+xv7vSgNitWrJCPP/lQHn58aux50s6GD9vHOMZ1PHnKTTJn7mvmbggabNl+0BATUHDbayDitddflkeful+WLl3sVmWtf++Y02XzzfpllWU/qc6ggo5xtyEj5MD9vpU93DKetcQFXmef94u8EX77sOOK3kUjb6M6K0gaVNDD3s6748h3PLPmLBoumvi3S+XzLxYW3bxWggoajtt4o82KHk8pDar9ovBKXMRfbe9DbeEY6+k1WcqxtGZb5rHMY93XH/PY1rkzmD0HzGOtBI8IIIAAAggggEB9CxBUqO/zy9EhgAACqQmUG1QoNWxggwWlblfogHP7JKhQSIs6BBBAAAEEEEAAAQQQQAABBBBAIF/gX94vod90xzWxv4h/+MHHmAvG87eMLrn3gcny6swXIiv1l66PGzdetih4AXn2pvfcd4fMnPVSdmHwrEOHjt6vkP/Q3PEhskGRQr3o/c57bjYXx8c17dmzlxz1rRNK3ofeBeKyv/zRXMSf2/faXkjhJG/cPXv0yq2SV197Qe69f3JeuRaUcyFzZIcxhZd64/7yy6i7KbTzLqQ+1owjalP11LDF4089EFUtetxn/vD/Iuu0UC+yXuLdNWOzTbeKbWMrNNihAZaP539ki7IeD9j3MBm6y55ZZdlPqjeooOPcf/RhXjCm0Pizj6bQM4IKhXQqW1dKUEFHMnrkWBkxbFRJg9K/d7dO/mvBsJXbIUGF/DtOVCIU4ZonXU/7Iv5qfB9qC8eY9Hxru2oPz5RyLK3Vlnks89jc1x7z2NYNKuj5YB6b+6rkOQIIIIAAAgggUH8CBBXq75xyRAgggEBFBEoNKugXHt6tEGLvhmDqvZHm3pY86Xbat11ywwzaR26/tq0+2sDC65PnyNxp89yqvPWmpibvlvTxt5jP24ACBBBAAAEEEEAAAQQQQAABBBBAoE4FmpqWytXXXRT7y/Q7DNpFvnXw0SUdvd6h4MbbJsh7H7wbuV1j41pyqncHhHV6rhtZ7xa+8PLT3h0a7nGLstb118f14v3mLs+/+KQ89Ni9sZuv26uPfO+7P5Duzbhbg95d4LkXnojs++TjfiSbbLx5ZJ0W/v3eW+X12a9G1LeTH43/lei4KrUUurB69932ljGjDim669vuvE7eemdOZLvTT/6ZrL/ehpF1pRZqsOGaGy4RvRA/d9lph93k0AOPyi12nld3UEE/Cz3q8O/JwP6DnDE3b5WgQvPc0tiq0N+nqP71vH/3yO9Lvy0HRlVHlj365H3yzPOPRdZFFRJUaDtBhWp8H0o7qFCNxxj19y6ujKBCnEyycuaxzGNzXymF3neZx+Zqlfb8yonny8LPPkm0EfPYREw0QgABBBBAAAEEalqAoEJNnz4GjwACCLScQClBBRtC0NFFBQbi6uPK3aN029iwghtUcOuj9q19ZYIKs72gwltu93nrBBXySChAAAEEEEAAAQQQQAABBBBAAIE2KbBGbpkU/yvcvdbpLaeddKZ06tS5ZJ2mZV/JxL9dGvOr/CJ9eveVU074ccG+3/Xu9HDzHRO9Oz2sjtz/XnvsK/vsdUBkXZLCBQs/8S5yv1hWrlwZ2bz3uuvJ9445Xbo1I6Sgn1ZdfNUfZPHiL/P6HrztTnLEocfmlbsFepHV5RPOk1Wr8sc2csQY2dv7r1LLrDdekbun3pbXfceOHeW/f/o7aWjokFeXW7Bo0RdyydV/yC02z486/ATZZsD2kXXNKbzvob/LS68+l7fphhtsYgIxeRVhQXUHFXSYeseQE4/9geiF5eUsBBXK0Stv20IXTMb13LlzF/PaTRJImj33Nblzyk1xXUWWE1RoK0GF6nwfSjeoUJ3HGPkXL6aQoEIMTKJi5rHMY/NfKMxjRc44pfXvqKBnhnls/uuTEgQQQAABBBBAoJ4ECCrU09nkWBBAAIEKCjQnqBAbFNC7LQRLbhsNGuSW2bbm0dvUBA2K3FFB2xbqR/t4fTJBhSxbniCAAAIIIIAAAggggAACCCCAAAIxAoXuJtDQ0CDfP/7HskHfjWO2Ll786YL58tebLpdvvsm/KFS3HrD1djLuiBMjP+/54svPZOINl8qy5U2RO9JfmR93xPe8OucDpciW0YV614drb7xMPp7/UWSDPr3XNyGFrl27R9YXK/zoP++b/qPaneCFH7bYrF9UVVbZLZOulXfenZtVpk/W67OB/OD7P88rT6sg7tepN9pwUy9c8pPEu7ng8rPlq6+W5LUfO+Zw2XXn4XnlzS2Y8dqL8o/7J+Vt3qVLowlW5FWEBdUTVNAQyIoVK8KRuStd1+pm3Hv27OUWl7ROUKEkrlQbFwoq9OixjmioJ2rRoJT+fdPQQtzyyacfm39jV6z4JrJJY5e1Iv8NJaiQ/56k73cbb7RZpGNLFqZ5EX+1vg+1hWMs5TVDUKEUrey2zGOZx2a/IvxnzGNbPqjAPDbqlUgZAggggAACCCBQ/wIEFer/HHOECCCAQCoCiYIKRw6SAWO3jvzCWAdh73Zg7oDQvO+FSzqWcH/eLbCjllkmqDAvqios444KIQUrCCCAAAIIIIAAAggggAACCCDQRgX+M/8Due6mK7xf7F8VKbD/6ENl2K57RdaVUvjWO3Pk9ruuDz9Dyt12xO6jZPTeY7OKNdigIQK940HUsv56G5gQRceOnaKqE5U9/vSD8tSzD0e21Qvcf3Dyz2XttXtG1icpjLtISvv+5U/Olvbt2xft5sVXnpH7H54S2e7Hp/1a9I4XlViemf6YPPrEfXld99tyoBx71Cl55XEF51/2W2lqWppXfcC+35Khu4zIK29uwRtzZshd/7glb3M9f2eecVZeeaageoIKx3znZO/vyQ2xdw/Ri9b1Qmp9/TRnIajQHLV0tikUVNA71tx424TIMIHuvX+/beWY75zkreV/Fr5sWZNc87dLYu9as/VW20i/LQdE/htCUKFtBBWq9X0ozaBCtR5jKf96EFQoRSvTlnks89jMqyF7jXlsywcVmMdmvwZ5hgACCCCAAAIItBUBggpt5UxznAgggECZAqkGFWKCA2UOMW9zG1TQiqi7KxBUyCOjAAEEEEAAAQQQQAABBBBAAAEEEMgS0CDAhOsvls+/WJhVbp/oBa7fPfJk72n+xbG2TSmPz05/XB55YlrsJt8+7DgZtM2Opl4/+7nj7zfIvLdnR7Zfy/t1+fHf+y/RXyJv7rJ48Zdy6V/OFb2rQtTy7UOPlUHb7hRVlbjsupuvkA8+/Hdeez1OPd4ki56fyyecF9n0sLHjZMftd42sK7fwuReeEL34M3dZu3sPOfOH/5dbHPlcbfXiy5UrV+bV68VMegF2WstjT94vTz//aF53+uvoenF//FI9QYXf/PoCeenVZ+W+h+6OHe5mm2wpxx99mujdTkpdCCqUKpZe+0JBhV+f+Xv56OP35eY7ro0Nqey1x76yz14HZA1ozZrV3jYT5d1/v51Vbp9oiGn8iT+VWbNfiXxNEVRoG0GFan0fSjOoUK3HaP8uJnkkqJBEKbsN81jmsdmviOxnzGNbPqjAPDb7NcgzBBBAAAEEEECgrQgQVGgrZ5rjRAABBMoUSBpUGHhQ/4J70i+QuaNCQSIqEUAAAQQQQAABBBBAAAEEEEAAgaoR+Pu9t8rrs1+NHE+3bmt7dxP4mWggIM3l7qm3yaw3XonsskOHjnLycT+UDfpuLI899YA8/dwjke30Au0TjjldNt14i8j6pIUPPHKPvPDy05HNB3sBhSO8oEK5y3kXnyV6cXjuUmoIQoMKUYGS3XfbW8aMOiS3+1Sev/HmTLnrnpsj+zrx2DNEL5gvtrw5b5ZMuvvGyGY/PPVXoncISGPRQMQ1N1wqn3z6n7zuNGyi3vFLdQUVdJwPPXavPP/ik7FDHrzdznLEId+NrY+rIKgQJ1P58mJBhc6du0jcRZV2dEcdfoJsM2B7+7Tg66RTp85yygk/lj69+8aGXwgqtI2gQrW+D6UZVKjWYwz/siZYIaiQACmnCfNY5rE5L4msp8xjWyeooCeBeWzWS5EnCCCAAAIIIIBA3QsQVKj7U8wBIoAAAukIJAoqHDVIBo4tHFTQ0bh3OnBH5971wLZxy+K2jWuTW+7uS9e5o0KuCM8RQAABBBBAAAEEEEAAAQQQQACBjMDM11+Se6bdkSlw1vRzl+PHjZctNt/aKU1nddWqlXLDLVfLh/95L7JD/bX+PYaOFA0RxC2HHniU7LTDbnHVicqbln0ll1z1e1mxYkVeex3DGaf8UvTC4XIWvWPDxd4+opZf/OS30rWEEMi0B++Sl2c8n9fVlpv3935df3xeeRoFS5culouu/H3kL7z3WLunnH7yz6VLl8bYXS39aolcfe0Fota5S2PjWvKLH/9G2rcv/a4AuX3p8/sfvltefOXZqCo56vDveRd3D46s8wurL6ign59OnnKTaNAjbtnT+4X9UTm/sB/X1pYTVLASLf+YJKigo7rrH7fIG3NmRA6wY8dOJnywXp8NzF0S7r73tsh2Wnjkt06QbQf6oYa4u3QQVKj/oEI1vw+lFVSo5mOM/QsaUUFQIQKlQBHzWOaxBV4epop5bOsFFZjHFnt1Uo8AAggggAACCNSXAEGF+jqfHA0CCCBQMYHWCiroAbmBAxtgcA80rt4td9vbdYIKVoJHBBBAAAEEEEAAAQQQQAABBBBAIFvgs88XyITrL/Yu0v8muyJ4NmL3UTJ677GRdWkU6gXsE/92qejFhaUuQ3fZUw7Y97BSN8tr//jTD8pTzz6cV64FB+z7LRm6y4jIulIK33l3rtwy6dq8Tdq1ay//77//5JW3y6uLK3jKu7vE495dJnKX7t6dL372o/+XW5zacx2/HkfUone++NZB40Qvms5dPp7/kUyZdrt8uuDj3CrzfL99DjaBlMjKEgr1LhNPP/eo6AWLUUu3rt3lzB/+nxeIaB9VHZRVX1BBB7Zy5Qr5261/iQ31aJtDx3qhne2Th3YIKqha6yxJgwoanrru5stl/if5dwfRkffs2UsO3v87cvtd15vXSNTRDB+2j+w78qCwiqBCSBGuVPtF4WldxF/N70Nt4RjDF1yClWp/TSY4hBZrwjxWhHlsspcb89hfmDsrJdNK3urKiefLws8+ydvgN7++ICxjHhtSsIIAAggggAACCNS9AEGFuj/FHCACCCCQjkClgwrt9EvXnO9dbSjBDRzYMveo3G1tvbuN29ZdJ6jgarCOAAIIIIAAAggggAACCCCAAAII+AJ6R4Nrb7ws9iLYjTfaTE469odFLuwuX3P+Jx95F+NeEXlHg7jet9qivxx71CneD18Uuug8butMuRpccPnZsnz5skxhsKZ3CDjzjLOkU6fOpmTVqlWiwYqOHTrIWmt19cpyPuTK6yFTMOuNV+Tuqfm/eK53UtA7KpSyvDzjOZn24N/zNmloaJCzfqmhh8osH/3nfXOeVq9eHbkDvSPCzjsMlU28143eZUEvxn7/w3/JjFkvStw23b07VvzktP+RDp5pqcub816XxUu+NPtZ+NmnJkRhPzPM7Us/Qzz62ydJ/37b5lblPK/OoIIOsqlpqff39XL54svPcsbsP9UAhv6d0DtrJFmaG1RYtqxJdNsky6V/+WNeswP3+5b036rYefA307ttlHs3k7wBVEFB0qCCDvXLRZ/LxBsujbwbSbFD8f+dPDXrB4JqPaiwQd+NvNdE/N1bCpkMHTJCBvYflNek2i8KT+si/mp+H2oLx5j3witQUO2vyQJDb9Eq5rEizGOTv+SYx7ZeUEHPEvPY5K9VWiKAAAIIIIAAArUsQFChls8eY0cAAQRaUKCUoELcF392uFkhgjW21HuM+Q7X7S9r22DTYvXazG0TbCav3zlH5k6bZ59GPjY1NUljY/O+4IjskEIEEEAAAQQQQAABBBBAAAEEEECgygXuf3iKvPjKM5Gj1Iv0TzvpTOnZo1dkfdqFc+bOkslTbvK6dT9Eit7Lur36yCkn/ER0jOUu7/77bbnp9gmR3QzZcXfpu/4GomP7zPu1/iVLFoWfPelF4ToOvfB9h0FDiv5C6UuvPif3PZQfLujTe30545RfRu4/rnD2mzPlzntujqw+65fnSUND6Rf9R3YWUah3ntBf7vl93ssAAEAASURBVE1j0c//vn3YcbLdwB1K7m7NmtVyzp9+lXi75HdtqN6ggh6s/nL0X72wwrLlTZHHrhf1n3zcDyPvbJG7QXOCCrrfS6/+Y+KgQu4+S30+euRYGTFsVKmbVX37UoIKejD/eu8d79+pa7x/f6JDQlEHrHdbGH/iT6Wxy1pZ1bUeVMg6mBKfHLjf4bLbkOF5W1X7ReFpXcRfze9DbeEY8154BQqq/TVZYOgtWsU8VoR5bGkvOeaxfUsDS9A6yR0VbDfMY60EjwgggAACCCCAQP0KEFSo33PLkSGAAAKpCtRnUGG2F1R4q6ATQYWCPFQigAACCCCAAAIIIIAAAggggECdCcx7e7bcftf1sUd15LeOl22bcQF5bIcJKp70LoJ/oshF8BpO0JCChgTSWB567F55/sUny+pKL7jfcfCuohfD6y/ARy3PTH9MHn3ivryqzTbZUk489oy88kIFhS5K++V/nS1rNerdHiqz6I+E/OP+STJz1ktl7UDvvnDEod9tVkjh/2/vTuDlqAp8AZ8AES5r2HdBJYQlrLKLuwIBQWQTQXABFPWhzriN88ZBx9/M6IyO4/ZUZFFAQEhUwICACIgIgsgaiJFVQPYdLsiSvDp9b91b3V3Vt7tvd6eXr/yRrj7n1Klzvurklkn9+8QTx3H821cnDnjEB/f33evg3G9Rz59AdwcV4pj/es+d4eQkXBO/RTlvWzFZzSL+Hllh+RXzqsfKmgkqPPnk4+F/v/fvY320e0dQYVz4qmsuDxdcfPZ4QY29qVOnhiMOOyasucY6Va0EFQY3qNDNP4daFVTo5jlW/WasUSCoUANntMp97AiE+9iJPyvZFu5jF29QIV4L97HZT6R9AgQIECBAgED/CQgq9N81NSMCBAi0RaCuoMKBM8OMPacnCyMULI0wOrJFOd+Al3dMbrvkH3izW+VKCROtuJAeG8934+ybBRVSEK8ECBAgQIAAAQIECBAgQIDAwAs8lawM8P0Tvx6eey7/W9m33XrHsPceBy4Gp0Xhq//7r+H5558rPHf8dvX48HKrtu+d8LXw0MMPtKS7VVZeLRxy4BG5IYrfXHZ+uPzKi6vOs8nGM8O793t/VXmtggcevC/84KRv5Db5+NGfDytPWzW3rnWFi8JpZ50Y/nL7rU13efD+Hwgzpm/e9PH1BhWWWmqpsNdu+4ett9wuOVf53zfmn7z7gwpx3Dffcl2Yc85pyV7+CiRrrblu+EASgHnFK5bOn2ZSKqhQSNP2ikZXVEgH9PNzTw83zrs2fVv4ut8+h4YtNtsmt15QYXCDCt38c6hVQYVunmPub8iCQkGFApjRYvex4z7uY8ct6t9zH1u/1cQtG1lRIe3NfWwq4ZUAAQIECBAg0H8Cggr9d03NiAABAm0RaDqokPPvfJXhgnTA2bBCXkghtssGEfL6mai+1MfoPz7eODuuqPDn9PS5r1ZUyGVRSIAAAQIECBAgQIAAAQIECPSZwKJFC8OPT/t+uPueO3Jntvpqa4UPvf8TYamlpubWt7Ow6JuQs+eMKxYc9b5PtORh/Pig2ze+++Vs95PeX265FcLHjvpMGFqmfGWFX186N1xx1SVV/W+erFpxQLJ6RSPbI48+GOJDQXnbMR/+pxADE+3c5i+4Ofxi7hmlB92bPc9aa64TDnjnYbmhjnr6rDeokPY1c9Otw77vODgsueRSaVHBa28EFeLgf3dlskrHZdWrdKQTm/6aTcN7DvhA8vesS6RFZa+CCmUcHX3TbFDhpZdeDCee+p1w/wP3FY53p+3fEHZ/6z6F9YIKgxtU6OafQ60KKnTzHAt/U+ZUCCrkoIwWuY8dt3EfO27RyJ772Ea0Jm7bTFAh9uo+dmJbLQgQIECAAAECvSggqNCLV82YCRAgsBgEui6okHwpWF6YQVBhMXw4nJIAAQIECBAgQIAAAQIECBDoeYHLfndhuDT5L2+L3z4fQwBrrL52XnVby/78l3nhjDk/Ss6R/w3x2ZPHMMWRhx9T89vis+2L9m/9843hzJ+fXFTddPmWM18b3vWO95Qdf9kVF4VLL7+grCy+efWGG4fDDv5QVXmtgnvvuzuccMq3c5t86phjw/JJWKJd2yW//VX47e9/3ZLu47f9v++Qo8M6a63fcH+NBhXiCXbdOVmN440TrcbRO0GFOKdzzz8r/OmGP8Td3G27bXYOe+2+f26doEIuS0cKmw0qxMHFY4/70f+G4eFnqsa64QYbhcPe/aGwxBL54ZR4QK8HFeKKMVOnNheke/3Obw0zc1aa6PaHwlv1EH83/xwahDlW/YatUdDtn8kaQ297lfvYcWL3seMW9e65j12rXqq62zUbVIgncB9bN7OGBAgQIECAAIGeERBU6JlLZaAECBBYvAJ1BRUOmhk2mbXxWIAgu0JCOvoYLiiVx5UW8v59ebS8MoSQ9pUtT8vSvuNCCdlVFvLqx9omOzeeZUWFrId9AgQIECBAgAABAgQIECBAYDAF4ioKcTWF+G20edteu+8Xtttml7yqtpY9+ND9pW8Jf+GFv9d9no032iwcvP8HylblrPvg0YZXX3tFOP+in094WHwodrVV1wzLLbt8eOLJx8Jjjz8aFi58ueZxhx50ZNjo1ZuMtbnqmt+GCy4+Z+x9urP2WusmK1j8Q/q2rtcFt90STp99Ym7bf/7Ufzb9EG9uh5nCdjwQt+KK05L5f7JkmzlVHbuLksDNReHRxx4Ojzz6UOm/+G3ztbapU18RPnH050Nc9aJ4662gwsKFC8NpZx0fbr9zQeGU3v7md4RddnxTVX0zQYX4uX/s8Ueq+ioqyFv5Y7e37B2mv2b890bRsbF8uWVXCHEVlX7bJhNUiBZ3/fX2cMoZP0j+HBr/s3yl0d9LyyZ/TtXaej2ocMRhx4T11t2g1hQbruv2h8Jb9RB/N/8cGoQ5NvLB7PbPZCNzaWVb97Hlmu5jyz0meuc+9tMhhr1bvU0mqOA+ttVXQ38ECBAgQIAAgcUvIKiw+K+BERAgQKAnBOoOKuyZBBUWjScQsmGBNGSQXfWgLKwQQwqj20R9xGbZvmNIIW5Fx6X1I61GfhVUyGrYJ0CAAAECBAgQIECAAAECBAZR4LnnhsP3T/x6eOrpJ3Onv+mMLcJB73pfbl07C59NvhX8hz/+ZnjyyccbPs2uOyXfkP+mib4hv7jbib5VNQYN3rDL28L668WHYsf/Quull14Kv7/60nD57y8ORQ/Hx4eGP3bU58ZCA/Fb7+O3hlZuK620cvjkR/5vZXHN99ffdE04e+5Pq9pMmbJE+NfP/VdVeSsKnn7mqfC9478Wnnt+OLe7JZdcMuy0/RvCjI02T0Ida4Sll166FOh46OH7w++u+k24/4H7co+LhTOmb14KnRQ2qKPi5ZdfCvEBxgt/c26IwZeibYfX7hpmvX3fouqkvLeCCnEiMXBw0k++W2PeU8KB+743bLbJVmXzbiaoUNZBHW++9JVPV7Xa/53vDTM33bqqfJAKJhtUiFZXX/u7JGj1ixJbXA3ng+/9P2HttdabkFFQoZqo2x8Kb9VD/N38c2gQ5lj9ySsu6fbPZPHI21fjPrba1n1stUlRifvYED56ZPcFFeL1ch9b9KlVToAAAQIECBDoTQFBhd68bkZNgACBjgvUHVTIrKgQB5kNE0wYVBg5oDS3osBB2kdl3+m/CRcdV+p0/N+NS28FFUoMfiFAgAABAgQIECBAgAABAgQGWOCMOSeFP/9lXq5AfKj+6A9+KiyzzFBufbsK48PlcYWHe+67K/cUSy+9TNg8ebg6PlxZtO23z6Fhi822KaquWR6DA3l9L7/8imHvPQ4IcdWGWtvjTzyarATx3fBM8hB/3vb+Qz8aNlj/1aWqebdeH2affWpVs1e8Yunw+X/896ryWgW//8Ol4aJLflnVJF6/z33yy2Pl8e/PvvHdL4cYBml0e8sbZoXX7fTmscOKrGKD9dbZILxr7/eEVVZebax9dieO47obrg5zL5xT9g3w422mlFY6mDZtlfGiJvdicOSc5LreNO9PuT3E1TH++VP/kdRV/AXiWOveCyrEoccA0vEnfys8XRBEig+yH/6eo8P66244NlNBhTGKju+0IqgQB/3rS+eWQkBbb7l93X8OCipUX+5GHwpv5Z+t1aOpLmnVQ/yL4+dQ9WzyS3p5ju34PDT6mcxX7a9S97HV17Po3sx9bAjuY6s/L90aVIgjdR9bfb2UECBAgAABAgR6VUBQoVevnHETIECgwwJ1BRUOnBlm7Dk9N5wQh1sKLST/1hf/graRLT0urr6QDSrk9TG2WkMdbW+aPS/Mn1u8/Hnsf3h4OFlGvLP/GJ83L2UECBAgQIAAAQIECBAgQIAAgVYLZL95u7Lv+C387z/0I+GV672qsqrt738x94xww01/zD1PHNehBx0RXvOqGaFWu/gA9gcO/VhYZ+31c/upVXj67BPDgttuqWqy3Ta7hL1236+qPK/gtjvmh5+ceXxeVfLN/e8KO7z2daW6v91/T2nliLyG//KZr4a4IkG9W3w4+YqrLqlqvu46rwxHHv7xsfJFixaGf/vqZ8feN7ITV6qIK1bEbeHCl8PXvvWl3NUUlh1aLnzkiE+F+FDcRFsccxx73jbZ1TGyfcbxfveH/52s6PBItnhs/5Mf/ZcQwzn5W28GFeJcHnjwb6WVFV544e+5U4vX6ojDjxkLlAgq5DJ1pLBVQYVmBiuoUK3W6EPhrfqztXok+SWteoh/cfwcyp9RdWkvz7Edn4dGP5PVov1V4j42/3q6j813iaXuY6ttujmoEEfrPrb6mikhQIAAAQIECPSigKBCL141YyZAgMBiEGhJUGHKyDeSNRxUGD0uTnuiY8eCCnW0FVRYDB8kpyRAgAABAgQIECBAgAABAgS6QiA+9BG/aT2uXpC3vfn1u4c3vO7teVVtLav10Ho88R5ve2fYcbvXl8YQx/6jn3wv3Pu3u3PHtELykPxR7/9kiK+NbKf+9Lhw+53VX24RPaJLvVvRt/xuu/WOycoMB5a6iQ+P/+f//EuyX/3FHh9Kxr72WuvVe7pw2lknhL/cfmtV+2222iHsM+ugsfJWPTx5z713JStHfGes3+zOAe98b9h8062zRTX2F4UTTv5O7nXc4JWvCe8/5CM1jm2s6tY/3xjO/PnJuQcddvCHw6s3nJ5bF6/Pl77ymdy6bn/AKw46BmdOO+vE5O9WF+bOIa56EcMsQ0PLBkGFXKKOFAoqTMzcyQe1Gz1Xq/5snVhhpEWrHuJfHD+HBmGO7fg8NPqZrNe5F9u5jy2+au5ji22yQQX3sSNO7mOLPy9FNV/6yqerqvZP/r/PzLr/v0/V4QoIECBAgAABAn0vIKjQ95fYBAkQINAagWaCCpWrH6QhgonCBpUjbmpFhaSTic4jqFAp7T0BAgQIECBAgAABAgQIECAwCAIvvvhC+MFJ3wiPPvZw7nQ3TB4OP/w9R4f073JyG7WhMK5iEB/uL/o7newD/unpn3nmqXDcj78Znn76ybSo7HXdtV+ZrAzx0RBXWKh3m/2LU8K8+TdUNW80vHH5lReH31x2flU/lSscfPN7/xGeePKxqnZv2nW38Mbkv3q2F198MfzXN78QXnqpOniy+1vfGXbafiTcEftq1cOT8269Psw++9Tc4X3uk18OyyxT/yqll1x+QfjtFRdV9TVt2irhE0f/c1V5swXPP/9c+Or/fiH38D132y9sv+0uuXW9HlSIk7r2+ivDL381p2B+Iay/3obh8IOPLoWXvvKNGJ4p31ZbdY3wsaOaW4mjvKeQhD484FVpEt8LKuSplJd18kHtRs/Vqj9by2dc/K5VQYV4hk7/HCqeVXlNL8+xHZ+HRj+T5Zr98859bO1r6T622CcbVHAfO+LUC0GFOFL3scWfazUECBAgQKAegeuuuy7svnv1l6985jOfCfE/G4F2CwgqtFtY/wQIEOgTgXqDCpvsuXHy/WLV3wAXGUqBg+S1sj4tL6LKtk/bZstKfees1lDUNj2PoEIq4ZUAAQIECBAgQIAAAQIECBAYJIGz5/40XH/TNblTjt+o/pEPfiqssMJKufXtKnzo4QfCCad8O8Rvds7b4jfrH37wh8ISSyxZVf23B+4JJ536/5KH9F+sqosFW2y+bdhv70Ny6/IK514wJ/zxuiurqrbaYruw714HV5UXFcSwQ3xYrHKLKzz84//517HiopUX1ll7/XDU+z4x1q7Wzp//Mq8U8shrE4MaG6z/6rGqVj08edU1l4cLLj57rN90Z/nlVgifOubY9G1dr/MX3Bx++rMfVbWN1/sLn/1KUj6yUmtVgyYKih70jKGQGA7J33p7RYV0Tr++dG6Iq5YUbZtvslV4xx4H5IY5BBWK1FpXLqgwsWXR798jDjsmrLfuBhN30ECLRs/Vqj9b6x1iKx/i7/TPoUGYYzs+D41+Jut17rV27mNrXzH3scU+2aCC+9gRp14JKsTRuo8t/myrIUCAAAECEwlcffXVYccdd6xq9sUvfjEce2xjf4dX1YkCAnUICCrUgaQJAQIECITQrqBCGiaoZZwNJWTbp+XZb/fLfuNeXtvseQQVshr2CRAgQIAAAQIECBAgQIAAgUEQuGnen8LPzj2tcKrvOeCDYeONNiusb0fF8PAz4Yc//lbuqgLxfCtPW7X0wH4MURRtN99yXZhzzk+KqsPb3rRXeN1Oby6sz1Zclnyz/6XJN/xXbpUrIVTWV76/+torwvkX/byyOKy+2prho0eOf1tZDEXEh8qqtynh08f8a1guefB/ou2c888M191wdVWzaPaZj38xWR1jibG6Vj08+Yc//i786te/GOs33YmrV3z+H/8jCZWMnzOtK3otCnXE9sf+038nv7YmqPD3vz8f8lYLiOfZ423vDDtuN77yRCwb3/ojqBC/Qmb2L07NXTEknet22+ycG9QRVEiF2vcqqDCxbScf1G70XK36s3VihZEWrQwqdPrn0CDMsR2fh0Y/k/U691I797ETXy33scVG2aCC+9gRp14KKriPLf5sqyFAgAABAhMJCCpMJKS+3QKCCu0W1j8BAgT6RKBdQYXIkw0U5HGlgYRs22xZqTyuqLCofLWGbL+V7eMxggpRwUaAAAECBAgQIECAAAECBAgMisBjjz8SfnDSNwpXLdjhtbuGWW/ft6McL7/8cjj59O+Hv957Z+55l156mRC/KTs+3D/RdvFl54XfXfmb3Gbxiy4O3v8DdYUw7rhrQTjljOOq+llyyaXCMR/6XFhppZWr6vIKzv3VWeFP1/+hqupVG2wUDn/P0WPlzzzzVPj6d76cvE/+cqti23vWgWHbraq/8SzbbOHCheEb3/1yeObZp7PFpf1tttwh7LPnQVXl8YH9ZrYYQogOcasVLjg6WZVjzTXWrvsUF/7m3HDl1ZdVtY8hjU83uDpDVSeZgrvvuSPEh3vztgP2PSzEFQXyt34JKoRk5ZGXwslnfD/cc+9d+VMtKBVUKIBpYbGgwsSYnXxQu5lzteLP1okVRlq0MqiwOH4O1TPPXp9jqz8PzXwm63HulTbuY93Hpp/VVvzech87otlbQQX3senvAa8ECBAgQKBRAUGFRsW0b7WAoEKrRfVHgACBPhVoNqgwUVigHq5m+yg8bvTffG+aMy/Mn7ug5hCGh4fD0NBQzTYqCRAgQIAAAQIECBAgQIAAAQLdLhADASee8p3wtwfuyR3qWmuuE448/ONjD6HnNmpD4dnn/TRcf+M1uT3HcEFc4WH6azbNra8sjCttnjHnpLDgtlsqq0rvX/GKpUtznCj08MILf0++df8LIX4bcuW26YwtwkHvel9lcdX7J598PHz3+P8OL774QlXdjtvtmnx7f3kg5IRTvh3uve/uqrbTpq0SPnbkZ0MMCBRtV11zebjg4rNzqw858Ii6/XI7qFF43/1/DccnK2HkbfGaHXLgB5OqiVdCeO754VKAJppVbltstk3Yb59DK4vDXX+9Pay04rTSahtVlYUFi5KQwvdCDCvkbbXDFf0TVIhzf+654XD8yd8K8aHPejdBhXqlmm8nqDCxXScf1O7kuSaeeXWLVj7EH3vvxp9DgzDH6itbXNLtn8nikU++xn1sCO5jJ/85yvbgPnZEo9eCCnHU7mOzn2T7BAgQIECgPgFBhfqctGqfgKBC+2z1TIAAgb4S6MugwuwkqHCeoEJffVBNhgABAgQIECBAgAABAgQIEMgVKPrG+th46tRXhA9/4B/CqqusnntsuwrjN+jHcRVtu71l77DzDm8sqs4tjyGD+AD2w488mFu/8rRVw1Hv/0QYWmbZ3Pq08CdnHh9uu2N++rbstfY378emi8JPzjyh8PjDDv5wePWG08v6vHHeteHn555eVpa+iQbRIm979LGHww9//M2Q982yq626ZogPH8XARzu2GAz5+re/FJ4dfia3+7e/+R1hlx3flFuXFsY+Tjur2Oqde747bL3l9mnzsdefnfOTcPOtN4TNN90qvH7nt4Q1Vp949YYrrrok/PrSuWN9ZHdWXGGl8A8f+0K2qGK/v4IKcXIxpHDCyd8Ow889WzHX/LetDCr821c/WxUEOjBZ0WKzwhUt8sfUb6WCChNf0U4+qN3Jc0088+oWrX6Ivxt/Dg3CHKuvbHFJt38mi0c++Rr3sSOG7mMn/1lKe3AfOyLRi0GFOHL3sekn2SsBAgQIEKhPQFChPiet2icgqNA+Wz0TIECgrwTqDSrM2LP8H1kjQrqywaKc5evrRWqmj/SYeI6qcyerKlhRoV597QgQIECAAAECBAgQIECAAIFeFvjL7bcmD4OfmExhdJnJiskUPQxe0aylb+OYTp99YvKwcv6Yttlyh7DPngc1dc7Hn3g0/PBH3wzxm/rztldtsFF477s/FJZYYom86lLZHXctCKeccVxB/ZQkQPGG8NY37pmsQLFkWZunnn4ynD33jHDHXX8pK0/frJisAvCJoz+fnLv8uOjw/5IVGB559KG0adnrG3fdLbxhl7eVjfnBh+5PruvxIZ4zb5s4UJF3VGNl513483DNn64oPGjjjTYLu791n7DKyqtVtbnr7tvChZf8Mtz/wL1VdWlBDA/EEEHlFoMKN91y3WjxlLDxRpuG7bbZuRRYWGnF2H48nBFXaph74c9C/MwVbbXCICPH9F9QIc7rnvvuCief/v3w0ksvFdGMlbcyqBBXPakMuGyehBTit0UP8iaoMPHV7+SD2p0818Qzr27R6of4u/Hn0CDMsfrKFpd0+2eyeOSTq3EfW+7nPrbcYzLv3MeGUqh59dXWmgxj7rHf/WH8/zXVwfFj/+lrue2bKXQf24yaYwgQIEBgUAUEFQb1ynfPvAUVuudaGAkBAgS6WmAyQYV0YmlwoDI0UFSeHpd9Tdtmy+rpLz0u2/amuKLCXCsqZC3tEyBAgAABAgQIECBAgAABAv0l8MwzT4Xvnfg/YbjgW+/jbHfcbte2TXr55VcMr9vxzWXf6v/wIw+EE075Tu4qAHEgr1z/VeHwg4+uCgE0Msg7k6DAqWf+MCxcuDD3sO233SXsudt+uXVpYVyp4G/335O+rXqN32obx7rWGuuUzhODAwtuvyU8//xzVW3Tgn33OjhstcV26duy13m3Xh9mn31qWVn2TXxQPH7j/CuSFTDuf/C+cMv8GwqDHmsmYzr6g/+QHD7+wH62r1btP/Ps0+E7x3218FrG88RQxlprrhNWW2WNsOyyy5WCFTGQ8dDD99ccxszNtgn773NobpvyoEJ5k/iwe7SKr/HbVp966onyBhXvYrsYHll22eUrarJvi4MKcTWHVVZeNdu44f111lovvD4JomS3TjzgFc8XP0dn/SJ+7vJDQ+mYWhlUSPv0Wi7QT0GFdv2+6OSD2p08V/knob53rX6IP561234ODcIc67vaI626/TPZyFzqbes+1n1svZ+VZtq5jw2lkK/72GY+PY4hQIAAAQK9JSCo0FvXqx9HK6jQj1fVnAgQINAGgXYFFdIAQRxyNkRQNIVs+7RN9rhs/UTlggqpoFcCBAgQIECAAAECBAgQIECgHwXityOf8tPjQnxof3FuHzvqs6UHx+MYhp97Nhz/42+FuOpB3jZtpVXCUe/7+AQPjecdWV129bVXhPMv+nl1xWjJXrvvX/oW/qIG8WH64370jfDiiy8WNWmoPH4D7mEHf7gstFHZwU9/9qMwf8HNlcUNvZ86dWo48vCPlx48aujAJhv/8borw9wL5jR5dP5hq6+2ZvI5+ESYmoQy8rZaQYW89rXK9njbvnWEdYqDCrX6rrdu+ms2DYcceERZ804FFeJJf/+HS8NFyeoWtTZBhVo6ranrp6BCK0Tyfl908kHtTp6rGa92PMQfx9FNP4cGYY6NXPtu/0w2Mpd62rqPdR9bz+dksm3cx05WMIS8n9fuYyfvqgcCBAgQINBKAUGFVmrqqxkBQYVm1BxDgACBARRoRVChiC2GC7KhgqJ2aXlRGCFbn9dfelxaJ6iQinklQIAAAQIECBAgQIAAAQIE+lHg8isvDr+57PzFPrU0qLBw4cvh5NN/EO6+547cMcVvtj/isGOSB+zXyq1vpvDcX50V/nT9H3IPjd/0f/jBHwobvPI1ufWx8Pqbrglnzz0z2av9bfOFHYxWrLLyaqUH75dZZqhm07///fkQV3J49LGHa7arVfmud7wnbDnztbWatLzu4kvPC7+76jct6Td+DmJIIT4YX7S1KqiwzVY7hH1mHVR0mkx5fwcV4kRj2CQ+rFe0CSoUybSuXFCh3DLvwcdOPqjdyXOVz7y+d+16iL+bfg4Nwhzru9ojrbr9M9nIXOpp6z42BPex9XxSJt/GfezkDPN+XncyqBBH7z52ctfQ0QQIECDQ/wKCCv1/jbt9hoIK3X6FjI8AAQJdIlB3UGHW9LFvhSsFAtJ/w61cZb6ofHS+aaggvo3fmlLaKvsYKR35dYL+sk3Tvm+cfXOYP3dBtqpqf3h4OAwN1f4H5KqDFBAgQIAAAQIECBAgQIAAAQIEFrPAPffdFeIDfgsXLlzMIwkhDSqce34SGrghPzQwZcqUcPD+Hwgbb7RZS8cbwxE/Pv374a/33Jnb77JDy5Ueip82bZXc+lh4w81/DOecd2bTlmuvtW4ytw+GFVdYqfAc2YoYUvjJmccXrjqRbVu+PyW89Y2zwq47v6W8uEPvfvv7X4dLL78w+bu85j9zMdCx96wDw4Y1wiNxOq0IKrx2653DnrvtG2JgZeKt/4MK8bqdPvuk8Jfbb83lEFTIZWlpoaBCOWfeg4+dfFC7k+cqn3l979r1EH88e7f8HBqEOdZ3tUdadftnspG5TNTWfeyIkPvYiT4prat3H9u8Zd7P604HFdzHNn/9HEmAAAECgyEgqDAY17mbZymo0M1Xx9gIECDQRQL9GVSYlwQV/lxTWVChJo9KAgQIECBAgAABAgQIECBAoAsFnn/+ufD9k/4nPPnk410xuhhUuO2OP4cLLj67cDxve9Ne4XU7vbmwfjIVw8PPhOOSVQqKPOIKDnElh/hN/kXbnXffFs678GfhkUcfKmpSVT5lyhJhm622D7Petm9YaqmpVfW1CuI1nH32qeH2O2v/3VXaRxz7fnsfEmZM3zwtWiyvcbWMX/5qdkNOcaBTp04Nr9/5rWGXHd8UllxyqQnHfsddC5IVHC4Jd951W9I2/QaTCQ8rNRgaWja8/U3vSK7NDvUdUGrV/0GFOM0XXvh7OCkJOD3w4H1VNoIKVSQtLxBUKCfNe/Cxkw9qd/Jc5TOv7107H+KPI+iGn0ODMMf6rvZIq27/TDYyl1pt3ceW67iPLfdo5zv3sc3p5v287nRQIY7cfWxz189RBAgQIDAYAoIKg3Gdu3mWggrdfHWMjQABAl0kUHdQYc/pi2/U2X+TrLX6wugIb5odgwpWVFh8F8yZCRAgQIAAAQIECBAgQIAAgXYI/P4Pl4aLLvllO7puqs+j3vfJcOKp3w4vv/xy7vFbzdwu7PuOg3PrWlX44EN/Cyec8p3w4osv5HZZT1Aifqvttdf/Idx0y5/CvffdPb4KaEWPQ8ssW1oZIgYvVl9tzYra+t/GVUZvu2N+uPraK0pBj7wH8pdfboWw3ba7hO222Tkst+zy9XfexpZx3PMX3JRYXRXuTlayeOmlF3PPFgMJq66yelh3nfXDG1+3W1hpxWm57WoVPvHkY+H6G68JN877U7ICxWNJ0+xfEJYfucbqa4eZm20ddnztrjVDKeVHpe8Whf/4+v8t/PykrZp93XrL7cM793x32eE/Pu174a6/3l5WFt8c+09fqyprZcHTzzwVjj/5W+Gpp54o63aDZJWL9x/ykbIyb1orUBRUWHrpZcJnPv6lJMRTz+ofzY3plvk3hrN+cXLVweuu/cpw5Ps+XlU+UtD53xdf//aXwjPPPl0xninhmA9/LsQVWVq5dfJczYw7rrwTf0ZUbnvu9q6w/bavqyxu6v3i/jk0CHNs5MJ0+2eykbnUaus+tlrHfWy1SbtK3Mc2Lus+tnEzRxAgQIAAgU4LCCp0Wtz5KgUEFSpFvCdAgACBXIF6gwqb7Llx8s+Bxf8gmNf5lDCSKmjJcZlTT5kynlaIf7E0to0WCyqMidghQIAAAQIECBAgQIAAAQIECBBoQCB+u+2DDz8Qnk0emH12+NnkAeIlkqDACqWH7ddea90QV1No5fbc88PJg/iPhieeeLz0baErrrhSWHnaqsn5Vg5LLNHac7Vy3DGccv8D94ann3kyDD/3bBJaeClMW2mVUoBj5WmrtNTp5ZdfCk8kq4g8+dTjJacXX3ohxNDIcsstH9ZMQgrLL79iK6emLwIECAyUQK/+HGrkIg3CHBvx0LZ/BdzH1ndt3cfW56QVAQIECBAg0P0Cggrdf436fYSCCv1+hc2PAAECLRJoV1AhDSnEYbY6qBDzD2n/ggot+iDohgABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgS6XkBQoesvUd8PUFCh7y+xCRIgQKA1AvUGFWbsOX3khJkFDEYXTKgaSAwRlMIJse344gfj7WqVp60qj6vjvOmCDzfNmRfmz12Q9pT7Ojw8HIaGhnLrFBIgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAgW4UEFToxqsyWGMSVBis6222BAgQaFqgoaBCNiyQnrEiUFBrpYPSIdk+ssdmy/P6ztZnj0vbxtfRNjfNToIK5wkqZGnsEyBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgEDvCwgq9P417PUZCCr0+hU0fgIECHRIYNJBhTjOTHCgbUGFeJ40rJA5Xywe2wQVxijsECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgED/CQgq9N817bUZCSr02hUzXgIECCwmgYaCCskYYxBh0VhiYHTQaYAgO4eKMMHYcXlt43FJ+1KbRZkGFX2MdZ82qawfLbeiwpiUHQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBDoIwFBhT66mD06FUGFHr1whk2AAIFOCzQSVEhXS4hjLAsrpMGB7OAzIYKy47JBhEz7KVPGD1iUthkvyrQsnXz8fbaNoMK4iz0CBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQ6DsBQYW+u6Q9NyFBhZ67ZAZMgACBxSPQSFAhjnBsZYR0uHkhhZGGaYvSa9VqCWW1Sb+jQYVSACLtMxtCyLZP62NZ2iZTZkWFLJZ9AgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIEOgXAUGFfrmSvTsPQYXevXZGToAAgY4K1B1UmDW9vnHlBAdqHpjXPq8s20lSPxaYyAQU0iaCCqmEVwIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBDoJwFBhX66mr05F0GF3rxuRk2AAIGOC7Q0qJAGDOIscgIEVZMrap+WF/SRrr5QOs2i6kaCClXSCggQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECgDwQEFfrgIvb4FAQVevwCGj4BAgQ6JdDSoEIc9AQhg6p55bXPK6s4MIYVFuWEFGIzQYUKLG8JECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAoC8EBBX64jL29CQEFXr68hk8AQIEOifQcFAhhgiqFzGYeMATHZeGE2JPaf95ZROdKTnmprPmhfnnLajZcnh4OAwNDdVso5IAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECHSTgKBCN12NwRyLoMJgXnezJkCAQMMCDQUVmgkOxBHVc1xRm7Q8DS/UmuFo29KKCnMFFWpRqSNAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgACB3hMQVOi9a9ZvIxZU6Lcraj4ECBBok0BTQYV6QgPZ8aZhg1hW69jYrrI+ryzbd+V+0l5QoRLFewIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBDoBwFBhX64ir09B0GF3r5+Rk+AAIGOCdQdVNhzenWIIB1lGkTICxnENtnyorZpX/W+1uinFFQ4z4oK9VJqR4AAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQK9ISCo0BvXqZ9HKajQz1fX3AgQINBCgbYFFdIgQRxrXlChsryRORX1PdqHoEIjmNoSIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAQK8ICCr0ypXq33EKKvTvtTUzAgQItFSg7qDCrGRFhUa2WmGCWJcNLzTSb9q2Rh+CCimSVwIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBDoJwFBhX66mr05F0GF3rxuRk2AAIGOCyyWoELeLNNgQ50BhrRZeli2S0GFrIZ9AgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIEOgXAUGFfrmSvTsPQYXevXZGToAAgY4KtC2oEGeRpgjSVEGtmTXQNttdeli2a0GFrIZ9AgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIEOgXAUGFfrmSvTsPQYXevXZGToAAgY4KtDWo0NGZjJ9MUGHcwh4BAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQI9I+AoEL/XMtenYmgQq9eOeMmQIBAhwW6MaiwKIysmTBlbEmGxlAEFRrz0poAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIEekNAUKE3rlM/j1JQoZ+vrrkRIECghQKCCi3E1BUBAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIEGijwMMPPxzOOeecqjNsu+22YZtttqkqV0Cg1QKCCq0W1R8BAgT6VKAbgwqNUscVGLKrL1hRoVFB7QkQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECEwsIKkxspAUBAgQIJAKtCCosWrSoZDllypSOm8aQQrqlYQVBhVTEKwECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECgdQKCCq2z1BMBAgT6WqBfggppSCFeLEGFvv7ImhwBAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECCwmAQEFRYTvNMSIECg1wRaEVQomnNcaSFvlYWi8rx+GmmbHi+okEp4JUCAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAi0TkBQoXWWeiJAgEBfC7QrqBADBumWDSsUladtK1/T9tk+KttUvhdUqBTxngABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECAweQFBhckb6oEAAQIDIdCuoELEKwoZxPJ6gwdFfdS6OIIKtXTUESBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgSaExBUaM7NUQQIEBg4gUaDCo2EDBrCTBZgWJT8ryjA0EhgQVChIXmNCRAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQJ1CQgq1MWkEQECBAg0ElRIwwJRrShQ0KzoRH1PVJ89r6BCVsM+AQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQKA1AoIKrXHUCwECBPpeoLGgQuRIlj5ItsUXVJiSnLs0hMJfBBUKaVQQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBJoWEFRoms6BBAgQGCyBeoIKWxwwM8yYNb0sIJCucFAZWEjLkyhDBeRIwCEtLD6uPASR9pdtv6i8q6TLRWXBCUGFVNkrAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQKB1AoIKrbPUEwECBPpaYLJBhYgzFiJIAgSLRldcKA8qVCULSqZjxyXv0kBCtr+RQMLIseVtS4eP/jLed9pGUCHrY58AAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAg0BoBQYXWOOqFAAECfS/QTFAhGyCIgYQpmcUTRgIHmYIxwfFAwUhR5XGxNLYZLx8/z3hZqVVlV6PhCEGFqGMjQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECLRHQFChPa56JUCAQN8J1BNU2PLAmWHGrOllqx5kV0zIBhUaARoJIowcke0jLc8ri62z5dnzpasy3DznljD/vAXZqqr94eHhMDQ0VFWugAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAIF9AUCHfRSkBAgQIVAh0W1AhDSnEYWYDCUXl2ekIKmQ17BMgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIEWisgqNBaT70RIECgbwUaCypEhkXJf1PKPLKBgrKKCd5Uhg+y7+Oh2X6zddny9BRpSCG+t6JCquKVAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQINA6AUGF1lnqiQABAn0t0HhQYYQjGxbIhgTGscrDDCMBh1g7Xl7ex/iRadspmQYjQYUYkogBhvE+8s4tqJC1tE+AAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQaI2AoEJrHPVCgACBvhfoTFBhJGAwgjkeMsjkDUJ2xYT8oMJ4H4IKff+xNEECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECgCwUEFbrwohgSAQIEulGgrqDCATPDxrOmVw0/Rg7G4wPje9lVE8oPim3GgwqxLn2XPXrkmJGSKaMtFmXOVCobPXm2fOS4KeHmOfPC/PMWjLwt+HV4eDgMDQ0V1ComQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBCoFBBUqBTxngABAgRyBeoJKmyRBBVmlIIKaZwgjReMdJmujFC+KkISQhhtVl6e9pEdThI9KO+yVLkoc2DRKgrl5SN9Cipkbe0TIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBFojIKjQGke9ECBAoO8FmgsqRJbxZEEaMsjkCkpu+eV5QYUYahjvL0XPBhXi+dIm2fLscen5BRVSQa8ECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAgdYJCCq0zlJPBAgQ6GuB+oIKm4+uqDASFhgJBMTAQXW4YAQrP4wwUpf2Udmmsq9a9dm68eNKQYak6qY588L88xbUvG7Dw8NhaGioZhuVBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAEC4wKCCuMW9ggQIECghkAjQYXy1QvSsMB4UGDkNGl5/knz+4hts/3k9VFUP16errhw02xBhXx9pQQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgACB5gUEFZq3cyQBAgQGSqCZoML4igopVRoWyAsYpG1GXpP1FEqZhOI+Yru8ftJzVNaPlwsqjBj7lQABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECDQDgFBhXao6pMAAQJ9KFBPUGHLA2eGGbOmh0Uj6YJRhfGAwHiwIFuWYlWGDvLaxLbZdnltyutjKKE67DByzpvn3BLmn7cgHUDu6/DwcBgaGsqtU0iAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIFAtIKhQbaKEAAECBHIE2h9UiCctDxnkDKOszZTRpRHKchGZPtL6Us/ljUpdCyrkCyslQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECExGQFBhMnqOJUCAwAAJ1BtU2HiP6YlKUeAgLc9bCSFipvVxf+I2aRChPIOQ7SPpJQkzWFEhetoIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAp0REFTojLOzECBAoOcF6gkqbHHAzDBjVmVQITv18fBBaTGEJFMwEitIwwXj9WlNdWAhbZvf7/hx2fq4n/Y9frwVFSqNvCdAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQITF5AUGHyhnogQIDAQAi0MqhQCimMqi0qWw4hDRPEyvFAwXjIoLJ8tJOxEEJRfSyv7ltQIfXzSoAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBBonYCgQuss9USAAIG+FmgsqBApskGDlGY8LJCGFcaDCuN1I60rj0/rK8sr+56oPrYfaSOokNp5JUCAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAi0TkBQoXWWeiJAgEBfCzQeVMjjyAsRpAGEyvZJ29i8qjotyOsr9pHWx/1sm+pyQYVoZCNAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQItFZAUKG1nnojQIBA3wp0PKiwKBMyyGYMCoMIKX22caaPnOMEFVIzrwQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgACB1gkIKrTOUk8ECBDoa4HJBxWyoYEsVTZYkJaPto0vVdXZgon6zNanx42XCSqk3l4JECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAq0TEFRonaWeCBAg0NcC9QUVNg8zZk0vd0hzAWlOYKw2LUgbjFXk7KRtY1W2fVqelKXFaVGpl+ybtMF4Fzf/7JYw/7wFpZZFvwwPD4ehoaGiauUECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIVAoIKFSDeEiBAgEC+wKSDCrHbsdzA2E5SmAkQ5J86e2BF+7SfJoMKc5KgwvmCCoXsKggQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECgJwUef/zx8Nvf/rZq7JtsskmYMWNGVbkCAq0WEFRotaj+CBAg0KcCizeoEFEzoYQx47yyscrRndimIgwx+taKCpVW3hMgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIBAPwhcffXVYccdd6yayhe/+MVw7LHHVpUrINBqAUGFVovqjwABAn0q0FhQIRMgyGYE0uKx0EHEyjaI70cbLcqUjx2XqY+7Y8dmG2SOK7UZ/SVbPGWk/c1z5oX551lRIctknwABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgR6X0BQofevYa/PQFCh16+g8RMgQKBDAs0FFZLBpYGDbJYgDSOUxl6WIBifTXpcLMk9NntctlFl+WiX2WJBhVEULwQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECDQjwKCCv14VXtrToIKvXW9jJYAAQKLTaDxoEKSDEjDAWVBg3QKaWHaKJanZcluGlTIFKVHNv2ankpQoWlCBxIgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIBA9wsIKnT/Ner3EQoq9PsVNj8CBAi0SKC+oMLMMGPW9PGQQTx3WdAgfZMNMaRlSds0nFA6LlM+lniIbWJlxZZtGqvSNqOBhIrWY+e5+We3hPnnLaiqzhYMDw+HoaGhbJF9AgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECDQ1QKCCl19eQZicIIKA3GZTZIAAQKTF2hpUKEokFBUPpY8SOaRhhCyU2o2qDAnCSqcL6iQpbRPgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAr0vIKjQ+9ew12cgqNDrV9D4CRAg0CGB+oIKm4cZeyQrKmS3UoggTRJkV1JIG6V18X0mhZDuZqvTQ+p9TfuobD/a580xqGBFhUod7wkQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECgxwUEFXr8AvbB8AUV+uAimgIBAgQ6IdB8UCGTNEhXTMgUhZB9k0kWZHbLmoy9yTaIAmk/mfLMbpnRaFNBhTIVbwgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECgTwQEFfrkQvbwNAQVevjiGToBAgQ6KTD5oEKSGkiDA2mmYGwCaUHaIKnI7I5lEErtc9oWlWf7GDtXsiOokNWwT4AAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQJ9JiCo0GcXtAenI6jQgxfNkAkQILA4BOoOKsyaPjq80TRAuopCLC3KGGTrRo8uDiokDbIBhLTP9Lj4mtZX1cWCpHK0vrSiwvkLskdW7Q8PD4ehoaGqcgUECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQKBbBQQVuvXKDM64BBUG51qbKQECBCYl0FhQIZMQqDeoEEeXOSwNE5QGXVSezqioPlue7Xx0TIIKKaBXAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIEOgnAUGFfrqavTkXQYXevG5GTYAAgY4LNBVUyIYU4ojT4EC64kHlLNL6tDxtl5an79P69DWtj++zbbLlpbZJQWZMggopoFcCBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgUgHcYAAAKMklEQVQQIECAAAECBAgQ6CcBQYV+upq9ORdBhd68bkZNgACBjgs0FlRIhpcNDFSONg0QVLYplcdfKioq3o51N2W0o0z4YCQMkdNHPKiiH0GFMUk7BAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQINBHAoIKfXQxe3Qqggo9euEMmwABAp0WaCioUBEIqBrraL6gVJ5tmwYPKiuybbKdpe3LggoFnef0IaiQxbRPgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAv0iIKjQL1eyd+chqNC7187ICRAg0FGBuoMKe0yfeFwFWYLSgaXwQSZVkNmt6jgvqBAb1dmHoEKVqAICBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQ6AMBQYU+uIg9PgVBhR6/gIZPgACBTgk0HVRIwwQhkzjI7DY8/rH+kiOzKyk03FEIggpNoDmEAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBLpeQFCh6y9R3w9QUKHvL7EJEiBAoDUC9QQVVnnVymHa+iuVnzC7ekJaM6mgQtpJ8jqZfpLDH7vz8fDEPU9mOqzeHR4eDkNDQ9UVSggQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAQJcKCCp06YUZoGEJKgzQxTZVAgQITEagnqDCZPrv1mMFFbr1yhgXAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBQJCCoUySjvlICgQqeknYcAAQI9LiCo0OMX0PAJECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAYGAEBBUG5lJ37UQFFbr20hgYAQIEuktAUKG7rofRECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgACBIgFBhSIZ5Z0SEFTolLTzECBAoMcFBBV6/AIaPgECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgMjICgwsBc6q6dqKBC114aAyNAgEB3CQgqdNf1MBoCBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIFAkIKhQJKO8UwKCCp2Sdh4CBAj0uICgQo9fQMMnQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAgYEREFQYmEvdtRMVVOjaS2NgBAgQ6C4BQYXuuh5GQ4AAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIEigQEFYpklHdKQFChU9LOQ4AAgR4XuP/++8OGG27Y47NofPhPPPFEGBoaavxARxAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAgcUkIKiwmOCddkxAUGGMwg4BAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgR6X0BQofevYa/PQFCh16+g8RMgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQCAjIKiQwbC7WAQEFRYLu5MSIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECgPQKCCu1x1Wv9AoIK9VtpSYAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAga4XEFTo+kvU9wMUVOj7S2yCBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgMkoCgwiBd7e6cq6BCd14XoyJAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgEBTAoIKTbE5qIUCggotxNQVAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIECBAgQIAAAQIEFreAoMLivgLOL6jgM0CAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAIE+EhBU6KOL2aNTEVTo0Qtn2AQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIEMgTiEGFnXbaqarq2GOPDfE/G4F2CwgqtFtY/wQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAYIAEBBUG6GKbKgECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQaLeAoEK7hfVPgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQGSEBQYYAutqkSIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAIF2CwgqtFtY/wQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAYIAEBBUG6GKbKgECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQaLeAoEK7hfVPgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQGSEBQYYAutqkSIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAIF2CwgqtFtY/wQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAYIAEBBUG6GKbKgECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQaLeAoEK7hfVPgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQGSEBQYYAutqkSIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAIF2CwgqtFtY/wQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAYIAEBBUG6GKbKgECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQIECAAAECBAgQaLeAoEK7hfVPgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQIECBAgAABAgQGSOD/A9gg4aI2RFFdAAAAAElFTkSuQmCC\n", - "text/plain": [ - "" - ] - }, - "metadata": {}, - "output_type": "display_data" - } - ], - "source": [ - "from IPython.display import Image, display\n", - "display(Image(filename='images/QICK_wiring_new.png', embed=True))" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "# Configuring the channels\n", - "\n", - "The data in this notebook was taken with a wiring diagram similar to the above. The QICK has eight RF DACs which can be configured in multiple ways. Using the QICK, two RF DACs are needed to control the qubit and its readout resonator, respectively. Also, the qubit control pulses (< 6 GHz) were directly synthesized without the use of an analog mixer. Note that the QICK RF board was not used for these measurements, only the ZCU111 evaluation board plus the analog components specified in the diagram." - ] - }, - { - "cell_type": "code", - "execution_count": 3, - "metadata": { - "ExecuteTime": { - "end_time": "2021-09-30T07:30:27.452111Z", - "start_time": "2021-09-30T07:30:24.088270Z" - } - }, - "outputs": [], - "source": [ - "# Load bitstream with custom overlay\n", - "soc = QickSoc()\n", - "# Since we're running locally on the QICK, we don't need a separate QickConfig object.\n", - "# If running remotely, you could generate a QickConfig from the QickSoc:\n", - "# soccfg = QickConfig(soc.get_cfg())\n", - "# or save the config to file, and load it later:\n", - "# with open(\"qick_config.json\", \"w\") as f:\n", - "# f.write(soc.dump_cfg())\n", - "# soccfg = QickConfig(\"qick_config.json\")\n", - "soccfg = soc\n", - "\n", - "hw_cfg={\"jpa_ch\":6,\n", - " \"res_ch\":5,\n", - " \"qubit_ch\":2,\n", - " \"storage_ch\":0\n", - " }\n", - "readout_cfg={\n", - " \"readout_length\":soccfg.us2cycles(3.0, gen_ch=5), # [Clock ticks]\n", - " \"f_res\": 99.775 +0.18, # [MHz]\n", - " \"res_phase\": 0,\n", - " \"adc_trig_offset\": 275, # [Clock ticks]\n", - " \"res_gain\":10000\n", - " }\n", - "qubit_cfg={\n", - " \"sigma\":soccfg.us2cycles(0.025, gen_ch=2),\n", - " \"pi_gain\": 11500,\n", - " \"pi2_gain\":11500//2, \n", - " \"f_ge\":4743.041802067813,\n", - " \"relax_delay\":500\n", - "}" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "# TOF Measurement\n", - "\n", - "Measures the \"time of flight\" of the measurement pulse. The time of flight is the time at which the measurement pulse appears in the ADC buffer. We only want to start capturing data from this point in time onwards. We store this time of flight in the parameter readout_cfg[\"adc_trig_offset\"] ." - ] - }, - { - "cell_type": "code", - "execution_count": 4, - "metadata": { - "ExecuteTime": { - "end_time": "2021-09-30T07:30:33.274722Z", - "start_time": "2021-09-30T07:30:27.459934Z" - } - }, - "outputs": [ - { - "data": { - "application/vnd.jupyter.widget-view+json": { - "model_id": "91da691d8cdb46d99a8ce42cf6fb8b9b", - "version_major": 2, - "version_minor": 0 - }, - "text/plain": [ - "HBox(children=(IntProgress(value=0, max=1000), HTML(value='')))" - ] - }, - "metadata": {}, - "output_type": "display_data" - }, - { - "name": "stdout", - "output_type": "stream", - "text": [ - "\n" - ] - }, - { - "data": { - "text/plain": [ - "" - ] - }, - "execution_count": 4, - "metadata": {}, - "output_type": "execute_result" - }, - { - "data": { - "image/png": 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A61mgb1sKtqNJaz0XY033BRgjFdwY79H7wNhwwba5v9ZaP4DxGVmJ8XtxYfx+5wJDwwXbZh+ngCuB32BceCnGuAiyE+Niz0AJtoUQ4vSTDLcQQghxFjKLc20yH16qtd7WkucjhBBCnIskwy2EEEKcnW41bysxsppCCCGEOMMk4BZCCCHaIKVURpht/YBHzIfvRjKcXgghhBDRJ0PKhRBCiDZIKbUKKMRYKm0rxjztThiVrf8DyMCY9ztEay0ZbiGEEKIFSMAthBBCtEFKqY+B0WGauIB7tNZvn6FTEkIIIUQdEnALIYQQbZBSajgwAbgaY83nTGoqWX8MvKC1PthyZyiEEEIICbhPg8zMTN2jR4+WPg0hRCuzL78cgJ7tE1v4TIQQQgghRFNt2bLlpNa6fSRtY073yZyLevTowddff93SpyGEaGXu/OeXALz+0PAWPhMhhBBCCNFUSqmIR5BJlXIhhBBCCCGEEOI0kIBbCCGEEEIIIYQ4DSTgFkIIIYQQQgghTgMJuIUQQgghhBBCiNNAAm4hhBBCCCGEEOI0kIBbCCGEEEIIIYQ4DSTgFkIIIYQQQgghTgMJuIUQQgghhBBCiNNAAm4hhBBCCCGEEOI0iGnpExDgcrkoLCyktLQUn8/X0qcjhGgCu91OcnIyGRkZOByOlj4dIYQQQgjRCkjA3cJcLheHDh0iPT2dHj16EBsbi1KqpU9LCNEIWms8Hg8lJSUcOnSIbt26SdAthBBCCCFkSHlLKywsJD09nczMTOLi4iTYFqINUkoRFxdHZmYm6enpFBYWtvQpCSGEEEKIVkAC7hZWWlpKSkpKS5+GECJKUlJSKC0tbenTEEIIIYQQrYAE3C3M5/MRGxvb0qchhIiS2NhYqcUghBBCCCEACbhbBRlGLsTZQ/49CyGEEEIIiwTcQgghhBBCCCHEaSABtxBCCCGEEA3w+/0tfQpCiDZIAm4hhBBCCCHCeH79Uga9Ooitx/a39KkIIdqYVhtwK6X6KqV+o5RapJT6XinlV0pppdSECPa9Wyn1uVKqWClVppT6Win1S6VU2NerlLpRKfWRUqpQKVWhlNqulPqDUkoW1G0hPXr0QCnF2rVrW/pUglJKnVVzdq+88srqJa7y8/PDth05cmT167d+kpKS6NKlC9dccw2PPvooGzZsiPjYK1as4N5776V3794kJSXhdDo577zzGDt2LHPmzGlS5e/du3czadIkunTpgsPhoHv37kydOpXjx483ui8hhBDnroW7ZwOw4dD2qPX5j00r2J1/LGr9CSFap1YbcANTgReAe4C+QERRjVJqNrAYGAZ8DqwGLgRmAW8ppewh9nscWAlcB3wDfAB0AP4MrFVKJTTnxQjR2u3evZsvv/wSAI/Hw6uvvhrRfiNGjGDy5MlMnjyZW2+9lf79+/P999/zwgsvMGLECEaMGMHevXtD7p+Xl8fIkSMZO3YsixYtIi4ujjFjxjB+/Hh69OjBxx9/zNSpU+nZsycHDx6M+PWsW7eOwYMHs3jxYjp37sztt99OQkICc+bMYdCgQezZsyfivoQQQpy7/H4/vpg8AAoqi6PSZ0FFKf+36/dMWPFvFFWWR6VPIc6EpTu+ZMC8Yew4cbilT6XNaM0B93bgOeBOoDewrqEdlFI/AX4B5AKXaK1v0VrfDvQBdgG3A9OC7DcM+CtQAYzQWl+vtf53oCfwGXAF8JdovCghWqtXXnkFgK5duwIwd+7ciPb7+c9/zvz585k/fz5Llixh9erV5OXl8emnnzJkyBA2bNjAlVdeyb59++rtW1RUxIgRI1i3bh3Dhw9n27Zt7Ny5k6VLl5KVlcX69es5efIkM2fOxO12c+rUqYjOqby8nIkTJ1JZWcn//u//smXLFrKysti1axfTp08nPz+fu+66C611hO+OEEKIc9WWYzV/v3LLwo/+itQ3R3Oq7/95XWQXuIVoDf659VWUzcX8b1e09Km0Ga024NZav6y1flxr/YbWOqfhPQB40rz9vdb6h4C+TmBkzAGeCDK0/AmMDPpMrfVXAfuVAVMAP/ALpVRaU16LEK2d1+utzmi/8sorpKWlsWPHDjZt2tTkPkeNGsWGDRsYPnw4+fn5/PSnP63XZtq0aezdu5fLL7+cTz/9lEsuuaRem+TkZB5//HG2bNlCx44dIzr2vHnzyM3NZeTIkUybVvsa28yZM+nVqxfffPMNK1eubNqLE0IIcc44XFwTZJ+sPBmVPnfkH6i+//nxj6LSpxBnQnJcKgCFlUUtfCZtR6sNuBtLKXUeMBRwA2/W3a61XgccBTphZKyt/eKAm8yHi4Pstw/4EogDbo76iYuouuKKK1BKsWzZspBtfvvb36KU4ne/+131c/n5+bz44ovceOONXHDBBTidTlJTU7niiiuYPXs2Pp+vUefR0Nxua276gQMH6m3zeDzMmTOHq6++mvT0dJxOJ3369OGxxx4LOa/6vvvuo1+/fsyaNatR52lZsWIFubm59OzZkzFjxnDXXXcBkWe5Q3E4HLz00kuAMcT766+/rt6Wk5PDkiVLAJgzZw5OpzNsX71796Zz584RHffdd98FYNKkSfW22e12Jk6cWKudEEIIEcqJ8prRVUWugqj0ubfQmCLVy3EjFbYf2Fd4Iir9CnG6KXOWb15lbgufSdtx1gTcwGDzdofWujJEm8112oIxPzwBKAyTSQ+2n2iF7r//fgDmz58fdLvP52Px4sW12gJ8+OGHPPLII+zYsYMePXowfvx4hgwZwrfffsu0adP4yU9+ckaGH5eUlHDdddcxdepUsrOzGTJkCGPHjsXr9fL3v/+dYcOGBQ3SDx06xO7duzl5smlX3q3AevLkySilmDJlCgBZWVlUVob65xSZAQMGcOmllwKwevXq6ufff/99/H4/AwcOZPDg6P7T2rp1KwCXXXZZ0O3W81Y7IYQQIpSCCiOTp/0OyrzRyeodKTuC9jsY1sn4+3fglATcom0odRt1DPKrjrTwmbQdZ1PAfYF5G66q0qE6bQPvHyK0YPuJVmjixIk4nU4++OCDoMHnhx9+SG5uLsOGDaN///7Vzw8dOpSNGzdy+PBh1qxZQ1ZWFmvWrGH//v1ceumlLFu2jDfeeOO0n/+DDz7I+vXrmTBhAvv37+eTTz7h7bffZu/evTz++OMcOnSo1oWCaMjLy2PFihUopZg8eTJgBKQDBgyguLiYt99+u9nHGDp0KAA7duyofm7Lli3Vx4qmkpISCgsLAejevXvQNt26dQNg/35Z3kUIIUR4hZVGhtupu1Dpj07AXeDKJdafSZoz2ThGReNX4hCiJZT7SgCo0JLhjlRMS59AFCWZt+FKPZaZt8lR2O+0e3r5DnYeKzmTh2y2i7uk8P/d2r/hhqdJWloa48ePJysri9dee41f//rXtbZbme+6QetFF10UtL/OnTvz7LPPMmbMGN566y3uvPPO03HaAOzcuZPXX3+d7t27s3DhQuLj46u32e12ZsyYwapVq1i3bh3Z2dkMHDiwentzlk1buHAhHo+H0aNH1wpQp0yZwvTp05k7d27QodmN0b59ewAKCmqG4lnD4zt06NCsvusqKyurvp+YmBi0TVKS8c++KUuNCSGEaH3uefspjpUfZPU9LxNjD7ogTZOdqjIyeu3izuOYOzojo8q8+STFtCc93gy4q9rW9z1x7qrylYIdtL2I4qoKUp2ykFNDzqYMtzVhtrHjfpu6X+1OlHrQXO/764bWLxanV6hh5UVFRbz33nvExcVVz1EO5PV6+eijj3j66aeZOnUqU6ZM4f7772fOnDkAp30ZKauA1y233FIr2LbYbDauuuoqgOrlu6Jh3rx5ANXDyC2TJk0iNjaWtWvXNjsT7Pf7AeM1nG5SeVwIIc4txVUVfFf2Nif11/x+9UtR77/EXYL2x9E5sSvaVs6xksJm9+lTZSTFpNIuPgWAosrWdwHY7/eTUyBZTFGbR9d8Vr87fqDFzqMtOZsy3NZvPylMG2tb4P9qTd2vFq31S8BLAMOGDYvKN/6WzBS3ZTfccANdu3Zl69attTLBWVlZuFwuJkyYQEZGRq199uzZw/jx49m1a1fIfktKTu/VZ2vZrNmzZzN79uywbaN1UWfjxo3s3LmTlJQUfvzjH9fa1qFDB26++WaWLVvGvHnzeOaZZ5p8HGt4f+D7bmW98/LymtxvMMnJNQNRysvLSU1NrdfGyoIHthVCCNE2vbT5g+r7W/O2RL3/Mk8JNn8Co7pfwZbsLJZ8t4bpV/2kWX36VSUJMUm0SzAC7mJXWQN7nHkzPssi6+AM/r3b7/njqOaNdBNnD58qJ8bbGW/McXbmH+DqCy5u6VNq9c6mgPuAeRt80qbh/DptA+93a+R+opWy2Wzcd999zJgxg/nz5/O3v/0NgAULFgD1h5MDTJgwgV27djFu3Dgef/xxLrroIlJTU7Hb7ezZs4e+fftGNXNqZXwDWZXQhw4dyoABA8LuHzj/vDmsYmlKKW644YZ6248ePQoYowWeeuqpJmeorfnagcPghw4dyquvvsrmzZtD7dYkKSkpZGRkUFhYyMGDB4MuNXb48GHAqBYvhBCibduc+y1a23H4u1Klop8prvCVEqOSmND/Kp7bFse6w18wnaYH3BUeF8rmJiUuhfZmwF3ibn0B96bjxt/uN/fPkoBbAOD1+dC2CtrHDOa47zg5p6RwWiTOpoDbmlTTXykVH6JS+WV12gJ8D1QCGUqpXiEqlV8eZD/Rit1///3MmDGDxYsXM3PmTHJycti4cSOdOnXixhtvrNX2+++/Jzs7mw4dOrB06VLsdeZ+7d27t9HHj42NxePxUFZWVj1f2OLxeDh+/Hi9fc4/37iuM2rUKJ577rlGH7OxKioqeP311wEoLi7miy++CNn28OHDfPzxx4wZM6bRx8nOzmbbtm0AtYL6sWPH8thjj5Gdnc3WrVujWql88ODBfPLJJ2zevDlowG2tLx7t6uhCCCHOvDJ3CcqfgNOWQpU/+gG3y1dOrEog0eEghd4crdzdrP6OFhtD0lOdqbRPNEZhlbXCgPuk67gx8dJeTlFlOWnxweuiiHPHsdJClNL0Su3DsYINHCmVgDsSZ80cbq31YeAbjPWy/73udqXUtcB5QC7GutrWfm5gpfnwniD79QSGY6zv/UHd7aJ1uvDCCxk+fDgnTpxg1apV1dntSZMm1QuorYrWXbp0qbcNqF5GrDG6du0KGMF8XR999BFer7fe8zfdZCwH/+677wbdHm1vvfUWJSUl9OrVC611yB9rvfKmrMntcrl46KGHABg9enStALd3797VReimTp2Ky+UK21dOTk7QCxXB3HbbbUDw353P5yMrKwuA22+/PaL+hBBCtF4V3lJidCLx9mS8OvqBq0eXEW8zpiDFx6Tg01XN6i+31Kh6nu5IIdHhQPtjKPeGq93bMkp9R6vv7y2I7O+vOLvtOXkMgM5JHbD50mQt7gidNQG3aYZ5O1Mp1dt6UinVAfg/8+FftdZ1x/P+FaNo2u+VUpcH7JcEzMV4n/5Pax2dtSDEGWEVAZs7dy6LFi0Cgg8n79OnDzabje3bt/PZZ5/V2jZv3jyWLFnS6GOPHj0agGeeeQa32139/I4dO/jVr34VdJ8hQ4Ywfvx49u7dyx133MGRI/WvGh4/fpwXXnihXkA+cuRIlFI89dRTEZ+jFUDfe++9YdtZ2999911OnToVcf9r167lyiuv5Msvv6Rjx468/PLL9drMmjWLnj178tVXX3HdddeRnZ1dr015eTnPP/88Q4cO5cSJyNYpnTJlCp06dWLNmjX15sM/8cQT5OTkMHjw4OqLHEIIIdquSn8psSqJxJhk/Koi6v37VAUJMUbAHavi8ONuYI/wTpQZf0vbJaQBoLSTCk/rCrjzy0rQMYU4fb0AyCmUgFvAxiPG8q7DulxEvC2TEk906/CcrVrtkHKl1BBqgmQAa0b+fyulfms9qbW+IuD+W0qpfwBTgWyl1MeABxgNpADvArPqHktrvVkp9QQwE9iglPoUKAKuBToAXwF/iOLLE2fAnXfeyW9+8xveeecdgHprb1vat2/PL37xC2bNmsWoUaO49tpr6dSpE9nZ2Wzfvp0nn3ySGTNm1NsvnCebA8JVAAAgAElEQVSffJI333yT5cuX07dvX4YOHUpubi6bN2/mjjvuwO/3c/Bg/SXjFyxYwLhx43jnnXdYuXIlgwYNonv37pSUlHD48GF27dqF3+/n4YcfJiam5p+vNSc8NjY2ovPbt29f9cWFhpb8GjhwIIMGDWLbtm0sXryYadOm1dr+8ssvVy9L5na7KSgo4Ntvv60uhnb11Vczb968oPOlMzIyWL9+PXfccQfr16/nkksu4eKLL6Zfv37ExcVx9OhRNm3ahMvlomPHjvWK3YWSlJREVlYWN910E9OmTWPevHn06dOHbdu2sWvXLjIzM1myZAlKqYY7E0II0aq5/eUkxbQnOS4F7arC6/NFbWmwcpcLv62UNEc6AA67E62aF3DnVRgBd3sz4LZpB1W+6F8oaI7NR38AoE/KJWSX53CoWDKZArbn70JrO9f2GED8xmSKvcda+pTahNac4U4BfhTwY5UT7lPn+Vq01r/AGBr+DUbA/G/AXmAa8BOttS/YwbTWzwI3AWsw5nrfCpwE/hO4Vmvduv4nFA2qW3k7WHbb8uKLL/LSSy8xaNAgNm3axMqVK+nYsSMrV67kwQcfbPSxe/XqxRdffMG4ceMoKirigw8+oLi4mOeee46FCxeGPedPPvmEhQsXcs0115CTk8PSpUvZsmULMTExPPzww3z44Yc4nc7qfXw+H9999x0OhyPi9bLnzZuH1prhw4fTq1evBttbWe5gw8q/+OILFixYwIIFC1i2bBnZ2dlceOGFPPLII2zYsIHPPvss7DE6d+7M559/zvLly7n77ruprKxk1apVLF26lH379nH99dfz0ksvkZOTQ7du4Wob1nbttdeydetW7r77bo4cOcLSpUspKyvjoYce4rvvvqNv374R9yWEEKL18qlyEuzJpDpSUUpzvDR6AxK/OrIbpfz0zegDWAG3p1l9nqwwzq9DkhFw24nH5Q9WeqjlnKoy5sJfmGEMGD1eJplMAYfLc4jzdybR4SDOHo+P8NMBhaHVZri11mupWSO7sfu+BrzWhP1WAauackxxehw4cKBZ+y9atKh6OHk4NpuNBx54gAceeCDo9lAVysNVLh8wYADLli0Lui3c67Lb7dx7770NDvW2bNq0ieLiYh599FG6dw9XpL/Gn/70J/70pz9F1BZg+vTpTJ8+vdZzVlY7Wm655RZuueWWqPbZt2/fJs3BF0II0Xb4VTlJsSmkO40CZEdLTnJ+Wruo9L3pqLFc6JDO/QAj4FY2D36/v8krdxSZwWznZCNrHmuLx+1vXXmdEpdxPr0zzkcfUpyoiM5ypKJtK/UfolOcseKMcfFJAu5ItOYMtxAiAqtXryYlJYU//EFmPQghhDi3FFdVoGweUh2pZCYYAeyx0sKo9b/r5F60VlzV/SIAnDHGCLMSV9Mz0sWuYgC6phgXBWJVPJ6gi+u0nDIz4E6PT0b5kzhVVdDCZyRamtvrxW8roWN8ZwDi7QkScEdIAm4h2rg//vGPFBcX065ddK7mCyGEEG3FsRIjuE5zpNE+0RiinV8eeYHPhhwu24/dl0F6grHEZ7wZcBdVNr3IWYm7BO2PJdkRD4DDntDsyufRVuExLgCkOROJJY0ST/QuYoi2KbfsFEppUh3GSJL4mASUzYv7DKys09ZJwC2EEEIIIdqkoyVG5rVdfCqdk4zCmvkV0ZvDXeo9SbytffXjhFgz4HY1fQh4uacUpeOrH8fbE/Gr1pXhLjcD7lRHIg6VhMvfuqqoizPPurhlTd1IiDU+w4WVpS12Tm2FBNxCCCGEEKJNyi0zgoD2iel0TjYC7sLK4qj178NNrHJUP7aCjJKqpgegFd4yYnRC9ePWOBfWynCnOhNx2BLwtrIh7+eSXyz/O//ctKKlT6N6qkZ7c+pGYqzxGS6oKGuxc2orJOAWQgghhBBtUp65pnWHxHQ6JBmZtzJP9AIAv3YTY4urfpxoBtyl7qYHoFX+MmJVYvXj+Jj46kJsrUWl1xjinhafYAx5RwLucE6UFbM7P/pLZLm9Xj4vnMusXb+Pet+NZU3VsKZuJMcZn+GiKgm4GyIBtxBCCCGEaJNK3MaX/XbxKaQ6jIxbpSd6waEfD7G2mgx3UpwZcDdjSLlHlxNnqwm4rUJsxVWtp1J5la8SrRWJsQ7iYxLRqnXNMW9tbnhjLBNW/FvU+92We6D6/oHCll2azZqq0THJyHAnxRn/3golw90gCbiFEEIIIUSbVOa2qmknEWO3o/2xVPmiFxxq5SYuMOA2g/rSZlQp9+oK4u3J1Y8TYow+TzVhmPq+whNUeKI/HL3KWwU6DpvNRkJMItpW1aoy8K2NtkdvGkOgTUd2Vd//15b3T8sxImVN1eiSYkzdSHEYhQSLXRJwN0QCbiGEEEII0SZVV9OON778Kx1LlS+Kw5+Vt1bAnWJm9axAvyn8qoLE2ICA2yzEdqqycYGL3+/ntuXXM2rRXU0+l1BcviqUjgUgKS4RpXSTLgicCw4X1SyZFu2LEjvy9xp3fEmsOJSF1+eLav+NUeQyMtzWcnapTmOURolLPhcNkYBbCCGEEEK0SRVeI/DNSDC+/CvtwO2LXsZXKw8Oe2CG2xhSXtHEYetenw9tqyIpNqmmzzgrcGlcEJ9bZgRAFbYfOFSUH9E++WUl5JeVNNjO7XehtDF3PTnOONe8stOTxW3r/rH53er70S4gdrD0APgSGN/tIbwxx1m688uo9t8YdZezk4A7chJwCyGEEEI0w+f7dzL61QeaNcxYNE2FtwLtt5MQawTFNuJw+6Pze3B7vSjlIy4g4E4xh5SXNzHgzi0rRilNSlxK9XNWIbbiRmaQd+Ydrr4/Z9N7Ee1z25sPcuubP22wndtXhR3jdac6jGx8frkE3HUt2/kVy4+9UP34eFl01ysvcB3DSSeGnz8QgINFx6Paf2OUuUuwBVTXz4hPNp9vPbUHWisJuIUQQgghmuG17avI829k7b7tLX0q5xyXt6o6EwtgVw48/uhkuK0iZs6YmoA7zczqVXibNk/8eGnttYyhJohvbCG2PQU1Aff2gh0Ntq/wuChhN+W23Ww+sjdsW492YVfG+5pmBtyy3nJ9O/L3AZDBEABOlEZvDXiASn8ByTHt6Z7Wwei/vKCBPU6fCl8pdl1T7C/DnMZR5pGAuyEScAshhBBCNMOxsqMA7C080sJncu6p8lWiqAmIY5QDj45OwG0N8baqiENNcNzUSui5pcbSShnxNQG3Ve25sUNzrWyn8mZwvDKnwfarf/gWZfMC8I+v3wzb1qtd2M31x9PNTGZhRcND0c81JyuMCyijzh8NQF5F9AJuv9+Pz3aKTGdHepgB98nKlgu4q3xltarrWwF3uWS4GyQBtxBCCCFEMxS4jMDnYEn01+EV4bn9Vdh07YDbG7WA2wiq4wMy3KlOM+BuYobbWss4MyEtoE8jiClv5Nrex8py0VrRPWEIleowbq83ZNtDRfk89eV/AmDzZvJNwadhC3z5tIsYM+BOcxoB96kqyXDXVVBpBNj9MnsYj6M47D6n8ATK5qVzUmcSHQ7wxXOqKrpD1hvDpU+RaM+ofpzqTEBrRaVXAu6GSMAthBBCCNEM5T6jYFVuWW4Ln8m5x+Ovqs7EAsQqJ/4oBdzWEO8Ec441QFxMDNofg6uJS4+drLOWMQQMKW9kpvBkVR7Kn8wlmQNRNg8bD+8O2faFL9/AG5OL8qZzfdc78MXk8sHuLSHb+7SbWPN9bZ9ozDcvkoC7nmJ3EficnJ/aHqgJwKNhR95BALqndAHArpMp9bTMPHoj215EO2eH6udsNhvoOCq9UruiIRJwizbB7/fz2muvcdttt9G1a1ccDgcZGRkMGzaM//qv/yIvL6+lT7FBSimUUi19GlFz5ZVXopQiLi6O/Pzw1VFHjhxZ/fqtn6SkJLp06cI111zDo48+yoYNGyI+9ooVK7j33nvp3bs3SUlJOJ1OzjvvPMaOHcucOXMoLW38l4Ldu3czadIkunTpgsPhoHv37kydOpXjx1uuQIkQovXz+/14bMYwz4Kq1v+3KJT/+OgVrlv4M/YVnmjpU2kUj66qzsQCxNkc+HBHpe9St5XhdtZ6XulYXE2shF5YZQRMgQF3ujk0t6KRgUuxOx8H6Qzo0AuA7Xn7Q7Y9UnYMrRUb71vNlEvHAvDJgU0h2/upWX+8faIx/L3ELest11XmKcamk+hk/j5PVUVv2P0PBcYUlT7tzgcgTqVQ4YvuHPFIWdn2Tomdaj2vdBxVPslwN0QCbtHqHTlyhMsvv5x77rmH999/n27duvHjH/+YK6+8kv379/PnP/+ZXr168cYbb7T0qZ4zdu/ezZdfGktTeDweXn311Yj2GzFiBJMnT2by5Mnceuut9O/fn++//54XXniBESNGMGLECPbuDV3IJS8vj5EjRzJ27FgWLVpEXFwcY8aMYfz48fTo0YOPP/6YqVOn0rNnTw4ePBjx61m3bh2DBw9m8eLFdO7cmdtvv52EhATmzJnDoEGD2LNnT8R9CSHOLcYXUQ8AJd7IlmZqjZYfmUu+3sTUFU+39Kk0ile7iFE1AXGc3YlW0Qm4y8wh5YlxdQJuHJS4TzWpz2KXcUG4c3LgkHIjw93YpcZcugSnLZWLOnQHYH/R0ZBtC6vysfsySIh10K99V7Q/hmOloadA+JWbOLvxujskGQF3mQTc9VR4S4hVydUBd4k7egH3wWLj99m/YzcA4u0puPwtM8pgZ94hAHqkdq31vE07mzza41wiAbdo1QoLC7n66qvZsmULI0eOZO/evXz55ZcsWbKE999/n9zcXGbMmEFFRQUTJ07k7bffbulTPie88sorAHTtavzHO3fu3Ij2+/nPf878+fOZP38+S5YsYfXq1eTl5fHpp58yZMgQNmzYwJVXXsm+ffvq7VtUVMSIESNYt24dw4cPZ9u2bezcuZOlS5eSlZXF+vXrOXnyJDNnzsTtdnPqVGRfhsrLy5k4cSKVlZX87//+L1u2bCErK4tdu3Yxffp08vPzueuuu9BaR/juCCHOJdknDhh3/E4qbD/w03dntOj5NMWuvCNgNwKFYk/bumjg0y7ibDUBscPuRKvoDCm35lQnBgwpBzjfOYQ8/9cNVvoOxhp+a1U7B0iLT6y1LVJeXUG8PZl+mV3Q2sbR0tAjsko8J3HajPm3MXY7dn86J6tCT4HQyo3DDLiTHfFov51Sjwwpr8u46JFEosOB9sdS6o7ee5RXkYf2x9AjzRiunhybjle1TOE6qyBk74zzaj1vVw5cUVqG72wmAbdo1X75y19y4MABLrvsMlauXMkFF1xQa3tsbCxPPPEEzz//PFprfvazn3Hy5MkWOttzg9frrc5ov/LKK6SlpbFjxw42bQo9NK0ho0aNYsOGDQwfPpz8/Hx++tP6a4ROmzaNvXv3cvnll/Ppp59yySWX1GuTnJzM448/zpYtW+jYsWNEx543bx65ubmMHDmSadOm1do2c+ZMevXqxTfffMPKlSub9uKEEGe1Q8XGEOze8aMA2FqwtgXPpmle3/6pcceXgke3reGhfmoH3PEx8SibJ2xBsEhVeI3APclRO+B++ppfoZSPBd9+0Og+q7xVaL8dZ2zNUmYJsQ60tjc64ParChJiEnHGxmHzpXKyMnQAXaULSIlpX/040daeEm/wKRB+vx+Up1Z1drs/LWz/5yqPLichxhgBYNMJVHijNwqg2H0Kmz/ZmCsNpDnS0bZyvD5f1I4RCa/Px1fHvgHg4g7dam2LwYHHLxnuhkjALVqtnJyc6mHis2fPxul0hmz761//moEDB1JcXMzs2bMj6v+KK65AKcWyZctCtvntb3+LUorf/e531c/l5+fz4osvcuONN3LBBRfgdDpJTU3liiuuYPbs2fga+R9hQ3O7e/TogVKKAwcO1Nvm8XiYM2cOV199Nenp6TidTvr06cNjjz0Wcl71fffdR79+/Zg1a1ajztOyYsUKcnNz6dmzJ2PGjOGuu+4CIs9yh+JwOHjppZcAY4j3119/Xb0tJyeHJUuWADBnzpywnwWA3r1707lz54iO++677wIwadKketvsdjsTJ06s1U4IIQIdKzWClqdH/oIOtivw42nhM2q8b/Oy0f442sdchFe3rWyVVi6c9pqAOD7GGJ5traHdHBVmhjsprnbAPcAc4lvahCHWLp8LpWPrPa/8cY2aF+71+dC2KpLijAriTtWO4hBTGrw+H357ca2CV2lxHXARfImpco8Lpfy13teUmPM55TkU8fmdK/y2MpJjjYDbrhMp80avqFmZt4hYlVL9OM2RhlKaY6VntlL5c+vfYlflewD0yqidzIixxUdtVYCzmQTcotV6//338fv99O/fn8suuyxsW6UU9913HwDvvfdeRP3ff//9AMyfPz/odp/Px+LFi2u1Bfjwww955JFH2LFjBz169GD8+PEMGTKEb7/9lmnTpvGTn/zkjAw/Likp4brrrmPq1KlkZ2czZMgQxo4di9fr5e9//zvDhg0LGqQfOnSI3bt3N3kkgBVYT548GaUUU6ZMASArK4vKyuZ9URswYACXXnopAKtXr65+3vosDBw4kMGDBzfrGHVt3boVIORnzHreaieEEIFOlBtBTq/0ziTEJOFXbStgBThemYNTd22T56+VG0dMYIbbuH+qqnFrWgdTYS79lVwn4HbGxqH9sVR4G38Mt78KiKv3vCIOly/y9/5kRQlKaVLijIAsJbY9Vf7gAfQPBcdRykeXpJqCVx0TOoO9lKLK+q+hoNwYFp0Ym1D93PmJF+Cx51HukuDKUlxVgbK5SXMY87eTYjpQFmLUQFNU+YuJt9UE3OlOI7A/VnJmA+59RcaFlstTJ1Vn2y1xyoFPS4a7IRJwi1ZryxZjuYrLL788ovZWYLRt27aIsswTJ07E6XTywQcfBA0+P/zwQ3Jzcxk2bBj9+/evfn7o0KFs3LiRw4cPs2bNGrKyslizZg379+/n0ksvZdmyZWekgNuDDz7I+vXrmTBhAvv37+eTTz7h7bffZu/evTz++OMcOnSo1oWCaMjLy2PFihUopZg8eTJgvO8DBgyguLg4KnPohw4dCsCOHTuqn7M+Cw1deGmskpISCguNP1zdu3cP2qZbNyOTsX9/6OqvQohzV6HrJPgSSHQ4SIpJRtsqozKc+Uzx+/1U6MN0cvYkITYRrdrOl+cqjxtl85EQUxMYJplB4qnK+tnnA4V5HCiMPCCq8BjvRZKj/qgqpR1NWn/Y7XNh00ECbh2H2x95MHu81KhWne4wgrBMZ0d89qKga3FvOmIsF9YzvWY4cLcUowbLd7kH6rUvqDQC7qSAgLtfuwtRys+GQ7siPsez3XEz05zqMILiDs6ueGz5Ufv379ElJMbUFNdrZ67dnlvWtIJ9TVXiLkb77fxr3O/qbYuzx+NDLsI0JKalT0CEsfIJyM1u6bNonE4D4aa/RqUra0h0pHNxrXY+n4/CwkLat28ftn1aWhrjx48nKyuL1157jV//+te1tluZ77pB60UXXRS0v86dO/Pss88yZswY3nrrLe68886Izrspdu7cyeuvv0737t1ZuHAh8fE1V9/tdjszZsxg1apVrFu3juzsbAYOHFi9fe3atU0+7sKFC/F4PIwePbpWgDplyhSmT5/O3Llzgw7Nbgzr91ZQUHOl3vosdOjQIeg+TVVWVvOFLDExMWibpCRjuZamLDUmhDj7lbgLidFG0JMUl4yq8FFcVUF6QlILn1lkth7fD/YqLkzvS7GrGGXzUuqqJLnOvOXWqNAMqgMD7gQzG10cJMN96/LRaK3Yfv93EfVfaWa4U+IS6m2zaUejMtIWt78KW5AMt105zOx3ZKxgLz3eCPa6JndhR4WPPSePMaBT7Xm2nxz4Eq0V4y8aUf1c+0SjgFqw4M1675IcNa/78q4X8+Yh2HxsFzf0uTTi8zybFVYYn78Uh/H9oXvK+eyp8rAr/yj9O57frL79fj9+Wxmpjprl49onGgF3XvmZDbjLPCUonVAvuw3gtMdHrUjh2Uwy3OKsETiM2xvkCm8woYaVFxUV8d577xEXF1c9RzmQ1+vlo48+4umnn2bq1KlMmTKF+++/nzlz5gCc9mWkrAJet9xyS61g22Kz2bjqqqsAqpfvioZ58+YBVA8jt0yaNInY2FjWrl3b7EywdWU42H/s0SaVx4UQzVXhK8JpM74IpzqM+bTHSs/sF+Lm+Pa4UWn7kg59SIozLhLklUVvHurpZAU8CQFVxJPM4LjEFTz7rFTk/+9XmUXTrGW7AtlVPFX+xme4PdqNPWDd8Or+cOBtRIY7v9zIcLeLNy72XJBmVI/ekVd/Sczdxd/g8HfjvNSM6ufSnMbvuqiq/sXkU1VWIFlz0eiCdGM4+smKMzucuTWz3qfkOCPg7pfZE4Bvjv3Q7L7zyo2LX+2c7aqf65hoBN8nK87sWtzlnlJidPCkRHMC7qc/fZWBCwZSUHH2JzQkw92aRSlT3FZlZmYCcOLEiYja5+UZw8RsNhsZGRkNtDbccMMNdO3ala1bt9bKBGdlZeFyuZgwYUK9vvbs2cP48ePZtSv0sKqSktO7bIO1bNbs2bMbLBIXqnhaY23cuJGdO3eSkpLCj3/841rbOnTowM0338yyZcuYN28ezzzzTJOPYw3vD3zfray39TuOluTk5Or75eXlpKam1mtjZcED2wohhMWti0mL7QtAutPINp4oO9XsDNeZUlhp/L1qn5RGWpHx/9yJsiJ6tesUbrdWodAc+mwFPFCTjS6qM6R8X2Fk3yUCVVlzuINk+2Nw4mnCckhev4sYVT/DHascuBtRsK6gwrgoYmU9+7YzPm97Cw/XalflcVPOPi5KurnW8xlmZry4qv7Q++JKK5CsudDQyVw3vNgla3FbiupcmBjcuQ/shB35OcB1zerb+rx2SKgJuDsnG9+LCivP7AWxKn8psSr4iJ34mASUzYvb6yUupnFh5bIDS8AOy3Z+yU+HjYnGqbZaEnCLVmvo0KEsWrSIjRs3RtTeWpaqX79+OBz1rx4HY7PZuO+++5gxYwbz58/nb3/7GwALFiwA6g8nB5gwYQK7du1i3LhxPP7441x00UWkpqZit9vZs2cPffv2jWrmNNhcIGuO+tChQxkwYEDY/QPnnzeHVSxNKcUNN9xQb/vRo0cBY7TAU0891eQMtTVfO3AY/NChQ3n11VfZvHlzk/oMJSUlhYyMDAoLCzl48GDQpcYOHza+vPTo0SOqxxZCtH1+vx+frZhUh/FFOCPBGvJ5ZjNQzWEFUJnxqaSZFwzyy9tGhvtkhXGxwLrQAZCRYNw/VSdz+9Xh76vve30+Yuz2Bvt3+avQ/pigbWNt8VT5G39x3YebuIDK05YYm4PKRlS4Lqg0PmMdzKznwE7GNK9DJcdqtdtbkIuy+eieUnuYeTsr4A4SQJe4jcy9lQUHI8uv/XbKZC3uasXVAbdxYWKgWb3+WFnjL+7UdajYSDB0Sq6ZHtk1xfh/psh1Zv99uv3lJMZkBt1mFdYrrCylU3J60DahtIs9n1z/YdYe2iQBtxAt5ZZbbmH69Ons2rWLzZs3hy2YpbVm4cKFAIwbN65Rx7n//vuZMWMGixcvZubMmeTk5LBx40Y6derEjTfeWKvt999/T3Z2Nh06dGDp0qXY6/wR3rt3b6OODcZa4h6Ph7Kysur5whaPx8Px48fr7XP++caV7FGjRvHcc881+piNVVFRweuvvw5AcXExX3zxRci2hw8f5uOPP2bMmMb/55mdnc22bdsAagX1Y8eO5bHHHiM7O5utW7dGtVL54MGD+eSTT9i8eXPQgNu6kBPt6uhCiLavoKIMZfOS4TS+CLc3h/eerGgbAStAiRlwtU9KId1pZLitrHdrd8o8z/T4mhFI7RON30Gxq3ZguO1EzVSvQ8Un6ZnRcH0Yt88ddAkvAIctnnJf4wMrv3YRa6ufFIizOfE3ovhUkct47V3MIKxTcjr4nOSW1/7OsLfQCMC7Jtd+vZmJxntW6q4/1936TKTH1/5OonQ85R7JcFtKXMZ7l2a+T0b1+hhcvuYXHjxaYoxOPC+5JtBNi09E+2MocZ/Zf59eykmwXxB0mzWdo6CirNEBtx8jobS7+JvmnWAbIHO4RavVu3dvJkyYAMAvf/lLqqpC/wf2P//zP2zfvp2EhASmTZvWqONceOGFDB8+nBMnTrBq1arq7PakSZPqBdRWResuXbrU2wZULyPWGF27GpVCv//++3rbPvroo6Dz0W+66SbAWBs60vnqzfHWW29RUlJCr1690FqH/LHWK2/Kmtwul4uHHnoIgNGjR9cKcHv37l1dhG7q1Km4GliWJCcnJ+iFimBuu+02IPjvzufzkZWVBcDtt98eUX9CiDPnD6vnMnDucO56848tcvxDxcaX4kwz4O6QZGS4z/SQz+YoMwOo9okptEswgtW2EnBbQ8qtrDZApvkaigIC7pyCXD48/Fb144NFkU1PKveUYtP1528DOOzx+Jswd9WHm1hb/arncTYHfuWOuJ8S8/V1TKqZChWjMyh0135t+08Zfwu7p9WeIpCZaLxnZUEC7jIrwx1fe96uTcdT6Wv+cmtnC+t9ygi44KN0bKPWUw/F+j+kU3LtaY3GRY8zO8rAb6sgKbb+qAyomc5RFGRqQkMqvcbrqLD9wD83rWj6CbYBEnCLVm327Nl069aNzZs3c/PNN9dbV9rj8TBz5kwee+wxAF588cXqALYxrCJgc+fOZdGiRUDw4eR9+vTBZrOxfft2Pvvss1rb5s2bx5IlSxp97NGjRwPwzDPP4HbX/LHdsWMHv/rVr4LuM2TIEMaPH8/evXu54447OHLkSL02x48f54UXXqgXkI8cORKlFE899VTE52gF0Pfee2/Ydtb2d999l1OnIi8atHbtWq688kq+/PJLOnbsyMsvv1yvzaxZs+jZsydfffUV1113HdnZ9QMZHDMAACAASURBVCv4l5eX8/zzzzN06NCI5/5PmTKFTp06sWbNmnrz4Z944glycnIYPHhw9UUOIUTr4Pf7WXEoC+xl7Chd0yLncKTYqDmRmWBkdjomGbdFVW0n4C73lKP9dpId8XQw5wOfqmobAbeVxc6Mrwk6rbnGpQEB9z82v4s35hidbUaV7iPFkdU2qfSVEqNCFYtKaFKxKK3cxAXJcDvs8dCIgLvMU4r2O2rNm020t6PcW3uZ06Olxt/CC9vV/m6UHOdEa1vQjLUVhFvzvC0xKoGqMxBw+/1+th5r/UtxlnmsgLtmJICxnnrzM9wlbvNCWELt34FdJ1LhPXMBd4XHhbK5qtd7r8sKuK0Cho3h1mUk+C/E7u3IrO1/ahO/86aSIeWiVcvMzOTzzz/ntttuY82aNfTu3Zsf/ehHdO/endLSUjZs2EBhYSEOh4MXXniBn//85006zp133slvfvMb3nnnHYB6a29b2rdvzy9+8QtmzZrFqFGjuPbaa+nUqRPZ2dls376dJ598khkzZjTq2E8++SRvvvkmy5cvp2/fvgwdOpTc3Fw2b97MHXfcgd/v5+DB+lVHFyxYwLhx43jnnXdYuXIlgwYNonv37pSUlHD48GF27dqF3+/n4YcfJibgD7I1Jzw2Nvgwubr27dtXfXGhoSW/Bg4cyKBBg9i2bRuLFy+uN9rg5Zdfrl6WzO12U1BQwLfffltdDO3qq69m3rx5QedLZ2RksH79eu644w7Wr1/PJZdcwsUXX0y/fv2Ii4vj6NGjbNq0CZfLRceOHSMunJeUlERWVhY33XQT06ZNY968efTp04dt27axa9cuMjMzWbJkCUqpiPoTQpwZH+z+Gm/McfAl47cVU+FxkRAbWf2OaMktM5Yv7JxsFDaqKSzVdua5VnjLUdrIuLZPMr5Ul7SRwliBw+Et1lzj0oAsYInbuD/lkrv472+/4Hhp7aA0FJe/DEeIYlEJsQnoKhd+v79RNUu08uCw189wO+1OdCMC7kpvOTZdu5/UuEyKqw7Ueu5EeT5aK3rXKYJns9lQ/uBriVd6jeJtGQm1LzbEqQTcTajM3li/X/0vVuXOopPtSj685x9nZNWSpig3M9ztEgIz3HGNWt4tlDIr4E6sXcw1ViWekYselqPF5vJzzvpFZQGSzSXRmlJMz6PLSYvtwswRT/Orz+/ixa9eY/7tf2j6ybZirfMTLESAbt268fXXX/Pqq69y0003sX//ft58803ef/99CgsLiY+P55tvvuHhhx9u8jHqVt4Olt22vPjii7z00ksMGjSITZs2sXLlSjp27MjKlSt58MEHG33sXr168cUXXzBu3DiKior44IMPKC4u5rnnnquelx7qnD/55BMWLlzINddcQ05ODkuXLmXLli3ExMTw8MMP8+GHH+J01vxB9vl8fPfddzgcjojXy543bx5aa4YPH06vXr0abG9luYMNK//iiy9YsGABCxYsYNmyZWRnZ3PhhRfyyCOPsGHDBj777LOwx+jcuTOff/45y5cv5+6776ayspJVq1axdOlS9u3bx/XXX89LL71ETk4O3bp1C9lPXddeey1bt27l7rvv5siRIyxdupSysjIeeughvvvuO/r27RtxX0KIM2PLcWMazkVJo1BKsyuv/kif0+1EufFl1Aq4jWDvzM+xbI4qb0V14FadHXa3jQsGgcPhAykdT4WnJigpc5ejtWJgR2Me6omKgoj69+gynPbgAXdibCJKaU4FWe87FL/fD8odNOCOj41HKT/lDUyZsrj8lfUC7gxHJtpWRpWnJnAvdOWj/Ik4Y+tXRlfaSaWvfgBd4a1A++31LmA5bAl49ekNuIsqy1l11Jjal+vfwL++XnVaj9ccFV7jc5USUMXerhx4GrG8WyjGyJMYEh11fweJuPWZuyB2tMT4t5IWIuBOdRoBtzWfvTH8qpzEmGRG9hwAPidFrrZTbLKxJMMt2gS73c6kSZNqBYknT55k5MiR7Nixg+nTp7Ns2TLi4ur/QYnUokWLqoeTh2Oz2XjggQd44IEHgm4PVaE8XOXyAQMGsGzZsqDb6g6jD2S327n33nsbHOpt2bRpE8XFxTz66KP/P3vvHSZHdaZ936equqvz5KAZhVEAJBAiSLAgLViAAa+RbWyzOAAm7ILBZm2CjV9fXlhsvB9r+1sv7IfXLJ+NEMEGBwzGJJOTAAGWQAgJZWmk0eTOuarO+8ep09Ohqrp6pmeU6nddumam63TV6e7qUt3neZ77waxZs2w957bbbsNtt91maywA3HjjjbjxxhtLHuNR7XqxYsUKrFixoq77POqoo8ZVg+/g4LB/GE6xspVF7cdg464/Y9NwLxZ3V18UnIw5zGwccxIWaACx3MFz45jRUhAJEww+lwyqyQfNgkEilwDVpIq2XeW1xiklCaJ5MLuJGYeNpO31klZJCj7JuCVkwMWE+FAyWhLhtCKdz4MQCq9kHOEGgHAmWSGyjMhpaYikdD/t/jaQBMXWkX4s7GSLzrHcKFy00XAfIjzIGgjujJIGoZVz8Ih+jKgJ7I4MlZzz9WT17k2AGMf53Tfi8d2/wv0fPYivn/zp6k+sExsH9+ChD57Dj868tGpkPZ1n71PxOBHumvqpm8EyTyrb0fnEIGKqvcXFd/ZsxY0v/AjfPOFKfGnRaeOaxzt7WQvcuc3TDbc36U72tQrunKKAChkE9VR1gfqRzB8c153x4ES4HQ5aWltb8fzzz+OII47AM888g69+9auFdlkOxjz33HMIhUL4wQ8OzZQdBweHw4dwNgxKCZbOYK0Rt41OfYQ7nImAUoLpobFeuS40IKHY97DY3+S0FCSM3dgLmh/xSVww0DQN5z/8Xdzw9C8nvK/idPhiJOJBtkhwp3Xx4pdlQLMXSdM0DVRImdauhvRU2pGU/WwAHg33GAhuv0n/cDPyWhquMsE9PcjSxrkzOQAktVF4RWP3aIl4kTPoJZ5RjQW3TwoAYhznPboC8WztPcjtsDPCTN6ObpuN6fIJiGnbJ+U4ZnzzmVvx+N6f48+b1lQdm1FTAC0N9IjEDYXaLw0wI61WlgwAQKPcAk2IGbaMLed7L/4HwliL2977FiLp8aWhP7frRUD14YtHLzXczh3auYGcXfoTYRBC0SCzyLlEAkipB0dmzXhwBLfDQU1nZydeeOEF3HrrrVi4cCHWrVu3v6d0QHPLLbcgGo2ipaWl+mAHBweHA5hYLgqi+XDcNJYmvDu2dz/MIQKieUqMq3xiE9LawRPhVmgG7iLXbBcJIqlOXqTpP157BNuyz+C5wf+Z8L6YKKmMArrKao0zahIi2Gskmg8ppbqoHUrFQYiGkGxSu1owi7IvEqK64OatlIrx649FbUYKFWThEkr3w53IuTN5PJtGjvSh22fc0slFvMjTynrjnJaGgErB7dej+hBT+OLvb8C97/7V1lxrYW+MebrMaerCzFAPICaxO2LP5K4ecL+Wm9+5Ev/6/ErLsVktA6FsYcJFZKhV2rt9PNSH5asuw6Yh80XCrJqERCrPk1ZvK4igoD9hfY15e/cWDNG3QdRGEEHBhsHdluONUFQV+3J/wzTXCYYlCcCYYZxRezkr+mIsy6TZw7IvZBJAVnMEt4PDAcuMGTPwb//2b7j11luxePHi/T0dBwcHB4cpIJGPQqQBls6r+jCQ6p/6OSgxCLS0xjfkakIeB49LuULTkMUxcyyPEERWmzzB/exOVpMrKu0T3ldWTUEiRi22/MjTsQhsVkvBpYsXCT6k1eqCmzvQN8vG6djcwbs/YT+bgQtuv6Hg1iPcNmvCVZqGXCa4uRM5dyZ/6uN3QQQVJ007oeL5AOAWvFBpZaQ6p2UgkUrBHXSPnev71Ndx5/v/AaXOmYUDKSau57V2Yn4LKxF5q/fjuh7DCo2OvZ7H9/4c/XHzzzenZSrS+l2CDLVKhHvl2icxgvdw1VPm2YY5LV04Z4vpDLBU/q0j1q1P//dvrA3eiumX6eP7LEYb05+IAmIK8xrNfWx4OUUqX1vGQ198VH8++355pSDy9NBtOXdICW5CyHJCCLX5b2bR8+6rMrayQbKDg4ODg4PDfiOtxuAm7GZPpEEk8lMvclNKFK4yF+smuQVUSCBX1pLxQEUjGXjEsRt7n9iA/CSaMsVVFsFUycSPkdPShlFAr+iHirEId56m4RKYoHUJvpJ0czN4BI4LgnJO6mYiZMPwVtvzjWXZnIwEd0Bm84tn7aXmaiQLj1jaI3xeSycoJRhIMtH6yq53AQCfmX+K4T5k0QsVlRHuvJYxXMgIZ0rFpyYN4Zdr/mJrvnYZSY+AajJafEEsnnYkAOCDgS11PYYVKTUCSenCRbP/FQDw09d/Yzo2r6UhoVJwa7AW3JEsW9Aape+bmuTlaRpuobIH/PQgW6jaPmotuNeNvgqvOg9nzzsZALAraj3eiH26KG70GJdVAEBI9oJSgpRSm1j+aIi1AJvRwF5PQApBq8M14UDlkBLcAPoBrLL4t1Eftw1Ar8Hz3zB53p8mddYODg4ODg4ONZHVEvCITHBLxIesQS3qZJOjCXiEUsOsdl8rCKHYHp76iPt4oCQDrzQW4Q66GqAKk3Pjq2ka8kRvySWmbDtym6HAWJR4JT8oGROSLBrMxnmEgK1I2lCSict2v3H989Ht0wHVg22R2gW3z1UpZkO64LZrPkVJFh6pVLh7XG4QLYD+FEtV3hheD6I0Y36bseEVe58qPwMF2Yr6cAA4sXMRACCgLUCIHgsAWDdQ35hUNDcKUWMCb/H0uaBUwLbw1PVnzmpRNLq68H9O/xKgebA9utN0rEIzcAml75Nso71bf5JdGwhR8fD6lw3HqEjDY3Bu9zSxsoE98UHLY+TIELp887BA/+z3xmu/HvXzKLTXeNEJ0NvLURnpGiPcz+96DlCD+MxRbEEg5G4AFTIHzUJlrRxSLuWU0k0ALjPbTgjZoP96LzW2jP4VpfS+SZiag4ODg4ODQx1RSQJ+6QgAgJt4kdOmPh1RpdmS+mcAmBboAAaBLcP7TIXOgcKZ9/8TiJCHLI6lDzd6GkGyWcSz6Qr374myJzYCCBmISjtUaRDbwvuwqLNn3PtTaRoewV/xuN/lBxWyUFQVkihCJenCooJXDCBs4MxdzqDuQN8eMBbcgiDAg24MZnbZnm9CF9wBd6WQCumPJWyYkWXyORAhD59U+dq73SdgT/4t9MfDGFG2oM0933Q/PskLKmQqeolrNAuXUJlS/t3TLsBXFp2J6Q3NAICFK09EJFtfg8CkGoZMmMDzuWSIahMGM7VHZ8eLSuIIudjrE7UGRHPmPdsVmkVwHIJ7NDsAQWmBKkTx5NYX8U9Lzq0YU74QxpnXMg0AsC9hLrjZ+ZFF0BVCZ7AJVJMxlKq9Dn5QX3RqNcny4BAqMwM5m0TSSQxr6zDXe2bB/6JBbgBJUPQnwpPmgL8/OdQi3KYQQk4FcDQAFSxq7eDg4ODg4HAQomkaNJIstJRxCz7DWtRJnwfyFcJkZgNrPbU7euBHuIcoc2Lu9HcUHmvSTYx2R8yFxnj5W982AECHzNKxt49O7D3SSBpeqVK8Bt1BEEIxnGKpu5RkCuLU7wpCI9XFQTjNntvuNxcb7Z6ZSNG9thyjASCpRwGDcuWceT/jRL763EZ1J/OAq1KQXXnCRSBCDv/n+f8BFSM4pnmR6X58ei/xaKb0mBoUSIKxSRYX2wAgaAEk6tzKKatFEJDGFjncpAFJZWpMCOPZNCCm0exhxrIeocmy44CGTMWCm0f0gAh5y3MioQwhKHajgczHjuTfKveraaBCBn6Dz3d6qAWUihhOm38/+/S68waZXR8lrQHhXO2CeyjF3vcOk0UnjkBlZLXK0gQzdoQHQQQFC1rGFoNafewYvdH6X3cOBA4bwQ3gCv3nM5TSqbcydXBwcHBwcKgLI6kEiKCgSWY3aV7JD5VMveCmJA+3WCq4e3Sn6L741DkrjxeqyQhqR+PWMy4rPNbmY4KqN1r/+W8cYtHgRW3H6ccYGPe+uCgxivKG3CzNvz8RLUSDuXgJuoMgQg6pvHU6e0Zl2xs8leKYMys4GxBT2BuzF+VN5JgoCRkI7pAuuJO56ucxX0jwG0TKP7/gFFBNxt/CzJxuec8S0/2EdBO0wWSpaKYkD7dBhLscFwkgqdTPO0HTNChCFCH3mKj3io3IalPjz7BtlJ2Pbb5WAEBQakGWWghuIYWAq7S+WZbY+xbPmQvQPBlFk9yONs90KKRyMSGaSYEQDX5XZX93QRAgqEGEsyOm++e1100e5rDPFg7s9Z4vZjTN3vfOYLPlOJHIyNUguEf085c7/QNjgntfrPZ5HgwcFoKbEOID8CX9z19bDD2DEPJzQsg9hJDbCCHnEkIOi/fIwcHBwcHhYGG3LgZbPLrgFv3QiP0bvnphJEw6AuwmN5Y7sA2ANE0DSA6zQwtKUsc7/Sy61xerf6SJt247QxeBe6vUoVoRy6Z1URKo2NboYUJlOBnFUJK1Ggro43jf331VRHJWF9xBt3lafYefCbMdNuv1k3r0mkezi2n2+kvGWMF7fxcLFo4gCJBpJ6gYAdUknDvvRNP9cNdxLoAKkDxcJhHuYmQSRKaOrZzW7NkCImRxZNMRhcdCriYoZPJc84vZqX+O03Qn8GZPKzQhahitjmZSIEIOjWUu9l69rj5q4jY/kooDYgrt3k72XDFT4WUwkGQivNgVvhiJBCyd9gf0lmHc8K/R1YEM+mt2lI9kmeDuria44UG+Bg+N0TQ7Zxo8YwsKXUH9uxSZuvKBqeRwEZP/CCAIYBCAlZ3i1wBcD+BKAP8K4BkA6wkhx076DB0cHBwcHBxswVs2tfnZjaDfFQARslNvuEPykMXSlNI2PxN0yfyB3eKGCVZa4lAOAG0BdpM+kq5/VHEkMwKqiVg6k6WSDqXMo3TVGEiw+TXIlaKkycs+g+FUFAMJnl7Lbu6bdMflviqRtIzCFnCCcqV5GGeaLhJ6Y/ayAVJ5831yEZ5Wqi8chfWU8ka5MgIKAC0u5h3goz3wy+aR6pDMBXepaKbIwy1WF9xeKYQ8rZ/gfn77ewCAT/SMLRIw1/8UMnnruuh6sH2Utc6a3cTqpNt97SCCip0GfcB79ZKLZm9purVPF9xm7d12htkiU4evFS1edv3aGSldeBpKsAUGo3MbAES4oWjmGRrc8K9DN/xb3LEYEJN4ftv7ps8xIp6Ng1IBLT7jeXBcggeKQT93M/hiRIM8tmB09rzjQTUX3tj7dk1zPFg4XAQ3Tye/n1KaN9i+DsC3ABwDIACgC8AKAO+D1X0/TwjpnoqJOjg4ODg4OFjTl2BCrTPAblh5JGi4PFI3iaTyWRCiwSOVChq/LINqEhL5AzvCzeuAfWUtqvy6g3ZamZiDuBGxbAQCDaDR6wfVJMRz4xdrwykmuEMGorNF75E9kopiMFkqzFt0MT6Ysq4LzqlZUCrA4zIXnt0hFgntsym40wqLAjYaRLiDbg8oJYUxVkT0CGFIrtwPAMwIzgYA9ASOttxPo4e9J5HM2OegqCqIoFYsJBkRdDXWtZXTusH1oJqEM+aMxbnadNf/HeHxZ0PYZbPuhr64i0XYu4PM22DzcGUl6h49A6StTHD79YyIaNo4U4H3bW/yhtDhY9kku8oE94juH1AcAS5GIjIUi17fw2W11/+48EwAwJ8/fsX0OUbE8zEQzVdiqGeEW/BAofavF/x8ayx6fUHZiwZyFHYm19Y0x4OFQ15wE0LmAThd//NeozGU0jsopf8fpfQjSmmSUrqPUvokgJMBvAWgHcD3qxznKkLIu4SQd4eGDvy6LQcHBwcHh4OVoSSLTnaHWISRR+p41HMqiOlGUx4DYUKoB2nFvmvv/oAbZZX3hPa72evJKvWPKCaVKCTKbrIJ9dTcu7eY4SSPAlaKklYfE9zhTBzbRlmLrJ6mLn0bi+APJq0Fd1bNAdRlOWaW3kN4IGkvUs/FdMigLlwQBIC6kVWrRwqjeuuwJq+xIDu6dR4A4KRpJ1jup1F/frHgjusu6bJYvYY75G4AxEzVeni77ElugYdOh881duxpAfYdn4o2e3vivYDqw4xGJoR7Glmke9Pw7oqxvOSi3V+abs2/T7Gc8fd/SE/3bvU1oktfsNlbVr4xqi8c8oWjciRBhmohcEcz7Do4TU8FP35aDwSlBRvDH5g+x4iUkoBIzT0MOLLghWbQz92MRI6dvy2+0vN3UctJUKUBbBk+9NLKbQtuQohMCDmHEPIfhJBnCSHrCCE7CSFr9b9v17dXXxKbWnh0+01K6UbLkWVQSnMAbtf//HSVsfdQSpdQSpe0tR16dvYODg4ODg4HCkMpJrhnNrD/b7kb73By6gR3NMOEiUeqvO0RqIzMAS64Ixnd6bqsDpiLHW4aVk/SWgyy3rdcoN6aWgmVM6pHAZsMooDcWTySiWFruBcAcFznHABjUb/RahFuLQtSRXDPbmIR0JG0PaOnrJIFpWKJoCyGUDcyavUIdyzLPrsmr3Gq79UnrcC5Hd/EN0/5jOV+mnXBHS3q/R3PccFdPaWcp1P3RsZfGlBMWhtGg6uz5LHpIbaosTs6+RHukWwfZIw59p897wRQTcIru1dXjB3Q07b5oh8noEe441njc5uXarT6GjFdF9z7EqWBurC+ANLsMxbcLiJDg/mCWCTDvhtdobHFAJk0Iq3WllGSUROQiHEWRTEeyWfYz92MuO5v0VyWqj6ncQYAYMtIXw2zPDio2oebEDIHwDfB+ls3AiBlQ2bqP88GcBOACCFkJYD/oZRur99Ua4cQIoLVZQPWZmlWbNJ/OinlDg4ODg4OBwCRTASUksINJY/U8TTjqYDfUHulSvEkwouMdmALbl5HWRHh1sXgZES48zSGBhcTNBLxIDsBwR3W06pbDERJh16HHs8l9LpxF45o6dS36YI7Y32u5NUcCLW+TfbLMqB6ELbZizqjZkA0cxEvUDdyNhY6uCGf0Wvn8/p/P3V11f3wCGM0WxzhZpFKr6t6/IynU/dGh3BUW1fV8VZomgZViKBFbi95fFYjO1/6YpMvuJPaADqK+pa3+IJoIPOxPfluxVi+6De9oUxw6w70cZN+6mPO301o0z+/wbIMibAumFv18ody3IIMzaLXdzwXA9WkEod9WQggqda2MJKjicICmRVe0Qsq2L9e8NZ33O+Cwz0R9kzBZz3VmEa4CSGNhJA7AWwEMxITADwFZib2BQDLAZyo//wigJsBPK2PuwHARkLIHYQQ627pk8u5YEI5CeCRce6jRf95YBdjHaL09PSAEIKXX355f0/FEEIICClfgzp4Wbp0KQghcLvdqFYasXz58sLr5/8CgQC6urpw+umn4/rrr8fq1ZWrwmY89dRTuOSSSzBv3jwEAgF4PB5Mnz4d5513Hu6++27E4/ZXZpPJJB566CFcd911WLZsGXw+HwghWLFihe19ODg4HLhEcxEQzQu3xAQRT73kUc+pgEcCfQbCRCJe5A4SwV3eoiroYQI8p9VfcGtCEkEXuy2UiBc5OgHBrYsSI9HZ4guAUgHxXALD6X2QtJZCHWq3vkgTzVqfK3maA4F1hBsABBpEPG+vTzRrnWQeORYgI2fD7Zmn5Lb6jQW3Xdp1wcP3BwAJXXB7bKSU83Tv3ZHxt3fjsN7MKjr9pRHuOc1McA+l6xNFNyOeTUMTw+j0TS95/PjWv4MmDWHj4J6Sx8MZtsjCs2w4Ib1VW8IkpTysL/R0BpowvaEFlAoYzZQu2PAMhraA8ecrix5Qiwh3Ih8DKUsF94oBKKjt+6bQNGSheoTb5/KBELXCbd2MZD4JSgmayrwMZuolGv2Jyf2s9wdWS3fbADQB+CtY7fNjeoq1GX8CWOo5gM+DpXJ/C8BFAPZXjvU/6T8foZSOVzBfqP98pw7zcXA4YPn444/x5ptvAgDy+TweeOAB3HDDDVWft2zZMsybx+rFstkshoeH8f777+O1117DHXfcgaVLl2LVqlWFMeUMDg7iwgsvxCuvMDOPBQsW4JxzzoHb7caePXvw/PPP46mnnsLNN9+Md999F7Nmzao6py1btuDiiy+2+9IdHBwOMhL5KEQ6lo5YXLM7ZXPIcsFd2TbKLXiR1uyJsP1FXBcEwTLjLR7hzqn1FdzxbBoQMoXe6W7Bh6Qy/tZjPMpbHiUDWD000WQk83HE1UH4xbHb0JDsBdVExHJVBLeWg2AhjjluEkLKZi/qnJqFYJGmLhI38pa32gzugN9iklJuF/69KRbc/LzwmqS9FzO/jSW58rT9ifDRINvHjNC0ksfb/Q2gVEAkM7nfp60j/SCEoitQKvinBdqBEdZqa0H7mBiPZqOgmlzhAh/QW+yl8sYLJ/FcHJQSTAs2QhJFEM2HaK5UcHPDxQ6/ccxSFj2gxMgDmpFSEpDKBLfPFQStscxFJZmKLgZG+FzsWCPpGPxydcmXzqcB6q4wY+tp4p4I9W9JuL+xEtxrAfyAUlqTPzulNAvgYQAPE0JOAfDjCcxv3BBCWsGcxgGLdHJCyPEApgN4mlKqFj0ugS0YfEt/6L8maaoODgcEv/41+5p0d3dj7969uPfee20J7n/+53/GZZddVvH4Sy+9hO985ztYvXo1li5dirfeegtz5swpGROJRLBs2TJs3boVp556Ku6++24sWrSoZEw8Hscvf/lL/Pu//zvC4bAtwR0MBnHFFVdgyZIlWLx4MdauXYurr66eXufg4HBwkFbjcJGxVEdes1ucGjvZJPQINzcZK0YWfYirB7bxD4/AlfeE9rjcoJQgp5rf0I+HXWG9d7reCskj+BCD/d695SR0wd0eME67JdSLtJJEDsPolsfShAVBAKE+JKu4yKs0B5FUj3B7xRDiir0Ib07LQIC5kJWIDEWrbj6VyqdANRmSKNo6runxRBFUc5eY1yVz7PhGC0nlHNc5G5QS9MYqXbxrZVuY7WNuc2kFzrPhhgAAIABJREFUJ1s88SOen9xykb44i6q2+kpdx0O6xwH3PODE81EIWmX0l2eMJM0Edz4OUvTZSTRUkSGRyCdANcm0pZssekCEPBRVNTwH4uogvEKpmVvQFQKyGeQUpZAZVA1KsvBK1SPcQRcbM5JKYGajDcGtpiDQyutmV7CZRfxteiIcTJimlFNKP1mr2DbYx1uU0k9OZB8T4BKwvJ1NlFKrvNYeAE8AGCSEvEkI+T0h5BkAuwD8pz7me5TSZyd1tg4O+xFFUfDAAw8AYMK7sbERGzZswJo1a8a9zzPOOAOrV6/GqaeeiqGhIVxxxRUVY6699lps3boVJ598Ml588cUKsQ0w8XzTTTfhvffeQ0dHR8V2I+bOnYtf//rXuOaaa3DyySdDtuhD6uDgcPCRpXF4xDHB3epnv3MznqmARwJ5G6BiPKIPGrHv2rs/4IK70ajXL5WQr3NK+S7d9KrDzyr1PNLE3iMmSsSSOtViRHgRVYYAMY1p/tL6YpF6kVKsF2cUm4I7IDVAIfYWevI0B5GYR80lIkNF9bTctJoCofX5f41QucS8jvcKNzN2K8YvyxDUBgykJm5ytTvKFqgWtM2o2CbRAJL5yS0XGYgzkdfuLxPcegZIJF16bWGLfpVilLd8S5n0U0/l4yXp3l6hESk1XDYmCWIgSAvP0ctYjOrEM/kcsqQPXf7SAAdvn8fbklVDUVWA5OCTqruU87p17qtQjayagmBw/rKIv78i4n8ocCi3Bbtc/2nYCqyI9wHcCeBjMAO4zwD4BIAUgJUATqaU/nSyJulQX0455RQQQvD444+bjvnOd74DQgi++93vFh4bGhrCnXfeiU996lOYPXs2PB4PGhoacMopp+AXv/gFVFU13Z8R1Wq7eW36zp07K7bl83ncfffdOO2009DU1ASPx4MjjjgCN9xwg2ld9de+9jXMnz8fd911V03z5Dz11FPo7+/HnDlzcM455+ArX/kKAODee6t9fayRZRn33HMPAOCVV17Bu++OGY9s27YNv/3tbwEAd999Nzwea4OWefPmYdq0aZZjHBwcDg8UJOAXx+obuduyWRrnZMAjgQGDSKBX8oEewIJb0zTE9TTiBm/l/AmVbJl31cJevVc1N0bySf4JvUcpxVqUuIgPKcrSlGc3loo4ifiRVa1bkqk0D5FUF50N7iZQIckEShVUmrUU3G7BY9nuiZNVUxAtXnstCNRT4oyeKES47e3fQ9oQyU/c5Ko/uQ+UCpjb3FmxzS0EkNYmWXDrruOdwdLIcKOeth/Llp4vKs1DNMhWaPQywZ02uRaltSQkjInYgKsZOVoa4c6oKQjUPMPAK7Ft4UzlOfxW72YQQcH85iNLHm/ysEyQvpi96HE4nQQhtJAubgVvyxjO2FvwzGlpiCZNrSQaQlw5sMtxxkPdBPeB1g6MUrqIUkoopT+rMm4HpfQ6SulSSmk3pdRDKfVSSo+glF5BKX1vqubsMHF4avN9991nuF1VVTz00EMlYwHg2WefxXXXXYcNGzagp6cH559/Pk488USsW7cO1157Lb74xS+CUjrJswdisRjOPPNMXHPNNVi/fj1OPPFEnHfeeVAUBf/1X/+FJUuWGIr03bt34+OPP8bw8PjqXriwvvTSS0EIweWXs/Wqhx9+GOn0xG5gFy5ciOOPPx4A8NxzzxUe/8tf/gJN03DsscfihBOse4U6ODg4cDL5HDQhhia5pfCYW5JANQkZZeoENxf3QbnyxtgvBUCEPHKKMmXzqYWLH/0RXhz6XwBmvZwlKLS+KeXcCIm3UQq4AiCCaurmXI2MYpyWypEFHyCyfc9vnVW2zY8stRbcGvKQbES4m73NIERDX7y6kFFoDi4LEe8SrNs9cbJaGiKpnvJth3K3+LQe4Q4YZG4Y0ejuQAbWJqt2GEjvg6g2GaY7e4QgctrkZq+MpJngnl7W5qvRowvuXLngNs6AaNCjvWmTCHdWTcIljInYZrkVmhiDpmmFxzJqEpKFrPLrgjuaqazJfrN3AwDg77oXljze4mVlN3Yj3MN6L/DytoFGNOhZADGDBQAjclrG9PV5hBAy6tSZX04VtfThPpoQ8g1CyBFlj59GCNkEIEkI6SOEfLXus3RwsMmXv/xleDwePPnkk4bi89lnn0V/fz+WLFmCY445pvD44sWL8dZbb6G3txcvvfQSHn74Ybz00kvYsWMHjj/+eDz++OP43e9+N+nzv+qqq/D666/jggsuwI4dO/DCCy/gj3/8I7Zu3YqbbroJu3fvNqyXngiDg4N46qmnQAjBpZdeCgA46aSTsHDhQkSjUfzxj3+c8DEWL14MANiwYUPhsffee69wLAcHBwe7rB/YDUI0zGoojVoS6kZ6Am2maoWn3gblygiQX48KDSYPzBvH9cmx63q5UzAAEOpCXquv4OZtlGY1MmOkgJsJmaFxvkcZLQURFlFAcSxV/vjO0vRajxiAUsUhXaM5uITqEe52H1v42RmuHuXVaBaSheD2iF5Qi3ZPnLyWhqtOcS6JeJGnY4sePBXabzPC3eHtgiZEbTtUmxHJ98EvVEa3AcAvhaCQyRXc3D28O1Qa4ea9ouPlEW7kIRlkK7C6eMm0n3qeJiELY+dmm68NhKjYGRlbtMhpaUgWCyo+NxfclQJ348gWUEpw+uxjSh5v030uBpP2BPeonh4eclc35uOLEtGsPcGtIAO3yevzSQ3I0QPzujkR7FXNM64Dcx6fzR8ghLSA1T/zvK5OAKsIIR9RStfVbZaHKT9Z8xNsGt1UfeABxPzm+fjeyd/bb8dvbGzE+eefj4cffhi/+c1v8K1vfatkO498l4vWBQsWGO5v2rRp+OlPf4pzzjkHf/jDH/ClL31pMqYNAPjoo4/wyCOPYNasWbj//vvhLUrzE0URt99+O5555hm88sorWL9+PY499tjC9om0Tbv//vuRz+dx1llnlRiSXX755bjxxhtx7733Ttjxu62NmWiMjIy1euDp8e3t7YbPcXBwcDBi7b4tAIAFraUiilAZWXXq0rjTChMYQblSmPAUy+FUDNMbmiu272+oJoEILPpuFFEUIEGps+AezYyCUoKZet9ifiM/lIgVWj/VQk5LWoqSo1uPxb7BNwAAMxtLo5Y+KQAtX58Id2eACe7eWPUor4oc3BYinrlP2xDcNI2AWJ8GQOVu8Rn9vDYyAzSi0dMAkqC2HaqN0DQNOTKI6Z75htuD7gbQfAqaplU4W9eLaC4CqrkKKeGcZr3lYKLsfNFoHpJgfH4Q6kbWJMKtkhR8RYtBXYEOYBjYPLy38D1QkIZfaDV8PgD49TKWeLZy0SiWi4JocoW3QYdemz6cspeuPZpigjtoI8JdyALI2lsUUWkGbhP38xa5HQPKu0jls7Z8BA4WajlrlwH4kFJa7P3/NTCx/b8AGvW/RQD/UrcZOjjUiFlaeSQSwZ///Ge43e5CjXIxiqLgr3/9K374wx/immuuweWXX47LLrsMd999NwBg8+bNkzrvp59+GgCwYsWKErHNEQQBf//3fw8AhfZd9WDlypUAUEgj51x88cVwuVx4+eWXsWPHjgkdg6dKTdZ/lA4ODocPH4/sBACc0DW35HERMnJTKLgz+g11eR9r9pguuJOT66w8Xgi1jreQSUgpj2YjIJq/4Krc6GGp7MPp8b1HOS0FWTQXAxcefVbh9/L/e4KuIKiQKUnjLYeSPFxC9bZg0/XewX02BDclObhFcyHrkbwgglK1FEFDBh6hem2tHTyCD2qRWzzP3AgYLCQZPl9ioiieHf93b9voACBkMCM403B7k6cJhKgYnMTvUyIXg0Arz6dmn26Cli8Vt2xBxlgQErhN+9hrJA2/a6yMo6eRRfV3RPoLj6k0Da9F/+uA3us7ZtDrO6OkQAxqy6fptemjNr9vPMLNxbQVTXqdu1nv8XI0kobX5Lu7sG0BiKDgtZ0f2drXwUItEe4OAOVu32cDUMDah8UAPEgIuR7A0jrN77Bmf0aKD2bOPvtsdHd3Y+3atSWR4IcffhjZbBYXXHABmptLIw6bN2/G+eefj40bN5ruNxab3BSX7du3AwB+8Ytf4Be/+IXlWDPztFp566238NFHHyEUCuELX/hCybb29nZ8+tOfxuOPP46VK1fiRz/60biPw9P7i993HvUeHJy42YqDg8Phw67YblBNwtFlbsYikZGjUyi4dXHfIBu1BqotxXIqUVQVlCgwt/UEBOKCWmfBnchHIBX1Tuc38qOp8f3fqiJVkjZeztJZLFpK1MpexkF3CIRoGErF0WHSVoySPGQLccyZ1cB7B49UGVl9n16JbQtnkqbzAgCNZCDb6I9sB6/kh1Zk8MUj3CG3PUHvk7hjdm3lHIqqQtFUZFUFV/zluwAB5pdlrXCaPewz7I2OoDPYZDhmoqTUOEQDwe1zyaCahFRZD2u2IGMW4XYhZ9DeLZPPgQhZBIoE95wm5qDfGx1rI6iRtGU7Lu4bkTB4z7OasbcBT5XnqfPV4NHqRkOPh1J42n0iV/16l8nnQIUkmmTjzJ/TZh2H3+8G/rjxeXyi5xh4XNUXvQ4GahHcIQDlfu9/B2AdpbTYKWIzxvpfOzhMOYIg4Gtf+xpuv/123HffffjP/2Td3VatWgWgMp0cAC644AJs3LgRn/3sZ3HTTTdhwYIFaGhogCiK2Lx5M4466qi6mqYZrapzJ/TFixdj4cKFFduLKa4/nwjcLI0QgrPPPrti+969rC/mfffdh1tvvXXcEWper12cBr948WI88MADeOedd8a1TwcHh8OTwXQfXFprRf9Z0WYP43qRUbKglMDrqrzp5vWviXEagk0mW0f3FdLJzRAhQaX1bQuWUmNwC2PO8k16qu5IenyCWxNS8EvWYuChc58wNP9qlJmY3RcPmwtbosBtI8I9q0kvmarSO1jTNKCK4OapwpG0teCmJAufjf7IdvBLgUK0XxAEZHV3+qDHnqD36IKbu5vbQdM0nPPQ1zGkfAA32pETdwEA/m66cXlfm4+Js72xYZyEebaPUwsZNQ63SVSZUHeFISOFeQaESGTktcqa9v44S+fmLboA4Kg2JrgHkiyQoqgqqFAaBS+H+0YkcpXXl6yJIVmTLwCqyRjNVF8YAsYWC3n02opmfUz5ooQROyODIISizddiuH3ZTHYOvBm+H1/7UwS/u/Dfbc33QKcWwR0BUFhOJoQsBNAE4I2ycQKA2nooOTjUmcsuuwy33347HnroIfzkJz/Btm3b8NZbb6GzsxOf+tSnSsZu2rQJ69evR3t7Ox599FGIZTdxW7durfn4LpcL+XweiUQCgUDpxSqfz2Pfvn0Vz5kxg329zjjjDPzsZ5bm+nUhlUrhkUceAQBEo1G88Ub5V3mM3t5ePP/88zjnnHNqPs769evx/vvvA0CJqD/vvPNwww03YP369Vi7dq3jVO7g4GCLlBqGV6iMjriIByk6df1bs2oGoC7Dhcigm98QT52Jm10+7GfixqvOxeyg8eLuZES4czSGJmksK2FGg57llLAnAIoxihQasaizx/BxLvb746PAtMoxOUUBISrcYvUa0qDsBVQPwlnrcy+dz4MQrRDFNoK3e4qkzSOFqXwWRFBstWuyQ8AdBElpiGZSaPIFChHuoE2Xcq9eZ5usQXDfsfoxDNG3ARHIYReg+nHjcT/GSdONxTSvox5JTV5KeZ4m0CB2G25jvcrLBDdR4BJNBDfcUAwEN3eyb/aMLaY0ev2A6sVwmgnu3dFhEELR4jX3fuDZB0mD1mN5C8M1SWtAJGevmw2PcLf4qke4PS63YRaAEdtHBwAAnX7jen+3JKGBHosINuCK479oa64HA7WEq9YCOIUQskj/+18AUAAvlY2bC6BSTTg4TCFHHnkkTj31VAwMDOCZZ54pRLcvvvjiCkE9OsougF1dXRXbABTaiNVCdze7aG/aVGl699e//hWKQX3WP/zDPwAAHnvsMcPt9eYPf/gDYrEY5s6dC0qp6T/er3w8Pbmz2Sy+/vWvAwDOOuusElE9b968ggndNddcg2wVh9Nt27YZLlQ4ODgcXig0CY9BKrFb8EKz0cO4XuS0LAg1TikN6oZFSYMI1P5ma3gPAODWZTfjkX/8seEYibigob6CWyVx+KUxoTFP77c8kKq9nSWv5W2QQ1VGGsMXRGImadBx/XPj9cnVEGgQvamN6I+bi27eM1m2EPG8BVN5z+dihnVXd7+rPhHuoG5eN5Bk0decmgWloqGZnhHc2IrXftvh1T1vgmoyXvziG5jtPhv/dtJ/4rLFnzQdP2bKNXkLWApJwu8yPp9EyMhpZd9lopga4ElEhmJwLRrU3+Mmb2n2gkgbEM2xhaddEVZmx6P6RjR4za8vCk3DLRgLblloRFKxtyjJ08Nbffa+Y4TKttoy9kaZ4O5uMDfMfeLCe7DmojX41JEn2jr2wUAtgvsusIj4O4SQ3QD+GUAvgKf5AEJIE4BFAD6o5yQdHMYDNwG799578eCDDwIwTic/4ogjIAgCPvzwQ7z66qsl21auXInf/va3NR/7rLOYWcuPfvQj5HJjaXkbNmzAv/yLsafgiSeeiPPPPx9bt27FhRdeiD179lSM2bdvH+64444KQb58+XIQQnDrrbfaniMX0JdcconlOL79scceQzhsP3r08ssvY+nSpXjzzTfR0dGBX/3qVxVj7rrrLsyZMwdvv/02zjzzTKxfv75iTDKZxM9//nMsXrwYAwMDto/v4OAwOfxxw2osX3UZUvmpE7fFqCQNr1QpuGXRA41MoeBWLQS3Hh1MmTgV70/64uyG/oiWLtMxInFBo/Vb+M0pCqiQRqM8Vn9ba4prMX0xtlDe6Bmf4OamU0Y1sAAQzzDhYCWOizl3+peRE3fhX1+8x3QMr3H2WrTbCujO4Ebtnji8jZod92g7cPO6wQRbxMhpOaCKqV4xfn6u1yC4+9M74KFdaAuE8Oev/BwXHLvMcnyD3roubqNGeDywNO4kGtyV9f4AIBJPSU12Jp8DIRpkkwi3JMhQDPqpD+kLRa2+UsHtFZqQVNn91W5dcHcHzR3fG/X3I2UgcFVkWA96A4JSC7I2s4CSuklcs42UcsA4C8CIvjiL5Pc0mncmaPIFDimHcqCGlHJK6ROEkG8BuAVAF4D3AFxJaUnO0Vf1fb5cz0k6OIyHL33pS/j2t7+NP/3pTwBQ0Xub09bWhm984xu46667cMYZZ+ATn/gEOjs7sX79enz44Yf4/ve/j9tvv72mY3//+9/H73//ezzxxBM46qijsHjxYvT39+Odd97BhRdeCE3TsGvXrornrVq1Cp/97Gfxpz/9CU8//TSOO+44zJo1C7FYDL29vdi4cSM0TcPVV18NqWj1mdeEuwxqCY3Yvn17YXGhWsuvY489Fscddxzef/99PPTQQ7j22mtLtv/qV78qtCXL5XIYGRnBunXrCmZop512GlauXImenp6KfTc3N+P111/HhRdeiNdffx2LFi3C0Ucfjfnz58PtdmPv3r1Ys2YNstksOjo6KszurPj85z9fiIhzk7k33ngDp5xySmHMzTffjPPOO8/2Ph0cHIAfvn0TqBjF272bccacY6s/oc5QkobfZSS4vaCYOsGdUuOQiPHNKBcIRimf+5vh9BAoFTC7yTzCJAnuuka4e/U02WZP6TVc1EKI5WsvAxhIsEhhi9dYIFXDqgaWPc7Eld0I90/PvQpP3/trDKbMF4UL+7QQ8VxExy1KEXi7pvFG98tp0gX3UIoLbvOFJCO4X0EtKeVJuhcz5CW2xzfW6IJdK33xURCiocljfI8hEQ/yRYKbO7LLJueHi8iG2TYjaXbe8hZdnIDUjIEcM+3dl2AZH90hc8HNry/lzukAQEkGHsk4wt0kt6JfecdWe7WUkgTVXLZNy0R4kLMhuHlGy9xm457rhyo1OSBRSu+ilLYDkCmlJ1NK3y8b8huwOu9f12uCDg7jpdx52yi6zbnzzjtxzz334LjjjsOaNWvw9NNPo6OjA08//TSuuuqqmo89d+5cvPHGG/jsZz+LSCSCJ598EtFoFD/72c9w//33W875hRdewP3334/TTz8d27Ztw6OPPor33nsPkiTh6quvxrPPPguPZ2yFXFVVfPDBB5Bl2Xa/7JUrV4JSilNPPRVz586tOp5HuY3Syt944w2sWrUKq1atwuOPP47169fjyCOPxHXXXYfVq1fj1VdftTzGtGnT8Nprr+GJJ57AV7/6VaTTaTzzzDN49NFHsX37dnzyk5/EPffcg23btmHmTOOWIUasXbsWb7/9Nt5+++2CA3wkEik89vbbb9fN7d3B4XCC6kJs83BvlZH1J5pJgQgKggapnx7RAyrU1+jLiowah0yM6xvHbogPPME9mhmBoAUrTOeKkYgLFPWLcPM02XZ/qVGSTEK2U1yL4am5bf7xCW7eyi1pEpXlqcs+i2h0OSINIJE3rzHm4t4qws1LEawcv3m7Jn6OTZRmPdrK66OtMjeM4ILbbjbHluF9gJjAnAb75mfNXr6ANTmCe2dYPz9NjLxcggdKUQcEXnJglgHhFmTDBSvekqsjWHreNskt0IQoNE3DYJIJ0h6LBbGg2wOoAfQlKzMhKcnCKxlHuNu8bSCCgr2x6t+5tJICofajzCKRDZ3ZyxlJj4BqEtr95qaAhyK1mKYVoJQamqJRSsMAps6xxOGQZ+fOnRN6/oMPPlhIJ7dCEARceeWVuPLKKw23mzmUWzmXL1y4EI8//rjhNqvXJYoiLrnkkqqp3pw1a9YgGo3i+uuvx6xZs2w957bbbsNtt91maywA3HjjjbjxxhtLHuNR7XqxYsUKrFhRvwYHEz13HBwcjKFEBQGwZXT3lB97n246ZBTd87l8IERDMpuFX578dMQ8jSMo9Rhua9AdnrkB1YFEXAnDBeubXUlwgZJ6RrjZ4ua0QKmg8YmNiCp7a94fjxSOV3AHC6ZTxgIuWWOEGwBcJIiUau64ntCjoj4L0zTeYi5hISwjGSa4eWR6orTohmSjult8Rk1ChP2FBr+eBm/3XH9j1wYAwKKOI20fgztlp23UCI+HXr2HemfAWHDLghexouwZvnhilq3gFmVQUrn4F82y93haoDSS3uZrA0mr2B0ZxnCayaiZjeYRbkEQECAzMJjdUfJ4MpsFEVT4TRzsu4IdwCiwZWQvZjQav1ZOVk1DqEFwu4gHeRttGSPZUQhaaNxdbw5WDq9X6+BwCPLcc88hFArhBz/4wf6eioODwyGMpmk4/+HvggjsxnNPvHahNFF4W51GA7HBHZ7H22aqVlSSQMBlLFz9LhmUEls1jVNNWovAK1gLVdbuqH4RbrM02aC7CQqp/fPikcJp4+zJ3OC1rjuO6anL/hoi3F4xhKxW3j13DH4sr9t8n7w216y2HACiGeYe3WSjP7Id2vRIY0zfb1qNwS3Y33dAZq8nbdPTgS/ULeow7rltBPs+CUhPUsZIX4ydn10mddOy6IVGxs4VvnjiNakzlkWPoeCO52KgVECLr7QUpSvAotlbRvoQzYYB1Ve1hrnLNwdZ0odMfuw4vEbczFBvVgNL4946Wv3andFSEGG/17tL8EK1UdKTVMJwk/qUQxxMmEa4CSH/PYH9UkrptyfwfAcHB5vccsstuOWWW/b3NBwcHA5xPhrcg23ZZwp/D6anvmsATyVu8VYKXb/eJmk0nbSMDtUDbgJmZrIkCAJA3cgcYKZp0UwKeUQQclmXErkFNyipn+AeTLLMhFmNpWmyTXILduZSSOWzNZkkmUUK7cKFrVnElKdXN/vsp736pQaE1W2m27ng9llEzTsCbAEhmjMX7pEs29Zi0z26GvyYEf09zdE4miT75Vu8RVVGtSe498TZdeOYDvvHEAQBRHMjPUkLWAN6GjfvqV6OXwqAkrFjV8uA8IgeECFfUSudyCdANG9FdHdW4zRgF7A93IdYPgyRVjcqO7plPjZnnsSbvR8XvDSGU+wzDLmNn39s5xzgA+DjkZ1V95/TUnCZmK8ZIQteRG1c79JaFAFpcq/PByJWKeXXWmyrBgXgCG4HBwcHB4dDhB3h/sLvgtKCGBmc8jkMp5jgbvVVCl3uPB1JJyZ9HntiIyCEosljHmEl1IWcQS/e/cnf/2Y5IKbR5LFOJ3WJLoCotsyV7DCaYYJ7ZkPpjXabrwWIA9tHBrCw074AM4sU2iWk10qbCW6eXl3uJm25T3cDaD5p+p7xenGrqHmbn0WW4znzc5g7ddvpj2yHdn+o5JgqiZtmbhgRLJRP2FtcGkz3A2qQ9S+vAQIZ2UkS3CNpdn7ObjJ2zg7JIZC0gkg6iUavv/BZmpUHcNOyWDbN+mzrJJU4BFopYo9p7wEAbA33IqVGbUWAT5h2FB7bC6zt21IQ3CN6fX9QNv5eLGyfAaq5sCOys+r+8zQNv2h9nSjGbpcIhcQQctkvJzhUsBLcxr2LHBwcHBwcHA47dun9U//1hP/BqvW/Q2/2vSmfAxdC7YFKwc0dnq1aKtWL3RFW89nqsxLcbuRsRv3qhaZp+P2Hb+AfFy6rEH2apgEirz21TpV2C24QQpFR8/CV9Rp+dMObmN3UiRO6ZtueVyQbAVRPRW19q5dFqPfFR2sS3JFsGETzj3sxwOeSQamIrEndMU+vbq+hRrzZ0wySUjGYjKLTINU9zUWaRUq5x+UG1dxI5s0FdzLPzu82f30i3G5JAtVkJPOJsfZtbvup+n49MyFr81yP5gYhw76Q4xDqRladnIyRcDYMqsmmiwCNMluA2BsbLRHcZgZ4Xl2Ic4HOyapJSKTyGMe0zwClInbHepHRwmhxVU+37+TZENmxbIhwFUM9SRTh1jowkKlueKnSNDw1RLi9kg+0iuBm51cCjfL4MlMOZkwFN6X0F1M5EQcHBwcHB4cDF96/eU7zNLR6O7A7n5gygzIOr93lN5vFcOfpSGbyI9x748P6PMyFgwC3LdfeerIYjjK0AAAgAElEQVRq7Qv4+Yc3YG3/t3BsxxG46LjlhW3RzFhd8LdP+bLlftx6f+FktjLV+9/eZZ073rtoLdySPe/deD4CgVZGZHla9KCeuWCXcG4AMlprek45RHMhYyLgeHp1R8B+pLfFy87JneFBY8Gti/uAheAGAIF6kVLMF42S+SQoFWuOEFsf04OUkhhr3+a1L4g8LjcoFWwvLqW0YTS57C+ucMSy1lz1JJ6PQNTMsyX4Z9sXG8ExHTOQyrHX6nMbX/u4u304k0RP0eN5moFEKj9/tyRBVJsxmN4LVYig2VM95ZrX3keLsiHCvL7fwlCv0dWFkbx56QNHIxl4TNzOjfBKPhAhB0VVTTsg7IoMgRCKVu/EvrsHI45pmoODg4ODg0NVeJ3jvOZOdAU6QAjFpuHKtjSTSaF210DQBOXqPYzrxYDull7uul2MSFxQtKlrUwYA7+5jDtBP7vtv/Md7/4dFtXUGk+y9O6v9aizq7LHcDxfccZM+1QCw+KET8Mzmv9maV0qJwm3QQo2XBowkzdtpGe5PG0ZIMm+bZA/zBRGeXt1aQ510h5+J1D3RYcPtGd1UjPcAN0OgHmRU80WjtJIC0eq7yCVSP1JqYqx9m6/GCCR1IatWP9c1TYMihNEsG6duWyFBtuWCPR4SyghkYp7NwDMdBpLMQTxdpTyAd1EYSZUaAio0C5eB4AYAv9iBkfx2ECGPDl/196ddXwyKZ8fOlcHECADrUogu/0yo4ijiWev0fEoy8Jm4nRvBX/O2UfNe9Nv1sqRO/+FXwz0uwU0IkQkhpxBCPkMIObHek3JwcHBwcHA4sBjNjIBqMpp8Acxq7AYAbJ5iwR3Px0A1sSRNk9PkYREqqx7G9WIwxW5spzeY3ziKkJGnU5tSviu2s2gCSWwcGnMj5jf/QRMH42JkXXDzSB5HUUu7wv7uo2dtzSujxeARK8Vrh14aMJqxL7gVVYUqjqLN22n7OUYI1GUalU3mE6CabDuCDwAzGphI+tGa75dkE3B4NL1ahFsiPmRV83M4o6RAqH33dDu4hQCyWrzQvs0qc8MIQl3I21hc2hMbsS0oy5HKemHXkxTtR7O723R7u58t8A0mmODmPcfNBHej7iA/nCo9r1WagVswfk6L3AkqsYW8GaFpVeccdHtAqYhEfiylfE3/u4DmwbKeBabPm90wC4RQfNC/03RMPJsGERQEXPY9EpZMOwYA8Pw281Kj3fqCzvSQI7gtIYT4dPfyUQBvAHgMReZqhJCrCCGbCSGL6ztNBwcHBwcHh/1JNDcKUWOi6YhmdnO6PTw5rcF+/PJvcMb9l2PnaKkx22CqD6JmHH1r1Hv1JnKTX8Md1gViV8g8EigRGcoUC+6hbGlv9Fd3rS/8PpJiN+YhE0OlYvwulq4czZa+l8NlEbvt0Y9tzUshMQSlygjitCB7/8IZ+63BNg3tBSEqpgfNBZIdBMimEe60moRAa0vZ/vSRS9CEE0GlMNb2ba/YnlGYIA3KVerniQ85ah59zGjpmvpk28EjBJDTkqbt26pBqGQrpbwvxgQlT9GuBTeRoU7C96k/HgbEOGYEe0zH8POU98jmPcf9Josn5b3NORrJQRaNz6vpgRmF3+c1Ta86b+bc7ikpP9iTfh9NwgJLx/+eRibmtwybX7sHE+z6FjBxOzfiU0cuAaUEa/o+MB3Dy5JmNda+4HKwY1twE0I8AF4E8E0AOQCvASBlw14CMA/AF+o1QQcHBwcHB4f9T1INQyYsVfHodnZzuCfeb/WUcfHqjg14ZNftGKbv4rFNq0u2hZVdaJJmGT6v0MM4P/kR7pR+jBav+Q2pJLihIT/pcykmRUtbtb0/sLHweyTDBLdRD/NyeKp3vx7R4wzqqd//0Pkv6BSWYUTdXJK2bkQ8mwbEuGFEujPIjhPN2o9wrx/YAQCY2zSjykhrROJGnhpHZdNKEmKNUWS3JOErC74EAOhPjFZs56ZiQbd1SrkseqFQ83M4r6UNjbcmgk8KQSVJDKWM27dVg8Bl+l4Ww8+nZoO2ftVwCx6oqH+Jxlu9bNHoyGZzE0C+sBbRF4Z4z/GAyeIJL0Xg3zkORdZUcJ/Rc3Lh9/lt9s5tgXqQUdi58kH/TmjSCI5vPcnyOXOauwAAu2Pm127ez9usvZgRHYEGSGoHtsc3mY7hZUlzmqtH8A81aolwXw/gZACPAuihlC4vH0Ap3QJgK4Cz6jI7BwcHBwcHhwOCrBaFT2QCqTPQCKrJGEia1+uNl3vXPVb4fTA5Uvh9KBGDKg6jJzTP8HnNeouoVH5yWgcVk1JSoJpsag4EAC5hciJyZnz32f8FxAQkhd1QQ/Vie3RrYTu/+eep91a06Sm0A2XCcVivA2+QAzii8ShAjGN3xLhmmbNhgEXdpwcrb7J9LhlUcyNu0Xe6nM0jbH8L2owXXuwiErfp55PVkpCIfcMoTkdZ6nExGTUDSgm8LpflPjxiACoxP4fzNA2XUF/BHXSFoJEkBpNDoJSY9qM2Q4A9vwIu5Gppt8aRJW9VF+zx8MEA+44s7jJvVdUZaASlAiL6whDvOR5wG38OrX4TwS3kTDsEXHDM0sLvR7Z22Zq7CC8yGhPcW0fYYtu8JmtDugVtLHq+12KxdEj/nttZnCumzT0HUWUnALZw+r1n/3+ctuqSwqLccGYYVBPRFbTv/n+oUIvg/jKAAQCXUkqtliJ3AZhYno+Dg4ODg4PDAYVKYmhws0iPIAiQtAaEc/Xvxf3B6OtwqeymcDg9Jvhe2vEBCKFY1GZcn9gg+0ApQVqZ/Ah3WkmCUGvjKrfgASVTY5q2aWgPnu77JYJ0IV78yh+x/tL1CJI5GM7tKozh6eHNNvo3dwb0FNoy93CeUt7oCRbSgsuj4OVsHGICea5Jmixz5bbvLN+XYIs8XDiMFxeRoZhEZfM0DXcNLZE4XXrq8VCq8j3JqTmASlVbmfkkPygxr1VWaAaySR3weAnJIRBBwb7UHhAtaJmSbIRIXFBo9WyOkTQ7n9pqaLfG8YiTI7i3hXeBUoLF3cYLeQBP3/YinmfyZyxbwVhwd+hdFIr7qSezWRCiwucyPq8EQcCnO7+FTmGpbe8Al+BFThfc3NCt3aCDQzGdwSZQTcZQash0DE+Fb/bW1nqu09cNTYzigbUv4puvfhlP9f83IliHB9a9BACIZEchaKFxt/M7mKnlFc8D8DalFnkujCEAh181vIODg4ODwyEKSwtOo8kzVrPsJiGkVfuRSTvkFAU5YR/mBU4E1SREMmOCb90+lvq5dOYxhs+VRBGgLqSVyY9wZ7VM1ZRjt+AGnaKU8n9/9V6AaPjZGbegSY/0d/lnI0f2IZNnojKmuxk323De7g4x06xyM7OwfiPe4msopAUPJKxbevE6/6NM0mRF6kO6BsE9khkB1Vxo99ceJS3GJcjQTCLcCk1BHofg7g6xdkejmcr3JKdmQah1dBsA/K4AiJArfG7laCQzrrlZwftMj+R2wY3a66tZtkD1xSV+/nQGa+/D7BG9IIKCnKLU/FwrorkIiOZBg6eae7yvsDDE+7eb1eO3eAOglCBRJLhH0+x3r2SenfCTc6/Ec5f8r+25u4kPeb3efyjJFif5YpkVbLHUXHCH9ch8rYJ7Zmg6CKH49Qf3lzz+4IbfAQASSgRuUp/+8QcbtQhuFUD1KwWLbk++Y4mDg4ODg4MJmqZhw0Dv/p7GIQNv9dLuG1tPlwU/clp9/7tfP7ALRFDR0zALAg0gmhuLFO5NsBTIYzt6TJ9PqBsZdQoEt5qCSKyjgLI0uRHujYN7cO6D38BzW9ZhY/Rd+LR5WDZrLPo/v/lIEEHBW72bAYyZydlpddXdwGtWS4UjvxFv8YYKacHlUfBy9sT7AADHtBunurqIH1GlH9st2gkVE80y876JRslcRDatCVZJGt4aWiJxpgUbQSkxrEnPazkQG7fRQb1udtCkVRqtsT+yHXi2giL1wS/W5lAOACLcptkCxURz5m39quHXa99H0/Vd5Evl4yA2DPJcJIC0wo6dUTKgVIDH5TYcK4kiCJWRzI9dH/l3J2CjS4BdZNEHVY+D8uwBvlhmhUdoQjjfi3Mf/AbuffevFduj+lx5arxd5rf2sLmgyKlc9aJfW42FK09AnHwIr3D4pZMDtQnuLQCOJ4SYXi0IISEAiwBsmOjEHBwcHBwcxoOmafjEA5fiy898GhsHp7Zt1aHK9lFWHzgtMCa4vWIACuqbvr1uH6unnN/SAwlBJJUx0TGcGQTUAPyyudAVqIycOjmtg4rJ0+rGVZMVkeNc9MSV6FNfw02vfg8Zsgddvrkl2/+um2UCvNm7Aat3bcJbQ88BAFp91Wu4WW21jFi21GU5ltH7U/sbCmnBIylrw7PBdD+gBgxbuQGAW/BBkfbic499Hr99/xX8Yf0blvtLKGG4ycSi2wDgFs0XRFgPYvuGURxJFFnqca7SdT2v5UFo9VThBpml/HOn6GI0TQMl2Zr6I9uhvSjFu8ndWvPzRcEFzUZKeSwbB6UEbTbKGsrx66nYIyn72RB2SGtJSKi+gCELAWQpO3Y4OwJBs34NhHpKSiVG9Xn7TdLQx4NH9EHTyw8iejYKXyyzIii1QJX60ae+hkc2PVaxPZrlfehr+54d2zmn8HsLlsCtzsIn2i8CABCBXQcDrtoXWw4FahHcjwKYBuCHFmNuBRAC8IcJzMnBoQJN0/Cb3/wGn/vc59Dd3Q1ZltHc3IwlS5bg5ptvxuBg/esI6w0hBISUG/sfvCxduhSEELjdbgwNmacmAcDy5csLr5//CwQC6Orqwumnn47rr78eq1evttxHMU899RQuueQSzJs3D4FAAB6PB9OnT8d5552Hu+++G/G4/RXwZDKJhx56CNdddx2WLVsGn88HQghWrFhhex8OBxYvbPsAEawDAGwY2FVltIMd9kTZNXZmUTsXnysIamHuNB42jewEAJzQdQQ8JIiMNvZdjuaG4aLW0REBMrImrZ5qZfvoALaPDuCXa56q6Kus0AzcVQQ3FwjhTP2T/vZER5GX9kBSuqFIfSBCHkc0ldagnj57ISgVsG5wPb7+wqXIi72WUblyBM2HpFJ6LY3q5mZt/oZCnWq1HtqR3BDcMBcBCVWPbItx/D/rrsUP/3Y1Xtxm3looo0XhFSceJZNFDyipFImpfBZEyMM/zkikQP1IKJWCW6FZCDYi3C1e9tr2xCrN6HaEB0EIRYu39pRsK9r9Y/tr9dbmUA4ALmLPkT+Zj4No3nFlJ/CFiJGU/RZydsiqSbiF6p+1VwxAoey7HFdG4YL1OShSLzJF/dSj+nXATls+u/hdgUK9fywXBTSPrfr7C476HGZIyyEp3Qjn9lVs57XnHYHaBPfRRb4Kd537Q7x3xV9w8aJPlYxpkh3BXY07AWwD8D1CyF8JIVfpj08nhFxCCPkzgG8D+BjAPXWep8NhzJ49e3DyySfjoosuwl/+8hfMnDkTX/jCF7B06VLs2LEDP/7xjzF37lz87ne/299TPWz4+OOP8eabbwIA8vk8HnjgAVvPW7ZsGS699FJceuml+MxnPoNjjjkGmzZtwh133IFly5Zh2bJl2Lp1q+nzBwcHsXz5cpx33nl48MEH4Xa7cc455+D8889HT08Pnn/+eVxzzTWYM2cOdu2yJ7S2bNmCiy++GHfeeSdWr16NdHry01EdJpd1/VsKv/fFrR2UHeyxV++f2lMkuAOuAKiQgaKqdTvOruhuUE3CsR0z4ZMakKdjN9cpdbRquqtIZOS1+nyHP/v4ufjcE5/E/2z8Hm5+4dcl2xSagdukvQ/Hp/eyDtc5BRYA3trN2n1dOO/ywmNLph1dMqbB44OfzsWW+N8Akd34E2LdwqsYCX6kymr0eVp6uz+EaYWWXtavL6UOIyCaR00DYqXAW7tvi8FIhkKiCNUhSiaLHoDkKs7fwThbQAi6a4/CAixFPq1WRmEVLQ/BPEm0wHGdbOGEu2cX89EgK5OZGapvW6XifvLTg5Xt26rhEmRoNlp2pZT/y955h0lSlfv/c6o6p8mzs3mXZWGBJciSBQUUrgIXULmICIJZTPcq1/TTa+Jeuci9Kgrqc1VAVIIiikRFJKclLssSNuednZ3UOVad3x+namZ6umem0+wMs/V5nn0YuquqT3dXVZ/ved/3+yaq7m9uYwvVRqeU52USbwWCO+gKYwp1/qeMAQL6+OegSwwbmgEMWtkhkQnawlVDyB1CaAbxbJpkPoYwKzv2J485g3s/+BO6fPuTprSUI5GLI6VGxFvddzXS7G15lyohOWbeUtrFcKuyNn/1GRQzgYoFt5QyAfwTsBp4J/Az66l3ADcCZwGvAWdKKSc/n8thn6C/v5+TTjqJ559/npNPPpn169fz1FNPccstt3D33XfT3d3NlVdeSSqV4oILLuCPf/zjVA95n+BXv1KTz7lzVUOC66+/vqL9Pvaxj3HjjTdy4403csstt/DAAw/Q09PDP/7xD4488kiefPJJTjjhBDZu3Fiy7+DgIG9961t55JFHOP7441m1ahWvvvoqd9xxB7feeiuPP/44vb29XHXVVeRyOQYGxnfOtQmHw3zkIx/hpz/9Kc888ww///nPK/wUHKYrGweHa7e7k47gbgR70upz3L9teKIf8UQQQtJdJvW1VnrSO3GZrbh0nZC7CVMbjg7nxSBNE6S7uoWPQoNacQltWIi93PtC0XOmyOCbQHCHPWoS39/gFFiAVbuVID1+/iFoBZXmf/J+h5Vst7zlWPJ6bV4GHi1EdpTgThYSSNODx+WiPRBBSkGsTPq0jWma5LUBWr2zxtzm5nOv4ZT2TxQ9tjm6o+y2qXwW9CStvvon7Z3BDoSQrO8vjvDtSdmtz2oT3F4tRM4sFYUFmUNj4uyCY+cfgJSCtf0bSp7bYBnQLWmtz6F9NAd1zgNDibWDOsbuRz0WKltg4usubSRqarcG0GwL7gZHuA2Rwq9PHHWOeJqGFhgLIkqTe/zFP7cWIDfCZzqeU39HvI0rBwhZ9f7d8UFSRhy3qO7Yc4LzQI/Tlyo+X1OFJML01ZSJ8POTf8/v333f0P9rmsZDH7oer6HOq66gI7gnREq5ETgSeD/wa+BR4EngNuAS4Agp5aZGD9Jh3+Uzn/kMmzdv5uijj+a+++5j8eLiHwK3281Xv/pVfvCDHyCl5KMf/Si9vc4EezIpFApDEe1f/epXNDc3s2bNGlauXFnzMU855RSefPJJjj/+ePbs2cNHPvKRkm0++9nPsn79eo455hj+8Y9/cNhhpZPLcDjMl7/8ZZ5//nlmzRp7gjeSJUuW8Ktf/YrLLruMY445Bu849aEObw52JnYgpfp5G9lWyqF2+tK9YBQ7+Tb7lKHOrnjjPmPV/1hNGlu8LaBliGfTlkt6gnb/+E1QXJq3IYJ7e7T4PfUZrw/1kgWQIodPH1842IJ7INN4wb1hcCNSahw9dym3n/M7Llt2Zdn0z/cd9M6aX8Ovh8jJ4QWP7z/6e95I3w2o0ihVr+wjMU4P7Z3xQYSWpSs4dtR0QXMHlx39nqH/l6abnYmdZbfd2KeicR2B6o29RrNfkxKtr3QXZ0P1JJX5VK2C26+HycvSMgJD5nCJiQV32OtHN9rZmdxa8tzWqFocOGgMx/daCbi9PH7hQ3zl8B9z/vITq97f5/JXZBCYM5NVi0KbFr/6PgYbfD2ZIk3QPfF3HfGqBcYN/btBT0y46OPTAhTkcLaN3SWg2d+4lPKlraoX/WObV5M1E3hEdcfer1lFoZ/dXpxRotoe1tZ67q0LD1ILOKPwWAstwQZG+N9MVL10IaU0pZR/kFJ+REp5spTyJCnlhVLK30gpJ8cZxGGfZMOGDUNp4tdddx0+39gX/+c//3kOPfRQotEo1113XUXHP+644xBCcOedd465zb//+78jhOBLX/rS0GN79uzhmmuu4V3veheLFy/G5/PR1NTEcccdx3XXXYdRZXrlRLXdixYtQgjB5s2bS57L5/P8/Oc/56STTqKlpQWfz8fSpUv54he/OGZd9Yc+9CGWLVvGtddeW9U4be699166u7vZb7/9OP300/nABz4AVB7lHguv18v//Z+qRnnkkUd47rnnhp7bsGEDt9xyCwA///nPxz0XAPbff39mz25syp3Dm4e+7C485pyStlIOtRPLD6DLYsdau9a0O15ZNkklFGQWt1DX9+yQWjR7uXszr+9Rkb054wg3AK/mx6R+wf3M9teH/pZSBz3Bfz5ysxqjYSC0iY2r7BTYRgsEgJ3JbbiMdoJeL0vbZ/PpY8t7Trxr6Vtqfo2AK4whhoXjXZvuAkBow5+vkH5ShbFr1F/ZvRmABZG5477Wge1zAJjnOhmX2Upfprxj+fp+JcTnhKqvMx7NAe1KtK7rLzZW7LXcwduqbIlkMzL1eCQGefQKUsoBIvocBvKlUf5diV1IqbGktfq074lo8gW46IhTaopq+vVARQaBeZnCV0H6djlaLcEdyzXuesrkcwgtS6gCwd3qU/e7p7a+CkBXcPxzcKShGUDCinA3+xoX4T7vkBORUvCPLU+Rlwn8enWLRMs7ldHi71bfU/R4xkzVnIkwFmcsPhuAY+Yua+hx3yxUfFUJIRZO5kAcHEZz9913Y5omhxxyCEcfffS42woh+NCHPgTAX/7yl4qOf+mllwJw4403ln3eMAx+97vfFW0L8Ne//pV/+7d/Y82aNSxatIhzzz2XI488kpdeeonPfvazvO9970NKWdEY6iEWi3Hqqady2WWXsXr1ao488kjOPPNMCoUCP/zhDznqqKPKivStW7fyxhtv1JwJYAvrSy65BCEEH/6wqiG89dZb665/Xr58OUcccQQADzzwwNDj9rlw6KGH8pa31D6BdNg3SBh7COmdJW2lHGonWRjEqxVHUNusPsx7ko0U3BncmkrVPnzWAQA8v2Mta/uUKJrfPP5Cmlf3YVaQ2joRq6362Q5xLB9d+i28xmJ+v/l/iWZS9KVtt+HxJ6RN1sQ6OgmCO270ECxT+zwaTdNoRt1TP3vQVdz6rnsrfo2Aa9iQCRiqm17qPWPoMRcBMmXqlW3W9qp09qUTpEBrmsbTFzzHXRf8iIDWTsIov2C8tldFfQ9oK99irBoO61oEwJZYseAean1WpUOzTdAdRGrZoowIAFPmK4pwA8wKzCev7S6pL+/L9KAZzUW1stMB269govrqgkjgd9WWOWC3qIplG2dC2B23sxkmXlxpCyjB/VLPGwDMC4+fRed3BcsK7tYaHNrHoivcgs9cwKrE7RiuHgJVfrbvPmAFTfIwXkr8nie3DC8y5swULhrnpg7wjZMv5MkLVnLCQkdwT8QGIcTfhRAXCTGBNaeDQwN4/nnVx++YY46paHtblK9ataqiKPMFF1yAz+fjnnvuKSs+//rXv9Ld3c1RRx3FIYccMvT4ihUrePrpp9m2bRsPPfQQt956Kw899BCbNm3iiCOO4M4779wrBm6f+MQnePzxxznvvPPYtGkTDz74IH/84x9Zv349X/7yl9m6dWvRQkEj6Onp4d5770UIwSWXXAKoz3358uVEo9GG1NCvWLECgDVrhrsL2ufCRAsvDm9OHtq4mk/+5X9KJqi1UtD66PDNLmkr5VA7ORklOMokqNNyqe5LN+4zNsnitQT38QvUxOy1vg1sHlCRzf1b5oy7v1erLLV1ItYPbEJKwV3vv44vvPU9/POif0FoBV7YuYH+VGX9dFt8KsKdyDa2dRpAjkEi7spqIW9/37X8y4Kv8PGj3sUhsypPRVZtzfJDoi9dSKIXOrnjgquGtnFrAbLm2O9vc9TqwT1r4phN0OvFpeu0eDvJ6lu4Y81TJdtsiipxfMTs/Uqeq5Y5kVYwfXQnu4seH8yoGuGOYG2CO+QJI4RZ4mxvksetVSa4F4TnIbQC6/p28edXnx6qsY0VevGJ6efyPGwQOLYYjmZSoMfp8FdW7jUau398It+4BazuhFosbPFNLLhnBdXnvmFQLcYtbhl/8S/oDiG07FDUP1WwBHcDU8oBju44FWl6EYVW3jr3+Kr29bhcfHi5Clat6xvOqMjLNB6t8VIvXKUJ20yimiWyOHAqcApwnRDiD8CvpZSPTcrIHOj+3vfIvvb6xBtOI7wHLaPr//2/hhzLTomutBbX3s4wDPr7++noGL/Wr7m5mXPPPZdbb72Vm2++mc9//vNFz9uR79Gi9aCDDip7vNmzZ/P973+f008/ndtvv533v//9FY27Fl599VVuu+02Fi5cyE033YTfP3wT03WdK6+8kvvvv59HHnmE1atXc+ihhw49//DDD9f8ujfddBP5fJ53vOMdLFw4PIH68Ic/zOWXX87111/PRRddVPPxgaHvra+vb+gx+1zo7Kw/jdBh+vHjlb9hffY+NvR/kKXt9ZUCJLOqpU+ztxlfKkLGbKzBzr6KocWIeIpbEc0KWX2Y041L2zdFVrlHo2p7MUJsiW1CWHXDyyaoXfW5/CBymKZZU2qsTW+6B82MDPX8PqRjP27fpvqEHzXnQGDi9j52rWYs19i2YJl8DqnFaavQOGxWqIlvnlL9fXmkiOoIRciaqZLe414tRLzQXW53ALqTKgV6aVvl1/XhHYezdedD/Ocz3+W9h9xX9Nyu5C4wfcyNNEZ0usxW+rKjBHd2uPVZLYRtI6vEIC0jep5LkcdVoeBe3DwPeuCXL9zF33b/FNdTs/nhKT8gKXcy213qXzLVDPkVpMcWw69YLRrnh8dfNBuLtkAIKQXJfAMj3Lbg9k/8XXeF1f2vJ7MFNNi/bfz3YZ8HPckY85paSeWTNTl/T8TP/vmLwBdr3r8rrPwQepLDvhUFmcar1/Y9OZSnml+jLuADwF+BAPAR4GEhxHohxDeclHOHqWZkGndhgjoim7HSygcHB/nLX/6Cx+MZqlEeSaFQ4G9/+xvf+c53uOyyy/jwhz/MpZdeOuRwvXbt2treRHfexP4AACAASURBVIXcd5+ahJx11llFYttG0zROPFEZn9jtuxrBDTfcADCURm5z0UUX4Xa7efjhh9m0qT7fRDvKWc9k2eHNxe60ShN90qqNq4e+tBLYfpefoKuJvGx8S6Z9jcF0ErQMbb5io6q5ViuhidpCVYMUWfyu4VRtP130ZnewO7UbabonFFoBtx8hJLFsfeUticIgLoajXsfMV+nt6/o3D6XN2iJjLOxIViLf2Aj3hv7dCCGZNUENab0Eh9KElYjKmSnco+o6g64IBTH2otZAth/NDOPS9Ypf93unfZQu7QTylGZO9GW7cZltDft9COptJI2+osfilrlVV7i2Xt+22dqeZPH4JXk8FQruZe1qSv3XXb8AoODaxece+wDocY7oPLKmcU0mds/5wXF6zr/ao+7z+7fWZvimaRpCehsquO3vqL2C8oHZYXXvSckdSCkmrKNv8hSfB72ZPWhGZNrNbeZG1MLdntRwaZApMvj1xtWaO1QR4ZZSZlFu5LcJIbqAi1HO5AcD3wG+LYR4GNUi7I9SSqeZbZ00KlL8ZqW9Xd0Edu8ub54ymp4e1SdW0zRaW1sn2Fpx2mmnMXfuXF588cWiSPCtt95KNpvlvPPOKznW2rVrOffcc3nttdfGPG4sNrlRNbtt1nXXXTehSdxY5mnV8vTTT/Pqq68SiUR473vfW/RcZ2cnZ5xxBnfeeSc33HAD3/3ud2t+HTu9f+Tnbke97e/YYWaRMHeABqt2r0V1mqydPqsFU8gTIORuYleh8fWz+xrr+5Qz8qxAcdZQJW2hqiFXKCC0fFG7rS7/YjZmHmVPJoRuNk84WQ1YYr0vFafZX/uEMWNG8Y2oWVfRdj/bElvZnVSp7q0TmGq1WbWayVxjBbed+llLv+RqCNgiykoTLsgUQb3493BOcB7bCw+zOxEt65Iez/cXLVxUSpuvk11GsiRTIVHoIeRq3EJD0NVMLFtcw53Ix5Gmq+b01xaf+t57R7WvkiKPR6+sC8Zhs1VHFqHlme86mUsOPZ//fPHTAJx1wFtrGtdkEvGqc2U8v4INA0pwL59VfdsxGyG9ZAqNu57W9m8GhkXneMyNWAuOegphRCaso49YJSW2CV8034NP1O+u32gWNqn33p8ZFtxSpCc0hXSojpqWWaSU3VLKq6WUy4GjgJ8Cg6iU818DY+cXTTJCiBuFEHKcf2VztIUQmhDiM0KI54QQCSFEVAjxmBCiNLzpsFewa3mffvrpira321ItW7as4tZOmqYNma2NjHL/+te/BkrTyQHOO+88XnvtNc4++2wef/xx+vr6KBQKSCl54w1lptFI07Ryda12jfqKFSu45JJLxv03sv68HmyzNCEEp512GieeeGLRv1WrVgHqc6ynFteu1x6ZBm+fC88++2zNx3WYnuxJxJAulZJs18bVw8CI6GOTtwmhZVXvXoea2TygFj1nh4snpaotlH/ctlDVMGBFx0aakZ21/2kILcsAL+LTJk4jDlkicbzU1krIyTghvVhAeplFb2YHL3arxdYTF45/b414/UgpxnTxvvH5v0/o6lyOTQNqAWSiGtJ6CVnfw6AV8TVEpqQV2tLWRQCs3FY+qyttRvFr1UeKW3wtCGHSMyJKrHp699HmbdxCQ8gdKer1DpDMJ2puiQTQYi3E9I0Q3KZpgijg0Ss0TRuxeHHKgrfx/sNOAkMtAJy4sHxZ21TSZInL8QzNtsd3IqWoykdgNJr0jesZUC2P7LgPvdDJ2xdNPE8Ke/1IU80tPUwcER9eeFHncMbsI+wev9RxKmjyBZCmi2hWjVOVZRUITuBR4VAdddscSilfAF4QQlwOfB/4PNBYR4DaeAIoN3vbNfoBIYQO3AGcDcSAvwFeVKjlZiHE8VLKz4/ez2FyOeuss7j88st57bXXePbZZ8c1zJJSctNNNwFw9tlnV/U6l156KVdeeSW/+93vuOqqq9iwYQNPP/00XV1dvOtd7yra9vXXX2f16tV0dnZyxx13oI9Kk1u/vnrB4Ha7yefzJBIJQqHiSyefz7NrV8kpy/z56gfrlFNO4eqrr676NasllUpx2223ARCNRnniiSfG3Hbbtm38/e9/5/TTT6/6dVavXj0k3E877bShx88880y++MUvsnr1al588UXHqXwG8eTW4UyRnsy2uo9n9zyOeIM0+5ohBjui/XXXho/F1sE9fP/xm7ns6PfWNZGczmyNKsG9oKlU6GjST6pBWQS2GZmdngrwoSPewU9Wh0BPEHJNnLkU9ChRMl5q60SYpompxYl4iwX+vMAy1mce4Nk9GYRsZknb+MLPToFN50sT/n7z4j/431e+wNbYV6qur94eVzGNpW3jt9qql7DHjlqqz9IUaQKu4t+oQ2ctgU3wSs9G/vmg0t/oPFHaXdVXHLb51We/ZaCXLiuVd3usD6FlmRNsXG1pk7cJkckRz6aHItoZI4Uma6+ztTMfbPM1dcw8Qki8FUa4R/L+Q08G4I6z76Q7PjDtUpJB3W8BYuMYBPaku9HMJgLu6j8DG5fwkTUzE29YAWt2byOtb+DY5osq/kx9cg5ZNhHQJr4X2V0c+tMxcoUChj5Ih29ys1JqQdM0NBkknlOC206BD3mmg5SbOdR91QohFgkhvgW8BnzOejhf73EbwC+llJeW+fe1Mtv+G0psvwocIKV8r5TyTOBQYDfwOSHEOXtx7A6oXsrnnXceAJ/5zGfIZMa+yf74xz/mlVdeIRAI8NnPfraq1znggAM4/vjj2b17N/fff/9QdPuiiy4qEdT9/cpUYs6cOSXPAUNtxKph7lw1aXr99dLki7/97W9l69Hf/e53A/DnP/+54nr1erj99tuJxWIsWbIEKeWY/+x+5bX05M5ms3zyk58E4B3veEeRqN5///2HTOguu+wystnxI5YbNmwou1DhMP1Y26dEtqvQRdKsPzkqmrYFd4hWn5rw7Ij1jbdLXXzuvv/mkb5f8sG7L52015hqdiVVWcri1lIDS5cIkDYaE+EuVxvtc3v4pzmqI4K7gpZK9sQ/WkfroL5UAqHlafUVT6r/65TPg9TI6ptoci2q6FhCesmapYL7rnUPAvD0zmeqHt/uZI9VQ1qb23Ol2FHLeDY51Hs86C6ehB8zV9W2rx8o9e5QCxcJmr2VlXiNpDOg9tkeHy6JWrVLvcbi5sYtbLVYvZW3R4fvERkjWWIOVw2dltnaYGb4uohn1fylGsEdNJeB4VPlDMDS9tmctPjgmsc1mdi9pRPjGAQmCoMVRYbHwyX85MtcT7WweVAtJB7YuqTifbp8yh1/tIFkOdqC9sJLnHV9uxDCYE5oehqR6TJIyrqP77EyMyKO4G4oNQluIURQCHGpEOIhVBT5m8BiYDXKKm/8hovTCCu6/WXrfy+TUg4VDEsp1wFfsf7363t7bA6qRnnBggU8++yznHHGGSV9pfP5PFdddRVf/KJyaLzmmmuGBGw12CZg119/Pb/97W+B8unkS5cuRdM0XnnlFR599NGi52644QZuueWWql/7He9QNavf/e53yeWG29msWbOGz33uc2X3OfLIIzn33HNZv349559/Ptu3by/ZZteuXfzoRz8qEeQnn3wyQgi+/e1vVzxGW0BffPHF425nP//nP/+ZgYHKe/M+/PDDnHDCCTz11FPMmjWLX/7ylyXbXHvttey3334888wznHrqqaxevbpkm2QyyQ9+8ANWrFhRce2/w9RiT9Ba3Asx9SiZfH0tnWyh1ewL0W71Td2dmJxe3NsG+9iQeQiAgr6npGfuTGFPSvkqLCmTwuwRoYalePZb9fejzci+f/onOHfu5fzXKRM78dr7RutIKd/Yr+4dHf7iestDZs3n1E71W9Hpq+x3RkgPGaNUIKyLq/KYnZnqjQIHsv0IM4jPXVl6cq002YsXmeRQand41CS8IxQBI8z2xNaS/bfH+hDCoN1fmZv6SGzn5F3xYSH8eq9yubYNxRpBm1/dI0YuyilzuDoEt5UOHssNn4MJy8TP66pccD968S08c/HjNY9jb9JSgUFgwUzXtZAB4NECFBpkEWWXHzX5Kk+d3q9JiXPDnPhe32EZsQ1m46zpUefu4ubpKbg9WoiMLbita725glZpDpVTVUq5EOIUlFHa+1BO5QLoA24GbpRSvtjwEU4+xwOdwHYp5aNlnv8D8AvgaCHEXCnljjLbOEwS7e3tPPbYY5xzzjk89NBD7L///hx77LEsXLiQeDzOk08+SX9/P16vlx/96Ed87GMfq+l13v/+9/Ov//qv/OlPfwIo6b1t09HRwac//WmuvfZaTjnlFN7+9rfT1dXF6tWreeWVV/ja177GlVdeWdVrf+1rX+MPf/gDd911FwceeCArVqygu7ubZ599lvPPPx/TNNmyZUvJfr/+9a85++yz+dOf/sR9993H4YcfzsKFC4nFYmzbto3XXnsN0zT51Kc+hWuEuYddX+12uysa38aNG4cWFyZq+XXooYdy+OGHs2rVKn73u9+VZBv88pe/HGpLlsvl6Ovr46WXXhoyQzvppJO44YYbWLRoUcmxW1tbefzxxzn//PN5/PHHOeywwzj44INZtmwZHo+HHTt2sHLlSrLZLLNmzarYOA/gPe95z1BE3DaZe+KJJzjuuOOGtvmP//gPzjzzzIqP6VAZcWtSuiC8mD2xZ1jTs40VcyuPOJQezxLw/hAFqSZFI9udNJJnd6xFaHkC5gGktLV0J6LMa6o+mjfdiWajSNM71CJrJF4tSLrQmAUNu33W6HZbmqZxxTsvregYEWvyHKvDqGyLlUI/J1xab/mjd3+GKx9t4wOHVWbupwsfuVEpsIPpJAXXLjCCGK4e3tizkwM7Kp+IJ/NRXDJc8fa1YguRRD7F7oSahJdrheahhWShtDXckNlesHrBPc92Th5x7W4abFwPbptZQXW9jhT2eZmgSa89Xb/dimzGR3gbxHPqHPBVWMMNqkeyp/7Kz71Cq2UQmCpTPmGTlxnCen0izqf5GaQxKeWDVvlRs6/ya2m/lvk81AtCTByvtNsmxnMJ1vWpBalGLhY1Er8WYbCgrq9+q9NHq3/y7zH7EhVfyUKITcAClMguAPegHMnvklJOhxTy0ZwihDgMVU++G3gceEBKOdrNyc5bLevGJKVMCSHWAEdY/xzBvZdZsGABzz33HLfccgu33XYbzz//PCtXrhyK3Pr9fp577jkOPrj2VCvbedtOCS8X3ba55pprOOyww/jZz37GypUrcbvdrFixgquvvpply5ZVLbiXLFnCE088wde//nUeffRR7rnnHvbff3+uvvpqPve5z7F4cXlHz0gkwoMPPsjNN9/Mb3/7W1544QWef/55WlpamDNnDp/61Kc455xz8PmGzV8Mw+Dll1/G6/VW3C/7hhtuQErJ8ccfz5IlEwuhiy++mFWrVnH99deXCO4nnnhiqP47EAjQ1NTEAQccwIUXXsj555/P8ccfP+6xZ8+ezWOPPcbdd9/NLbfcwlNPPcX9999PoVCgo6ODd77znZxzzjlceOGFBIOVr1q/+OKLJYsag4ODPPPMcLpno9zeHYqxIyKHtB/I8zF4bc/WhgjuVn8Yl6bKPnpTjesTPRLbkbfJ1UHKXMvuxMCMFNzJQhzNDJR9LuAK0Wc0JsI99HlWEXEazXBqa+1j2hFT1/q8SKkbtqZpfP3kCys+lgtfSQqsLUQ73YfSYz7Nk1vXVCW402Ycjzb56Z62y3silxpyWm7ylgoml/CRl8UiKJpJ8a+PfhQ0mBeu3lV8QbPaZ09qWHDvTO5Emt6G9eAG6LQE902v/J63Lz6UzmATeW0PnYFjaj5mwO1Fmu6i9lXxjDof/a7azdimMy3WdTee4DbJ4NXqjHDrPqSoLwvKJmql/FcjLD99zFms2v0q33jbRybc1u4bnsgl2BrbCcChXdNTcAfdYfoMdf+1Td7aKmiV5lA51SydLQReQbmQ/0ZKOd3783yozGOvCiEukFKOzEW11UxpCHGYrSixXXsvA4e60HWdiy66qEgk9vb2cvLJJ7NmzRouv/xy7rzzTjye2lPsfvvb3w6lk4+Hpml8/OMf5+Mf/3jZ58dyKB/PuXz58uXceeedZZ8bnUY/El3XufjiiydM9bZZuXIl0WiUL3zhCyxcWNmN/4orruCKK66oaFuAyy+/nMsvv7zoMTuq3SjOOusszjrrrIYdb7zP2GFySeVTSCk4au6B3LQR1vfXZ5xmt2BqDYQIedTkti89SYLbSl9v83WyK1Xad3emkC7EcVFeBAfdYWSuMSmetsNxPYK7xZo8j1dLOhHdCZVCv7Cl/hppt+Yjaxa3h7Jd34/sPIr7u59mdc964LQye5cnZ8Zpck1+aqrtspzMp4Ym4eXEiUf4SZrFWSSPb3kVNCXC37pwedWvPSfcjJQag9nh7Im+bDfuBvbgBphntUTqNp/g4jv/ne+d/FWEZrC0ufZFPwAhfUXu9Mm8+iwC7pkpuD0uF9J0kR6nZZcpsnj1+gS3z+VHisZ0nbDvN22ByqPuHpeLG95TWcteTdMQpuobHs/FwPANGQBONyLuZmQuRa5QGMoqqaRVmkPlVHPXOlpKeZiU8n+nudh+CeWUfggquj0HOAtYheoZ/nchxMhcIXuZeLxfZ7sQZ8xlMCHEJ6yWYs85kbC9Q3t7O3//+99ZunQp999/PxdeeOFQuyyH8jzwwANEIhG+/nXHksBhepDKp0B6OKJLrWdujdWXRJS0Iuat/hBzIip6Zbc7aTQxq13SrJASZnuSkyPsp5qsmcCjlRfBEU8EoeWJZ+sX3fHscHZCrbQ0IMK9J60E9+KW+vs9u4UXQxZH5LbF1BTq+HmHIU0vG6MbqzpmQSQIuic/+tRq1eWmC2n6rDRT23l5JB7djzEqwr01qt7jV4/4SVXRexslVoKsi62iO65Ed7yws6E9uAHmRYbr9Pt5gU89fD4Ab+k6sK7j6tJPuozg9s9QwQ1Wj+wyfgU2UmTxu8pnylSKX/cjtHxD/DLscqb2KgR3taiFlwT9uR5ccvpmP80OzUYIk7W9OxnIqN/LuZHpO943IxULbinl85M5kEYhpfyRlPInUspXpZRJKeUuKeU9wDHA06h67ZFO5cLetc7X/T8p5VFSyqM6OqZfn72ZSldXFw8++CDf/va3Wb58OS+99NJUD2la881vfpNoNEpbW9vEGzs47AVUCx4fLYEQGCF2p+pzl08XUkjThc/tweNygeEnnm+Mi/Zo7PT1BWFlJmaLkplGXibxaeVFcJNXPb4zVn8dd7KgJuu20KuFlsCwSKyV/kw/mD6afPWJAwC35sGk2LhyZ0KJ0f1aZ+OVXfSkK8/qME0TqSVp8ky+4A56vUipkc6nebFbmbsd2lWa6OfT/Zijoo47rUWFxc21t0E6bfYHyegb+cY//o+XuzdjuHo4pPWImo9XjrZA+XPtxEX1uYHrwl9kJpiyargDVZimvdkQ0kvWKF9fncnnlN+Fq77ezgGrZeBAuvYMFpuUFY3vCE5erbJOgKyRImn0EtKnrzawzdzW9GxhMBtFSo0uqwbdoTFU7cYghJgHfBRlNtYB3COl/Kb13JHAMlRd9+TMcGpESpkTQlwJ3AmcMeIpe5zj/cLbz02r9+SgmD9/Pt/61remehgODg41kDHSaFJNQl0yQjxfXzQ6baQQcnhSq8kAyfzkCGE7fX2/1jmwobjv7kyiIJIl/Zdtmq3Wa7vi/TVFMkdif55tgdonwGGPT4nEcVJbJyKeH0QzGzMJd2kepCi2uRlyfW+dRat7HrtzlTuV74wPIoRJs3fvpKYK00PaSLMx8QpuOb/sd+zTAyVpvj32e2wrdbavlB+8+zMc/qs/sCH6Oret/gcAZx9wcs3HK8dY6en1pv56RID8SMFtp5R7Zm6EW8dDdowId7/VNSDorm8RK+j2Dx2vI1RfZDqVH16cnSy8Wph+YwOmSDPPe9CkvU69LGtfCGthXf824vkowvRPy37vb2aq+jSFEBcAr6PagJ2Oqmse2QJsIfAb4NxGDbDB2I2OR6aUb7b+O15Bq930cfM42zg4ODg4VEnOTKMLJZDdIkjWrL2dE0C2kC4S3C4x3F+00djp6we2q5/BgRkouE3TRIo0IU/5ya2dYtzTgHT6ZD6OlBoRb+11npqmIaSHdKF2J+NkYRCPaEyaqUfzICkW3P2ZPjD8hL1+OvxdmHq04hTZ7VFVstbm30uCGy/RXB9JsYEDw0eV3SbgCoDIFb2H3nQv0nTTUcfiCUCLaxG98jn+su0XCKOJ0/dvbIQb4MuHXcPhofMAODJ8AT8/+fd1H9Oj+cmPaF+VyqsFieAMTinXhBtjDA/lXqu3c8jTqAh3/ff0VCGJkJP7ffz7UV/AFEmElmVWoPbFp8nGNnPbGttBMh9Hl/V9Tw6lVCy4hRBHAzehUrC/C7yD4XRsm3tR9c7nNGqADcbOox05o3vB+u/R5XYQQgQA2/Hjzdj2zMHBwWHakpeZod6sXj1IzqwvVTBrptEZnkR5RP3HHItUIYk03cxrUj8tI9sAzRSimRRCKxAZQ3B3BJXw25OsP6U8kU8gTF/9kZUxel9XStaM4dcbk7Lt1j1IUZxSHssNoEt1/HZ/G0KYbBmszPtle1RFjmeF9k5ZkCa99BXWIoTJifPLTpMIuAMIIYlmhyO6sdwAuhmp+7tcHDnA+qvAf7/1Gly6XtfxynHxW07lxnO/wYeXfIdfnfNV3rqw/kikTw9iMHwO2gtAwRkc4Ra4MGSh7HP9KTXtDnnqi3Db+w9m6r+nZ0dkV00W5x36Vj598HeRppujZpe2mp0udIVbwPDTndxF2ojhFpPfBWFfo5o74Vet7c+UUn5HSvnQ6A2klFlUFHm6nlXnW/8d2QLsKaAHmCeEeFuZff4FcAPPOj24pwdSSvJb1mHGZ6ZBkYPDvkRBpnELNQn16yGMcf0rJyZvZoYi5gAuzUtBNsbVdjTpgkpfD3v9SNNFIldfdH46siOmHGtbfOXr+TqD6vG+dP3GdMlCHK0BkRVNekt6X1dDQcQIuxtTv+jRvDAqpTxlDOLV1AJGV0g5AW/s767oeLssB/XZ4b0kuIUXqavv9qRFh5bdJuhW39lIl/5EYQB3A7IElnco87IVLedyxoEr6j7eWLh0nS+e+N6GCXq/K4gUw+egnVIe9tbvCzBd0YUbg/IR7n4rIt3srS/jIWwJ7mgDBHfGTKGL+lzTK+HTx57Fyoue4pPHnDHxxlOImzb6s7vJyQTevdB2cF+jmhruE1Gi8+EJttuOin7vdYQQdor7fVJKY8TjLpRz+eeth35oPyelNIQQVwNXAz8TQpxiu7ALIZYC/21t+l974S04VEIhTyGepZDYjv8Qx9TBweHNjCGzeHU1iQq6wpjj9HGthLzMDAl4AI/mw2RyBHfWyAxFSIT0kyzMvAj3jngfAK1jCO7ZYeVkO5ipX3BnjCQuUb8g0aldcOcKBaSWpMXbGIder+5BCJNMPjdUK5qTMVpcKoVzrtWjemt095jHuPbpu/jFmv/l4MjbWNikKtzmhfeOAZNb+JWEMnws71xQdpuIVwluO4oJkDGjhF31t1X71+PPxe/28omj3l33sfYmQXcQqWUwTRNN08gU1D0oNIMj3Dqukn7sNtGMOjfsc6VWmnxKCMaytXs02OTNNC72zvcRcE9/s7yQ3kmssB2TAm16+WvdoXaqiXA3M36v6pHHnDwHgvFZBNwF9AghnhJC/EEIcT9q3P9rbfMVKeVfR+33Q2u/g4F1Qog7hBB3AS8DXcBPpJTlmyQ3gPH6MzuUwbTWUpyPzWEa4lzP1WGIDF5NTXrCnghCy5LJ5ybYa2wKMo1bG45aeDVfiYNyo8iaaTTURGp0G6CZQk9CpYq3B8oL7q6wejyarX+xIWcm8Yr6I9wu4SVv1rZwsy3aixCSNn9jIshey5U6mR8+Bw2RIuBSkb4FzUpw74iPnVJ+/as/xXT18Wrscd7oX4c03bxlTqlb+GRweNtx1l9izPTwsFWX25dS58C9bzxPXusl4q5/0cKl63z62LMmJZV8Mgm5Qwgh6bMWIYYF9+RHVKcKXbgxx4hwD1qCu6WOln8ATZZgt1sy1kNeZop+K/Z1FoaWUND3YOpRQnuh7eC+RjWCuxclaCfiAKC+vi61swq4BngDWAD8M/B2IAXcABwjpfz+6J2saPi5wOeA9cA/Wfs9D3xQSvn50fs0Ck3TME1zsg4/I5FOr22HaYwd0XCoDNWbVU2imrwqBXVnvPZ6YEOkCOjD6XBe3Y8UtQv48cib6aH6c5cIkDEqE9wFw+ChjasnZUyNpjuhUsq7QuVNupp8AaTpIpar3zAuL5N49UYIbl/NZQSbBlSkuTPQqAi3EtzxjFoAGDKhcyvhsaRVtc3qTpQX3E9vfYO8vh0MH4bey9bUq/jkPNXybi/w/068BICwtmTMbZqtqGPUEkHfeuIKhPTw6RUXT/4ApykRK3W6x0qzzxrqHhT2zuAIt3BhyvLzM7uFYksdLf8Amnzq/pDI1R/hNmQaryO4hzis8yCEkAhhEPFOXm/yfZVq7thPAucKIQ6TUr5cbgMhxNuBg4AbGzC2qpFSbgL+rcZ9TeBa699ew+fzkUqlCIcnrw/gjMN0BLfD9CWVSuH3Oz/ilWCaJogcfpf6vFpHtJjar7W2dFRTpAi6h++nfpcPRG5SFkLyMoPHSoH2aWFSxsQLBd996Lc8tv0xus0n+YXrdo5bcGBDx9RoupNKCO7XOrbDrpABkg3oda4iv/XXDro1L+lCf0379lluyq1jRPSrxWcJ7oTVh1mZ0BmEPeocnRdpQ0qdvkxf2f1vXfN3AN7W+UEe7fsVOX0LizzvbMjYKmFRayc/OOE3HNgxd8xtmrzqO+tPxTBNk7TYzv7+Uya15nq60zQkuAc5hPlkjX0gpVwbO8JtR6TbAvUJuWa/Jbjz9QtuUwyXa5QpOAAAIABJREFUMznA2xYewU0b1d9dwc6pHcwMpJrZx48BHbhDCHHC6CetHtzXAyZwXWOGN/MJhUIMDg46aajVMEJwO5+bw3RCSsng4CDBoNNSoxIGMkmEkEOtXtr8SuR0J2qLcMezaYSWp8k7nA7ndykH5XiudhOtsTBkBo+VDt/s6SQvxhd5yWyWP2y9im7zSQDe6N3e8DE1mp5kL1IKFreOPQHTZYBUof4UTynSRYslteLV/Bg11u0PZmxzp8Zcw363LbhVhNs2oWu2zlFN09DMEIPZ8ufOttg2pOnmY0cON39Z1rqsIWOrlNOWHsGC5rFrxputqOUv1n2D/3jwRoSWZUnzfntreNOSZp86j/uSagEnZ2SRpv6mS42vBpdwIykfELFbKLYF6ltQa/UrwZ5sQITbFBn8juAeYsXc4Wv2Kyd+YApHMjOpWHBLKR8Dvg3sBzwmhNiJqqI9SwixAeX8vRj4lpTy+UkY64ykpaWFQqHArl27yGazjoCsADkyBb+OWk8Hh0YhpSSbzbJr1y4KhQItLXunR+6bnd6kEjcht5qEtQWbrMdr60CwI6aihM0j0uHs6PlAqvEO4gZZPLo6/qzAbNBTQ3Ws5dgaLU4b3hKdquqryhnI9iHM4LimP6p/en3163b7sbC7/lRGj+5D1li3H8uq92GbM9WLz1Uc4d4VV8K61T+8KOQmQqJQ/pzvy+zGZbZyeNdC5ugn0aWdwCdWnN2QsTWKkVHL+7fdAcARs6Z35sZk02YJw/6MLbhzCOmeyiFNOi7NjRTlI9wJK6W8tc4a7taAWghLFcYW3Bv7d/NK99Zxj5PMZhFa1kmdHoFL1/m3Q/6Hn77tNlrqXBhxKKWqIiAp5XeFEGtQfbjtRoXt1r+NwDellDc3dogzG03TmD9/Pv39/WzdupVCoXwPw+lAOp/FrbtwaVO7QmsmYxhRNXl2FXIIr5O+6zD1uFwumpqa6OzsdGq4K8RO37Vbvcyyejr3pmoT3Lus2u9m37CYCVrR84FMsiITkmqQIyIkCyJzWBmF1d1bOHm/5WW3Hy24d8QrawU1lcTy/bjk+JNSrxYgbdbXptEWok0NmAD7XLXX7duC2xZM9RJwqQyIpCW4dydLTegCehuJQk/Z/ePGHgJ6B5qm8deLftqQMTWakVHLHOp9vHXhdO0Ou3dotRYh+tOW4DazqA6zMxeXcMEYEe5YbhAMf93eAwG3Fyl10oWxTREv/ssXiJkb+MU7bxqzZGfzoDpP2/yN8WqYKXz0qH+a6iHMWKo+86WUfwT+KIRYgIp268A2KeXaRg9uX8HlctHZ2Uln5/StmUjlsxzz2+M5OPRufv8vU9shLXbDley46iYAOt57NO3fu2lKx+Pg4FAbA0OtYtSE3W4x1V9ji6ndZRy1g5YrsO2SW4733voVmn3NXH/u16p6PSmyeC1BtaR1HmyDN3q3jim4d8ZUD2W3MZ+8vo2eVHmRNZ1IGYP4tfHrmf16mLixs67X6Y4rwT4y8lsrft2P0PIUDKPqFN5k3orENSjC43er88Puw7zHyt7oDA5nwbR5uxgwXyvrM5Cjjy7P9E7Pbg+OWJzQ02AEa/ZgmCm0W4I7Zt138ubMj3C7dQ9SlA8axfNRNNmYa0qYHjJjCO5kNktUvo7Q83zqgc9y77/cxpxIqajeYgnuWYG908/ewaHmMIyUcquU8mEp5YOO2J75vLhzI0LLszO5eaqHgkyrVCJPi0bvnSsxB3uneEQODg61MDhKcM+N2D2da3O83mNFDzsDw2LGblkUzYyd8rwuey/PRqtLzsoVCgjNGIpwH9Sh+pZuGBi7Ltt2/L7qpO+hFzoZyI7dCmq6kJNRQq7xSyQCrhCmqK+m0l4saW1AZNn2BBhIV5/mbpsxtQcaY2Qa8KiUcltw96fVYlJncHgRY05wDkLLsnXUb9lgOgl6QpUrTGMCbi//NOszSFMtbniZvsGDvcUsy9U/mlMlJnkzh1Z9jOtNhVu4QZSPcKeNGB7RmGtK4CVjlBfcd73xDELLs8T7LgxXN9979Ddlt9thLX7ODrc3ZEwODhPh5D06VMQLO9WaStyY+ppDW3BHTliONARGdyXt4R0cHKYbg2k1GbVbvTT7g0jTRbzGFlN9lpiZNaKFVcSrxNdYgrtQY5tBO0XYo3sAOKRzPlIKdiTGjvTuSSnBPb+5HZ/WSsIo70w9XTBNE1OL0ewdPwoU8oSRWqbmzxKGywjG6vddDUG3ymroS1d/HiXzSaQUNPkaY6YUHBXhHrCyN+aEh6NuS1rUYs2q7k1F+77cvRmA+eE5DRnLZPI/7/oUYQ4AoMU9/cc72XRaUf94zopwyyya8EzlkCYdt+5BCKPsfSBjxvDpjSnT0KSHnFkquP+67kX+68XPAPC/p10ORoDNsU0l2wHsstrwzWsa2wzQwaGRjLncJoR4bz0HllLeUc/+DtOL13pVrwBD7yOZzRL0jm2gM9mYluDWm9Wk2kzV3//VwcFh7xPLqmt5pJGOkH4S+dquaTt6ODKFMGy5TcfHcLVd3z+8iLgz1l82/bAccct12msJbp/bg2Y0sSe9e+zxZZTgXtDcQcTdTnf2lYpea6rYGR9EaAXa/eNHgSKeCEJIepLRij+/0djnQksDzMrsCPdgDRHudD4N0tMwHwZbcKfzysQtmlXn9sjPaVnHQtgAr/Vu5t2FFfSmYsyJtPLsjtfV8+2LGjKWycanB0lImB2cN9VDmXI8LhfS9JDM2ynlaVzM3JZgAG5NpcynCznCerG3TkHECbmWNuZ1RJi0UWpOeffaxwA4tvkilrR14aWTvmz5BdDelMqoWdjsZGM47B3Gy2+5HeVCXiszt/fBPsi2hHJ8FMLk+Z3redviqTNEkWk10dVb1IRFToL7sIODw+QTt3qztviHRZYuA6SN2q5pW8zMjgxHuO3oeTxbXnC/vmc4BfzFXRsrFozJnBJQtgs1gE+0Ec2PXZc9mB0Ew0fA7aXZ28rO/PS+d20dMhYaP6W8xWpxtaOKBYvRpPLqvh5ugAlmyDLhGxynjGAsMkYKIRu3oBy0+i6nC+p8iedjYPqKzKPeMlvVaG8a3MZn7vkhT/fdzkkdF/Bkz71Izc1Zy45p2Hgmk4KZBwH7NS+Y6qFMC4T0kS6oczAvU/i1md29wl58TOYyRdexaZpILUmTpzG97QN6E7FCqZDeGtuCNL383z9/CVCZFrtzr5c9Rn+mHykF8yJODbfD3mE8wX0H9QluhxlEb2YHEhdCK/DCrnVTKrjNjCW4W1UqkExO70mrg4NDeeKWQVXHCNMltwiSMWprMRXPxZCmt6iFVbNVH263pRnNhv4dQ3+/2rOJMw88qux2sV98F/fiZfjfeb51PJUibE8yAcLuDnpz68YcX2KEcVDYHUZoBaKZVMPSlxtNj2Xw1TZBmvf85tmwC97o3cbR8/bnle6tfOPhn3DjOd+m2V9ZP+t0QX2eYW/9n0XEO3Hd/lhkzQy6bFwkMuS1Bbd6f6l8HGEWv8c5kVaE0czKPQ8AAlwpHuu/HlzgMxY1ZBFib5CXGRDQEZjZwrJSdOkbqjUuyBR+ff4Uj2hycesqwp0a1a51Z3wQIQxafY1xBA+7W+g3ioX0j5+8ky2pl/CKWUPZKbOD89llPFX2HjuYHUCYgbpd0x0cKmXMM01Ked7eHIjD9CYr43iZTY5t7IxPrbOuzGYRmkQEVRqqmXYEt4PDm5GUZVA1sgWTVwvW3GIqVUigjRJLtuBLjuFquzU2nFK+fqC8H0Tu5SfY8YOb0X2w5MG3obd2kbBSym0XaoB23yx2G8+O6Y6dKsRwW8ZBYa/6b3d8cNoK7j1JlaLfHhjfOfygdsswrl9lC3z+b99hj1zJna+9i0uOfEdFr2UL0kgjBXe2+t+GrJFCF42LcIcsl/yMoURI2kziovQ9Xrb8a1z36lcRojjOcUTbiQ0by2TztWO/xBVPX8F5y9821UOZFujCT9ZU9zhTpPG7Klt8erNiLz6mrOwfmy2DqsymI9AYwd3ibWNLPkUqnyXg9lIwDH6x7hvggjbtuKHtljQv5MW45Pkd6zl1yWFFx0jko+iyMSZuDg6V4JimOVSEIbMEdRVR7s8MTOlYzEwO4QLNShW1TdQcIP3wH1m34iAKW8qnUTnMfMyBHradcxy5VY9N9VAmJJlPIk29yBPCr4cpyNqu6ZyZRchiY6JWK13dFvej6U52I6WOMJpYNzhG+uE1V4AAIy2I/vwKABJZJRD9I1LK54bmIoTBG73l6wYzZhSfpiZ5LVa/6Z5Eff2rJ5O+tBpbR3D8CPehXQsB2Brbwa0vP8oeuRKAjeM4to8mY6VcR3z1R3ObvOOXEYxHXmZwicZFuMOW4M5a7y9rJHBrZQT3MWdwfMvFSCmGHvvN6Xdx7RlfaNhYJptzDj6W5z5yN7NC9bd2mwm4hZ+8mbZSqjMEXY1pizVd8ejDNdwj2RZVBmWzQo1J3+4IKE+JTf0q+LNlcLjbg18fXtTYv01lFKzrK70Ppc3GuaY7OFSCI7gdKsIUWUKuCNJ0Ec3W1iO3YWPJZtFcIILqx8uswRhnpjLwfz+hkITYb66Z6qE4TBHpR+4k8UaUrR/7BKm/Vtfqam+TLpTWy9bTYiovs2gUC+4WK8KdzpePcPdn9qAZTXS4D6K38DqmaZZsk+vuxdfhBk1S2LXLGrsSUP4R6euLm5U785qe0ki5aZrktV7avF1qXD5LcKemr+C227N1TiC42wJhMILsTnXzg+d+AIaayG6PV97VImtkkFIQ9tQvdu26/cQYRnnjUZAZ3I0U3FZKedZQ50teJvFp5YXXL875ErefeS/3nPMPfv/u+zhi9iJ87pntbD2T8Wh+8jJNNJNCCJOQZ2YLPNvPwu7gYLMrrroxzA03xhF8dkgJ7o393QC80TtcFvSWziOG/p4TVgJ/d7K/5Bh5mcarz+yMA4fphSO4HSpD5PDqfjQZJJab2gmizOUQbg0RUBNWJ8I9jKtNpWxl145dR+ows5FWdCEfhy3/esUUj2Z8Mka6RHCHPZGaW0wZZg59VOsdl64jTTcZI1N2n1ihF59oZXnb4Ug9you7StvImJkCmteFyweFQbXgmMqVRrgPsFKr1/VtLTnG5sE9oGWYG1IOzq3W/asvNbULmOMRzSon4Nnhic2OPLTSk9lMWt/Akc1nDgnwSskaWZCuhriD2673iTGyGsbDkBk8WuNqpn1uD1JqQ4LbECkCrrGF17KOeSxo7uCgTsfp+82OTwtgkKbbymKJeGd2hNtrRbgzoyLcdqbMnAYZlM1vmgXAtphKVd88qBb2Ll3ybb5z6oeGtltgtfyyX38k6jqf2a7xDtMLR3A7TIhpmkiRxe/yocsQqTLtGPbqeLJ5NJeGFlA/XjJTPnK1L2JELTGwduxewA4zG3OguLezLBSmaCQTkzXS6KNa5dgtproT1QvRgsyhC3fJ40J6SRXKZ8JkzAHC7nZOWaTM0v6x8YWSbcxsAc3vQQ+4MKKqLjhl1RwHRtRwH9yhBPeOeGlrsBd2rAdgaesiYDhNu7+GXtF7i1guhpSC9sDE/XNDegdpfQMAR8w6GA+tDOQq9/vIGVmELP3uaqHZKiNI1hDhNkUWr97gmnrpImfVcJsiRdA9syOdDgqfK4AUGboTqgyvyTuzv3efy6rhzhfXcNuZMl2hxpjpLWpWgntnXKWSb4+q++3bFx1etGA31+qY0J8uLYM0RQZfo69zB4dxcAS3w4TEcxmEkPhdQbxaiMwUC26ZKyA8GiKkJoFm2hHcNoUB9d3kBk3kKKdQh30DI1q8mi/jpel004WczKCPSt9ttlKtd9UwboMcrjKGV7oMkC6UGmiZpomhDdDq7eDAdhVR7E72lm6XNdB8XlwhL0Zc3W8y1vU1UnDPjbQgTRe96dJjvNqrIueHdy0BhtO0BxosuE3T5H23fZUv3vezuo+VyMURpq+sAdxoOv1zh/4+aeGhBPV2Ukbp5zAWOTOLoDHp060BlSqaKlQvuKXI4tMb6woupIuckSWeTSO0PBHPxAsYDm9+Aq4gUssOmQ+2+md2bbvPZZVPjIpwx3JqXtKo2v4lrbMB2G3dq3clleA+sGNu0XY+twcMf9mszMm4zh0cxsMR3A4TMmD1uQ64/fj1MHk5xYI7b6C5dbSgunnLrCO4bQox+7MQGHt2jLutw8zEtAR3x3tUxNaMV1YCYpom97zxHM9uXz9pYxtN3kyX1Mu2+ZUQ7a5BcJsyh1uUijbXGK3Gtg72IrQCswKzRqQflr6umZdoAR96U4BCMg8Mu2oHPcMCX9M0NDPCYLav5BgbB1Vd95FzlOC2J5/2ZHQiNvbv5hN/uXrCVPv/efx21mbu4YGen1Z03PFIF5IIWdmk9KLl5wz9feSc/Wj1zqKgVW6wqQzvGhPhDri9SKmTHsOZfiyGs7kaG/kSuMmbOXbG1OcR8TqCe18g6A4hhMGOmIrETuT2/2bH57JM00ZFuBO5eEnv+XroCEWQppv+jLrP9mb2gBEo2z5PkyESheJFzYJhILQcgRnuGu8wvXAEt8OEDFi9TINuP0FXE4aYWpMyM1dAeFxDNdxmpnxt5r5IIVEAq62M0V1aR+ow8zEScUDi6lBpd2aFwvX7j/+Brz79YT7ytw9M4uiKKcgM7lH1su1Wz+eeZPXdEEzyuLXSCLdHC5KTpRHuV/dsA2BBZLZySjd8DGZLFyjMHGgBP3pTBCOtri/bNC3oLh6/RzQRL5R+5t3JnQijaahNWWewCSkF8QoF96V3fYmnBm7iz68+Pe52d226CwBRqL8Fz1gtrMpxzsHHIqVAGM1omkabrx20DIMVmlrmzVyJ4V09CNNDpkrBHcumEUIScDc28qVJL2kjOZS10eqb2cLLQRHyqGt9S0yVeM10wW37Wdgt8GySBZUp00h0M0I0p66naK4PlyzvM+EWIdKjBHef1Uo26HFSyh32Hk7Hd4cJGcyom1PIEyTiiSBzqTH7zO4NZN5E87gRXh8IicxmJ95pH0AWChTSEm+bi2yv4US491HMeBLNDVrI6lMfqyzC/XLPGvWHnsE0zYaYV02ESQbvKME9y6rz21ODe7cpcri1UtHm10MkjdK6artv9H4tKhVRkyHi+VEp+ZkU0hRowSBCCMy8wEzFh9pYhbzFE8mA3kK8UGoWFsv34mG4htGl6wjTSyJfWa/oWGEXuCCWHV/ARgtbwQWmFq/7e8waybItrMbi/vc8PPR3sy8CUdgR6x9aZBgPVX/fQMGNl4xRneDuS6nFj6C7sZEvj4iQNmLstmp522Z4arGDIuJRXgLdCXU/6Jzh7dK8Vg13ZlQ5W9pIole4cFcpbhEhWRjENE0GC1todi0su51PC5E2i+/p/UPXuSO4HfYeToTbYUKiVoQ75AnQ7G1BCMmuCtNUJwMjZ6L51I1dc4HMOrXKAEbPNjAF3rlqUm/sqbwlj8PMwUwm0b0CEVSCW1bY53lncjgjIraXyjSUQVWxYO0K20Y3tbh35/HopZGUsVqNbYmqa+QAq/bPLcIl0RDT6iGrB0Po7Srt3Ni+gawVxQmPEtwRdwsFUfqZp81+gnpx1FnIAKkyteXlMKzxb4+PbUS2M9aPdPWD4UdoeXqS9Tmg52UK7xgtrMoxr6mVeU3qPdpR3Epr8Q2ZLWt4Vyua9JAzi7Ofntm6jlNv+hgPb3yl7D79VuQr7Gms4PbrEbJmfGgRqSPYGPMoh+mN7Urel1HX7KwGmYZNV+zymqyRL3o8ayZwi8ZeUwG9hYwZ5c+vPYN09XPSnJPLb+dqIi+LFyl7k+oeby+IODjsDSoW3EKI9wkhXhZCnDbONqdb25wz1jYObz5swR3xBGi16iu3WZPQqcDMSvSwulEKXfXldoD8mmcA8O6/HwBGX+UOwQ4zByOVQfPpaLapYLwy0RUtDDvb28JjspEiXyK451qCO5qt3kxMijwevTRKGnaHkVq6pMe2Xa+9pEWZ8Pi1CBlzlOAeUMY8WiiMq0P10C7s3DTU5ik4qm90m68D9BTJUfelghik2dNe9JiOn7RR2WctLcG9u4ypm80jm1YD0Ok+HIDX68xyMUjhr7FXrV0a0J2oVHCXN7yrFZfwkzWKF1k+9uCF7JHP8Oc3Him7T1/Knog3VhyE3E0URJw+S3A3yq3ZYXpjt6eL5nuQUqMjsG+4lNv3Rpu8mWp4z2u1sBnjljV3IaXOp44uLzvC7iZMrfgea2dtNnphzcFhPKqJcF8MzAceG2ebR4EFwIfG2cbhTUbcaq0S8QaHJiKDmamp45bZDGZeoNmC2yWQufwEe+0bxO+8FYQkcsEnATD6S42bbO5f+wLff/T3e2toDnsRM5VD97uHBXdy4hrhTD5HXusBQ13fA3tJcEMBt1Yc1WwLhJBSI1al4M4VCgjNwFumt2rYE0EIkz2p4s9iMDsIpk/VbwMBV4SCKH7vZtQS3OEIersS3GZv95ATb9BdLBJnBVUUfF3/cIbJnkQM9Awdgc6ibd0iQM6c2Em7Oz6A0FR7t7702Nf187teA+D42ScAsLG/9vaApmliaglC7toMvuwo7p5kZRkWhsyXNbyrFa8WJjvC4LM7PgCaingncuXP76GJuK+xka8mTzNSSw71A57pkU4HRYtfXTtpdiPM4F4p05lKAtbiY65QPCcrkMKvNVbctnhbQU/wRuJRmjmE+c3le3w3eZsQWo74iKyt/rS6LzQ3+Dp3cBiPaq7+w4FVUsoxHaqs514C3lLvwBymD/GsmhA2+YIEPKreMpWbGqMys1/VQulNKnqiuQSmI7gBiK18g+B+YdyHHAdCYgyObTr1pacu4TebriiJ+Dm8+THSeTS/By2sJvUyNbF4fmnXJoRmEBaLAIhlq2+nVC2maSI0o6TmWtM0hOknnq9OcMdzakJlt6YZSbPXTm8uviYS+SiaOTwRbPK0YIpE0XVhDqoIrRZuRlg1mGYqTt7MIqWmWs+MYFHzHABe3Llu6LHXLHO2uaGuom29epB8BYL7kU3DKdCD2bEjxruTKvPo1MUrANgWK61br5S1fTsRWp554Xk17T/HylSwReZEmOTKGt7VSkCPkB9hlPfCzo1Dfydz5ReMo5bgbvY2VhyoUiyTTbGNSKmxuKVz4p0c3vTYEW70OG5mdv02gN+u4R5lmiZFmkCDe893BJTAlnqUU+aNmXhLq0/9Dm4dHM4MimXVdd7kdwS3w96jGsHdBVSSn7bD2tZhhhC3ogHN/hBBq+dsIjc1rbhsIzDNEtzCrSFzhSkZy3RC5nPkY+A/eH+EpqF7wYhOLFg2DThp5zMNM2ugBXxoYXWNmMmJBXe3ZebU4lVCILoXMliSVuuYcingWhW1zTbRjBKuPlepaLNNqka3GksaMdxieCLY7GtGaAX6RixSGNY+WqQZzaqLN1MJVcMtS31Hz152AlIKHt6ycuix9X3qvrWwaXbRtj4tSIEKBPeW56zBREgU/j97bx4uSVbW+X/OicjI/eZda7m19t4N3UDTrC2KiMiiAg7ijg6CM4qD228YHcfR3zwMLvhDcMRhfrihoiKIosimstotW3fTG3RXV1fXemu5e+5LRJwzf5yIXG4uN/PevFXVVfF9nnzqVuaJyJOREZHn+37f9/v2D6StN1bBT/HU3cZA6FRh6ynlXzt7DIAbp3ubEW2G+QlDuNdqw5U0aOH2NLzbKtKxCZRsncdfXzze/Lvc59wKDelyY1a+dqUNOThXPYb0c2NrjxTh8kbYLxogIa58wh2W1zTaCLfn+2hZIxMb7zW1J8gkAviPz35l33GzKUO428sgw+u8GRCJEOEiYBTCXQFmNx0FM0DkYnUFoewacj2ZSJMKCHf4XC9UPvHnHH/hbfir3U6920W4T2vKnIrSlmg3ItwqSF+1siaFzUpK/OLmpOnesxev53KEiwO/rrEyKURIuCubnwdhAG0iZrYpXgSFuxxkycR7EO6YSFMbsrY5RGj0luyhcIf1xKFLdIi6KpCQrUXXbMKQxJPrrUCUKhjCKHPTyEDh1tUqrmogehDu/blpHH8fR/L3N58Lzdmun9nXMTZlp9Fi8+DlI2sPIbxpcvIQ6zzMx4/c23NcyV3H0ll2Z3I4/iG+svoPnF5vpaC//QsfbDpxA/zeF/+eU+u9/Ti+sWQI6tN2X7fp/HohrFMetjRA0+hpeLdVTMYnEbLerKV/Yj0wBfSTVL3e10S4EJ9JjrdP9u6M+b2qyVMkRO/U1whXHvZNTEHQDitj925bdSUhHWT7NFSLAixXCgihmXDGfU2Z6yirntI0auw5Lm1eO1ds3QfD63wqItwRLiJGIdwPA98kRP9fCyHELPAC4BvbnViEyweVgFzPprJk4kFKudvfqGzpd36H2gWP8t/94djnopbNQjgk3CJmoVx/7O/zZINaNcdFhoQ75eAXN1/IP7p8YienFeEiQyuFckFm0sggpXcYwl1uhEE1syjcrPXUOFBumHtIzOp2pnZkpmff7EEoBgr3xr7YAHNp87lWKp1qq6tLpKzWQjAbugpXW6Q0NJ2TuZlWEKNaMYSb3q7aB9O3UuIYnm/uTRcqJp3x+plOhTsdy6JlbdPSjhXvKHPOjQhhIYTml+76+Z7jKn6euDSf5xef/UtgFXnPVz7CL//zH/HqD7yFPz/+Vn7ww28B4Lf/9UO897Ff4b/88//qua8T+VNoLXjm/NYIt2Pb4CcousP1Ge9neLdVTAfn8umCCSgslM6AnyTGDLU+afxFN1C+UuNV4+YDciCETzY2jG4R4UqAlBJbmftwLt6fFF4p6KVwhx1tQsf2ceH7b/tmXjD9ev7mNe8ZOG5+wlxvF8qt7KZScJ3PpsYbBIgQYRBGIdwfBFLAB4QQXWepECIL/CWQBP56PNOLcDmg6lXQWpBLpMgGNdxVr38Nt5UNSPm/3TX2ufhBHY6cNqmvwrHRjYhw+2tfZPyyAAAgAElEQVRmUSknjAJnT6bxCv2DIlqZtNsn1k/u/OQiXDSo9UXQAiubRWSnAI2qbh54CdXmmaRRJUOjxJ1E2e2vcCetDK4ebQ5hDXeYhdOOsNXYcrVT4VayTNZpKU8TcdOXtT2lXhUNYZS5WWSg2upqBU+5CN2bcO/L7ENIt7nYzNfyaC3Zk+lUubJOBiF0l5lbO87kV9HWOtfnbuKlh15u3l/0zuqpqyJJae4B/+4pz0erOA+vfJ2Pnn0Xx+qfBOBC4wiv+/Bb+dPHfwMAX/e+f56vLCD9qaah3FYgdIryEITb832E9Hoa3m0V4bl8Jm+UraXaGRxmiYkkDdU7oFQOzvvZMbtJH5xs1WzPJnaPdd8RLm84QVu9meSVn9ng2DZaSxptLuVrQfBy3IQ7EXN4z3f/QrN0pR/2B4R7udK695ebhDuq4Y5w8TAK4f4D4GvAi4HHhRD/WwjxM8Hj94FjwLcDDwL/Z/xTjXCpUPWqoGNIKZsRzMqAlHJ31ShTxQdOogYsJLeC0AjMmjXGRDJmo7zI+EuFhDtnFpmxPbO4RYXuoZwppUAYo7lz5e21DYpweUEtm5ILOZFDSImwQVc2J9yVIIAWpt+VL4JHQzUwO+xFuPv1zR6E0gDCff20sRVZrLSMc/K1CkLWmYy3E+508Fob4Q7queXUHCITKtwmpVzSuxY3VFcXCub9im4BoZJdLsUTcUPsNqa6t+PeBWO+dv3UIX7lW3+Ifda3ILB6jvVFoRlAsC2LNIc4Wz3aMUbZy9xf+iBzlmkdVvV6H+eCt7zt9GdbpKn6m/8GhA7CvQzvtopm3XRxhUcWz1AUR7guezuOTOPq3ud3xSs3g8vjxE1z882/92b2DhgZ4UqDFTjv705dJZkNOmb8LQKE13aqR+bRxcDBSXPcV2ute2zFq6CV3WV4GSHCTmJowq21bgAvAz6DqeX+SeCdweOnguc+C7xMax01Rr6CUPdrCG1uTKECtNGFMkTjoX+jsdIglgWvBCu/9h/GOheVDwh3sIARTgwdEW5U3qRLWZPGSCS2bz/aF/gnH+0au1QpIoQ5Zuvu1l2MI1x+8FdCF38TeJH2cH3qKwFZ3RvUmg7yaBgXQpIf9m5tR8bu3Td7EMIgQa+U8qlUBvwEy9UW4T4dZMtMJ1stmsI2McV6u8JdAqkR6RzCthFSo2s1PN1Ait4K91xg1HM2MFyreCUs3e18PZUwyWKLpf7GYl9fMu7aT911LRAGI7q/n4bnoWWVSaf1eQ6kb6Runegam/Sv49M/8kdIb66vOZ2v68S2qTg7Ik29j5rcjkGGd1vFnowJHp0vrfKuL30AIRQ/+5wfISFT+H0Id9WtgnbG3r4pFYszK54FwGwyagl2NcEOCHe8x33uSoTQMRqq9ZsTZkuF2ZEXG9l4Eq3i5Oute2zFLSP0+O41ESIMg5F+VbTWS1rrbwe+GXgb8BfB423At2itX6y1jlbwVxjqfg0Z3Jwmgsh/rUdKucqvcOy1b0C5gqmX30n6mhSFux4c61z8QgGERuQC07R4DO3psb7HkxF+wQQiZBDNdQ5fD4D72ANdY8/kW6SjroZr2RPhyQEVGGDJoCepjAlUbXMPy4pvruf9wXVV9S4C4Q58IHqRrIl4777ZgxCmqGf6LOwsnSPfaJ37pwLX2l2pVkpiLmFIccltqb5+qYTlgAhImLBB1Rr42kXSexG9K0g9v1A212XNL2KLHoQ7cE8f1Ks6NPu6Y5+5ptOxNELWm/XhIU6uLyGEZjrZ+jy377qtY4zl7SKnb+OPX/G/kFIONKfzdWPbfbETMoOrNyfchWBR3svwbqs4EAQflyqrnCmdAj/LNx26haSd7hmwAKj6FaQe3xza8Wev/P+4Kfld/MSzvnNH9h/h8sTz9nwTALft2poXwpMNQtu4bYJMMxB6iQg3gFRpim4b4fZKSD3eLJYIETbDlnpTaK3vBu4e81wiXKZoqCoSsyjOxs1ipO51q2bu0Ra5ix2+jlSjztJH7sW/cBJr99Zay2yEXyhhxdsWv/E4KjIpR+XNgl1OBQr39bcC0Dj+CBt/5s4WjOom/El8OVqv4wiXN9SaIZRNF/+YRNc2V7jDANr+nDl/BpWMjAvVRki4u0ndTNA79fT6Erszw7XTCVX60NhxIxJyknJbS63TeRMbnp9otZeZTBpSXGy0K9wVrEQrNi1jAlWv4+s4luj9Exqqq0uBUU9dlzvc0EPMBYR7pdr/OjxbOgN+pnkcso7Zz2I531G/eGLNfJ7d6VYa+KtufgEfaLNpuGPmO/ijV/9i8/+OzNBQvYMapi/29shnys6w4m9OuEPn9HHWeR7KtVJJTYaBOS/SdqZpVLdRya771WZwedw4MDnD33zfb+zIviNcvvjNl7yR7z/3Yu7Yd3UQbomDq1uEuzQg8+hiISbSVLwW4a75JWI9AqARIuwkxps3FeGKhKvqWMIsQlKxOFpL6n63wu2eeASAqW++huwP/RzJ570QgOpnPjK2uahyBRlvW/wmEuiIcKNKZsFqTRtDntiNtwPgnjrRNfZ8yZCArNwPssZaZTQ36AiXL/z1oGf0VGgqaKGG6FMfEu7ZVAatLKr+zpumVYOgXbKHwj0X1JKfKSx3vdYPYYp6tg/hztjT1HVLSX5izfgXPGWuFQycDtpBldtM4/xKDZloEWtpC3S9gY/brM/ciH0ThvSuBj2oPV0iaXUT7tm0IdGr1f4p5auNcyRomW6FpPTChjT0M4Ebd1gWAHDrnoPNvz/wso/zB698S8c2g8zplGhs2zU8E5tAi8qmpQGLJfO9zKTG1zopLCNYrFyg7leaGQYZJ4sQqpnG3o6GqjZ/6yJEGAeklFcN2QYQxHDb2oKF5Unj9kUYBXExQU211jkNXWqa2UWIcLHQl3ALIaa387iYHyLCzsLVNez2RcgGU4wQ3inTt3X6534VkUiRfOGrQGiq935xbHNR1TpWvGUYJJIJtBLoen/X9KsBfqnUmWo/OYsV17jnuis8liqGlO1NHQbgyHJknHY5ofSX7+Sx229GrQ9PNkM0PQ5mjEmYjNuomrvpdnWvjtaSRMxBaIf6gC4E40KTcMe6Cc7erCGsZ4sjEG53MOGeis/iy3yT/C2UzqK14Ja5Vm/s6ZQhZZU2IzG/2sBKtYiniElU3UVpF7tPDfe+oC/ses0QSSUqpO1uwr07MGFbr/VPna+qVbJ2i0RPhnXfG9LQzxYN4T6Q29XxPL5ZWN40O9+l6Jp68H4KtIuzTYV7Ij6BkH5PctuO5Yr5LKHiPy7E2c1S7QwNXcaR5rvNOuZ4nC91p/Gb37qdSSmPEOFqgCUcvDaFO8yWysYvHeFO2RO4upVF5OoKSSsi3BEuLgYp3EvbeCzu3JQjXGz4dJrnCG13mGKEcBdOA5rYtaZuUE7twkqAt7g0trmomouMt6lNCbO4VgNqIK8GqGIZGWul2gPIhERVuhe6K1VzrG6cMjWhx9bOXZxJRhgKi+/+Q/yqoP7lfx55W78Q9IyeNU7IVtJB1TdXuOt+HYIWVwKnZwbLIHzwobt4//2fHWmbmmsWZb3MhPZlDcFcbOuduhnCVoUTTu+F3VxyDiE9zgatupaqF5B+rsOpNhWLG4W/rYZdVT2sVOv+J2MS3XBRuNiytwJs9hOnUC/g+T5a1sg63T1f92ZN6nyh0T+lXIkS2VhL+Q1V+OUNPcUXg0DaoclOwv2h7/4Qv/yMd2Nb3c7m2QF9wLV0iVvbU3sn44ZALxQGf48rgcK/KzM+hRtgMjZPWV3A0xUS0pwXk4nQGb77N8PTNWIR4Y4QYcuwRAy/jXCHgdVLqXBPJ+bw5XrT90KJMik7ItwRLi4GEe41YLXHQ7Q93ODR/txqsG2EKwS+rncoHULHOvoshnAvLGElQSRbtTF22sZbH1/Ksqp7yERLVZJJQ7h18Son3JUK0hEdz1lxC1Xp/p7WgzTXO+ZvAeDUeuRzeDlBxAwxqh/pNrzbDKpYQgSO2gAyncKvbe703VD1Zk9pqeM9A2qD8Nb7forfeuBnRnIVrwULsVQPhfvwlCmNCLMxhkHYW3Um3buH8p6MqdU+umIyOvLuYs+2V0I71NoIt19TyExLNReOjWr4aPor3GCMekpegXPFdYTQTPQg3BPxJFpbFBu9Fe6KWwerymS8lTQ2kzLfbdjfNsRKdQWtBYcm5zqev3luPz/49Bf23P9EPNfTnK7mNhDC33abrulAsT5XHPw9hvek3ZnxOnjPpw+irDV8USQZLLD3Z01A4sjyqa7xxpk9SimPEGGrsIWDr1tZVWHw8lIS7v2Z/Qjpc2T5LEopEwCN9f6diBBhp9CXcGutZ7XWc+ED2AV8DFgHfhk4ACSDxwHgv2LI9seC8RcdQoiYEOLFQoh3CCG+JIQ4J4RoCCEWhBB/I4T41j7bvU8IoQc8unsrXUVQok68jXBLnI4anRDecp5YrlPxsScSeIXxGTCpuo9MtKV3Js1NXPVQK64mqEoNK955OcuEjV/t/p7yjTxaxXja7msAOFuKCPflBGGZwEnj6GMjb+uXy8g2R20rk0LVN3fxb7S1/pMijquGV7hX2sjaPzz6laG3C1sL9iLce7OTaC1Zqw1/XVfcClpbfVPKD06YNPvjqyajo6pWyMa6f6oEcWq+uWdppVANsDItNUQ6Ntr10cIj1kfhhqAHtVdsmhROJbrTpaWUCJWg7PYOSp5cM9lBM23O4zOBwr2x7nu9voZQKRx7eC/UybjZ19kNCnR+TH2xZ4Oa7NCtvR/ydXMOzU+Ml3BfP3UYITRYVdIx8x1+27XPAODe81/vGq9wt20UFyHC1QxLOB0KdxhYzV3ClPJrp/YD8PCFEyyW8wihmIiPt3wlQoTNMIpL+c8APwg8V2t9/4bXFoDfEkJ8CviyEOIBrfU7xzXJEfBCIMzDPA/cC5SBpwCvAV4jhHir1vpX+2x/N/B4j+ev7pxb0SButSk8xDpqdAC026C+VCF5uLN8386laSxu7lI7LJSrkMk28h/UXOoBfWyvBvjVRofyDyCTcdyV7oV8qVFA6jTXTO1Ca8lKdfRa4Qg7B69orq36qdFr61Vpg6ngRBblGY8DEe9PJFxdb7a4snFw9fCE+xOP3dP8+28e+RSvfsrzhtqu7vUn3LZlIVSKQmN4wl31KgjVX528dtqk2Z8qnMfzfXy5xmxid9c4o/Cbz6+La2glkBMtNUTEYyi3BMLDGaCGxkWGmipyrrQCwGyqN5mUOkW1j5P38cB5fFe6dV8N675Dkhqi5Oax9GiqzUzS7OtccZXbuab5fCGouU5tk3DvSpvPPKjtGZiUeq1ifYMlW8Wtu67jQ4GQHSpah6d3IbxJjuW7A1paNAZ+pxEiRBiMmHTQtBTuml9FK7tnScvFwlPmDsEROLJykutn5oFWsDFChIuFUQj3G4DP9yDbTWit7xdCfA74ceBSEG4FfBj4Xa31v7a/IIT4fkzP8P8uhPis1rpXweEfaq3ft/PTfPJAKYUWjY7+qJZw8DYo3KW/fCdeGSZe/rKO563JHF71AlqpjvriLc+nQQfhFimjWqirnXCXGsSmOyPIVipBfaH7uFT8IpZOB6QmTuUi9Fy+0qFKeUQ8iYhtz9VZuw3ckgYEjfPD96AO4VfqWInWwsbKmkWFv3IOe/6afpvhqgZWkB5tiwSNPs7VvXD36a8Fb57idOmJobcLjRfTTm9SZ+sMJXf467rqVxADWjrdNGdUjnOlRY6unENIn32ZvV3jrDaF318+a57LtWqLpRNDuRqNS8zqn1I+EZvlbONr/P9fez9aS567/5ae42yRpNaHcC8ELu3tzuN7AsJdqHcG0yp+nrgcbRE5FwQBzm0wp8vXzHy2q3DvCVLEQ9+Ifii7RYQef9ug5+y/CYJ4UC7eCkbk7MOsNI53jdfCjQh3hAjbQEw4KFrrw4bfaJYrXSo8fa/57TtVWOB8yWTbhMHGCBEuFkZhQNdjDNE2wwpwSXogaK0/o7X+3o1kO3jtr4H3Bf/9kYs6sScxym4dIRRJu0XmLNGtcBc+9o9YSU32dZ1tZ+zZGbQvUOvb99HTnofyBDLdqhGXIeEuj05OrhSo4hr1VY/4tQc6npfpJH6jO5245hebjr2CODVv51tAXek48R13svzf/v229+Md/wZogbA0XmX4eugQqtpAJts8DgKiqALi2Pd9dQMrVLhlHF8PX8N9PH8M/CyT8gYK3vmht2sR7t4Ex5FZqmr4PvENv4pFf4K4O5NDK4fl6jJfv2CaUx/O7e8aZ4tEU+FXK+bzWJMthVnE42hPI6Q/kJw9Y+52sEqc8T7PzalXcOehm3uOc0Sahup9DZ4rmZ/cg21GaLlECq0lpQ113w1dIGWNRrhv22MWoo+unOh4vjim3rlhn/C12uDASdUvYenxp5zuz003Xdon21L6D6Svw7MWaXgbDAWFS6JHm7oIESIMh5jloEXruqr7NQTbC0RvFzOpLPgpzpfPsRgQ7rk+GUcRIuwURiHcJeB5QohBrcQk8Jxg7OWIQIqhe5UVoSfWquarTNqthZe9IYIJ4K4Wic8lu9JWrTmTsumfPrrtuahA7ekg3GmzwNTly/WU23nU7voYaEHymc/peF5m0ijX1KG2w9UlktKoPVLHqatI4d4OtOdRX/NpnDi97X25x78BQHyXg3IFepN2ShvhV12sdFs2SkAU/dXBRNjXjWZP6bhMoBiecK+550myi7nEPly5NLRxWmMThTspJ2io4QNppofyYEXWUjnW6sscXT0DwI2zB7rGxEQcLwg4+AHhlpMtczWZiKOCjMleDushXnnzC5p//48XvqnvuLhM4eneCvdSD+dxU/edZq2+0jHWF0WysdEWkU/fcxitYjyx3qn2NlPKt0m4Q4U7Xx9MuGt+mZhIDxyzVSQwv0FTiZbCPRHPIoRmrdY67pUguBy3ohruCBG2CkfG0aKVUu6qetMf5FIipqdZbyw1WxDuGrNBY4QIm2EUwv1p4DDwe0J0r2qEEHHgd4FrgrGXI24I/u1Xk/0iIcTvCCHeK4R4qxDipYMCDFcDVqtmQZKOtdSHjS6UAH6xgZ3rXjDZu02PW+/siW3PReXNArOdcIuMIdyqcvUq3LWvmoSOxAte0fG8lc6AFugNhkieKJMKegJbItGsV21H9VN/xbkfe0kXWY/QDbV0BrTAL24/U0CtGkXT2W0WA/6FbiflQfCrCivbFpCamg32O7hO39cN7ECtdawESnSb7fVDVS0y6ezlwMQBhHQ5somaHqJJuHvUcANMONN4Ym14Aq+rm7Z0iotJyv4qpwqmPv7W3Ye7xsRkoqnw+8H3YU23zNVkIoH2Aa1xBpimPf/ATQAIb5Kn7u4m9iESVhpf9A56rdZW0VpwMDfb8XxG7GepcaL5/5rbAKtCzhltEWlbFo7ezYVq53lWCnrnZvq0WBsWjm2Dn6A4oO0ZQEOXicudMVWadkzNZmjgBq3a9Han9/XqeNLoI0S4mhG3HGgj3A1VR3JpU8oBEtYkNZVnoWSyLffnujtURIiwkxiFTP4KUAB+EjghhPjfQoi3BI/fB04AbwrG/Pexz3SbEELsAf598N8P9xn2o8DPAz+B+byfBB4SQty24xO8TBEuSNJOm8ItuxVur6Kwp7trYuy9ZqHpnT257bmotUDhzrZSA2VAuHVlfMZsTzbUjj6OldDErus8TeVEq343hKnJr5B1zDG0+zhSF//xQ6x/+Qz++c2/t3vOPM5SafjU3ysNISn2SqO10uoFVTDpbrG9RtH0F88Mva1WCr8OVq6VVmxNB/tZX+m3mXlfGsTaFG49JOEu1qsoK8+e1D5unD4EwH3nevlOdqOhGmgtcKzeViIHsgfBqnF8bbhyFNO+cLAim7Gnqcij3LX6J2gVZz7bfc+KyyRKmO9SB+e1bFuciWQCEMT8weRMSsmfveQf+NhrPjJwTulYFiV6m9St1pYRKt1lOLQ/fT11cda0DQNOBCU7c6nprn1shkl7nqLfGYMu1U3wKNMn+2AUSJ2m4g3OQPJ0hYS1M31x92cOAjCXbiPcQQA5JNkAheAzt2dzRYgQYTTErQRCKBMEJChXEpe+TCNjT9LQRR5Yuhfh57h118FLPaUIVxmGJtxa62PAtwFHMC3CfhL4zeDxU8Bu4Cjw7Vrr4VZcFwlCCBt4P5ADPq21/uiGIfdjXNifCmSAeeC7gAcwDuf/IoTYd/FmfPkgNM/JOi3VbGPKkFpfRrkCa7Y7Yhh7iklzbjz2yLbn0kwpz7YIhQgMhNQOEW7/wklOv/K5LP7sa9Du8KrfxYRfKGFnuklLs353tdX2a61WRkifXNASwxFJPN2trnlrJu3KPz24NVXD83j9p7+Hb/vgS5uL/6sN3gVDiv2Kv+19+UVD8Jz9ZjHgLw/fIEEtL4AWWJMtldOaMa2w1Hp3H+Ty37yH4y98GrpaNoQ7ULgTdhJEYyhl+Wtnn0AIzTW5Azxj7/UA3H/+yFDzdX0XtIXsY6Z4y6yxAvnKmeH251Mjbg1WSd0Ntem93jtuJdBBSr0qmYCjnGgRWZkwhMxxITEgpRzg9vlrODA5WElJxzIIWW8uUENU3Dpn6vcybd3Ytc2ts7cgpMe/njAlCCfXjRI/l5rtGrsZ5tMH8a0VivXWfaDcMAGA7SrcALZIUfUHZyApUSFt70xf3H93y7eTUjdyx3zLWib8XOttKeXFuvnMyaiGO0KELSMeXD/h9eSpetOQ81Ii50yhZJ5l72H2Ok/r+7sTIcJOYaQzTmv9NQwpfQXwW8BfBo+3A98JPEVrfe+4JzkG/B/gxcBpehimaa3fpbX+Pa31N7TWZa31Oa31xzD16F/CBBj+66A3EEL8ByHEPUKIe5aWhvGWe3IgJNwTbT0UHRnvaPvgBaTM3rWna3trdp5YFurHxqBwFwwJlJk2hTtQqFR1Z+qQq5/9e0qPFVj51DdY+62fxTs5uCV748G78U6N3j95O/CLNaxM98LfCnraqvVWOvHpIC1/Km6Om2Ml8XvU6/oF8717C91Ovu34xGPB5W6V+I3P/9Xok78C4C8ZUuzXNu93vRlUQLhj19zQse+h5nHeKO3WdFu98axJp/Xz3S7RC2/9XWoXXNyj9xt3ZssslJJ2AiE0xcbmrcEeumBcyW+Zu4bnH7gJ4U3y5fN3DzVfV7kI3b9RxjP3mmPw0OJw8VstaiSswerk9934vQjPXBdC9g4QTTg5tKxRcxuowBuiQ+FOGNXX8RiLwVbWMcruYrmzzvmP7vkkWCVedd2rurb5poNPA+CLpx8C4EzeKNx7M6OnSe5K7UIIzUKhlQVRco3aO442XY7IUFctYquV4tyPvYTSB98NBFk3skY6tjOE+ztvehZffv2HmUq1FPRsQLjzHYQ7rFuPUsojRNgqwqyfMGPEp0HsMlC4pxPTCOmDVeXO+edf6ulEuAoxcohHG3xSa/1ftdavCx6/pLX+hNb6siv4FEL8Lqal2XngxVrroW10tdYN4DeC/75ik7Hv1Vo/S2v9rLm5uUFDn1QoNsxNMxdvLVaMC2Ub4T5zDAB7T28vuvj8BLWFtW3PpUm4cy0FT2aN8qSrO+O07Z1rGWFdeP/nOPum1/Udq5Xi1BveyMIbv5/Gg3ez+J9ejd7ogrsD8CsudqZbiQrrd/21FuE+Wwh7AhvCHZeJnumsXtEEMLxzg1OaP3HsrubfR9a2b4z3ZIS/YsiO9kXTZ2CrCBXV2HVPNfseUHt9Jr/Ko0ut78dfNHXJ1kybwdbUbkCjCt0p/35dmPdcX+pohxSm1LaTkX44lTe305tmDyCl5Nr081hVD7EyhKeCqxoM6kz5zPlr0VryxPqJLvW3F7Sod3RT6IU3P/9VPPiGL3Ct8x189/zP9Rwzk5pBCM3J9eUm4RYdhDtQuL3xqKFhP9gLba0NlVJ85uTdaBXjPz77O7u2efZ+E4w4vm7uT2Gv73Y382EREsx8W9CyFmSr5BLbNzJLWGncNlM47+QjrH/5DKd/9ffxL5xkqVJECMVEfGcIdy9MxM3nKjVavxuF+niM4iJEuJqRsEzwPwzYKl3HvgwI96627J9vOfyMSziTCFcrruicCiHEOzCp4ksYsr0VRhBKmldlSnkY9W9feCWtFEK6eL5JoQ3rs+19h3vuI37tQRrr/rZ7Zaui2V62GwjFkyA0qr4z6czeBaMwzr/5NQDUFvoTCe/IvbhFqJyqcez73sjKvxyh8bXP7ci8Ot63orBy3fWPoSqn8q104pWKOYaTCbPIT9rpnvW6fskEVMLP3w8PrdyL5e3G8vZwoTJ8vfGVBH+lRYr9cye2tS9VKiNtjTV/rdnfWncqeIhXfviHee3HX95M/Q7VcGuu1Vta2DYyBn6xfw2tu3gOhNt0Zw4NElermxPu9cB9Omz/9OJDL0BIj08e7Z3odP6NL6fy0T8BwNtE4U7EHGx/liOFr/Lsv7yDt3/hg33Hlut1hPRJx4YjiH//g+/g11/yhp6v7Q4WZifWL5jMGaERbfc/mTTHx/EgOQY1NLwWzxdNUHKtUuJpf3oHj9c/QZprSMe7F6u5RArh5zhfMUGWxbIh3Ie2QLjD73u9ra932TPke2IMCnfKzuKLFrGt3/u55t/59/4G54LPnXNGa2m2HYSEOyTZAKXGeIziIkS4mhEGrIpBpwPF5dHbfm+2tW587oHuMp0IEXYaWybcQghbCDElhJju9RjnJLc4v7cDv4DpC/4SrfU3trirUNq4KvtOlRpm0T2ZbBG6dLAgWQsW5CEpsw/cQC8kbn4qaEHja5/f1lyahLutJlJIibRBVzdPf90KvKVlpKPJ/fT/ZOoF1xh34j6ofPYfgr9aqcXusa2edsNB12uohsCazHW9Zs2aFH/vQiupo+Sa4xSmiiaDet0weBLCq5rP4C33L4+ouHXy+jEOpG4ja+8ZqQfzlQR/vZW94Z0fzRaQFw8AACAASURBVFV8I1S1inRAzuwFoTv2vRGuZQIcH3zYZBn4K6ZW35rrjA1KR6BqnddHe5lBbeUCQuhmenRokLhe3fyWV6gX0FoylzLq5M2zxjjtxFq3U7kq5Vm76wQn3/J2ADztIjZxr93l3IBnG1L5F0ff03fcStUo+KlNFO5hsH/CZCidyS+iKjVkzNxnQoiEeY+YB6kxKNwzSUM0w2DYpx6/DyFNZszhzC19t4szy7prvvOV2gpaCw7kRq/hzgblQsW2FnQ1z5wvk8ntK9zpWBYtKs3AUP3h+wGwEpriv36Z80UTVJpJdt/DdgphALnYaAWVyk3CHaWUR4iwVYRZP+VgraFEg5h16Qn3gYndzb9TfTpjRIiwkxiJcAshskKI3xJCHAPqwDJGPd74GM5WdocghPhN4C3AGoZsP7CN3X1f8O9Xtz2xJyGqTaWjtZANFZFwkRuqcNaewz334dz6bAAa37hvW3NRZbM4khsWlcJmRxTuJ+58Kmt3n8ROG4fg2O5dKFf07Wlc+fKXkDFN7tktwtN4YjjDp60idMi2ZroX2vb1zyCWExS/8MXWHINFZTqIQqdiKYTQ5NuUHrW+jPZMurG30l37G+IfH/0qQta5c/557BqxB/OVBH+9la4dpnVveV+VGtKRCCmx4uAX+mdUCM/ENf/6G/9otl01Kqe1p9N9VdoCXevMYqjf/6/Nv2tBSnwiULgzwfVdrG9eplF0CwiVahrQ3DxnuhIsFC90jd3Y4sxTLnJASjnAM3ff0fxb2cs83CegsVQ238GEs32n6wM5oxIvFJdQ1RoyJjpelwEJNQr39hduoXv2StUQ7i8tPNR87fbd/Rtk5GK7qCoTOMnX1xEqbdpwjYhMqEi1pVdXA8Kdi28/gDHhTCCkTz4g9PWjx7CSmqkXPY3K6SrrgQfITOriEe4wgFxuVPHOHOPs616MF3RkyDhRSnmECFtFmPUTEm4tGsTlpQ9iXTO1e/NBESLsIIYm3EKILPBF4D9jem27gMAov6LtsYohupcEQoi3Ar8IrGPI9tc2Gf8MIcR3CSGsDc/bQohfwKSkA7xzRyZ8maPum9TidFvUP3QsX60YBUyVywhLI+K9b6rO0+4ENPXHt0c+/fU1EDqoS21B2gJdH7+DeH3VkEc7ZxbV9rypUfee6Fat1doihftOk7lljpmf/xViQXake+Z019hxImzbZc90+wYIKZn81tupnKrhPmpSfMtBf91Q4Q7J1XK5Rey8s8daf+f7q5z/9IQxx/q+W1/IoaAH8yNL2yOcTza4xx5i/SsLIE1GgL+0PZVfVevIuCFNVkI2zet6QpishJW6Ibf+2hqguxRu4UhUw+14rt0Mrx4EzEKzm0xwbuTrm6eUV7wSlm6Rsn0TU2gV40KlB+HeEIzwtYsUgwniK2/6ZgCkZ7JaPv7Yl3qOWw1qxrPx7RPua6fN/eVCeRlVq3cRbpEMFW49FoOtXWnjSbEaEO4jq4+An+aXnvF7/JcXvLb/dsl5lLVOzW1QdNew9dZqoLOJ7gBL3a+hld3VjmwrmAw6IiwUzHlWX1gmvitF4pnPMf3rj5l4eHuf7J3GdBA0KbsV1t/9a+S/epYb/uFDQEvxjxAhwuhIB/fEUr1KsV5FyHqzK8qlREi4Z7hjk5ERIuwMRlG434JpkfXXmDTrD2A81HKYlmD/D6YH999orS+Ja5gQ4pWY/tkAjwNvFkK8r8fjl9o2Owx8FFgUQnxRCPEhIcQngZPAO4Ixv6i1/tTF+hyXE1wVEO5YywU7JNxrtYBwV03aZT/I7BSxrKBxcns1vt7yKnZKIDaoODImUXW3z1Zbg25TasN0UvvANWYePVzIC3/ydpQrmHrDTxF/5ou4/iuP4EwJVj9zlOVf/tGxzq0dftCSyprrdogHSH7TtwHQ+IZJ0AjNkELCHda8hv3WAfygJl9YGm+9f6r+8cLjSG+G62b2cMOMOTb3nz/Wd/yViNXfMbebzPU5EJr6o9srIVA1D5kMCHfSRlV6H3+lFEoYQtwIHKD9fB4rDiLW6VgvHbvr+giN3gDcwFAtbHEV1rcWG5s7/9f8ErZoq2+WEktNslbvNnvzl7oJt9hE4X7egRu5Lv4yfvppv4jWFvdc6J2stBqcvxNjIEvz2Wm0lqxWV1H1BtLpJJ0ibUi943UGIreKG2dNzf25sglSnK89TlYc5oef/q0DW9ccyO5DCMXDF05R9Qs4cmuEOxcaiLktwr1aW0Lq8fTFng5SxReKJgPDXWvgzM9iHzBtunRwD9uTuXiVaGFKedUtk/+sybzac+9ZpNJjcWaPEOFqRRiErHh1jq+Ze9pW2hWOG+l4nD980d/y0R/oX5oUIcJOYpT8s1dj6qHfoLWuCiGahapa6yXgnUKIrwCfF0Lcq7X+wzHPdRi0/2I/K3j0wucx/cPB9Nr+XUwLsEPA7Zgi3DPAnwC/f5m2OrsocAOFO9m2iJ8IVKT1kHBXakhHdG/cBmcuTeN8//TkYeCtFbEz3cxexKzxE+5Cy6zKXTEL0dghY7Thnu5uldU4eRyEJvmSH2htV1SAYOlvv8rsr491ek14oTP1rt6efqHa6S+bH76KbwhcSExCcrVSbVe4TwCQvnaC0tEC/vJZrKC9VDtWG6fJWmb/N80Y9f/Y6tVlnKaKZYSt2f+3d3PyO+6g8vBwLaz67q/m4WTN9SUTMVSt93mdr1Wadb6uDsxpqt1qLIB0LPwN+wnTz4XUeCVzHYdmN00H5yEU7roukdhA9BJyipLX7dbeTvIBPN3AFoP7WEsp+cgP/DYA733o9zlV6p0ls1g21+vu9PZJm21ZCJVhvbGKrnvNjIPmnJItwj2Oet+pVAb8DBcq5/jcEw/j2QvcNvXtm2533fR+OA9fXzxJXa8xbV+7pfcPyWe5LcCy1DhGzj68pf1tRKhcL5bW8JcW8OsCZ/8+YtcaJ35reQkOwt6Ji6dwZ50EWgtiq+dp5DXOpIB1yFbHE7SJEOFqRdMfoVbi+KpZd+xJX3rCDfDcg719hiJEuBgYReG+FrhHax3+KmuA9lRsrfXdmLTznxjbDEeA1vp9WmsxxONb27Y5rrX+Oa31nVrrfVrrhNY6qbW+QWv941cz2QajcGstcKzWojO8oeZDwl2rd6lAG+Hs20V91e1QjkeFV6hhT3arD9Kx0I3xtt/yF1u1onNvNCTavvZWM49z3WnTqlgy6mKbIjX3qucBIOzt92fuO8+lwChrQ91uCGuPqan1V4z5WTVIKZ9IdBLuMHgC0AhS/yde/lJAUPvCR7v2W3MbuPIC86nDADxlV1i7u7WUan/1PHoIV+zLDapWx05LhG2Tuu16qucbfWv8h9pf3UemDImTyTiq3tul72S+pSB7AeHWroewuwm3iMfQjc7rLizPiE1IVNmcE6kgpTwXnBvtLZP6wdNlElanEpq1Z6jr7qqi8BwE0NUyHnVicng1cV/yJkqcoOJ2+zWcK5rjcXhMdXoxPUHJXUfVPWSiM8gnAsId8yDljMd8x2GGtfoi77n3A2gt+YXn/9Cm29w4Y665Dz36UZS9wu1zz97Se0+GhDvw6zhfXMOzFrlu4uYt7W8jwiDIUnm9WdoSO3StceKXmti6SaXflb54aadSStAOiaCDgzNnvtNEvXU8IkSIMDr2BK1aV2t5zhRMkHV/bvTuCREiXGkYhXBrTF10iHB1PLNh3GlgPL/UES45XOWCtjpSG0PCXQgUMFVzu1SgjYjt2YP2BGobZMQredhT3a1jhGOhGgPsw7eAsMXSvv/8Q0z8xK8CJjXeimvcC93O3X65gox3Xk4zb3sfu17zXLQn8Je7XZvHAXdhAYTGPtTbzdgOjOxMfS/UvKC/bpA2mUuYhWa+nXCfPIUV12S+x7RNqt5zd9d+v3rmcYT0uGHKpIXuyU6BSvSs3d0MulrmsTtfxMKPfMfI215qqFoD6ZjvPXnHc40bf1vbo1HhNzQyZb4bmYzj13sHqBYKAeH2syhhiJLyPITVQ+GOOyi38/rw8wWsOFipGLpi/A/C9OjJ4JwI6/0HQYkKabtT4Z5OzOHL9S4DPdXW4sw7fRRf13BGMNN5wf7nIWSdv/36v3W9tlg1x+O66d6lFaMiLrPUVBHV8BHxDYQ7be5BRuEeT/px1pqjopY5XvwGKXUtN811Z5RsxC1BkOuk+2nwk/y3F/7Ilt57splebb7vTx29DyE0z977tC3tbyPCVPGV6jqNow8DELv+VoRtE0sJ4oUqWsVJxAZnO4wbQjvEg1aVsd1GgUu4rYBThAgRRsferPGkWK8XOFs0a6VDuciwLEKEUQj3WWB/2/9DCfD2DeNuwBiqRbgC4CkP6FSvp5NmgV1sEm4PmRhMuO09ZgHpndqacZqulvFrAnuuOzVJOjG0O2bCvWICA9Z0Z2TWztp4q92p8X65hpXoVvljh0xts3tkoHffluGeWyQ2IbvqdkOIZBppa/y8WVjW/Rpay+bidir4Lgtt6cONc8s4M3GsvYeJZaH+eGcK/ZGls7zpC98PwO17bmo+b6spVuujNyjIv+fXACh+vX/P6csVqt4KNlkBSfJX+7dSGwStFMoFmTYLfplMotze2REXglZKCebQsoZSCu36CKv7lm4Id+d+/EIZKyGRKQdRNdkhYTuwMKBW2YRwe76PllWyG/on78/MI6TPkQ1BpvAcBGPMN6p77Q8//cVoLfn445/tem21uopWcZOePQbYwsHXDZSrkYlOFVsGLdBiHmTHRLhnErvx5CpVzjMT710eshG7MznwzfGbsm5mJrXFGu6AYIbO5I8sPwHAc/f3b0k2CvblTEx+tbaOe9yUXDhPMdVedi5Osugi1cUnuVLHSZbMfS+23xzzZF1syek9QoQIBnOpLFpLCvU8S1VTWhQaUUaIcDVjFML9AHCTECLc5nMYV/K3CSEOBK7ebwbuAB4e7zQjXCp4ykXojYTbLGpDkx3V8JCJweqEvdeoMd7prZlqeScfNfvZ1X3jFnEH5W4tVb36zx/gxLc/A3+x0008rDe1Zjvfz84l8da6U21VpYGV7D4GsevMotU99vUtzW8zNJYKODODF6tWUjTbS9X9OuiWYrcxeALQWK7i7DWqlJWO4Zc6ideXTj8CQMK/ju+6uZXGmrRmKPvdtbubYf3j/wKAMz1Sl8LLAqruIZ2AcE8br0iV31rgQJfzoAUybQivTCdRLj3LMC6UTcbCZGwPQijytQra8xF2D8KdTKA3VFz4pSpWKoaVSSFqZv+hWjudChRPbzDhXiznEUKTczpTga+fNr247zvXWc/uF1rt07yFk2jqxK3hCev8xDQJdYhjxe5rKe+uYqmtEc5esKWDooFqaGSyMyggMubzOp4x4hkH5jPzCOmCVWQ+fWDo7WTgTL4/vbX6bQDHttHKpuab7zssJdiVGU+K93x2Eq1iLFYWcRcWkI7GCtR5eypNsqywuASEmzjJoJzCOWwydVKNJ989KEKEywlSSoRKUHJLrFRX0CrGXKY7MzFChKsNo/y6fByYBV4CoLX+KvDPwDOBE0AVeBcm9fxtY51lhEsGT7ts9NYLlZSyGyjcDY1MDFaqQkda72zvPrqbzuP0UbOf+e5aZRl3UN7oddJaKU68+X9QPVOn8om/7HhNrRniKAMH4RCxmRxusTuBw695yHT34jt2k0kAcU/sjHu3u94gtnuwUZSVtPGKZhHdUHVEB+HeEDxZW8SrCJyDJpnFSjn4lc6WayfzJt3+7d/61o400MnYLA1GI5tqbZHqglHW/PJ4sxS2itf/3a/zjrs+PNRY1fCbwaawXZ2f31pXxJCoy0CllZkMaIEudu9vuRqYhKWMqn6+tI72VE/CLZIJlNdJ3P1yAyuTQCYTiED9Dgl3KhZHa2tTwn02MBacTHQupp6+x1zrjy6d6HjeL1aw04DUlO/+PFo2SNqjmY4lrRyu6g54Vbw8jhjfos6RCZRuoDyaKf4hRBCkclxNwhrQnmEE3BgEKQBumD489HZamHvRzTPXb+v9hXaoBwp3eF+fSY7neLac65fw1ovY6VYANzY7Taaocbj4zuC2iJOsmBKb2LWmCi4i3BEibB9Spyl7RQqNdeQYA6ERIjyZMcqvy18BtwBfbXvutcCfAhVM3vEJ4PVa638e1wQjXFq4ykXoTsI9EU+itWimnKqGbho99YN9yKQee+dHq2Ve+L5v5uRLbqfyuU8C4NzS3UNRJuJdCt4wqN/9j82/q/d9peM1P6g3DZWYEPauWfyq6DL4UjUfK929aLTmr0PGNPXjJ0af4Cbwl88ax9/5wfWeViaOXzYLS9evI3SLJG8MnoSZBLH5kHAnUNXOg3uuZNT/G2Y6U19nk7vBKvY0teqHyif+ArQgdSCBX+8+rhcb+VqFewp/xfuO/b984MEvbDpeNVSLcM+a+mHVpuSOAl0ypQoyFaSUB+2n1Hp3ivpyxZyfByfM93QhJNyx7rIGmUgY4l5pa/1W9bGyKWQijgi+3qzTUhmFilHz+7eEAzgXpLXPJDvdpZ+x51q0FpzIdwbXvGKV2FSc9DUZil99DIFP0h7NoMqRCXy6z6+aypO0xudyHZMOlmqYjIPkBsJt2/iWJu6JgW27RsGPPP3Fzb9v233d0NuF9fvP3f/Ubb2/wKEefN8Vr4JW1tjUe4CknKHoLTczK0LYu3fjeIJd3qUh3OmKhxXXyBlz7aYbg7ttRIgQYXPYIkXNL1P21nHEpe/BHSHC5YChVwta67rW+ojWerXtuYLW+vVa6ywQ11pfp7X+sx2ZaYRLAl97iA013FJKhI5T9Sqm7rSHCrQRcnaf6eu8NFqNb+HBZSqna6x+8sukDiaIP/OFXWNEIt6l4A2D+oOGZAtLUz3SWafsF/IgNHKDCVNsryGZ3onOfst+HWSmmzwIKUnsTVI7fm6kuQ2DpuPv4cHppFYmiV8JW0jVkbQWvBuDJ/6yqV2XQXq0zKa6jLuWqktoFWM+20lwMkFP79XK8KS5er+J32W/+TlAK5PhUuELx1vpyn/+8OYqt3ZbKcdychcIjV/cGuFWgYGTCAi3lTUKYy/CfbJ4FOnNMZ81HgOL5XW0r7p61APIIEW8XSn3axprIotMJJCeAK2ZSLSuYaGTVLxS177asRiktYdtn0Kk43GkP8X5Siu4tvbbP0f1TJ3EoT1kX/A8vCLM5VutyIZFXCZQoptwe6JANjY+wh23EiQ8k9kRBj7a4VsQ98ZHzqZSGYRnMlWes+/Gobe7PvkiAO48uD2fUqkdGsoc16pXQejxkW2Aidgsdb2KX3GxMq19h4G9w6Wd6+TQDzGZJFlVWEmJDOrMs/WIcEeIsF3ERZq6KlHXJeIycv2PEAFGU7gHQmsdGaVdgfCVi+zRrl3oODW/2lV32g9CSuyUwFvZWi9urwxT3/vqnq+FCh71zV2V21E/+igITe6OfdQWKmivpeT6hSKW09nmC8DefxgA98Sjzed0tYz2BVa2d+pU4roD1Bcb6NrmbZZGgXvcGNCF6ZD9YE1k8KuGNLuqgWzrfRwGTyqeIckh4Q7N4qxsBr/eGcxYqy9jqVyXupcOFNL16mCi1g6VLyBtTSyoofTObK+P9XbxlQVDuG1vL6dr93Y5bW+EcmkqoEJKZAxUaWsqfUi4mynlQV9if225a+yq9wSzznXNtN+VaqGvwi2C+alAkVbFNXO+5iYQQaBso+O2RYqqP/h7XKqYa3l3ZqrrtZScY91tBZlKd32JWE6w+90fxt5nykIyVUiPSLgTVgq9gXA3PA8ty0zFt9+DO0TcShB3zf0gDFi0w7Mh0cfQbqv48Ks+wE/c8D9Hqnf8wGvexide/Xmy8e0pxFLEcZVRuGt+FaG331+8HbOJOZRVMJkVmVYmhReUCB28BOUkKStDqqqwMg4yZ8w4M5HCHSHCthG30ni6guWWSeuL230gQoTLFVHBUoSB8LWHED1UMx2n7ldRa0Z9k5nN63TsrIO3PjwZ24j0d/9Yz+dF0izgQkIxLBonzuBMShK33YZyBe6Re5qv+fkSVqL78rAP3gCAd6aliPsrRsmTud4KW+K2p6OVoH7Pp0ea32ZwT5s52NcOTie1chOohkDXa3i6gUXnD6AIvktokTsrSI+2cjmTjtzW97nkrRIX3Z81EzPfw9oIhNu0UxPY84cB8M6eHHrbncAjq0fQyuY79r8WbeX59LEH+47VtQpaiWYKOIDlCFR5a4EVXTbKeOiCLYMMAlXoPK+PLp9D22vcOHkLsymTrrdWzaN9jYz1uFbTZn8hoVfLhgjLiRwyuHbiLh0KtyPTNNTgwMFq1ewv7Lvajqw9S0O3uZKvlXFm08Y1f9Koiam6JuuMpn4k7CSIRkcg5HxpDSE0k/HxKdwJO07cN4Ra9CDcvi1wtlDGMgg3zO7lZ+581UjbJGIO+3PbDzTYxHG1CWTU/QoW41W492b2IoTCCzIrQpyfMpk0+4uDyxd2AlknR6qqsTIJRDqHEppsJBtEiLBtpOwsvqjwB793nv/x3q9svkGECFcB+hJuIcR7hRCbNwMdACHEPiHEe7ezjwiXFr72eirclojTUFVUQMR6pV1uhD2dwVsffmGl2mpOAay9h3uOk00FbzT1vH6+QHz3BImnPdf8/95WzW711Brx/d3Knb3HKDL+cis1PiQwVq57PEDiWd9i9v/Al0ea32bwzp0zPbgP3DRwnD1rFrX+2SfwdQNbdBJu2UG4jVmctcukesrgM/lLZ5rj62qdjN29yM+ECndteIVXlavIuMTeHyjc5xeG3nYncK5yEkft4aXXm3Pi7tP9CbcqBMZ6bdkdMmHhV7ZGHlTZnO8iIMjhsVeFzvP6M0+YFnPPmb+NuYwhmeu1ItrXiJ6E21ybS4sLfPjr/9a6ZjPZJuF2GpB1WqpmfAjCvV43hHpfD8KdjmVRorW9W3CJzZjggBWQrFSdkQl3KpZECE2hLZtlpWICPBPOeFqCASSsBPGAfPVSuF0bEmMm3JcStojjBYTbVTUsMV6F+9DEPDFXQ5BZEeKJQM3fdQkIdy6eI10DlU4gpKQeE2TGnLUQIcLViHQsg+NVcDyY3JqHaIQIVxwGKdw/BjwuhPg9IcQzRtmpEOJ2IcS7gaPAj25nghEuPrRSNB76N1R+BR8Xq4fCbYsErq6h8gHpyG5ujOHs2YVbVB2p24Pgn32i+ffca57Td1yzRrU8fO2sWl+mkVc41xwg/hxjWFR/+AEA3MfuxytB6um3dm1n7TFuwt5aS3UMe3bLyd5Kk33NU8w2IxrGbQZ3aYVYWvSs222HtSeoOz/9WE/CbYkEDRUY4K0bcheaxVlT5jP5SyaooJTCk3lyzkzX+2TjhrwVGsMTbr9ax0rYWPuNy3J7IONSoKbWSVlTPO/gTWhl8cjKY33HqnVz7ot2hTsZQ21wdR8WOiCOMiAhMiCmGwn3uZIhzDfO7mdP0Lqp0CiifXqeCyIg3H/xwD/xa195E6UwQDQx2VRvE67VUSKQtDL4DFbqC/UCWlvM9Oh9PeHkwKpRcxuoUh6/JrD3mDIFOWnSd1P11jkzLNKBT8BKWzBurWr+zoy4r0FI2AmcgHCLHsFE12LsCvelhC3j+AHhbugqsTET7n25OTIBpw7vKQAnawXWUzCZH2+5zTCYTkyRcKEWN54WVQdSjYhwR4iwXUw4E9xwLkoXiRChHYMI99OBLwA/DdwrhHhACPEOIcT3CiGeKoTYI4RIBf8+VQjxWiHE7wghHgTuAd4EfBZ42s5/jAjjxOKbv4djr30DF37mB1Da76lwh4pIqCrLIeoOY/v3o5XAOzFcT2r/nEkv3vdfXsfs2/6077iQNIQps8Og+oW/By1IPuv5yKldxCag9sQJ89pnPwJA8gUv6X6vZBoZ0/jrrffyly8ArT7MGyFn9gaGcd3mV9uBt1LAntw89dOeD4IECydRNLBlJ+EOgycAfj6PsDUiaY6pNWXIURhUuPvkowhZ54ap7jZEE3GzTaE+/OJZVV1k0kFmcghLd/RqvhRwdZmkNUEqFiem9rBQfqLv2DDVu/3cl0kHv7a1hYYKzOZE2pDosK5UFTvP65Wqueb2ZWeYTU2gtaDYKKJ8ELHuNlUy2F+tmkdInwsXTM95OTHZVL+TG9ohpe0sSlZxH7uf/P/51Z7zLblFhEr2dOqejJv3PFtcw3viYaBlkCVnTKu9VB1yidFU6bDmu71sYa0WKNzx8SncqVgCJ2g1KJM9CLctmq9fCYjLBCpwf/d1HUeO1zV8b2aaTJCUYE3PNp8/V1pmNQup/Gj+G+PAXCJHogEVJ0bFrVNzIOWOZrwZIUKEbuTiE9x20twf3cSVc5+MEGE76Eu4tdaPaq1fBrwM+CfgVuDngb8GHgQWgGLw74PAB4CfA54CfAx4idb6O7XW/SWiCJcddL1G/i5jxuUur6HweircUthofFTQc1gOUUcYO2zqn92j3Wm6v/mFv+a2P35+h3LlXzDpxfbc3q7xHXMJal5HUbirX/wcAMkXfQ8A8fkc9QXzWWrfeAiEJnHnK3puayUEfqG14HdPGGftWKBkb4SQEjst8FY7lcqzhVU++NBdQ895I9x8jdjUEKn8+42LuXf+DAqXmOwk6TGRwAsJd6mMFW8ZB8lp01tarZpgwSeOfhGAV9xwZ9f7hIS7VB9B4a75WGmjpm08rpcCWlbIxAyBnnUOUfDP9B3bk3CnEqja1gygQsItA9W6qXCXOo/Jes0Q8PmJaWzLQqgEpVDhdroNasLsk9C0bzV0op+Ybl47SbfTbC3jZBGyzuk3vo6z7/oQ/oXu2vqyV8DSvVXlsFXYQn4F9/gjAMT2XwOAFZxTqTpMJkZLKc8GaePthHs9ULhz8fG54aZirZRyke4OJro7UMN9KXEwey3KXuHuk4/gUyM+ZsI9n50mWzULb2tmV/P5xcoyq1lBrDB8K8FxYY+dQGooOhbni+tUBkCj3gAAIABJREFUHUhGCneECNvGXHyCb3k4uJYiH8IIEYAhTNO01v+ktX45cAPwC8BHgdNAHXMp1YBTwEeAnwGu01q/Ums9XoeoCBcFlU++Hz9ojaKqLkp7SNGtmtkihtJeS+GeGIJw33gbAO6xR7pee/8Tvw5WifsWjjWf84I0ZmvPga7x7QhTPsMa2GFQ/fpjOJMCe96QgMQ1B2msK1Qpj3th2aRqJ3qTCStl4xdbpLJx4gTC0tjXP73v+9nZeJdh3I//w3/nrff9FK/4izfz9i98cOi5g0n790oae1d3anfXex8MeqAvnkcLF2cD4XZksplO6peqWMkW+bKCYEdY233f4n3gp/iWw93BhZA8FUYg3KqukEH/cish8Uubq+P3LhzjP/3j77JWGS85r7h1kDWTDg0cyB5G22t936d57reVU1jpJH59uEX76//u13n5X/wn/vQ+c6vU1UqwP0NW5cQsoFHlzuNZdAvgJ3CC9HGhk9TcImiBcHoo3AGBFw0TVCmFZSC56Wa9eNLtXBVNOOZ5t2xYZ+PrX+3ab80vYYveJDdsFXautIp3ylzTduCmLxIplK1J1TW5UQl3kDYeqtqNB/4V5wETtJocUS0fhFQs2arhznSXy9RtiF1BhPst3/TDaCV45Df/Iz/9yWX2lsebDjo/Md1KKZ9rWcOsVFdYzwhU8eIfzP1Bu8tCTHK+uEbNgXgjUrgjRNgubn/oPmYLsDQB1hV0n4wQYTsYpQ/3E1rrd2mtX621Pqy1TmF6b6e11tdorV+jtX631vrS2gxH2Baq//ZZANKHU6i6h8bD7lnDHUPjoUqG5Mo+hmHtiN1grADcU52niFIKIcxC53S+VcPrrxhV1dp7aOB+my7MIxDuxnKJ+N7WQjr+1NtAC+r3fGbTVG0rHccvtep0G2cv4ExaA2up7VwKr9ip4pR9o8if9j7Hnx9/69BzB/DPHkMrQWzPYPUfQGankDGNt7zSk3DHrWSzt7FfrmElW6TNmjP13/66Uf+XGsfJymt7phFPBam3ZbczPfSl738Tt//RS3nHXR+m0Va/r5XCb4AVmI5ZKQdV3lzp+qXP/DafX/lDXvnBn9x07CAs//KPcvKlz2z+/1zBfMbJhDkv5jPGqf3Icm8jtzDVu51wy0wa5W7eE/7ehWPcU/grznif57cf/HnuPvkIKiDcImuuJWHbps1YQLjvOfM4Xz51lLJbROoWUbVI4jUMAe2lcIf7wzXnbKUUBApys011PrWBcE8Fx0AnDClpPNadldLQZeKyN8ndnTYBuMXyGt6iKbkIAz8AnmMU7pnk5t0N2hGq2MUgqHPuF3+WW//Y9EsfJ+FOx5JNBbsX4W5cYSnlN8/t5/+y997RkmV3fe9n75Mq36qbuqe7p7snaYI0I2kkgVC2JAQWsv0knmSMjXj42Q8so0Uw2DI22LIxYWFjMAZMNBiMCBZKYCEQWEJCwyjMaGY0mtg9oXPfWPHkvd8f+5yqW7eqbt97u3pifde6q6urTtinTqj9/YXv93Un5nj1/1nhdfcp3nLnaFD0cuDaNnNd88zInykA6+EFumWbNBR7agmaBg5qc49uOoKL3U0CR+DOSspnmOGysZy1z917jUAkl/49nGGG5wMuyxZs5r393EPaapts7XyVNFBoEqwxGW5L2GixhXDXl0eW2Q5ZbWAVNdG580Pvf+qxr/Rfn24PCHeytgporAOXINzZhFhPyESm6+dJTp8Yfq+XYtUHk33v9tcAEN7z18QbAc7iZBE4q1ok9QeXfnSxg7u0M3Gw5+dIOsM/OiVrsI5I9mZpFD9qvjP7yM7fTX//ZUmy3gQR41nDhLtgFVHCpJ+UHyPLg8/l/FWARmW91YnuDY17KxpZ33cvGc5Sn0n+isQ+y2+c+Lf87B0f7r+vu01QApnZBMmSR9rb+ZHSi0POx0ale1Ndnmd3544v03vCJ1031+OpTL07L4c+OmcI94mNc2PX7/tmVwfBJqtSHbFRG4df/tKHAHjn0X+BEJq7zj6M9gNAI0qD71c6kPZ8kjTlH33iO/knn/we/LQ1lFl2RAkdZwrn7migKK8+kXGWre5m4myNpX42vbTta58vmus/yQn3SfNdpytn6HzgZ81nukvRGk9yr8r2udrbIG1ugtDI+YP9z2NPUAqhMUZwbSfkpLoZdNF+F/9UDyvzmF8cU/q9X1S94kA0bYw+RWSD/dRbR19R/J3Pr7NWg/uPwk33b0x9krzYNUEd6/C1/ffayQp+1VQtJI/tTttjWjiQmhO4YcNar0nggj0rKZ9hhstGPQtGtkogtED3dp8MmWGG5ypmPtwzDMH08IIsl1CRRosUW47JcMttGe764sgy4+DUXJK14UzGF8882H99vjMQFoseO4UzJxHOaNZuK3KCkvfAbseJN76BR978tv7/dRyRBmA3BkTJvfXVCEsT3P8V4q7GOTD5eKxqlTTrR9RxRNxMcY8cnLg8gL24gIoFqj3wyOilbbSysJNDaLE3Zevkyaxv/Oh1u1rernrEzS5CKDx7mJQV7VLf2zj1U6zyoJRe2DbShbRtzrMSPkV7fBnwfJat7G3LcAvlscDLAHiiOcgW9+3UqobQWJUS6SX6n//gvs+C1cNJjoDVpR3uT2xJBz2Ci+Y7D+/8JADnO6YneynLzl5TN9UDT2yOJ9zpBUPUrUMDAiFr5ljStfHr5Lhn7U6c9GreesMrATjXXkUFAcI2Pf/97bkS5Qf8wp1/RGpfJLZO0U7P44kBUfVkCeIsO+6NIdxZQMCOTco2zUvX60uILFhV3Ea4c3/vNDGkKz5lFPZX3vf/cur9/43eJ34HJXqU7fHBl8NV0+qw5m+StjtY3vBxha7MbMH2poadl6C3oy7+X34EnQqsrChivrS3bPlOKDtFvH6Ge7R6J7LBfo6VSjZaiocOCz53s6TUgvj+v57q9g82Nd2iHgpQhayRZL7syeMPTXV/l0Ih+71Yt3WfcMtZhnuGGS4bpaySrVXK2hNb6zstPsMMzwvMCPcMQ1BdH1mw+qWx6Am2YNIBUlTPB6n74kuXgtMoEW8Ok6QTm0/2X6/6g8ygf6pJ8filibzMvIj1GMKtk4Q0GC6XTc89DgisxcG2hePiztv07n8CtMA5dJhJsOo1VCzQQY/kxH2mtPvozplm+6DpW4wfurv/Xpi2qXADL114A1g9msHu1L3P/6O3cvrH/jsAzrWj1mVjx1wrkWRl8AV7mOTk3sbNoIeKDPEdWtcTpO0uSim0DClNINyubaOVTZAMzm+UJGgZcKRyDVpbQ+d3u52aVauQBjtnmD53OvOgXn4zAA+u7M+3O/zCJ9GpuS5yf/SLHRMMOVA2hODGrPT1TPvC2G3EZ88iLI2V6QAAWNmxqPWd7c0Ctc6cfZDrM8XuC71VVBCyPbYlPRvlh/zOQ7+FVuZDZa9Q2FJlULAqyMxHfVyGWxRKIDVWRp51GCIsjXDcQYY7Gb5HlnOSmQVAeicvEp+4j2TNlKNv/PavoWVA1R2fVT6UZbg3gyaq3cPyhn9qAk9SDvTY1oSdkAd1OnGP3l9+AgCZCpxE09hjP/hOGM5wj1afRJbATp9b2VAv1oQONLOvUW3uXKWxVyy3FBu1wfne6HXA6iCXjgIQn35sqvu7FHINhnVbsR40CRwQs5q9GWa4bIggJLagl/0c6RnhnmGGGeGeYRhpLzC+yJUqIChESUauh+FIx5SU93pYox9PhL04T9IezmKe7Z6BtIRI5tkMjaBT/Og9JF0ovmi88vdWiIw0KH+YyKv2Bufe/eaR5ZMzJ7OxDJfBe1c1CNfM2HbKHOekKr3w5ECB+eprJy4PUHrLNwPQ+r1f6b8X6S4FWeGqslFtfuDiqR23kWPjs4OJqXX1C3a1jiwVSDNBoJI9TKgrmfLzSnsDlQhkaRvhLtqkXZ9W6CNESsWZHFwR2iVIB+fhdGsNITSNQgOpqmxk5xdAbRhSamX9/1atik4Faofys0ebDyGSeV584GYAHl6brCI+Cem5xzn3I/86HzDBQ8ZIYaVnCPfhqgnEHKktoJXNSm+8nVt8YRWnZg1npDO1/nRtPEnvj0G2mHMXqBfLaOWxHqyhwxDpDBNfWbBp+xFd+RBf03gXWpmbrbzlHJTsMlKZNO+4Hm4AaYOdEW4RJeTOcKJqxluMh8njcjkTbgs0VlGTdBRnv+vdxJsmKNT+8hlspWgUxms3uLYNaZF23CLt+sjScCTB9yTlfQhT13OdgKhH756v9t8v9Zy+iNw0UPWKeIlGWXqsNkNkaeRzrKTcjiFwzB+Aam3svMIeMd9UrMwNru8vnzfPscrRFwKQnN3d829aUB3TJrNhxzTDNoEL7EJ/YYYZZtgZKggIHQjzZ0l7us+SGWZ4NmJGuGcYgurFyJKLrGbqxVGCM5Zw2yBSlB8gnN37PjhXHUDFgnT1bP+9tfA8Lku4Yo5Okllzfc5krwpf87pLbjPPcKtgmHB3fvfnaN41ID55z22a+RBbB4az2O6xI/3X3ktfM/kYjhly7X/6oySnMgXmYzfsOEb3lq+ldLxI89Nf7r+Xii5lp8qxrHT5kbW9Z2t3EmrbCqtUJFdcKDnDGe6KYwj25oo5J9sJtyw5qF7E+SwDPLeD37HQHmEa9P9/OutlXiw2cBicX4A0sxqTmde3VTfkTV2YPPFei07SsI9zfcNUDDy+cXbispPgf/qjBOdi5t9wPYWDLvE5M8Y1PyPcc6bEVUqJpeaGggRbEa93ceaH7ZPyY1Gb49cBSFQKMmChkB23qtGKN1BhjHCGH8my4BKEpjzvn7z8nTSkISfVLYS77JSxlKlekN6EEm2bgQhYlCBdsx9RKJMKKG4rpV0s1RBaY4VQf8OtLP+9v0HvVEBwPsYuaXQsuP4sLJUmuxNIXaYdb5L2IqzScCCgl/Vw7xXzJZN+DcI2/hNtpGsCBbXA2mm1PaNeKOPGoCbcXrEN1nOMcIsEAhcCNysD7ezeZvFS0EpRbWsu1Aa/FV+9+DgAx47dirA1ycXxga0rhfz4Np2EVtQidITRX+g+teJtM8zwXIMOQyJ7C+Ge3VMzzDAj3DMMIw0SrHKhn3UsRakh19tgSxchFKkfYrm7v4zsQ8biKzk5EMjppheo2cuUrAa+MmV+yQVDpCZ5W29FXjJrRKcGiJ80GRRv3oxPZX21fX/vbXZj3gtu7r92bnrZxP1V3vkenCqs/cb/JD57etfjLL3wBuKW6ftWSqGF8Xy+ft4Q/8c2L00eVXMykdsJslSCGNCasjNMqGtuZue1br4XWRkm1Fa5QOrHXMwCFnPeZHEqiUekBoGPs20z3qVyg5Ks46cDL/J01QRDrAMm0GHNGwKajikT/8hX7+TXv/inJNYK19Zu5KYlc+4mlXvvhOScIfSN9/4r7EqBJFNGb0ZNtBYc3KJK7Yo67WQC4W7GOEvDGV4r885OdzhPvdjs72DZLOuJGt1kAx3FyG2E2yp5yEzI6XBtnlvnjar6ajAgJxW3iqPMMmIC4daOpJDJBFixHhBuKYmc0R7u+WKFYggCgTVXp/49PwbC7KP+xpeghebFjykOVibb0hXkPO14hdRPsMrDgYmuNxjPXlByPERi8fd/9Q9QsaByi6kOmTbhrnkl3ATSCYQ7kmAp8ZzJhmq/i1CCwBEm0wtTVQ1PTz+KnQrOzxlXCoDHm+Z5d8vyUdO20t1dS820kOuPtJyIbtwlyu49dQnBwxlmmGFnqDAaynDr9vSCdzPM8GzFjHA/j/E/7/kUQTw861WhxiqX+qWxxUhjy9Ey1Tzrnfghwtv9ZDcv1Y4zgZwoSUjlOsvFQ8y58yTCELJcFVsu7ixGlkNaoMLhlFl85izS1Sz8g3cAgzLfZCUjeoeHy8Ddm4xtmbe08/GIQom5196GfzYiPn0aYWnkgaOXHKNVM0ROrZ9jI+giZErNneOmJUM4z7RNT7NWikdedjMrP/AtI9uIH7qr/7pwYPcltLJSBgRePPAyzlHNlJ/9LCAhK8Ml41a5RBooVnvmnMwVJpeUW8IjUoPzkAuRHawsUHUaxGIwiU9XTUm5nZ2HPDucrowGHv7DX/8kP33f+xBCc+PCdRyuNdDK4UJvH4T7gjlO+9jNWLUyac+kKpvhJkKVsa3B+S9bDQI1Wg6nNldJQ4Fz1fD1KedNm4Jqbo6skyNIzD13JFNBL1l1AtVEhTHSHT6nslhAZuXei6Ua3/WKtwPwjce/vr9Mza32FbOFN0xs++N1zLknreBECqswqFqJHCgkw8Sx7HlU/MzGqTGPrDY49D3vAqDytncSLlrccAYO15YmHuecs0zAGmmgR3QBAtv0Xe8HhzeKHHrcpOtrf+vvmH+D3VfZ7AZzhRJeDIk9frtRfpr2Kdr3TINqGZIpLIeXNb7BvNeZnrJw/KixlbtY132tivOdC2gteMHCIaQrUP4+Sh4uAzqz22t7Pr24TeJkGgn7DGrOMMMMBiqMsS1M1QjTrZaZYYZnK2aE+3mKP37oi/zEl9/L3/m97+2/l/siy2qlT7hLoR5bUu5ZhoSnYYLl7b6J277mJgCSUyb7fNfZEwiZcs3cMQ6WDoHVY6XTIm23jJXQLuzGAIQNOhwOHkQX13Hm7C1CVoacpWtrIEbtxrxXfiMLb7mZI7/0a5fcn3O1Idj+I2ewK3Koj3cSZFYyna6e40zLTOoahTkOVupoZbERGGKXPHw3SRdW/+gedDIshZz7IR/54X/MsY/8n0vus7/vsiHVxQgqzjApq2fexkGW2dnqKw1GzEyFsJYR7oXi5Ay3LTwSPag0WN3SF90oLKBlp+/FnaytmnOcZautZVNan66eZzsCvYaQJg37goWjWbl3nc1o8uS4+Qs/zOZP/8DI+8nqGtLVyMocVr1GGmi0UnTiTWw9HEyounVSMUo8oq9+HgDn6DVD71uZCFoeMBqHIDHHcWzuQLaPBqlooeIU4Q4He2SphBWBVh6ubXPbwePc82338P2veUd/mXqhtoVwj89wJ47ETaDAASMGtuWeDW0jmLUdtdw3ed6Q6rnv+nfceMenKb7hm+nMuSy0NVfPTRY1XC4eRItNVARybviaCWyQWqDDYMLak/FN5a8D4MF3vwr3RhMkq+99MzvCtW28GOIJ7TKxnbkUBOOdEZ5KrPzzb+Xst73psraRk8zvve6N/MhbvtO81x1vs7gfpOdNVUmzLLj7nNHQWAtWEKpCwXGRroUKnlrCnfa6aDShG9BLWyS2+U1TzZnA0wwzXA50lHDEcfiVV/8oAKo7I9wzzDAj3M9T/PlJo8x8Nv0MJzMiqpuroAVWrdafZJeiAbneCidTSlNRiizsnnA717wI0MTnTNnw5540peWvOPxCjs+Z0up7zj+G6nSRDrsisgDSFuhomHDH6z2chQoyL/PNlKOT9Q1jU7TNbkw4Lsv/5Q9xb/naSx9HJpIWXIhx5kaVocehT/zXznM2U+1cLNaRUiJ1hVZksqLh3Z/tr+N//Lf6r7VSdD/95wAUX/u2XVuxwSBrXQyhWhjONs5lGe4oE0mSlWHCLatVtBK0Mj/qhdJkj3JHeCR6MHFe980xXV1fYKm0hBCakxuGUCcbTezi4BzbWZVAnvnOkaQpyhpkjG89cBwAV1TpJU2CO/6E0+94FWfe9Vo2fvy7B/v+vQ+z8tt/NFL2m6w3scuG2Nr1BjoV6NY6vbSJJ4eJYd1toKXfDxLkCO40wY7Cy4c1BsTcIghNukN2MErNdXrDgulDb3gLYPXMveQO30uyUsZSAjceXKvblb0bhWo/WyyKw+e2v09XUog08+4hChHEhSybpxSBC94YO6Q533xH+bMAQDZMAGyj5jLfgWM7BMQOVw5RijQg+tUdOfwsQ6y6kysBJuEdy9cD8LgO+NCqcTiYuwJcrRCbXu3tiJKEOIuLKP/pJ9ydv76Pzn37U+vPoVrmPMhyBZlpGEyVcG8YQt8pDGwgm/EaLpk4n2ejwqfWZ033fJQDQkI3XSX1MsLd3vs1OcMMMwygogTLtanmFV9TfJbMMMOzFfsi3EKIuhDiFiHE7ZP+pj3QGaaLr6x9pf/6Lx+7Dxh4B8vaXJ+klsIBud4KN3tPRwpZ3B3hBBDFMlYR4gumB/Urq6a0/HXHXsQNC4ZwPbDyOKrbw/J2XyYqbImKBo2oWinjj31gEWvBZBJzIat4dQOntgdp9TGwr71p8LqxO0u0fsn06gXOtzPCXTITTpsq3cSUW4cP3Ntfp/e5v+i/bv/mT7LxmceovWgB68j1expvnrUuRFBzh0nZfKb8nGTCJnJuW1/ynBljtGr61ZfLkwm3Z5VJ9ICEbIYbaC05WKlzoGSO//FMnTxtdrC2qFfnftbJ2rB40qPr5xAis7RSNtfNm/NZsGqEqk33439A+6sbtO5dZeX3P9lfL27GJD1B8vDdQ9tLNrvYNXPNWgtmTMnZE0S6RckaPrb54jxCaJ7YHB6Tf8+XkY7Gfekbht4XUmK5oDqTiViURmgtuSYjrzXXXD9prBDecBAoD5RUw8le9PViFecSJeWRLfFiOFQ+QjECPytdb0cBkQ3umAx3wzf3n7U8apG3UnUohVDpTc5cXDd/hEpWcZ0L4uUI8gzxDor0k1DJ3AhWnJSfevKXzHbC6ff/FmKIxpSU9+KQJCPcV2K/e4FWinA9Jg2GhSj3itwnV1ZqiGoD0Kje9I4t3TDb7xbggbVHAfDVBiUrEygsuqjgqSXcyjeEGyCWK2jX3DszReUZZrg86ChFujYys4ecEe4ZZtgj4RZCfIMQ4kvAGnAf8IUJf5+f8jhnmCJOba5xIXwAOzEZtofXngBM5hVMJlbOZ/2l4YBcb4Ur8wy3RhYnKCNPgFNzSNYMuXuifRKRzLNUqXHbweMAnNg8TdoLkHvoDZeOREeDCVt69jF0KnAOHUIumGNJN82kL173cRYmK23v6hiuu63/2rvu+K7WsbJob7q5xl3njZ3YrQcNyfREFV8Z8hKeeAyrqHFqEDx8sr/+5gf/ELsMhz7wF7vO/OfI/ZaLke5bK+VoZN7GqmvIj6xtFwJbyMZtiPJyZTLhXigsk8pNkjTri46aCFVCStn3t86DDUnbx64OgjVybgFhadJ1M+Fd67V5y299F+/82N/tL2Or+X6Gt2zVSEQHlfmvL//dV5P6gviBL6A6zb7/eu9THxkaY9KOsOvmO7Aya7j0/ClS0abqDHsuL2cq3E9sDmfd/RPnKB4uj1WJl64g7UwmK2Ea4KQH+73itUz1XcUaOYFw16LJ90LR9gYl5YXxGe4g6+G+vnGcQgS9rHS9FfhENjhjPKXne+Y9e0xw53wl03A4+dWRz3LctHiUclbqnQvi9cdzGYRbZ2JeK1ZCalWIbHhheHn38zgUYk0wpqS8E4X9zLf2pzeR1EGP6P6/3tM6yaP3ojMP9fiBL+5737lAmixXEVIiHZMBnhbSLIPu2w1Od8zvTcwGc05GuAsuKnpqZd+VH0KmyC5kgsoqfdRM4GmGGS4LKk4RntMn3Np/bmhdzDDD5WDXs3YhxFuAPwJeCoTAo8BdE/7unrCZGZ4B+Psf+T5Sa52/ffxb0VryRNv01+Ul17KxgMz8ed14QK63wsv63YhBlsZn1SbBbpRJNs0DeCM+Tc0yomEvWDiEVjZn2mdQvQiruPsstHAs1BbCrVZNiaW1sIi1aAILqtk0me9WirM8WV15N8jLLgFKr//GXa1jZcRfba5z18odyGSJV2RkpmTPEWszeY/OreEtFSkcaRCcysjp6RN0T7SZe/XNI6XwuxuvIbvFyCgwb8Vy2ZRRa7+XLTtMjvLMPJni+E4Z7iOVIwiZ8lCWbdsIL+BivqsD2TWV+12n3RirVh5a3yoK0qYhYf/pr36fc+qvwBpMgEtyMLaaW0eJDmm3h7A05bcYQbHun32Q5MSgSsD/4oCIaKVIehp7wRDrXCG9d+5JsHwahWGbq1yF+3RzkOHWSUK4mlC4frxQnixYqN7kpuIUn6sKA//0ulfNtguyMFwtImtmnPV4MuEuOR5OdumLQnnsMr5rMty3LRynEEM7J9xhj8gWfY/urWj0FEpo5NIRLnSa3Pqbt/KDnzAZ5TMV89ORPPnwxHHdvHQ1jY4h1tY2R4CccO9HmEt1zH2yakcoAhJX84qWGtE7uFx4CfhjCLcfhyTZL6cOptc8fu47/iYnvvk7aP3Kv9v1OtG9dwxeP/KVHZbcGaqdEe4s2CYdkwGeFlSzhbA1BfcI6/Ep2qEPVpeFgqmkksUCKtqfiN5+kTS7iMLgvhKZNoWeCTzNMMNlIQ8ei9yy1X96K4FmmOGZgL2kyX4YsICfBBa11jdqrV8x6e/KDHeGaaCVnGVR3M773/TtWGmDCz1DjnJfZKuxZMSXhMZJ9YBcb0HBcrFSDUogS+Mn+ZPgLM4Tt002I6bJnGtIlJQSW82z4p8jDWJkcffEUjoWOh5kSNKsBFjW6qZEUmrSdov07AmT+T5yZNKm9ozi6/+v3Y0xI/7Bxhqb+kGuKQ+sx6pOHZWJc8XNCGepTuEF1xK3IL14iuAvPwpaUH7zN+1rjDmJLkRQLw6fr7lCCa0FIvMx3xpMgEFJsd3cRCuXwg6E/9qG+V6/cuFxALrqInO2CTQcrpkxrPZMtivtaez6cM+0XbJJWiZj/clTf4xMBv3DWtksFgblzfVCHSETwl4P6YD3td+AsDXBV+4jPmEyr8LS+A8PfL3V+nl0KrCzUnI7I9xrZ814F4rDhDtX4T7fHYizqZXToAX28vj+ZavgkPrjPa+aQQ+E4tbFQYVEo2gCGDoBMUK4zWdzOxDugu0OSsoL46tNuragEMP12bnbzGzB2mGP2AZ7jGJ4o6volgTCtvmde0xrw5+c+R8AnK5m9+/pxyeOa6FU4WBWneve/PKhzwIny3DvI0Ock/Q120fJDqevK9N+sEnrv/3Inre1E7wY/DExv268JcM/eoi5AAAgAElEQVQ9JdE0/1MfpHm3CXiu/Nrv7nq98OEByY4fe2Tf+9d5dUvWeiIdOVXV8LTTxfIEBwtHCcV5Hsys/66qmHtIloqoeKctTB/RWoC9PAgeWiUTbJimOvsMMzwfoZOMcDsuwppue8oMMzxbsRfC/VLgXq31v9Raz+6eZzFS4VO0TVatJJfZjE0pucpKrvNMLBY4yYSSctvt++hu922+FJwDy6hYEK+cQYseVWdAujw5h69aqCBFlnZfqi5cG7WFcOfHIufm+321abtL/PA9Zgzb1KX3g8ZrrqF6S2NiGe92yMYBEJqN9VWEjHnhwsD3e86tgxXQ7TZNBnZ5kfKb3gZA85d/DP+uOwFN4TX7JNx1Q6KLETS2ZUGllKBdRKbyLuvDVk/21SYL77VaSL1zNcNNiybr+8j6KWP5Zq1xoGgCDVdnRH492EQ111CJwJrfVr5e9Ug7IT93x0fwrUd49fLfgtRcqz/5ql/hP339D/aXXczIsd/rIV1DDJ2aRXJxjfiUKcWv3rxIsBKjNo0Ce3rRkG+rYda1rjJK9a2L5h44WB7O7ueiYBe7A+Xi5JxR2LcWxltiyZKH8sdnWzcDQzBff3wgczFfqmKlGqEFchthtrKqgPoOntVltzAoKS+Ovxe7jsCN4VAmILeZZW7boU9sgxxDuGs9RSu7tP/Pk58x29eSJE05UzMZ0STzoR8HKSWHNyB29IjmQGBnPfn7EB3L+wGbhXWETPjTbzUtB9HjJ3dabc9wE90Xd9uKYGsPdzSdLHB47xcAqN5cJ9pDtr77+S9hl8HyNNGpyefiUshJZl4CKlyJCvZhlD4BacfHKlhc17gWIWM+9NVPA3BdwzwvZLlsxAv3oVq/H6iNiyRdKB8bVF44WXAtb1GZYYYZ9gcVD4LHVkGQbs6qRmaYYS+EOwUmN+zN8KyBFj4l25CuhnuAkIyMNDOV6kVjbaQzwj1OpdyzXePrC4jiHkvKD5tJzsaDXzRe1N6AcLuiRKx90lBjlXe/XeHY6FjxyKoRfsutXfJsrVWUxOdXiU+a3mnn2pvHb2gPOPir/5sjf/i53Y/RtpEORG1DGOqFwXEvFE3p1an7Pw9a4Bw4SPHrv4XiEY/1D3+K4KGTuPMW1vzufMm3IyfRpcBYHo2MTXvIMEJIjdiWAbeP3ABo7E4Xl/mRdbfixQdNIOOJ5hnuPf84QiiO1sz5bhTKaGXRjDZJzxpyZC8OZ4mtapm0F/M/HvjvWMkyP/WW9/CHf/uD/KuX/jzfdOPLuSG7NgGWy+bcRkGIzEqknUaR7slNzv3iRwGovvWtoAX+pz8MgMquD5n1pcuFwyA0QRagObTNV/pYJh645pvPN37ivTz5j99jxrp4YOx34CzWiVvJiDo6DBTKX7TFt32hWDNWXYyqjMtMIby+Q7lt0XYpZOvLSn3sMl0HLA1e5kiwnmWYu3FAbIE1ht9V/JRW0RDzJ3umRF/bm7zxt/8hkZeQOpp0Y2dF56s2NJv1Ydu8KEmIXPPdqH30cKtul9TWKNt8l4u1AyaL0p1eHFgnCV4IrcLo9z4kmjalsut01VTkFG+5EZQgOXnp8vB0/Tzdhzep3n4N7rxLdHZ13/vPSabIAjxGNXx6KWfVC7FKDrct3wDAp878GQBvvPbFZn9ZlZRqrozfwJQR3Wee2/WbXoRWhhgUa7mi8iyfMMMM+4VWCp0KZMHM3+yqQ7I5E02bYYa9EO67gfFNizM8a9CLQ4SMqTgma3hV+QhYbdZ6bVTTTJ6tzK5IW+Ck4NmjGe6C5WxRRt6baJp73S0ArN1rtPUa3oAkFKwyqeqiYuMHvltI16GdaN7xx2/hL07c27e5sbL+49prX0L3sR6tj/8JAM62EtenCpYnSLpmkl4vDNTNlzIF79VHvgyAfeS4WeZvvom4A51H2hSPj8+o7ga5n3kpGq/8LrWHFSWMaddHeAWsAni9iJq9sy/6UqUGaYlz3TPce96Q6hsXTBZZSonQZTpRi+ScEU7Kvbdz2HNVEl8TssYB70bKnscNi1fxLbcN228BXJX1VydBgvRMEMFZbKCyY6y9eInSN/49AIIvmgl2umoIZ251JWwby4OkZSYEh6vDGe6S40FaZDM0hLtzxxdIsgSYdeDQ2O/APXoUFQvSs4+NfJaoBK3hUHUQuDhQqeNlhFduC17pzNe7MSFjDlByPcqBRguNXLhq7DKdjGAnZx4HYCProe5EPpEDcoxoWrmn2SybLHhirVDVLzLrchcAwhOkrZ0nUgc2Nav14XL4ZtAjssw50vvo7VM9n3TLdXqwujT1nuP0/BNIJVgd8wjyk2hLhns6Gdl0fR2kxrvNtJnED3/Z6A2MuYZy9P74t9FKUH3bO3APLRKu7P/486qB3GpQes5UbbrSXowsebzqqHn2t+X9kFa5LqumyqukcieJK43wq+Yadm++nQomSOi5BYQ9K3+dYYbLgc7cTkQmpmvPlUiaT03lygwzPJOxF8L9U8DXCSFec6UGM8OVx/nMY7TqmgnOtXWTfbzrzAnSdhthDTKc2hI4CVTd0ZLpgu0OyljdvYl4uS97PQD+w8aDO7fGMtst4Sa+8QOv7s5uC0B4DmlGGj5/5gHSTGlWNkwWcv4HfhJhadr3r+M2RF9I7amGLFjorDdyvjQ4voMVQ8C6TxrLHOeYyQSV3vLN/WUqb3zTvvcrbJvY0ZQnEG5LFLDiFDlGJArArtiUeorFwvis7tCyuk4r3uChTP0+V2I3n5XpJi3S86a0295mOWXNN9CJwE5a1L2ds+lHsr50FW0h3AdNQMAuaQ7/3l9iH7oGq6gJH3scgHQj0ylYGByHXbKQXTMhODAmQyx1hXaclVBvDspN7QPj44/OdTcCEN8/ataQ6ASB1VcoB6P6nleLbNdD2MhErOr+5GxjyXGp+hB7k33r+4T7gumdbblZhjvyiSwQYwSiCz3NRhm+cPoRhFC85ejf5Bde93v9z92itaMau44j5puac9sIdyvrGwejzL1XKD+ALdfpkeoS0hXm/SkhOWX6oTeqmm443MvsRyFxHjAIpkPyk80mdgGcG0xvf3TyQS6+9+088sa3TrT7ih42BWeFV3493rXHSX1Beu7xfe1f+T4IjcieSdNWDU+DFKtSNAQ7Nb8nFTHQ0ZBVU+2jmvvP0u+4/5UzhF/YYhn42AkA3Fu/jjdf/VYADpTns8DNjBzMMMN+kfvYy6xay56vkXSeWsu/GWZ4JmIvhPsO4D8AHxdC/HDmt70ohJgf93eFxjvDZeJixzwM83Lmm5dMdP8rFx9DdbpYWzSbUlvgpFDzRkXRis4WK6IJ3r+TYC0ewq6AOmUmkkulQR9v2a5QjM2EJ5+E7QbS87CzZ3qUxn1rF5l5NlvLV1M6boIMxeM7Z2mvJKyiAxl5WigOju94w2R6oowQ2deYknfnha/sL1N553sua9+RA6UJpck2BZxIId3xj4Sk6jLX0RyqXjpQ4coKQdrmQs+IQN2ytKVPUlQIVIfkointtg4dG1o392uuRCkLhZ2V5I/OZecx1siCCfo4RwwJ3urv7S0Vic5kbROZH/DWgItVdrF65uIZZ3nmiDJBajKASXtAfK2rxusAuDeaMtno0fv77wV/+WHCL3ySNCPcW9EolHGzQIjYRrgvxBE9F6o7EO6yW6DiQ1yY7FvfcUwJd3rB9Ko3+4Q7MOR323xIdZo4saBZFtxxypQ3v+TgC3jtNbfgpuacuWWXtDtZWCu98ASWEqxUh6+pzaBLlGWo1X56uP0IZ8t1eu38QaRnoSYI1e0H6RmTWd6oCC50h8vmg3Rrhns6wmK5J71zk+nt791xB+t/bhTg40fuHbtOdPo0lqexDhzDvclUH4Rf/sy+9q96PtIeBGxkwZuqargKNVbFXNtHC18LwLHKjf3PZXbf5a1A08Zjb30zJ7/tvf3/py0TXJbVBj/65u/gP7/6t/nOr3kr0hGoKSrPzzDD8w26k7Um5oR7aZE0FPtqH5phhucS9kK4V4B/BZSBf4vx276Qvb/97+L4TczwdGMlK/dpZIT7JVeZ7OOJjSdJu/6Q93VqC9wEamNEwQq227ciknssKQfwDlSwLhoSc3BLeW3ZqVCKDDmw5hpj1x0H4bl9wt0KO6hOF+QgYwNQuNaQMXth99udNqxqCembSMXSFnutGxZMplevryOkxjp0HWAmwFd959s48O43jqiH7xWRKyhP4AeOLGBHaqL3ebdaoN6F43OHx36+FUVZJdZtNoJ1SIuUvUEUp2BViVSHdMU8IrZ7PMu53C8cDmwTMNuOpXKWjYs0suhl65tzu9Xf27v6AOFqhFYKlesUbMmsW9Uijp+itRgRlAMTQIh0Bx0GJFsSmqI2Pq7o3PwKQBM99mj/vTP//Ic4/0M/iNLpCOGWUlLMfLZlabiqY7XbpFOEcm8y4S7aLuUAwuLkx3nXzVTFL5jvvZ39v5cYwi2UGBLqysvhW0X43Sd+HIBXXm0I0p//vd/jY3/rz7HKRdIdxpX3yze39UG3Q59cdH0/tloqiCgVHKzEBFyO15dNz/EURb6Sc08CsFkeBClz+HE0GH84pQx3J8CueMhSFbtCX7EcIHlyvPp4fG4Np2ECTd5tJjAX3r8/R07lB0PtJLJUIA01Or7871QHPVQikHPmN+dj3/Iz/MCtP8NPf8P3DfaX2d+p1sZl729k/0oRZ3P9/HhUz0duKcx68/VZL7lrTfU6mmGG5xtUJyspz4LH9rJJJqRPPPi0jSmH2lzl3LvftKOd5QwzXCnshXBvAOvAWvbvTn/T/9WcYSpY7ZmH4XyWXT1eX0Irj9Od06huiFUcZAZTC+wE6oXRRsaC7ZIJDSPcfRDuY1fhbiiE0hzaQlyqXoVyNgeXc7svlBCFAlILrFSz5q+jul0sZ7jEdv77f5TSsSKNf/pDex7vtGDPVbB9Q0C2+lkfqtbRyka2ethlMTTu+vf9FPM/9POXve/IgcIYNWoAVxYohBpZ8sZ+vl7xqHfhpsalM9xlZ45EdGnF61h6mECW7Sqp6JJsrJv2hW2e31ZWQl0M4VB150qEguOilYUVa2TWL1Z627up3FDl4E/8zODYrrsOFQuSk/eRNpsgdL+n3eyzjBNohPKMYvs2FK0Kse6RPPEg6EEWeVL5tqzMYZcF8RmTTU4vniLa1ATnfbROkGJUtK6U1ViL8vC9tu63aRehsEOG27Ysqr4mKIwPliilOHnA3Ky9r5oy/1YmwNCLfSI776ceZCDySVM41CudlbcXyxyfX8aqlUmDUWG4HOm6IY2twvAy7bBH1C8p3zthVUGC9Bw+9a0f5ae+7jcpe57pOQ6mV7aYZKr1m2VY6Q4r7IZDGe7pkLO0G2PNmcDmkf/4YzReO6ieSM4+OXadaK2He8A8Q5wbXmKWPXdmX/uPz6/j1Af3fulrvw6dCHof+bV9bW8r0otGPd3KSLWUkm+//U1Dz/1cHT0vR50WdNDj9Dte1f+/Ws9ENf1gbDWPLNio4Cn2J5thhucQdPbb0c9wX2VaR5InH524zlOFzV/4N2x+/ixr/+H7n+6hzPA8xK4Jt9Z6UWu9tNu/KznoKwkhxLcKIT4jhGgKITpCiC8KIf6pEGIvwYlnLNZ9M3lcLGV+q1Li6iXWgnOkfjTkfR3bEifVzI3JcBdtDycjb6Kwt5JyAOfI1chUUPXh6tqAdNW9KqXQbFc2ds5wbkWeZXcT2Ag3SHsB0h0usbWvuYVjn7gry0A+PbAadZxQIFLjU5xDSoml5nB6MVZljHLZFBBmXszjULBKlAKTgR+HlbKDreAFTC5bzlFz5tCySzdp4snhEu2KU0OJLulGC6soRkhrHmQphZqj9UuX/gvtYscDsTFr/iBXf+zzuC9+bX8Z93pTnh8/cBdpu4O1rdfZatRxA5BqfLChZFdQomsI9y5hl22StimXDj77vwFQscBJEywxSozLWcpUlocDFJtBm3ZR4PZ2JpMVH3oTCPdar8PFuiaoQLhuyG8naxoPkmBAfnsDYpkL3+Sl3+848gMj27VqVdKQsWrsAGrd9Mu3CylqyzKtaEC491O+q6IUWXSpF8t84wtMCbYsTrfnOFlZRduawBOsZUHKHOFW0bQp2VilvsbKMsDFN7ydg7/yv7nxzs+asZwb7eHWfpe4o3EPGZE8USghXU262RxZ9lLQShFe9PGuHtxvlb/73UhH0/zQH+zncIaQZjZ69tLk+3lAuPc+/p0QfOajdB4cbDPNXSz8cDzh9uypisXNMMPzDSoTwsztUp2rTRVlfGayAORTBdXKngXi0vOYGWaYNp4TJHJaEEL8PPA/gZcDnwH+DHgB8F+B/yXEmJnyswwbgZlUL5cHZdUVa5lOetEI25QH2eo4KymfH+PtW3SdQQ/3Ln2otyK3g5rryCFCP+dVKWVlz9b87nutc2syN4F2vGkyGBPKo59OWAsmiDDXdUeyqZ6o4/UUdm3vAYzdIHDAi8dnuD2rSMk3tlzj0CwYhrSwixLaeqGOEAqf85SsYRGyOW8OIRPCZge7PJrpzVWSixFc27i0BZqdOEglkOXJ16B9xPzgtz70u2zecQrLG/7e7cY8UgvqwfhAR9WpomVA9MT40t5xsEouqmeyn8GX7ui/78UKW44edyXOeme39ZA3gy7dAljBzmSyEkC3OP56v9DZBCHYPJqJIaLxXXOT+UnYFzBTvYHieP46suE7rns/73/Tt48e41wdtECtnRu73zTzPu8WYWVL/1438geiafsgrCpS/YqGHLJYQEWTs+17RbK+CSUzKcuDlDmCJJxqD7fqtVGxwG4M3ytybgHL08Qro1ZZ8cn7jH3g1QPhPrskSZp775NMHrufNBR4N9ww2He1QfFwmfAyrMb6288EEq2l8Qr6MAiu5n7g00Jy0QQrGq8y35PKqi5UEPeFFofGMWWxuBlmeL4hF8LMEzHWweMApOtXRhBxL0hWjQuCTmf3+AxPPWaEO4MQ4puB9wDngdu01m/TWr8duAF4AHg78N1P4xCngmZoJjQHtkzslwpXEctVVKiGiEuc+XDXxoiilZ3Cvm3BAKwDpod2vmsPEc/5Yq1PuHPBs90g93x0Y+glTZQfIQujE6qnG3mgod4bHVvZblDsmbLzK4HAERMJdxWXUgSyNl4ZfjOrFvB2UfI5X8iIg9Wm5gz3yzeyz6JOgFUdvW7yiXcxgGP1SxfKVLNUqSxP/s7so4ZIbHzOlOYKezi6bS2Y/cz74x+HNW8OJ01Z+cD/AqE58r5v5/jPv3/HcclygTQrA+995QHsCiA0hQicMd5r5Yxwi22EuxV2aBdB+JMFrHTQoxhBpzj+et/wDXlevcmUKQsEwkqIkoQgCQb9yJ1BJlB3zXPin13/bXz/a94xdrvWvNEUSC+eGvt5bjPY9eBCZ9Bl1Al9EssQfx3urSS7+5FfJekJvGuOD4+lVERNsfU2aXURWUAoD1LmiNJ48J1NoaQ896TPv8+tsKs2yfpo1letnc/WGVQBWWWXtLV31ffwS58GwLv19qH3ZdFFh5c/MU1XMoHEA0cmLmNl93puTzYt5DaA3i0vNP/PXApUmCALo/ehEYubXuBmhhmeb8jbhHIxXZklTnIh26cT0Vlz/ydr021dmWGG3WDPhFsIURNCvFcI8UEhxF9nfx8UQny3EGL3stLPPPzL7N9/obXup7K01heAf5L9933P9tLydmQm0svVwcT+6trVCBGRhsMZzsiSuCnj+1od9/Iy3AeNcvVSd5gkbCXc1gRP4XEQWb+Qm0BXnyX0Y6zi3uzKngpYy6YHer43WtLUsBpUfGONdSXguyYgMQ4LWVYnrY2/hZsZ4d6NT+5SedCbOb9NaXyhaAh32kvHBhaszMatFlq49qUDJuUoywzvQLitg9eAGBDWcG14Qm0tmn0uTuAq816dG89o4jMRB9/9Zqr/z/sovuldO47LqpRIfUW326R3sknllsNQNhUjzrgMdy5AuM2WrB13aReBiIkCVnmPbGdCgKkdmQnQ+Ve+Yej91V6LMI0GJeVbFMNz9fAbD13LJORkL71wevy4MsLd8+DiFjLfSwIQAmGB2mOGe+1Xfgm7DI0f/I9D78tSCZUwJPx2OVBBgp0Rsm48rKQeJNPt4e4T0sYYwj1XJNkYvTDTrFx/a9uNVS2Qdvc+niizZ/ReMuz4OS3yma4Y0msdOj5xGZEJZ6rO3lXrd9z3unle5W0lasNk2VSYYhVGW0hksYCeEJScYYYZLo1cSDKvOsz1UqZdvbJXaKUIzmZuIxvTDezNMMNusCfyKIT4G8AjwM9gMr5fk/29HfhZ4GEhxBumPMYrDiHEEeBlQASMNK1prT8NnAEOAq/c/vmzCe2ojVYOJWcw2bi+cdT4AGuBtcWKK7QNgR2HkuP1Vcr3Q7itw2Yif8wfzjIsl+uUQo0WeqIK9DjILYRbW00uxmlfufqZBCtTx14YQ7iPpy5SQ1wf9YKeBnxH9/vut2M5s1QKqqO2WADr2WlKd2Hbk3uKAyyVhvvwD5TnQWvwNVZ9lNzLhvlxbgS7aweo5qXYO1jICdvG3lKk4da3ZbizzNviBAGwRnGOWsZ5im94267GZdWqJBH8g599NSoWlF/9GsI5BycFzx4NBJVyPYTq8LnvRj06RQEI0gvjM8k54W5OyHB3MsItl4d9ww3hDkgyT/CtJeU6ey1KOwQyshLhdPX82M9Vu41GE3iwtqU/vBVm27ZAh3sTqIrXexSvnkNWh4NSslIGBLo9HVspFaU4mdVcJx4mvLGKBiXx0ygp38zIc32UcDtLdaLNeKRPPs2I49a2G7tWIentPSOdZ56s5auH3pdFDzUF8plkVnz2BBs9MPeotDWqt/cM/U5IN9ZBaJzjRmE/zVwK0kiNFYiUxSLpTDNthhn2jbxNSGR2ssK2kY6eejBtrzj99leRBua3P27NbvIZnnrsmnALIa4DPgosAfcDP4Ah2u8A/hnwFWAZ+Gi27LMJL83+vV9rPalJ9Qvbln1W4jWf/Rzf88fDk8QXLV/TJxSyMSBLkSX6pHo7Slt9uIvj+353wiPCQgHHtxGrpUqNcgCpO1kFeiwy0u9FFq+9T1FvPr32X5NgX3UcgIXeKLk7lvXpbkzIMl8OkjTFd+hbp23HfGCuiU5l/LnczHycVevSpViHqgPicFVluCz8QGWeYgQiFdhjSmhFoURkaxrh7kRNahN6n0c3bLZX/7qjHPvA/xr6KCctc+F4crFUqlPJngr2waNjl9mONc9BKMHLHzXfW+mb/j7NOROk2hrsylHMiI0sbyPccZdWFizIxae2I10xfaqtCRnuTmhu7rJT5Lrf/SU+870maLDWaxOpkMQy3+FwhruXjWd8iwGAtZgR7vXxLpBpuwMuaCF4sjkg5e0oI9z23jPEaTfFaoye67zCId0c7XfeD3SkcAoeWgt62wh3kESk2aNJx5efUc+zrtYYkcjCjTeiIkHy0JeG19k0JFYuDNpurMYcabD3LL/q+cZCcdtzXJZKqCnMS9P1TaSjLxmYlS4ofzo2a/19b7awCiAXTaAzF01SW4QWh8ZQKoISQ/fCDDPMsHvkhDtPggBIV5B2pxtM2yuC002cOUHjtdeQ9PTUqqFmmGG32EuG+19iPLjfr7W+TWv901rrj2itP6y1/s9a6xcD/waoAO+7EoO9gshD70/ssEzuzTI5TP8swP8d13jNA+lQxuSlh67lwKaZ8OeldwCBTb9Peztc276skvJPPnkf7RIc8YeJ54FynVIIkbc3Fcmea1Kwr5Iv4h13w0oDFn/kv+x5XFcaVka45/1Rwn2oa0jvanX6PdzNsEfggjVhAt3wzY9kszJ+35uZb/NuVISPzC1S62re9/sp79pGuA/VFqhlc1lrgmqx7wkau+Rh+feYl4VPgk7N9V1+3Ruwr7ll6LO8x6w2gXAvVxr9gJR18NiuxvU7kenLfeUDmo1FgX3kBi7MmTaM8pgMdyHWxNaoHoKf9GiVDJFOTp0Yuy+VKYp33fH3TDc2JKbiFnFf8jqC20zp8LrfJkwDUsvcO1tJhs6VZiuTqy2sZVMZkJftjo6ri52N6YG1gSVMJ+qgtcCyBSraPaPTfpc0FNiLo5UvsmICAzl5vVyoRGMVC6Bd/GSYBAapKYlH6umUlOfe8I3R+6Fw+6vNPu/8823rmMCXtTiw6bPnF4yI3cr4Ev9JUL7PmC4HZKmEngL5TJstrNKlpxrSkaje5VcMDO273cUuWoPgUKuJThJ0IpDl0eBiHrhRUwrczDDD8w06NPfw1uoo6UqUPx1Hh/1AK0UaaKovvwH3mmtAC9JTMy/uGZ5a7IVwvxl4UGs9US1Ia/3vgQeBr7/cgT3FyJ8MO80s8nrLySmfZwHKR49BKkieeKD/3lyhxNWrZsbl3vKy/vuBzcQSZAAvMZNpUdh7hvueiw/SLMF8d3jCXfY8ygGEE8jDJKxnGcyaEpRCzdl50Se3zySIQoluAea7o5GMpSwCfLY0fZXy1W6byBZIJfoqoltRyya6GxNKiJtZ8/du+rCO15f47s9Xuf2ExvmNnx367NjcInPZ7u3lUU/vC50mXRdquyXcmV2WdYnMs86+bueam0Y/zHrMqvH4kvKrqvNUfE3qjmYBJ2GlaL6vQxvwlWMmo32q5iAAGY5+/8VEEToM2WcBBGmPjYpZPzk7Ph6oM6Epf0LLezc2E51qFhibK5hzvOm36SUtsM321VbCndl1ycrkagvrgPnO082NsZ+nvQC7YCGSOqfaj28ZTxehPYQt0fHuCXdyykhrjLOXklkrhGpdmnCHd36C3sd/a8dlVAyiWEBoDz/Z3sPto7VASPY0/on7ygn3wmjQyHvlW0BognvuGl6n3QI0cn6gc2FlgozJhEqIifv3Q6Qz+rzNCeluvtOdkLZ97NKl9RikZ5EGUybcnQCr7CIKJYSlUe0OatNUZOxIuLVoc6gAACAASURBVJuX1qqYYYYZRpHrcojCFsJdsFD+FFUt9wjdWkenAqtexzlkWmfiLXPgGWZ4KrAXwn0QuHsXy92dLftsQj7b2HfDmhDi/8s8u7+4MsbG5ZkC91rTyxY/ODyBO7KpSSyNfe1t/fdCC+xUTPTZzfu7RWnvMYiV3kW6RYHsjk6wKiH4hb0R7ovZlbwQxHiB7pfhPtOglOJCHRY3Ryfq812TSTs9RszncrHhtwmzPmzVGS0Lr2Vkf22C+FjXiVBCk3YuLTYipeR1GftT7eHl5wol5rrm3FoHD4+se/+FJ/A9qIa7E2uq54T78GRxL6Dvyf7jF7468llbWsQWVCYoMh+tL1L1IdzDNdksDrZ153Gz3uM182+ePd4KLzaEuxsP3w9B2mOzYohyfOYUZ77l9Tz+ppfw8EtuIj5xHzAgymOE7wHwc8Ltmptivmju182gQ6g6YJvtbw3E9L1Uy5Mz3KJQMr15zfHqs6oXYRUdKtYR1uJB/7mfdhG6gLQlOrp0WZ+OI5o//6+JH7kHAPvAaKBGZr3vOXndCSe//Xt54vt+bOJzTccROhXIYhGpPUI1nJkJ0wi0i7SmQ7jTrMzZmh/92ZRzC7h1i+Dkk8PrtDtIx/RH5rAOZFncCYGZSVBB2L8/tkLk5PMyqwaSTohVvfQDWXo2esoe2Ek3wqqYqhHLg7TT7ZNpOaaap18p0ZqOFsAMMzzfkFf9bA1OWwXnaSXceTuWPb+InfmCJ0+OrxibYYYrhb0Q7i67I9IH2DlT/ExEnrbbqZY3/2xsik9r/cta65drrV++tHRpO6OnC84LXgxA/Ogw8Ti0odiYE0MTuCAXBgrGn86+LZi7d3bbjNbpliXJ5jjCrel6exODf2DxIOsVOH73I7ihpluA9i48o59qnO9scq4haGyMTiyrWcnVaWv6KrnrfmdAuNujpKTUDVDAijte2V1bIYm7OxVhrRS9R80kPXh82KNZSslCx5xb+9Bod8aDq0/ie4LSLtWR672EyBoooU7C0V/8L3zgdZIP+R8Y+exit4XvQnkC4V4oVZnvQWeXhLsd+nSK5hwqqbnneMT59gaP1rOy/O7oI8SLFaENm9vIeKQCYq+CdDSrH/0CrS9fxD8TkgaC6P7PA6AzoanJGW5zH9Q8Q6znswBZK+wQ6w6Wm/lzBwNiqcIQ0JcMplmeIG2Nr3pI/RhZcjlYOEokzpNk3qd+0sXSBYRjoXbRA732w/+Qsz/3QVZ/4ecAsA+NlvXLOaPXsBuNgRzxvZ8d+77KhNdkqYwlCkTp8HMkTAOEdozo2xT6AFW7Y3qoq+M1J5z5Isnm8H2nOl3ktrab/H5Kzg2T80vuP4iQ7qhIYS6gebnkM/VTrOql245kwSENpitmlPZSrJr56ZaeRPV8VNM8m+QYgUhRyY/50oGbGWbYDXSS4P/Z7xLe9emneyhPCXIhSVHckuEueqRTsBjcL5IL5ploLS5jHzdtk8mZvT0nZ5jhcrEXVnMX8FohxMsmLSCEuB14PfClScs8Q/F49u9ODZq5hOvjOyzzjIdz0+2AJnpiuOxweTPlQmP4cvBtQxp0d3wGy0sFqdRDJH236KbrXFguEHcgOf3I0GelEDp7TPI+2VvjU7cJvJM+dizoeoKVCeN+OvHo2jnON6DQ1iOl3V4voOfCWjogMB974Au852P/+bL32wwGhFuP8dL2wojAg04y2meVpClahKSOMAJLl0By8j7yKtzwQjCSSVzMFNqtQ6Paik9snjP2Zbv8ca72YlqlS5emeF/z9Xzo1bIvnrYVa70WvgfFaPI+53uwUdod4V7ptuhkMajwoEPoCv7qyQc43eihpEZ1R4MWXqyIHGhuC27FyscWBeyyRKeCwkGn7wGeZ3NV5nvas8d/C352Tuey1o+FjES3ow6p6GJ7hmTk/qnmdYiwLi1caJVs0s74ayL1U6xykVsWb0LImI8/bH4WItXDEkWkY6F3+M4BVKfJ+se/aI7jSVMtYR8ZvW7knBEc243GQI7uJz88fp95BrRUwqZAtE1HM1ZRRrjFrkTTonv/asc+6LTTxdpBJNJu1Ejaw0Q07QZYhWGS3J9InjtzyTFthQpjpDf6DJ8W+VSRRpZ3Q7jdqXpga6WM1WXNXO9WwSbZ7PWtDfNs9tAY+q0J0yfc4Z2f4IGbbib4zEenvu0Znrno/v7P8fh738/Jb/2uiVU1zyX0M9xbWg1lsYDaZdXalUB6MbNeXD6EffRGEJr4wnh3jRlmuFLYC+H+RcAG/kwI8c+FEP2GMyHEASHEDwJ/mm3zF6c7zCuOvFT+hUKISenaV2xb9lkJWapilwXxmcHDRitFY1NzZhvhDrNM66TJopdAujv3phGEepMzR8wl5H/6Y0OfFQNNa4+iaec6F3jgyGCdbsGoMD/T8MTmBc43BEILoq9+YfjDbg/fg2Y4IMT/+nM/yGfWf53PPfHgZe13M+xuKSkfJSVOGBM40I5Gy51Xey2E0KSuQPUuLXwSfv4vAKi9aAEVC9JtY5/vagJXj1UWb0Yteh7IXf44l3sJrRI0x/Slb8UDFycLSa31TIbb24Hk13zNakmP9FiPw8XOJu0iaKlxbr0egA8+8CdghaSeReqPZvHcMKXnQWtbf3dCgCOLIM21XX31S5GZV3lOLvMSdd8ZP7YgMRmHWsE82g5kZeLNsI2WPdxSlh3e4omtw3CskNZ2WCWXdExbiA4Dkp7GXl7kH97+VrSWfOD+PwIg0j6uLCMKDuoSgZX2b/4UaaZYr+IsUHP1C0aWyy21LkW4t/bmdj7zubHL6CyjK8sVHFkg0cPHF6sQSU64dx5/8thXOfGuf8TF7/uWyWPq9caWdOewlxZI/GEfdtULsYrDlorWwWMIqUkuXthxTCP7DxOk54y8Pw3yqZMEFQusCWKMQ/srFqZLuNsboAUyE6Esv+JF+GdCHn/PD5v91UYrCmQta00Y84y8XLQ++JsAbP7GL0x92zM8cxE9MugV1s+DVgUdRaZiZ0siRpaLqOjp87dPV80z0Vo6jHBc7JIgWZnpNMzw1GLXhFtr/YfAzwN14MeBs0KIrhCiA5wFfgKYB/6r1vpDV2KwVwpa61OYDL4LvHP750KI1wNHgPPAHU/t6KYPZ84lXh9kf5PH7sdOBKfnhx+IgZMR7gnE1U3Evgi3Ugolm6wdv8kIAn3pzv5nOujhRrBZ3NvDeTVYobXFV9UQ7mdehvtU6wLn5s3kOnpguBAk7fgEBegmW8dtbtFfvfvybqn2UIZ7DOGOkqyHeDS4cjFTwdae3FUfVnCf0QcoveJ2ANKV4Yxbo6fpTMgW92KftRqkHb0r4aJiL6VVEqz7k3vLf/2Lf8q7Pv7/s/fmUZJc9Z3v597Ycq2svar3bnVrt5AAsQqMwQYDNmYxNt4Zj2fsOTNe32Nm8POM/byPwcx79nmMfbzhfWyMPWCDZQ9gwGzCYtEGSKjVavVa3V1r7pkRce/740bkGpmVWV1qtVr5PUdHXZmRGTcjIyPu9/6+v+/3Na2/e1sN1mulbavq6bpmMwP3r2zfH3upUqThCj7/f76Zoz//O2hl8WDxHwGwM2l0CMGpbodUp6GoeaKPcIe6TkpmaK6bsWVf+QasGdOyEsunVSQFr9sDCHdoTL7yrullLaQyaGWzUj2HEJpM1pBV3RHJpBpNhL39opfMpQir/QsIwRNfAS1w9uzlutklcvoGvrplfueBruHJNFbaQ21T4d76u7txpqDwXNOfbGeTI+DkdHRMEtQDXeN6/Mut9yk/sknjXz7ct42KFCAiN4UrU4S6e5HJEG4XYUnUNpLy6kdMBF31qycHbqOqDawBkW4AztIyaNGlBIrl+p0QUprF1NXxCLL2FdLrbyWRU8YNXiUoYkaF2jATXZnf3udDZtK7EkPW2vdWdyV7/hf/gOkXtc0VrQSTutZnHsEcclyEG+Y4jvv9TPD0hn/uXOvfcTvDtQzd9OkV61jZLMrfnRacTqhqierdf7rtduGa8VWKU0bsvEOwfvXNDye4tjFWo6zW+seA7wI+j1FxpoFM9O97ge/SWv/Ebg/yCuFXo///mhDiWPygEGIRiJek/5vW+mmvCbKyHmG1TZz8rxjJ5rlZ3VUprEcSVVVNJjOegsAarxINcKa4hpAh+dkDuAVJ42TbUCk49TUEgktj+rBtNdcodkQYVVLGFOpqw/nyJS5FfCE4daLrOVVt0HQFtbB9I9CYGegX1j7c6oHdCYrNCo3IiVglSO3lEMK9Gm/vWiP1WDYefRwnD87h6wEI17qlW9PVkK0BCtN6UOP4Hgu0oP7Jv0veqANeTVHKwOYAnwGAe87d3/V3b6vBRr1EzRPYA6prul7FagrKacG9Z7dXGqzXzPsHt389mekFHLUIVhXCPKko19r/2n1dr7EbiqoL5Z7FACXqeFaa+W+9A4DUS16HnI0r3IYU6FqdUGpCmTz+RtgAbSOjWZCUEqmzrDXMRDA3Zfrf4zgX828fOQLhtvI5wnr/fv3HjEeEc9DIv/dljuLLS9FnqpGysqai6Q9fWGtcqpI5uoSzx4xx9ltenLhdS1JeGf6b908+AsDiv/0OQFB6f79beUwwZTaPJ9Mo0V3hDnQTS3gIe3tJefWznwbMNXcQwmoTme6vMMewI1fdoEMpouohVkKagZ13CTbGI4uqqRDp/vHtBvlU0W9f5ge73bf2l8mgA7Frk/JWr3Zk/ia8FHve84/c8JmPse9t34P3otf2j6H1mXd/Mt44ZY5F7eTWM0JaPIGBv9quaj8T3O+17yN6CjFmwU1cduJBL1Z/5l/zxE/9MtV//POh24UbG4DGWjLXUmc6g7/11MWUTfDMxHjOVIDW+r1a6xcAU8Ax4HpgSmv9Qq31e3d7gFcKWuv3YaTwy8CDQoi/E0L8DfAocAvwfuD/ewqHuGuwchlUrU3emo+aqs+FacG5SPIUhCHNSKI6yDTNDSDYQYX7a6tmor8vv4SVc7t6QIMoG3Etr6j6o0fEVMN1mpm2WV0lJdi4Cgn3anWVcmQIF5a6J3Vhzcf3JA1lJribtQra3sQKllD2JX773r/f8X7LfrUtKU8w7dJNn6ZDX+YwwKWowj2KBBigcX4Db89Uq4IUrl3sej5XUaxnRaI8ux7W+NoeM/mvfW57kxmnpiNJefscVUrxuVPtauBWo7uif6lnMl1slKm5YA34bHE1eisLp7a27/vaqJvjO5sxJCNjmQry0cxdrZztXmMr2dTUvH5JvxYN0naGhV//C276ypcRtm3MtYQmjMilajQIbdAimag0wwZC98iPdZaqNtXH2dwCCN0lKVe+j3C2vz1YhTxho79yEZwyudv2YZOKMJuaQ0if2/7gxWhri4ydNRXNIYIJHQRGlj4/y+x//DWWfuAVzP7MuxO3FY5rYp8qw1sLgtNmkSv1/G9EOprgYv8EMJaly3yBlJ1B00+4beEiHGtbSXn1EaPuCDYHex+ouo+VTjYrBLD3d7vq1j/1d/gVjT3XL4m2Z7IExfEmkso3cu5eyMLlk89wPZJyFga73bf2t0sxZDF6K9wxrNllpv7Nf030Hmkv3Oy+72vjgjk3w4ZoKS0muPbhr7XnIc8E9/vBhBvU+njtLtuh/uhJAIp/+UdDtws3N7E8c58AsOemCcpPnYnbBM9MjE24Y2itq1rrE1rrx7TWw2c5TxNorf898L0YefnLgG8GjgM/Cny71vqa+IVaUznCRruy1Dx5Ai00qwU4WzSTlI1aBT+6aOoBcl031K1txsFj62YSerCwHFXb21XT4OxJADazgvNj9A422WTKnW/9XUnBVv3q6+HebK4TiLwhOD0RW2E9JEzZBMKM+4vnzAT7Ww99L4R53vfI3+x4v5Vmm3DrBMWCbgQEtqAe9v+Uz5XMBNjOpAjr2/8EwrrCmspizZtQg95YoXRVs5FL7rtuhHVK6QzOFNS+/MjQ/ajyFtIXFNOiVeH+wy98hDe99z/zbz72Ju45ZV6/Wr8AYZrr3FcBcLHSLZEtNspUPRADesziRaCNHHzg1G/x4ve8Zei44vNuLm0I98+/5O28af/beN93/DeEZ6qSwUp3T7nwoeZBuYNwN4MAIX3SUWxXbKolpEQ6tMiljgg3DCHcdBM6V2bRljkOy1PzSNsYpcXQzQA5EuGeBi1Q691u9P4Zs6DgHLsNgIXMbPQCc2wM4c6iB+TCA4Qrj4MW2EtLWEuHmP2/3t1asEiCdNnW1M8/a9Q0znW3YuckwUa/XDommDI/TcZOo2Wja3EoxBBu6dqobQi3XzTfSbMYDqxqhnWFzA5OerAPmUWL4JwZ+6Vf+0UsD2bf/o7+bWemCcr9+3nilc/m1Gvv7HtcK4UKjJy7F7IQ9cVfBvlskd6IvA9DHNOlNnYnVrOlVMhvT/ZbY5iKPnN1dwl3uHqOsC5I7zW/w+D08V19/wmuXgTFJnbkH6a2ngmEO0D0KB+t2Bthl37bMZoXzFym+IUnhqpGgq0yVrp9P7MKBVSz2xdjggmebOyYcF+r0Fr/udb6Lq31lNY6q7V+rtb63deClDyGnMqj/PZEt3n2AuGUQEnBStncEDbrFfw4FiwhNxjADdkR4T6+YSaOX7d0BCuXJeyotseTyvU8rWr7KFCyzLTXntRVPEOkrjaU/HUcWcBy6avGqYZGpF20LFNpNLh/xRDuZ++5kUOp57OqHtjWHGwQqkGFZvRdJU0mVVPhO4J62E9YVsqGMKcXFwhrpm9qGJSvkakUct7kbIeb7YUTXa/i1gVbWTidUMlqqhoSD28pT/Pi8MqainrDy2njwl71G7zroZ/iscY/APCl6PgV/UtkxUFef/03A23Jd4xSs0zdBQao5eNFoK2MA1aNkvzKUPO0rYZ5/8WoxeGbjt3Oz3/jW7Etq024L7Wr/qpaQoSCqieo+O3q5GrkQZBz2m6vMaTbdoxXDZ/QFmiRTP6aqr/C7cl21W85N4uw4yiwaEzNEOFs/+O2Zg1BCVe6K/b+ygrS0VgL5hzYm++Obcu7uQ6C1a2AiBGcNBJqe09/XnsSpCtRteHV3eaZc1hpjZyex857BJv9vycdKUBkfpq0nUUIRanZUf3XDWwZV7gHnweqvGUMw1IaHQjCc48nb9fUiYQ3hr3/euOqu2IWNfz1CunD0+bx3m0X51G+QG1cRJW3WPmhV1P94B9SPV2ncqL/d68rW8ZYLJ1EuEeT6Q9DvNhmzcxvsyXI2BV9l/pcY4+DcQi38FJGKVHd3RqC2jREw90b/V7OndzV95/g6oSuVQiq4C1F6o0xUhSerlB+0Of/ERsUqvXdI9zBEw/jl8CdFoQNgf/QYHulsFjFyrUXna3paUCgVs8NfM0EE+w2BhJuIcT/Ef033fP3SP9duY8wwbiwoszacNUQlsbZDVg0N4SLZUOODOGOen4HScpDWqR8HJwqnkYri1sW9ptqe71dWQwuXkSj2crChfJoFe6630SIkJTdrn5VUt3VwqsFNbVJWk53ESYwK63KF7iZLEJoHrpwigcuGnfTuw7ezGuu+0aEbPKn9310Z/v1a9QjOVVSxUr5IYEtaKp+wrJaM1Wq6SPHAIH/8BeH7ksFRqIak61wq11FjI2fNrOCMwn9bE1VxxYeztIc/lbQWrU+/4Ov4tx3f0PXtmFkyFT14MGLx/ucyB9bNySwwSoFZ7El8d7oUT5U/ApVV5j+0UZCLNp5876ljkzqlfJgI6li0xCUpQRzL6RlHN9X259drRvCWXWh0myfE+uREiHn9hNuy5Mtx3jdaBI6AgZIyn3dwBLdPbpZu91Te6Awj7QFutFe7dd+mOhc3TeOOUOke43xgkvr2Pk2Yd8/tdD1fMWvtqS+g/oaY/l3LKneDtKVqPrwikVzZR13zlwn7JkcQbG/bSUmmGJqlqxj1AWdiQcKH0d6SMdBB4MJdxgpVNIHzLH2H+5PyxxWYY4hvBTulKR52hDuoBpiTyW7fjv7jSmQ/+j91D/xfjY+/QRPvO3XBr53XHGL+5y79juiTH8Ywii6Tk6PQrij82GXZLetCneCG/nQcTiMlMYw1lgi8u/u3wu0rykTXNsITn4FELhRIsuT4X5/tUH7IcLqphZy2hRDwl3sYa/fYwwvp199l/n7s/0GmDGCUgO70DaOsWai8Vw8PeglE0yw6xhW4f514J3AYs/f2/0XbzfBVYpWVeriGcL1FZqbCvuoMZNYrZkJ0la9QjOucA+Q1zmhblVNx8HF2jlsNYdr21iFKXQoWjeiYHUN0qCk4EJltIlXKSJJnuVhR/PGQQZgTzV8iuSdWaRnEXZM6uKV1kwkvfrqpSc4UXwEK1hkOT/D9zzr5QB8/vyDO9pvPaziW4Z0JSkWlK8JHImv+ivc6/V1tPKYuv7rzGf42v1928TQ9SoogUinEF4K6WjCYpusBGcMidrMwYVy//frK0MOnb17TaXukrkh1h45S/V4d/+XWjN/+7bHA6tf4quXuqusZ0pnqfoNlCyymF5uSbx7Ww2qfpVmFMukNvt7zEzMkqaSa5OG42vn+7aLUWlW0Foy5SWTKGEJgo12lT12cq557cxs6Khwu/0Oc9KzW47xyg9QtkAIlWisF6omkm7ynHciwh2mODKziHAkqtEu8StfIdztV9OsBeMeHuecxvDXKzjT7c9/eGa56/kpL98y0hpU0QzOme/TPtCfu504lpSD2sbUr7lWx10yky17doagqvukiPGClCzMtY79egfh1sLHlR7Cc4aavgVRRTv7gucCUP1U/4RQ1yumwpwZnlPtLuVprhizrbAO1nSyCZlz1GRxNx99sKXM6ETpj9/RpVCJ+6WTCDeAk5P4F3ZecY6z4mOjv2EQabOwpC+jot6178jsLY6MGxXSEej67hJuHflgOIejfvxJBvAzAvFCpLPXLLQ8Ge73Vxt0ECDsHsIdt6fsYr5946sPADD1/T+OkJraA4MTe4Oqwu64ZspZswAcXhp8H59ggt3GsBnVf8e4j6/1/D3B0xyxvE9dWqFx9iQgyN/xfOA4G3UzMdjqzG0eMAGyQ92qgo+DYrBC1jITMGs6qrZfOIXM3UawUURkDYtfrY4WR1OKqoIpO8WRv/pr6vd/Cr357quOcAdhiJIlZrxZZMruitgKI8I9O7cEHOexjTNsBI+z4Jr+zZlMDhFMc6Z8Kumtt0U9rBFECgBV7yfVOgDtWDRV/zEr+htYKo9zo3HK9h//Wt82MVQpmmCnDYGQnkCV2u8ZSyk3M4JLlf6bb0idtJjBOXwU+Az+I19CLhzAL4YoFd/MzWUrjOSq6fQSF5uPcGLDTG5+4yV/xk99/Ce4VF/hgfMnEUJzYGofC5Fkdaun1aAWVmg6NhCiNlaxlg51PR9cWsNKQdgxh3h8Y4WvP3Jr4jGoBhWESrVcwXshLEmw1V70iCXVNQ+031HhrpnJ2bTXb9kvUw5hdP7oZoiKfocVv0HB6iZvgW5gi+4e7ilvCmpg6znjWt5DuHWgkO72FW57aT8A4Wo3gfCLPqnDbRn5kZn2v3/y1l/ne29/OcH7fst8/s3khTX/gpkM2Ydv2XYcYI6JnyARjxGurxDWBO5Bo7ywFxbQ4aOo1bNYiwda26loQUrmZ8m7hohudPhYaOHjWSmE66DDwbfEMFowSD/v63H//p8p3/MFeqmf2owIb6ZfxdAJ98AyleOPEK48AVq0Fk174dxwOwD+E4+Bb75PK6UJ6+b8OPMr70H++h+QPpDjwAfuaRPiXHIshLd/mvqZy4gFi5z0rbk9224rIwd/NSTib6x9Rx4Z8WR/VJjWhNENO0cbi7mvWrOLSFcTrF37btUTtO9Rzj5zfXlGEG4/7CPc7SjL3avwN0+cwEppnKO3kVpyqXzpONpvtozRWuOpVVBNgTXXbjmM/WV671sTTPBkYmCFW2v9Nq31f9Rar/X8PdJ/V+4jTDAurPnYPXqF6qc+AsDiy16P1pKthplclepV6tsQbieEps1YbuIATVaZ98wEzJqLVhovRm6+xRpO3hDDi9XRJiXFKEopZXnYR24h94YfRiiPanB1Ee5TW6sIoZhLz2OlXVS9LQEOo2rtckRgHlr9Ctre4FjhxtY2WbmHDX9nUsSmqiJlxkhEa92EO5a14rQN2zpRDbZwxRT24VsRUtM8M1iGFctB44qdlbIIKx0u9BfMwsJmDi7VEgi3buDKFM51plL3+A//NKX3/AoqEKAE4ek22Y/lsHvmjqLtde6/+BAAty4dIiMX2PIv8C9nTB/w7Us3sJQ16oFSs/t8rodVmpF8OkwwdQk2ith5m7DDrfp0cbDbajWoIPUQibBtEZQ7Fls2zXledaEetitrW5HLfiHVX32UaQ8VGdipZoiKDM5qCb/F2OSrEzMpcyxS0ixCSNdGN9vno/I1wh3snB3D2mMWJ8L1Dol8tURYF9hLbZJdSLUXAX7ozm8m5bjISM0RlpIJd3BpFcvTyEwyGeyFTLnoAdFuAP5D9wDgHr0BAHs5kvc+0W3Op2o1hKURjkveM+OOEw+UUiB8PMtFui56SIJVEFX9rf1HyD37GNVT1T75vC4OlnR3wjt6PVoJTr7eRFnZc8kSbfvQzQhL458+jX/xAkJqjn74oyz9wCvan68pqDxWwf/yZ9FRxSkmu/37PYy/pQb22W+HsFwCoRFT25umiegYDFJUjYs4jSHuRR8V0rW6Fp92ZyyxEV8BO2sRrF/70uIJ2h4G9kGTNHs5fghPF+hAIe1u6aOcNfcCVdq9uL3GmVW8BXOfnf2uN9FYV2z91s/2bRecNm1s9ny7ramlzNrFnvIJJtgOE9O0ZyCsBTPR3Pzrv+LS336BzMEU7pFbECpDsWkuiKVmpcPVOnkCZAeawILiGEZepzfXwKqxN2eqTL09oGE1IDWVRWvJRn00SXnc95px2j3ctp5ho3l1XUwfi2TIe3ILyIxH2BFDFVe480v7IcxxvHE3AN98II2pygAAIABJREFU9K7WNoupAzTEhaGGXYPQVFUcke5zowbQ1ZKRtboeSpT73r+utkhbBYRt40xJ/JXBx1VHvc1xxc7KOITV9v6Ci2ZFeSsLG/UEh2jRxJUp3Buf3Xrs7Dv/rPVv/8RDrX+HUWV0aclMZp6oPARhmqVcgRl3iYY4zwce+yAAdx26lUIqg9aSit+9qNBUNZoRuYwrjp0ItmrYU+lWvBfAXz7xq/ynf/ydxGNQDYvYYrBEWDg2QVm39hVXGWuuoB60j1WcIz+dRLgzKVRELrUfoqMJTlIeeahNz3EnHGFUAlnbkF7hWqhm+3zUAcjU4Ozo1jjm9oHQBBvt32pw3Ej94qrOwNfGsVMDqh7hVhkrM3rPikynCIcQ7uZjxhPBOWZaI+x9ZrEgOP1Y936LZaLuC/KRpLzcMNe4mu8jhDIV7pSHGmJSHkbGePa+Y3g33ARKdGVpQ8cC1TaE2731OQDEp248YeyFkBInb2TgweoGdlZgLewj++o3921b/9w/Ubv3n4H2MelF6tbbAUHjX3bmHaHKFaTTdtgfBhl5LAwy6Rx739WqIfvZBC+FYeNIOajG7mSBx9CxvD2bx57yuhQuE1y7iD0M7D2HTDLJLpvxXY3Qgeoz3JTTUZFnlyr8Wikaqw3c/Wb+mP+3P4uV1lQ/97m+bYPIS8NebF8zrcVImbU+UZpMcOWwK4RbCGELIW4UQiQ3lk1wVSF2jy59eYP0ssv+P/8QAJbOUA3MBbHcrNOIClxqwATICjW+nTzJH4RHVk2F9sBUVOGOpT1RVnNY19hTOYTKstUcUVIeVbjTdpsgTNnLlIInrz/nj774Ub79L98+1mtORv3BB6aWTAZxoyNqaMUsOFh7j5ARZkHEChZ5w80vaG1zcOoQyDqPro0vg/J1DVdmEY5ANbqNpXQkA7dTaYQM+wzBAlEi7xhiZuc9wuKQTOHIqEhEFTMr46E6Y9/W1pGOpmE5FBv9q92aBp6VQi4dJHssx8xLDnc9f/I//BzVD5nMTVU0rz940EiOG9YT2Nq0KLz1tu8EbXNR3QNhjv2FWaSUCJXqazVoqhq+60Xv2V91DyoB9nSeP3ndu3jT/re1Hr/77O8mHoNquN5FznthzcyhlaD83ndH+zTHrO46NDoq3LHL/my6v/poZdKoKMZMBQoZ9VuvlBIWMWji9JimZVxTGTg2bRQU0nVamdI6CCIjr+F9xQDCtrE8CDfbpNl/PCK2B7vNzl6x8CO8+cB/av3d6usbkPMclmtY2e1l7a33S6dQQwqTaj2qNkUqkrg3PDjfrdgwRN8cz7jCXY4W9bYa5txJ2SmklwI9ONYsWFtD2JEj+mJslvVE95ii357IDb91pl/5XSy86Xmtv63lwc7tzlyGyqPrNM6uY0+Z790+fHPr+cXvfDEA9QfuY+vDn8JbsPCe/8rE9/Ke/RIAGl8ZbpQ4CKpaw/JGazsSLUn5bhHuGtIejex3QnoOqrG7CaBxMoTIzWBPZwlKkziiZwJUZBhqLeyLzPiGxxZeC9ChQvRUuFvu/+XdUa/o4jqqKXD2mvmjkBJ3LoV/sf/+F7f2WHsOth6zFsxicLwgMsEEVwIj34mEEHcJId4hhHhWz+Pfienz/gpwUQgxHguZ4Iojdo8GOPDnf4s1byaDjshRC2PCHeVwi34JcgypIJCwNeD5JDyxacjigamohzvqnQzXLpleG19gTRewdZ6SP5rsLo5SikkEwFJmP4FcpRnsbqUixvse+SBfq3+Ij3dUXLfD2ZIh3Ienl7GyGVTHnCuOibL3X8e7X/lrTHMHb73pR7v6gG+eNwTm3rPD86mTEFInZWWQjuhzclaRpDeVNlW2kx3y0SAM0bJMwTXVSJnxCGuDWU0cexJLVGU+S9AR+xaub2FlJFJn2Wr23+y0bJK2MwgpOfjBe1n67b/r22bjj3/fvFckV731WLsanrPNivdbnvVSvuu6HzMPWm0Zn9ApqkG3rC/QNYJUFNvSQ7i1UoQ1jT1T4PDsIj//jW9tPeeRbAQViA2m3cEyVjm3jJ3RFO/+h2ifZpJQc7oJd6lpJiezCZJqmcui/NjdXmNH/da9GeMAWjRxrG7C/faXvoXvOfxf+M3X/AQAwnNRUcSVUSlsb+QVw0pLwo4+/eBUVFHoIHkAv/HaH+XnXvH97c8Q9/UNqHqEFR8rOzh3uxcymzVO8wN+83E8nVwy1xz7YJRvvdIdDROWatg5c7ymYsLtGxJYjCrdaTuN8KJFmmrygkGwWcROG7JpLUWO/Re6W0Jav5dtCLeQkrlf+sPW3/bSwYHbZu/4OpQvaKyG2NNRa8esmZg6eZj7hd/HW7Aoff4R6hcCCi9/wcD3sg+Y6LFwfWfGaWG5hkyNplLY/Qp3HemO7zEi016X2mNXxhLL23MFrKl8VzLHBNcuwkhCLWeXzb13l93vr0boQCOcfnsomRCFulPELS5Wh/eEuzBNcz0hZSRq7bH3Hm491jJ03do9ifsEE2yHcZZ+fwT4SaA1OxFCHAD+GMgDW4AL/LIQ4qW7OcgJdhfCSzH9ooPs/5kfwtpzuPW4J3M0tSEjtaAGQiBs0AOyba3AVLiLjdFXLc8UzYXy8LSZAFrR5DdcXzWGQJjIBk/mqYWjEe5yVOHOdFS4D08dQsiQB1ZOjjy2cVBsGpL6pw9+aOTXXKiYSevRuWVDDpRoOQaHa2sgNXJ+H3fuP8Yn3/on/NRdb+x6/e3LpiL38OrJscerRY20lUE6FrrZTZhjwpeJSPKprTbhPldaRwjd6vm1cumu3PS+/bQmlmby7B7cT1gTrfiNoFjBzrvYTFEJur/fqt9AiJC03V44EbaNO909aY5v5qpURjqwb2YBrc021+Vvam334y8yx29Zvrj1WEYusuF3Kx9C6oTRYkOvvFmtnUcrgTXb7kF1Q3PONnU/UdysVcCqspBe7Huu/QEEmesXqZ0yxz2elNVcj2YH4S5Hlfj5bD8Zcw4dAQTNL30CHYATkb8kIzotfDzZTVxty+KnX/YW3MiATnouKogq5pFruMgON/KKYWVdwlJ70a3yuc+B0DhHk2XKMVo5z4MIdy3AmhptDGAIN4DaTO43Drc2QWjktPlu5OwywtIEF7u3Dyo+1pQhqtPRQkwcMRgnIqRtDxFlV+sBFXp/dQu7EFWY9x4x732xW50SV/dHyYrurNRaewdHpc398h+y54e/BaDreznynv+Hwx/4ewAyNx6guWm+7+yr3jB4n4V5kJpwY2fGaUGxjp0fbdFERDF6apccwlW9sSPCLVKpoe7zO4GOpMSyMIM1lUf5yRGEE1xbUMUS0taG4LkSVd9dM76rESpMJtydUZaXvY/oHhUnXQA4+5YJKlD603d1JU8E5416MF5gbY0nJVCla7+nfoKrB+MQ7hcC92utO5e6fwBDsv9vrfUs8LLo8R/dpfFN8CRhz3v+kfz3v63rsYyVx9dmkl+J3JKFDWoA4ZYh+BYUx8i7XqmY/t+jc4Zwy5lFLE/jnz3fImXW7BwZa5qmHm31sRr1vWY7Kty3RNXgL55/tPXYOz/5Vzy2Azl24j5DMwG9b+3TI79mrbaGVjbLuWlkPppcRhnMwcYWdloMlT/esXwdWgue2BovO1IphZZ1sk7e9Or2GAKpKO88nzek8lyx/RM/F/WYzqTMeK1ctiVlTtxXZA4kIpLo3WwEMY0vfByI8jCnMqRkgbrqJrfrkeyyk3ADHP7A3Rz5vXew98e+3RhCXdqM9lXFiibUQpgxvXB/u9qd99J86PX/xN985//bemwpdZCGON/Vp65FHR0ZqvWSv/BclAW90CbQ9/6rD3Jb9o0oa6PPMPAr0Tm8N9cdg9UL77pDBBXjXeCfOYflaQI7RVO1368SVbjn0v39vekXmJi4+r98DBWClzakZq2WsEglfDxreD+2THktA7DY2GuQc3UvrGyKsGLOqerdf8LW588z+/XHtnWHFtmCUdAk5MLH8Vd2YbQxmPFGiyabyR4DYbGE5bWJq5ASOysI1rvJZFjTrditQkS4q1FcWymqcGecFDIVEe5K8sJgc62Ou2x+U9Y+cz0KV7vJfexePQrhBojT3LY7toUf+xWmX7CfhR/78dZjqRe9ukX88699fetx74WvGfg+QkrTMlDcWSUoqPjYheH96TFkzhwDnZCisBOoehPpjp9bKTPDWxN2NJbY+X5qvp3M0ZNdP8G1h7BSRUYtFdK1+tRl1yL0AMItPZtwl9z/w+gaH8+jANxD5tp25pd+j/o/va/1eOPkaexs/zXTStuE5Wtf4j/B1YNxCPcC0GuR/I1AA3gXgNb6k8A9wHN2ZXQTXFFknSm0NBODakS4LUegGskXSeFD3TWO5qNitbbaIp0xnBmX5oU1wotGPGHNL5F3Cigx2upjNcE07Tn7jJHWI2snAWPW9scnfoFvf//3jjzWYWjqLbQWNKzH+fKF0QhwyS8idMbEME1FGcTrZgEgLG5vEJX1PGQ4w/HiQ3ymx3xpGNaqZYTQ5Nws0rX75JI6qrDORk6iK5U24V6JyPhc2nxfcpvqTOzCGjtQe882pm+NBz8PQFBR2DNT5KxCX4V4M4oDyvbkTltLh0i95HUU/sMvkb91AX/DfN9htd4nV/3WG7rlsQenF8h35GEfnb4OZJ2vXDSXsngxgqwhRr2mLsG5SHXRYVIlpTQKCqH7vvtH18wk+lBhb9LhacG7+TYAGl/8BI0zl/AW01gyRVO3j2s1qKKVi231nxfuHS9DWJraffeBEqSjGLb1epJqQOHZwwm3SHmoIHKsj428tpE5x7CmsoQ1w9bj1IP5X3j3tq8TUpq+xkr/pEdvrRplwczMSGOA9uRLbSYb4YSlKlaq+5ZnT3kEm23Cr6ollC+wZ8z5G1e4a9H1sNgi3GlERLhjuXDXvlbPmQiyQweisc0g7f5KsY4zv/Ojfc7D7/97jvzeO7bdTjgue/7ow2Re94OJz2de+wOAiQyLY/YGwU5bhMXxey+1UoRVjTU7ommZlzYLMAPuN+NCNXykt32WfC9kJoMOd7cCrWo1EBq8NNZMZBa4OiHc1zpUpYblmWuO9Hbf/f5qhA5BOP3eGzJto+q78/lbcYYdC5XOkXYFu/Hgva1/N89v4C31K6Vkuh2tOcEEVwLjEO4s0LoDCSEkcCfwea115934JDB8tjnBVYkptwCyTtVv0AjraGUjHSvxIqnrVYQSNBxB2R99lXCzsY5UU129ye5iAX+tRhBlItqL+5j2ZsGqjRQ5Vosq3J3E6qb5/WgtWKmYvun7zptKZWhfHDvGrBdKKUJZpIDJYf79L35wpNfVghK2jnoq40ikVhzaaNLLjFygLL/Kj3z8O0Ye78WoAjfl5k38k99NuGPCsDBvSOVqba3jtebGthBVgK0pM3keVJ1p9yoaAuHceCfC0jSOHzdkJsrDzLvTKNlNVOKs45wzuHfYWV7AL2nTu1xtYqXNjf2Vi/+OKX0bB6aHV/6etWhuyp85/WUAHt+4aKLacsuJpi7x92MtdztuXz9nemgfXDnR9fjJzXPR84NNrQC8O9oLEY1Lxm3VFikC1Z7k18MqQicTZeGlSC15VL9qFgRyEdnc6iHccYJAyh5+bsmUMQCjUWsZ341KuJ09SwRVCM48RuPREzg5+rLMB+7XBt3sn/QE5x8HjMHcqGgR7q3kfmNVqWNluieCxsCqfT0Iz5j+cyuK3ZpJRxXu6BoXm6dl3RQiWuTQCbnRzYc+C4B7tD0JtDKCYLOnZSFSdYyaFW3vPULqJa8badthEKkMR3731zjy3r/YdluZcQgr418z1epZtBIDI8z6xiQlwupPUdgpVCNApraPtutFnLCgirvnYKzrjZaBmzUbRWFeOrfNqyZ4uiOsNpDRPUqm3F13v78aoUMQbj/htlLdUaiXg7gNTnbc770Xv5rUktlv42vG50YHAY01H+9Av+JM7uJ4JphgFIxDuFeBzsaxO4Ec0Kupdekg5hM8fTAdyYbPFzeohzWEdpGuRCesysaTkbrb7m8cBeVgHVd0VzzcfXvwy5rgvKk6WosHmEubKsATCbnIvYgnwzm3TSpc20aqKdZq5vUPr7bdgd/7wCdHHm8SLlVLCOlz6+xzEME096+O5uBbV2UcYeSVqZe9DqRm6y/+EDAGUXZh+37VcFjw76DxxoTby5lKZk90UiwDz88sopXHRr3dB7xaNTe2pawh0LEcUq0lTxZ1ZKAXrzwL28abc2ievUB4ymRo2wuLzKbmENJnrdom3bHbfd4dfByc/QdAC4LHHyKs+ci0mVD/99f8Bz79r/5822Nx1yGzSHLfilEIPNzhmi/dfhfZtuFKN4E8NmsI9alid4vC2bL5++bF4ZFYzi0vQFiayqc+g/IF3vXHcGSKQHcS7hpSDybK3oFFGmvmu8xedwNaOa1Yvxhb9djfYDjhjsmjKq23JzMjypxzr3oDIKh84D3UT6/j7Rs9hknYAu33X1/CSIFgzS30PTcIsaoiNiLre89qE5npJmD27DRBpTMt4KTZ74KZoNmWhVZ2y8yuHdWWR0ZkXFUTCPfD9wPg3nRH6zEr6xD2xEHFihAxIuHeTaRe+m04N9yx7XZWLkVYHb8SFJw5DoC9mGwumARp05eisFOoptoZ4Y69AAYs3OxoLLU6URIfVtROFa5e6N5mc5Vz3/tyGl/82K7td4KnFqrmtwl32u27916L0AqE2/+7k5nUrrn/t8wmOwi3NbvMkU88gLdg0XjCzE/8r30BHQrco0f73sPKeLueRjDBBMMwDuH+HHCnEOK1QggHeDuggY/0bHcj8OTlMU3wpCGWDZ8trtEI6wjtIjwb1ewnebHstO60c7BHQV1tkbG65ZPO4SOgBfWvGhJkLR9iIWMI96mt7Ql3PTATtDjCJ4bLNEXfLAw8vtmW/j689vjI401CK087u0je2s9Gs7fTIhlNVcGzDOF2jtxK4fZlNj97Al2vEtQ01vT2ROWmQrtbY7M2msxzNSLcM6l8lzlWjLhvWeansVSOot8m3OtRT/CeqL9bzphqVbia/BNvxd90EAi7kCYo1gnORu7Vy/tb3++J9fakc7NuxpH3BhNu9zpjitZ86F7CaoCVH91UC+D6+T0Q5jm+aVbAH4sk4NfN7o1MXbrP5XDNTLqtvd037OVIArzZ6KnS1zfQymYpN/y7FLZN5nCO0sPm+KZuuxNXpghpV/eaYQ1LDCbK7qG2U7Vz/W1InelzYI97jretcEcGYKq02e4rnhpN5pz6hjdhpTRbf/8PNDdDUsdGq24DCFsmXl/CaKHDWhxdLCUL0WJQQrQbRCZsue5rhL0wj/JFKxM9WDG/ZXt5f3uM2m0R7q3oHJ1N5xFRJVQnSMr9x8257t7abnGw82mCcnf1NpYai9R45/GVhJXPDjVKHITw7Enz+iERZr0QlkhUPOwEhnBvnyXfi1jZEd/jdmUsjSbSiXp5F8w5Ha5339s23vUf2frCCqu/8l93bb8TPLUI60EraUGmUtc84db1KmiBdJIId4ZwiP/LOGgtChf61TOp/XPUz5cJz5+k8flPAODddmfCeNJD/WgmmGC3MQ7hfheggL8DqsAbMFFgH403EELsAW4FvrCLY5zgCmEh6mM9W1ylqepIXJNJmhCREk9GGg5Ug9EJdyC2mHK6J/Le1z0XgK17zyGkRkzNMp8x5P9SQsxRL+qRoVHe6yYVGWuWmtrg0dXzPLj2BbSy0VpwtnR560GPR9Fme/MLLKcP0ZQXCMLtJ6QBVdJW20Aofftt6FDQ+MLH0KHAnt9eevm73/Z2Xjht+i+Pr432OdbrUY92ptBljhVDlSLCPb2AI6aodriHbzbMv/dNReZPMeEeoDxIIhDWdJ6gHBBEeZj2noPsyZn36XREj7/rxezgyqr73K8HoHbvpwiqAvfg6JP5GAV5hEtNIwU/VTTH8Ma5/UjX6jN1CdY3kI5G9hDo5aj625slXmpuIfVo5Cl3V5uMpV/5FlJWGiU6CLeu4Qwj3Ne3Y7fcW56HpTNUg27y19lzPAyxjFaXN9sLMCMSbmHbTL/0FiqPVUBD7jXfPtLrAKQt+1zzoV3964ww3Pa9onNUlQbketd13wKNPW98C4KzphobXjK/basjdquTcMeJDHOZqXaFO2HhK9zcMhncHQtPViFHUOn+8e00K/pKwi7kCet0Of8Ogq5XW7FswYpZ5IyN2kaBdESiomonUL7JZh8XsVng7hNu48VgLZrFnHCjW7K+cfc9ABQfWuPkN90xMN5ugqcPVFO34hVlevfN+K42qLK5h8cJDp2Q+SjKchfO61gZZM32q2dyr3o1YR3OvPWNVD/zSYSlSb302/rHk8kQ+qNd1yaYYDcw8l1ea/0p4M0YMn0WeB/wWq115xLR92NI+T/t5iAnuDI4WDCTzzPFi/iqgSU8UxFNJNzmwlp3oeaP1kHQDAK0rFLwuglV6uVvpvA8s+rvztgIKVnIGoKzWt0+GqwRGpJS6KmMTrvzBGKD7/7bH2FT3I/UWaSa4mLt8pzKT20aMnCgsMSx6aMI6fOl89tXzbWskrXbrsvWkvnMpf/1JwCknnfXtu+RclyetXgDACc2RvscmzVDoObSU4h0qmWOFaPVdz2zQNoqUFdtwlJqltDKopCKes/njRxSDcjl7exVjGHPzRDWoXncKBic65/F3ikjFT7boWBYq5lzajk3yyDYh25GuprSZyLJ7rEbB247CEfyN+JbK6xVS5yvrKC15Ib5vchUv6lLuFXESvdHC+W9NFo5lJvdFeVKWMTSo7ky59/8QwAsfPvzEakMnkyDaFf3Al3HEYOJsnurWaiy0ho5s4gjstRVb4V7REl53LdaLraN7xKqB4Mw/6vvIXssx+JbXkL6m75z5NcJW/Z5CgCE64aM9PbOD0MrZixBUq4bdZQvsKa6Xc9j6Xi4YhaD4kxu++D17ffFpRn11pei73s+M4WI8tF1gmlkWCpjed3njbM4T1jr3n6n0VVXErJQQCuBHoGAnvmOb+DES59FeOEJggtRO8b+YyPvS9gSldBiMC50EKAD0ZKHj4N4cS2+x+0GdMNHuuaaGC8ixbnwYEz2/LLJSQeonWngf/mzu7b/CZ4aqCZY2YhwZzLoQFzTCyk69v9IINz23AJoQRgtbl4OjNeKNrGFPZj6wZ9m9hU3Uj1To/LACdL70n0L5gAylwUl0NV+hdIEEzwZGGtZXWv9Aa3187XWh7XW36m1Pt3z/Du01o7W+o92d5gTXAkcnTWTz/Pli/i6joWHTLnooF92oyPZacNpE97tcKa4hhCa2VQ3oRJSsuePPsx1f/7bHP57IwFajky31qojVLjDOloL0j3OmAvpRbBq1IWRiWrRwGOOLX97mfowPLZ5EoDn7L2OO5YN+f3cma8OH6PfBFkn77aNqOK+4NI9D4HUpF82OA+3EwcL5ns6s5WcN9yLWKq9kC20zLF0vdOZuWqq0tkCOXuaQLRvQGW/1HJWB5DzkRxyI9lQqLNXMYY9b260lXvvw85o7EM3cSha3Fkpt4n7RmT4tW9IP6uQEm8xRf2CmZS7N48fiPCc5dsQQvOR4/exVruEVHnT85/2+kxUgo0ydn6AcZlOU+mpKDfCEq4cbZLv3PAcbvjY3cz94nsASDtptGi0IstCXceVQwj3zc8HoXFnzPg8K4evu8lfbGiY87arcEfksYtwj2FYlitw8IP3MvfzvzfyawCEY6GChAW9iDRbc2NIymfMIk48/k7EJn+xB0EMO5b3RhL2YHUVYWnkbNtkRwoPP4prq/jm+C5k88got17XEgh3pY7V46BvL+8BBMHJ9rVC1xotqfHViti4Llx5Yuh2jS9+gvKjJZobmtVf+HH806cRUmPtOTzyvqRroXfBWEqXIqf97GADxoFjmIpbE3aPcKtmiIgc04WXQjqacKu9sOk/bESBC//6O5j/NhNtWL/347u2/wmuPHStglaidQ7Giz/xuXktolXhzvTfA+29RtkRRF4ul4OwUkE6g5VB6ee+AJSgsa7IPCt5UT7O8Fabo82jJpjgcnH16tgmuOK4bmYZrQUXq6uEuoktU4hUsgwqnhDXHTEy4T4VZSfG/budEFLiPedlrUl+TLg3G9vnvzbCBmi7y/kcYDkbZyebCe1/fvY7yNsL1NTluc+eLj0B4RTL+Rmes9dUwo5vnBr6mnMlU80oeJ2E+7AZ/2pIaskdmeAciWRU58qj3Si2moYULman29Lhjpu+qrRlrdPuDFqWW6SvGpSwdHvSasWEu5isPFCNfgJhLxryUjlRIbXfrDQfmDbkaL3RntQWm0W0Fixv0//sHWhnYru3vWjotkn4ukUjcT2xcY6iv4pLJJdPMFEJig3s6WQCbSX0TDd1hbQczd0bwNpzuDVpSNtphNCUmqaaGoo6KWswURbpLKkFh9R15jtJWzkC3S1vLkeS8s6M+sT3ykYZ1pUiuloDNGLEqKrLQZJrPkBYLiMsjUiPXqGUU1GFu9wv8Y5N/uRU97ll7THS8eBSRLjXN7CzoluhgYevzTWuGlTQyiHluIhMNGFLINyq2uhzRHf2m/POf7xNuFVjZ1nRVxKxcV2wMvwaV/yz/wFCY2c0jcfPUnv0NKk9KURCP+cgCMdCJZwP46KV05sw8d8OLcJd3l5dNSpUM0B2ODdbKdF1njYffQgA9+bbmfvZ3wKhqXz6k6it3XNKn+DKItww9+e4RaFlxre5e2Z8VxvianHS787ZZ65/wenHLns/qlpD9huht5B+yatb/y58379P3KbVOrI+IdwTXBmMTLiFEFIIkRFCWD2Pe0KItwsh/qcQ4leFEKNbkk5wVcG1bYTKsdFYI9QNHOGavqOgv88ldrZuONYYFW4zCVrObU8s4x7ZrREItx82Ebr/6nto2sRcCdlkv/0NfN8dL2c+tUQoN1qEcidYb54lIwyJ3D9lPktvL28vzkfpB04+AAAgAElEQVQEdzbVnvDbB25o/Tt9dH/fawbh6Iz5XJeqo03G1mpraC1ZyhVavVVxjiWYvutY1jqTmkEIxdnIeKoelnFE++Yp8jNYKU3lCw8m9j6Zyl53idvqMKBK3WBuuguZPFrLrhirUrOIUKnE3OlOTL3uTa1/j5pf3InDM+YSdaG6SlWtkrcNUTM9dt1qjqCisOeSe8ptkaYR9sSIiTJZZ3TC3YmsY45z7NyuRYOUNbxCd+gDH2XxN98LgGel0KL7t1iJyHtuux7uqFqrqmVUtTq0erCbEI6N9vvPI1WpDp1QJb6XbSNtbRQbve9XjHNbewn3YaBtjhdsVrBzPU7mwiPoINxxVFtLUp6QGx1WfWSmWxlhHzKLc8GZdpScqu8sK/pKwokWBsNzJ4du1zy7gpMTZI4t0FgpU19pkL7x4NDX9GLQAsy40BFRjatYY40hWgwc5AWwo/H4Cul1EO60TdCRbe4/bmS27s13InMFLA82P3uaCz/+Xbs2hiuB+qc/NOmJjaAjl/sW4Y4J3i66319tiBepkhZK7UNmvuOfO9333Nj7qTWQ3uD7k33MpC+4MxL3jq9P3CaOZlWbl6d4nGCCUTHOjOpngRLw4vgBIYQAPgb8MvAW4D8B9wghRsuTmeCqg6MLFP0NQlEjZWVNL06PBBnaztZN26Y5IuE+XzKToNgwaxhSjotWHuXm9v01TdVA0D87j6ObIMoYB5azywgZ8Nj6hb7tR0WdFRY801ua9bzEOKZerJTNhD92ggeQ0+3j4N14Q99rBiHreRBmWG+MduNeqZ7BDueNbDoTVTI7qjeq1mj1Fy5lzZgej/rDm7rSJZEWUjL/5ldQPVmj+v7f7dtXsFXDLnSTO3t/O00w/cKXAiClRKgMJb993CpBCam3l4Bm3/TvOPzbv8Kh39iZm++h6QWj5KhcILBW2ZMxpMAqFAgb7R7bcH0F5QucheRoKk9maXZUlJVSaFllyhk9FqsT2YgUr1dLZkFINMkMySQHkDOLLTm4IdzdcpRqZCg4ldrmfaKFC10poWr1scnuTiEcGxUkEO5qHWvIhGoQpAthtd/EUW1FEuOeCrec2wNSE26Y55MUDbb0CCPCXQ+rrai2uC8wjsLrRFgPW+7EMZwjtwDgn21POINKEys3vrHXlYR90PRgbzdRDrfKWDkH98BegqpAK0H6eeMpUIRroxIWYMZFbHg2apZ8J1qtCaXd6+1UvkZ47YWcOLkhhn/mDNLVrfz6+TcaklC6//LJyZVC7cN/weM/9DaO33kLJ+76umc88Q43o0WfFuHefff7qw0tP5hsvu85+5BJGIm9HS5rP7UG0h28UCmk5Pq7/5ojd39i4DaxkiX+niaY4MnGODOabwLOa607Q4xfB7wQeBT4SeB/AweBH961EU5wRZG2pqmFGyhRIe8W2hLkHmlbHP9UdxyaajTCfalqbjSHZkbL1pWqv0c2Cb5KrnDfMN+urE5HRm1LWVORPj1C3FgSTqxfAKvKwXw7+kjqDBW/v2+0ExcjB+6FAQ7cqWe9IPHxQfBY4EJttHizreA8ectUxWUkHdbljgp3vYn0TFV5T94Q7tORGiHQlS5ndYCpf/VTADS+/KW+fQXlAGu6+2bbaZqUff2/bf2711W7FpaxxWgS0PQ3vJHMN3/PSNv2wig5MpwofRUhFEenDwPtjG//xIPms5w00WH2nuQ+4lRPz/RKeRMhFNOpna035l1znDfrFdaqZYTQrar3KEhZKYT0u9QbcUZ9fhtJecvhu1wyRl7Olek2Eq6DTihohtV665wcB9KV6Fr/9SiucFv5fv8IO2VcxQGCSog9203KPZlCYczsmmENC0OQRTaaQDf6TSPDhsbKd/9u5NJBhKUJLrQX+8JqiDU1msneUwVrxIlyUGxgT2W6jAyzr/7usfYlXQedsAAzLmIFT5JZ0rZjmB7sBbDj8fja+GdEsAo5wg7H+uaFNdzp9j1s9ud+h4U3PJewLggvDO+dv1oQJwsEVUFjLSQ4ft9TPKKnFq1Fn0it92SY8V1t0LH/RwLhFuksVkoTrF4+wVV1H5kargyyj9zSVdToRTtG8tr9Pia4ujDOrOoI8HDPY2/EZHF/j9b6NzEE/CLwHbszvAmuNHL2DA1WEdKn4E4jokmCqnT3s+mKIdxN28NXo+WmrtUiwj29uM2WBhZZauH2kx5fNZD09wnuzU+jlZnEzKXNxTWWs58t7kzW9eVo8nNkuu2ebOk0tWD4OM8WzWRkTz5ZTu8+7+VjjeOmwvOoyhOc3Kb/KAhDfHmRxbRZfBBxhbsjO7jz5rUvcg8/FxFuJbqd1cFkUgtL45871/W49puEdbDnu0mNnDdKg5kXH+zq57RFllrYHkdDlfHElSEfts5T5lEAbl8yUl/nUFTJO276KYPT5vnY3K4XaSuLEu3q5ulopXx2p4Q7ypHfrJVZq5nK/1iEO3IiLzbaY6q2IvO2qXBH/gGqUkbVmwj3yhBu6SWbMo4yoUp8P9cirCcQ7rI5niIh6iyW96ryFqopsOe6z1/X8lpxbU1dw4mM7ITjIqRG9+zPRGMJZI8jupASJyfxL5prjw4CwgZYMztTRFwpyEzeTJQvDb9mBpUAezqPe+OzAHByjGWYBiBcF5VwPowLFbslF8ZvORGOi7A1qtLfmrBT6ICuTHB7boag1o5Ial6s4C51nwfpO01qRe2TH9y1cTyZ0EG3uqb2qX94ikZydaClqonOwTbB2xj4mqc74ojEeDGyF3bOJli/fG8E1QiRqdG9IZLQUrJMCPcEVwjjzKrmgN4coruAM1rrLwJorQPgHkyVe4KnIWa8ObDMRXM2PY2Isq11T9Zs3CfpO27LwXc7bDY20cprRUxtB1dm2OBL/NxHh5veB9pHiv4Kt5QSSxnyExu1xRXclfLOVlnPR6/rJM5JcUy9+My5T0GY58UHb+oeo2Mml1aHK/IoeONNr0QIzR/f/7+HbvfQxdMI6XO4YEhj3MMa9+ADqEbQunnF7uEXKmsEYYiWdXLuAOJwqfsYhmeOgxbYC4t929/04P0s/d7dXY+nZK5Lkh3oCinryhBuV04hpCmtPj/qpXeO3QqAf9IQ7eCsWVzpjIjqRM7Jo0WtVVGOz404z35cxLF2xUal1cc95Y1X4TavbxOFOKO+kNqmwt1R1VO1JlbqymjKheugEkypVS3o64EeBUnRbtDux7Wm+xe8rKxDWK4TnjbuufbSnq7nXZmCSKof6FpXVJuwQdW7K9zhauSIXuhfeEkfW6LyyDrh+grhxdPm9zI7uhv8UwU7axNsDG6b0Y26WWybmyX14tcy85LDHPyD8RzrAYTnonchNSleYBk1S74X0iHRC2An0I06WglEpn3e2AuLJiJp5XFUaQO/pHEPdft4pF72bSA01Y9/ZFfG8WSjl7jU7/v8UzSSqwOtczCucLfM+HbPG+Bqg64OrnAD2FMpgs3+FpxxkdSyMy7kjJmnTAj3BFcK4xDuAGgtWwkh5oBjwKd6tqsAyb+2Ca56LGbaZGkhPYNwzaRX98gmVa2GsDVCegR6tAp3sbmJVKMTiLh3+G/O/PrQ7QLdwEqocAOkpLnJxQT5YMEQi4vVnfVRXayY1em9HYTblVl83e+MHGOrXuVieB+HUs/Htburdkf/9m84+t7xJ6avu/H5aC15eG14xMaXzhnyeMu86aNuRRmVOyrcDYWVNt/zvkhavNUosVLeQghNwe2vwNnTKYK1brl/cMYY/9jL+/q2N9XA7stN2sp3uWqHokrGvjKXjqwVkaEwx8GIbNrHbgfAPxNlMp83xMk+lBwrknNzCBm2Ksrny+acWsrubJIfk+utRoX1mHC7oy9AZKIe8M0Ov4X6iD3cIp0FqVHVGkGpgVUYP05pJxCeh1YJpoyNECs9/oRKeg4qIVYq9pyIFxY6YU1lCMtNglPJ52/aTqGjfPRA1/E6jOykI1A9Fe7wolF+9EaQAcz8wA+jAkHpPe8kPGdaQqz50RQ/TyXsQopgczABDc+dAATW/DwilWH59+7GfdZdY+9Heh7q8j3TWgsscavEuLA8iaqOtpC8/ViiSme6fd7EizrBqUdpPvAZQOBd370Yay3sI3tdnuI9Dz8t+qHj5BIAhKZ+fLir/bWO+HjE6qHOtp1rFXGrocglq7xkxku8Po+9n6beUeRfJ6wnoXVkggmGYRzCfRx4kRCtUuIbMHLyXsK9BExs/56mOFxoTzYXs7PtCnevaVq9jrTBwh2ZcFfCLVwxOqGqhm1SXPcH7yPUPnZChRsgb5ubXUyQ4/7xWN4+LuI+9AOF9sTdxDENnox+7MQDCNnkZQde0vecfeSWHU1MXdtGqinW6sNlnmdL5qd43azpQxZxH1m1w+zL18iI3BRSGbS2KDWLLWf16VS/PMyZL+AXuyuJwRlDIOw9owlcss4USphxxIZjOefKEO5cZGy2YN/aekzmCtgZjX8uMow7cxbpamOslYA44u18FPm2HmXGL+V2Rrhn0oZcl5oVNutmElBIjb5AFZuubXXEVDWCBlpLMs721WJpm4W0oKKwr5DMWbouaAHNnirxDidUMt0f7QagohaYJMLt7lumuaVoPGx6Tu0ovivGtGec+0+sX0D1RLVJW6Ab3dcmtWZ6neVMf/9g6pVvQdiaxtceIYxitqzF8dQtTwXsmSmCUkI+ZIRhi23jQKbToETLuHCnaGXJJ3zfI41jQGvCjsYSXR9kuqPCvWxakoJzj9P8sqkEu7c+t++1hVd/E34Z6h//m10Zy5OJ2GQutWiTu6FA8+LgRehnAuLjEUuXRSGKLbyGCV5sIBlX9XshU15fEsjY+/CbKF9g5S9vrmC+D01Yvna/jwmuLoxDuP8aIyv/iBDiF4B3Yqre7483EEJI4DnA5QftTfCU4Pq5dm/ynqm5DsLdLQMyLpECW7iEevBErBO1cI2MNbp8MnYGBvjiuRMDt1P4WDK5wj3rmZtdXNnOe2m08tis70xGtBG97kBHZnbGzqHE4Anio2vGafaWxcM72ucguExT8odL49dr3RV5GZHBTsId+iAzhtwY9/A0Zb/ESkS4O53VYziLCwRV3TUxDs6bzxm7Gm+HvDMFVp1mEHCpWkIIRcG7MkRvvWF66l+8t3uxwym4+JfMd9w8fwl3tr8yH+OGWSPTf/9XPw3ARt1U1XZKuKejKJVys8pmvRQ9NvqkIuOY32qp2f6t1sM6JBgKJkE6gmCjiPIF9sL2SQK7gfj6oqptmaVWCuWDzO2AcA+Y0KlqBSGTc72zr3gNaEHxHz8KgHWgu4Xg2cvGXfxjJ+5Di3pXVJtwJarRff0L14yvgjXbX7k2Jm2CsFgiiCrh9tKBvu2uNtjzUc/xgIXP4FzUfrHn8j6LnDbXmvDimct6n8sm3ANaE3YCHfeTZ9tqFWufURyFK2dpfO2rgMa9vX9BNv3S1wDQePDeXRnLk4mwUgahOfzx+0ldfwS/rFuLDc9EqFheHXnWWLGE+VqucNdjwp2sLJHpFKp5eYRbbVyI9nGZhFtKrBSE6xNJ+QRXBuMQ7ncBnwNeCvwXoAD8F611p3XpK4AZ4JP9L5/g6YDbltoGUfun5hFeLCnvIdyNJtKxsKVLOGKFO5AbzHqjyyd//WXvYlkaQvTD//R9fOiR5J4wpZs4Iplwv/7GV7Is72J/B0G2VI6S32/ccWL9Arf9wV2845/fO3BMxeYWhClSHeZfOTePlnWCMFkLeXLLSJNvXdhda4OsNUtNDZ/QbEQ513FeeLzyrCPCraolUKKrmih1mlpYacnn5zP9hNvet984ej/adqINLpkbob0/uee5F3GF+FxxvWX+tpC5Mv2srz3yrQC89Y5Xdz3uLM3gr5lzvblaw10abID2g895FTKY43899j8BI8MH2LuDbHCA2bQ5HuVmhWLDfD8zqdEl5dnIibzU0cPdVA2EHs1cRrqS5kVzvvT2MT9ZiE0ZdbU9CdXFddACKzt+P79IeYk9wGGlNjDqLPOq70bYmsqJCgjdd/6+4jrTavAv5x5ESJ+M3Sbt0rFQzW5i5p8y681x7nYvrIxNUKoSXjJKCmtPsinf1QR7bt70HF86m/h8cCFqv4gyu3cKK+pnDy9cnhxZVaowYIFlFMi0i6rvQjM5bQM3kWmPJfaFCC6cp/nEGZy8aEXzdcK56U4QmubJwQvOVwLNBz+D2hhu0KkqVaRjiIx79AZAUPnb9wxcpLnWoSrmeiKi2MbOtp1rFapeB6HBS/YMkZk0KuhvIRoH4WrUspPgkTEunCkH/9Izd1FogiuLkQm31roKvAT4FuBfA7drrd/Zs5kF/Ffgz3ZthBNcURzsiFE4OD2PjNyNewm3bvgIV2ILtxWZMwwrpQ2QdZYySyOP5ZuO3c7/eM3PASBkg3fe8+7E7RQ+jkyWzH7v7d/Ah7//t7GtdsSQI3JUw37C/Zufex9YRf74sV/pilbqRNnfQuruSdyUO4UQmouVZPfNlcoKWjldx3Y3MO3OE4jhq7PFZhGt/n/23jtOkqu+Fj/33gqdJ4ed3Z3NuxIKKKOIANkIRAYT7I9tMBgbfsZ+8N5zeBibZILBwAP/cALbYBOsZ0ywCc/IJtmSQFgI5ZVWG2d3J8/0dO6quve+P25Vh+nq7qruntXMqs/nM5+d7a5wp7uq7j3fcI6pvLsBEHdRJ9yyY+ESXc8rFAB0EkOJ57DYokQ6eo3yiS3+4JuV1/hqGoTJSs9aO3iZ8zPZZZxcc1XcA3i09wJvv/nncf8v3Y8Do+sEsnZOwc5J8PmTcHKAMd28RNbQNBxK3oACPQEAyFlZSEkDiwKux7ir7Jq1chXCPRwL7iOcNGLuOKqE2+ZlX8s8P1CDwV5VJKPbTGVQUFfMTdYICXEvg5HqwEO5SQ+wLJVADeK7D4nGEduh7mkWQZ2SPgDsG5kEeAoPrygbvGRNXz01NUir/oTW8eMgVEI/2FgiDAAsboDny+DLqjqFTe313W4zgY2oTLFXBr8efFm1toRVJW84j1sVwJe68+oVxSJYF7p/NGJCWD1oJkf12qY1ys10eBLUkLBmTqM8l4Yx7h9cIpEY9CSBPdO9d3E3OPrKN+DY857VchtRKFbuMeNCFaQ6/d5PYe1P3971+a0H7sTCW16mhAa3CIQb5KutkPLads5XyGIJlKFpVRiNxQBJGloUw6CyZukF4R5Nwl7tnRtBH320QijvFykll1J+S0r5GSnlQz7v/6uU8n1SytZKTn1sWtCaB2XSjIJ4C+L1JeU2B9UZdGpAkvaldw+5GYudKX9P42bYN1wl6FnuH2GXxIbepKTcDyZNoSQay7rumr0DAEAox7eO/MR334KTgb6uD33ILYOebVI+t1KehyaG6z7bXmA0OgawItLF5pNXzs6AipoS2FgSILKirCxcP/Jawm2QOMoij1XXmmrSpzzMvO42UEOi8KO7K6/xTBYs4k9q/OCpeZ9KL+D0mvpud6TOnYCU3/dh7DsAgCD3lb9W/9/bOlufNFIghCNbLiLnZEFEtOPv2dA0gEeQtTPIWqoccTQE4fYy3PmafmiriWWeH6jJIBz1/Wnb97TZujfwni9e+SUAiGWPcIdfUJFoxLcHmBfLoC2szszd6rmkxfytyFJ0F9LyYQDA/qFqRpoYegMxs87OwxhkIJr/sVgiCp63Yc2cATMlaGzza4yyUfUc5vP+hIenVwEiQYe7q4xgo6qf3fN07hSiWALRgj+L1oPGui99rYzFDcTWKjcTShGZiKJ0ch7WigNzR/NAtDEar1SePBnwMtv2moRzunm3oCiUwNx7zLj4usrr5aNHuh7D8sfejeV/O4xTr7ytYqW22SGKRVC9/hqkOoEolprssfUhymWQFm6OXluFSHdmywoA3CXczEcjIyz08RHYGbElRAn72Po4N2arfWxZVHq4rXVes44A0RgMZkKiPeF+3O1j3jcUTlSHUor3X/M32KXfgjKdwXyuceEhiQ2jSYbbD3GWgi3XKWxzjgI5gWFcAQD43ol7ffctyyxMuo5wu6XAczl/wp11lhCjvc/cbkuoRdrhxeb9jgWehYZqRp5QCsoA6Za1Cdc7miarxM5kcTiygHRZfdbbfQg30Q3E9gwif7jqxc2zBbAYa9i2GS6dUJm9RxaPYy6vJuBdQ8ErIDYCxgWXAwCyd6h+XuPCy1tunzDUZ7uQW0PRyYPK1vZb7UBkDAU7i4KjCONoLHhZdcqtRsnZNX31sgzWRFBwPWi0xiN918HA5+0GlYBesYZwu4sx1oGHspcxF7n6yg9RskDN5itB84IL1Xa2f1ZzZ3xfxUbu8qlqEIaaOoRdv1izFrIwxpuTaDaQhFOQyD48h8TTntzrPSjYmCLSfPGs7/s8kwUz0TTIEPw8KvDBV7rTXRVlu2lFQ6BxxGMQPaqE9vrJSbI+eGbu2obSrA3JCYx9+5rub0yNwVq1uyYFxTv+ASvvfVPo/ZyThyu/5770l023EyULNKK+fzY6hcQBdQ+IbPeiVMXH1XVXmneQ+8JHuz5eM5R/8n0svu1VPSmDF6XGIB/VCKTVG22AzQhZthqCDLXwCLdc65xwV9YsPagY1HfsgOSkYgnZRx8biaaEmxByhftjrPt/oJ9z9yf00Wv8yr5349mjvwYAIK5K8npbMOkIEF2DQc1AGe4TaTVhXtBBH/OLLrwat+55NgiR+O6x+xs3IA4MFjzDPWiOQNBMXdn4keVZEMpx2djVAI/g0eVHffe1ZQ4xVr9w8oTmHp7377MrYxkDRmfiPa0wPaCyQUeW/fsqAaDMszBoPWkjuopEAwBfdvtIh6vji2kJcG0edy19GVJSjDQhfdEL9sHOVAkSz5fB4sG/hyun9kNKgmNrJ7BUVJPonqEn1yLJuFRlZrIPr4BoEpHrnt9y+6RLuJfyWZR4DhrpzqpEI3EUeQ4FuwAptDqtgHbwFM3zNaJptiyDIZi9lufFDiLBJs9Nhpu6PbaypkqDV0oGw1s6VXrC8/Vet8prvnngwbxMfe+86J/VvHhMEXIpCa7aXhUFpBEDsoZwS9uCtSZg7GiuPM4GUpAOgbAIkre9qM1ftDnAXFVtvuRfZcQzebBI9/F75grI8dXOXCQ8SMsG1YMH/9aDxuKQgtRdl51CuNciXdeaYx6qBrXMpzUP7BnT0xA2AT97FPYT9+PU866EdX94mZwTv/luzH/++6GJu3O6Oq/ZZ5qXdPOSXXeP7fyXexCZ1GEvdZ6dl7aF0y+9FuVljtEXXw4tAaS/9E8dH68dFt//dix960Hkvvi/uz6WKFqgZv01SHQKYW2NDH0nEGUbRGv+HPAq6USm8/ubp9W+bKT7YKW+SwW67Md/2mbLPvroHq1myP8CcA+A3TX//3HAn3s2Zrh9nAv89xtfjk+84DcBqB4yABC+hJvBZAZA7KY9zx7O5mYhJcGFY53ZxkylXP/sdVlky3FACIfJgnv2jsXGQKiD05mqwvcDc8rSav/QTsTJLsyVGkvnhBAQNI+EXk+4b959MaQkeHDxsYZ9Hl04DbAsppO9F0ba7n4mc7nmk5cl84isI9xUIxAlFcEXbiaJ1pTuxz0vbKaUw5uVSOt71GRlPaJud16wwRLBM7xx0wTjI5jNz2CltAKISMf9z70CG56EPqAi9NHtsUqFRzMMmOqzWi5mYIkC9C4Jtyrnz6Hg5EFkOB/qpDvWolMl3JbIIcKCZcmpS1b1JOk6UxkUxPUmFjWiaWLVzXCPhrfLoq4wVUOGu8xBzRaE+6rnAACiu/wz0zdOX6rGxIeRrBEEIqYJURNvtA//FyAIjD3NM5ZsqBpIiL/4V5put5mgbVMBGK9Xez14rggW66Jp2gUd3gYQCb7WnXKwKNsgRheEO6HuGe4jFFb8zpdgPxpcNVwWCu4x6x0Yos94FgCAMAnz+uet360Cfd8hAID18I8x+5bXI3+igMztnwp8/vUQIQXpPAV6AHAWmmcmRYnXVckAgD6c6KpH1jn6ILKHFWFPvvQXEds3htKZTJu9Ogd1tU5Wb28unBoUomSDrQvyEY1C2ucv4VaBrlaE27UlzXQuVCYybovGSPd2ivpeFUi1jzeu3froo9doRbh/AuA+AMWa/wf9uW+DxtvHOUal5NOqL7GSjgTVdZgsAkIkSrx1lnuxOA8qUqEydrWYdLMDy8X6hZhngWRqwY+7I6nKIx+tKcU+sqIi9xeM7sKO+AGUyGlY63rFHlo4BULL2JHcUff6UCwBjY/hVO6JhnN9/gHVF/6SQ88OPL6gmIirHtfVYvMMAid5xNd5W1OdVryD+aor3DRW7b1MGsF6So0DFwMA7McfUMcqCrBkOGXpBJtE2plF1k6Dis3RyzryslsAAMa29uJvgxE15tVSFrYsIEI7U0X2EKEJ2DKPvJMBk+HI+6Cb4S461fYPh+QQ14L1gXte7MZod39DGJBKhru6KPcyGHQ0nN4DUCXccl3riSgL0GjzthOaGMCev/0Ytv/dv/i+f/30BZBCR5zV9yjTSKROpM16RLWiGIcuaXouT4AsjMDgkw0yMApCJZy0/0KZ5y2wePC2nqbn0TQwAxBr3ZEqYXNQo/OgEU25xGCpsYT+xP/3B3jiZb8M6+EfBhuL6whBUvUVG5FnvhS7P/luHLzrTrDh5uTBa2vJfevLyJ9Q94l92r+0vxlqK9ScmXA91c6ca1+XAJyV5nONsETlGeJBHxuGne28R9brGd/x+29A5PrbEDm4D04e4LMnOjpe2/OtqcBf/mgeudv/tKtj8YINmqj/PKjOIJu0rZwPaBfookn3vsp2HlDjLuFmI+Hnh/Vgk6rikq90XuLeRx9B0ZRwSymvklJeLaWcWff/QD/n7k/oYyNBXFui9T3cgksQQ0dEUxNKptQ6ip2xl2AgfImoh21uH/FKqX7CX3PPGwmR4d49qBY3x1aryq8nXeuuS7ftwXRyGoQ6OLoyV7ffHYLfnTAAACAASURBVE+oxfSNOxvL/4b0aaSdxnK7u2fvAngSzzvQuhe4E0y5C7jVsv8iSAgBSQsNGXliVK2MuLuAZjWVBwlXhZk54/j9y/2V4QHAuPgZAADr2BFIxwG3ADYYTll6LLIDFllA3lmFScKrUm8EBt/6xxh7yRUYfft6E4ZGeLZdq8UsOCkiqoW3sqpFTEvAIXkUeBomDedJnnKrA7wMtxACkuSR1IMdh0ZVcM3Ydm6U4tU5XReEmueHl91kHRBuj8CLfL1Gg7AlaKx19UXkuuc1JT6GpuG64Z/HK/b/XN3rNBqtE2mzjqhWFOOia5qex2vfMAY7z8CeaxBKwaIEPO3vIcyLHCzZm+oUFqXg2e5KuaUlQLog3PoOldG3j9e3FtX6Sqf//I8DHcsj3J4lYy2it7yqbdDFuPAagEis3PEQCJUwhilKM60tutbDergqbllbIh4EzsICCJUwJxOw083neWE13mPatm2QDsHMi67piHQ7syobr00pYmReopT/Sz+6I/Sx2iH7uY/Ams8hvicGLQ6sfuFzXR2PlwRYsj54SXTWVCciKKRtbVqRL9km0OUJYYps520GIpsDYZ1b/tWCjbjaFNmNq5roow8PfdG0PlqikoEqrxNN4wDRdUQ1ldVYK7W2uiiKZSS1zhfynrfxWrn+wZhzM9wRLXh25cCIIpcz6SrhniucBXgUE4kBbE+qPuInluuzCPfO3Q8pKW490ChRsDOxD5wtVQIAX374btz0mV/EovUYRrULeq5QDgDj8QFISZCx/CeL5UIOhHAMmPWEixoMoqyy94rc1KsLZ9zPeF/iarzm0mc2PT+b2FWxthGLpwFJoA2GE7rakdgBQsvIy7OIsHAEc6NAIjGM/vHnoR+8rO22w67C9F8+8kFIlkasS8Kd0FOQpIiyWEOchfssY7oJKSlKjspmLRdyIJRjMBJM7dtrG9HGzh3hJlE3oFfz/BCZLAiVFQu7MKiI8tQQbikEhF0NKHSKT73kt/E/bnxF3WvEPaZHxKwTJ0B1CbbrguZjTKjAUvzic9Mn3yuwKAPP+RNhXpJgqd5UqLCoBp7vTslZ2K1bCNpB338RAMA+UZ8Ntg9XxTQLh48HOpYslgBIkHhnzzcSjUNPEEhOkLx0AvGn7UJ50Qql1l2+787K785cc5FNPzjLq2AxAn1kEE7W/5yyVICwARavJ0HmxeoZmj+aBz/dWAHW9tzuWLWdSjchcrVq/SjfH7ykPwjsow/i9B99GnYW0CeGEZlKwl7uPOgjhQAvo+GeIIZWp/kQFuV77sCRqy7F/K+21hZ5siDs1oEu6iYJRM4/cBcEPJcH676YBoBbdUIkRLbz8fTRR1D0CXcfLeH1cK9X7ZQcIKZeySxnyy0i30LAoasYNjsXxIroBiAiyK4jl1nXHzymB89wH3KzuWfz1Qz2SnkeOhTR2OWKkZ1I13ufnsg+DoNPYdAnsjqd2g5CJB52++Nuf+QbSJP7IbVVbIuFF4oLAo0xEBFBzvKfLB53xdTGovUZFGJUvYNFJgtq1KsLX79DZRFedeEL2o7BGNJhzy6Bu383Gw5XIjudcok+y2LIOHdEr1cY9bx1mbou43p3hDtppECoA4cuI2V0IBomDZS5Co6dci3fhgMSbmdZZZa18e5744KCuFZJorakPJsDNZt7ubY+nvo+ajPcspAFJAGN914fgMbcHnS3Z9yaXYAxpLcce/T5v4Ttv/vLGP94932i5xIsYYBnG4mwyK1BcgI22JuAGY2b4Lly+w1bQDoS1OysfQkAtP3KR9o+Xd/vbB95EAAQnTJQOluq0x5oBlEsgmidXc8ejFF1nQ2/4c0wDx6AdAicI8E79/Lf/27l97Of+BJyX/hY4H2ddBZaUoc2PgpeIr5/c+k/vw6AwHzaxXWvx1/+Zkz8ggra2o/6O3+0Al9UzzC2QzkDaHueBqqrIG8vYT9eFWPVxsegjQ41DS4EgViZAyQBWxeAproG6XRGuPNf+zSOv+43wcsE2fvD9eGfK0hHgOrNCbcXRBW5zjPKolhqafEYBoRS1cLSJJDYRx+9REdXLSFkkBDytM2mUk4IOUQIeRsh5FuEkCcIISVCyBoh5G5CyFs9xXWf/Z5FCJFtfq4913/PZgCJqgVxbQ+3FEIRbsNARFehxpzVPCNxKr0EQm1MxrtbyBMRQ96pn+y984bJcCfNKMDjWCpWrWcKfBEJpko997m9Qacz9WV7ebGAIaO+f9vD3kFF4h9bmoEQAqfzx2re671gmgcqYyg4/rYrP5x5BABw5dSF9fuYRsXKiOcKDd7Zb7z6VvzglXfj1Zfe1Pb80YM7UTiVh+X2cbORcEGVvTU2cdsS3fdknWus98leKnbnHzwYUccjlGMk0kF/r9RhCXVPnHVFAcdiwYh79BKV1Ytc9zPhz9shaEoFWUSueg3zfAHM7GxBRV1FfVGjLu2p6Nd6zfcKlZ5xtyfRWszDmGhNPAmlSP3K/6oEM7cKtGQMTq7RLonPnQCABnLRKVgsAl7uruxW2ErQrlPQxABYVMKerb+frRMqSzvwszdBCoLSf/j3/NeNpVwG7VKDMPmsG5B6+hiiP/sa6HuVurn9xEOB9pW2hewDZ5C6uPo8Of3+5vZe6+FkStAGYtAn1fPZOf5wwzaF//g2ACD6nJfVvU4oRfz5rwQAWEcfCXzOyrmXl0GNeq96PclgL3WnYr8e9omqLZQ2OgZ9chy8TCDWllvs1RyVAPRQ/bOXGAaE05m/e/qLfw9qAPG9G6exYT9xP04+93LYT/i4wQSAdCRIC8LttU+IfBfVA2UbpIUwW1hQg4DnW1do9tFHLxDqqiWEvIgQch+AZQAPYvOplP87gI8CeBaAWQBfAXAvgMsAfAzADwkhrVaf8wA+2+SnO2PQLQqiaQCR9aJp5SIAAmoYiOuqpNLLNPvh4UU1+exKdUeoNMRQbCDc6rzxEBluANDkINZsNZkKIWDTFYyYSqn7oEu45wtVwi2EAKdpDBr+JOjQmLKz+e7JH+Hyv30OMuTBynsXjzdXLO4WykbKP8vykKuafvOe+qxDrXcwzxfBIo0T5FBA/+eBV/0ypCBY/dzfAwDYRDgV+gvczw0Adg/4BzM2M9YT7tdf+pqujjccqZK1iVh4KzkqDVhuhns2p67viUQwwj30e3+K/f/8eUSua66Y3GuwUVXh4CnPAoDIl8CinTEUr2xXFmoIt5vp98rNewniqaJn05BCwMlJ6BNbr1IjCLThQfBCI1ngC6qSxhOD6xY0FoEod9ejKnhVdb9T6IMG7KV6cSd7ZgaEScRf+AsAgPID7Zc6slRu6U0cBEO/+wlsv/0Haly7XWXlU41OGn4o3fkv4CWCxHOqwp2RseDZfyfHoQ0NIHLNzQCA1T/7QMM2xQcehp4E9H2NYoH6BapiyjoRbLx1505noMXrl6naUBTOSm8zkvapansAjcWhb1fzkn30gY6Oxxfde2K4/llADB2ShyPc9uM/BV88g/zhecQPjSFyaA+cgmywau0F1j79YRROlbD8wf/V0f6etk8z0AE3wFro/PsTZRvU7J2LBo0wiGJ3FTV99BEEgQk3IeQVUAT26VDK5Y9j86mUPwbgDQDGpJQ3SSl/Xkr5HAAXAngYwOVQxLsZDkspX9fkJ/xscZ6AUGX34EEUFcEjhomkqbI0a2X/LCsAHFlW5V/7RrojVAZVlkm1KLgZ7jAl5QAQpYMocrWYOpFeBKEWtsXV4j9umgCP4d7MP+A3v/EJAMBcLg1CbYzH/DO4F42rsvH7srdDaPVR8au3H/TbpSdQNlL+k9fJ7FFQZwQjsXV9ZKYJ6UbZecECi3Veehm55VXQk0Du8YwS1nnGraH23z8yCSnVYvTgyMaU3m8kjJpS/Hde8Rf4uUtu6Op4o7Fq+fe2ZHjiRmHAFmrxMOcS7qlksEw50TToB89tcRKJxECYBK/p6eMFC7TDa7JiO1OoPidEWn0ONNl7UT7qlrDLXAZiZQ5SkNBtFVsFbHQEwiEQ66yy+KLSuuiFLy4A0HiszmotLGSpAAgCEu2ScI8kYa/Wkxrr7Dz0FIN+4TUgTMJ6on1fsii3tkoKPa79yqLOPn2yzZYK5XvvAgBEb3hu5TVtIFh1hSzmwcsE2tgIIje9GKnLxrH63cca+sfL8xlEtvtXdtDkELSYhH1m1vf9VnDWCtCS9ZUK+sgg7EwXF4gP7Nk5UENi26+/EKk3/iG0aRUkd44d7uh4fEm1q62/J6ihQ4aoVJdC4NjLX4PHb/oZ8BJB/PrroW+bAiSBczJ8xUCQ8wGqb7+j/V1tn2YgugHCJEShc6s4Ue7OgWA9WESHKDZW7vTRR68RZhZ4BwAC4PcAjEgpL9xsKuVSyluklH8jpcyte/0EgDe5/31Vs9LyPvxBGOomWOn2cBEzgom4yp4t5pvbPJzJqrK8fcPdZbg9y6Ra5Gy1IIob4QSREtogLKn6iB50SyL3DFazrZKoCf17S8rv9LElFbHelvAn3LV93SbfDQCgzijAY9gz1HnvejtEWBy29J+8Vu1TSGk7G16n0ap3sCg6oPHOF6aEUiQu3wsAMEf1Bq/ZdojoBqhQpOWSid0dj2Mz4GCHHvO1uGG6Wo0wPRC+BYORCMpCXQ+ehd721ObOuDKzvoeOlzhYvDOBM+Jef7JUJUqe56ufSnS3oF4Pej4DfkbFZNlobzK9mw1eb/96W6kKuRjvTUsIiycgOalTrherC3UK4a3g9dPTSHciecbUBOyMqPQsS8dB8cQaonvHQTQNxrCG8um5NkdxrZL03inS08FRMFPCngumVF46/CiIJqFfdB12fez31ZisYKzPOakIp/fdRw4dgBQEYrW+1F6UBWiiOYnXhyOw5sORuLVPvgPF02VoqfoSam1yvGkveaewF1ZhDOkYfNuHQcwI9D1uFcFMOEV3D2LZ7T0fq78nSMSssxFsB+eJByAcFZBOXDCA1Gt/G/pONd/aHZTot4MXFCnNdGbbpVoNW4sVUh0Qhc5LuLsVRGwYT9QAL/Y2gNNHH34IQ7gvAPBDKeWHpJRbsf7Cy7pHAJyfKYgNAmH1GW6vXJNEIphKqY9ysdC8p2qpoDJM+4a7y4BEtSQcUk8ui26GO2xJ+YA5DEEzEELg8WVV8n7BaDXDSqj6ewlXC3hPsXzPYPtF5Tuu/X188yXfw2dv+1u88+qPbohCuYeYlgQn/hluh6QxYjaSNhqJqgWt4yjrkhYLpSBIPPc2AIA23FlvmYFhSKF3fX082TjYA1/QiyenQRwVxNrfwfFMmoDlBqVWS2rRtHNwcz/uqEnrVKlFSXQscOaR6loRtgrhTvWecFdE3/JZOHPKFlAb29Zqly0LbVJVKDln6kkI98jFeGNwrxPQpPuZ1mTST73iZzH7hhcH2t/rp+9WlT5yyWWAJCjfo/qTy3d/E7xMEL9WybmYU0Ow5tuXxkrb6WnPKQBoKQ3OUjACWz45i8iYAaJpiD3/FxHbHYUoBSMYXnBFm1TBROb5k68n3JYEa3HP6qMDcNZaLxszn3oPMp96T+X/6a99AwAw9LpfrT/WlHsdPtFZufd6SCFgLeWhj1QrwTS3NN6ZDed37sHzdWbrgrDENAFJApeDl+7+VwDAro//AXZ+9Yegg6PQdh9SYzsVXvW9HewFde/YuWpZfFB42j7UaK2dwCIUPNt5hlvaAjTSu5yZamEJpxnBV9oH2vroYz3CzAKrAILVMG1OHHD/tQA0Y4cThJB3EkL+ihDyMULI6wkhm3u1eg5AGIG0azLcbkk5NU1s97ygS819FVfLqwCPKLGyLpDQk5DrCHfBtUBKhDz2cGQYhDpYLGRxPK1K3mszrLdO/AYApfoMAKfWVOS3VZZeSpXFeOGhq7FzcASXbdvddYlxO8S1JCRpjBYrD24LMa2RBHsLUZlLK+uSZHe9rfGXvBGjL74ckx/6i472HzF2wJRTGxqYOBeI6L1ZBHzlpbfjpdv/By6aCE9gYiwJxyXcWSsDKUzE9B55qGwQWESDKKj7WAqh/NxTnV2TlR7uYg2B9whYKrzqezvQQZXNFmsr4PPqOcK2bT0tgiDQtu8GADhn65cBPK2IH+vgevWDV/rPXVLnnD6C4lkL+ccXA/kPexlu0mXPfuQZtwAACt/7vzh63UVY/JP3AQBit74aAGDumoadQ1thrXbexJ1AH47DXm1PWqQQKM8XYU5Xg5nU1CGsYATDOXMCAKDt2K32dQk3X64GQ6TjQNgENNE84KqPDsPOy5ZWZmc+8kWc+cgXq+deKyN58TBiL3xd/bGm3Qzvsd5keIvf/DvYGSB+zZWV12gsCUJlx73G3j1B190T1FSJAdGiIrAWpZ/eCxCJyLXVVi19vwoGrFfQ7wWslZrn5mpIAVCrBIC0zXBrKRNOuosebluCRHo3p7F4FLwcvK/ePv4wHr/+2Tjz6ps2rR96H5sTYVa4/wbgyrZbbV78nvvv11tk6C8A8C4AbwTwVgB/DeAUIeQ3N354mxeUkbqJUlQy3FFMJgYhJUW61HwCyVirYLL7/smUMQBCnYrXNQAU3ZLyZMiS8vGYKrM9ujyLU9mTgIhgerBaevsnz3sT9hrPhSCqO2E2ryafQy3Khv/85i/gnVf8BTTWu/LBdvBspGo/EwDIWiUQIhDTGz8X4nqlOjOPK7ukge6+G6IbGPvQFwL5Vvvhsy95H/7PSz7d1RjOJ+wbmcR7f+Z1He0b11MQblCqxIugsrs+1nOB2pK+ip1OqrNrklCqegRrMkie5yvdgEy/tk05EPCVZTgLKuuhTe7u+Xk2A7SdKmbtzNf34vJ0GoTJigJxt/AqEcSqyhIWvqVIGC8R2A/8Z9v9PcshT0G+U+gXXweqS6S/fResVYHcYxkYA6TynGNDrsXRSmtiIhzR05JyANBHh2Bn2peFi8UZ8DKBsatavUUjRnDCPev5YCsdEjrg+iinqxqyHjFr5QKgTW4DBAE/275EWwoBKQTsnIA+0qh8r+/z90jvFOnP/y2oITHw5nfVvU51ZUHVCZzVNIhWr64OqDY8oNqW1w75Bx+HOazV3Vt0ZBsIleCrnfVZN4PIrcHJS5gjihaI1XA6wbKo1kqkTYZbG0rAyXReJCtslezpFWgiDmEjMHm27lXihZn7l2D95Hs9G0cf5z/CEO53ARghhLyHENKd5OY5BiHkdQBeDaAA4O0+m6xBiandBGASQBLAFQA+DVWC/glCyBvbnOPXCCH/RQj5r8XF80vQnGjrMtxll3CbEVBKQUQMWbu5r2KBp2GQ7gm3Z5l0NlMtUCg66sGdMMMRi6mU6qs+mZ7HbOkI4tjdkGFNGQOQtIQPfP92/Cj9OUBEGgTIanHTnqdteEZ7PTzLp0cXZupeX3Yn9LjeuOj0ygPL96nFKxvofaltGEwmh7Bv5Nx5P/caH7vhc/jwdZ99socBAEjqKYAVYTkOyrwIKjd3dhtQNlCipJ4vlT7osc7bC6imlKE9VAh3jwhh3bnGdgBEwlldqZZWb9/b8/NsBrCpvepvXVwnmraWa7AW7Oo8KZfIunZuhR/eBUBloArf+3rb/WXeI9zdZbgJpYhMRmGtVBfisQurAdeKQn2htaewtAVoCyGpTsCGhyCs9qXJnnWYvqOGcJsmhB0so+csLACQ0FwfbDbkqkynq3NwhXC3ECXUPNXvY42WYoCyLvPATz8BsTwLyQm08Ub9E/3QlQCRsE4eb3ivE9grWZijZsPzgWgEotQZMSwfPwtztLHiqVJdFoBwl37wVRRPlzHwnGvqx0UpqAnwTO962AHAOfkoAAJjm1oP8HQ4SzSRr2r7tII2MqRU1jvIDkvHgeSk63aRWrBEUpX5Z4JZzVlHH638Hrbsvo+nNgLXOUkpjxFCngngywBeQQi5A8BpAL53jZTyo2EGQgj5EIBgTVr1uEVK2fSqJ4TcAuAvoWbsX5dSPrZ+GynlfWhUVr8PwBsJIQ8A+ASADxJC/q5ZdlxK+VcA/goArrrqqs6MFjcpCKMQTjUiLt3+SM9HlskY8k7zRUdZrGFA615QyrNMms2u4MJxVbZZckvKU2a4ns/pATWRH1mZQZmewf74Cxu2GYoMgeQkvnDij6A7O/CCXa/uZvgbgut2XIpvzALfPf5TXDt9qPL6ijuhJ/TGz0Xfq7YrPagueTb0lO+a6Ao/s//pT/YQKhiMDAA5FZSyRAGMbH7CTeNRcNcGyjmtMmBaSHu5WhCNQJSrC/hqhrv34oVE08AMgKczkEZRZbWSvfGj3mwgugEtCjjrPJB5Lg8W7aUomOvVu6bOYy+swBzV4OQdZL/zfQy+tfX+wiXcXn99N4js3Y7CTNWgJH5dNaBa8WDPNW+nAlxv4h6XlHv+znz+FLTp5i4YzknlL63tOlB5jUYjkAE1ong2C2pUSRR1q8B4TRm9lwn1+rv9oO90Vb9n/M1e+OlqP3L6k+9G4oVqrtWmGtszSCQGPUFgn+lNH60oOWBxH3JsEIhSePVqWSqgeLaIoRv3N7xHXCE/kWtPlrNf+QJAJAbf8s6G91iEgec674P2Az+tAhjGzingoZWKu0NQyJKb4TZbt1Zp4xOQ/AjE4gzYxK5w5/DaRWK9I9zUrabiy7OV67sV7JlqKb9Y622VQR/nN8LOAq8FsAeADlV+7QcCRW5DEW4AUwAOtd2qEU1Dx4SQGwF8DYAB4LeklJ/r4PifBPCHAEYBPAPADzo4xpYG0SjgVOMqVcKtHno6STb1ggYAh2SR0LvPonqWSfO56kOu7HoOh+0P3z2oMmh3nbkbhHBcOXGpz/mqC+cPPPP9uPXA5aHHvNF4zr5LIX/EcN/CA1BFHAqrbnlX0mzMcOv7VUlk+YiaYNnQ+amq/FTESFTdI2eyy7BlCRrp3cJko8CScbhOZlXhMbdfuBNQnUCWa2wMCwWASJAW1SndgEUpeDYHwRi06JYq/goNLWnAWedNzfNlsFgPVYM9UueK3dnpAvShGBJX7MDyHY/AfvynLdtXpJtp8yzbukHkkkuB7x8FoRKpy6cQf+WbKu8RN4Mu2hBu4ci2JCQsNNfznM+dbEm47Rn1jNf3PK3yGo3FIBxVQkva6GZIywKtWSVSV9hSrFWvAS8T6pWb+47XVf12zvjLADkzj1d+X/zaT5D/ierP1nfs8d1eH4nCWmz9uQeFsBzoo43VEFRndYG7oCjd+XVIThC96pqG94jrDe+VX7eCk14DM+BLSllMrxOa7AWcWfXdGHv2AXioIjYZFLJYrXxsBX2bCqY6Jw6HJtzCzULTaHftIrXwEg5n3/zL2PXt9o7G1my1wsfTB+mjjyAI48P9PwH8NgAG4N+hsrkf9fn5CMKTbUgpf1FKSTr4OdFkvNcD+CaAOIDflVL+adgxueMSALxmoe7TtFsQRFuX4Xb7hb2HXoQmYAn/CaRkW5C0gCGze8GisbgiwPP56kRQ4iVISRAPKQy1Z1hlu07bdwIAbjt4rc/5qmO+cfppDe9vBiTNKEy5AzO5+n62VTfanPIh3GxqDwiTKJ1VCxY6unG2ZX2cW3hBotnMChxZgk62QA93IqGshnJrlf5gbfu+jo9HdFqf4S4UQXW0JRedgsV0FI4sI3P/Ili8t6XDmw36aAL2ar1II8/bYIkeZpzcAKDIqOeTk3OgDaWQevUbAElQuONLLff3PNhJLwj3Nc8GAMR2xTH1+e+ADVdbX2iNQn0rKOXm3hJuNqbG4Qn1NYM9exYgEloN4VbZQQIZwGZN2g4IqwaRmEe4azK0Xq99K40EbfoQQCTsOX8vbud0fXl4Yabk7teYJQYAY2IE9mpvvJOFJUEjjc9JamqQ5RCm2S5K96o1ReSGWxve89ZMQUrKRS4PGvF/ZrGYAV7orXe0M68U2c1DqmLLu/+CwiPc7ez4vGCqPRNeZV1kXcId7x3hjr/8jTAGCQqnSoGsB62FDMxht88927qdpI8+ahEmw/3rAEoAniWlvGeDxtMTEEKuBfAtqF7sd0gpP9TlIb2ZpH1Y8jwE0RhEzcNdlNSCi7iTR0xLYY37R65PppdAiMRYrPuy5cmEIhPLhWpU0eIWILXQCtcx3YTJd6PMTkB3duDiyemGbaYS1THHeyjS0WuMm3twunxv3WtrJTX5DUQaI/eEUugpBmtVVS2wkfPTxuipiHE3KLVQWAWXZRh082e4PeVjsTwLvrgIEAm2w3+hHQQsqoMX1xPujcs8s0QE/KwFqkuM/fobNuw8mwH6+Chyh1fqsqO8yMGSPcw4eaQum4Usl8CLgDY6Av1Cpdlqn51ptXtF1JMmuifcxuU3g+oSxk4fe0WXcMt862WB4O3LbMOCjbtZwkV/AuvBmV+CFiMgNQ4K1FVvF2vLbXUNxDrCTQZGASLBszWE282EshaEm+gGtBiBM7/kP05XnG3gyknok+NY+oay/NJ2+we69R1T4D86Db50Fmy0OztGYUnQWCPhJoYGngufRXbm5gBI6PsaW428NjxRbK/SzfMlsIj/Ep0lYijP9riHe0m1BugXqcw8D0kmZSlYhlubdsUXz4RXWRcZ13GiSweCWrDRKQy/4rmY++t/BZ892bYlyF5zkLhgDOWVpUCtAX304SEMS9kB4PtbgGxfA+BfAaQAvEtK+b4uj/d0AAehyuT/q/sRbj0QjUHympJyV6iFRNQiK6GnIKh/P9ETKypqOhnvvmx5KtloQWbxMojsLKt047bnAQAmIv6L++2prdHbPGAMQtICRI0ISaasFoGDPoQbAPShKhHzFm99bH1sS6h7ZKmQBiclmGzzE242oBY4fHkezsoqmIk6ghD6ePEIeKGmpLxkgZobZznnkc3odAKJn/9vG3aezQB9+3ZITsDdEmAphLIWTPWuXJ8MjAKQELkcnJnHABBoExNgw5OguoQzv9Byf1kh3N23MRHdwO5Pfxxj7/5k43tuBl20yFZK2wIEUf7LPQRz6yWnXAAAIABJREFUA8R8qbVCur28Bn2g/l7yes+9bGErSJurljIXhFJQHXAWVyqVbtzNhNI2rUnGcATWgn8JrjOv+rEn//KrGPvI7dj1kd/Dtl9/YdOAgL5DlSI7TUTYgkIKAeEA1MdDnEZ0CCu8sJeztAQW9Seenq6ADGA3xguWb285ANBkPJSVVRA4SytgpqzY+4Ulk7LoJmLatPdV3A4Wwvfgyx7qM9SCjaogH5870XI7kVuDsAiM6e3u/5+SObg+OkSYVchZAJs6nEMIuRLAt6HI9nullO8OuN9v+fltE0KuA+DVr90upWwdTj5PQXQG6VQf7tLLcLsT94A5AEItrBYaHz6HF1Xm+9BouF4dP0y5Prpr5Wrk1RJlkOZt/C3xzptfi33m8/DhW37b9/09bqZlEJ3ZXZ0rDJgDIIRjuebzz1pqQh9qRrgnvMtdgo70Cff5gu3uAnW5mIYkZURZODHBJwNeDx1fPAMnnYUW705giiZiEKVqC4woWaDGxln1sYT6jM1d3WXatgL0XarU3z6iMpBi6YyycRvpXXDSI3U8n4dzUmmcalOKYOopBnupddmnKLgaI4nmIl5hYD7jVrBtuxtep+7xW5GnimK6T8lyN2Cu9RxfaS5slf3MB1E4VUJkf73wmGff5YnStYJ0nDrCDQDMIFi7dxanX/0cdZwK4W7tLKBPDtf5PNeifPwkWFRWPtPYC16Lwbd9uOmxPFFFr++4U8jsqrLG9ClRpqYBYYcn3PZKBnrSf01Co+pZIUvtBc9E0QHzybwDKsAlbBLoOEHB0xmwOAPRDVBNQuTCeWULL8MdbT3nkIFRZWuWDt//7Okl9KJ6pRbamKrycxZaq4574n7a5FRXPu19PDURZmXzJQCvI4REpZTFtls/ObgDwACANIBpQshnmmz3P6WUtbVN7wHwEULIowBmoOzDDgC4FEoE7k6okvqnJIim+We4o4rM7R/ajR+vAXfNHMYLDl1Vt++xtCr/e/qkv/hJGBiaBvBInQVZiRc69hoeiiXw1dc0n9RHYkl8+LrP4tqdnWj5nTsMmmqRcia7gjF3IvII93ATa5zIwQPA3acAEBCttwq6fTx5mEoOQUqCE2vHAWIh6uPDvtmgeQrGZ07AyRSgpbrLBrJUArxmXS9KNmiT0sxegGdVoMuY7j6ouNmh71XiV/bxw4iiRlV+tLfCi9QkENl8pbdX26nmD20wCmel9SJXuKKedHBjxSBJ0vULb7Ho9rLf7cpsw4ImBkA1Cb7anLSkv/JV6Elg/KNfqN/XzczLbPse3fUZbgBwihIAQe4xtb+X5WtHuI2d28F/fBZ8Za6uF16kl5B9ZAkDV+1sOx4PXh8wn2vdw94Onp+4X4kyjZiQAe3TauGsFaEP+pNOEnOrIortiTIvC9Ck/3HYoFsVtHSmYtnWLZy1ArSEyqhToxq4CopKIibShnBTChYB+Fr4/J3IuQGsHugz1IJNqKAUX2xdMeKcdZ9HE1OgBsDzm5UK9bEZESbD/W4AJwF8mRAS/Ml4buE1XwxCKao3+1n/dH0fVM93HMCNAF4KYBsUgf8VADdLKZ+y6giKcFf/L8tKUtjzOb16Si3C7j17uGHfs7mzkMLEdAC7hUBjkTEU7OqD2hJFsA0UhnrewSsw2ENFzI2Ap95+NlPNduRtNVmORP0nJvOyRpG4PrY+IrqBbex6HLO+DUIkYtrmvnYBQNulDC+cszPgWRtsoLv+PJZKKRE2VwBHlDlopLc9tLXwyoX1/c2MO84f6AeUm4M9ozKLfPYEAICN9za7bwxFYM2vwjqmxCC9a0QfGYCdbe1pJQoFECa7aksIAq9kXRSbL7o9yzDSRkiqE7AoaenFbC/lYE6lKlljDzTpaiYEUFiWjgDV6qtDJFc93d6jReTzoLpsG7g19ik1dfvh+q7E3Jf/CpITpF7xmrbj8eB53XdSllwLj3AzHw9xEo1AhNBMk0Jg7vW3orzIoQ37V1d4VYEeOW11LF4GWNL/WVgh3Atngw+wDZycBW1AjY+aFLwQrn9dloOVlAMAi2ng2fDZ4YoDQbI31SuV8WxTAT2+vNhyO+65aEzuANUJRLG3SvF9nN8IQ7j/AcAagFsBHCGE/JQQ8nVCyD/7/HxtY4bbGp0qm0spPyylfLGUcp+UckBKqUspJ6SUt0opPyNlLd186oGael1JubAU4SZuufK104cgJcXh5UbVyeXyHHQxElrUrBk0EkeRV0unbbE1lJg3Eh7hXqixS8tbinAPNQkWmM/4mY0fWB9PCv73c3+/8nvS2AIl5VN7ASLhzM3CLkjoY92VJ1cWo/NKlEdYHCy6caKH4x/6G0y+/rmIv/zNG3aOzQI6ul2Vg7qlzI674Ne2NYpOdgNz5zhK82WsfuNORMY1aLtUUFebGAcvkooish9ksVRnZbVR8MSVZItspSy6BKHHJeWAIi1OpvFzkI6D7Gc+CCvtwJhszPLTlBsoyLfPIUhHgOjr2jGIdM+vXue5AqjRXpTQcNWvrcfur3vdcUXwzKue0/YYHtjkHvXMWPYXYQsK4fqJ+xE4Go1CcqL68IMcK72A1bvUM0dr8gyjcbcNoQ3hFitzqlVjwJ9YsmFXyX+xd4RbWBI04RFuDaJYDrW/9zfRJlV1tWAxHTwX7vgAIFyBQq+6pFdQfesSfLm197in5M6mdoOaLPRn1MdTG2FY0AsB3OL+bkCVW9/mvu7308d5AhqLgdckFbwMt+drmzSj0PgozuSPN+yb44tIsN6V9hkkjnKNBZmDEvQtoMS8kZhwhbIWC1XCXeQFSGFAY/69q7UlfX2cX7hwrNqTH9c3f4abaBq0GEHp2GlAEGjbulPNr/aEK8kNYcmK/+1GgI1tx9DvfHzDbMc2EwilYFECZ1VlbvmC+ozZtt6W0xv790NyAjsHjL35Vyufrefhax9/qOm+oljeUFV6DyQSA4iEKDXPcnmWYe36WjuBlorCyTSee+3/fztOf/CzkJxA39kYCCGu20fhnrvankM6AmRdhnvf7X8Nc4xVdBLspTS0VHsdFf0CV2X+ZP06wRNd89Tpg4BomipLXgnnFb0eYk3t7wUhauH1WwcRlwMAfuZYdXxNRPK8NVOrawYAxKLqJaYD/orZdMQV+VruLsNfd04bFbV2FtEhiq0rSdajKqbb/lpnyRh4PrytWcWBINW9zWwtiG6Amcr7vBWcJSXYqG3fr4ISpd5as/VxfiNMHPhFGzaKPjY1aDwGCAJRyILGkpBlCyD1JXspbQfWnEbBCRtLGDZ752EdoQmsOdW+LS6LMJ/ihHubq96+XKyWCJacIohsndXb9ZHfA+mhvUYfmwO11SR+PuybEXpKR/F0DgCBvr27bCkbVr7yYskl3DbA4k/tZ0QvocU1OGsq6OllGLXtndu4+cG86HIA3wEAxF/5G5XX2bgKxvDZk8DTnuG7ryhbIMa5CX5QDZCl5lkuWXQzcgFISFhoo4MozlSz1Jm/fBfsMzNwFqoq7sbexv5e45LrEN+fwMq/P47U976C6LNe1vQcgksQvX6ZaFx6A2KHprF2jyKY1lIRsQPjbcdLhydBmISzTuhNZHOqBSDkZ1R7HXYKnvEIdyOBozFX4GxtBQgQoK71RI9eeZ3vNp6yvUdOmx7LfXaxIX9i6VmwiQB9+EEgbQuSk8rfTKMGnGy4cmnhJWIi7ecclkqAH22dTfY9h6ucTgd606JYCxaj4JnW1xNfXgHRJOjgKKipdRQ06OOpi8CEW0r5jY0cSB+bFxVV05UF0FgSPJcDW8flRs1JrIiHIISoLPgXcxmAlTAR71021aAmOGo8dkkZkS2gxLyR8NTba+3SyrwI2oZwx17w2g0dVx9PHqQwQWh5yxBubTCO4qzKqGi7uiNvdFQt/vnKAmSpAClIxQqpj+7Bkia4uxjnK2lQQ4L0WOfCvPJmAB9B4lCqrjdYG1O94ny+uZrwRqvS14JogGhFuL2M3AbogOjjY+ClGaXcbJdx5mO3N25z0McLWjcw+YGP4+gr34DSPd9rSbil00i4AdVbLCxVku3kAWNn+x5+JZZFwNP1pewin29YTwSBljThZLoTrfL62OlAI7H1gtGeFkQ7cFfhevr9/w3xl7/JdxtFRmWFnDY91rIS72JNrNY8wtkrH2ixpgJn3nOSxiLg5XAq4tLN2ntZ/FZggynwsqeCHzzvx7NZECrbemV3AhY3wLOtheKc1TVoUVU9Q6MG7NVgwnLLf/B68FwWPL2GiT/9xwZdhT6eGjj/a+D66BrUFRQRa0pQgq/lwKL1C5qJ+AQItTCXqz6kH19WE9BUInipWDvozIQk1VInScqIaE/t7NVYLAkpKTI1dmnlDRaT62Nzgwm1WByM9NavdKOgjVRLOvU9F3V1LOaW1POVJYhVle3zs/3pozNoqQScvFKT4ukMtGjvlxHajgPY/WfvxfbPf7vudeb2ijuLzUtpheWcM8JNdQJRbp7lEkXPKqn31582pZSVi//3Czj23JvVi25/tT5AENsZgXGRfxWAfuE1oLpE+XCj0GktJJcgRmO5OE2lABCU7vomAMDYEyxI5peV5vkSqBn+GmKpOHguXNnzeoisq3rtkzGlFcIdjHg6rie6vq/584tQCsKqbXnNwFcVAfb8oRvG5to/ej3N3aLSy+5luGNRCCucQrv0tH0CBDe1oWFAEojFcCrzIpsD3SA5DpaItM1Y80weWkLdDzQSCfQZyVIBC/94N5a/9RDSd8+gfPe3ejLePrYeejJTEkJeQwj5ACHkTYSQpzb7OQ9RIdyrLuHOFsHi9ZPw9qTKYj+yMFN57YllJTAxnepthhsu4S7ZFgi1t4QS80aCUgoiYnV2aWWRg4b+rfhUhU7UYtHZInqPxt69ld9Zl+XJFcKdXq0uJBNbI/CwFcCGUuBFCSkEnEweLLExauDR5/xcQyaITblqwkvN1YRF2dlQVfpaUJ2qFqsm8MTd/GynuoXuWqWtfvHvYWeB0dsuxcE7v4fhWw5i+lOfwq477mtK9ImmwZyIoHSidQ+w5ADRGwk3G1ABstI9/wEAMA5dEmjMtdURHkSx3JFtnzY0AKcQ3rar7twVSzMfcTm3/Nvzfm4H7rZXsKm9LbejGlpeMwAgMm7mvYm1nfe6N/5uId0svudvTRNxCFuppQc+hku4aTRAhntYBQzC+qjzXBEssjHBNC2VgFNoPV/ygg0ac63TYsEIt3P8YQBA4qD6bJ0urez62LoITLgJIW8lhCwQQm5e9/o/Afg8gN8B8EkA/0lIP7V2PoF6fqNrSjyE5y1oyXoyt2dIlZT906P/jtWCmgROrqk+pL3DvbOMMWsy3Ctuf1xiCwhDbTSYjKHgVMvLSmIFSb07tec+ti5+7ZLfgJQUN+3qLlt8rjD45ndWfu/WF54ObwOIBM+sVUslfWx/+ugM2sgIJCcQ6QU4mTK0gXPX0kOHJ5VK+mrzMl9hCVCzvYhXL0B0BmE1z7JWvImjvSfc2u5DAIDc4RUwU2L0T74INjyJiU9+DcalN7TdP7JrEuWFcktSJTlA/TLcrjBh4acPAlB94YHGnEqA5+u9tnjBAouGD5BUrsPVhfYbN4GXIfYjth75DOJXDgB8ZQUgEnSktegjYWh5zQCAyGabjgtQFROEytBe2U3Pl1FrOy8wyRIJQBLITDDBOMALIkggiC3YqErC8PmZNlvWg+dLYNGNsSBggynwUusgg7A4aESl2GkiDuGosvhWsI89AgBI3KisWHmL6pw+zm+EVSknAP7Te4EQ8mwALwOwCODjAB4AcBmA1/VuiH082fD6m7yoq1PgYKn6BcShEVXe9p8rf4tf+uo7AABnc6rE6oIa1eRuYbIICOGwHAdLBZXRjW8B66ONRoyNY9k+CodzOJyD0zRGIu2FbPo4P/FrVz8fD73ufkw3WbBtNtChcez8w1/D1Fua95MGBdE0MAMQaxmItLeQ7BPuXoG5PfKnXv5cWGsCxtS5e86oPuDWasLSFqAbaANXC2owSKt5Vky4lmEk3vsKC6/1QnICcyIaWiVfm5yAcEglu7keUghIQXz9zNmQKsHOPppGZFwDG98Z6JxsKAXHrY7wIEoOaCz898XG1HXnzBwJva8HnskqD3GfvzGMfRoA8LU1sAjafg9EI5DtCLfnN92khxsAqN7aAz4MKhn1uJfhVtcrX50PfAxpWyCs/d8PANou5cnunGq0km05zmI1w9xrMK/MfamFPoQlKoTbK4vnC62DBvZJ9TdGrnkmgKrSeR9PPYR5Qh8E8PA6T+pXApAAXiOl/O8AngkgA+AXezfEPp5sVBUx05COA15W0cBaXDhWnXAXy+oBtFhYhBQGxuO9E4iIaOpht1YqYLmgJqWk0c9wv2D3iyC0ZfzFj7+J46sLIJRjMta3/upj6yDxC2/DwFve35Nj0QgFzxWqokip3ovsPFWhjannSmnOBiSBPt1bS7B2YDEN3Md/2oOwsaE2cLUghgZhNc9wVbyJA5TZhgUdGocWUyWtxlR41WaWUvMyX2ri5Vx2s/M+GW7PBxoA4pc1KqE3gzY0rLyt16r+2bwswGLh25+0CRXID1uWXAueyYFF/C3kPOXyoErgTiYPLda+3JlqtD3hLhSUE0yLtRPRCUQhnJJ40/O5f6NXzVgJNoSoHhBlCyQgo9APXQYAsE41Wsm2Ai86G+Y4oY2qa5rPnmi6jbAlaNS1TvPEOeeabw8A9hnlzW4+/SYQTYIvB68a6OP8QhjCPQpg/ZP5JgCLUsrvAYCUMguVAd/Tk9H1sSngCYrwzBrE8hlAEmjD9eXK8RrfSYOqjPNqeQlMDNTZFHWLiKYedplyAatuSfmg2e/PfNsNr4AUGr578k48sqAe8LsGelfK30cfWwksqoHniuAtVIj76AzRn30V4rurVUXG/t7ZPgaBljDBs/6ZPSkEhKNEn84FqKlD2C1KUD3l5g1SJZ586+sBAPEbbgq9Lxt0CeWKfxZTFF0PcaMx+0xHqsHcxPNfHvycXlb6bNWzWlgATYSvUvME9PjsqdD7euDZQtMS5YoSeDZghjtXAou3z74SjULYrcuQRb4IqrXOFjODtlTIDwMvi0/cwGSVcDfXSlgPadsgAau92fAkmClhn50NNU5elmDJjUmweGXuzlzzjLV6tniE2/VCb3P9OXPzoIZUAbIogbPWG2X5jYJYXWgehOujK4RlQpVZjBCSBHAhakrMXaQB9Fc35xHoUNWCwjlzAgDARhoj6jcNq8m/wFUEL+csI0IHG7brBlE3w50pF5F2FwRbxfpoIxHTTVCRQM7O4OiKKonaN9y7Uv4++thKYDEDvGBVMzf9DHfPwMa2Y+fXf1T5v3HhFef2/KkYnII/YZH5NUAS0Og5ItyGAWm16IF2/ZY9/+VeI/nLv4MD//bPSL7hHaH39YJQfMU/i+lZmhGzkXBrrjBYbDqC2PODFzQytzqCnz2hzlEqQHIC1oGooeYK6DkL4UhbLXi+DJbwL2enw4pQBRUmc7IWWKp94IAYDLJFVQSgSsWp4Z95rxzHZBDl7lTaK+fz/K1dos28NsK1ED3ctgPCWo+5FvqADnshxPEdB8ICWHJjEixsXPXe8wV/sikKWUBUvcq1SdVG6TTZ3oO9uAo9pSIRLK63rM7ZDDj+gmfj8RtvQfbvPvRkD+W8QxjCfRLAVTX/v83d/851240ACO9o38emBR10J558riJy4UUDa/FnL3obdmjPgoVVOJyjiNMYM6d7OpaYrhZS2XIB6ZKaCIc2oFxvK0JDAgUng5MZNQFcONbbz76PPrYKWCIKXnSqC8kt0su+VVDnjb2/0et5I6ENDcDJiQqZrYVHEDZCFdwPNB4Db6FULEolVRoc2bigsLbjQOj+baDq8SxWl3zflwUvw+3T3zw0jv3//EVMf/PHoc5ZISmuUjNfUmRZ2YyFg7ZTlbI7LRTr24EXbLCEf3CGJIeU+GIA6y0pBJysgD7eXqiUagzSaa3+LYplUKP1d0pNDaLUK8Ltise5dmPUbSPka8E8yAGVlWdtxlwLfTQJeyW46JtYmQVAQAc2plqETboVE0tNKj7SrgCn+2xhk7tbbu/BXs1DH3JJejICJ9ubNoD1kLYVSlXe9xjlEqwVdYzcd/+9F8PqowZhntLfALCdEPJFQsjrAXwIgADwz+u2uxyKnPdxnoCYERAmIXJ58AWVPWWT/tnT0cg4JM3hByceBlgJF4/2ViU56paUZ60ispaKFA73CTcAwKRJFEUGs/lZSMGwb7h3/ud99LGVwBIxiJJoqULcR3cYf82NSF0y4is4tZGIXnUNJCcofudLDe+JjLsoDuAF3AuwgSSERSBtf5snkS+0LQ1+skDdPmyebkK4S26GO+JPSPWDl4V2FPCy0p5Ss3CtQ2kqPIki0Tio0b4nls+frJClhvdKskEAtnJ8SkE19R22Az/9BKQg0KfaV5URQ4OwW9tPiZIFarbuB6cRA6LcG9tHzy/eK6P3xNo8MbUgcHKlUBaB+sQo7IwITBL5orv2HOht1aQHr2qDrzS5H9bWEW7vWl72396Dk3GgjbqVA6kEeBvrsU4gClkce+ZlOPvzz+rqOM7JRyq/l453XjnShz/CzAIfAHAMwKsBfArATgB/JqU86m1ACLkWwAQay8z72OKgOiAKRXBXYVGb8M+ebktMgBCJ3/qPXwIAPHNXb8sN44Yi3LlyERlLLaaHY33CDQBRloItc5grnIYmxqCxjfGr7KOPzQ46kAK33MwNkSpb1UdPMfKuT2H7P577qT7+4tcCRCJ/x780vCe9nv1z5LvuLf5Fk55HUWhfGvxkgY6qElqRbqJSXlJEk5q9E6DzPKo9pWbuinKxgc7uTy1G4aRb98TOvOZFeOzam1D+8b/VvS5tC8IiYAPNs+vUCCZMZj/xAABA37m77bZE19pnuEt2W29yGjEhWijkh8F6kTY65FY1BuxfBwCes8CSwXvxIxddDMkJFt7yUuS+8DEcu+nihu+o7viLigCyoY2xOyUDoyBUwlnxD+Cst06jiQFQTYKvNg9KiLVl8DKBPqk+T21ooEGlvxdYed9bYK1KZO7vvNoDAOzjhwEAxhBFecGqPAP66A0CE24p5TKAKwD8BoD3AnihlPK31m22E8BfA/g/PRthH5sC1CAQxRIcN/rnTZzrMT2gJnFC1APlWXsv7uk44m5Jed4qomiriXAo2u/hBoCkPgBBcsg6Z5HSWnuB9tHH+QyWGgAkgXV6DszcnBnGPjoDm9iFyLiOwsONdlAio8jjRthw+Y5lyO2DbmINpEqDNyfhZqNKVJM3IVWVDHcPCTcdGKlTauZLc+5YOnPUYAkDPNOcFEghUJxVZddrn/+Luvcq7XFDzSWHqEErwnetYJ9U16K+51DbbamhQ9rN2xAAQJQ5aKR1tphGTYg2xwkKWagXaWNDStwuFOEuCmgDwVs5Ur/6DuhJYOU7RzDznr9CeZEj+0+fabq9J+5HhzemWolQChYl4E0CON6zpdZikrURQbOPuoGY7crFh42MAIJALPc2e1x+oqr27pw83PFxHPc6Tl59CFIQlO/9btdj66OKUKsQKWVGSvnnUsp3SSm/6fP+P0op3yilvLd3Q+xjM4CaDKJYBl9ZBWGy0uuzHs8/cDXi4hB+dvxNeOOBP0JM760fasJ0CbddRImriXCgL5oGAEgZAwArwmYLmIwF80Xto4/zEd4iunB0Geb4uRHQ6uPcQRuMgecby7ir9kYb0+e5Hp6gqNeL3DCeUhnUDFd2fa5A4gMAlVj8p3sw/+YXN7wvXY9nYvb2/qlVahbLKiPHxjpz1GAxE7zYvI9ZLFYDISJTT4y46+bBhptbqql1j3+7QC2cmRMAgukZEEOH4G0It8Urfs9NxxaLQvSmhRuiWAKtcX8j0bhqI8wHE/iS5RJ4mYANBS/3JpEYdnz8Ixh78RUwhlRQyjp1uun23NUaYCMbZ3fKYgw86/83Vywmk4M127cWQXOOKfKrTe9T/3rWY2eONt2nE/BsNehU+lHzKoF2sM+o+yV2rXI9cE4fa7V5HyGxOWeCPjYdWMwAz5fB1zJNfSsBYN/IJH74K429db1CwvAIdwklpwgpKaJ6o0/oUxGDkUEgp6oL9g/4VyD00cdTAV7ZIS8RmLv79njnG2g0AlFuzL6JnEu4N8iGaz3YiOvFu+yv9C1KTtvS4CcLhFIQAkgAK989gvWKH6KsFvG9zHAD9UrNXr8sG+vMUYPGIhCzzbOw9mP3VX7n63qx+bzbE9wiY8oieiBhMvvsWRAmwSbbe9ITQ4dsLVIOYVX9npuBxmLK07xc6vo7EqUyqF6ff6N642fWDJ4XtZ97TStErr8NketvwyiAUy+4GqVTzfuh+eqKe46NI9xavLnloBfMI7WEO2GC55pXQNinFLHW9yktIzau5iJn9iSMy3oyZHW8bAnR7SaKZ8oo3fcjJF71ls6OMzcHoknoBy4BAPCV7krU+6hH6JmAEMIAXAJgCkDTu1xK+eUuxtXHJgNLRlE+vYr/x96dx1mWlnWC/73ve85d48a+ZEZulZVVWVXUBkUhazEMgoACgoiiQjcNorg7yjj22N3a2to2NO46I4rO4K4oogMiyCqrVFFQ+16VmZVrRMZ24+7nvO/88Z5z13PXuBFxI/L3/XzykxEnzn3vGxEnIu5z3ud9Hj+bh5PevRcQmSDgLlSKKPllwLhD7fO9l82laqlxNy9cs4szIdpdaqYWPiRu2Nk+0bT9VDoJHVEdvFokb3xnOpOqYB90u9ZauuTBzexMxfRBGL/9zXNTDFa4k/33yO7EySRQWbOBnL9q03R7CVSjqLEU/FL71eLKE7X02ubAqJrOPtc+gJMJF162e6/ryvIK3IzsaeuKjMdhumy91hV7jXccJygMqNeXoOa3ltGmi2WIpgrjMi6h89HBZzMvaPPmzA1eqDVx4gguf+JDgT5PAAAgAElEQVQB6HwWMqIujw4qpsv57Wt3qjJJlFfbBNzV1mm13y0y7sJbbX9TonLuaQAG7tU2gHUO2u9TeLNnWPy8j8TReRi9jNVP3Inpn1sf6KZjZXkF7pisbTdZZcOpYeorUhFCvAPAWQB3AfhHAH/T4R/tI85EBl5ew8sW2/at3AnjcfvHP+8VUfKLEIar26G5dO0PwctOPGsXZ0K0u9zra9d//FnP28WZ0Haw7bjQUnxIb9rVzrCf8HYLX5jq1TaFlko+VHL3/l72yo2oGxYWTBp2Snl9pWZ/fR3SMRAD1mGRY2noSut1EKqctntb43OtqeFhBe6wQFjk+MlET5XAvbUcnExv32cRj8FoAeO16SVfyMFo0bXSvhyzN3L02taDIlsVvXEhRboSutg9nR4A/PO2MVG4gjuI1PPuAIzA5l/+dvRzrK8DwkBOzg/8HN2oiXH4hehrqfq7ZaL2Oku4DnSHAnje5VWoBKrXd9hKbCu945sZreEXDJypccy98x3wNoHNv/jNgcby1vNwMnHIBXtjQK/3XqWeuus54BZCfC+A3wcwD+AMgH8B8Hcd/tE+oiYnoMsC3malr0qUwzaeqK1wl3UJwuxsS5pRNpe0dzSVdwBzY/33NSXaL9xrbsXxP/gfOPD2VyDx4tfv9nRoyGQmAxgBk22ssG3yQWXtNjVGhj6P4IWp3+aFaS+pwaPAiWjnFPY5F4khr3DXVWr2s5uQHbaodaOC60CvRWcYVM6ehVAGsfnxlr3e1f3+Ux32cKcSPRUm87NlOJO93TQQCXs9mNx69FhB5fYwoG47t+BvfFg9eyt02W8JuIUrYbq0LwuFFcSdA4OvtKff+CNw0sDaX/9t9HNkc9teAFNN2de5UdW5w/3s9b9bRMztmK1gikVIt3Z9q8N2L3e3VmL90CsXYLSAmppG4vmvAAB4Fy8MNJafr0Cl45CpDIQy8Dc6dwCg/vSTG/zTsNt9fsgY875tmg+NqHBPpLdpe4/ulnCFu+gXUdFFSDDgDr3q5O34s/tfhV96xWD7d4j2k8Qdr0XijtZiULT3qaA1j1652PACuPqieLy/vaSDqr4wXY/eR6wrdq/tqJp/4/Nw6W++HNkXOgy4ZWq4KfHVSs1LZ+BvFqCSg7evlJkg6Fy+ADXdmhruXV6zKbLpFPxiY2Aabj9Qk+33cMtUCn4Phcm8nIYz3VtWRdhmzeSzQMSNoWq/5y6t7aoB9/rWgzdd9uHONL6Wko7qOeD2loL2bgePDzwH4cYw8aJn4PLH74e/fK6aPVKd42YOKr692werXQfOPwXneONWJJ1v7FUOBBXnvfY3ZGyXgtqcZSoD6Rp4K9Gt+Abhn7NZHGp2rtbqLxt9M6frWAUfajxYjU8I+NnN4UySAPSXUn4DgK8w2L4yOXO1NB5ncmfS9aKMB+ltJa+Eii5BCQbcoXQ8jg+96d246UB0j3Qiov1ABn2b/dWLDcd1oQDIwVOUB9HuhWk1NTg9ugH3zC/9McZvmoGptKbFhgGGSA03W8pZsEGBd/pR+LkSVGrwv+Fq0gZIuuk6CHmbeai0CzU+Bt20FVtv5gAYiIkOK9zplL05kG+/0qdXL0F7As5sbzd5whVu3W6FO0gRD28mtJ1bUIl/0OCqni5ryHjj90G4CsbrLeDWG3YOav7wluaRvuNlgBEo/Etr4V0/V9z2AoTOrH2d61043fIxnc9DKAPh1r5OIhaD7vAl0mUPItZ4Q0mlJPy19oX+vKcfR/GLLU2g2vLP27k6cwdqNwCz/a9MG63hFwE1bq87lZDQm+zDPUz9BNwFAE92PYv2pfrCImpmZ9L1okgpYbSDkl+CZ8pQXOEmIrqihHu09WpjFV1dsP2Ed5JKSPgRL0xrqcG7lxHWCxGPRaZN6/XhBFHNnAN2PO/skzaFdWzwlPtwP227onX+Zhkqk4DMZGC0qFaxB2wAJd3OKcrVVeQ24wOAd/phAIBz4GBPcxbBtjiTj149DFPEuxW9kuP2ptMwAm5Tad36IFzVcX9yPT+3aYPRLW4/SL7sjYAwyH/xM63PkS9Dpbf39V64Bz3s0d7w/NkcZNPTi0TnAni6WGlJ1XfSLrxs+0D23Pd/F55820+jdOenepqzdymoth+k88sYBgqU9dolwNRau8mkCz/fvWAg9a6fgPsrAK7fronQaFMLtb057pHB04aGQRgXJb8Iz5ThiNEvSENERMOjJu1NX91URVcXSg17JneCjCmYUmvecbiveNQDbpmIRabF+tkNQBiIIVd8d47YfazeudM2hXVs8GwENWlXlfVqdFp1OL6asEGEv1Tr8+znCw29p6NUC5NttE/b9s7Y1k/qYG83JmRQ9d0U2gTc60HA3aXwX1gteygr3BVAJhuL4wnX6Zgu3fD4zXxLMDoIOTmLxHwMhYda1/Z00YNKbW89BBVUQA/3pNfzltfgTjSl3cditpZEKbo1mN0b33iRqbEE/M3oYnR6bRm5p2ywvPTf/1NPc/bO25sDzqJ9Xa7iEn6ut+ry9fwLQeG7YPuoSsfh54fU6J0A9Bdw/zcAtwgh3rhdk6HRperSlFOv+r5dnAkAuCjrMnxThjOM3/JERLRnyCDg9jca90LafsI7G3CLuANdaq04rXtMDd5tIhGHjiiY7Wc3t6VIlXPsOgCAd+Ec/BKgxge/ISGDHtr+euueWJsia6AmM5CTwWrwci2Q0oViw/7ayPHD4DjXPkXXO2cDFefQiZ7mHK4C6zZj6mxQPX2i842OasC92T49uRemVITRAiLVGHBL14HpcYVb5wtQXb6WvYotTKCy1hrA+kUNuc0Fe9VB257OX27NaKisFuDONNYzCPuf61yboomV1lR9mYhBR2zhAIDNv7M7doUyqCz1lhZefPBBSNfAuebWYHwHutD/yrR/yd6MUjP2Z0qlk/ALvW0poN70k3xVBPBuAH8uhHglgI8AOA0g8soxxnxt69OjUaEOXlV9W05tX1uGXkgTR87bgEYZruQKNxHRlURO279BuinQ0qUyZGzwIlwDzSXuopJrXbGqrlRmdq/mSS9kIgHj2zZVwqm9JNSb+W0pUiVnD0FIg+KDDwNGwF0cvJVUtUjUWmulbrOxAuMLqMlJqKkgMF+uVW/WhTJkvPO1EqZ/twuOAcC7GFToPtJjwJ3sklKeDdtPdd66J4PPKSwUOCi9EdwYampDJlwXxu9thdsvlLp+LXvlzs8ge99Sw/VotLY3Z7pUbt8qJyj65jW1+TNao5LVGJtr/J5UK87ns0BE0T5d1pCJxteoMhGPrJkAAOWH7gcAjF0/jeLp3gqrFR8/j+ShdPVrpVIx+Pne2rnV84NWZWrWfh4qMwZdGqzaOUXrJ+C+E7ZKuQDw1uBfO6bPsWnEyVQG4zfNIPMtL9/tqeBo6lY8Wfw0oDRi8hndH0BERPuGCnonh8FJyJS8lj2T203GXJhyRNGxYPU93Gs7qurbVIm6IM/Pb0+RKiElnLRA7rFlAAKxG24deKywMrmfbV3l9c/btGRnehYqXAmv24utS637a1vmGhTfa5f+DQA6KFClZg/1NGeZCVbb261wb9rnCgPqtuOMB9sqclurJB1WOZfppoA7Fuu4P7lhjGIFMtklP79HzuIhGP0w/DOPVCuFm/Vlu794fHuzRUQiBeka+CuNK9b+uSdh/NabQw0V5yMYDy1742UyAd0mU7t8/gJU0sCZnoT/SPd2bzq7iuJSBTPfcrJu/DgqK/3v4fYvB5Xmg7R6OTEO7dkWacNuDXil6ue36ddgA2m6Qh364Od3ewoAgJ974Tvxjk//CwAgxhVuIqIrimwTaOmSBzW+s32vRSIemSJaDbgnd6ZF2aDCtGmdXWtYVd3OIlXOmIvCeRt1xG994cDjiMwUIAx0RJV472KQIjs7D7V4FQDAv3iu+nFd9ODOdN4/HrZEM4X2q8g6n4OQvRcMC4uh1RdwaxgvCMTlZOdMQhFPQCgDnd9aJelakbbGYFbEnMitBpFjFDy4c8NZfXYP27TuyhP3VQPuypMPAgDUQusq8rCppGjpP1157B4AgHPkqobjnQrgGa2hPUA0F6NLJaEr9uPN2zW8pTW4kzGoyQnoSvdgt3TXZwAjkLjlWbX5p5PwS5fbPqadsDe4WrDbR1XYcm/1UkOGKw2u54DbGHP7dk6EqFfPO3od4CcAVURc7eyLKyIi2l3VYKMp0NJlH258Z+t6yHZ7oIOCbmqut+rVu6W6T3mzcVVPFzy4M9tT8M2ZSAHn1yFdA3Vs8Fq8QkqoWHRatR9Wb549AOfYDQBq6d9AUNAq0fmGvQgC7rBFWhTdQ/G1etXq4pttVrhzOVusLtX9ay9duxd9K6oBd7p5f3Icprct3NAlHyo5nNdi7nF7PVSeegThrvLKozbgjZ24YSjP0YmTduE3VRH3nno4mNvJhuPVFm9RAXduHTACMtUYMNv3hc0oyTRmv1RWC4gfmYIK2x5ePA2nw8+HXg9+x8ws1MYfS0H3n1HeEnCH14Nev8yAe0i2t4s80TZRxt59Y8BNRHTliep/rSumaxA1bDKRiA64120Aq+aG21Zr2ESwd7d5xdUvaaht6iE+9uIX2eesiC0XZZOuiCwS5S/b3txq4Qjk2ARkzMBbrq386bKB7FL1WiR7WOEulCBjvRfqk0Hf73ap4GEA38vXRboCOr+1gNuEe8ab2pB1q8Bdzy8byHSy63m9cK+5BQBQOXOqeqzyRBDwXvfMoTxHJ2osAW+z8XqqnLOVwN1jjQF/uPocteWgWsOhaW+8DLYphKn8IeN5qGQ13IVZqBl7jYSFzNoJC+bVf+9UJgPjd+4dH2Xz6w8hPqeqheDC7grhDRnaOgbctCe5wv4hTDgMuImIrjQqpeBvNAZCumIgkzsccCeTgLbpnw1zWd8ApGlZxRo1YUBg8rX0fKM1dMkWTtoOEz/5bkx/80kcfMe3bnksGZORq7z+SrBiF/QndtIK3kpdH+5K6/7alrHTQdBRaJ+23Uu184Yxg+ripk2xMxtw9xbAy5iCLg6wnFn/fGFV9KZaAyJmf47qr4soRmv7tdxCe7d6cuEopGtQevTx6rHy02cgpIFz1Y1DeY5O1Hgafr5x87ofFFFrXumttXhrvT5Mtk3AXW011xjIemcehtEC7qHDUDN2O0GYpdFOWD1fZmoBd/h2fUX+bioPfhXF8xWM33Fb3TyDlPKN3oq3UXcDVcQQQjgAjgEYhy2i1oJVymk7xWQaRQBJBtxERFccZywOf7Mx0NJeaz/h7SaClFG9cRmqbr+ln92Eig2/rdawiTB1tK6Il8mtw2gBuYWWXR2fU0os/O6HhzKWjCvoqD7owQpyuBfaGY/DW7eBkSkVYXzRUiisZZ5pG3REBVTV5+mh+FrDmGOTANrvvdaFEmSP1eHt577FgDtcJc00rnDXWl5lO3amMRsrtqBZejg3Z4SUyNx8ANl7zkFnVyEzU6icX4I7Lhuq6G8XNTkOv3i+YY+1v2q3PzTvpw4zIHSx9eZJbW98489QLVW7MZD1HrcVyt0jx6uVwv3LFzvONbzGRV0nBDUZ9JxfPgvn6MnIxzXLf8r+LI69+k21eQZjcoV7ePr6SyCEOCyE+CsAGwAega1c/tWIf/825HkSNUiqcIWbRdOIiK40KpOCl6sFWqaQA7TY8YA73KMZrhSG/FweKjHawTYAyCCo1LnaSqa/bIuLqYnRbmkG2LZsuhgRcBeLAGp7oZ3JMXhZG5zq9SX72C5BYrjKZ0rt+xrrPivjC8eBdNA+4C5Vem6xJRMudLHHymZtVG9MjDf2/RZBLQRT7FwF3V+1QaHMDO/mzMR3vgm6IrD5wf8bAFBZznYtcDcszuSUbZNXl/Ltb2Shkq1ri7Uq9oWWj+mszaYQ6aaAO0j/Nk0rx9750/b5F49CLdhtKP7lpY5zDWsX1H/v3GtvAgCUvvHljo9teO4L54LH1joGhEF8+HnQ1vX810AIcQDAlwG8EbYn9yrs6vZ9AAqorXR/A8Ddw50mUaOUY/9QFr32fwiJiGh/UhMZ+IVa4xS9FgZRO/PCPFRNyc429QTPFaGSo98dNUybNnV7ivVSEHBPTkc+ZpTIhAtdbu1fZYolCFXLMHBmJuHljU2BDq+Vsc5BokgHQUexNaAK2YC7v5ZYwgV0Mfq1iy5WoHocT8ajP/d+VFdJJxqr6csOFbgbHr9q20nJ8eHdnEm+/LsBGJTu/wZ0PovS5Qrihxe6Pm4Ywv3TXtBWDgD8bB4q3fo96VTFPqyJ0Fz9vZrynWuqmRD0wXYWj0PN220Q/krnauM6eF6Zqf2cJl74bYA0KNzZR8B9eRlCGciZWoFHNRm0nWtT3I/618/t158FsAjg1wDMAPj/ABhjzK3GmDEAbwBwFsA5AM8b9kSJ6o259hfdeqnz/iIiItp/1NRktXUOAPhLdr+j3OFV2XAFq2WFO1+GTI1+BpZIBSvcdZW4w+rHo95DHLB9h3Upoi1bsdRQPdyZm7fFpJbPwl++AABQk50/v3B13LQJjgFAl3XXveAtc3ZFsAIfMV7Jg0j0GHAn49ARPeD70XaFOwy4O/QgBwC9Gty8mBjetSIzU3AzAuVTT6P4yQ/C+AKpF9wxtPE7UbPB/umzdQF3rgxnrPV7HK5wR92QCVeGZabx95EI28I1rRx7y0Ef7MWrbeArTLXwYjsmXwDQWCdCjk0gsRBD4eFT7R/YxFtZh5NsLGAoJsKAm6+xh6WfgPuVsMH0zxpjDJp6chtjPgTgFQBeDuCnhjbDPgghXiKEMF3+tb0ZIIR4rhDiQ0KIS0KIohDiUSHEu4UQE+0eQ7vjRUe+CQBw4+y1uzwTIiLaac6UDRDClSh/JQiipmbaPmY7VAtrNb0w9QseVHr0a4xUU1zrA+5qOuz2FE0bJplMQFdMy3FTKkGoWhqwMzsHAPDPPQk/KCilprv0upbStp/rUKl7kEJ9nYqd6ZKG6nE8mUzARHzu/WjXhqy6h7vD/nUAqJy2xc3CfcfDEpsfQ+nCGnKf+RggDFKv+t6hjt9O4nkvA2Cw+fFajQEv70GNtVbsr92QiQi4c+He+MaAO7yx0Vyl3l9ZhXQM5MSMbXcXB/z1zqvLulCAcFrrRCSvOYzi+SKM7u1mjL+2CZVpvMkjw4C7TXE/6l8/+U5HAXzSGBNuGNGALaAWHjPGPCiE+ByANwN4z1Bn2p+LAD7W5mORmyKEEN8D4E8AKABfgF2tfx6A/x3A64UQLzTGXNqGudIAfvi5r8ZzDl2P5xy+ZrenQkREO0zN2RRT//wpuMdvhA5XiLoEUcNWDbibUkR1yUS+SB81tohXYwAQ9hVubhU1imQqCd26hRu6XGmo9h2uwPorl+BfDq6VHnqkCwWYiKJsteexc+hrznEnct85EAbwvd2okckk/PZT64m/noWKtwZttZZXET3OL55C+d6vIPmy78LmJz8B6RokX/ztW5tIk/jhBeQ//xg273wAiflYNc16u7knb0PqWArrn/06ZoPCaX7BQE20bj+QYcAdscc/rEIvm7oUyIkg4G66QeetrUOlaterSkr4m52DXV0sQkZEcc7sDIz/JEw+W11Rj3Lue/4XGK3hZUtwZxtvroVp6p160FN/+gm4ywDqv/Lh2/OwK9+hZex+SvlDxpi39nqyEOIwgPfD7kN/nTHmw8FxB8CfAvhuAL8P4PXDnyoNisE2EdGVKQyW/Au2R64fprbO7Mxez1C4J9PU7XU0WsMvY9uqfA+TOnAMMmZQeuyx6rFqu6E9EXCnYbSAKeSqKb6ADZKFWwsiZbgnde0ydNgybO5Q9/EdwJSjU8pNMW+ruaf6qxsg4w78QpsV7gogeg240ynbkq7pc++Hn81BpVqLtMlqQbDWgOvpN78O+TNFXPell2DzvnMYu2Fu4OdvJ3biBMxnH0fxoof5N+5sSJG547m4+KefgXfqQajZRRhfQE21blWprXC3ZkBUU/UnGjNuaivcjV9Xfz0Pp26fuErF4Gfb1w4AAF0sR7aQq94EXLnY9mfYlIrYuPcijCcAaZC8pinDwY3Z7I5c5wwH6l0/KeXnYFe5Q2GTvG9qOu9mNAbme8FPAkgC+H/DYBsAgpX7H4Ctyv46IcQzdml+REREFHCC/sr+kk0P9lftvmM1u7ij8xBjdgWrYYV45YJtlTQ++gGrcBwkj2RQeOxC9Vi4qtWcDjuKwiJ5emO54biueJBuLZBUU0FK+foK/LWgr/JC91VT4YjItmP2OS83zKHnOcddmFJEoTfPswF8vNeAO2gxtRZdzXrjD34Rjzzr+up2iyj+ZgEq1bpnvLqHOyKdvnDOBoJLP/s2+EWB8de+rqf59mPsDd9ffXv8e3946ON34h47AcC26qo8eCcAQE23blUJA24dcUMm/BkSLQF3cOOnKVXf2yxBjdcyJVQ6Dj/fOX3BFEuRPeDleFCXoc11AQDFL33EBtsAoAWcmdYCiTJm09YHsfZr70LuH94/0GP3q34C7n8D8AwhRCx4/+OwK8LvFULcIYQ4LoR4D4BnANhrPbjD3xZ/1vwBY8wGgH9sOo+IiIh2iTpkM5y8izbg1us2pVvNH97ReYTVmXW+vsq3LeC2F9pqAUDyxmtRWvGrhefC1TexBwLuah/x1caA25R9yFgtiVNO2urTen0V/to6IE1LZe4o0pEw5TYBd4/VzlvGTEQXOzPBtgSR6HEPd5uA22iN5Z/5Ppx971/ALwjkPvj7bcfwc2WojgXBWlc4VTC9lc8+jsRBF2Pf+7/1NN9+uCduxom/eT8O/9zb4d7wnKGP3/G5j18HACjd+1U88e9+HADgzLXuURduDJAmMqVcFwp2b3yi8WaMiCcgpIFpagvn5z04E7W0bpVJwS90rkCvyx5ELCI7IayE3iHgLnzu4wCAidttppCabf1ZkK6ALvTXCSj34T/Ehe//Vpx/30dw+mf+J/L//Od9PX4/6yfg/icA4wBeDdj92rAB6nEAnwHwGGyxNA/Afx7qLPu3IIT4eSHE+4QQvy6EeJsQIrKSihBiHMCJ4N2vthkvPP6sYU+UiIiI+qMWj0Mog8o5u6PN39iwQdT4zrayCleB619Ah0W55A4XcBtU8rbnARAofeUTAAATrL7VtxsaVSoTrOZtrDQc1xUfoj7gDloe6Y11+NnofctRhCuhy9G9rvW6fc6+A+5kHNprLXZWLbSV7G3vf/i8zZ+798jdWPqH2rpX9hOfaDuGX/ChMq0r9CJseRVREKy+T/jkK1/S09dxELGbX4DMW961LWN34l57CwBg5W//CQAwcdsC0m/4wchzpQJMqXV7gM4XICMKmgGAdO3HQ8bz4BXQkLauMmPwi50L4umS13BTqfrYoF6BXl9t+RgAeE8+gOUPfRbxGYmF9/4xxq6fQPpb3tA6zw7F/do5+wv/E6ufr1V4L3zhk309fj/r+afEGPNXsGnXH647/DYA/xXAAwAuwAberzDG3DXEOQ7iegC/AOAdsOni7wdwWgjxYxHnXhX8vxasZkc5Hfx/fIhzJCIiogEIKeFmJCpLNtjws1moWG9B1DDJ8WDltK64kL8SFnCb29G5DEqF6fnBvMM0UpHeAynxQZ/jsJVZyFQ0ZKxuT+x0UGQvu2H7Kid6u06Eq2AqbQLuINAVTb2Wu46ZTEQWejOb4Qp3jynl4UrmRmNg5Z16pOH93GONq//V59MafhFwIgqCVYumRaSU16/Op1+9M9XDd5KcOwLhGJSWfbgTAgf/9FMtxc9CQtkCfc2a29I1jB8X8Ov2RuulpwEj4MzUVpnV5IRtY5eNDpoBu8Id1QM+3Cfur6+0fAwANv7sd+AXBBb/+y9DLRzDkb//MuK3vzRing50xM2ETtxJmwSdXIxBJQ2WPvgFnPu+l0KvXsLpVz8Hpa/+S1/j7Sd9/WUyxpSMMX7d+xVjzH81xtxsjDlkjPlmY8ynhz/Nnq0D+HUAdwA4ACAD4DYAfwggAeC3hBDvaHpMmMPRad95mCs2+hVQiIiIrgDuZBKVFVvgy9/sPYgaJpFMQygDP1srmuav2FROtcMF3Aalpmrp1kDQbkgZCKefurq7QwW9wpv7oOuKgagLRkQiZYtAZTfh5wpQyR57XcccmEp0aq934Wk7hz5vrMhUCsYXMJXGYMbk+1zhDrIrmlcyK0EP6eThOGZefgP8goC/fK7l8WZ9GUaLyK0PMhnd8spoDb9QW3mN3bjbNZKHz97Ms6v4E3fc0vEmnk27br0pYYolSDf6cSrtwt+oBdze2Sfs8bna74uwR7x/8TTaMWUdHXCH2yeaen1Xn+/iBUAaxF/w6rZjA2E1/eibTW1pID6ncOSvPor4fApGC6zfdR6bf/17yD22ieyHPtDfePtIz3+dhBAfEEK8d7smEvS7fmiAf9Uyk8aYu40xP2WM+bwx5qIxZjM4Fq50A8CvCiHqN8iEJf621MxQCPEDQog7hRB3Li213zdBREREW+fMTsBbt0GLzhUhk7sTIDpJAX+1liCnqwXcuredGgVyxu5P9bP2c+i0Ojdqwn3meqMx4DaegYzHGo6pOODn8nbfcrq3fdLCVdCV6H7GhS9/HhAGiee/qq85h1XN9XpTobegOrzoMeCufu6bjYGVd87eCDj8R3+NxK12J2T5vq+0PN6/cApAm4JgQaVrU268KaCXzsBogemXXosTf/vHPc1zL3KnbAGzibf8SMfzVNKBzkX04S6WISIKmgGAk0nCy9b2Rvvn7ffBWagVfFQzQZG/S2fbPreu6Mj9/tWK/O0C7uXLcFKi6w01mYhBRxT360QXPcQPTELNHWq4GbD6oX8AAJSeONXXePtJP7eDvxvAdjbCWwRw3QD/ev2z8LuwLcumATy37nh4W3qs5RE14cfadqE3xrzPGHO7Meb2ubm9kUZGRES0V7kLc/DytnWRn69ApWLdH7QNVNqFt1Ermuav2RVHucMV08l1x5kAACAASURBVAclp23ArTfsC3RTLEE6re2GRpFqE1xoDxDxxmBExiT8bA7lFa/nHunSdWG86IA7d99jSB6MV1cUe1WtrN6cBp8P2rH12GKr+rk393S+dAEQBmrxasSufyYAoPLIPS2P9y4GK/Qzra9ZRTIoyNaUUu6dsQ2KEjfesi9Xt0OZO56HiWcfROzWOzqep9Ix+LmIommlCmQ8OqBVE2Pw87WV4+r3oa5qfpgd4y+1ZiZUn6NiC/A1k8H2CZ2NDlkqK1m4491/V8pUIrK4Xyd+SUOm7c2K5I0nq8fzT9mbEoXHLl2xhdT6CbjP93l+X4wxbzbGiAH+PdXj+BrAo8G79c0Xw8dPBgXUohxpOpeIiIh2kXvoCACByhP3wi96UOlk18dsB5WJw69fscpuAMJATu2NlHKZykBIA71pd9bpcrmhh/Uok1PzAGqr84BNeza+gGzaCy0TDjYfWofxBZyZ6D25zUTcha5EFDjLrqJ4oYzUTSciHtVlzmGf5KY9ttUV7lSn9Z+6uU2ENxuaAu6lleoKZuym5wMAyo8/0vL4MM1czUZU4A5TypvSpb1zNl3dWejew3wvm/qPv4PFP/tU1/NUOhnZvkuX/bYBtzM1Aa9gr1MguEECwFmslYlSczY7xl9u39JNe4CM6NlerSuRi94p620U4Ux1v6nTS+G2ljmVATVmr9+ZX/gDnPjL38fYtbXduJVN4NRP/FLLdoorQb9Vyu8QQvRWzWE0hXkz1VvRQaG0sKd4u94DYa/xu7dpXkRERNQH96gNdiqP3w9vU8OZ3p02Vs7EGLxcbcVKbwQF3PbAHuiQjAF+8AJdFyuR/X1HUX318VC1vVZTMCKDFkrJgy5mfvH/6ml8EYvB+K1Bh798DjAC7qH+29C1qy5ugtZyMtlbwC3DgDvfGFh5q1m44zb5U07OwkkZlE+3pib7QaCnFlo/B+E4kI5pCdpK37BNe5yrr+9pjvudzKThF1tXgW3AHb2K7MzMAkZAL50BAPiX7dYCtXh19ZxwO4peiy6a5q9cAIyAzEQUvGvzvQt5m7qnG05qPGMLt+XbJvc20Jvrto98xl6/Ip5A7JkvxuR3tlZA988/1dOY+0k/v1F/HkAFwJ8KIea3aT7bRghxK4CTsHu172z6cFh5/fsiHjcO4DXBux/atgkSERFRz8IX/aW7vwLjC7iLu5PC7UxNwC+Y6oqVv5mDjO+NlOyQjMvqXlRTjm43NIpEKgPUrc4DtWrfMtGY8VBZtau109/zBqjp1lXdKGpyHH6ptVq3CYq09brful5YXdw07b3WhaD/ebrHgLu6ktnY07myUYQzWVvBjB/MoHCqtbZQdWX18DXR48dqFesB275q9SOfQ+Kgi/ht/2tPc9zv1ETGXh9eY3ExW9AsOuAOi6OFxdK8lTWouIGI124QyenWzI165Xu+AACInbgu8uMyBvj51r3l/soF6IqA28PW17Bwm754puu5AKAvB+0QM43JwmNv+gkk5h0ceOvLkLnJVlD3zjza8vj9rp+A+z8B+AqA7wDwhBDi40KIPxBC/FbEv9/cnul2JoT48ah+20KI5wP4YPDuXxljzjed8hsACgD+vRDitXWPcwD8Pmz/8b83xjywPTMnIiKifrgnbL/c/DfuAwA4R67alXmo6RkYLaovOP3NIlRibwSsIRVX0AWbFq/LXkMP61EmpISqW50HahXLRbIp4A4W6pIvfV3P47uLhwAj4D15f8PxsFBZWACtHzJot9a87zzsfy5SvbUZE44D0bSSaTwPlXUf7nztpXDq5utQXtHVdPCQv7wMSAO5cDR6njEJna9tlajc/yWU1wwmX8VgO6QmJu1q9erFhuPaM5DJ6MJ8aj4oUnjOFhDz17NQKdVwjpwOVrjbBdz324Tb+E3Ribn2e9daPd17woYxzmL3zAw5FbQXi6hwH8UPfv+pyemG4yKewPHP3Yupn/1tTP+HH7DzOP9UT2PuJ/38Rv1R1Cp5pwC8rMO5BsBPDDqpLfhFAO8VQjwI4AyAPIBrAdwCW438CwBautcbY84IId4O4E8A/L0Q4vMAzgF4HoBjAB6LehwRERHtDjkxAxU3yD+5AkDAPX6y62O2gzMXrEadfRxq7hB0vrRrBdwGJRMO/EJQ8b2s4Ua0GxpVMiYaKkW3a6+1+KOvx9o/fgzuNbf2PLZ77BoA/4zK4/fBvf7Zdc8RpH/3uN+6nghbmbWscNuAO0w574V00dCWynvsGzC+QOzqWnpy6kUvA/7+LhQ++bfIvOVdtXNX1+AkRdu2VzKm4BfrahMs24DKWYwO0K9EYYV3/9IZqLnavnZdad3SEHIO2K9fWCzN28jDGWv8fSHcmL2ZshmdFl5+7BFAGLg3RReusy29Wou5VffgH+wecKupoFL6cvMaZTQdtEOUE+3T1Z3D9rr0zz/d05j7ST8B949t2yyG55dhe3DfCOBFsDcGVgB8AsBfAPiT+j7i9YwxfyGEeALAfwTwQthK5mcAvAfALxtjouvrExER0a5wxh2UluyfdfeaW3ZlDmreprJ7509Bzj+J8koZqWt6D5pGgUzFUVm2QaSptE+HHUUq4cCvW80LA9nm4mMTP/ormPjRX+lrbPfqZwAAKqceaziuczaoD9tn9SMMSHRus+G4KdrPQYz1VtANCFYy6wKr0n1fBgDErq/9LCRe8npA/CqKd38VmbfUHuutbcJJtw8DZMKBLtYKgoVF3tTEdLuHXHHCHuz+xadt5AHAVMq2aF8yuoijOmSDTu+iDWS9jRKSR1tbs6k2aeEAUDpzFm5GQKairz+ZcKALrcXc/EtBobyF7k2n1GxQKf3ypa7nAoC/Ys/r1JdeHbkWQG07w5Wk54DbGPO72zmRYTDGvAc2QB708V8B0HuuEREREe0adzqN0tIGhDJQi/1XjB6GcNWmcupRLP/Ob8IvCcjY3lkhBgCVTKBUtIGq9gxEYu8E3M3BRVjte5DV52bhTZzKmacajpstPEd17/VmY8Ctiza4kuneUsqBIOAu1ALu8kN2e0X8lhfUzhmbgJMWqJxvTHv2s0WoTPs6yDIRQ2W1tsLqrwft7qb6a4O2n1WD0rpq4jprb0y0227gHLkOkAbeubPQm+uoZA0mjrTWn5BxCd0m4C5fXEdsrv2150ymkX98ueW4v2SvgfqK6O1UC7etto4TJbwhIyfbB9xych5CGXjLl9ues1+13cMthPgjIcTbdnIyRERERL1yZ+1qoJuRbVNjt1v8tpdASIPiPV9H4YwNoibe+D27MpdByXQKftnuGrT9ffdOQxqZikMXa0WrTLj6PMD+6paxJ2eh4gaVC017dKsFznoPjqtjBivEOt9mhTvY490LlXCrWwEAoPzEE5CugTrWWEXcnYyjstyYqOnlPDiT7YM2mYxBl2pJoboacHcvuHWlCIPScHUXqPVXl6nognrCceBmJMoXllC+90uAEYhd21r8TMYd6EJ0+yxd8OGMt7++48eOwtsE9Grj6rS3YuemDl7V/pMKn3/Opp37qytdzrT8dVs7Qc20L0gopISTFvBW1noacz/p9NfprbBp2UREREQjJ/Oqb0fqWBIH3rV7u95EMo3EQgzFR88ABph60VVIf8feKvsix1LQFcAU8x3TYUeRSiXg1weGG8EL/8nWNN1BOOMOKkuN7ZlM0IpLjvUeHIdEegIQpqECOACYUglCmr7ayanxFPxsLSgrnVtCbCbWcvPJnZ2oVmkHbA9ov2DgTLVvpSeTCehyrSVaWMBrr/SX3wlqPghKV2ortiZo9yY7VJuPTSdRWcqi/IBtmhR7xm2tYycbb6bU0xUDmWp/Uyx2vc1vL939uYbj/soqZMxAJLpX1w/3pIeBdDc6OE9G9HWv54zF4K1vdjxnP9objRaJiIiImqS/84dw7J+/hvR3/tCuziNxzWHkny5AVwSc6b23x1VlMoARKP7rPwAAYsev7vKI0SFTKehSLTD0g4C7U2prP5x0HDrfGPiEva9Fpv/e70JKSAcwTenCuliC6LM4vDM9AS9X6wNdXiogfrD1+nMPzKGSM9X2ZnrpDIwWULPt08NlKgldtw04bFGlphlwh6p94OuqiVer5HfY3+/OT6OyXkb5kQcBAPFbX9g6djIOXYwsOwW/go43xeI3fxMAoHz/XQ3HvfUsnFRvoZ9wY5Cugb/RWx9ufzMLCAM52blztBpPws+2FnRrVr73iy3t1vYyBtxEREREW5C89ZmAsb23VQ89bkeNs2iLKGU/+rcAgPizXtDp9JEiM2m7Oh+8ONcbwUrsdOcX/r0ScQe63Bj4hOnf/ey3rmerizcF3KUyZL8B99wstCegVy/BX7kALwfErmotiOUeOmzbmz1xLwCg8ug99vjBQy3nVueYTsP4ohakb25CqN5WR68UUX3gw/3caqb99ecuHoBfFCg8/DicNCCnWs+VqQR0Wbcc1/ksoAVkuv33IXbzCwBhUHrk4Ybj/kYeKt17fQaVEPCz0ZXSW+aV3YR00XVrjzM+Bi8ffSMhVHnoLjz1lrfh4jtf2/G8vYQBNxEREdEWxG6qtYxyFloLII262HW2OFj2yw8AwiB220t2d0J9UGMZAAJ6ze5X1ZtBwN1lpa1XMh6DrjQGPtUWXpnBshmk21jsDABMuQzhiL7GcRbsCqt36iGU7/kCACB27Q0t57nHbXXo8v02hbl0z7/Zc2+JbisF1FKi9bpt96RzBci9U0tvR1T7wNcF3N6FMwAA5+Cxto9zj9miZblH1xCfiw6cVboxcyOkg/3indrHiUQKbkagcmmp4bifK3cslNcyh6TT0HKvE53LQ8W7X79qchx+0W5raOf8T78Txgem3vmutufsNQy4iYiIiLYgfusd1bedg3uvT3Hs5ucDAMqrGvEp1bbd0CiS43aVOQxEdC4PSGNXH4cxfiIG0xxwF4uAMEB8sL3uIiahS41tm0ypAun097LcOWhXs72nn0D5/rsBAPGbntNyXvKF3wYVN7j4G7+LymPfQP7LXwSkQfyZd7ScGwoDOr1WC7hVnGFDMxkTDdXE/aWgPdZi+20Z4ffI+AKxw9E3hmQ6De0JmErTdobgBki3fu0q5cLPNgbLXt6HM957ZX2ZcuHnuqd/A4CfK0ImVNfz1PQMYAT08tnIj5tSEfmnsph47nHEb39pz3Mddd2SV75TCPGSAcY1xpjd6c9BREREtIPqU0LVoe4td0aNmjsE6RroikDi+HBWhneKCvtar9pK4jqXg+ohtbVXIh5v2MsMAKZQhHQGfw4Zd6CLTYFUxYNw+wy4g5Z03rlTKD32MCAM3JtaV63Vwasw//bX4fzvfRiPvfpNAIDYlIRItq90rTLBjYw1WxDML5Qg490DqiuNjKuGbAXv8jIgDNSB9ivc8ee8vPp27OrowFxmajc8wgJmQF37rUzn7QxqLA5/o65QnufBLwJqqo8q+OkkSuur3U8EoAtlqET3dojObNC7/NyTUPOt2x9Kd30KxhdIPvNZPc9zL+gWcI8F//rVmgNBREREtM85R07u9hQGois2HXTi9d+1yzPpT9hmy1+xK39+vggZ6y81u+P4yQR0U+0mXS5DbCH2lHEH/mZjwG3KPoTb36DOUdtOyrtwDuXT5+COy7bZCenXvAX4vQ/Xns/v/FJdZmxgFra50oUyZHJv9ZffCSrhNrTv8lfWoBLoWG1exGtp3fHrb448Jwyo9eULbQLuzgX7nEwK5Qu1auClL30UMALxiBZk7aixFPxibz2z/UIF7kz3kFEFVcy986cRe2brx4tf+iQAIPGCV/Q8z72gW8D9MQD/YycmQkRERLRXJQ+6KJyvQGamdnsqA8ncOI3s/StIffvbd3sqfVGTttJ2uBKrC8WhrsTKZBIwAqaQq64Im2IZ0h08qJeJGCqrzUXTvL721wKAWjwOSAPv0kWUL6wjPt8+4HGP3wh3DKhsAvFpifmf+uHOcxwPMgeCFU5d8hAb3zvt4naKTMZQWa3bw72ehZPuXv0uPiNRuqwRi8hIAAA1YQNqf+Ui6m9z6I2gH/p454BbjWfgFWv943Of/EcAQOqV3911btUxMmPwS3a/dbdsDl30oTq0KquOeSBoN7Z0LvLjhW98AzJmEOuw3WEv6nZFXDDGfHZHZkJERES0Rx390KfgXzq929MY2KE/+wRMYRPC3VuVseSUDbj9+pXYRJ/lvjsQSVvUSmdXoIKAW5fLfad/15OJBHSpMVVXl324yf6+9kJKxMYlSk9fQHnNQ/qWzj2Qk1fPonLfEq76p89BTnTuU17NHAjaXPkl3bH385VKphLQF2ptwfyNApyxeNfHHXn/B5D9uz+Cc80t0eNO2e+Pvnyx4XjYdkyOdy7Yp6YmYTwBnV2FzEwh/7V7EJsQcK+5tevcqmNMTABawGysQEy2byEHAH7ZdKycHnIWbI0Lf+li5McLT1xA8vDY0LaEjIrh/UYiIiIiukLJyVnILi9KR5lIpPZky6ew/ZfeWLf/Fz2o8eEFhjIVBNwbK9U9p6bs9V3grJ7KpOE3VaDWZQ2Z7H/esbkx5B5bswW4TlzT8dy5n/sVjN/7b12DbQDVc3Q2+LqWTPVrQTUqlWioJu7lKkjOd+/P7l7/bEz/n89u+/Gw37m/2lhpPOz5LSc7fw/VtP24f/4UZGYKpfMbSF7d3+8nORmssl96uuPvNuN50GW7It5NWEzOu7zU8jG9tozSZQ9jz9l7dTC62V+3D4iIiIjoiqFmbGusMBDRJR8q2X2FsVcyHRSv2lirHtOlCkRs8LR1NT4O49k09eqYFUCl+k/Zjh0+AOPZ9Pb49dGrpdVzb70DmTf/dE/jyklb3EpvZuGvXICuCDgLe6/H/HaT6TT8Sq3NlZ83cCYH689eT83a69pfbdxDrTez9nknOn8v1GwQsF86A6M1vJyBM9tfGzsVrLL7S9EVxatzWrsEQFQLvXUiJ2YglIG/utbyseIXPgIYgeRtz+1rnnsBA24iIiIi2pPExCwgDPysDUT8soYcIHBtO34q2LedW68e0xUfMjZ4kmht5dD2bDZaQ1cw0Apy7HhtNTBxx2sGnlMzOVULuCsPf90+19H9t/K4VTIzZtOu81nofBbaE1CTvVcCbycslKbXmrYehAH3dOduArWA+yz08lkYLaoVwnueQ/Ac/uULHc/Ty+ft+RPdV/YBwEkJeJdbq5+X7rsLAJB47v5pBxZiwE1EREREe5KQEtIF9KZdLdZlQKaHF3BXV7g3awG3qegtBdy1lUNbOMqsLwMQkGPt23S1E7vmBjtmwvSUKt4rkZ4AhIHO5VB5/H4AgHv19UMbf7+o9iu/fB56xQamYYX3LY07uwgA8NfXG47rfAGQpm01+pCzcNg+fukCvFMP22MHFvuaQxi065XW9O96/ordjy17DLjd6SQqS+stx/1VW4FdLe6/ztJtA25jjDTGvG0nJ0NERERE1A8VF9C5PEwxD+MLyHT/gWs71fZY2foVbg0RH7xFlgoLvQUBt79mAxqZ7r8Tb+LFr0V8TuHwL/0fA88nSvVGRq6AylOPAwDcNgW+rmRqPLg+Vi9BB/ute0mt7ka4MUjXwN/INhzX+TxkD/d61CG7V7ry9Gl4Z+z3z1k82tccZJjWvrLc8bzw81Y91rBw56dQXiu3HPc3NiCUgRzb+g2LUcOiaURERES0Z8m4gp8vVVfa1NjWA57q2MEKt8nbnsY6uwpvU8OZHrz9W9iL2F+5ZMdctQGNHGDeanYRV//rfQPPpRPpCuhCAZWzT0MoA3WMK9zNan3gL0HEbO2AYaxwA4BKCPibuYZjusc+887haxGbFMh97Z7qyrZzpL+V47BIYLjy3E61N/hEbz8TscUD8L96Dnr9ckNWhp/NQQ2v/MJIYUo5EREREe1ZMuFAF0rwzz0JAFBzC0MbW4wF/ahzNuDOf+RPYHyB9EtePvCYYcAdBtp6Iwi4hxSoDYuMS+hCCZVLy3Azct+1ahqGMFtBryzVAs/x4XwfZUJB5xr7tfubeahEbwX70rccR/6pTZRPPQEAcI6c7O/5pw8E9RE2Op6nN4PK6eO9BdzusWD1/eGvNY2Th+zxc9tr+JNDRERERHuWSsbgFyrwz58CADjz/e1V7USO232pOmdTe3Of/jiEMkh965sHH3PWFsQKVw71ui0gJTO97YHdKTKuoItlVJazcKfZEiyKmg++l5cvVgNulemvGnjbsVMx+LlSwzE/V4Ia661fe+aVr4XxBZb/4W4AgAwq+vdKSAkVA3RTWnuz8GZUt97gIfeErTtQfvTehuN+rgiVHHyrxihjwE1EREREe5ZMJaBLPryLTwMA1MH+9qp2HDsIgk3BrjSWzlxAfDYGmdlCSnlQgdpft62RwpZjvabk7hQVd6GLFVTWK3DnR2tuo0It2LRr7/JSdZ+/nOqv33XbsdMJ+AWv4Zifr0CN9VYUMPW6d2D2tc8CAMRnBstQkAkJfzPf8Zww4BYTPe7hPnkrAMA7/UTDcb9QgUr1djNhr+EebiIiIiLas1Q6CV0y8C7ZKtHO4vDaV8nxIGU4H1RBL5ShUltbhRPxhC2ItR70Dg8DtR4Dlp0iEy7Kl/PwiwLuYn+ro1cKtWBv7virK7U93JPDqRavxpLQpcb9035BQ2V6K64npMTcu/8ckz94b/eT280h4cBvSmtv1u8Kd/Vrtt7Yi9sv+Egc3p+ZFAy4iYiIiGjPkmNp+GXAX7Z7odXi1UMbWyTTtj1WsMLtF3040/1XE2+m4qLWyiwMuIcUqA2LTCZQCebmHr1qdyczokQiZW+erK1Xq8zLyf76XbcjM2Pwi7ZPu5ASplKGXwKcPvt8uyduHngOKh2Dn2+tKF5PFwqAMBBdWpWFZCoDIQ305mbjOCUDmRleh4FRwpRyIiIiItqz1PQMYATKT5+DihuIeGK448cBfy1YjS5ryOTWx1cpB17WpuqGgcewArVhkana5xk7fsMuzmS0qYSAv7FZW+mdGM730V04AKNFtRigv3QWgICa2rn0fpVKQDeltTfT+QKkg75S1mUMDRXYTakIXRFQ48PrMDBKGHATERER0Z7lLNh05+LTK1Cp4Vc5js8lUXra9hrWJQOV3nraqxqLVwtihenqcnJ+y+MOk0zVPk/nJHtwt6NSDvzNPPRmDkIN74aPe5Vt41V5+C4AgH/htH2+6Z3LhJBjSfhF3fEcUyxC9rnLQsVlQwV2ezMBUBOjVThwWBhwExEREdGe5SzaPaHlFQ2nxwrO/YgfO4jSpZJdhfME5NjW015VJgk/VwEA6FwewjEQzmjt9JR1NxacI9ft4kxGmxqLo3Qxh+LjZyCHePm5J24EAFQefxAA4F88Y58vaCu3E1QmA79k09rb0YUSZKy/kFLGFfx8rQK7Xg4C7sn9WZyPATcRERER7VnOodqebTU+/KJLiRtugPYEil/6JwCAzIxveUw1noFfMAAAb3UdTlJsecxhMyW7dzd9dXrkbgaMEjWWgrcJ5E8X+w48O3GvsxXGK6eClPJlWxRQze1gwD0+DhgBs77c9hxdLEO4fQbcSRe6UNsbXvzqZ+zzLRwaaJ6jjgE3EREREe1ZztFrq2+7C8NPt40/87kAgMLnPgYAUOP9Fa2KoqYmoSsCppCDt5KFMxHf8pjDln7pq6ASBgd+9Td3eyojTTi1bQx+oXP6dT/U7CJU3KB87pwd+/Ile/zA8NredSMnbYq3d/7JtufoUgUy3t8NGZWMQRft3nCjNZb+6C8RmxJIf/v3Dz7ZEcaAm4iIiIj2LDlbWxVL3HTr0MeP3fJCAEDxwYft8w0h4HambAsl78JTqKwV4c6MXrGo1Gv+A05+/aHq50/RvNVs9W1dHm6mgjvhonLJtgbzli4CANTBq4b6HJ2oKXsD6/HveGt1n3UzXfIh4/1t4pbpJPySvTnhn3kE5VWDqVfdMfSCh6OCATcRERER7Vn11ZETt7946OOruUOQMYPiGZtWKyd76zfcccxZWyDNP/sEKjkDd260enBT7+b/83/D1IuH14qunjs3jvKSLapXeuxJOGlATe9cSrnM1IqYVR75euQ5uuxDJvoNuFPQZbulovLoPQAA9/i1nR6ypzHgJiIiIqJ9IXbrHdsyrjvhoLTsAwDUxNbT1tWcraxeuvergBZwDhzc8pi0OxLPfyUOvO8jmH/Dc7H4k28c6tjxqw6jkjXQ2VWUzlxGYnFnMyHiz6r9PIVF25rpioZM9LclQo2N2S0VlTIqTz4EAHCv3r+t5xhwExEREdGelr46DZUcfg/uUGxmrPq2nNp6+y61cAQAULo/WN07cmzLY9Lumvnl/wcT7/zFoY4ZP3kDYARKX/wYSqs+4tfs7HXinnwmrv7AbwEAvEvnIs8xFdN3b3qZsTcOln7qTaicfrL6XPsVA24iIiIi2tOOfvROXHvXA9s2vrtQS/mWU3NbHs8JCl8VH7erhs6xk1sek/af2M3fBADY+NCfA0ZsS42CbtTiVQAAf3kp8uO6AshEfwF3WHjw8iceROGBhyFjBmpuf1YoBxhwExEREdE+UL+Xe9jcI0eqb6uZrad/28JXBoWzdn+ue80tWx6T9p/YM+8AhEH2a48BAOI3P3fH56AWjgEw8C9fbvmYKeZhtIBM9dmOz63t+c4/sQJ3fH+3nWPATURERETUQeLZtlK3ihuI8a0XTROJFNwxAV0WdnVv8fiWx6T9R6YyiI1LVDbs++51t+34HIQbg0oA3upqy8f0hg3CZTrd15ixE7X92n5BwJ3p7/F7DQNuIiIiIqIOUq96M05+8dO45nNfGNpKemzeBhmxqdi2rs7T3hY7MA4AUEkDOYSCfYNQKQV/fbPluF6zAbfoc4U79W3/Hif++g+r78eP7d90cmCfBdxCiKeEEKaHf/+l6XEv6eExz9utz4uIiIiIdpeaPjDUgCe2aIuvxRa23teb9q/4sUUAQGyqv0rgXrxPFgAAGUdJREFUw+SkY/CyhZbjetOuesux8b7HdG96fvXt+DNuGnxye8B+S5j/IIB2jQynAbwmePvTbc65COBjbT4WXSmAiIiIiKhPsauPA59/ErFDbAlG7cWvvQ74+INw5/oPaodFjSdROrfWclxvrAAYLOCuz+pIPPvFg09uD9hXAbcx5l3tPiaE+BnYgPsRY8y/tjntIWPMW7djbkREREREofjJmwB8Cu7xq3d7KjTCYjffDuDv4R5c2LU5OFMTyD2yAqN1Q6CsN2wQLtNb6w8eu+VFW3r8qNtXKeVdvC34/492dRZEREREdMVLfuubMfPKG5H5nh/b7anQCIvf/jIkD8Ux9s3ftmtziF11HLoi4D15f8Nxs2mrucnxqYHGPfjO12D6pddCxPtrK7bX7KsV7naEEC8EcB0AD8AHdnk6RERERHSFk6kM5n/jg7s9DRpxcmwCV33y67s6h/hNzwLwaZTu+izcEzdXj+sw4M4MVodg8iffPYzpjbwrIuBGbXX7o8aY8x3OWxBC/DyAQwByAO4F8GFjTGvjOSIiIiIion0ufvtLAPwaSg98A2N1x/VmFgAgh9Aqbz/b9wG3ECIN4LuCd9/f5fTrAfxC07HfFkL8rDHmt4c9NyIiIiIiolHmHL4WKmFQeuzxhuM6nwMAiIl2NasJuDL2cH8XgDEAFwB8tM056wB+HcAdAA4AyAC4DcAfAkgA+C0hxDu2f6pERERERESjJT6XRPnCSsMxnbO9ubnC3dnIrHALId4N4LUDPPSbjTFnO3z87cH/HzDGeFEnGGPuBnB30+G7AbxDCHEPgN8C8KtCiA8YY0pRYwghfgDADwDA0aNH+5k/ERERERHRyHKmMyg80dglWRcKgDAQqa1VKd/vRibgBrAIW9isX267DwghTgJ4YfDuoNXJfxfAf4Ht7/1cAJ+LOskY8z4A7wOA22+/3Qz4XERERERERCPFnZvBxr2XYDwPwrEhpM4XIJ3GntrUamS+OsaYNxtjxAD/nuowbFgs7fPGmIcHnJcG8Gjw7qFBxiAiIiIiItqrnMVFQAv4Zx6pHtOFImTbpU8KjUzAPWxCCAXg3wXvdiuW1s1M8P/mFschIiIiIiLaU9xDdsts5ckHqsdMsQQZ27fh5NDs56/QtwI4CCAL4G8GHUQIcSuAkwAMgDuHMzUiIiIiIqK9wTl2EgBQOfVo9ZguliFjaremtGfs54A7TCf/S2NMrtOJQogfF0LMRBx/PoAPBu/+VZce3kRERERERPuOe/WNAADv7OnqMV2qQDDg7mqUiqYNjRBiHsC3Be/2kk7+iwDeK4R4EMAZAHkA1wK4BYAA8AUAP7gNUyUiIiIiIhppavFqCGngXaitP+qSDzUW38VZ7Q37MuAG8BbY6uUPGGO+0sP5vwzbg/tGAC8CkAKwAuATAP4CwJ8YY/xtmisREREREdHIEo4DGQf8jVpJK1324SZiuzirvWFfBtzGmPcCeG8f578HwHu2b0ZERERERER7l4pL+PlC9X1d1pAMuLvaz3u4iYiIiIiIaAhk0oHOl6rv+0UDlRnbxRntDQy4iYiIiIiIqCOVjMHPlwEAem0ZxhdQM9O7PKvRx4CbiIiIiIiIOlKpBHTRAwB45x4HADgzc7s5pT2BATcRERERERF1JNNJ+CUNAPDPnQIAqPmDuzmlPYEBNxEREREREXWkMmnoYAu3d/FpAIBz4MguzmhvYMBNREREREREHclMBkYL6M11+JdsP2518Oguz2r0MeAmIiIiIiKijtT4BABAL52Ft3wJAOAcumY3p7QnMOAmIiIiIiKijuTEFADAv3wB/soqhDKQk7O7PKvRx4CbiIiIiIiIOlKTtgWYXr0Ef20dTlLs8oz2BgbcRERERERE1JGcsi3A/JUleOs5qLS7yzPaGxhwExERERERUUdqZgEA4C9fhL9ZgsrEd3lGewMDbiIiIiIiIuoodvMLIF2D/L99BV7OgzMxtttT2hOc3Z4AERERERERjTaRTCN9chqb956BVwScqYndntKewBVuIiIiIiIi6mrsRS+ElxeAFlBT07s9nT2BATcRERERERF1FX/WC6pvq7n5XZzJ3sGAm4iIiIiIiLqK3fL86tvO/OIuzmTvYMBNREREREREXanpA7W3DxzaxZnsHQy4iYiIiIiIqC/O4vHdnsKewICbiIiIiIiI+qIWT+z2FPYEBtxERERERETUk6Pvfhem7jgOOca2YL1gH24iIiIiIiLqSfq1b0f6tW/f7WnsGVzhJiIiIiIiItoGDLiJiIiIiIiItgEDbiIiIiIiIqJtwICbiIiIiIiIaBsw4CYiIiIiIiLaBgy4iYiIiIiIiLYBA24iIiIiIiKibcCAm4iIiIiIiGgbMOAmIiIiIiIi2gYMuImIiIiIiIi2AQNuIiIiIiIiom3AgJuIiIiIiIhoGzDgJiIiIiIiItoGDLiJiIiIiIiItgEDbiIiIiIiIqJtwICbiIiIiIiIaBsw4CYiIiIiIiLaBgy4iYiIiIiIiLaBMMbs9hz2HSHEEoBTuz2PDmYBLO/2JIjAa5FGA69DGhW8FmkU8DqkUTHK1+IxY8xcLycy4L4CCSHuNMbcvtvzIOK1SKOA1yGNCl6LNAp4HdKo2C/XIlPKiYiIiIiIiLYBA24iIiIiIiKibcCA+8r0vt2eAFGA1yKNAl6HNCp4LdIo4HVIo2JfXIvcw01ERERERES0DbjCTURERERERLQNGHBfQYQQ3yuE+FchxLoQYlMIcacQ4keEELwOqCdCCFcI8c1CiPcKIb4shDgvhCgLIc4KIT4ohHhJl8cPdA0KIV4phPi4EGJFCJEXQtz3/7d379F3jXcex9+fSCRCIm5xaQzithhmQkRc6k7rnplpqoKS1css1EJDtGuZsTCmJagqipmEuBejccswxiWNoCJqtYbqJCTqEoKISyKSxnf+eJ4ztuOc3+/8Ts4l+eXzWutZO2c/z7P3Puf3zd7ne/bez5Z0tqTeDX2DtlKT9BNJkcuZHbRzHFrDSVpD0lmSnpG0IMfIbEl3StqzQvseOe5m5Dj8IMflqBrW5eO5fYmkQZKukPQnSZ9IWixppqRrJA3uoJ/3idYlkraVdJqkmyW9JOmzfOwdWUPflsabpOGSJkmaV/g/MU7S2l1933WLCJdVoABXAQF8AtwPTAI+zPN+DazW7m10WfELcGCOmQDm5li6HXi+MP/8Kn3rikHgrNzmL8DDwJ3AvDzvKaBvuz8Xl/YXYFiOkc9ybJxZpZ3j0KXhBdgCmJnj4W3gHuAOYDqwBPinsvar5TYBfJBjbzKwOM/7RQfr8vHcpVJc7AS8n+PgNeDuXF7P8z4C9qjQz/tEl3ri7eeF733FMrKTfi2NN2BU7hPANNJ31lfz65nAwJZ8Xu3+g7m04I8M3+DzBGnrwvwNgRdz3Wnt3k6XFb8A+wP/AexVoe5bhZ3afmV1dcUgsAspgVoIDC/MXwv4Te53Wbs/F5f2FqA38ALwRj54V0y4HYcuzSjAmsCsHAfnA73K6tcDtimbd0Zu/wKwYWH+1sBbuW5EhXX5eO5SsQBP5r//vxVjEOgFTMh1vy/r432iS73x9j1gHHAUsCUwhU4S7lbHGzAIWAQsK+5PgZ7Ar3K/SS35vNr9B3NpwR8ZZuSgOr5C3T6F4O/R7m11WbkLMD7H04Sy+XXFICm5D+CcCv0G553op8CAdr93l/YV4KIcJ0cAE6mecDsOXRpegJ/m+Lihxvarkc6CB7B3hfoTct30CnU+nrt8qQB9+PwM40YV6jcp1PctzPc+0aUhhdoS7pbGG3BJ7nddhX79SVcXBbB9sz8f3+vTzUkaBAwlXdJ2Z3l9RPyGdFZoI2C31m6ddUPP5emg0ox6Y1DS6sAh+eUtFfq9QrqMaHXg0MZsvq1sJA0nnS28NSLu66Cd49AaLsfH9/PLC2vstjswEHg9IqZWqL8TWAoMk/SVwrp8PLdqlpGuMANQhfrI04WkS3m9T7SWalO8/V0H/T4E7itr1zROuLu/nfL0hYj4pEqbZ8ramtVr6zydW5hXbwxuC/QF5kfEy13oZ6sISX2AG4D5wGmdNHccWjMMJV0y/lpE/FHSHnnwvmslnSdp9wp9SnHyTIU6ImIR6VJzgCEV+vl4bl8QEUuBR/LL8yT1KtXlf1+QX06IfHoP7xOttVoab5L6ky51L9bXsr6m6NnsFVjbbZGnr3bQ5s9lbc26TNJGwOj88q5CVb0xuEVZXa39bNXxr6SD8dER8W4nbR2H1gw75ulMSRNJl4MXnSPpLuDbhS+ZtcbiECrHoo/nVsnJwIOkKy4OkTQjzx8GrANcDowttPc+0Vqp1fG2eZ4uyGeza+3XFE64u7+18nRhB20+ztN+Td4W66Yk9QRuBtYGHim7tLfeGHTsWlWS9gBOB+6OiNtr6OI4tGZYN0/3Jt2bfQlwDfBenvdL0kBBHwLfyW0di9ZwEfFK3i/eSLoEd1ChegYwNZ8JL3EcWiu1Ot5WqDj1JeXdX+lenuiwldnyuQY4gPQokuPK6uqNQceuVSRpDeB6UhJzcq3d8tRxaI1U+h7Vk3S57tiIeDkiFkTEvaR7AwM4ofAcZMeiNVxOtv8H2AoYAawPbECKwXWAuySdU+ySp45Da4VWx9sKFadOuLu/j/J0rQ7alOo+6qCNWUWSLge+S3qUzQER8VZZk3pj0LFr1fwE2AYYExFzO2ucOQ6tGYp/838vr4yIGcCzpO9b+5b1cSxaQ0gaQHrmdj/g4Ii4NyLei4h3I+Ie4GDSYGn/LKk01orj0Fqp1fG2QsWpE+7ub06ebtZBm03L2prVRNKlwKnAO6Rke2aFZnPytKsxWPr3X3Wxn3V/f096JucJkqYUC+mLJcBJed74/HpOnjoOrZHmFP49u0qb0vyNyvrUG4s+nlu5w0hns3+bR23+goiYBTxNuhJj3zx7Tp56n2itMCdPWxVvpX8PyAOo1dqvKZxwd3+lxzT9db4Ms5JhZW3NOiVpHDCGdK/iQRHxYpWm9cbgS6Rf5NeVtOWXuwCwa4V+tmroQXpuZ3nZMNcPzq93ya8dh9YMvyv8e70qbdbP09L9gqU+wyq0RVJfYIf8shhTPp5bNaVk5IMO2izI09K4A94nWiu1NN7yQGmlUc0r7msr9WsWJ9zdXES8Rjq4rw58s7xe0j6kgTXeIj3HzqxTki4kjXb6PinZ/n21tvXGYEQsAR7IL4+t0G8w6Xm2S4DJ9b4XW/lExOYRoUqF9JgwgLF53pDcx3FoDRcRb5DOHEIax+ILJK0D7JxflkaNfgqYBwyStHeFxX4T6AU8k5dfWpeP51bNm3k6tPhIsJI8b2h+ORu8T7TWalO83dNBv/7AEfnlpC68lfpEhEs3L8BI0qABc4GtCvMHkp71GcBp7d5Ol5WjAP+SY+Z9YGiNfeqKQdKvkp+RRpnctTB/LWBK7ndZuz8TlxWnABNzXJxZoc5x6NLwQvrSFsDbwJDC/D7Ar3LdDECFujPz/BeAgYX5W+f4DGBEhXX5eO7ypZL//gvz3/9KoHehrjdwda6bD6xdqPM+0aUhpfB3H9lBm5bGG+mS8UXAMuDIwvyewG2536RWfD7KK7ZuTtIvgZOAxcDDwFLSr/H9SQNtjIyIZe3bQlsZSDqSz38xnEHaQVbyUkRcWNa3rhiUdBZwEWmH+Sjpsrh9SDvop4H9I2LR8r0z6y4Kz0IeGxGXVKh3HFrDSbqYlEQvIcXDe6TLFTcB3gD2i8IYF5JWI51VOYI02v4jpLPaB5IS9Ssi4tQq6/Lx3L5E0gnABNLj6d4kDdYn0pntjYFPgaMj4u6yft4nWpdJ2pn02MOS7UmD9s0k/bADQETsVtavpfEmaRRwE+mq7mmk/xu7ke4lnwXsGRHzuvwBdFW7fxFxaV0BjgGeIB3cF5J2xj8AerR721xWjgKMJv0i2FmZUqV/XTFIGgjrv0ln1T8hJfpnU/gV38UlouMz3IU2jkOXhhfSYH6P5vj4lPTF81JggyrtewCn5PhbmONxGnBMDevy8dylUlzsTHoO92xSQrOYdB/reGD7Dvp5n+jSpUIafK/T74NV+rY03oDhpGT+nbxvngWMo3C1R7OLz3CbmZmZmZmZNYEHTTMzMzMzMzNrAifcZmZmZmZmZk3ghNvMzMzMzMysCZxwm5mZmZmZmTWBE24zMzMzMzOzJnDCbWZmZmZmZtYETrjNzMzMzMzMmsAJt5mZWYtIOlTSTZJmSfpY0mJJr0uaLOlESf3K2p8rKSSd26btnZLXv2+L1rdvXt+UBiwrJEUDNsvMzKxuTrjNzMyaTNLAnEROBo4DlgAPAXcDc4ADgauBVyRt1qbNbDpJc3IivHm7t8XMzKwVerZ7A8zMzLozSQOAJ4CtgKeAEyPiD2Vt+gEnAWcD6wCvtno7VxDTge2ARe3eEDMzs0Zwwm1mZtZcV5KS7enA/hGxuLxBRHwEjJP0a2Bhi7dvhRERi4CX2r0dZmZmjeJLys3MzJpE0pbAqPzyxErJdlFEzIqIuV1Y/mGSHpD0rqQlkl6TdIOk7Tro00vSP0p6TNJ8SZ9K+rOk+yUd24V1ny5pmaS5knbupO3ofD916XL52aV7rIuXmHd2D7ek9SSdL+k5SR9KWihppqSJkvaocbtXl3RrXs+TktYv1H0t308/T9LS/Pm8JOm6zt6jmZlZJT7DbWZm1jyHk37cfj4inmvkgiX9FPgx8BkwDXgD+BvgeOAoSSMjYnJZn3VI95HvDnxKutR9HrAJsCewA3BLJ+vtAVwC/JB0NvqQiJjTyebOAm4ARgJrAncBHxfqP67UqWy9O+Vt3xiYD0wBFpOS+NKPGk92sowBpPvm9wEmAcdGxCe5bjRwPenzfJp0Wf9awKbAaOB/gd91tp1mZmZFTrjNzMyaZ2iePtPIhUo6lJRsLwQOjYiphbqxwDjgFknbRMS8QteJpGT7KWBkRLxZ6NcH2K+T9fYBbga+ATwOjIiI9zvb3oiYBkzLo52vCZxZQ5JeXG8/4F5Ssn0NMKaUKOf6DYBtO1nGZsB/AtsDVwCnR8RnhSbn5OleEfFkWd9BQP9at9fMzKzEl5SbmZk1zwZ5Oq/DVl13Rp5eXky2ASLiYtIZ2rWB75fmSxoCHEk6mzyimGznfosj4oFqK5S0HvAIKdm+EziolmS7Qb4LDAJ+C5xcTLYBIuKdnNRXlM+OP0UakG1sRJxalmwDbAgsKE+28/Jfj4gXl/dNmJnZqscJt5mZ2UpEUk/S5d+QzlhXcn2e7luYd3Ce3hMR73RxtYNJl2vvAfwM+FZEfNrFZSyP0rZPiIguPVtb0sHAVGBd4OiIuKRK0+nAAEk3StpJkurfXDMzs8QJt5mZWfOUEtuBDVzmekBv0r3G1R4f9nKefqUwrzRgWT2jgF8LbANcHRFndDXpbYDl2fb7SPdiHx8Rd3TQ7mRgNvBt0r3a70t6SNJYSRvVsV4zMzMn3GZmZk30bJ4Oa+Ayi2deqyW+jT47ewspwT9e0gENXnaz3ZinF0jatFqjiPgj6T7wI4DLgD+R7mkfB7ycz5SbmZl1iRNuMzOz5plMSlR3zPcRN8K7pBHGewCbV2mzRZ6+UZhXOhve4eBiVUwEjiOdWb8/D9rWSsuz7d8DrgK2BqZKGlytYUQsjYj7I2JMRAwnXZlwOdAXmFDHus3MbBXnhNvMzKxJImIWcHt+ebWk3h21l7SlpI07WeZfSI/zgvQIsEpG5+mUwrz/ytMRxWdP1yoibgOOIn13mCTpH7q6DGBJnnb1KSmlbf9OV++tjuQU4GLSDxRTJdWUuOdB4caSfjTZJI+GbmZmVjMn3GZmZs11CvAKMBx4VNKO5Q0krSlpDOkS9A1rWObP8vR0SXsWK/Jydgc+AMaX5ufngN8H9CMlzBuX9esj6ZCOVhoRk4ARwDLgdknH1LCtRaUz7tt1sd944E3SoG1X5MeT/T9JG0j6akcLiIizgPNI97VPLf4dJPWVNKZKQn0Y6fvSh8CCLm63mZmt4vwcbjMzsyaKiPk5GbwD+CrwB0kvkgYAW0JKAHclXa79NjC/hmVOlnQR8CNS8vg4KSHdEdgBWAwcFxFvl3UdDTyYt+MVSdNIA7ttAvwtKUnfvJN1PyjpMNJzsW+S1Ccirutsm7NJpJHTb5H0EJ8nsD+KiPc6WOdHkkaQLtH/AXC0pCfy+9wM2Am4Daj6aLC8nHMlLSTdl/2YpK9HxLPA6sClwDhJzwMzSWe1twR2KWzj0hrfp5mZGeCE28zMrOkiYi6wl6TDgVGkM9AHk47D7wAPA/cAt0bEwhqX+eOcMJ9CGpRtD9Lzvm8CLqz03Oic/O9Fej73KL6Y6D8O3Frjuh+T9DXgAWC8pDUi4qoaul4J9AeOBQ7P6wa4AKiacOd1zshnpX9IGtjsIFJS/Gbe7mtr3PaLJS0CrgAeyfejTwdOIv0YMAT4OtCLdEb+VuAXEfF0Lcs3MzMrUuuf7GFmZmZmZmbW/fkebjMzMzMzM7MmcMJtZmZmZmZm1gROuM3MzMzMzMyawAm3mZmZmZmZWRM44TYzMzMzMzNrAifcZmZmZmZmZk3ghNvMzMzMzMysCZxwm5mZmZmZmTWBE24zMzMzMzOzJnDCbWZmZmZmZtYE/wfO17Ubl+FDTwAAAABJRU5ErkJggg==\n", - "text/plain": [ - "" - ] - }, - "metadata": {}, - "output_type": "display_data" - } - ], - "source": [ - "class LoopbackProgram(AveragerProgram):\n", - " def initialize(self):\n", - " cfg=self.cfg \n", - "# self.declare_gen(ch=cfg[\"jpa_ch\"], nqz=1) #JPA\n", - " self.declare_gen(ch=cfg[\"res_ch\"], nqz=1) #Readout\n", - "# self.declare_gen(ch=cfg[\"qubit_ch\"], nqz=2) #Qubit\n", - "# self.declare_gen(ch=cfg[\"storage_ch\"], nqz=2) #Storage\n", - "\n", - " for ch in [0,1]: #configure the readout lengths and downconversion frequencies\n", - " self.declare_readout(ch=ch, length=cfg[\"readout_length\"],\n", - " freq=cfg[\"frequency\"], gen_ch=cfg[\"res_ch\"])\n", - "\n", - " freq=self.freq2reg(cfg[\"frequency\"], gen_ch=cfg[\"res_ch\"], ro_ch=0) # convert frequency to dac frequency (ensuring it is an available adc frequency)\n", - " self.set_pulse_registers(ch=cfg[\"res_ch\"], style=\"const\", freq=freq, phase=0, gain=cfg[\"pulse_gain\"],\n", - " length=cfg[\"pulse_length\"])\n", - " \n", - " self.synci(200) # give processor some time to configure pulses\n", - " \n", - " def body(self):\n", - " cfg=self.cfg \n", - " self.measure(pulse_ch=cfg[\"res_ch\"], \n", - " adcs=[0,1],\n", - " adc_trig_offset=cfg[\"adc_trig_offset\"],\n", - " t=0,\n", - " wait=True,\n", - " syncdelay=self.us2cycles(cfg[\"relax_delay\"])) \n", - "\n", - "expt_config={\n", - " \"reps\":1, # --Fixed\n", - " \"pulse_length\":600, # [Clock ticks]\n", - " \"readout_length\":1000, # [Clock ticks]\n", - " \"pulse_gain\":5000, # [DAC units]\n", - " \"frequency\": 100, # [MHz]\n", - " \"adc_trig_offset\": 0, # [Clock ticks]\n", - " \"soft_avgs\":1000\n", - " }\n", - "\n", - "config={**hw_cfg,**readout_cfg,**qubit_cfg,**expt_config}\n", - "prog =LoopbackProgram(soccfg, config)\n", - "adc1, adc2 = prog.acquire_decimated(soc, load_pulses=True, progress=True, debug=False)\n", - "\n", - "# Plot results.\n", - "subplot(111, title=f\"Averages = {config['soft_avgs']}\", xlabel=\"Clock ticks\", ylabel=\"Transmission (adc levels)\")\n", - "plot(adc1[0], label=\"I value; ADC 0\")\n", - "plot(adc1[1], label=\"Q value; ADC 0\")\n", - "plot(adc2[0], label=\"I value; ADC 1\")\n", - "plot(adc2[1], label=\"Q value; ADC 1\")\n", - "legend()\n", - "axvline(readout_cfg[\"adc_trig_offset\"])" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "# Single tone (Resonator) Spectroscopy\n", - "\n", - "Measures the resonant frequency of the readout resonator when the qubit is in its ground state. We store this resonant frequency in the parameter readout_cfg[\"f_res\"] ." - ] - }, - { - "cell_type": "code", - "execution_count": 5, - "metadata": { - "ExecuteTime": { - "end_time": "2021-09-30T07:30:33.344414Z", - "start_time": "2021-09-30T07:30:33.286325Z" - } - }, - "outputs": [], - "source": [ - "class SingleToneSpectroscopyProgram(AveragerProgram):\n", - " def initialize(self):\n", - " cfg=self.cfg \n", - " self.declare_gen(ch=cfg[\"res_ch\"], nqz=1) #Readout\n", - " for ch in [0,1]: #configure the readout lengths and downconversion frequencies\n", - " self.declare_readout(ch=ch, length=cfg[\"readout_length\"],\n", - " freq=cfg[\"frequency\"], gen_ch=cfg[\"res_ch\"])\n", - " \n", - " freq=self.freq2reg(cfg[\"frequency\"], gen_ch=cfg[\"res_ch\"], ro_ch=0) # convert frequency to dac frequency (ensuring it is an available adc frequency)\n", - " self.set_pulse_registers(ch=cfg[\"res_ch\"], style=\"const\", freq=freq, phase=0, gain=cfg[\"res_gain\"],\n", - " length=cfg[\"readout_length\"])\n", - "\n", - " self.synci(200) # give processor some time to configure pulses\n", - " \n", - " def body(self):\n", - " self.measure(pulse_ch=self.cfg[\"res_ch\"], \n", - " adcs=[0,1],\n", - " adc_trig_offset=self.cfg[\"adc_trig_offset\"],\n", - " wait=True,\n", - " syncdelay=self.us2cycles(self.cfg[\"relax_delay\"])) " - ] - }, - { - "cell_type": "code", - "execution_count": 6, - "metadata": { - "ExecuteTime": { - "end_time": "2021-09-30T07:30:40.343926Z", - "start_time": "2021-09-30T07:30:33.352700Z" - }, - "scrolled": false - }, - "outputs": [ - { - "data": { - "application/vnd.jupyter.widget-view+json": { - "model_id": "2f2f4d7c535c41ffb18d2b37fd8c2c3b", - "version_major": 2, - "version_minor": 0 - }, - "text/plain": [ - "HBox(children=(IntProgress(value=0, max=400), HTML(value='')))" - ] - }, - "metadata": {}, - "output_type": "display_data" - }, - { - "name": "stdout", - "output_type": "stream", - "text": [ - "\n" - ] - }, - { - "data": { - "image/png": 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ZVCkrea7Ye90VEYuAl+b7F43DF2uSNOYMriVp6vsAWU8xZBm9y4OJ9+WPhwOfqhboQjb+tzSbb/l+FcWES/3s762GA4eBvqlK3QvYv1TQp6qUGY0/5o/PrHQyIl4BPG6IaxSXCltSrUDZckOviYgHlZfJk8utyXcL1M6APioRcX5E1AqEihnd/6Pk0PdrFH9tRJxYfjAiTiUbPQHwrZTSn4vn8qXHPpfv/l1EdA3RnoUVEvN9KH9cCrxziPrln/sh37d65Bnvv5jvPi8iHlehDbPI1hGHbP3vL5WcW1xrmau8/cfnu8W2F78g+3C++8SIeFWNa8woy73wTaD4nrw7z8xeXqeTLNkfwPqU0j3Vrg+8KyLayg9GxN+yf2TM58rPl/g62Zrnc4CPsz87v0PCJU0OtRbBdnNzc3Nr3o1syGTKt8cNUfYtJWVfWOH8e0rObyRL7HU80E4W/D6OLCv4DUB3Sb2ZZMM8vw+8imxe7hFkvdRnkAXug/l1Lyq7Z5D1mhfv+3Gy4cGHkg1v/UzJuW9WaPPMkvMvrvHcn1hS7piyc28vOXdh3ubDgIeQfSkxQDY0uljmLytc/7/yc1vzey3M2zYTiJJyDyRL+JaAu4C/z1/bxWTB/bUl91lZ4T6vyM/1j8Fnpzu/1nXAm8nm8h6Tt/144Hlk89CL7bkSaKnSngGy4d4F4MXAUcDR+efzzrzMbmBphXa0k61RXbzOp4DH5p+hRcApZL2mnyH7YqarwmfokpJ2fgtYkbfh0Pzz9BrgN8BpZXVfUFLvlfn7UHzfZozkdc+vcUdefgfwr2QB4mFkvbo/K7nn6yt8Tu8jC7hfkH9eDiVb8/wcsmXAinVfVVZ3NtnvbfH8F8iW+SqOFjmTLHHfjcC8srovKanXAzw9r3cs2e/0Pfm5bcDxFZ7zhfn528hGA/yCbAj7YWRTHP6DbHm5RJZVfvYQr+HHS9qTgOsb9W+sm5ubW71bwxvg5ubm5jayjfqC6wUl/0m+lpKgLz8/g6yXeKDsP7aVtotK6s0cRvlicLa4QrsWcWAQV2n7PjC/Qt2xCK4PydtW7d7XkGVerxVcn14SPJRvL67Qlm017tcPvLrK8xjL4PqLw3zfEnAFcGSt9pCtfVzted1PWVBcdp0OsoBsOG15WoX6c8l6PIeqWx5czyUbuVCp7KdH+rqTfTFUGKIta4f4nNbaPkdJ8F9S/3CyOctD1Z9Xoe551P7dvxs4q8rzLQbXl5EtmTZY5Rq3AScP4/VbXlZv1Vj9m+nm5uY23pvDwiVpGkgpbWf/8O9TKZsjm1IaTCm9hSwR0wfJgsptZP/h3ka2fu5HyXqkXlhSr5/sP8PnkWUHv5Gsx24vWQ/eBrLg5BEpm/9d3q57yXpNX0b2n/Oted278uu9CHhyqj5Hc1RSlhH7sWRfLGwmC5K3kfV0rgYewf5hs9WucXX+HC4Gbmf/XN5KZS8j6419F9lc2Z1kvbp/AD4NPCSl9JFRPalhSFlm94eRPcdvAb8j6zUdIOshvp4saHom2RcKd1a5VPF6vyD7HHyOLFnVHrL3/0vAQ1NK3TXqFoBHk81T/jrZ+tq782vcTjbP+DzgpJTSpRXq70opPRd4CnBRfv/7yRL1XUf2RcIzKFuLO2VzeB9DNvLgprzOqKWUriKbE/0Wst7kbflzuZXs9Xh0Sun8ClV/QpYley3ZF043k70Ou8m+BPgK2e/Cy1OF5HspG3J/NvB8st782/P73k32+/wJsoz4By2ZlbKl184ge//+SPZa7ACuJstWfkpK6YphPPeP5M/hO2S/w/cDvycbGbMsZUnLhrrGxry9kH1x88UaxSWpqURKqdFtkCRJk0w+H/1TZOs/j3T9b01yEXEh2ZdgP0jZEmJjcc1fkn2xdUlK6VljcU1Jmgj2XEuSJKkp5Mn+HpHvmshM0qRicC1JkqRm8S/54xay4eWSNGk4jEuSJEkNky//N5ds3v0r8sPvy3M6SNKkYXAtSZKkhoiIk8gS6pW6Dhj3xH6SNNYcFi5JkqRGS2RDwT8LPDGlNCbZ2yVpIpktfJQOP/zwdPzxxze6GZIkSZKkcXDllVf+OaW0eKhyDgsfpeOPP56NGzc2uhmSJEmSpHEQEbcMp5zDwiVJkiRJGiWDa0mSJEmSRsngWpIkSZKkUTK4liRJkiRplAyuJUmSJEkaJYNrSZIkSZJGyeBakiRJkqRRMriWJEmSJGmUDK4lSZIkSRolg2tJkiRJkkbJ4FqSJEmSpFEyuJYkSZIkaZQMriVJkiRJGiWDa0mSJEmSRsngWpIkSZKkUZrZ6AZIkqSx1d1TYN2GzWzp7WNJexurViwFYN2GzRR6+2iJYCAlOvJzXZ0dDW6xJEmTn8G1JElTSHdPgdXrN9G3dwCAQm8fq752NQTsHUgADKS079zq9ZsADLAlSRolg2tJkqaQdRs27wusi/YOpqrl+/YOsG7D5n11S3u7DbglSRo+g2tJkqaQLb19ddcp9mCX9nbboy1JUn1MaCZJ0hSypL1tRPXKe7v79g7whq9ezQnnf4ez1l5Od09hLJonSdKUZXAtSdIUsmrFUtpaWw441jojmBH1X2sgJRL7e7INsCVJqs7gWpKkKaSrs4M1K5cxe2b2J76tdQbrnnc6Dz22nZY8wi7G2S11BNylc7MlSdLBDK4lSZpiujo7OGLBbAAeePQCujo7aJkRLD9uETevfTr/+axTAaiR56yikcznliRpujC4liRpitk7MMiW3t0AFO7NAuItvbvpyOdjn3TEfAAOPWRWXdcd6XxuSZKmA4NrSZKmmC29fQwMJjra27hrx/307Rngju276ViUBccnHzkPgMecfPiw52K3tbawasXS8WqyJEmTnsG1JElTzJ/u2QXAo088DICrbu1lYDDt63k+7JBZLJrbyowIApg3eyYBtLe10lphIvaiua2sWbnMZbkkSarBda4lSZpibrk7C64fdeJhfO3K2/i/P94D7B/WHRGcfOR8vnvdHQwkeP/zH8qTHnwkAN09BdZt2MyW3j7mzZ7Jjvv7+fWbnsjMFr+PlySpFoNrSZImqWIgXOjtoyWCgZQNBV965DxmzZzBGQ9YBMDGW7LguqN9zr66M2fArj3Z2tZv/ea13Hd/P12dHfs2gAt/eQtv7r6WP+/cw1EL5yBJkqozuJYkaRLq7imwev0m+vZmAfJAylJ/F3r7uH1bH4fPm8WS9jYi4De33AvA0Qvb9tX99c337rvW7dt2s3r9JoADhn4fnQfUt2/rM7iWJGkIjvGSJGkSWrdh877Autxggm19/cyaOYMj5s/mvj0DtM9t5ZDZM/fV3Ttw4DpcldaxPnJBFlDfuX33ODwDSZKmFoNrSZImoaHWnL6/f5DunsK+5beWLNy/jFa1uuXH9/dcG1xLkjQUg2tJkiaZ7p4CM2LoNbRWr9/EYD5cvHSN6mrrVZcfP/SQWcxqmcEd9lxLkjQkg2tJkiaR4lzr4hzrWvr2DnDDlu0AXHbDnZy19nK6ewqsWrGUttaWA8pWWsc6Ijhy4WzusOdakqQhGVxLkjSJ1JprXcn9JXOrC719+xKXrVm5jI72NgLoaG+ruo71UQvmGFxLkjQMZguXJGkSGWqu9VCKicuuOP+cisF0uaMWtnHNbb2juqckSdOBPdeSJE0i1eZLt7e1HjTUu5p6AvSjF2Y912kYw9AlSZrODK4lSZpEqs2X/vdnnnrQUO9Fc1srXqNagF7JkQvmcH//INv69o6m2ZIkTXkOC5ckaRLp6uxgcDDx+q9dDWRB9KoVS/cN8S4d6l1MflY6R7tS4rJaSpfjap87ayyegiRJU5LBtSRJk8zy4w8FYO3KZfz1wx9QtVwx0F63YTNbevtYUhaID8fmO3YA8NQP/vSgQF6SJO1ncC1J0iRz09Ys4D3piHlDlu3q7BhxMNzdU+ATP/79vv1Cbx+vu+gq/uNb1/G2c081yJYkqYRzriVJmmRuumsnMLzgejTWbdjM/f2DBx2/d9deVq/fRHdPYVzvL0nSZGJwLUnSJHPTXTs5fN6scZ8DXSureHFJL0mSlDG4liRpkrnprp2cuHh8e61h6Kzio11zW5KkqcTgWpKkSSSlxE137Rz3IeFQedmvUvUs6SVJ0lTXNMF1RLwmIr4aETdExN0RsTcitkbEZRHx4oiICnV+FBGpxvbdGvebHRFviohrI2JXRNwTERsiYsX4PlNJkkamu6fAo9Zczvbd/Xz7mi3jPue5q7ODNSuX0d528HrZ9S7pJUnSVNdM2cLPA44ArgV+DtwHHAecAzwBeG5ErEwpHZxZBTYAd1Q4vqnSjSLiEOBy4OHAVuA7wKL8Pk+OiDeklN43uqcjSdLYKV+zeltfP6vXZ3/mxjNrdzHbeHdPgXd997fcvm038+fM5IJnnWa2cEmSSkRKqdFtACAi/hLoSSndV3b8VOAHwJHA36aUPldy7kfA2cDjU0o/quNeHwZeDfwYeEZKaWd+/BFkQXcb8LCUUs9Q11q+fHnauHHjcG8tSdKInLX2cgoV5jh3tLdxxfnnTFg7zn735WzZtpv+gTSidbMlSZpsIuLKlNLyoco1zbDwlNLPygPr/Ph1wEfz3SeN9j4RcSjwj8AgWbC+s+RevwLeDQSwerT3kiRprFRLHjaRScW6ewoUenezdyCRyNa9dkkuSZIyTRNcD6E/f9w9Btd6GtAK/Dyl9IcK579ULBcRB08ykySpAaolD5vIpGLrNmymf/DAEW8uySVJUqbpg+uIOAF4Zb77rSrFnh0RH4yIT0TEWyPiMTUu2Zk//rrSyZTSTcC9wCHAKSNpsyRJY23ViqXMaT3wz/ZEJxWr1kte6O2z91qSNO01U0IzACLi5WTzqFuBY4BHk30JsCaldHGVaq8t2/+PiLgCeEFK6daycyfkj7fUaMatZAnOTgCuq6P5kiSNi67ODm69Zxfv/f6NQDbXeqLnOy9pb6s47xuYkORqkiQ1s2bsuT4LeCnwQuCx+bG3AP9ZoexPgb8j62GeS5Zd/AXAH/PrXJZnBi9VXBj0oPndJYrzsOdXOhkR/xARGyNi49atW2s/G0mSxshh82YD8JNVj+eK88+Z8EC21rrXDg+XJE13TRdcp5RekVIKsmD5VOADwL8Dv4yIJWVl35JS+mxK6Xcppb6U0p9SSl8BzgD+QBZ0v6rsFsX1skecJj2l9MmU0vKU0vLFixeP9DKSJNVlU2EbC+bM5NhDJ26edaniutfVTGRyNUmSmk3TBddFebB8fUppFVnm7tOBjwyzbi/wwXz3aWWnd+SP86iueG5HjTKSJE2o67Zs47SOhUTE0IXHSVdnBx1NkFxNkqRm07TBdZni2tbn1pHB+7f5Y/mYuZvzx+Nq1D22rKwkSQ3T3VPg0Wt+wDW3beOa27Y1PHlYpeHhE51cTZKkZtN0Cc2q6CVbjmsmcChw5zDqHJY/7iw7/pv88cxKlSLiJLJkZruAG+tuqSRJY6i7p8Dq9Zvo2zsAwM77+xuePKx433d/97ds2babQ2a38I6uZSYzkyRNa5Ol5/qxZIF1L/DnYdb5q/yxfMmtS4G9wKPzZb7KvSh//E5KaU+9DZUkaSyt27B5X2Bd1AzJw7o6O/j56idw9imLOWrBHANrSdK01xTBdUQ8JiJeFBGzK5w7C/hMvvuZlNJAfvxxEXF2lE08i4i5EfFuoIust/vDpedTSvcAnyR77p+NiHkldR8B/BtZsrM1Y/YEJUkage6eQtWlr5olediiua38fut9nHD+dzhr7eUNH7IuSVKjNMuw8BPJ5lV/JCJ+A9xBtgzWicCD8zLfIVuSq+ihwPuBOyPid8AWsqHgD80f7wf+LqVUaZ3q84CHA48Dfh8RPwbagXOAFuBfU0o9Y/kEJUmqR3E4eDXNkDysu6fA/157B5B9K13o7Wv4kHVJkhqlKXqugR8DFwBXkS2ftRJ4MnAI8A3g2SmlZ6SU+srqfAK4FTgZeDbwKLL52B8BHpJS+lKlm6WU7iMbav4W4G7gXLI52JcDT0kpvXesn6AkSfWoNBy8qFmSh63bsJn7+wcPONYMQ9YlSWqEpui5Tin9EXhrnXV6OHgN63rq7wbenm+SJDWVWsO+16xsjuRh1drYLENADGY3AAAgAElEQVTWJUmaSM3Scy1JkkpUG/bd0d7WFIE1VG9jMwxZlyRpohlcS5LUZLp7Ctx3f/9Bx5tlOHiR611LkrRfUwwLlyRJmfJ1rYsWzW3lbeee2jS91rA/adnbLrmObX17OWrBHM5/6gObqo2SJE0Ug2tJkppItURmc2fNbMqgtauzgzmtLbzywiv59EuXc1rHwkY3SZKkhnBYuCRJTWQyJgk7auEcAO7YtrvBLZEkqXEMriVJaiKTMUnYUQvy4Hq7wbUkafoyuJYkqYmsWrGU2TMP/PPc7EnCFs+fTcuMsOdakjStGVxLktREujo7eNEjHgBAkC291SzrWlfTMiNYPG+2PdeSpGnNhGaSJDWZQ2bPpGVGcN1/rGBO2VJXzerIhXO40+BakjSN2XMtSVKTubawjZOPmDdpAmuAoxbMdli4JGlaM7iWJKmJpJTYVNjOqUsm15JWRy2YY3AtSZrWHBYuSVKDdfcUWLdhM4XePmYEDCa47IY76O45vKnnWpc6cuEcdtzfz33393PIbP97IUmafvzrJ0lSA3X3FFi9fhN9eweALLAG2NbXz+r1mwAmRYB9dL7W9YW/uoUv/vwWtvT2saS9jVUrlk6K9kuSNFoOC5ckqYHWbdi8L7Au17d3gHUbNk9wi0bmyHyt6/duuJFCbx8JKPT2sXr9Jrp7Co1tnCRJE8DgWpKkBtrS2zeq883iqDy43jMweMDxyfQFgSRJo2FwLUlSAy1pbxvV+Wax8eZ7qp6bLF8QSJI0GgbXkiQ1SHdPgfvu7696vq21hVUrlk5gi0amu6fA2y65vur5yfIFgSRJo2FCM0mSGqA8kVlRMVt4xyRKBlZr3vhk+YJAkqTRMriWJKkBqgWkRy9s44rzz2lAi0au1rDvNSuXTYovCCRJGi2HhUuS1ADVAtLJOD+52rDvw+fNMrCWJE0bBteSJDVAtYB0Ms5PXrViKW2tLQcdX3HakQ1ojSRJjWFwLUlSA6xasZTWljjg2GSdn9zV2cGalcvoaG8jgKMXZstyLVk4t7ENkyRpAjnnWpKkCdbdU2Ddhs3sHUj7jk2mBGaVdHV2HND2zv/83qQc4i5J0kgZXEuSNIEqZQkv9lhP1sC6kiXtbQbXkqRpxWHhkiRNoEpZwvv2DrBuw+YGtWh8HL2wjdu37W50MyRJmjAG15IkTaCplCW8lo72ORSm2HOSJKkWg2tJkibQVMoSXsuS9jZ27O5n++69jW6KJEkTwuBakqQJVGnZqsmaJbyW4pcFt/c6NFySND0YXEuSNIG6Ojt467kP2rff0d7GmpXLplQyM4Al7dlyXFu2OTRckjQ9mC1ckqQJdsYDDgXgwy/o5NzTlzS4NeOj2HM91eaSS5JUjT3XkiRNsGLAOdXmWZf6xU13A/Cmi6/lrLWX091TaHCLJEkaXwbXkiRNsMK+4HpOg1syPrp7Cryp+9p9+4XePlav32SALUma0gyuJUmaYLdv66NlRnDE/KkZXE+XtbwlSSplcC1J0gTb0ruboxbMoWVGNLop42K6rOUtSVIpg2tJkiZYobePjik833q6rOUtSVIpg2tJkibYlt6+KTvfGqbPWt6SJJVyKS5JkibQwGDijm27OXoK9+IW1+xet2HzvuRtpXOup9qa3pIkgT3XkiRNqK077qd/ME35IdJdnR2sWrGUWS37/6th1nBJ0lRmcC1J0gQq9uR2TOFh4UXrNmxmz8DgAcfMGi5JmqoMriVJmkC3byuucT21e67BrOGSpOmlaYLriHhNRHw1Im6IiLsjYm9EbI2IyyLixRFRcb2SiJgREf8cERsjYmdEbIuIn0bEC4ZxzxfmZbfldTfm12qa10WSNHV09xR44/pNALz8c7+e8sOjzRouSZpOmimIPA/oAvqAnwPfAG4CzgH+G7i4POiNiBbgYuAjwMnA94CfAWcCX46ID1W7WUR8FPgSsBz4KfB94JT8Wl/Pry1J0pjo7imwev0mtu/uB+D2bbun/Pxjs4ZLkqaTZgqu/xpYlFI6I6V0bkrpr1NKjwKWAXcCzwJeWlbndcAzgeuBU1JKK1NKTy+p85qIeFb5jSLiOcA/AXcAD0kpPSOl9GyyAP0G4NnAq8flWUqSpqV1GzbTt3fggGNTff5xV2cHa1Yu27em94yAd3adZrZwSdKU1DTBdUrpZyml+yocvw74aL77pOLxvGf53/LdV6WU7iyp8zuynnCAN1W43er88by8bLHencCr8t3zHR4uSRor03X+cVdnB1ecfw4vfPixDCZ4/deu5qy1l0/pHntJ0vQ0WYLH/vxxd8mxRwFHALellH5Soc7XgL3AmRGx7yvyiDgGeBiwJy9zgJTSj4ECcBTwyDFpvSRp2pvO84+7ewqsz4PphEtySZKmpqYPriPiBOCV+e63Sk515o+/rlQvpbQLuC7ffWiFetellKp1F/y6rKwkSaOyasVS5rQe+Gd3usw/XrdhM7v3uiSXJGlqm9noBpSLiJcDZwOtwDHAo8m+BFiTUrq4pOgJ+eMtNS73J7LA+oSSY8OtV1pWkqRR6ers4JZ77uP9389mI3W0t7FqxdJpMf94ug6JlyRNL00XXANncWDisn7gLcD7ysrNyx8PmqddYmf+OH8M6kmSNConHJ79Cdrwusey9Kjp8ydmSXsbhQqB9HQYEi9Jmj6ablh4SukVKaUA5gKnAh8A/h34ZUQsKSlaXPc61XmLkdbbf4GIf8jXxN64devWkV5GkjTN3HrPLgCOPXR6BZUuySVJmg6asecagHw+9PXAqoi4A3gP2RrUK/MiO/LHeRWqU3ZuR8mxkdYrbdsngU8CLF++fMRBuiRpauvuKbBuw2a29PaxpL2NYxe1cfi8Wcyd1bR/fsdFcej7ug2bKfT20dbawpqVy6bFkHhJ0vTRdD3XVXwufzw3Ilrzn2/OH4+rUe/YsrKjqSdJ0rB19xRYvX4Thd6+fRmy/+/mezhkVsuQdaei4pJcT3jgERyzqM3AWpI05UyW4LqXbO71TODQ/Nhv8sczK1WIiLnAafluT8mp4s+nRkS1cXlnlpWVJKku6zZspm/vwAHHBhPctWNPg1rUHE7tWMjvt+5k157+oQtLkjSJTJbg+rFkgXUv8Of82C+Au4BjIuKxFeo8jyzj+K9TSvsW0kwp3UoWmM/KyxwgIs4my1J+R34PSZLqVi0TdnnAPd0s61jIYIIbbt/e6KZIkjSmmiK4jojHRMSLImJ2hXNnAZ/Jdz+TUhoAyB/X5cc/HhFHlNQ5GVib776jwi3X5I/vioiTSuodAXws312bUho8qKYkScNQLRN2e1trxePTRaE3S+r2nI//grPWXk53T2GIGpIkTQ5NEVwDJwIXAndExA8i4ksRcUlEXAf8DPgL4DtkS3KVej/wLeDBwO8iYn1EfAu4BjgK+HBK6ZvlN0spfR34eF5mU0R8KyLWA7/Lr9VNljxNkqQRWbViKbNnHvxn9kWPfEADWtMcunsKvOt/f7tvv9Dbx+r1mwywJUlTQrME1z8GLgCuAk4hywj+ZOAQ4BvAs1NKz8gziO+T9153Aa8BbgJWAGcDVwIvSim9ttoNU0r/BLyIbIj42Xndm4BXA88p9pBLkjQSXZ0dPPuMg5N2ff3K26ZtMJnNQz9wUFjf3gHWbdjcoBZJkjR2mmItkJTSH4G3jrDuIFkvc909zSmlLwNfHsl9JUkaSnvbLFoCWmbMYM9AFlTeuf1+Vq/fBDDtMmZXm4de7bgkSZNJs/RcS5I05fx+604iYl9gXTRde2urzUOvdlySpMnE4FqSpHHyh6076R9MFc9Nx97aVSuW0tZ64Drfba0trFqxtEEtkiRp7BhcS5I0DvYODPKne3Yxb3blGVjTsbe2q7ODNSuX0dE+B4C5s1pYs3LZtBseL0mamgyuJUkaB7fes4u9A4lzTz/a3toSXZ0dXHH+E3jMyYdz/GGHGFhLkqYMg2tJksbBH7beB8Dzlh+b99a2EUBHe5u9tcBpHQu58c4d7N7r4hySpKmhKbKFS5I0lXT3FHjrN68F4J+/9BvOe8oDueL8cxrcquayrGMh/YOJG+/cwUOOaW90cyRJGjV7riVJGkPdPQVWr9/E9t39ANy+bTer12+atmtbV3P7tiyh2zM/cgVnrb3c10eSNOkZXEuSNIbWbdhMX9lQ5+m69FY13T0F3lPyehR6+/wCQpI06RlcS5I0hqotsTUdl96qJvsCwrW/JUlTi8G1JEljqNoSW9Nx6a1q/AJCkjQV1ZXQLCIOAx4PdAJHAu3AvcBdwG+AH6WU7h7rRkqSNFmsWrGUN3ztagYG075j03nprUqWtLdRqBBI+wWEJGkyGzK4joiZwPOAfwIeBUS+lUtAioifAx8Dvp5S6h/DtkqS1PS6Ojt456XXs62vnz39gyxpb2PViqXTfumtUqtWLGX1+k0HzE33CwhJ0mRXM7iOiL8B3gksIQuo7wR+AVwP3ANsBxYAhwEPBh4J/CVwFvDuiHhjSunCcWu9JElNpLunwJr/vYG7duxhYdtM3vWchxhUV1B8TdZt2Eyht49ZLTNc+1uSNOlVDa4j4lfAcrKA+r3AF1JK1w11wYg4DXgZ8ELgCxHx6pTSI8emuZIkNafiElzF3thtff2sXr8JwKCxgq7ODro6O3j7t6/ni7+8haecdlSjmyRJ0qjUSmh2LPBa4LiU0r8NJ7AGSCldm1L6V+A44F+AB4y+mZIkNTeX4BqZR/zFYezpH+TqW3sb3RRJkkal1rDwE1NKI07bmVLaC3wkIj4z0mtIkjRZmAF7ZLbu2A3A8z/5Szqcny5JmsSq9lyPJrAej+tIktTMXIKrft09BS749g379gu9faxev4nunkIDWyVJ0si4zrUkSWNg1YqltLYcuJiGGbBrcyi9JGkqMbiWJGkMdHV2cMqR82mZEQTQ0d5mBuwhOJRekjSV1MoW/odRXDellE4cRX1JkiaVgcHEn+7ZxfMedgxrn/OQRjdnUljS3kahQiDtUHpJ0mRUK6HZ8aO4bhpFXUmSJpXungLvuPQGduzuZ8N1d/DIvzjMHuthWLVi6QHLl4FD6SVJk1et4PqECWuFJEmTVPn61vfu2uv61sNUfH3Wbdi8rwf7X1ec4usmSZqUIiU7mUdj+fLlaePGjY1uhiSpQc5ae3nFoc0d7W1ccf45DWjR5PRfP/k9ay79LYBLckmSmkpEXJlSWj5UOROaSZI0CiblGr3ungIf+P6N+/ZdkkuSNBnVHVxHxIyIeHpEvD0i/isi/rbk3OKIOCUiWsa2mZIkNSfXtx69bEmuwQOOuSSXJGmyqSu4jogzgN8ClwBvBF4B/GVJkWcCNwBPG6sGSpLUzFatWErLDNe3Hg17/yVJU8Gwg+uIOA74PnAScCnwb0CUFfsGsBfoGqsGSpLUzJ55+hLaWmfQ1jrD9a1HyN5/SdJUUE/P9ZuARcCrU0rnppTeU14gpdRL1nN95hi1T5KkptXdU+Dh7/wBO+8fYE5rC+9//kO54vxzDKzrtGrFUtpaD5xRZu+/JGmyqbUUV7kVwA0ppY8NUe5W4FEjb5IkSc3PJbjGTvmSXK0tYe+/JGnSqafn+kjg2mGU2w3MH1lzJEmaHLIkXAMHHDMJ18h1dXZwxfnn8KrHnUhK8JTTjmp0kyRJqks9wfUOsgB7KCcAfx5ZcyRJmhxMwjU+Tj9mIf2DiRtu397opkiSVJd6guseYHlEHF2tQEQsBR4K/N9oGyZJUjMzCdf4eMgx7QBcc9u2BrdEkqT61BNcfxaYC3wpIg4rPxkRC4BP5tf87Ng0T5Kk5rRqxVLKVuAyCdcY+NUf7mZGwNsuuY6z1l5Od0+h0U2SJGlYhh1cp5S+AlwMPA74Q0Rckp96ZERcBPwReAzw1ZTSt8e6oZIkNZOnLjuKlhnBIbNaXIJrjHT3FHjjxdcymLL9Qm8fq9dvMsCWJE0K9fRcAzwfeDdZlvFn5MceCDwPmAd8APibMWudJElNqLunwKPXXM7egcRsl+AaMyaJkyRNZvUsxUVKqR84PyLeBTwe+AughWz5rctSSneNfRMlSWoe5Utw3XPfHpfgGiPVksEVevvo7in4+kqSmlpdwXVRSuleYP0Yt0WSpKZXq3fV4G90lrS3UagSYPsFhiSp2Q17WHhEvCoi2sezMZIkNTuX4Bo/q1Yspa21peI5h4dLkppdPXOuPwrcHhFfiYinREQMWUOSpCnGJbjGT1dnB2tWLqt63i8wJEnNrJ7gej0QwF8B3wFui4i1EfGgcWmZJElNprunwM779x503CW4xk5XZwcdfoEhSZqE6lmK67nA0cCrgSvzn/8NuDYifhkRr3TYuCRpqiomMtvW13/A8UVzW12Ca4xVGh7uFxiSpGZX11JcKaV7U0ofSyk9HHgw2bJcW4CHc+Cw8afWc92IaI2IJ0TEe/NA/faI2BMRhYj4ekQ8rkq9z0dEqrH9tsY9Z0TEP0fExojYGRHbIuKnEfGCetouSZoeKiUyA5g7a6aB9RgrDg/vaJ8DwNxZLX6BIUlqeiPKFg6QUvot2bJcq4EnAy8FnkU2bPy5dV77bOD7+c93kPWM30cWwD8HeE5EXJBSemuV+lcAN1U4fnulwhHRQjbM/ZnAduB7wGzgCcCXI+JRKaXX1tF+SdIUZyKzidXV2UFXZwfP+8TP9+1LktTMRhxcF6WUErAhIm4DdgB/TzY3ux6DwDeAD6aUflp6IiKeD3wJeEtE/DCl9MMK9T+dUvp8Hfd7HVlgfT1wTkrpzvxeJwM/BV4TET9IKX2zzuchSZqiqi0T5Tzg8XXKkfP51tVbSClhLlVJUjOra1h4uYhYlA+t/jVwDfCK/NQV9VwnpXR5Sum55YF1fu4i4PP57otH017Y12v9b/nuq4qBdX6v3wHn5btvGu29JElTx6oVS2ltOTC4cx7w+Ft61Hy27+7nzu33N7opkiTVVHdwnc9VfkZEfJ1svvWHgIcBBWANcEpK6bFj20x68sdjxuBajwKOAG5LKf2kwvmvAXuBMyPCMWiSJCAbltx5bDszIhue1dHe5jzgCXDyEfMB2Hznjga3RJKk2oY9LDwilgEvA15IFpwGsBv4ClnP8mX5EPHxcHL+WHEONfD4iHgIMA+4E/gZ8P2U0mCFsp35468rXSiltCsirgMemm+FEbdakjSl7O4f5NEnHs6Fr3hEo5sybZxy5DwAbrxjB2efsrjBrZEkqbp65lxfDSSyoPqXZAH1V1JK28ehXftExFFkQT1k87IreUmFY9dHxF+nlDaVHT8hf7ylxm3/RBZYn1CjjCRpGhkYTGy+Ywd/88jjGt2UaeWnv/szMwLecekNfP7nN7NqxVJHC0iSmlI9wfXtwBeBz6eUNo9Tew4QETOBC4GFwA9SSt8qK3IVWWbxH5AFywuAM4B3AKcDl0XEGSml0t7nefnjfTVuvTN/nD+6ZyBJmipuufs+7u8fZOlR/mmYKMW1xQfzcXGF3j5Wr8++MzfAliQ1m3qC62OrDLMeT58gWx7rViokM0spfaDs0H3AdyLi+8CPgUcCq4FXl5QpZqMZ8RD2iPgH4B8AHvCAB4z0MpKkSeS3d2Rzfh909IIGt2T6qLS2eN/eAdZt2GxwLUlqOsNOaFYeWEfErIg4OiIOHftmQUR8EPg7snWvn5BSumO4dVNKe8iSqwE8rex0MSPKPKornquYPSWl9MmU0vKU0vLFi53/JUlTXXdPgfO+cQ0A//DFjXT3mI5jIri2uCRpMhlJtvCX5Etv3QfcBryn5NxzI+LLETGqucoR8V7gtcBWssD6dyO4zG/zx/Kvtm/OH2tNmju2rKwkaZoqDk3esbsfgC3bdrN6/SYD7AlQbQ1x1xaXJDWjuoLriPg88Dmypbf62D/EuuhW4K+B5460QRHxbuD1wN3Ak1JK14/wUofljzvLjv8mfzyzyv3nAqfluz2VykiSpo9aQ5M1vlatWEpba8sBx1xbXJLUrIYdXEfES8mycl8NLCdLMnaAlNKvyNa+fupIGhMRa4FVwL1kgfXVI7lO7q/yx/Ilt34B3AUcExGV1uN+HtAK/LosEZokaRpyaHLjdHV2sGblMjrynuoZAe989mnOt5YkNaV6eq7/nmwO8rkppd/UWNP698Dx9TYkIi4AzgN6yQLrmr3GEfHQiHhGRLSUHZ8ZEa8nG1YO8P7S8ymlAWBdvvvxiDiipO7JwNp89x31PgdJ0tTj0OTG6urs4Irzz+GCrtMYTND5gEWNbpIkSRXVky18GfDLYfTmbqHKkOtqIuKZwJvz3ZuA10SUjzgH4LcppWLwezxwMXBPRNxINv97ft7OJcAgcF5KaUOF67wfeCxwLvC7iPgBWW/1E4E5wIdTSt+s5zlIkqamVSuW8oavXs1AyXfKDk2eeI88Icuf+qs/3s3xhx/S4NZIknSweoLrVg6ev1zJYcDeOttRmnF8eb5V8mP29yxfDXwQeDhZcrJOsuW1biObF/7RlNKVlS6SUhqIiC7gn4CXAyuAAbI1sz+WUvpyne2XJE1Rz3jI0Zz/jauZPaOFvj0DLGlvY9WKpQ5NnmDXFrYxI+C8b2ziQz+4yfdAktR06gmu/8T+RF8V5UO0TyUbGj5sKaXPA5+vs84fgdfVU6es/iDwkXyTJOkg3T0F3v6d69ndnzh07gze+exlBnQN0N1T4I0XX8tgPnig0NvH6vWbAHw/JElNo5451xuAkyLixTXK/CNwNPCdUbVKkqQGKy7B9eedewC4Z9del+BqEDO2S5Img3qC63VkCc0+GxHvjIgz8uNzIuJBEfFW4H1kS2h9eIzbKUnShDKgax5mbJckTQbDDq5TSrcBzyabd30e2RJXCXg+cC3w78Bu4LkppbvGvKWSJE0gA7rmYcZ2SdJkUE/PNSmlHwIPBt4DXAf0AXvI5lh/GDgtpfTjsW6kJEkTzYCueaxasZS21paDju/a0+8wfUlS06gruAZIKd2RUjovpfSQlNK8lFJbSumUlNK/5L3bkiRNev/65FMoXxTSJbgao6uzgzUrl9He1nrA8XudBy9JaiJ1B9eSJE113T0F3nnpb0lA5BF2R3sba1aaLbxRujo7OGT2wYucOA9ektQs6lmKS5KkKa+YJbyYzCyl/T3WBtaN5Tx4SVIzqxpcR8RnR3HdlFL6u1HUlySpIWplCTe4bqwl7W0UKgTSzoOXJDWDWj3XLxvFdRNgcC1JmnTsHW1eq1YsPWBUQVExsZlffkiSGqlWcP3yCWuFJElNwt7R5lUMnv/9kuvo7du773gxsVlpGUmSJlrV4Dql9IWJbIgkSc3gNeecyPnrrz3gmFnCm0dXZwfrNmw+ILgGh+5LkhrPbOGSJOW6ewqs/W6WeXqGWcKbVrUh+oXePpflkiQ1jMG1JEnszxLeuyvrER00S3jTqjVE33WvJUmNYnAtSZr2unsKvOGrV1fNEq7msmrFUtpaWyqe8z2TJDWK61xLkqa1Yo/1QEoVz5slvPkURxK87qKrKp73PZMkNYI915Kkaa3SutalzBLenLo6O+io8t74nkmSGsHgWpI0rdXq5TRLeHOrNDzc90yS1CgG15Kkaa1aL2dLhFnCm1xXZwdrVi7b14M9I/A9kyQ1jMG1JGlaW7Vi6b5lt4raWlt471+dbpA2CXR1dnDF+efwxqc9kMEEjz1lcaObJEmapoYdXEfE7Ih4QETMr1Fmfl5m1tg0T5Kk8dXV2cGCOTNpa20hcF3ryepBRy8A4Ibbtze4JZKk6aqenut/Af4InFGjzBl5mVePplGSJE2Ue+/bQ29fP6974sn8ce3TueL8cwysJyGDa0lSo9UTXD8TuDWl9ONqBfJztwHPGm3DJEmaCNfnwdipSxY2uCUajcPnzeaI+bP3vZ+SJE20eta5PhGovKDkga4HTh9ZcyRJmljXb8mCsQcvWdDglmi0Dj1kFpdctYWLf1NgSXsbq1YsdRSCJGnC1NNzfShwzzDK3ZOXlSSpqXX3FHjf928E4NwP/4zunkKDW6SR6u4pcNNdO+kfTCSg0NvH6vWbfE8lSROmnuD6z8BJwyh3EtA7suZIkjQxunsKrF6/ib69A4DB2GS3bsNm+gfTAcf69g6wbsPmBrVIkjTd1BNc/wpYHhFnViuQn1sO/N9oGyZJ0nhat2HzvsC6yGBs8trS21fXcUmSxlo9wfV/AQF0R8STyk/mxy7Odz8xBm2TJGncGIxNLUva2+o6LknSWBt2cJ1S2kAWYB8NfDcibomI7+XbLcB3gSXAp1NKl45PcyVJGhsGY1PLqhVLaWttOeBYW2sLq1YsbVCLJEnTTT0916SUXgW8AbgbOBZ4Yr4dmx97Q0rpH8e6kZIkjbVVK5YSZccMxiavrs4O1qxcxqK5rQAsnj+bNSuXmS1ckjRh6lmKC4CU0vsj4kNkc6uPyw/fAlyZUuofy8ZJkjReHnbcIhKwsG0m2/v6XbppCujq7OCskw7nzHdcxsvPOt73UpI0oeoOrgFSSgNkCc5+NbbNkSRp/HX3FHjbJdcBMHtmC+9//mkGYlPE4vmzOWrBbD542e9Y993NfmkiSZowIwquJUmarMqX4Lprx/2sXr8JwABsCujuKbB15x4G8mW5ikusge+vJGl8VQ2uI+Ilo7lwSumLo6kvSdJY6+4p8IavXs1AqrwessHX5Lduw+Z9gXWR768kaSLU6rn+PJBqnK8m8noG15KkplHssS4PrItcgmtqcIk1SVKj1Aquv8jBwfUi4Jn58WuAm/PjxwMPyX++BLh3zFooSdIYWLdh876h4JW4BNfUsKS9jUKFQNr3V5I03qoG1ymll5XuR8ShZAnMfg68KqW0qez8acDHgFOBR4x5SyVJGoVaPZcuwTV1rFqx9IA59UW79vTT3VNwaLgkadzUs871BWQ9108rD6wBUkrXAufmZd4+Ns2TJGlsVOu5bIlwPeQppLjedXtb6y1DQhcAACAASURBVAHH7921l9dddBWd//k9unsKDWqdJGkqqye4Phf4YUppe7UCKaVtwA+BZ4y2YZIkjaVVK5YSZcfaWlt471+dbmA9xXR1dnDI7MqD8+7dtZfV6zcZYEuSxlw9wfURQMswyrUAi0fWHEmSxsdjTj6cBCyYM5MAOtrb7LGewmpNAyhmD5ckaSzVs871bcDjI+KwlNLdlQpExOHAOcCWsWicJElj5erbegH41EuW84i/OKzBrdF4q5bYrMjs4ZKksVZPz/VFwELgsoh4TPnJiPhLYAMwH/jK2DRPkqSxcdWt25gRcFrHwkY3RRNg1YqltLVWH3Bn9nBJ0lirJ7h+B7AROB34UUT8KSJ+nG+3AD8GOoHf5GWHLSJaI+IJEfHeiPhlRNweEXsiohARX4+Ixw1R/4UR8dOI2BYROyNiY0T8c0TUfH4R8ZSI+F5E3BMRuyLi2oh4U0TMrqf9kqTm1d1T4Ky1l/Oh/8/evcfJUdV5H//8ptMhHQNMVBAzIRAUgmJIRoKiuNw1IIs7CwK73tlHeQQRUYyEZ1XAyyYaeYiroIursi6KXHd0nwgRCSKisCROQgQTo9wbEBQGgQzJZOb3/FFVSU9PVd97+vZ9v179qkxVnZrTmerq+tU553du2USXGTff96dGV0kmQFJiM1B2eBERqQ9zz5/KusDOZlMJsoZ/CJiWt/kF4N+BT7v7C2VVwuwY4ObwxyeANeHxXgu8Llz/eXf/bEzZS4EzgReBW4Bh4GiCFvT/Ak5293ETm5rZp4AvASPAzwnm5j6cYLz4ncDR7r65WN0XLFjgq1evLvWtiojIBOofyI6blimTTmmsdYfpH8jymf7f8tyWbczYdQqfOnZ//f1FRKRkZrbG3RcU3a+c4Drn4FOAg4CZ4aossMbdKxrAZGZHEQTIX3X32/O2nQp8nyBR2lHufmvOtpOA6wgC8sPcfVO4/hUEWctfA5zj7l/NO+YC4H+AofCYd4XrpwErgMOA5e7+8WJ1V3AtItK8Dl26KnbcbU93hjsWH9WAGkmj3Lj+cc74/m/48VmHcuDM7kZXR0REWkipwXU53cK3c/cX3f0Od786fP2y0sA6PN4qd39nfmAdbrsauCL88T15m88Pl+dFgXVY5k/AGeGPi2O6hy8GDPhSFFiH5Z4HTgNGgTPNTN++IiItLClplZJZdZ7XztgFgPseS5xRVEREpCoVBdcNMBAuo5ZyzGwmQev5VuDa/ALufhtBi/oewCE55SYDx4U/fj+m3P3Ar4HJwNtrU30REWmEpKRVSmbVefacPpWdd5rEfY8ruBYRkfooZyqu7czsNcB+wC4ELcDjuPv3qqhXvn3D5eM563rD5b0FWs3vBnrCfX8VrpsDTAWedvc/Fih3aFjuB5VWWkREGqd/IMsLW7aNW69kVp2pq8t4zSt34b7H/kr/QJZlKzfy2OAQM7ozLFo4R2OwRUSkamUF12b2ZuBygrHMibsBDtQkuDazPYAPhD9en7Npdrh8qEDxh/P2zf33wySLKyciIi0iLpEZwPSpaS444QAFUh1qp3QXt2/6M6sfemb7uuzgEOffsB5A54WIiFSl5G7hZrY/8FOCDN6/Bh4IN/2QYIqu6A6mn9oF1pOAKwnm177F3f87Z3OUrbxQZvLnw+XONSiXW6/Tw+m+Vj/11FMFDiMiIo2wbOXGcYE1wNTJkxRAdaj+gSx33v+X2G1DwyMsW7lxgmskIiLtppwx14sJulP/b3d/C3A7gLu/293fSDD/9RqC7uJn16h+3ySYVusRxiczi7qjl5vuvNJy27n75e6+wN0X7LbbbpUeRkRE6kSJzCTfspUbGR5J/urXuSEiItUqJ7g+Atjk7t+K2+juvwP+FpgFfKbaipnZV4H/RTDN1tHu/kTeLs+Fy/z5tnNF257LWVdpORERaQH9A1m6LDYdiBKZdbBiwbPODRERqVY5wfUewG9zfh4BMLOdohXu/iRwG/D31VTKzC4maP1+iiCw3hSz24Phcq8Ch9ozb9/cf88qs5yIiDS5aKz1iI9voVQis85WKHjWuSEiIrVQTnD9PGMzg0dzWbwyb78hggzdFTGzLwOfAP4CvNXd70vYNZqe6wAzS/rGPDhvX4ANYR1famavSij3hphyIiLS5JLGWqfMWHLiXI237mCLFs4hk06NWz91ckrnhoiI1EQ5wfWj7GjRhSBIBTgyWmFmaeCNBC3OZTOzpcAi4BmCwHpd0r7u/gjwG4L5qE+OOdbhBPNiP0GQgC0qtxW4Mfzx3THl9gHeRDB/9opK3oeIiDRGUtffUXcFTx2ur7eHJSfOpac7gwE93VPYZcokjtp/d50bIiJSE+VMxXUHcJqZ7eLufyUIPEeAS8xsCkHw/SGCgPaH5VbEzD4PnAcMEgTWpbQaLwGuBb5kZr9y9z+Ex9oduCzcZ6m7j+aVW0rQdf08M7vJ3f8nLDcN+A7BQ4fL3H2w3PchIiKNM6M7QzYmwNZ4WoEgwM4NpN/5jTv4yfrHmb14hea7FhGRqpUTXN8AvI0gsdmP3T1rZksIkpd9PdzHCILjfy6nEmb2DuDT4Y9/AD5q8cloNrj70ugHd7/OzL4BnAGsN7OfAcMEGcZ3IZgW7Ov5B3H3u81sMfAl4Fdmtiqs9+HA7sBd5b4HERFpvEUL5/Cp69axNScrtMbTSpz+gSzrHn2W0fBU0XzXIiJSrZKDa3e/Bdg3b90FZnYP8E7gpQRdxZe7+4Nl1uOlOf9eEL7i3EbQ6pxbhzPN7JfARwiC41RYj+8A34hptY7KfTms+7kEY7OnAPcD/wp8xd23lPkeRESkgfoHsixbuXFMYN2j1khJEDc1VzTftc4XERGpRDkt17Hc/Xrg+iqPcQVwRRXlfwD8oIJyNwE3Vfp7RUSkcaJgOjs4hAH5+cGjFmsFShJHc6GLiEitlZPQTEREpClEU25F46vHT7y1oxVSJE7SOHyNzxcRkUolBtdh5u+q1eo4IiIikaQpt/KpFVKSxE3NpfH5IiJSjUIt1783s/dZQmaxYizwAeD3FdVMREQkQalBs1ohJcmOqbmmbF8X9XboH8g2sGYiItKqCgXXzwPfBTaZ2T+b2axSDmhme5nZZ4BNBEnF/lp9NUVERHYoJWhWK6QU09fbw6KF+5Pq2tGOEGUNV4AtIiLlKhRczwM+BnQDnwceMLONZnaFmZ1nZh80s1PC5Xlm9h9m9nuCjNsXAbsCZwG99X4TIiLSWRYtnMOUdPJX2PSpaZacOFfJzKSoZSs3MjIanzVcRESkHInZwsMprL5uZt8FPgCcCbyGYDquuNwx0WPfe4DLgCvdfXNNaysiIkLQ4njfY89y+e0PAJAyY8RdU29J2ZQ1XEREaqXoVFzu/gJwKXCpmb0aOAKYD+xO0Do9CDwJ/Aa4tYI5rkVERMrW1dVFOmXcc8FCMpNTxQuIxJjRndmedT5/vYiISDnKmufa3f8A/KFOdRERESnZXQ/8hQNndiuwlqosWjiH829YPyb7vMbri4hIJTTPtYiItJT+gSxvWnILAw8PsvGJ55R4SqqirOEiIlIrZbVci4iINFL/QHZMK+PzW7Zx/g3rATTOWioWnTufvHYd28LkZlHW8NztIiIihajlWkREWsaylRvHdN8FZXaW2li2cuP2wDqic0tERMqh4FpERFqGMjtLvejcEhGRaim4FhGRlpGUwVmZnaVaSedQlxmzF6/g0KWrNAZbREQKUnAtIiItY9HCOaRTNmadMjtLLSxaOIdMenzm+RF3nB1jsBVgi4hIEgXXIiLSMvp6e5g7Y1e6DAzo6c6w5MS5SjglVYuyhr982k4AdNn4fTQGW0REClG2cBERaQn9A1m+vHIDjw2+SCadUlAtNdfX28PCA/bgdReuZCQvuVlEY7BFRCSJWq5FRKTpRVNwPTb4IhC0IKqLrtRDZnKKfXefxk6T4m+RNL5fRESSKLgWEZGm1j+Q5dxr1mkKLpkw82Z2kzKwvK7hGt8vIiKF1DS4NrP7zGzEzLbV8rgiItKZohbrEVcXXZk4I+5sHh7FPRjbD7DLlEkaiiAiIgXVesx1Fzu+h0RERKqybOXGcS3WudRFV2qtfyDLf697bPvPTnBj84pddlJgLSIiBdU6uH4vMLXGxxQRkQ5VqGVaXXSlHpat3MiWbaNj1jmw6ckXmL14BTO6MyxaOEeBtoiIjFPT4Nrd767l8UREpLPN6M6QjQmwU2bqoit1UeiBTu5814DOPxERGUMJzUREpGktWjiHyXlZmzPpFBefMk+BjdRFKUMNlExPRETiVNxybWZdwMsIHuQ+7e6jRYqIiIgU1T+QZdnKjTw2OMSM7gz7vGwqG/70PAbqkit1t2jhHM6/YX3Bsf6gZHoiIjJe2cG1mR0LfBx4CzAlXP2imf0S+Kq7/6SG9RMRkQ4SZQePApuoS/ikLuMrJ6u1WuovOseiBzxdZrHZ6h3Ye/EKevTAR0REQuYJ05vE7my2HPgoOzKCR63VUZ89By5197NrVsMmt2DBAl+9enWjqyEi0hYOXboqdow1BN3BNc5aJlr+A584OjdFRNqbma1x9wXF9it5zLWZfQA4G3ge+BywL5AJX/sCFwHPAR8xs9MqqLOIiHS4Ql1tNc5VGqGvt4clJ84lZckzjercFBERKC+h2VnANuAYd7/Q3f/o7sPh64/ufhHwVmAEOLMelRURkfZWLJmUxrlKI/T19jBapKefzk0RESknuH4NcFuh6bbCbbcBr622YiIi0nkWLZzD5FTyV1MpmZxF6qHYuadzU0REygmuNwNPlrDfU4Ae34qISNn6ens4bL+Xx27LpFMsWjhngmskEli0cA6ZdCp2m85NERGB8oLrO4CDzZIHHYXbFoT7ioiIlG1w8zC9s7pZfup8erozGNDTnVHCKGmoaOx1T9hCnTsGOxpz3T+QbVT1RESkCZQzFdcFwK+Bi83sPHcfzt1oZpOALwEzgVNqV0UREekE/QNZvnzTBh579kWm7RR8Pd2x+KgG10pkh77enu0PePoHspx3/T1s2RZMnJIdHOL8G9Zv309ERDpPOcH1POAK4GPAyWZ2LfBAuG1v4GSgB/gmcKCZHZhb2N2/V21lRUSkPeVPd/T8lm0KVKSpLVu5cXtgHYlasHXOioh0pnKC6ysI5rE2giD6Y3nbo/5RHw5f+RRci4hIrGUrN46bR1iBijSzpOzgyhouItK5ygmuv0cQXIuIiNSUAhVpNTO6M2Rjzs8uM/oHsnooJCLSgUoOrt39A3Wsh4iIdLCkQEXTG0mzWrRwzpihDJERdw1pEBHpUOVkCxcREamLRQvnMKlr7GQUmt5ImlmUPTwVM4lKNKRBREQ6i4JrERFpqP6BLMtWbmDb6I6RR5p6S1pBX28Pox4/Yi47OKSpuUREOkw5Y64BMLM9gcOBGcCUhN3c3T9fTcVERKT95WcJhx0t1gqspRUkDWkAOOfqtVz03/dywQkH6HwWEekAJQfX4TzWXwc+yI7M4Pl9oaJs4g4ouBYRkXGCluqNiQGJsoRLK0kaex15ZvOwxmCLiHSIclquLwROB7YBPwE2Ac/XqiJmNgc4FjgYWADsRxCon+zu1yWUuQJ4f4HDbnT3/RPKdgFnAKcB+wMjwD3AZe5+VYVvQ0RECohrqY6jLOHSKqKA+Zyr1ybuowdGIiKdoZzg+r3AC8Ch7n5PHepyBuPnzi7VHcAfYtY/HrezmaWAG4B3AH8FfgrsBBwN/MDM3uTuZ1dYFxERSRA3n3UcZQmXVtLX21OwNwbogZGISCcoJ7jeHbilToE1wG+BZcBqYA3wbYKx3aX4d3e/oozfdQ5BYH0fcJS7/wnAzPYFbgc+ama3uPuPyjimiIgUUUqAoSzh0oqKdQ/XAyMRkfZXTrbwh4Et9aqIu/+7u3/K3a9x9z/W6/eErdafCn88IwqswzpsAs4Lf/znetVBRKRTFQswUmbKEi4tKZqaqzuTjt2+ees2ZQ8XEWlz5QTXPwQON7Np9arMBHkTQSv8o+7+i5jt1wLDwMFmprs7EZEa6R/I8sKW4cTtmXSKi0+Zp8BaWlZfbw9rL3gby0+dPy7IjhKbKcAWEWlf5XQL/xfgGGCFmX3I3X9fpzpV4kgzOxCYBvwJ+CVws7uPxuzbGy7vjjuQu282s3uB+eFL34IiIhWIsoI/NjjErpk0L2zdxvDI2DmBuwxGPZjXWtNvSbuIxmAPDo19mKTEZiIi7a3k4Nrdt5jZ24BfA/ea2UPAo0BcAOvufnSN6liK98Wsu8/M/sHd1+etnx0uHypwvIcJAuvZBfYREZEE+VnB84OMyCt3zXDH4qMmsmoiEyIpv4ASm4mItK9y5rl+OXAzcADBFFn7hK84nrC+1tYSJD+7hSBY3gV4PfBFYB7wMzN7vbvntj5H3dpfKHDcaIqxnWtbXRGRzlBqVnAFGtKuZnRnYrOHO7D34hXqrSEi0obK6Ra+lCBg3Qh8k2Dqq5rNc10Jd1+et+oFgm7rNwO3AYcA5wNn5exjUfFKf6+ZnU4w5zezZs2q9DAiIm2r1KBZGZSlXRXLHp4dHOL8G4LOdQqwRUTaQznB9fEE80Yf4u7P1qk+NeHuW81sCfAj4O15m58Ll4USs0Xbnovb6O6XA5cDLFiwYKJa6UVEWkL/QJYuM0a88OVRU25JO4sC5nOvWZf4WdAYbBGR9lJOtvCdgV81e2CdY0O4zP/GejBc7lWg7J55+4qISAmisdbFAmtNuSWdoK+3h9EinwUNjRARaR/lBNe/o7XGIL8sXOZ3Xf9NuDw4rpCZTQVeF/44UId6iYi0rVLGWmvKLekkxYY+aGiEiEj7KCe4vhQ4wsz2q1dlauyUcJk/5davgSeBmWZ2WEy5k4E0cHdeIjQRESmiUCucEUy5pRZr6SSLFs4hk07FbtPQCBGR9lLOVFxXmNn+wM/N7DPASnd/tH5VK8zM5gMzgRvdfSRn/STg7PAFcEluOXcfMbNlwDLgG2Z2pLs/GZbdlyBxGwQZx0VEpAxJGZJ7ujXllnSm6EHSspUbyQ4OkQrzEaRTGhohItJuypmKK7ef3+XhuqTd3d3LSZaGmb0euCxn1WvD5b+Y2SdzDnxI+M+9gf8Cnjaz3xPMub0zMBeYQTD/9nnuvjLm110CHAacAGwys1sIWquPAaYAX3P3H5VTfxERCVrpPnHNWkZzhpmqdU46XV9vz5ggeumNG/j2L+/n2Nft0cBaiYhIrZUTACdG0lXuG9kFeGPM+n0T9l8HfBV4A0Fysl6C6bUeBb4LXOrua+IKhq3XfcCZwGnAQmCEYM7sy9z9BxXUX0Sko/UPZFl64wZGPfgScNBcviIxemd1MzzifOPnf+C6NVkeGxxihj4rIiItr5xu4eWMzy6bu/+cMoJyd38AOKeK3zcKfD18iYhIFaIs4VEyM2dHi7WCBZGx/vRsMHTiq7f8Yfs6zXstItL66howi4hIZ4jLEh7N4SsiO/QPZFlyY/znQp8ZEZHWVtPg2gJvN7PranlcERFpbklZwjWHr8hYxaar02dGRKR1lZV0LImZvRr4J+B9wCtrcUwREWkdSVnCNYevyFjFgmd9ZkREWlfFLddmNtXMPmBmvwA2AucRZOn+C8Gc2CIi0iEWLZxD/gQSyhIuMl6h4FmfGRGR1lZ2cG1mbzazfwceB74NvCXcdB3wDmCGu5+dVF5ERNpLMIb0d7jvyErZ053RHL4iMRYtnEMmnRq33oATe2ewbOVGZi9ewaFLV9E/kJ34CoqISMXM3YvvZLYHQZfv04D92HH/tBZ4BbCHu4//pugACxYs8NWrVze6GiIiDZGfJRyC1jcF1iLJ+geyLFu5cfsUXEfMeTnfv+sRdprUxZZto2P2nT41zQUnHKDPk4hIA5nZGndfUGy/xDHXZpYCTiAYS30skCIIqv8C/AD4rruvNbPbgT1qUmsREWkZ/QNZzr1mHSN5D2mjjMcKBkTi9fX2jPl8/OedDwKMC6wBntk8rCm6RERaRKGEZllgN4KAegS4Cfgu8CN3H56AuomISJOKWqzzA+uIMh6LlKZ/IMu/rNhQcB89sBIRaQ2FguvdAQceBf7B3X81MVUSEZFmV2w6IWU8FilNsc9SJDs4xOzFK5jRnWHRwjkKtEVEmlCh4PpRYGb4+oWZ3QpcAVzv7i9OQN1ERKSJ5I4TLZStQxmPRUpXTi8PJwiy1U1cRKQ5FcoWvhdwHEEW8GHgaOB7wBNm9m9mdsgE1E9ERBqsfyDL/It+yjlXryVbJLBOmSmZmUgZKunlEXUTFxGR5pIYXHtgpbufQjB/9TnAPcAuwIeAO8xsA7DvhNRUREQmVG5QPThUPNVGJp3i4lPmKbAWKUPc1FzpLmP61HTBcsprICLSfEqa59rdn3H3f3X3XuD1wGXAMwTTcu0OYGYrzew9ZvaSutVWREQmRJSwrJSgGtRiLVKpvt4elpw4l57uDEYwR/yyk+dxwQkHkEkn36Ypr4GISPMpaZ7r2IJmk4ETCea+PpogUHdgM9Dv7u+tVSWbmea5FpF2dOjSVWTLaBkz4IGlx9evQiIdpthnUPNfi4hMnFLnuS6p5TqOu2919x+6+0Jgb+BC4AHgJcC7Kj2uiIg0XrldTtWKJlJbxT6D0fzX/QPZCaqRiIgUU3FwncvdH3X3z7n7q4FjgO/X4rgiItIY5QTLyg4uUnulfAaV2ExEpLnUJLjO5e6r3P19tT6uiIhMjP6BLM+9uDV22/Spad5zyKwx40M11lqk9uISncVRYjMRkeZRaJ5rERHpMFEis6HhkTHrNb5TZGJFn7VobvkuM0Zi8uQ48Krzf8KIOz3dGRYtnKPPqYhIg1Sc0EwCSmgmIu0kKYlST3eGOxYf1YAaiQgkP/iKo4dhIiK1VWpCM7Vci4jIdkldTNX1VKSxcluyi2Xyj5Kd5ZYTEZH6q/mYaxERaU39A1nM4rcpG7hI4/X19nDH4qNI+JiOoWRnIiITT8G1iEgH6R/IcujSVcxevIJDl67aPo1P1OV0NGakkLKBizSXUh92ZQeHNFWXiMgEUrdwEZEOkT9mMzs4xPk3rGf1Q09z1V2PxCZLSpkpG7hIk1m0cE7J46/VPVxEZOKo5VpEpEMsW7lx3M340PAIV975cGxgDTDqrptykSbT19vDkhPn0hO2YBfqJq7u4SIiE0ct1yIiHaKSpGQaay3SnPp6e8Y8+OofyHLO1Wtj930s7B4eTes1Q1N2iYjUhVquRUQ6RLmBssZai7SOvt6e7S3Z+XbNpDn/hvVkB4dwdgwJ0XhsEZHaUnAtItIhFi2cw+RUaZd9jbUWaT2LFs4hk06NW//XF4djh4Sou7iISG0puBYR6QBRl9CtI6NF982kU1x8yjwF1iItJhqL3Z0ZO+ovbhYAUDZxEZFa05hrEZE21j+Q5cIf38vg0HDB/QxwoEdjMUVaWl9vD8tWbmRwaFtJ+yubuIhI7Si4FhFpU/lTb+VLmTHqruRGIm2mnOSFUfdwff5FRKqn4FpEpE3FTb2Va9SdB5YeP4E1EpGJMKM7Q7aMALuSmQRERGQ8jbkWEWlTxW6YNc2WSHtKSmyWRNcCEZHaUMu1iEgbyZ3LtsuMEY/PZKRptkTaV9TFO2ne61y6FoiI1I5arkVE2kQ0xjqayzYpsJ4+Na1ptkTaXKF5r1MWLI0dY66VNVxEpHrmCTdfUpoFCxb46tWrG10NEelQpbZUgzKBi3SauKSGmXSKkw7q4aq7Hhl3vZg+Nc0FJxyga4SISB4zW+PuC4rtp5ZrEZEWVWpLNezo+qmbZpHOEc173dOdwQgesC05cS63bngq9nrxzOZhzrl6Lb2f+6laskVEKqAx1yIiLapYNvBcmm5HpDP19faM+9x/vMhY7Gc2D2v+axGRCii4FhFpYrndvnPno+4fyJY11Q5ouh0RCZQyVdfQ8AjnXrOOj1+9dsy1R0REkim4FhFpUvnjJbODQ5x/w3pWP/Q0168pv8umptsREQim6sofix0n6joeXXtALdkiIoVozLWISJOK6/Y9NDzCVXc9UnJ38Iim2xGRSDQWuzuTLrlMNLRERESSKbgWEWlSSd24CyUuy5UyG5PESC1OIhLp6+1h7QVvY/mp80sOsjW0RESksKbpFm5mc4BjgYOBBcB+BFMwnuzu1xUp+y7gDOBAIAVsAL4LfMPdRwuUOxb4RPj7pgD3A1cBX3H3LdW+JxGRapQyLjJJJp1SQC0iRUUJz/oHspx7zbqCD++6zPh0/3pu3fDUuDwQIiLSXC3XZwDLgXcDcwgC66LM7FLg+wQB8u3AzQSB+deB68wslVDuU8CNwFHAb4AVwO7AF4Cfm9nUat6MiEi1Fi2cQ6qrpEsh6S5j+tS0WqpFpCJ9vT2MFukVM+LOlXc+vH36v2gstqbtEhEJNE3LNfBbYBmwGlgDfBs4vFABMzsJOBN4AjjM3TeF618B3Ar8PXAW8NW8cguApcBm4Ch3vytcP40gyD4M+CLw8Rq9NxGRsgRZwjcwMlpaF/BlJ89TMC0iVamkt0yUVRyU7ExExLzEsXsTzcx+ThBcJ3YLN7PVwEHA+939e3nbDgd+ThB49+R2Dzez64CTgAvc/XN55fYBNgHbgFe4+2Chei5YsMBXr15d3psTESkgP0t4MT3dGe5YfFSdayUi7a7ca0++LoNRD65J6i4uIu3EzNa4+4Ji+zVTt/CymNlMgsB6K3Bt/nZ3vw3IAnsAh+SUmwwcF/74/Zhy9wO/BiYDb695xUVEiojLEp5EWcBFpFaiLOI93RmMICliOaKONuouLiKdqmWDa6A3XN7r7kl9mO7O2xeC8dxTgafd/Y9llBMRmRDFMvJGN7waWy0itdbX28Mdi4/igaXHc/Ep88ikY1PXFKWpu0SkEzXTmOtyzQ6XDxXY5+G8fXP//TDJ4sqJiNRcMLZ6I9nBIVJmjLhvX+ZT928RmUjRQlDpuAAAIABJREFUg7tiWcSTZAeH6B/I6gGgiHSMVg6up4XLFwrs83y43LkG5bYzs9OB0wFmzZpVuJYiIgnyxzdGN69xN7Hq/i0ijRAFxpWOxT7/hvVjjiMi0s5auVt4NBCo3EeplZbbzt0vd/cF7r5gt912q/QwItLhSh1bPX1qWt2/RaRh8sdi93RneM8hs+jOpIuWVfdwEekkrdxy/Vy4nFZgn2jbcznrKi0nIlKxuO7fpZo6eZICaxFpqL7ennHXoS/0zR1zbUui7uEi0ilaObh+MFzuVWCfPfP2zf13of7cceVERMrWP5Dlwh/fy+DQ8PZ15Y5dLJbgTESkUXKD7kOXrkoMss+5ei2fuGatpuoSkbbWyt3CB8LlAWaWSdjn4Lx9ATYAQ8BLzexVCeXeEFNORKQs0Zjq3MC6EjO6ky5xIiLNY9HCOQWzi2uqLhFpdy0bXLv7I8BvCOajPjl/u5kdDswEniCYtzoqtxW4Mfzx3THl9gHeRDB/9oqaV1xEOkY581XDjoQQuZTITERaRTQ2uxQaiy0i7ahlg+vQknD5JTN7dbTSzHYHLgt/XOruo3nllhIkNDvPzN6QU24a8B2C/5fL3H2wbjUXkbbUP5Dl0KWrmL14RcExiLmmTk7x4NLjeWDp8Sw/df6YpEFKZCYiraSvt4eeEnvbRGOxRUTahXkF8xbWg5m9nh0BMcBrCabC2gQ8Ha1090Pyyl0GnAG8CPwMGAaOBnYB+oF3uvu4piMz+xTwJWAEWAUMAocDuwN3AUe5++Zi9V6wYIGvXr265PcpIu0lSubz2OAQu2bSvLB1G8Mj5V1XXzI5xRf/XkG0iLSH/GkGi5k+Nc0FJxww5hqYe22doTHaItJgZrbG3RcU3a+JgusjgFuL7efu43pOmtm7gI8Ac4EUwbjq7wDfiGm1zi13LHAusACYAtwP/AD4irtvKaXeCq5FOlNcorJqZNIptVKLSNuo5BrZZcG47O6YB5W6RopII7VccN2qFFyLdJ5yW2UiKTMuPmVe4rQ1Pd0Z7lh8VK2qKSLScKVM1VUqXSNFpFFKDa5bfcy1iMiEKzdRWWTUnb7ensSptTTlloi0m77eHu5YfBQPLj2+5LHYSXSNFJFmp+BaRKRMld7gRVNqJU2tpSm3RKSdFZuqqxhdI0Wk2Sm4FhEpUyU3eLlTasXdYGrKLRFpd9FUXd2ZdNllp6S7dI0Ukaan4FpEpEyffNt+sXNS50uZxU6pFd1gasotEek0fb09rL3gbSw/dX5ZQfbph+2ja6SIND0lNKuSEpqJtKekaWD6B7L8y09+x5PPbcEMXJltRUQqVmrCs3Pfuh97vnTq9n1TZoy405N3fdb0XSJSD8oWPkEUXIu0n7hs4Jl0ipMO6uH6Ndlx65ecOBdAN3UiIlU4dOmqgkG2AXF3rcWuz7oWi0i1FFxPEAXXIu0n6QYvainJp+lhRESqV+k0h5B8fY6mQFSALSLVKDW4njQRlRERaSVJ2cDjbtwK7S8iIqWLAuCoF1BXQsAcJ2m/EXfOv2H9mOOLiNSLgmsRkVA0Xq/c/jyaHkZEpDb6enu2B8GzF6+oyTGHhkdYtnIjoOE7IlJfCq5FRKi8O6Km0BIRqY8Z3Zmiic5KlR0cGnONj34GtWiLSO0ouBaRjpWbWbac7oe5lCxHRKQ+Fi2cM+6hZ1JSs1LkPzyNWrR1DReRWtE81yLStvoHshy6dBWzF6/g0KWr6B/Ijtl2/g3ryQ4O4SSP1yukpzujmzIRkTrp6+1hyYlz6enOYATX3EtOnc+DS4+np0bDcbKDQ2O+G0REqqFs4VVStnCR5pTUzXv61DTHH/hKrrrrkYoC6oimeBERaZxiQ3nKaeHW9VxEiik1W7harkWkLS1buTH2puuZzcNceefDJQXW6S4jnbJx66dPTetGTESkgaJW7e5Mety2TDpF99Tx65MMDY9w7jXr1IItIlXTmGsRaTv9A9mqk+BMn5rmghMOAJRdVkSkGUWZxXPzZ0TX6Y9fvbasY+VO2QW67otIZdQtvErqFi5SP3E3TMVucCrN+p2vpzvDHYuPquoYIiLSGIcuXVWzTOPqNi4ipXYLV3BdJQXXIvURFySnu4xpUyYxuHmYGd0Zjtx/N27d8BTZwSFSFWb7TmLAA0uPr9nxRERk4iQ9aJ2a7mJ41BkeKe/7Qg9cRTpbqcG1uoWLSNPpH8hy7jXrxgXLw6POM5uHgSDD65V3Prx9Wy0DawjmVxURkdYUtTLH9X5K+o4pJDs4xKf713PrhqfUXVxEEim4FpGmErU21DpYTsocG9eKkUmnWLRwTk1/v4iITKxoTHbceqDsIUS5D3Szg0Pbx2grwBaRiLKFi0hTScryXY1MOsUlp85n+anzx8yXuvzU+dz3+eNY9s55Y9ZrbJ2ISHuLso2nbPyMEKUaGh5h2cqNNayViLQ6tVyLyIRJSlCWu77WWSBSZmOC5aRWDAXTIiKdpdIW7FyP1Shpmoi0BwXXIjIh8pPLRF3qVj/0NNevyda8tRqU4VVERArLHZudmxyz1CSZpeTnqGTmCxFpTcoWXiVlCxcpTS2nRSkkuiHq0Q2MiIhUqNRpHbsMRp3E75y44+Q/+FXwLdL8lC1cRJpKpV3nUmb84xv33J6hdddMmhe2bhuXgEwt1CIiUivR98mFP76XwaHhxP1Gw6+i7OAQi65dx0X/fe+Y6SKvuuuRcS3gQ8MjnHvNuu0/x/Xqyq2DiLQOtVxXSS3XIuPFPYWPutyVK26+aT3lFxGRiZL7ndNVYnfxUmTSKaaku7ZPMZlL82qLNJdSW64VXFdJwbXIWEld4E46qIcf/s8jbBst75qjGwwREWkWsxevqHnizSQ93Rk9RBZpEuoWLiITrn8gy7nXrIvtAnfrhqfYY5edeHTwxZKPp/mmRUSkmczozkxI/hCD7b8nOzjEOVev5RPXrC04vltEGk/zXItITUQt1knd5bKDQ0UD63SXMX1qWvNNi4hIU1q0cA6ZdKruvyfumzR3fPc5V6+l93M/pX8gW/e6iEjp1C28SuoWLp0oGn9WybQlRvxNQ8qMi0+Zp2BaRESaWu53YDOYPjXNBSccoO9PkTrSmOsJouBaOk2p05OUQ9m+RUSkFZU6zeT0qWmOP/CVsdnDa0VBtkj9aMy1iADJmbWLZdxO2r5s5caaBNYpM0bdlahFRERa1qKFc8Y9cE53GdOmTNo+JVfud9yCvV5a8wfUkWc2DydO46VZNkQmhlquq6SWa6mVenzxFcrcff2a7Lj1UetxUuv01HQXm4dHq6pTJG6KLRERkVZT7vd3UvLPWskdZtU/kI2dqzv/AcCR++/GrRueUvAtkkDdwieIgmuphaQguNqu0qV2V8tX6vjpQrozaV7Yuo3hkfjjaIotERHpVKUOserOpHnJTpPIDg4l5iyJk/QgvVTRPQigFm8R1C1cpKXEdbUeGh5h2cqNVX2JPVZhspVqA+tMOsWF7zgAIPaJuabYEhGRThZ9t0eB664xD6Sj79L8IVtx36v5hoZHuPLOhyuu39DwCBf++F62bBvdfn+SHRxK7HYuIgG1XFdJLddSC7MXr4h9Gl1O1+m4bmmNzGaa2zKtsV4iIiKFlfNdWWqQXQ/53c71/S6dQN3CJ4iCa6mFpO7bPTlBcqGEZHFPvBtNY6pFRETqq97jt5OUkr9FpJ0ouJ4gCq6lFpK+HKemuxge9XHdxKoZR1VLmXSKKekuntk8/sm5xlSLiIjUXz2myKxGoe9/tXRLq1JwPUEUXEstuDvzLlrJ0NZRhkeb8zNpwK6ZNGaMmV4EqEsyNhERESlNo1qwC4mSo/bofkHagBKaiTSJUp7SPvSXzfz1xRF2zaR5tkHjpwp9IZfSCq0n0SIiIo0RfecmtWBn0qkJb9mO7iuyg0MsujYI/PPbD+KSt6p1W1qZWq6rpJbr1jRRF+64rlpxc0v+v3WPT0hSku5MekzmTyg+v7WeKouIiLSG6P4mOzg0ruU4KclpyoxR95Kn+aqHnu5Mwazpug+RRuuYbuFmdgXw/gK7bHT3/WPKdQFnAKcB+wMjwD3AZe5+Vam/X8F1a0nKrlnNhbtQoF7pPNP1UOqclXpiLCIi0n6KPUBv1D1LKfN3axy3NFonBtd3AH+I2eVxdz8/r0wKuAF4B/BX4BZgJ+DocPk1dz+7lN+v4Lp1FEv4Ue7UUYWmwZg+Nc0FJxzAx69e29AnwflPrfVlIyIi0rkK3d8Uuk8qlMB0oiw/dX5Jc36X2mCioFzK0YnB9WnufkWJZc4FvgLcBxzl7n8K1+8L3A68Auhz9x8VO5aC69ZR7IlsNHVUqV25i2XrbuQXkTJ1i4iISLkKdSuH+DHdcTOb1EvUeJFUl0ix+6CJGAZX7EGGAvvWouA6ef8U8BiwO3C4u/8ib/v7gSuAu939DcWOp+C6dcxevKJgK3LKjH98455cddcjDc+2GTe/9ZH778atG54a84XXrbFJIiIiMkGSgsK4oLyeuoxxydHyGSQOf0vKrF6rxolCwTsoa3orUnCdvP9bCFqnH3X3PWO2TwUGgTQw092zhY6n4Lp1NNP450LKvcDq6aeIiIg0m2aZfzu392FcwrQ41Q6rS7rn7OnOACRuU6/D5tWJU3EdaWYHAtOAPwG/BG5299G8/XrD5d1xB3H3zWZ2LzA/fBUMrqUxyg0o+weyvLBl2wTWsDJRd6dyLuJ9vT0KpkVERKSpRPcm+fdrSVnL62V41LcP0St1ZpbcacTOv2E9QFn3Wo8lvL+k9cW2Setop+D6fTHr7jOzf3D39TnrZofLhwoc62GCwHp2gX2kQfKfhOZe+GD8RRwKj8tppGj6C7U4i4iISLtJagCI6xZ90kE93LrhqcQpuRplaHiEc69ZBxQOsHMbfroSusbPKNByHW2T1tYO3cLPIZhG6xaCgHkX4PXAF4F5wJPA66Pu3WZ2OfAh4Ivu/umEY34feBfwf9x9SaHfr27h5Sm1xTkpocaR+++WOCbagEkpGzf+OCmpWC3HBBWrW5IoiZqIiIhIp6h2VpZGye1hmPseSnkYkDvm+hPXrB03ZjwaR96Tk2dHQ/6aR8eMuU5iZpOB24BDgEvd/axw/beADwJfcPfPJJQtGFyb2enA6QCzZs066KGHCjWCS6TULNz/b93jE3YhzaRTVbVo54+PLnd8kcbXiIiIiCRrxiC7kgzpF598ICcdtCejo85rP3sjI6NBl/VSKOFZ45UaXHdNRGUawd23AlFg/PacTc+Fy2kFikfbnovb6O6Xu/sCd1+w2267VVfRNtc/kOXQpauYvXgF516zblzQGY2DcYIuMlfe+fCEXTx7ujPbnyAmec8hs+jpzmDh/vk/51/o+np7WHLi3O0JK1JmAHRn0qRTNubYmXRqe7d1ERERERmvr7eHtRe8jeWnzqc7kx63PZNOMX3q+PX1tHl4tOTAOrr/2+8VuwCw6cnneXGb85IppY/OHRoeYdnKjeVXNEHu/fmhS1fRP6AUU7XSTmOu42wIl7mPeR4Ml3sVKBdlEX+wwD4SiuvaA4x7ytjo6a1yRYFtX29PYmKNnu4MX+grHHzHSRpfpKzeIiIiIpWJ7q+S7jvLza9Tbe/FUkVB+G8efoa5M3dl9UNPA/BszJDFQmqV8KxQ7qKJuC9t9/vhtu0WDmBmbwJ+BTzt7i8L13XsVFy1PpmbsZtOKVJmXHzKvIJdudX9RkRERKR1lJJQLD+RbFIDS3cmzZZtozUPvrszaTZv3cbWESdlUE6+tkJDCcu5xy80TVi9hyq28j13x4+5BjCzS4BzgJXufmy4LgU8BuwOHO7uv8gr837gCuBud39Dsd/RKsF10ljguKmfSk0y0awZuIuJSyLW7k/RRERERDrF7MUriItw8u8BCwV7ML4XZiNNn5rm+ANfya0bnhqT8Lc7IZlaboK06L62fyDLOVevjT1+oSS7tbpPbmRgX62OCK7NbD4wE7jR3Udy1k8CzgaWEYwrP9bdV+Zs/2S47T7gSHd/Mly/L/ALYA+gz91/VKwOrRJcJ53MkSjIhvjpEfKfKBU73kRImfGPb9yz7ARorfABFhEREZHKlBPEFQsc691TMwqSo2C4HtJdRjplbB4eTdwn6f64lq3NpT70aEadElz3Af8FPA38HngU2BmYC8wARoHz3f3LeeVSYbkTgL8STOOVBo4BpgBfc/ezS6lDMwfXudNZlaLQtFW5H7hCT71qKeq+DcUD/vwLY1LW8VbpeiIiIiIilalH9+Nyguyo+3kpUVYUWPYPZGOn6Joocb1ZoXiDWk8ZLdlquW5yZjYb+BjwBoIEZS8DnCDIvp1gCq41CWW7gDOB04D9CebKvge4zN1/UGodmjW4rnW3bQMuOXV+zZ7c5U7BFTc3YLHgudQPsbp7i4iIiHSeet0DFpvfOvcetpSenlFg2Qy9QnO7xJfbQFfKfXvcA4RWafjqiOC6GTRrcF3rD6hBSU/f4uSOESnU5UZBsIiIiIi0kkL3sMUau3IDy6Qu062ilB6nxx/4Sl772ZvYNhK06u+xyxSOee3uBWOEZqHgeoI0a3DdiA/o8lPnAyhIFhERERFhfEu3GQxuHh53n9wMLdfVKjTEFODl0ybz5+e38pEjX8Wlt/6R9x4yi+vWZFsie7iC6wnSrMF1sQ9oNS3RcVphrISIiIiISDOKa+UuJRFZrmjYZVJwm6ueCdSK2TWT5sWt20iluti8dXyrfjPGFaUG110TURmZeIsWziGTTsVuy6RTXHLqfJafOp+UWdW/K5NOsWjhnKqPIyIiIiLSifp6e1hy4lx6ujMYQYC57OR53Pf541h+6vwx65efOp8Hlx4/bv2yk+cx8Nm38eDS4yl0h7/81Pn831PmJ8YK9fbs0DBbRjw2sAZ4rIVb8Cc1ugJSH1FXiigZQZTmPy6jXzWJz5IyC4qIiIiISOn6enti76nLXQ8wozuTmJk7t8y516xjpMSezOW0jFdjRnemrsevJwXXbazQBy53HyjvgwUKqkVEREREmtWihXNiE4vl9jaN7uMLNbRF3cfzG+hqPTNRUh1bjYJrKemDFVFQLSIiIiLS3HJ7sRZKNFxOb9e4cudcvbam9W7GZGblUEKzKjVrQrNK5GYz7Ao/WPmaMcGAiIiIiIhMvGJJlLszaQAGh4p3JW/mOEMJzaRsfb093LH4KB5YejyjCQ9dWjnBgIiIiIiI1E6xJMoXvuMA1l7wtjHJ17ozadIpG7dvK3cHj6hbuMRKSoLQygkGRERERESkdkrtVp6fCyq3x2xSl/VWpG7hVWqnbuG54pIUNOuk7iIiIiIiIvVSardwtVxLrFKTIIiIiIiIiIiCaymglKm8RERERERERAnNRERERERERKqm4FpERERERESkSgquRURERERERKqk4FpERERERESkSgquRURERERERKqk4FpERERERESkSgquRURERERERKqk4FpERERERESkSgquRURERERERKqk4FpERERERESkSgquRURERERERKqk4FpERERERESkSgquRURERERERKqk4FpERERERESkSgquRURERERERKpk7t7oOrQ0M3sKeKjR9ZC6eznw50ZXQgSdi9I8dC5Ks9C5KM1A52F728vddyu2k4JrkRKY2Wp3X9DoeojoXJRmoXNRmoXORWkGOg8F1C1cREREREREpGoKrkVERERERESqpOBapDSXN7oCIiGdi9IsdC5Ks9C5KM1A56FozLWIiIiIiIhItdRyLSIiIiIiIlIlBdfS0cxslpldZmb3m9kWM3vKzH5iZm8tUi5jZp8ys7vNbNDMNpvZA2Z2rZkdOlH1l/ZRybloZjPN7GtmttHMhszsRTPbZGbfNLN9JrL+0hrMbI6ZfczMrjSzDWY2amZuZu8soey7zOx2M3vWzJ43s9Vm9hEzK3gvYWbHmtlPzezp8Fr5WzP7ZzPbqXbvTFrNRJ2LZtZlZm82sy+EZR41s61m9qfwGttXn3coraIR18W8Y5we/j43s69X926k0dQtXDqWmb0RuBGYDjwIDAAzgIMJHjyd5+5fjik3G/gp8GrgSeBOYAuwNzAf+Jy7f6H+70DaRSXnopn1AquAbuBRYE24aQHQAzwPLHT3X03AW5AWYWbLgY/FbDrZ3a8rUO5S4EzgReAWYBg4GtgZ+K+w/EhMuU8BXwJGgJ8DzwCHA7sRXDuPdvfNVbwlaVETdS6a2auBTeGPTwOrCc7DfQiusQBXAP/kuinuSBN9Xcw7xl7AemAaYMCl7n5WJe9DmoS766VXx72AKcAjgANfBVI5244kCEwceFNeuZcAfwi3fQ5I521/GbBfo9+fXq3zquJc/FW4/vLc8xBIA98Ot61r9PvTq7lewAeBLwOnAK8iCHgdeGeBMieF+zwO7Juz/hXAfeG2j8WUWwCMAi8Ab8xZPw24LSx3SaP/T/RqzGuizsXw2LcAx+ZeX8Nth+dcY09r9P+JXo15TeR1Me8YBvwsPAevCMt8vdH/H3pVeT41ugJ66dWIF/CP4UXsj/kBcrj9c+H2FXnrl4Tr/6PR70Gv9nhVci6GAbmHrz1iyszI2T610e9Rr+Z9lXgTuTrc530x2w7PucHsytt2XbjtszHl9iFozd4CdDf6/0Gvxr/qeS4W+b2fDsvd0uj/A72a4zVR5yJwRrjfR4ELFVy3x0tjrqVTRV3Bfu7uwzHbfxYu32pmuwCY2WTgQ+H6pXWun3SOss9FgqBkW/hviykTdW18ARiqSS2lI5nZTOAgYCtwbf52d78NyAJ7AIfklJsMHBf++P2YcvcDvwYmA2+vecWl7VR6LpZgIFzOrLaO0hlqcS6GQwy/DNwBaJx1G1FwLZ1qWrj8c8L2aH0aeF3474MIun0/4u6/CxOk/IuZ/ZuZXWRmb6pjfaV9lX0uhkH4LeH6i8wsHe0c/jsa8/9tDx+Pi1SoN1ze6+5JD2ruztsXYA4wFXja3f9YRjmRJJWei8XsGy4fr6hW0omqOhfNzIDvAJOA/6Xv6fYyqdEVEGmQJ8NlUkbl3PWzCca3zg1/3mRmVwDvzyvzWTO7HnhvgYutSL5KzkUIkqjcRNCb4jgzWx2uP5ggMdpXgUW1rap0oNnh8qEC+zyct2/uvx8mWVw5kSSVnouJzGwqcHb44/UV1ks6T7Xn4lnAEcBid99Yw3pJE1DLtXSqVeHy+LB7T74P5/w76or70nB5GPA+4CsEGcOnA39H0AXoJODSmtdW2lkl52LUrfbNBFnGZwJ94auHIJnKLxK6mYuUI+pZ8UKBfZ4PlzvXoJxIknqcU5cRBD/3ESSHFClFxeeimb2KIH/PGoL7SGkzCq6lI7n7KuAXQAb4qZkdZWY7m9l+ZvYt4Hh2jGkdDZfR52USQXfbRe7+R3cfdPcfEwQ2DrxfcwxLqSo8FzGzNwO/JXjA83fAywmmN+ojeOBzvZl9duLeibSpaEx/ud0WKy0nkqSm55SZfYagB9qzwCnuvqUWx5WOUNG5mNMdfDLB1G8Fp+mS1qRu4dLJTiboBvYWdoxfjXyNoIV6HsG8mADP5Wz/Vv7B3H21ma0hmH7mCOD+GtdX2ldZ56KZdQP9BFPDvTlsxY78yMzuBe4BPmNmV7n7JkQqE133phXYJ9qWe42stJxIkpqdU2b2CYKZGJ4HjnP3e6uvnnSQSs/Fswm+zz/n7vfUo2LSeAqupWO5+5NmdhhwDMF8wi8nGP/6I+A3wGC46/pw+WBO8QcSDvsAQXC9R63rK+2rgnPxeIJW6lV5gXV0vD+Y2V0ED3mOABRcS6UeDJd7Fdhnz7x9c/89q8xyIkkeDJflnotjmNlHgYsJZlL4W3f/dS0qJx3lwXBZ7rn49+HyrWZ2eN7+e0f7mNnrgOfd/W+rqKM0iIJr6Whhhsabw9d2YaAzjSAhRZRs4jc5u7wMeCrmkC8Pl8/HbBNJVOa5GAUszxY4ZBSQv7TAPiLFRNMUHWBmmYRkjQfn7QuwgSB4eamZvSohY/gbYsqJJKn0XNzOzD4C/CvwIvCOcMokkXJVey4Wml1mRvgq9P0uTUxjrkXiLQ6Xl0ZTJLh7FrgrXH90fgEzmw68Pvxxdf52kQqNOxeBx8LlQbnTcEXCdQeFPyb1shApyt0fIXiwOJlg+MIYYevLTOAJgnmro3JbCZLtAbw7ptw+BDeYW4EVNa+4tJ1Kz8Wc7R8mmE94C9Dn7j+ra4WlbVVxXTzC3S3uBVwU7nZpuK67/u9E6kHBtXQsM5sbTsORuy5jZl8DjgPWAcvzin0xXH7WzObnlJsCfAPYlSADpLqZSckqOBdvBDYTtGBfYmY75ZTbiaBlZk/gGWBlnasv7W9JuPySmb06WmlmuxNkWwZY6u6jeeWWEiT8Oc/M3pBTbhpBUp8u4DJ3H0SkNBWdi2b2oXD7FuBEd9d1UapV6XVR2pxp3nLpVOFc1e8kCIYfI+h6eyhBpuX1wEJ3fzym3DLgkwQtLncBfyHo3jiDYDquI5VASspRybloZu8Hvg2kwjJrCDKYHgS8kuAm8h/cvX9i3oW0AjN7PTtu/ABeSzBVzCZ2JG/E3Q/JK3cZcAZBd9qfAcMEPXh2IUiu9864zLdm9ingS8AIwbRzg8DhwO4E18+j3H1zjd6etJCJOhfDB+G/Ibg+bmBHD7R8f3b3T1b3rqQVTfR1MaEOFwIXELRcn1Xpe5HGU3AtHcvM+oAPEWRh3o2gJfB3wA+Bb4bdGpPK/j3wUaAXmEowHvbHBE8p48ZiiySq9FwMbwjOAf6GIKCG4AHPrcD/dff76lx1aTFmdgTB+VFQ2E0xv+y7gI8Acwke6mwgaIH+RqHWGTM7FjiXINnjFIKZFH4AfEXTH3WuiToXS/09wEPuvncJ+0mbacR1MeY4F6Lgui0ouBYRERERERGpksZci4iIiIiIiFRJwbWIiIiIiIhIlRRci4iIiIiIiFRJwbWIiIj2Pn9aAAAQOElEQVSIiIhIlRRci4iIiIiIiFRJwbWIiIiIiIhIlRRci4iIiIiIiFRJwbWISJsyswfNzPNeL5rZw2Z2jZkd3ug6SmXM7IMxf9v81+pG11Nqx8zSZrbRzDaZ2aSc9VPy/u7vL3KcNTn7fjNv2/7RdaLIMXJ/5x5VvKe9zWyLmV1Z6TFERJrJpOK7iIhIi1sJPBH+ezrQC5wMnGxmn3D3SxpWsyYX3vS/G3ivuzdjAPA48NOEbQ9MZEWk7j4G7Ae8y923FdjvNOA/4jaY2Vzg9XWoW0Xc/UEz+xZwppl93d3vbHSdRESqoeBaRKT9LXX3n0c/mFka+CpwBrDUzK5190cbVTmpyn3u/oFGV0Lqy8ymA58BNgI/LLDrauAwM5vt7nEPV04Ll3cDB9e2lhX7IvC/ga8Ab2lwXUREqqJu4SIiHcbdh4FzgeeAycDbGlsjESnin4BdgO+4uxfY7wrAgHFdw8Ou5O8GngR+Uoc6VsTdHwduAg41s4MaXR8RkWoouBYR6UDuPgT8PvzxFXH7WOBdZnazmf3FzLaa2UNm9m9mNiuhzLFm9hMze8rMhs3saTP7nZl928zmx+w/zcw+Y2b3mNkLZva8mQ2Y2WIzy8Tsf0w4zvNnZjY5LLsxHEv+pJn9p5nNTKjbyWb2XTO7z8wGwzKbzOzrZtaTt++rzcwJghGA/8wb1/qevP3nmtmVZvZo+P/0lJmtMLPYBxfhvm5m7zGz+WZ2nZn9ycxGzOysuDLVMrMnojGy4f/FL8L/Bzez/XP26wrr9bOcv/uDZvZNM9uzwPFPNrNfh3/Hp83sJjM7NDwn3Mxuytv/w3HjfnO2x5bL2b5X+LfbZGZDZvasmd2e/7fJ2f/O8HiHhK8VYT2HwnPuvQXeW1f4WVgZ/m23hH/rm83swzn7/Sr8HX0FjnVZuM/nkvbJ298IepmMAv9ZZPfrgOeB94flch0P7A5cCRTqVl4xM1tqxXMBbIgpGnVjP7Me9RIRmSjqFi4i0rl2DZd/yt9gQdfxa4G/AzYDa8L95gKnA+80s2PcfSCnzAeBbxEEAXcBDwHTgFkE3VF/B6zN2X93YBVwAPA0QetVF3AksIRgTPgx7v5MTN0nE4wlPwj4BXAf8CbgPcDfmNk8d382r8w1BIHHfcDNQAaYD3wEOMXM3uTufwz3/SvBDf/fAPsAtwP35xwr2g8zOxG4KqzTb8P67AkcB7zdzC5094ti3gPAYcC3gUeAW4GdgaGEfWvln4GzgDsJWjD3IvibYWaTgeuBvwVeIPi7PwkcSNB19yQzO9rd78k9oJl9FrgIcOAO4NGwzG3ApbV+A+FDi+sJzq/fAzcSnM+HEDwIOczdT08o/g5gEXAvwTm0d1jue2a2i7uPqa+ZTQH+CziWICj9NcH72wOYR3CORA8I/pXgPDwT6I+p984E5+g24N9KfLuvA14F/DZs5S3kBYLz/J+AIwjOqcgHwuUVBJ/relhDwnhvgs/q64CRmG23EJw77zAzK9I6LyLSvNxdL7300kuvNnwBDxLcsB4Rs+0Aghv8rcDMmO1fCcuuAmbkbftYuG0jkMpZ/zBBkPbGmOPNBF6Tt+6G8Di3ArvmrH8pQQDjwH/mlTkmXO8EAfzLc7Z1EwTvDpwXU4dTgUzeukkEgbwD/x1T5spw23sS/o97CLrXO3B23rajCQJlB45JOK4DFwJW5t/2g2HZn5VR5omwzIvAWxP2WR7uczPwypz1RjCUwAkeTnTlbHtj+HffAizMO96nc97nTXnbPhyu/2ZCXY5NKDcLeBYYJkjulbttb4IHHA78Q962O8P1o8C7E/4//wxMztv2b+G23wKvjjl/Tsj5OQ08Fv6OfWPe05nhsa4r4+/20bDM5Qnbp+T8H08jCPYd+I+cfXYj+Kyvzvu7fDPvWPtH50iROuX+zj1KeA/zCB5YbQOOS9jnd+HxDizns6CXXnrp1UwvdQsXEekgZjbdzI4jCGy7gI/5/2/vzmPtqqo4jn9/VAJBRCmDDKlAQSo4xSDIJKEWoRAFKkNERCgqIBiCkBBFQyuTIqCRBmoVKIPFAIIMgjJpmKwMMtoWEBAskxQKNJHQgl3+sfaxt6fn3vfuu6/z75O8nPfOufue4Z732nX22mvXiplJWo/s2ZwDHBgRL7Zuj4ifkz1+W7LweO31gdkRcW99vxHxfETMaNnHcGBfshfriGjpZY6I2WQvaQAHSdqo4VTmA2Mj4tWWdm8APyk/jmo4hisi0+Fb170LnET2yu8p6b0N++rkCDKguTMizq299+3A+eXHE9q0nwacEhED7akb1SH9tjE9ngzSbq2vlPRBMv34dTIw/X8vaaRzyB7GrVj4+h5LBt+TI+Lm2tueTgalg+kEcvzxGRFxeeuGiHiWDNohg9Iml0fElNq6C8nMhHXIbAYAyjX8OhkUjomIp2r7ezcibmj5+R2yF7tK5a6r0p7Pb9jWTnU8Mzq+asEx3AU8RWYZrFlWf5UM/Cf3c5+rdUrtpovsinINbySzMo6JiD+0een0svxUf9/bzGxZ47RwM7MV358XHX7JXLIHqR4MAXwOWI3sMXy1YTtkuu8eZAps9Z/l+4GdJU0mq5E/0iFo3IUMQO6JiH/UN0bEo5L+Bnya7Im7ovaSf0bE9Ho7oBrP2RSQI2lEOe4tyKC4esi8CjCETAF/rM0xN6nmCr+4zfaLgOPJCs6rRMT82vZrG9Z1o9NUXP9ps/6aNut3I1Pbb4iI19q85g4ysN6B7N2GBddgkanKIiIkTSGzAwbLXmV5VZvtU8le2m0lDYmIehry7+sNynE+QX7+rffObuR9cXvTfdrGJDL1/jBJ368e6Cjnlf8oMCMi/tTP94J8aAXQ7jNpcglwKjnl3mQyJXwuOXyhP/oa3z2EDNg7KmnwN5IZHmdGRKdU+Nll2VgDwsxseeDg2sxsxVfNcy1ynOguZFrnpZJ2qvfGkQEGwD6ll6qT9Vq+P4oMXA4rX29Iuo8Mwi6LiNax3VUBsU5zMT9NBtcbN2z7V5s2c8py9daVZQz5RLIXspO1+the19d5VOO01yDT1mfXtj/X5f7qBjIVV7t9Vp/7fv393EvRrA3LunbX4Nmujq5vm5blYw0Pjeo+wKJBaTf3ziZl2VSEq1FE/FvSlWTweRD5gAUG1msNC2ojzOn4qoVdQo6BHyvpEXL8+1UlK6Q/3ul0X5Vx6B2Da2V18t+WfV8BfK+PfVbn94F+HqOZ2TLHwbWZ2YqvPs/1hmTA/XFgiqTtaz3MQ8rycXJccyf3Vd9ExLTSMzyaLEq2E9nLuTswXtKYlnTkKirqFMR1ipy67e09ngysXyjfTwVeiYi5AOUhwLZ97LPTMQ40rXtxFy/rZp/V5z6dzELo5IGy7PZ6dWORoWuSVmlZfzk57rqTpqrYvWQK9NcEMvg8GrhI0gbAGLKg3qVdvtcbZdnvBz8RMVPS7WTPe1WVvL8p4YNlIvm7fzdwaD+GPlTn11TA0MxsueDg2sxsJRMRL0k6EHgU2I6cbqo1pXdmWT7cba9oRMwDri9fSBpK9qB9mxzXWk3hVY3zHl5/jxableUL3RxDGweU5Tciomlqpy0G+L7Pk5Wch5Mp03XVObzFgiBpWVV97g/293OPiPmSXiZTqTel+bPatE3zeWW5Zpvtm9RXlP29SBbIOzkWVHdfXKpe/hHdNIqI+8oDm+0kbUc+cFoVuDAiuumBhqzWDjkevBsXA58np+DqNHxg0Ek6iSwS9ySwT/UQqw/V+b3S8VVmZsswFzQzM1sJRcTjLEhPHV9SOCu3kj1+u0vqNk26vp/Z5LRHAQyTtHbZdGdZt5OkzevtJH2MTAn/LzkNVq+GluXM+oZS4G3t+vqiCgDbPYyuAuqvtdk+tizv7HFs9ZJwC3m9R5exsv1VXYOD6xtK2vhX2rSrAvGPtNm+V5v11Rj/A9psH0y3kddk16b7tA8TyvJYsvAddJ8SDvBgWW7dZbtryIcDrwG/ahh7vlhIOgg4DZhF1nXobyp6dX4PdnyVmdkyzMG1mdnK63RyGqnNgUOqlaU6+C/IgPR6SVvWG0oaKumIUlkcSe+TdJykdRv28wUyffh1yrjKiHgGuI5MRZ7UGsSXAHxSafOberXyAarGzH5LLQN1JX2YzgFPFQBu1Wb7L8lU310lHd26QdJIcg5tgHO6PuIlLCJmkvOUrwtcW67NQiStI+lISa29qBPIByWHS9qt1uS75PCDJlPJHv1tJI1p2YckfYe8b5qcSRZrG1/uwSGtG0v7Hcv84z0plfQvIh+u/K5UuW/d13sktTvOK8kq9AeTY/PviohuiuVVqrmqd+imUUS8HRGbRsS6ETFuAPvtmqTPkunnbwN7l9/z/rQbSs4+8CqDX13ezGyJcVq4mdlKKiJmSTqbTNv+gaTLytRUkNMdbQjsB0yT9DBZsGoNYBgZbK5KzoM9i6wu/jPgbEmPklMBzSfTrbchg68Ta71nR5L/oR4FPCPpDjKgHkkWNXqI7PUbDGeQ40+PAXYr57MOWdztbjII+kxDu+vIys8nSPokGWwHcEFE/DUiXpB0KFmF+TxJR5LTa21MVjkXMD4ibhuk81jcjiOL3u0LTO/wud9MKRQWEVMlnQqcDNwi6W4yXf4TZK/0BBqmxYqIOZJ+RFa1vrq0m1XafQg4i8x6qLd7ugTOV5IPYcZJmkYWi9uYvOc2IIt6tauM3u012Yy8fx6X9BfyPtiAfHCwFrUCeuU450maRF4XgPMGsvOImCHpSWBrSRsN0sOmxeXH5N+CJ4CjJB3V8JqXIqJe3GwU+btyfQ/T0pmZLXXuuTYzW7n9lAwshwOHVisjYl5E7E8GWTeRY1z3BbYn/+34dfn52dLkTbJ409VkILYH8EUy8JgCbB8RF7TuOCJeKe83jhwTuic5NvU5cu7pnSNiUIobRcTdZV83kYH73uQ44VPLfpsKXxERDwBfJgt47QwcThZG26LlNdeQxdCmkL2++5NTLv0RGB0RPxyMc1gSImJuRIwBvkSmXw9j4c/9MmAfFoyZr9qNI6/T/WQ6/17kZzqSvObt9ncaOR/038mHGyPJLIMdyAc37drdQqYRn0n2du5YjmsYOR/0ieRDo55FxFvkfTkWuIcM/g8gx2E/RPv5tGHBdGUv01ugfz4ZfB7S1wuXsiqLYAT596Tpa0xDu+pvz0DS5s3MlhnyA0IzMzNbXCSNJgP1myNi9NI+niVJ0kRyirpTeknNlvR+8qHTy8BWK1LvrqSNyHO7NyJ2XtrHY2bWC/dcm5mZmQ2yMj77MHL88cRe3isi3iSzLEaQGQIrkpPIHu9FhgCYmS1vHFybmZmZDRJJ50iaQs4RvzpwVkS8PAhvfS45lvmUWnX/5ZakTYBvkoULpy7t4zEz69UK8cfZzMzMbBlxMLA+WfTsNAZv7Pc7tJ+2bLkUEc+RBdDMzFYIHnNtZmZmZmZm1iOnhZuZmZmZmZn1yMG1mZmZmZmZWY8cXJuZmZmZmZn1yMG1mZmZmZmZWY8cXJuZmZmZmZn1yMG1mZmZmZmZWY/+BzKfEBIRSqpHAAAAAElFTkSuQmCC\n", - "text/plain": [ - "" - ] - }, - "metadata": {}, - "output_type": "display_data" - } - ], - "source": [ - "expt_cfg={\"reps\":500, \"relax_delay\":10,\n", - " \"start\":95, \"step\":0.025, \"expts\":400\n", - " }\n", - "config={**hw_cfg,**readout_cfg,**qubit_cfg,**expt_cfg} #combine configs\n", - "\n", - "fpts=expt_cfg[\"start\"] + expt_cfg[\"step\"]*np.arange(expt_cfg[\"expts\"])\n", - "\n", - "amps=[]\n", - "for f in tqdm(fpts):\n", - " config[\"frequency\"]=f\n", - "\n", - " rspec=SingleToneSpectroscopyProgram(soccfg, config)\n", - " avgi,avgq=rspec.acquire(soc, load_pulses=True)\n", - " amp=np.abs(avgi[0][0]+1j*avgq[0][0])\n", - " amps.append(amp)\n", - "amps=np.array(amps)\n", - "\n", - "plt.subplot(111,title=\"Resonator Spectroscopy\", xlabel=\"Resonator Frequency (MHz)\", ylabel=\"Amp. (adc level)\")\n", - "plt.plot(fpts, amps,'o-')\n", - "max_freq=fpts[np.argmax(amps)]\n", - "plt.show()" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "# Single Shot\n", - "\n", - "Measures the single shot readout fidelity of the system. We acquire single shot (I, Q) readout values by first preparing the qubit in its ground (blue dots) a certain number of times (in the below demo we take 5000 shots) and then preparing the qubit in its excited state (red dots) the same number of times. We then extract two parameters which are used to optimize the associated readout fidelity: the rotation angle of the IQ blobs and the threshold that classifies the two qubit states (ground and excited). We store these two parameters here readout_cfg[\"res_phase\"] and readout_cfg[\"threshold\"] .\n", - "\n", - "Note that this experiment already assumes that you have found your qubit frequency and $\\pi$ pulse amplitude. It is placed towards the top of this demo notebook because every time you reset the QICK firmware the single shot angle and threshold changes. So, this experiment is used to calibrate any experiment below that uses single shot data (such as the Active Reset experiment)." - ] - }, - { - "cell_type": "code", - "execution_count": 7, - "metadata": { - "ExecuteTime": { - "end_time": "2021-09-30T07:30:40.750629Z", - "start_time": "2021-09-30T07:30:40.352047Z" - } - }, - "outputs": [], - "source": [ - "class SingleShotProgram(RAveragerProgram):\n", - " def initialize(self):\n", - " cfg=self.cfg\n", - " \n", - " self.declare_gen(ch=cfg[\"res_ch\"], nqz=1) #Readout\n", - " self.declare_gen(ch=cfg[\"qubit_ch\"], nqz=2) #Qubit\n", - " for ch in [0,1]: #configure the readout lengths and downconversion frequencies\n", - " self.declare_readout(ch=ch, length=cfg[\"readout_length\"],\n", - " freq=cfg[\"f_res\"], gen_ch=cfg[\"res_ch\"])\n", - "\n", - " cfg[\"start\"]=0\n", - " cfg[\"step\"]=cfg[\"pi_gain\"]\n", - " cfg[\"reps\"]=cfg[\"shots\"]\n", - " cfg[\"expts\"]=2\n", - " \n", - " self.q_rp=self.ch_page(self.cfg[\"qubit_ch\"]) # get register page for qubit_ch\n", - " self.r_gain=self.sreg(cfg[\"qubit_ch\"], \"gain\") # get frequency register for qubit_ch \n", - " \n", - " f_res=self.freq2reg(cfg[\"f_res\"], gen_ch=cfg[\"res_ch\"], ro_ch=0) # conver f_res to dac register value\n", - " f_ge=self.freq2reg(cfg[\"f_ge\"], gen_ch=cfg[\"qubit_ch\"])\n", - " \n", - " # add qubit and readout pulses to respective channels\n", - " self.add_gauss(ch=cfg[\"qubit_ch\"], name=\"qubit\", sigma=cfg[\"sigma\"], length=cfg[\"sigma\"]*4)\n", - " self.set_pulse_registers(ch=cfg[\"qubit_ch\"], style=\"arb\", freq=f_ge, phase=0, gain=cfg[\"start\"], \n", - " waveform=\"qubit\")\n", - " self.set_pulse_registers(ch=cfg[\"res_ch\"], style=\"const\", freq=f_res, phase=cfg[\"res_phase\"], gain=cfg[\"res_gain\"], \n", - " length=cfg[\"readout_length\"])\n", - "\n", - " self.sync_all(self.us2cycles(500))\n", - " \n", - " def body(self):\n", - " self.pulse(ch=self.cfg[\"qubit_ch\"]) #play probe pulse\n", - " self.sync_all(self.us2cycles(0.05)) # align channels and wait 50ns\n", - "\n", - " #trigger measurement, play measurement pulse, wait for qubit to relax\n", - " self.measure(pulse_ch=self.cfg[\"res_ch\"], \n", - " adcs=[0,1],\n", - " adc_trig_offset=self.cfg[\"adc_trig_offset\"],\n", - " wait=True,\n", - " syncdelay=self.us2cycles(self.cfg[\"relax_delay\"]))\n", - " \n", - " def update(self):\n", - " self.mathi(self.q_rp, self.r_gain, self.r_gain, '+', self.cfg[\"step\"]) # update frequency list index\n", - " \n", - " def acquire(self,soc, load_pulses=True, progress=False, debug=False):\n", - " super().acquire(soc, load_pulses=load_pulses, progress=progress, debug=debug)\n", - " return self.collect_shots()\n", - " \n", - " def collect_shots(self):\n", - " shots_i0=self.di_buf[0].reshape((self.cfg[\"expts\"],self.cfg[\"reps\"]))/self.cfg['readout_length']\n", - " shots_q0=self.dq_buf[0].reshape((self.cfg[\"expts\"],self.cfg[\"reps\"]))/self.cfg['readout_length']\n", - " shots_i1=self.di_buf[1].reshape((self.cfg[\"expts\"],self.cfg[\"reps\"]))/self.cfg['readout_length']\n", - " shots_q1=self.dq_buf[1].reshape((self.cfg[\"expts\"],self.cfg[\"reps\"]))/self.cfg['readout_length']\n", - " return shots_i0,shots_q0,shots_i1,shots_q1\n", - " \n", - " def analyze(self, shots_i, shots_q):\n", - " plt.subplot(111, xlabel='I', ylabel='Q', title='Single Shot Histogram')\n", - " plt.plot(shots_i[0],shots_q[0],'.',label='g')\n", - " plt.plot(shots_i[1],shots_q[1],'.',label='e')\n", - " plt.legend()\n", - " plt.gca().set_aspect('equal', 'datalim')" - ] - }, - { - "cell_type": "code", - "execution_count": 8, - "metadata": { - "ExecuteTime": { - "end_time": "2021-09-30T07:30:53.697413Z", - "start_time": "2021-09-30T07:30:40.757794Z" - } - }, - "outputs": [ - { - "data": { - "application/vnd.jupyter.widget-view+json": { - "model_id": "c54ed8e3d35549e4a9fbbab13ee0780e", - "version_major": 2, - "version_minor": 0 - }, - "text/plain": [ - "HBox(children=(IntProgress(value=0, max=10000), HTML(value='')))" - ] - }, - "metadata": {}, - "output_type": "display_data" - }, - { - "name": "stdout", - "output_type": "stream", - "text": [ - "\n" - ] - }, - { - "data": { - "image/png": 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Is8ZQYtYXnQJVfUNEinHx13rh4hTdFqr2GM4F6AfAlnT6FZGDcEGbs3CKjKNVdUfyVkn7Ox2nJFHgGFV9OnB6M3CliCzHLaQfhLMWujTQfhROwVOPC2FR15xxeMrIOV6J4g6cTuNcVd3hWfssxv3N3oazROuDix93IC6A/1kJ+sp4zPLGaE/81dB0FBMQy+wUadkBDe45qUgWzjzVxN3/INiWxnX8Os3S6Hom7rfjns//cGb9++Besj29foNB25qrfG3Ox0TQHLJ74OdUzyWd52YYhuFziL+qiZN33yRmNTIWWCCNU1QEZW4qmRNUgjR39e2PONlcgwvWfjjug6ovsaCbv/LqtmSRrDmyOpiRypfVJqcNo+vQ0v/r5iqUw9nu2hzPstsPFzAtlDzjNG/7rKqmWoiNpIMCFvv39hdgHC4o8EqcoqYceBEXRP94XNwfcJYmqe5lPC7bYgEu9sthqropeauUzPS2/wwpbhpQ1b8Tc6n6cej0Td54fpfCy6HZiMipOI+Hv3hjARcnZwSwGvi5qm5S1XeAU73zPxKRliysdCimvDHaEz9VXe+ktWL4/1hNih7fyvgT/e5Ja8XXaW4K2rNxiqb3gf1U9R5V/a+qfqKq5aq6jdaxlgu+0L+Urnlogvapnks6z80wDKMRntx7GZea23ftOQSYFqoalLlNkUlNltWe6b7vznS2qp6vqv+nqh+o6mZV3ebJ6mQWn+niy9o/NcGM/8qI9ianDaPr0NL/6+Ac7qwmyJYXEvTX1viuU4PxYoh5LlyHeMfvjWqUJrNIHIsondLcFNwAqOr7qvpzVR2rqoWq2lNV91fVe3Hf6F/zqi5L1o+I7I2zBu2Jc6P9jqq2yEpKRHYFRnq7qVLF++PrL/EZfod727OCbsUB9+Kg29+8wLkvpTnG3jjLoO3Ex9n0M//+MxgrTlVX4KzH8nBuYJ0SU94Y7ckab1uYpu+sn0a7WRr1VmKtt+0tIrslqiQig4gpm9YmqpcC3wT/0SSm/F9uZt9Bgs/zawlrJaaMmAlnqvSFezWjf8MwjAa8yddZxFKszvXMon02B87tTXL8gL6fNsdlinhXqYeS1GtNWd0cOQ2xd1E/EemXpJ7JacPoPKz1ts2df31BbA7XXNnSbnhxffzEGqcFtoKT+1EB7LsChxFTwCWM7ykiI3DZXfvh5udHelYmLSVoaZXMgwHi9QlNjj3UAq7GpbMvVdWgdZL/votyF/40VKfTYcoboz0JRio/PllFEfkKsdgxkdmQ2ongSsOJSepNTtAGYu5ipIhy7rsmJasTXnEO418rWR9vAhu8n3+Uor9GeB9S//Z2jxGRSGsgL+uJxbsxDKPFqOqnuMCD4FyUpgXO1QP/8XaPSyKTCoBjvN2oVeR05GfQhTTRdYYTC+oeRTCgcrJrPelt9xSR/ZLUS0TwHr+XpN4JzejbMIyOwf+//pKXgKIRIpJHTNbF4c3h/uXtntgBwVvTlX9BfOub74lIH2LuLw83UwkPdGjA4nS4yNt+QOxdEIe3cPwvYHdcGIijVfX1Vrr+p8TCVqSyUvED5W8lPj7PiTgFYaJyXKDu7YHjq1MNznMTOxMX5+6m0OlKb9s/omn/UJ1OhylvjPbk7zg/TIBLRWT3qEreiqo/SVfg7nYYWySq+iouQjrA5VFjFpHBxFK1vqYuTXmQzwM/R96zh7/KeqREpNwTkUNJrWzxr5XwOt6L2xd0h4rI+YnqetfNj7CUut/bDgYujmiTTWNhahiG0RJuJuZGOzOkDA+a1l9GNPOIrbb9PuJ8SvlJvOXiceGT3kfT3SSfX6X7TngwUPdez4w9ISISl9lKVV8iFtR0VpT1jYgcRorFFMMwMoo/EvuovjEUB8bncqI/XH1u9Lb9gN8nUniDyzAazvTUQr4I/JxM/gVZjLMqKQDuJOaO0xKXqYzFy/D0HW/3Qo3IpOW5Jz2JexbVwPdU9d/hes1FVauILdR+R0S+nWCsRxHLgPaPkJvSSlV9I1EhPqj2xsC5KpLg/c3fiXvPnqONM0z6iQmODP5/iMiXgSGhOp0OU94Y7YYXeOwcb3cg8IqInC0iY0Skt4jsISIn4Cx0/JgC16tqR6eb/hnODHAA8G8RmSoiu4nIQBGZihNuuwJ1wLkR7V8nZkY4V0SGekHSckIfHw972zHA4yJygIj0E5c6fBYu7eNKkvOqtz1QRKaISF/vOjmhF/zNxCyhbhSRv4jIUd599RaR4SJyjIjcAqwDpoSu8+dA+yvFpTbfy7ve/rgMAd+h+S5khmEYcajqVmJK4dHADwOn/wz8n/fzHBG5U0S+6smkfUTkHmIrmUtUNcoM3ZefJ4jI4SLSKyA/fbPxl4llXLlNRM4VkREi0l9EJuEsRQ8ledard4nFnbhUREZ7SvK4d4KqluMU9opzkfiviJwvInuLSB8RGSAiE8WlmX0aeCniWr5yfg/geRE5TkR2FZeW9he4YNBrk4zVMIwMQlU/JLbAeQywRET282TdOBH5DS7Dz/tJ+ngx0McPgZdEpFhEhnlzwMEicrA391yBiyvSWuMvx8lAgJ+LyFdEpNCXtQnaVBBzU/Xl/tuegrrTISIFIvK2iFwiIvuLyO7eN8V3ROQvxJ7371S1kVuYuDTuf8e5CdfjEpy8KE0MrCwiV0oszsyBEVXm4d4/gktpfkngm21PEbkc+KtXtxq4qiXPpQmcgcvCOF+js7j9xRvPMOBu7x09Hqf4BHhZmxnkOiNQVStW2rUA03Hmapqi3ARkR7Q/za+T4jr3e/Weacq5BH1NBaqSjLUSmJKk/YIE7dYG6mThIsUnusZ6XOpYf/+0iOsMxK1qRLWfE6rbEzdxT/V7UOBnEdcagHupJ2pzVVOfsxUrVna+EpTpwMEp6vYMyLg3AQmc64NTKieTZf8EeiTo+6u4CV9Uu1MC9Q4l+TvsGlxqUgVWJ7jW9Qna1kbU/T5u1TmVnN6U4FoX4ib4UW0+wMVW8PcP7Oi/BytWukJpilyLaHt4oO3giPM5OIV1Mjk3I5FM8frIwn2c16UhWx6OaP+hd+7yiHOp5N/ZSa7V6H69NhNC9Uo6+nfcgr+NghTPuw6XsVAStD88RfuU75XQ7ymh7McpSpJ9/yguePMJzXgOowJ9NPo7StCmH7G4TQOT1Ds/yVi/1tF/Ay0pZnljtDuq+iAuhds83Erh5zgT0K04M7Y7gX3UZfFIJxV4m6OqD+GCv/kp/Sq8shK4FRirqouSdPEjnBnr67gVV424Rj1ukn4+zlWryqu7AvcxsI+qJrW8UdWNuCjrf8BNyquT1N2qqt/DTdwfwAWU3o7zR/4UZ1FU6l33NxHtN+FepnNwpo9VuN/lU8D3VTWR64JhGEazUGd945v8j8PJTP/cZuAg3EfTv3ByrAb4BLdKeTJwhLqV36i+/+u1/ysuLljYFNuv9xTwDWBh4BobgMeA76rqpWncykzg5zhLnq1EvBMC1/srzjT+Mpxy6jPcO3M7bgX7IeAkYplBwu1/DRyMs978HCerV+Oe43hilkSGYXQC1FmyT8alZn4RN1csx80xLwCOIoH8CvRRr6pX4Kw3bgH+h1MS13nbN3BxSA4Dilt5/Hfg4pY9i3OFTRnkVlWXe2MEJ/8ebM0xtTPVOKv+v+JccbcTk+d3AhNU9SL1tBAdiar+DvgS7n3xOu59VYdTnizHfZ/srS71eXtwPW6h5grvmycSVb0J915chnvnleHe0ftr68UF6hAkA/4uDMMwDMMwDMMwDCMSEXkJpzhfoqoWq8vYKTHLG8MwDMMwDMMwDCMjEZG9cIob6KKBig0jHUx5YxiGYRiGYRiGYWQq53nbj4GlHTkQw+hI2jI/vWEYhmEYhmEYhmE0CS/7VCFwIi6jEsCNXswfw9gpsZg3hmEYhmEYhmEYRkYgIqOAVaHDbwHjVXVHBwzJMDICU960kH79+umwYcM6ehiGYXQxXn311c9UddeOHsfOjsl4wzBaG5PvmYHJ98ylqqqKt956C4Dc3Fx69uzJoEGDyM3N7eCRGUZy2lq+m9tUCxk2bBjLly/v6GEYhtHFEBFL35sBmIw3DKO1MfmeGZh8NwyjtWlr+W4Biw3DMAzDMAzDMAzDMDIYU94YhmEYhmEYhmEYhmFkMKa8MQzDMAzDMAzDMAzDyGBMeWMYhmEYhmEYhmEYhpHBmPLGMAzDMAzDMAzDMAwjgzHljWEkoKwMxo1zW8MwDMMwDMMwDMPoKEx5YxgJWLoUVqyAJ57o6JEYhmEYhmEYhmEYOzOmvDEMD9/SZvJk6N4dTj3VHZ8+3e0XF6ffh1nrGIZhRGNy0jAMwzAMo+mY8sYwPHxLmwMOgCFDIDfXHc/NhaFDYd681H0sWuT6WLy4bcdqGIaRiaSjmDGrxhbSHO2XacwMwzCazZw5HT0Cw3DkdPQADKOjKS6GJUtgxw63f/HFkJ0N1dVQVOSOz50LI0e6ee83vuHqvfwy9OoV30dlpds/4ww47zw47jhYsKD97yldamtr+eKLLygrK6O2trajh9PlyM7OprCwkJ49e9KjRw9EpKOHZBhtSlAxM3Vq/LmwrJ0+HX7608yXkxlHsofcmm0MwzAMw8goTHljdBnWrYPRo2HVKmc5ky6lpfDGG7B2LdTWOksbv8yZ4yxuFi1y7lRLl8LKla5dcA5cXg4VFaDq9uvr3X55uVP47L8//Oc/MWVPJlBfX8/69evJz89nyJAh5OXlmXKhFVFV6urq2LZtG5999hmVlZX079/fnrHRJUlHMRMla9O1ajRonvbLNGaGYRiG0WUwtymjy3Dddc5a5oYbmtZu112dkqWmxlna1NTApZfC6tVw4YVOWbNlC+TkwMknx9oVF7tjxcVw002w++7x/Q4aBDffnLkuAps3byYnJ4fddtuN/Px8Uyq0MiJCTk4OvXv3ZujQoWzfvp3y8vKOHpZhtAmlpandTUeNcvWCsta3ajTSIJ2H3Bptgpi7lWEYhmFkDKa8MTo9w4aBCNxxh9u/7Ta3P2xY4jbB+ejSpfDhh25OO3eu+6h4/XUYMMDVHTAAbr8d9tgjvg8RGD7czYFHjYpZ++TluW1VFXz1q80LfNwebNu2jd69e5vSph3Izs6mb9++bN26taOHYhhtQrqKmYUL3Xlf1i5a1DHj7ZQ0R/vVUo1Zpq4+GIZhGMZOiClvjE7PPffEFhV98vLg3nsTt/HnowMGxJQr1dUwezYccgiUlMTXHzXKWZkHycqCa66JzYELC6FHD7j6arcdM6ZlC55tTVVVFYWFhR09jJ2G7t27U1FR0dHDMIw2I5FiJqgsLylx1oy+VWNY1hopaI72qzltioubn3bRMAzDMIw2wWLeGJ2eww6Dww+Hv/0tduzcc+HQQxvXDbv/+1twCp+hQ+FXv4pflPTbhL+76+tjsXDAKXKGDHEKoVNOgfXrXWyHqVMbBz7OBOrr68nKMv1te5GdnU1dXV1HD8Mw2oySEvjNb+JlICSOlTtgQMzC0UiTRA+5uW0SBWWzAEWGYezkhDNMzZljWaeMjse+3IxOjb846CtufA+gO++Mrh92/8/x1Jd5ec6afOtW6Ncvuo3vDlVQ4KxqbrsNli2LhQKYODHe1WrChLZzEWitMATmMtV+2LM2ujphGXjjjZ3HeKPThHaJetG0pE0itygLUGQYhmEYGYcpb4xOTZRiZcQI+OUvoyfi/ny0qsrt+9mxa2td+fDDxHPYujo3h62thauugt694f33k4cCaCsXAQtDYBhGptPSWLntScbI1PbSIqXjFmUBigzDMAwjozDljdGp8TNF1dfHFgevuw4GDnQT8b32ajwH9uejQY+h+vrYz1Fz2PnzXZ2ZM511z0knpbea3JxF0mRYGALDMDoLncF4I+NkantpkdLRrFmAIsMwDMPIKEx5Y3RqwpmifMXKmWe68xs2OKVJcCJeUgLXXx9T2ARdp8D1tdtusHgxrFvnju27r6s/ciQ895xLA+6HL6mrg8GDQ6vJbbR62plWsg3DMDLdeCNjZGp7a5GSadb899eYMa27+mAYhmEYRosw5Y3RKQnPc6urYdYsp2Cpq4u3pNmxAx5+2LUpLob99oOzz46d912nqqud8qe62s1fa2pc0OOsLDf0JqNJAAAgAElEQVTHBTefPuwwpxRSdYofVTjqqNBqsrd6WjLuCcrKWk+X0xlWsg3D2LnpTNmlMkamhrRImpvL6pqhlF/chlqkRJq1jPEhMwzDMAwjSMYqb0TkahFRr1yUpF6xiDwvImUisk1ElovIOSKS9N5E5CgReVJEvhCRChF5U0QuE5H81r8bo7UJr5bm5UGfPjFrmDAjRriV1NJSZzWTCFXXxz/+4fbXrHHHfAVPfT1UVroJPsSO33KLUyb9e1gxWtSd2pOdVunqj6ZT2L87T+1WnNZcOB0lT6avZBuGsXMRllvBb//Wdh1tC9KRqW0eiiakRdLqGmZWz+Xxt9tQixTWrJWVZZgPmWEYhmEYQTJSeSMiE4GLAU1R73ZgPjABeB74JzAGuA1YLCLZCdpdDPwNOBR4DVgK9AeuBJ4RkcLWuROjNQlOnoPz3Jwcp1D56KPEbd97D664wrWrrm7+GOrrnTInjJ9mfPA9pazVIezAaZWqyeXd6qFcVOlWT6dNSz4XTmfBs6TEZbm69163zbSVbMMwdi58uTVpUuf89k/HOqhNjVH8l9v8+VRIEZfWzKW8rogpLOLcaWW8nTWOn0z2TDjHjnWlNbRIYc3abbdF+5BdfHEnScVlGIZhGF2bjFPeeJYv9wObgEeT1DsROBvYCHxFVY9R1e8Do4G3ge8D50a0mwBcC1QAB6jq4ao6BRgBPAd8E7iqNe/JaB38yfODD0J+Ptx/v1slveiiWIrwRBQWwrPPunobN7buuLKynFKnTx8Yd/woSipLyaOGcorIo4bZzOU93OppXZ2rH46nEBXuoKgIevVqPF+eONEpbVasgOXL41eyO026W8MwOj1hubVsGVRUxNxWU8WPyRR5lcw66CeTnfLkZ9PdINtEIeW/3MaPZ9NzK3l05IV8tWAlN1DCsVlL2UtXcPWBT7h6K1e6EtYitcbDTORDtmKFuVEZhmEYRgaQccoboBTYGzgLSDYLudTbXqKqq/yDqroJmOHtzoxwn5oJCHCdqr4caLcN+BFQD5wtIr1bdBdGqxH+QDjvPGc987//uY+FJUtg9uzkfVx+uVP6+EGJW5P6euc+JeIWLadmLWQ7RcxhLttxq6dBystd3JwgUUEz+/SBrVvj58upYlpaqILW5Y033uD444+nb9++FBUVMX78eO69914ARARJpTU0jC5MlNwaNMjJwkTxY4I6hs4gr67a3ylPjslyg2zVgMZhgT53LsMPH8nf+xZzzY7zeZaD+X2NOzfg/GI4+eT4tjk5rS/8gz5kTUmtaBiGYRhGm5NRyhsR+QZwIbBAVR9LUm8wMB6oBhp5p6vqs8BHwECcJY3fLg+Y5O3Oj2j3HvAikAd8t9k3YrQK/iS/pMR9IPjxZXy3pfXrXTKMFSvgjjuS9zVzJvzkJ3BuI1us5tOTMt5kHD09HeMLL8Dnn8O19SWMZSU3ciF74lZPw2zcGD//jXID27DBnQvOlxNlRikv75zuCpnMU089xX777ceSJUsYMGAAxx13HD179uSMM86gxHzVjC5Ec402ogw19tjDyZ5E8WN8HcOAAS2TV21uteMpVgZe4gZ5d810ttGde6qKWy+gcQKBfkPPeVxfVEpV/yHUeC64jRCB4cMbC//iYvfggw+zKQ8r6EP23HMulaIfTM7SGxqGYRhGh5IxyhsRKQAeAL4AzktR/Wve9i1VrUxQZ1moLsCeQCHwhaquaUI7owPwJ/nvvOPmuNmREYwcn3ySur/KSreoCPDlL7d8fEezlHGs4LvEVjo/+QSWMxHt72zwP2EAr9I4QufIkY3nv/6C50UXOdcqn+B8OZFV+003ZUi62xRkiptEKioqKjjllFOoqqpi1qxZrFixgoceeoinn36a5557jt/+9rcdPUTDaDVaYrQRDvZbVBQdPyZsZLJjR0whn0heheVFc6x2mi1zQoqVGnKpHDCU64rmtV6Q+AQCffrckfx99Sh2ub2Ubjk11HUrci/AoKVfVhZcc01j4Q/ObNN/mP4DCD6sZA8l6EP2zW/C8ce7FZP8fEtvaBiGYRgdTMYob3BxZvYEfqaqn6WoO9zbfpCkzrpQ3eDP60hMVDujHYlyDTrppJb3+9lnrjz5JLz5Zuy4b0EzmHVxljSJmE8x5XTnAdwAH2Q65XRnPrGVzk8+SR6Hx5//RqXUveYauOuuxK4HUZlRMibdbQo6g5sEwOLFi9mwYQNjxoxh9uzZce5R+++/P2cHc80bRiciKHNSuWGmQzjY7zXXRMePicoQCNCtW2J5FZYXzbHaCfcRqbeIOhgQqnXdiuiWU0O/2+byj9UjYwGNW0MbHSHQG/QnCxciRUVkz/NcmFTdNj/fKW/mz3fKlV693OqEz8aN8JWvuIfdv38smr9vlTNpUmpB7P9x/OY3br+mxmnbfvGLxBo1wzAMo3MxZ05Hj8BoIhmhvBGR/YFfAI+o6sNpNOnubbcnqbPN2/ZohXZxiMgZXkry5Z9++mnSgRpNJzzJr69PnAI87LoU3g+y665QVQVHHBGfMcq3oLmY6xtZ0kQxi1LWMYTqQEapDxjKFcQvG/vXCI4pNxcKCmKuBIlS6j75ZGLXg0SZUTI5hXhrfCS2J88++ywAP/zhD8nKaiwmizN14IaRgkWLnMxZvDixG2ZTLPbSTQUeVDDvVljGa9XjGNitjHnzGsursLwoLnY6i1NOcfvpWO0kkjmReotEWmVPqGbPm4t4g4y7x9bQRidLdRU8d8EF7pgq3HwzPPYYjB/vrl9Z6ZQ5QesbVfeQwukVKyrglVfcz9OmNY6M72e0euklF8AoqG3LzYUjj4z9AbXWMzAMwzAMIz1UtUML0A1YCWwGdgudux+XLvyi0PHLvON/SNLvVV6duwLHTvaOPZ+k3U+9Ov9IZ/zjx49Xo/VZtEg1O1tVRDUrSzUnx+27GWmsTGW+KuhJLIjc78kWfZO9tSdbGrWdz1Qtp0jrEFVQLwu41iFaTpHOZ2qjNn45kUVaTY5upUirydETWZSwbnBMu+yi+u67qkVFqoWF7r7AbYuKVKdOdff/yiuqGze6nzduVF22LPUza2qbFStWNP8X1ERWrVLday/Vbt3c/Xbrprr33qqrV7fbEJrEkUceqYDefffdkec3b96snpxoUr9NeebAcu1g+Wyl68j4qVOdjMnKcv+DWVlu/4ADYvInJ8fJ3pawZYv7396ypfG5KVNUe/VSfbzYycQb9l2gW7aojhmj+vTTsfajRrljvrzw5WRurtvm5cXkSNSYo/rIynLvk6DMfTh7qlZmFzVdEPsPM1G7FjyjRkydGv3yC5bs7NjD8X/BIsnb+A900CD384IF7nrz58fOn3derL9Exb9OE5/Bzo7J98woXUW+G23D7NmNS5ejS95Ux9LW8j0TLG+uBsYAF6jqhjTblHvb7knq+OfKA8ea285oJ3wL7Pnz3UKfqnP1r62Nt5YJuy7N52TqEf6IW5r1XZmeYFJCaxrfgqaK+BRUO8iPtKQJ8gNiGaUqKOQeftzI2ifKvWr95u7knlrM9u3Qu3fsnmprXVxIf/XYX80uK4NDD4XRo1M/u3RXwDuCzuLWFSZRNqkoaxzDyGTKy+PTeNfXu/333kvPYm/dOuetsy6Z0zExQ4wHH3T1R4+OGXXcWVbMFzXdOXqhk4kX/nc6RQO6M/vd4oYA7YsWwerVcMABMU8g38qmpsZtq6uhsJBIqx1/DKtXOysbX+aIwO67x1sZ3Te8lKxhSUyPEgnVFposNclYpbTURYFORl5eLFDakUe6bfCFmYiamphL1cknu4cUzGh1yy2xP5hE+DIyUwOtGYZhGEYXIhO+QL6PS899qog8EyzAUV6dGd6xu739td52aJJ+/dnO2sAx/+chTWxntBP+pHbp0tjE3Z+wB+eQYdelHeSzg7wGRYygdKOCr+PMw6Pi0qxhFLMoJZc6KskHoJJcCqjiVs7lPRJrFm6ghD1Zyd2cznYK6UV5IwVRlHvVe/VDOexFN7n9+ON4d7CVKxunEO9KFumZ7NYVZvfddwfggw+iw2qtXbu2HUdjGC3nppuc8iLIoEFw++2JvXaCXHedU5rMmuWUMm++GR/qJOymdN55rv7q1TH5tcvtpWQNjSk9KutyeXeHU5T7uoOf/tTVve8+t00UqL6qyuk1li1LHBT51lud4mfECKfL2H332PukshJOunwUedc2Q6vcTG10s9xHR42C445LPp7KSudLBvCPfySvm4j8fPd7SRasLUxRkXsxN+XZWYwcwzCMzMDi3XRKMkF5A24cB0UUb8mLEd6+b0vwurcdJyLdEvQ5MVQX4B2gEugrIolmGF+PaGe0MeFJrT/BToSveMmjhnKKyKGW2ziXXOoopwhF+JjdqfaUOYni0vgWNCvZEwW20RMBLuTGhNfuSRn3cxq3cQ6bGMDubAQaK4jCY8yjhtnMTaoU8lOId7YYMemQLLRDpvHtb38bgIULF1IfsfL80EMPtfeQDKNFjBrljEUgFix4jz3g+99PYrFXVsa7uePoJWXccYc79MADTikzYUK8Ytk3RvGtZIKGH37Mml7jR7F9plN61BcWkUsNV+Y5mZhIZxAV76ygAHbZBbZuhb33djF5g2MIhn4ZOdIFvK+vd9ZHwXO//S1xWmUtLOJvP16Unl5h4UK0sIjru7t26WijUxrshBUbfoDhW29NY0AeqSxlwoi4UlsLP/tZ44xWWVmJFTrbvfCB/fo11sgnUtJ0pRUJwzAMw2hnOlx5o6rDVFWiCi51OECJd2wfr8164DUgD5gS7lNEDgIGAxuBFwPXqgb+5u2eHNFuBLAfUA0sbbWbNFISNelORdB1aTtFjfbXMSSl4sS3oOnPJwjQj88BGM1q6hHeZ1hDXT/w8GQWMY4VHMsS8tnRcD6HWurIjlMQhcc0hcQT/Oxs96Fx1cVl3LdsHHsPKoub5NfUwMUXp/98Mo1MdusKM2XKFAYMGMA777zDVVddhQa+RF9++WVuv/32DhydYTSPwkLo0QOuvtpti4pSNFi6lDG10W6nvqGHr2ieNcvJ8USWMt27O2XLZ3c4ZUlWqVN6fK/aycSm6ByqqsDPFVBb6+RmcXG8QUx+vlMgffABXH65q/vOO/FJmV56Cb755xLOOmQlZadfyLcKljGmfBn/XBytvYnTR5SU8NdrV3LJpgt55Lr0tNFJDXaCKb0XL3Y/l5S4X1Rb4acfV4WcHKckyspy2rGCAnc8Kyu129ZHH7mb2bIldsxX0rRmajPDMAzD2Nlpy4A6LS0kCFjsnZvsndsAjAoc7w+85Z07L6LdRJyb1nbg64Hj3YFnvHY3pTtGC3bWeixa5GIe+gEmw3EVw8cm8Ir2Z6OCan826jTuj9t/ksN0M730An6lm+mlf+IHce2DwYwP5V9aSV5D0OJ60Ery9GD+r6H+C+ynClpDVkOdYP160LP5TdIxjmdZ0tiPBxygDQEjXzpvQUMMSD9epR9TsjVoz4DFnZEnn3xS8/PzFdC99tpLp06dqocccohmZ2fr+eefr4Dm5uY2qU8LWNz5SleS8WkHNZ/qAvlW4wLyVpOTMIi7SCz4+JQp0fI7WCbyig4v3KhTp6qefuxGnZBCJkaVRIHohw5V3WMPjYvbm6y+iAtsfMwxqvn5seDyJ2ctiIy968fy3W+/+HjFfbO36ArZW398YoIIxH6E4g8+0PXd99SVWXvqrfO2aK9eqj/4gXvemp/f+EZTBQtuzeIHHs7NVV2+XHXkSNVdd1X9859VDztMtXt31R/+MHqcwQj04WDO4Nocc0znilrfxph8z4zSleS70fp0+oDFqQbdKW8q82lr+d7hgjPp4JIob7zzd3jnK4HHgL8AZd6xvwLZCdpd7NWpBZ4EFgKbvGMvAYXpjtEEf9NJlGljyhQ3b/QziQRL796pE26EJ+oH8VSc4uQgno6bwPsT9fUM0p5s0Ru4oEEJUw96AxcoxLJS+R8yvsKmFmmoW0uWbqOwkYKoKcW/To2469SI+2B6SGIfTK2Z0MOUN6l59dVX9dhjj9XevXtrt27ddJ999tHf/va3um7dOgV0t912a1J/przpfKUryPgmZTdSVV21SneM3Eu34z60t9FN32RvHcHqSNk1vO8WXd9zb+2fvyWlnM7Pd2NJJxlSohLOKuiXPfZQ/cMfVEePjlciJaqfleXq/SkrXsZXk6PbKNKtxzhBG9ZH+JkQ/Xs9Ndf1v/GmBNp1X+tzzjmxiy9YoBs3qn525NTUGq/2LkHFy4IFMa3fli2xc/37x+pkZ8dSfq1apdqzZ+M+u3Vr/dRmnRiT75lRuoJ8N9oOU94YzaGt5XuHu021BFU9G+f+9BouJs6RwGrgXOBEVY3wlgdVvR6YBDyNs8Q5FvgMuBw4SFUr2n70Oy++NbVvGe67xJeUwHPPORNyP3FGTo77OTc3OvZBFEezlHGsYDc28okXNukTBrA7HzOOFTzBpLgsUIP5iE0MYAZ3osBjHIPiXJ6gceBhAMUFRa4inznMppwe/JPDuYH0Arn4LljBDFXzckrZkDuErHx3nRrNhSFDuW/EPAoKXB1L6NG+7LvvvixZsoTNmzdTUVHB66+/zplnnskzzzwDwPjx4zt2gIaRgqA3TtphRkaN4o6BpeSmGa/r1H5LGbx1BUdnPZFUTveWMl7dMY7Lzi3jpJPiz0XJxDCxDH7TAXiQaXFxxtavd55Al1/u3KP+lNU44184cH1lJdzar5T1oeDyVQOH0uNmJ2jDbr15eTB2tzI+q+vFNor4fY3rf0BJyBXIdxU6xWVBJOhuWVzMgEE57JJbDsOGNS1QcFvjBy4Cdw/77eeiPvfuHTv3ySexOnV1LpgZON+wK6+M7y8nB4YPh549O0/UesMwDMPIRNpSM7QzFNPap0/U6iU4E3TV2Orw/fe7c4WFbrvbbqp33ZV6pTZsIeNM/Qt1B7laTmHgeLbWBSxo1Pu5ilx9nKMUVMfx//QUHmjo+0QWaTU5Wk12Q7s60MeZ5BYh03CJSrVyLKL6nwuc71h1vruP589b1OBO1tqLlWZ5k5xNmzbp2rVrGx1/8cUXdcCAAQro4sWLm9SnWd50vtIZZHwiy5qwN07Yci+ZRc7Wo6bolgi306Anjy9za7NSu1eF5V7QuCOZdUywjGSVvs2eWucdqCQ3qUXQBcet0rfYS7elsCASicn4rd475Nf7xQvasByeNcqN9+Os3RsslBq5Aq1a5VyFCgqib2jEiJjPVkdb2yQqIs5lKsokNliysmJ/WL7vWrDk56secUSafntdH5PvmVE6g3w3Og6zvDGaQ1vL905teWN0LvzVS1W376/QvvKKW5ycNMmtDt95p1uU69HDLdht2ODSwfrtEhGVmnsLfcijhi30DhzPYxMDAfC7rCaP1Yzm59xGT8p4mB+yhOMb+v4BC1EEJbY6mgV8h3+xkMk8xaGsYnSjMYVXk2Mrx41XglVh/Y0LKast4pc1LsDxhlsXcdJJblHWFivbl//9738MGzaML3/5yxx33HFMnjyZfffdl/32249NmzYxbdo0TjzxxI4eZqdERK4WEfXKRUnqFYvI8yJSJiLbRGS5iJwjIknfXSJylIg8KSJfiEiFiLwpIpeJSH7r303HE5XAp7gYHnkkFlgYnNFEVlbMci/YLpwcqEdpCQ/8ciU3ciF7srLBqjAYWNiXuVX1MZkbldUvSu5trnVybz7FbKOI+V4OgSjrGJ9SZjGSNQ0Tl3xq2Iu3uZZLIp/LrU9EZ/xblxNvQSTiZHxtXhHXFcylOqeI04riBe38+e7eXxk6mR21wpzVbry71m+kG5XUZ+c0TpftRyj2H3yYdevcNvhLyjRU3X2lSgE5YkTsD+vmm91LPUheHtxxR+eJWm8YhtGVsTThnRZT3hjthj+PDSthVKGiwiloAJYvh23bYNOm2Jz27rtT9x9MzV1DNoVUMtBL4z2QTRRSST2QRzXvM4wKCqknC/WOXcclvMfIBrerYIaVGyjhWzxHJYVx18ylhuN4jHGs4K0Ik/9wX1EKJv9jp39/d50v563k9nz3wXRLXgmDB8OgQXD66ZmfYrsrMXbsWGbMmEF9fT0vvPACjz76KB988AGHHnooDz74IA888EDqToxGiMhEYnHHktW7HZgPTACeB/4JjAFuAxaLSGReIxG5GJdV8FCcS+1SXCD7K4FnRKQwql1nJFkCn9JS543jpwX3OeEEuOKKxu3694+5swIwcSIvrBpAURHMmD2AFd3iP7RF4mVuMveqZHJvNqVspneDWjyZAuh4HiGH2rjjWSgvcGDk88nNhWl5LuPfVTlzqc13Gf+CXkG5uV7CpQtLOHLYSk7934Wsenwlfa+JF7T77uuUN1Vf258saBhvNvXUk8Wv5SIqJEK77qciHzOm8QBra50GbZddIsefMezYkXr1ZO3amF/ZCSfAZZc5H7aiIre97LKYUsswDMMwjObRlmY9O0Mxk8v0mTo1cdDhQYNaJ2bjw0zRzfTSq5iptWRpDe6CNWRrHc7vahvd9EkO10c5VjfTSxdxgiroJ+wS4XblXAD8IMgXcn1klil/AJXk63ymJnDhcn2FzfNPZFHSezrzTLf1M001OfhoAsxtqv3Z2d2mgHxcNsCPcEHllehsgid65zYAowPHBwArvHNR2QQnEMsm+I3A8e7As167tLMJaobLeN8rJ1ECn0WLGssTEVevZ89omZuVFXOteuUV1UMPTU/mJsrq55couTefqbqNwkby9DkOaNR+JM4FqioQON5vl8xda2KaGf+G9XEyftHdW+JkrO/uu0CmxrnNauD6qxihe++t+v5LEa5AfrDfI47QRr5iXaX4Ps3nnhu77ylTVHv0cC/9Hj28tFqGT1eU752xZLJ8NzqWKJepTudhlGzQnfamMp+2lu9meWO0Ob45fkkJ7LEHDcF3Afr2dSvAQ4Y4q+xCb028ubEbb6CEPVnJZVzDGdwFQA05ZFPXsMxfwA4O4AUmsIxcajieJQD0YQuFVCDUe+1iK8C+Bc1k/uxZ7EQPMJ8dfI9HOIbH+JDBjVaar+Ni7uHHbKeQOTjXqCksShqs8y53Gw2r6r57WdrBRw0jcygF9gbOgiSRaeFSb3uJqq7yD6rqJmCGtzszwn1qJs4o4jpVfTnQbhvwI5xi52wR6d2iu8gQfGvGmhpn4BD22lm4ELp1g379Ym3y8lzs2KuucvXD3jz19bB9u4tHO20a/Pvfycfgy9ywe1WYH+AsYHy5V8x8JrKMLfRskKYK1JPFVnrGte1JGY9yPNcyk9yALPdJZK0DsIyJcYHrXyXaVeeALU7GP3LGEw1WSI8+WMZ9y8ax96AyrsorZS3D4lxnfUbwHv9d051ht5wPo0fH+59NnOhchK69Nt7nrCuh3m/kttvcy3vYMPfCnzzZ+UdnZcGMGUm7MAzDMNqBOXPMZaqTY8obo83x4yq88w7ccIOzFC8ocJbUd90Fr70G//2vU9yUlrqPDQ3PztNkeWCifiRPso3uvOvFosnypvxZ1JPPDt5mLz5gaIOCZQd5fMQg8OrlUc0X9OG/fLUhVsM3eJlCKhr68vH3qsnjC/rSk238jaMauROMYwW9KGcOc/gx93II/8cEljGZRY1ctcLU1rqPqpe9T9LpocQmhpHJiMg3gAuBBar6WJJ6g4HxQDXQKMKTqj6Ls9wZCHwz0C4Pl0UQnLtVuN17wItAHvDdZt9IhuHHYpk5s3FMrJISeP99F0csJ8fJ1ro6p+B57jlX/+KLo/t9+mnnppm/I3kWqOVpKkfCSp6RrGE0qxnIJsDJ0CzgPYYxm9K4tr7y/Gzu8BTfs6mgEAW2U5DQXSvdDFbb6M596mT8ffXT+bzaxdx58ryl5K92cnll3Sjm5l9LPRKhPMpnQ/5QF/MlUTrFb36zaypvwtq/3Fz48EP4+tfhvvvcsbIyOOQQp9QxDMMwDKPZmPLGaDPC8RimTYMpU9zPV17pzi1a5GLdVFTAdde5bKN77eXqtDRzqv+xcDxL+NgLUOxTRzYXcmNcvIZuVLEbH5PtTc2zqWM/XqSWbOq9fxXBfWRUeQqfOrKoh7jYOQPZAMB53EoOtaxiNIrwJ05qUAL9ihLGsYJnOZiRvM9dnAUkD9bpk+1F+qirg8GDLW24kfmISAHwAPAFcF6K6l/ztm+pamWCOstCdQH2BAqBL1R1TRPadWr8WCwjRzaOieUbffhhV+bNiyl4Zsxw7W69NbpfX88QFQOsKfgKlHcZwycMYD7FrGEke/M2QCNF+Eje4xkObghmHAx0PIHlZKHsybv8i8PYThGzuLLBgjFMOmO/pqCUDbnx8XjqyOZ4HmlQ6Fz27nS21Hbn3vrpZBNTwPjvg3yppvfwPvDVr8ZeeGec4ZQ4w4e7l1l1dbOeX8YTVkjV17uXU9QLfOPGlq82hCNrG4ZhdABmvGJ0FKa8MdqM0lKnXPCzSvkLdLNmOSXNIYfAkiWxue6MGW6+99prbr+51jc+/orwGkbxAcMAqMJF78yjlr14O86UfxtFVFFABc6vSxGqKKAH5eQRm3hnAQVeUGQQXmM85fTgVn4Wtyq7g1x2kMuPuI9v8RzrGNJwNhv3UHqwLW5f0ITm/z5+0g9VOOooiwFpdAquwilXfqaqn6WoO9zbfpCkzrpQ3eDP60hMVLtOia8cL/WMVKZPd7Lgxhsb1y0pcYqdCy+MKXg2bIDycuidwIEsWWa8dCxafFIFbQfi1Dc7yG+QgeG6O8hjLcO4gnlcyRWMYk2ku1aysYd5s2oUM2vigy5fxpV8wDCqyQGglhzyxwwl76vjom9SlYo336Nu8JCYMsPfbt6c8hl1KfwXfhgR9wfa0tWGqNRqhmEYhrGTYMobo80YNQqOPDKmhPGVDqWl7qOjttYtSubG5vBkZ8di4vjKnpZa4ABsp4gacuKiFSygmGNYwlMcwo1cyL68xnYKKaSKergqJEIAACAASURBVNyK8CKmUEG3yD7ryaKeLLbQhz1ZyS+4lTP4HYJQThG51FJADXvzNq/wTS7mehShLkG8nDovFXmU+X8ibr3VPafJk5v4QAyjnRCR/YFfAI+o6sNpNPFzDG9PUmebt+3RCu0aISJneGnJl3/66afJqnYYpaUuVpgvP3NzYejQ6G9j3wIH4Pzz4eCDY0rzjz+O7j9ZhijfzfNEFkc3JrECpZRZcVkBAZ7lIABqyCaHugYZuIZRXMslFFJJOYVx7lHJ3LWSjT2In4krHI/nW7zALErJ95T2BVSR88uL4aGH2JrXL64PBdYyjDPq7uDFo0rdC6s1XlqdnfDqiyqsWeNSnTWHZKnVDMMwjORYrJsugylvjDbBn2f95jeNz+XmOoucd96BXr2gMuAYUV8PVVXuZ1VXt6UWOAC/5Bq+xfOsYWSDZY0An9OPEn5FT8p4hkMYwGcIsX+M03iAbuxoMI+PxbbJYTWjOZDnuZRr4uLs1JNFHjUN5vULKGYbhSxgakNAziB+n39kWkLz/2SowoHRmXINo0MRkW7AfcBW4Ox0m3nbpv7nN7ddI1T1d6o6QVUn7Lrrri3trk1IFaw4ESUlrm5OTvJ6UWnA/Rhgvpvn7zgzoUVLMgWKryy5nXMppwejWEU9wu/5aSMZeDZ3IsCjfD/unG/9M5h1jayA0k1h7nsy/Vri4/H0Ygt/4qQGGS5A3Wk/4t+Hz6KwR3aj90EJN7CE77Hh1oWU1XVnU7ehced3OsJxcHx27IBnn21en03RVhqGYRhGF8WUN0ab4M+z/JVNf1tQ4D4cjjwSVq92CpwgQUVNfn4ssHFLWc5EXuGbbKEXhVQ1TKp3YyMr2ZPN9GYwHzVqJ8RcmoLkUsts5rKMb8St+N5ACUd57gGV5Df0UUUBedRSyhVUUBjX1w5y2UYhBVQlzdYShf+8SkpsEdLISK4GxgAXqOqGNNuUe9vuSer458oDx5rbrtPix7KZO9cFfP/xjxuHAgmHCHn1Vae02LEjdf9hi5QRvEc3KhpkYjZ1dKOC7hGPM5kCxY9Hdj43M5pVLOFYslGe59sNMtC33JnAcgBOZj55VNPLU9L47lgXc31kXJuTmU8W9VzLzJRK8Vc0ZsVTRQEjeY8qT377ZKHs/8FD5H6+Ke64AD8UlzFwgi7npJHLqBgy1llmNkqGtpOQKDBzdjb84Q/N67O52krDMAzD6ELspDMLo63x51l1dbF5VmEhjB3r3KV8i5ytWxP3UVXlYjIkcqFvCv4qbXfK3SqqZ66fRR3ZCRyZkq2aCrCIKaxlj7hV3+VMZCCfkE813djR0EdfXNyDUmZT4CmPtlNALVnMZh6jeI8bKEmYrSUqxkS3gDeXLUIaGcr3cem5TxWRZ4IFOMqrM8M7dre3v9bbDk3S7x6husGfhzSxXaclGMvm2mudvAyHAvFDhEya5BS8Z5zhjqdj0RjOEHUOt/Mxu8fV+ZhBnM/Nke195c+1zCSLeoq9JGDLmUgVBWyhF2sYzgzuAuBBpvExu3EJ1zZY7uzw4pQJ8AV9qSaXcrrzR04B4FxuB3wLx6IGK6BX2Zds6nmPkWkpxX0ZO5lFjGY1j3C8e07e+fqsnEbWNHXZeczLnsO+uoyT8xYxnPfZ9YPlFK8q5QzuQlR3bgucMNnZMH5889sHtZXh1GqGYRgtpMt6FnXJm9p5MeWN0WaEV4UPP9zNtUaPjlnipDLdby2eYBLjWME4L8NJNnUo7oMgrLhJd7KtwMP8oGHVdyGTqSOrIcZDFDXkUEU3ttHdy5LSg315jSoKeIBT45QzPSljBWN5m7GRqcR9d7PsbFuENDKaLOCgiOJFYWGEt+9rLV/3tuM8t6soJobqArwDVAJ9RSTRf8LXI9p1WiZOdDFsuneHn//cHZs+3cnd3Fy39UOEvPgibN/eNDfUcFyZR/k+H7MbEMu4t4494tyRgnLrDmawJyt5nxFkUx+nmD6apfRiKzvIb5DBdWSRjfJvDmQNo/icvhRS2SCPB7KBw/g/6shmR8gyRoDN9KE75ZTTvSHd+INMZw0juYDGkZyDSvG/ee8I3yWsmIfi/PCkvo5tnuGWP56c885lSo9/MJL3ua3aacXuqZ3Gv+oO5k5mUEE3lhUcmCDKWdcj5Z9WdXVMu1hW5lZzxo5NP3NUVORtwzAMw9iJMOWN0WYE51l+nMJRo+Dqq2Mm+22dPdU3vf86LwN4ib0d4Ylm1MQz2WQ0CyjxPggeZDrH8RhZaENMGz/WQ7CPPGopoJJnOIgfcy8TWMYNlESmtD2apezFSsaykrs4s+E64RgTJSW2CGlkJqo6TFUlquBShwOUeMf28dqsB14D8oAp4T5F5CBgMLAReDFwrWrgb97uyRHtRgD7AdXA0la7yQ4mKhRInz7OwrF379jx1nJBLaQSARbzA7bSg+0UxZ0Pyq2ruIw1jGxQaM9hDtXkUENOg+VMX7YAXsptXFT7GyihnO6M4D3qyWrI+uSCAw/nl1xFDrXUebLWl7GD+IjD+Bd1ZKcMVgw0KMU30Z+JvAIEM//FqCYXRejJNhR4jGMAqL/xRvYsX+bVj2US3Ewf8qilG5VMrHqh6Q+5K3PyyU7bOGmSmyCsXJl+5qhg5O0BA2BCYytVwzAMw+jKmPLGaDMSzbMWLnTxbNoD3/Ted5MC58Phr9L6wYt9fKubas9UP+ixFbV66h/LobYhnXge1SiQRw31uJg2QaroxlMcxjhW8ACn8gwHx2VkqSaHOoT5ge/P7AalU33ch8gFF8DMme75zpiR7lMxjIznGm97nYiM8g+KSH/gDm/3WlUNB9e4FvcvfImIfD3QrjtwL+6dd4eqbmmzkbczvouqrxCvrHRpwAE2bXL72dnODbWwMHE/qXCK8CK+xFsA/JCHyaGOLOp5m7FspifV5MTJrf15kSK2gye/qsllLcN5n2GNLGeCSu5s6ljPYM7hds7gLrKAbRQiXja+g3iO7RTxHsOgoXcnj7fQh19yFXnUsI0iCqnkOi6Jsw7ylfq+Ujzfk7pRYwEny8W7Sj3ZHMrTPMNBVPTcvVF8F8EpkcDFydmZCL4jE1qwijgTsBdfjB0rLnZmuFFB28JBmwzDMDqQLutaZXQaTHljtCvFxfDYY7G04S0hKg5MmGuYyVjeaVjRhdgEsw9bGoIXC7CDPOYwmx3kk091XNapcNsoghNVAWrJJht4lfFe/271toBKbuBiAL7OMgqpIPxxs44haOhq9Z6Tlx/0MzcXPvzQxbR4993YB5vNdY3OjqouBu4EBgL/T0QeE5G/AKuAvYFHgNsi2i0DZgKFwH9E5EkRWQiswblmvQxc1j530T4UF8NJJ8XrEPyf/XhhvvVNeUSY5nSzWs+ilC30bpBKTlYN43GOYSwr6U05n7FLnNxShI0MBKQhaPGlXMOlXEsOtVSTgwDVZLsAv56KJAvlKQ7hKi7nGJaynSJmU8o2ujOFRQ2xeF5n3wY5HXOt2sTN/AJFWMp3EeBc4tMedqecQioCSnHvuXnbcFB5l13KvQ3qyOYDhnI693Da/2fvzOOjqs7//z4zk0kyk7CJBJA9CYtxqxC1aquIC7hbwWrcqj+1UnEBDYvKFlaJiqBotdqvtcVawFZBrLtVW7USVCqiCGETBESBkD2znN8f5947d+7cmQQM+3m/XvFm5t5z596RnHvOc57n89k1C2Q0IUghbNvDtWQq6b0LEVvVsb/Xvbu7aJsp2tTU7ByNRqP5iejgjOZARgdvNPuUykq1QuxmRpGdvXvncis1cvIhp6ZY/VTvmwPMdBqYwEQyiNmwuHkPS5f37MeamCu5p/IxYK7eSgSSkJGNEyKNTRyFc3JzDw8RtRLxFX/mGqqNyQuo1fSFC2OaFtddF8tG12NdzcGOlPJ3qPKnT1GBl/OA1cAw4HIppauUuZRyBjAIeBeljXMR8ANwP3CGlLJm71/9vqOkBDp3VmVREAvUmLpioLJuktEUDZy5FPE5J9Ae5bQkUeVTfVjBTEZYx7XnewQxkd4oHtbSnWqyLMeqIcznIUbgI0waYXXNRIzwjbQGJUP5PQWsoAflcaLJTzCU/3AqW2jPEBYkXKuHKF4ieIhwOX8H4EQ+jSs3HcFMNjmElyWCP3EdlWRTLzKs+7SfF1RmZW9W8Ck/42rmEmYfCbcdRKT8JxWJqJSwuAZSBXRyc2OrD4MHqwea8wGnLRU1Go1GcxijgzeafcrMmUqHwU67dmpxraCgaecwU97tpUZOHZi5hvPIw9xtvWefUITwuq4MRo3wSip2dyXVPL6ODL6hJzMZjt8IEPlp4Fs6u05unKvCRTzPO/S3XFN691ZaF+bqupRQUwOfKOmG3R7rhsOwfLnaajR7GynlbwytmwdTHPO8lPI0KWULKWVQStlXSjnHpVzK2e41KeU5UsrWUspMKWWBlHKKlLIJBtkHF3l5UFqq/m5NZz/YPT2xxrIYzfJTkxBpRBHUkOnaXwqUOHsUD9UE44IvpRRzF4+wivw4O+5kwfCj+YpycpnHYN7hLI7hf/gJEya5gE8d6XiQNkvzaJyleTl5fGvcj+lmVUZfbuRP9BKrkD1yCfkCST/DC7SkkjL68gs+iCu/PVwybZJhZrImxZNk2LlsmQrczJ+vVh9OPDFRzElbKmo0Go3mMEcHbzT7jKIiOOEE2LEj/v0ffoDTToM//zmWfWNOJjqxIWFSYU4k3AQpzXalFLPDluIPsJUcYzAetQb1TjxGiMcM9PwF5VfsBbqBYXQbjznpELbfI459EsigjtZsZwQPW4EZLxFO4r+8Q/+Eyc0GOluTgjr8bKALxTxoObZ06gQDB6qgTXq6CuJ06BBbcd/dsW5FhVqh1+VWMaqrq5kxYwaFhYW0aNGCzMxMCgoKmDBhAlVVVfv78jQaINHZLxBoejkUNJ7FWE4e4wz3JqU9I7mFp5jEeCNfxt73qQ8WSMJ4iOCJc6xaSj9e4lfcy1R8RKg13KaqCbpmOpr9ew/WUMAKZnEXEMtstB9bZwRivuLohMwap6V5NQEqyeZeplJJNjtRqwpbZA4XrJ1DrljDLO6M+wxngGkyY/kPp5Np6J2ljCgeJjT6z84t7faSS6CqSmXf/FbpEDF2LKxZox5KZlTSbqm4YYN68G3Y0JyXr9FoNBrNAY0O3mj2GaYrirnwZi6oRaNqPJafH9NkMCcTI5mRMKkwJxJ+QlapkakDY7Yrox9H8V3c57djKyH8PMv1eEguQGz+PIeHW4FvUYP29cAtuAdw3M8UQyKI4uFLjuZbW1Cmhgy+pTPHspwWVMRNbu7mYfyEqSSIjyijmGGJbvr98Pbb8Kgh5WCKle7apca4waBaed+1C9q2TX2la9bAp5/CunXq9bp16vWaNU260UOWjRs3ctJJJzFq1CjWr1/Pz3/+c84991x27NjBxIkTOe2009jhjERqNPsBu7PfmjUwblzTy6GqCFoiw/Ysxk5soJZ0OqEmx1cwjyrDgruaIOfyJn1ZShRBHelGQSiYw4oG/Kwll9ssfekYLajgea7CR5h0Iwsxi2ogPkASwkcmdfSgnJ/xuXH2+HLXLbQDVNbkfUxlF9n8yBF8S2cgFtA5gh/5gVhneC/TyGcVD3M3+aziXksjGz6RhXwXyeHXzEOCZY8edenXd/nb4iGK9GeAN16c/nDiJ2UcLVyotvaa6mhUvZZSqfI7LRUfeEA95EpLf8onazQajUZzUKGDN5p9humKIoTSawmFYoGcH39UW7MkyrSRHcYc4/2rqSSLeQxmOQVczVyqCTKBidQQ4HmuooqgVUrlcVkD9QBBarnRcihOXZs/jihOcYwa4F6XY+1uJz/QhtkMYwQPEcFDDZkIJHfyCMU8xEhKraCMnzAvcwn5rE7IMLqCedY9muVUJg0NakFSyviSh6oqVT6Rn68CPBs3Nq5907GjOtZcqRdCve7YMXW7PeIgUVOWUnLFFVewYsUKhg0bxrp163j99dd5+eWXKS8v55prruF///sfw4cP39+XqtEkOPstXdq0duMoictQtGcxjuIBMmhgJGpybIoE2zMESynmIhYxgpl4kPyDSwBJBGG4PI2Mc3kyuYDF+AmzmRyrdMq8hjA+JErw/TFuo4ogDfitIIyTHL7nY07iDmbxMHfT0wjEVBNkF9ncx1RqySBAbdwiQBmF1JHBcgqoI4NV5Fv9qJQqdnA/kzmOL7iUlzmTd5nDbURsmUYCSYuGbcaX14An0gxK/IcjyTzsW7RQ29xcFZ0sLoZu3dRD6nEjKPjYY+p1t2774ko1Go1Go9mv6OCNZp8yb57SYSkuVoEbZ2q/WRLltJGtw896uvIfTjMya/paE4lRTMdPmB20skqp7GnujQkLJ+Pb3Xjf7nbShp3czB+5i0eoIpu/cxkCKGUkf+YaI/AUwEcEH2HuMJxQOrOJreRY2j1ukyU7pkCps+TB51PjXFP7ojHtm4wMFaiRUv0/kVK9zshwP/4ncZA4h7z22mt89NFHnHLKKcyaNYuAzWM5MzOT3//+97Rr1465c+fq7BvNXmd3K0SKi+Gkk1IfExMh3gLERIh7sJrV5FkZM8N4jCiC+QxJKH8azkxeZDCzuQOAy1iIlyheQwlnKL+PCy7H9MquA6ADW8mkPq6/9hFmF9lcwGJG8Aj5rGYq95FBg2uw3QO8wFU8zu1x13Yv03ibAUxkPGmG26BTH83sOy9nAV9SkJDl+RzX8yXHUEYh73Mm7dlKFA91ZFhaOeZCgdBFU3uOU2jNXNXZtUttr7tOBXAefhieeSZejRvU6z/+ce9fpyYBIUSaEGKAEOIhIcTHQojNQogGIcQmIcQCIcSZjbQvEkJ8IISoEEJUCSHKhBC3CSFSzk+EEAMNN8HtQogaIcRyIcR9Qoj0VO00Go3mYEcHbzT7FDO9f9o06NcvJrZrYpZE+QhTawRwakkngwZ6UG5ZbE9gIps4igZ8PGpMHNqzhQC1hBFGMEUkDdTYgzpOJymzTeckbbNozRbaUe8IFJntPEQJUENHNpFGA79mHgCZ1NGHlfSgnImMJ5M66kiP85RKp55LeIm5FFFGYcJkyc7Tte7Czc9TROfO8TqPBZ0qeHZJ8oyXHTvUeLljR7Vt9nhEUdFB5RzyqhFcuvzyy/G4CGwGg0H69etHOBxmyZIl+/ryNIcZjVWIVFQoAfPevdXvhYUwd27qAKxThLjBEBhexvFWYMKkHj83EJscmwGZGRTH6Y855d5P4WO209oKkIyjhI0cZWmOJStd3chRfEUfaknHTz19WUq9oY1jYu+rH+SeuKBMCyr4M9dyPMvYyFE0GPdjZhZlURnXdz7DTXRiE+AugG+esx9l/JoX6MY6jmE5PxpZS02oUNM0FZ8PRo5UDyJ7jbUp4DZgAAwbFt9m2DA466x9f60aUE6AbwEjUBKBS4F/ANuBy4F3hRAlbg2FEHNQlej9gA+AN4GewGPAAiGEa0qWEGIk8E/gLJQb4WKgHTAZ+JcQIuDWTqPRaA4FdPBGs0+xp/cfcYQamzkzps1yoZX0QgIr6W2lzttFitfSnXV0s97zGIoEXksTQW1TZeGken8q4BwBBIDH2ElrKvATTuqsESLN8GOR+IhfVTyOLywXLD/xljD1+FlHd8YSUxlO5gSTTLh5dHhSgs7j7PMW41+dPOOlfXs45pj4bbNiCh4dJM4hawzBn+LiYoQQrj9mgGfbtm3781I1hzBNrRCZP18FxVeujP2J5+WpH4glKnTtCm3aqN9jIsSCKgJ4gFt4kmE8zmOoybHZLz7GMP5FbHJsZqz04WvGUUImdUkDGKZGzVPcwtf0phffxA083ESKe7OKcnLJoIG3OJsLWYSP5CVJPiJE8PAAI1lOAYOZT29Wksta/smgBH20Ecw0AleJ2TI+wkTwxvXB5j33YC0ZNPA9OZzBe7RlZ4JrYbLniaYRPB6VPfPKKzB0aCxwYz7E7AJu89SCCBdeGP9asz+IAi8Cv5RSdpBSXiil/LWU8ljgSpR/w1ghRH97IyHE5cDvgC3AcUa7y4B84CvgMsARpQMhRD9gOqqK/TQp5dlSyiFAD+B94BRgyl66V41Go9nv6OCNZr8xcSI8+WRMA8fELBe6mac5ji+4iaet1Hn7IHwM0xjDdGvikCzLxikyaVJJNgKlsWCunprrxhIoAp5CLSUJoIvx+gp81JNOPf6EiYe5TTOCMunUp1yZ9dj2SCCdBrbTOk4nIpkTzPbWyYWbw2FV/jQ/rYid4Sz6Ppo64yUYjI+rBINJLnhPMQWPTDVlp3PIAUbESAk744wzuP7661P+dO3adT9freZQxa1CJC0tViFSVKQSFW6+Oba/qEj1qYMHq0B5djZMnaq2dXXK1MfETYR4Kf0sod5FXIg0jgNsZU+xbL8XuJIwXrYawsHgHsDwGi5/ybJt4o+NkGYEvXuyikzqLHcpNwQQoIal9KWAFTxN7Au5i1n4CLOKfEs7zB64sl+Rec33MsXqg1/wFFHri93zXK4mioj7DPMadNDmJ5CfDzfcAOedp1LNwmElPDR6tPpHbxdwmzwZvvgCFi1S2yl6rr6/kFK+I6UcLKX8wGXf34BnjZfXOHaPMbajpJSrbG22AkONl6NdyqdGo/7cHpBS/tfWrgq4ARVM+p0QotUe3pJGc2gwYcL+vgLNXkIHbzT7h4oKCn9TwAeLKwgGY4ts6elY5UJlFPIlx7CUfnxPDn1ZmiDgqyYfwbiJAyQGbCZzL0voG7cvG2VtlWbLjBGGTbh5TBGwFrV0tB64GkgnRAt2WS4p5sqr2c7+yR7HcN5tcB8T6hREEdSQyXIKmMdg17IoM51/xw74dRJR47Q06NkTjl5QQnp+F4Q/ScZLOAzLlydqDuwN7H7GTueQA4zOnVXR3JAhQ3j22WdT/px++un7+Wo1hypuFSLnnBOrEKmsdHdeBujbF1avhnbt4KabYNUqNT8O2RJYkulq3c9kfs6H5LKGn/Mh9xkL2c5sPy8RNtKJ0/k3w5gTF7RpTFssVSakk3CS0I39WKUhlvhlSARr6cYQFtCPJRSyhBZUGBmeMXF81X97qCHAL4nNQ++LlrA23IWQcc/JFgMg3q1Qs5v4fImpZqAsw2tr1e/m4sPrr6sUUVDb667b55eraTKfGdtO5htCiE5AX6ABSBgISCnfAzYB7VGZNGY7PzDIeJlg/CmlXAN8BPiB85vn8jWHCzrWoTlY+EnBGyFEVnNdiOYwwxCuDbz7KhUVsQmFaXntRjK3k3xWM5IZSdt5kYzhATqzkUqyeYBRRPFYK66x7BlVeDWL24kYxVepBuFu++w2to21d05SfMY77dlKASv4D6e5lkXZ0/lnJJl8hcNQUwOt+uXhm1qCN5Ik46WiQi3HV1Ts/TiO3c/YdA45QBk0SI0P5x/AASbN4cETT6itKe7+6qux5LmZM5O7wt17L6xfD+Xl0KcP3HabcqGyW4gn09V6iUt5kSEUsIIerOMvhsDwNo4km0r8NFBLuuEwdSlLOJmrjblUGF/cddj7wKZI+rr1mT7C2Ktrm5LhYgaHoghGUsoacjmD9+jBWi5ngfU8yaSOagI8xU1UkkUED09YC/+qvGyskeEog0Ekgoht6LQ7QShNCr7+GrZsSX3MAV5uq3El39hutr33M2P7pZSyNkm7JY5jAXqhqte3SynLd6OdRqPRHDI0OXgjhMgTQowQQrxiqMg3ABU2VflFxv68vXi9moMdh3DtnCp3cUg33CYaZRQyk+H8HzfGDfqFYVcLUEsGG+jCUJ4g37CRXUJfvEaWDaiBtocoS+hHO34ggtd1hdU8/l1+Gfe6wQj2hEhieWojCkTw8ANHJOzzIDmarwDlTtWDNWRSl1AWleo7EUJN0DZuVK7cDXNdMl6KipR1zbp16kTr1uFd9ikd6tbsPRdvp59xv36pj9+PXHrppfTt25f33nuPW2+9le3btyccs2bNGubMmbMfrk5zODFhAvToERMf9vtj89e8PCUl1RibN8Pf/67mvk6HPydzKWIrOa4CvhewmM5sxEcEv6FBcyezqSSLHpRbAwq3vlOQOOBoaqmRBMtS3Gzn3O/8PYqgjgyieHiIu6kkiyf5LaD0d96lPzMZTinF5LKGW/kDY5hOC6rowOY4rTEzw/Oe6omE8FsZPm6fu7sc1kEerzdWr+v3q0WFwYPjjzHTcjMzD/hyW008Qoj2wG+Mly/adnU3tutTNDe99brb3uvu2NfUdhqNJhUTJujUo4OIRoM3QojzhRCvA18DpahUxA6ADzWG8hmvLzD2fy2EeE0IMSjJKTWHMw7hWo8/jS3+rgnikE1lLkVcwkuWXatJHelIvFQSJI0wI5nBy1xmBTp20RKITQKiCKJ4KOArZlDMWnpQj5othfHGTTJqyeQ4lhvvKVlkv7EWm5ZCl8GklgCn8iFD+b0haRzL0tlFi7hMm3rSqXIpi0qFlDGR48pNFfRfXMyt/R0ZLyUlKk3dmMlFpKBO+vmOjqxbB59+CoZm72GJx+PhpZde4thjj+XJJ5+kW7du/OIXv+Cqq67inHPOoVevXuTm5jJJrwBr9jIjRyoJEFMuKhpV89e2bVVw1u9P1MVxQ0ql+Zot3QXQIdafmiWhoLJe/DRwCS9ZJZwQs8iOIghQQwErAFWG6iwXbfTajG3UGJKYeTYRIIyHaoKkJ7EKdz+f4B3OohvruJBX2MRRBKnGa1yz13AEzKLSWgCoIsjj/A5QAaut5FhaY6UU8w79DdvxmMh82DJFT7yXppZOHdYlVpGI+oft86lt69awYEH8MdGoCvJMmnTAl9tqYgghfMBfgJbA21LKRbbdZtZ+dYpTmOpc2c3QTqPRaA4ZkgZvhBDHCiHeBhYB56DqVmcAl6Ks/Nqi6krbolIZL0MFb5YB5wKvCCHeEkIcs1fvQHNw4SJcOz2gsklSrQinclxaTzfL2tYcOK+gj6sWDKgJfgOGrQAAIABJREFUypm8Fyc27EGyhm5kU5XgoGKqLZgBlgxqacVOIOZo5YZzVdkM0kxiHEs42RIBtZPNLgLUEsKHnxBTGUM+qxPKopJhLlLaRY4/DBXy3Os5SqPYzHjJy4NWrUBKpMeDQLJZdKSeDIRQk8Fk5RiHC506deKTTz7hscce42c/+xlffvklL774IsuXLyc7O5t77rmHv//97/v7MjWHAW5yUUblKe+/r2zEm0oyAXRQpaleIpa1ttl/TWUM623Ofub+KjKRRoaLN0nguinuS9s4kgb8CKJUEsRLlAb8eIEoPrKpph5/nLaZWZ5VTYZ1/pDx3v84hh6soY4M3uQ8FnFhghbNJo5iOI8A6jmyw7D9BhWwMgNYz3Ed79IfH2GjjFXdew0ZfEMvbuAZVtAr7vvaHVdDDSqTJhCAZcvUM8ocDJhOBmeeGVt8GDpURS33Woqoppn4PTAA+JZEsWI3k7mmsKft4k8ixC1CiDIhRJl2i9RoNAcbqTJvPgNOAmYCx0gpC6WUY6SUC6WUq6WU26WUYWO7Skr5spRytJSyL3AMMAs4mZhYmUajcMxErvTMJy0tXovBTgsq+JIC1wmHXYPBLji5nbauWjDmynKai+1sLmuB5A4qwrb12tLmBRCxlUslG1WY7U/mY0BNlG7iabbQ3pYB5CGKh1LuoZogJ/KZqyaF87tpQQVpafBJXhFVLiLH89OKEmUCqqvB40F07AgeD63kDjwe9f+hY8dYmcbhTEZGBrfddhvvvfce27dvp6Ghgc2bN1NWVkZpaSmnnnrq/r5EzWGAXS6qf39YuNCqPE3abzpxc4pylqz24SsyaCDN0Z+aAW3T2S6NEDUEGM8kJB7SqU1aymTqw9gDG3OBbqgBSDfgQq7iNc6jmiCryEcg8RsZLuY2g3py+N46v88Qml9JbyJ4CePjb1yBAI7mK3JZy6sMogEfU7kv4boyqWENucyliM85gfbE662YWUCm1thwHnG4+4UZz0Se4wa+p32TNNLcAvp7C+d3nKDueiARCMD06coK7cor1SpEIKCCOH/4g9oHKrDz3XcqavlqYvBRc2AghJgF/D+UDfgAKaVTzKjS2KbSzTT3Vdre29N2cUgpn5JS9pNS9jvyyCNTnEqjSY2uNNLsD1IFb+YAuVLKe6SUK3bnpFLKFVLKEUCecR6NJoZtJrJryUrmBIpJT3c/NJX+AmBpMNSTzgTGU0k2b3I2Y5jmGvQwM3WcK8vfc6SVvdNAGhvoYjmoOPVvIoajlMrYUXiJWOeqoEXcPdgH9R7gQhYzlyKGM5NHuYMjjQmJRAWFltCX+5jWaKZNWpq6/6ONoFYoBDd8W8ImX8wZxZx4eKZMSpQJaNFCOXW0b8+G7GPY5mmPEcdhx46kH6vRaPYxdrmo0lLo3j1eKqQxWlBBIUvYyFGuAujOwI4w9kfw8iZnU0qx4c5kZjMGeIuz6ctSwnhdBxL/4gyqCfC9oe21DuXgNhe4BSVMIY3tMuYwmmPZQntaUsFqelj9sYndBdCkiiBDWMC/OZ0QXor4q/pOjMDOqXzk6lMlgCwqaUEF4yghjNcKyJt4iBLCG6c1doWLu99cijiVDxO+g8aC+I0d91Mwv+P1xvnXG68P2ADOZ5/B71TJGrNnq3Kqnj3VIs+bb6psUYdenuU8VdS4Xp5m3yGEeAi4A9iGCtyscjlsnbHtmuJUnR3H2n9PpfTl1k6j0WgOGZIGb6SUd0opv0+2vylIKbdKKe/6KefQHILYZiKvLMnhpY39uOCCxMOS6S9E8JJFZdxkw0eEYh7kHfozmbEJGSom5eQxjhJLtyBKzErWR8QSBk4jxGY68Aw3EnW4i3iTDLclUEOALykgbEwF3FZi0whxKf8gi0o20smaNDTgI4qHH2kLuGfa2L+b7aHEVfRpaePYcVcJfhGiiiAZnhDT0ify7AcuAo/p6dYM8MiOafQ4Nkj79lY8R6PRHIC4VJ42ygUsJp/V/JNBtsyRWFDCaQFeQwaryec8/slxfMEq8uPc/vIoZxJjGUcJIdyjR2fwPm9wLis4FgF8wim8wbnci6DGcWwDETbwFPmUk8taXuEivESpNUSKG/DhAT7k53EugYu4iDXkcjNP00C6axmrXZPGvjeDEFvJoYRx3M/kuP1KA01QSnFc2a3T8bAlFVzKS5Z4s3ld5jZVGZV5zN7QvLkPEr7jGuP9g4LcXKV9Y3cldOjlaeepAw8hxAxgBPAjcE6KhV8zI79ACJGZ5JhCx7GgtDdrgTZCiGSq1Se5tNNoNJpDhp9kFa7R7CnORbS//S3xmGR6NvcyhRHMdLXRLubBpAEPUEGPv3JlXCaMB0lvVlorqiHS6MxGRjKDllTyFX1cV29NzOv6IzfSgzXksto4PrmQ5XaOYDiP8BrnIYBa/HiAW3iS8ZQAarX8K3qzgt6uWj9u919//yROXj8PAkHk+Il4s4P84bz5qWUCwmGCa5eTJtRqdVqamhRqNJoDE3vlaSCg4uFuZY7OjJo7mY2PMKvIjwtKmEFtZ0lQB7bSg7Usp4Bv6Mn35NCCCt7hLLbSjpe5hElGSMAZoIgguIyXGMA7AFzBfM7lDTYmCWXU8oP1+13MwkfYEkVOMzJpTufDuOD5VbxAAz7XAIy5XW8sxLt9ajr1XMo/KKaUGgJEDallAdzCUwkZkHZ3vzoyyKXc0tmx4wzINNVVq7lIZsWTyqLngEFK+PZbpchtdyV0i1pq56kDBiHEdKAY2IEK3CxLdqyU8lvgU5Ru5hCXc50BdEKVXX1ka9cA/NN4ebVLux7Az4EGYPGe3otGo9EcyOjgjWa/4FxE8/tjv5vYJxR2/YVf8oHLZCO2ipxM3BhU0GMTRyW8n0U1QSp5gFFkUAvAMKPi71i+SBh42ycI5sruubzB9+SwgMuNd6Tr8QAd2cRq8riT2er+CeMjzDgmWcGnC1hMb1bSh5VczoK4e3K7/xbs4vF5baG4GF/5SrInKIHHzLHFqWUCKiqgrk4LQGo0Bwl2DZzTT4clS6C+PvE4Z5C3Hj/f0JMhLLCCEmZ/eTVzqSZANVlI4AWutII+ndnEVnIsu/ACVjCSGRSwgsv5O3WkG1mMWH31FO5LKH0K40ta79DZ9rtAlbLexSOsoYdlE+7WD6+lO2OZxC/5gBoCccfVEKA1OxHAi/wq4TwC+JEjuJNZvM0AKslmAuOpJsC5vAnEMiCdz5XBzCef1WyndcK17Stdm2Qk+46b4Cp/YNDQoAI3RUXquWSuPLgpd2v2O0KIScAoYCcqcNOUrJdpxvYBIUSe7VztgMeNl9OllFFHu+moP6tRQoiTbO2ygD+i5jWPSyl37tHNaDQazQGODt5o9jkVFXDJJTB6dLz97e23Jx6rNAYCcXo25iqom/4ApHZTUQLHVQji9RPq8bOOHqylm2URblJHOrWozF6zfKramCR8TU920YLXOZeNdKKSLG7lKUD9cZkD983Gaq05ConioR6/NbmpI52V9OROZjGXIkL4mGtbWHqGmyhgBa8yCFA6jvb7N7OFjix7Fd/PCykankNFBbTsmUPwjH5xMgHBILRsCXLbD8oTfN06tVN7hGs0BwV2DZy2bd2PaUEFL3MJ0xllBXl9RLiPKawh1wpKmP1lGX0Zw3Tas5VJjKWODEsUGFSWylX81eqXzOD2yXxCGmGrBCiMlwgehjOLP3AzEOsHfYSZAkbvGSMATCXekekIfuQxhrGVI/ERtjJi7HYzAthKDmvIpZRi3mYAVQR5kHsI4yWderIM5+BLWEiacR77NXVgC3/hWvzU04uVlDCBPMqt54wZtBnMfApYwVucRRTBU/wWgK4HYD5Lsu94yn64lqQIEbNHdKO+Hl56CQYNiq082KOW9pIqzX5DCHExcL/xcjVwuxDiWZef0fZ2UsoFwBNAe+ALIcQiIcTfgVXA0cBLwGPOz5NSLgFGo/5JfyiEeEMIMQ8oB84A/stBVCGo0RxwaBXmA55mDd4IIVYIISJCiHDjR2sOV0yL28cfj19EmzcPWnti7kmgNAbyKKeECfRiZZyeTaL+wM6Ubiqm+PERbAfi9Q38hBjDNMYwHR9hS2uhlnTSiLCaXCrJ5lFup4osvqSAY/mCa5lLL1ZyP1P4gbYEqU4QvgQ1yRjBQ0i8VBEABI8xDK9hjesnxP1M4WUuZRwlrKNbnFaDyUl8QiVBdsiWPMFQ3ud0ZlBMms3Wdlc0iycri3hjfgUf7iqgc4uKOJmA1q1h1y6oTW+pUp5MW1btEa7RHDR06aL+ZOcaKrRO1ykzKDOUJ1yD3M6SqsmM5XGUaOw4JlmOfOZpG0ijHj91CULCAg9Ry50JQ3mmJbsYaiygVxvBb4GqdXgcL12N112ApwCn7KxA4kWSSR249oaKCloCqqRpEmPJo5yRlHIer1lBcvP6N9CFjzmFKJ64cqf1dOU2Hk8QuQ8G4XXOoYAVPMktAPTjUwRYJV2NOUy5/b63uRr1nZrfcVfjdUKdyf6kfXu1apMMIVRG6CefqNfXXaes1oYPV6/tJVX27BzNvqaN7fd+wPVJfgY6G0opf4f6Z/kpKvByHioANAy4XErpWq8upZwBDALeRWnjXAT8gAoinSGldEo+aTQazSFDc2feeNh7Gnyagxynzk1Zmcq8WbpULaJNngzv3qPcky4Ur+L1xmsMOAV8nfuGMcdVB8Z0U7nUIX7sMaYlf+J6qglSxFye4UZqCLCSXkiUDW01Qb6nPfmsYjiPkMdqbuNxvuQYltLPuq4RzGSLcT0mEiW2GcHLL/mAaoJUkU01wQT3lmf4f7SggnLyGM10S3/BPidrwM9OWtOSXbRnCx/xc7xIKyOogTS2ZnTl1LcnsfC3avL2zpY+LK1Vujm1tbDFMO3ctiONNfUdkVGJ9gjXaA4urrnG/X1nUKaQMtII0ZelcfotzpIqibBCJA2kUUcGtWRY/VAaYR5jGD6bkLDJJjpaQRIfYcvtyWecMYvauIyX64iwDoigLGHMoEI1AZuTn2pxAsvwOQIl5rkeYygTmGhdh/2Z0J7v8RMiQB1VRoB8JDO4k9ncwpMIMALpWCW3zu9xW20WJ4mlQHKhepMDbdBzNeq7jRL/HR8wbN6cer8ZjTS3qQSKzRUhbR++z5FSPiulFE34OTNJ++ellKdJKVtIKYNSyr5Syjku5VLOdq9JKc+RUraWUmZKKQuklFOklC4FpBqNRnPo0NzBm2uB/sBZzXxezSGAm85Nt25qLJYzvIjrb8vi+IfVhOPPnljWjNfbtPOn0sExs1mcFuFjmMKN/B+9WMlS+tKSSkbxADfzNMfxBTfxNL1YmdR63Pn5a+lhnd/8jHTCdOI7TuU/TGMk7dnKeCZwP5OtzKExTKclu6xSryuYRxRBHRmW7XcUCFDLUYZt+vMUMdXIVk43ygEyqaM6vTX/rTueP0bVd9mRzfRhJWVHDsLjgRZSlQF4iNKG7Spwoz3C9zrSmRqh0ewBZhC8tDRxnxDuOjfr6MZYJsX1Xc7+Ujkseay+cypjeJNz4nRgrmAeEoHfcOsDlYHSgc1Ghkxy3IIb5uzMdJAKJngkpeZiFif0xW625xnU4SVMEXMpo5DzeINqgoynhCqyrGwkO63YTka0GmGbQ7r9Bdvvq7H9mhS4lVBlZKh/1MkEirV9uEaj0TQfumTqoKBZgzdSyiVSyveklO8153k1hwYpzSIckR2PP42qNiprZnfmvMl0cGIW4fHixz9jGXMpopxcawX3CYbyL87kXqbGZdakwtRFqMdPmFi0yT5wz2Eb04xgy4Pcw+Pcxn85mUqymM0dgArIhPHQhh+4iEV0Yx3/ZCDVBHiW6y2dBzckID1eOvXMJIOaOL0KgLxtHxGSPl6JDqKAFXgqq4nmtEUca3iDa4/wvUpDQwM+X6IzjUazOziD4ADmPyspUwexndj7yygeonisvvNEPmMyY+N0YO5nMr/gfdbTlQaj7CgKeOMUxIxrcbx267fMAcjX9DY+Xx1lZvGYmT9u56smwB3MSjjnOEqI4I3r/7xGbuL5/JMWVCSU3JrZSHbe5FxX1yinc1SyPlmHancTKWMlvCZ+vwrGJBMo1vbhGo1GoznM0ILFmn1KUrMIW2Sn1hckVBti2I9qwpGqLN5JqkG5U/z4LUP82LlSLYCdtGQsqQeAdvcRU1/iLc7mIe5GANtIoiSKmuwEqKGcHgmf7UXyChfzBgP5nhwmM5YdtOYG/pRQNmBHAN6/L6DVOSfjkdLdnlZGKGQJAL0/eJ7I5tXKlhW0R/heRErJjz/+SMuWLff3pWgOcuxBcCHcdV+TBbFBzYVN7P3lRSziQhbF9Z3O0tQ/cz13MpsObLZKo8yPNrNnIo5QhrP000klWVzMIm7hSaQt86eGAPczmQgewoaSmN3NahLjWMilCecrJ4/7DNtwJxnUs5V2vMnZ1BnC9M7gvMrcCfIwd8e1bWoGjQ7a/AScKzW9eqUWKNb24RqNZj+jk1U0+xodvNHsE0w9waFDU4zFjMhO9T0TqSHIr6K7bwOaSiPHKX48yRA/LiePH2lDwKbL0J4tLON4S+zYDTNgs5V2lgPLZMYyihkAtEGVICUbzG/iKG7hDwmfDTCT4YbjVBFlFDI1/0+E8blOIMxVagFw2WXIKYmeIua560UmnnQVKGq7aCHbN33HD5mZNDQ06LKeZkZKSSQSobKyko0bN1JfX0+bNm0ab6jRNMK8eSrWKiWkp6sfe9JCqiB2VVXsOHt/+QYDeZPzgOSloaAyWxocosXC+G8lQcBDuVE+GtuXiCli/BD3sIZczuMNqghSTRbVZPImZ1tBpf9yEgKoJ516/ETwciKfup53LkXMZLj12tmrpdNAK3ZZzn1u97eTVo2WQznfN3/fQjtXS3NNIzizbkC5H/bsqQYQdoFiO43Zh2sxY41Go9EcQjQ5h18Icd3unFhK+dzuX47mUMXUE9yyRRlGgBqL5dj1fYuL4dFHaZuTw9NZ1/D7+79t1msoo9D6/XtyrEkLQA/i7bE9SALUkEUlLajgQ07lVD5kFy2ZSxEXs9ASP06nwZYRY05jJB7ijRLMAXwEgQfJBjqzhlwqaUEUYZMLVedZS3dLbPniVQsTzqfszonTn0hVYyaBuq69yNy4HIJBMjZ+SzeibAfWrVtHJOJq7KD5CXg8HjIzMwkGg7Ru3RpPKmtcjaYJFBXBokUqyQDUNhKJ/9NP1df9VMrJYyr3Mo0xce97ieInhCBKrqM/hfgARj3pvMIF/JoFXMArlDCeUop5l/48we+4lScoM4JHbzCQQpZwOh9xF4/wDy7jeD5nO0e4Xt84SjiFj+jCBnxEiSDwIhPKm5RzXxYLuZihPMGHnMoK+jCI18gw9HtiIsuqf7bfQwQPEoHP6JdjmY6C5RRwLF+mLHM9mHHe10+6z8xMaGhQ2TLffBO/LxxW1oiDBsGHH7q3N8YN5OQoFe9vHeMGu5jxVVft6VVqNBqNRnNAsDsCDM/StAUkcwyjgzcaiopg4UKoN/T/r7sObr4ZLr4Ynn/ecXBhbMLxxrIcvgrkIGpTxiOajWE8xmPcRke2WO99Rwf68DWDmU8BKzifV3mBqxhHCSfwOT35JuE85gC/kiBBapAuFrdVZCGAaoK0oILefM2dPMIjDEcYEp5RPIxhmiW2fAGLLfeVVLitBNeThk9Eecg/moE1H9M6GISxY2HSJNL/+lc6XHopHTp02K3vi4oKOPVUNaC2lwIle1+j0TQLJSXw+eewbh3U1ipZEJ9PJS40NDTavFnoy6dUkUUNAXL4HoBa0llLLmOZyBPcxpFsM0zDFRII48NPmDRCXM4/rHOF8FmBD4BHuZ160vmBtrRlmyVk/Ci38yD3sJCLuRrnA0RRTh4jKeUFrqSKAAFqqSfNKPOKXU8DfsuN0Myi/AM3UcAKq28PkYaPcFzgpoE0PET5F2dyBonyfq3YQQa17mWrmkRqa9U/3i5d1ADh/vsTj1myRNX7uQ0cbOOGuBWh3Rp8aDQajUZzcLA7y8DPJfn5C/ABUG0c9xI6cKMx2FM9weJiGDAAvN7EkoBU7Gliw0v8ivV0B2JlSC3YRT6reZLfAvAcygGrhHGMo8Sw1k1EAKvIp4ogIdLigjdbaMetPMF3dGAq93EBi+nBWq7meaJ4qCODOkOk0y62bGo4OD+vngx+pE3CPvvv4R498QrJ7Wd9iW/GtMS6tSRp5SmzzZNZs2rLVo1mr+KU+airU/PffRW4AVWWlc9qhjHHkALGEkb+B4Mpp3tC7yjAEhH2EMVrZKx4DKniOjIt7a8G0lhPV27kmbgSJvP9xvTIrmAeVWQxnhKqycRLlEqymccQAEJ48RNiO61ZxvGWM1UpI+nBGjxEqCKAQLKUE6klgx20opIsXmMQF7CYMUznEe4CYv1tFEE6IVqxy7qWQy2A45Zl85Oyi/x+Veo0bRosWwaBQOIDf0+EiLWYsUaj0WgOQZo81ZVS/kZKeYPLz/VSyjOBPOBNY3v7XrpezUHGnuoJFhaq5JBFi2D9epXIkZnZ+Oftjrixk2oCVJLNlxwNQJYRj/RahrZR1tOVBxjJM9xINQH+YQhmmgP0MIL1dGEjnfASJY1Q3H4fEQSC3nzDO5zFn1DViIWUEcHLPxlIN9ZxIYvidCqKSfQFlmCVbgHIYJb1/gTGU0OAH/NPJnjDlRCNknlaP46+vjC2MmlqCCQJuLi+ncyatVs3bdmq0ewjnDIfyUzMOnXaO59fRiEzGc4LXGn1j16izGcI6+jMyXziOsEPGcm+zoDGd3RgNNPiHLK205qFXEJ7tlptAtSyndauzll27Jo/I3mQNCKM4gEEsItsHmMY1QTZRYs4wfgG0qgn3Rb4CbKT1ozgYdqwk5GUMkWM5T3/eawmn9/yJDVkEjXyIj2GpLJ5785tYxwMgZ5mLwOTEl58UT2LzFWbFi1giAq04fPtmRCxFjPWaDRNQAsOaw42mk2AQUr5PVAEHAVMaK7zag5+GtMTTEZhIQwcqGIMp5wC48bF9tmdnvYEt/b3Mo0TWUo2VZTTw8rAAdNBRTCeiRSwgpZUMpoH6MvSuPP6kNZkYz1dkcafWIg0JNCa7dYqrwdp6SV4iLKObhTzIN+Tw5ucxyry+dK4xvV0db2PCF7KyWUU0/FUV/EUN7OFHB5hOK9zLoFVywiPUxbo3H+/+h9gBlScgZiiIvB4+Ljz4ORxmCSrmVWzn6E81AXZ1FVOLSKp0ewxxcUqcW7pUhWwrqtLPCYzUyUwZGTsnWtQLn2dqTVcm0wb7fZsjSvxtAck/ITjMjdCeBHAkWzjbN62HLJqCHACy9hILPoUIo0oHipIXo5p9uvf0JOZDKeSLGZzB6BKri5iEQKYwER6sZLxlCTYqk9lDPms5mHu5h36cxr/5lHbOd6RZ/L50UVc5FlMSyr5mj5Uks0XFFjfg53dCXYcivo4jRIOw8iR6nnQs6datVm5Uu3Lzobbbks9cEj1LNnTwYdGo9FoNAcozaqeKaXcDiwBLm/O82oObsyJRjK3z6by6adq/NWnT8zp6Xz2rDzHrX0ZhZzEEvJZzSIuwkeEEF4AdtECieAFrrSCL49yO+3YSgRP3KC7nnSG84hVWmWm39/HFGoJWKUDJuaK7WsMjFtRvoDFHG1c405auTqYbOMIjuULpqB0Am7hD3RkK68yiFGUssnX3XKXAqB161hAxRmIAZCS3OtOT55tnmQ1c2HVAEY1lCDrm7jKqcurNJo9ptBIoCspgc6d3Y/p0gVmzYJzzlHlp81NOXls4igyqXMEaELW726ZJFvJsXIZzSBPOiHOZzHv0J+HuZtRTCebKv7JQACrD72TR+jDV0mD9vZ+XQWX4rNqfuQIWlDJ+bxqOWo5bdVP5DNL4Hkkpayje9w5wnjp8cVL/Emo58CJ3mUE/SHasCNO4exgyKI5IOjUST0LzOeB+Y976FDo0EE9R1INHFI9S5pr8KHRaDQazQHC3rA+aQB2U/1UcyhT6FKpsycUF8O2c4r4Ym0Wc71q4Gzq0NgtvVPp3syliEqyrACM2X4t3eLev5PZ+AhTTi51ZNCaCiYxlo0cZWk1CKThrqKG6eZgfQ3dWEOuQ3chyAksYwzT4o61cyezXa/lOa5jAG8Tdfy51pHJb3kKD1FL6NicOpzEJ3zGCbT3bcNTVxtrtGULHH+8SqPJy1Pp6bW1cec9cupwlq/08UxdkXscxraaWSOCvHjlfK6/XulMVEaDjAmp911XOZOVXenyKo1mt8nLg/OUu7dVOmVuBw6Eyy5Teq32+GxzUkk2UUe+iLRto3iox49EUEc6YXwM4zFu4hlqCOAhVufqJ8TFLCSKsDJd7mQ2XiJ8Q0+qCXI1c8llLZezgOUU0IkNLKeAeQw2+kxVhvoc1/I5J/AjbfATIoSPALW0Z7OxP/bcSGWrXk4ek9PiM3PmtJ+M7NKN+qj6UoXfz5aMbtyS/hy7sjr+5O/0sAv6bNwIV1+tfr/22tjzYPNm5T716quJA4eKCiWIHwyqZ4izrUlzDT40Go1GozlAaNbgjRCiPXAasK05z6vRgBqHZZaWsNnfhdpIvLDlWCYhBLRvrzKoAwE45pjEc7itxprCmPb36/FTSTad+RafsZI8jkl05Ds8SGpJRyL4jo7WamsDPqJ4+I6jAFwnBb/kA2oIWBoJ5meZW/u1SJ+6Fi8RMqllnaN0ahV5HJVdRQYNNl0ehY8IYbwsrTs6fnIVjarVzHnzlBL0rl0kIARbM7vzQHCSe7a5bTVz6/sreaFzMUf4KuhHGaenL2Fh3t18/0GSVU4tIqnRNAtmHPTRR9XrcDh+O3u22u/3Q5s2e+caxlPCM/w/y1nJ7NNMofZ60vESoYYA9zGFaoIMYT7PciOjmA62NvX42caRCLAC1fX4WUlPNtKJNEIUUgbAU/yWAlbwFmdTwAr+w2lsoIslnhzBw3q6UkkLaghxGBKzAAAgAElEQVSwk5Zxfa79uVFGoZVpY2bjQKwEa0hoLtUEKfFMpIYg13X/N0suKsEnQ4TSVXS7fsxE0gcN4OvqLnH3tDuBmGSC84c8djtJj0elib30UuoA/+LF6tnVqlVstcbj0c8SjUazR2jdG83BRJODN0KIX6b4OV8IMQL4D9AKeHmvXbHm8CYvD+/kEtIIUWWshI5nImtFLl6vmsiYrtdff53YvJw8JvniV1LHM5F3GRCnfeAjwr1MYT3daDCCKz7CpBklT35C+AiTQR0YpVEeJFvJYQYjAVwnBaUU8zYDqCSbCYynjvS4z3yAUTzKHUxnNJ5wiDrS8RjKOT1YG3cvx/EFT1RenfSrWkUeJ/NJvFm5lLB2LUQiyp7mq69c21bfP403Pm3L3X/ozQ9tezN6qK1Mwbaa2f2UHH5d2o9zGpRr1vGhMiZOhG4nJ1nl1CKSGk2zYMZB/YY0l2kZbsZF/X41D377bfjuu+b//LkU8S79uYln4t4XYAm1+6kjjQgr6J2Q2eIMZKfTwJHGuo+fBuu9+5nCCGbG6X6Z2Y89WQXATEbQh69INz43nRC5lOMhwiimcyQ/8jQ3IhBx/X4q4WOzBKuMvvRmJb6Rd1PgW8ng/xaz5VFVanVvaCIV4SBfT5rP669DrfQTxUM1ey40ZGoHHZaEQlBVpf4RuwX4nZmb332n2phty8uVZo5Go9FoNIcou5N58y/g3SQ/i4BSoDvwORgCHBrNnpJChLDDB/OQgSATjZXQIczn2mtjGSJz5qixXrJSgcvC8RoHpiW3U/vgF/zbCuhUoayuTLeUOtJZSU9W0ssqjWrAT0c209FIzTexiyN/Q0+OYTn9WEIJE3iDc6kmYH3mUB6ngBU8zAi8hOPcpOwDenN1Wjr22Vds+/EpGdTFlSYAKnDTCHn/nUu7/gWwciW+8pX8bHMSbZqiIi68Mos/RtVg+v+i1/GrIR4YPDj5ybWIpEbzkzHjoJGI+jOKRuGOO1R8NhhU70+eHJvb/lScIu9mFqOZOVhDBmvpxnabtbfX6JF+xjIqyWImw63MllKKecsIZM/mdqIOc/EwXqt/LifP0hCLuIQ26vEnlJV6iPALPrBKsG7mGbxEWEW+9dxww1laO4GJrCaXE0qLOLp/Dt936cdsv8qqnJN+Nxf1XEm70mK6dYN/eQbgJcqT3Mp2Wh70QZj9kgGUmalSZxsaEgP8bjptdvx+WLJEC+FrNBqN5pBld4I376f4eQv4E3AtcIqUcufuXIQQIk0IMUAI8ZAQ4mMhxGYhRIMQYpMQYoEQ4sxG2hcJIT4QQlQIIaqEEGVCiNuEECnvTwgxUAjxhhBiuxCiRgixXAhxnxAifXeuX7MXaESE8LYBK/lD9t2U3rSSxwPF1NXF9AjtyR2m/sNRR8VEO5NpHLi9bwZ0xjOJGgL4iFgrt/czheE8wjv0ZyLjLaFOU09hHoNZTgGDmW+JaF6AylAx0/8nM5Y8yunL0riygFbsSLjtRBcTmfAH7Azw7PbkweeDE0+El1+GTZti7xcVqX1ObZqSEmTnLvgy0ozmQoWU+vZN/hlaRFKjaRaccVDz9ejRKpgzY4ZynGoOnCLvZkDF7BMzqacjm2mJKsW0T/ztZUomZRQymbH0YiV3MZtbeAqBoBr1+E0jQjGlVv9s9sV/4VoAwkbvV0s6XqL8lSsJ4yWCIIyXmdxlZE7GSmFX0pPfBBYw9Cz13HCLASQrrZ3ddhJPPAGlpfBxpJDqYA6hENwxJYeT/v0w/1sTZEJUWSKO4BHaGEEuezmZ/XcnB2KgZ59fkxBw0UVKm83vV1k2gUAswO/M3PR41E8wqJ5PF1wAq1drIXyNRqPRHLIIKffL2kr8RQhxNvCm8XILsBSoBo4GTOWSSVLKcS5t5wC/A+qAt4EQMADIBv4BDJFSJqQaCCFGAg8AEVRW0Q7gDOBI4GNggJSyprFr79evnywrK2vqrWoao6gIFi5UKpvhsBqQpacr9c2vvoIPP4SWLVmyRC3A5eTA1q3w7bfxVTpXXAFvvKEyqMeMUavQ0Wjyj7UjRKwMvx9L2EAXvieHl7mY/rzDBCYylkm8znlcyd/IZTULuZiurCNILdVkso7u1JFOXz4jjAcf0bgsmRA+vER4kV9xBQtcz7GLlrRni9UGiLPZtf+eiqYe1yh5efDaa9C2LZx6qvp/AUpcaNOmRO2CzEy4+GJ4/vnm+PTDDiHEUimlVtjczxzIfbyzH3ztNdVVvv220oAdPhyefhoqK/f8M+ZSxMUsJJ160ggTwkc96SzkYnyEOZc3KOUeShhHNVkEqcKLJIIHD1HCeAHBVfyVF0mekfc3ruBSXkIQJc0oi7J/1kyGs4EuPMrtnMdrbCGHfFbzP46nG+vYRTZH8KPVf77CRcxnCH/lKupIJ4N66xoyMlTyhs8HOxLj5FzOgoR2//AMJjNT6Qft2qWeLZMmKcHov01ZzY/HnsERdao+zd7XJ/v9YKLZniGpMB+85tbjUQ/tfv3giSdiD3j7w330aPXeMcfA55/H2prjhgP4+aP79wODA7l/1+wbmkPv5oDUzDlkb+zAZ2/373vDbWpPiAIvAr+UUnaQUl4opfy1lPJY4EpUgGWsEKK/vZEQ4nJU4GYLcJzR7jIgH/gKuAwY5vwwIUQ/YDpQA5wmpTxbSjkE6IHKJDoFmLKX7lWTimSCtqedFpeJY8quVFTAWWdBfn7sFBUVUFamJjZ33w3vvw8ZuyFBYI9B2HVrJjGWk9uUJ2TsmCvQpnZNJnX0oJzj+AIgTkzYHABH8eBB8m9Odz2HnxBr6Ra7JpfrbOpgutkG3W3bqsHw/Pmx/xfz5yu3EOfyfjQKNTV7NmtMUTKn0WhiOM10Xn9dVZeYkiCPPgp1dYntsrJimYhmdmIykmWijGWSla24lh54kWRSYxVzmuWaa+keV56ajBZUEMGLj9hai48wYbxxwsKlFNOTVVzD8xzHF9zE07xDf9qxzcp+9BPiIhbyECNcS2Tr6lTXdMUV8NBDiQ6FzhLaIcwnGlWu1nOmVvBDTgF331TBypXweEURnHACrRu2uN5Xsv53/y+bNZ2mLhIkkJ7etNQvrxc6Gk5d5gPYXG0pK4MzzohlfdozNxctgldeUc+h/PyYAJQWwtdoNIczOuhySHNABG+klO9IKQdLKT9w2fc34Fnj5TWO3WOM7Sgp5Spbm63AUOPlaJfyqdGo8cgDUsr/2tpVATeggkm/E0K02sNb0uwpzrToujolQjhSiQA7nSfcqqsWL1aavOZiyimnqEU6c4AuBFx+uRrr7U5JQRmFrNyZ6EoC8YP9KoI04LcmO5DoJOKnAYAHKbYsa50Thmqy2Em2uuamX+be4+OP1Zd9663qdVER3Hyz+j0aTfwyjzoKHnlk9z8nVcmcRqOJw4x1btigAtadOsXHvjMz1Rz6nnvUFuCaa9Sct0+fmDtVMtwCy6bY73BmUk6upQ9jD7yA6ree4cYEC243hjGHtXS3BOLNPvM+psQJC5tBnDIK+ZJjWEo/RlLKGnrEBZjW0oM7mZXUBhzgySfVo0VKNe83u7BSijnOv5I/tlLtHvaodgMHwkWexfi+Uf1TTg4c8ZhacLAGGbZo2MEUoNkrhELxqyFOzIdyJBJfpuukdetYIMYesRw4UKU+5eXB1KkxASgthK/RaPYhEyboeIlm33FABG+awGfGtpP5hhCiE9AXaIDEJT0p5XvAJqA9KpPGbOcHBhkv57q0WwN8BPiB85vn8jW7hVPIwe9PyMS5q3JSnOmEKcni88U7jAaDqsn998cW8rJlBSUvFtC9TYXruLJ1a/fL8nphXELhnsKul5PPaqZyH35ChFDL28mCLwJJgGoeZyilFNOPJdzIHzmTdziTd2lFpeP4A4Bkgsfml2mufnbuvHuDZ6eTiJtFrEajicOMdc6YoeQ+Bg6MN3MbMwYGDVKVJ2ag5umnlab4jh1NC2C7ZaJAYlaOKehu71anMJZychnBwyk/wwwSpRFCorITawjwSxLWdJK2dQaYXuYyVxtwO14vtG8Py5fDU0+p1595C/m2IYedO1W7T6L9mEsRk2dlEbra0T+NG6cWHIRQ+iyA6KqcscLEpzU5NckOeRqrVW5qLfOmTXDccamfBVoIX6PRaDSHAc0avBFCrBBCRIQQjazl7TZmUYzdxudnxvZLKWVtknZLHMcC9AICwHYpZflutNPsK+xp0atXw333JVhLD5uZS5cu8Sn/bdtCt27xcZ7WrdWEpU2bWOnUZWmLOZoVnFX3KhkZavxttgd3DQRQY/PSUvd9TlvwvixFIuJsut0G614ieIBXOZ8yCjmD9yhgBUN5wtJ9SMYBuaobDKoV0Oxstcy/O+VPyUrmdOq7RpOAGeu8xshHnTNHbWfNUn1efr76c/zsMxVfCIXiq0o6dVL957XXNv5ZTjH3JxjKcgrYxpFxQRMfEcI2FzxQfVwmNWTReAmlChIFmMB4KsnmLc5uNGPHdMG6mrmuAabGCIVg82Y4/ngVCMvKUo8gjyc+sDWOEr6lC2Hh0j/Nm6calpSoLz0rC4EqHYsaib8Hq96NHeczp7HXe0y3burLN2v7QOngmRm4bmghfI1Go9EcBjR35o2HPTS5SYYQoj3wG+Pli7Zd3Y3t+hTNNziOtf++geS4tdPsK5xCDkuXJqyo5eX9f/buPD6q8nr8+OckYbICbhAEkS3gAq2tEOvSFhStS7WWqm2NivWr1YLYFmnE1qIQRBR3WdytVdFfAS2VYl1qXWjVFlwqSkUUQVSwVCACgazP748zl1kyM5lJJpmZzHm/XvO6mZl7J8+dSWbmnnueczQgE1zPYfNmLb+ye7celOzapV/KAb74Au7frS1g763XM6eV74xlZ04J/x5WwQsvwF/+omeog78vBjv88Ob3hbfP9bLA72Qcn9CHtQza00o31hfbruygCeE+dBrSxdzX4jZpeRBw00365XnNGhg9OrHpT+FT5iz13ZiovFhnfoTeiIMGwaJFgWPY//xHOy/v3q3HxLt26bHwJ5/AQw+1/LvCg9O9+WxP56nQrJwiXmIUn9InZPvP6MNEWp5CeSOVlPEhVUzlIFYznSkRs2WCeV2wVjA85hSpaBlGXsJgl13VzFg8lBOPrObJJ3XGZ05O4Pn9JL+MqTlV5OeEvj9V7zeIH62o5Ms//U2DC7W18N57gAZvctIzzN5m4UWMBZC2tjYbOlSXX36p3wOCszwbG3UOdLTsm/DvDSOsFrAxxpjOJ9nBm/OAY4HjkvFgIpIHPAJ0B553zi0JutufL8HOGA+xw7/smoTtgsd1sb8d+YrNmzfHeBiTFBHOqFVUaAmWYE1NgSnvv/pV8yKUU6WKnfseSL0/xV98Xcjp34+Bj0xn1Cj9rnfHHTBkSORhvP22xheChbfP9bLA92cjA1nHXziJXJoiTieIpHk78IDwujlpafx4jZz17q2FhiCx6U+W+m5MXLxYZ0NDIMDgZSKeeqoGcCZOhFGjAjMRnQsEK9ati/93eUHqBZzJdkr21Lh5iLGcyhL+xrHcwiTK+JAruYEN9AVgtz9w/TF9Q+rWhD+uF/wODxLFCtzMpyJkLFOZxocMYj4VEbdtqbHmd9GMTN9fn2LVKpg/X9+2DjpI7y8rgzObFrBLQt+fli6FBR+Vs2nG/foBUFCwJ8VJCgqgf3/kkkvSM9gep7gzbNravXTVKl126QL77tv8/tpaWLzYptIaY4zJWkkN3jjnljvnXvLXm0mGu9C23xtoXqw4uGNyIlq73R7OuXuccyOccyN69OjR2ocx8YpwRq2qSkuqdOkSuuovf6kzrWbO1GKUIvodWwSuuKeM0ruqKMjRFH9XF8js8Ip+9uihB0Se4IOL2lp49129PfzA4SHGsp0SPqJ/yO2/4A7yaNjTb+oL9om4i7GCNpFuS+sDgQEDAnPQILHpT5b6bkzcvFinNyXUq2lzxx0aeNi+XbNz4i0tEo0XpP4HxzTrPPURA6nkJiAQcNlJMV/Slau4ji/pSi35IUGa8Mf1gt+JiNUFK5pevQLTZD3h7+UPNOp7+c//WUF1tcYQVq6EH/8YZlHJvb/S96efHbuabz1ZydHn9KcJYfBz8wBw27ZpahPoCzJrVsYXXw8/iZC09OrwMyxe8OfzzzUVtrAw9H6fTz9fbCqtMcaYLJW2BYtF5HbgQrQN+GjnXHgfTm8CfdhXsRDefcGT7Vu7nUkjZWVaf8Y7WMnJ0VqRH3+sBzJDhwbqF0ybpsvp0+GJHy9ge5Om+G9vLObxHy+koiLQ/XrRIj0gys/XbYIPLvbfH265xV+jMsqBw/9xPx8TyO6pw8cHMoSrmMEoXuAtvhYSNWwpIJPWQZpInIMNG+B//wvctmuXFh+KZ/qTpb4bEzcv1vnAA3pM62Xg+HwaL73ttkAt3dbMaNHARjHzOQeAG7mCgaylkN3NOk8F+w0zGcIabmESQ1jD84wOCdJEC37PJ/6MilhdsKKZPTtQ98eLG0R7L78l9wreYSgNX1Rz5JH6ObKCcipvKqWkBD5tKOWLASMY57t/z9TYEJdcopG1SZPgv/+Ne79AAyQhZ5cizY3LBrvCyhnW1dlUWmOMMVktLYM3InIz8HNgMxq4WRNhtXX+Zb8YD9U3bN3gnw9McDuTZhYs0IDNNddofdzjj9eDGa/7yvDhoUkct90G/69vJYcVaF2EwwpWM7ugksWLA92vL7kEliyBZ/er4L81oQcXazaWMP7vFVx1VfQDhxcYTVWu1kXYQTF5NNC9Sw33cgkvM4rnGd3iP13aTomKV21t4FR/bq4eJXXvntoxGdMJebHOH/xAEzy8aaONjYFjXK+W7rnhuatxuJoqtrHXniByHV2oJZ8dLRQG9qY/zaeCDxnEVKYBgSBNCdsTzpqJJFoXrEjy8jRIP2iQPkezZmmg/3/dy7i+SDMydwS9lw9pXMVQVnHgO09RUxN4S/MSCb3A2F+bRnN33gQgqA7MBRfAsmXau/2222DgwNDq+vHyIkyHHpr4tu0g6ScTvLMkRUVw8MGh9+2zT2jQar/9NBPHptIaY4zJYq0K3ojIISJyuoicJyJjI11aOyARmQVcDnwBnOCcWxVlVa99+FARKYyyTnnYugDvAbuAfUQk2umbIyJsZ9JMZSV8+CFMnarBmd27Q+s7eAcvFRV6gDNmDPzwxnI+bSiluFjPnG4/aAS7dwfqIjY2auzhkSFVbJCw6QGuH0P+MJ1f/1rXDT9w+CELKS+Hm45YQA3F7Jo8Dcn30bPuE57iZLZTwnQCvcZd2DL8tmhBnESCOykPBDU26lHPiy/G13XKm78Wb4cqYwygNVqamuDKKzU4MX++/iuNGxd4f/RiAZGycMKzc+ZTwVt8jV58Duh7SRG7WMsABvNB1MLAwaJltUzktoSzZqB5/ONGKjlEVnNbTuwixV27wp//rJ8Zc+fq58akSVrHrLAQfiwLyCkpZsGh03AI/48f7wnc/65JA06PNFXsqVN8xRXwve/pc1xcDBcULwDg9f1P1V/4pz/pGYQVK/SDp6oqtPhuBOHv+U3k8GfxP96b6fNVpE0BnOB5zt6TOXCgXvcXed5jxw59zgoL9YW/80746CObSmuMMSarJRS8EZGjReQd4B3gCeBB4HdhF++2hInI9UAlsBUN3Pw72rrOuQ3AG4APOCvCY40EDkCnXb0atF0d8Bf/1XMibDcQOAqoA5a2Zj9MxwifYTN3bsudpsPr4ZaWam3dYH36wOR7y9gysQofdTQi+Kjj2rxpuIGD6NNHHzu4fe6hOavxXVXJvHnwzsmVPNd0LHvfdg25jfUAHM1rFLOT3LD239GKEEebTtXaAk8pV1MTX90HL20qw2tEGNPRDj9cgzeDBmmwZvhw/VfatEkLFy8JKvcfra5scHDEC7x46ulCEzl8Sp+4iwrHmtqUSNaMx5sm61lBOZtcKU1NzceSm6tTa4uL4ZBD4MQTdRZm8OfG8uX6/Fyzs5LFN6zmKw9OYvvSl6ntGRpw+rygHzeUTN/zuXHnnaHZnd1uv5YvXljJgK921WDDtm36CyoqdIPLL9fskmHDWtxH0PftRoRTGpe0uG7GENFidLm5evGezJ499YX1PrgLCzWgc9BBev/06YHi9TaV1hhjTJaLO3gjIgcDzwKHosGQj/x3/T9gBew5Kl0MxNF8tNnjTwcmA9vQwE08p5pm+pc3iMiePkAi0hOY5796vXMuvFzj9ehx8GQROSJouxLgAfR5meec25bofpjUiafTdHg9XK/wMQRqIfTtq9scuX4BLtdHLo56fPygcSGlpVrOpb5eDxx2U8C7DKUup4BfPDyCUaPgtKpyruBG1tQeSE2DfiGtJZ8GQk8bNwH/CjrYEFouBJk2wZjWqKjQo8NInUIqKjR93kubSqRDlTFZzPvX8Qqtn3OOFua92p/kN3asNujx+QKzUIIzbPLztcPeAw8EOjVDIPACsIMiBMfF3L1nClQ0B/Axu8jnAD4Gok9tCg5+t5TB0xq9eun7/No3q3lxc2g2n/dWdI7/9M0KyvnBuFKOOgoue+RI7ho0Cx/11Pk04PRI2TSe+WAQr7/uf+9fodvtye585nz2GzWMfedUQf/+odN99t4bbr9d033++Ef9gImQ+hR+SxcakdTnTiZPly7w+uuaArV0aeBDeORIrWXjzfmrr4cbboD777fi9cYYY0yYRDJvrgSKgEucc98ElgE4585xzn0DOAx4HRiC1quJm4h8D/it/+oHwGUi8mCEy5XB2znnFgF3Ar2AlSKyRESeANagQabFwJzw3+ecWx60P6+IyLMisgD4EBgJ/BO4KpF9MOmhpU7TkerhFhdrWv111+myuBj+0b+CXQuXIP7MmS7U8133JJe+UhGS+e21l33t6qe47bZA5s+HlDHdV0UX6mkqKsaX28A6/1nsJvSLeg1FlLMi6r7ECtRkRNvwSAoKIncKqapqOW3KplQZ00z4v47PFwhEg94+YADMmBEIbOfkBOIHtbVw1VXwk5/APfcE6n+BBl52UMI1VLGTYr7DczEzbQAmcwMF1HEFNwLRgzSJtAWP5dhjQ6/7fBpQEdG3ip7Ll1L4UWg2X5U/xhIcQxEJNDK6oGgBuV2L8V03jdyuxUwo1cB9VZW+LXnPb7O3qbIyrdUSXGh30yY47zxNfyor06r3XoV9ryZYeNtEMux9vSUiuu/Tp8NJJ8GRR2odtIED9cMaNG2svl7XXbjQitcbY0xrTJ2a6hGYdpZI8GYUsMY5d2+kO51z/wFORQsBT0lwHMH9k0cA50e5nBTh945Hpz+9gQZeTkQDQBOAM5xzESeaO+dmAScDL6C1cU4D/ocGkUY652oS3AeTBlrTaXrmTFizRrdZs0avH3B/FZ/5BuzpGlVPFzbkDuS3bjrf/S48SgU7grqllFWNZcx5JTy9T8WeA6Qx9QtwhcXcWDyNna6YAfIxQuCfroSauFqutvQlPqOycXr0iNwpJJ60KZtSZUwz4f86jY0werROjcrPD/wrvfyy3j94sK4TPHXqggs0G6W8HJ58MnB7ItkxH6Etsy/1J71OYA5NCAs5KylBmmhee03jIF49n/p6+O534YZPKiguDWTzubFjqckpoe7MCsrK4PrrQztVe7N6Bg2CfWZWkrNGP0hy1qxmn5m63/G8TdGtW/OATHCEx6sg7bUBy8mBswIzv72Xpdn7urduqrTUrszn0yyjSOs5F/pELV0KX34Je+0VeJ4KCvQJXrbMsmyMMcaYKBL5JtALrXXjaQQQkT35wc65/wIvAWMSGYRz7kHnnMRxGRVl+0edc8c457o554qdc8Odc3MjTJcK3+5p59wJzrm9nXOFzrmhzrkZzrnaRMZv0kf4ybrBg1tO1oh0gq/f6DL+O0EzZ3ZQTBfqmdKktRoWLIApVPF5fqAluHcK9sZu09m/qJr1JUNZVHgeG5tKGbj5VQqbtpPrGqIPIobwr8JtDfak1Pr10adDee3DvO4jXtqUTakyJiYv43DwYC0f8hd/Vbf6er0+aVIgsL1wof57BWtq0hk9FRVw2ml6W15e8+yY1SUjojZNupDmLbNr8XEBDyS8P+GJKOExi+DCy/X1GgPo2lVLyjinLcGvpipk6mpjjhadf+abGkRZsEC3LyjQS05OUKZmjKyPlrI7mTYN7r5bB+I90cGBi+AzDN/8pj7RC7TgcXAwXwAJD4Q0xfxKE/nJ8uTmtrxtS497YIwmnUVFsHUrXHihrhs8jvx8+L//gzPPDH0v37RJs5Ty8vQPddo0+MY3kp9lY1mbxpjObupUy7rJEokEb3YQetz4pX+5f9h6u4A+bRmUMcnSpmSNBdo16qVjp1FDMWc6/Zbu80HukDKKbqqiMK+exsLAKdix0wax8vql7Pv5Kr5d8wz9at9nIB+SS/Mv3W3JmMnYujjOwQEHRJ46VVmpp8M//1xrHnhnX+OZUmVMFgsOzAweHPhX8erZ3H57IB7hZZ2EE9HaOPffr9fDiwPn5GgDoO7dI3e9/huj+V1RoGU2wBwm8CLHJbw/9fWh130+WLkSpkwJLSlTUKD7N2eO7v8f/6j77/OFTl3dQTGuTosl/6ByECUlehy/ZAmsW6cXrxtVS1rM7iwvh2ef1chOVZUGK4IjPMGBoXvv1blawS9Yr176c05OaHqUcy1nv0DkAE9pqW7rBZO8Yj/ReL8nOACTk6PtvG++OZBZlJOj++PzaSYN6B9QU1Po2OvrYft2WLs29L3ce9xf/SpKJCxJLGvTGGNMJ5FI8OYToG/Qda+v454Z5yLSBfgGsLntQzOm9ZKRrNH92krqVq7mu3+bxILpq5lFJUVFOuVgxgzY5/kF7Ggqpu43/lOwkyZRfmwJ3S89F4DxzAXgcN6Kmg0jRG4Z3qk513zqVEWFFq/4ub9c1mWXad/3ioo45yoYk72CAzPXXaf/Yt6/yhM3d58AACAASURBVIwZ8P3vh66/bFnzRIzaWm0nHq0TlRcT+OKL6F2vT6vRDJIlnIpDa+Ykw9lna1ZNVZV2kAp/KxgzJnT/Gxs1/jCmfgFNBcXM66kB+LNYuCf2O2+ell8pLdWL142qJXGVYol3/m7we1tenr4ImzbpfZGCMNFeHIgd2Pn8c43G9eih1xcv1mWkKJzPB5MnNx9Dfb3+4dx2m6Y5zZypy/320/diL6Lm82mEbeDAQPDHe5y339YAzu7d+gKKaJbSzJntU5TYsjaNMcZ0MokEb/4BDBWRbv7rS9GpU7eKyDgROQ14HG3P/ffkDtOYxCQjWePQ88vpMUy/pd//Z63VMGZM4ATh3w6v5OtNy6m76wHtOetVLPaFTh3QAE1OSKAm/P6s8v77zb9At/SCtThXwRgD8f2rVFZqk5+cnMDxuwj06aNL77g6J0c7N4cLjiEEz5C5imv5Cis5nSV8lZVcxYyk7NPDDwfeMqLtnzczZv58fftwDu7wVXLZd1YzcO4kDs1dzZyCyo6J/SZSbNfboV/9KjQAE9w6OycntINVJFOmRJ8y5T3u+vW63LlTl+HpVaCdn2bPhq98JfT2vDzNErr99uYtG8OLLt14Y6CoUPA+eS3PvBewpASee07va4+ixJa1aYwxrWfTsNJSIsGbJ4BP0cLFOOc+RVt1d0M7Oi1GCxZXY52aTIolK1nDO3HntYb9wx906sDjj2tL8JG8RPdPVzF+2MtcOP84TQ0POi3tHePkRJg2FS5dgjjtngGUn9/8C3RLL1hrKlEbk4Xi+VcpL9dj67vv1uvebJoDDggcV+fm6mX6dJ2eFE1TUyCx4iHO512GAfAuw3iEsUCzeHZcehVW8w5D6UY1OTmBt4xo++fNjFm6VOMPAK82lPPws6VcfjnsLCnl+9eOSL/Yb2WlZh3Onh16e3194AXo2lXnh0WqW+NVa54xI3K2jheFy8tr/kL4fLD//vrkei+y9/78v/+FrtvQoO3OFy5sHpiKFFHzbjvvPF03N1f36de/hg8+6Jj3csvaNMYY08nEHbxxzj3vnBvsnHsy6LZrgLOABcBfgdnAcOfcumQP1JhEJSNZwztxF9wadsAAeKKwgm0NJdyN9tWdXXcJ9y4phU8+0ZX694/4eOkSoImlXcY4apQuc3N1asDkyc2/QEcrWAzWNtaYOMX7rxKpNEtJSSAwsmSJXiZNgtNHVfOuDGUvaV3B10MP1d8TnDxSUhJ9/S5d4Dv1SxnKKk7hKerqNG4wZUrz/bvlltCZMfX1gfi5z6ezd8KTRdIi9uulCg0ZopkqBx4YyFLJy9OfR40KDLpnT91Rr2iwt+5hh2l7sWjFjJ3TJ6ShQS/ei5Cfr9vccQfcdJPe52XOTJumhYTCXySfL3q9svAn2Ltt1y4NPk2YoI//5psd+15uWZvGmA5iiSqmI7S576Rz7nHn3NnOuROdc79wzn2UjIEZ01bJSNaIdOJu5kwYMWQ7BdSQq03XyKGRnDptUtawq466dZ/uCYJkTS2bWF58UQ9Ijj9er19ySaDzh3cQM25c5ILFxph2Ef4eOXNm4Lj6pJO0DgzAjKOXcqhbxQ8KnuKQQ+J77G5o5kyvwmo2boSaGo3benbsaL5Nbi7Mp4JtjSXc16DRmIcYy3ZKeLixImLcIHxmjBdoLyxsXhMH0ij2G1xE1/ugCS4qfM89gcrSpaWBujCDB+uH0c9/rkGR8KhYLE1NgbSkgw8OBDPmz9f7rrwycNsPfgBXXaUvSnGxLq+6KnLWSqSIoXdbZSWsWaPTipcv10tHdn2yrE1jTATWnMlkqjYHb4xJV8lK1oh04m5m6a1skt4R18+lkS4E2qVkQrZNu+vSRYM3zz+v13fv1jPJ3bvrE7pqFZx8cuSCxSajiUgXERktIjeLyGsislFE6kTkUxFZJCKjWti+QkSWiUi1iOwQkRUicqmIxPz8EpGTRORZEdkiIjUi8o6IXCUicR7pdn4tvkf6540OqtJAyn31Y1n5UQnP96qguFiDItGcnquZMz8oeIpt26LX2g2umdvUBHkzqpB+gWhMPV34mH5smTg9JG7gxXx9Pp2tGhxgLyrSBJGiIu1cnVYdoqMV0b38cl1WVemOPPdc6AvivVgzZ2oa0m23aVBk5ky49dbYARwvolVQoFmhS5fCffcFghmHH65P/qBBoQGON97QMV15pb6Ar72W+P4G/5EtXw4ffdSxXZ8sa9MYY0wnEvXLr79zVJsl63GMSZVIJ+7GTiujx2G9EaApL+hPvLBQgzURjiuzOgOnvl4DNsEFMuvqtL3sT3+q12trA/dbYcnOZCQ6rfZyoB/wOvBHYAtwBvCCiFRF2lBE5gLzgRHAMuA5YAhaZ22RiEQoAgIicgXwF+A44A20wH5P4FrgRREpStbOdWphaS3SpQu5A/vxUNl0nNNpVcEGDYLHciqoySnh96LBidlfjmVLXQmPSWggNicHfvMbjdl27QoXXaTBlsf/XUbhrCqkQVt85+fUc33RNP62PjTjw0tcmTUrMFt12jR9jOOP1/fr66/Xt5i06hAdrYhuvHO7IgUjysr0AoHpVCIarPFqzRQV6XvwNdfAKafodhMnapC8yv/vN3asvoi33KLXvQ+/gQM1uNPawId1fTLGGGOSItaZy/dFZKxIrP6T0Yn6CfB+q0ZmTJqImBE+pBrfqn8DkPOjHyLB1T2LisA5HIGsm+B/oqwO4sTivdUUFVlhyc6lCe1E+G3n3P7OuVOdcz9yzn0F+DHatXCKiBwbvJGInAGMBzYBX/VvNwYYDPwHGANMCP9lIjICuB6oAY5xzh3vnDsLGAi8DBwJSWqD1NlFKfj6298Nol+/QPwhP19LtzzzDBz/jyrodyDivzPH14X6Pv34rQsEYrt00bfLDz7QOjZr1sC992pCSWUl/vpXxbhrppHbtZi7j1+4J5bhxQHOPVevz52ry1274Oqr4YQTNA5cUhJI5IsWK/Cydzo0MydaEd3jjtNLdXXrMkRKSzUK9vOf6wtSUKCtuY84Qu8/5RRd3nVXYJuWujHdequ+B3tBl6lTWxd0sa5PxhhjTFLECt7sAH4HrPGnmh8YzwOKSD8RmQKsAR4Avmz7MI1JIxUV+kXZqx3whz/ol9FvfUtPH9fWAi5qzZusnUaVm6sHFNHa2TqnhSq8aQNWWLJTcM79zTl3pnNuWYT7/gA86L96btjdv/YvJzvn1gRt8zkwzn/1ygjTp65E/81ucM79M2i7HcAFaDBpvIjs1cpdyi4R5o2Gxx8aG7XZ0aBBsN+RmjkTHJy4r+80NhUP4qKLNL5w8smatVNZGWVWS2UleR+uputUzUIpnFK5J5bhxQEizRLae2+tvTtnTnyxguCyMx0q0lzcaIMJjjDFijbNnBmoLXPrrRrNWrFCiws5B3/8o663fHkgAOO9kHV1GjyvqwsNmicr6GJdn4wxxpikiBW8OQz4BbAXMB34SERWi8iDIjJZRC4SkR/6l5NF5Pci8j6wFpgGdEfPin69vXfCmA5TUQGLF4dW3mxo0JoC992nRyWNjVEDNFmdddPYqGn7zkHfvpHXKSiwwpLZ503/8gDvBhE5ABgO1AHNonjOuZeAT4FeaCaNt50PONl/dX6E7dYCrwI+4JTkDL+Ti1LwNTj+UFQE//d/QTGFsODEBcUL+fBDza5Zs0azbU48MUZySYw6JV4coKGheRx40yZtvnT11bFjBSmfxRP8nB57LDz5ZPTBBAd1YkWbyst1GlRwylFFBaxcqT97LbggNACzYIF+fjmny+CgeTKDLtb1yRhjjGmzqMEb51yTc24OWqPgMuA9NF19LHAdcDfwmH95HXAeUAasBH4G9HPOzXPORelfaUwGqqrSgo9eAUhPWRkcdBC8+mrEzbygTdZm3Xjy8uDoo+GzzyLfv3WrrjNxohWWzB6D/cuNQbd5Qf93nXO7omy3PGxdgIOAImCLc+7DBLYz0UQJpATHH66/XosG74kphAV89plZ2baasWEZJ14cYLD/Lyd4crcXl4gVK0j5LJ7g5/TGG2HAgOaD2b49NMJUUQHnnKM/R4s2he+YSOiT4133AjAVFZoCVe8vsF9fr4Gk4MdtKegS79wz6/pkjDHGtFmL3aacczudc3Odc0PRQpEXA3eiNQz+CiwC5gEXAgOdc19zzt3jnKtpx3EbkxrBZyJBT/0WFekX8f79Q78ow566N1kftPF06wbXXafPW3CbmWAHHmi1ELKEiPQCfuK/+njQXQP8y/UxNv84bN3gnz8mukjbmQRFSvTYE1O4NckdfsIyTrw4wMMPw803B96GIRCXiBUrSKtZPNEG490WHnyB6NGm8McS0Scn11/X+7zzQgMwVVXNA0cDB+rjekGZceNiB13inXtWXq6ZlUOH6tKC88YYY0zCEmoV7pz7wDl3n3NugnPuh865E/2FJy9zzv3OObeuncZpTPpYsECPFK65Rgs4HH+8fgmeMqVZP1yJ8nPW8QI1W7bA97+vBxfBnaeCfe97VgshC4hIHvAIOsX2eedccO+iEv9yZ4yH2OFfdk3CduFju9jfknzF5s2bYzxUdmuXDJbgTI4o85vKb62gtFTjAa+9FuiwXVISiEu01CE6rWbxRBrMpZdqDRrvRAHo50teXuxoU/Bj5eTo5dJL9bNq9+7QAEysKJYXlNm0KfIT2Zq5ZykrMmSMMZ3Y1KmpHoHpQAkFb4zJSMluKVJZqW1Rpk7VL8JTpugX2jvvTM7jd0bBgZqtW2Ove8cd1kY2O9wFjAY20LxYcbR63y1p7XYh/NmjI5xzI3r06NGWh+rU2iWDJfgAP47oUGtn46TVLJ5INXD+9a/I6/7qV7GjTcGPtWSJXm6/XYsNVVY2j2SFB44mTYovKJNI5C7lRYaMMcaYzsGCN6bzS/bZvvBTurfcol9Eo33ZTpH5QH/0n7w/Eaq3piufz9rIdnIicjs61XYTMNo5tylsle3+ZQnRefdtD7qttduZVkpaBkukA/yvfQ322SdmdKilDJtoWrtdu4hUAye4rpo3/emqq7SrVKxok/dY1dUaiDnSX8+7oECf2/CTGOFRrNtuiy8ok0jkLuVFhowxxrSaZfakFQvemM6ro872xepdmyLz0eJU69EUhPX+62kfwMnL064o1ka20xKRm4GfA5vRwM2aCKut8y/7xXgor2XZuqDbvJ8PTHA700pJy2CJdoDfrVsazW/qAMFBkeBaNV27avZMdTUcd1ygWnM04Sctop3ECI9ijRkTf1Am3shdWhUZMsaY9mNxDtPeLHhjOq+OOtvnfTENbh/u58KWHeUqILxieI3/9rTW0pQAk9FEZBZwOfAFcIJzblWUVb324UNFpDDKOuVh64J2RdwF7CMi0Y4Mj4iwnWml8GP/wYNbOUs12gH+tGlpNL8pSLKn4wbzgiKRatW0lEkaftLinHM0c+dc/8zEeE5ixBuUSSRyl1ZFhowxxsTFolFpx4I3pvPqyLN9XhFjSY+yxNFa7cRqwZMyXjeUeKYEmIwlItcDlcBWNHDz72jrOuc2AG8APuCsCI81EjgAnXb1atB2dcBf/FfPibDdQOAooA5Y2tp9MdG1aZZqpAP8tJrfFKQ9i+96QZHgWjUTJ8KoUYnXosnP1ylY3jSseE5ixBuUSeS1SasiQ8YYY0xmitKr15hOwjsYmDJFv6wuXAhnntn6x6uuhqOPhldege7dA7dXVmqhyfHjgUCL8GBe9k1HhHcOJHKP5VhzSVLmiiu02PO77+qZ7FdeSZ8DNJMUIjIdmAxsQwM38WS9zAQWAjeIyCvOuQ/8j9UTmOdf53rnXFPYdtcDY4DJIvK0c+5f/u1KgAfQkxbznHPb2rpfJqCiQuvsegmIY8fCT3+qzeMefTTOB6mshNmzNRBw7rmwYUO7jbfVkrKjLSgvD/xcWqqXqip46y1Yt04LwEcKwlRXw+mnw+TJcNFFNJSWsuWEE6i+4AIaams1UO4c9Oihnaz+85/Iv7+kRDsDbtmi14uLo68br/Z4zDSQl5dH9+7d2WeffcjLs6/Uxhhj2pd90pjOLdkHA8FnW88+W28L/zIfJnjqVEfl5cxAa9wET50q8t+eFnJztbbNIYdots0vf6mv0+LFsGgRXHhhqkdokkREvgf81n/1A+AyiZyh9p5z7nrvinNukYjcCYwDVorIX4F6tENVN2AxMCf8QZxzy0XkSuAG4BUR+RsaNBoJ9AT+SQbMIMw08cQWWhQpaJFukrKjreBlkp59tgY+amubZ5J6n0933klT9+5seOQR8ouLObCoCF9jI9KrF3z2mZ54KCtr3/FmAeccdXV1fPHFF2zYsIF+/fqRk2MJ7cYYY9qPfcqYzi1ZKfexih9XVuqULC9NndAgjQAOYWeP/h0WvDkHuAet9ir+5T1EmEeSKo2NutyyRTOh9t9fgzgAF19sbWQ7l32Cfh4BnB/lclL4hs658eif7Rto8OVENAA0ATjDOdcY6Rc652YBJwMvoLVxTgP+hwaRRjrnwktCmTbKmpq0qdzRaHVjwj+fVqxg68iR5O29N/sPH05+nz7IV74SKKpfXNz+Y80CIkJ+fj77778/eXl5bN26NdVDMsZkG6tJk3USDt6I2ldESkWkS8tbGNMJxCp+/J//aAr6rl36pdifVRBcpDgHR/HmSBOZ2s85aDudJv8ybQI3oM9R//5w112wdq2m8jf5Z780NUFNDWy3Ts6dgXPuQeecxHEZFWX7R51zxzjnujnnip1zw51zcyNMlwrf7mnn3AnOub2dc4XOuaHOuRnOucgpcqbNsqYmbap2NFrdmPDPJ5+PHd/5Dnv174/4fPDll7BypWYLgWbfvPGGvveaNhMR9tprL3bu3JnqoaSEiBwkIr8QkUdE5D0RaRIRJyItzlEXkQoRWSYi1SKyQ0RWiMilIhLz+EREThKRZ0Vki4jUiMg7InKViKRP209jjGkHcU2bEpF9gEuB7wGHAf7+lTSJyHvAn4C5zrmN7TJKY1ItUsr63nvDYYeFTpfavXvPj5pxQ9D1ju45lcacgz59dCpb0HO2R58+cNtt0WsMGWPSTiaUrEmKVO1otGllET6fdg8fTtFee+n9vXtrQLyuTt97RbSAce/eHTPuLFBUVMRnn32W6mGkyjjgF4luJCJzgfHAbuB5AtNi5wCjReSsSNmVInIFOi22EXgRLYI/ErgWOFVERlt2pTGms2ox80ZExqBp6lOB4WjAR/yXXGAo8GvgfRG5IGxbEZGvJ3nMxqRG+NnWbt20dktDQ2Cdxkb9cuwXPn3K+OXmakCmV69AFxQIdOvq21enIbRnRxdjTFKla2OopEv2jiaj7XjY51NTTU2g/kpBgQZqnAsULe7dW283SZGTk0NTU8xkwM7sHeBG4EdAGfBSSxuIyBlo4GYT8FXn3KnOuTHAYOA/aNH5CRG2G4EWpa8BjnHOHe+cOwsYCLwMHEkalfcz2clmMpn21FJa4llot4+90DfnSmAUcAhwqP/nK4B3gWLgPhH5qX/bLsAf0FoDxmS+ceP0i/pFF2nKelUVXHttqkeVebwDCudg8GCtGeHddt550LWrpvNHqzFkjDGdSTKC1OFTqrp1I6Qw+Nat+j7bu7curT5LUkUpwp4VnHP3OeeucM4tcM59GOdmv/YvJzvn1gQ91udoJg/AlRGmT12Jngu7wTn3z6DtdgAXoDPFx4vIXq3ZF5MdLLhiMlnU4I2I9ADu91/9hXPuMOfczc65l51zq51z7/l/vsk591VgIjpL5HYRORidSnUG2FwR00ls3Ajvv69fsL2zrcuWQVFRIPgAEN4uNC9PAxJZJuo/flNToGDx009r5lJxsT5Hu3fDmjXaOjxajSFjjOkMYhXCT1R4NlB+WOmPXr1g2LDQpTEpICIHoJn8degJ4hDOuZeAT4FeaCaNt50PLUQPMD/CdmuBVwEfcErSB26MMWkgVubNZUAJ8Bvn3OyWHsg5dzvafrUAWIF2DvkAeCAJ4zQmdVrqNDV6tAYerrlGvzAHT6MCvZ6FxXfjPg/p82mL8DVr9PksLYUxY7KkdY0xJmvFKoSfbMXFob/HOk6Z1PHKKbzrnNsVZZ3lYesCHAQUAVtiZPhE2s4YYzqNWMGbk4EvgJsTeLybgS3om+u7wLedc5+2fnjGpIFYX7DLy2HKFE1TnzoV9t03pUNNpWiZNi2m3jU1wX33Na8dkTWta4wxWSlr+qsbE2KAfxmrBefHYesG//wx0UXazhhjOo1YwZuBwKuRKr1H45xrAF5Bj9dG+ueuGpPZysrgyisDrcDDv2AHp6vPnq11XHJarAVuPI2Nkc80R2uLa4wxnYUFqU32KfEvY/VW3+FfBs85b+12IUTkYn9L8hWbN2+OOVBjjEk3sY4wi4HWzPXYDjQ457a0bkjGpKF583SZmwuFhXDhhZE7g/zgB1oIMgu7ToRPk3JRbm/m3HMjn2nOmtY1xpisZUFqk328rwWJ1sRs7XYhnHP3OOdGOOdG9OjRoy0PZUxUU6daYWTTPmIFb/4H9G/FY/YDLJRtOgev3s2KFXr9yy+hpkaX0TqDHHpox40v0xUVQW1tqkdhjDGp0YmD1A0N8M47zcvAmaznnRguibGOd1/wSeTWbmcMYMGUNrFoVNqIFbx5HThCRA6M98FEpB/wDf+2xmS+qirNtmkMmj3o/XzOOTo96swzQ7e56Sa45JKOG2Oaippx400pE4Hjj7czzcYYkyaSGXCprtYGgpGSVE1WW+df9ouxTt+wdYN/jnVcEmk7Y4zpNGIFb/4A5AIP+NvzxeRf5wH/Y/4hOcMzpp1UV8PQoS1/qywrg2uvjXxfXh44B9/8Zujt5eWwdKn+7J1RNQEFBXDSSXD77VrsuROdaTbGmKSI9zOqHX5tWwMua9fCG2/AunV6fd06vb52bTJGmDxvvfUWp59+Ovvssw/FxcUMHz6cBx7QBqkigkjcPRNNYt70L4eKSGGUdcrD1gV4D9gF7CMi0ap6HxFhO2OM6TRiBW8eA94AjgVeEpHDo60oIsOBl4FRwFv+bY1JX0uXwqpV0ac+BVu2TKf3hBchrq/XZWVloHW459prYeVKeOwxrZEDsNdeyRl7puvbF+bMgcsus8CNMcZEkshnVBIkM+DSuzf4fJpcCbr0+fT2dPG3v/2No446iieffJLS0lK+973v0a1bNy6++GIqLRu0XTnnNqDHFz7grPD7RWQkcACwCXg1aLs64C/+q+dE2G4gcBRQByxN+sBNp2Azf0ymixq8cc454Pto271vAMtF5G0RuU9EZvgv94nIO8C/0Gj3BuB0/7bGpB+vhs355+v1sWObB17CVVbC6NHQtWugnk1+fuD+4NbhnvPPh2HD4MMPtUsVwLZtyd2XTJOXp8vNm2G//VI7FmOMSUet+YxKgmQFXKqrYfhwHbJzes7DOX2cgoLkj7s1ampqOPfcc9m9ezdXX301q1at4rHHHuOFF17g5Zdf5q677kr1ELPBTP/yBhEp824UkZ6Av0ME1zvnwrs/XI8WLJ4sIkcEbVdCIPt/nnMuy79wGWM6q5j9jJ1znwCHo9OgHDAM+D/gSv/lAuBQ/30LgOH+bYxJT1VVcOCBGnCByIGXcOXlOr1n9Wp48EHNqJk2TWvhFBQ0bx0O+kU7Lw9++tN23Z2M4nXg2rJFp5O188GIMcZknNZ8RiVBQYEGWNoacPEShhYv1sfp3VuXW7e2z7hbY9GiRWzcuJEhQ4ZwzTXXhEyPOvrooxk/fnwKR5d5RORwEXnNu6DHDQDXhd2+h3NuEXAn0AtYKSJLROQJYA16XLEYmBP+u5xzy9HjjyLgFRF5VkQWAB8CI4F/Ale1z54aY0zqxQzeADjntjrnzgaGAL8EHgae8V/mAxOBg5xzP3bOfdGegzWmzcrK9MtxfT0UF0cOvEQyZAgcd5wuhw2D11/XU4vXXquPs3Bh6Prbt2dlu/CYgp+P2lr9dm8BHGOMCWjtZ1QSbN3a+oBLeMJQZSV861tw+eX6kdmrV/uMuTVeeuklAH70ox+REz4dGqiwz6VEdUMz9L1LV//tg8NuD+GcG49Of3oDDbycCHwATADOcM41hm/j324WcDLwAlob5zS0Q+5vgZHOuZpk7ZgxxqSbFoM3HufcWufcHc65851zp/gvY51ztzvnPmzPQRqTVAsW6JfiadMiB14iCa8/UFmpmTiTJukyfI78rbemT454OvL5YMCAdj+bbIwxGac1n1FJ0KtXINCSaMAlVsJQly66G+ni008/BaBfv8jNjqLdbiJzzr3onJOWLlG2fdQ5d4xzrptzrtg5N9w5NzfCdKnw7Z52zp3gnNvbOVfonBvqnJvhnKttn700pnWsxo5JtriDN8Z0Gi0FXoJFqz9w662BTlKlpYHCu16HkB494KCDoj+uV//F+6abbTrwbLIxxmSURD6jkqi4ODT4kkjAJYUJQ60WrZtUpGwcY4wxJh3YJ5TJTG1po1peHjnwEkmi9QeCM3T23Te0AqTH54Mf/lB/zrba3kVFcM01uuygs8nGGJNREvmMiqWhAd55R5fJXDeKFCUMJay3vwrz+vXrI96/zmu5ZYwx6WrqVEvryVIWvDGZKdE2qq0N9sR7OjFShs7f/w6NEaZs19XBo4/qz234opyRamr0AOHDD1s+m9yWAJ0xxmS76mrYvTu+99BE1oWIwZ4UJQwl7Nvf/jYACxYsoClCbbrHHnuso4dkjDHGxMWCNyaztLaNaqLBnmDxnE6MlKGz334avOneHQYOtBo43lSx4cPjO5vcltfMGGOyVUUFfPwxeBkk69bBG2/A2rXN1127Vu+LZ91gEYI9yUoYam9nnXUWpaWlvPfee8yYMQMXlAH7z3/+k7lz56ZwdMYYY0x0FrwxmSXRaUytDfYE804nXnSRfiMdNy5wX3CNGy9DJzcXdu2CTZt0nW3b9It0ba0G0m52WwAAIABJREFUf7J1Pr13hva3v9XX4MwzI2fWJOM1M8aYdNaemYVVVRos96bsiuh0Xf90oRC9e4dO7421LrQ+2JNGiouLefjhh8nPz+fqq69m6NChVFRUcNxxx3HMMcdw0UUXAdAlW2vSGWOMSVtZehRpMlaiVRETDfZE4p1OXLoU3n8fNm4M3BecHeJl6Hi54sFTphoatL7N4MEavPEubeTClhmhqUmnT61dGzmzJhmvmTHGpLP2zCwsK4O99tLPnJwcXfbuHTn7s6BA74tnXUg82JOmTjjhBF555RVOO+00Nm7cyOLFi9m6dStz585l4sSJAOy3334pHqUxxhgTyoI3JvMkUhUxGS0wImWC5OXpJfi2JUvg2GNh5kyYMSP0Mbp0gSFDYNEiXe+YY6BrVy3eW1iomTuZLidHv8SDLvv21SykX/wC+vRpvv7KlboMz6zJxLYlxhgTj47KLNy5U9+Te/fW5dat0dfdujX+dRMN9qSxww8/nCeffJKtW7dSU1PDm2++ySWXXMKLL74IwPDhw1M7QGNMUlht3ySyJzLlLHhjMk+iVRHb2gIjUibIgAHQv3/z7JB33tE0+Lfe0o5KXnZNQ4MGdAYNgpNO0rGUlur6IrB5c2JjSkdFRZpVU1ysy0MP1eyjxkZ9/oIVFMTOrMmUtiXGGJOIjsos7NYNhg2DXr0Cy2iC12lpXUgs2JOm/vvf/0bsNvXaa69R6f9O8ZOf/KSDR2WMMcbElpfqARiTsPLywM+lpYEKidFUVsLs2breuefChg2J/T4vE+TsszWQUFur2TUQetuJJ8Idd2gafGWlFnN8+WX45S/hpps0AHHmmbrdxo06BetnP9PU+Q8+0AyTwkK9bNmS2BjTRXGxLnfuhGee0Z/nzGm+3u7dgfVra5tn1rT1NTPGmHQU6fOkPTIL8/NDA0Sx6rd479vxrAsa3PECUPvuqx0UM8zbb7/NCSecwLBhwxgwYAA+n4+1a9fy5ptvAnDeeedxxhlnpHiUxhhjTCjLvDGdXzJaYETKBPFuGzxYM2tmz9Z1x47V6VO1tZoZNHWqtsYeN047TxUXB1Lmr7hCa780NOjtu3drgeNWSmntm5oaDUBFmiIFgSlVBQUaoIqVWZMpbUuMMSZRmZ5ZWFwcGhgKDv5kiIMPPphx48bR1NTE3//+d/70pz+xfv16jjvuOB566CF+//vfp3qIxhhjTDOWeWNMPCJlgmzfDv/+NzzwAPzoR4GOUl4a/Lx5oQGI55+HL7/UVPOtWzVg06WL1s7p0iUwKXfnTr3N684UBwlbggZyJMK67UZEAzirVjW/b6+9YMeOwJnm6dPhO9+Bo46CV1/VaVbGGJMN0jGzsKEB3nsPDj5YP386uQMOOIB58+alehjGmCxgNXdMMlnmjTHxiJQJ4k19eu89uO46re0SqcBueIHKzz/XVuK5ubrub36j06YmTdIvzs41D9xI8zBMtCwbRwoCN6ABmNLSiGNl2zbdp8GD9Tl68024/35Nt//d7yyzxhiTPdIxs7C6WjM/26N1uTHGGGOSIuuDNyJSISLLRKRaRHaIyAoRuVREsv65MVFE6hby4x9r0CJSGnx4gUrQIo+VlYFAxsSJ+pj++fYhSkrgt79tdrMQX4CmQ6ZSlZbqvgwcGDl4k5sb6LZVUqLTBryznnPm6Db9+3fESI0xxnjWroU33oB16/T6unV6fe3aVI7KGGOMMRFkdYBCROYC84ERwDLgOWAIMAdYJCK5KRyeSVeRuoUceCAsWxa5A1Z462uAu+/Wosfeut5jenVhQAMaubkaELnuuriHFx7U6ZAMnLIyzR7yOmwFd5PKzdV98bpt/f73ofsJev2BBzpipMYYYzy9e+v7rxd0F9HrvXundlzGGGOMaSZrgzcicgYwHtgEfNU5d6pzbgwwGPgPMAaYkMIhmnQVHoypr4dZs+Ab39D7I6XBBxeoLCmB554LrDt4MJx+OkyerI+V648ZnneertunD/Tt23H71xrduum+zJwJS5bo2duTTtJgzoQJodlIo0frbcEmTIDjjuvwYRtjTFYrKNBAjXMaeHdOrxcUpHpkxhhjjAmTtcEb4Nf+5WTn3BrvRufc58A4/9UrbfqUiSjRbiGVlbB8uWaXLF8empmzdKkW+b3zTn2sSy+Frl21/sDq1RoouvFG/WLd0UR0WlikqVCeHj20axZoLYeTTtIv/u+8A2+9Bbfd1jwbacECXZ56auh1Y4wxHWvrVv186d1bl1u3pnpExhjTqVjRYpMsnb+lQAQicgAwHKgDmh11O+deEpFPgT7AkcArHTvC9PP0vR8z6uLBvHjPGk766YGpHk7qJdotpLwcHn1UgzQrVsDZZ2vtnCef1O5LoLfn58PmzbBmjT5maaleZs3SgM727R3TmSk/H772Nc0EevzxyOvk5GhXks2btXhzsKVL4aOPdJ8GDw7sh+faa2H4cBg2TIM8b7zRfvtijDEmul69AlOB991XC8kbY4xJTxYFymrZmlXydf/yXefcrijrLA9bN6t9ctkNFFDHhstuTPVQ0kMi3UIiFTguKdFATHDtHJ9Pi/ZOn978MSsrNXulVy+9ftJJ7ZuJ09CgbdA3bdL23y6s7HFurgaRvC/53j717x95XysqQrc//3wN3IAux45tv30xxhgTXXFxaA03rzabMcYYY9JKtgZvBviX62Os83HYullpnfTHiXBhrXYGuqh2Dk6EddI/dYNKhupqGDq0Y9qiRipw3K+fTicKr50T3GI82K236u2ff67Xn3mmfTNwfD4tlPzQQ80LV+63H9xxh2bU5OeH7tP990fe1+nT22+sxhhjjDHGdHaWdZP1sjV4U+Jf7oyxzg7/smv4HSJysb+l+IrNmzcnfXDp5PGT76eW0M5Atfh44rsZ3hnIqzPz1FPt/7siFTj2gjTx1s4J70aVn69TltrL7t06ptGjA8WSvULKe+8N48drB6zGxtB9Gj06/oCUMcYYY4wxxpi4ZGvwxqu+6mKuFYVz7h7n3Ajn3IgePXokcVjpZ9JTo3mgUDsDeU/WA4UTuPzPbegM1JFZL+GiTWEKn9aTbNGCNN50qEgtxoNFCgB169Y+U6e8v+n583X50Ue69KZOffCBPmeXXx55nxIt5myMMcYYY4wxJqZsDd5s9y9LYqzj3bc9xjpZ4bRdC3DAUjkVB5y6q42dgToy6yVctClM7T2tJ1qQprxcOzMNHarLWLVzgoMiPh9s2aIBla9+NXQ9r2V5a4hoMWXnAmOZNy90ipTPp8/Z7bdH3qd4A1LGGGOSyzs50hGF7Y0xxhjTobI1eLPOv+wXY52+YetmrYeGXMsjlSs5tWkJj1Su5JGDZrTugVKV9RIs1hSm9hSrwHG8wazKSjj2WLjmGh03aJDl7bf15299S5dvvx2Y4pQIEX282bP1+tSp+vosWqRTpLznrLFRn7MxY5rvU3U1/OQnGoiKtK/GGGPaj/d5sitaLwZjjDGmDazuTkpla/DmTf9yqIgURlmnPGzdrHXV6vMZO0s7A42dNYzfvNfKzkCpynoJly7TehINZpWXw403amCmoSH0Pp9Pu0O98gpccQX8+c9w7726rpcx0xLnNIAj/lmFwa9PvM9ZKrOqjDEmW4V/nvzvf/DGG7B2bWrHZYwxKWRxBtPZZGXwxjm3AXgD8AFnhd8vIiOBA4BNwKsdO7pOLFVZL+FaOa0n6aV6WhPMKiuDa68Nvc3n0zo1X34J69bpJ9VJJ8Gzz+qX+RkJZErtvbcGb8Jfn5aes3TIqjLGmGwV/nkiop8N4d0CjTHGGJOxsjJ44zfTv7xBRMq8G0WkJzDPf/V655xNHE+mdMh6iTWFKYakJ5W0Npi1bBkUFQWKFdfVwcaN+vPYsfpY3bvDuHGBgMtee8U3pi1bdFrU4MGhr09Lz1m6ZFUZY0w2Cv88cU4DN94UVtPMzp07mTVrFuXl5XTr1o3CwkKGDh3K1KlT2bFjR8sPYIwxxnSwrA3eOOcWAXcCvYCVIrJERJ4A1gCHAouBOSkcYueUgcVs2zWpJNFgVnU1rFgB3/42dO0Kl10WmOYEGjTZe2/Nwtm0KRBwGTcu/jENGaJ1brzXJ56Uo3TJqjLGmGwV/HkiAlu3pnpEaeuTTz7hiCOOYPLkyaxfv56jjjqK73znO2zdupVp06ZxzDHHsNWeP2OMMWkma4M3AM658cA56BSqkcCJwAfABOAM51xjCofXObUy66WZ9mo3HuFx2zWpJNFg1tKl2rr7mGN0/TvugHvu0S/qublapHLTJl137FjIy9PLjTc2fyxvh4Ll5uo0q0GDAq9PcMpRrOc9HbKqjDEmWwV/nvTpA716dfwY2uuzOYmcc/zwhz9k1apVTJgwgXXr1vHMM8/wpz/9iQ8//JBzzz2Xt99+m4kTJ6Z6qMYYY0yIrA7eADjnHnXOHeOc6+acK3bODXfOzbXpUmmuvQrjRnjcdk0qiTeYFZ7+4w2goiJQ26ayMjCVCjQ4M2AA9O8fGqgpLtal17HKk5en23tBl/DfWVEBPXtGf94zMKvKGGM6jeDPk9zcwHt9R8qAovVPP/00r776KkceeSS33347RUVFe+4rLCzkrrvuomfPnsyfP9+yb4zJYOlYrDgdx9RqU6d2sh3KDFkfvDEZpr3mMLXwuClPKomV/uMFTWbOhLvv1vu9KNPMmXD99fpzfr5+oe/TJ/rvWbYsEHQJ/52g9XUg8vOerKwqY4wxmSWDitY/5Q8snXHGGeTkNP8aXFxczIgRI2hoaGD58uUdPTxjjInMAiUGC96YTNNec5haeNwOTyoJTz2Plf4THDTxsnCCo0xe5OmQQ7QY8Zo1kX/nxInwjW8Egi5lZbDPPjoVK1xTU/PnPQPS5Y0xxrSDDCpav9bfPr2yshIRiXjxAjybN29O5VCNMSY9WSApZfJSPQBjEuIFMc4+WwMStbWtm8NUXQ1HHw2vvKKdmVp43PLywKalpYFYSbsJTj0/+2y9zQvCTJmiX4gXLoQzzwzdrrISZs/WAZ57LmzYoF1HZs+G7dvhlFPg4491/zwiUFgI69c3H0fXrjqVKicHGhoC64s0f94jjdkYY0znl6zP5g7Q2KjlDEeOHEn//v1jrtuvX78OGJExxhgTH8u8MZknGXOYIs3LT/ncKGKnnseT/hNp6pJ3W1kZXHedZt/k5uo6Z54J3brB8cdHfryqKp2K1RRUAurcc3VM0WrjpHG6vDHGpK1Mz15Mh8/QOPTt2xeAs846iwcffDDm5Zvf/GaKR2uMMcYEWPDGZJ62zGFqa3CkvcVKPU9GTRnvy/WECYGsmtWrNZsn0uPdeiv87GehwZtHH4Vjj41eGyeN0+WNMSZtZUCx35jS4TM0DieffDIAC9M0uGSMMcZEY8Ebk3naEsRo7+BIW7VraysCX65vu01r31RWxt7Xqiro2xcKCvR6QYE+fzfdFFobpz3HbIwxnVlnyV5Mh8/QOHz/+99n+PDhvPTSS/zsZz9jy5YtzdZZu3Ytc+fOTcHojDHGmOgseGOySyYEGtoz9TzRL9dlZXDjjVrvprhYl7NmNX++MiRd3hhj0o5lL3aonJwcFi9ezFe+8hXuvvtu+vfvz7e+9S3OPvtsTjjhBA466CAGDRrEdHv+jTHtwDpsm7aw4I3JPq0JNHRkLYJ0Sz2P5/lKtzEbY0ymyISTCp3MAQccwL/+9S/mzJnD17/+dd59910ef/xx3nnnHbp27cqvfvUrnnjiiVQP0xhjjAlh3aZM9onUkaklreikFN7QKm4d3tqqBfE8X+k2ZmOMySTxdBM0SVVQUMCll17KpZdemuqhGGNMdJamY4JY5o3JPolMHWpDLYJMrz25R4bUMTDGmIxl2YvGGJM0Fu/oQPZkdygL3hgTSytqEXSW2pPGGGM6iAXJjTHGGNMCC94YE0srahFY7UljjDHGGGNMVrDsmw5jwRtjWpJggWOrPWlMehCRChFZJiLVIrJDRFaIyKUiYp99xhhjjDEmo9gXWGNa0opaBNY525jUEpG5wHxgBLAMeA4YAswBFolIbgqHZ4wxxpgs1mLLcOspbiKwblPGtKQVnZRa09DKGJMcInIGMB7YBHzbObfGf3sp8AIwBpgA3J6yQRpjjDHGGJMAy7wxph1Y7UljUurX/uVkL3AD4Jz7HBjnv3qlTZ8ynZlzLtVDyBr2XBtjjOkI9sXVmGxWXQ1Dh+rSmE5ARA4AhgN1QLMJi865l4BPgV7AkR07OtOZPX3vx+yWfJ6+9+NUD4WcnByamppSPYys0dTURE6OfaU2xhjTvuyTxphstnQprFoFTz2V6pEYkyxf9y/fdc7tirLO8rB1jWmzTy67gQLq2HDZjakeCgUFBdTU1KR6GFmjpqaGwsLCVA/DGGNMJ2fBG2OyUUUFlJTA+efr9bFj9XpFRWrHZUzbDfAv18dYx0uNGBBjHWPisk7640S4sHYeABfVzsGJsE76p2xMJSUlbNu2zabzdADnHNu2baO4uDjVQzEmq1ltX5MNLHhjTDaqqoIDD4QuXfR6ly7Qrx9Mn57acRnTdiX+5c4Y6+zwL7tGulNELva3FV+xefPmpA7OdD6Pn3w/tfhCbqvFxxPffSBFI4K9996bhoYGNm7cSG1trQVx2oFzjtraWjZu3EhDQwN77713qodkTNbL9AZNmT5+0/6s25Qx2aisTAM4Z5+tvcxra7Wv+aBBqR6ZMW0l/mWrj1adc/cA9wCMGDHCjnpNTJOeGs28ogmM23XLnj+6BwoncPmfj0vZmHJycujbty9btmzh448/pqGhIWVj6czy8vLo3r07PXv2tJo3xqRAewQ6Rr04lRdHtcMDRxEcsBn1ovd7O+73m8xiwRtjstWCBRq4mTJFM24WLoQzz0z1qIxpq+3+ZUmMdbz7tsdYx5i4nbZrAQ54Sk7lFPdnTt21ALg5pWPKy8ujZ8+e9OzZM6XjMMaYTBcroOMFXNoS8LGMGxMvO01gTLaqrITVq2HSJF1WVqZ6RMYkwzr/sl+MdfqGrWtMmzw05FoeqVzJqU1LeKRyJY8cNCPVQzLGmE4tmcGOQMZL8+vhP4evmyyR9ufFF9vlV7UPLwJlUah2ZZk3xmSr8vLAz6WlejEm873pXw4VkcIoHafKw9Y1pk2uWn3+np/HzhoGs4alcDTGGGMS1dagTEdPtzLZyTJvjDHGdBrOuQ3AG4APOCv8fhEZCRwAbAJe7djRGWOMSQYRqRCRZSJSLSI7/EXmLxURO7YxHSaZWTghj2XZKyYKe4MzxhjT2cz0L28QkTLvRhHpCczzX73eOdfU4SMzxhjTJiIyF5gPjACWAc8BQ4A5wCIRyU3h8EwGSST4Em0qVWvW66ipWCljwad2Y8EbY4wxnYpzbhFwJ9ALWCkiS0TkCWANcCiwGP2Sb4wxJoOIyBnAeDR78qvOuVOdc2OAwcB/gDHAhBQO0aSxRIM1rQ2qBG/b6QIz8bIATruwmjfGGGM6HefceBH5O3ApMBLIBd4DHgDutKwbY4zJSL/2Lyc759Z4NzrnPheRccCLwJUiMtve50008WbRxPsY8a774qj4gjoZVag4Fi+AY8WMk8aCN8YYYzol59yjwKOpHocxxpi2E5EDgOFAHbAw/H7n3Esi8inQBzgSeKVjR2iMMe3LgjfGGGOMMcaYdPd1//LdKJ0EAZajwZuvY8GbTiU8iSMekbJb2nMaU0uP3Zrf7WXhjBoVuO79HHx/8DrRtg9/rPD1gtcJ3ybadgkLfiG9pWXkxM1q3hhjjDHGGGPS3QD/cn2MdT4OW9d0Ai0d2wdPReqUBYDRIEpL06m8dSKtF23bWI8bfrt3vdXTuoJfSAvYtIo451I9howmIpuJ/SHSmewH/C/Vg+hk7DlNrs70fPZzzvVI9SCyXZa9x8fSmf632pM9T/HJ9ufJ3t9bQUR+A8wA5jvnzo2yzgzgN8A9zrlLItx/MXCx/+pBwOp2Gm4myPb/w0xgr1FmCH6d2vX93aZNtVE2ffiKyArn3IhUj6Mzsec0uez5NMmWTe/xsdj/VnzseYqPPU+mlcS/bPWZZ+fcPcA9yRlOZrP/w/Rnr1Fm6MjXyaZNGWOMMcYYY9Lddv+yJMY63n3bY6xjjDEZyYI3xhhjjDHGmHS3zr/sF2OdvmHrGmNMp2HBG5MISzNNPntOk8ueT2Pah/1vxceep/jY82Ra403/cqiIFEZZpzxsXROd/R+mP3uNMkOHvU5WsNgYY4wxxhiT9kTkdeBw4Hzn3ENh940EXgQ2AX2cc00dP0JjjGk/lnljjDHGGGOMyQQz/csbRKTMu1FEegLz/Fevt8CNMaYzsswbY4wxxhhjTEYQkXnAOGA38FegHhgNdAMWA2c65xpTN0JjjGkflnljWiQiFSKyTESqRWSHiKwQkUtFJCv/fkSki4iMFpGbReQ1EdkoInUi8qmILBKRUVG2e1BEXIzLezF+Z47/OV/hfw2q/a/J2e22ox2otc9NW54X+7s22U5EDhKRiSLyFxH5QER2+/8fXhWRX4qIL47tHxGRz0SkVkTWi8idIrJ/C9v19q+33r/dZyLysIgMSe4edpxseD9p7Wdf0Pateo5E5CQReVZEtohIjYi8IyJXiUh+UnfQZAzn3HjgHOANYCRwIvABMAE4I5sDNyIyqoXvU05Ejoyx/TdE5I8i8l//Z8IaEZklIt1b+L2t+jwwkWXDZ0qqZeqxh2XemJhEZC4wHj278TyBsxtdgT8CZ2Xbh6SIHA8857+6CXgd2AkcCgzz3z7dOXd12HYPAucD/0C/ZITb6Jz7dYTflws8AXwP+BJ9HfLR1yEfmO2c+3nb9iq1WvPctOV5sb9rY0BEPgH6oP8HK4BPgFLgKKAALfh5vHNuS4RtRwJ/AQrRA6g1wGHAwcBm4JvOufcjbHcIsAzYF3gP+DcwGK1hUQN8xzn3j6TuaDvLlveT/9/e3QfdVtUFHP/+uIR5vV4MFdCuCuJFUUuURFEUFIsy3xq11BxkdKhU0qnM1BpfcpwUS1BHU8cc8WVksgbfy1EC06RSQLSLpKhXlEgUBBSu3Lz8+mOtMzzuZ+/zPGc/D3ef8+zvZ2bNus9ee+27zzpn/dbZ6+yXvmNfrdurjSLixcDrgD2Ue5n8kHKwfmfg34ETMvPG9XmF0uKrk6jnAt8D/rljtVdn5jda6j4deC+wifJ97ArgocDdKd/NHp6ZV7XU6zUeqN1YxpShLeyxR2aaTK0JeDKQwJXA9iXLDwIuqWUvHHo/B2iXRwP/ADyipex3gJ/WtnlUo+zddfnJM/5/f1Lr7QAOWrJ8O+ULdAJPHLpd1timM7dN33bxc20ylVS/PDwb2NJYfgjwX7UvnNlS73a1/yRwaqPsr+vyC6g/EC0p2wf4Ui1/faPsD+vyK4DNQ7fNDG04mniyhrGvVxsBvwLcTJkgesiS5VuAz9R6pw/dLibTPCXg+No3zpux3jbKBPqepd+dgH2Bs+o2z26p12s8MHW+D6MZU4ZOLOixx+ANZ5rfRPklNoGTWsqOW/Ih3GfofZ2nBLyzts3fNZb3CRKbKL+eJPDIlvJn1bL/HPp1r7HNZmqbtbSLn2uTaeUEHFv7wi5gv0bZqbXs3JZ6myi/YCXw2EbZ4+ryrwObWuqeW8ufN/Trn6GdjCe3vN6usa9XG1EmihJ4eUu9e1IOMm8C7jD0azeZ5iXRf/JmMtHyrpayrcB1tfy+jbJe44Gp831wTNl7bb2Qxx5eN6dWEbENOArYDXywWZ6Zn6H8Qnow5ZRK3eKimm9bh20dAxwIfDcz/7Wl/IOU0+4eHBG/uA7/36Lo1S5+rqVVm8Sxn6dc4rTUk2r+vmalLKf8ntVYr1nvrGw/Nfj9HfXmkvFkmWVjX982inK/pd+of76/pd43gfOB/YDHrs/uS6M2ibtt/e164KON9Zr1Zh0P1OCYMvfm4tjDyRt1eWDNd2Tmro51vtBYV8X2ml/ZUf6oiHhDRLwjIl4dESdOuVHVpG2/0FaY5Vr/HfXPI/vt7lxZbdv0bRc/19LqTOLYbqB5z5up/Y/uPtS33rwynvystrGvbxvdG9gMXJMt9+aYUk9ScVBEvKJ+nzo9Ip4dEc2JeAAiYitwWP1z7HF9SI4pw1ioY499V1pBo3Vozb89ZZ3LG+uOXkQcDJxc//zHjtVOall2SUQ8LTO/0li+2vfhSDbG+7DatunbLn6updV5Sc0/lpk3TRbWL/kH1D+7+lFXH1qp/03q3SkitmTmj2fY3yEYT6opY1/fNjq0UbbaepKK+wCvbCx7c0S8JDPf3Fh+SM2vrWfZtFnW39Y4Hmg5x5RhLNSxh2feqMuWmt8wZZ3JF+vb38r7shAiYl/KaaP7A+dk5kcbq3wJeAFwP0r73pVyD4iLKU/r+HTLpU9jeR9mbZu+7TKW9pR6i4iTKTegvRF4WaN4y5J/d/Wjrj60Uv9bOlmzCP3PeMKKY5+xWtq7rgNOBx5BuQzj9pSn+b2TchnsmyLilEadtfbTaXXtp6tn3Nu7FvLYwzNv1CVqnoPuxWJ5G+WRb98BntkszMwzGotuAD4eEZ+iPDnjocBLKTd/mxjF+9Cjbfq2yyjaUxtfRJxGeVTlrE7IzCumbPcE4O2UPvL7mfnfzVV6/J9NXf1v0fql8aSYNvYZq6VVWo+4npkXccv9pyYuAk6JiC8DbwJeGxHvWXJW5Vr7qdaHcW8vWtRjDydv1OVHNd8yZZ1J2Y+mrDMKEfFG4DmUx8SdkJn/u9q6mbk7Iv4K+DDLb7w46vdhStv0bZdRt6c2lLtS7gsyq5/rKoiIYyl9bT/gBZm57AaU/Gy/uB3lV96mrj70Y+AX6O5/S39xWoT+N/p4soqxz1gtrd66x/WGtwAvB+4EPASY3HR1rf0UZh8PtJxxbw7M+7GHl02py86a32PKOndrrDtKEfE3lNPuvk/58vr1Hpu5tObsnGvBAAAJLUlEQVTNy6Z21nzM70Nb2+ys+azt0reeNFcy85mZGT3SzrbtRcTDgE9QvoD/Wcs9ESb/7/XccgPjrn7U1Ycmf69U7+oFuN8NjDyerHLs21nzvrH67jPWkxbWesf1lu3fDEz6adt3qjvU+9i0Wdbf1jgeaLmdNR/lmDJn5vbYw8kbdZmccnm/iLhtxzoPbqw7OvUU1z8GrgZ+NTMv6bmpyRMAmgcsF9b8wbSIiM3A/eufG/V9aGubvu3i51pqiIiHAv9EOfPlLzLztBWqTPpGa/8Djm6sNzG1306pN69GG09mGPv6ttGlwC7ggIg4bHkVYPE+L9I8WPadqk7CTJ7qNmt87jseaLnRjilzaG6PPZy8UavM/A7lQ7of8NRmeUQcB2yjnCp9/t7du/kQEa8F/hT4IeXL68Vr2Nxv17z5+LnzgauAbRHxyJZ6T6WcLvuFafexWHBtbdOrXfxcSz8rIo4GPglsBV6Zma9ZRbUP1/x3W7a3CXha/fPsjnpPq+s1TbbXrDeXxhpPZhn7+rZRZu6mTChC++fsnsAxlEfZf7zva5HGJCIeABxOuffGFxvF0+L6VuDx9c+uuD7reKCGsY4pc2p+jz0y02RqTcBTKAH+SuBeS5YfSHmOfQIvHHo/B2qbV9fX/0PgqFWsfyTlDuabGsv3pfx6uadu78SWui+qZTuAA5cs317fmwSeOHSbrKEte7VN33bxc20ylQQcBVxbP/N/OUO9LUv62PMbZa+vyy8EolG2D+UpDgmc1ig7tS6/Atg8dNvM0Bajiiezjn1raSPKL5E3U24ieXTj83derXf60G1iMs1TolzKeMeW5cdQLplK4AMt5XejPGFwD/CEJcv3BT5Q653dUq/XeGDqfP9GNaYM2M4Le+wRtaLUKiLeCjwX+AnwaeD/KE+V2Ap8CHhKZu4Zbg/3voh4Arf80vBFSqdrc2lmvrbWeRLlV4drgK8B36VcovBLlBvU3Qy8NFsuV6i/XJxN+dXjeuAcyszuYyiPfXxzZr5gXV7cAPq2zVraxc+1BBFxDeUGwtdyS0xr86LM/EGj7nGUMyNuC1xAOSh4AHAE8APg2Fz+pCoi4gjgs5RTkr9KmczZTplI2gX8WmZ+bm2vbO8aSzzpM/YtqdurjSLixcDrKF+k/4XyWT2O8oX3P4BHZ+aNa3tl0sYREddS7l32VcoT4G6kxNhfpjz15t+Ax2a5VKpZ9+nAeykT7Z8D/ofyxJ17AJcBD8/Mq1rq9RoP1G4sY8qQFvrYY+iZL9P8J+AZlGB/PeUXsAuA5wP7DL1vA7XHyZQZ0pXSeUvqHAqcAXye8svyTygHKl8H3sUKv2BSBtJTa9vfUN+LzwHPGLo91qE9e7fNWtrFz7Vp7GmVcSyBQzrq3xt4P+VU35uAyymPjb7LCv/vXet6l9d6VwLvAw4fuk3W0JYbPp70GfvWo42AXwc+RTnbZxdl0ujPgdsM3SYm07wlyiWNH6Hcw+Y6ygHi9yiXx55M40yDlvoPoRxIfr/G58uA04D9V6jXazwwdbbnhh9TBm7fhT328MwbSZIkSZKkOeYNiyVJkiRJkuaYkzeSJEmSJElzzMkbSZIkSZKkOebkjSRJkiRJ0hxz8kaSJEmSJGmOOXkjSZIkSZI0x5y8kSRJkiRJmmNO3mgUImJnRGREHN+j7qaI+EpEfDsibnMr7N6tKiLeFBF7IuIBQ++LJK0347vxXdLGNy3WG8s1Fk7eSCt7LnB/4JWZedPQO9PDa4BdwBlD74gkzRnjuyQtPmO5RsHJG2mKiNgCvAr4FvCegXenl8z8HvB24PiIeNzQ+yNJ88D4LkmLz1iuMXHyRpruWcABwLszc8/QO7MG76r5CwfdC0maH8Z3SVp8xnKNhpM30nTPq3nrTH5EPCYi3hIRF0fE1RFxU73e9syIOGLW/ywizpt274aIeHctP3mW7WbmDuAC4ISIOHzW/ZKkDcj4LkmLz1iu0XDyRuoQEduB+wKXZebOjtXeBjwH+CnwWeATwG7gJOCLEXHsXtjV1fo0EMATht4RSRqS8V2SFp+xXGPj5I3U7fianz9lnRcBB2fmUZn5pMz8LeBw4A+AzcA7IiJu3d1ctcnrePSgeyFJwzu+5sZ3SVpcx9fcWK5RcPJG6nZkzb/atUJmfigzr20sy8x8O/B54AjKLwLz4JKaP3DQvZCk4RnfJWnxGcs1KvsOvQPSHDuw5ldPWykitgG/CdwH2ApsqkUH1/xwYMetsYMzuqbmd46IyMwcdG8kaTjGd0lafMZyjYqTN1K3/Wt+fdcKEfEq4GVM70tb13On1mDyOjYBt2fK65KkDc74LkmLz1iuUfGyKanb5BTL1oAeEU8GXg7sAk4BDgM2Z2ZkZgAfmKy6jvu0lj47eR17gB+tw75I0qIyvkvS4jOWa1Q880bqdlXN79hR/tSavywz39lSfq8e/+fumm/pKL9Hj21OTF7H9z0NU9LIGd8lafEZyzUqnnkjdbuw5l03MTug5t9pFkTEEfS72dgVNb9PyzYPAh7UY5sTk9dx4dS1JGnjM75L0uIzlmtUnLyRup1b82M6yi+t+SkRsd9kYUQcCJxJx5ltEXF0RFwaEZe2FJ9T8+dHxF2W1DmgbrN1ln+FbU5MXse5U9aRpDEwvkvS4jOWa1ScvJE6ZOa3gC8Dh0XEoS2rnAFcR7l7/WUR8cGI+BjwDUrg/lDHpjcD966p6e+Bi4BDgB0R8dGI+CRwGbCt5zYnHgMk8JEp60jShmd8l6TFZyzX2Dh5I0331pqf1CzIzG9STo08i3Kjs8cDRwDvoMycXzfrf5aZuymB+28pN1c7kXJa5pnAw/psEyAi7lf39ZzM/FqfbUjSBmN8l6TFZyzXaIT3QpK6RcTtgG9THtW3PTP3DLxLvUTEG4A/Ah6fmR8ben8kaWjGd0lafMZyjYln3khTZOYNwCuAQ2mZ0V8E9eZpvwec52AgSYXxXZIWn7FcY+KZN9IKImIT5drW/YHDM/OmgXdpJhHxRuBU4EGZefHQ+yNJ88L4LkmLz1iusXDyRpIkSZIkaY552ZQkSZIkSdIcc/JGkiRJkiRpjjl5I0mSJEmSNMecvJEkSZIkSZpjTt5IkiRJkiTNMSdvJEmSJEmS5tj/AwSlFn96LDZ4AAAAAElFTkSuQmCC\n", - "text/plain": [ - "" - ] - }, - "metadata": {}, - "output_type": "display_data" - } - ], - "source": [ - "expt_cfg={\n", - " \"shots\":5000, \"res_phase\":0\n", - " }\n", - "config={**hw_cfg,**readout_cfg,**qubit_cfg,**expt_cfg} #combine configs\n", - "\n", - "ssp=SingleShotProgram(soccfg, config)\n", - "di0, dq0, di1, dq1 = ssp.acquire(soc, load_pulses=True,progress=True, debug=False)\n", - "\n", - "fid, threshold, angle = hist(data=[di0[0], dq0[0], di0[1], dq0[1]], plot=True, ran=600)\n", - "#print('Optimal fidelity after rotation = %.3f' % fid)\n", - "readout_cfg[\"res_phase\"]=soccfg.deg2reg(-angle*180/pi, gen_ch=5)\n", - "readout_cfg[\"threshold\"]=round(threshold)" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "# Pulse Probe (qubit) spectroscopy\n", - "\n", - "Measures the qubit frequency f_ge. We store this parameter here: qubit_cfg[\"f_ge\"] .\n", - "\n", - "This program uses the RAveragerProgram class, which allows you to sweep a parameter directly on the processor rather than in a Python loop as in the above resonator spectroscopy example. Because the whole sweep is done on the processor there is less downtime (especially for fast experiments)." - ] - }, - { - "cell_type": "code", - "execution_count": 9, - "metadata": { - "ExecuteTime": { - "end_time": "2021-09-30T07:30:53.847151Z", - "start_time": "2021-09-30T07:30:53.706007Z" - } - }, - "outputs": [], - "source": [ - "class PulseProbeSpectroscopyProgram(RAveragerProgram):\n", - " def initialize(self):\n", - " cfg=self.cfg\n", - " \n", - " self.declare_gen(ch=cfg[\"res_ch\"], nqz=1) #Readout\n", - " self.declare_gen(ch=cfg[\"qubit_ch\"], nqz=2) #Qubit\n", - " for ch in [0,1]: #configure the readout lengths and downconversion frequencies\n", - " self.declare_readout(ch=ch, length=cfg[\"readout_length\"],\n", - " freq=cfg[\"f_res\"], gen_ch=cfg[\"res_ch\"])\n", - "\n", - " self.q_rp=self.ch_page(self.cfg[\"qubit_ch\"]) # get register page for qubit_ch\n", - " self.r_freq=self.sreg(cfg[\"qubit_ch\"], \"freq\") # get frequency register for qubit_ch \n", - " \n", - " f_res=self.freq2reg(cfg[\"f_res\"], gen_ch=cfg[\"res_ch\"], ro_ch=0) # conver f_res to dac register value\n", - "\n", - " self.f_start =self.freq2reg(cfg[\"start\"], gen_ch=cfg[\"qubit_ch\"]) # get start/step frequencies\n", - " self.f_step =self.freq2reg(cfg[\"step\"], gen_ch=cfg[\"qubit_ch\"])\n", - "\n", - " # add qubit and readout pulses to respective channels\n", - " self.set_pulse_registers(ch=cfg[\"qubit_ch\"], style=\"const\", freq=self.f_start, phase=0, gain=cfg[\"qubit_gain\"], \n", - " length=cfg[\"probe_length\"])\n", - " self.set_pulse_registers(ch=cfg[\"res_ch\"], style=\"const\", freq=f_res, phase=cfg[\"res_phase\"], gain=cfg[\"res_gain\"], \n", - " length=cfg[\"readout_length\"])\n", - " \n", - " self.sync_all(self.us2cycles(1))\n", - " \n", - " def body(self):\n", - " self.pulse(ch=self.cfg[\"qubit_ch\"]) #play probe pulse\n", - " self.sync_all(self.us2cycles(0.05)) # align channels and wait 50ns\n", - "\n", - " #trigger measurement, play measurement pulse, wait for qubit to relax\n", - " self.measure(pulse_ch=self.cfg[\"res_ch\"], \n", - " adcs=[0,1],\n", - " adc_trig_offset=self.cfg[\"adc_trig_offset\"],\n", - " wait=True,\n", - " syncdelay=self.us2cycles(self.cfg[\"relax_delay\"]))\n", - "\n", - " def update(self):\n", - " self.mathi(self.q_rp, self.r_freq, self.r_freq, '+', self.f_step) # update frequency list index" - ] - }, - { - "cell_type": "code", - "execution_count": 10, - "metadata": { - "ExecuteTime": { - "end_time": "2021-09-30T07:34:17.638682Z", - "start_time": "2021-09-30T07:30:53.854751Z" - }, - "scrolled": false - }, - "outputs": [ - { - "data": { - "application/vnd.jupyter.widget-view+json": { - "model_id": "103a41a85fd54708976fe70c7ce667cc", - "version_major": 2, - "version_minor": 0 - }, - "text/plain": [ - "HBox(children=(IntProgress(value=0, max=50), HTML(value='')))" - ] - }, - "metadata": {}, - "output_type": "display_data" - }, - { - "name": "stdout", - "output_type": "stream", - "text": [ - "\n" - ] - }, - { - "data": { - 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VrvX2Cs9/SaXr58cvIFurudw1X1XH+3btCd6v0u0zwKoy17gqP3478AKyYcTlzn8QuKhKXx5N9iPHifoxATy2zPmnkv0wcaLzu2ecdyZZYF+u7VXlXmeN7+0zyH5UqNSPMbLgeeZ5r6rx77GzwvNuBL53gnMHypxXnAZR7bw7gPMqPG/xvb8G2FnlGjcBZ9Tw/m2bcd4vNvv/M25ubm5LZTMDLUmqKqU0mFL6NWAL8HayDNtBsi/epX4zpfSRGi75W2TLBn2TLJN4BOgDfo8sMDpaY9ceAJ5ClrH7AdkSSAPAF4CfTyn9fo3XmSal9N9kWeHdZPN/R6ufUdFlwEVkweG/k2UvB8l+iBggC8Q+CFyWUvr5lFLVJYpSSp8Gngp8PO/XCPATsmG4m1NKFed6p2wo92PI5u9+puT84fwa/w78LnB2Sum7Zc4/SPa3eSnQW3L+QWAv2Y8ilzJj3e+UrV39VOAjZAFiaTZ41lJKXyIrEraT7H08Qvbjwq3Ah4DHpWy5qpn+L1mV7XeSVZr/Cdl7MAj8kCxAfWpKaUeZc0kp3U5WKf3XgD1kPxqN5rc3kmXrn1XmvJRSuoLs39U/AXeRvRcPkv13sAM4P2Vzzk/02neQDdm/luz9HyL79/9m4Ekpy3ifyL8CxXYDwD/XcI4kCYiUZn7/kSSpNvl6uV8FTicLYp6RUvp2c3t18siHBL8ZuCOltLG5vVGzRMSXyZaT+7uU0qsacL0WslENZwPvSyn99lyvKUnLhRloSdKspZR+SDbXd4BsDdrP5UG1pMXrMrLgGVz7WZLqYgAtSZqTfMjvc8mGXp8G/EdENKTqsqR58br89saU0g1VW0qSpjluKQVJkuqVUvo6WQZa0iKTV48vAKuBXycr1AfwF03rlCQtUQbQkiRJJ7eLgS/N2PclsqJqkqQ6OIRbkiRpeZgA7iSrQv6iZCVZSaqbVbhrsH79+rRx48Zmd0OSpEXj1vuy1cbOPW1lk3siSdLc3XDDDQdSSqedqJ1DuGuwceNGvv1tV2WRJKnoZX/9dQA+/ptPbXJPJEmau4i4o5Z2DuGWJEmSJKkGBtCSJEmSJNXAAFqSJEmSpBoYQEuSJEmSVAMDaEmSJEmSamAALUmSJElSDQygJUmSJEmqgQG0JEmSJEk1MICWJEmSJKkGBtCSJEmSJNXAAFqSJEmSpBoYQEuSJEmSVAMDaEmSJEmSamAALUmSJElSDQygJUmSJEmqQWuzOyBJkpa23r5+du3Zx/6BQTZ0d7F96ya2belpdrckSWo4A2hJkjRrvX397Ni9l8HRcQD6BwbZsXsvgEG0JOmk4xBuSZI0a7v27JsMnosGR8fZtWdfk3okSdL8MYCWJEmztn9gsK79kiQtZQbQkiRp1jZ0d9W1X5KkpcwAWpIkzdr2rZtob53+daKrrcD2rZua1CNJkuaPAbQkSZq1bVt6eO4FZ04+fsjaTnZevtkCYpKkk5JVuCVJUlnF5an6BwYpRDCeEj35MlWVfOrVFzp8W5J00jIDLUmSjlNcnqo/LwY2nhIwtUzVgSPDk23/e/8hWlsCgMNDYwvfWUmSFogBtCRJOk655amKBkfH+cn9WWB9dHiMH993hMee3Q3A4aHRBeujJEkLzQBakiQd50TLUI2MT3DgyDAX7/oSKcEP7z4MwCEDaEnSScwAWpIkHedE85gLLcFtB45y4MgIAIeHs6HbX7r53nnvmyRJzWIALUmSjrN96ya62sp/TehqKxDARDr+2Ke/+9P57ZgkSU1kAC1Jko6zbUsPf/KCCyYfR37b093Fzss3M1YuegYeHHQItyTp5GUALUmSyrpk02kAvGXbBfzikx/K+lXtXHflpWzb0kN7ofxXiFUdrpApSTp5GUBLkqSyivOaV3e2sqqjddoSVWef0kVLHH/O5rPWLFT3JElacP5MLEnSMtfb18+uPfvYPzDIhu4utm/dxLYtPZMBczGAHh6bYHR8grZCC+tXdZAS3HrgKJAN7R4eG2f9qs5mvhRJkuaVAbQkSctYb18/O3bvnVzzuX9gkB279wKwflUHAKs62liZD80+OjxG94p2ANZ0Zfv+8qWP5SVPOIsXvOdrrgMtSTqpLboh3BHx8oj4akQ8GBFHIuLbEfHbETHnvkbEb0REyrf3NKK/kiQtZbv27JsMnosGR8fZtWffZDC8urOV1XkAfWR4ahj3yFhWSOy01VmgvaazjUODo/T29XPR1ddyzpWf5aKrr6W3r38hXookSfNuUWWgI+K9wGuAIeCLwChwGfAe4LKIeGlKabzKJapd+2HAXwKJqWKikiQta/sHBivuLw7hXtXROpmBLg2gR8cnADgtz1Sv7mzllnsOV8xob9vSMz8vQpKkBbJoMtAR8WKy4Plu4DEppeenlF4EPBL4AfAi4LWzvHYAHyJ7vX/fmB5LkrT0bejuqri/WERsTWcbqzqnhnAXTQbQq6cC6PuODFfMaEuStNQtmgAa2JHfviGldEtxZ0rpHuDV+cMrZzmU+7fIMtk7gNvn0klJkk4m27duoqN1+kdrV1uB7Vs3TQ7hXtlRYFVHAWBaJe7R8QlaAk5Zmc+J7myjwvLQFTPdkiQtJYsigI6Is4AnACPAJ2YeTyl9BegHzgSeUue1zwH+AriObCi4JEnKbdvSw2svfcTk457uLnZevpltW3o4MjTGivYCrYUWVnW0AXB0eCq7PDKeOHVVB4V8PavVnW0Vn6dSpluSpKVkscyB3pLf3pRSqvQT9beAnrztf9Vy0Xzo9ofJXuevppRStkuSJBU9/qHrAHjJE87iL1/62Mn9h4fGWJ0P3V6ZZ6CPDE9V2R4dm5gWGBfbdra1MDQ6Mbm/mNGWJGmpWxQZaOCc/PaOKm3unNG2Fq8FLgGuSik5+UqSpDIODWZB8fiM8ddHhsdYlRcPW51noI+UZKBHxycm5z8DrOnK2vza06Y+qtevap/MaEuStNQtlgz0qvz2aJU2R/Lb1bVcMCIeDuwEbiCrvi1Jkso4lM91LhYFK91fHJY9mYGeMQe6NIAuZqBPWTm17y3bNvPsC86cn45LkrTAFksGujiuukLpkTovNjV0ux34X7NZ+ipfM/rbEfHt++67rxHdkiRpUTo0mAXF5TLQxaC4tdBCZ1sLR0dKA+g0PQOdB9vf/+mhyX0Hjw7PW78lSVpoiyWAPpzfrqrSpnjscJU2Rb8LPB3YmVL63mw6lFL6QErpiSmlJ5522mmzuYQkSUvCg/kQ7rEZAXTpHGjI1oMuVuEem0gkptaAhqkM9E37D1EsOXLg8Mg89lySpIW1WIZw357fPqxKm7NntK3mRfntsyLi4hnHNhbbRMQFwJGU0vNruKYkSSel4hDumRnow0Ojk3OgIQugi+tAj45NXwMapjLQP7r3MGes7mRobNwMtCTppLJYAui+/Pb8iOiqUIn7STPa1uKpVY5tyLcH67ieJEknnUMVMtBHhsamLU21sqOVI3kAPZLPlz59WhGx7GvF6Hji7FO6uP/oCAePmIGWJJ08FkUAnVL6SUTcCDweeCnw96XH8yzyWcDdwNdruN4llY5FxFXAm4H3ppReO/teS5K0NPX29bNrzz72DwyyobuLtXngOz4xVURsfCJxdGT8uAx0MYAuFhwrzUCXtj1r3QoiggNHzEBLkk4ei2UONGQVswHeFhGPKO6MiNOB9+UPr04pTZQce21E3BwR0wJuSZJUXm9fPzt276V/YJAE9A8M8oO7s/IiY+NTGehioDxzDnSxCne5ALq10MKK9qxa99nruli/qp2DR81AS5JOHosmgE4pfRJ4P3AmsDciPhMRu4FbgPOAXuA9M05bD2wCHrqQfZUkaanatWcfg6PTF6dIedxcOgf6cD4vek3JEO5Vna0cHRmjt6+fux7IZls9+53/SW9f/2SbYvuzTlnBqSs7OGgGWpJ0Elk0ATRASuk1wCuAG4GLga3Aj4DXAi+ezXJUkiRpyv6BcmVGMqVzoIsZ6FUlGeiVHa0cODzMjt17KTbtHxhix+69k0F0MWN91rouTl3VzgPHRo9bX1qSpKVqUcyBLpVS+ijw0RrbXgVcVef16z5HkqSTxYbuLvorBNHTM9DHD+Fe3dHK0ZHjf8seHB1n1559ANxx8BgAv/fx7/Czj8yWgXzg6Ainr+lszAuQJKmJFlUGWpIkza/tWzfRVoiyx0ozxcUh3KWFwVZ2VP7dvX9gkB27905W577n0DCf/k6Wlf7EDXdx0dXXcs6Vn+Wiq6+dNuRbkqSlxABakqRlZNuWHp7+qNMmH5+5diozXD4DXTIHukoAXYg4bm71SF6U7F1fuGVa0bLSId+SJC0lBtCSJC0zna2FyfvX/MqTJu+faAh3MYBuL0z/+tDVVmA8TV9DutTIjDnQpUO+JUlaSgygJUlaZu68/9jk/R/ecwSA7hVtZYuITQug8/vP/JnTJ/f1dHex8/LN9HR31dWHasXMJElarBZdETFJkjS/7jh4lHPXr+TWA0fZd/chAE5Z0c7w2PQ50IWWoKttKltdnANdzDY/4WHr+NSrL5w8vmP33mnDuLvaWhgcLV+Be0OdAbckSYuBGWhJkpaRB4+NcmhojCefeyoAN//0MACnrGxnbGIq2D0yNMaqjlYipgqOFYdw/3f/IQotQWvL1LFtW3omM9FBMTP9GNZ0TgXgRV1tBbZv3TQfL0+SpHllBlqSpGXkjvuPAvCUc0/hY9+8k5vvngqgbz94dLLd4aGxacO3YSqA7h8YZGXH8YHxti09bNvSM/m4t6//uAx0a0uw8/LN09pJkrRUmIGWJGkZKa7TvOnM1XSvaJtcEzrLQJcUERseO67q9qqSgLp0aHc5vX397Ni9l9HxqWu2tgRjE4mnPXL9nF+HJEnNYAAtSdIyUiwgdva6FTxkbTYPub3Qwor2VsbzYLe3r5+v/PA+br778LR1m1e1TwXQpZW8y9m1Z99xy1oVA/QnvuULrgctSVqSDKAlSVpG7jx4jPWrOljZ0cqGfA3oNV1ttBWy7HAxczySFxQrXbe5dNh2Z1v1rxAnqrLtetCSpKXIAFqSpGWit6+ff/5OPweODHPR1dcylGeI13S1UmgJxiYmymaOi+s2txZaJgPnzhMM4a6lyrbrQUuSlhoDaEmSloFymeXrb7sfgDWdbZPzkytljvcPDNLb1z95/g/vOcyBI8MVn2/71k0nnCddvK4kSUuFAbQkSctAtTnJa7raKLS0kBI8pLuz7Plru9rYsXsvxTpjI+OJ2w4crTgEe+ayVoWS5bBKuR60JGkpMYCWJGkZqJbp/c8f3seHvnYrAK9/5qOOyxx3tRWI4LgAfCJRdQj2ti09XHflpdx29fN4+y88tux1XQ9akrSUGEBLkrQMnCjTe2hoDMiC4p2Xb6aYL+7p7mLn5ZsZODZa9rxah2AXM9Knr+4A4JQVba4HLUlacgygJUlaBrZv3VRxGHWpd3zhh2zb0kOhJXjNJQ/nuisvZduWnooBeD1DsLdt6eFzr/tZAK541qMMniVJS44BtCRJy8C2LT10r2ils62FamH03Q8OkVJibCLRWpj6mlCuKFhLUPcQ7HUr2im0BPcdHqa3r5+Lrr6Wc678rOtCS5KWBANoSZKWgfuPjnDw6ChXPPNR3Hb18+ipkDk+Y23nZHGxtpapUHtmUbD2QgvnrF9Zdxa50BKcurKdb912Pzt276V/YJBEVhX8io9/hy1/+h8G0pKkRcsAWpKkZeA7P3kAgMed3Q1UXmbq1Refy9h4FkCXZqBhelGwLQ/tZv2qjln15bTVHXznJwPHFSUDeODYKDt27zWIliQtSgbQkiSd5Hr7+nndx74DwO99/Dv09vUfl1HuXtEGwDPPO5OR8Wyt57bCiedMz8ZpqzsYyteTLmdwdLxqdW9JkpqltdkdkCRJjdXb18+uPfvYPzDI2q42jo6MMZpnlX/64BA7du8FsoxycQj27hvv4vX/97uMjU8wNhlAz8/v7Ket6qAlmFxTupxaq3tLkrSQzEBLknQS6e3rnza3eGBwdDJ4LiqX4S3k853HJtLkHOjWecxAA3S1Vf4aUk91b0mSFooBtCRJJ5Fde/aVnVs808wMb2tL9pVgfCIxWsxAt8xTBnp1BxPWIwUzAAAgAElEQVQJ3vi888oe72or1F3dW5KkhWAALUnSSaTWoc8zM7yTGejxVFJEbH4z0A8/fRUA2x63YXLfKSvb2Xn5ZteIliQtSgbQkiSdRGoZ+lwuw9uaB9DTMtDzOAca4Ppb7wfgBY/bwD+/5kIArnz2ow2eJUmLlkXEJEla4mYWDSu0BOMzKnS1BKSUBdjbt246LkgtFIpzoCcYHc/uz2cVboDrbzsIwMNPW0X3inYABgZH5uU5JUlqBANoSZKWsGLRsOK854HBUVpK4t4NazsZHhvnKeeu572veHzF65RmoMcmJvJ98zcHGuCGOx6gvdDCWetW0BLZMPIHB0fn5TklSWoEh3BLkrSElSsaVpp8/quXPY6DR0d59Jmrq16nGCyPTaTJqt3zNQd6VUcrnW0tDI9NsHH9CgotQUTQ3dXGwDEDaEnS4mUALUnSEnaiomG7b7wLgEc/ZE3VdsVgeSHmQEfEZBb63PWrJvevXdHGgBloSdIiZgAtSdISVqloWEvA6s5WPvu9nwKcMAM9bR3oPAM9XwE0TBUSe/jpKyf3dXe18aAZaEnSImYALUnSErZ96ybaZwy1bgk4Y3UH529Yw9GRcVZ3tHLWuurVuafmQE8wWpwDPU9DuHv7+vn+Tw8B8NHr76S3rx+A7hXtFhGTJC1qBtCSJC1h27b08LInnT35uKe7i42nruRh61fS1ZZ9zB8eHuNpb/vSZKBaTjEDPVqyDnTbPBQRKxY9GxrNgvQHjo2yY/deevv6nQMtSVr0DKAlSVriLuhZC8BzLjiT6668lNZCcGx4jK/96OBkm/6BwclAtZxiEbHxicTY+PxloMsVPRscHWfXnn2sXdFmFW5J0qJmAC1J0hJXzOYePJINf37g2Cg/uu/oZDXtomKgWk7pHOiReSwiVqnoWXEN68NDY5MBvCRJi40BtCRJS9xQntE9cHSYlBIPHhvl2Mh42baVAtjSOdBTRcQan4GuVPRsQ3cX3V1tABwaGmv480qS1AgG0JIkLXGlGehjI+OMjE+wprO1bNtKAexkBno8MTZZRKzxXxO2b91EV1th2r6utgLbt26ie0U7AAPHLCQmSVqcDKAlSVrihsaybPODg6Pcd3gYgOdsPrNioFrO9HWgi0XEGp+B3ralh52Xb6anu4sgK3q28/LNbNvSw9oVWQbataAlSYtV+Z+nJUnSkjFUUpTr1gNHAHjGpjN46rnr2bVnH/sHBtnQ3cX2rZvYtqWn7DVK50CPjs9fBhqyILpcP4pDuItrQff29dfcf0mSFoIBtCRJS1xxCDfAj+7NAuh1K9p48rln1hxwtk2rwj1/c6CrmRzCPTgyudxVsWJ3sYo4YBAtSWoah3BLkrTEDY9NZaB/fO9RYCoYrVWhUJKBnpi/KtzVlGagqy13JUlSsxhAS5K0xA2PTtCeB7s/ui/LQHfn84lrVa4Kd+s8zIGuZk3X1BzoastdSZLULAbQkiQtcUOj4zykuxOYGsK9tqu+ALo4B3p0PE2uw1xY4AC60BKs7mxl4Nho1eWuJElqFgNoSZKWuKGxcdav6qC9tYUHB0fpaivQOaMC94m0lsyBHhlPtBdaiFjYABqyzPmDg6NVl7uSJKlZDKAlSVrihkYn6GxrYf3KbN7zujqHbwMUk81jE1kGunWBC4gVdXe1M3BsZHK5q2IQfcrKtsnlriRJahYDaEmSlrih0XE6WwucuqoDgLV1FhADiAhaWyKbAz2RFnz+c1H3irbJdaC3belh81lrAXjT8883eJYkNZ0BtCRJS9zQ6DidbQVOXTX7DDRkc5CL60AvdAXuorVdbZPrQAPce2gImL7WtSRJzeI60JIkLXFDoxN0tLXQ2ZZloOutwF3U2hKMj2cBdNOGcOdzoAFSStxzaBjguCWtJElqBjPQkiQtccNjWQZ6fZ6BXttV/xBumMpAj42npmSge/v66e3bz8GjI1x09Rf52LfunAych0YnFrw/kiTNZAAtSdISNzQ6QWdrgZ8+mK2R/LFv3slFV19Lb19/XddpK7QwPpEYnVj4ALq3r58du/dyZHgMgP6BIf7k09+fPO4QbknSYuAQbkmSlrih0XHuvP8oX/nhfZP7+gcG2bF7L0DNxbemMtATC15EbNeefccN0x4em8o6D40ZQEuSms8MtCRJS9jYeFY1+/rb7md0PE07Njg6zq49+2q+VrEK9+h4onWBM9D7BwarHh92CLckaREwgJYkaQkbyrO0h4fGyh4/UWBaqlAIxvIiYu0LXERsQ3dXxWNru9oYHDEDLUlqPgNoSZKWsOF82PParvKVt6sFpjO1trRkQ7gnJhY8A7196ya62grT9hVagq62FtZ2tTmEW5K0KBhAS5K0hBUz0M++4IzjAtCutgLbt26q+VqFlsiKiI2nBZ8DvW1LDzsv30xPHvC3BJz3kNWcfcoKOttaLCImSVoUDKAlSVrCioHlhQ9fPxmABtDT3cXOyzfXXEAMsjnQYxMTjI1PNGUZq21berjuykv50xeez0SC+w6PcMaaTjrbCi5jJUlaFKzCLUnSElYMoDtaCzz7gjPrCphnmpaBXuA50KXO37AWgLsPDfG0R65neGziuArdkiQ1gxloSZKWsGJmtrNt7h/prfkyVqNNykAXnfeQNRRHkJ+xpoPOtsLkXG9JkprJAFqSpCWsGFh2zpj/PBvFDPTYRKKtiRnoPTfdTUtkz/8P37iT+48MO4RbkrQoOIRbkqQlrFiduhEBdGtLC2PjibHxCVpbmvMbe29fPzt272VsIlvT+sHBUY4MjdG9wq8skqTmMwMtSdIS1tAh3IXmz4HetWffcfOdx1PigWOjTemPJEmlDKAlSVrCikXEOlsbM4R7bGKC0fEJ2ps0B3r/wGDZ/XlCWpKkpjKAliRpCZvKQDdiCHdWRGxsonkZ6A35OtCSJC1GBtCSJC1hkxnoBgzhLuRzoEebOAd6+9ZNdM34MaA1L8k9YRpaktRkBtCSJC1hjS0illfhHm9eFe5tW3rYeflmerq7CKCnu4tnX3AmAMNjVuKWJDWXJS0lSVrCikO4O1obkIEuTM2Bbm3iOtDbtvSwbUvP5OO/ve42/vV7P2VodJyu9rn/UCBJ0myZgZYkaQkbHhunvbWFiLlnjEvnQLc1MYCeqZhdn1mdW5KkhbZ4Ph0lSVLdhkcn6GxA9hmyKtzDeUa7raU5Q7jLKc7vHjKAliQ1mQG0JElL2NDoeEPmP0OWgS7OqW7mEO6ZikXFisPVJUlqlsXz6ShJkurWyAC60NIymeVtVhGxcjqKAfSYGWhJUnMZQEuStIQNjU40ZAkryDPQxSHciygD3dmaB9AjBtCSpOZaPJ+OkiSpbkNjDRzCXZJ1bl1EGejJOdBmoCVJTWYALUnSEjY0Oj6ZoZ2r1pLCYW0ti+crQnHpKudAS5KabfF8OkqSpLoNjU7Q0aAh3IWSoHlRZaCLQ7itwi1JajIDaEmSlrBGV+GevL+Y5kBbhVuStEgsnk9HSZJUt+GxiQZW4Z4KoNsXUwY6z7APmoGWJDWZAbQkSUtYNge6cVW4p+4vnq8IUxloA2hJUnO1zuakiDgL2AB0VmqTUvrP2XZKkiTVpqHrQC/SKtwdrS1EwLABtCSpyeoKoCPicmAn8IgTNE31XluSJNVvaHSCjnnIQC+mdaAjgo7WFobGnAMtSWqumoPciPh54P+SDft+ELgVONToDkXEy4FXA48BCsDNwN8C708p1fzJGRGvAJ4NPA44E+gGjgA3Af8E/HVKabSxvZckaeGklBhu4DrQpVW4F1MADdkw7sERM9CSpOaqJ0v8h0AAbwR2zUfwGRHvBV4DDAFfBEaBy4D3AJdFxEtTSrV+er4aeCrwfeBbZEH/hnzfRcArIuKZKaWjjX0VkiQtjNHxxESaKrI1V9OrcC+eIdyQLWXlHGhJUrPVE0A/BuhLKb11PjoSES8mC57vBp6eUrol338G8CXgRcBrgXfVeMnXAz9MKQ3MeJ6zgM8DTwH+N/DmhrwASZIW2NBYFlA2bBmrkqC5bREVEQPoai84hFuS1HT1fDqOAvvmqyPAjvz2DcXgGSCldA9ZNhngyoioqc8ppW/ODJ7z/XcBxR8BnjWH/kqS1FTFjGzHvKwDvbgy0B2tLWagJUlNV08AfQNw7nx0Is8KPwEYAT4x83hK6StAP9lc5qc04CnH8tuhBlxLkqSmGB7NMrKNWsZq+hzoxRVAd7Y5hFuS1Hz1fOJeDfyPiJiPrO2W/PamlNJghTbfmtF2ViJiPbA9f/iZuVxLkqRm6e3r58Xv/y8A3vq5H9Db1z/nay7WKtyQzfM2gJYkNVs9c6D3AX8OfDoi3g18FrgTKDshKaV0Zx3XPie/vaNKm+L1zqnS5jh59fAXk1X0fghZAbFO4Bqy4mSSJC0pvX397Ni9l8E8oHzg2Cg7du8FYNuWnllftzBtCPfiCqC72gocODLS7G5Ikpa5egLo28nWdw7gD/KtknrXgV6V31ariH0kv11dx3UBHgv88ox97wLeXK2SeET8BvAbAA996EPrfEpJkubPrj37JoPnosHRcXbt2TenAHpaBrrFIdySJM1UT5B7J1lgPB+Kn9INv35K6S3AWyKiHXgY8AvAlcC2iHhuSun7Fc77APABgCc+8Ynz9bolSarb/oHys50q7a/VYs5Ad7YVGBobp7evn1179rF/YJAN3V1s37ppTj8aSJJUj5oD6JTSxnnsx+H8dlWVNsVjh6u0qSilNALcAvx5RNwMfBL4+4h4UkrJAFmStGRs6O6iv0ywvKG7a07XnbaM1aIrItbCA0dHpg1d7x8YbMjQdUmSarVYfl6+Pb99WJU2Z89oOxe7gUNklb83NuB6kiQtmO1bN9HVNv0jvKutwPatm+Z03elVuBfLV4RMZ1uBo8PjFYeuS5K0EBbLp2Nffnt+RFT6+fxJM9rOWp5xPpg/PH2u15MkaSFt29LDFc981OTjnu4udl6+ec5Z2GnrQC/COdCVhovNdei6JEm1qmcONDC5DNSvA5cAxU/qfuBLwIdSSvfVe82U0k8i4kbg8cBLgb+f8ZwXA2cBdwNfr/f6M0XEOWSZ5wng1rleT5Kk+TZz7u+Tz1kHwFf/9zM4+5QVDXmO0jnQhcUWQLcWKh6b69B1SZJqVVcGOiKeA/wQeAvwLOC8fHsW2RJXN+dtZmNnfvu2iHhEyXOeDrwvf3h1Smmi5NhrI+LmiJgZcJ8XEb8VEcdV7I6IC4BPkBUu++fZBPySJC2k4rJV/QODJLK5v7v79tMScMMdDzTseYrzntsKQcQiC6Dbyn9lacTQdUmSalVzBjoiHg18imwN5euBvwV+TBaIngP8CvAU4JMR8YSU0s31dCSl9MmIeD/wamBvRHwBGAUuA9YAvRy/bvN6YBNZZrrU6cD7gbdHxA1kGfIOsqzz4/I+fxP4zXr6KElSM5RbtgpgItHQIlrFOdCLbf4zQFf7VAZ6TWcrh4bGCKbPgbaQmCRpvtXzCXklWfC8PaX01JTSB1JKX0wpfSGl9DcppQvJ1obuAt4wm86klF4DvAK4EbgY2Ar8CHgt8OKUUq0LQN4EvBH4KvBQ4AXA84AzgH8DXgVcmFI6WOkCkiQtFtXm+DayiFZx3vNim/8M04dwv/7nHkVLTK19WazG3dvX35zOSZKWjXrmQF8K/HdK6e2VGqSU/ioiXkWWNZ6VlNJHgY/W2PYq4Koy++8jG1IuSdKSV2nZqqJGFdEqzntebBno3r5+dv7bD4AsuH/XF25hYkZFseIPCWahJUnzqZ5PyDOA79XQbi9WtpYkqWGyZavmv4jWZAZ6Ea0BXZz//cCxUQDGJtLk/Zmsxi1Jmm/1BNCHmKq6Xc0G4PDsuiNJkmbatqWHnZdvpqP1+MC2kUW0FmMGutL873Ksxi1Jmm/1fEJ+G3haRFxUqUFEXAj8LPCtuXZMkiRN2balh1ddeA6FyNZ9Dhq3/nNR6yIsIlZrVtlq3JKkhVDPHOj3kBX1+reIeCfwd8AdZDU8NgKvBK4gq3A9s1q2JEmao6MjY6xd0c51V146L9cvFBZfEbFK87+7u9o4NDTKRMp+SNi+dZPznyVJ867mn5hTSp8F3gasAv6IbD3oQWAov/9GYDXwtpTS5xrfVUmSlrdjI+NV50LP1dQc6MWTgS43/7urrcBVLzifR56+mq3nn8F1V15q8CxJWhB1fUKmlHYAzwe+DIwAhXwbAb4EPD+l9IcN7qMkSQKODY+zsmP+AuipOdCLJwNdnP9dbtj6KSvbuf/oSLO7KElaRuoZwg1Anl3+XEQUgFPJhmwfqGONZkmSNAvHRsfpaq/7o7tmrYuwiBhkQXS5DPMpK9u5+e5DTeiRJGm5mvWncB4w39vAvkiSpCqODY+xsn0eh3DngfNimgNdjRloSdJCW1w/MUuSpIqOjYyzYj4D6EWaga5k3cp2BgZHGZ9Ize6KJGmZqJiBjog35Xffk1K6v+RxLVJK6c/m1jVJklTq2MgYK+ZxCHdhsojYEslAr2gjJRg4NsKpqzqa3R1J0jJQ7VP4KrIlqv4JuL/kcbVP1eLxBBhAS5LUQPOdgS7E0spAn5IHzQ8YQEuSFki1APpPyQLhAzMeS5KkJsgC6PnLQLe0BC2xuKpwV3PKinYADh4Z4RGnN7kzkqRloeKncErpqmqPJUnSwkkpcWxkbF6XsQJobWmhtWWJZKBXZgH0A8csJCZJWhhL4xNSkqRlbnhsgokEXfM4hLu3r5/R8Qk+/d39XHT1tfT29c/bczVCMYA+aCVuSdICqTmAjohbI+JtNbTbGRE/nlu3JElSqWMj4wCsnKch3L19/ezYvXdyrlb/wCA7du9d1EH0upVtADxgAC1JWiD1ZKA3AqfV0G593laSJDXI0eExYP4y0Lv27GNwdHzavsHRcXbt2Tcvz9cIHa0FVnW0moGWJC2Y+RjC3QWMzcN1JUlatuY7A71/YLCu/YvFKSvbzUBLkhZMQwPoiFgLXATc3cjrSpK03B0byX6bnq9lrDZ0d9W1f7FYt7LdDLQkacFUDaDzec+3RsSt+a6XlO6bsd0J3As8FNgz3x2XJGk5KWag5yuA3r51E11t06/d1VZg+9ZN8/J8jXLqynarcEuSFsyJxoFtLLmfgFX5VskI0Au8YW7dkiRJpaYC6PkZwr1tSw+QzYXePzDIhu4utm/dNLl/sVq3op2bf3qo2d2QJC0TJ/oUPie/DeBW4JPA9gptR4D7UkrOf5YkqcEmh3DP4zrQ27b0LPqAeaZTV7VzvxloSdICqRpAp5TuKN6PiL8Dvlq6T5IkLYz5HsK9VK1b0c7Q6ATHRsbmLTsvSVJRzZ80KaVfmc+OSJKkyorLWBkkTnfHwaMAnP+mPUtm2Lkkaemaj2WsJElSgw2agT5Ob18/u2/sB7JCLf0Dg+zYvZfevv7mdkySdNKq+2fsiHgS8BLgUcAasvnRM6WU0mVz7JskScodHRmnvdBCW8Hfvot27dnHyPjEtH2Do+Ps2rPPLLQkaV7UFUBHxDuA32UqaE5MD6CLj1NDeidJkgAYHBmjy+zzNPsHBuvaL0nSXNX8M3ZE/CLwOuAu4DeA/8gPbQV+G/gvsuD5bcClje2mJEnL29GRcVYaQE+zoburrv2SJM1VPePAfh0YAy5NKX0Q+ClASunzKaX3p5SeBlwFvB442uiOSpK0nA2OjJuBnmH71k10tU1/T7raCmzfuqlJPZIknezqCaAfC3wjpfTjKm3+DPgJ8Edz6pUkSZrm6MgYKzuswF1q25Yedl6+mfZ8XnhPdxc7L9/s/GdJ0ryp55N4Jdnw7aJhgIhYnVI6DFnlsIj4Fg7hliSpoY6NjFuBu4xtW3r46i0HuO5HB7juSr9+SJLmVz0Z6HuBU0se35ffPmJGu7XAqrl0SpIkTXdsZMw1oCs4+5Qu7jk8xPDYeLO7Ikk6ydUTQP8IOKfk8bfIiob9VnFHRGwCngFUG+YtSZLqZAa6srPWrSAl2D8w1OyuSJJOcvUE0J8HHh4RP5M/3gP0A78WEd+MiE8B3wDagY80tpuSJC1vx4YNoCs5e11WdfuuB441uSeSpJNdPWPB/pEs4F4BkFIajohfAP4ZeGK+AXwGeEcjOylJ0nLnEO7KzjplBQA/ud/1nyVJ86vmT+KU0p3An8/Y9/WIOAd4OnAKcHNKqa+xXZQkSQ7hruzMNZ20tgQ/MQMtSZpnc/4pO6U0SDacW5IkzYORsQnGJpLLWFVQaAk2dHdx1wNmoCVJ88tPYkmSFrljI2MAdLWZga7k7FO6+Mn9x+jt62fXnn3sHxhkQ3cX27ducl1oSVLDVAygI+Khc7lwPuRbkiTN0bGRbHmmlR0G0JWcvW4F//q9/ezYvZfB0ez96h8YZMfuvQAG0ZKkhqiWgb4dSLO8bjrBtSVJUo0mM9AWEavo0OAoR4aPXwd6cHScXXv2GUBLkhqi2ifxncw+gJYkSQ0ymYG2iFhZvX39fP4H91Q8vn/AudGSpMaoGECnlDYuYD8kSVKJ4lze/oFBWiLb94ZPfY83Pu88s6kz7Nqzj9Hxyr/5b+juWsDeSJJOZo4FkyRpkent6582l3cijw0PHBlxTm8Z1TLMXW0Ftm/dtIC9kSSdzFqa3QFJkjTdrj37JoPnmYpzejWlUoa5EMHOyzf7Y4MkqWEMoCVJWmRONGfXOb3Tbd+66bglvgJ4+y881uBZktRQNQ/hjojyP4WXl1JKDg+XJKlGpesXt0QwnpzTW6tikFx8/7raCwQOc5ckNV49QW7MU1tJkpa1mXOeqwXPzuktb9uWnsmA+Z1f+CHv/MItjIxN0N7qYDtJUuPU/KmSUmoptwEF4Fzgd4D7gT/L90uSpBpUm/MM2VxegJ7uLuf01uCMNZ0AHDgy3OSeSJJONnMeZp1SSsDtwHsj4rvAlyLiBymlf5rrtSVJWg5OVEXaoLk+p6/uAODew8MOd5ckNVRDM8Uppa8BNwJXNPK6kiSdzKoFeVbdrt/pq7MM9L2HhprcE0nSyWY+hlrfAZw/D9eVJOmkVK6KdCmrbtfn9DVZBvqeww7hliQ11nxUyj4fmJiH60qSdFIqDs++4uPfKXvcYcj1OXVlOxFwnxloSVKDNSwDHRGnRsR7gUcD1zfqupIkLQcvfNwG2gpBoWX6QhZW3a5fa6GFU1d2cK8ZaElSg9WzDvStVQ6vAk4lW75qBLhqbt2SJGl5OTI8xuh44gWPeQg33DnA/oFBNnR3sX3rJguIzcLpqw2gJUmNV88Q7o0nOD4CfBV4U0rp67PukSRJy9A9+XDjy847g3e//PFN7s3Sd8aaDu497BBuSVJj1RNAn1Pl2AhwX0ppbI79kSRpWbrnUJYtLVaQ1tycvrqTm/YfanY3JEknmZoD6JTSHfPZEUmSlrNiBvqMvIK05ub0NR0cODLM+EQ6bl65JEmzNR/LWEmSpDrdPRlAm4FuhNNXdzCR4OAR50FLkhqn7mWsIqIdeDFwCXAWkID9wJeBT6WU/KSSJKlO9x4aZnVHKys75mOFyeXn1gNHAXjyW79oMTZJUsPU9SkdERcCHwXOJqu4XepXgZ0R8YqU0tca1D9JkpaFew4NcbrDtxuit6+fj15/J5D9yt8/MMiO3XsBDKIlSXNSzzJW5wP/AawAbgU+BtyeH94IvAx4BPDvEfHklNJNDe2pJEknsbsPDXHmWodvN8KuPfsYHpuYtm9wdJxde/YZQEuS5qSeDPSfkgXPO4E/TilN+2SKiDfnbf4Q+BPgJY3qpCRJJ7t7Dw3z5HNOaXY3Tgr7Bwbr2i9JUq3qKSJ2MbAvpfRHM4NngJTSRErpjcA+svnRkiSpBhMTiXsPD3G6BcQaYkN3V137JUmqVT0BdBdwYw3tbgT8BiBJUo3uPzbC6HjiTOdAN8T2rZvoaitM29fVVmD71k1N6pEk6WRRzxDufcBDamj3EOCW2XVHkqTl5x6XsGqo4jznt3z2+xw4MsKpK9v54+ef5/xnSdKc1ZOB/j/A0yPiokoN8mNPB/56rh2TJGk56O3r55Uf+iYAf/wvN9Hb19/kHp0ctm3p4WtvuJS2QvCSJ5xl8CxJaoiaM9AppQ9ExKPJqmy/D/hH4Lb88EbgFcBrgHellP5PozsqSdLJprevnx279zI4Og7AgSPDLrfUQJ1tBXq6u/jwdbfxgf+81fWgJUlzVs8yVuMlD/8g38q5IiKumLEvpZTqWnNakqST3a49+yaD5yKXW2qc3r5+7npgkLGJBLgetCRp7uoZwh1z2Op5HkmSlgWXW5pfu/bsmwyei4o/UEiSNBv1DOE2CJYkqYE2dHfRXyZYdrmlxvAHCklSoxkUS5LUJC63NL9cD1qS1GgG0JIkNcm2LT3svHwzrS0BQE93Fzsv3+z83AYp9wMFwLGRMaudS5Jmpe7CXhHRBrwEuAQofsL3A18GPplSGm1U5yRJOtlt29LDmz99Ey983Ab+9IUXNLs7J5XiDxFXffq/GRgcm9z/wLFRi4lJkmalrgx0RDwB2Af8A/DrwHPz7dfzfTdHxOMb3UlJkk5WI2MTPDg4yqkrO5rdlZPSti09rOxoO26/xcQkSbNRzzJWZwF7gFOAn5CtA/1jsirb5wAvz2/3RMTjUkqOjZIk6QQeODYCwKmr2pvck5OXxcQkSY1SzxDuK8mC53cD22cO1Y6INwO7gNflbX+nUZ2UJOlkdeDIMADrDaDnjdXOJUmNUs8Q7mcDtwK/V26ec0ppDPj9vM1zG9M9SZJObgePFDPQDuGeL1Y7lyQ1Sj0BdA/wzZRSqtQgpTQBfBPYMNeOSZK0HBw8mmWgT11pBnq+FKudF6x2Lkmao3oC6EGyIdwnsi5vOysR8fKI+GpEPBgRRyLi2xHx2xFRc18joiUiLoyIt+TXuisiRiLinoj4XERsm23/JElqJDPQC2Pblh7OXb+S524+k+uuvNTgWSW+8wYAACAASURBVJI0K/XMgf4ecElEPDqldHO5BhGxCXgG8I3ZdCYi3gu8BhgCvgiMApcB7wEui4iXppTGa7jUucB1+f37gW8DX8v3Pwd4TkRcA/yvahl1SZLm24EjI7QXWljTWffKkqpTZ1uBwZFavkZIklRePRnoDwHtwLUR8b8iYnKsWUS0RcSvkAW9bcDf1NuRiHgxWfB8N/CYlNLzU0ovAh4J/AB4EfDaGi+XgGvJguXTU0pbU0r/X0rpf5CtX30UeFW+SZLUNAeODHPqqnYiotldOel1tRUYGp1odjckSUtYzQF0SukjwMeAM8kC5KMRcWdE3AEcAz5INvf5Yymlf5xFX3bkt29IKd1S8rz3AK/OH15Zy1DulNKPU0qXpZT+fWbGOqX0FeDq/OH/nEU/JUlqmIN5AK3519leYHDUDLQkafbqyUCTUnoFWRb4dqAAnAWcnd+/DXhtSqnuoDRfY/oJwAjwiTLP+xWgnyx4f0q91y+jL789qwHXkiRp1g4eHeHUlc5/XgidrS0MGUBLkuag7glXKaX3Ae+LiB6yytwB3JVS6p9DP7bktzellCoVIPtW/nz/j717j3Pjru/9//pKq93VejdeXxNbuULCBhKHbBNuDRASWkxPuCxOAz09PT30/E77K5eWS9gQQ4FAS+3i0lIOlEvbtIe2tLm5SyAc3EIgN6AkYe04TuyEXB3ZTnxb27ur3dXle/4YjazVaqTRSlrNaN/Px8MPeaXR6CuNNDOf+X6+n+8g8OM6XguctHCA/XWuR0REpC6Hx2c4d3Vvq5uxKMQ7owqgRUSkLvOuWJIPmOsJmoudk799psIyz5YsOy/GmB7gD/N/3lbPukREROphreXQ+DQrVYF7QcRjSuEWEZH6VA2gjTFXAtcAZwHTwHbgb+vscS7lXnqfqLDMeP62r87X+mucIPwR4OteCxljfg/4PYAzzzyzzpcUERGZa2Imy3QmpzmgF4iqcIuISL0qBtDGmC8C73P/zN++DfiwMebt1tofNagd7rqbOqWUMeYTwP8AjgHvtNZOey1rrf06+QD70ksv1VRXIiLScIfHncOQeqAXRreqcIuISJ08A2hjzNs5OW3UPThzKZ8CvAmncNg3jTHnVApCa3Aif1tpEJj72IkKy3gyxnwY+AxOT/avWWt3zWc9IiIijXJofAZAVbgXSDwWZSabI5uzfHvHPrZs28O+sRRr++MMrx9gaDDR6iaKiEjAVarC/bs4PcJ/YK293Fp7rbX2d4GXAncBpwJvbVA7ns7fnlVhmTNKlvXNGPMHwOeBFPAWa+1Pal2HiIhII42MJvndbzwAwPCtDzEy2siRUVJOvNM57bn1gb1s3LqT5FgKCyTHUmzculPbQEREqqoUQF8C7LbWfrn4TmvtJHA9Ttr1JQ1qhzut1AXGmLjHMq8oWdYXY8z7gC8CU8Db8lNiiYiItMzIaJKNW3dyZMLpgT54YloB3ALojkUB+MsfPD6nmFgqnWXLtj2taJaIiIRIpQB6BbDT47GH8rfLG9EIa+1e4OdAJ07BslmMMZfjzNl8APDde2yM+X3gSzjFz4astd9vRHtFRETqsWXbHgVwLeAG0M8fmyr7+L4xr5k0RUREHJUC6A5gstwDRXM1xxrYlk352z8zxpzr3mmMWY1TORtgs7U2V/TY+40xu40x3yhdmTHmd/PPmwY2WGu3NbCtIiIi8zIymiTpEagpgGuueD6AXtVXvmjb2n6vJDgRERHHvOeBbjRr7a3GmK8A7wF2GmO+D6SBN+IULxvB6U0uthIYwOmZLjDGXAx8DSfN/CngncaYd5Z52UPW2o809I2IiIh4cFO3vSiAay63B/q/v/osvvyjX8yqyB2PRRleP9CqpomISEhUC6AvNsZ8cj6PW2s/U2tjrLXvNcbcizN11uVAFNgN3Ah8pbj3uYp+Tk6NdX7+XznPAAqgRURkQZRL3XYpgGs+twf6VS9aQV+8gxtufwSAhKpwi4iIT9UC6Jfn/3m5uMzjBqd6d80BNIC19pvAN30uewNwQ5n7f8TJAFpERCQQKqVob9qwTgFck7lVuKfSWS578UoALj1rGbe+55db2SwREQmRSgH0/1mwVoiIiCwCa/vjZcc/J/rjCp4XQFeH0wOdSmc5MZ0BYHKmfEaAiIhIOZ4BtLX2dxayISIiIu1ueP0A1299SGNvWyTe6QTQU+ksE/kA2iulXkREpJxKVbhFRESkgYYGE3zgjecV/k70x5W6vYDcMdCpmSzjU04A7QbSIiIifgSmCreIiMhicMbyHgDu+MPXcsHapS1uzeLiBtBT6SyRiFMqJaUUbhERqYECaBERkSYaGU2yZdse9o2lWNsf58K1pxAx8OJVva1u2qLjTmOVSufI2fwY6HQWay3GqPaoiIhUpwBaRESkSdx5n91xtsmxFPuPpVjeEysEc7JwujqckWupdJZ01hmHns1ZpjM5bQ8REfFFY6BFRESapNy8zzkL49NKG26FSMTQHYswXVREDJTGLSIi/imAFhERaRKveZ+nMrmy90vzdceis6axAieNW0RExA8F0CIiIk2ytj9e9v6IcdK7ZeHFY9FZVbgBUjOqxC0iIv4ogBYREWmS4fUDhcrPxXIWNm7dqSC6BeL5Hujxoh7oCaXUi4iIT74DaGPMncaY63ws9xFjzJ31NUtERCT8hgYTbNqwruxjqXSWLdv2LHCLpCsWZSqdY3wqQ34mKyY1BlpERHyqpQf6DcD5PpYbAC6fV2tERETazNtevtbzMa8x0tI88ViEqXwP9IreLgBSaaVwi4iIP81I4e4CdClXREQEGEulPR/zGiMtzRPvPJnCvbrPCaCVwi0iIn41NIA2xkSAS4BDjVyviIhIWB0enwYgFjWz7o/HogyvH2hFkxa1eCxa6IF2A2hNYyUiIn51VHqwzFjmN1cY39wBnAucCtzcgLaJiIiE3qHxGQB+93Uv4lvb97FvLMXa/jjD6wcYGky0uHWLT5dbRGwqw+q+bgAmVYVbRER8qhhA44x7dlngtPy/SkaBj9bRJhERkbZxKN8DPTSY4Lo3+yklIs0Uj0U5nkozk81x6ilOD7TmgRYREb+qBdBX5G8NcCfwPeDPPJadAZLW2mcb1DYREZHQc1O4VyzpbHFLBJwA+vCEkxWwfEknEQOTGgMtIiI+VQygrbV3uf83xtwF/Kj4PhEREans8MQMEQP9PQqgg6A7FsFa5/+93TF6Ojs0jZWIiPhWrQe6wFp7RfWlREREpNih8RmWL+kkGjHVF5ami8eihf/3dnXkq3JrDLSIiPjTjGmsREREJO/w+DQrlnS1uhmS1915MoDu6+5gSWdU01iJiIhvnj3QxphP5v/7JWvtkaK//bDW2j+ur2kiIiLhd3hihhW9St8Oiu6O0h5opXCLiIh/lVK4b8CpvP2vwJGivyvloLmPW0ABtIiILHqHx6dZd3p/q5shefGiHuje7g56lMItIiI1qBRAfwYnED5U8reIiIj4dHh8hpXqgQ6M4jHQfV1OAD0+rQBaRET88QygrbU3VPpbREREKptKZzkxnWFlr8ZAB0V3bG4P9AvHp1vYIhERCRMVERMREWkSd75hzQEdHN0x59QnYpze6J7ODiaVwi0iIj75nsaqlDEmAqzASes+Yq3NNaxVIiIibeDwuNOzuUI90IHhpnAv6erAGONMY6UiYiIi4lPNPdDGmDcbY7YBJ4ADwPPACWPMNmPMf2l0A0VERMLq8Hi+B1pjoAPDLSLW1+X0IWgaKxERqUVNAbQx5gvAHcCvAnGc3meb//+vAt82xnyx0Y0UEREJo0P5HuiVmgc6MNwx0L3dTgAd7+wglc6Sy6lOqoiIVOc7gDbGvBv4Q2AcpyL3eTiBczz//0/j9Eq/zxjzOw1vqYiISIiMjCb54+88AsC7vv4TRkaTLW6RwMkU7t58D3RPvkd6KqNeaBERqa6WHuj3AxngV6y1N1hrn7DWpvP/nrDWfhqnFzoLvLcZjRUREQmDkdEkG7fu5PiUU5xq/7EpNm7dqSA6AE72QMcAJ4UbYFLjoEVExIdaAuiXAndZa+/3WiD/2F3Ay+ptmIiISFht2baHVHp2QJZKZ9mybU+LWiSuHzx6AIC7HzvIZZvv5JH9xwGY1DhoERHxoZYAehJ4wcdyB4HU/JojIiISfvvGyh8Gve6XhTEymuSGbz9S+Ds5luK2B58D0FRWIiLiSy0B9H3AK4wxxmuB/GOX5pcVERFZlNb2x2u6XxbGlm17mErPnnVzJusUD1MKt4iI+FFLAP0p4HTg88aYWOmDxpgO4M/zy3yqMc0TEREJn+H1A8Rjsw+x8ViU4fUDLWqRQOUMAKVwi4iIHx1eDxhjfrvM3f8AfAC4xhhzC/BU/v6zgWuABPBV4CJgeyMbKiIiEhZDgwmOpWb41O1OunCiP87w+gGGBhMtbtnitrY/TtIjiJ6cUQq3iIhU5xlA4wTL5SZFNDiB8gfK3A/w+/l/36i3cSIiImF1YaIfgBvffSlXnn9qi1sj4GQGbNy6c1aBt66OCNOZ3JyibyIiIuVUCqC/QfkAWkRERKpwezoT/T0tbom43AyALdv2sG8sxdr+OL/7+nO44fZHNAZaRER88QygrbXvXsB2iIiItBV3vG1imQqHBcnQYGJWKv2xVJobbn+EiWmlcIuISHW1FBETERERn5JHUyyNx+jtqpTsJa32/UeceaH/5I5HuWzznYyMJlvcIhERCTId1UVERJogmU8RluAaGU3yRyO7Cn8nx1IM37KDT397F2OTadaq+JuIiJTwHUB7VOX2ZK1VETEREVm0kkdTnLFc45+DbMu2PXOKh6VzlqOTacAJqDdu3QmgIFpERIDaeqD/AX9FxUx+OQXQIiKyaO0bS/GaF69odTOkgkrzQrtS6Sxbtu1RAC0iIkBtAbRXVe4IcBbwS8ASYAQ4Vn/TREREwulYKs2J6QwJpXAHWqV5oYv5CbRFRGRx8B1AV6vKbYxZjRNknwv8cn3NEhERCa/kUSfg0hjoYCs3L3Q52o4iIuJqWBVua+0LwG8CCeCGRq1XREQkbJKawioUhgYTbNqwruIy8ViU4fUDC9QiEREJuoZOY2WtPQLcD1zdyPWKiIiExchoko/csgOA3//HBzUtUsANDSY8U+2jxrBpw7qWj38eGU1y2eY7Oef6OzTVlohIizVjHugZYE0T1isiIhJoI6NJNm7dybGUU8X5wPEpNm7dqYAn4IbXDxCPRefc/+fXXBSI4Hnj1p0kx1JYTlYG13dKRKQ1GhpAG2NOAy4DDjZyvSIiImFQblokt4qzBJebyp3oj2OAU7qdEjFvfNmprW0Y+k6JiARNLfNAv77Cw73A+cD7gH7gX+psl4iISOh4VWtWFefgGxpMFHqbb35gL9fd+hDHJtOc0h1rabv0nRIRCZZaprH6EdXngTbAKPBH822QiIhIWHlNi6QqzuHSH3eC5rHJNGcsb21b9J0SEQmWWgLou/EOoGeAJPAD4GZrbbrehomIiITN8PoBPnzzdnJFR0tVcQ6fZUs6ATg6OdPiljjfqetue4iZTK5wn75TIiKtU8s80G9oYjtERERCaWQ0yZZte0iOpYgYyFknHcsCif44w+sHWl6ISmpT6IFOtb4/YGgwwe4Dx/nqXU8C+k6JiLRaLT3QIiIiUsStkOwWeXJ7ni0newkV6IRPf4/TAz0WgB5ogFeds4Kv3vUkn7/m5Vx9yemtbo6IyKJWcxVu41hhjDnVGNPayhoiIiItVK5CskuVksNradEY6CDI5K/MZHK5KkuKiEiz+QqgjTHLjTGfMMbcD0wDLwD7gEljzE5jzJ8YYzT3s4iILCrVKiGrUnI4dXZEWNIZDcQYaIBM1gmcM7lqtVxFRKTZqgbQxph3AL8AbgAuwUn7Nvl/UeACYCPwmDHmd0qea4wxgw1us4iISCBUq4SsSsnh1d/TybGA9UBnFUCLiLRcxTHQxphrcOZ0jgA7gW8A9wPP4wTQq4FXAr8NXAj8rTGmw1r7N/n07n8GHsaZ2kpERKStDK8fmDUGupgqJYdbf0+MsVS6UCRu31iKtS0q4OUGzpmsAmgRkVbzDKCNMauAv8v/+QFr7f8us9hunOmt/twY8wHg88BfGWPuAf4CWI8TeIuIiLSdocEE1lo+dPMOAKLGkLVWlZLbwLKeTp544cSsCyTJsRQbtzqnNQu5bdOFFG6NgRYRabVKPdB/APQC13sEz7NYa//KGNMNbAIeAHqAx4EbG9FQERGRIPq1dWv40M07uO7NA7z3Dee2ujnSIEt7Yvz0yak5447d4nALGUAXeqCVwi0i0nKVxkD/GnAYp1fZr88DR3CC513A6621yfk3T0REJNhOTGUA6OvSzJDtZFlPzDNgXejicIUx0ErhFhFpuUoB9IuAn1hry8/PUYa1NgP8GGcKzMuttc/X2T4REZFAm5h2AuglCqDbSn+80/OxhS4OpyrcIiLBUSmAXgKcmMc6TwAZa+2R+TVJREQkPMbzAXSvAui20t/jzAXd2TH7VKkVxeE0D7SISHBUCqAPAWfPY51nAQfn1RoREZGQUQDdnvp7nB7oK16yqnBfoj/Opg3rWleFWz3QIiItV+lo/yDwX4wxZ1prn/WzMmPMWcCrgO82onEiIiJBN54fA93brQC6nfTHnR7ooylnLmhj4J7rriASMQveFo2BFhEJjko90DcBUeBGY4z3QKC8/DI35td5U2OaJyIiEmwTMxoD3Y6WLXEC6O3PjgFg7cltvdDc+Z/VAy0i0nqVAuh/AX4OXAHcZYz5Ja8FjTGX4MwH/QZge/65IiIibU9VuNvT0nwRsZlsjljU6XV2t/VCy+Y0D7SISFB4Hu2ttdYYMwTcg5OWfb8xZhfwM8Ctrn0q8GrgpYABngXebq3VJVIREVkUVIW7PS3LFxEDWJdYys+fHWtZAJ12U7jVAy0i0nIVj/bW2ufyPc9/DVwDXJj/V7wHN0AOuAV4n7X2cJPaKiIiEjjj0xmMgZ7OaKubIg10154XCv9/7PlxAE5MpVvSlkIRMY2BFhFpuaqXy621R4H/aoz5OPAW4BLALUl5CKfY2HestU80rZUiIiIBNT6dobezA2MWvriUNMfIaJKPj+wq/O1WWv/3XQe49OzlC96edH4eaPVAi4i0nu98M2vtk8AXm9gWERGR0BmfyqgCd5vZsm0PqXR2zv23PPgcH7vqZQveHjdwTiuAFhFpuUpFxERERKSKiZmMxj+3mX1jqbL3H51sTQp3YRorFRETEWk5BdAiIiJ1ODGVoVcBdFtZ2x8ve/8pLco0yORTuDUGWkSk9RRAi4iI1GFiWgF0uxleP0A8Nrco3CvPWfjxz1DcA60AWkSk1XTEFxERqcP4dIbVfd2tboY00NBgAnDGQu8bS7G2P86RiWnWLC3fM91sGgMtImE2MpqctT8dXj9Q2M+GkQJoERGROkxMZzUGug0NDSZmneC97nN3tmwaKzd1W2OgRSRsRkaTbNy6s1CYMTmWYuPWnQChDaKVwi0iIlKHE1Np+lSFu+31dcU4MZVpyWtnchoDLSLhVG5Wg1Q6y5Zte1rUovopgBYREZknay0TM1mWdM0dLyvtpa+7o2UBdFZjoEUkpLxmNfC6PwwCF0AbY37TGHOPMeaYMWbcGPOAMeZ9xpia2mqMOcMY8x5jzN8ZYx4yxmSMMdYY85FmtV1ERBaXqXSObM7S2xVrdVOkyfq6YxxvUQp3Oqsx0CISTl6zGnjdHwaBCqCNMV8G/hm4FLgH+A/gJcCXgFuNMbVc4r8a+GvgfwLrAHUPiIhIQ41POz2SveqBbnundHcUtvdCy2oeaBEJqeH1A3R1zA4547Eow+sHWtSi+gUmgDbGXA28FzgAXGStfYu19h3AecCjwDuA99ewyqeAvwJ+G3gZ8I+NbbGIiCx2hQBaY6DbXitTuNOaB1pEQmpoMMGHfuW8wt+J/jibNqwLbQExCFYV7o35249aax9377TWPm+MeQ/wI+B6Y8z/ttZWvQRrrf0W8C33b2OMLtuKiEhDTeQD6CWdQTqcSjP0dccYn85grcUYs6CvrTHQIhJmr3/JajZ/bw9f/a1LePOFp7W6OXULRA+0MeZ04BJgBril9HFr7V1AEjgNePXCtk5ERKQ8t0dSPdDtr6+7g2zOMjmTrb5wg2XygXNGAbSIhJCbRdPZsbAXH5slKEf8wfztLmutV0m2+4FEftkfL0irREREKpgojIEOyuFUmqWv2ykUd8uDe/mbu59i31iKtf1xhtcPND0VsTCNlcZAi0gIuQF0LBqIvtu6BeWIf07+9pkKyzxbsqyIiEhLjSuAXjTcub43fXc30xnnZDA5lmLj1p0ATQ2i3bHPWY2BFpEQmmmzADoo76I3fztRYZnx/G1fk9siIiLiiwLoxcMNoN3g2ZVKZ9mybU9TXzurFG4RCTF3Kr5YtD1SuIMSQLufZmCODMaY38vPQf3AwYMHW90cEREJIFXhXjzcFO5y9o15jT5rDI2BFpEwS2fUA90MJ/K3vRWWcR87UWGZhrHWft1ae6m19tJVq1YtxEuKiEjITExniBhnTktpb6dUuEiytj/e1NcujIHOagy0iISPuw9TAN1YT+dvz6qwzBkly4qIiLTUiakMS7o6FnxaI1l4bg90pGRTx2NRhtcPNPW13bHPmsZKRMJoppDCHZTQsz5BeRej+dsLjDFel3FfUbKsiIhIS01MZ+jT+OdFwR0DXRw/r+7rYtOGdU2vwp3OB85pBdAiEkJuCnenAujGsdbuBX4OdALXlD5ujLkcOB04APxkYVsnIiIy18hokm8/tI99x6a4bPOdjIwmW90kaaKezijRiCFrT54EfuE3Lm568Awne57VAy0iYeROY9WhImINtyl/+2fGmHPdO40xq4G/zv+52VqbK3rs/caY3caYbyxgO0VEZJEbGU2ycetOptKzpzNSEN2+jDGFauuvfvEKAA6NzyzIa7snn9mcxVoF0SISLu02D3Rg3oW19lbgK8BpwE5jzLeNMVuBx4GXASPAl0qethIYAM4sXZ8xZo0x5qfuP+Cq/EN/UHy/MWZNs96TiIi0py3b9pBKZ2fdtxDTGUnrjIwmC1XXd+wdA+DQiekFee3inmf1QotI2LjTWLVLCnegBm5Za99rjLkXeB9wORAFdgM3Al8p7n32oQt4VZn7z2R2wN01z+aKiMgiNDKaJOkxbVGzpzOS1nAzDtzg9VgqDcCPnzjE/3ztOU1//eLpqzI5S4eKvotIiBR6oDvaI4U7UAE0gLX2m8A3fS57A3CDx2NPM7vWh4iISF3cQMpLs6czktYol3EA8OMnDi/I62eyObo6IkxncpoLWkRCRyncIiIii5RXIAULM52RtIZXZsHkTPnvQiPlcpacha4O55TNndJKRCQs3GmsOkrnAQwpBdAiIiI+VUrRXojpjKQ1vDILYgtQUTabLxrWFXPytjO5WkaziYi0XjqbIxY1GKMAWkREZFHxCqQS/XEFz21seP0A8djsgcdRY+jpbP5g5Ey+56Y75pyyKYVbRMImncm1Tfo2KIAWERHxbXj9QCGV1qXU7fY3NJhg04Z1JPrjGJwLJm8YWEVqJtf0aaXcHufuDrcHWgG0iIRLJmfbKoAOXBExERGRoBoaTPDkoXG++INfAE4gNbx+QL3Pi8DQYGLWdv7be57kB7tf4Hgqw9KeWNNe16383RXTGGgRCaeZbHv1QCuAFhERqcFLTu0DYNsHX8/AaX0tbo20yqo+ZxbMg+PTTQ2g3flTT/ZAawy0iIRLOpOjcwFqRiyU9rkUICIisgAOHJsC4LSl3S1uibTSyl4ngD40Pt3U1yntgVYKt4iETTqbI9bRPmFn+7wTERGRBbD/2BTxWJRTupXEtZgtVAA9Zwy0UrhFJGTSWds2U1iBAmgREZGaHDg+xZql3W0zHYfMz8reTgAOnWhyAF2owu0E0Fn1QItIyKTbbAx0+7wTERGRBXDg2JTSt4VlPZ1EI4ZD4zNNfR03Zdut/q4x0CISNulsjk6lcIuIiCxOB45NcdopCqAXu9t37MNay5d++Asu23wnI6PJpryOGzB3xTSNlYiEUzrbXtNYtc87ERERabJczvL8cfVAL3Yjo0k2bt2JG8smx1Js3LqzKUH0yRTuyKy/RUTCwpnGqn2GPSmAFhER8enQxDSZnGWNAuhFbcu2PaTS2Vn3pdJZtmzb0/DXKlTh7tAYaBEJp3YbA60SoiIiImWMjCbZsm0P+8ZSrO2PM7x+gBetWgLAqUrhXtT2jaXK3p8cSzEymmRoMNGw1ypU4Y5pDLSIhJMCaBERkTbnpui6vYzJsRQfvGk7S7qcXsA1S+OtbJ602Nr+OEmPIHrj1p0ADQui3ZTtLk1jJSIhlclapXCLiIi0s3IpugAT0859o3uPLHSTJECG1w8Qzxf1KtXoVG43ZftkD7QCaBEJl5k264Fun3ciIiLSIF4puq6v3vXkArVEgmhoMMGmDes8H6/2/alFOqd5oEUk3NLZHJ0KoEVERNrX2v7KKdr7xqaaNm2RhMPQYIKEx/ek2venFll3GivNAy0iIZXOaBorERGRtja8fqAQsHhp1rRFEh7lUrnjsSjD6wca9honp7HSGGgRCad0NkeHxkCLiIi0r6HBBL/3+hdVXKZZ0xZJeLip3CuWdAKwsreTTRvWNbgK9+wx0ErhFpGw0RhoERGRReCCtacA8JH1L/FcppFjXSWchgYT/OP/9yoA/vjtFzY0eIaTAXShCrcCaBEJmUzW0lklqytM2uediIiINNCh8RkArrnkjAUZ6yrhtfqULgBeODHNyGiSyzbfyTnX38Flm++sO80/k509D3RWY6BFJGSceaCVwi0iItLWjkw4AfSyns4FGesq4bW8p5OOiOHexw+ycetOkmMpLM784fWOlS/tgU5rDLSIhEguZ8nktOIddQAAIABJREFUVERMRESk7R2ZmKGvu4POjkhhrGuiP44BEv3xho91lfCKRAwre7u474nDc+YPr3esfOk80BoDLSJhks5nzbRTAN3R6gaIiIgE0aHx6UJxKHDGuipgFi+rT+niwPGpso/VM1beTeHWGGgRCSM3a0Yp3CIiIm3uyMQMK3q7Wt0MCYnVfV10RMqfINYzVr6Qwq0x0CISQu5FwHbqgW6fdyIiItJARyZmWF7UAy1Syaq+bro6Ig0fK5/VGGgRCbEZBdAiIiKLw+GJmVkp3CKVrO7rYmImy8evOr9wX388VvdYeTdg7oxGiBiNgRaRcCneh7WL9nknIiIiDZLL2XwKtwJo8cedyqq/5+R35jdeeWbd4+bdlO2OqKEjEtEYaBEJlXQm3wPdoTHQIiIibev4VJpszrJ8icZAiz+n9nUDcN8vDgHQ19XB04cm6l6vGzB3RAzRiCmMJxQRCYN0fp/VEWmfsLN93omIiEiDHM7PAa0UbvHL7YG+7xeHiceivPKc5Tx9uAEBdNYSjRiMMXREjXqgRSRUNAZaRERkETiSD6BVREz8Wp3vgX72yCTnru7lnJVLePrwBLk6A95MzgmgwemF1hhoEQmTjDsGWincIiIi7evw+DSAxkCLbyt7OzH588PzTu3l7JVLmErneP5E+bmh/cpkc4XpsaIaAy0iIZNuwx7ojlY3QEREJGhOpnBrDLT40xGNsGJJJ4fGZzhvdR9nr1gCwFOHJliztL55oDuKeqDDNAZ6ZDTJlm172DeWYm1/nOH1A3UXVRORcFEKt4iIyCJwZNwJoJctibW4JRIWI6NJxibTAPztPU/y2PPHAXj60GRd683mLB35E8+OaHhSuEdGk2zcupPkWAoLJMdSbNy6k5HRZKubJiILyJ3GSgG0iIhIGzs8MUNfVwddHdFWN0VCwA0W3fTqwxMzbNm2h6iBZ+osJJbJ5WaNgQ5LCveWbXtIpbOz7kuls2zZtqdFLRKRVihMYxVtnzHQSuEWERFhdrppdyzKkk5dYxZ/ygeLzknj1+5+ku88tH/e6cuZrCVWGAMdnh7ofWOpmu4XkfaUySmFW0REpO2Uppum0lkOTaQZ/My/K+VUqqoWFNaTvpzNWaJRtwc6UijIE3Rr+8uP+/a6X0Ta04xSuEVERNpPuR5EgKOTaY3blKr8BIXzTV9O5ywdkfCNgR5eP0A8NnsIRDwWZXj9QItaJCKt4KZwdyqAFhGRoBsZTXLZ5js55/o7uGzznQoCK6jUg6hxm1JNuWCxnPmkL2dzudlVuEMSQA8NJti0YV1h/HZvVwebNqxTFW6RRaYwjZXmgRYRkSCrVgFXwfVs1XoQNW5TKnGDxUR/HANETfkTxfmkL2eythCEhmkMNMDbL15bCP6vPH+1gmeRRcgNoN1MmnagImIiIm2oWgXcjVt3Fh53g2ugcIK72OZvHV4/wIdu2o5XaKJxm1LN0GBi1u+n+DcG809fzuQsHSEcAw3OEIjpfPpmUhehRBYldwx0O6VwK4AWEWlDlSrgVgquhwYTc07+ywXY7eaXz12BBbo7DFOZ2WG0xm1KrdzfyZZte0iOpejuiMw7fTlTMgZ6JhO8ANrrgpu7H+rr7iB51DuAXmwX7EQWk4xSuEVEJAwqVcCtNr3MYpu/dWQ0yfq/vBuAvngnv/XqMwupuIn+uMZtyrwMDSa47/oreevL17Kit2ve36HiMdDRAI6BrjRcxN2nXHLWMp4/MVW297zacBMRCbfCGOg26oFun3ciIiIFlSrgVpteplKA3W5jp92T96OTaQAOnpjmtgeTDK8f4KnNV3Hf9VcqeJa6vHRNH8mxFMennO9Yrb+hdNEY6I4AjoGudMFt/7EpAF5x9nKshQP5v/0+X0TCz03hdi8EtgMF0CIibWhoMMEn3/rSwt+d0ZMppB9500soPYwVpyl7BdhL47G26ikaGU1y7c07dPIuTfXS004BYM+BE/Pqbc3mbKHnJhrAMdCVLrjtO5aiMxrhotOXAvBcmTTuahkxIhJu6WyOzmgE41FcMYwUQIuIhJxXj9ZppziB8Nkreujt7ij0pJ53at+sYlmlacrD6weIRWcf6OKxKMbQNsGmG8hkbfnePJ28S6Ocv6YPgJt+9uy8LthksrlCD3QsgPNAV8po2T82xWlLuzl9WQ9QvpBYtYwYEQm3dCZXKITYLhRAi4iEWKUerZ89fYRY1HDNpWdwZGKGQ+PTjIwm+a9/81MAejqjRA3cfd0Vs9KUhwYTvPbcFYW/3QB7LJ/mXCpswaZXz3MxnbxLo/z0icMA3Prz5Lwu2DhFxII7jZUzXGT26aSb0bL/WIo1S7tZs7QbKP8+Kz1fRMIvU5RF0y5UhVtEJKTcQLD0pDyVzhbuj0UNJ/JjL2+87yn+/t6nC4Hj5Ixz+/f3PcXK3q5ZVXCXxp3DQ8TAj4bfQCwaKVQULhWmYLNazzPo5F0aZ2Q0ycf+7eGqy1X6DWVnTWMVvCJiQ4MJTkyn+cTILgB6uzr4k6ELGRpMsGXbHl55znK6Y1FW9naVrcQ9NJhg/7EUf/Y9pxd+SVeUzw6tA+CyzXeqMrdIyM1kcwqgRUSk9aoFgu796azlH+57GoB//umzZXtd//I/HiNnmTVt1b4xMEDOwv6xKc5c0cPw+gGuvWXHrB6wsAWb5QoWFYsao6rb0jDVvm9Q/TeUzuYK01hFI5HClDBB8uJVvQAYA686ZzlDgwmyOcvzx6cKvc+JZXFGnz1aNih2T677ujt4w8BqwHuuejg5PVjUGLLWklCALRJY6UyOzjZL4VYALSISQn5OzF1TmRwGOJYqn4I9MTN3PRan8NhMNsfeo5OcuaKHt1+8lk/d/jDHUhkA1izt5qNvPj/wJ63Fc8xW6ruLx6IKnqWhqg1vMFD1O5fN2VljoIPWAw3wixfGAbj0rGU8nv//ofFpMjnLmv44I6NJHkmOkS6K/ZNjKYZv2cGnv72Lo5NpOiKGVb1dvHB8yrMy9w2372I6kys85l4oXAxz1YuEVTqbI9bRXj3Q7fVuREQWiVrHHVuYUxismpl8T9dzRycBeOLgBMdSGa4YWAXAV37rksCfrJaOEfeinmdphkqp2REDZy6PV/3OZYpSuIM4BhrgsedP0NfdwWvPXcXeo5PcfP9e3vLFewHY/N1HGb51x6zg2ZXO2cIUcpmc5ZnDEzx5aNxz/zaWSnteOAxrQUORdpfOtt8Y6PZ6NyIii8DIaJJIjdNBxKKGdHbuiXfEeM/NuKq3i2jEsPeIM//z1V+5D4CHnjsGwDOHJ2ps+cLzm0L7+Xe+XMGzNFy5+dgBlvXEePWLljOWymArjMcHyGRPFhEL4hhogMefH+e81b285NRerIVPfOthDo5PA06GS7l9TzlZC4dOzMy7rkLYChqKLAYz2VxbzQENCqBFREKl0tjnqDHEY2bOCXssYsiV6f1Z1hPjFWcvw+u4du2bXsKapd385IlDbNy6s5C6fXhiBoD/u3O/5xRaQVHphNowdwovkUYaGkywacM6Ev3xwvftC++6mNFPvolfeelpHEulC78nL04PdLDHQD/+wjgvObWP8051xkJPZ+bfRgt88FfOm3PCHY9FWdYTq/jcMBU0FFksMtkcnW2Wwq0x0CIiLVI8NtdvlVmvHtWoMbz5wlO5Y+cBbnjbADfc/gjgnLBPzmQKaZLFejo7OLWvm5l871DEOEXDXP/7zl/QHYuwM3m8kM5d7AePvsBdjx0qW+gnKAHp2v542crhy5d08vNP/GoLWiSLzdBgouzv4UWrlgDw5MEJVvZ2eT4/mzvZe9OqMdCl+6orzl/FD3cfJDmWKuw3/u/D+z0vxtXq1S9awYWJU9i+18l2WdvfzZXnr+b27d4X6MJW0FBksVAKt4iINESl+Zsr8epRzVnL0ODpAEznBxv+/btfwX3XX+k5f3NyLMX3dj1ftI65jz99aLJs8AzO+MVyhX6CNA5xeP1A2ZP6XM4GrrdcFhe3cvUTB8crLpfJniwi1oox0OX2Vf/002cLF6bc5hxLZfjmz/bWtO7Sugyd+ZNsJ/375GO//eqzuO3BJMenZu9v3JEsp3R3KJNEJKCcaayUwi0iInXyqjJbLfj0SlFc2x/nvNXOCfm/5QPDCxKnVHxO1BjP4NhVab5kL0Eah/j2i9cSi5o5B++xVNrXBQuRZkn0x+nqiPBktQA6d7L3xh0DXW3cdKO4c837rfjvJRYxLOuJFdLY33fFiwF4+elLgZPDKf7gjecCcPDENM8dneTlZ/QD8LW7nyzbhrVL4yT6u5lK5/jQTdsDOYxEZLFLax5oEZHGmk8aczvwCjKrBZ/D6wf46G0PzRpj6KYunrG8h66OCLsPnODUU7pY3dddeE7xnKruc+o5KfYqSgbBGoe490iK6YylPx5jrGQaL/eCxWL4vknw3L5jH9mc5W/ueYob733acz7jTC5X1APtnIRmiypzN0u1ueZrseWa2UX6bnnA6al+4JkxDPD5ay5iwyVn8PzxKT7/74+x98gkh8Zn+G+vOotdyWNlh6CA0xteXFgtiMNIRBa7dgyg2+vdiEiozDeNuR1U6kmuZGgwwdsuXgvMLYL17R37yOVPdo9NpgufY7lCRu7f87GsJ8ZlL15R9rGgjUPcmXTGUHrNgR2k3nJZPNx9nxv4lc5nXLwPzOSKqnDng+Zmj4NuVM8zOPub4mB2ZDTJJ7+1q/C3BT4+souR0STLl3RiDIw+OwY448TPXd1Ll0cBoqiZOybcK5Mn6AUPw6AZn6G2S/tLZ2zbpXCrB1pEWqZSGnO79x5U6kl2ub3zybEUUWMKPVSnntLFqr4ufvaxN2LygwDdE3K3V3gqk5vVE+NVyKi0Z9oPa+EnTx6Zc39nR6QQzAcls+DhfceIRQ2rervYd2xqzuNB6i2XxaPS9GrF+8BczmItdEROpnADTR0H3cie53IX1Krt95f3dPLzZ48CcPqyHpZ0RstW9a6URZMcS3HO9XcU9j0we1+nnurKyu2/ofGfoftd03Zpb+lc+/VAK4AWkZaZbxpzOxgaTHD/04f55/90Uhm7S4LPG27fNSvluLiHKjmWIhY1fGv7vsJJxnwuRhQ/t7S67r58VkA5panQrlzOFtofhJOikdEkN977FOmsZXImOyftPGi95bJ4VNvHuY+n8/PPuT3Pbip3o3qgywVKfuZOLydRsv/wunBWbb+/qq+L3QdOALArOcaO/LzzxZb1xPjUWy8oXGAspzirqTsWWbQXa2vltf9uxme4mC+it1K1C9yNvgCezuYKBQLbhQJokTYUlN6/arymGIoYM6v3IIhtb4S+7k5iUcN/WbeG+35xiLdfvHbOyYuXdNbOCkrnezHCq2ca4LLNd3qenJaTyVnOvv6Oso8t9EmR8zme7OEfS6ULhYzGJtNt/92SYPPa9xU/Did7mt3A2e2BbsRc0F6BUq3BswGe2nyV7+W93rv7nt0AuqsjwtfufrLsxYKezo7Cb7dam1PprOfjYbtYuxDHdq+gthmf4WK+iN4q1S5wN+MCuJPCrQBaRAKslp1fMw7GtaxzeP0A1932EDMl6XnFva3Dt+zg09/exdHJ9Kw05iAHP34/g1+8cIIXrezl0rOX863t+3juaKqm3p/ioLTaSel8eBUf645FPIv6VLKQJ0XO5zj7e5XOWXo6Oxj95JsWrB0i5ZT7bRWbnMkwMprkypeuBigaA32yiFi9vAIldz/rV637GK/9ipsNsio/J3ZiWZynDk6UXYe7L3H3q5/btpt9Y3OHaDS67a00n8BmPsf4WvfTa/vj8z6XaMZxSyqr1uvfjKyAdDZHrENjoKUNhKWHEhrX1jC953r43fk14ypjuXV+8KbtfPrbu7jqojVlU/u+/+jzfOeh/Z7rTOdsIVgrLbRTT1ubpdLnCrPTpVPpDK958UrGJmcAeN3nfljz67knO9VOSuejXIp3ubFwfi3kSZF6NiTIin9bybEUBmYNmTg66Uyz9vGrXgoUBdANTOH2+i1krZ1V2RqcfcnVlyS47cFk3fsYr/2Ke/+qPieAPmNZD9PpXNUAy33etbfsqOnCQtiGcPg5thef5yyNx5iYyRSGrfg9bnoFtf3xGNOZ7KwLk/FYlCvOXzXvc4nh9QN8+ObtFG+2sG2XsKl2bGzGsXMmmyvUcWgXCqAXoaCMT/SjUW0N03uul9+dXzOuMnr1nh6dTPNPP3228Hfx55/O5jh7RQ8XrD2FO3Ye8P1aQR0n5fW5fuim7bNOkN0TlL2HJ/jBo8/P+/XcE8lqJ6XzVSnF230tP6esC31SpJ4NCbri31a54RKpdJYv3fkLAKL5nudoA4uIef1GEv1xIhE4cGyKTNbO2pdcetbyhuxjKu1Xnj/u9CTf9dhB+uMxX7ULtmzbU9NnsrK3kz+66mW+2h6Ui+/Vju2l5znlalVUCrjd9+Z1MfaGt13AofFp/uSORwHojDp1O+o5l3jry9fy0Vt3MJ3fvkHPLgs6P9/VasfGSo/P97eQyVo6PSrph5UC6EUoTEUbvNp67c07AP/Bb5jec738Bg6NuspYvEOt5ZTO+fx3k85azlgW5/uPvlDT60IwexO92uT12Ty87zjzPRcuPZGsdFLaaNVO/osZKBRIq6ZRxU0+8qaX8KH8fsKlng0JKq/9hhtMxkqmsUrnx0DXE9wNrx9g+NYdc+Zz33cshbVwSncHn/n1C2etr9n7mJHRJHfsPJmR5Ld2gd9jQVdHhOlMjt+//MVV057LZQa08uJ7tWO73+E/+8ZSZQtVuu9t04Z1fOItL+Vj//Yw4Oy/P/P2CxgaTPCdh/YB8Iqzl/Fw8jhvuWgNH7ppe8XXqfT93H3gONNZy8reLiZnMtz70SsKM0u0o2ZejPHbUTS8foCP3LJjToaJe2x0LqA81NBMA2ce6PbargqgF6FmpzZ67SAaORYna21hbKzXQdVPYBfEAMyPSp/l8PoBrt/6EFNp7+mRoDE9dH4LXnnZNzaFBaYzubLTlFRT3Nag9BJUKw5Uyk/w/IV3XRyoqaFKVRrPaYCXre3zHTw3qrjJBYmlgJN2eCylomESbF77jdWndPH88emiImInx0A3ot7FzQ88y4+fmD0lnTv8+fhUZsGDxS3b9swJ6P3ULvC7333ry9dy12MH2X3ghK+pmsrtnlt18b1a4OP3fGZpPOa5v3bf25d+cxCA1523knseP8TwrQ/xhe8/zvmn9RGLGt556Rnc//RDPPb8uOdnX/o65b6f9z/lfPc2/FKCr9/9JIcnZliZHwPfbmoZ3jWf82b/Kf67Z32HIgb+9B0nL5QNDSZIjqUKc6n3dEb503fMP9Mgl7NkcioiJm2gWamNXlc0h2/Zwce2PsRkUUBX71gcmD02ttqJdqX1z0crx2WX2wmXXkx45dnLuPvxw4XnvOllp7Jl2x4+dNP2WWlafgLtSuY73YnLGOdk7ZjHtEiAZ0GbeCxSaGuQUvTLjemqR6I/PuvAFsQAsHQ8Z3Gxt7VLu3nq8ATW2qo9C40sbnLP44cA+M4fvpbTl/XU+xZFmqrcRajuWIT/9doX8dnvPlroeS4eA11PvQu3NkVPZ7TQK1vOQgeL873AX+7zi0UMvd0dswoe3v3YQZb3xPjpE4e446H9cz6TiPF3UbO4PQt1YXNoMMFX7nqCJ14YJ5OzLOmM8tl3nMzs8XMRIR6LYgwVj9v7xlI8fdgp3vazp05eXEmOpdh/LMWapd286pwVAPz9j59iYjrj+3WKv08jo0k2f283ALc9+BwAzxyebFkAXet2LF2+3BRucDIwjpQ5l0mls9xw+y6mM7k55y8PPHNkVs2B4t/tp956wZzfuNe2T46lOPv6O+ZkUwCF4RHrTu+fdf+ynk4A1iztLpyDVMo0qMSdik8BtITe8PoBrrt1BzMNnA+1UsCazlnSZY5Ifg7M5a64eql2ol1qvu95PlcRa11Ppc+k3HsrvZhw4PgUUQPX/9pL+ex3H+VbO/YVli1O03r3L5/NV+96svDYx686v6YDf709+H5OVNYs7ebA8SkyOTsrmE6lc1x78w4+eNP2skG21/er2Sc7b77wNIZvNdisrSmlvZwwpRx7Bff/+NNn+MTIw9x431PceO/Tc042igNuL7UWNxkZTfK5/InZu772U/U8S+CV1jCwwG++8kyuOH+VE0BHZo+BzmRtXfUuwKlN4aea/kJmas33An+lgofFaeovnJjmyMSM5zmF3wufbnuaNetFuWXffvFaDp2YZsMvJXh0/3F27TvOh27azpZte7ji/FWcmKq+LStNR1X83p46NAkw58JKzjrfmwefcQLrWx54ruw6PvprA3z69kfKPuamdm8suoB/eMIppLl1dC+XnLXM8zNoViZWredj5ZYvrfMyfMsOMBS+e17HOK+x6v/yn3vLPsctMOi2zW1LNeVe3W3br/zFXbPGn2/fe5RlPTEuf8kq/v0Rp0bLfH+b7msohVsCqdZxg4n+OE8fniz8oD79tpfVtWOab09kuQNzaRuW9cQ4OD7je32VrsS53OIX89npel3197qKWPy84s91vukwfk5msjlL1MBf/MdjZR93X+eqi9bQGY3wd+++lP/+dz9jZW931XUXW9vfTbKGqUPcHmc/ogayFp4bS9Hb1cGfDF0IMKvX3D24eB2Y3CuvboDWP8+qpK5qB/TkWMp3D4b3+w7HVF1+uRXG//g7jxbuKz3ZqDZljp/iJq6R0STXF83/3M4FA6W9uBehbntwLx+55SFuvO/pwgwFbs+z24uTyeXqrnfhqrbPWsjCe/XMJlDuIt5lm++ckxJebwVztz0jo0muvXmHr4u3tQba5TIGPnX7wxxLZcjmLLsPnChss9L9aSPe2527vWuSTM5kue62hyquZ/eBE2V7XMH5PpWbZhDg9u37+ezQRZ6fV7le2UbMHuJ3O7r8nPOW6ziqRaXjYnEtoHozAV3Fn+X2vWNcfEY/567u5V/v38vRiZmyv82ujkjV3+a3RpMA/Ol3d/N/fvxMW5zXABhbw1x/i9Wll15qH3jggVY3w5NX7++ynhifeusFQPkpZzqjhtedt5If7D4IMCe4AGdn6ifQPOf6O+rqbUvke6S+s2N/2atxHQZMxMw5EJZyplnIee5MDPDa81by4DNH2XnDeqIRUzENZ2k8hjHMmoO4VuXaFI9FK7bxqc1Xea6vWsGmWnV2RLj6lxL8y8/2FtprDIV08HI9hX4/i/54jMmZzKxsh3JpRMUMzJl+A+qbf7iaRH+c+66/suIy9Y73bkQbwsYNZqfKnCj55aZhjk2mWRqPMT6dmXMC7AYAlb6X7fj5ttq7vvYTAG76/1/T4pa0j0r7mUR/nLe+fA1fvetJbv391/Dc0dSc6v7Fv5fii7XVjhmlla5dfs8BGqmRPYz1npt4KXe+VMpA4Rjq1Zvo7peK37NX4Onq6+7gxNTctOlGSfTHiRint34+tUnq9fTmqzzPc7z28eX27346lkqHHZYqdz42Mprkgx7pzO3APZ72dXfwG684g7+55ylue89ruOSs5dz24F6uvWX2xZPSi/5wssPI61xuofcptTDGPGitvbTqcgqgqwt6AF0poGpE0FHtxHNkNNnQMZ9eYhFT8YpeLOL8iKu1wz1R+P6HL+fh5LGmBkXz4efzvu7Wh5jJLvyBrRbz+e65773RFwmqqXbRAhpz4aLSXKpBPqDMVyM+M68T+1r52cZSGwXQjVftN9MZjTCTzfGvv/dq1izt5vItP6KzI8JMJkdfV5SpTG7W7yUWMXRETdnevmLF44XbKQumUceSfo+Ld43QH49VDOKazeBUdy/dz563egnPHZ1a0POjzmiExz77a/O68OEW24TyF6Lc4yxQNXB2RY0hZ+2sIQFBO2dsJrc+wueuvoh3vuIM9hw4wfov3O15XI5FzKy0dS9BvqDtN4BWCncbqJSe5We8S63rL76q515d8jqmdHcYprPWd9puJelclZ5PAzkfMaX7w96171jDUl8axStVrfRK6rmnLuGRfScAJ9XZGNOUA3utSg82XkUnyplPNdFG8UpRnO8UXaXcnohGz6UadI3Yjo0InkHzP0s4VPvNuBdO79pzkG/+zEnbPaW7g0PjM0TKZGl51SAp5afSdRhVmiHAj+KLus0Icg3lx8A2gns8rtajbSm/n33hxDSbNqxbsN7WqDF0dThDFbyGJ1Q6ByxO5fY71K4a97Xc9ObuWMT3c91haEHlZ7iZm4HwxKFxwJl2DLyPy37T1sM6A04xBdAhNzKarLpzrFfp+MLig5HXjt/9YX7umov55MhOpjM5ptK5ulOpstbOSX/uiDjBY60n2h/418YcFCqlJNfaC3v1JYk51bKBOWOB9h+Ds5bHee15q7h9+z5ed95KvvvwgQa8m/rkrJ3Vy+cnddBV3APrdfCslqI/X8mxFC/e+N1Z6el+UvT8KHelNajVtBut1im9miVMxdhkcfP7m/nKXU8U/n8oXyPkWKq+tN52OKktVa44m18LcVG3WWduxVlN8x1+5H6fEguwH48aw4WJPnY8d5xzrr+DpfHy4YmfccGlwxqK1XOxotYOqaDGzol59KZ/7a4n+c6O/Zx/Wl9D2tAOF7Tbq6b4IuPuFJsZPANMzmT4o5GdXLb5Tj5403ZfPzZrnVScOx99nrFUhmvfNMBTm68iUeePJtEfZ9OGdST645j83689d0Vd66xXpU9/04Z1fOqtFxDxWXzwn376LMn8Qd4tHPLhm+d+5jkLzx5JkbOWE9MZHt53vFBkplTUGBaq9mHpTnF4/QDxWLTq84qnavJ6XjwW5Ya3XVDY/o1WWpBsLJWuO3he7IGb3+1fTkeDvrTuPmMxXLCQ8KvnN1OvdjipLWdoMMF9119Z8Rwk0R/nC++6eNa5RelF3WqCUmR4WU9sVtuHBhNs2rCO/nhszrLxWJRlPXPvd23cupNatXPgAAAgAElEQVQrzl815zsZixiW9cQKn5X72Xmp9tFkreWR/U5WnQXG5nkxKGvrn/2iUZqRFOh331Du/OkL77qYpzdfxX3XX1m4iL9pwzqiVaaXdCXHUvxwzwt1f8/b5bxIPdAhtlDpx0cn0zVXeFzbH2dFbyff3en0ig6e6UxLUE86lfujK+69c4sUefEa27NQPnTTdk5b2l3XjtTruRa4+X6n8NezRyaJRc2ccSnFV6GbPa643E6x9Oq/V0GJas8rTXN2b+t5T9WKmc2Xm33RDuMH6+V3+7vj0kqXqyf/rV3HlUt7K51TvRn7Ka/Clu1wUltNpSrflTKDqp27GCASMWQX8FzDK525p7Njzvtw31u5wlrg3ROZSmf54e6DbNqwztewI6+CtlddtGZO7Y/S99Kq87Ri1dKa++MxpjLZeRXGdFPqyx0HAXpiEWfIhcfn4J5TVBu/7S7nZ3tVmt+5HPezmW9tkqgxbXNcVhExH4JaRKye6pLF1SEbNf2Byz1xvemBZ/nJE85cgWuXdnPdm8+fM+VPJb/16jPnTEpfboqKSgXUSk/Ma/28DNDfE2tI5edmBWzFylVgrVRUA04e3Iorjx+fSlc8iJRW464lWGxkhVU/qWnlvgeNSC2u5zNYzPxsfz8XRsoVPdK2WFgqItZ8jarD4PLaHy6m38t8j0FeVZtrGapV6zSHlQpPzncmj3IqVZauZX2VPttKn1+ra9G4s9ZUSv+OxyJs2nAR9z99mH/+z73ORZMahlAWf46VpsT0+oyKA0+/y/kxn46IcsdfP8JQzDO0VbiNMb8JvAe4CIgCu4G/B75ira35ko8x5s3Ah4FLgW7gSeBfgD+31k77WUdQA2ivL31/PEYqnfWcfqB0TGYjeyajxvD5d74cgOFbd1QtXe/12n4r9FW6iFBckbHa65VTboflp/e83nmA61Xps/N74lCpgmXQTrIqTUNW6T3W+70Pw4EgrCr9rksLsknrKIBeWPXus9zjs3439Sl3HK0UePmVqHD8KveaXh0R861wXO/5mF+1vJeFUHyuWO035gaLEQOf//WXYyJmzrmSV2dJLZ9jLedq9V4I8zrfq3ZRqPj9+N03Bbn6tiuUVbiNMV8G3gtMAT8A0sAbgS8BbzTGXGOt9X2ZyhhzHfBnQBb4EXAUuBz4E+Atxpg3WmsnG/omFpBXKpIxeAbP5dK06q1SWSxnbSFduDS9o9yk9JXSqfzw6kksHVNb6fWKlVaRLl5HaTqq15XHasFz6Ws0+sBRqdiJ3+JV1VKog2S+Bbnq/d6363jBIKj0uw76wVekWbz2WX4v2rrHZ6lPuWNOvcfxavs2r+NcPedPpeo9H/PL73upphE91+Xqr1Rqh3vOl7PwsZGH2bRh3Zz09ivOX1U2Y6CWz7GWc7V6f9Ne53tQeZsUn2v6KbLXbsNEAhNAG2OuxgmeDwCvt9Y+nr//VOCHwDuA9wN/5XN9lwKbgUngSmvtf+bv7wXuAF4PfBb4UGPfycLx+tJXGs9QrgfRzzjFUl5X2NygwuvHVHp/vYFarTt8d71eqUqlVaTLPd9dxznX3+GrjX5eo5HzCjYqsGv3StGlYw1rSUNqtwNB0CzUiZxImMz3RNeli37N4/eCbCPHnzf6QncrL5y7r1EuLbnSHOV+LlzEIk59mMmScct+6q9UStF2O4XcolzFwjZVZaXzvWtv3lH2Myjen1SadsyrUyrsApPCbYx5ALgE+B/W2m+UPHY5Tg/yASDhJ5XbGHMrcDXwKWvtZ0oeexHwOJABTrXWjlVaV1BTuL00Ig3Ha3wFeBeE8FOwqhk9SPNJYWlE+yql0Feaaqnca5RLQ/7Ojv2eB5KxyXTFgkzttJNaaOXSmSqNLZfmaORYeWkOpXAHR/HvRceG1vC7DSAc2V2tUsu+v5bj9XyOKdVqDS2GoVx+hvSFadhfNaEaA22MOR3YC8wA/dbaOVGJMeY5IAFcZq39cZX1deKka/cA51prnyizzL3AZcB/s9Z+s9L6whZAN/KLXK0gRKXHgvxjakT7Kq0Dyl9Jnc9rVNrhK8hoDn2uItUpgA4u7cNaT9tgYTTzc642tnexDCvy8xm3y/c9bAH0W4HbgVFr7S95LPNvwBDwfmvtl6usbx3wEHDEWlt2kmBjzF8CH8QpJjZcaX1hC6AhGF/kILShkkYVX1CAKyKLkQJoEWlnlYrHBqlTSBonbEXEzsnfPlNhGXeupXMqLFO6vkrzM9WyvtAJwvjVILShkkYVX6i0jqB/BiIiIiIyl1etFE2VKEEJoHvztxMVlhnP3/a1YH0iIiIiIrKIqCNEyom0ugF5Jn/bqHzyutdnjPk9Y8wDxpgHDh482KBmiYiIiIiISFgFJYA+kb/trbCM+9iJCss0bH3W2q9bay+11l66atUqHy8pIiIiIiIi7SwoAfTT+duzKixzRsmyftZ3ZoPWJyIiIiIiIotcUALo0fztBcaYuMcyryhZtpLdQApYbox5sccyr6xhfSIiIiIiIrLIBSKAttbuBX4OdALXlD5ujLkcOB04APzEx/pmgP+b//O/lVnfi4DX4Mw7fce8Gy4iIiIiIiKLRiAC6LxN+ds/M8ac695pjFkN/HX+z83W2lzRY+83xuw2xnyjzPo24xQR+6gx5pVFz+kFbsR5739trR1r8PsQERERERGRNhSYANpaeyvwFeA0YKcx5tvGmK3A48DLgBHgSyVPWwkMUGass7X2fuB6oAf4sTHm340xNwNPAJcD/wl8vElvR0RERERERNpMUOaBBsBa+15jzL3A+3CC3CjOeOYbga8U9z77XN/njDEPAdfijKHuBp4Evgj8ubV2upHtFxERERERkfYVqAAawFr7TeCbPpe9AbihyjLfA75Xd8NERERERERkUQtMCreIiIiIiIhIkCmAFhEREREREfFBAbSIiIiIiIiIDwqgRURERERERHxQAC0iIiIiIiLigwJoERERERERER+MtbbVbQg8Y8xB4JlWt6OKlcChVjdC5tB2CR5tk2DSdgkmbZdg0nYJHm2TYNJ2CaagbpezrLWrqi2kALpNGGMesNZe2up2yGzaLsGjbRJM2i7BpO0STNouwaNtEkzaLsEU9u2iFG4RERERERERHxRAi4iIiIiIiPigALp9fL3VDZCytF2CR9skmLRdgknbJZi0XYJH2ySYtF2CKdTbRWOgRURERERERHxQD7SIiIiIiIiIDwqgG8gY86fGGJv/95GSx95Q9Fi1f2fW81pFywwYYz5gjPknY8xuY0wuv/yvN+C9/qYx5h5jzDFjzLgx5gFjzPuMMYH6Ti2GbWKM+Ycqbd8933U3S5C2izEmZox5ozHm88aYnxpj9htjZowxSWPMrcaYN9T5XkPxW4HFsV3C9nsJ0jbJL/MHxpibjTGPGmMOG2PSxpiDxpjvG2N+yxhj5vk+I/nfxQP538mx/O/mv85nfc22GLaLMeZHVdr+vVrX2WxB2y6NfF6Z9ejYUuNrNeN5Rc/XsWUer1W0TFM+P9OkY0tHPU+Wk4wxrwCuAyxQ7kB1APg/FVbxSuClwBPA3jpfy/Ue4AOV1jUfxpgvA+8FpoAfAGngjcCXgDcaY66x1mYb/bq1WkzbJO8+4Bdl7t/fpNeblwBul8uB/yh67QeBCeBlwNXA1caYP7bWfrLSa3m8fih+K7C4tkte4H8vAdwmAB8FVgMPAz/G2SZnAVfifLd/3RizwVqbq/R6Ja8dBbYCbwOOA/8OdOXX901jzGustX/od33Ntli2S5FtOO+p1M55rKtpArpdGvK8MuvRsWV+r9XQ53nQsaW21yrVsM+vqccWa63+1fkvvzF2AUng33C+JB+pcR278s/7WKNeC/hfwOeAdwIvBn6UX/7X63ivV+fXsR84r+j+U4FH8o99QNtkQbfJP+TX8e5Wf+5h3C44J5i3Aq8r89i7gEz+uVfU2M5Q/FYW4XYJxe8liNskv+xrgSVl7r8A56TLAr9TYzuvzT9vF3Bq0f3nFa3z7a3eJotwu/wo/7w3tPpzD+t2aXQb8+vRsSWY2+Uf0LFl3q/VjM+PJh5bApfmEVKfwekV+X3gWK1PNsa8Jv/8LJWv+NT0Wtbav7XWXmetvdla+0St7fKwMX/7UWvt40Wv9TxO7yrA9QFIIVpM2yRMArddrLV3Wmt/3Vp7T5nHbsLZqQP8Vo3NDctvBRbXdgmLwG0TAGvtvdbaiTL37wK+nP/zV2toZxSndwLgPfnfh7vOx3F6VgE+7nedTbYotksIBXK7NLKNRXRsaexrNWq7hEUYtkndmn1sCcKPK9SMMa/CucLxTWvtt+e5mv+Zv/2etTbZ5NeaN2PM6cAlwAxwS+nj1tq7cK4ynQa8emFbd9Ji2iZhEuLtMpq/Pd3vE8LyW4HFtV3CIsTbJJO/narhOa/BST1+zlp7d5nHb8FJT32FMSZRZ/vqssi2S2iEYbs0anvq2NLY11ps53Bh2CYN1NRji8ZA18EY041z9eUI8xzXaozpwUlHBPi7Zr5WAwzmb3dZa1Mey9wPJPLL/nhBWlVkEW6TYlcYYy4CeoHngXuB/7DzG/PWUCHfLuflb2sZfxP43wosyu1SLJC/l7BuE2PMOTi9DAC1nCy5v5X7yz1orZ00xuwCLs7/8zxha6ZFuF2KvcMY8w6cdMx9wA/LZYa0Qhi2S4P3fTq2NOi1mngOp2NLfa/VqM+vqccWBdD1+SwwAPyGtfbQPNdxDdAHvAB8p8mvVa9z8rfPVFjm2ZJlF9pi2ybFfrvMfY/8v/buPf6yud7j+OttkMQ4bpVcGqE6qVxyyS1zIsohEucREaIeJyKpOImDo8PEo5BrPeR2PByKUBQnatxyidyiwWBcipjkmkEzn/PH57vNtmfv/Vu/3977t397fu/n4/F7rNlrre93fdf67jVrf9f3JukzEdHvwV4GMl8kvR3YvXy8aBhBB+FegfGXL/XG6v0yEHkiaQ9yoLeFyFYAG5Kt2o6OiIuHEVXVe2VNfK8MqYv5Uq9xkJ0jJN0A7BQRbQcQGgWDkC/d/K3gZ0v3jtWr33B+tnR2rG5dv54+W9yEe4QkbQjsD1xS+uONVK0pxDkR8VqPj9Wpxcpynn5WdV4sy8V7nJZ5jNM8AbiD/IGzOplH7wC2Bu4k+55c1c+mj4OaL5IWBM4FlgCuHmYTpDF9r8C4zRcYw/fLgOXJRsBuwM7AR8q6Q8k+b8Phe6W7x+pWvgBcB+wJvBtYlBzVeyfg4XKcqyS9ZQTxdsUg5EsPfiv4funCsXr0G87Pls6O1e3r19N7xQXoEZD0ZuBMckj0vTuIZ1XmPuDO6OWxuqQ2/Hz0NRVNjOM8ISKOj4gTI+LeiHgpIp6IiMvJaQZuIvuAfLN9LL0x4PlyGjnVwWMMf6CqMXuvwLjOlzF7vwxankTEXhEhsmC1OnA8cDhwk6R3DCfJtShHko5eG8f5QkQcGhFnRMQDEfFyRDwaEecDawMPkQXrL7WPpTcGIV969FvB90uHx+rVbzg/Wzo7Vg+uX0/vFRegR+Yo8sFxQER0Mq9b7U3OjRHxxx4fqxteKMvF2uxT2/ZCm316YbzmSUsR8SpwdPm4VZ+SMZD5IukEsublSWCziGg2B2o7Y/legfGbLy2NgftlIPOkFKzujYhvkD9u1iDnoq3K90r3j9WNfGkX97PACeWjny29T2M93y+dH2tUf8P52dKZDq5fT+8VRYzJl1hjmqQZwIpk86ZG7yXn4nuIrCGZHhF7NYljAtkuf3lgr4ho2hm/G8eqi2sq2Tdqx4i4sNV+bcJ/ErgUuD0i1m6xz0+BTwH7RkRXHtYV0zaDcZgnQ5H0buA+4NWIeFO3469w/BkMWL5I+i5wAPA0Of/pva3PsLmxfK+UY89gHObLUPp5vwxinjSJdyngr+Soz4u2auLXEGY/sjB2cURs32Kf35MDwmwTEe363XXdeM2XCnFuAVwJ3B8R7+k0vhEcfwZjPF96kZ9+tnR+rF7dZ+342VL9WC3iHfb16/mzJcbApN6D9gfMIJsEVPm7o0UcW5XtLwKL9fJYdXFNLfvtMMLzXrGEfwV4c4t9Hiv7bOQ86X2eVLguG5T4/zqa+TGo+QIcU7bPBNbo4LzH7L0ynvOlwnXp2/0yaHnSIt4FyGlBAnhbxTAbl/0fa7F9UXLKngCWd76MTr5UiHOnEt9to50ng5IvvchP/GwZk/lS4br42dLZ/2HDvn70+Nkyqpk4Hv6As0pmfH2I/S4q+/2o18eq239q2X/EhTXgthLH55ps27RsewJYoN95MV7yZIj4jyvxX9HvfBjr+QJMKfs8A6zVhfMbuHtlPOTLEOkZk/fLWMuTNmEnl7B/AyZUDDOBnKokgI802b5b2XZLv/NhPOVLhTgvLnGe1u98GMR86TA//WwZg/kyRLx+tnT2nR/29ev1s8V9oPtA0jLkyHLQZh61fpF0tKRpko5usrm27jtlQIFamLcCp5SPU2IMzD08HIOaJ5LWlLR1aV5Tv35BSQcwd/qR40Yrrd00Wvki6UjgIOBZ4GMRcXvFcOPuXoHBzZf5+X4ZjTyRtImkz0qapwmdpI3qjvujiJjdsP2ckidfrl9f9ju2fDy13B+1MKuRL1Agp0UZOIOaL5ImS9pUkhrWLyrpGGA7skn4iV09mVEyqM/8ws+WPvGzpWf/h434+vXr2eJ5oPtjV2BhYFpE9GySe0lrM/c/U8hh4AGOkvT12sqI+HBD0OXI+duWa4wzIi6UdCo58ubdkq4im4ZtBkwELqFLA5WMskHNk0lkTcAzku4HHieH4/8AOQXAHOCgiLiyW+cwynqeL6VP2SHl43Rg34bfjDXTImJKw7rxeK/A4ObLJObf+2U0/g9bhRxh9aTSd+xJ8vqtwtz/yy4np01qtBKZJ8s02XYcObrrNsADkq4m5zHeHFgEODEiLu3ieYymQc2XNcl8+YukB4A/A0uX9UuTTYj3jIh7unsqo2ZUnvkd8LNlsPJlEn62dGISI79+fXm2uADdH3uUZdNh4LtoIrB+k/WrdRJpROwt6XpgH7K50ARgGnk+pw7iW08GN0/uJAdJWI+co3MtsknK4+QPqpMj4rYRxj0WjEa+LFX373XKXzPXMPeNZSXz6b0Cg5sv8/P9Mhp5cg1wJLAJOdLqhuRUIU+STfzOjYhLhhtpRMyWtB057ckewJbAbLKp6ikRcV53kt8Xg5ov15BTxq1DPp/WJwtpM4D/JX943t+NxPfJaD3ze8LPljHHz5bO9OT69fLZ4lG4zczMzMzMzCpwH2gzMzMzMzOzClyANjMzMzMzM6vABWgzMzMzMzOzClyANjMzMzMzM6vABWgzMzMzMzOzClyANjMzMzMzM6vABWgzMzMzMzOzClyANjOzYZG0gKSdJV0q6U+SXpH0jKRbJR0p6a09OOZZkkLS7sMMd3gJd3iP0tPu7/huHtP6S9K7JM2SdG6bfRaXtL+kK8q9MUvSS5JmlPtlH0nLNgm3efnOTB8iDauW/f7R4bmsV+KZ0kk8Zmbj0YL9ToCZmQ0OSSsAlwAfAuYAtwDXAosDGwCHAPtL2jMifty3hA5B0mTgN8A1ETG5g6juBO5ose2WDuK1sed7ZMXDYc02StoGOAtYCngVuBW4oWxeAfgE8EngGEk7RMQve53gViLiFkmXkvfqDyPioX6lxcxs0LgAbWZmlUhaCrgOmARMBT4fEQ/XbV8I+Brw38D5kmZHxEV9SGq9k4DzgZk9iv+SiDi8R3HbGCHpI8C2wJkR8WCT7TsCFwBBfv+PjYjnGvZ5C7AL8E3gnT1P9NCOIM/pKOAzfU6LmdnAcBNuMzOr6mSy8Pw74BP1hWeAiHgtIqYABwACfiRpmVFP5RvTNDMipkVErwrQNj58tSxPb9wg6e3AmeR3/ksRcUhj4RkgIl6KiB8AHwCu6WViq4iI28nWE5+WtHy/02NmNihcgDYzsyFJWgX4t/Jxn4iY1Wb37wN3A0sA+zTEM7X0vZzc4jhD9nWWtKakSyTNlPR3SbdJ2qPFvvP0gZY0lWy+DbBpQ7/lqW3Oa8Tq+q5Ol7SgpAMl3VX6x85s2HcxSf9R+pQ/L+llSX+Q9J+lFrNZ/AtJOkjSH0u/2yclnSNpJUnfLsc+pCHMuWX9Li3ibBqubvsGki6o6wf/dOnnu2GTfRes77sraSdJN0l6sZzjVc3CNVyTA0uYZ8s1eagcf8uyz0RJL0h6VdJybeK6s6Rli1b7NOy/IrANMD0ifttkl68AbwFujogfDhVfRLwQEX+scuyq6vKy3d9VTYKeTbZG/GI302NmNj9zE24zM6tia/Kl6z0R8bt2O0ZESDoHOJbs83lEF9OxPnAq8CfgV8BbgU2BMyStFRH7VYjjCmAWsCXwl/K5ZloX09rMAmQf8s3JvuP3AK/X/klaCbgSeC/wFPBb4BVgPfI6fkrS5PoaTkkTgEvJPrazgKuBl4CPAR8v8XWVpIOAo8vH28i+vrWC5taS9oqIM1uEPQo4ELgeuBxYA9gM2ETSJhFxS8P+K5dzWA14oRzrOWAl8nu5NHBlRDwv6Wzypc0XgP9qcuyNgQ8CD5Dfnyq2BiYAzQqglHMGaDm42Ci4Fmg1sNhHgJWB2U221c5pW1r07TYzszdyAdrMzKr4UFlWHRirVsheQ9KEiGj2430k/p2s4T6gFqek9cnC0L6SroiIX7SLICKmSLqJLEBPi4jdu5S2KlYmm/q+r3HgJkkCLiQLzycA34yIl8u2RcnmwzsB3wX2qgu6H1l4fgyYXItX0puB88h+t10jaWtgCvA4sH39CxVJmwC/AE6VdG2T/sITyNrOdUsTYiQtUM5tD/IlwSfq4ptAvnBYDfgp2e++/uXBRGDduvhPAvYGvijpqIhoLFTuXZanRERUPOXJZXlj4wZJiwCrl4+3Voyv60rN9zy135I2A3YG/g58q0nQe4HngQ9KWjoi/trThJqZzQfchNvMzKqoTb3zl4r71/abQI5K3C1/Bg6sL5BHxM3AceXjV5uG6p3DWjSXndEmzEEtRj3emiwM3gB8tVZ4BoiIv5MFz5nA50rBseYrZXlwfbwl/N5krXQ31VoUfL6xNUJEXEcOovUmWjcLPqRWeC5h5pCjt0M2qZ9Qt++nyBrjB4GdG/sWR8TzEXF13edpZK3q8mTrh9cpp1f7NFmYPGvo03zdmmXZrNn10nX/frpZ4NIU/qyGv3lqx4tV2jXDJmvOK5H0fuAi8h7cKSLmKeCXaz+NfKmzZuN2MzObl2ugzcysF1T3724+a34SEa80Wf8/wH8CG0tasEnNY6+0msaq1aBlc8ga1Wa2KssLm9WORsSLkn4PbAGsA/xa0iRyROd/kKONN4Z5QtLVwL+2OYfKJL0NWBv4G9lUvJnaAFkbtNh+WeOKiPizpOeBicCSzL1+Hy/Lc1vkezMnks3X9yZrrWu+ACwMnBMRz1aMC7KbAMBIa2e3Y24tdc2d5Pe10Qu8Mc2NFge2H+qApQ/45eQ4BPtGxM/a7P5MWb5tqHjNzMwFaDMzq6ZWoKn6I7tW6JjD3B/o3fBwi/WPlmMtQtYKVq0p79Rwp7F6MiJebbHtXWV5nKTjWuxTU2sRsEJZPt7mpcGMYaRvKLU0LgnMzlbnLS3bZN0csv96My+QBehF6tbVpnsaTt/0y4GHgI9Kek9E3FdqtWs14qcMIy5KmiCbOjeqL1QvS9aUv0FEvL/2b0mb077v9VPtuhRIWpUhCtBloLnLyD7i34uIk9rtz9zz+qch9jMzM1yANjOzam4j+9J+uOL+65XltGHUHEJ3uhZV7dvaDy+32VZrujwVeGSIeB7tSmraa5YXtTQ+Sw5c1k6zlxgxjL7HIxIRcySdTPYV/xKwPznQ10rAjfXNxyt6jnxhMJGGlgURMUvSvcD7yFYBN3WY/I6UFwUXkK0ELgK+USFY7QXB33qVLjOz+YkL0GZmVsVlZIHknyWt224k7jIY1ufKx8amo7Xa18VaBH9ni/U1k1qsX4ks8M2iuzXeo+mxsjy/zBdcRa02d4U2TdcntQg7kryopXHWKA2+VnuR8J5hhjuDHIV7N0kHM3fwsJNHkIanyAL00mTNdqOfkwXoXchBzPrp+2Rz/ZuAXUsf56HU+nE/1bNUmZnNRzyImJmZDSkippMjRAOcXEYfbmU/4P3kYE2NBYpage+9jYHq+te2s6OkhZus/2xZ3lCx/3Ot8DiWXiT/six3rBogIh4mC7ULMnee7teVa7pZi+Dt8mJRcnqwxuM9Qg6m9fYyJVSv1abg2rVFvjdV+jifSzZLPoycNuxp4CcjSMPvy/J9LbafQH7X15fUt/mUJX2dfFHwIPDJ+kHo2oRZgHw5ETTvy29mZg1cgDYzs6r2IZsOrwv8ogxg9TpJC5X5gb9XVn0lIhr7u9YGntqnDHRUC7sUcData0NrlgemlB/+tbDrAgeUjydUPJdaulaVNFYK0ReRhZjNJJ0sacnGHSStImnvhtXfL8uj6vOkvOQ4hTf2Ka5Xy4vdJK1WF25R4AfUzU/d4NCyPK/06W1M48KSti3Ti3Xqp8AfgFWAcxtGH0fSREkfbRH2xLI8kBzU7vQ2/c/b+U1ZNh0ULSKeAPYkC6GnSjpS0hKN+5W+yfO8lOgGSTsAx5B9sreKiKYjgjexOtmE+y5PYWVmVs1Y+dFgZmZjXETMLPP8Xgr8CzBd0s1kM9vFgQ3JKateAfaPiNObRPNjsrC7FnCPpBvIkZHXJaeouoQctbiV08hatm0k3UoO3LQp+Tw7JSJ+XvFcHpF0e0nHXZJuK+m+LyKOrRJHt0XEbEnbkvMo703Wut5Jzre8DNmkejWy8F8/ENbx5KjTWwD3Svo18BKwCbAQWRM7z1zQETFV0hXkSNe3S7oOmE3mxWvkVE+7Nwl3kaQDybmgfyXpPuD+EmYFskZ7Ijnq9c0jvyKvX5PtgP8ja+a3lAG6zCUAAAKbSURBVHQ9OfDVSuTUSzcCv24S9p5yLT5azuu0ESbjcnKU83leFtQd63xJr5BNxw8BDizfz8fJyorlgA+Q1+VlmoyY3qHvki8JHgEObjG42z1Nvtu1cxqqP7uZmRWugTYzs8oi4lFysKRdySbHK5MFm63JwvPLwNoR0bSwUmoANwdOLftuSRa4ziYL4M81C1fn5rLftBJ2I+BusrD25WGezvZkgX4pYCeyFrEr0z2NVLm+65LN4O8gawg/XZbPAccCOzSE+Qc5SNbBZAuBjwGTyZrTdWg/INn2ZM3lTLKp99pkv/UP0Xq0bEpBbB3gTLKQXivAL1mOuxdzm/x3JCIeJF90HEo2T94U2JYslP4M+E6b4LURry8r13Ykx6+92FlF0kZt9ruY7G/+NeBacsTy7cjv1IrAdeSc3ZMiYspI0tJGbXC3tYHdWvxt2STcbuTLgR92OT1mZvMt9XgwTDMzGwckLUOOHr06cAWw7Qiby1qXSfo28C3g0Ij4dr/TM5ok3UXW/G4REe2mjxoqno3JAvCZEfH5bqWvnyStRfbvviAiPtPv9JiZDQrXQJuZWcciYiZZs/wA2ST4vDKljllfSNqRLDzf3UnhGSAiridroXeR9K6h9h8Qh5HdFr7V74SYmQ0SF6DNzKwrIuJJshnw4eTAT2v2NUE27khaVtLpki4m+35DtbmQq/gaMIecHmuglYH3tgVOKE3kzcysIg8iZmZmXRMRjwFH9DsdNm4tQfZlfw2YDhwVEVe2D1JNRDxE6xHNB0qZx73pSGNmZtae+0CbmZmZmZmZVeAm3GZmZmZmZmYVuABtZmZmZmZmVoEL0GZmZmZmZmYVuABtZmZmZmZmVoEL0GZmZmZmZmYVuABtZmZmZmZmVsH/A1iZ0DpSfCcoAAAAAElFTkSuQmCC\n", - "text/plain": [ - "" - ] - }, - "metadata": {}, - "output_type": "display_data" - } - ], - "source": [ - "expt_cfg={\"start\":4741, \"step\":0.01, \"expts\":400, \"reps\": 20,\"rounds\":50,\n", - " \"probe_length\":soccfg.us2cycles(2.0, gen_ch=2), \"qubit_gain\":10\n", - " }\n", - "config={**hw_cfg,**readout_cfg,**qubit_cfg,**expt_cfg} #combine configs\n", - "\n", - "qspec=PulseProbeSpectroscopyProgram(soccfg, config)\n", - "expt_pts, avgi, avgq = qspec.acquire(soc, threshold=readout_cfg[\"threshold\"],load_pulses=True,progress=True, debug=False)\n", - "\n", - "subplot(111,title=\"Qubit Spectroscopy\", xlabel=\"Qubit Frequency (GHz)\", ylabel=\"Qubit Population\")\n", - "plot(expt_pts, avgi[0][0],'o-')\n", - "axvline(qubit_cfg[\"f_ge\"]);" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "# Length Rabi\n", - "\n", - "Measures Rabi oscillations by sweeping over the duration of the qubit drive pulse. This is a preliminary measurement to prove that we see Rabi oscillations. This measurement is followed up by the Amplitude Rabi experiment below.\n", - "\n", - "Note that we could speed up this measurement by using an RAveragerProgram (tProcessor loop over duration) instead of a AveragerProgram with a Python loop. We would need to update two registers, one for the pulse length and one for the sync after playing the pulse (sync_all automatically accounts for the pulse length if it's a fixed value, but that doesn't work if the pulse length is being modified by the tProcessor)." - ] - }, - { - "cell_type": "code", - "execution_count": 11, - "metadata": { - "ExecuteTime": { - "end_time": "2021-09-30T07:34:17.738477Z", - "start_time": "2021-09-30T07:34:17.646273Z" - } - }, - "outputs": [], - "source": [ - "class LengthRabiProgram(AveragerProgram):\n", - " def initialize(self):\n", - " cfg=self.cfg\n", - "\n", - " self.declare_gen(ch=cfg[\"res_ch\"], nqz=1) #Readout\n", - " self.declare_gen(ch=cfg[\"qubit_ch\"], nqz=2) #Qubit\n", - " for ch in [0,1]: #configure the readout lengths and downconversion frequencies\n", - " self.declare_readout(ch=ch, length=cfg[\"readout_length\"],\n", - " freq=cfg[\"f_res\"], gen_ch=cfg[\"res_ch\"])\n", - " \n", - " f_res=self.freq2reg(cfg[\"f_res\"], gen_ch=cfg[\"res_ch\"], ro_ch=0) # conver f_res to dac register value\n", - " f_ge=self.freq2reg(cfg[\"f_ge\"], gen_ch=cfg[\"qubit_ch\"])\n", - "\n", - " # add qubit and readout pulses to respective channels\n", - " self.set_pulse_registers(ch=cfg[\"qubit_ch\"], style=\"const\", freq=f_ge, phase=0, gain=cfg[\"qubit_gain\"], \n", - " length=cfg[\"pulse_length\"])\n", - " self.set_pulse_registers(ch=cfg[\"res_ch\"], style=\"const\", freq=f_res, phase=cfg[\"res_phase\"], gain=cfg[\"res_gain\"], \n", - " length=cfg[\"readout_length\"])\n", - "\n", - " self.synci(200)\n", - " \n", - " def body(self):\n", - " cfg=self.cfg\n", - " self.pulse(ch=cfg[\"qubit_ch\"]) #play probe pulse\n", - " self.sync_all(self.us2cycles(0.05)) # align channels and wait 50ns\n", - "\n", - " #trigger measurement, play measurement pulse, wait for qubit to relax\n", - " self.measure(pulse_ch=cfg[\"res_ch\"], \n", - " adcs=[0,1],\n", - " wait=True,\n", - " syncdelay=self.us2cycles(cfg[\"relax_delay\"]))" - ] - }, - { - "cell_type": "code", - "execution_count": 12, - "metadata": { - "ExecuteTime": { - "end_time": "2021-09-30T07:35:01.409813Z", - "start_time": "2021-09-30T07:34:17.745801Z" - } - }, - "outputs": [ - { - "data": { - "application/vnd.jupyter.widget-view+json": { - "model_id": "588ce602f14b4808aaecc0c7e14ac59b", - "version_major": 2, - "version_minor": 0 - }, - "text/plain": [ - "HBox(children=(IntProgress(value=0, max=200), HTML(value='')))" - ] - }, - "metadata": {}, - "output_type": "display_data" - }, - { - "name": "stdout", - "output_type": "stream", - "text": [ - "\n" - ] - }, - { - "data": { - "image/png": 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vuO0HRvl5rBmibCHedE8OrzeAhazLxZviKNrr2ol30SHqc4Wsuz3ktUdafgykR9h+YbyvZYjXmQ7cDXQO8R3r8MsNqkvY5xdrOQ5cEWX79+JdMIq1/TfDtlkTsm7hML/bd/rr9kdYNxaf73n+exZp+w/EUw9/fTHwxBDvy1agcKT/L9Hex7DHYy3/Fe17oUWLFi3JtKgFWkQkxTnnfos3BvYv8cYaHsXrztuGN4XQz4A/B2Y7505F288ont855/4Cr3VyG16X7la81rcv4U391B2yyaAMwM65zcCbgUeAY2Hlk5bzWqG/4d9dSUjmaOe1zq/Bew924QVKzUAd3vRHl+K91nh04rU01+DNhdziL7/FC3r+2DkX7xREw+ac63HOfRZvDGtw7uNGvO9ZI97czl8FVjjnPhujLu/Ha0n+X2AHXrDcAzQBvwe+CFQ6534XpR73AkvwupVvx0ui1Y4XBG8B/i+wYZQvNy5j8fk653biZTh/EK/VvStW+Rj7acJL3vZneEM7GvH+hxr9++8Drnfjkzzst3hd1TfgTee1H+/Y0+H//WPgzc65943nd1REZKyYcy7RdRARkSnOzP4aL9A8AxQ5/TiJiIhIElILtIiIJINgBuAXFDyLiIhIslIALSIi487MZsRY9y687qUA901MjURERESGT124RURk3JnZUbwpjH6GNx60G2/qmj/FG5udAbwOrPLHjoqIiIgknaQJoP25H98MXAJcjJfwxoB3OuceGMV+/xT4KLAKL0voLuAHwHecc72jrbeIiAzNzNqBWHNMv4GXSOjlCaqSiIiIyLBlJLoCIT4K/NVY7tDMvg18DC8D5xa87JXXA98Crjezdyrjo4jIhHgv8Ba8zMOz8abVOQPU480h/G3n3KDs2yIiIiLJJJlaoP8PXqvzc8DzwPeBaxhhC7SZvR14ADgCXO2c2+M/Pht4HG+qjU865/5xqH2VlJS4hQsXDrcKIiIiIiIiMgk8//zzx51zpUOVS5oWaOfcv4XeN7PR7nK9f/vZYPDsP89RM/so3lyk68zsn4fqyr1w4UKee+650dZHREREREREkpCZHYinXEpm4TazecCbgE7g/vD1zrkngAAwB7h8YmsnIiIiIiIik1FKBtBAlX/7snOuLUqZZ8PKioiIiIiIiESVqgH0Iv82VjN8Q1hZERERERERkahSNYDO92/PxijT4t8WRFppZreb2XNm9lxjY+OYVk5EREREREQmn1QNoIMZyEacYtw5d49z7mLn3MWlpUMmYxMREREREZEUl6oBdHAu0fwYZYLrNO+oiIiIiIiIDClVA+j9/u2CGGXmh5UVERERERERiSpVA+g6/3almeVEKXNJWFkRERERERGRqFIygHbOHQReAKYB7wxfb2bXAPOAI8DvJrZ2IiIiIiIiMhlN6gDazDaY2S4z2xBhdfCxu81sScg2s4B/8e9udM71jnc9RUREREREZPLLSHQFgszsIvoDW4AV/u1dZvY3wQedc5eHlJkLVPq3AzjnHjCz7wAfBXaY2WNAF3A9UAjUAt8a0xchIiIiIiIiKStpAmi8oPayCI8vHekOnXMfM7PfAB8HrgHSgV3AvwPfUeuziIiIiIiIxMucG/FUyVPGxRdf7J577rlEV0NERERERETGgZk975y7eKhyk3oMtIiIiIiIiMhEUQAtIiIiIiIiEodkGgMtIiIiIkmsti7Aps31HGpqo6w4h5rqStZWlSe6WiIiE0YBtIiIiIgMqbYuwPoHd9DW1QNAoKmN9Q/uAFAQLSJThrpwi4iIiMiQNm2u7wueg9q6eti0uT5BNRIRmXgKoEVERERkSIea2ob1uIhIKlIXbhGZEBo3JyIyuZUV5xCIECyXFeckoDYiIomhAFpExp3GzYmIJMZYXry8edUc7nly36DH/+91S0ZbTRGRSUMBtIiMu1jj5hRAi4iMj7G4eBkagJtBYVY6+dmZHG5uZ2Z+FsdbOiK2SouIpCoF0CISl9G0YmjcnIjIxBvtxcvwANw56OhxfPnNy/u2/8v/qeNftr3Gj587yLHTHZQV53Dt8lIe39WoITsikpKURExEhhQ8iQo0teHob8WorQvEtX208XFmsGjdw6zeuDXufYmISHxGe/EyUgDe0d07IOt21fwiunvh6OmOvt+He59uGPHvhYhIslMALSJDGu3UJR++elHEx3sdOsESERkn0S5expv0K54A/Pu/2T/kfoY71VVtXYDVG7fqAquIJCUF0CIypNG2Yrx0sJl0g9mFWRiQbjaojOYSFREZWzXVlaSFHW4z0oya6sq++7GC1XgC8Hh/B+ItN9oeTyIi400BtIgMaSStGKEnZQ/WBbh2+Sx+f8cN7Nt4M73ORdxGY6JFRMbOmspSDMjLSseA7Iw00gyuXDITGDpYjRSA52SmDwjA423NTjOLq0V5tD2eRETGmwJoERlSTXUlGWFnUZnpA1sxQoWflAH85rXjfSdNGhMtIjL+Ht5xmB4HP779CvZtvJlHPnk13b2ONZu2sWjdw3z6vu0xg9XZhdn0OijKycCA8uIcNtx2/oCEYDXVleRkpg9Zlx7n4mpRVtJJEUl2CqBFZEhrq8qZW5TNtPQ0DC94zslM46aVsyOWj9SC0N7Vn3gm2gmXxkSLiIyd2roAS2bls7KsEIDtB5swM1o7e3B4QW0kwWD1H7fsZlZBVl/voafWXTcom/baqnI23HY+5cU5fUH2ey+v6Lsf3oINsVuURztuW0RkvGkaKxEZ0vGWDg6eauPTNy7jL69fyvMHTvL27/yOy+7aQkt796BpSoZqQQiWC06LlWY26ERO80SLiIzcwZOtPLv/FDXVlZifd2LT5np6eiMHzaGCvYEccOuFZWQP0cK8tqo86rF60bqHIz4e7XeiprqST9+3fcBvQni3cRGRRFILtIgM6dd7GgFYUzkLgIMn20g3ONPe3ddiXHP/dqq+/EsWrXuYCDnCgIEtCGurynlq3XUaEy0iMg6CPXjedmFZ32PxHlODvYEAHnn5yKh6Aw23RfmtF5SRnZlGdoZ3ilqQlTGo27iISCIpgBaRIW2rb6Qkf1pfN8BNm+vpCYt5u3odp1q7cHgnX+FitSCoy56IyNjwEjhu4eu/2s209DSe23+qb120Y2q6WdQZEkKH34xEpCE72ZlpUX8P6hpOcbazh03vvIAVcwu5YH6xgmcRSSoKoEUkpp5ex5O7G7l6aSlp/mC2eFsxgidlkRLPhIo2Jvr2KPNHi4jIYP0JHNsB6OzpHZRVO/xYm5OZztffdcG49QYKHyMNcMmC6VF/D3716lEy0oxrKkupqijmxYNNcXU7FxGZKBoDLSIx7Qg0c6q1i2sqS/seKyvOIRDHCVWvc+zbePOQ5cLHRM8qzOJESwc/fvYg9zy5l0NN7YPGWYuIyECxpoAKHaccPNaGH1ejHdtH2xso9Lk/V7uD/366gUv/7jEaz3QMqsNjrxzl8sUzKczO5KKK6fz37xt47VgLlXMKRlUHEZGxogBaRGLaVn8MM7hqaX8AXVNdyfoHdww6UQs3nJOu8CQ0n/zfOmpfPNR3P5iZO1hWREQGimcKqFgJvyId28c6gdfyOQU44NiZDmDgsX3VvCJebzzLn12xEICqimLA69atAFpEkoW6cItITNvqG7lgXjEz8qb1PRbeJa84J5PM9IFj50Z70vXM/pODHos19YmIyFQ32nwSkaakGusEXt/ZtnfQY8Fj+2OvHgXg+nO9hJWLSvIozs3khYZTg7YREUkUtUCLSES1dQHufnQXh5vbKcjOoLYuMOAkKrwVo7YuELVb4Egc9sfwhVNmbhGRyD5+7Tnc8dOdAx4b7sXMWC3UYyFWK/ljrxzj3LmFzJueC4CZUTW/mLqGpnGrj4jIcCmAFpFBgologt34zrR3D9l9eqxPusZrLJ6ISKo60uxdeJxVkBVxfHEyiHZsN/N6HhVkDbxge1HFdB6vb6S5rYuinMyJrq6IyCDqwi0ig8RKRDNRomWLHcuxeCIiqaK5tYsfPLWft5w3h2f+9gb2bbyZp9Zdl1TBM0SfdSGYaPtMR/eAzOFVFdMB2H5QrdAikhzUAi0iwMAu2NEmDJnI7tPBk76vbd7FoaZ2sjPSxnwsnojIZBc8dgdbdc8rL0pwjWILzwRu1h88B4VmDr9gfhFm8ELDKa5eVhphjyIiE0sBtIgM6rIdzUR3nw52C//ao7v47hOvc9niGQPWj/W4axGRySTSsftbW1+jvDgnqY+FoUN+Fq17OGKZ4AXbguxMls0q0DhoEUka6sItIhG7bIdLZPfpd19SQa+D+559o++x4IljwG8xD06FEuz2JyKS6pJhuM1oxZM5/KIFxdQ1nKI3vKlaRCQBFECLSMyu2eM1lclwVMzM5aqlJdz33EF6/BOoVDhxFBEZjXjmfU528eS7cMDp9m7OueMXrN64VRdKRSSh1IVbRKJmRS0vzuGpddcloEaDvfuSCj7+oxe49O8e4+TZzqQYpy0ikkipMFtB+Jjo8OE4tXUBfvqCFzCH9jYK3VZEZCIpgBYRaqor+dR9Lw5I5JJsGa/bOrsBOHG2M2a5yXTiKCIyGjXVlXz6vu30uP6Dd7Idu+MRaxrETZvr6ejuHfBYaJIxEZGJpgBaRLjynJn0OijIyqClozspE3L9w2N7hiyTZtDa2c2idQ8n5WsQERlLN6yYjZkjLzOd1s6elDzuxdNNXQklRWQiKYAWER7afgiAn358NUtm5Se4NpENNU47zaDHwanWLkDd/EQk9T268wjdvfDjP7+UNy2YMfQGk9BQ3dTDM5Hr2C8i401JxESEn9YFWDWvKGmDZ4jeNbu8OId9G29mVmH2oHVKKiYiqeyndW9QMSOXiyqmJ7oq42aoJGNKKCkiE00BtMgUt/voGV4+dJpbk/xK/VAnUUea2yNup6RiIpKKjjS389vXT7C2qhwzS3R1xs3aqnI23HY+5f5F1DSDr7xtZV/rcipkIheRyUVduEWmiGhjxH5aFyA9zbhlVVmiqxjTUJlaUyEbrYhIvB7aHsA5kv7i51gIJhnbuusoH/rhcxTlTutbp2O/iEw0BdAiU0C0MWKu1/GzugBXLS2htCArwbUcWqxMrTXVlQNeI0zObLQiIvF48IUAF84vZlFJXqKrMmGuWlrKzLxp1NYFuHHFbCB1MpGLyOShAFpkCog2RuzTD2yn13l/19YFJnXClWDd7350F4eb2ynIzuArbztvUr8mEZHw3kPXLi/lly8f5diZDopyMif9sXs4MtPTeOsFZfzomQaa27ooysnkvPIiepwj359FIiPN2HDb+VPmPRGRiacx0CJTQLSxYMF5n0+1drH+wR3U1gUmsFZjb21VOb9bfz2XLpzB/Om5OoESkUkt2Hso0NSGw+s9dO/TDRw70wFAc1tqHLuH49aqcjq7e3l052EAvrV1DzmZ6TxRs4b1b1lOd6/jssWpmZFcRJKDAmiRFNfZ3Utm+tD/6qmUtfSGFbN45fBp3jjVmuiqiIiMWKTeQ+FS6dgdj1XzilhcksdP6wK83tjCQ9sP8WdXLGBmfhbXVJYC8OTuxgTXUkRSmQJokRRVWxdg9catLPvcI3T29JKeNnSW1lTJWnrDud7YuC2vHktwTURERi7eY3KqHLvjYWYsn1PA03tPcv3Xn8A5mDfDSxhWObuAOYXZbKtXAC0i40cBtEgKCu32F5QGTM/NxID0KFOepErW0sWl+SwuzeOxV48muioiIiNWnJsZV7lUOXbHo7YuwJZd/RdHHXDXw7uorQtgZqypLOU3e47T1dObuEqKSEpTAC2SgiJ1++vqdeROy2Dfxpv5+rsuiDmnciq4ccVsnt57gtPtXYmuiojIsB093U5bZzdDdR5KtWP3UDZtrqeje2BwHNqN/ZplpZzp6KauoSkR1RORKUABtEgKitadL/j42qpyNtx2PuXFORhQXpyTcllLbzx3Nl09jidCuvIFu7UvWvcwqzdunVKJd0RkcvCOU1u47K4ttHc7blk1d8Cx+r2XV6T0sXsoQ/2+rV5aQkaasa1eQ3hEZHxoGiuRFFRWnDOg+3bo40Gx5lROBVUV05mRN43HXj3KWy8oizoXNpDS74OITB7hxymAX72BWvxrAAAgAElEQVRybMoFybEM9ftWmJ3JRQums62+kc+8eflEV09EpgC1QIukoJrqSsKHOU+1bn7pacaS0jweevEQi9Y9zKfvezHiXNih2WvVQi0iiRRp+M1Uy7I9lJrqyiGHIF2zrJRXDp/m2On2ia6eiEwBaoEWSUE3rJiNc1CQlUFLRzdlxTnUVFdOqRaM2roALx5swp/qmh4XuVyw259aqEUk0Ybqniz9x+NNm+s51NQW8ffN+Uf+S+/aQnlxDtcuL+XxXY1Ry4uIDIcCaJEU9KKfPOXb77mIq5eVJrg2ibFpcz2d0aLmEMFuf7FafnSiJSIToTg3k1OtgxMfTqUs2/GINQSpti7At7e+1nc/0NTGvU83DLivi6MiMhrqwi2Sgp7df5I0g6qK4kRXJWHiabEJ7fanlh8RSaTjLR10dvdO+eE3o+VdDI09hZW6xYvIaKgFWiQFPXfgJMvnFFKQHd8coqkoWqKZNINeBzPzpvH5W1b0tUDEk3hNRGSs1dYF2LS5vu/4c8uqOdQ1NKu78QjFe9FTF0dFZKTUAi2SYrp6eqlraOKShdMTXZWEipZo5stvWwnAR9ecM+CktKa6kuzMtEHl1fIjIuMlmHsh9OLdllcbqamuZN/Gm3lq3XUKnocp3oueujgqIiOlAFokxbx6+DStnT1cvHBGoquSUNHmun7PZQsoyslk7/Gzg8r/+R8s6rufk5muqWNEZFwp6/bYi3TxNJwujorIaKgLt0iKeXb/KQAunuIt0BA90czi0jz2NrYMenxOYTYAF8wvprm1U8GziIwr5V4Ye5GydAezcAea2khPM10cFZFRUQAtkmKeP3CSedNzmFuk7mnRLC7J59d7Ggc9vvtoCwVZGdy0YjabNtfT1NpJce60BNRQRKYC5V4YH9Eunt7z5Ovc9YtdXLW0JAG1EpFUoS7cIinEOcez+09x8QK1PseyuDSPY2c6ONM+cLqYPcfOsHR2PhfO97KXv/RGcyKqJyJTRE11JWFJt9W9eBytmqdju4iMngJokRTScLKVxjMdU37881DOKc0DYF/YOOjXjrWwdFYB588rAmD7waYJr5uITB1XnDMTBxRmZwzI1aDuxePj/PIi0gxe1LFdREZBXbhFUkhw/PMlCqBjOqc0H4C9jWf7WiROnu3keEsnS2fnU5idyeLSPLarlUJExtFTrx0H4H9uv5yVZUUJrk3qy8vKYMmsfF56QwG0iIycWqBFUkRtXYAv/GwnAB/84TPU1gUSXKPkVTEzlzRjQCKxPUfPALB0dgEAF84rZvsbTTjnElJHEUl9v3ntODPypnHunMJEV2XKuGBeMdvfaNaxXURGTC3QIpNQbV1gUIbRnzwf6JsO5VBTO+sf3AGgroARZGWkM39GLq839nfh3nPMC6aXzvJap1fNK+LBugBHTrcrIZuIjDnnHE+9dpwrzplJWlr4SGgZL6vmF3P/82/wxqk25s/ITXR1RGQSUgAtMgmEBsxFOZmc7eymq8e7eh5oauPepxsGbROcS1QBdGSLS/J4PawFOj8rg7lF/VNZgTcOWgG0iIy11xtbOHq6gz9YoozQE+lCf9jO9jeaFECLyIioC7dIkqutC7D+wR0EmtpwQFNbV1/wPBTNJRrd4tJ89p84S2+v917uOdbCkln5mHktQefOLSQjzTQOWkTGxVOvnQBQAD3BKucUMC09TZm4RWTE1AItkoRCW5zTzOgZ4VgtzSUa3eLSPNq7ejnU3Ma86bnsOdbCmmWlfeuzM9M5d26hMnGLyLj4zWvHqZiRq1bQCTYtI40VZYWDMnGHD42qqa5UDy4RiUgBtEiSCbY4B8czxxs8GxBaUnOJxra4pD8Td35WBo1nOljmJxALWjWviIdePERvr9MYRREZtmhBWXdPL0+/foJbLpib6CpOSRfMK+L+59+gp9eRnmaDfncDTW3KIyIiUakLt0iS2bS5vu9HPF45mem85/IKyotzNJdonIJzQe9tbOlLILZkdv6AMhfML+ZMRzd7w+aLFhEZSvjwm2BQVlsX4KVAM2c6ulmt7tsJccH8Ylo7e3jNP/ZH+t0N5hEREQmXdC3QZvanwEeBVUA6sAv4AfAd51zvMPc1HagB3gosxnu9R4Anga87514cw6qLjIl4xi1nphn52Rk0tXapq9kIlRZkkZ+Vwd7jZ8nM8K4lhrdAn2jpAOCGbzxBud5nERmGaEHZnQ+93Nez6O8efpXuHqfjygRbFZJIrHJOQdTfXeUREZFIkiqANrNvAx8D2oEtQBdwPfAt4Hoze6dzLq6mOTOrAH4NVADHgcf9/V4IvBd4t5m92zn3kzF/ISKjUFacQyDCj3a6Gb3OKWAeI2bG4tI89jaeJc2MvGnplPkZuMFrPfqnLXv67qtLn4gMR7Tgq6mtq+/vw82acjARdhxswoDPPPAS3/zVbtLTjO7ewcOllEdERCJJmi7cZvZ2vOD5CLDKOXeLc+5WYCnwKnAr8Ilh7HIjXvD8C2CBv793AMuAL+FdPPiemWWO4csQGbWa6kpyMtMHPJaTmc7X33UB+zbezFPrrtOJ1hhZXJLH3sYWXgvLwA3B1qOBnV7UpU9E4hVv8KXjysSqrQtwR+3Ovpwhh5rb6fbHQodSHhERiSZpAmhgvX/7WedcX7OPc+4oXpdugHVmFm+dr/Vvv+Kcaw3ZXy/wFaANmIkXoIskjbVV5ax7S/+PtsYzj59zSvM51NzOzkPNLA3rvh2t9SjQ1MaidQ+zeuNWausCE1FNEZmEaqoryc6M75RFXYUnTrQ8IwVZGWT4QbR+d0UklqTowm1m84A3AZ3A/eHrnXNPmFkAKAcuB34bx2474nz64/HWU2SizJvuTWty30eu4NJFMxJcm9S1uNRLGtbU2sXSWQMTiEXrSg8MSAgE6nopIoOtrSpn7/EW/mnLa4AXlLV2dnOqtWtQWXUVnjjRLlY0t3Vx08rZvHashS2fXjOxlRKRSSVZWqCr/NuXnXPRLsM+G1Z2KI/6t58zs75JFs3ro/kFIAd4yDl3bLiVFRlvOwLNmMHKssJEVyWl7T/Rn137nif3DmhRjtSVPpy6XopILL29kJ5mbP/iTTy17jq++NaVEYfoqKvwxIl2saKsOIcFM/M4eKqN3gjjoUVEgpIlgF7k3x6IUaYhrOxQPgc8A9wMHDCzn5vZA8BuvO7i9+IlExNJOjsDzSwuySMvKyk6iaSk2roA/7y1P0nYibOdfVPMgNd6tOG28/umBotGXS9FJJondjdyUUUxRTleupXw44q6Ck+8aHlGaqorqZiRS2d3L0dOtyeodiIyGSTL2Xmw72SsyVZb/NuCGGX6OOeOm9l1wLeB9wO3hKyuB55wzp2Jtr2Z3Q7cDlBRURHPU4qMmR2BZq5YPDPR1UhpmzbX0x4lSVjwZHZtVXnf36s3bo3YpVtdL0UkksYzHewINPM3Ny0b8HjocUUmXvC937S5nkNNbQNmtvj1nkYADpxo1bFdRKJKlgA62MAzZn1mzGw58BBewP0+4DG8xGFvAjYB/2pmVzrnPhRpe+fcPcA9ABdffLH68siEOXamnaOnOzivvCjRVUlpw533s6a6kvUP7hiQfEZdL0Ukmid3e8HYmspZCa6JhIt2EWPBjDwAGk6e5YpzdBFbRCJLli7cwZbg/BhlguuithoHmVkG8BNgCXCbc+5e59wR51yzc24rcCNwFPigmV0ba18iE21noBmA8xVAj6tY4+AiCe16GfSlP1qpliQRieiJ3Y2U5GexYq5yWUwWZcXZZKQZB060Dl1YRKasZAmg9/u3C2KUmR9WNpbLgBXAPufc78JXOudOAo/4d2+Ir4oiE2Nn4LSXQEwB9LiKNQ4umrVV5Ty17jr+688vBWBG3rRxraOITE49vY4n9zRy9bIS0tJiZVGQZJKRnsa86TkcOKkAWkSiS5YAus6/XWlm0QadXBJWNpbgoOXmGGWa/FvNESRJZUegmUUleeQrgdi4Gk0yn8sWzSQ/K4PHXj06/hUVkUnnpTeaaGrtUvftSahiZh4NaoEWkRiS4gzdOXfQzF4ALgLeCfxn6HozuwaYBxwBBrUoR3DIv11uZsXOuaYIZS73b/eNrNYi42NnoJlLFuq6zkQYaTKfaRlpXFNZymOvHqO316mFSUQG2FbfSJrBVUtKEl0VGaYFM3J5seFUoqshIkksWVqgATb4t3eb2ZLgg2Y2C/gX/+5G51xvyLpPmNkuMxsQcOMF2Yfw5nr+vpkVhmyTZmafwwugu/HGSoskheMtHRxubtf450ngphWzOd7SwYtvRLo+JyJTUW1dgNUbt/KPW/aQnmY84ScSk8ljwcxcTrd309TameiqiEiSSpoA2jn3APAdYA6ww5+3+UFgD9545lrgW2GblQCV9HfZDu6rE/gAXtbt24C9ZvaIv7/XgK8AvcAnnXOvj9uLEhmmHX4CMWXgTn5rls0iPc147BV14xYRL3he/+COvunuunrcgLnlZXKomJELwH514xaRKJImgAZwzn0MeA/wAnANUI0X8H4CeLtzrifG5uH7+hVwAfBd4ASwBm8u6Azgf4HVzrlvj2X9RUZr5xteAL2yXFlbk11RbiaXLpyhcdAiAnjzCodOcwf9c8vL5LFgpjeV1YETZxNcExFJVkkxBjqUc+5HwI/iLHsncGeM9XuAj45JxUQmQDCBWGF2ZqKrInG4YcVsvvL/XuHAibN9J10iMjUNd255SU7BFmglEhORaJKqBVpkqnv50Gl1355MnAPgmk3bWL1xq7pqikxhw51bXpJTzrR0ZhVkaSorEYlKAbRIEqitC3DFhi0Emtp4ov6YArFJoLYuwN//cnff/UBTm8Y7ikxhNdWVZGcMPK0aam55SU4LZuaqBVpEolIALZJgwcQzh5vbATjd3q1AbBLQeEcRCbW2qpx3XjIfYNhzy0tyqZiRx4GTGgMtIpEl3RhokakmViCmE6/kpfGOIhKut9dRkJVB3RduJCNdbRST1YKZufzkhQ7au3rIzkxPdHVEJMno6C6SYArEJieNdxSRcE/vPcHFC6creJ7kFsz0E4lpHLSIRKAjvEiCKRCbnGqqK8kJa5nITDeNdxSZohrPdPB641kuXzwz0VWRUeqfykoBtIgMpgBaJMFqqivJUuKZSWdtVTkbbjuf8uIcDMhIM0rzs3jbhWWJrpqIJMDv950A4DIF0JPeAn8qK80FLSKRKIAWSbC1VeW88+J5gBLPTDZrq8p5at117Nt4M39363kcam7nd3tPJLpaIpIAv997krxp6ZxXVpjoqsgoFedmUpCdoS7cIhKRkoiJJIF0M3KnpfPSF2/S2LlJ6m0XlnP3o/X8+2/2ceU5JYmujohMMG/88wwdw1OAmbFgZq66cItIRDrKiySBFxqauGBesU68JrHszHQuWVDMY68eY9G6h1m9caumIhOZIo63dLDnWIvGP6eQBTPy1IVbRCLS2bpIgrV19vDq4dNUVRQnuioyCrV1AZ7YfRwABwSa2jSft8gU8cy+kwBctnhGgmsiY6W9u4f9J1p1QVREBlEXbpEE2xFoprvXcVHF9ERXRUZh0+Z62rt7Bzym+bxFpobf7z1B7rR0zi8vSnRVZAzU1gV4cncj0H9BtOb+7Xzp5y/T1NpFWXEONdWVOraLTFFqgRZJsLqGUwBcqBboSU3zeYtMPbV1AVZv3Mp//O4APb2Oh186nOgqyRjYtLmerh434LGuXsep1i71MBIRBdAiifZCwykWzMylJD8r0VWRUdB83iJTS21dgPUP7iDgXyTr6O5VUJUi4rnwGexhJCJTjwJokQRyzvFCQxNV89X6PNnVVFeSk5k+4DHN5y2SujZtrqetq2fAYwqqUkO8Fz7Vw0hkalIALZJAgaY2Gs90cNECjX+e7NZWlbPhtvMp90+80tNM83mLpDAN20hdkS6IRqIeRiJTkwJokQSqa2gCoGq+AuhUsLaqnKfWXcenblxGr3PcsGJ2oqskIuNEwzZSV+gFUQOKczLJTLcBZdTDSGTqUhZukQR6oeEU2ZlpLJ9bkOiqyBhaMbcQ52DX4dNcvFDT2oikoprqSj77k5foCMm+r6AqdaytKh/Qg6i2LsAXfraT0+3dzC3K5rNvXq4eRiJTlFqgRRKorqGJVeXFZKbrXzGVrCwvBOCVw6cTXBMRGS9rq8q5emkJAAaUF+do2EYKW1tVzrffcxEAX3/nBfqcRaYwtUCLJEBtXYCvPbqLQ83t5GdlUFsX0I9xCplTmM303ExeDiiAFkllDSfbuGLxTP7n9ssTXRWZACvmehdHXz50miuXlCS4NiKSKGr2EplgwalPDjW3A9DS0a2pT1KMmbGyrEgt0CIprOFEK/VHzyjXwRQyMz+LOYXZOraLTHFqgRaZALV1ATZtrudQUxtpZvQ4N2B9cOoTtUKnjhVlhfzwt/vp6ulVF32RFPSrV48CcMO5sxJcE5lIK8oKeflQc6KrISIJpLM6kXEWbHEONLXhYFDwHKSpT1LLyrJCOrt7eb2xJdFVEZFx8NgrR1k2O58FM/MSXRWZQCvmFvJ641naw+YAF5GpQwG0yDjbtLmetjh+aDX1SWoJjpV75ZC6+omkmubWLp7Zf5IbzlX37almZVkhPb2O3UfPJLoqIpIgCqBFxlk8Lcua+iT1LCrJIysjjZcVQIuknG27j9HT67hR45+nnBVl/YnERGRq0hhokXFWVpxDIEIQnW5Gr3OUFedQU12p8c8pJiM9jeVzC9UCLZJCgvksAk1tpBnsbzxLVcX0RFdLJtD86bkUZGXo2C4yhSmAFhlnNdWVfOaB7XT29I99zslM13yhU8CKuYU8/NIhnHOYWaKrIyKjEMxnERyS0+vgjtqdWJrpWD6FpKUZ585VIjGRqUxduEXG2dqqci6qmI4BBpQX5yh4niJWlhVyur07Yg8EEZlcIuWzCM6gIFPLirJCdh05Q09v5KSgIpLa1AItMs6ccxw42Ur1yjl8931vSnR1ZAIFx8q9cug086bnJrg2IjIa0fJZaAaFqWdFWSGtnT0cOHGWxaX5ia6OiEwwtUCLjLPdR1s43NzOmsrSRFdFJtjyOQWYKdmMSCqINlOCZlCYeoKzLOjYLjI1KYAWGWdP7D4GwDUKoKec3GkZLC7J45XDOskSmexuv3rRoMc0g8LUtGx2AZnppmO7yBQ1oi7cZjYPKAOyo5Vxzj050kqJpJJt9Y1Uzi5gbpFaKaaiwuxMtr56jEXrHqasOIdrl5fy+K5GDjW1KQO7yCThnOPXe46TblBSkMWx0x36/53CpmWksWRWgVqgRaaoYQXQZnYbsAFYMkRRN9x9i6Silo5unt1/kg+tHtxyIamvti7AjkAzPc5LNBNoauPepxv61gea2lj/4A4AnYSLJKHQaasA1l5YxjffXZXgWkkyWFlWyLb6xkRXQ0QSIO4g18zeCtyH1+27GdgL6NKbSAy/e/0EXT2Oa5ap+/ZUtGlzPd1DZGkNZvFVAC2SXMKnrQLY/PIRausC+n8Venp6Od7S0de7SL0RRKaO4bQS34E3C8/ngE3Oua7xqZJI6thWf4y8aelcvHBGoqsiCRBvdl5l8RVJPpGnrerVBS+hti7AwzuPAF6XS/UmEplahpNEbBVQ55y7S8GzyNCcc2yrb+TKJSVMy1C+vqko3uy8yuIrknw0bZVEs2lzPZ3dvQMe05zgIlPHcM7quwAdGUTiUFsX4LK7thBoauOZfSeprQskukqSADXVleRkpscsoyy+Islpet60iI/rgpfo4orI1DacLtzPA4vHqyIiqSJ83FxzW5e6dk1Rwc970+b6vqzb1y4vpbYuQEtHD2XF2Xymerm+FyJJIpg07FBTGw5v3FpoFgNd8BLwLqIEIgTLurgiMjUMJ4DeCDxqZjc65341XhUSmewij5tToqipam1V+aDPfWVZEesf3MGPb7+C+TNyE1QzEQkVKWlYukFBTiZNrV1KFCV9aqorB31XdHFFZOoYTgBdD/wd8JCZ/RPwMNAA9EYq7JxriPS4SKpT1y4ZypJZ+QC81tiiAFokSUS6+NntIHdaBnVfuClBtZJkFLyI8re1Ozjb0UO5Lq6ITCnDCaD3Q1+Ppr/xl2g0D7RMWeraJUNZUuoF0K8fa+HaylkJro2IgC5+yvCsrSrn2Jl27vrFLh755FUUZmcmukoiMkGGE+Q2MHAokMiUFTpOLrxbX011JZ/9yUt0hGToVNcuCTU9bxoz8qbx2rGWRFdFRHy6+CnDFfxuHGpqo3COAmiRqSLuANo5t3Ac6yEyaYSPkwuf/3FtVTmvHG7mnif3YaBxcxLRktJ8Xm9UAC2SLGqqK1n34Eu0d+nip8QnNIBePqcwwbURkYmibtYiwxRPkrB5071xrb+/43pmFWZPeB0l+Z0zK59Hdx5OdDVExLe2qpxTrZ186eevAGhcqwyp3A+gA03tCa6JiEwkBdAiwxTPOLkDJ1rJyUyntCBroqolk8w5pXmcau3iREsHM/P1PRFJBqvmFQHwgw9eovwEMqTS/Cwy003j5EWmmGEH0GZWAnwYWAMEL8sGgMeB7zvnGsesdiJJKJ5xcgdOtFIxIxczm8iqySQSzMT9euNZBdAiSSLYklhWpHHPMrS0NGNOUbYCaJEpJm04hc3sLcBu4KvAjcAKf7kRb4qrXX4ZkZRVU13JtPSBgXH4OLmGk2epmKnpiSS6vqmslEhMJGkc9gOhucUaeiPxKSvKUQAtMsXEHUCb2XLgJ0Ax8AzwF3iB803AR4DfA9OBB/yyIilpbVU5b145p+9+aUEWG247v2+cnHOOhpOtLND8vhJDWVEOOZnpCqBFksjh5nYKsjI0JZHErbw4h0MaAy0ypQynC/c6IBuocc59PcL6fzWzTwF/D3wW+OAY1E8kKeVmZZBm0Otg3ZuXD0gyc+xMB+1dvSxQC7TEkJZmLC7N4zVl4hZJGoea2tT6LMNSVpzDkdPtdPf0kpE+rI6dIjJJDec//TpgZ5TgGQDn3DeAncD1o62YSDLbd/wsq+YVk5lu7AlrQTxwohWAipl5iaiaTCJLZuXzulqgRZLG4eZ25mr8swxDWXEOPb2OY2c6BjxeWxdg9catLFr3MKs3bqW2LpCgGorIWBtOAD0beCmOcjsApa6UlLbv+FmWzspncUk+rx07M2Dd/hNnAdSFW4Z0Tmk+gaY2Wju7E10VEQEON7dRphZoGYbg9+Vwc/846Nq6AOsf3EGgqQ0HBJraWP/gDgXRIiliOAH0afqzbsdSBpwZspTIJNXS0c2xMx0sLMljyex8dh8d2ILYcKKV9DSjfLpaMSS2YCKxvY1nE1wTEeno7uF4S6daoGVYIs0FvWlzPW1dPQPKtXX1sGlz/YTWTUTGx3AC6OeAPzCz1dEKmNmVwFXAs6OtmEiy2n/cC3YWl+SxbFYBB0+10tbZ/0N54GQrZcXZZGoslAzhnNLgVFbqxi2SaEeavQBobpFaoCV+c/0AOjQTd7Ss3MrWLZIahnOG/y0gHXjEzL5sZueYWYaZpft/fwl4BDC/rEhK2ucH0AtL8lg6Ox/nBgZADSfOslDjnyUOC0tySTNNZSWSDIKZlMuK1QIt8cvPyqAwO2NAcBztO6TvlkhqiDuAds49DNwN5AN/izcfdBvQ7v/9OaAAuNs594uxr6pIcugLoGfmsdTvgrsnZBz0gZOtVGj8s8QhKyOdBTPzFECLJIHgGFa1QMtwlRUPnAu6prqSzHQbUCYnM52a6sqJrpqIjINh9TF1zq0HbgG2AZ14LdLp/t+PA7c45+4Y4zqKJJX9x89SVpRNzrR0FpbkkZFm7PHHQTe3ddHU2qUprCRu55TmqQu3SBI43NeFW62EMjzlxTkDxkCvrSrngnlFffdL8qex4bbzB0x5KSKT17AHaTrnfuGcux6vJXoOMBfId87doJZnmQr2Hj/LwhKvi3ZmehqLSvL6Eok1BKewmqEu3BKfXufYfbRFU52IJNihpjam52aSMy090VWRSSa8BRrgxNmuviD6L69bquBZJIWMOMuRc67HOXfMOXfUOdcz9BYiqWHf8bMsKukPkJfO7p/K6sBJfwortUBLHGrrAvx6z3EATXUikmCaA1pGqqw4h+a2Llo6vCkJT53tZN/xs1SfN4einEzqj2pyGpFUojTBIsNw6mwnzW1dAwPoWQU0nGylvauHA30t0AqgZWibNtfT1eMGPKapTkQS41CT5oCWkembC9pvha47eAqAiyqmUzmngN1HFECLpJKMaCvM7Av+n99yzp0MuR8P55z7yuiqJpJ89voJxMJboHv9TNwNJ1opyc8iLyvqv5ZIH011IpI8Dje3c8nCGYmuhkxC/XNBt7F0dgF1DU2kpxmr5hVRObuA2hcDOOcwsyH2JCKTQayz/DvxehX+L3Ay5H6s//7gegcogJaUsz9SAD2rAPCmIjpw8qy6b0vcyopzCEQIljXVicjEOtvRTXNbF3PVAi0jUNY3F7SXSOyFhlMsn1NA7rQMls0p4Ex7N4eb23VsF0kRsQLoL+MFwsfD7otMWfuOnyU9zZgf0kV7UUke6X4m7oYTrVy+eGYCayiTSU11Jesf3EFbV38aifCpTmrrAmzaXO93L82hprpSyWhExlhwCqsyjYGWEZhVkEV6mnGoqY2eXsf2g82srSoDoHK2d5G9/ugZBdAiKSJqAO2cuzPWfZGpaN/xs8yfnkNmen/6gGkZaSycmcvOQ80cPt1OhVqgJU7BQHjT5noCTW2kGXzlbSv7Hq+tCwwIsINJxkK3FZHRC7Ycag5oGYmM9DTmFGZzqKmNPcfO0NLRzUUV0wFYNjsfgN1HznBt5axEVlNExoiSiIkMQ3gG7qClswr43esncE4ZuGV41laV89S66/jBBy+h10F6ev8omU2b6we0ToOSjImMh74WaLUQygiVFWdzqLmNuoYmAKr8ALo4dxqzC7OoVyIxkR6P+MwAACAASURBVJQRdwBtZnvN7O44ym0ws9dHVy2R5OOc8wPo/EHrls3Op6O7F9Ac0DIy1ywt5ZzSPL7/m304542WUZIxkYlxqKkdM5hdqBZoGRlvLuh2Xjhwium5mSwMuZheOadQU1mJpJDhtEAvBErjKFfilx0RM/tTM/u1mTWbWYuZPWdmHzezEbWWm1m6mX3EzJ40sxNm1m5mB83s52b21pHWU6aeo6c7aOvqYVHJ4BbmJf4YJ1ALtIxMWprxoT9YxM7AaZ7ZdxKA4tzMiGXVSiYytg43t1GSn8W0DHXMk5EpK87hcHMbzzecoqpi+oCM25Wz89lzrIWeXqUSEkkF4zHXTg7QPZINzezbwMeAdmAL0AVcD3wLuN7M3umc64mxi/D9zQAeAS4FmoGngDPAfH+/R4Gfj6SuktoiJW4KtkxEaoE+eLK17++3fes31FQv1xhVGbbbqubx1f/3Cu//wTO0d3k9GoLTGgSFJxkTkdFThmQZrbKibLp6HHsbz3Jb2O//stkFdHb3cuDEWRaXDj6HEJHJZUwDaDMrAlYDR0aw7dvxgucjwNXOuT3+47OBx4FbgU8A/xjn/tLwguNLgX8DPumcOxuyPp9RtJRL6oqWuOmWC+YCsKg0b1D5f966p+9+oKldiZ5kRDa/fISuHkd3SCtFehpkZ2bQ0tHNzLxpfP6WFfpeiYyxQ01tLAvpSSQyXKEXYILjn4Mq53jfrd1HzyiAFkkBMfsq+eOe95rZXv+hd4Q+FrY0AMeACmDzCOqy3r/9bDB4BnDOHQU+6t9dN4yu3B8GrgSeAG4PDZ79/bY453aOoJ6S4qIlbnpkx2GyMtKYGzZGbtPm+r7WwtDySvQkw7Vpc/2A4BmguxcKsjMwg/devkDBs8gYc85xuLmduZrCSkZhV0iSsL+5fzu1dYG++0tm5WM2sIyITF5DBaMLQxYH5Ic9FrrM88vUAp8dTiXMbB7wJqATuD98vXPuCSAAzAEuj3O3n/Bv73bBjDwicYiWoKmlo4eO7l6u+trjA34YlehJxkq078yR5nYqZxdQd7BpgmskkvpOt3XT2tlDWbESiMnIhPdEO9zs9UQLnivkTsugYkYuu5VITCQlDBVAL/KXxXhD8R4IeSx8KQfynXNvd86dGmY9qvzbl51z0aKOZ8PKRmVmc4Dz8MZQP25m55vZnWb2PTO7y8xuHGb9ZAoZahxcsEt38IcxWnmNp5PhivVdqqoopq7hFL1KQiMypg75U1ipBVpGKp6eaMtmF2gqK5EUETOAds4d8Jf9wH8Aj4Y8Fr4cds6NKHkYXgAOcCBGmYawsrGs8m/3A58HtgNfBG7H6yr+SzN7wsxKhl9VSXU11ZVkhszFG0noD2NNdSU5mekD1ivRk4xErO9SVcV0zrR3s/d4S4JqJ5KagnNAz1ULtIxQPD3Rls8pYP+JVtq74s6FKyJJKu75GpxzH3TO/fs41SOYUeFsjDLBs8Z4snzM8G8XAXcA/wWcCxQC1wGvAlcD9w27ppLy1laVc13lLMDrdhFN8IdxbVU5G247n/LiHAwoL85hw23na6yqDFus79JFFcUAvHBA3bhFxtKhpnYAytQCLSMUT0+0ZbML6On1snSLyOQ2HtNYjUQwThmrvonBCwMZwBbn3PtD1j1uZjcBu4Frzewaf4z1wAqZ3Y7XYk1FRcUYVUsmi+LcacwqyOKZv72B1Ru3EohwdTn0h3FtVbkCZhkT0b5Li0vyKczOoO7gKd51yfwE1Ewk9dTWBdj4yC4AbvvOU3xGUxDKCNRUVw6YvQMG90R745Q33eUf/tOvKfenx9R3TWRyGnYAbWaXAO8AluG16EZqpHPOueuHsdvgoJBYuf2D6+IZQBJa5p7wlc65N8zsYbzXcT1epu7wMvcEt7344os16HCKOXy6nblFXne+eH4YRcZbWppRVfH/2bvz+DjP6v77n2tG22izbC22Je9L5NjZRAyhOCVbqSAFIkJDKeXXpxs8LCm0NCo2lBK22mAoDXv5Ae1DaaAQggqERoWYBJIQsimJ40WxHdtyRpItydaukUYz1/PHzMiSLI1mrJm5Z/m+Xy+9Jpq5NT5JNLfvc1/nOmepVqBFEmT2yMJOjSCUixT5fdnb2k5n/xi1sxLkljYvdz0wfdzlGM0/eJaP/eQA/aP+C44XkfQWVwJtjPk88D5mrhhPT6Aj38ebcJ4IP66NckxkyeVElGNmvx/A8XmOiTy/Iob3kxxzesDH2spiYOG/GEVSpWFNBXc9cIQhn5+yonynwxHJOC1t3qlzuctAYNbVSqS/hc7vEq9olWhzNRnzBy3nRv3A+eakkfcRkfQWcwJtjPlj4P3AKeAThFZvXwM0ApuAPyE0d/nTwP1xxtEWftxmjPHM04n75bOOjeYwof3UJUDlPMdEGoipI49coGtgjFduWDb1vUq0JR28bM1SrIVnTw1w7Wb1QBSJx+wV59nJc4RGEEqixfI7pZs3Ipkj5iZiwDuASeBGa+03gC4Aa+3PrbVftdZeC9wJfIDozcAuYK09BTwNFAC3zX7dGHMdoTnT3cBvYng/P/DT8LcXlJIbY/IJNREDeDKeWCX7jU5MMuibZPkSdWSV9HLl6lAjsbaOeCcFisje1vYZW3HmoxGEkmix/k7p5o1IZogngb4SeMxaeyzKMZ8gtEL94YuIZXf48dPGmE2RJ40xNcBXwt/usdYGp712uzHmsDHm2/O8XxB4rzHmpmk/4ya0Sr4R8AI/uohYJYt1D4Q6sq5UAi1pZoknn801pTytBFokbrEkJ+pvIckw14jCuejmjUhmiCeBLgFemvb9OIAxZmqslLXWAk8QKuWOi7X2HuCrhPYk7zfG/MQYcy9wBNgKtABfmvVjVUA9cEGbbGvts8DfAEWE5j4/Zoy5h1D37b8FBoDb5ikXlxzWPRhKoJeXK4GW9NOwpoK2U/2ETrciEqsV89wUdRujEYSSVLNHFFZ48sl3z+zBq5s3IpkjniZiZ5i5n7gn/LiJmfuSlxC9m/a8rLXvMcY8DLwXuA5wE9rP/C3gq9NXn2N8vy8aY/YDdwCvBF5GqPT868Bua+2Ji4lTstv5FWjdCZb0Y4D+UT8bdv1MDe1E4nBZbTld4fN7hCffraRZUmJ2L5XQCLVDdA+Os8STz8feuE2/hyIZIp4E+iiwftr3TxC6lnsX8P8CGGPqgRsIrRpfFGvt3cDdMR57J6F919GOeRB48GLjkdwTWYFeoRVoSTMtbV5anukEQqMO1LlVJDYvnRvloSO9XL2mgu7BcU1UEMc1NdRxy1W1XH7n//ImNSoVySjxJNA/Bz5pjLnUWnsIaCW0h/ivjDENhPY+30ioEdh/JDxSkRTpHvCxxJOPp2Dh/UoiqbS3tZ3xyZmFOOrcKjK/yNgqb3j/8+uvrOXPd6xf4KdEUsMYw8bqEo6e0UAYkUwSTwL9n4T2TBcDWGvHjTFvIdSEa3v4C+AnwOcTGaRIKnUP+LT6LGlpviZI6twqcqHZY6sAPnN/O0uLC3TDSdLGxupSHj3W53QYIhKHmJuIWWs7rLWfstY+Ne253xAq634doTnQV1trb7HWTiY+VJHU6B70zdtsRsRJ83VodRlYv/M+duzZR0ubN8VRiaSnucZWRSo2RNLFxppSugd9DI/r0lkkU8TThXtO1toxa22rtfa71tq2hX9CJL1pBVrS1XyjUAJ25p5oJdEiqtiQzLCpJtR395jKuEUyxqITaJFs4g8E6RkeZ7lWoCUNzR6FMmsKCqAVNpGI+So2NGtX0snG6lACrX3QIplj3j3QxpgLZivHw1rbsZifF3FCz9A41sJKJdCSpqaPQlm/8745j9EKm0ioYqP5nmfxB87PTNesXUk3ayuLyXMZjvUogRbJFNGaiJ0gVBV4MewC7y2SljTCSjJJbYVnqrvw7OdFcl1TQx3/s7+L1oOnMaCxVZKW8t0u1lWpE7dIJomW5HZw8Qm0SEbqHggn0FqBlgzQ3Fh/QZdhrbCJnJef52LNsmJ+9fc3OB2KyLw2VpdwRAm0SMaYN4G21q5LYRwiaWEqgdYKtGSAyEraZ1oP09nvo6TQzaeaLtcKm0jY0TPDbKwucToMkag21ZTyi0NnmJgMUpCn9kQi6U6fUpFpugd9FOa5qCjOdzoUkZg0NdTx6M6b2LGpknWVJUqeRcICQcvx3pGpLsci6WpTTSmBoKXj7IjToYhIDJRAi0zTPRCaAW3MHO2NRdLY9rXLONQ1qFmiImHec2OMTwaVQEvaUydukcyiBFpkGs2Alky1fd1SghbaOs45HYpIWjjaMwScT05E0pUSaJHMEnMCbYwJxPGlJRDJSN2DPjUQk4zUsGYpLgNPnFACLQJw7EyoHFYJtKS7ksI8apcUcaxHJdwimSCeUVPx1LSq/lUyjrVWCbRkrNLCPLbWlvPkibNOhyKSFo6eGaaypIClJQVOhyKyoI01pVqBFskQMa9AW2tdc30BbmAD8NfAWeAT4edFMsq5UT8Tk0GVcEvG2r52GW0d/fgDQadDEXHc0Z5hNmr/s2SIjdWlHOsZJhjUBFmRdLfoRNeGnLDWfhloAj5kjHnr4kMTSa2ugTEAVmoFWjLUy9ctY8wf4GDnoNOhiDjKWsvRM8NqICYZY1NNKaMTAboGfU6HIiILSOhKsbX2YeBp4G8S+b4iqXA6/JfWcq1AS4bavm4pAE+ojFtyREublx179rF+533s2LOPljYvAH0jEwyM+bX/WTJG5Hf1mMq4RdJePHugY3USeF0S3lckYVravOxtbaezf4zaCg/NjfWMTIR6361c4nE4OpGLs7y8iNXLPDx18hx/9btORyOSXC1tXnbdu58xfwAAb/8Yu+7dDzDVy0Ir0JIpjpwJdY3/0289Tl34uqSpoc7hqERkLsnYq7wN0AY8SVuRiy5v/xiW8xddv2o/g8tAVakazkjmevnaZTxx4hzWah+dZLe9re1TyXPEmD/A3tZ2jvWEVvGUQEsmaGnzsvtnh6a+j1yXRCoqRCS9JCyBNsZUGmO+DGwBfpuo9xVJtPkuun59tI+asiLy3OqBJ5nL7Tb0Do+zYdfPZpS0imSbzv6xeZ8/emYYT76bldqSIxkgdF0yc+0pcjNIRNJPzCXcxpgXo7xcClQSGl81Ady5uLBEkme+i67RiQCbl5elOBqRxGlp8/LjZzoBZlRXACoFlKxTW+HBO8f5vLbCw7GeETbWlOByaaqmpL9oN4NEJP3Es9S2LspXFeAHHgBusNY+mqgARRKttmL+Pc7PnurXqp1krL2t7YxPahVDckNzYz357pkJsiffTXNjPcfODLNJDcQkQ8x3XRLtekVEnBNPAr0+ylcdUGqtfY219jcJj1IkgZob68mLsiqhvUeSqbSKIbmkqaGOV19SPfW922X4VNNlvGbrcrz9Y+rALRmjubEeT757xnORm0Eikn5iTqCttSejfHVZayeTGahIojQ11LFjYyWG0J4DM0curVU7yURaxZBcU+B2saGqhK+9/WUEgpbiQjfHe0cANRCTzNHUUMfuWy+npqwQgKXF+ey+9XJtvRFJU+qWJDmptCif9VUlHN/zB6HNonPQqp1kGq1iSK450TfKuqoSXrN1BauXefjmw8c5ekYduCXzNDXU8fAHb8TtMrztmjVKnkXSWNxzoI0xBcCbgeuBVYTSj07gQeCH1trxBMYnkhTdgz6Wh7uzRmtEI5JJIhdcn77/MF0DPsqL8vj4LZfpQkyykrWWk30jvHLDMtwuw5+9aj2f+OlBPAV5uF2GtZUlTocoEpeCPBdrlhXzYs+I06GISBRxrUAbY14FvAB8B3gH8DrgZuCvgP8AXjDGXJvoIEUS7fSgj+XloVIprdpJNmlqqOM3u25ibWUxOzZVKXmWrNUzNM7oRIB14UT5LdtXUeg2/OqFHgJByw2ffVC9LCTjbKwuUQItkubiGWO1DfhfoBh4EfgucCL88jrgj4BNwP3GmGustQcSGqlIglhrOTM4zvIloRXoSIKxt7Wdzv4xais8NDfWK/GQjHbFqgqeOnHW6TBEkuZE3ygA66pCCfQDh84wOW1Ljsa4SSbaUF3Kr470Egha3BrDJpKW4inh/jih5Hk38BFr7YxZKcaYj4aP+RDwMeAPExWkSCKdHZlgIhBkRbiEG0IXV7rAkmxy5aol/OTZTs4M+agpK1r4B0QyzIlws7B1lcVA6CZoIDizqUWkIaTO75IpNlSVMDEZxHtujDXh320RSS/xlHBfB7Rbaz88O3kGsNYGrbX/ALQT2h8tkpa6B30AMxJokWxz5eoKAJ47NeBwJCLJcaJvhDyXoS7cr0Jj3CQbbAiPXzvWO+xwJCIyn3gSaA/wdAzHPQ0oM5G0dWYw1OcuUsItko221Zbjdhmefanf6VBEkuJk3yirlxWT5w5dymiMm2SDDdWhLQnaBy2SvuJJoNuBlTEctxI4cnHhiCRfZAV6uVagJYsVF+SxuaaUZ1/SCrRkp+O9I6ydVuKqhpCSDSpLCigvyuPFHq1Ai6SreBLorwGvNsbsmO+A8GuvBv51sYGJJEv3gA9joKas0OlQRJLqqtUVPPdSP9bOM+xcJENFRlitmzaqqqmhjt23Xk5dhQcD1FV42H3r5dr/LBnFGMOG6lKtQIuksZibiFlrv26M2UKoy/ZXgP8EjodfXgf8CfAe4C5r7dcSHahIopwe9FFZUki+O64pbiIZ54pVFXzviVN0nB3VTFzJKr3DE4xMBKYaiEWoIaRkgw3VJTxytNfpMERkHjFnEMaYAPB+Qp247wDagP7w1zNAM1AC/I0xJjDrazLxoYtcnNODPlYs0eqzZL8rVy8B4JlT2gct2eVEX2h1bm2VbgxJ9tlYXcrpwXGGx3X5LJKO4lmCM4v40lKfpI3uwXGWa6yP5IBLlpdRmOfiOe2DlixzfoSVEmjJPhvCN4aOq4xbJC3FnNhaa12L+Urmv4RIPE4P+tSBW3JCvtvFZXVLeFYr0JJlTvaN4nYZVi1Vh23JPhtrQqOsXtQoK5G0pMRWcsr4ZICzIxOaAS0548pVFTzfOcBkIOh0KCIJc7xvhFVLPeplIVlpbWUxLgPHtAItkpb0N4/klMgMaCXQkiuuXL0Enz/IC6e1kiHZ42TfiBrjSdYqzHOzammxRlmJpKmYu3BHGGPygT8ErgcirS69wIPAPdZaf6KCE0m00+EZ0DXlaiImuSFy0+jmL/yaugoPzY316lIsGc1ay8neUa5es9TpUESSZkN1iVagRdJUXAm0MeZq4AfAWkLNwab7K+CTxpjbrLVPJyg+kYTqDifQK7QHWnJAS5uXf/55+9T33v4xdt27H0BJtGSsvpEJhsYntQItWW1DVSmPvdhHMGhxuWZfcouIk+IZY7UKaCU08/klYA/wDuCdwG6gA1gPtBpjdGUmaal7IJxAq4RbcsDe1nbG/DP3Po/5A+xtbZ/nJ0TS38nwCKt1VcULHCmSuTZUl+DzB+kK3/gXkfQRzwr0TmAZ8AWgeXaptjHmo8BeQrOidwJ/naggRRLlzNA4hXkulnjynQ5FJOk6+8fiel4kE5zoHQU0wkqy24bq0O/3iz3D1FWo27xIOokngX4t8CLwt9ZaO/tFa+2kMebvgDcAN6MEWtJQ94CP5eVFGKNyKMl+tRUevHMky7W6GJMMdqJvBJeBVUu1Ai3Za2N1eJRVzwi/u7maljYve1vb6ewfo7bCww1bqvnl4Z6p79XfQiR14kmg64AfzZU8R1hrg8aYx4E3LToykSToHvSpfFtyRnNjPbvu3c+YPzD1nMvAHb9/iYNRiSzOib5R6pZ6KMjTIBHJXo8e7cUAH/3xAT7/8xcYmZjEHwhdgnv7x/jOYx1Tx6q/hUhqxfO3zxihEu6FLA0fK5J2zgz6WK4GYpIjmhrq2H3r5dRVeDDAEk8+QQsf+8lB1u+8jx179tHS5nU6TJGYtbR5uf/5Lk6dHdPvr2StljYvH/rR80RWrPrH/FPJ83zG/AH+7vvP6twukgLxrEA/B1xvjNlirT081wHGmHrgBuCxRAQnkkjWWroHfbxGI6wkhzQ11E2tSPzoqZf4u3uepX8s1MJCqxaSSVravOy697kZq3D6/ZVsFGoAGVj4wFkCVp8NkVSIZwX6m0ABsM8Y8xfGmILIC8aYfGPMnwMPAPnA/01smCKLNzg2ic8fZLlKuCVHffbnLxCctYihrtySKdRVXnJFIho96rMhkjwxJ9DW2v8AvgusIJQgjxhjOowxJ4FR4BtALfBda+1/JiNYkcWIzIBWAi25Sl25JZPp91dyRaIaPeqzIZIccXXgsNb+CXA7cAJwA6uA1eF/Pg7cbq19e4JjFEmI0+EEeoX2QEuOmu+iTF25JRPo91dyRXNjPZ5894zn8l2GpcX5GKCuwsPbX7lmqr+Fe57JIvpsiCRHPHugAbDWfgX4ijGmjlBnbgO8ZK1VtwJJa5EVaHXhllw1V1duT76b5sZ6B6MSic0dv38JH/j+s0zfhaDfX8lGkX3L08dWRRtTFeoPoHO7SKrEnUBHhBNmJc2SMU4PhBLo6jI1EZPcdP6i7DDefh/FBW7+6U2Xq8mMZIQrV1dgCXWTHxzza/atZLXpDSBjORbgM62H6ez3UVaYxyeaLtNnQyRJFkygjTE3ArcBa4Fx4BngG1pxlkzTPehjaXE+RbPKokRySeSi7E+/9Ti9Q+O6wJKM8dALPQD85PZrWVNZ7HA0Iuklcm5/+ad+wU1banRuF0miqAm0MeYLwHsj34Yf3wh8wBhzi7X2wSTGJpJQpwfH1UBMJGzrynK+eexFJiaDFOTF1Q5DxBEPtvewoapEybNIFFWlhfQMjTsdhsgMLW3emLckZIJ5r5qMMbcQahhmgIeBzxMaZfUSUAbcbYxRLaxkjNODPjUQEwnbWluOP2A5cmbI6VBEFuTzB3jsxT6uq692OhSRtFZdVkjvsBJoSR+RPfre/jEs5+eUt7RlbjFztGWHdwAW+Gtr7XXW2r+z1r4DuBR4CFgOvCEFMYokRPegj+VlSqBFALbVlgNwsHPQ4UhEFvbYi32MTwa5vr7G6VBE0lpVaYFWoCWt7G1tn9HgDjJ/Tnm0BPpq4LC19svTn7TWjgI7Ca1MX53E2EQSoqXNy6v2PEDP0Dg/e74ro+94iSTKusoSPPluDnYpgZb092B7D4V5Lq5Zv8zpUETSWmgFegJr7cIHi6TAfPPIM3lOebQEuhLYP89rz4Uf9TeZpLVI2Uhnf6gD95BvMuPLRkQSwe0yXLqyjANagZYM8KsXevidjZVqAimygOrSQiYCQQbHJp0ORQSYfx55Js8pj5ZA5wGjc71grY3cMshPeEQiCZSNZSMiibK1tpxDnYNaqZC01tE3you9I1x3ifY/iywkMqqzZ9jncCQiIc2N9eS5zIznMn1OuVqvSlbLxrIRkUTZunIJQ+OTnDqrz4Okp5Y2L2/40sMAfO2hY6oeEllAdWk4gR6acDgSkZCmhjouWV5KnstggLoKD7tvvTyju3AvNAf6KmPMP17M69baj198WCKJUVvhwTtHspzJZSMiiTLVSKxrQKOBJO1EtuBEqohOD46z697QzrJMvvASSabzK9BqJCbp49yon9dfsZJ/eWuD06EkxEIJ9JXhr/lcNcfrhlD3biXQ4rjmxnqa73kWf+B8iWqml42IJEr9ijLcLsOBzkFee9lKp8ORHDd7TujoxOS8W3CUQIvMrWpqBVoJtKSHsyMTdA342Bq+aZ8NoiXQ/1/KohBJktdetoKPtOzHYPEHglkxvF0kUYry3WysLtEoK3Hc7NXmuSqHIrQFR2R+Szz55LuNZkFL2ohcY2yrXeJwJIkzbwJtrf3zVAYikgzfe7yDofEAd7/jGl61scrpcETSztaV5fz2+Fmnw5AcN1fDx/loC47I/FwuQ1VpoVagJW0c7BoA4NKV2bMCrSZikrV8/gBffegYr1i3jN/ZUOl0OCJpaVvtEroGfJwdUcMZcU6sq8ragiOysKrSQq1AS9o40DnIyiVFLCspcDqUhEm7BNoY8zZjzK+NMQPGmGFjzJPGmPcaYxYdqzHmncYYG/76UiLilfTT0uZlx559bPnI/ZweHGf7uqUYYxb+QZEcFNmTpDJucdJ8q8oVnnzqKjxZ07lVJBWqy7QCLenjYOfgVNPSbLFQE7GUMsZ8GXgP4AMeAPzATcCXgJuMMbdZa2Or8brwvdcCnyXU4EzZVJaavY8O4N8eOc4ly8t00SUyh63hkqoDnQNcu1nbHMQZzY31fPCHzzE+GZx6zpPv5s43btO5WyRO1aWFPO8dcDoMEXz+AMd6hnndZSucDiWh0mYF2hjzZkLJczdwhbX29dbaNwGbgUPAm4DbL/K9DfBNQv++305MxJKO5tpHN+YPsre13aGIRNLbQy/04Daw+38Os2PPPs3ZFUc0NdTRdFUtgFabRRapqqyAvpEJgkG78MEiSXS4e4igha1Z1EAM0msFelf48YPW2iORJ621p40x7wYeBHYaY75orQ3O9QZRvIvQSvb7AG2GzWLz7aNT11aRC0UqNiJT3rz9Y5qzK44ZmQiwvLyQx3bdpG03IotQXVpIIGg5NzpBZXislYgTznfgzq4S7rRYgTbGrAKuBiaAH8x+3Vr7EOAFVgCvjPO91wOfAR4hVAouWWy+fXTq2ipyobkrNgKq2JCUCwYtjx7rY8emKiXPIotUVRaeBa1GYuKwA50DlBXlsWppdl2Hp0UCDTSEHw9Ya+dbKnxi1rELCpduf4vQSvtfWmtVy5LlmhvrKcib+Wutrq0ic1PFhqSLQ92DnB2Z4NpN2ocvsljV4VXn3iFNVxBnHewaZOvK8qy7MZouCfT68OPJKMd0zDo2FrcD1wN3Wmu1pJIDmhrquC7cCEn76ESiU8WGpItHj/YBsEMJtMiiVU+tQPscjkRyWSBoOdw1NDXtI5vEvAfaRx/fJwAAIABJREFUGLMPuN9a+5kFjrsDuNlae2MccZSGH0eiHDMcfiyL5Q2NMRuB3cBThLpvS5ZoafOyt7Wdzv4xais8NDfWz0iQuwfH2b52Kfe8+1UORimS/pob6y/oWq+KDXHCw0d72VRTyvLyIqdDEcl4kRJurUCLk473jjDmD0xN+8gm8TQRux44EcNx9cB1ccYRWddPSIn1tNLtAuAvLmb0lTHmncA7AdasWZOIsCQBZo+pmt30qGdonP3eAe74/UucDFMkI0RuPO1tbcfbP0ZxgZt/epMqNiS1xicDPH78LH/08tVOhyKSFcoK8yjMc2kPtKTMXItbLlcovduWZR24ITkl3IVAvAnrUPixNMoxkdeGohwT8T7g1cBua+1zccYCgLX269ba7dba7dXV1RfzFpIECzU9+vWRHgCur69JeWwimaipoY5Hdt7IK9YtY1ttuZJnSbm2jn7G/AGVb4skiDGG6rJCeoaUQEvyRRa3vP1jWM4vbv13m5d8t2FTTbT0LjMlNIE2xrgIddPujfNHT4Qf10Y5JnJr+kSUYyLeFH58jTHmwelfwJ9Fjgk/99M4YxUHLdT06MH2HqpKC7KyXEQkmdZXlXC8N9ouGpHkeORoL26X4ZoNy5wORSRrVJUW0qsVaEmB+Ra3Hjh8Bn/AcsNnH6SlzetQdMkRtYQ7vO95utfO8dz099oELAe+H2ccbeHHbcYYzzyduF8+69hY/E6U12rDXwNxvJ84rLbCg3eOJLq2wkMgaPn1kR5u2FIzVTYiIrFZX11C75MTDPr8lBflOx2O5IBIyZ+3f4x8t2HfoTOqgBBJkOqyQk6dHXU6DMkBC03umL3dMhsstAJ9/bQvS2gO8/XzfF0bfv0Z4IPxBGGtPQU8TWjP8m2zXzfGXAesArqB38Twftdba81cX8DHwod9OfxcRTyxirPe+ooL98i5XYbmxnqee6mfc6N+rrtEJfci8VpXWQLACa1CSwpML/kD8Acsu+7dn3WrFCJOUQm3pII/ECTfvXBB8/TtltlgoSZiN4QfDbAPuB/49DzHTgBea23HPK8vZDfwA+DTxphHrbVHAYwxNcBXwsfssdYGIz9gjLmd0Kiqx621f3qRf65kCGstjxztpaTATbknn+4BH8WFbkbGA2xZWcb/7O/GZeDVm5VAi8RrQ3UogT7eO8IVq3RfUZIrWj+LbFmhEHFSVWkhZ0cnmAwEyYshwRGJ1fSGYcWFbiYCQfLdBn8gei/ohVaqM0nUBNpa+1Dkn40xDwEPTn8ukay19xhjvgq8G9hvjPkF4AduAsqBFuBLs36silDX7+5kxCTpYXqZH8AfvqyOz77lKgD6Ryf4nd0PcMuXHmF8MvQBfuiFHl2AicRpzbJijEH7oCUlFupnISKLU11WiLVwdmSCGo2HkwSZPQ1nZDyA22X4o5ev5peHe+jsH8NlDAF7YTJdW+FJdbhJE/MYK2vtDQsftTjW2vcYYx4G3ktoFJYbOExoJNVXp68+S26Y/UEF+On+Lq7dXE1TQx0PtvcwGbRTd70iZYCQPfssRFKhKN9N7RKPEmhJiWj9LERk8apLCwDoGR5XAi0JM1f1UCBo+eXhHh7ZeSMw97W7J99Nc2N9SmNNprSr6bDW3m2t3WGtLbfWllhrr7bWfnmu5Nlae2d4H/P1cbx/5GduT2jgkhRzfVB9/uDUPoq9re0XlIxk2z4LkVTZUK1O3JIazY31FOXPvATJtgssESdVlxUCaB+0JFQs1UNNDXXsvvVy6io8GKCuwsPuWy/PqoWteVegjTH/GP7HL1lrz077PhbWWvuJxYUmsvAHVWWAIomzvqqEH7V5sdZijDrZS/I0NdRx6uwon/v5C0DoAqu5sT6rLrBEnFRdGlp1VgItiRRr9VBTQ11Wn8+jlXDfSajz9veAs9O+j3ZVFXndAkqgZdEW+qCqDFAkcdZVljDkm6RvZIKq0kKnw5EsV+4JjUt7ZOeN1OmcLZJQVWWhEu7e4QmHI5Fs0txYn/Xl2bGIlkB/nFAi3Dvre5GUaW6s54M/fI7xyfMV/NM/qPogiyTO+mmduJVAS7K1dZyjpqyQ2iXanymSaMUFeZQUuLUCLQnV1FDHZCDIHfc8B+Ru9dC8CbS19s5o34ukQlNDHQ8f7eWep17CEFpZnv5BjTxG2unPfl1EYreh6nwC/fJ1yxyORrLd0x39vGzNUm0XEEmS6rJCeoaVQEtiXVpbDsAX/7iBN1xZ63A0zoi5C7eIU4JBS1VpIU98+KY5L7SyfZ+FSKrUVXjIcxk1EpOk6x0ep+PsKH9yzRqnQxHJWlWlhfRqBVoS7EDnIABbw4l0LrroLtzGGJcxptoYU2WMSbtu3pI92k7107CmQqsUIkmW53axprKY4z1KoCW52jr6AXjZ2qUORyKSvbQCLclwsHOQ4gI36ypLnA7FMXEnvsaY1xpjWoEhoBs4DQwZY1qNMTcnOkDJbWdHJjjeO8LL1ugiSyQVNlRplJUkX1vHOfJchsvrljgdikjWqi4rpFcJtCTYwc5Btqwow+3K3YWtuBJoY8y/APcBrwE8hJqK2fA/vwb4iTHmC4kOUnLXM6fOAdCwpsLhSERyw7rKEk70jRAMqmekJM/THefYWltOUb7b6VBEslbP0Dj9o37W77yPHXv20dLmdTokyXDBoOVg1yDbanP75mfMCbQx5s+A9wHDhDpybyaUOHvC//wxQqvS7zXG/HnCI5Wc9PTJftwuwxWrcvuDKpIq66tLGJ8M0jXoczoUyVKTgSDPvTRAw2rdGBVJlpY2L784dBoIrXR5+8fYde9+JdGyKKfOjTI8PpnT+58hvhXo24FJ4PestXdaa49Za/3hr2PW2o8RWoUOAO9JRrCSe9pOnWPLijKKC9TvTiQV1kc6cWsftCRJ++khRicC2v8skkR7W9vxB2ZWEo35A+xtbXcoIskGB8MNxLYpgY7ZpcBD1ton5jsg/NpDwNbFBiYSCFqePTWg/c8iKTSVQPcpgZbkiDQQa1itc7tIsnT2j8X1vEgsDnYN4nYZLlle5nQojoongR4FzsRwXA+gT6cs2pEzQwyPT2r/s0gKLS8rwpPv1gq0JM3THeeoKi1g9TKP06GIZK3airk/X/M9LxKLA52DbKouzfn+FfEk0I8ALzdRZgmFX9sePlZkUabGnGgFWiRlfvxsJ/5AkG89cnzepjMtbV527NmnxjQSl8jvzb1Pexn2TfLfz3Q6HZJI1mpurMczK8lxGxidmNS5Wy7awc7BnN//DPEl0B8FVgGfM8bkz37RGJMHfDZ8zEcTE57ksqdPnmNZSQFrK4udDkUkJ7S0edl1734mwx2452o6EznG2z+mxjQSs+m/NwC+yaB+b0SSqKmhjt23Xk5dhQcDGCBg4dyoX+duuSh9w+N0D/rYulIJ9LydmYwxfzrH0/8OvB+4zRjzA+B4+Pl1wG1AHfA14ArgmUQGKrmn7VQ/DasriFL0ICIJtLe1nTF/YMZzkaYzTQ11MR8jMpt+b0RSr6mhburzdc0//YLTgzNnQuszKPE42KUGYhHRWhv/O6HO97MZQony++d4HuBd4a9vLzY4yU0tbV4+ff9hugZ8nBn00dLm1cldJAViaTqjxjRyMfR7I+KsM7OS5wh9BiVWkQ7cKuGOnkB/m7kTaJGkiZT5RVYqBn2T7Lp3P4CSaJEkq63wTJXYzn4+YsWSIroGLpwRrcY0Ek0sv1sikjz6DMpiHegcpK7CQ0VxgdOhOG7eBNpa+2cpjEMEUJmfiJOaG+tn3MACyHcbmhvrp77fVlt+QQLtyXfPOEZktubGev7+nueYCASnntPvjUjqzHV+L8p36TMoMTvYNcil2v8MxNdETCTpVOYn4pzZTWcK81zkuQw31NcAcOrsKL860sv2tRUU5oX++qir8LD71st1g0uiamqo44pV5VPNjPR7I5Jas8/vAK9cv0yfQVlQS5uXV+1+gKNnhvnt8T41niN6CbdIyqnESMRZ05vOHOoa5A++8GvueuAI//iGrXz6/sO4DHzxbS/jG78+znceO8mv/v4G3C41+pPoRsYnOdA5xFtfsZrdt17hdDgiOWn6+f0fWvbzncc62P7Jn9M3PEFthYfmxnol1DLD7K2VQ9paCcSRQM/TlXte1lo1EZO4NTfWs/Pe5/D5VeYn4rRLV5ZzzfplfOuR43zrkdDQhcaty1m5xMPmmlLGJ4O8dG6UtZUlDkcq6e5/D3Yz5g/wpoZVTociIsBltUswQO/wBHB+rBXkdmIkM2lr5dziWYH+d2JrKmbCxymBlrg1NdTRNzzOJ+47BITK/HRHVMQZLW1e2jr6Zzz30JEeWtq8bF5eBsCR08NKoGVBP2rrpK7Cw/a1S50ORUSAL+47esFFvRIjmU1bK+cWTwI9X1duF7AWeBlQArQAA4sPTXJV5ML8v975Sq7ZUOlwNCK5a29rO77J4IznfP4ge1vb+dn7fxeAI2eG+b2ty50ITzLEmSEfDx/p4d3Xb8Slcn+RtKDESGKhrZVzizmBXqgrtzGmhlCSvQl41eLCklx2om8EgPVVWtUScVK0C6wlnnxWlBdx5PRQiqOSTPPjZzoJWniTVrVE0oYSI4lFc2M9d/zgWSaD59dQtbUygV24rbVngLcBdcCdiXpfyT0nekfx5LupLit0OhSRnDbfhVTk+c3LSzlyZjiVIUkGaWnzsmPPPj553yHy3YbnvYNOhyQiYc2N9Xjy3TOeU2Iks73xylrKivIozHNpgsI0Ce3Cba09a4x5AngzcEci31tyx8m+EdZWFmOMSv1EnDTX3NDpF1ibakr53uOnCAatSnNlhtmdW/0BqwZFImkk8jm88ycH6B/1U1NWyIduvlSfT5nhyZPnODfq5/N/dKWaQE6TjDnQE8DKJLyv5IjjfSOsU1MiEcfNnhs6+87zJcvLGPMH5iwDlNwWrXOriKSHpoY6vvOX1wDwj2/YquRZLvCjNi+efDe/v3WF06GklYSuQBtjVgA7gJ5Evq/kjkDQcursqD6oImli+tzQ2TbXlAJw5MwQq5cVpzIsSXNqUCSSGTbVlOJ2GQ53DfF6jWiXacYnA9z3XCevvWwFJYUJTRkzXjxzoF8d5eVSYAvwXqAC+O4i45Ic1dk/hj9gWVepi3GRdLe55vwoqxu3qBO3nKcGRSKZoSjfzcbqEg53q0eBzPTLw2cY9E2qMmEO8dxOeJCF50AboA34h4sNSHLbyb5RAM2VFckAS4rzqSkr5IXTaiQmM6lzq0jm2LKinKdOnnM6DEkTLW1e9ra24+0fw2Wgb8jndEhpJ54E+lfMn0BPAF7gAeD71lr/YgOT3HRcI6xEMsrm5aUcPaNRVjLTLVfV8qn7DjLom2RiMkhthYfmxnqtZIikoS0ry/jxs50MjPlZ4sl3Ohxx0OwGkEELH245gMvl0vl7mnjmQF+fxDhEADjZO0JRvosajbASyQiba8r4/pOnsNaqc75MaT89RM/wBJ9suoy3v3Kt0+GISBSXrigHoL17iFesX+ZwNOKkaA0glUCfl4wu3CIX7UTfKGuXlWgkjkiG2Ly8lNEJdeKWmX72XBcuA6+9TA0hRdLdlpWhfhbaBy1qABmbuBNoE1JpjFlujFGdhyTUib4R1lWpgZhIprhkebiR2Bntg5YQay337e/imvWVVJWqmkgk3a0oL6KiOJ9DXdqOk+vma/SoBpAzxZRAG2OWGWM+Yox5AhgHzgCdwKgxZr8x5pPGGM1+lkUJBC0dfaOaAS2SQTZVh0ZZHVUjMQk7cmaYYz0j3HyFLgtEMoExhi0ryrQCLTQ31uPJd894Tg0gL7RgAm2MeRNwFLgTuJrQvmkT/nID24BdwAvGmD+f9bPGGNOQ4JglS3UP+pgIBNWBWySDLC0poKq0kBdOa+VCQu57rgtjoHGbRpuJZIotK8pp7x4iGFxo4I5ks6aGOj5+y7ap7+sqPOy+9XLtf54lahMxY8xthGY6u4D9wLeBJ4DThBLoGuAVwJ8ClwHfMMbkWWv/b7i8+z+B5wmNthKJ6kRvqAO3SrhFMssly0tVwi0zRp8UuF08erRPF10iGeLSlWWMTgToODvKOk1CyWlXrq4A4K63XsUtV+kcPpd5E2hjTDXwzfC377fWfnGOww4TGm/1WWPM+4HPAXcZY34N/DPQSCjxFlnQifAIK5Vwi2QWt4FnT/Wzfud91FZ4uGFLNb883ENn/5jGF+WI2aNPJgJBdt0b+utf/+9F0t+lK0OduA93DyqBznEv9oSuxzdUlTocSfqKVsL910Ap8KF5kucZrLV3AR8GioAngdcSKv3+VgLilBxwsm+UwjwXK8qLnA5FRGLU0ublseNnsYAFvP1jfOexDrz9Y1Pf77p3Py1tXocjlWSKNvpERNLf5poyXAY1EhOOqyJ0QdES6NcBfYRWlWP1OeAsUAwcAF5trdVVk8TkeO8IayuLNcJKJIPsbW3HH4i+Z06JVPbT6BORzOYpcLOuqkSNxITjvcNUlRZSVqRhS/OJlkBvAH5jrQ1EOWYGa+0k8CihhYjrrLWnFxmf5JCTfSNqICaSYWJNkJRIZTeNPhHJfJeuKNcKtHCid5QNKuOPKloCXQJczKdoCJi01p69uJAkFwWDlpN9o6yrVLmISCaJNUFSIpXdmhvrKcqbeUmh0ScimcVaS8fZUdbvvI8de/Zp602OerF3hPVKoKOKlkD3Ausu4j3XAj0XFY3krO5BH+OTGmElkmnmmhk5mxKp7NfUUMfbX7kWCI3o0OgTkczS0ublF4fOAKh/RQ4b8vnpHR5XI7kFRBtj9RRwszFmjbW2I5Y3M8asBa4BfpaI4CR3RDpw646XSGaJJEh7W9unum5HunB7w2Xbf3ntOiVSOaDck48xsP/ORkoLo07JFJE0s7e1nYlAcMZzkf4VOn/njhO9o4CuxxcS7W+4/wLeAHzLGHOztXYi2hsZYwoIddx2hX9WJCYtbV7u/PEBAD7w/WfY9bpLdbIWySBNDXVzfmZ9/gDXfvqXPN3R70BUkmoHOgdYV1mi5FkkA6kRoAC82DsMwIZqJdDRRCvh/i7wNHAD8JAx5mXzHWiMuZrQPOjrgWfCPyuyoMjs0P4xPwCnB8dVMiSSJYry3bzrug08eqyP7Z/8ufbVZbmDXYNsrS13OgwRuQhqBCgQmohjDKxZpp5E0cybQFtrLdAEdBAqy37CGPOcMeYbxphPhb++YYx5HngceAVwCrgl/LMiC9LsUJHsVh4eg9E7PKF9dVlsYMzPqbNjbF2pBFokE83Vz0L9K3LPid4Rapd4KFqgt0mui1pnZa19Kbzy/BXgNuCy8Nf0BNkAQeAHwHuttX1JilWykEqGRLLbXQ8cueA57avLPoe6QrNjtQItkpki5+M7f3yA/jE/y8sLtaUuBx3vHVH5dgwW3KhkrT0H/LEx5sPA64Grgerwy72Emo391Fp7LGlRStaqrfBMNRqa/byIZD7dJMsNBztDCfQ2JdAiGaupoY41lcXc+pVH+WTT5bxm63KnQ5IUstbyYu8ITVfppslCYu70Ya19EfhCEmORHPTH16zms60vzHhOJUMi2UM3yXLDgc5BqkoLqSkrcjoUEVmE+uVlABzuGlQCnWPOjkww5JtUB+4YRGsiJpJU1loeOdJHcb6LlUuKNDtUJAtpX11uONg1qNVnkSxQUpjH2spiDnUPOh2KpNjx3vBIWZVwL0izJiTlWtq87G1tn1qVevPL6vjcW65yOCoRSYbIzbB//O/nGfRNsnJJER987RbdJMsiE5NBjp4Z4vr66oUPFpG0d+mKcg53DTkdhqTYi+EEeoNWoBekFWhJqcjYquklnfft71JHXpEs1tRQx2f+8AoAvv5/tit5zjIvnB7CH7DqwC2SJbasLON43whjE4GFD5ascaJ3hDyXoU5brBakBFpSaq6xVT5/UGOrRLLcpppSAI72aFUj2xzsUgMxkWyyZUU51oZujknuON47wprKYvLcSg8Xov9CklLqyCuSm9YsK8HtMhw7M+J0KJJgBzsHKS5ws7ZSZX8i2eDSleFGYtoHnVOO946ofDtGSqAlpebrvKuOvCLZrSDPxdrKYo6eGXY6FEmwg52DbFlRhttlnA5FRBJg9dJiSgrcHNI+6JwRDFpO9I2wTjdCY6IEWlKqubH+gossdeQVyQ2bqks52qMEOpsEgzbcgXuJ06GISIK4XIb6FWUc6tIKdK7oHvTh8wfVgTtGSqAlpd5wZS2efBdF+S6NrRLJMRtrSjnZN4I/EHQ6FEmQU+dGGR6fZKv2P4tklS0ryzncPYS11ulQJMla2ry88UsPA/D5n7+gxr4x0BgrSaknTpxleDzAl97WwOuvqHU6HBFJoU3VpfgDlo6zo2ysLnU6HFmkljYvH//JAQD++ecv4Ml362aoSJa4dEUZd/+2g+5BHyuXaJtdtopMx4k0+O0dnmDXvfsBdD6PQivQklI/299FYZ6LG+prnA5FRFJsqhO39kFnvMhF19lRPwA9Q+Psune/Vi5EssSW8Fg6zYPObnNNxxnzBzQdZwFKoCVlgkHL/zzfzQ31NZQUqvhBJNdsCO+tOqZ90BlPF10i2a1+RagT90Htg85qmo5zcZRAS8o8efIcPUPj3HzFSqdDEREHlBXls6K8SCvQWUAXXSLZrbwon1VLPRzu1gp0NtN0nIujBFpSJlK+feMWlW+L5KpNNaUcUwKd8co9c1cR6aJLJHtsWVHOYa1AZzVNx7k4SqAlJULl211cd0k1pSrfFslZG6tLONYzos6uGailzcuOPftYt/M+BsYmMbPGPuuiSyS7XLqyjBd7R/DN2q4h2eONV9ZSUuCiKE/TceKhTEaSrqXNyyfvO0jv8ARPnDhLS5tXH0yRHLWpppTh8UlOD46zYkmR0+FIjGZ3agVwGyjz5NM/6qe2wkNzY73O7SJZZHDMTyBoufQj9+sznqWe7jjHoC/AXW+9iluu0v/bWKVdAm2MeRvwbuAKwA0cBv4N+Kq1NqbhocYYF/BK4GbgOmA9UAOcA54Cvm6tbUl89DLb7Iuuc6N+tccXyWEbp3XiVgKdOeZqGjYZhOKCPNr+8fcdikpEkqWlzcv3njgFgAW8/WO6fstC9+3vokDbK+OWViXcxpgvA/8JbAd+DfwcuAT4EnCPMcYd41ttAB4BPgxsBQ4A9wIngdcBPzLG/JsxswvQJNHUqVVEptsUnv+sTtyZRU3DRHLL3tZ2xidnrlvp+i27BIOW/9nfzas3V1NWlO90OBklbRJoY8ybgfcA3cAV1trXW2vfBGwGDgFvAm6P8e0ssI9QslxjrW201r7VWvsK4HpgBPiz8JckkS66RGS66rJCyory1Ik7w6hTq0hu0fVb9ms71U/3oI8/uGKF06FknLRJoIFd4ccPWmuPRJ601p4mVNINsDNcnh2VtfaYtfYma+391trArNceAvaEv317AuKWKHTRJSLTGWPYVFOqBDrDvOPV6y94Tk3DRLKXrt+y38/2d1HgdnHTpcudDiXjpEUCbYxZBVwNTAA/mP16OOn1AisI7W1erLbw46oEvJdE0dxYT4Fb7fFF5LyN1aUcVQl3RjkzOA7A8vJCdWoVyQHNjfV48i/cOTk8Psn6nfexY88+Wtq8DkQmi9XS5uVVex7gmw8fx2Vg36EzToeUcdKliVhD+PGAtXa+2pAngLrwsY8u8s/bHH7sWuT7yAKaGurYd+g0P36uCwPq4igibKop5Z6nXmJgzM8Sj/ZdpbuxiQB3P95B47bl/Ov/2e50OCKSApHrtL2t7XT2j1Fa6GZoPMDAmB9QU7FMNbu5r28yqP+PFyFdEuhIbdjJKMd0zDr2ohhjioH3hb/94WLeS2JT6slnaXG+OrWKCAA9Q6HVzKs+9r+6qZYBfvj0S/SP+vnLazc4HYqIpFBTQ93UuXnHnn0Mjc9c44o0FdP5O3NEa+6r/4+xS5cEujT8OBLlmEi9X9ki/6yvEErCDwJfX+R7SQw6+kZZU1nidBgikgZa2rx857HQvVKNRklvLW1ePtN6mM5+H/lug/fcKKxf5nRYIuKA+ZqHefvHWL/zPt0MzRBqDpcYabEHGohskrVJ/UOM+Qjw/wADwFusteNRjn2nMeZJY8yTPT09yQwr6508O8LaZcVOhyEiaUCjUTJDpMyvs98HgD9g+dCPnteeR5EcFa152PSboTpHpLfqssI5n1dzuPikSwI9FH4sjXJM5LWhKMfMyxjzAeDjhFayX2etPRDteGvt1621262126urqy/mjxTAHwjS2e9jbaUSaBHR3e9MEa3MT0Ryz3xNxabTOSI9tbR52bFnH+t33je1hWo6NfeNX7qUcJ8IP66NcszqWcfGzBjz18DngDHg9dba38T7HnJxvOfGCAQta7QCLSKE7nJ750iWdfc7vehGh4hMN7up2HwlozpHpJfZTcMA3AbKPfn0j/pVen+R0iWBjoyV2maM8czTifvls46NiTHmvcAXAB/wxvBILEmRk2dHAVirPdAiQmgVY/Zf5rr7nX50o0NEZpvdVEzniPQ3VzVRwEJxQZ6a+y5CWpRwW2tPAU8DBcBts183xlxHaGZzNxDz6rEx5l3Al4BxoMla+4uEBCwx6+gL9YVTCbeIQOgCbPetl7O0ODS+qqasUPOE09Df/t7mC57TjQ4RiZirpLso36VzRJpRNVFypEUCHbY7/PhpY8ymyJPGmBpCnbMB9lhrg9Neu90Yc9gY8+3Zb2aMeUf458aBW621rckLXeZzsm+UonwXNfM0LRCR3NPUUMd//OU1AHz0DduUPKehksJQgVplSQEGqKvw6EaHiEyJ3Aytm7biPH2FWtLDfBUBqhRYnHQp4cZae48x5qvAu4H9xphfAH7gJqAcaCG0mjxdFVBPaGV6ijHmKuBfCXX3Pg68xRjzljn+2F5r7R0J/ReRGU6eHWXNsmKMMQsfLCI5Y2MolqnRAAAgAElEQVR1qC/ksZ7hBY4UJ9z9eAcrlxTx8AdvxO3S+VtELhRJmK21vO6uX/NMRz/WWl3zpZHmxno+8P1nCE7btK5qosVLmwQawFr7HmPMw8B7gesAN3AY+Bbw1emrzwuo4PxorC3hr7mcBJRAJ1FH3yhrlmn/s4jM5ClwU1fh4egZJdDp5tTZUR4+2sv7b9qs5FlEFmSM4S92rOfvf/gcjx7rY8emKqdDkrDL6pYQtFBelMeQb1JNwxIkrRJoAGvt3cDdMR57J3DnHM8/yPkEWhxireXk2RGu3awTqYhcaFNNqRLoNPRfT5zCAG/ZvnrBY0VEAN54VS0f/+kB/uLfn2BiMqhELU187/EO8t2GfXdcT1WptlMmStol0JI9zgyN4/MHWacGYiIyh001pfz2eB/BoMWllU7HtbR5+UzrYTr7fRTmuXj8+Fld/IpITO5/vhufP8hkuFbY2z9G8w+e5WM/OaBxSQ4Znwzww6df4jVblyt5TrB0aiImWeZkX2iE1RqNsBKROWysLsXnD845CkVSKzIrtLPfB8D4ZJBd9+6npc3rcGQikgn2trZPJc8R/qDl3KgfSyih1jkltVoPnObcqJ8/fsUap0PJOkqgJWlORkZYLdMKtIhcaFNNqJHYUTUSc9xcs0LH/AH2trY7FJGIZJJYxiLpnJIaLW1eduzZx/u+24bbZegdHHc6pKyjBFqSpuPsKG6XoW6pWuWLyIUiCfQx7YN2nGaFishixDoWSeeU5IpUE0UquwJBy4dantfKf4IpgZakOdk3Sm1FEflu/ZqJyIWWlRSwtDhfo6zSgGaFishiNDfW48l3L3iczinJpWqi1FATMUmak2dHWasRViIShTpxp4fmxnqa73kWf+D8HkbNChWRWEWag+1tbaezf4wlnnxGJiZ1TkmBljbv1H93O88xWvlPLCXQkjQdfSO87vKVTochImlsU00p9z/f7XQYOa+poY4fPnWKh4/2AahjrojEramhbsY5I5LYefvHyHcbdt96uc4pCRYp2Z696jybVv4TSwm0JMWgz8+5Ub8aiIlIVBurSzk36ufsyATLSgqcDien+SaDXL12Kfe8+1VOhyIiWSCSUN/1iyP8ywMvcH19tdMhZZ25SrZn08p/4mlzqiRFR3iE1VrNgBaRKDZGOnGrjNtRwaDlYOcgW2vLnQ5FRLLMjk2VWAu/OdbndChZJ1pptgHqKjxa+U8CrUBLUkzNgNYeaBGJYlP1+QT6FeuXORxN7uo4O8rIRIBtSqBFJMGuXF1BSYGbR471amtfgtVWeKY6bk9XV+HhkZ03OhBRbtAKtCTFybOhGdBrtAItIlHUVXgoynepE7fDDnYNArB15RKHIxGRbJPvdvHKDZU8clQr0InW3FhPwaxpNyrZTj4l0JIUHX2jVJUWUFqoIgcRmZ/LZdhQpU7cTjvQOUCey7B5eanToYhIFtqxqYrjvSO8dG7U6VCySlNDHTdfvgJQyXYqKbuRhGtp83Jvm5eJySA79uxTJ1cRiWpTTSlPnTzndBg57WDnIJtqSimKYY6riEi8rt1cBcCjR/t4y8tVnZhILpehpqyQxz/8e06HkjO0Ai0JFWmnPzEZBMDbP8aue/fT0uZ1ODIRSVcbq0vx9o8xNhG9k6gkz4HOQbau1P5nEUmOzTWlVJcV8vDRXqdDyTqHu4bYovN3SimBloSaq53+mD/A3tZ2hyISkXS3KdyJW/ugndEzNM6ZoXF14BaRpDHGsGNjJY8e68Va63Q4WcMfCHL0zDCXrihzOpScogRaEmq+dvrR2uyLSG7rCDcdfP0XH2bHnn2qWEmxQ5EGYkqgRSSJdmyqond4gvbTQ06HkjWO944wEQhyqVagU0p7oCWhVi4ponPAd8HztRUeB6IRkXTX0ublrgeOTH3v7R+j+QfP8rGfHKB/1E9thUd9FJLsQGcogd6mDtwikkTD45MAvPZffk2dzu0JEbkBumWlVqBTSSvQklCRJhHTqZ2+iMxnb2s7Pn9wxnP+oOXcqB+L+iikwsGuQeoqPCwpznc6FBHJUi1tXj5z//ntfDq3J8ahriHy3aFpFpI6SqAlbi1tXnbs2cf6nffNKLe01tLW0U/tkiLqKorUTl9EFhTL9g71UUiuA50DbFP5togkkXrkJMfh7kE2VpdSkKeULpVUwi1xiXTZjpwEI3cQAZaWFHDkzDCfu+1K3nz1KifDFJEMUVvhwRtDEq0+CskxOjHJ8d4R3nhlrdOhiEgWU4+c5DjcNcSrNlY6HUbO0e0Kicve1sPz3kH85sPHqS4r5A26EBORGDU31uOJYfaw+igkx6GuIaxFI6xEJKnmO4fr3H7xzo1M0D3o0/5nByiBlgVNL9n29l/YIAxCK9G/eqEHnz/Az/Z3pThCEclUTQ117L71cuoqPBigwpNPvttccNzAmP+CbSOyeAfDDWi21amBmIgkz1w3S9UjZ3EOd4e6mW9ZoRugqaYSbolqdsn2QoZ8k1Ml3dr3LCKxaGqom3G+aGnzsre1nc7+Mco9eQyMTU51b52+bUTnmMVpafOy+2eHAHjL1x6luXGL/puKSFJEzi17W9untu189A1bdc5ZBHXgdo5WoCWquZo+LERNIURkMZoa6nhk540c3/MHlBZe2Bla55gLzdfcMdrxu+7dz+hEpJ+FTx1xRSSpIuf2u//qGgBqygsdjiizHe4epLKkgOpS/XdMNSXQElW05g4XFlnG9nMiIrFS45mFRZJhb/9YzKO/1BFXRJzysrVLKcxz8fCRPqdDyWiHu4e4dGU5xkS7IpdkUAItUZUUzl3lX1fh4fieP6BOTSFEJInUeGZhF5MM68aEiDilKN/NK9Yv45GjvU6HkrECQUt79xBbVqh82wlKoGVeT3ecY3h8Erdr5p2t6U0f1BRCRJJpvi7dgz41FYu4mGR4aUnBnM/rxoSIpMKrNlbRfnqIM0NzN6eV8+baonOib4TxySBbNEHBEWoiJjNMb97jdhkqPHnsfN0WvrjvGJ39Y9RWeGhurJ9q+jC9KcRcr4uILMbsc0ykqdiQT03FIuabpT1fMjww6sc/GcAAdtrzuvkpIqly7aYqPg385lgft1yVm+fuWMxu5hv5O+8t21cBaAXaIcZau/BROW779u32ySefdDqMpJur43aB28Vn/vCKnL0wFZH0smPPvjmTxboKD4/svNGBiJw337SEOxov4fYbNs84bnoH3JsvW8GzLw3o5qeIpFwgaLn6kz/nNZcuZ+9tVzodTtqa7++8yA3Q2iVF/P1rNUEhUYwxT1lrty90nFagZcpc++gmAkH2trbrgykiaUF7dy/U1FDH0Lifj7QcAGDlkiKGfX7ufqyDu3/bQVe/jyWefEYmJvEHzt80/2V7D7tvvVzndxFJObfL8KqNlTxytBdrrRphzWO+v9siZ/LOAV/OV2E5QXugZYouTEUk3amp2NxWlIf+/e951+/wm1038Zbtq+kc8NHZ78MC/WP+GckzqOu2iDhrx6YqOgd8HO8dcTqUtBXL3206l6eeVqDl/2/vzuPkqOv8j7/ec+QikAHCYSYEwmGQexQQCWfAhTUCQUV3lV1gdfen4LVqNMhD1wsZBHZ1BfTHzwNdYVdACLoRucIlhxIzIEcSroSEIQeBTMh9zHx+f1T10OnpnumZzEx3T7+fj0c9iq6qb9W3J1+q61Pfq1Nv+9GZmQ226adN6tJceUR9TdX33Z27eBV1NeKQxjEA/OGZ5UWl8wtSMyuV9ZuS+/iUqx6gsWEkJx+4G/fNf83dSrJ8Zsp+zLj16R6P8718cLkG2jpNP20S9bWFR9w2Myu1aU2NXPaBQ2lsGNk5F/2Zh4+r+oeslsWrOHjcToxIRywv9mHKL0jNrBRmtrTy73e/VWva2raBXz22uFfz2VeD2pokVBs7ejgCags0dfe9fHA5gLZOZx0xjt1GD6euRohkUB73jzOzcjOtqZGHZ0zhpcvex6Q9dmT+sjWlzlJJbW3v4Mklq2masHPntmIepvyC1MxKJRl3p6PbY9w0GWY+0creu47i8UtOYWHzVK768OGePrYMOIC2Tk+1rubV1Rv5+hkHsbB5Kg/PmOLg2czKliT+/ui9+Osrq3m6dXWps1MyC5avYcOWdpomNHRuyzd/dn2N2HlUvV+QmlnJFdtKppqbJi9bvZFHXnydaUc0dg6yltsKy/fy0nAfaOv0339ewoj6Gs/HZ2YV4+ym8Vx2x3z+5/HFfKfx0FJnpyTmLm4D4J1ZNdC582e7P6GZlZNC4+7kO65a3f5EKxFdR9ee1tToe3mJOYA2ANZt2spvn2jl/YeNY8zI+lJnx8ysKGNG1XNo407c8NhibnhscVUGii2LVzF29HDG77ztg6YfssysXOUbEDJXtQ8QeVtLK00TGpg4dodSZ8VyOICuMjNbWrepkciMeJh5C9hYxW/6zKzyzGxp5a+tb3bOiZkZeAaqZ07MlsVtNE1o8DyqZlYx8rWSyR6FO4C/P2qvqrmPZ5vZ0sp3fz+PFWs2MWZkPTNbWqvy71DOHEBXkZktrdu87cuMeJjtugdfZOLYHfw/qplVhCvuXMDmrdsORJMZeKYa7mOr1m1m4cp1fPjIvUqdFTOzXinUSmZrewfv/u69vLZ2cwlyVVq5z+qrN2ypupfClcCDiFWRZMTDwk1lADZs6aj6EQ/NrHIUGmCmWgaeaVmyCmCbAcTMzCpZXW0Nf3Pwnsyev4KNPTy3DjX5ntU9Gnn5cQBdRTzioZkNNYUGmKkRTJwxi8nNs4f0PKIti9uorRGHjR9T6qyYmfWbqYe+jfWb27l/wWulzsqgqvaXwpXCAXQVKXYkw2oe8dDMKku+6ZoA2gOCt/pED7UgemZLK5ObZ/PD2S9QI7jrmeWlzpKZWb85Zt9d2GWHYfz+qaWlzsqgahiVfyBfP5uXFwfQVWT6aZMYXtf9P7knYzezSpI7J2ZtnnG0hlrzt0wfuczgj1vaY0i+JDCz6lVXW8NpB+/BvfOWD/lm3JkXohNnzGLV+i3k/oz52bz8OICuItOaGjnugLEAnZOvn3vMBE/GbmYVbVpTIw/PmMLC5ql0RP5jWts2DJkm3e4jZ2bVYMzIetZtbufAr/1hSNy788l+IZr5+aoV7Dyq3s/mZcyjcFeZxa+v59j9duXGfz6m1FkxM+t34xpGdtbM5spu0g2VO6Kp+8iZ2VA3s6WV6x9Z1Pm50L07d3rW6adNqqh7e74XolsDRg2ro+Xrf1OiXFlPXANdRRatXMfzK9Zy6jv2KHVWzMwGRKE+0dkqvba2UF8495Ezs6HiijsXsHFL/ikKM3JrbytxzAu/EK1MDqCryD3zkkFm3nuQA2gzG5py+0QXUskPJ5+Zsl+Xbe4jZ2ZDSTGB5VDozuIXopXJTbiryN3PLufAPXdkr11GlTorZmYDZlpTY2cTvsnNs/M26a60h5PsZoojhyU17LuNHs7KtZsqstmimVl3CnXHyb53D4Xa208cP5Fv/u7Zbbb5hWj5cw10lVi1bjNzXl7l5ttmVlXyNemutIeT3GaK6ze3U1cjLpn6DhY2T+XhGVMcPJvZkJLv3i3BF9/79s7Pu44eljdtJb0gbVu/BYA9dhruQcMqiGugq8R9C1bQ3hGc6ubbZlZFMg8hV9y5oLM241tnHVxRDyd5B5npCK64c0FFfQ8zs2Jl37tfbdtAw6h6Vq3fwhvrNwOwdPUGNm5pR0D25AuV9IK0vSO4ac4STnj7bvzyn44udXasFxxAV4l75i1n9x2Hc1jjmFJnxcxsUGWadN+3YAUX/Pxx3jam/GsnsptsF5iZq6KaKZqZ9VZ2d5yI4J9/OYfLfj+P6x58iRVrNiHgjMP25P7nVvLmxq3sOWYEM04/sGJeLD7w3AqWrt7Iv51xUKmzYr3kJtxD3MyWVo697F5+/9Qy1m7aym+ffLXUWTIzK4mj99mF+lrxxxdWljor3co3L2g+ldRM0cxse0ji+APG0h6wYs0mIKl5vnvea5x37D4AfOesQyomeAa48U9LGDt6OKe4e2XFcQ30EJNda5FMQL+VLe3JI9j6ze0VP/+pmVlf7TC8jqa9dubhMg+g8zXZzlVJzRTNzPrDdQ8u7LJtw5Z2fvOXV6irEXMXryp5V8XcealPPnA37pv/Wpd5qpet3sh9C1bwLyfsS32t6zMrjQPoISRTa5F58GrbsKXLMZnh/R1Am1k1mrz/WL5/73O0rd9Mw6j8A9CUWndNswUeddvMqlKhe+PS1Rs5pHEMLYvbBjlH28p9Dm9t28CvHlvcub+1bQPTb36Sb/7uGValg4ftukN5/g5Z9/zKYwgpptYC3G/OzKrXcQfsSgQ8+uLrpc5KQYWaZjc2jPSo22ZWtbqbM7lpQgNPvtLG1vaOQc7VW4p5Dt/SEZ3BM8BVdz3HzJbWgc6a9TMH0ENIsYGx+82ZWbU6bHwDo4fXlXU/6OmnTaKuRttsc5NtM6t23U1L+M4JO7N+czvPLV9botz1rYIq0zLUKosD6CGkmMDYD2FmVs3qa2s4Zt9dyrof9FlHjKNhVD3D62o8L6iZWWpaUyOXfeBQGhtGdrk3Nk1oAKBlyaqS5a+vFVRuGVp53Ad6CPn0lP24+Nant9lWXyNGj6ijbf0W95szMwOO3W8s98xbwSur1jN+51Glzk4X85auYeXazVx69iF87N17lzo7ZmZlI3tqq2wTdhnFrjsMY+7LbSW7b04/bRLTb3myc/DeYrllaOVxAD2ErNuU9LvYbcfhrFyzyQGzmVkexx0wFoBHXnidDx9VfgH0HU8vpUZw2sF7ljorZmYVQRJNExq61EDnjoo9kM/F05oa+cUji3jylTYi6DIKd+7sOOCWoZXKAfQQsbW9g58/vIij99mFmz75nlJnx8ysbD3TupoawZd/81d+cO/zZfWiMSKY9dRS3j1xV8aOHl7q7JiZVYymCTtzz7wVnbMs5BsVeyCnc928tYMXVqzlnHftxeUfOizvMYMZ0NvAcQA9RNz17HJa2zbwtfcfVOqsmJmVrZktrXz1tqfpSCsACj1Q9fdDTrHnW7B8DS+9to4LJk/s87XMzKrRW/2g2zh50u55R8UeyOlc/7zwDdZs2trtXNSFmqBbZXEAXeEyD2WtbRuorRHrN20tdZbMzMpWMQ9U/V1r0Zvz/f6vS5HgdDffNjPrlcPHN1AjaHl5FSdP2r3g4FytbRuYOGNWUS9He/My9Z55yxleV8Nx+4/tl+9j5cujcFewzENZa3qDaO8ILpn5tOeTMzMroNADVfb27oLsvijmfDNbWpncPJv/nP0C9TU1ZT1KuJlZOdpheB0H7rkTLUvaABg1rLbgscFbLzMLPTdnP2f3dHxEcPezyzn+gLGM7Oa6NjS4BrqCDXbTFDOzSjeuYWTnS8dso4bVMrl5Nq+mD0r59HWqkZ6C9twa6s3tHQPaT8/MbKhqGFXHH59fyT4zZgFQIzq77OSTrwVSpsa5RqI9otvjM+YvW0Nr2wY+M2X//v1CVpZcA13BiqlJMTOzt0w/bRIj67vWDqzb3N5Zy1BIX6caKZSuRjBxxiy+eNOT/VrjbWZWjWa2tPL4olXb3MdrBDuPqkfdpMt9mZn5LcgNnjMyTcAnN8/urI2+59nlSHDKOwr3f7aho+wCaEkflfSQpNWS1kqaI+kiSX3Kq6TTJd0l6Q1J6yU9LekSSRU/vGmhhzLPJ2dmlt+0pkYu+8ChNDaMREBjw0gaRtb3mG5Yrfo81ci5x0zIu7096PYhzS9DzcyKd8WdC7rMwby1A0YNq2Nh81Qae3huzteys5BMk+7pNz9J07fu4qq7n6OuRu5+UyXKKoCWdA1wA3Ak8BBwN/B24GrgFkm96lQg6cvAHcAUYC4wC9gd+A5wv6TymwC0F/LVpHg+OTOz7k1rauThGVNY2DyVh2dMYfWGLQWPFVBfKwRc/of5XWodivHMq28yrFa8bcwIBNSqu7qQt/hlqJlZ8XpqmZnvubmu5q2Xo315abmlI1i1PvkN2dIe3faptqGjbAJoSR8ELgSWAYdFxPsj4mzgAGAecDbw6V6c70igGVgPTI6IUyPiHGBf4EHgGODS/v0WgytfTcplHzjUfebMzHqhUKDa2DCShc1T+fypb2dTe7B09cYutQ49BdTPL1/DrKeW8onj9+XRi09hYfNUOgrUOGfzy1Azs97pqWVm7nPzqGG1bO0ILp01j4lpn+l8aqVum4Bnc/eb6lBOg4hdnK6/EhHPZzZGxHJJnwLuB2ZI+mFEdBRxvhkklQeXR8Sfss63VtIFwPPAhZK+GRFt/fYtBpnnkzMz2z7TT5u0zSBesG0Ae+OfFndJk13rkG9aquwpBsW2D3aFBjKrleiI6Jd5p83Mqk1P93LY9rn5v//8Mhff+jSvrd1U8Jwj62s7K6cmN8/Oe+/O5e43Q19ZBNCSxgPvAjYDN+fuj4gHJLUCjSQ1x4/0cL5hwN+mH2/Ic76XJD0KTAbeB9y4XV/AzMwqVuZhqtBcn8U8DG3Y0s4Xb3qSf/31E4wZWc+6zVs7++IFcOmseYweXse0psaCD3luQWRm1nc93ctzXT37xbzbC73MzHfvzsfdb4a+sgiggaZ0/UxEFHpSeZwkgG6ihwAamASMAt6IiPz/dyTnm5yezwG0mVkV6641T6Ea41yZwcDa8vSpzp76pLcPeWZmVpzetMws9HK0I4KFzVPznhveunfnviwFd7+pFuUSQE9M1y93c0ymDd3Ebo7JPV/Xdnd9O5+ZmVWpYmsdepL9sObuN2ZmpVXo5Wh3Nci59+7seaP9MrR6lEsAPTpdr+vmmLXpescSnM/MzKpUMbUOxXCzPjOz8lFMn+me+GVodSqXADozuF3vnkYG8HyS/gX4F4AJE/LP4WlmZtWhu1qHGqngXM4ZbtZnZlZe3J3G+qpcAug16Xp0N8dk9q3p5ph+O19EXAdcB3DkkUf2V2BvZmZDQHZAPbOltUstRn2NGD2ijrb1W/xQZmZWplyDbH1RLgH0onS9dzfH7JVzbDHn667quDfnMzMzy8u1GGZmZtWjXALolnR9sKSRBUbiPirn2O7MBzYAu0jar8BI3Ef34nxmZmYFuRbDzMysOtSUOgMAEbEEmAsMA87J3S/pRGA8sAx4tIjzbQbuSD9+LM/59gXeQzLv9Kw+Z9zMzMzMzMyqRlkE0KnL0vXlkvbPbJS0O3Bt+rE5Ijqy9n1a0nxJv8xzvmaSQcS+IunorDSjgZ+RfPdrI6Ktn7+HmZmZmZmZDUFlE0BHxC3Aj4A9gack/U7SrcDzwEHATODqnGRjgUnk6escEY8DM4BRwCOS7pJ0E/AicCLwJ+CSAfo6ZmZmZmZmNsSUSx9oACLiQkl/BC4iCXJrSfoz/wz4UXbtc5Hn+56kvwJfJOlDPQJ4CfhP4MqI2NSf+TczMzMzM7OhS9HD3JWWTGM1Z86cUmfDzMzMzMzMBoCkv0TEkT0dVzZNuM3MzMzMzMzKmQNoMzMzMzMzsyI4gDYzMzMzMzMrggNoMzMzMzMzsyI4gDYzMzMzMzMrggNoMzMzMzMzsyI4gDYzMzMzMzMrggNoMzMzMzMzsyI4gDYzMzMzMzMrggNoMzMzMzMzsyIoIkqdh7In6TXg5QG+zFhg5QBfwyzD5c0Gm8ucDTaXORtMLm822Fzm+t/eEbFbTwc5gC4TkuZExJGlzodVB5c3G2wuczbYXOZsMLm82WBzmSsdN+E2MzMzMzMzK4IDaDMzMzMzM7MiOIAuH9eVOgNWVVzebLC5zNlgc5mzweTyZoPNZa5E3AfazMzMzMzMrAiugTYzMzMzMzMrggPoEpL0UUkPSVotaa2kOZIukuR/F8tL0iRJn5P0K0nzJXVICkkfKiJtn8qbpNMl3SXpDUnrJT0t6RJJw/vvm1m5kVQv6RRJV0l6TNJSSZsltUq6RdJJPaR3ebNek/QZSTdJmifpdUlbJL0m6R5J50pSgXQ1afmak5a31Wn5+/sirunfYusk6bvp72pI+lI3x/keZ70m6fqs8pVvmV8gne9xZcRNuEtE0jXAhcBG4F5gC3AKsCNwG3BORLSXLodWjiR9H/hcnl3nRMQt3aTrU3mT9GXgcqAduB9YBZwI7AY8BpwSEeu34ytZmZJ0KnB3+nEZ8BdgHXAQcEi6/dsR8fU8aV3erE8kvQLsDjwNtJKUub2BdwMCbgc+EBEdWWlqgVuBM4E3ScrccJIyNxz4YUR8tsD1/FtsnSQdBTxKUsEkYHpEXJnnON/jrE8kXQ+cBzwMvJDnkKURcXFOGt/jyk1EeBnkBfggEMBS4ICs7XsAz6b7PlfqfHopvwX4BPA94MPAfiQ/wAF8qJs0fSpvwJFAB8kD7Luzto8GHkjT/Uep/yZeBqysTQFuAY7Ps+8jwNa0DJycs8/lzUufF+A4YIc82w8meZETwAU5+76Ybn8G2CNr+wFZac7Kc07/FnvJLg/D0zLUShJYBPCl/io3vsd5Sf+9r0//rc/vRRrf48psKXkGqnEB5qSF9h/z7Dsxq7DXlDqvXsp7obgAuk/ljSR4CuDredLtS/IGfRPQUOq/g5fBX4CfpOXjpznbXd68DMgCfC0tIzdmbasFlqfbT8iT5rx035/z7PNvsZfsf/PL03/zM7KCnHwBtO9xXvq89DaA9j2uPBe3fR9kksYD7wI2Azfn7o+IB0jefu4JHDO4ubOhpq/lTdIw4G/TjzfkSfcSSTO3YcD7+j3jVgla0vX4zAaXNxtgW9P1xqxt7yFp8v1KRDyYJ83NJE0Wj5LUmNno32LLJundJLV8N0bE77o5zvc4G2y+x5UhB9CDryldPxMRGwoc83jOsWZ91dfyNgkYBbwRES/2Ip1VjwPS9dKsbS5vNiAkTQQ+mX7MDnAy5eFx8oikP+kz6ccj8qTzb3GVkzQC+AXwBvnHGMnme5z1l5Ml/buk6yR9WyI9IT0AAA7/SURBVNJpBQb18j2uDNWVOgNVaGK6frmbYxbnHGvWV30tbxNz9hWbzqqApD2B89OPv8na5fJm/ULSBSRNDOtJWjkcS/LS/7KIuC3r0GLL3BHkL3P+LbZLSQLcv4uIlT0c63uc9Zd/zLPtWUl/FxFPZW3zPa4MOYAefKPT9bpujlmbrncc4LzY0NfX8uZyanlJqgN+BYwB7s1p7ujyZv1lMknfvoytJH2g/z3nOJc56zNJxwKfB2ZGxK+LSOLyZtvrCZJZLe4lCW53At5J8iLncOAeSe+MiNb0eJe5MuQm3IMvM4el5w+zwdDX8uZyaoX8mGQKjCXAuTn7XN6sX0TEJyJCJM1eDwa+D3wDeEzSuKxDXeasTySNBH5OMi3QhcUmS9cub9YnEfH9iPhhRDwbEesiYmlEzAKOJpnKbHcgexorl7ky5AB68K1J16O7OSazb003x5gVo6/lzeXUupD0A+DjJNNmnBIRy3IOcXmzfhURG9IHzekkD5WHA1dnHeIyZ331XeDtwBciYmlPB6dc3mxARMRm4LL0Y/ZAci5zZchNuAffonS9dzfH7JVzrFlfLUrXvS1vmf+e0Mt0NkRJugr4LPAaSfD8fJ7DFqVrlzcbCD8HrgTOkFQfEVvY/jLn3+LqdTbJvMznSTovZ9+B6fpTkt4PvBARn8D3OBtY89N1Y9a2Rena97gy4gB68GWmfjlY0sgCI+MdlXOsWV/1tbzNBzYAu0jar8CooUfnSWdDkKTvAV8AXgfeGxHPFjjU5c0GUhtJX+g6YBeSuVHnpvuOypdA0ijgkPRjdtnxb7FB0hLzxG7275suDeln3+NsIO2artdmbfM9rgy5Cfcgi4glJP8zDAPOyd0v6USSEUeXkcwJaNZnfS1vaVOiO9KPH8uTbl+SuQk3A7P6PeNWNiQ1A9OBVSTB85OFjnV5swF2Aknw3AZkRkt+FFgBjJd0Qp4055CM5P141qA8/i02ImKfiFC+hWRaK4Dp6bYj0jS+x9lA+nC6zp6yyve4MuQAujQyfRwul7R/ZqOk3YFr04/NEdEx6Dmzoaiv5a2ZZPCJr0g6OivdaOBnJPePayOibcBybiUl6dvAV0gClvdGRDFvqV3erE8kHS/pY5KG59k3Gfhp+vGnEdEOkK6vSLf/KC1nmTQHkJQrSEa4zeXfYusL3+OsTyQdIen9kmpzttdJ+gJJNymA/8js8z2uPCnCg7OVgqRrgU8BG4F7gC0kI9vuBMwEPpR5QDDLkPRO3rrpARxEMv3A88AbmY0RcUxOuj6VN0lfBi4H2oHZJIHUiSSjRP4JmBIR6/vp61kZkXQmcHv6cQ7wTIFD50dEc/YGlzfrC0nnk/RzbiOpOVlGcn/bj+ReB0nt3DnZzRHTh9HbgDNIRlS+l6RG5lRgBPDDiMg8mOZe07/F1oWk60mmUZseEVfm2e97nPWapGkk96o3gOeAV0jucYcC40j65F8cEd/LSed7XJlxAF1Ckj4KXETyP04tSR+ZnwE/8tsgy0fSScB9PR2XNkHLTdun8ibpdOCLwJEkN+qXgBuBKyNiU++/hVWCrGCmJw9ExEl50ru8Wa9ImghcABwP7A+MJZmKZRnJS5xfRcTMAmlrSKYiuoBkAKh24K8kNXo39nBd/xbbNnoKoNNjfI+zXknvcZ8j6e++N0mf5yAJpB8CromIvxRI63tcGXEAbWZmZmZmZlYE94E2MzMzMzMzK4IDaDMzMzMzM7MiOIA2MzMzMzMzK4IDaDMzMzMzM7MiOIA2MzMzMzMzK4IDaDMzMzMzM7MiOIA2MzMzMzMzK4IDaDMzqxiSFkmKnGWjpIWSfinpiH681vXp+c/vr3P2B0nnp/m6vtR5GQiS9km/36IBOv9H0vN/ciDO38O1x0laL+mWwb62mZn1DwfQZmZWie4EfpEudwEjgH8AHpf0d6XMmHWvlC8mJI0ErgBeBH462NePiFeBa4EPSjppsK9vZmbbzwG0mZlVouaIOD9dzgT2BW4A6oDrJO1S2uxZmfpXYC/guxGxpUR5aAY2AVeW6PpmZrYdHECbmVnFi4gNwKeAdcCOwGmlzZGVG0l1wEXAWuDXpcpHRKwEfge8S9LkUuXDzMz6xgG0mZkNCRGxBngu/bh3ZntWv+l98qWTdH+6/6RiriOpVtInJT0iabWkzZKWS5or6SpJu+VJs4OkL0t6XNKbkjZIekbSNySN7vWX7T5/e0n6gaQF6XXelPRw2ndaeY7v/P6S3iXpt5JeT9M+Kenj3Vxrd0nXSnol7Yv+gqRLJY3M/btm+jYD56XJf57Tl/38POeXpAslPZH2HV4l6XZJh/ThT3M2MA64JSLW5blWZ9NySftLujH9d90kab6kr0jq8twkaYSkGem//9r0+KWSHpX0HUkj8uTlF+n6wj58DzMzK6G6UmfAzMysH+2UrjcN4DV+ShIEbgD+CKwExgL7AV8AbgZeyxwsaTxJn+2D0u2PAhuBo4B/A86WdFJErNrejEk6GbgNGAO8APwBGA0cA/wcmAL8Y4Hkp6f5X0DSr3wCcCzwE0kNEXFVzrXGAQ8D+wArSGpVhwOfBU7Kc/61JIHjcSR/q4fTPGa8kCfN9cBHgAeB50n+ZmcCJ0lqioiXCnyXfKal63t6OO4I4Ack/673AXukeW4GxgOfyRyYBtSzSP6uq4EH0vUewCTgEuBqYFnONe4D2oH3S6qNiPZefA8zMyshB9BmZjYkpCNwT0w/PjFA19ibJHheAhwVEcvz5OHVrM8CbiIJnq8GvhIR69N9I4HrgHOB/wDO3868vQ34DUnAfD7wy4iIdN9ewG+Bf5A0OyKuz3OKrwAfj4ifZZ3zXOC/gK9L+lEm76lrSYLnO4BzMrW6kvYE7k2/c6e06fL56ejh+wE/KZCPjL2B44GDI+LF9NzDgVuB9wEXA//c7R9lWyem60d7OO5zwDeBb0VER3rdE0iC3gslfS8ilqTHHkcSPM8FTsiu2U7/7Y8F3sy9QESsk/QUSbD+LuDPvfgeZmZWQm7CbWZmFU3SzpLOJAmsakiC5wcG6HK7p+u5ucEzQEQ8ERErsjadDrwHeAz4XHYAmvbb/iRJ7e3HJO28nXn7PLAzcFVE/CITPKfXWsJbweZn8iUGfpMdPKfpfgXMI6nZPzKzPX2RcCawFbgwO3CMiGXAl7bzu2R8NhM8p+feRBLcApxS7EnSZvWNwKYiaq0fB76ZCZ7T6z5I0oqgBjg569g90vVDuc3CI/FwzkuHbM+m66Yiv4aZmZUBB9BmZlaJ7sv0nQXeAG4nqX2eC0zLDn762XxgDTBV0lfTQLI770vXv8mXpzTomkPSIuyo7cxb5lo3F9j/F5Jm1EcU6Jf7vwXSzU/X47K2nQAIeDQiFuUmiIg7gO1tkr6VpAl6MfnpSebFxxtFHPv77JcPPVx3LklT7I+nfbX36JqsoExeepPGzMxKzAG0mZlVoux5oK8DvkFSI3lkRLw8UBdNByr7J5L+z5cCi9IBtG5OB5/KDUz3TddX5AyYFVkvADKBb5fBx3opc63HC1yng6R5dw2wa570iwucN9MEOfu7Nabr7v7Whc5XrKURsTV3Y0Rk8jO8F+cak667NKfOo+i/Q1o7/q/AMOAaYJmkFyX9l6QPSart5jqZ8zUUkSczMysT7gNtZmaVqDki7u+nc/XqZXJE3CLpHuAskprYycCH0uUbko7P6iObCaAeABb1cOrtDfwz1/o1ySBl3ck3yFpfau3z1dRuz/n6M322tnS9U7dH9eG6EfFDSTeTDFJ2XLqcmy5PSDoxK+jPlsnLdg8eZ2Zmg8cBtJmZDXWb03Wh6aJ6aobdRUS08VYNOJL2A/4fSf/Yy4GPpodmAumbI+Ka3l6nl5YA+wPfjohnBvhamYHSuvvb9frvOoAy/dLz1bxvt7Tf94/TBUmHkwy+dgQwA/hqnmSZvKzIs8/MzMqUm3CbmdlQ15quD8zdkc4nvNf2XiBtyntp+vHwrF13pOtztvcaRRjMaz1EUvt8bL5+4JJOA3YpkDbzQmPQXuKnI4AvAYalLzsG+npPkkyFBduWh2yZUcrnDnR+zMys/ziANjOzoe7edP1lSZ1NeNOpna4nGQyrKJKaJH0knYIq1xnpOrsp9kySwbtOlPRjSV2CSkn7Srqo2Dx04wqSfrVflXSRpC4BqqRjJG13gB0RC0nmP64DrpE0KusaewBXdpM880LjHdubj166L12/p79OKGmKpPfl/q3Tvs+Zvu1dmuZLGg0cQvLv5QDazKyCOIA2M7Oh7hrSeZuBBZJulTSbZHqmN4FHenGuvYH/AVZKekjSjZJukfQiyfzBa4CvZw5OR96eBjwF/B+SQccekvTfku6WtAB4Efja9n7JtN/1tDQPVwOL02v8j6QHJbWSzIH8we29VupTJANuTQVeknSTpNuB50lG+34sPW5zTrrbSfoZf17SnZJ+Kuknko7tp3wVMjNdn9qP5zyM5EXCSkmzJd0g6TaS8vYBYBlJk/5cJ5P0Wf/fiGjvx/yYmdkAcwBtZmZDWkSsIhno6waSGtOpwHiSGtvTgS29ON1jwMXAg+k5ppEEZOuBq4BDI2JOzvVfAY4GPg20AAeTBLGHkAS7V5IEW9stIu5Lz/9dkr61x6R5nEAS2F4MXNJP18p8r/9LEhCfBRwK/IhkRPTMqOIrc9I9AXyEZL7lY0lGNf848Pb+yFc3fgu8AnxQ0g79dM7fkcxLPZek//kHgeNJAud/Aw4rMCr8een62n7Kh5mZDRLln+rQzMzMrG8k7QO8AKwDdh7Aebl7RdIM4DLg4xHxsxLlYSxJIP90RBxZijyYmVnfuQbazMzMek2JLgFg2rf8v0iaKP+yXILn1A9Imp1/VVJ9ifIwg2QO6y+V6PpmZrYdXANtZmZmvZYOnLWFJCCdTzKf8V7AO4ERwNPAcRGxumSZzEPSh0nmyv5URPx4kK89jqRm/o6I6K++6GZmNogcQJuZmVmvSRLwbZI+4PsCDcAm4DngVuAHEbG2dDk0MzPrfw6gzczMzMzMzIrgPtBmZmZmZmZmRXAAbWZmZmZmZlYEB9BmZmZmZmZmRXAAbWZmZmZmZlYEB9BmZmZmZmZmRXAAbWZmZmZmZlaE/w/os5nwAqzj6wAAAABJRU5ErkJggg==\n", - "text/plain": [ - "" - ] - }, - "metadata": {}, - "output_type": "display_data" - } - ], - "source": [ - "expt_cfg={\n", - " \"qubit_gain\":2000,\n", - " \"start\":4, \"step\":1, \"expts\":200, \"reps\": 400,\n", - " }\n", - "config={**hw_cfg,**readout_cfg,**qubit_cfg,**expt_cfg} #combine configs\n", - "expt_pts=[expt_cfg[\"start\"] + ii*expt_cfg[\"step\"] for ii in range(expt_cfg[\"expts\"])]\n", - "\n", - "\n", - "results=[]\n", - "for length in tqdm(expt_pts):\n", - " config[\"pulse_length\"]=length\n", - "\n", - " rabi=LengthRabiProgram(soccfg, config)\n", - " avgi,avgq = rabi.acquire(soc, threshold=readout_cfg[\"threshold\"], load_pulses=True, progress=False,debug=False)\n", - " results.append(avgi[0][0])\n", - " \n", - "subplot(111, title=\"Length Rabi Oscillations\", xlabel=\"Pulse length (ns)\", ylabel=\"Qubit Population\")\n", - "plot(soccfg.cycles2us(np.array(expt_pts), gen_ch=2)*1000,results,'o-');" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "# Amplitude Rabi\n", - "\n", - "Measures Rabi oscillations by sweeping over the amplitude of the qubit drive pulse, which is an $\\approx$ 100 ns ($\\sigma$ $\\approx$ 25 ns) long Gaussian pulse. We measure the $\\pi$ and $\\pi$/2 pulse amplitudes which are used in subsequent experiments to control the qubit. We store these parameters here: qubit_cfg[\"pi_gain\"] and qubit_cfg[\"pi2_gain\"] " - ] - }, - { - "cell_type": "code", - "execution_count": 13, - "metadata": { - "ExecuteTime": { - "end_time": "2021-09-30T07:35:01.584025Z", - "start_time": "2021-09-30T07:35:01.417884Z" - } - }, - "outputs": [], - "source": [ - "class AmplitudeRabiProgram(RAveragerProgram):\n", - " def initialize(self):\n", - " cfg=self.cfg\n", - " \n", - " self.q_rp=self.ch_page(self.cfg[\"qubit_ch\"]) # get register page for qubit_ch\n", - " self.r_gain=self.sreg(cfg[\"qubit_ch\"], \"gain\") # get gain register for qubit_ch \n", - " \n", - " self.declare_gen(ch=cfg[\"res_ch\"], nqz=1) #Readout\n", - " self.declare_gen(ch=cfg[\"qubit_ch\"], nqz=2) #Qubit\n", - " for ch in [0,1]: #configure the readout lengths and downconversion frequencies\n", - " self.declare_readout(ch=ch, length=cfg[\"readout_length\"],\n", - " freq=cfg[\"f_res\"], gen_ch=cfg[\"res_ch\"])\n", - " \n", - " f_res=self.freq2reg(cfg[\"f_res\"], gen_ch=cfg[\"res_ch\"], ro_ch=0) # conver f_res to dac register value\n", - " f_ge=self.freq2reg(cfg[\"f_ge\"], gen_ch=cfg[\"qubit_ch\"])\n", - "\n", - " # add qubit and readout pulses to respective channels\n", - " self.add_gauss(ch=cfg[\"qubit_ch\"], name=\"qubit\", sigma=cfg[\"sigma\"], length=cfg[\"sigma\"]*4)\n", - " self.set_pulse_registers(ch=cfg[\"qubit_ch\"], style=\"arb\", freq=f_ge, phase=self.deg2reg(90, gen_ch=cfg[\"qubit_ch\"]), gain=cfg[\"start\"], \n", - " waveform=\"qubit\")\n", - " self.set_pulse_registers(ch=cfg[\"res_ch\"], style=\"const\", freq=f_res, phase=cfg[\"res_phase\"], gain=cfg[\"res_gain\"], \n", - " length=cfg[\"readout_length\"])\n", - " \n", - " self.sync_all(self.us2cycles(500))\n", - " \n", - " def body(self):\n", - " self.pulse(ch=self.cfg[\"qubit_ch\"]) #play probe pulse\n", - " self.sync_all(self.us2cycles(0.05)) # align channels and wait 50ns\n", - "\n", - " #trigger measurement, play measurement pulse, wait for qubit to relax\n", - " self.measure(pulse_ch=self.cfg[\"res_ch\"], \n", - " adcs=[0,1],\n", - " adc_trig_offset=self.cfg[\"adc_trig_offset\"],\n", - " wait=True,\n", - " syncdelay=self.us2cycles(self.cfg[\"relax_delay\"]))\n", - " \n", - " def update(self):\n", - " self.mathi(self.q_rp, self.r_gain, self.r_gain, '+', self.cfg[\"step\"]) # update gain of the Gaussian pi pulse" - ] - }, - { - "cell_type": "code", - "execution_count": 14, - "metadata": { - "ExecuteTime": { - "end_time": "2021-09-30T07:36:04.648458Z", - "start_time": "2021-09-30T07:35:01.590986Z" - }, - "scrolled": false - }, - "outputs": [ - { - "data": { - "application/vnd.jupyter.widget-view+json": { - "model_id": "5a87e643c3c84da79c4aaccfd5e85f6c", - "version_major": 2, - "version_minor": 0 - }, - "text/plain": [ - "HBox(children=(IntProgress(value=0, max=120000), HTML(value='')))" - ] - }, - "metadata": {}, - "output_type": "display_data" - }, - { - "name": "stdout", - "output_type": "stream", - "text": [ - "\n" - ] - }, - { - "data": { - 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+8NbV/s1fBFSoH2Asioj5RdEewAsGe4G3Oud+mcsxMoh/rbN6HpJ8CG8oc7pLzM/jtuWayc+1n/Hv/UzVt3MR/zfiz8N43CHzs823x21Kd9JPRCYABdAiMtG9I+7nbOYK/h/9gd1gMtfDaU2qYb1m9nb6q0l/d5gfM7a815wMQ7BjQzsvNLMLk3f6Q18/GXRn59whvAAF4P1mdnaKYywD3pfmGCfpr4p8s5ndkKa/mNl0v8DRSPgyXoE6gFVJGeL4TPmACu9+xvpbZD5pEW8s3hvpxJbOmkaKubJmVoL32arEGwr9odHrWm78vv6U/hNv73LO/TiH+6cbURHLbMeWPuthEMtEOed2Ouc2p7vENW+K2943VWK4++m/52OV2P/snHs6m9/FzBZk2H8V/X8HtuEVDBxVZrbUzNJ9Zz4z7udjga1EZEJQAC0iE5Zf0Cm27u8zGZbWAcA5tw941L950xCXTBmK/cC5wCNmdq2ZzTazM83sk8C3/TbbSLNO8iA96V+XAJ8xs0ozK/KXYIp/Lu6hf37tT/1KtLPNrMrM3oq31m876f0z3pDfUrzf821mNs/M5vuB4MPAoQzHuA1oxPt/do+ZfcfMrjSz08xbq3mpmd1gZt/GW3poeZbPQ078YP5L/s2lJAaRm+gPor9iZv/kv5ZzzOxVeJn0VwLZFqYasfeGme0yb1mtXTne9Xv0V5b/upn9vZnNNbMKM/trvPfDq+nP5g4m6zri/Pf43XhLJ4F3EujuDAXKkgtOPW1mPzGzt5vZef5zMMvMXmRm/wQ8BZznt/1CqufCzBZb/xJnd43QrzvkfiZZSf9Q61yyzw1mdp//+T/Pfz/PNrNLzezf8NaILsErwHfLMA4Lz8XHgRfM7A4zu87MFppZuf+5eyf90xFa8TL+IjKBqYiYiExkV9K/XNIPc7jfj/z7zgeuJWA95xG2DfgsXhCUas3f/XgFjTIFqTlxzj1hZo/hrbG8mv4ht+AFelf57ZrM7L14X5RPx8vYxYvgVT5/Js1jPWtmN+G9NvMZ+KW7GXg9aTJOzrkTZnY1XkC/HPg7/xIk0xzdofgKXmZ1JnCbmf3IeXr8L9kP4mVov0L/EkQxX8D78v2pLB5nTN4b6TjnDprZP+C9htPpD+TjHcMLnh8crX4NwkISRwl8xr+ks4TEOf0hoNa/BOkB/hUvMBsrw93P2IidbrIb7RNThDftIN10jePA3zvn0q1/PtIW41UlXxWwP4r3/k63fKGITADKQIvIRBY/Hy+XL3T30D8XeMyGcfvVmq8FfoFXhbYDbx7ivwHnO+caR+ihXwOsxcuItgU1cs79AK+68QNAU1z/vghclM1SP865e/GWd/oR3jrcnXiFr74NXJxNxWP/C+sr8OZJ3uPfv90/1gG8TPYqYKlzLufhstnys9Cxyu3nETdv0zn3O7z1a/8P77Xswvt9fwG8zjlXRw5G4r3hD12OrZP9WK73d879EG85q7vxgvguvMDnMbzn/4w8D56HyxV4J0J+g/eanMJ7Lo7iPRdrgHOdc7f5RejGyrD105/f/nr/5oPOucPp2id5J97ojcfwPruteJ/dQ8AGvHWXlzrnMq0vPpI+hvf/5C5gM17fuvGeswa8v5fLcqxwLiLjlI3t324REYnnD9d8B/Bb59xVY9sbmUzMbAVeMNWJFwzsHOMuiYiI5B1loEVERAS8edgAX1PwLCIikpoCaBEREQFvaaxm4HNj3REREZF8pSJiIiIignPu4rHug4iISL7Lmwy0mVWb2QfN7PtmttXMev3lG944xOP+rZk9amYnzKzFzDaZ2S0Z1vMTERERERERSZBPGej3Ah8czgOa2deA9+FVY/0NXnXJa4CvAteY2Zuccz3D+ZgiIiIiIiIyMeVNFW5//cizgU3Ak8B38NZhfZO/zEmux7sBuBdvmZArnHPb/O2n4S1pcg5wq3MueS3OASoqKtzixYtz7YLIhLTjSCsAZ8wpHeOeyGSg95uIiIiMhieffPKoc25OpnZ5k4F2zn07/raZDfWQq/3rj8WCZ/9xDpnZe4FHgFVm9h/Oud50B1q8eDGbNm0aan9EJoQb/+txAO5+98vGuCcyGej9JiIiIqPBzHZn025CzgM2swXAxXhrWd6TvN8591sgAswDLhvd3omIiIiIiMh4NCEDaKDGv37GORcNaPNEUlsRERERERGRQBM1gF7iX6dLw+9JaisiIiIiIiISaKIG0GX+dWuaNi3+9bRUO83sXf6SV5uOHDkyrJ0TERERERGR8WeiBtCxCmSDLjHunPumc+4S59wlc+ZkLMYmIiIiIiIiE9xEDaBP+ddladrE9p1K00ZEREREREQEmLgB9C7/+vQ0bRYmtRUREREREREJNFED6Ab/+jwzCwe0eUlSWxEREREREZFAEzKAds7tBf4MFANvSt5vZlcCC4CDwOOj2zsREREREREZj8Z1AG1md5jZVjO7I8Xu2LY7zeysuPvMBb7u31zjnOsd6X6KiIiIiIjI+Fc41h2IMbMX0x/YApzrX3/ezD4a2+icuyyuzXyg2r9O4Jy718y+AbwX2GJmvwa6gGuA6UA98NVh/SVERERERERkwsqbABovqH1piu1LB3tA59z7zOz3wC3AlUAI2Ar8N/ANZZ9FREREREQkW3kTQDvnHqF//eZs73MzcHOGNj8EfjjYfomIiIiIiIjAOJ8DLSIiIiIiIjJaFECLiIiIiIiIZCFvhnCLiIgEqW+IsHZ9I/ubo1SWh6lbWU1tTdVYd0tEREQmGQXQIiKS1462dLB63RaiXT0ARJqjrF63BUBBtIiIiIwqDeEWEZG8trcp2hc8x0S7eli7vnGMeiQiIiKTlQJoERHJa509qVcc3N8cHeWeiIiIyGSnAFpERPJacSj1v6rK8vAo90REREQmO82BFhGRPvlYrGvBzDA7jrYmbAsXhahbWT1GPRIREZHJSgG0iIgAXvA81GJdIxGAhwoMgNmlxRxr7WRqcYjPv+H8hOPmY+AvIiIiE48CaBERAWDt+sbAYl3ZBKOpAvAP3b2ZW+/eTNUggtr6hggNe5rp7OmlwODjrzmHX2w5wK5jrQOC51SB/6bdTTy89UjaoFqBt4iIiORCAbSIiADBRbnit6cLOFMF4M6/zjWbHQuKYwXEeh18vP5prjlnLjuOtHK0pYOKspLAx4129fCDP+xJePzkYB7Q8lgiIiKSEwXQIiICeEW5IimC6FixrkxDvDNVxY529XDr3ZtZu76xL4DNJRiPdvXwhx1NADyxs4lXnz8fCA78XcDtWL+nFBVknXFXplpERERAVbhFRMT3kevOHrAtvlhXuiHekH1V7EhzlLp7nqLu3qeINEdx9Ae19Q0RIDgoPtbSwZSiAv60q6lv22CqcUe7ejje1pVyX/Jjx04cBPVVREREJg8F0CIiAsCssmIASktCgFe0647r+4t1BQW1keYoy9dsSJm9DtLV6+jqScwRZxOMV5aHWVAe5vt/2M2SVfezfM0Grl42h0K/0NhwSH7sTCcOREREZPJQAC0iMsnVN0RYvmYDN3/3CQoM/tnPOL/3qjMThikHBbUGKYPnwYS0sWD86mVzKClM/BcVLgpx9bI57DrWRleP68sG3/dkhGklIYpDBX2PWZjFf7fy8MBZTKmWx8pmbriIiIhMDgqgRUQmsfjhyeAV61rzQCOlxSG2HWrpa5Muw5w81xigqjzMl268iKpBDK+OBcUvXlSecLw7rj+fh7ceobt3YOb6eLSbD167lC/deBEFBt296R8jXFTAzcuXADBzalHCsdaub0wYnp0uGy4iIiKTiwJoEZFJLGh4clePY9vhUwMC7Gztb45SW1PFxlUr+PKNFxEuCiXsLyowikLBOepoVw9P7TtByOClS2axcdWKjIXKViyby9r1jfSmiOjLw0UJwfz7Vyylp9cRKjDqVlYnZLuT5zjXraxmSlHiv8uikA3IVIuIiMjEpwBaRGQSCwpIO3t62Xa4hbXrtw4IsAFCln6Adnx2tramijuuP5+pxV4QXVUeZu2bLuS9V52Z9hhtnT2UliQOs06X9d164GTg73Mi2sXGVSvY9IlrKTBo7+phw9bDXLxoJl97+AU6klLW8XOca2uqeNMlCwFvWHrIoKfX8aG7N7N8zQYVExMREZlEFECLiExiQQHpjHARp9q72d/cnnJ/j0s1cNuTah5xbU0VH1ixFIAHbn0FtTVVLJg5FYDTppcEHmvalMQAum5l9YBsdsxtP3ma8rjh2PFiv2dFWQlnVJTytYe388z+k2w9eDIwux4fjJ+KdjGrtJgvvulCQgVGr0MVuUVERCYhBdAiIhNcbA5zrGp1fLBXt7Ka4hTFum66bBEAs0qLUx4zKAMdMkuo3B1vSUUpALuOtvZdFxYYH0sRFMf6VFaSGBDHstmpHj/a1YNzDDhWfEBf3xBhd1Nb3zDvk+3dgcXOHLB8zQbWPbmP3z5/hKvOnsMXH3qezjTVw0VERGRiUwAtIjKBZVrDuLamiqvPngN4w5Njxbr+zi+wdcXSCopDAwPst7x0YcpA9Yt/c2HK4BngjDleAL3TD6B3Hm1l0aypXH/xQu64/vy+Ocohg2uXzQWgbMrAStm1NVX0BmTAT0S7+o4V//vE+rR2feOA5bMcwRXDI81RPnzPUxxv6+LhxsNZZatFRERk4hr4zURERCaMdGsYx4LKo62dXLiwnJ/esryvjXOOmVOLmFJcyMWnl/OHHU2ANxS6bmU1tTVVXHL6LNaub2R/czRhe5BFs6ZilhhAx7LStTVV1NZU8amfPs3/PL6bXz59kMICo7mtk4qygUO8K8vDKYPZyvJw37FSCQp0HV6wna5Y2vG2LozUVcdVkVtERGRyUAAtIjKBZVrD+FR7F5v3NvOeK89I2G9mLJ07ja0HT7L7WBuvu7CS/3hLTUKbdIFqKlOKQlTOCLPraCu9vY5dx1pZflZF3/76hgh3b9rbd7u71/UF28nqVlazet2WhJMDqeZeJwsKvKvKw2xctYIlq+5PGSDHxLLV8W2yeVwRERGZGDSEW0RkAsu0hvGfdjbR0+sSAtmYwhA07GmmqbWTjduODEuhrCUVpew82srBk+20d/X2ZaDBy5a3dyVWw+51sLdpYMAbmwsdNFQ7SKoiZPEBcDaZ5Fi2GrzlrJIfN2jOebq56CIiIjI+KAMtIjKB1a2spu7epxLm/YaLQly9bA7L12zoy8ZGjicGqfUNEZ7YdbzvdlNbF6vXbQHIKeucbElFKfWbI32Z5TPiAuh0S2qlkmsGPHYfIHDoearMdrJYtvqLv2rkaw9v59pzT+vbF5tzHrt/bM75pt1N3PdkZMD2+D6JiIhI/lMALSIygdXWVPGjP+3mjzu9YHh2aTGvPn9eQjAH8MmfPkNRqCBtsa3kudODsbiilFPt3Ty5+3jf7Zig4dXJRcyGKl3gHf/7R5qjaYdrv2TxLHod/Hn3ca7wC7EFzTn/0R/3Dlj6azieTxERERldGsItIjJODGYIsHOOfcfbqVlUDsCt1y7l4a1HAguLxWSaOz1YsYzzhq2HmVJUwLzpU/r2pRpeXWCwcNboFuiqrali46oV7FrzWr5040WBw8RffPpMQgXGE7ua+u4b9PwErZut6t0iIiLjizLQIiLjQNDQYEg/BHj3sTYizVHec+UZPHfgJLuOtWUVHKercj0UsTnPT+1rpvq0aRQU9C8glWp49ZSigpRVuEdLumx1WUkh51VO5487+wPooOctZJYyiFb1bhERkfFFGWgRkXEg3XJU6Wx84SgAy8+q4PRZpew+1pqxsBhkLrY1WAtmhiksMJwjoYBYTCz7u3PNa9m4asWYBs/ZmDW1iD/tbOobFXD1sjkpnrcC3vLShRQkLTat6t0iIiLjjwJoEZFxINch1bHh3h//ydOEDJ7a28zps6ey+1hbVsHxYKtcZ/KLvxzo+/nRbUfHdSXq+oYIj71wDPDmSUeao9z3ZIS/vmh+Qrv3XHUmH1ixlF5HXxA9f8aUYXk+RUREZHRpCLeIyDiQy5Dq5OHePQ5u+8nTXHbGTHY3tfH6CysB+PCPN9PrvOA4vhJ1zGCqXKcT61d3rzeUuaWje1xXol67vpHOFIXWfv3cEQB5f3C7AAAgAElEQVS+8KYLWXXfX2jt6OHBpw8CcNtrzuFz9z/HV95cw6VLZo16n0VERGRolIEWERkHvKxx4p/soCHAQcO9/7znBJ3dvRw61c4rllbQ6+DjrzmHjatWjEoAO9hh6PkqKPt/tKUDgJedOZuz5pbxnd/v5FM/e4bCAuvLQG87fGq0uikiIiLDSBloEZFxoLamiqMtHXzu/ucAL3gOGgIcFNidiHYBsOtoG9293trK51VOH6EeDzRSlb3HStCogKnFIYoLC/jTjmO8cKSFHj/j3t3rWLu+kaKQse1QS9pj1zdEAteqFhERkbGjDLSIyDgRLvbmLVeVhzl73rTAgCqoSNhp072CXHuaWnl2/0kAzh3FADqb4mXjSdBc8tmlxZw7fzpf+NXzKdbS9k5cbD8cHEDHhrpHmqN9c6tXr9syrueLi4iITBQKoEVExonHth9j/owpXHH2HPY2tQW2q1tZTUnhwOHeH1tZTVHI2HWsjWf2n6SqPEz51OKR7nZCv0aisvdYiRVaqyz31rKeWhziX2rP4/CpDs6dPz0ws97V43j+UPAQ7ok21F1ERGQiUQAtIjIO9PY6Nr5wlMvPrGDRrKk0tXbS0tGdsm1tTRXXnjMXIKGC9vUXL2TBzKnsPtbKswdOcs780cs+x/o1EpW9x1JtTRWPrbqG114wn9KSQs6rKqeju5fzqqYHZtanTynk8KkOTrR1pdw/0Ya6i4iITCSaAy0iMg48e+AkzW1dvHzpbIpDXhZ3b1NbYBC861gbNYvK+cn7lidsP332VLYePMWuo6285vz5Ke87koa7sne+WFE9l/v/coAfb9oLwLnzZ1C3sjqhGjp4GfcbX7KQbz26k+1HTnHx6QMrcedScV1ERERGlzLQIiJ5rr4hwt9+6w8A3PlAIzuOePNn9wQM4959rJVn9p/ktSkC5MWzS9lxpJVeN7oFxCa6q6rnYAY//OMeigsLOGNOaWDG/e0vWwzA8wGFxOpWVlMYK9ftG89D3UVERCYSZaBFRPJY8prOB0+287VHtgOknAdd3xDhkz99GoBvPbqDirKShIzvollT+34+d5SHcE9ks8tKWDgzzJ4mL3N81dpH+ipnJ2fce3sd4aJQYCXu2poqvvm7F3j2gDdPuqp8CnUrl03IzL2IiMh4owy0iEgeS1VQqr2rF2NgBjoWbJ9s9+ZGHzrZMaB684ET/UOD3/zNx1XZeZjUN0TY39zedztd5eyCAuOsuWVp14Juau0i5Geh171vuYJnERGRPKEAWkQkjwUVjnIMDKAzVW+ub4jwvcd39+2LNLdreaRhsnZ9I929yUtWpa6cXd8QYfvhFh7ddpTlazYMeP6PtXRw8GQ7V509B4CtB4MDbRERERldCqBFRPJYUOGoKUUFAwLoTNWb165vpKO7N2GflkcaHtlWzk4ekh9pjvKhuzezeNX9fcH0swe8Nbrf8GIv69x48OQI9lxERERyoQBaRCSPffSVZ2NJ28JFIS4/czb7mqL0xmU9g4Lt2HYtjzRyMj33MalGCcRewdiw73ue8Cp5X35mBadNL1EGWkREJI8ogBYRyWMvqpqBA8rDRQmVnFcsO43Onl4On+roa/vRV5494P7x1ZuzDfIkd3UrqwkXhRK2paqcnelkRbSrh4eeO8z8GVOYVVpM9bzpNCqAFhERyRuqwi0iksc2bD0MwAO3voL5M/oD3d89fwTw5kHPmzEFgHP8ZanKpxZxoq2LyvJwXyVoIHBdYi2PNHSx53jt+kb2N0cHPPcxQWs8x4t29bC8cjYAy+ZN467HjtHd00thSOe8RURExpoCaBGRPLZh62HOmT89IXiG/uWo9jS1cemSWQD8fttRAH75T69ImVXONsiTwUm1ZFWyVCcxUoktMVZ92jQ6u3vZdayVs+ZOG7a+ioiIyOAogBYRyUP1DRHufHArB060U1ZSSH1DJCE4qywPU2CJlbgfe+EYZ8wpTTskO5sgT0ZO/EmMSHMUo38ONEBhgdHd6zi3cgYA1fO8oHnrwVMKoEVERPKAAmgRkTyTXKm5paOb1eu2AP0B2C+3HMAw/v0327jvyX18+Lql/GHHMW548YIx67dkJ/4kRn1DpG9EgIO+pbA+9bOnae/q4VUvmkeowGg8eIrXXTCGnRYRERFARcRERPJGfUOE5Ws2cOvdmzOu57x63RZ6nBdsRZqjfOSev9DW2cP9Ww5oXedxpLamio2rVvClGy+isKC/3vqhkx2sXreFz93/LAb8x4btKdeMFhERkdGlDLSIyCiJzzYmzz9OzjqnEr+ec1C7ptbOAdlqyX9r1zf2ZZ9jol09/OAPewYscwV6bUVERMaKMtAiIqMgFiBH/KG6sWAollFMFxTHZFrPOSY+Wy3jQ9Br6pJu67UVEREZWwqgRURGQaoAOT4YyhQUZ7Oec7xMx5P8ksta3HptRURExo4CaBGRURAU9ESaoyxfs4HyqUWB960qD3PH9ecnrOccLgqlfbxcAjIZe6leUwtoq9dWRERk7CiAFhEZBemCnkhzlJb27oQiUuBlnb9840VsXLUiYc5rbU0Vd1x/PlX+MZMDrfhstYwP8a+p4Z00uemyRSlPlMROuqigmIiIyOhTETERkVFQt7I6bZGwrl5HScjoxguIk4uMJQtaCinT/SR/pVqj+5LTZ/WtGR0v0hzlQ3dv5ta7N1Ol11xERGTUKIAWERkFtTVVdHb38M/3bQls09HjuPj0mdz33stzPraCp4kp9touX7NhQBCt6twiIiKjT0O4RURGyYULZwIwM8185xXL5o5Wd2QcUeV1ERGR/KAAWkRklOxpagPg5uWLA4uA/c9juzS3VQZQ5XUREZH8oABaRGSU7PUD6Le+9PSEImDxDp/qSFgfWgRUeV1ERCRfKIAWERkle5raKC0OMau0mNqaKjauWpEyiNZwXEmmyusiIiL5QUXERERGyd6mNhbOmopZf/gTNOxWw3ElWarK65HmKKEC4/O1L1IBMRERkVGgDLSIyCjZ09TGollTE7YFDbvVcFxJJzaC4W2XLaKn1/Ghe57S2tAiIiKjQAG0iMgocM6lDKBTzW3VcFzJRn1DhHue3Nd3O7aclYJoERGRkaMh3CIigxAbQru/OUpleZi6ldUJQ2iT97/7iiV0dPeyaHZiAB27T7pjiaSydn0j7V29Cdti8+f1/hERERkZCqBFRHJU3xBh9botRLt6gP7MH3gBcar9//LLrQAsTMpAx+6jgEdypfnzIiIioy/vhnCb2d+a2aNmdsLMWsxsk5ndYmY599XMZprZ581si5m1mlmHme02s/81s4tGov8iMvGtXd/YFxzHxFfOTrW/o9vLFC6cOTCAFhkMzZ8XEREZfXkVQJvZ14AfAJcAjwIPAWcDXwXuNbP0i2AmHmsRsBlYDcwDHgZ+DnQBbwWeMLMbhvUXEJFJIVPmL10GcMFMBTcyPDR/XkREZPTlTQDtB7PvAw4CFzjnXuecewOwFHgOeAPw/hwOuQZYBPwSON0/3hvxAvJP4w1f/y8zKxrGX0NEJoFMmb+g/QUGU4qyPg8oklby2tBFIeOO68/vm0awfM0Glqy6X9W5RUREhlHeBNB4mWKAjznntsU2OucOAe/1b67KYSj31f71Z51zbXHH6wU+C0SB2XgBuohI1upWVlMcsoRt8Zm/upXVFCXtLzBYPLt01Pook0NsOaubL19McaiAv76osm8OfqQ5ikPVuUVERIZTXgTQZrYAuBjoBO5J3u+c+y0QwRuKfVmWh+3Ist3RLNuJiABe0PL6CysTtsXmQNc3RKitqeKKs+ck7O91cOBEu4IYGRFnzS2jtbOH/SfaM87RFxERkcHLiwAaqPGvn3HOBU0efCKpbSYP+tefMLO+qj1mZsAngTDwM+fc4Vw7KyJS6RcDi880x2f6DJg3vYSSwv4/s9GuHmUCZUScfdo0ALYdOqXq3CIiIiMoX5axWuJf707TZk9S20w+gRdsvxbYbWZ/wMtKXwicDnwfb861iEjOjrZ0UGDQ1eMStscyfYUh40S0q6/6dvJ+LVslw2np3DIAth1qobI8TCRFsKzq3CIiIkOXLxnoMv+6NU2bFv96WjYHdM4dBVYA/wNUAK8DbgDOAnYAv3XOnQq6v5m9y19Ca9ORI0eyeUgRmUSOtXTQ61Lv298cZU9TG9Gu3sD9IsNpZmkxFWXFbDt8KuUcfFXnFhERGR75EkDH/tMHfB0dxAHNlgENwErgbcB8oBy4Bi9Q/5aZ/XfQ/Z1z33TOXeKcu2TOnDlBzURkkjra0pkwPDtexbQSnIOZU1MX+VcmUEbC0rnT2Ha4hdqaKs6Z13+u+bTpJX3VuUVERGRo8iWAjmWCy9K0ie0LzBrHmFkhcB9etvl659z3nXMHnXMnnHMbgOuAQ8A7zezqdMcSEUnlWEsH586fnnId3pXnnQbAu644Q+v0yqhZeloZ2w+10NPr2HWsjTMqvKrvd95wgYJnERGRYZIvAfQu//r0NG0WJrVN56XAucBO59zjyTudc03AA/7Na7ProohIv6MtnVy0qDxhHd4Cg8/XvogZ4SIKC4y/f/kZffsNqCoPKxMoI2bp3DJOdXTz6+cOcbK9m5su8/6l7jqabnaUiIiI5CJfiog1+NfnmVk4oBL3S5LaprPIvz6Rpk2zfz0ri+OJiPRp7+qhpaObirISamuqqK2p4p5Ne6m79y8sq5zOA88cZHFFKcWFBX37RUbaUr8S910bdwHw+gsr+dJDz7NTAbSIiMiwyYsMtHNuL/BnoBh4U/J+M7sSWAAcBAZklFPY718vM7PygDax9aR35tZbEZnsjrZ4y8xXlBX3bVt+VgUAG7cfZdvhlr6qyCKjJfaee3zHMZbNm8acaSUsqShl57G2Me6ZiIjIxJEXAbTvDv/6TjM7K7bRzOYCX/dvrnHO9cbte7+ZbTWz7yUd63G8IDoMfMfMpsfdp8DMPoEXQHfjzZUWEcnasZZOACrKSvq2VZaHOaOilIcbD7P7WKsCaBl1j247SoFfknPv8TbqGyIsrihl59GW9HcUERGRrOVNAO2cuxf4BjAP2GJmPzezdcA2vPnM9cBXk+5WAVTTP2Q7dqxO4GYgClwP7DCzB/zjbQc+C/QCtzrnXhixX0pEJqRYBnp2XAANXhZ64/Zj9Lr+4bQio6G+IcLqdVv6llZr7ehh9botdHb1EDkepaO7Z2w7KCIiMkHkyxxoAJxz7zOz3wO3AFcCIWAr8N/AN+Kzz1kc6yEzuxD4MN560Ff5xzsI/B/wFefcH4b3NxCRiaa+IcLa9Y3sb45SWR6mbmV1XzASP4QboDCu4PZnf/EsPb1O859lVKxd30i0KzFIjnb18KddTfQ62NvUxllzdVJHRERkqPIqgAZwzv0Q+GGWbW8Hbk+zfxvw3mHpmIhMOrGsXiwwiTRHWb1uCyuWeWvDxw/hrm+I8KM/7e27ffhUB6vXbQFQEC0jbn9zqtqb0NzWBcDOo208HTk54GSQ3psiIiK5yZsh3CIi+SYoq/fI80coKylkStwaz2vXN9Le1Tug7dr1jaPSV5ncKv2l1JLNmzEFgJ8/5Z0MijRHcXgngz5092YWr7qf5Ws2UN8QGcXeioiIjF8KoEVEAgRl9Vo7epidNHw7qG3QdpHhVLeymnDcCR2AcFGIj71qGbNKi/n1c4cHnAzyp0v3jaxQEC0iIpKZAmgRkST1DRGWr9nQF2AkKyksSBi+DcEZwKDtIsOptqaKO64/n6ryMAZUlYe54/rzqa2pYklFKW2d6YuIabSEiIhIdvJuDrSIyFhKnvecLFwUYka4cEABsbqV1QPuFy4KUbeyekT7KxJTW1OVck7zkopSGvYc76vQHUSjJURERDJTBlpEJE6qec8xU4oKuOP68+nqcQOWsEqXARQZS9HO7ozBM2i0hIiISDaUgRYRiZMuCzdv+hRed8F8PvTjzQOGcENwBlBkrNQ3RHjo2UMZ24WLCrh62RyWr9mgKt0iIiJpKAMtIhInKAs3bUohu461se94FOcGrgEtko/Wrm+ks2dg+rk8XERV3Hv98jMruO/JSEKVbhUWExERGUgBtIhInLqV1RQWWMK2cFGIG1+yEIBHtx8FSJmBFsk3QSMqTkS72LhqBVs/+yqmFBobtg6s0q3CYiIiIgMpgBYR8dU3RPjXB7fSHTdhNDaX+e9fvgSA3z1/BFAALeNDpurwDz59kK5eAivOq7CYiIhIIs2BFpFJp74hwtr1jQlzPYHAKtq1NVU455hVWszjLxwDGLAOtEg+ylQdfu36RnrSVBhTYTEREZFEykCLyKQSW6Yqea7np3/+TNohrGbGufOn09LRDSgDLeNDpurwmTLMkeYoy9ds0FxoERERnzLQIjKppFqmKtrVE7h0VXyAcW7ldH6//SjFoQKmT9GfTxkf0lWHrywPE8kiiF69bkvfsURERCYzZaBFZFLJdU5n/BDWaKeXfe7s6eXldz6srJyMe3UrqwkXhRK2WYp2KigmIiLiUQAtIpNK0JzO8nARxaHEP4nxc0XrGyL8eNO+vn1a5kcmglRDvFVQTEREJJgCaBGZVOpWVjOlcGCgfPvrz+P1F84HSDlXdO36Rjq6exPup6ycTAS1NVVsXLWCnWtey8ZVKxLWh46ngmIiIiIKoEVkkqmtqeKGi/vncZaVFPYFyrOnlVAcKuCFz7+GjatWJMz3DMq+KSsnE02qYd2ggmIiIiKgImIiMglFu3qZVVrM1OIQNYtm9gXKkeNR5pdPoaBg4CzQoGJLysrJRBM/6iL5Pa+CYiIiMtkpAy0ik4pzjse2H+NlZ85m0ayp7Dve1rcv0hwNHL6aKisXP0daZCKJDetO9XnQ1AUREZnMFECLyKTywpFWDp5s5+VnVbBw5lT2He/PsEWOBwfQmdbTFZmINHVBREQkkYZwi8ikUd8Q4VM/ewaAL//6eS5eNJMjpzpo7+rBDA6f6qBqZvCQ7HTr6YpMRJq6ICIikkgZaBGZFOobIqxet4UT0S4ADp3s4KHnDgGw73iUgyfaAQUGIvE0dUFERCSRMtAiMimsXd9ItKsnYVtXj7fi7b7jbX1rQC9QAC3Sp7+g2FYize1MKSrQ1AUREZnUlIEWkUkh3ZzNfcej7PP3pxvCLTIZeQXFruEtly6isKCA15w/f6y7JCIiMmYUQIvIpJBuaPa+41H2N0cxg/kzFECLpHLNsrm0dHTzxK6mwDb1DRGWr9nAklX3a81oERGZkDSEW0QmhbqV1Xz4x5vpdf3bwkUhSosL2Hu8jalFIeZOK6G4UOcVRVK5/KzZhAze9b+baOvoobI8TN3K6r7h3LE6A7GpElozWkREJiJ9UxSRSeH1F1YypbCAqcWhhGWols2fwb7jUSLNURUQE0njV88cwgGtHT04vAD51rs3U/OZX1HfEElZZ0BrRouIyESjDLSITDixL/P7/aC4bmU151ZOp62rl3994wX8zSUL+9r+cecxHnr2EKUlhZxfNWMMey2S39aub0wYwRFzvK0rIfOcTGtGi4jIRKIAWkQmlKBhpK+9wCt89NIlsxLaL5g5laMtnTS3dfGqF80b9f6KjBfpAuFoVw8hM3rcwAhbIztERGQi0RBuEZlQgoaR3v+XA8ydVsKiWVMT9i3wq2539zotYSWSRqZAuMc5SpJqCGjNaBERmWgUQIvIhBKUJYt29XDpklmYWcL2BXHLVilTJhKsbmU14aJQ4P6q8jBvfsnChNtaM1pERCYaDeEWkQmlsjxMJCCIvjRp+DbAwpn9GWmtAS0SLBYI3/6zZ2iOdiXsi2Waj5zqAGD6lEI2rlox6n0UEREZaYPKQJvZAjO71MyuCLoMd0dFRLKRLkv21Q3bB6xLu3Hb0b6f3/ndJ7RurUgatTVVbP7UK/nyjRdROWMKANOmFPZlmvef8E5enWzvpj2gqJiIiMh4llMG2syuB+4AzsrQ1OV6bBGR4VBbU0VrRzcfr396wL7DpzoS1qWtb4hwW1y7AyfatW6tSBZqa6qorani0n/5NVdVz+n7vMRPoTh8soNFs6cGHUJERGRcyjrINbO/An6Ml7U+AewATo5Qv0REBm3padMAmF1azLHWzoR9sXVpa2uq0q5bqwBaJLMFM8PsO94fNB840U5xqIDOnl4On2pXAC0iIhNOLlni2wADPgGsdc51ZWgvIjImth0+BUBTUvAcE8uSBRUc07q1ItlZOGsqDXua+27vb45yTuV0ntrbzGF/PrSIiMhEkssc6AuABufc5xU8i0g+23aohdLiEJXlU1Luj1XbDqq6rWrcItlZMDPM/uYoPb2O9q4ejrZ0ctGCGQAcPtk+xr0TEREZfrkE0F1A40h1RERkuGw/3MJZc8uoW7lsQEGx+HVpUxUc07q1ItlbMHMq3b2OgyfbOXjCC5jPq5pBqMCUgRYRkQkplyHcTwJnjFRHRESGy/OHTvGKpf2Fjdaub2R/c5TK8jB1K6v7tmfaLyLpxdZR39fURo9z3rbyMHPKShRAi4jIhJRLAL0GeNDMrnPOPTRSHRIRGYoTbV0cPtXB2aeVAf3VgoNk2i8iwRb466jHFxKrLA8zd7oCaBERmZhyCaAbgX8BfmZm/w7cD+wBelM1ds7tGXr3RERys/2IV0BsqR9Ai8jIqSyfghnsPd5GyAyAeTOmMHdaSUJQLSIiMlHkEkDvwlvf2YCP+pcgWgdaRMbEtkMtACydO22MeyIy8ZUUhjht2hT2HY9SFCqgoqyYKUUh5kybklCdW0REZKLIJcjdgxcYi4jkrecPtRAuClGlStoio8JbC7qNksIQ82d4n7u500o41tpJV08vRaFc6pWKiIjkt6wDaOfc4hHsh4hI1uobIn2Fv2aEizCD5rYuKsvDlJWEOGtuGQUFNtbdFJkUFswMs2n3caYWh1g8uxSAudNLADja0tEXVIuIiEwEOi0sIuNKfUOE1eu2EGmO4oDmaBfH27pwQKQ5SuOhFhoPnqS+ITLWXRWZFBbMnMqBE+3sOx7tW0N97jRvDfbDJ1VITEREJhbNUxaRcWXt+kaiXT1p23T2OFav2wKgCtsiI2zhrDA9vY62zh4qy73Aee40LwOdXIk7fvSIlo0TEZHxKOcMtJlVmNlqM1tvZk/7l/VmtsrM5oxEJ0VEYvY3Z1fZN9rVw9r1jSPcGxGJLWUF9Gegp8cC6Pa+fcmjRyLNUVav26LRIiIiMq7kFECb2auB54HPAdcB5/qX6/CWuNrqtxERGRGVORQHyzbYFpHBWzCz/zMZm+9cUVaCWeIQ7lSjR3SiS0RExpusA2gzWwbcB5QDfwLegxc4vxJ4N/BHYCZwr99WRGTY1a2spjDLAmG5BNsiMjhP7Gzq+/mWH/yZ+oYIRaECZk0tThjCHXRCSye6RERkPMklA70KmALUOede5pz7pnPuN865XzvnvuWcuxxvbegw8LGR6KyISG1NFfOml1AcKsCA8nARU4sG/ikLF4WoW1k9+h0UmUTqGyL8v58+03f74Mn2vmHZc6aVcCRuCHdsfnQynegSEZHxJJciYiuAp51zXwxq4Jz7NzO7GbhmqB0TEUnl8Ml29jW3U7eymluuPqtvu4oTiYy+dMOyz5xbxuFTHX2fzUhz+4D760SXiIiMN7kE0KcBv8ui3RbghsF1R0QkvYcbDwOwYtnchO21NVUKmEVGWbph2S87czab9xxn9botgZXzV79mmT63IiIyruQSQJ8EsvkvVwmcGlx3RERS689iRSkw2HrgJOfMnz7W3RKZ1CrLw0RSBNEzwkU8+PRBWjq6U95v7rQSDp/q4Iu/auRTP31Go0ZERGTcyGUO9Cbg5Wa2PKiBmV0OvAJ4YqgdExGJiV/+BqDXwW0/eVrL34iMsbqV1YSLQgnbigqM1s7uwOAZvPWhzeBEtFtLWomIyLiSSwD9VSAEPGBmnzGzM82s0MxC/s+fBh4AzG8rIjJk9Q0RPvLjp7T8jUgeqq2p4o7rz6eqPIwBVeVhyqYU0tXj0t4vZIZLaqLPtIiIjAdZD+F2zt1vZnfiVdj+uH/p9XfHAnED1jjnfjmsvRSRSSmWee5J/qbt0/I3ImMvuf7AklX3p20fLgoFzonWZ1pERPJdLhlonHOrgdcBjwCdeBnpkP/zw8DrnHO3DXMfRWSSSlXhN56WvxHJP+k+l1Xl4b6Mda73FRERyQe5FBEDwM8u/9LMQsBsvKzzUedc8LdcEZFBSJeN0vI3IvmpbmX1gMrb4aIQd1x/fkKmOlUbfaZFRCTf5RxAx/gB8+Fh7IuISIL5M6aw/8TAtWNDZgO+jItIfoh9LtOtyx77+bafbKGts4cqVeEWEZFxYtABtIjISIktWZUqeE6VyRKR/JLNuuy1NVUcbengc/c/x88/8HJmlRaPUu9EREQGLzCANrNP+j9+1TnXFHc7G84599mhdU1EJpP4dZ4NiC8bFrutLJXIxHLmnDIAdhxpYVbprDHujYiISGbpMtC3431n/T+gKe62pblPbL8DFECLSFZi1bZj8yGTa27HgueNq1aMet9EZOTEAugXjrRwyeJZ/aNPAoZ+i4iIjLV0AfRn8L63Hk26LSIyrDJV2wYtbyMyEVXNDFNcWMALR1oHnEiLNEdZvW4LgIJoERHJG4EBtHPu9nS3RUSGSzbBsZa3EZl4QgXGGRWlvHC4hfv/cmDAibRoVw9r1zcqgBYRkbyR0zrQIiIjIVNwrOVtRCauM+aU8sKRlsATaRp9IiIi+STrANrMdpjZnVm0u8PMXhhat0RkMqlbWU24KJSwLVZsoao8rKrbIhPYmXPK2Hs8yvwZU1Lu1+gTERHJJ7ksY7UYmJNFuwq/7aCY2d8C7wUuAELAVuC7wDecc72DOF4I+AfgJuA8oBQ4AmwGvumc+/lg+yoiw6O2poreXseH73kKULVtkcnkzDll9PQ63v6y0/niQ8/T1dNfbkWjT0REJOiLoJ0AACAASURBVN+MxDrQYaB7MHc0s68B7wPagd8AXcA1wFeBa8zsTc659JWGEo83C3gAuBQ4AWwETgEL/eMeAhRAi+SBS8/wlrC54/rzeculi8a4NyIyWmKVuBdXlLJgZpidR9sAmD9jCh971TKdSBMRkbwyrAG0mc0AlgMHB3HfG/CC54PAFc65bf7204CHgTcA7we+kuXxCvCC40uBbwO3Ouda4/aXMYRMuYgMr71N3jzHRbOmjnFPRGQ0LZlTCsBjLxxj17E2Fs4Ks7cpyj3veRkLZurvgYiI5Je0c6D9ec87zGyHv+mN8duSLnuAw8AiYP0g+rLav/5YLHgGcM4dwhvSDbDKD4yz8Y/A5cBvgXfFB8/+cVucc08Pop8iMgL2NnlZJwXQIpNLWUkh86ZP4e4n9uIcfSNQmtu6xrhnIiIiA2XKQC+O+9kBZf4lSCdQD3wsl06Y2QLgYv/+9yTvd8791swiQBVwGfBYFod9v399p3NO61eL5Lk9TW2ECiywkJCITEz1DRGOt3XS0d1LYYER7fRmah1v6xzjnomIiAyUKYBe4l8bsAO4F6gLaNsJHHHODWb+c41//YxzLmi9iifwAugaMgTQZjYPeBHeHOqHzex84AZgPnAMeNg599Ag+ikiI2RPUxuV5VMoDGl1PZHJor4hwup1W+jo9mqEdvc6vvk7b9Db8Rwy0PUNEdaub2R/c5RKFSEUEZERlDaAds7tjv1sZv8DPBq/bRjFAvV0x96T1DadC/zrXcD/wxsebnH7V5vZ74AbnHNHc+iniIyQPU1tGr4tMsmsXd9ItCuxNmgsmG7OMgMdC8Jjx4k0R1m9bguAgmgRERl2WRcRc869cwT7ERsW3pqmTYt/PS2L483yr5cAtwHfA+4AIsAlwNeAK4AfAyty7ayI5C4+QzQjXISZN8cxli3a29TGK887bay7KSKjaH9z0KCz7OdApwrCo109rF3fqABaRESGXb6MlYxlh4drrnLs9yoEfuOce4dzbqtz7pRz7mHglUAUuNrMrkzZIbN3mdkmM9t05MiRYeqWyOQUyxBFmqM4oDnaxfG2LhxetmjVur9wrLWThcpAi0wqleXhlNuN7OdABwXhkeYo9Q2RwXZNREQkpZwDaDN7iZndaWY/MbPfmNmGFJff5HjYU/51ugJlsX2n0rRJPh7AN5N3Ouf2Aff7N69JdQDn3Dedc5c45y6ZM2dOFg8pIkFSZYjitXd5QzY1hFtkcqlbWU24KJSwLVwUonxqUdYZ6KAgHGD1ui0KokVEZFjltA60mX0J+CcSM8bxc4tjt3PNJO/yr09P02ZhUttsjgewM6BNbPu8LI4nIkOQbphmvIVa81VkUokNsU4uAPad3+/MOgNdt7Kaj97zFN29A796aCi3iIgMt6wDaDN7C/BBYC/wWeCNwHXASuAs4Ca8dZfvBB7MsR8N/vV5ZhYOqMT9kqS26WzFm09dCswOaFPhX7cE7BeRYVJZHiaSRRCtDLTI5FNbUzUgwL3vz/v6MtCZKmzX1lRx18adbN53IuXxsz2BJyIiko1chnD/I9ANrHDOfRs4AOCce8g59w3n3MuB24EPk74Y2ADOub3An4Fi4E3J+/15yguAg8DjWRyvC/iFf3PAEG0zK8IrIgawKZe+ikjuvGGawX9uQgX2/9m78/i47vre/6+vpJE02nfJGu92IifBISJhDc3iQB0oizAN/Lrd23vb2x/bhaStwSktpC2tQw2XLgRuudAdaMiC4DaAoQkEYgjZ5MTYseI4jpexte/SaGY0871/nDkjjTQzmrG1jKT38/HQYzRzzpx8DQ8ffz/n8/1+PhTlG6pKPEs4KhHJVVUlhQxNhObUT/APBbjj3sNs3vcQ19/9SHx59pS1FBUkv8ekW+ItIiKSrWwC6FcCj1trT6Y5589xMtQfv4ix7I+9ftoYs9390BjTAHwh9vZua210xrEPGWOOG2P+JcX1osAHjTG3zPhOPk6WfBtOVe5vXsRYRSQLba0+Pvn2q+Lvq7weqmPBckGe4fKGMrY1lGOMSXUJEVlDqks8DE6Ek9ZPcBdqu+2qvvnMOU73TfCazdVJ91Pv3d2yRKMWEZG1IJsAuhQ4N+N9EMAYE28rZa21wJM4S7mzYq29H/gizp7kI8aY/2uMeRA4AVwJtAOfn/W1OqAF2Jjkes8CtwPFwPeNMY8bY+4HXgDuAIaB21IsFxeRBfb6bc5uis/c9koOf/KX6fjEL/OJt13JVNRybiig5dsiEldVUsjIZHje5deBcIRPH+xkNDjFTTsa2b9nJ76qYgDKigrYv2en9j+LiMiCyiaA7iFxP7Hb22n7rPMqSV9NOyVr7Qdw9lI/A9yIs7/6ReBDwLuttanL+Ca/3t/h9Hn+bmyc78DZ9/0l4Bpr7bzLwUVkYfSNBQGoKyuMf5YXuwONTk7x2It9qpYrIoCTgbYWmiqL5z23e3gSgM21JbS1+ji07xa21JVyY0u9gmcRkQXU3uHn+rsfYcusbTSL9b1clU0V7heBLTPeP4lTcft9wP8PYIxpAW7GyRpfFGvt14CvZXjuXTj7rtOd8yPgRxc7HhFZGH1jTkXdurIiwLmZfvq7nfHjY8Ep7nzwCIAmvSJrXHWJ86Dtv12/mc/94ETaNnhVseXem2pL4581VxVzQcXDREQWjFuTwr0fu9toIP287WK/l8uyyUD/ANhmjLki9v4gzh7i3zXGPGGMeQB4HKcQ2L8u7DBFZKWbzkA7AXSyvY1uyxkRWdsqYzUSrt1Uw/49O+MFwmZXSfB68nntlhqMgQ0108XC1lV6OT80uVTDFRFZ9bKdt7lZ59vvPbzq5nvZBNBfBT4BlABYa4PAe3CWcl8HvAtn+fZ/AJ9b2GGKyErXH8tA15Q6maVUexvVckZE3Az00ESItlYfTZXFvO3qdXzuvdfgi1XV9uQb9u/ZibewgOZKL0UF0wXEmiuL6RmdJByJJr2+iIhkJ5t528wOCtlebyXIOIC21p6x1v6FtfbpGZ/9DGdZ91tw9i5fa619p7V2auGHKiIrWd9YkEqvh8JYJilVaxm1nBERt0r/4ESYSNRyfijA+mp3j/MuPnDTNqyFW1/RxOn+8TlFCJurvEQtdI8oCy0ishCymbcly1Zner2VIJsMdFLW2oC19qC19uvW2o6FGJSIrD79Y6GEAmJOb2i1nBGRuapmZKCdTLJNWKLdurGaqajlF/5hTvdPsLkuMYBeF5uYXRhWAC0ishCymbfNl11e6fO9bIqIiYhctN6xILWx/c8wXTjiwMFOzg8FaK7ysnd3y4otKCEiC6eiuID8PMPQRJizA85EbH31dJDcurEKgB+/0Ev/eCihgBgQb2W1kpcIiojkEnd+dse9h7FAeXEBf/7OVySdtzVXeVMu3/atgvleygDaGDOnt3I2rLVnLuX7IpL72jv8GQfA/WNBdjRVJHzW1upb0TdQEVkcxhgqvR4GJ0KcG5wAYH31dAa6rqyIjTUltB8+D8CmWUu411U656qQmIjIwrn1FU3cfq/z+xu3182Zw7nzwmTBs9eTz/49O1fFvC9dBvplwF7kde081xaRFS5ZW4I77j3M7fceTvp0sW8sRO2MJdwiIulUlXgYmghzbtCZiPlm7Zdr3VjFt9wAelYGurSogIriAi4MKwMtIrJQBidC8d87u0YTjs2eF860GrLOM6ULcs9w8QG0iKxyyQpEuDeM2T3+QlNRhgPheAsrEZH5VJcUxjPQ9eVFFM/ae5efN93U6nf++Uk+duuOhMlZc5VXS7hFRBaQ21FlR1M5L3SPEghF8BY69+ZUhcN8VV4O7du1pONcbCkDaGvt5iUch4isMPNNTN0ef22tPgbGnRuuMtAikqnqEk98CfaG6sTsc3uHn4eeuxB/f2F4MuGhHbgBtJZwi4gsFDcD/fpttRzvGuVEzyhXr3dqUqyl9qSXXIVbRNamTNoPuDfNvrEggDLQIpKxqpJChiZCnB2cSCggBk6mIziV2OPZfWjnaq4q5ryWcIuILBg3IfL6rbUAHJ+xjHsttSdVAC0iFyVZO4PZ3JvmdACtDLSIZKa6xEP/eIgLQ5MJBcQgs0zHukovQxNhJkJTizpOEZG1wg2gWzdWU1SQl7APei21J1UALSIXpa3Vx/49O3G3IZpZx2feNPtie2aUgRaRTFWVFBKcijIVtXMy0JlkOprjray0jFtEZCEMjIfIM1BTWsjljeUJAXRbq49PvP2K+HtflXfVVN2eLeMA2hgTyeJHj3tF1oC37GwiauH333w5n3vvNfHeq8UFeQk3zf5YBrpWAbSIZKiqxBP/fXYGOpNMR3OslZUqcYuILIyB8RBVJYXk5xlamsoTlnADXLGuEoAv/da1HNq3a1UGz5Bdq6nZCaaFOldEVqjeUScwbqwoivd0/uP2Izz4jJ+37GyKn9c3FqTYk0dpYfol3yIiruqS6S0fG2b1eXYnZen60LvZ6NVYwEZEZDG4fZxT3VcHxkPUlDr35qlIlL6xIFv2PRQ/N2qdfizbGsqWZfxLJeMA2lqbNFttjDHAJuBXgD8F7rHWfnJhhiciuax7xAmgGyqK45/t2tHAvz1+hp+/NMANl9cDTtuDurIinNuFiMj8Zmag3eXYM7kP7VL5+Uv9AHzsgSP87cMvrqoepCIiC212H+fZLUkhFkCXFNLe4ec7R7oAp4Wpe+4bt9dSkGfYOOuh52qTTQY6KWutBV4G7jHGPAv80BjzvLX23y/12iKS23pGnL2FjeXTk9vXb60j38D7v/o0E8EIzVVeyorytXxbRLLScWYo/vuuzzyaVQDc3uHnT751NP4+2URQRESmJevjPLMlKTgB9Lb6Mg4c7CQUmdsJ4Scv9rGptgRP/uous7Wgfzpr7WPAM8DtC3ldEclN3W4AXTEdHB882oUFxoOR+FPJF7rHmIpEkl9ERGSW9g4/f/fwifh7NwBu7/Bn9P10E0EREZkrk+4GgxMhqksLU547GY6yrX51L9+GxanCfRq4ahGuKyI5pns0iCffJOxVPHCwk6hNPM8Cp/omlnZwIrJiHTjYyeQ8fZ7TyWQiKCIi0+brbhCNWgYnwtSWFqbt7bxVAfRFuQqIznuWiKx43SOTNJQXk5c3vbc51QR1IqQMtIhk5lID4EzaXImIyLS9u1soLkgMDWd2NxiZDBOJWqpLC5N2QiiKfXdbfenSDHgZLVgAbYypNcbcA+wAfr5Q1xWR3NUzEqShInFvc6oJaqX3kksuiMgacakBcCZtrkREZFpbq4/fu3Fr/L2vqjixJel4CIDa0kLaWn3s37OTdZVODZyyogJ+6/WbgNVfgRuy6wP9UpqfHqAHeD8QBu5apPGKSA7pHplMKCAGySeuAFMRm/H+RRFZ2y41AHYndw3lzgO+6hJPwkRQRETm2lQznT3+zkduSLhnDsYC6OpYG6u2Vh8/u/MW3rCtlnWVxfH77bY6BdAzbU7zU4cTOD8M3Gyt/elCDVBEclf3yGRCATGYnrhWeT0Jn4+HIlkVARKRtcu9j/iqvBjAV+XNOgBua/Xx2Md2kZ9n+PXXblTwLCIyj7OD0/Vq+seCCcdmZqBn2rWjgRM9Yzz6Qi91ZUVUliTO/1ajbNZUbklzLAT0WmunLnE8IrJCBEIRRianEnpAu9pafRw42MlQIJz4nVntEEREUpmvz3MmCgvy2FxbwonusQUalYjI6nVmYEYAPR5ia/30MTcDXZMkgP7UQ89z6MV+XrOlZknGudwyzkBba0+n+bmg4FlkbekZdVtYzQ2gQVVwRSQ3XN5YzokeBdAiIvM5OzBBebGTX02VgZ4dQG+tL6Ou1Mk6P3FqgOvvfmTVrzZc3V2uRWTRdI84N9bZS7hdqoIrIrngsoYyTvePMxlWJwARkXTODExwzYYqAPrGQgnHBsdDlBTmUzyrPkV7h5/BwHQe1T8UWPVb9rIOoI0xhcaYXzPG/L0x5iFjzH8YY75kjPl1Y0zymbSIrDrdI+kz0KqCKyK5YHtjOVELp/rGl3soIiI5azIcoXskGA+gB8YTA+iB8RDVJYVzvnfgYCeRqE34zN2yt1pl1VfGGPMG4GvABsDMOvw7wH5jzG9Yax9boPGJSI6KB9DlyQNod+/igYOdnB8K0FzlZe/uFu1/FpEldXmjUxH2RM8YV6yrSHpOe4df9yoRWdPOxQqIbasvo9LrmbOEe2AiRG3Z3AB6LW7ZyziANsZcBXwfKAFeAr4OvBw7vBl4L7Ad+J4x5rXW2qMLOlIRySk9o0GKCvKoSNPfeSGKAImIXIotdaXkGTjRPZr0eHuHnzsfPEIgtsTbXX4I6P4lImvG2QEn4N1Q46W2rJC+DDPQzVVe/EmC5dW8ZS+bJdx/hhM87wcut9b+ibX2K7GfPwF2AH8ZO+dPF36oIpJLnBZWxRgzezGKiEjuKCrIZ3NtacpK3AcOdsaDZ1cgHOH2ew+viWI4IiIwXYF7Q00JtaWFczPQ46E5LaxgbW7ZyyaAvhHotNZ+3FobnX3QWhu11v4x0AnctEDjE5EclawHtIhILtreUMaJnuQZ6HTLDNdCMRwREXAC6GJPHvVlRdSWFtE/liQDnSSAbmv1sX/PTnxVXgzgq/Kyf8/OVb2CJ5s90F7gmQzOewZ458UNR0RWip6RIFc0J99PKCKSSy5vLOfh4z2EpqIUFiTmDlItP3Spf72IrAVnBibYWFOCMYbaskKeeHk6gJ4MR5gIRea0sHKttS172WSgO4F1GZy3DjhxccMRkZWie2QyZQExEZFcMhwIEYlaWv74u3OWZd/+psvm/f5qLoYjIgJOD+iNNSUA1JYVMTgRilfXHkjRA3qtyiaA/t/ADcaY61OdEDt2A/D3lzowEclNfWNBOs4MMh6KcP/TZ7W0UURyWnuHn288dQ4Ay9xl2W5Gui5JdVnXai6GIyJireXswAQbYgF0XVkh1sLgRIj2Dj/vvOcQ4NSM0LwviyXc1tovGWN24FTZ/gLwVeBU7PBm4DeADwB/Y6393ws9UBFZfu0dfk71jeO2+xuZnFK1WhHJaQcOdhKcSizdEghHuOvbRzlwsBP/UIB8Y/j4W67A5JmEityw+ovhiMjakapl38B4iPFQJJ6BdjPN9z11lr99+MX4PXFgPKR5H1lkoI0xEeAjOFW2/xDoAIZiP4eBvUApcLsxJjLrZ2rhhy4iS+3Awc548Oxy9weKiOSiVMuvhwLh+N7niLX8UfsvANi/Zyf1ZU6BxOoSz6ovhiMia4Pbss8/FEhYjfPH7Ue49a9/AsDnH3mR9g4/taXOPfArj51K2qVgrc/7slnCbS7hJ5v/jojkqFQTUe0PFJFcleny65nFwn565y5KCvN5xyubFTyLyKqQqmXfVx8/Q2+sZVV/LMP87NlBAPpmVeJ2rfV5X8aBrbU271J+FvMPISJLI9VEVPsDRSRXJetRmoo7KfTk5/GqjdX8/NTAYg5NRGTJpAp6Zy0sJBCO8M8/Ow1ApTf5bt+1Pu9TYCsiCdo7/Fx/9yNs2ffQnGq1e3e3YEzi+dofKCK5zO1RWhvb01dXVkh1iSfpuTMnha/ZUkNn9yjDE+ElGaeIyGLKJujtGp4kz8BrNtfg9SSGi5r3KYAWkRlS7Y9xg+i2Vh9NFdOtq3xVXu0PFJGc19bq4+AdNwDwvhu38cm3X0VRQfpJ4as312AtPHU6MQud7iGjiEiu2ru7hYK8xCyISXFuc5WXmtJC6sqL+f03T98XNe9zZFyF22WM8QC/CtwEuP/r+YEfAfdba/WoVmSFSrU/xt0XCGCtc8N9/s9vpTjDZZEiIsutrqyIxooijp0f4X+99xp+fqqfrz9xFgMJ1Whd5wYnAPidf34KX+w4kFCl233ICGu7Iq2I5L62Vh9//+hJnu8aBcBXVczNOxp44Gl/0s4DX/zRSfrHgrxuaw0A3/nwL3Flc8WyjD3XZBVAG2OuBe4DNjH3ocXvAp8yxtxmrX1mgcYnIksokyJhw4Ew5cUFCp5FZMW5cl0Fxy6MAGCMoby4gGc/8cvkzcrKtHf4+cS3jsbfu4FysSdv3oeMIiK5yFpLz2iQPANRC9/5yA1Uej1ct6mGO75xGGuJPyxsa/XxjafO0j8e4si5YYoK8rissWy5/wg5I+MA2hizHjgI1ABncfpAn8QJpLcAvx57PWiMucZaqzVNIitMc5U33tZl9ucAvaNBAuEIdWVru3iEiKxMVzZX8OMTfUyGIzxzepBrNlTNCZ4h9Wqc2Z+51npFWhHJfeeHJ+kfD/GazTU88fIA3SOTVHo97L6qCWudJd4fvHl7/PzasiKOnBviOf8wVzZX4MnXzl9XNv9L7MMJnv8W2G6t/SNr7VestV+21n4cuAz4G6A2dq6IrDBOtdrk+wLbO/z88uceBaBrZFL7/kRkxbmquZJI1NJxZogXukdp3Vid9LxsA+K1XpFWRHLfc2eHAHjzlY2AUygMnDkdwLrK4oTza0sL6R0NctQ/zNW+yiUcae7LJoC+FXgJuCPZPmdr7RTwB7Fz3rowwxORpdTW6uOjt+6Iv6/0eti/Zyfg7PsbjFWjDUdsQnExEZGV4Mp1zv69f3/yDFELr9pYlfS8VAFxlddDYb4q0orIyvOcfxhPvuHmHfXAdOB8Ydh5YNiUJIAeD0UYD0XYuT75vXKtyiaA9gFPWGtntwuLs9ZGgSeA5ksdmIgsj/XVJfHff+t1m2hr9aUtLiYislJsrCmhrKiA7x7pAqB1Q/IMdLLe0V5PPne94yrecc30FGddZbEq0orIinDk3DAtTeXxeV63m4EedjPQiQ8Oa8uK4r9fvV4Z6JmyCaADOEu451MdO1dEVqBj50cwBiqKC+gdDQKZFRcTEcl13372PKGpKKFIlII8ww87e5Ke5/aO9lU5GZnSovx4oNxQPj2p/MJvvErBs4jkPGstz50bYqevimJPPtUlnhkZaOd1ZptSgBd7RuO///Y/PqFVhzNkE0A/B9xkjNmR6gRjTAtwc+xcEVmBjp4fZktdKRtrS+gdcwLoVMsZte9PRFYKt899KBIFYCqafitKW6uPQ/tu4bKGMt64vS4eKPuHAvFeqi/3jy/N4EVELlJ7h5/X7X+YkckpvnvkAu0dfhoriumesYS7usSDtzA/4Ttf/fmZ+PvzQ5PaujdDNgH0V4BC4BFjzH83xhS6B4wxHmPMfwMeBjzA/1nYYYrIUjl2YYQr11VQX1YUz0Dv3d2ifX8isqJd7FaUDTUlnBucXm3jHwxw9fpK8gyc6lUALSK5y31w2D3izOeGAmHufPAIhuk90F3DkzTNWr594GAnwalowmfaujct4wDaWvuvwNeBJpwAedwYc8YYcxqYAL6Ms/f569bary7GYEVkcQ1PhDk3GODK5grqy6cD6LZWH+9snd73V5ifp31/IrKiXOxWlPXVXs4OTMTf+4cCbK4rZX11Caf6J9J8U0RkeaV6cHh6YIKuYWeOd2F4ck4Fbm3dSy+rhl7W2t8APgS8DOQD64ENsd9PAR+y1v7mAo9RRJbIsQsjgFOptr68iL6xINGoUzewsbyYPAOv2VJD68YqBc8isqJc7FaU9dVeRianGA6ECUeidI9M4qvysqWulFN9Y4sxVBGRBZEq4J0IRegfDxKORGMZ6MQAWlv30su6I7a19gvW2m04gfPrgNcDG6y12621X1joAYrI0nED6KuaK6kvK2IqahmcCAFwfjhAU0UxZjkHKCJykVJV1p5vK4pbsdY/GKBreJKoJR5Av9w3QZrmJCIiyypdSz5r4ezABP3jIdbNKiB2sffLtSLrANplrfVba5+w1v7cWqsd5SIrXHuHn8/E9ra03XOIU33O3j63kNiFoUnW6cmjiKxQ05W1vRicIDiTrSjrq5373rnBCfyxbI6v2gmgx4JT8XukiEiu2bu7BTMr8+H15POe69YD8Oy5IWBuD+iLvV+uFQXznWCM2QXcBmwCgsBh4MsKmkVWD7fIhLtPxj8U4OtPngWgdzTIjiYnA331+ip6YkUnRERWmrZWX9YTwA2xDPTZwQBVk1OAM5mM7W7hVO84DeXFqb4uIrLk2jv8HDjYyfmhABYnaJ4MR2iu8rJ3dwuXN5bzpZ+c4vAZJ4BOlqm+mPvlWpE2gDbG/C3wQfdt7PUdwO8bY95prf3RIo5NRC7CzJume6Oc7waYrMhEKFZ9sXfU2Qd9YXiSW68qVgAtImtKVYmH0sJ8zg1OMB50GpA0V3nxxDoTvNw/zmu31i7nEEVE4mYnRQAsls+995r4fHBg3Nme13E2eQZa0ku5hNsY806cgmEGeAz4HE4rq3NAOfA1Y0zRUgxSRDLj3jT9sSeO/qFARn370lVV7B0N0j8eIjQVnVOlUURktTPGsL7aaWV1fihAXVkhxZ58mqu8FObn8VKfWlmJSO5IlhSZDEcTWlBVl3goLMjj+Vjtm6YKze+ykS4D/T8AC3zYWnuP+6ExpgR4CLgBeDtw/6KOUEQylq7PabosdHOVN763byYD9IwGuTAciJ8nIrLWrK/2cm4wwGQ4gi92H8zPM2ysLeHlNAH0xawIEhG5FJm0oDLG0FhRxNmBABXFBZQWzburV2ZIV0TsWuD4zOAZwFo7AezDmVtfu4hjE5EsXWzfvr27W8ifVWXC68mnptRD72iQ80POsm0F0CKyFjkB9AT+wQC+WFGx9g4/5wYmOHi0m+vvfmTOSp+LXREkInIpMm1Bta7Ceb+uUnO7bKULoGuBIymOPRd7rVnY4YjIpbjYvn1trT4qSwoo9uQlVFvcUlcWC6CVgRaRtWtDTQmjk1OcHpigudIbD44nY7UikgXH6VYEiYgslkxbUDXGtuVp/3P20gXQBcBEsgPWWjed5VnwEYnIRbvYvn29o0EGxsP8/psv59Tdv8Khfbtoa/VRX15E75izhLuoII/qEv2VF5G1x21lFYlafNXejILji10RJCJykX3ucwAAIABJREFUKdwWVF6PE+alakE1NukUEnv0hd6kq2gkNS14F1lF2lp92KjljvueBaCxoog733LFvHvuOs4MAvCqjdUJnzeUF/HTk/2cH5qkucqLmd1MUERkDVgfa2UFzmQ0k+A4VW0JreQRkcXW1urj3588QyRque99b5hzvL3Dz2Mv9sffu6to3O9KevMF0NcYYz5xMcettX928cMSkYt1446G+O9/92uv4jVb5t9p0XF2iII8wyt8lQmf15cXMRwI83L/OM1VWuIjImuTm4EG8FV7MwqOb3/TZey9/7mE45msCBIRWQh9YyG215clPXbgYCfhiE34LJOis+KYL4B+ZewnlWuSHDc41bsVQIssg76xYPz3rgx7Nj9zepArmysonrX8u77c6VTX2TWqG6qIrFk/PN4Tn9z87j8/xS1XNPDA0/6EZdyzg+PZ91OfqnCLyBLqHwvyuq3JkyjaYnJp0gXQ/7xkoxCRBdM3Oh1Adw/PH0BPRaI8d26Y9756w5xjbgA9FbVadigia1J7h58/+uYvcHM1F4YneeBpP+++1scPj/fgH5qkrKiAT7W9IiE4vv/pczRXFtPSVE7XSJDvfuSXlucPICJrTjgSZXAiTG1pUdLj2mJyaVIG0Nba/7aUAxGRhdE3Hor/nkkGurN7lEA4QuvGqjnH6suml203q0qjiKxBqQqG/fB4L4f23cIbP/0Ir95cEw+e2zv83P3d43SNTFJeVMDkVISeDFcDiYgshMHYXLCuPHkAvXd3C3c+eCTtKhpJTUXERFYZNwNdXeKJB9DtHX4OHOzk/FCA5hnLCNs7/Hzy20cB+MvvPI+1icUj6mfcePVUUkTWovmWOtaXF9Ebu++67a3cSelocIonTw0yFbWEpqIUFqRrfiIisjB6Y9v56koLkx5353rJ5oYyv5wLoI0xvw68H7gayAeOA/8IfNFaG73Ea/8e8Pext/dYaz90KdcTyUX940EK8gyXN5bTPTw5Z0LnHwpwx72Huf3ew/E9fQDdI8E5FRhrywoxBqxFRcREZE2ab6ljfVkRp/udrp/JstVTUecu2zsWxKcHkSKyBPrH0megwZnrKWC+ODn1KNQYcw/wVeA64CfAD4DLgc8D9xtj8tN8fb5rbwI+w3S8ILIq9Y2GqCktZF1lMV0jk0kndHbWq2t2H9OHnruA27jqt77yhHoEisias3d3C95ZBcFmLnWsLy+KZ3vSFeDp1jJuEVkibkHZ2hQZaLk0ORNAG2PeDXwA6AKutta+zVr7LuAy4HngXcBFZYyN07z2Kzh/3n9ZmBGL5Kb+8SB1ZUU0VhbTMxLMuqKie76buY4lT7gwPMmdDx5JqPItIrLatbX62L9nJ74qLwanmvb+PTvjmZuG8mIGxkOEpqJpt7poH7SILBV3rpYuAy0XL5eWcN8Ze/2YtfaE+6G1ttsY837gR8A+Y8zfXcRS7vcBtwAfBmoXYrAiuap3LERtWSFNFcWEIlGaKovpyqAat8udAKYqnHN2IEBdmW7IIrJ2pFvq6NaK6B8Psnd3Cx974DmCU9PTlGJPHpPhKN0jevgoIkujfyxEYUEe5UW5FOqtHjmRgTbGrAeuBULAfbOPW2sfBfxAE/C6LK+9Bfgr4BDOUnCRVa1vNEh9WRFNFc6e5d983cY5yw9TmbksMVXmOhS5pFIEIiKrihtA944GaWv18Vuv2wQwna1u20lBntESbhFZMr1jQepKC3EW4cpCy4kAGmiNvR611qZab/rkrHPnFVu6/Q84mfbfsdZq/7OsatZa+seD1JYV0hhrO3Xlugr+ou2q+Dmzb6Xu+9nLElMtRSzMz5XbhojI8psZQANsqCkB4ImPv4lD+3bxrmvX01BepAy0iCyZ/rGQlm8volzJ62+JvZ5Oc86ZWedm4kPATcA+a23nPOeKrHjjoQiT4Sh1MzLQXcNBXrOlBoDP3PZKCvJMRm0LUvUIVDVuEZFpswNo/1CAooI86sqmi/c0VBTTM6oMtIgsjb6xIA0KoBdNxgG0MeYR4HvW2r+a57w/BN5qrd2VxTjKYq/jac4Zi72WZ3JBY8w2YD/wNE71bZFVr98tGlFWRH15EcZA18gknV2jAOxoKucVvsqM2hak6hH49SfOzPNNEZG1ww2Ue9wAejDgFBybsXSysaKIU33ppjgiIgunfyzElesqlnsYq1Y2GeibgJczOK8FuDHLcbj/yizIEusZS7cLgf9urY3M85Vk1/g94PcANm7cuBDDEll08bYFZYV48vOoLyuie3gSay15BrY3lM1zhUTJCucogBYRmVZUkE9ViSchAz17C0xjRTGPvzSwHMMTkTVmejufMtCLZTGWcBcB2Qaso7HXdLN799homnNcHwZuAP7MWvtclmMBwFr7JeBLANddd532TsuK0DcWAohXyW6qLObCyCQDEyG21JVSnGExMRERyVx9WVFCAL2rpSHheGNFMcOBMJPhCN/7RVdG22hERFJp7/CnvI8MB8KEIzZhG4ksrAUNoI0xeTjVtPuy/OrLsddNac7ZMOvcdN4Ve32zMWZ2Nnyze44x5hXAmLX2bRlcUyTn9c1Ywg3OpO1M/wSBcISdvsrlHJqIyKpVX15E71iQyXCE3tEgvurEDLS7F/Grj5/mM99/IV5bwj8U4M4HjwAoiBaRjLR3+BNq1My+j8xOpsjCSxtAx/Y9z3Rrks9mXms70Ah8I8txdMRerzLGeFNU4n71rHMz8fo0x5pjP8NZXE8kp/WNOjfNmlLnqWNTRTGHXuxjIhThV69dv5xDExFZterLi+g4M0TXsFMozJdkCTfAFx89mVCYESAQjnDgYKcCaBGZV3uHnz/4xrNEZjUWmnkfmZ1MkYU3Xwb6phm/W5w+zE3zfKcD+Fg2g7DWnjXGPAO8CrgN+JeZx2NZ5PVAF/CzDK53U6pjxpi7gE8C91hrP5TNOEVyXf94kEqvh8ICp9VUU2UxEyFnstbSlFH9PRERyVJ9WRE9o5P4h5zn/8n2QMP0NpvZzg+l6uApIuJwM8+zg2eXex/pdzPQ5VrCvVjmC6Bvjr0a4BHge8CnU5wbAvzW2outMLQfuA/4tDHmp9baFwGMMQ3AF2Ln3G2tjbpfMMZ8CKdV1RPW2v9ykf9dkVWjbyyYsOfFnbSBU4FbREQWXn15EZPhKMdjHQ/WV88OoJ1MUKW3gOHA1Jzvzw64RURmO3Cwc84Klpnc+0i8oGypMtCLJW0Aba191P3dGPMo8KOZny0ka+39xpgvAu8Hjhhj/hMIA7cAFUA78PlZX6vDqfrdtRhjEllp+sZCCVUXT/aMxX//tf/zOB/dvUPLBEVEFpjbC/rw2SHyjLP6ZyZ3ZdC1G6t59EQfkeh0BsnryWfv7pYlHa+IrDzpVqoUe/Li95G+sSDGTG/nk4WXcRExa+3N8591aay1HzDGPAZ8EKcVVj5wHKcl1RdnZp9FZK6+sSBXNDl9/9o7/PzDoVPxY+eHJlWsRkRkETSUOwHzs2eHaKwoxpOfl3DcGENjRRGlxR6KC/KIWMtkOEppUT5/0bZT92QRmVdzlTe+TWS2t13dHL+P9I2FqCkpJD/PJD1XLl3e/KcsLWvt16y111trK6y1pdbaa6219yQLnq21d1lrTbo9z2m+o/3Psur0jU4v4T5wsJPgVOJfG7fIhIiILBw3A31mYCLlcuzG8mJ+eLyH8VCE//Wea3jNlhoubyxX8CwiGdm7uwUzKyb2evKoLM7nW4f9bNn3ENff/QhHzg2pgNgiS5mBNsZ8Ivbr5621AzPeZ8Jaa//80oYmIvOZ2QdwXWUxI5NT8SXcqZb6qFiNiMjCcgNomFuBG5x79dHzwwTCzkPNsckwV/sq+dfHTxOOROdkrEVEZnvb1ev4w/sOU1SYz0QwQnOVl5t31HPvk2cJR5xtIf6hAOeHA2yvL13m0a5u6ZZw34VTefvfgYEZ79OtB3CPW0ABtMgimt0H8HysfcrZwQkg9VIfFasREVlYVV4PBXmGqaid0wN6+l49vSLok98+xq9e6yM4FeVE9xhXNlcs9ZBFZIV5sXeMqSh8Zsa2j+vvfiQePLushRM941x/9yPs3d2iVS6LIF0A/Wc4gXDfrPcikgNSVWN84OlzXL+tjr27WxICbFCxGhGRxZCXZ6grK6JrZHJOBjrZvToQjvD9Y90AHPEPKYAWkXk9d24YgJ3rK+OfpVtV6B8KqPbNIkkZQFtr70r3XkSWV6qbZtTCnQ8eYf+enezfszO+xLu5yqsnkSIii6C9w0//uNM65nM/eIGyooL4vTbVvbpnJEh5cQHPnRvmva9esqGKyAp15NwwZUUFbKmdXp6drrAYTNe+0dxvYWVchVtEcku6m6Z7wzy0b5dumiIii8hdou0uo+wfDyVkfdJtp9lUW8IR//CSjldEVqbn/MO8wldB3ozq2slWG86m2jcL76KrVhhj8owx9caYOmOMql+ILLG9u1soSNOiQDdMEZHFl2qJttvxYO/uFrye/ITj7naaYk8ez50bjlfPbe/wL9m4RWTlCE1Fef7CCK9cX5XweVurj/17diYtXuhS7ZuFl3Xga4y51RhzEBgFuoBuYNQYc9AY89aFHqCIJNfW6uNqX2XK47phiogsvvk6Hsyc4BqcKt379+wE4CcnnDIzlun9igqiRWS2F7pHCU1FE/Y/u9pafRzat4u/fu81KR/WycLKagm3Meavgf/JdCVut6SkF3gz8CZjzD3W2g8v3BBFJJVw1NLSWMaZgYCKhYmILINMOh60tfrmbKdJVj03EI5w17ePqnaFiMS1d/i569tHAfjz/zjGVMQmvSe4n+n+sfgyDqCNMb8NfBgn8/w54F+BM7HDG4HfBO4APmiM6bDW/uPCDlVEZrLWcqpvnHe/ysf7b6rWDVNEZBlcbMeDVJnroUCYoUAYUBVdkbVudsvS7pFg2ntCsod1svCyyUB/CJgC3mStfXLWsZPAnxpjvgMcAj4AKIAWWSDtHf45AfL12+sYC06xua5UN0wRkWVysVmf+arnugLhCLffe5gDBzv1cFRkjUlXY0H3guWTTQB9BfBokuA5zlr7pDHmUeANlzwyEQHmPn10MxK/+0tbANhSV5ru6yIissgu5iFmJtVzZ1I2WmTtcBMnqR6yqVDs8sqmiNgE0JPBeb2A/l8VWSCpnj7+689OA7C1rmw5hiUiIpfALS5W6XVyGU2VxVSXeNJ+Z2Z1bxFZndzESboVKioUu7yyyUAfAl5tjDHWWpvsBGOMAa6LnSsiCyDdPjlPvqG5qniJRyQiIguhrdVHbVkhv/WVJ/hf73klPSNB9j34HJPhaMrvKPMksjrNl3V2qVDs8ssmA/1JYD3wWWPMnEekxpgC4DOxcz65MMMTkVRPGYs9eWysKaEgX23YRURWqssaygF4sWeMtlYfd7zpsrTnK/MksvpkknWG6TZ42saxvFJmoI0x/yXJx/8EfAS4zRhzH3Aq9vlm4DbAB/xv4Grg8EIOVGSt2ru7hY898BzBqemMhNeTT6W3QPufRURWuMaKIsqLCzjRPQZAU6UTIH/01hb+7uEX1aJQZA1Itl1vNl+Vl0P7di3RiCSddEu4/wlItlTb4ATKH0nyOcD7Yj//cqmDExFnid/Tpwf418edrnF5Bv6i7RXs++YRBdAiIiucMYbLGsp4oXsUgGPnRyjMz+N//NJWmiu9/NX3jnN+eJKyogI+1fYKZZ5EVqH5tmbo4VluSRdA/wvJA2gRWWIRC+VFBfzx267gYw8coay4gNBUlC0qICYisuJd1lDOfz7fDcCxCyNc3lSGJz8vXt37//vSzxgJTCl4Flml0rW182XYGk+WTsoA2lr720s4DhFJ48lTA1y7uZpdOxqBI3zlMWf3xOa6kuUdmIiIXLLLGsu496mz9I8FOXZ+hFuuaEg4/sbtdXzm+y8wMB6iprRwmUYpIoslWVs7rydf+51zlKoPieS4gfEQJ3rGePXmGurLi3jlhip+fmoAUAsrEZHV4LJGp5DYYy/20T8e4qrmyoTj12+vA+CnJ/uWfGwisvjctnaFscKwKhaW2xRAi+S4J192guXXbqkBYF3FdNuqd3/xEO0d/mUZl4iILIzLGpyHod86fB6AK5srEo7v9FVSXlzAoRcVQIusBu0dfq6/+xG27HuI6+9+hPYOP22tPqpKPNx27XoO7dul4DmHZdwHOkVV7pSstSoiJrIAnjg1QFFBHjvXV9Le4eeHnT3xY/6hSe588AiAbrQiIivUuspiyooK+PELvQDsaCpPOF6Qn8emmhK+8dQ5/v2JszRrT6TIiuW2rHKXa/uHAtz54BHCkSg9o0HWV2t7Xq7LOIAmdVXu2UzsPAXQIpegvcPPgYOd+IcCFObn8d0jXRw42JnQzgogEI5w4GCnJlIiIiuUMYbtDWUcPjvE5toSyos9CcfbO/x0do8SiTrTMHfCDXp4KrLSJGtZ5c7lADbUqNd7rssmgE5VlTsP2AS8CigF2oHhSx+ayNo1++lkKBKdU1xipvnaH4iISG4rzHe6gb7cP8H1dz+SkGE+cLCTcCRxCqaHpyIrU6o5W89oEEAZ6BUg4wB6vqrcxpgGnCB7O/CGSxuWyNqW6ulkvjFE7NznWM1VelopIrJStXf4eebMUPz97Axzqgm3Hp6KrDypWlZVeT0MBcKsr9acLtctWBExa20P8OuAD7hroa4rshalmhRFrMXryU/4zOvJZ+/ulqUYloiILIIDBzuZiibPMEPqh6R6eCqy8uzd3YIntuLE5fXkc+3majz5hsYZxWIlNy1oFW5r7QDwJPDuhbyuyFqTalLktjXwVXkxqM2BiMhqMF+Gee/uFj08FVkl2lp9vGFrbfx9ldfD/j07KSksoLnKS36eSfNtyQXZ7IHOVAhYtwjXFVkz9u5uYd+DzzEZni4Y5k6W2lp9CphFRFaRVEs63Yep7j3/T9p/wWhwiubKYj566w79WyCyQk1ORblmQxUv9ozxjmuaaWv18c8/e1nLt1eIBc1AG2OagOuB3oW8rsha09bq473XbQBQpllEZJXLJMPc1urjU+96BQD/9N9fo38PRFYoay3HLoxwVXMFLU3lHO8aBeDcYID1VSogthJk0wf6hjSHy4AdwAeBKuDrlzgukTXFbVl1figQ7+8ZiljKiwro+MSbKchf0GddIiKSQ2ZW257578DsIHlrXRkAL/WOcXlj+ZzriEjuOzcYYHRyiiubK7DAfzx7nkAoQu9oUBnoFSKbJdw/Yv4+0AboAP74YgckstbMblnlVl/1Fubx2q21Cp5FRNaATLbnbK0vBeBk7/hSDElEFsHR8yMAXNVcSSRq+drPp3j69CAAG2qUgV4Jsgmgf0zqADoE+IGHgW9Ya8OXOjCRtSJVy6pAOMIbt9em+JaIiKw1pUUFrKss5mTPGJB89ZKWdovktmMXRsgz0NJYTjA2//vP57sBlIFeIbLpA33TIo5DZM2YPeFJVjjG9YUfnaSqpFATIhERAWBbfRkne8dSrl4C9G+GSA47dn6ErfVleAvz2dFUAcDDx90AWhnolUBrQ0WWkDvh8Q8FsJA2eAboGQ1y54NHaO/wL80ARUQkp22tL+Vk7zgHDh5PunrJ7R0tIrnp+VgBMYDKEg9NFcWcHQhQmJ9HQ3nRMo9OMpF1GytjjAFqYt8d0HJtkcwlW649H3dCpIyCiIhsqy9jLDjFeHAq6fFUPaVFZOkk214B8OnvHefC8CSjx8O0d/hpa/WxY105XSOT+Kq95KkH9IqQUQbaGFNjjPkTY8yTQBDoAc4DE8aYI8aYTxlj1PtZZB4XO7HRhEhERMAJoAFqywqTHrfA9Xc/opVLIssk2WrDvfc9y977n+XC8CQAI5NT8RWGbsx8qm9cf3dXiHkz0MaYdwFfASpxqmzPlA9cBVwJfMQY82Fr7T/O+K4BrrHWdizckEVWhmRPH+fb85xKc5WKSoiICGxrcCpx39TSwIPPnCOapLyr9kOLLJ9kqw3DSf6iBsIR7vr2UcZD06tJ9Hd3ZUibgTbG3Abch9Pb+RfAXuAm4AqcoPkm4KPAUaAU+LIx5n/EvusB7gXevjhDF8ldyZ4+3vngEW7eUU9BmuU5VV4PXk9+wmdeT3586Y+IiKxtTRXFlBTmMxIIE7VQXpw8F6L90CLLI5tVg0OBMOFIYnCtv7u5L2UAbYypx8k8A3zEWvtKa+1nrbU/ttZ2WmuPx37/jLX2auAOnJVDf2OM2QF8C3g38/eOFll1UrWm+uHxXq5YVz5nKQc4gfJd77iK/Xt24qvyYgBflZf9e3bqKaSIiADwrcPnCUeifP+YU7X39jddlvTfFND2H5HlsBCrBvV3N7elW8L9P4EyYJ+19u/mu5C19m+MMcXAfuApoAQ4AfzDQgxUZCVJdeM7PxSgrKiAW65o5G1Xr0vZv1MBs4iIzOaubpqZsfrMwReoKvEwODG3pqu2/4gsvb27W9h7/7MJf089eYYoEJmxlNvryafYk6e/uytQugD6LUA/8NksrvdZnGXeNTjLut9kre2++OGJrEyp9jqvqyrmVP84N1xeR1urT4GyiIhkLNXqpqKCPLye/IRj6bb/JKvRoX+PRBZGW6uPf3v8ZZ45M0TUQmF+Hn/1q1dzzw9PcKpvgkjUJlTmntnPHbR1byVItwd6K/Aza23GPXestVPAT3GWbd+o4FnWqr27W5LuZf7dN24hNBVlS13ZMo1MRERWqlSrm4YDYfbv2UmV1wNAY0VRyu0/qWp0qPKvyMIZC0a48fJ6/vCXLycUiXJZYxkne8d5343bOHX3r3Bo3654IkVb91aedBnoUmD0Iq45CkxZawcubkgiK19bq4/QVISPPuBUUiwpzOcv37WTurIiALbUlS7n8EREZAVKtbqpucpLW6uPDTVe3v3Fn7F/z0527WhMeo1UWewDBzs1aRfJULpVHJPhCC/2jHHLFQ28Zec6PvP9F3jn5w8RtXDvU2fZ3lCW8HdNKxJXnnQZ6D5g80VccxPQe1GjEVlFXrmhGoA8Q/xmeapvDFAALSIi2Uu1usld7rm9oRyAF7rHUl4jXY0OEZnffKs4TnSPMRW1XNVcyZFzwxhgKrb3uXc0qBUfq0C6APpp4DXGmI2ZXswYswl4bey7ImvamYEJAK7bXMPxrlHCkSin+ibwevJprCha5tGJiMhKM99yz0qvh8aKIk6kCaBTFSdS0SKRzKRbxQFw7MIwAFeuq+DAwc457YjUpmrlS7eE2+3h/A/GmLdaa0PpLmSMKcSpuJ0X+67ImuYG0Lde1cQTpwZ4qXecU31jbK4rxZjUvaBFRERSmW+552UN5bzYk3oH3t7dLfzhfc/GM2KgokUi2ZhvFcfR8yOUFRWwsaZEKz5WqXQZ6K8DzwA3A48aY16V6kRjzLXAj4GbgMOx74qsaWcHJigrKuCNl9UBzhPJU33jbNXybRERWSTbG8o40TOGtbPzXo62Vh/bGqYLWapokUh25lvFcez8CFesKycvz2jFxyqVMoC2zp23DTiDsyz7SWPMc8aYLxtj/iL282VjzC+AJ4DXAGeBd9pUd22RNeTswAQbakrYWldKUUEez54d5uxggM11Jcs9NBERWaUuayxjIhRJWmzMNTThLCosKcznsY/drOBZJAt7d7eQP2slobuKIxq1PH9hhCvXVcTPTVe3QFamdEu4sdaei2WevwDcBrwi9jMzQDZAFLgP+KC1tn+RxiqyopwZmGBrfSkF+XnsaCrn+0e7iEStWliJiMiiubzRKSR2omeM9dVzH9gOTYToHgmyrrKYC8OTDE6EqSktXOphiqxYba0+/uI7x+gddR5E+Wb0dH793Q8zHorwrcPnad1YHX84pb7rq0vaABrAWjsI/Jox5uPA24BrgfrY4T6cgmH/Ya09uWijFMkR6doWzGSt5czABDe1OH9Vrmyu4OtPnAVUgVtERBbP9nrnIe2L3WPc3NIw5/jxLmd/9C1XNPBvj5/h7MCEAmiRLAxNhOgdDVFYkEeegcc+djPfOnyeOx88Ei8uNhQIc+eDTitTtalafdLtgU5grX3JWvu31tr/aq19a+znv1hr/0bBs6wF87UtmKl3NEhwKsqGGufpfzgyvWjjQ197Ru0LRERkUVSXFlJXVsQL3ckLiXXGA2inT/S5QRUzEslGx9khAHa1NDAZjtI3Fpq3MresLhkH0CJrXTY3R7cC94aaEto7/PzfZ8/Hj10YnlQPQBERWTTVJQW0H/azZd9DXH/3Iwn/3hzvGqWqxMO1m6oBODc4sVzDFFmROk4PkmfgrVevA5y/Q6q2vbYogBbJUDY3x7OxCcnGmhIOHOwkOBVNOK6nkiIishjaO/y81DdBOGKTrpY63jVCS2M5FcUeKr0eZaBFstRxdoiWpgpaYvUGzg0GVG17jVEALZKhbG6OZ/oDGOMUltBTSRERWSoHDnYSiSY2QwmEI/zBN57lm0+f44WuUXY0ORP/DTVeZaBFshCNWg6fGaJ1YxXrq53537nBAHt3t1DsSQyrVG179VIALZKhbFoRnBmYoKmimGJPvp5KiojIkkn1cDZiLfu+eYTxUISWJqfFzvqqEs4qAy2SkfYOP6/b/zCjwSm+c+QCPzjWTU1pIWcHJ2hr9fF7N2yNn6v+6qubAmiRDLW1+ti/Zyee/Onef598+xVJb45nBybYEGsfoh6AIiKyVNI9nHW3E7XEMtDrq50MtLU25XdEZLqQbM9oEIChCafKdmlhfnwbRH1ZEQA/3beLQ/t2KXhexRRAi2ShrdVHbWkRm2ud4LjSm7z1x5mBiXgFbjfw9lV5MeippIiILJ5kD21nc7tBrK/2MhmO0j8eWqLRiaxMqQrJ9o4F49sgjneNUl5cwLrK4uUYoiyheftAi8i0qUiUntFJ3nfjNr768zM8fLyHt+xcFz/e3uHnr753nK6RSb5/rIv2jrp4/z8FzCIistg8iCa2AAAgAElEQVTcf2v+4BvPEkmRWXa7QfzGazcCzh7Oulj2TETmSrU1YjIcxT8YwFpLZ6y+gDEm6bmyeigDLZKF3rEgUQvrq0u44fJ6ftTZQzRWrMVd3nN+eBKA0ckptasSEZEl19bq47PveWXaTHQgHOHbsRaLKiQma1V7h5/r734kacu3mVJtjaj0eghORekZDdLZPRrfHiGrmzLQIlm4EAuO11UWU+HNp28sxLY/+g7NVV4mQlMp+0Qr+ywiIkvJ/XfnwMFO/CmyZ72x/ZxnB1RITNYeN/Hhzt3clm+uAwc7OT/ktKi6eUc99z91jskZbUm9nnzee916vvSTUzxxaoDRyal4gT5Z3ZSBFsnChSEngD52YYQHnnaeUrp9Ngcnwkm/o3ZVIiKyHNpafRzatwtfmm4Q1SUeZaBlTUq1r/mubx/lzgeP4B8KxOd4Dzzt58bL6+LnufVsbrtuAwAPP98NEG8RJ6ubMtAiWbgw7ATD//b4aSbD0XnOdqhdlYiILKe9u1sSMm0w3Q3iK4+dilcRFllLUiU4hgJzEyKBcISfvzwIwA//8Ca21JUCMBGacj7r7AXQEu41QhlokSx0DU9S7MmjK7aUez5qVyUiIsstVTcIgBM9ozz6Qm/a/Z8iq1G2CY6hiTB5hoQVHSWFBdSWFjIcCOOr8lJR7FnoYUoOUgZaJAsXRiZprvQSnIom3VNW5fUwMhkmap0b7N7dLdr/LCIiy252Nwh3/6e7mso/FOCOew9z+72H9e+XrAl7d7fwsQeei/dHByfxUezJS7otz+vJp668kMKCxPzj+poS+sdDyj6vIcpAi2Sha3iSpsripH02vZ58PnprC1ELf/TWHRzat0uTDxERyUnJ9n+6Ta/cYkrKSMtq1tbq47++YVP8fXlxAfv37OSTb7+KvFmdqLyefOrKCtlcW5rweXuHnxe6RgB44tSA/s6sEQqgRbLgBtDucrh1lcXA9E3Xrb64rb5sOYcpIiKS1nwFLt0uEiKrWUO5M4+rLvFww2X1tLX6eOc1zRTmT0fQzVXF7N+zk5HJKTbWlMQ/n67i7WSwx4JqX7pW5FwAbYz5dWPMT4wxw8aYMWPMU8aYDxpjMh6rMSbPGPMGY8ynYtc6Z4wJGWO6jTHfMca0LeafQVanSNTSNTIZD5rbWn387M5b2FRbEr/pvtQ7BsBWBdAiIpLDMtn/qS4Sstq91DdOVYmHazdVc6JnFHBalk5OWV65vhKAr/7u67ippZ7hQDghA52qircePK1+ORVAG2PuAb4KXAf8BPgBcDnweeB+Y0x+mq/PtBU4BHwcuBI4CjwInAbeAnzTGPOPxhiT+hIiifrGgkSilqbKxElHS2M5z8eW75zsHceTb9hQrcrbIiKSu5JtRZrNgoqLyap2smeMbfVlXNZYzqm+ccKRKJ1dTiD9jmucbXidXSOc7ndavW2qnc5Ap3rApAdPq1/OFBEzxrwb+ADQBdxgrT0R+7wR+CHwLuBDwN9kcDkLPAIcAH5grY0/HjLG3Ag8BPw28GPgHxfuTyGrSXuHnwMHOzk/FKC5yst7Xr0egOZYBtq1o6mc/3y+m8lwhJO9Y2yuLaUgP6eeTYmIiCRwa3QcONiJfyiAYXoP9EzufuiZ3xFZLU72jrNrRz2XN5YRjlhO949zPBZAv+3qdXzqoWMc7xqNFxrbNCMD3VzlTVpQVu1LV79cmuXfGXv9mBs8A1hru4H3x97uy2Qpt7X2pLX2Fmvt92YGz7FjjwJ3x97+5gKMW1Yhd1+LfyiAxZlA3PPIiwA0zQqgW5oqiFp4sWeMk71j2v8sIiIrQlurj0P7dvHy3b/C5957TUJ7npm0LFVWo+GJMH1jQScD3eBU0D7RPUZn1wjrKotprChmc20pnV2jnIlloGfugU5VUFbtS1e/nAigjTHrgWuBEHDf7OOxoNcPNAGvW4D/ZEfsdf0CXEtWoWT7WkIR59n8utlLuGNtC37hH+ZM/wTbGhIrNIqIiOQ6N5hOtbfNPxTQcm5ZVU72OXVrttWXsa2+DGPghe4xjneNxud2LY3ldHaN8nL/BI0VRXgLpwPmVP3VtVJj9cuVJdytsdej1tpUGweeBHyxc396if+9y2KvFy7xOrJKpdu/Ul3iSXi/ubaEooI8fnCsm6moZWudMtAiIrIypVqWClrOLavLS73jAGytL8VbmM/6ai/PXxjhZO8YN7bUA06S5OCxLkqK8hOWb7tm91eXtSEnMtDAltjr6TTnnJl17kUxxpQAH469feBSriWrV6r9K/l5htm15wry87issYyfnOgDYFuDAmgREVmZ5isupuXcslqc7B1zCr/GlmVf3lDOj0/0Eo5YdsQy0DuayrEWfuEfYfOMAmKytuVKAO1GHONpzhmLvZZf4n/rCzhB+DHgS5d4LVml9u5uIW/WOjZjSHnzbGmsIBRxCkxsrdcSbhERWZlmLktNRVWGZTU42TPGptpSPLHCr9sby5gIOdv3djRVOK/rKuLnJ8tAy9qUKwG0G6okKwC5cP8RY/4E+K/AMPAea20wzbm/F+tB/VRvb+9iDkty0Ft3rsOTZyiZsdfFWqdaY7I9YFOx4BngLX/9E+0RExGRFcvdD50qiFaVYVkNnMKv00HxSCAc//13/ulJ2jv8dJwejH/25Z+8pPmdALmzB3o09ppu7at7bDTNOSkZY34f+DOcTPZbrLVH051vrf0SsQz1ddddt6iBveSeJ18eIBix/J/faGU0EOYP7ns2/nRn9h6w9g4/3/1FV/y72iMmIiKrwd7dLdz54JGEopqqMiwrXXuHn786eJzzQ5N0jwTjQfGDz0wHx+eHJ9l737PMrKo3OBHW/E6A3MlAvxx73ZTmnA2zzs2YMeZ/Ap8FAsDbrLU/y/YasrY8cryHwoI8rt9ey2d/8MKcpREz94AdONgZX76d7LiIiMhK5C7n9uQ7UYSqDMtK57YpPT80CcBYcIo7HzzCn/7fo/Fez65w1BKOJM4ANb8TyJ0MtNtW6ipjjDdFJe5Xzzo3I8aYDwJ/C0wC74i1xBJJqr3Dz4GDnfiHAhQV5PH9o90p93q5n893XEREZKVqa/Vx8GgXL3SP8vAf3LTcwxG5JMnalAbCkTmfpaP5neREBtpaexZ4BigEbpt93BhzI07P5i4g4+yxMeZ9wOeBINBmrf3PBRmwrEruU0m3fUdwKsqdDx6halbbKpe7ByzVXjDtERP5f+3de5yddX3g8c93JpNkQkIm4Z4JlyCYKEYJIFqjINA2imhTkNr7bbvdrdJV1CjWtVLbbqLYaq2V1t1at+sNAYlaVvEC6qKiEBNEMBHlmoEQLpkkJJPJXH77x3nO5MyZ55w5M5mZc87M5/16Pa+H89zyzPn9+J3n+/xukqaDpYva2b6rh5Ts0abmNhHBr893aogAOrM+W78/Ik4rboyIYymMnA2wIaU0WLLviojYGhH/Xn6xiPjP2Xm9wKUppVsm79Y1HVR6K5kSI6b0KO0Dljflh33EJEnTxdJF8+jtH+SpZw/W+1akcdu4uYuWsqlIizra20Y8y7W1xFD3hSKf7wSN04SblNINEXEt8GfAPRHxDaAPuAg4EthIoTa51NHAcgo100Mi4kzgXyh0/X8Q+I2I+I2cf/aplNLbJ/QPUdOq9FZyd08fH3rDmVxzyzYe6+5hSUc769YsH+oDVlxX2i9JUjNbuqhQ47Z9136OWTCnzncjjV2xleFATiuK9rZWrn7dGcDIZ7m8bT7fqWECaICU0hsj4nbgTcD5QCuwFfgEcG1p7fMoOjg0bt6KbMnzMGAALaDQJKcrJ4he0tHO2lWdVQvM0fZLktSsli6aB8Cju3pYddKiOt+NNHZ5rQwBWiOGDYyX9yzn853KNVITbgBSSp9JKa1OKR2ZUjoipXR2Sumf8oLnlNLVKaVIKb2ybPu3su2jLadM1d+lxrduzXLmtg3/X8KmOpKkma60BlpqRpVaGQ6mZICsMWu4AFqql7WrOrniwqHu907XIUkScMScWSw+Yjbbdzn6sJqTA75qIjVUE26p3pYsLBSkX7/yPE4/bkGd70aSpMZQHIlbakbr1izn7dffTf/goT7QtjLUeBlAa8YqzvlcOjDE1h17md3awilHH1Hv25MkqWEsXdTO1sf31vs2pIrynutK+zZ//Du/4GdPPMvAYHJAMB0WA2jNSMXRGIsDSnR19/CuL9zDSUfN4znHzqet1d4NkiQVLV00j2/8dCeDg4mWlvypgKR6qfRcB4cGAdvd08/FK0/gI7+1qm73qenBKEEzUqU5n+9/Yi8rjrfptiRJpU5c1M7B/kGeera33rcijVDpue6aW7YBsPdAH13dPSz3GU8TwABaM1Ll0RgxgJYkqUzpVFZSo6n0XFfc/rMnCt0PfMbTRDCA1oxUbdRF305KkjTceKey2ri5i9UbbmXZVTezesOtbNzcNRm3pxlutFG2f5r13/cZTxPBPtCakdatWc66G+6mb+DQaIxtrUHfQGLF8UfW8c4kSWo8nUMBdM+wwZoWtrcRAd37+0YMzFRLv1RpIqxbs5wrP7+FdOixbtgo29t27GXBnFl0Om2VJoA10JqR1q7q5CXLFlMcBmV2awvnnLyIhe1tHHfknLremyRJjeZr9z5BSxT6ml553Ra6untIQHdPH7v295E4FCAXa5lH65cqTZRfef5xkKA4vt1xR85h/aUrh17UbNuxl+cev4AIB8DT4TOA1ox1cCBx1smLeO0LT+DgwCDff+AZeg4O8MUtj9X71iRJahjFmuTiFLqpyrGlAfJo/VKlifKjR3aRgPe+9gwA/vzC04eC55QSW3fssfm2JowBtGaklBLbduxl9qzg6/c9MbT94MDgsLfnkiTNdHk1ydUUA+QTFs7N3V9tHBJpPO588BlaAi47eylLFs7le794amjfjj0H2HOgn+cZQGuCGEBrRnpiTy+7e/q477G9HOgfHLbP5mWSJB0ynhrjVe/7Go/tPjBie2m/VGmi/ODBZ3hB50Lmz5nF6tOO5nu/eJrBrMnE1h3FAcQc40YTwwBaM9LWHXsA2NPTl7vf5mWSJBWMtcY4Abv2j/x97eyYO6xfqjQRevsH2PJoNy8+ZTEAq087mu79fdz3+B42bu7izZ/dDMCbP7fZFoaaEI7CrRlpW/Y28viFc3k85w25zcskSSpYt2b5sNG0AYJCoNzR3saeA31D/aOr2fiml3PMAgfq1MS6Z/tuevsHOXdZIYDec+AgAJf84+1D+RTg8d0HHAVeE8IaaM1IW3fs5fgj5/LOV62gva112D6bl0mSdMjaVZ2sv3QlnR3tBNDZ0c6H3nAmD214DVve+6vDpg6q5pFnxjaHtDSajZu7+ONP3gnA1V+6l/++8R7W/99D3fDKs6bd9DQRrIHWjLR1x16WH79g6A1kcT7L8jksJUlSIYiu9Nu4pKOdrhq6Pm3ftZ+zT1400bemGap8nvHHdx/g03c8UnWUeLCbng6fAbSa0sbNXeMOevsGBvnFzmc57/SjgeoPBZIkqbq8Jt6l5ra1cKBvkEeetgZaEydvdPhaGkPYTU+HyybcajrFN45d3T0koKu7Z0xTTz301D4ODgw6H6AkSROgvIl3R3sbi+a1DTX33nDpCzl2wRybcGtCjacm2W56mgjWQKvp5L1xLPZpyatJLq2tXtjeRt9AYdqq9V/ZSkuEtc+SJB2m0VpzfeqOhw2gNaFO6JjLY90jB4ItHTis9HOn3fQ0QQyg1XQqvXHM217eP6a7ZNqqJ/f2OhqjJElT4KTF87jjgaeBw+uGJRW9+gUn8K+3PzhsW3tbK5ed3cltW580f2nSGECr6VQarCSvT0tebXWpajXXkiRpYpy4eB43benihrse5T1fvHfot7nYDQt8ma3aFF/AdHX3FLoMzGuje3+fwbKmjH2g1XTWrVk+YuqpWS2R26ellv4xjsYoSdLkOmnxPFKCa75WuRuWNJrScXCg0DT7QN8gH3rDmXz3qgsNnjUlDKDVdNau6uRdFx8KlttaoH8wceV1W1i94dahwcQ2bu6iJUa/nqMxSpI0uU46ah4AT+zpzd3vy2zVoto4ONJUsQm3mtLSRYUf4j+/8DQ+/p0HYHBw2Ijcdz38DDdu6mJglPkMHI1RkqTJd2L2u72wvY3dJeORFPkyW7UYyzg40mSxBlpN6cfbdxMBN2zaTm//4LB9PX0DfPYHj+b2fQ4YNrXG+ktX2txHkqRJduyCOcye1cJZJ3Uwq6x5mC+zVWrj5i5Wb7iVZVfdPKxlIVR+0eILGE0la6DVlO7ZvpvTjpnPz3c+m7t/IFWuet78l786WbclSZJytLQEJy5qZ86sVo6eP5tn9vVxMJtW8h2vcuAnFZTPntLV3cOV123hLddtobOjnQtWHMPnfvgo/YOHnvN8AaOpZg20mk5KiR937Wbl0oUV3zi2Rn7nZ99QSpJUHyctnscPHnyaHXt6+YuLV/CNt54HQFurj6MqyOvjXAyVu7p7uHFTFwvmtDK7tcXWhKoba6DVdJ7Y08uTe3t5YedCzjv9mGFvKqHwJnLtqiV89oePDjvPN5SSJNVP/8Agu/YX+j//87cfYGF7Gycubue2rTv53ZeeXOe7UyMYrS9zT98APX2FGVnedMFpU3RX0nC+8lPT+fH2bgBWLu1g7apO1l+6ks6SmuX3XPI8LnnhEgAWHzHbN5SSJNXZxs1d3PHgM0Ofd+w5wF/c9BPmzWrhm1t35vZ31cxTa0vBC1ccO8l3IlVmDbQa3sbNXVxzyzYe6+5hYXsbB7La5j//zI94x6tWsHZVJ2tXdbLp4V1cdu33mD+3jW/+dCezZ7Vw+zsvYN5ss7kkSfV0zS3b6CubGqOnb4BtO/cBDJtJA/CF9wy1bs1y3vb5u6uOZQOw9fE9PO+EI6forqThrIFWQysOJtHV3UMCunv6OJCNuv3Y7gO86wv3DL2tPvPEDhYfMZvbtu7ktm07+aVTjzJ4liSpAdQ6zVBP3wBvuW6LtdEz1OtetIT22S20txVClPwRbeAvbvqJ+UN1YwCthpY3mESpnr4BrrllGwCtLcGpR8/jps1dPPjUPrY82m3hKklSAxjrIJ7F2mh/x2eWnzy2m2d7B/gfl67koQ2v4UNvODN3YNjS5z9pqhlAq6HV8sa6eMzGzV3cvX330PbdPX3++EqS1ADWrVlOe1vrsG2VaheLDJJmnm/+dCcRcP5zC32c167qZLBCc+5aWzVIE832rWoopf2dl3S00zGvbWjEzkqKb7Ur9a+65pZt9qWSJKmOir/Dpb/xF6w4hhs3dVVtaWaQNDMUn/+6untoaw2+87Mnh/LMko52unLygVOTql4MoNUwiv2diz+kXd09tLUELQGDFcaSKJ2aqtKPrD++kiTVX3HQz1LnnLx4KHDK0xLBxs1dI84rf+G+bs1yX5Y3mFrTqPz5r28gDRtMbt2a5blTljo1qerFAFoNI6+/c18WObe3tXCgb5CF7W1EQPf+vhGFsW8oJUlqLsWgujyIKhpIh4IpYCjYDgojd4OjdzeivEqRSmmU9/xX2oIwr/WCL0xUTwbQahjVaoo/ePmZvOaFJ1Q93zeUkiQ1p2IwlDeFUU/fAFd/6V56+weHfuPLG6bZZauxjBYUl6qlBWFe6wWpXhxETA2jWk3xvt7q/aChULiuv3QlnR3tBNDZ0c76S1da4EqS1ASqDRjV3dNXta802GWrkVRKi67unhFTlFV6/rMFoRqVNdBqGOvWLOft199Nf06H5/d+6T5mz2odNRj2DaUkSc2rUnesWs9VY6iWjuXNufOe/2xBqEZmDbQaxtpVnazsXJi7z6ksJEma/vKmu5rb1sKieW1VzzPgaix56Viq9Lnu185cwsL2Wcye1WILQjUFa6BVF5VGZuwbHKx4jk2zJEma3koHjCrWYP7hy07huccu4K3X3517zvFHzuWqV68w4Goga1d1MjA4yNuu/3HFYx7r7mHj5i7+5ub7eHpfH4vmtfHey15oOqrhGUBrylUamTGlxENP7eeIOa3s6x3Zz8mmWZIkTX/F7lgH+gY4+6+/zu6ePhbPnw3A4nlt7Mpm4rj8nKV8+Bv385evfT4XrzzBqa0azMqlHQAsytKs3ML2tmHPg7v29zmaupqCAbSmXKWRGd//1W0829vPpWd18pV7djiatiRJM9jctlaee9wCrrvzUT77w0eJgL+4+Hm8/pwTAegbGORfvv0AP3zwGQ72D9Y8bZKmxtYdewH4k1ecykdv/fmw57q5bS1EUPNI3VIjsQ+0plylpthP7DkAwK+d6WjakiTNdBs3d3HvY7spji2VErzni/cOjeDc1trCWSd38MMHn6k6bZLqY9uOPbS2BH/yimVDz3VFLRG5tdJglz01PmugNeUqjcy4sL2N7p4+Tj36CE587jEGzJIkzWDX3LKNgwMj54QuraE895Sj+PA3fzZyYuiMwdjUyGs+v23HXk49+gjmZLOorF3VyU2btvPW6+9m/8HKU5LZZU+NzhpoTbl1a5bT1hrDtrW3tXLWyR3Mbm2x4JQkSRWD39LtvQMDpFQxfvaZYgoUx7bp6u4hcaj5/KaHd7H8+AXDjv3g139WMa3ALntqDtZAa8qtXdXJv97+APc+tofBBHNmtbD+0pV85SePc9JR82htidEvIkmSprVKLdaKQfHGzV184vYHK57f3tbKBSuOYfWGWx1YbAKV1zbvP9if23y+p2+AFWUBdLUWAZ2mj5qENdCacvt6+/nZE8/y+790Cr/30pOZ1RJc8sITePCpfSw7+oh6354kSWoAeXMJl9ZQXnPLNg705U9/eeTcWVx2dic3buoaUTNa7EOtscurba7Ulxlg+fFHDvtcqUVAZ0c7373qQoNnNQUDaE2ZjZu7WL3hVs547y309g8yf04rL162mH0HB/jJY3t46On9BtCSJAkotFirNqhotdrMs05exG1bn8ytGX3LdVtYveFWA+lxyBusrZryGujRXopIzcAm3JoS5XM/A/zr7Q/yzlevAOCLW7o42D9oAC1JkoYUB5/KU6mJ97zZrdz10C729fZXvK7TXI1PrYOytbYEswKWLhpe41z8rp2vW83MGmhNifzpJQb5n995kJOPmsdN2VvgU44ygJYkSaOrVJt52VmdPNvbz9EL5lQ932muxu7YI6t/p0UDg4negcTL33/biJr+tas6+e5VF/LghtfYbFtNyRpoTYlqI2ledvZSbti0HYBTjzGAliRJo6tUm3nussX8nzse4eXPOYr/uOdx+gYqj/vsNFeVlQ4WtrC9jQiq9ncuagmG5u62pl/TkQG0pkS1kTRnlUxpdenHvsu6NSssZCVJ0qgqNfE+cXE7PX2DHLtgDk/s6aV/MD+IdpqrfOVd77p7Rg+cAVojGEjV5+6Wmp0BtCZF+RQHF6w4hhs3baenZLTM4vQS19+1fWhbV/cB31RKkqTDctyCOXz13h0AdLS3ccmLTuDGTV3DupM5eFVltQwWFgyff7u9rbXiOdb0azqxD7QmXN4UBzdu6uKVy48ZOqY4kuZtW5+kt3/4FBT2SZIkSeO1cXMXd2/fPfS5u6ePGzd1cdnZnXSW1Dj/5Wuf58v6CmoJeBOMGCG9s0KNvjX9mk6sgdaEyx8wbIDbf/40EXDXu3+Zo+YXBqG48rotudfwTaUkSRqPa27ZNqLfc0/fALdtfZLvXnUhmx/Zxa9/7HsU6lBHtppzVGhY0jGXru4DVY8pzt1crnzWFWv6Nd0YQGvCVQp+9x7o56yTOoaCZ6jeN1qSJGmsqg1cCnDmiR0cu2AO7/3ivbzrC/cMa4pcHPTqroef4batT07roDrvxQEUXkCMFjxXCoqdpkozgQG0JkyxIK481iVcuOLYYZ/XrVnum0pJkjRhRns5/8Utj/HMvoNDA4uVP7f09A3w6TseGRZUX3ndFt5y3RY6p0lAWD5IWFd3D+uuvxuCYbX3xZcLHdko3N37+0YNiqvN3S1NBwbQmhDlBXEl//v7D7N00byhgtU3lZIkaSKN9nL+mlu2VRyVu6h8b3kNNTT3YKd53e36cr6TYj/nvKba0kxlAK1cY+0PVMtojQBP7u0d8cPjm0pJkjRRRns5f7jjrPT0DXD1l+5t6pf/Y/kOHJdGGs4AWiPkNet5y3Vb+Ksv38t7X3tG7g/EWApX5wOUJEmTqdrL+UpNvMeiu6dvaG7kZqyVHst34Lg00nBOY6URKtUm79rfx5XXbeGUq25m9YZb2bi5CygE3C0xtn/Dt5mSJKke1q1ZTntb64Res9Gn4Ny4uYvVG25lWfYMd8GKY4iyZ7dZLYzY5rg00kjWQGuEasFt3iiVN27qYiCnK1F7Wytz21rYtb9vxD7fZkqSpHrIa+K9/2B/7vMKMGyU7moatXIgr2Xh9XdtJyU4cu4s9h7oJwGtLS309w8O/b3TZcA0aaIZQGuE4xfO5fHd1acvgMLb1k/d8UjuvtYI1l+6EnA+QEmS1FjKm3gvu+rm3OMC+NAbzuRtn7+bgTT6wGNn/tXXah6teqrktSzs7R8E4EtXvJwtj3bz1s9vGdqWOPSsVu97lxqRTbg1pNi8p5bgeTSDKQ39OK2/dCWdHe0EhbeZ6y9daYEsSZIaRqWWcUs62lm7qpPBUYLnou6ePnbt7yNxaAyZVe/72lC3t8lQ3jy7tIvd6g23Vu3rvOXRbq65ZRvlA3A3epN0qZ4argY6In4b+DPghUArsBX4N+DalNLgOK73KuCtwDnAXOAB4LPAB1NKvRN1342q1tG0a52GqlalP0SOsi1JkhrZaFNfHc7AY7v29w0NMgaFGuGu7h5aIxhIaUxzLJfLa55dnLO6lqbn1Z79GrVJulRvDRVAR8Q/AW8EDgDfBPqAi4CPAhdFxOUppZojvIh4B/B+YAD4FrALOB/4G+CSiLgopbR/Qv+IBpJXqFYrwPN0tLdxxJxZdE71l0gAABL9SURBVHX31NwHyCbakiSpmYw29VWlALvWioeevoERQW3x2as4mjfkP6uV3k/5tv0H+0fcQypbj3ZflZ4DHa9GytcwAXREXEYheN4BnJdSuj/bfhxwG/DrwBXAP9R4vXOADcB+4MKU0g+y7fOBm4HzgL8FrpzYv6R+ymub8wrV4tyFvf2DQ/uq9enZ3dPHlvf+6rDrV3sD64ATkiSpGVVrMVcpwB7tuahcrUFt+bNasTl4qcOdiqtoIKURLwOsDJEqa5gAGnhXtn5nMXgGSCk9ERF/RqEG+aqI+Mcam3JfRWHsh/cXg+fses9GxB8B9wNvjIi/Sil1T9hfMcVKg9rSt5rVCtXSN52jyWuKndfcu72t1b7NkiRp2qoUYE9kF7iisTyrHa7OkpcBo3X5k9QgAXRELAXOBg4C15fvTyl9OyK6gE7gpcD3RrnebODV2cdP51zvgYj4PrAauBj4zGH9AXVSHsjWNrxF7Sq9fRytmZMkSdJMUP5MtLC9jYP9A+zvG/OwPZOurSUgoK9k7tHS0bZ9jpNq0xABNLAqW9+bUqpUdXonhQB6FaME0MByYB7wTErpF1Wutzq7XlMG0HnTEkyU0ZpiW9BKkiTlPxPV0u1tKpTP6QxWgEiHq1EC6GXZ+uEqxxQnHF5W5Zjy6+VPUjz26zWkyRgd0abYkiRJh6dat7diUFs+Cveu/YffbLs4+Gu1ANlnPOnwNEoAPT9b76tyzLPZekEdrteQxjKlQrWRtov7HABMkiRp4oyl29uyq26uqTteMQAvnx2lva2Vq193hs9x0iRrlAA6svVEdeM97OtFxJ8Cfwpw0kknTcQ9Tbi8KRXytLe1ctnZndy4qcuBvyRJkqZQrd3eKlWMVKpVLp99xUoQaWo0SgC9N1vPr3JMcd/eKsdM2PVSSh8HPg5wzjnnTPT4XBOi0lvNvG1rV3VyzsmLLWglSZIaUKW5pivVKjsejVQfjRJAP5StT65yzIllx9ZyvWpVx2O5XsOqVHha0EqSJDUPZzmRmkOjBNCbs/UZEdFeYSTuF5cdW81WoAdYHBHPqTAS97ljuJ4kSZI0qazskBpfS71vACCl9CjwI2A2cHn5/og4H1gK7AC+X8P1DgJfyT7+Ts71TgV+icK80zeP+8YlSZIkSTNGQwTQmfXZ+v0RcVpxY0QcC3ws+7ghpTRYsu+KiNgaEf+ec70NFAYRe2dEnFtyznzgExT+9o+llLon+O+QJEmSJE1DDRNAp5RuAK4FjgfuiYgvR8QXgPuB5wMbgY+WnXY0sJycvs4ppTuBq4B5wPci4msR8XngF8D5wA+Ad0/SnyNJkiRJmmYapQ80ACmlN0bE7cCbKAS5rRT6M38CuLa09rnG630gIn4MvI1CH+q5wAPAR4APppR6J/L+JUmSJEnTV0MF0AAppc8An6nx2KuBq0c55qvAVw/7xiRJkiRJM1rDNOGWJEmSJKmRGUBLkiRJklQDA2hJkiRJkmpgAC1JkiRJUg0MoCVJkiRJqoEBtCRJkiRJNTCAliRJkiSpBgbQkiRJkiTVwABakiRJkqQaGEBLkiRJklSDSCnV+x4aXkQ8CTxc7/sYxdHAU/W+CTUs84cqMW+oGvOHqjF/qBrzhypp1LxxckrpmNEOMoCeJiLirpTSOfW+DzUm84cqMW+oGvOHqjF/qBrzhypp9rxhE25JkiRJkmpgAC1JkiRJUg0MoKePj9f7BtTQzB+qxLyhaswfqsb8oWrMH6qkqfOGfaAlSZIkSaqBNdCSJEmSJNXAALqJRcRvR8T/i4jdEfFsRNwVEW+KCNO1SUTEJyMiVVm2VjivJUvru7K0353lhd+q4d8cV76JiFdFxNci4pmI2B8RP4mId0fEnPH+/YKIWB4Rb46IT0XE1ogYzNL+9TWcO6VpGREviYibImJnRByIiPsj4gMRsbCGv/FTEfFYRPRGxMMRcW1EnDDa3zjTjSd/jLdcyc61bGkCEdEWERdFxN9FxB0R8XhEHIyIroi4ISJeOcr5lh3T2Hjzh2XHzBERfx4Rn4+In0bE0xHRFxFPRsQ3IuJ3IyIqnNc06TzecqcmKSWXJlyAfwIS0AP8B3ATsCfb9gWgtd736FJTOn4yS7Pbs/8uX9bnnNMKfDE7b3eW3jcDB7JtH5nofAO8IzumH/gGcD2wM9v2fWBevb/LZl2AD2ffY/ny+lHOm9K0BH4rO6eYX68DHs4+3w8cW+G884H92XGbgM8BP80+7wSeW+80aORlPPljPOVKdp5lS5MswC+X5IXHs+/8OuCeku3va4S0suxonvxh2TFzFmA7cBD4EfDl7P+v7wOD2Xe4EWhp1nQeb7lT8/dX7wR0GUeiwWUlheLpJduPA+7L9r253vfpUlNaFn+s/nAM57wtO+de4LiS7acDO7J9vzZR+QY4JytQ9wEvKdk+H/h2dt6H6v1dNusC/AnwAeA3gOcA32L0AGlK0xJYSuFBdqA0bwGzsh/dBNyUc94R2T0m4IqyfR/k0INx1DsdGnUZZ/4Yc7mSnWfZ0iQLcCFwA/CKnH1v4NCD4wX1TCvLjqbLH5YdM2QBXg4ckbP9jJI0+6NmTOfxljtj+v7qnYAu40g0uCtL/N/P2Xd+SSZtmep7cxlzWo7px4rC278nsnPOy9n/B9m+H05Uvsl+hBPwlznnnZoVUL1AR72/z+mwUFuANKVpyaEH1k/knHckhTfRCXh+2b4rsu235ZzXCvw8239xvb/3ZllqzB9jKldK0sOyZZoswP/Kvtt/rWdaWXY05lIlf1h2uAC8J/t+P9OM6Tzecmcsi31lm0xELAXOptDs4vry/SmlbwNdwPHAS6f27jQFfgk4FtieUvpOzv7rgT7gxRHRWdw43nwTEbOBV2cfP51z3gMUmtDMBi4e35+ksahTWq6tct4eCs2/So8rP+9TOecNUHgTnHeepp5ly/SyOVsvLW6w7FCJEfnjMFh2TD/92fpAybZmSufxljs1M4BuPquy9b0ppZ4Kx9xZdqwa3wUR8fcR8fGI+OuIWFNhUIVimt6Zs4+U0n4KTWsAzsw5b6z5ZjkwD3gmpfSLMZynyTOlaRkRR1JoOly6v5Z/r/TzWM/TxKi1XAHLlunm9Gz9eMk2yw4V5eWPUpYdM1RELAP+a/bxyyW7miKdD7Pcqdms8Z6oulmWrR+ucswjZceq8f1+zrb7IuI3U0r3lGyrNf3PZHj6jzffLCvbV+t5mjxTnZanZOvu7M1tTedlP2KLR7lX887kqrVcAcuWaSMijgf+MPt4Y8kuyw5Vyx+lLDtmiIj4IwrNqNsotEh4GYUK1vUppZtKDm2WdD4lW4+p3Bkra6Cbz/xsva/KMc9m6wWTfC86fFuA/0Zh0Ib5wBLgEuBu4PnAN0qbwjD+9J/q8zR5miUPzC/570rnmncmx1jLFWiefKUqImIWhWbPC4FvppRKa5CaJY0tOybJKPkDLDtmotUU+i//NnBetu09wPvKjmuWdJ6S/GEA3XyK87Klut6FJkRK6cMppX9MKd2XUtqXUno8pXQzcC5wB4X+Ju8qOWW86T/V52nyNEseyJ1DUpNvHOUKNE++UnX/DFwEPAr8btm+Zkljy47JUy1/WHbMQCmlP0kpBYXm0mdQmDrxauCOiFhScmizpPOU5A8D6OazN1vPr3JMcd/eKseogaWUDgLrs4+lgyOMN/2n+jxNnmbJA6X/fcQYztMkqVKuQPPkK1UQEf8A/CcK08lclFLaUXZIs6SxZcckqCF/VGTZMf2llHqyFyfrKLwkeRHw0ZJDmiWdpyR/GEA3n4ey9clVjjmx7Fg1p63ZurS51EPZeqzpf7jnnTTG8zR5HsrWU5WWxf/uyPom1nRe1vfomexjpXs170y9vHIFLFuaWkT8HYWmt09SCI7uzznsoWxt2THD1Jg/RmPZMXP8W7Z+bUS0Zf/9ULZu9HQu/veYyp2xMoBuPsWpB86IiPYKx7y47Fg1p6Oy9bMl236UrV9MjoiYB7wg+1ia/uPNN1uBHmBxRDxn5ClAoWlX+XmaPFOaltnDbHEEzNx8l3de2eexnqfJk1eugGVL04qIDwBvBZ4GfiWldF+FQy07ZqAx5I/RWHbMHN0UprKaxaEB/ZoinQ+z3KmZAXSTSSk9SiETzwYuL98fEedTGEVvB4X50dS8fiNblw7D/31gJ7A0Is4beQqXUxhJ8c6UUldx43jzTdZs6yvZx9/JOe9UCnMDHgRurvUP0/jVKS2/WOW8I4HXZh9vKttd7bxW4DcrnKfJk1eugGVLU4qIDcA6YBeF4OjuSsdadsw8Y8kfNbDsmDnOoxA8dwNPZduaKZ3HW+7ULqXk0mQL8HoKneMfB04r2X4shTnYEvDmet+ny6jpeCaF0S1by7bPovC2eCBLyzVl+9+ebb8XOLZk++lZnkjAr01UvqHwBm+QwoiG55Zsnw98KzvvQ/X+PqfLUvKdvr7KMVOalhSaO+3P8uTryvLqZ7Pzbso5b35JnnxT2b5rsu0/AqLe33uzLKPlj/GWK9kxli1NtAB/nX1Hu4CzazzHsmOGLGPNH5YdM2cBXkEhuJyTs281hRrcBHywGdN5vOXOmL7DeieiyzgTDj6WZYAeChOdfwHYXcwU5QWgS+MtwNosvZ6m8NbteuCrQFe2fQB4R855rcCXsmN2Z2n/5SwvJOAjE51vgHdkx/QDXwM+DzyRbbsDmFfv77NZF+Cs7DssLnuy7/VnpdvrnZbAb2XnDALfAT5Hof9QAu6n5Me07Lzzsx+yBNyV/Xjdl31+Elhe7zRo5GWs+WO85Up2rmVLkyzA67LvKFGoEfxkheWqeqeVZUdz5A/LjpmzUJgHvPhy5ZvAp7P0KwazCfgPoL1Z03m85U7N32G9E9HlMBKvMGfbdyk8UO0DNgFvAlrqfW8uNaXfMgrTBXwv+4E6kBUs9wOfoMobYwrdL67I0nxflgduB357svIN8Crg61mB25MVtO8m5w2my5jywStLfrAqLo2QlsBLgI0UHl57gZ8DHwAWjnLe8uwHekd23iMUplM5od7ff6MvY80fh1OuZOdbtjTBwqEH4NGWbzVCWll2NH7+sOyYOUuW1u8DbqMwpVlPlt4PATcAa6dDOo+33KlliewfkCRJkiRJVTiImCRJkiRJNTCAliRJkiSpBgbQkiRJkiTVwABakiRJkqQaGEBLkiRJklQDA2hJkiRJkmpgAC1JkiRJUg0MoCVJmgYi4lcj4t8iYltE7I6IgxHxZER8NyKuiYhzJ+jf+cOISBHxyYm4niRJzWRWvW9AkiSNX0QcB3wOeGW26RfAt4BngaOAVcDLgLdHxKdSSr9Xh9uUJGlaiJRSve9BkiSNQ0QsBu4ETgW+C1yRUtpSdkxQCKDfCSxJKZ1zmP/mQuAEYHdK6fHDuZYkSc3GAFqSpCYVEZ8D3gDcDlyUUjo4yvHnppR+OCU3J0nSNGQfaEmSmlBEnA5cnn1842jBM0B58BwRL8n6R98VEU9k/aYfi4gbIuKlFf7d3D7QEfHKbPu3IqItIt4dEVsj4kBE7IyIT0XESeP8cyVJaggG0JIkNafXUPgdvzuldM84r/G3wJVAG/BD4EvA08BlwO0RcXmVcytpA74CXAX8PPvvQeB3smt2jPNeJUmqOwNoSZKa09nZ+q7DuMYHgc6U0otSSq9NKb0+pbQSeB2FoPefI2LeGK/5MmAh8JyU0iUppV8HlgM/Ak4E3nQY9ytJUl0ZQEuS1JyOztZP5u3MprX6ZM5ySvGYlNJXU0pPlJ+bUvoycD2wGLhgjPeVgD9OKe0sud5u4P3Zx4vGeD1JkhqG01hJkjQ9PR/4g5ztHwUeKn6IiKOBS4AXAB0cejZ4QbZ+LnDzGP7dRyo0Kd+arZeM4VqSJDUUA2hJkprTU9n6mLydKaUPAx8ufo6Ih4CTS4+JiP8C/D1QrZn2kWO8r0cqbN+TreeO8XqSJDUMm3BLktScfpStxzWvc0ScA1xLYdCvdcAKYD7QklIKYH3x0DFeenA89yNJUjMwgJYkqTndTKG/8YsiYuU4zn89heD4IymlD6aUtqWU9qWUUrb/tIm6UUmSpgsDaEmSmlBK6WfADdnHayNi9hgvsThbP1q+IyKOAX7lMG5PkqRpyQBakqTm9UYKA4KtBr4ZEWfmHRQRqxnZl7k4qNfvR8T8kmMXAJ+gMKCYJEkq4SBikiQ1qZTSUxHxMuDzwMuBzRHxc+BeYB+FAcaeA5yanXIr8HD23/8GvAU4C3ggIm6n0KT7POAghSD6j6foT5EkqSlYAy1JUhNLKT2eUnoFcDHw79nmi4DLgVXATuBDwEtSShellJ7MzttFYQCyjwPPAq/JPn+BQlA9omm3JEkzXRwaK0SSJEmSJFViDbQkSZIkSTUwgJYkSZIkqQYG0JIkSZIk1cAAWpIkSZKkGhhAS5IkSZJUAwNoSZIkSZJqYAAtSZIkSVINDKAlSZIkSaqBAbQkSZIkSTUwgJYkSZIkqQb/H9not7/144fiAAAAAElFTkSuQmCC\n", - "text/plain": [ - "" - ] - }, - "metadata": {}, - "output_type": "display_data" - } - ], - "source": [ - "expt_cfg={\n", - " \"start\":0, \"step\":100, \"expts\":300, \"reps\": 400\n", - " }\n", - "config={**hw_cfg,**readout_cfg,**qubit_cfg,**expt_cfg} #combine configs\n", - "\n", - "rabi=AmplitudeRabiProgram(soccfg, config)\n", - "x_pts, avgi, avgq = rabi.acquire(soc,threshold=readout_cfg[\"threshold\"], load_pulses=True,progress=True, debug=False)\n", - "\n", - "subplot(111, title= f\"Amplitude Rabi, $\\sigma={soccfg.cycles2us(config['sigma'], gen_ch=2)*1000}$ ns\", xlabel=\"Gain\", ylabel=\"Qubit Population\" )\n", - "plot(x_pts,avgi[0][0],'o-')\n", - "\n", - "axvline(qubit_cfg[\"pi_gain\"])\n", - "axvline(qubit_cfg[\"pi2_gain\"]);" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "# T1 \n", - "\n", - "Measures the qubit T1 characteristic decay time by preparing the qubit in its excited state with a $\\pi$ pulse followed by a variable delay ($\\tau$) before measuring the qubit's state. This exponential decay curve can be fitted in post-processing to obtain the qubit T1 time." - ] - }, - { - "cell_type": "code", - "execution_count": 15, - "metadata": { - "ExecuteTime": { - "end_time": "2021-09-30T07:36:04.818431Z", - "start_time": "2021-09-30T07:36:04.656319Z" - } - }, - "outputs": [], - "source": [ - "class T1Program(RAveragerProgram):\n", - " def initialize(self):\n", - " cfg=self.cfg\n", - " \n", - " self.q_rp=self.ch_page(cfg[\"qubit_ch\"]) # get register page for qubit_ch\n", - " self.r_wait = 3\n", - " self.regwi(self.q_rp, self.r_wait, cfg[\"start\"])\n", - "\n", - " self.declare_gen(ch=cfg[\"res_ch\"], nqz=1) #Readout\n", - " self.declare_gen(ch=cfg[\"qubit_ch\"], nqz=2) #Qubit\n", - " for ch in [0,1]: #configure the readout lengths and downconversion frequencies\n", - " self.declare_readout(ch=ch, length=cfg[\"readout_length\"],\n", - " freq=cfg[\"f_res\"], gen_ch=cfg[\"res_ch\"])\n", - " \n", - " f_res=self.freq2reg(cfg[\"f_res\"], gen_ch=cfg[\"res_ch\"], ro_ch=0) # conver f_res to dac register value\n", - " f_ge=self.freq2reg(cfg[\"f_ge\"], gen_ch=cfg[\"qubit_ch\"])\n", - "\n", - " # add qubit and readout pulses to respective channels\n", - " self.add_gauss(ch=cfg[\"qubit_ch\"], name=\"qubit\", sigma=cfg[\"sigma\"], length=cfg[\"sigma\"]*4)\n", - " self.set_pulse_registers(ch=cfg[\"qubit_ch\"], style=\"arb\", freq=f_ge, phase=0, gain=cfg[\"pi_gain\"], \n", - " waveform=\"qubit\")\n", - " self.set_pulse_registers(ch=cfg[\"res_ch\"], style=\"const\", freq=f_res, phase=cfg[\"res_phase\"], gain=cfg[\"res_gain\"], \n", - " length=cfg[\"readout_length\"])\n", - "\n", - " self.sync_all(self.us2cycles(500))\n", - " \n", - " def body(self):\n", - " self.pulse(ch=self.cfg[\"qubit_ch\"]) #play probe pulse\n", - " self.sync_all()\n", - " self.sync(self.q_rp,self.r_wait)\n", - "\n", - " #trigger measurement, play measurement pulse, wait for qubit to relax\n", - " self.measure(pulse_ch=self.cfg[\"res_ch\"], \n", - " adcs=[0,1],\n", - " adc_trig_offset=self.cfg[\"adc_trig_offset\"],\n", - " wait=True,\n", - " syncdelay=self.us2cycles(self.cfg[\"relax_delay\"]))\n", - " \n", - " def update(self):\n", - " self.mathi(self.q_rp, self.r_wait, self.r_wait, '+', self.us2cycles(self.cfg[\"step\"])) # update frequency list index" - ] - }, - { - "cell_type": "code", - "execution_count": 16, - "metadata": { - "ExecuteTime": { - "end_time": "2021-09-30T07:38:38.583856Z", - "start_time": "2021-09-30T07:36:04.826941Z" - } - }, - "outputs": [ - { - "data": { - "application/vnd.jupyter.widget-view+json": { - "model_id": "4e007504ecae469196e6228bcd82bd6d", - "version_major": 2, - "version_minor": 0 - }, - "text/plain": [ - "HBox(children=(IntProgress(value=0, max=160000), HTML(value='')))" - ] - }, - "metadata": {}, - "output_type": "display_data" - }, - { - "name": "stdout", - "output_type": "stream", - "text": [ - "\n" - ] - }, - { - "data": { - "image/png": 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ERGTmFKArzKaOdhpqq3nb1/by73/6fNaf3jTXQxIREREREakImsJdgVoawgAcHx6b45GIiIiIiIhUDgXoCtTa6AXoE0PxOR6JiIiIiIhI5VCArkBBBbpHFWgREREREZGyUYCuQI211YRDVfQMqwItIiIiIiJSLgrQFcjMWN4YpkdTuEVERERERMpGAbpCtTSEOaEKtIiIiIiISNkoQFeo5Y219AxpDbSIiIiIiEi5KEBXqOUNYa2BFhERERERKSMF6Aq1vEFroEVERERERMpJAbpCtTSGiSWSjMTH53ooIiIiIiIiFUEBukK1NtQCqAotIiIiIiJSJgrQFaqlIQygTtwiIiIiIiJlogBdoZY3KkCLiIiIiIiUkwJ0hVruT+E+rq2sREREREREykIBukKpAi0iIiIiIlJeCtAVqj4cora6SntBi4iIiIiIlIkCdIUyM1oba9WFW0REREREpEyq53oAMjs6u6I8OzjK9+57hrv393Dl+Su47ZFjHOqL0dYcYcvGdWzqaJ/rYYqIiIiIiCwYCtAVqLMryrZd+0gkHQDRvhjfuPvp9PVoX4xtu/YBKESLiIiIiIgUSVO4K9DO3d3EEsmC98QSSXbu7j5FIxIREREREVn4FKAr0KG+WFnvExEREREREQXoitTWHCnrfSIiIiIiIqIAXZG2bFxHpCZU8J5ITYgtG9edohGJiIiIiIgsfArQFWhTRzvbN6+nPaPCfHpzHVXm/bk+HGL75vVqICYiIiIiIlICBegKtamjnTu3XsXbXroWgGf6RqmtDrFmeT3r25sUnkVEREREREqkbawqWGdXlK/ffSB9HEskOdgb49jg2ByOSkREREREZGFSBbqC7dzdzWgiNelcMuUYjifpHY7P0ahEREREREQWJgXoClZom6rHjw2dwpGIiIiIiIgsfArQFazQNlWPP6sALSIiIiIiUgoF6AqWazurGv9/8W279rFhxx46u6JzMDIREREREZGFR03EKljQaXvn7m4O9cVoitQwHB8HHADRvhjbdu2bdK+IiIiIiIjkpgp0hQu2s3pyxzU01FaTSLpJ12OJJDt3d8/R6ERERERERBYOBehFJF9TsULNxkRERERERMSjAL2I5GsqVqjZmIiIiIiIiHgUoBeRXE3FIjUhtmxcN0cjEhERERERWTjURGwRyWwqFu2LEakJsX3zejUQExERERERKYIq0ItM0FTsynUrOLOlXuFZRERERESkSArQi9TF7U08fmyI0URyrociIiIiIiKyIChAL1IXtS0lmXI8cmRwrociIiIiIiKyIChAL1IXtTUB8NCh/jkeiYiIiIiIyMKgAL1I7X3qBAZ88PsPsmHHHjq7ojnv6+yKsmHHHtZuvaXgfSIiIiIiIpVOXbgXoc6uKB/4/oM4/zjaF2Pbrn0Ak5qKdXZF2bZrHzF/nXS++0RERERERBYDVaAXoZ27u9OhOBBLJNm5u3tG94mIiIiIiCwGCtCL0KG+WFHni71PRERERERkMVCAXoTamiNFnS/2PhERERERkcVg3gVoM3ujmd1hZv1mNmRme83sXWZW8ljNbJmZfcLM9pnZsJmNmdkBM/u6mV06G+NfCLZsXEekJjTpXKQmxJaN62Z0n4iIiIiIyGIwrwK0mX0W+CZwOXAH8FPgPOAzwE1mFirw9uxnnQncD2wDTgNuA24GEsAfA/eY2XVl/QILxKaOdrZvXs/KJbUAtNTXsH3z+imNwYL7ghAdqrKc94mIiIiIiCwG8yZA+2H2ncAR4BLn3LXOudcBzwEeBl4HvLuER+4AzgR+BJzlP+/1eIH8o3gdyL9gZjVl/BoLxqaOdn747pcA8L6N6/KG4k0d7Vy+ZhkAKed41UWrTtkYRURERERE5pN5E6DxKsUA73fOPRacdM4dBd7hH24tYSr3lf7rx5xzIxnPSwEfA2LAcryAvigta/B+d3BiKF7wvmODY4RDVTgHjx0dOhVDExERERERmXfmRYA2s9OBy4A48N3s6865nwNRvKnYLyrysWNF3ne8yPsqTm11iMbaak6MFA7QPcNxOs5sBqD76OCpGJqIiIiIiMi8My8CNNDhvz7knMu3R9I9WfdO53/81w+ZWX1w0swM+AgQAX7onHu21MFWkpaGMCeG8wfoVMpxYjjO885aRl1NFd1HFKBFRERERGRxqp7rAfjW+q8HCtzzdNa90/kQXti+BjhgZnfjVaWfC5wFfANvzfWiNl2A7oslSKYcR/tjJFOOL//ySf7nwSNsKbBuWkREREREpBLNlwp0o/86XOCeYPHtkmIe6Jw7DlwFfBVoBa4FrgPOBfYDP3fO5S2nmtnb/S209h47dqyYj1yQpgvQPUPeTPibf3uYRNIBEO2LsW3XPjq7oqdkjCIiIiIiIvPBfAnQ5r+6sj3Q7HygC9gI/AmwGmgGrsYL6l8ys//I937n3Bedc5c75y5fsWJFuYY170wXoI/5AToIz4FYIsnO3d2zOjYREREREZH5ZL4E6KAS3FjgnuDatItwzawa+B5etXmzc+4bzrkjzrl+59we4JXAUeAtZnZloWdVuiBAO5f7dxc9BTp0H+rLt1xdRERERESk8syXAP2U/3pWgXvOyLq3kBcCFwJPOufuyr7onDsB/Ng/fEVxQ6xMLQ1hxsZTjMSTOa8fH8rfzLytOTJbwxIREREREZl35kuA7vJfLzKzfKns+Vn3FnKm/9pf4J4+/7WliOdVrJaGMEDeadw9Q3EMiNRM/qcSqQmxZeO62R6eiIiIiIjIvDEvArRz7iBwHxAGrs++bmZXAKcDR4ApFeUcDvmv55tZc557gv2knyxttJWlpb5wgD4+NEbrklq2b76E9oyK89++Wl24RURERERkcZkXAdq33X+90czODU6a2Urgc/7hDudcKuPau83sETP7Wtaz7sIL0RHgy2a2NOM9VWb2IbwAPY63VnrRammcLkDHWd4QZlNHO3duvYqfvPdlgFeBFhERERERWUzmyz7QOOduMrPPA+8A9pnZz4AEXtfspUAn8Jmst7UC6/Aq05nPipvZm4EfAJuBK8zsHiAGXIq3l3QKeI9z7olZ+1ILQDEV6BVLatPHz1nZyNK6aj5680Ns27WPtuaI9oQWEREREZFFYd4EaADn3DvN7JfAu4ArgBDwCPAfwOczq89FPOunZvZc4K/x9oN+uf+8I8C3gU875+4u7zdYeKarQPcMj7FmeX36+Af3H2J4LEnSTd4TGlCIFhERERGRijavAjSAc+5bwLeKvPcG4IYC1x/Dq2hLHktqq6kJGSdG8lSgB+Msb5yoQO/c3Z0Oz4FgT2gFaBERERERqWTzaQ20zAEzY1l9mBM59nseiY8TSyRpzQjQ+fZ+1p7QIiIiIiJS6RSghZaGMD1ZU7g7u6Jc+Y+3A/CFXzxBZ1cUyL/3s/aEFhERERGRSqcALbQ0hOnNmMLd2RVl2659HB0YA6BvJMG2Xfvo7IqyZeO6KR24tSe0iIiIiIgsBgrQi1xnV5Sup3u590AvG3bsobMrys7d3cQSyUn3Za5z3r55PXXV3j+d9uYI2zev1/pnERERERGpePOuiZicOkGlOZbwmpsHHbWzw3MgWOe8qaOdhw7189W7DnDH315JVZWdsjGLiIiIiIjMFVWgF7F8leaQ5Q7Emeuc17Y2Eh9PcahfzcNERERERGRxUIBexPJ1zk46N+0657WtDQA8eXx49gYoIiIiIiIyjyhAL2L5OmcH65obwqFJx5nrnM9e4QXopxSgRURERERkkVCAXsQKddTe1NHO1Res4qzl9dy59aopTcJWLqmlPhxivwK0iIiIiIgsEmoitogFoXjn7m6ifTFqq6smVZr7YwmaIjU532tmrG1t0BRuERERERFZNFSBXuQ2dbRz59areMPlZ1AfDvHaS9vS1woFaICakHHHY8dZu/WW9BZYIiIiIiIilUoBWgC4uH0pvSMJDvePps8NxBIszROgO7uiPBgdIJlyOCa2wFKIFhERERGRSqUALQBc2NYEwIPR/vS5QhXonbu7GU+5SediiSQ7d3fP3iBFRERERETmkAK0AHDB6iWYwUOHBgBwzhUM0Pm2wMp3XkREREREZKFTgBYAfvLQUUJmfPrWx9iwYw/fuecg4ymXN0Dn2wIr33kREREREZGFTgFa6OyKsm3XvvSU7GhfjI/88CEAmvMEaG8LrMn/fIItsERERERERCqRtrESdu7uJpZITjo3Np4CyFuBDra62nLTAySSjvbmSHr/aBERERERkUqkAC0F1y0X2sZqU0c7P334KA9F+7l9y5WzMTQREREREZF5QwFaaGuOEM0TovNtYxU4q6We3Q8eYTyZojo0P1YEdHZF2bm7m0N9MdpUGRcRERERkTKZH4lH5pS3njk06VxNyIDCFWiANcsbGE85DvWNFrzvVAnWc0f7YtqfWkREREREykoBWtjU0c72zetpa64DoLG2mmvWrwagqb5wgD5zeT0AB04Mz+4gi5RrPbf2pxYRERERkXJQgBbAC9G/2no1Z7REuOr8lZzRUk+VQWO48Cz/s/wA/VTPyIw/u7MryoYde1i79RY27NhzUtVi7U8tIiIiIiKzRQFaJlndFOFwf4z+WIKlkRqqqqzg/auW1FFbXcXTPTOrQJd7yrX2pxYRERERkdmiAC2TtDdHONQ3Sn8sMe36Z4CqKuPMlnoO5KhAF1NZLveU61zrubU/tYiIiIiIlIO6cMskq5vqODowSu9IcQEavGnc2QE6qCwH4TioLAOTOmKXe8p19v7UrY1hPnTNherCLSIiIiIiJ00VaJlkdXOE8ZTjiWeHig7QifEUjx4dnFRpLrayPBtTrjd1tLNqqdcQbfvmSxSeRURERESkLBSgZZK2Ji94Rvti0+4BDV6l+Vf7e3AwaQ1zvn2lsyvLWzauo65m8j/Dcky57o8lAOgdjp/Uc0RERERERAIK0DLJ6qaJym8xFeidu7tJJN2kc9mV50zZleVNHe185NoL08ftzRG2b15/UlXjZMoxODoOQO+IArSIiIiIiJSHArRMEuwFDcUF6FLXKo/Ex6c0E3vZeSsAeMGaFu7cetVJT7keHE2k/3xCAVpERERERMpkRk3EzOx0oA2oy3ePc+4XMx2UzJ2mSA2RmhCxRLKoAN3WHMk7XTuX3pHElGZiI3GvYj06nr9yXYpg+jZoCreIiIiIiJRPSRVoM9tsZt3AAeAu4LY8P3vKPE45RcyM1X4VupgAnWvbqOlkNxMbHvOmW48WmPpdiswAfWI4UeBOERERERGR4hVdgTaz3wW+gxe6+4H9wMAsjUvmUFtThP3HhosK0EEV+X3feYCkc9PcPSFz6vfwmBecx8ZTJY40tyBAh6ur6NMUbhERERERKZNSpnB/ADDgQ8BO55xKexWosyvKfU/3AvCRHzxIfDw17Zrk4Hrmvs+BupoqRhNTg3FmM7HheHkr0H0j3j/Ns1rqtQZaRERERETKppQp3JcAXc65Tyg8V6bOrijbdu1Lr0k+PhRn2659U5p+5bKpo53tm9eztM77nUxrYxiA37/8jClTvLO3qRpJB+jyVqDXtDZoDbSIiIiIiJRNKQE6AXRPe5csWDt3d0+pIGevVy5kU0c7n//jywB45YWnAV6A3r55PSHz7sm1TdWQP4W73Gugz25toC+WIJkqfmq5iIiIiIhIPqVM4b4XOHu2BiJzL9+WVKVsVbX+9CbM4JbfHgJgbWsDF7c38dnbHuecFY38259cNuU9I34TsbHxFM45zGwGo58wEEsQrq7itKY6nPOOlzWET+qZIiIiIiIipVSgdwAvMLNXztZgZG5lrksu5nwuS+tqOGdFIwOj46xcUktDrfc7moba6vRa52zD8YnKczkaifXHEjRFamjxQ7PWQYuIiIiISDmUEqC7gY8DPzSzG83sZWa2xszOzPUzS+OVWZRrS6rs9crFaKn3unc/OzjGhh176OyK0lhbzdBYngCdcX6sDOuggwC9rN4L0FoHLSIiIiIi5VDKFO6nAIfXiftv/J98XInPlnkgWJe8c3c3h/pitDVH2LJx3bRduDN1dkXpOtiXPo72xdi2ax/nrmzIW10eyahMj44naWL67bMKmVKBVoAWEREREZEyKCWS7WiIAAAgAElEQVTkPo0XjKWCbepoLykwZ9u5u5tEcvI/k1giyePPDqcDbbZgH2goTyOx/liCVUvraPYr4cG2ViIiIiIiIiej6ADtnFszi+OQCpGv4VgskSxqCvdoIkVnV/SkquD9sQTnrVqiNdAiIiIiIlJWmmYtZdXWHCGaI0Q31lYzPDaes8t2ZnOx3Q8d5vO3709vpxVMAQeKDtHBFO5ITYja6iqtgRYRERERkbIopYmYyLTyNSK74rxWxlMu5zro4bEk4ZD3T/Frdx04qb2okynH4Og4SyM1mBktDWGtgRYRERERkbIouQJtZq3A24CXA0FJMArcBnzZOXesbKOTBSdfI7K+kTi37DvC8Ng4dVkBezg+TktDmCMDoxwfyh12i92LenDUW+/cFPHWPzfXh+nVGmgRERERESmDkgK0mf0O8E2gCa8bd+BC4BXAFjP7Y+fcj8s3RFlocjUi++7eg4BXbV7eOPn+kbEkyxu9AJ2vYlzsXtT9sYkA3dkVZf+xIR4+PMCGHXtKXkstIiIiIiKSqegp3GZ2PvA9oBn4DfAXwCuBVwF/DvwaWAbc5N8rktZY6/2uJlcjseGx8XTDr2suWX1Se1EHAfrhwwNs27UvPWU8WEvd2RWd8XcQEREREZHFrZQ10FuBOmCLc+7/OOe+6Jy71Tn3M+fcl5xzL8bbGzoCvH82BisLV4MfoDMbhgE459JTuAHWtzfx8U0Xpa+3N0fYvnl9SQ3EAH5wf3TatdSdXVE27NjD2q23sGHHHoVrEREREREpqJQp3FcBDzrn/infDc65fzazNwNXn+zApLI05KlAj42nSDlY3lDrHSeSbLy0HfgtAD/f8nKqQ8X/nicI0D3TrKXu7Iqybde+k+r2LSIiIiIii0spFehVBKmmsH3AypkNRypVMIV7OCtAB4F6eaNXgR4bT026pz+WKLpS3NkV5UPffxCArJ2y0oK11Dt3d59Ut28REREREVl8SqlADzDRdbuQNmBwZsORStVQ661rzg7QI2NeiA2mcI8mkpPuueneZ/jUzx6btlKcXVFOualjyFxLna+rd7HdvkVEREREZPEppQK9F3iJmW3Id4OZvRh4KXDPyQ5MKstEE7HJVd9gTXRzpIYqg9FEatI07y/dsb+oSnGuijJAlV+JXrW0dtJa6nxdvYvt9i0iIiIiIotPKRXozwAbgR+b2aeArwIHAAesAf4UeA/e9lafKe8wZaFryJjC3dkVTe8THUzdbqitpq4m5FegJ4JwsftC56scB5Xor7zlBVywemn6/JaN6yZVrKG0bt8iIiIiIrL4FF2Bds7dAtwINAIfBB4FYsCo/+cPAUuAG51zPyr/UGUhqwlVEa6u4v6ne9m2ax/RvhiOiYB874ET1FZXMTqenFSBbq6vyfm87Epxvsrxcn9q+EhW9+9NHe1s37w+XRlvaQiX1O1bREREREQWn1KmcOOc2wZcC9wOxIGQ/xMHbgOudc59oMxjlArRWFvN3U+eyDnV+r9+c9CvQE9uIvay57QSqZn8zzRXpXjLxnU594/+4xedCTCpqh3Y1NHO9ZefDsAHX3OBwrOIiIiIiBRUUoAGcM79yDl3NV4l+jRgNdDonHuFKs9SSENtiJH41CALcGxwjLqakNeFO6Na3L6snq2/c/7EcZ59oYOKcrW/6Dm479UXrwamVqADMX88A6OJmX8xERERERFZFEpZAz2Jcy4JPFvGsUiFawhXU1ddxeh4asq1VU113hTuxMQU7iW11fSNxHn1RacB3nTuO7delff5mzraueHmh/jdS9r42KaLAXi6ZwTIXYEG0oF+cDR3wBYREREREQmUXIEWmanG2mpOXxYhHJq6SfP7XnleRhOxcaoMTmuqo3c4wZGBUWBiy6t8xpMp+kYS6S2xAOr97bPyVaCDAD0QUwVaREREREQKy1uBNrOP+H/8jHPuRMZxMZxz7mMnNzSpNA211cSTKa69ZDW7ug4BUFddxdh4itdfdjo33fsMY4kUw2NJGmqrWVYfpnckzpF+L0DHkykSyRQ1ody/9+nzQ3BmgG4I+92/80wdH02cXAU6s6N4W3OELRvXaS21iIiIiEiFKjSF+wa8Laq+DZzIOJ5aPpwQXHeAArRM0lhbzcHeEVYsqZs4V1dDzXgSM6OuJkTvSJyhsXEaa6tprq/hQM9IugINXsW4KZI7QJ8Y9jp6ZwboupoqzGBkLF8F2js/kzXQnV3RSVthRftibNu1D0AhWkRERESkAhUK0H+PF4SPZx2LzEhDbYjhsXEO9Y9y2tI6nh0c5fjQGKct9QJ1XU1Vegp3UIG+/2BfugINXuBtiuTe2ipXgDYzGsLVeSvQJ7MGeufu7ikdxWOJJDt3dytAi4iIiIhUoLwB2jl3Q6FjkVI11FYzPJbkcF+MNa311NZUcaBnhAZ/nXLQhXvID9DNDTX0jSQ43B9LPyNfMzDIHaAB6sOh/F2401O4S69AH+qLlXReREREREQWNjURk1Omsbaa4fi4t164KcK5KxoBL1gD1FVPNBFrrA2xrD5MPJniyePD1Pl7QecLwgA9foBenhWgg+Cey8Q2VqVXoNuaIyWdFxERERGRha3oAG1m+83sxiLu225mT5zcsKQSNdRW4xwc6h9ldXMd567yAnR9OKhAVzEaNBELV7Os3puqfXRgjLNbvXvz7SMN0OsH6Ob6EirQ8YkKdGdXlA079rB26y1s2LGHzq5owe+zZeM6aqsn/ycUqQmxZeO6gu8TEREREZGFqZR9oNcAK4q4r9W/V2SSoNIMsLopwkOH+gG4e/8JNuzYw3mrGtP7QHtNxCaC8NkrGvjfwwMFK9AnhuMsqasmnBVqG8JeBTq7Y/bfvOo8Rvwp3L3D8ZIbgm3qaOfRo4N87nbv90Xt6sItIiIiIlLRSgnQxYoAM9sTSCpao7/WGeBAzzC77puo8Eb7YhwdGGU85dJroJdlBOhz/One062Bzl7/DN5e0E88OzQ1IH9/H8mUoyEcYjienFFDsOeduQyADecu55tvfVGhry8iIiIiIgtcWddAm1kTsAE4Us7nSmUI9mQG+MH9hxgbT026Pp7ymrz3xxJ+gJ7otn32igag8BrofAG6IVzN4f7RKQF5NOF9/qqldVPeE5iuIVgsXcEuvQmZiIiIiIgsLAUr0Ga2P+vU683s5QWetcp//fLJD00qTWPGFO5jg2PT3BuaNIU7qEAXWgN9YjjO6qapYbg+HEqH81xWLq1l//HhnNemawgWBOi+kXjB+0REREREZOGbrgK9JuPHAY1Z5zJ/Tvfv6QTeP9MBmdkbzewOM+s3syEz22tm7zKzGVXLzSxkZn9uZr8wsx4zGzWzg2Z2s5n97kzHKaUL1kDXh0O0Neev+gb3/uLRZ9PHb/vaXmD6AJ2zAl1bjRX4rGAf6pk0BAuakPWOqAItIiIiIlLpplsDvdZ/NWA/cBOwJc+9ceCYc27G65/N7LPAO4FR4FYgAVwNfAa42syud87lT1BTn9cC/Bh4AdAP3AkMAmf4zz0K3DzT8Upp7t7fA3ghOByqoiZkJJITleHM4+6jg/yg61D62uH+UQC6nu6d0gxsy8Z1vPbSNi9AN+ZYA+13+Y7UVBFLTEwbr62uYmw8lZ7C/ZYNa/jPO59ibDxFfTjEJ163ftqGYEEFOpZIMppIUlcTKni/iIiIiIgsXAUDtHPuQPBnM/sqcEfmuXIys+vwwvMR4GXOucf886uA24DXAe8GPl3k86rwwvELgH8H3uOcG864HlTT5RTo7IryyZ8+mj7uiyWoqTKW1dfQN5KgrTnCKy5YyVfv8v55/eTBI1PWLAP84tFj3Pl4z5Ru2aOJJPFkipb63BVoB3zstRfzwc4HGRtP0doY5o0vPJN/ufVxVvoBen17M2uWN9B9dJDnr2kpqpt2LKMi3jeS4LQmBWgRERERkUpV9LRo59xbnHP/MYtj2ea/vj8Iz/7nHgXe4R9uLWEq99uAFwM/B96eGZ795w455x48yTFLkXbu7mY0q2lYIuWoD1fz5I5ruHPrVbz0ORO7pJ3IMyU6nnQ5u2V/8mdeOM/ZhduvQF99wSrWtnrNyD722ou57KwWAFYtrQVgYDTBoX6vaVh0muZhmZ8d6NU6aBERERGRilbWLtwzZWanA5fhTQP/bvZ159zPgShwGlDsXkHv9l9vdM7l7yAlp0S+btaZ5zOnP7fmmIpdyLMDXlOyfF24AYbj4xwf8kLuwGiCmN/RO5jCfbh/lMHRcaqrjGhvjGL+2WRWoBWgRUREREQqW8n7QJvZ84HXA+cBSyFnfybnnLu6hMd2+K8POefylf7uAdr9e381zRhPAy7GW0N9m5mtB64DVgM9wG3OuZ+WMD45SW3NkZxV3cwu13U1E7/P+X9espZ/vfXxSRVeMwiZ5eyo3dIQpqfAPtAAQ2Pj6ZDbH0tQE/I+r7WxliqDR48MAnBxexP3H+yjdySR83mZMsfXN5LIuT67mKngIiIiIiIy/5UUoM3sk8BfMhGaHZMDdHBcasU3aFZWaH3101n3FnKJ//oU8GG86eGZ49xmZr8ArnPOHS9hnDJDWzauY9uufZMCZ3aX68wK9O9e0kZbU2RSGK2rrsLBlD2dIzUhXnXRKv7rNwcLVqAP942S9MP3QGyc+vBEV/AldTV0H/UC9OVnLeP+g31Ee2NFBegltdUMjo1zW/ez/PcDh6eszwYUokVEREREKkDRU7jN7A+BvwKeAd4O/MS/tBF4F15V2IAbgatKHEej/5p7M17PkP+6pIjntfiva4EPAF8HLsCrmF8FPAy8DPhOieOUGdrU0c72zetpb45gQHtzhO2bJ3e5ztxGqrG2mk0d7dy59ar0GumzWhuorw2xffP69G9D2prruO6ydm757WEA/uCLd9PZFZ302cEa6IO9I+lz/bEEo37QjYRDLKmr5kCP98/v8jXeP59o3wjTicWTrPa35Nqdo/FZLJFk5+7uaZ8jIiIiIiLzXykV6LcB48BVzrknzGwDgD8V+qfA583sI8AHge+VOI7MinY5BEmsGrjVOfemjGu3mdmrgEeBK83sCn+N9eQBmb0d7xcFnHnmmWUa1uK2qaO9YCU2swId7BmdqT4cYiSe5FUXrUr/Q3nny8/l47c8nA6uh/tHp1R9g2c93TMRiAdGE+k9petrvAp0ysUwg+ed1QzAM73TNxKLxZM0R8JEakIMjObewS3aF2Pt1ls0pVtEREREZIErpYnYc4G7nXNPFLjnY8BBvBBdikH/tbHAPcG1wQL3ZD8P4IvZF51zzwC3+Ic512o7577onLvcOXf5ihUrct0iZVbrr4EOh6oIV0/9p9kQrmZkLEnP0ESzrn/d89i0Vd8gQAcV6HB1Ff2xRHo/6upQFUvrvHtWNNayorGW+nCoqE7csUSSSDjEsvoaIgX2gHZMTOnOrpCLiIiIiMjCUEqAbsCbvh0YAzCz9JRqv9v1PXjbR5XiKf/1rAL3nJF1bzHPA3gyzz3B+dOKeJ6cAkEFuqE2dxCNhEMMx8c5MTwRoIPu29kyu3s3+FO4nz7hnVu7vIGBmNeFO2hctqSuBoDVzRHMjPbmSN7O4Zli8SSRmhDN9WHWttZTXZWrp17G/ZrSLSIiIiKyYJUSoJ8FlmccH/Nfz826r4nCleRcuvzXi8wskuee52fdW8gjTKynXp7nnlb/dSjPdTnF6qqDAJ17ZUFDrTeFu2d4IjTna/KV2d273n/eMye8CvRZy+vpjyWIJZLpRmJLI95rW1Nd+v0lVaAbaqirCXH+aUtytqXPFO2LqQotIiIiIrIAlRKgH2dyB+x78NYu/0VwwszWAVcChaZ5T+GcOwjcB4SB67Ovm9kVwOnAEeCuIp6XAP7bP5wyRdvMavCaiAHsLWWsMntqQkaVeQ3EcqkPV5NMOQ73j6bPveaS1VOmTmd39w6uD46N0xSpYXljLQOj44zEk+kGY0v9CnRbc4TOrij3PHWCB6MDbNixp2DYjSWS1PkV6L6RBCOJJK+8cBWrm+qI1OT/zyvfVO7Origbduxh7dZbpv1sERERERE5tUoJ0D8FzjGzC/zj3UAUeKuZ/cbMvgfcjReCvz6DsWz3X280s3RV28xWAp/zD3c451IZ195tZo+Y2dfyPC8FvMvMrs54TwivU/g5/vi/P4Oxyiz4wf2HcA4eOTKYMzwGU7EPnpioDJ+3asmkrty5unuHqiwdopc3hFkaqfYq0HGvetzZFeV793qrE77166fYctMD6QZj061bjvkhfFl9DccGxzjQM8JzVjWyuqmOWCKV8z2Qeyp3Z1eUbbv2Ee2Lac20iIiIiMg8VEqA/ibwEaAewDk3Bvw+3lTuy4HX4U3f/m/gk6UOxDl3E/B5vDXJ+8zsZjPbBTwGXAh0Ap/JelsrsA6Y0ibbOfcA8B6gDviJmd1tZjfhdd9+L9APXO+cm36ersy6IDwG3bVzhcdguvXBEyPptcYDsQTXXLIaB7z3Fedx59arcna5DtZVL28Ms7Suhvh4it6ROCNj42zbtY/BMa+DdizhSCQnN4PPt27ZOedN4a4Jsaw+zODYOMmUoy8WZ1+0f9rvnL3Geufubm2DJSIiIiIyjxUdoJ1zTzvnPu6cuzfj3F1407p/B/gj4DLn3Gudc7n385n+M97pP+c+4Aq8PaYfB94NXOecSxZ4e67n/Svevs8/xlur/Xt4W1t9EbjUH7/MA8WEx/raif2cVy6ppa7G66bd6zcVa2nMvR4aJsJ3S0OYpog3XfvowBiH+kenfG4uuRqKJZKOZMoRCXtTuAM/eejZKSE8l8x12vk+o9B5ERERERE5tUrZBzonv4K7uwxjCZ73LeBbRd57A3DDNPfcDtx+ksOSWVZMeGzIqEC3L4uQdI7+kQQnRvwAXV8oQAcV6FqWpgP0KOOp4rYezw67QDp4e124a9Lnjw/m7gyeKXuddvAZuRqX5frs2dTZFWXn7m4O9cW0d7WIiIiISIZSpnCLzJp8IXFSN20/BPeOJFjeUEtTpIb+WIIT/r7Q+Tpyw0Rn7+UZFejxlCu4d3MgV9gFb/0zeNtrPXJ4IH2+ynL34S60Thtgy8Z11Gbtf53vs2eL1mGLiIiIiOSXN0Cb2Zkn83Mqv4QsfFs2rpu2m3YwDRu8tcxBgO4Znj5ApyvQDWGW1k0859IzmqZ8bk2VscyvKNeELGfYhYkK9EOH+vnqXQfS55NualU7UhPidy72thzf8zdX5Hzepo52fu/StvTx6qa6vJ89W7QOW0REREQkv0JTuJ8CipvfOpWb5tkikwQhsdDU4WANNHhBeCCW4FDfKL0jRVSggzXQjbXpCjTAhW1NvOH5Z+b83Bt++BDf3XuQ12aE2kxBBfpH+44wNj6143bIjJRz6WfGkyl+9OARnh0Y494DvTk/sz4jzH/nz/8PZ7TUT/t3V05ahy0iIiIikl+hkPs0Mw/QIiXb1NFesNraMKkCXUvPcJyHDw/S40/hzlyHnKmzK8rPHz0GwN/f/BB/9YrnpK/Vh0N5P/eclY0Mx5Mc7h/Nswba65V3wq+AZ0s5x5M7rkkfB2O46d6DfPEXT6YrvcE0afC28DID5+D40NgpD9DzZR22iIiIiMh8lDdAO+fWnMJxiEwrswIddNMeiCXoHYnTFKmhJjR1RUKwpjcIq8eH4nz8lofT1yPh/Gugz13RCMDjzw7lDtBxr+rc2hjm+NDUEJ39nlVLawH4+l0H8kyTfoTheJKL2pbyYHQg/YuBU2nLxnX87U0PEM/oIl5TZYzEx1m79RY1FRMRERGRRU1NxGTByJze3OqvgR4cG+fY4Fje6du51vSOJlLphl6Fmoidu3IiQOcSPPdNL14z7fptgFVL6gA4MZLI+bxDfaP0jSTYcE4r4FWgT7VNHe1c//zT08fNkRowr3GbmoqJiIiIyGKnAC0LRnWoirDfpbqlYWIt81M9I3kDdL61u0F9tb5ABbq1MUxzfQ2PHyscoF+zfjXbN6+nvTmCkb/LdnN9DeFQFY21uSd+BN/hxed6Abonz9Tw2XbR6ub0nyPh0JQ9rdVUTEREREQWKzX6kgWlIRwiPp6atB3VU8eHeclzWnPen29Nb3WVedtYhfP/J2BmnLuikceP5gnQcW8NdKQm/zrq7OetXFrLaUtr+e0zA8STkxuPBWupt37vt9SGjGNF7Cc9GzIr9kf6R3Peo6ZiIiIiIrIYFV2BNrNkCT/jszloWbyCrayCbazAC3wt9bkr0Pm2xzpjmbc+uX6afaCrq4y9B06wdustbNixZ9LU5fQ+0EXsJR1YtbSOcHWI16w/bcq1oM57uH+UeNLxwMG+op+bT2dXlA079uQcfz7BLwaASR3LM6mpmIiIiIgsRqVM4bYSfjQ1XMqusyvK0QGvIvrKf/4FDzwzETBbGnMH6E0d7TmnV5/tNwgrNIW7syvKvU/3knLkXP8bS3gV5EKNyLKtWlrL0YFRwtVVVFn++xzw0OGBop+bS9BALdoXK2n9ciyRJFRl1IdDrD+9iexh5lrfne/zSw3vIiIiIiLzWdFTuJ1zOUOxmRlwFnAN8FHgs865vyvP8EQ8QRgcT3l12mhfjC/8fH/6er4KNOTeHivYUqquQPjdubs77/rfTR3txOLjmEFtdfG/L1q5pI47Hj1O99EhUtNsEhfPsbd0KXI1UMscfz6xeIr6mhBnr2zk8WeHcMDSumoGRsexjGfsPXCC2x45lnPf7uzu55lbdamDt4iIiIgsVCe9Bto554CngM+a2QPAbWb2sHPu2yf7bJFArjA4lhEw8zURy6WzK8pP/vcIAH/x9Xv5wGsuyBnq8q3zDc7HEkkiNSG83yEVZ9XSOgbHxnn48AANtSGGx5J57y1UoS7GdOPPJ5YYpy4cIlJdxeGMNdDB/tTgBeJv3P10+lq0L8aW7z7AR29+iL6RBFVmJF3+Xz6IiIiIiCxEZZ1q7Zz7JXAf8J5yPldkutBXbIAOKqNBcH12cCzvtOZ863yrzFi79Ra+9eunp0xvnk6wF3R8PMW1l6zOu366uspIORhPzrwKnW/8061fjsWTJFMp7n26N31uYHQcN03FPJFy6e2ussNzQM3HRERERGQhm421ygeAi2bhubKITRf6ig3QhaY1Z9uycR11NVP/E0k6hwOG40lG4smS1vauWlqX/vMfvuCs9PpsgJBfyW5vjrDp0jbA2395pvI1UJtu/XIskWQgNj5l+no5qPmYiIiIiCxks7GN1UXAyS3eFMmyZeO6SWtqwQuD1VUwOJYsOkCXMq05mGr83u/cj3NewM2urDooaVryvozGZ+/4xr28/9Xnc+fWq6bc96N9h7npvijHh8ZYsaS2qGfnG//7v/dbxvytvz587YXTjjWWSKXXmpdTsc3HRERERETmq7JVoM1suZl9Fjgf+HW5nisCubtpX3dZe7oT9u9/4a6iKsGlTmve1NHO2tYGrrlkNamTnJbc2RXlU7c+lj4+3D+ad/p4a6MXmnuG4kU9O59NHe2c43cc/8jvTh+ewdvGKlxCY7RirFhSy/bN67X+WUREREQWtKIr0Ga2v8DlRmA53hZWceCGkxuWyFSZ3bSzu3IHYTS4L598lexCldHlDWF6hsZoa44QzRGWi52WvHN3N6OJyZMz8jXWWu5vy3V8aKyoZxfSN+KF8MHR4rZnjyWSnLuigSePj0z6e6qpMkJVxuh4irbmOkIGB3u9JmPNkWoGR5OTKvThUBVxfw331lefr/AsIiIiIgteKWWmNQV+WoEEcCtwpXPuV+UaoEgupaxlzpRvX+hC4W55Qy0nhuNs2biO6qzW2FVG0dOSS5k+3trgVaDLEaBP+AF6aKzIAB1PsnZF45S/p53XP5d/eN16AL7+Zy8kEq4m5P993PSOF/PCs5eln9HeHOENzz89ffz4saGT/h4iIiIiInOtlDXQawtciwPHnHPF/X/oIidppls0Qe59oQtpaQyz90CcTR3tfL/rGX7+6HHA65R9YduSop9VSgV7zyNHAfiHWx7mP+98atIey6WIxZPpqvfgaHENyUYTKSI1oZx/T/cf9NZwdx8Z5Mnjw7xwbQu/eqKH/ceGCRqGr1pay51br+Irdz4JQGtjmMefVYAWERERkYWv6Aq0c+5AgZ/DCs9yKs10i6aZaG0Ic2I4TirlWFJXM+nauSuWFP2cYrtid3ZF+cD3H0wfR/tieddKTyeoPgMMZUzh7uyKsmHHHtZuvYUNO/ZMevZIfDzv9lrnrvTWU9/68LMkko5XXLAKgCePD6dDcu9wAudcuoP4885cxhMK0CIiIiJSAWZjGyuRWTfTLZpmoqUhTMpBXyzBswNjLKnzJm6MpxyRcO6gmUux08dnOj09l97hiQAdrIEO1o9H+2I4pgb0WCKZ93s11lazuqmOnz3sVcifd9YyljeEue/pXnqG46xcUks8mWJobJy+kThL66pZd9oSDpwYIT6u5vwiIiIisrCVvI2VmYWB64CXA6fj7eRzCLgd+J5z7uQXbYpMIwidO3d3c6gvRltzZMbTnKfTku6IPcbRwVFedPZyfvbwUZwjb6W20LinG2Mp09M7u6IF/w56MyrQg/4a6EIB/fee25aewp3PuSsbueMxbxr7OSsaWNvawC/8ae0vWNvCf//2MCeG4/SOJFjWEKZvJE4y5Vj3oR/P6v9OIiIiIiKzraQAbWYvBr4FnIHXcTvTnwHbzeyPnHO/LNP4RPIqdS3zTLU2BB2x4xzpH+VVF67irJZ6nuoZKakCXaxi10oHleQgDAeVZJj4BcMJvwLd0hBmcDRBZ1c057PBC+ij496ziv1er/7UHbQ316XH8MJJATpOyjm+s/cZgEnV7swxioiIiIgsFKVsY3UR8BOgHtgP/BfwlH95DfAG4Fzgf8zshc65h8o6UpE50uJvKfXk8WHGxlOsWlqXnsb9r3seZ9d90bJWVYvdaqtQJTkYSzCF+xe6jBwAACAASURBVMyWep45MZIOr7m0NUeIxZPpz8ulsyvK3ft70sfRvtikyvi/3Po44AX3vhFvyvvYeO6tu4LvMNszCEREREREyqWUCvTf44Xn7cCHnXOT/r9iM/s7/54PAB8FXl+uQYrMpeX+llIPHx4A4MCJER4+PJi+Xu6qavCMD3x/HyPxJO15wmUxU717RxKYwenLIuyL9pNMuZzvCQJ6EMjzVaB37u4mkZz8jMyjY/62Wz97+Ci9I/Ep4TkQ/J0Vqp6LiIiIiMw3pTQRuwLods59MDs8A7j/n707j4/zLO/9/7ln04w2S/KuseOYOMjZSETCEkwJCYspYVFMoYe2v57COXDK0pYCbm2gJZQWu6ScUzhAWw6FlrKUAEEFQjGFBAhmyaYkjhM7mxPb40W2JVnbjGY0un9/PM8zmu0ZzUgjW7a+79dLr/HM3PPMLSWxcs113ddl7ZS19kPAfpzz0SLnhfZGp/P2I24A/Z97jjJZFIjOtsmXn57uOFueG6ejKcLubTeUDSqr6UQ+OJ5mSSzMkljYN3gGcs3MUpnKGehqxoQB3P7QUYbGMzQ1lL9O0JgZG6VV6hQuIiIiInI21BJAx4D7q1h3PxCd3XZEFp5QMEB7Y5h9bgB9ajRddl21wWW1oqFgLqAtp5pO5ANjaToaIyXjt/I1NQRzAfr4DCXc1Y4JG05NMjoxyUsuXl52j1lbPpj3foYzdQoXERERETkbagmg9wOrq1i3Gnh8dtsRWZg6miKMucHlqiXlPx+q9wzqaNgJoK1PsOmNxQoGnH5+TQ3BkrFYg+Np2psiuTPb0XDhf/IGuNid7QzkzkA3+pRwlwvay2kIOe/zoouWsmPLFbnXeKO74jNkz+s5yktEREREpF5qCaD/EXiJMWaT3wL3uZcA/zTXjYksJEvdUVYt0RB//qqNZ2QGdSwSZMpScuY4X093PBesXt65pKTUe3AsQ3tjOBdAf/DGS4i5QXS8Lcb6ZU1EQtPfixe0Rn0C6OJZ1m2xMOFgYUN+A7nS7bbGCD3dcf7b89fSEg3lytFnyp7XMspLRERERORMqbqJmLX2c8aYjThdtj8LfAU44D59IfC7wDuBT1pr/7HeGxU5m5a6o6xWtkbP2AxqLzBOTWaJhMp/1jU2Mcl4OkvAwCNHhpmasgQC0wHt4HiayzpbaW5w/lN/8YblXB4/QjBg+Pe3X8u7vnI/jx4bzq2fqQs3lI4PK55F3RQJ8viJUQDaGyO525HUJJnsFOFgIPf6P/36A1icjPfHbprOnlc7yktERERE5EyqZYxVfj3l+92vct5jjHlP0WPWWlvTzGmRhWRpsxdAO5noMzGDOuoGsal0llafM8wn3a7Xz72gnXufGeTQ4DjrljYBYK11zkA3TZ+BHk1N0j8ywZVr2gBY1hzhxMhE7nrJGZqIlVP8s/jjr/XxWL8TQLe5Ddja3Q8gBsfTrGhxSuBfd2Un7/n6A4Dz8339VZ25a1Q7yktERERE5EyqJag1My+Zl9eKnHUd7iirlS1nrj9eLoDOlB8FBeSC35d2LefeZwbZe2Q4F0AnM1kmJqdoa4zkMtAjqQwnRiZY0eJ8P8tbGhhJTZLKZImGg7mA1e8MdDU63GAZpgPnDjcTPTiWyQXQ4+57dTSFOTSQZP327xM0hqy1xNtivOHqOF/51UEsTif0D7/2Mo24EhEREZGzquoz0NbawFy+5vObEJlvicFxAG5zRyudiW7QXsOv1KR/J24vA+2N1XrnV+7P7W9wPAM4Aap3BvrYcIrxdJblbgC9zD3b7V3HK+H2OwNdjYIAOpeBdm4HxqY7mI+mJgEYTk7mHvO6cyeGknzzvsO5GdNvf8lFCp5FRERE5KxTYCsyg96+BN958Eju/pkaqRQNeRlo/wDay0D/40+eLNnfbfcfBpzzx14A/dSJMQBWtE5noAFOuqO5qjkDPRMvgI6EArnreGehh8bzAugJJ8Avnqntyc+8J4bGZ70fEREREZF6UQAtMoNbdu0v6YR9JkYqVVXC7Qa+qcnCNclMlv/zX48B8IFv7+Gux08C8NRJ52yyV0btZaC9QDyZyRIOGsLB2f/V4AXQ7Y1hjDEFjw3kBdAjqcnSF/tIDE43FOt1qwDWb7v9jFUDiIiIiIhAbWegATDGhIHfAl4KeDWVCeAnwDettZl6bU5kIThbI5VyJdxVZKDL8RK7J0fT/PXtjwDTGejlLcUZ6OkAOjqH7DPkB9DTpdxeM7HBvBLusQn/7ytfc0Mo15G7ty9R0FzMy7YDZ7TEu7jz+Hx0YRcRERGRhaemNJMx5mpgP/Bl4G3Aq92vt7mP7TPGPLfemxQ5m/xGJ833SCUvkE1WCKBPjk4QCszco8/LYj910i3hdgNnr7t4LgOdzs6pfBug7+AgAPuOjeQyxA2hIE2RIANj05+veSXcDT4juiLufOlLO1tJDCax1nLLrv0lP48zUQ2QzwviE0NJLGeupF9EREREzr6qA2hjzBpgF87M58PATpzA+e3ADuAgsB7YZYxRKkbOG1s3d5UElWdipNJ0CXflDPSzljVVHfSmJ6eIBAMsiTkZ4YZQkCWxcEEGOjaHBmK9fQk++ePHc/fzg8v2pkjBGWivhPvPXtVF3P0wwvssYGVrAze5Gd3LO5cwls5yOpk5a9UA+RZCEC8iIiIiZ0ctGehtQAfwKWCDtfYD1tp/ttZ+3lr7QeBi4JPAUnetyHmhpzvOji1XEG+LYYB4W4wdW644A3Ognf88JyqcgT45OsFl8SXs2HIFq1qdc83GJyEddKPT5S0NubPJUDgLeq4Z6Ft27S85s+0Flx1NkYIz0KMTTgC9pXsNu7fdwNM7b+RLb30BAJ/6b91cuKwZgMvjrQAcHkyetWqAfAshiBcRERGRs6OWAPpVwFPAn5Y752ytnQTe5655dX22J7Iw9HTH2b3tBg7svJHd2244I+ddcxlonzFW1lpOjEywrDlCT3ecX2y7gXDQcEPXirIZ89VugO2de/Ysb2moWwa6UnDZ3hgpOgPtBNBNDdOtGLzu4P0jEwyNp4mEAly0vDl3ja2bu4gUNTg7E9UA+RZCEC8iIiIiZ0ctAXQcuNtaW37mDGCtnQLuBjrnujGRxW6mEu7RiUkmJqdyAXEgYFi9JEZjQ4iP3XQ5Xo7Zy5hfsLQRmD7/7FnW3FC3DHSl4LK9MVzYhXtikkgoQCTvDPTyvK7gg+Np2hvDxNudayaGkvR0x3nxxUtz6zuawmekGiDf1s1dJee2z3QQLyIiIiJnRy0BdBKnhHsm7e5aEZmDaMjrwl2+hNsLer1RVOAEy4nBcTZdvAwL3PzaS3MZ82Y305ufge7tS3Dn/n6ePjXOpp13cPR0ksY5ZKArnRdvb4owlN9ELDVJS0PhIIC2xjCRYID+kQkGxzO0N0a467ETAHzku49w0fbvc8e+E7nGaX/ysmef8e7XPd1x3rppfe7+mSrpFxEREZGzr5YA+iHgpcaYjX4LjDFdwPXuWhGZg1AwQChgfLtwewF0fkAcb4+RGEpy8NQ4AOuWNeWea4k6jcO8GdBeN2lvnFRiKMmRoVSunHs2Kp0X72iMMDIxSdqdWT02MUlztDCANsawvKWB/pEUQ+NpMtkpPvDth3PPZ90CmEl3Rtddj5+Y9V7n4pJO51z2jc9ZfcZK+kVERETk7KtlDvQ/Ay8B7jDGfAj4srU2DbnZ0L8HfBQIA/+v3hsVWYxi4WDZEu7evgQf+e5eAN5364N84NWX0NMdp7MtRv/IBE/0jwKwrqMxt/4He48C8MXdB1i3tLFsN2kLPHZ8dE577umOlw0o29350EPjaVa0RhmdmKQpUvpX0LKWBreEO0NiKOmbgQfY/cSpOe11trxu4pUavImIiIjI+afqANpa+2/GmFcBb8YJkP/JGHMU5/+5O3Gy2Qb4qrX2K/OxWZHFpiEcLAkgvcyxF/z2j0yw/bY9AKxpi2Et/OqpUwQMrGlvLFk/lMwU3C82nvYfmzUX7Y1OAD3gBtAjqdIMNDhntA8NjDM0nq4YPEPlGdnzacBthjbh0+BNRERERM5PtZRwY639XeDdwNNAEFgDrHX/fAB4t7X29+q8R5FFKxoOMFEUJFaaQ+w13PrFk6fobIsRCQV81wd95l01N9RSmFK99ianhHzQPQc9OlF6BhqcAPr4cIqh8cyMe/HOQp9pXjfxSjO6RUREROT8U1MADWCt/ay19iKcwPmFwLXAWmvtBmvtZ+u9QZHFLBoOloyxqjQqKu52we4fmWCd23Xbb33W2rIdt1+8YWmZ1XPX4ZZwD7rlz2MTkwUjrDwrWqIMjmeYnLK8bGPpSC5PMGAIB89OAD0w7nwIMDGpEm4RERGRxaTmANpjrU1Ya++21v7aWpuo56ZExBENB0rKmCuNilrdFs3dv6CjqeJ6r8FXvOj57gva57JlXx1eCbebvR0t00QMCpuivfjiZQV79LLm8bYYmy9dSTIzdVaywN4ZaGWgRURERBaXGWs1jTE3AG8E1gETwAPA5xU0i8y/aKi0idjWzV382TcfIp2dDqy9UVENoSArWhroH5ngQjcDvXVzV8mZZ2+91/DrBw8f5Q+/fD/AnMZYVfIzdxzVh3of5h9+8iSDY2nfEm5Pe2OEl1+6smxTslvvPcT3Hz5G//BEbsb1mTJ9BloZaBEREZHFpGIAbYz5FPAu7657+zrgvcaY11trfzKPexNZ9KLhIGPpyYLHerrj/PvdB/n1gQHAyTB7wXBvXyJXIv1PP3uSla3RXPB5y679HBlKFqz3XHPh9Ij3qE/J9Fz09iX4i//Ym7ufcMvKDw2Ml6xd0ZoXQLvnpstZ2epk24+PpM54AK0z0CIiIiKLk28AbYx5PU7DMIC7gHuBVuCVOOefv2qMWW+tnf3QWBGpKBoOcsoN1sAJRD++ax9HhlLEwsHcjGXvue237SGTdWYkD4xlct25/UZLeX7++ElCAcPklOVj33+UcDBQ19nG5RqZAex+8mTJY/kl3G1u2Xc5K91A+/hwqg47rM1AroRbGWgRERGRxaTSGei34Yyo+iNr7XXW2vdZa98GXAL8FFgJvPYM7FFk0crvwu0FyEeGnIAxmcmy/bY99PY5pykqdeeuxLvu5JQTeA+OZwquWw9+jcxOJydLHlvW3IDXILy9QgC9ystAD5/Zz/CS6SypzBTGaIyViIiIyGJTKYC+Gthnrf1M/oPW2nFgG05J99XzuDeRRS8anj4DPVOAXKk7dyWzDbxr4dfIrKOxtET79oeO5s6LvOb/3uUbyC+JhYmEAux+/ASbdt7B+m23s2nnHXUN/MvxSuSXNzeQykxhrZ3X9xMRERGRhaNSAL0U2OPz3EPubYfP8yJSB9FwgJTbqGqmALlSd+5KZht412Lr5q6y46je9Ly1Bfe9bLibDOfIUMo3G26MobkhyE8fO0liKInFOVtd7+x5Ma+B2OolTgZcjcREREREFo9KAXQIKO3wA1hrvf+z9u/wIyJzlt+Fe6YAuVyQ6nXbrmS2gXcterrj7NhyBUvdWdBe9+1XXraqYF0t2fDevgQDYxmyRRngemfPi3kZ6FUKoEVEREQWnVnPgRaR+RcNB0lmslhr2bq5i2i48D/Z/ADZC1LjbTEM03OeZ2oGNtvAu1Y93XG++Y4XAXD1hc6s6eIxVtVmw71MtZ96Zs+LDY5nAFi9xPmAYUKduEVEREQWjZnmQF9ljPnL2Txvrf2r2W9LRMAp4bYW0tkperrjHB9JseP7+wAnQC4eRzVTt+1yqhlzVS9r2mOEAoY9h08D0FQUQHe2xXIjroofz+fX1dtvfT15I6w625wMtDpxi4iIiCweMwXQV7pffq4q87zB6d6tAFpkjryZzKnMFA2hIM9e0QLAt95xLVevq18LgtkE3rMRDga4oKORp06OAdAcLfwraOvmLrbftqcgOC6XDa+UYZ4pe97bl5jThwUDY2mMmZ5DrU7cIiIiIotHpQD6X8/YLkSkLC+AnshkIRbmmVNO4HlBR9PZ3NacrF/WlAugmyKFfwVVmw33y1QHDBXL1r3Sby9A95qO5b/3TIbG07RGwzS6e1cGWkRERGTx8A2grbVvOZMbEZFS+RlogKdPjdMYCbKs2X8+8kK3fpkT/DdFggQDpuT5arLh5TLVAG+4ek3F11ZqUlZtAD0wnqGjKZI7j55SBlpERERk0ZiphFtEzqLiIO3gwDgXdDRiTGngea5Yv9wNoBtm/9dPcaZ69ZIoR06nWNfRWLFEe7Yju/KvGQkFWNXakFcdoAy0iIiIyGKhAFpkAYuGvAy0E0A/c2qMi91z0Ocqr/S6f2SCTTvvmHXDsuJM9WV/+QPuOTDAZ+580rdEu9omZfmKy74nJqd4ZiDJW//lHmD6n42IiIiInP80xkpkAfOynMl0luyU5dBAknVLG8/yrmavty/BF+46kLvvBbi9fYk5X7ujOcLdTw9WnCM9m5Fdfh2/R1KTANz1+Im5bl1EREREzhEKoEUWsOkS7imODadIZ6e44BwOoG/ZtZ/UZGHJc36AOxcdTQ2+o628Em1vVrY3fzocNDPOyp6pvPs7Dx6Z5Y5FRERE5FyjAFpkAZtuIpbNdeC+cOm524F7tmeQq9HRGCYcLH82PL9Eu6c7zk3PdQLmWDjI66/qrHjdmWZKD45natypiIiIiJyrFECLLGBeAP3zx0/wzi/fD8B7b32gLiXPZ4NfMDpTkFqNjqYGmiKhqkq0vaB3ODXJidGJitfdurmLhpD/X5VLYmolISIiIrJYKIAWWcC8Eu5/v+cQQ0kn6Ds+PFG3c8Nn2mzOIFeroylMajLLji1X5DLRzQ2hsiXaQ+NpvEbmTxwfrXjdnu4477r+It/nf+PiZXPbuIiIiIicMxZcAG2M+R1jzF3GmNPGmFFjzL3GmHcZY+a8V2PM240x1v36dD32KzKfvAx0JmsLHq/XueEzzTuDHG+LYYB4W2zGM8jV6mhqIJWZ4pWXraQ1GgbgxRuWlb326WSGrpVON/MnTlQOoAGev34pAO986UV5e48C8Kzl53ZXdBERERGpXtW1h8aYO4AfWGs/PsO69wOvttbeUOtmjDGfAd4JpIAfAxngZcCngZcZY95orZ3VzBhjzDrg7wALnLtDdGVRiRZla/PV49zw2VA8fqpeljZFAOfncmosDcAzA+Nl1w6Op7n6gnYSg0me6J85gE6mnb92Xn7pSv7sVRtzj3d96D+Z0BgrERERkUWjlqzuS4GNMy0CuoDrat2IMeYNOMHzMeA51trXWGtvAi4GHgVuAt5d63Xdaxvgn3G+3y/N5hoiZ0O0wtnbepwbPp+0uwH0w4lh535jmIOnxrDWlqwdGs/Q1hjhohXNVQXQ424A3Rgp/EAjGg4yUdRVXERERETOX/NRwt0AzCYls929/XNr7ePeg9ba48A73LvbZlnK/Yc4meztwNOzeL3IWREKBjCQO6/rqde54fNJhxtA70mcBuDai5Yyls5ycjRdsG4yO8VIapK2xjCRoOFXT51i/bbb2bTzDt9z5eNpZ+ZzY7iwaKchFCClDLSIiIjIolHXANoNbq8GTtb4ujXu69LAN4qft9b+FEgAq4AX1njt9cDHgd04peAi55SmhlDuP9R6nxs+nxQH0C+6yGnudXBgrGDdabcZ28FTY9x/cIgp65zrSAwlfZuzefOlY2Uy0AqgRURERBaPimeg3XPP+V5V5rH8a20AVgK31riPbvd2r7XW72DnPUDcXfuLai7qlm5/wd3b/7DWWlOcyhNZ4KLhIKMTk6xsbeDXH3j52d7OguUF0HsTpwkGDM9f3wHAM6fGuXpdR26d1838zv0nmJwq35yt+MMJ/xLuwFkt4e7tS3DLrv0cGUrS2RZj6+YufbAiIiIiMo9maiL20rw/W5wM8KoZXtMH/HmN+1jv3j5TYc3BorXVeDfO97DNWnvutSwWYXqU1WWdS87yTha21miIUMAwls4Sb4uxbmkjxjgBdL4hdwa0Nwu6WLnmbF4AXTyCqyE0twz0XALg3r4E22/bk8uOexl0QEG0iIiIyDyZKYC+3r01wB3AD4C/9VmbBhLW2oM+z1fS7N6OVVjjdfqpamaMMeYiYAdwH073bZFzkteJ+/LO1rO8k4XNGEN7U4QTIxPE22I0hIJ0LonxzKniEm7nTPTy5gZOjE6UXKdcc7ZUJks0HCAQKKxgiYYDpDKzy0DPNQC+Zdf+3Gs9fhl0EREREamPigG0e/YYAGPMT4Gf5D9WR97/lZa2y53NxaZLtyPAW2cz+soY83bg7QAXXHBBPbYlUrPevkQuAPzyrw/yrOXNCo4qWOoG0J1tUXr7EpwcnaD3gSPc8/RgLrs7OOZknt/+kmfxif/aXxAA+zVnG09P0hgp/esyGg4yNjE5q73ONQD2G2NWr/FmKg8XERERKVX1HGhr7fUzr5q1Efe2ucIa77mRCms8fwy8BPgra+1Ds9mQtfZzwOcArrnmmroE9iK18DKUmazzr9/AWFolujNob3TOQY9NTLL9tj2588n52V3vDPQbr1nD0qYI7/3Gg4DTnM0vSBxPZ0vKt8Hpwn1qtPYMdG9fgsQcA+DOtljZa9RjvJnKw0VERETKm48xVrPxtHu7rsKatUVrK7nJvX2FMeYn+V/AH3hr3Me+V+NeRc6IShlKKdXbl+CBQ4MA/Ghfv+/P7vR4GmOgNRpmy9VraG4I8dZN69m97Qbf4DCZzpY0EANoCAeZmKytwMULTv0EjPEdp5Vv6+aukqC+XuPN9O+eiIiISHm+GWhjzF+6f/y0tXYg7341rLX2ozWs73NvLzPGxHw6cT+vaG01rq3wXKf7dbqG64mcMfNdons+mc6YOtlg61MzcmQoyeB4hiWxcO48c2s0xEiqfEMxz7hPAB0NBWs+A10uOM2XtZat33iQj3x3L0PjGd/y6Z7uONmpKd73DafIpq0xzM2vvawuGWL9uyciIiJSXqUS7ptxziT/OzCQd7/SHCjveQtUHUBbaw8ZY+4Hngu8EfhS/vPGmOuANcAx4JdVXO+lfs8ZY24GPgx8xlr77mr3KHKmzWeJ7vlmpqDU09kWYyiZoS0Wzj3WGgszPEMAnUxnS2ZAAzSEAzVnoKsJQjNTNtclPDGU5D1ff4CPfHcvHy4KkK9c25778zuuu6hu5dX6d09ERESkvEoB9F/hBMIni+7Plx3AN4C/Ncb8wlr7BIAxZgXwWXfNTmttLt1jjHk3zqiqu621vz+PexM547Zu7io4hwr1K9E931QTlHo/u2/df5gl7llpcEq5h5OVG4GNZyZZ0RIteTwaCjJRYwbaLzidyeB4puQc8hP9o7nnB8bTNV/Tz9bNXfzZtx4iPTlzgzURERGRxcQ3gLbW3lzpfr1Za79pjPkH4B3AHmPMj4AM8DKgFegFPl30smVAF05mWuS84gVJ6oQ8M7+gNGgMWWtpCAXYseUKerrjfGH3ATqa8gLoWIijp1MVrz/uk4GOhgOkasxAb93cxfu/8SCTU7V/HlncpfuJfqenYms0xMBo/QLonu44Dx4e4ou7nwYqN1gTERERWUyq7sJ9Jlhr32mM+TnwLuA6IAjswxlJ9Q/52WeRxaCnO66gpQp+2fodW67gF0+e5I59/bmf4+B4mmcta8qta42G2X+8cnP/ZDpLY9ku3EEyWUt2yhIMmBlHP3nP5wfPbbEwY+nJXLf1meRn25/oH6VzSZS2xgiDdcxAAzx7ZQsAG1e18IP3vKSu1xYRERE5V806gDbGBIClOGXdA/UKbq21XwW+WuXam3HOZtdy/ZpfIyILW6Vs/amxNLfee5iToxMsa25gaDxDW34Jd6yKEm6/JmJhZ5DBxGSWH+49XnH0U/FoKHCC/Jtfd5m7930khlKEA2Axvhnq/HPIT5wY5aIVzVgLp8bqG0APuNcbqPN1RURERM5lNY+xMsa8yhizC2ce8zHgODBijNlljHl1vTcoIlKNnu44u7fdwIGdNxaMpNq4ysmk7j82wmR2ipHUJG2NeU3E3C7cUxVKqp0mYqWfN0bdrHQqMzXj6KdKzzt7fxmvv6qT9qYGXrZxRdl95J9DnpqyPNk/xoYVzXQ0RRicpwB6cDyN9WtrLiIiIrLI1BRAG2P+HrgdeAUQw8k+W/fPrwC+a4z5VL03KSIyW14p8r5jI5xOOp2ti7twT1kYS5fPQk9mp0hnp8rPgQ45f4WmMlnfRmaJoSS9fYmqRkM9f30H/SMTPHj4NFetbePvf/sqVi9xmpe1RkO5c9y9fQmu3fljkpks374/weB4et4y0JmsZWSicoZeREREZLGoOoA2xvwB8MfAKE5H7otxAueY++eP4GSl32WMeUvddyoiMgvLWxpY2hThh3uP8pufvAuAT/74cXr7EoBzBhpgOFU+SBx3s8blS7idxyYmpyqOeHrP1x/A+AwAzH/dqDtO69hwiidPOB22f7n9ZaxqjfLyS1YWlIIfH54AYCiZ4ZdPnmIkNVnQNXuu8gPyejYoExERETmX1ZKBfjcwCbzcWnuztfZJa23G/XrSWvsRnCx0FnjnfGxWRKRWvX0JhsbT/PrAIP0jTtDpjYTq7UvQGnNKs4eT5WdBJ9NOAO3XhRucDPTWzV25jHQ55SrE80uye/sS/P2PHs89N5KazO1xw4pmnnAD6nKl4N556aE6NhIbHEsTCjhRfz1HZImIiIicy2oJoC8BfmqtvcdvgfvcT4FL57oxEZG58rK15Rpce+ePcxlonwB6PO2fgW4IeWegs/R0x3nbb6yvem/xtliuJBu8wLgwg+ztccOKZp7sH8VaW3HmdT3LuAfG0lzoditXBlpERETEUUsX7nGgv4p1JwD//8MTETlDymVr8x0ZStIam6GE2z0bHQuX/nXZkOvC7QS+G1a0VLWvW//XtTx/fUfJXvz2eNGKZsbSWY6eTvnOvAbq2khsYCzNS9cs54n+UWWgRUREXHsqhAAAIABJREFURFy1ZKB3A88zxu8kH7jPXeOuFRE5qypla8E5f9wSra6Eu9IZ6JQbpB85nXQfr/xX69qO0vPSfmeoO9tibFjeDDhzn7du7iJWNJPaKx2vVwY6mc6SzGTZsMJ5X42yEhEREXHUEkB/GFgDfMIYEy5+0hgTAv7OXfPh+mxPRGT2KjX28s4fTzcRm00Jt3cG2slAHx1K0RoNsXPLcwo6fXtCAUPQwMqWaMlz5QJjb48Xr3QC2cf7R+npjrNjyxVE3PeOt8X40GsuAZyRU+CUrm/aeQfrt93Opp135BqmVcvLOMfbYjSEAgqgRURERFy+JdzGmN8v8/C/AH8CvNEY8w3ggPv4hcAbgTjwj8BzgAfquVERkVpt3dzF9tv2lJRxtzeG+fBrL6OnO85k1gl+h5N+JdyVmoh5XbidNUdPJ+lsi9HTHc91zP6b2x/lxOgEHU0RLmiPcTo1SSBQWsiTfxb6yJBzna2bu+jpjvPt+w9jDHz0e4/whZ8fYOvmLp61rIk17TE+/9+fx2R2ir/o3cup0XTu3Lf3PSeGkmy/bU/Be8zEO/Pc0RRhaVNEAbSIiIiIq9IZ6H/BmfFczOAEyn9S5nGAP3S/vjTXzYmIzEWloNQTCgZoigR9M9DJjBNYN0ZK/7rMBdBuBvrIUCo3t9l7/xsuWcFzbv4hb/uNZ/GfDx9lTbt/VtwLvPP19iX4wLcfxrp/G3sBcThouDy+JPc9tDWGGRhL8837Dpd8YJDMZLn5O3sr/hzynRpzupUvbY7QrgBaREREJKdSAP0lygfQIiLnjHJBabHWWJiRuZRw52Wgr7qgrfDa0TArWxt4on+UQwPjXH7F6pr2X64RWjKTJZlxMumejqYIA+Np33PfQ8kMQ+4575my0l4peHtjxLnumJPZrjYAFxERETlf+QbQ1to/OIP7EBE5a1qj4YIS7vxg0ZsTXa6E+0ePHAfgL/9jL//4kycZHM8QL3PuesOKZh44NMjgeIa17Y017a1SI7S2xkjuzx2NEQZG0xW7dOfzRmSVC4JPuSXcS5sa6GiKsPfI6TmXhYuIiIicD2ppIiYicl5qjYVyJdzeGeLEUBILnHYD6x/tPVbwmt6+BDd/d2/u/pHTKed2aLzk+huWN/PkiTGgfAfuSio1QmvPD6CbIgyOp8s2I/OTGEpyYZlGY4PjaYIBQ0s05Fx3LFM2C37Lrv01fS8iIiIi5zoF0CKy6LVGw7kA2m929Cf+6/GC+7fs2p/rvp1v197jJY9546CAmjPQlcZWeSXcvX0Jfv7ESfYdG+GWXft5w9VxQm6jsuaGUEGpdzleRtkLogfG0rQ3RggEDB2NEd+zPDONCRMRERE531Q6A13Apyu3L2utmoiJyDmhNRbm8f5RwD8oLH7cb51X/pzv2HAq9+c//PJ9/PmrNlZd+uyt+9j3H6V/ZIL2xjBvfv4FfPYnT9LWGCnbdfub9x0mO+WEva+4dCXXPXs57//Gg0xO+be1yC/pHhhLs7TJyW53NEd8X1MpOy4iIiJyPqo6gMa/K3cx465TAC0i54TW6HQJt98Z4uJg0W9dfhducLLD/3zXgdz9o6dTNZ8f7umOc/3GFVz5kR/yrus3sMp9j/amMO//xoMlGfP8zPiJkQl6uuN89dfPcPfTgxXfx/tQYGAsTXuTk7X2Auli3oxqERERkcWklgDaryt3AFgHPBdoAnqB03PfmojImdEaCzOczGCtZevmrpJsrYGSYNFvxnQyk6W3L1EwQis1OVWyxq+Bl+8eoyGi4QDHh1M0uCXd7Y2RimXUy1sa6B9xst8N4SDhoCGT9f8cNGAMH+rdQ9/BISanLJt23sGlq1tK1sXVhVtEREQWqaoD6Jm6chtjVuAE2RuAF81tWyIiZ05rNMyUhbF0lp7uOJ+/6ykePjIMQDQUYFlzpCRY9O7f/J29ufFQAIPjmYIMc7Ul4TMxxrCyNcrx4Qlao052uK0xXLHr9gvWd/DzJ04CTub7klUtPN4/VvaMN0DWWr78q4O5+4mhZMm1jUHBs4iIiCxadWsiZq3tB34HiAM31+u6IiLzzRtVNewGwuN5AeaFy5robCvf+KunO05TQ+nnkPkdqv3OCc/m/PDKlijHh1MMjmdojARpCAXLNhkLBgyN4QAXr2hhaDzDxGSW46dTPHddBzu2XFF21Fa1rEXdt0VERGTRqmsXbmvtAHAP8IZ6XldEZD49etTJNm/aeQcv2vFjDpwY44r4EgAeOz5Sdga0Z6YMc7kAd7bnh1e0NtA/MsHQeDo3wqqnO14SFK9ubWDj6lZWtDYA8MypcUYmJlm1JEpPd5zd227g6Z03YmreQeH3JiIiIrLYzMcYqzSweh6uKyJSd719Cb7660OA0+ThyOkUFrjAndc8ZaGxQgA9U4Y5P8A1OOeHd2y5YlYl0E4Jd4rB8TRteaOpvKD41v91LQCHh1JcuKyJFS1OAL3nsNOWYlVrYYOz2XbRVvdtERERWaxqaSI2I2PMKmATcKKe1xURmS+37NpPOls6z/nupweJhYMkM9mKGehyzcSKM8w93fG6nBle2drAeDrLocFkSTAMcGhgLDcG4UePHGf90iYAHjo8BJDr3l1p79V4/yuePav9i4iIiJzrapkD/ZIKTzcDG4F3AW3A1+a4LxGRM8KvHPnkyASXxVt5ODFcMQOd3237yFCSznnsUL3SDZoPnBxj46rC7ti9fQk+1Ls3NyphODXJZ+58AoCHEuUz0H6N0DztjWFufM5q7tx3giNDSVqiIYZTk7zi8lX1/LZEREREzhm1ZKB/wsxzoA3QB3xothsSETmTKs19vnhFixtAV/6rsl4Z5pmsaHEC4OyUzZ2B9tyya3/pPGh3fNYjbkfx4gw0TO+9ty8x44cAX7v7INtv28NoapLmMs3TgKquIyIiInKuqiWA/hn+AXQaSAA/Bm611pamMkREFiC/Mubx9CQHTowA8LmfPcXtDx0968HgSrcpGDjZ4XyVGntNTE7R1hgmGq6cSZ/pe/OC5tGJDFAajPf2JQp+lomhZMFILxEREZFzXS1zoF86j/sQETkrKs1zHhyfvr8QgsEVeSXYbUUZaL9MeihgmJyyZc9M16o56vzKGElNln2+XBbcG+mlAFpERETOB/PRhVtE5JziN8+5WP5857OhuSGUywK3NxVmoP3GZV20ohkoX75dq5ZcBro0gO7tS5QN4EFjr0REROT8UXMXbmOMATrc1w6oXFtEzgfVBnlnOxhc0drA6InJkgy0XzOznz9xkv3HRlhdhwDay0CPFmWgvdJtPwtl7JXOZ4uIiMhcVRVAG2M6cDpsvw64EvDSHFPGmH3AfwCfsdYenZddiojMM78S6HLrzpbevgSHB509/tk3HuKDN15SEAAWn2Pu7Uvwg4ePAfC9h47ygvVL5xQwetnv4hLucqXbnuKRXsXOVFCr89kiIiJSDzOWcBtjbgKeAG4GrsYJuo37FQQuA7YDjxlj3lL0WmOM6a7znkVE6q5cCXSxmYLB+eQFgGm3s/aJ0Qm237aH3r5ExfVeufVIarLi+mq0NDhl4yNFJdyVsvI7tlzhG6B6e0wMJbFMB7Vz2aOfSuezRURERKpVMQNtjHkjzkznALAH+BJwD3AcJ4BeATwf+H3gcuDzxpiQtfb/GWPCwFeAh3FGW4mILFjlSqCv37g8NwP5bJf81tqgaz4aejU1OB8wFJdw+2XvVy2JlrxXfsY5YAxZWzjcoXiP9cpQ+wX5Z7skX0RERM4tvgG0MWY58M/u3T+x1v7fMsv24Yy3+jtjzJ8AnwA+aYy5C/jfwGacwFtEZME7U/OcZ6PWAHA+AsZQMEAsHHTHWE3burmL9976AFNFgw7/+7XrCu4Xl1EXB8/Fe6xn2XWled8iIiIi1apUwv1HQDPwAZ/guYC19pPAB3GGg94LvAqn9PsLddiniMii5hfo1evxajVHQwVduHv7EvztD/YxZZ2yJIBlzU6Ds+4L2gteW+msdLk91rPseuvmLkIBU/DY2SzJFxERkXNTpQD6N4FTOFnlan0CGAAagb3AS6y19T/MJiKyyPiNqfILAGtdX62WaCjXRMzLEB89nQLAuu/xlk3rARgYSxe8tprsd/4e65lF7+mOc/W6ttz9eFus4vlsERERkXIqnYF+FrDbWjtzusBlrZ00xvwCuBG4zlo7MNcNioiI/5gqvwCw1vXVammYzkD7ZYj/7ZfPAHCqKICeqdN5wMDHbro8t8dKZdfVnI0uXhMLO58ZL2tuYPe2G2r8zkVEREQqB9BNwMgsrjkCTCp4FhGpr1rPaM/Hme7maCjXRMwvE3x82MlIDxYF0Fs3d7H9todIZqZyj0WChnTW8uINS/n5E6d4760P8nc/fIytm7vYurmLP//WQ0xMTq+PhYNcv3H5jGejy52f9gq4T45OkMpkic7QdV1ERESkWKUS7pPAhbO45jrgxKx2IyIiC1pzXga60jnrlmiopIS7pzvOB2+8NHe/pSHEyy5ZCcA9Tw8CFIyzAnjNc1bn1nc0hdmx5Qru3HdixrPR5bLjFgi6UbS6b4uIiMhsVAqg7wOeb4y5oNqLGWPWAS9wXysiIueZ5oZw7gz01s1dREOFv0a8M8wdTZGSABrgyjXT55Cfv76DcDBA0JiCLDM4AfH7bn2Qb92fyGWO3//KjfR0x32D38RQMjdD2m9N1k6vFREREalVpQD660AQ+IIxJjLThdw1X3Cv+fX6bE9ERBYSp4mYM8aqpzvOO6+/KPdcfmMuvwA6MTQOwMUrmnn4yGme6B/1HWflPe49+/PHneKmSp3Et9+2h96+hO+atljY2cegAmgRERGpXaUA+mvA/cD1wE+NMc/1W2iMuRpnHvRLgQfc14qIyHnGK+G2bnB7yeolAHzn3ZvYve2G3BnkpU2RkiZiAIfdwPWVl63k+PAEjx0fobmhurPIP3UDaKfDePlfX17m+vqNywkHTcnz77z+IgJGGWgRERGZHd8A2jr/d9QDHMQpy77HGPOQMebzxpi/cb8+b4x5GLgbeD5wCHi9tT7pBBEROac1R0NMWXLni72GYStbowXr2hsjJU3EwAlcY+EgmzYsA2ByynLjFatLRm6VMzbhvGdPd5z3vsJ/HFfWWr51X4Kulc25x5oizvXfsmk9K1ujZzSA7u1LsGnnHazfdjubdt6RKzMXERGRc0+lLtxYaw+7mefPAm8ELne/8gNkA0wB3wDeZa09NU97FRGRs6y5wfm1MZqapDESon84RcA4Ged8Hc1OCbe1FmOmM8FHhpLE22M8fXIs99iP9/Xzhqvj3LGvnyNDKQyFv2Q8DXnnrZc0hivuM5nJ8tTJ8dz9cChAvDFCOBgg3hY7YyXc5bqBF3cMFxERkXNHpRJuAKy1g9baNwPPBt4D/Buwy/36CvCnQJe19r8peBYROb+1RJ0AesTtxH18eIJlzQ2EgoW/TjoaI6SzU7mO3Z7EUJJQwPDR7z2ae+zkaJpv3ZfgzzZv5Kq1bTxrWRPRohLtgIHlzdNB+t0HBmiKBH1LuQHG01kuWt5EJBRgaDzD2g7nXHS8vfI86nrym5Wd3zFcREREzh0VM9D5rLVPAZ+ax72IiMgCl5+BBjg+kiop3wbocDPSt95ziC/sfpojQ0k622IMjk2AMb5B5Uu7lvOdB47wP1+8nk/f+STgNCfrXBLNddm+Zdd+EkNJouEAv3X1Gr7260NlG5GFg4Z4eyPWwlMnx/jVUwNs2nkHl6xu4djpFNkpSzBQek66nvy6gWuMloiIyLlpxgy0iIiIpyXqlE6P5mWgV7Y2lKzzAuiPu8GuN995PDPFeDpbsh6coPKyziWMTEzSPzIBQN9fvILd227gqgva6B9Jsf22PbnscSozxbfuS/DmF6wtOUMdCwdpioQYn8hwcGC6lDsxlOSOff1MTlk2fOD7834mudKsbBERETn3KIAWEZGqeRlobxZ0/3CKFRUy0MXzncEpxy6nsy3G5fFWAHofOELXyhba3et0NDUwOUXZzPWd+06wY8sVxN2gNBoO8LGbLmc8nWXfsVEmpwqz095dL6j3Rl/NB6djeGlwv3WzfxM0ERERWbgUQIuISNVyZ6BTGdKTU5waS7OypTSAXtpUmpX2TFl8g8r9x0YASE9OcXhwPBfYdjT5Nw07MpSkpzvO7m038OINy9i4qpUbLllZ9gx2OfN5JrmnO85HX39Z2fdTN24REZFzjwJoERGp2s8ec2cxf/MhfuPjdwCULeFurxDwBgy84eo48bYYBueM844tVwDwl/+xN7duLJ3NZYc7KgTk+eXQq5dEOXo6yQm3BLx9hm7dnvk8k/wid2RXKC/1Pt+ZbxEREZkfVTcRExGRxa23L8FHb38kd//4sBOkPnVitGTtjx457nudKQvfui/Bji1XFIxy2rTzDt/mYp96czcAkWCAdHa6LLy4HHp1W4z+kQmOnXbmU7/5+Rfwxd1Pl1y3WLkzyV7DMq8B2vUbl3PnvhO5+1s3d1U1iso7z11cSp7MZHnfrQ/yp19/oKbriYiIyNmjDLSIiFTlll37SWVKzzR/+4EjBfd7+xJ84NsPV7xWubLpSh2rvTPVW547HWB6mev8oLNzSRRr4eEjpwGnhNo7H22AtliYcLDwEHa5M8ne/Ob8Bmhf/tXBgvvVZpD7h1O+z2WtPSNnsUVERKQ+lIEWEZGq+AW4J90Mq6fc7ONqrtfZVn4+c2dbLBdAGzf2/d9vupItz11Tsna1m0l+6PAQAMuaG+jpjhcE2V5wnMxkiZfJ/Pb2JXjfrQ+WHY2VL/9DgPxMdfH1ToxO+F2i7PVmk4UuzpYrmy0iIjI/lIEWEZGq+I1eWt1W2ESs2vPExder1LG6NRoiFDD8+sAAABevaCl/zSXOXh46fJpQwNAWKz0D3dMd5y2bLiQYMPx060sBp3x8/bbbueojP2TrN2cOnj1e5rhSZrrfLXWPhmf+lTubs9jlsuXv+foDdP/VD5XRFhERqTMF0CIiUpVyAS5AMp0tCNSqmXFcrmy6uNw6v0TbGEN7U4SnTowBcNGKprLX9TLQhweTLG2OEPCZmbW2o5HslOVff/l0QfA5lMyQyVYXPAMEjfE9t+3pH5lgaVOEnVuew7JmJ5PuN8orYAzrt93Opp138KHePbnAvtK8ar+M/+B4RmXhIiIidaYSbhERqYpXEnzzd/YylMzkHvcCNW/N1s1duRJpTzhgaI6GGBrPVCwxLi63zre0KcKJkQnibTEaI+V/fTU3hGiJhhhJTbK8xb9z99r2RgD+4SdPVlVuXk4sHPR9bX4m+cTIBMtbnFLyay5s58V/eydvvHoN33nwaMnrvcy3d+ba42W2gZKfT6Ws9VzKwkVERKSUMtAiIlK1nu44TQ2lwWt+1rVcJvmWN15J31++kgM7b2T3thtmFdC1NzrZ24tWNFdc17nEyUIvb64QQHc4a06Opqt6b2NgVUtD7gx2Wyyc+x7L7iHv8RMjKVa0OqXlK1qizrWWxPjYTZdX9d4ev3nVM2X8qykL7+1LVJXtFhERWewUQIuISE0qdcv29HTH2b3thjkFzPl6+xI8cGgQgPueGagY4HlnspdVCKA722IEDLSU+TCgnCvirZxOTfL/vXAdLdEQv3nF6ly2PRio3NW7f2QiF8xHQgGWNjVwfDjFdV0rqnrvfOV+9ls3dxXMmC42U4Bd7gy1Sr9FRETKUwAtIiI18QvIqjn7PBvTXbOdEVpjE9mKAd6EWxb9jfsO+2ZTw8EAq5fE6FrVTNCUBp8BQy57vq4jxkOHh0lmsnzvwSN0LonywKEhevsSfHzXPrJ5851XtDQUjNaamrKcHJ1gRet0ML96SZSjp1MkBmtvGNbZFivJFgNctXYJ5ULocmfNi5U7Q+2X7RYREVnsFECLiEhNKnXLng+1BHi9fQnueXowd79SNnVNewwwLGkM5Zp6LW2KEAsHeNM1azmw80a2bu7iyOnpOc4D4xmePDHGo0eH2XbbQxwZKpzx/PqrOguy7V5Tsvxy8pWtUY4Pp0gMjdf0c4iFg1y/cXnZbPHAWIbnre/g73/7Kpoizj+bzrZoyZzscqqpKBARERGHAmgREalJpW7Z86GWAO+WXfuZnCrsou0XbK/taOSRo8MMjGV4z8ufTTBgeNGGZSQzU1y5ti13veKu3N71U25GPN+t9x4uuN8/4gTYxRnoY8MpDrsZaL/xVr+xYWnB/Q+/9lLu3Hei7IcJz5waJ94Wo6c7zodfdxkA//Y/XlDVP5MzXVEgIiJyLlMALSIiNav3GedKagnwagm217THGE87wej1XSu4vLOV7+85CsBVbgBdaxb2dF53cnA6cIPTPMyzakmUITeT3RgJsuOmwg8j3vKidc5rR9M0N4T417c+H3DOdPvtJ2ttrqHZZZ2tAOw9MlzVnrdu7iISrHyOW0RERBwKoEVEZEGrpWS8lmC7f3i6/Pp/ffle0pPZ3Hnm//Gv99Dbl6g5C1ucTe4fdgLo/JFaq9yO3Pc/M0i8LcZNz11T8GHExStbANh3bITJ7BQ/ePgoBvifX7qXQJnz2p54u7PXi1e0EA4a9h45XdWee7rjvPKylbn7xee4RUREZJoCaBERWdBqKRmvNtju7Uvwzfunz0UfGUrx6LHRgvvbb9vD9RuXl1zPT8BAhztqy3uPj3x3LwC/8/9+lTuHvWqJE0A/1j+SC3rzX/PR7z2au5+anOJrdx/CKyL35kTni4ScX+VeBjoSCtC1qoW9ieoy0M5rgrlu4ttfvVHBs4iIiI/q5neIiIicRT3d8aqCOm/NLbv2c2QoSWdbjK2bu0pee8uu/aQnS88w50tmsty57wQ7tlyRu17AmLJBbNAYrr2ogwcPO1nf6c7hTon40dNOQA5wxZolAFhbmhkv1zCtHANYIBw0vPGaOF/51aGCYLw5EuIXT57kwm23E3T3HPf5WQA82T/K8y5sp+/gEHsTwxgSM/4MRUREFiMF0CIicl6pJtiu9mzzkaFkwfWKA2NwMtw7tlzBiZEJfv7EKU6PZyp2Dv/hn74k91i8KICudl/5IfzSpmjBtXr7Etx3cBCvl5oX8Hsdu4GCn4+1lif6R/mtq9eQzExx5/5+vvLrg7n9+73ubOntU3AvIiJnj0q4RURk0an2bHPxukrl5Gs7nLWHBscrNjNragjR0uB8fr2mqIS72n0FA4bGSJBM1vLT/f0sa44QdUvNy3UO95TrSH70dIqxdJYNK1u4vLOVp06MLdi50N4HGMVjvPxmgouIiNSbAmgREVl0yp2VLubXqMyvA/ma9kYADg2MV2xm1tuXyAWoH/3eIwXBX3X7CmCt5bpnLwfgwcOnCzLZM2Wxi59/ot85+71heTPp7BTlQ++FMRe6lpngIiIi80EBtIiILDrlMsm/98IL5jTb+qHDQwC84yv3MzYxSbjMaKjrNy5n+217crOkT46mCzKolfYFTpfv7b+5kSkLL3zWUpoiTrCdf/55pix28fNeAP14/wjfeeBI1a87G2oZUyYiIjIfdAZaREQWpWobk1WjuHv2UDJDfvzsNfCqlEH19uK3r7f+yz0cGUrynLXtgJPp9kq1f/bYCXr7EvR0x9m6uavknLanOKve25fg737oZG8/8p29+FR+AzCensy9R7XqfV65sy1GokywvBCC+2rpDLeIyLltwWWgjTG/Y4y5yxhz2hgzaoy51xjzLmNM1Xs1xgSMMS8yxvy1e63Dxpi0Mea4Meb7xpie+fweRERkcSkXGHvB6Ff/5wtypd5zyaCuW9rIwYFxjrpr/+1Xz5DOOp3ERyeyuUx2fhY7X3FW3TtPPJ7OFuzXz+B4pqbzxvNxXnnr5i6KR2H7ldovRDrDLSJy7ltQAbQx5jPAV4BrgLuA/wKeDXwa+KYxprphnPAsYDfwQeBSYC9wG/AM8JvAt40xXzSm+NewiIhI7SoFwNWUV1eTQV3X0ch4OstDCWdU1kTRGK78s8DeOe2nd97Itc9ayvMubC84rw3Vj8zyew9wAsJNO+9g/bbb2bTzjlwg2NuX4H23Plj388qvvbKTUN6v7tmU2p9NOsMtInLuWzAl3MaYNwDvBI4BL7HWPu4+vhK4E7gJeDfwySouZ4E7gFuA/7LW5n5bGWOuA24H/gD4GfDF+n0XIiKyGPmVFgOsXjIdHJcrr642g7puaRMAv3rqlO+acoF8R1OER48NA4XlwzMknGd8j+KRXl429d5nBvjWfYmy87K9dV6mvNZy5gMnx8i458dfd2Unn3pzdy6IPxdKonWGW0Tk3LeQMtDb3ds/94JnAGvtceAd7t1t1ZRyW2uftNa+zFr7g/zg2X3up8BO9+7v1WHfIiKyyJXrnh00htZokEho+tdWpTFYM7lgqdPl+6HDpwkFyhdQlctkdzRFGBxLl5QP+wkag3FvK72HXzb1a78+NGNme/tte/hQ756ay5n3HnGy7y0NIQbHS7+nepRE+2XV62EuFQgiIrIwLIgMtDFmDXA1kAa+Ufy8tfanxpgEEAdeCPxijm/Z596umeN1REREcgHwjv98lOPDE7TFwixvidAcDZddO5sM6Zr2GAED2SnLxSuaODyYqiqT3d4UYSiZ4eO79s0Y2MbCwVxAX5xhLn4Pv6ypX+Y5nxdoF68tbqhWbO+RYSKhAM9d186JkYmqmrLVwi+rDtQlqz2XCgQREVkYFkoGutu93Wut9atjuqdo7Vxc7N4ercO1RERE6OmO88ttL6MxEqSnO046a0saec1FQyiYKwe/cm171ZnspU0RrIWjQ6mK129vDBdcw8uWL4k5HwKsao0WPO+XNfXLXBfzC7TzA3MvG3zhttu5aPv3+dzPnsJaSzI9yeB4uu4l0fN9Rtn7mTa648eWNkXOqTPcIiKyQDLQwHr39pkKaw4WrZ0VY0wj8Mfu3W/N5VoiIiL5AgHDs1e28MjRYY4OpXjV5as7+2qPAAAgAElEQVTqdu3evgQnRycA2PXwMV68YRm7t90w4+vamyIALG9poH9kwnddYyRUEsj1dMdpawzzB1+8h//7O90878KO3F7GJiZLrhELB3nD1XG+dV9ixmx30JiyQbQXmBdng721mazl/oNDWGvpbIuSKPPBwGxLos/EGeWe7jj/9chxbt9zlL+56XJedfnqul1bRETm30LJQDe7t2MV1oy6ty1zfK/P4gThjwCf81tkjHm7O0Lr3hMnTszxLUVEZLHYuKqFBw4Okc5OsaZOGWgvmPQ6b49MTFZ91nepG0C/6Zo1hIP+2WG/IHFth3P2+tDAeMFehpKZgnWhgGHHliv4654r+NhNl+O9U1ssXPK+sXCQN79gLdFwoORxr5y5UpfwySlL1sIf3XBx2WvXUhKdf+Y5MMO573oZcT98GEmVfgghIiIL20IJoL3fWLNtClrdmxjzF8B/B04Db7LW+n4Ub639nLX2GmvtNcuXL5/PbYmIyHmka1VLbj5z/giruZhLaXF7oxNAX9a5hFdd5p8R9wsSvTL0QwNJ372AE9S+4tKVALzs0pVY4IOvvoQHPvxKbvmtK1nZ2gA4AbUXaL9103RRWWs0VFDOXE3Wd9OGZWy6aGnBXmspiS5uQlYuIz4fZ5RHU86HD+Wy+CIisrAtlBLuEfe2ucIa77mRCmt8GWPeC/wVTib7N621e2dzHRERkUq6Vk0XSsXbGutyzbmUFi9tdgLoU2Np2hojxMIBwFTdyCoaDrKipYFDg+MzvudlH95FvC3G7197AQAr3KC5pzvOa56zmo1/8QN+94UX5ALcUDBAwDjv/7qrOgsC30qjwTynxtI0NThntJ+9spkf/ul1JWsqjcqaaRb2suYIH7rx0rqfUfYyz2Pp2uZwi4jI2bdQMtBPu7frKqxZW7S2asaYPwI+ASSB11hrf1nrNURERKrx1InR3J//4It312UM0lzGH3kZ6MGxNImhJOuXNdc8SmttR2OuhHum90wMJfnED51plCtbo7nHQ8EAq9uiuUw2wN0HTnFpZysXLmsiMVgYLJcbDeZpcEeDDY6lOXLaeV25Jmkzjbma6QOId7x0w7w0+BpVCbeIyDlroQTQ3lipy4wxfr+Zn1e0tirGmHcBnwJSwOvcOdAiIiJ119uX4G9u35e7f/R0as5ziaF8MFltaXEkFKClIcSpsTSJwSTx9hg93XF2b7uBAztvZPe2G2YMEte2xzjsBrhbN3eVnF0u5pWw5wfQznUaOTQ4Tm9fghft+DG/emqAAyfHMFCSbe7pjrP91Rtz973u3nE3iwxOBtoLnEcmJhlJFZ7Lnqn03e/DgKaGIB1NER47NquitxmNehlolXCLiJxzFkQAba09BNwPRIA3Fj9vjLkOZ2bzMaDq7LEx5g+BTwMTQI+19kd12bCIiEgZ8zUGyRt/VEvWOF9Hc4QBNwM9m9FaazsaOXo6SSY7RU93nD+87qKqXreipaHwOu2NPH58hO237eHIaSfwHZvI8uixEZ4+OYYtOoO8rNl5/bff+SKe3PFqnnYD/t9+nlOU1j+Son8kxfplTYDzgUW+mUrft27uIhgobRy2pTtO18oW9h2vfwA9NWUZTZ/dADq/cdqmnXfUpUpCRGSxWBABtGuHe/u3xpgN3oPGmBU4nbMBdlprp/Kee7cxZp8x5kvFFzPGvM193QSwxVq7a/62LiIiMr9jkGrNGudrb4zw9KkxRicmWTOLxmZr2xuZypslvbbdOdv94/dd5xuQG6CpobDVytqOGKMT2ZIPGbJTlnTWcrqos/fdBwaIhYNcHl9S8HhzQ4hw0LDv6AhTFq5e1w6UzpD2G0ntZZ5fe2UnsXDAPRc+7YePHCcUNDx+fISpqfr2Nx3PZPE+JxgpE0DPd3A7U1m7iIhUtlCaiGGt/aYx5h+AdwB7jDE/AjLAy4BWoBcnm5xvGdCFk5nOMcZcBfwTzu/vA8CbjDFvKvO2J62176/rNyIiIouWX+Oreo9BqtXSpgh3PX5y1ntZ0+F24h4c54KljRw4OUYwYFjb3sjWzV0F85oBAsZpwFXMG4nl5/BgkrbGSK7xV2IoSUMowO0PHS34wMAYQ0dThL1HTgNwzbp2vnnf4VwG2gsSy8W+Xul7b1+Cv779EUYnsjSGAwQDhqz7guPDEwyMpclkLV/YfYAv7n66pAlZpeZklYzmnXsuzkAXz772glugbmexK1VJzMd5bxGR882CCaABrLXvNMb8HHgXcB0QBPYBXwD+IT/7PIM2pkdjbXS/ynkGUAAtIiJ1US6YnI8xSLVqb4pMj9aaRQD96NFhAH73878m3hZjeXOEte0xIqFALuj62x/s4+jpFK3REB1NkbKB+pr2ygF0YijJE/2jBT/DicmpskFke2OE/W6J9ZVr2wgYODpUedRW0DizqoGC9xjPlP7vRSbrBNN/ffujBfvbftse7n1mgG/dl5hVoDs6MZ1lLw6gz0RwO59VEiIii8GCCqABrLVfBb5a5dqbgZvLPP4TpgNoERGRMyJ/PFKtmcn5tLRpOhtc62xqL9PqSQwlOTKUZGPeuK6e7jg93XGu3fFjrn3WUu5+eqCkgRg4JdzgZKjzs8PRcIBUZorEYJJ//vmBqoLIpc0RrFt/tqY9xsrWaO5ctV8wOGUtPd1xNu28o+L4qkqSmSxf+/WhkpnRfoFucab6jdesAaApEmRkYrLgeb9i8XoGtwu1SkJE5Fyx4AJoERGRc5kXTC4k7W4AHQ0HCoLpatyyaz+pogytBQ66c6HzbVjRzOP9o/QPT+RmQOdb3tyQC5a9T7k722K8/5XPZvu39/DTx/p9Zz8XB5EdTc71WxpCtETDrF4Sza2ZKUica0BaHDz77bFcSfZn73wSgJVLopwcSZVULJRTz+B26+Yu3nvrAwUfYCyEKgkRkXPFQmoiJiIiIvOgww2aO9tiGL/OWj78gs2xidKg76LlzTx6dJh0doqVLaUZ6P944AiTbml0JBTg//z2VezedgM3PXcNrdFQ7px2OcVBZEdjGIDVbVH3NsbR0yl6+xIMJ9Nlr/Gel19c9lq1Cvr8DIuvW64k2yulX70kykiqtKFasXoHt695zmrCQZP7AGNla0NNHd1FRBY7BdAiIiLnucfcs8JPnRj7/9u78zi5qjrv459fV1dv6SSdPXQDIWwBQiSRTYjKpsTBLYLgMr5GfEbHcXtEMWNwBtBHMdGIOqPj9sw4jgP6sNouAQKyCgYkoRMhkLBlrey9ZOl9Oc8f995KdfW9taU6veT7fr3qdVN1lzr3ntzu/t1zzu/kndk5KtgMSxJ28tRqevymzfQu3EFrbLA+GNtc35CgviHB7gNdoUm/IDyIDFqgjxnvla92fAVbGlu54d6/ciAtuK8q8+bQnn/yZCB8+qp4iTGhKo4RHSAHZfnQ+ccNmAs7rIyZWrqnj6uM7LIdKIuVFDW4rW9I8KYlD9PZ45LX5LvXzFXwLCKSBwXQIiIio1h9Q4L/Wbk5+T7faYsWLZhFZTw24PPu3r4BxzhlanXy39PSunBHJcj66u/WJRNwRQkLIrc2tQLw+Mt7mL/0ERo2N9ProD0kIViFX/6mVq9leuG8OiZWxakoLUnOq73s6rNouOlyNi59J7dec1boOcdjXhKybyycw/++7JTk5+MqSkPLmKmle/r4gV3cU9VUxZlUXVbU4PmGe59n70HvGrR2eXXxuzWavkpEJB8KoEVEREaxZSs20NnTP6gMEl7lYuG8OpZcOYeayni/z/e19wwIxF/ZfSD578/86rl+66JaY1vauzN2Y66rqQxNzPXbtduT7xMt7aza0hJ5jGY/cG70l7sPdLDnYBdfvPzU0Hm1g3Ouq6lMBthnH19DTVUZ751bC3jd1QMLZk8PDXQXLZhFPNa/NbvUb/kOWugrSvv/KRZsv+CM6ezY10FHgcnO0kVlJl/+/M6QrUVEJIqSiImIiIxixZi2aOG8Opat2EBLe3e/z1MzT9c3JLhl+frkul37O/tN7RSV2CuTqPG/y1ZsSE4zlYspY8vZfaCT5tYu6hsSfO336wD4v09sZOrYitDgNz0Z3KK717J6Swsn3nAftTWVnDNjAgBnHDOOV/ccHJBt+5LTpvDo+j39yllTGWfe8eN5+vVmxvsPJL7w9lP53kMv0+E/5KgdX0FLew8XnjyJO1ZtZWtTG6dMG0smucxJHVXfB9Om0hIRkczUAi0iIjKKRXUjzjeRVrZAPNMcxhDeFbwyHmNCVf+W7UAwZ3NYcJtP8F8ZjyWThz22YTc33Ps8zW3eg4A9Bztz6s5e35Dgd2u8Fm+H1+L9h+d3UBkv4ewZE3hx+z5uuPevJPypqBIt7dz29JYBDwwuOGkS08dXUl1RSnW514bxphMncXrtOKaO9caUb25qp6O7l417vS7qmxsHZjtPL9sN9z7f77vDzimqvtNbyIeL+oYE85c+wszFy/Mety8iMpgUQIuIiIxiUYFrvpmdswXi2QLssG7RS66cw83vnh1avluvOSty/G+uwX8QhH/w3OOJlRgPv7Q7Y5AfJawbfG+fo6fPcfLUajp7XOjY63SPv7yHAx09jC0vZYwfQB/s7GFzYyuNBw+17nf29PGTx73prjY1tmYtWy7ntGjBrGT38UCsxCgvLf6fgocb/Ob6UEBEZCioC7eIiMgoFgSh2br4ZrNowawBcxanBuLZ5l4OyhL1vfmUL6ws6SrjsX4t2BOq4skEWumytWhHre/u9QLoXLV19XKws6dfC/TBzh6aWrsHbBvMlb2lKXMLdK5d9BfOq+PfHn6Frc1t9PQ6amsqOevY8dz3wk7au3qpLBuYNK0QYXNfp3blj9ontf7bunoiHwooY7iIDDUF0CIiIqNcpsA1n2NAdKCbLcAuZvnCyhKMOY4KwieOKeNgZw8dIS3F2Vq0ox4OjC0v5dWUxGnZxGPGwY4eqssPBdC793dEbu/I3IW7viFBiUHYcPD0c+ro7mVbSzsfmz+Tr1xxenL/+17Yybbm7OOsc5WpRTysjsMC7ij5dN0XERksCqBFREQkJ5kC3WK1dBejLGEmVJXR0+vY2tzWL7FXLkF+VIv3mXXjWHr/+oi9+ouVGJXxEg529jCjuirZhXvj3ugAOV4CT766l5mLl/e7nvUNCb76u3UDkrpFnVN9Q4JvLH+Rrp4+7l69jTOOGcfCeXVs3HsQgLd/7wnq8qivTEnL8k1aF5UdPEy+4/ZFRAaDAmgREREpimK0dA+WSdVl7D3YyYUnTeLxl/dikHOQn/pwILWF9JXdB3Ma+zyhKs65J0zgjy/tZl97N9XlccZWeH+CbfbHOJfFSujqPXSseInR6xx9zgv2g67QqzY3cc/qRGTQmZ58Lb2Ft6m1K3mcu1dtS+6XS1frsOOl75dLV/5UubYqFzJuX0RkMCiJmIiIiIx6E8eU0dzWTZ+DOXXjQ+d/zmThvDqeWnwpHzz3uORnUWOqgWSitO9/YC4NN13OW06dSp+Dnfs7GFtRSnlpCbESY6MfQH/+baf0S7BWXVFKX1rX7PbuXm57ekvGFts+5/qdU1SX6l8/szU5dVbq57kkVCsk2/qiBbNCk4tFBdZlKdnBg4Rzg/lwRlm/RSRXaoEWERGRUW9iVRnNbV28tGM/F506taBj1DckqF+TPbCqq6nkqcWX9vts2thyAJyD6vJSzIwxZTG2+knCrjnnOD5zycnJ7WcuXl5QGaeOK+/3PqqFt9eFz6Mdtn1ql+2o2bdTs60DfOmutfT0OWoq43z1PbMBBrRcX3fHGqriJcRjNqBb/czJVby44wCnTK3moS9eFH3CIWXMd/hAIYnPROTopRZoERERGfUmjinDOa/V+LTphSXMWrZiQ2gSslRRXY2njatI/rva7749tiJOd6+jxLzypSp0vO/VZx+b03FiFj7/c4lZv9bX9CmloqR+z3vn1hLzp8y6dv4JLJxXFznWua27r1/wXFFawpIr5yRb3xMt7biIYD+qjPlOe5XrVGAiIqAAWkRERI4CE1IC1FkFBtCZxuumzm0d1mrZL4D2E4iNKfe6Ok8cU54MOANhXaEzGecH5SdM7j+t1qIFs0iPlSvjMT50/nGhx+91rl/wmUuSr/SHBnsPdiXnzd7lZxnPZaxziUFNVZyF8+pINLcTjxltXb20tIUnSwscbgCcb+IzETm6qQu3iIiIjHqTxhzq2lxoC3RUgqywLtvpJleXYeZ14Q4SiAWZuCdXlw3YPgjCr79zbWh36yAmDror/82c6Zx24wPJLuHgtcx+876XcM7b3vllDbo3nzNjYujxU4PPTNNKgZcg7eZ3z+730CB1nx37OpLlzHYsb4x4J/vaujnQ2cM5MyawanMziZb2fg9A0uUTAId19Y4qW9Aar27cIpJKLdAiIiIy6q3Z1pz89/t+9FRBSaIyJcjKpjRWwuRqL4gPWqCD5ZSx5aH7LJxXx63XnBXaUvyJt87slwitvDTG9HEVbG32AuigW/PuA52AFzwHZQ0CwoXz6pJZvtOljgPO5LwTJgwIMIPAta6mkp1+AJ1Pi3rDVq+uzps5EYBtzZkD76hu6iVm/ZKCRXX1vuS0KVSUDvyTOL01XkQEFECLiIjIKFffkOCHD7+afJ9o6SgoMFo4r44lV87ply07n+zQ0/wEX2Mr4kD2ADr1O2vHV/T7/A9rdwwo/3ETqtjW5AWbuXZrzjRGOpf5mZ94Ze+ADNYrXtgJwNkzJiS7cAfnURI+9Lqfla81AocC6Gwt14sWzCIeG3jgXuf6Bcpf+/260Gvy6Po9fPKik0KPrbHQIpJOXbhFRERkVFu2YkPklE35ds8tdK7r+oYEr+46CMBnf/UcX7ni9GQX7inV0QF08J3Qvzv39n0dAzJFHzuxMhl85tqtedGCWf0yUAeisnSna+/uG5DBeuf+DspjxqnTqvnd2u10dPdSEY+xcF4dS+9fz/ETK3l510Fa2vuPbS4vLaGzp4+nXtsLwOza8VTGYySa2wd0vb7ktCk8un5P8v2c2nE8t3Uf4I2lDpsCLOqBwPaWdk6cMibyHDUWWkRSqQVaRERERrWhThIVdB0OgvjdBzq54d7nk62zmVqgA8tWbMg4Vhm8Fuid+zvo7OmNbFlO/zxoGa6pjOd1TunlSNXb5+h1MH28913Befb09rH7QAfnnziJNTdfzvc/MLdfa/4333cmsRJj3fb9lJeWMLm6jNqaClZtahzQ9fq2p7f0e782sZ+437ydHjxnU1tT2W/seNh6EZGAWqBFRERkVItKEnWkAqOo7tRPvuK1tP77o68yubo8Y8t2Lg8Bdh/owDmY9S8PhG4bNV47mGYqvUU4m/T5m1P19Dmm+5nHd+zrYMakMew92EWfg+l+d/Sw1vzvP/wKW5vavcDajLoJVax8bW/k9wR6+xxWYpwwyXuIkG26sUBwTVa+1kh1eYzevv4PBHId4y4iRw+1QIuIiMiodjjJv4ohKvgNQsLmtu6sY7KztSjXNyS457no/SdUxTOO185liq6PvOn4fi3GH3/ziZH7jCmLJQPloAV6xz7vO6aPq4jcb8ZEryt13QTvvOpqKrMGz4GePsfs2vFUlcXIYag1JUbymmxtbuOUaWNZcuUcpvo9ArJdMxE5OqkFWkREREa1IABKn77oSAVGuUzhlG1MdthY5dSHAMtWbKCrJ7rVtaqsNOP5Rk/lBK8veWfoPomWdn78+GvJKbJSXXra1GQAHUxlFQTS08dHB9B9zjuHP72yl/lLH2FKde5dy8eUxTBzNLV6Lelh5er/XYf+b2xtbmPecV5G8Xec6U0Jdu2FM0dU8Bw2RddIKr/ISKEAWkREREa9QpN/FUNUoq50mVqBsz0EyDaeO9v6sDIaMGta9JzZf/ETloUFqU++upc/vriL6vLS5FRWQSAd1QJd35DgLxsPTTeWaGnP+uAh1axp1Ty4bnfyfVCuitKSAUnkAKrLvV4JPb19bG/p4D1nea3eFXFvSrDNTa05f/dQC8bZpyZzS08yJyLFoQBaREREZBClB78lZqFZrrONyc70ECBbK3cuxw7KmGhpJx4zenodl50+LXT7+oYEX6l/IfJ4Qbf0sRWlyZbnnfs7KIuVMHFMWeg+y1ZsoCeHDGAlBpPGlLHnYBfgdbVubutmY2MbXb0DA+Xu3j5iJUZvyrENOH5iFeAF9r19juMmVCXXz5hUxebG6MRiw02macuGUwCtVnIZDTQGWkRERGSQLZxXx1OLL2Xj0ndy6zVnFX1Mdtg473yPHZTxstOm0t3rzaH8q2c2h47NDgvY0rV397L7QCf3v7CT+Usf4dmNTUwbX45Z+AjlXLOi9zlv+qzzTvDmiX7zKVMAaGkLT4LW62DimDjlpSXJ8dtvOHZcMtHY1mYvUD5u4sgNoIc603wuglby1OzphczHLjLUFECLiIiIHEHB1FGpCbkON1lV6jEBYn6Qmu+x6xsS/MnPDg7QFJHgLN/ALNHSzpqtLZSWRKf3yjUrelVZjIOdPbxnbi1lpSU8tt7rtj0tQ3KyPQe6qIiX8L0PzOWpxZfy5lOmsKWpjXtWb+XTtz8HwBfvXJM8Ty9reCetnT25nuJhq29IMH/pI8xcvJz5Sx+JDCzDtst12rLBkGu5M7WSi4wk6sItIiIicoQNxpjsYhxz2YoNA7pBh3UFziUxWro+Bzv3dUauz2WsuOF1yQaYe1wNp00fy1+37aOstIQvL5jFV+pfiNx/X3tPclzwzMnV9PQ5vvKbF+j0x0fv2t+ZXB90797S1Mbpx4wbcKxid0XOdQxz1HZXnV3Hnc9upSslY3l6z4PB6D4dVp7r7ljD136/jpvfPbvf8aMeuiRa2qlvSKgrt4wYaoEWERERESD3rsCZuoxnkik4DmuZT58669gJFclprf7hl6to81uIu3r6+M5DL3PV2XXJ7WMhXcWDhwFbm7zu2Z094Q8LTpjkTae1uXFgIrHB6IqcS+tsfUOC6+9cG7rdo+v39Buvnt7zYLC6T0d15Q+bmi1Ta7i6cstIohZoEREREQGiW5bTg5+wrOCXnDaFR9fvyZgobXxl5j89M7Wi1zck+NJda5Pvt/tZvQOJlnbuWZ1IBo4zFy8PPU6ipZ2fPvFaZBm2t7Rz/CSvBTpsHPRgJOzK9uAiCIDDrmmw3dzjagAoLTGe/PIl/caaD1aSsUxd+dOPv2jBLK6/c23oOQzHhGciURRAi4iIiAiQfb7pVNmC3bDu2D29ruDuurlk6U4NxKIeBsTMkgnEwtTWVPLo+t2YwZL71/PLlZtzmjIsl3HhUd2osz24yJa0rbamkvU79wPQ0+fY397D+Kp48jujuttv97tPF9q1O1tX/tRrsnBeHbcsfzGZPT3TtiLDmbpwi4iIiAhQvARnwXFqKuP9Pm/t6i24u26uAVawXVg388p4LLIVN1h/yWlTuOHe5wk2S+/uXGjCrkzdqBctmEV6j/PUBxeZzr0yHuO6t53Cpsa25Njtva2d/b4zyvjK+GF17c7WlT/1mhzs7GFvaxdjK8Lb7wpJeJZrAjORYlIALSIiIiJJqVNuPbX40oK71S6cV8eY8oHBUqGZl3MNsILtoh4G1EUcJ2bGkivn8Oj6PaHdna+/cy0zFy+ntbOHeKx/tJvLVGGZulFfMmsqzkFFqfeneU1lPPngor4hQVTycjNYcuUcTj9mHL19jgtPmgRAU2tX5Hemltls4Lj0bPWTGrQuW7GBq86uIxZSvvRr8tKO/TgHHzj3uMhp3PIJiDUtlgwVdeEWERERkUFRzPmJc8nSnR60RXUzD+umHgSsX7hjTeixg5brlvbufgFjzODKN9aybMUGvnDHmgHjwYNu0ZmuxZOvelOH3f6J8/nEL1fR2tnLdXes4Qt3rCGqvdyA2ceMY+G8Ou5ZvQ2AC06axP97diuNBzuTx46y5Mo5keeaaGln5uLlA7p0h2Xdvmd1grEVpZw8tZod+zqTXbpvfPfp/a79usQ+AD7xlhM5s3Y8X7prLT19jjr/O4CcMpEHBmtct0g2CqBFREREZFDkmpQsF9kSl+U6fjfsOKn75TJFVzBb1D9fcTq33PcSd69OJDN6J1raue3pLcltEy3tLLprLWYQ1nt8fGWcRXd7ydH+/hfPsr+jh2Cod1TwHDNj5uQq1m3fzwmLlxPE89+87yUAGv0W6KhzKTFwzkUmewu+O31aqqigtb0bLjhpMtdfPou/bGzimp+uZGJVWb/t1m3fz+TqMqaOLfda1tck2Huwkz987i0AzF/6SGTLf/BgItex6IMxZZdIQAG0iIiIiAyKfJKS5aJY82dnOk4uLd2BEn8wZPp0WOm6I5KflRq0dvUkp+Zqae/J+p3gtYZvaWpLBtjBctd+r+X5yVf28rfnz2DRgll8+Z6/9itfiXlzcn/hzrXkKpiWKtM1CbrGb21qxYB/vO25fq3Lv2lI0NPnePO3HmXRglkcM76S57ftS+4fFRAHAX56i3TUw4FgXHeuLdki+dIYaBEREREZFMVKSnYkBWXOxdL71x/Wd5XFY8ngOR8xM7oy7PfEK3sA71w+cO5xgNflu6YyTixqQHUW7d29oXNrB+omVFLfkOBf6tclA/qg9X3R3WuTGdSDgHZfWxeNrV10dPdS35AYkEQtqgzB+OxFC2ZRFusfyhQ6rlskH2qBFhEREZFBU6xW4yNp4bw6lq3YkLUrdyHBb6q2ruyt3Okq47GsreOtnYfWTx1bDsC6/7OAt3/3CVrau/P+zkCvcwO+Px4zunsdtTWVLL5nYCt1WOt7e3cvf369EYD/WbmZ7z70MllmKEsKWqoXzqvjyVf3crc//jto7Y4a1z3apslK76ZeyHAGKYxaoEVERERE0mSbomkoTKiKZ8wkHigvPfQn/ubGNqaOLaeqrPSwg8i6mkpuWXhm8n1ZrIS3nz4tuS6f4+9r8wL5nz7xWk7d5QOp4+dTp0n746yWqtwAACAASURBVBcvSnbtzrbfSBeWgfy2p7coI/kRogBaRERERCRNevfzfMw/aWK/9+nTXmU6XrzEmFDlBYZBl+m6mkq+/4G5NNx0OQvn1WUM7ksMJlYdCiw3N7UxY5I3P/ThBpFtXT20tHsJyirjMarKY4yrjDO5uoyKeCyv408d57WM7z3YFblNaUh387aunmRguLmpLfl5U5t3nEULZvV7gBCUtdBx98NRpunJAuq2PngUQIuIiIiIhEidEztbqy+QHJO7r6OHstKSZND2uUtPTm5TV1MZmV0bYNnVZ9Fw0+VsWvpOXltyBZtC5uNODe6hf6B9/syJdKfkNNvc2MrxE8cAh9+q3tzWzdL7vaDsradOpqWtm4YtLcly5Hr8yniML13uXZtxFeEjSieOKeOM2rEDHjYECc3qGxJsaWxLXvMmPxBfOK+OD513XHL7injJsB93n69cW/pHW7f14UJjoEVEREREsgjLzh0vMaorSmlp66a2ppILT57EXau28UJiP2WxElo7vazaieYOAH732fm84dga5i99JHR8dV1NZc6BXtTY8mUr1vOXTc309Tm6evvYtb+TE/wW6KgpvKLGe8dCprnq6vWi88vPmM6KdbvYsOsAV8yZ3u/410WMQw7OMRifu+T+9cyaXs0zrzcNGAN94UmTeHH7fsrjJXR0989y7rWurqextYvZdeNo2NKSbIEGmDK2AoB3zJ7Os5uaeO/c2sjyFNvhTqGVbf/6hkTG6cdSZeoRkMv3aCqwcAqgRURERESyyDZ/dDAuNdDV28fPn9oIwO/WbqestITTpo8Dij+9V6pJY8rp7XPsa+9mz0FvWqvj/QA6OI+wQCisPJm6CV88a0ry36mt85kSsNXVVPLU4kuT748ZX0F5aYyqshi9fdDR3UttTSX72rsoMWNTY2tkcrFEi/dQYu5xNV4A3dqZXPf6nlamjStnfGUpja1dnHjDfUckCAz+DxQ6hVa2/YP1uQTPmf4/5fo9mgosnAJoEREREZEcZMooHjYuNWg5be/uJR4z7nt+R79jDEYL36TqMgAaW7vYtLcVgBmTxmTcJ9+W6dIS40+v7E3OKX3nqq3Mrh2fPE6uDwhqayp5dlMTBzt7+dp7ZvPRC08A4JqfrOTRDbvpc9547qa26MzhwfRYjSljqTfuPUh1eSn1a7YD9EuslXq+xRb2f6C9u5fr/Tm3w743taU3rGU5GMscPJgIe6hRYvC206fy4Iu7AW/MfaZu61HlzPQ9qWOqj/aWaQXQIiIiIiKHKdt40+5e1y+AG6zpvSaN8ZJz1Tds43+e3gzAp25bzZffcVrG78u1ZdqAqdVl3HDv88nW4X3tPQPODbIHWrXjK2jxg+O5x9UkP585eQx/2dQEwCcvPonvP/RKZGv4g+t2EisxmttSA+hWOnv66OwJ6/q9oWjXPb2bc9S0Z73OhQbv6S29US3Lwf+tqP9jfQ7efsZ0HnxxN+fMqGHV5ha+cMcalq3YEHrdo46T7XuChxBHe8u0koiJiIiIiBymXDJQH4nMyBPHeC3QP3vidfa1e2Owd+zrKGhao/RkZQaUxox9nT0ZWyiDfYMEbOlJ0AJNrYeC3k/dtjpZvraunuTn//3nTVx1dnRwtmt/J5XxkuSxmlu7aG7rjpxju1iJtcKmksqUXT39+tQ3JLj+zrU5TeEV/N+K+j82rqKUzY1tGPDXxH6AjNNZZZvqK2p9zCxrvR8NFECLiIiIiBymXDNQD3Zm5FWbGgHo6g3vCpyvIBD++Jtn4vBa0ls7Dz84rW9I8MC6nYf29YP8f6l/nhWpn7d0cM/qRHJqrzCtnb08v20fABsbvW7rwYOEdPlMtVXfkGD+0keYuXg585c+0i8QDevmnG1kcqKlnfqGREFjmesbErR2hndlP236WDY3tVFSYnRFtLqnWrRgFhXx6Km+wv4vV8ZjWVvIA5mu22igLtwiIiIiIocpvdtyVKbkw52LOZP6hgTfvH995PpCg/f6hgS3PbM563b5nNuyFRvoDgnyf/3M1tBxwOWlJZGJzRzw8q6D1Dck+Nrv1wHQ3eONO0/9jmyJ2oIu2UFrcmop0rsrZ7qW6fumWnTXWnqdi0yOlmrSmDJufNcZwMCu9AATquLUVMXBjC2NrfRGHDS9rAvn1bG1uY1bH3wZgDFlMW5536Ex08mx7HevpbvXUV1eyjcWnhk5Jr7EjPqGxFGTgEwt0CIiIiIiRZDabfnWa84KbcUrRqbtKMtWbBgw5VOqQoP3bMeF/M8tKgCNauXc197NkivnRB6vq7ePG+59nmZ/TPWBzl5wJFuuy0uj54Oub0gw92sPct0da5IBYlgpUltzM13L0hIvkVeY7r7swfPFp07GDD564QkZk4dVlZXyxuMnsrmxlU2NbVSVhfeACCvrlGpvrPzUseXMrhs/4LosnFeXbMW/7PSpLJxXF9nLIhjjHTyAiEqkNlpaohVAi4iIiIgUWer4YcObwilTZuRiyNQqejjBe7bW1kLOLdM426jtF86r6zdlVrr0wK27z1FVVsr/mj8TgHecOX3APkGLaUt7dKbvVMG1yNRlv7sPxpQV3tH3kxedzElTqlmztaXfd4aV5YRJVeza38m+9m7edvrUnB/arNu+n7HlpVx2+lQ27DyAS3tw0d3bx+4D3tRgiWbv+4P/02GChwuZHowUMg5/OFIXbhERERGRQTBYmbajRGWCjlnmaY0KPW76vM75iJrq6qqz67hndSJyCqyw/UpLLDmdVbrtLe2UxqCzp4/TbnyAmN+1vi5lqq5cEnkFSsyYuXg5tTWV/M2Z07i3YXvodvvau6nLkJk7k+vvXMOxEypZs7UF51zk9a+tqew3x/c731DLpadN45b7XmLPgU4mVMW5+d2zQ+v9he37OL12HKdNH8ev/7KVXfs7mT6+Irl+1/4OnPOubep3v3duLdfdsSa03NmykRc7C/pQUQu0iIiIiMgoEJX86dZrzjqsoCXquIfTHT2qhf4bC+dkbLkP2+89c2sjv2d8ZZxfrjw0fjvoIh6Mzc03wO11Lpnh+vd/3RG5XTB1Vy6J5QyIlRxqed++r4NVm5tpau1i5g33hZYxuP6pc3zPmFTFwnl1PLHoEszg2gtnhtZ7b59j/Y4DnFk7nlnTxwKwfuf+ftvs2NcBwJl149m1v4PuXq8Lf2rm9KhzLsmQjnywk+gdCWqBFhEREREZBXKdf3k4HTfsGNla7tPX/27tdu59LjGgJboyHsOMyPHb+bQ8hwkSlFXGS2hP+Y4guA3K+K0H1icD0nSV8RgV8ZLk2O1ApnHSqS3Lv0pJ7vax/3o2Od/3sRMqeXXPwQH71jck+OZ9L9He3ctvGrZx8lQvAN+w8wAXz5qa3C4IdM89YQJrtrawc18Hx02sYuNeL8t5WayErt5D51wRL2HRgllcevpUnItOpDaYSfSOFAXQIiIiIiKjxGB1Gz/S3dHzMclPdjV9XAXb/AzaQZD/hYjuxtmUmBfExiKyqae66uxjeXT9ntCHC8Hy+jvXDjhOEAjnW8aqstJkxuuv/+Gl5OfBfN8AJ0+p5tXd/QPo9AzZzW3d3PzbdRiw5P71/HLl5mTZt7d4Af/ZMybyf/+0kW3N7Rw3sYrX/QB60YJZ/OLPm5Kt49f6Cc8eeGEnDvjsJSfxn09uiuyKP5IpgBYRERERkRFrQpUXQG9raef8mRO545MXJNdFTb0UJWbWr8v7zMXLs+5zz+pExjHmy1ZsCA3Cg0A43zIGrcNRGa+XrdjAFXOm8+fXGrl39TZufejlyKnVulOauhMt7Vx3xxq+9vt1zK4dx7iK0mQX76B8G/e2UlpifGz+CXzirSfS0d3LnK+u4JcrN/OTx18n6L19b0OCq86u4+GXdrNjXwdG/yzmw/VhTC40BlpEREREREasSdVlyX+fP3Niv3W5jkMO9DnXL7jLpctxamAYJlMW7ULKGJQp03FPnlpNZ08fN/zGG+ftiJ4iLF1zWzd/fq2RMWUxjvETiwWZuDfuaeX4SVWUxrww8oEXdtLX52jr8gL54Bu2t3Rwz+oEl50+lZhZ8vNg7PlIzsatAFpEREREREasP728J/nv25/Z0i84S006lov0gDnX4DZTcqyoIDz4PD0xWk1lPHIe6dRu0JmOe/LUasDLPl6IPgdNbd1UxGNMri5Pnt/Gva2cOPlQ4jKvdT38GO3dvfz6ma0DAvdsDxyGOwXQIiIiIiIyItU3JLjxt+uS7xtbuwa0cC6cV8dTiy9l09J3kiFBdOgY3fTgNtM81VFyyWIelHHj0ney5ubLWfb+s5JBf/Cd6RnJMx13w84DGc40N0HwXTehkoYtzVy49GE27DrA0683Jq9vtqzaUa3eIzkbt8ZAi4iIiIjIiJRpHHDYONtC5spOTaCWnogLsifHKiSLeS5J26KOC/RLLpZJPGbJbOLpxlWUUt+Q4MVEC6mJzA929iaTlWWa9xmik7CN5Gzc5nLsC380O+ecc9yqVauGuhgiIiIiIpJi5uLlodMlGbBx6TsHfB4VAGdKAhZ2jGJP6VVM85c+klNSsjq/7F/93Tpa2rsHrA+6kUcF2MH+6dczUBmPcdXZddyzOnFY1/tIMbPVzrlzsm2nFmgRERERERmRolpAo1o4izGn9XCe0gty6x6dOld1MCVWeiAdFTinfk/q9Uy0tCdbnOtSrus5MyYO6wcO+VILdA7UAi0iIiIiMvwUo0V5tIlqgY6Z0edcZBCba8t1oK6mkqcWX3rY5R0u1AItIiIiIiKjWjFalEebsG7VuTxUyCexV7Zx36OZAmgRERERERmxhnuX6iOt0IcK2RKCBSZUxbn53bOP2muuAFpERERERGQUKeShQljLdbzEqK4opaWtW637PgXQIiIiIiIiRzl1h8/NsAugzezDwKeANwAxYD3wX8CPnXN9mfaNON47gC8C5wAVwOvAr4HvOOc6i1VuERERERGRkUzd4bMrGeoCpDKzfwduxwt2/wQ8BJwK/BC428xieR7vn4D7gUuB54DlwFTgG8BjZlZVvNKLiIiIiIjIaDZsAmgzuwr4NLATeINz7l3OufcBpwAvAe8DPpvH8c4BlgJtwHzn3Nucc1cDJwJPAG8CbinuWYiIiIiIiMhoNWwCaOAGf/ll59wrwYfOuV14XboBFptZrmVeDBjwLefcMynHOwh8DOgDPm1mNYddchERERERERn1hkUAbWbHAmcDXcBd6eudc48DCWA6XstxtuOVAX/jv7095HivAyuBMuCKggsuIiIiIiIiR41hEUAD8/zlOudc1ORjz6Ztm8ksoApocs69VoTjiYiIiIiIyFFuuATQM/3l5gzbbEnbNpfjbcmwTT7HExERERERkaPccAmgq/1la4ZtDvrLsUNwPBERERERETnKDZcA2vylGy7HM7N/MLNVZrZqz549RSqWiIiIiIiIjFTDJYA+4C+rM2wTrDuQYZuiHc859zPn3DnOuXOmTJmSw1eKiIiIiIjIaDZcAuhN/nJGhm2OS9s2l+MdX6TjiYiIiIiIyFFuuATQDf5ytplVRmxzbtq2mawH2oGJZnZSxDbn5XE8EREREREROcoNiwDaObcVeA5vXuar09eb2UXAscBOvPmbsx2vC7jff/u3Icc7EbgAb97p5QUXXERERERERI4awyKA9i3xl98ys5ODD81sKvAj/+1S51xfyrrPmtl6M/tlyPGW4iUR+7KZnZeyTzXwc7xz/5FzrqXI5yEiIiIiIiKj0LAJoJ1zdwM/BqYDz5vZ783sXuAV4AygHvhh2m6TgVmEjHV2zj0LLAaqgD+b2YNmdifwGnAR8Azwz4N0OiIiIiIiIjLKlA51AVI55z5tZk8Cn8ELcmN445l/Dvw4tfU5x+N928z+ClyPN4a6Angd+DfgO865zmKWX0REREREREYvc65YUy+PXma2B9g81OXIYjKwd6gLIQOoXoYf1cnwpHoZnlQvw5PqZfhRnQxPqpfhabjWywznXNb5ixVAjxJmtso5d85Ql0P6U70MP6qT4Un1MjypXoYn1cvwozoZnlQvw9NIr5dhMwZaREREREREZDhTAC0iIiIiIiKSAwXQo8fPhroAEkr1MvyoToYn1cvwpHoZnlQvw4/qZHhSvQxPI7peNAZaREREREREJAdqgRYRERERERHJgQLoEczMPmxmfzKzfWZ20MxWmdlnzEz1OkjM7Bdm5jK81kfsV+LXzSq/rvb5dfehI30OI5WZzTKzz5vZbWa23sz6/Gv+/hz2LeheMbN3mNmDZtZkZm1m9oKZ/bOZlRfvzEa2Quql0PvI31f3UgZmFjezy8zsVjN72sx2mFmXmSXM7G4zuzjL/rpXBkGh9aJ7ZfCZ2efM7E4ze8nMGs2s28z2mNkfzewjZmYR+xV8fQu9z44mhdSLmT2W5X55IMP3lfs/s17wf4Y1mdkKM1swuGc6spnZN1Ou75cybDeqfreUDuWXS+HM7N+BTwMdwMNAN3AZ8EPgMjO72jnXO4RFHO2eAl4N+XxH+gdmFgPuBd4D7AceBMrx6utXZnaBc+5/D2JZR4tPAZ/Pd6dC7xUz+yfgW0Av8BjQDFwEfAN4l5ld5pxrK+xURpWC6sWX830EupdydBHwkP/vncBqoBU4A7gKuMrMvu6cuyl9R90rg6rgevHpXhk8XwamAi8Af8arlxnApXjX6/1mdqVzri/Y4XCur/5+y1ne9ZJiBd59lu75sC8yszHAI8B5wB5gOTDB/57Lzex659x3D+90Rh8zOxf4J8ABoQ+a/O1G3+8W55xeI+yF98vW4f3iPCXl82nAi/66zw91OUfjC/iFf32vzWOf6/191gHTUj4/Be8HvAPeO9TnNtxfwMeBbwPXACfh/TB1wPsz7FPQvQKcA/Th/cI+P+XzauBxf7/vDfU1GQ6vAusl7/vI30/3UvZrdClwN/CWkHUfAHr863RJ2jrdK8OzXnSvDH7dvBkYE/L57JRr9bFiXN9C77Oj8VVgvQS/fy7O87t+4O/3GFCd8vn5/s+2PmDeUF+T4fTCe2C0DkgAv/Gv35dCthuVv1uGvAL0KqDSYJX/H+fvQtZdlPIftWSoyzraXvn+MQPEgF3+Pm8NWf9Rf91fhvrcRtqL3AK1gu4VvD90HXBTyH4n4j0N7QRqhvo6DLdXjvWS133k76N7qTj18x/+dfrPtM91rwzPetG9MrT1cqN/rX5VjOurv98Gr178z4PfPxfncayJQJf/s+rEkPU3+8e8c6jPezi98FqGHfDulJ9TYQH0qPzdorEWI4yZHQucjXez35W+3jn3ON7ToOnAm45s6STEBXhdkLY5554IWX8XXleWc82s7oiWbJQr9F4xszLgb/y3t4fs9zqwEigDrih6wSWK7qXiaPCXxwYf6F4ZFgbUy2HQvVI8Pf6yI+Wzgq6v/n4rqrB6KdQVQBz4s/8zK13ws+0KM4sX4ftGPDM7H68Xxq+cc7/PsN2o/d2iAHrkmecv1znn2iO2eTZtWym+S8zsu2b2MzP7upktiEiEENTBsyHrcN7YjXX+27mDUdCjWKH3yiygCmhyzr2Wx36Sv1zvI9C9VCyn+MvUsbO6V4ZeWL2k0r1yhJnZTOAf/bepQUKh11d/vxVBhnpJ9T4z+1cz+4mZ3WRmb8lwyGz1+Sre2NsxwKmFlHk0MbMK4L+BJrLnPxm1v1uURGzkmekvN2fYZkvatlJ8fxfy2Ytm9kHnXGqSilzray6qr2Ir9F6ZmbYu1/0kf7neR6B76bCZ2XTgWv/tPSmrdK8MoQz1kkr3yiAzs4/hdSmN4/UEuBCvoWmJc+43KZsWen3191sB8qiXVOkJ3L5mZk8BH3LObU1bl0u9bMVLKjaTQw9Hjla34AW4H3TO7c2y7aj93aIW6JGn2l+2ZtjmoL8cO8hlORqtwfvBPBuvLmqBdwFr8bKp/jGtS5zqa+gUeu1VZ4Mv3/sIVC+HxcxKgduA8cDDad3udK8MkSz1ArpXjqT5eOOXPwy81f/sRuD/pG2n++XIyrVeAP4E/D1eS3EVXtbuDwEb/eP80c+4nUr1kiMzuxC4Dqh3zt2Rwy6j9l5RAD3yBGni3ZCW4ijlnPu+c+4HzrkXnXOtzrkdzrnleFMfPI03LuqGlF1UX0On0GuvOhtkBdxHoHo5XD/BmzZkK/CRtHW6V4ZOpnrRvXIEOec+7pwzvMBrNvB94KvA02ZWm7Kp7pcjKI96wTl3o3Pu5865V5xz7c65Lc65/we8EXgdL7D+VNpXqF5yYGaVwH/hTdv26Vx385ej7l5RAD3yHPCX1Rm2CdYdyLCNFJFzrgtY4r9NTWig+ho6hV571dkQyXAfgeqlYGb2r3itMjuBy5xz6fOj6l4ZAjnUSyTdK4PHD7xedM4twns4cRbefLUB3S9DIId6ybRvC/Cv/lvdL4X5Jt4DiC8656JyNaQbtfeKAuiRZ5O/nJFhm+PStpUjY72/TO1Ot8lfqr6OvE3+Mt9rH/z7+Dz3k+IIu49A91JBzOxWvC7Ae/CCtFdCNtvkL3WvHCE51ks2ulcG33/5y3enZGDe5C8LvV9UL4cvrF6y0f1yeN6HNy/zR83ssdQX8A5/m0/5n/2H/36Tvxx1v1uURGzkCaa6mG1mlRFZ7c5N21aOjEn+8mDKZ8/5y3MJYWZVwJn+W9VXcRV6r6wH2oGJZnZSRAbI80L2k+IIu49A91LezOzbwBeBRuDtzrkXIzbVvXIE5VEv2eheGXwteFMmleLNF7yLwq+v/n4rnrB6yabQ++VkvARibcDLeZd0dCnBS+gW5UT/VeO/H7W/W9QCPcL42QOfw5v77Or09WZ2EV6Wwp14c6TJkXONv0ydCmElsBs41szeOnAXrsbLLPmscy4xyOU7qhR6r/hdI+/33/5tyH4n4s0D2gUsL3rBJew+At1LeTGzpcAivOlX3u6cWxu1re6VIyefesmB7pXB91a8IK0FCDIOF3R99fdbUYXVSzZR98t9ePN2X+hPkZUu+Nm23P+Zd1Ryzp3gnLOwF960VgCL/M/m+vuM3t8tzjm9RtgLeD/ewPodwMkpn0/FS6/vgM8PdTlH2wtvSop3AbG0z0vxWhN6/Wu/IG39l/zP1wFTUz4/xa9DB7x3qM9vpL2Ax/xr9/4M2xR0r+A9Ee3DywB5Xsrn1Snf+72hvgbD8ZWtXgq9j/xtdC/lVgdf969FM3B2jvvoXhlm9aJ75YjUyVvw/kAvD1k3H3jNv1bfKcb1LfQ+O9pehdQLcDFe66ilbV8FfNvfvhuYHXLMH/rrHwWqUz4/3//Z1gfMG+rrMlxfwC/86/elkHWj8neL+YWREcbMfoSXSbAD+CPeD4XLgHFAPd4fr71DV8LRx8wWAr/Bmzz+ZWAbXvr8OXhTi/QBNzjnvp22X8zf79142Qsfxns6/TagAviBcy59zkJJY2ZvBH6U8tEZeNf/Fbw6AcA596a0/Qq6V8zsn4Bv4f2R+gjek+6L8H7oPwNc6pxrK9LpjVj51kuh95G/r+6lLMzsPcBv/beriJ6zdL1zbmnavrpXBkkh9aJ7ZfCZ2bV442lb8FrKduJd45PwfpaB18J1tUvpfno411d/v2VXSL2Y2XXA9/C6c78CbMfrtj3XX3YCf++cuz3k+8bgBc/n4vUueByvG/KlQAwvMLx1EE51VDCzX+BNNbbIOfedkPWj73fLUD+10KvwF96ceE/h/fBuBVYDnwFKhrpso/GFN1n794E/Awm8HwTteD+of06GFgW84RKf9euo1a+zJ4EPD/V5jZQX3tNll+0VsW9B9wpeYoyH8FqM2vH+6P1nQp6KH62vfOvlcO4jf3/dS5mvz7W51AfwWMT+uleGSb3oXjki9TITbz7hR/GmEmv3r/Mm4G5g4WBc30Lvs6PlVUi9APOAH+N10d6J17231f9Z9APg1CzfWQH8C/Ci/33NwIOE9PDQa8C1+wURLdAp24yq3y1qgRYRERERERHJgZKIiYiIiIiIiORAAbSIiIiIiIhIDhRAi4iIiIiIiORAAbSIiIiIiIhIDhRAi4iIiIiIiORAAbSIiIiIiIhIDhRAi4iIiIiIiORAAbSIiIiIiIhIDhRAi4iIiIiIiORAAbSIiEiRmJkr4PULf99N/vsThvQkDpOZvcnM+sxs6RB8d5WZ7TCzZ83MjvT3i4jI6Fc61AUQEREZRf475LPpwAKgFbg7ZP2Tg1qiI8gPWv8N2A9860h/v3OuzcxuAX4A/B3h9SEiIlIwc84NdRlERERGLTO7GHgU2OycOyHDdicBceA151z3kSldcZnZh4Hbga87524aojKUAZuBPmCmc65rKMohIiKjk7pwi4iIDAPOudecc+tHavDsuw5wwM+HqgB+wHwbUAtcPVTlEBGR0UkBtIiIyDAQNQY6GCvt//taM1tlZq1mttPM/tPMpvjrKszsa2b2spl1mNkWM7vFzOIR3zfGzP7JHy+838zazWydmX3VzKoLKP+5wLnA4865TRHbnOGfz7qI9eP98dO7Q9ZNNbMlZrbWzA6YWaeZJczsMTO7IW3zoOv2p/M9DxERkUwUQIuIiIwAZvYt4KdAE/AAXkvv/wL+6Ae8DwOfA9YBjwCTgK8A/x5yrGOBv+CNU54BrAQeBCYANwNPmdmEPIu40F/+McM25/jL1RHr3wgY8Fxaec/CO6/FwBi8c/0tXlft84EPpm7vnHsB2AVcEDxgEBERKQYlERMRERkZPgrMdc69BOAHuCuBN/jLFrwxv/v89XOBZ4GPm9ktzrnN/ucG3AmcAfwQ+LJzrs1fVwn8DPgI8D3g2jzKd7G/XJlhmyCAXhWx/mx/+Vza5/8BTAY+4py7PXWFmY0HTg851kq8oP4SvPMVERE5bGqBFhERGRluCoJnAOdcM/AT/+0ZwD8EwbO/fg1wH16L7kUpx3kHcAHwNPD5IHj292kH/hHYDfxtnq3QT++8/AAAA+NJREFUc/3lSxm2ydYCPSCA9gPkc4Ad6cGzX+Z9zrmnQ471or+cl6E8IiIieVEALSIiMjI8EPLZq/5yc2pwneIVf1mb8tkV/vIe51xf+g7OuVa8FuJSvDHNWZnZGKDKf9sYsU0MOAvoBRoiDhUE0KkBdjvQCRxjZt83s9qBu4Vq8pfTctxeREQkKwXQIiIiI8O2kM8OZliXur4i5bMT/eWyIEFZ+otDQXau44fH+8vODNNGnYEXZL+U2uodMLNxwMlAs3NuY/C5f7xP4wXSnwe2+YnUvmpmJ2co035/WZPjOYiIiGSlMdAiIiIjQFhrcYpM69LF/OXjwKYs227O8Zgt/rLczMqdc50h2+SaQGxA67Rz7udm9gfgfcAC4O14rdU3mtmXnXPfCTneOH/ZnOM5iIiIZKUAWkRE5Oiy1V/e5ZwbkKG7EM65NjNrxcuQPRHYEbJZEECviThM0OqdnkAs+I7deFnIf+onO1sM3ATcYmb/GjJ/9iR/OWBKLBERkUKpC7eIiMjR5X5/eXWRjxsEvmdErA/GN7enr/AThX3YfxvVQp3kJztbgjeeOhaxWVCO0IBcRESkEAqgRUREji71eEHqRWb2EzObmL6BmZ1oZp/J87iP+ssLQo5XipdADOBDZlaesu4Y4A6gzv9oQ8q6t5nZ+8ysLO14ceCbeMHzH0JanwHehDdX9mN5noeIiEgkBdAiIiJHEX8s9ULgeeCTwCYz+5OZ/drMHjKzDcBrwI15HrreX74tZN2ZeInMtgHnAZvN7D4zW+l/1yQgCIL/w8z+zv/31cC9QKOZPWZmt5vZ7/G6oX8Bb8qsT6d/mZnNwcu+vdI5tyfP8xAREYmkAFpEROQo45wLAtnP4iXtmg1chRfoHgC+A1yZ5zEb8OaWfquZnZC2Ohj//DBeIrAdwKXA8cB/4gXdP8Lr3l0CPOtvfwfwA7xW6dOBa4C3AK8D1wNvdM5tDynOR/3lj/I5BxERkWzMOTfUZRAREZFRwMw+CPwa+Lpz7qaUz38M/CPw2WIlLstQhjK87OF9wMwM02qJiIjkTS3QIiIiUix3AH8BPmdmE1I+D1qgVx2BMvwDMB34ioJnEREpNrVAi4iISNGY2fnASuDbzrnFfsKvA3gP7cc55zoG8bur8MZUbwPOc/ojR0REikwBtIiIiAwaM3sjXtbvBufcG4e6PCIiIodDAbSIiIiIiIhIDjQGWkRERERERCQHCqBFREREREREcqAAWkRERERERCQHCqBFREREREREcqAAWkRERERERCQHCqBFREREREREcqAAWkRERERERCQHCqBFREREREREcvD/Af9emllzi13PAAAAAElFTkSuQmCC\n", - "text/plain": [ - "" - ] - }, - "metadata": {}, - "output_type": "display_data" - } - ], - "source": [ - "expt_cfg={ \"start\":0, \"step\":1, \"expts\":400, \"reps\": 400,\n", - " \"relax_delay\":750\n", - " }\n", - "config={**hw_cfg,**readout_cfg,**qubit_cfg,**expt_cfg} #combine configs\n", - "\n", - "t1p=T1Program(soccfg, config)\n", - "\n", - "x_pts, avgi, avgq = t1p.acquire(soc, threshold=readout_cfg[\"threshold\"], load_pulses=True, progress=True, debug=False)\n", - "subplot(111, title=\"T1 Experiment\", xlabel=f\"Time ($\\mu s$)\", ylabel=\"Qubit Population\")\n", - "plot(x_pts, avgi[0][0],'o-');" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "# Ramsey Fringe Experiment\n", - "\n", - "Measures the qubit T2 Ramsey characteristic decay time by preparing the qubit in a superposition state with a $\\frac{\\pi}{2}$ pulse followed by a variable delay ($\\tau$) before applying another $\\frac{\\pi}{2}$ pulse with a phase advanced by $\\Delta \\phi = \\omega * \\tau$, where $\\omega$ is the Ramsey frequency. This exponential decay envelope can be fitted in post-processing to obtain the qubit T2 Ramsey time." - ] - }, - { - "cell_type": "code", - "execution_count": 17, - "metadata": { - "ExecuteTime": { - "end_time": "2021-09-30T07:38:38.823154Z", - "start_time": "2021-09-30T07:38:38.591844Z" - } - }, - "outputs": [], - "source": [ - "class RamseyProgram(RAveragerProgram):\n", - " def initialize(self):\n", - " cfg=self.cfg\n", - " \n", - " self.q_rp=self.ch_page(cfg[\"qubit_ch\"]) # get register page for qubit_ch\n", - " self.r_wait = 3\n", - " self.r_phase2 = 4\n", - " self.r_phase=self.sreg(cfg[\"qubit_ch\"], \"phase\")\n", - " self.regwi(self.q_rp, self.r_wait, cfg[\"start\"])\n", - " self.regwi(self.q_rp, self.r_phase2, 0)\n", - " \n", - " self.declare_gen(ch=cfg[\"res_ch\"], nqz=1) #Readout\n", - " self.declare_gen(ch=cfg[\"qubit_ch\"], nqz=2) #Qubit\n", - " for ch in [0,1]: #configure the readout lengths and downconversion frequencies\n", - " self.declare_readout(ch=ch, length=cfg[\"readout_length\"],\n", - " freq=cfg[\"f_res\"], gen_ch=cfg[\"res_ch\"])\n", - " \n", - " f_res=self.freq2reg(cfg[\"f_res\"], gen_ch=cfg[\"res_ch\"], ro_ch=0) # conver f_res to dac register value\n", - " f_ge=self.freq2reg(cfg[\"f_ge\"], gen_ch=cfg[\"qubit_ch\"])\n", - "\n", - " # add qubit and readout pulses to respective channels\n", - " self.add_gauss(ch=cfg[\"qubit_ch\"], name=\"qubit\", sigma=cfg[\"sigma\"], length=cfg[\"sigma\"]*4)\n", - " self.set_pulse_registers(ch=cfg[\"qubit_ch\"], style=\"arb\", freq=f_ge, phase=0, gain=cfg[\"pi2_gain\"], \n", - " waveform=\"qubit\")\n", - " self.set_pulse_registers(ch=cfg[\"res_ch\"], style=\"const\", freq=f_res, phase=cfg[\"res_phase\"], gain=cfg[\"res_gain\"], \n", - " length=cfg[\"readout_length\"]) \n", - " \n", - " self.sync_all(self.us2cycles(0.2))\n", - " \n", - " def body(self):\n", - " self.regwi(self.q_rp, self.r_phase, 0)\n", - " \n", - " self.pulse(ch=self.cfg[\"qubit_ch\"]) #play probe pulse\n", - " self.mathi(self.q_rp, self.r_phase, self.r_phase2,\"+\",0)\n", - " self.sync_all()\n", - " self.sync(self.q_rp,self.r_wait)\n", - "\n", - " self.pulse(ch=self.cfg[\"qubit_ch\"]) #play probe pulse\n", - " self.sync_all(self.us2cycles(0.05))\n", - "\n", - " #trigger measurement, play measurement pulse, wait for qubit to relax\n", - " self.measure(pulse_ch=self.cfg[\"res_ch\"], \n", - " adcs=[0,1],\n", - " adc_trig_offset=self.cfg[\"adc_trig_offset\"],\n", - " wait=True,\n", - " syncdelay=self.us2cycles(self.cfg[\"relax_delay\"]))\n", - " \n", - " def update(self):\n", - " self.mathi(self.q_rp, self.r_wait, self.r_wait, '+', self.cfg[\"step\"]) # update the time between two π/2 pulses\n", - " self.mathi(self.q_rp, self.r_phase2, self.r_phase2, '+', self.cfg[\"phase_step\"]) # advance the phase of the LO for the second π/2 pulse" - ] - }, - { - "cell_type": "code", - "execution_count": 18, - "metadata": { - "ExecuteTime": { - "end_time": "2021-09-30T07:44:01.658674Z", - "start_time": "2021-09-30T07:38:38.831516Z" - } - }, - "outputs": [ - { - "data": { - "application/vnd.jupyter.widget-view+json": { - "model_id": "935971ee939b4bb89999a3c0cce3e3f6", - "version_major": 2, - "version_minor": 0 - }, - "text/plain": [ - "HBox(children=(IntProgress(value=0, max=200), HTML(value='')))" - ] - }, - "metadata": {}, - "output_type": "display_data" - }, - { - "name": "stdout", - "output_type": "stream", - "text": [ - "\n" - ] - }, - { - "data": { - "image/png": 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GM7sGb39txJ9TO8rzPotXswDgv8zsNjNbE7ZPn+Hv01/E26evibKOnJGB/SJaG04AT/k33+N/P1aZWUm8gF5EZLqy5ovFzFrwxq49H29exBV4Z4pf65y7bQbrfQPwTuA8vNSeJ/F+YL8aZ0yhiEi6fAFvGqjZwIfN7Ed+7yx4B5uvwPtefL1/Cfc48L/xetYyqRL4e/8Sy/eBr4Tf4ZwbMrNXAf8N/A1e4BsvdXYg1gPOuUEz+z7wz/5do/56xfMveCdpXo43P3ZbxON34J3s+AowHGcdIbwe2AvxerZjeXQmjfXbM5kRwo5jzOw9eP8fwLudcxNOCDjndvrLfBt4lZm9yzk3YZ8M8xa8ImRfYvzkQ2AUeI9z7p7IJ/n74SuA7wGvBq71L7HE3KdzSDr3i1i+AHwZb5aDR8IfMLPFzrk9KXpdESlA2dQD/U683og34hUymfE0BWb2Zbwv8tV4Z43vxAvMvwTcFiVdUkQkrfxe6CAN8mzCAkjnXB9eEa5P4J38GwCOAR1401tdxPiYy0z5A14a+Q1437PP4B1MD/h/3wJc7Zx7s3PulGlqnHPHnXNtwBXAd4GdeFWjh4BDeGNM/x24wDn3xUna8q2wv+/QQfM459wA8Crg7cCf8XpiT+BN9fRevBM1QYXqEzHWMeqc+1dgFV7A8ije/jjiX2/BC2KuAN6Qqv8lGjMLLxD2Y+fc96It55z7DhCclP9PM1sVY5U7gOcBX8TrmR8ADgM/By5xzn05Vlv8Qnp/DVyJF0jvwpuSKnyf/gRwvnPuqwn/k1kqG/YL/0TIm4F78YbFqINERFLGxjs6MsvM3ooX3G4GHsY7EHop0+yBNrNr8X4k9wMvcc497d8/H7gHr5jNe51zX0jOfyAiIplkZmcynsr5d865WzPZnlzjn3R+F97Y3oKrqmxmL2O84J16LUVEJKqsSeF2zn0z/Hb0GidTst6//lAQPPuvc8DM3gn8Dq9ozxeVyi0ikheu86+PAL/IYDtyjl/s7ZX+zYcz2RYREZFslk0p3EljZovwxuEMAqf0QPjTqnThFRJ5YXpbJyIiyWZmVcBb/Zvf9VOWxedXMY9WdCuwHgiqnP8kDU0SERHJSXkZQANB6tnjzrlQjGUeilhWRERyiJkV+ZV2F+MVhmrEO3F6c/xnFqQGYIeZfdyvwD3PzBrM7K/M7LvAp/zl7mM8jVlEREQiZE0Kd5IFc44+G2eZ5yKWFRGR3PIx4N8i7vuMc64zE43JAQvw3q/I9yzwKPB6ly3FUURERLJQvgbQNf51b5xlTvrXtSlui4iIpNYgXvXur+BV+5VTHcSbmmkNcD4wH6jDq1i8Fa/o5recc4MZa6GIiEgOyJoq3JHM7HdMswq3mX0ELx3t+865N8dY5tN4cxZ+3Tn39iiPvw14G0B1dfWFK1eunNo/ICIiIiIiIjnh4YcfPuyca5hsuXztgQ7msKyJs0zwWKz5Lr8OfB1g9erVbvPmzclrnYiIiIiIiGQNM4s3/HdMvhYRe8a/Pj3OMosjlhURERERERGJKV8D6A7/+mwzq4yxzPMjlhURERERERGJKS8DaL8C61+AMuC1kY+b2UuBRcB+4MH0tk5ERERERERyUU4H0GZ2g5k9aWY3RHk4uO8mM1se9pxGvEqtADc650ZT3U4RERERERHJfVlTRMzMnsd4YAuwyr/+jJl9MLjTOffCsGUWAi3+9QTOudvM7KvAO4GtZnYXMARcgTd1RzvwpaT+EyIiIiIiIpK3siaAxgtqXxDl/jOnu0Ln3LvM7PfAu/GmxCoGngS+DXxVvc8iIiIiIiKSqKydBzqbaBorERERERGR/GVmDzvnVk+2XE6PgRYRERERERFJFwXQIiIiIiIiIglQAC0iIiIiIiKSAAXQIiIiIiIiIglQAC0iIiIiIiKSAAXQIiIiIiIiIglQAC0iIiIiIiKSAAXQIiIiIiIiIglQAC0iIiIiIiKSgJJMN0Bmpr2jiw2btrO3J0RTfSVr17TQ1tqc6WaJiIiIiIjkHXPOZboNWW/16tVu8+bNmW7GKdo7uli/cSuhoZGx+wxwQLOCaRERERERkYSY2cPOudWTLacU7hy2YdP2CcEzeMEzQFdPiPUbt9Le0ZX+homIiIiIiOQhBdA5bG9PKO7joaERNmzanqbWiIiIiIiI5DcF0Dmsqb5y0mUmC7JFREREREQkMQqgc9jaNS1UlhbHXabIYOm627n4xruVzi0iIiIiIjIDqsKdw4ICYRs2baerJzRWQCzciH9HMCY6/HkiIiIiIiKSOAXQOa6ttXksIA6f0qrIxoPnQDAmWgG0iIiIiIjI1CmAziPhwfTSdbdHXUZjokVERERERKZHY6DzVKwCY4kUHhMREREREZFTKYDOU9EKjFWWFrN2TUuGWiQiIiIiIpLblMKdp4JU7vUbtxIaGqG5vpK1a1o0/llERERERGSaFEDnsbbWZrp6QmzYtJ1N73sJNeXa3CIiIiIiItOlFO48t6yhGoDdh3oz3BIREREREZHcpgA6zy1rqAFg56GTGW6JiIiIiIhIblMAnedOm1tFcZEpgBYREREREZkhBdB5rrykmNPmVCmAFhERERERmSEF0AVgWUM1Ow9qDLSIiIiIiMhMKIAuAMsaath9uJeRUZfppoiIiIiIiOQsBdAFYFlDDYMjo+zp7st0U0RERERERHKWAugCsKzRm8pK46BFRERERESmTwF0AThjnj+VlcZBi4iIiIiITJsC6AIwu7qMudVl6oEWERERERGZAQXQBWJZQ40CaBERERERkRlQAF0gljVWs/OQUrhFRERERESmSwF0gVjWUMPR3kGO9g5muikiIiIiIiI5SQF0gTh4vB+ACz95JxffeDftHV0ZbpGIiIiIiEhuUQBdANo7uvjug88C4ICunhDrN25VEC0iIiIiIjIFCqALwIZN2xkYHp1wX2hohA2btmeoRSIiIiIiIrlHAXQB2NsTmtL9IiIiIiIicioF0AWgqb5ySveLiIiIiIjIqRRAF4C1a1qoLC2ecF9laTFr17RkqEUiIiIiIiK5pyTTDZDUa2ttBryx0F1+2vZHX3nW2P0iIiIiIiIyOQXQBaKttZm21ma27T3OK/7rfoZHXaabJCIiIiIiklOUwl1gVjXV0TSrgk/dvo2l627XnNAiIiIiIiIJUg90gWnv6OLQyQGGRrwe6GBOaEAp3SIiIiIiInGoB7rAbNi0fSx4DmhOaBERERERkckpgC4wmhNaRERERERkehRAFxjNCS0iIiIiIjI9CqALjOaEFhERERERmR4VESswQaGwj//icXpCQ8yvK2f9yzUntIiIiIiIyGQUQBegttZmZlWV8pbvPMRX3vg8Ljx9TqabJCIiIiIikvUUQBeoxtpyAA4eH8hwSyRSe0cXGzZtZ29PiKb6StauaVGGgIiIiIhIFlAAXaAaaysAOHhCAXQ2ae/oYv3GrYSGRgBvnu61tz7CJ375OD19QwqoRUREREQySAF0gZpTXUaRwSEF0Fkh6HXuijKd2NCoo7tvCPAC6vUbtwIoiBYRERERSTNV4S5QxUXGvJpyDp7oz3RTCl7Q6xwteI4mNDTChk3bU9wqERERERGJpAC6gDXWlSuFOwts2LR9LGU7UXsTDLZFRERERCR5FEAXsMbaChURywLTCYab6itT0BIREREREYlHAXQBa6xVD3Q2iBcM11eWUlpsE+6rLC1m7ZqWVDdLREREREQiKIAuYI215RzpHWB4ZDTTTSloH7jyTCzivsrSYm5+3QVs+ber2PCa82kOC7L/5WpV4RYRERERyQQF0AWsoa4C5+BI72Cmm1LQqspLcHiV0Q1orq/khmvOHQuS21qbeWDd5fz+Q5dhwH9u2s7Sdbdz8Y13097Rlcmmi4iIiIgUFE1jVcAaa8sBOHh8gPl1FRluTeEJn7qq2IyPvuIsrrlwUczlNz/TTVGR0Ts4Pke0prQSEREREUkf9UAXsLEAWlNZpV3k1FUjzvGR9sfi9ihv2LSdkVE34T5NaSUiIiIikj4KoAtYo9/rrEJi6Rdt6qrJguFY1bo1pZWIiIiISHoogC5gDTXjKdySXtMJhmNV69aUViIiIiIi6aEAuoCVlRQxu6qUQyeVwp1u0wmG165pobK0eMJ9ZSVFmtJKRERERCRNFEAXuIbacvVAZ8DaNS2Ul0z8+E02v3NbazM3XHMuzfWVGGDAyMgo77tliypyi4iIiIikgQLoAtdYW6Ex0BnQ1trM/7lkKUDUqaviPe+BdZfz+dddQEmxMeLAMV6RW0G0iIiIiEjqaBqrAtdYW87uw72ZbkZBWjqvGoDfrb2U0+dWT+m5GzZtZ2gkekVuTWklIiIiIpIa6oEucA115Rw6MYBzbvKFJan2HfPGni+YNfU5uFWRW0REREQk/RRAF7jG2goGR0bp6RvKdFMKzr5jIebVlFFeUjz5whFUkVtEREREJP2yLoA2szeY2f1mdszMTprZZjN7t5lNua1mNtvMPmNmW82s18wGzOxZM/uemV2QivbnmsZafyorjYNOu709/SycNb2AN1pF7smKkImIiIiIyMxkVQBtZl8GfgCsBu4H7gRWAF8CbjOzhLvqzOw0YAuwHlgA3AP8EhgC3gQ8ZGbXJvUfyEHjAbSmskq3fcdCLJxG+jaMV+RuqveeX1NeklARMhERERERmb6sCaD9YPZdwH7gPOfcq5xzfwucCTwB/C1w/RRWeSNwGvAr4HR/fa/BC8g/gVdA7f+aWWkS/42c01jnBWCayir99vX0zyjluq21mT+su4JlDdVcsnyegmcRERERkRTLmgAar6cY4EPOuaeDO51zB4B3+jfXTSGV+zL/+pPOub6w9Y0CnwRCwFy8AL1gKYU7M070D3FiYHjaPdDhljXUsOPQySS0SkRERERE4smKANrMFgEXAoPArZGPO+fuBbrwUrFfmOBqE40IDye4XF6qLi+huqxYKdxpFlTgXpiEol/LG2t45nAvQyOjM16XiIiIiIjElhUBNNDqXz/unIs1D89DEctO5jf+9UfNrCq408wM+BhQCfzCOXdwqo3NN411FeqBTrMuf7qppiT0QC9vrGF41PHc0b7JFxYRERERkWkryXQDfEv962fjLPNcxLKT+ShesP1K4Fkz+yNer/T5wOnA9/HGXBe8hhpvLmhJn309yeuBXtZQA8COgyfH/hYRERERkeTLlh7o4Ki/N84ywSDP2kRW6Jw7DFwOfBeYB7wKuBZYDuwC7nXOnZhWa/NIe0cXW7t6+PPuo1x84920d3RlukkFYd+xEEUG8/0x6DOxrHE8gBYRERERkdTJlgDa/GuXtBWarQQ6gDXAm4GFQD1wBV6g/g0z+3ac57/Nn4N686FDh5LVrKzS3tHF+o1bCQ15Y2e7ekKs37hVQXQa7O3pp7G2gpLimX8Ea8pLWFBXwU4VEhMRERERSalsCaCDnuB4+afBY5P2GptZCfBTvN7ma5xz33fO7XfOHXPO3Q1cCRwA3mJml0Vbh3Pu68651c651Q0NDQn/I7lkw6bthIZGJtwXGhphw6btGWpR4dh3LMTC+pmPfw4sb6xhp3qgRURERERSKlsC6Gf869PjLLM4Ytl4XgCsAnY75x6MfNA5dxT4tX/zZYk1Mf/s7Ylery3W/ZI8+4710zRr5uOfA8sba9h5qBfnkpbEISIiIiIiEbIlgO7wr882s1hRxfMjlo3nNP/6WJxlevzrOQmsLy81xShgFet+SQ7nHHt7QjQlsQd6WUM1JweGOXBcxeBERERERFIlKwJo51wn8BegDHht5ONm9lJgEbAfOKVHOYq9/vVKM6uPsUwwn/TuqbU2f6xd00JlafGE+ypLi1m7piVDLSoM3X1DDAyPsjCJPdAqJCYiIiIiknpZEUD7bvCvbzKz5cGdZtYIfMW/eaNzbjTssevN7Ekz+++IdT2IF0RXAt8ys7qw5xSZ2UfxAuhhvLHSBamttZkbrjl3rCe0tqKEG645l7bW5gy3LL8FKfLJ7IFe7k9fpUJiIiIiIiKpkzUBtHPuNuCrwAJgq5n90sw2Ak/jjWduB74U8bR5QAvjKdvBugaB64AQcA2wy8x+7a9vB/BJYBR4r3NuZ8r+qRxwvXqnAAAgAElEQVTQ1trMH9Zdwfy6cq4+e4GC5zTYd8yfAzqJPdANteXUVpSoB1pEREREJIWyJoAGcM69C3gjXjr3S/GmoNoBXA9c65wbifP0yHXdCZwPfA04AlyKNxd0CfBj4GLn3JeT2f5c1lRfyd5jKh6WDvv89zmZVbh/vmUv/UMjfO+Pz2o+bxERERGRFCnJdAMiOed+CPwwwWU/Dnw8zuNPA+9MSsPyXNOsSp7YdzzTzSgIXT0hSouNedXlSVlfMJ/30IgbW//6jVsBlFEgIiIiIpJEWdUDLZnTVF9BV09I0yClwb6efhbMqqCoyJKyPs3nLSIiIiKSHgqgBfDG4w4Mj9LdN5TppuS9fcdCSR3/rPm8RURERETSQwG0AONzPyvoSq32ji7+8mwPf959NGljlTWft4iIiIhIeiiAFmB8SiUF0KnjjVV+lBE3cazyTINozectIiIiIpIeCqAFUA90OnhjlUcn3JeMscrBfN7N/jasKCnSfN4iIiIiIimgAFoAmFtdRllJ0dgcxZJ8qRyr3NbazAPrLucV5y5gYX2lgmcRERERkRRQAC0AmBlNs7xK3JIaC2ZFn/c5mWOVlzXU8NzRPgaGE54yXUREREREEqQAWsYsnFWpHugUWtVUd8p9yR6rvLyxhpFRx7NH+pK2ThERERER8ZRkugGSPZrqK/nDzsOZbkZeae/oYsOm7WNp2qfPqWR41EvbbqqvZO2alqSmWy9rqAFgx8GTrJhfm7T1ioiIiIiIAmgJ01RfwYHj/QyPjFJSrOSEmfKqbm8lNDSeTr3/+AA3XXteysYon9FQDcDOgydTsn4RERERkUKmKEnGNNVXMurgwImBTDclL3hVtyeORR4YHp1x1e14qspKaK6vZMchBdAiIiIiIsmmAFrGaCqr5Epl1e14ljXWsFMBtIiIiIhI0imAljFNfpVoBdDJEau6djKrbkezvKGGnQd7GR11KX0dEREREZFCowBaxiwc64FWJe5kWLumhcrS4gn3JbvqdjTLGqsJDY2w95hOhOSC9o4uLr7xbpauu52Lb7yb9o6uTDdJRERERGJQETEZU1NeQl1FCfsUeCVFUCjsg7c+wvCoozkFVbejWe5X4t55qJdFs6tS+lqSuPCK7EEFdmBCobmunhDrN24FSPl+IiIiIiJTpx5omaCpvlIp3En0Nxc0UVpcxFsuXsID6y5PS1C0vHF8KivJDkFF9q6eEI7xQPkTv3z8lEJzoaGRlBaaExEREZHpUw+0TOAF0ErhTpajvYOEhkZYnMae4DnVZdRXlSqAziLRKrKHhkZOuS+gk1giIiIi2Uk90DJBU32Fxs4mUWe3914unpO+ANrMvEJiqsSdNaYaEKe60JyIiIiITI96oGWC7t5BevqGWLru9rFxmhqLOX2dR/sAWDwnvQHRsoYa7nriQFpfUyYKH/NsBi7BouiVpUUpLzQnIiIiItOjAFrGtHd0ccc2L+gKH6cJKmg0XZ3dXgCd7mJe/UMjHOkd1ImQDAnGPAcp2okGzwD/55Kl2lYiIiIiWUop3DJmw6btDI1MPNJXQaOZ6TwaYnZVKTXl6TtX1d7Rxa8f2w9MPBGi6ZHSJ9qYZ4Bis5jPWTirgqqyYo70DqayaSIiIiIyAwqgZUyscZoqaDR9e7r70jr+GbzgbXBkdMJ9OhGSXrE+M6POcfPrLog6P/iHrl7JVavmc/uj+xgYjl5cTEREREQySyncMqapvpKuKAf+Kmg0fXu6Q6xaWJfW19SJkMyL91kK0rMj54Rua22mvqqU9i17edENd9PdO6j0exEREZEsowBaxqxd0zJh3CZ4PWMqaDQ9o6OOru4QV509P62vqxMhmbd2TQtrb3tkwpCI8M9SW2tz1KD46MkB79pP4+7qCfG+W7bw3lu20KxgWkRERCTjlMItY9pam7nhmnMpL/F2i+b6Sm645lwdsE/TgRP9DI6MpnUOaPCCt2gpwjoRkj5/c0ETc6vLKCkyjMQ/S5+98+lT7gtCcI1lFxEREck89UDLBG2tzTz0zFFu37qPB9Zdnunm5LTOo+mfAxrGK6Z/7OePcbx/mIWzKvjQ1St1IiSN/rDzCPuPD7DhNefx2tWLE37eZGn2wVh2bUsRERGRzFAALac4bU4VPX1DHAsNMauyNNPNyVl7xqawSn/qdFtrM7OqSnnLdx7iC69v5aKlc9LehkIUzP3c1ROiKHbB7Zhipd+H01h2ERERkcxRCrec4jS/x7TzaF+GW5Lbgh7o5gyNPW6ZXwvA9gMnMvL6hSaY+zkIgEcdfOznj08p5Tpa+n0kjWUXERERyRwF0HKKIOU46EGV6ens7mN+XTkVkwREqbJwVgW15SU8rQA6LaLN/TzV6cOCOgTBSZfITmyNZRcRERHJLKVwyylOm+sF0M+pB3pGOo/2pb2AWDgz48z5NWzfrwA6HZI1fVh4he72ji4+/ovH6QkNMb+unPUvP0vjn0VEREQySD3Qcoq6ilLqq0oVQM/Qnu5Q2guIRWpZUMtTB07gnJt8YZmRWKnVM0m5bmtt5vtvfQEAH3vV2QqeRURERDJMAbREddqcKp47qmJF0zU0Msq+Y6GMFBALd2ZjLd19Qxw+OZjRdhSCD1y5IiUp12fOr6G02Hhs77EZrUdEREREZm5aKdxmtghoAipiLeOcu2+6jZLMWzynim17j2e6GTlrX08/o46MpnCD1wMN8NSBEzTUlme0LfmutrIUB8yuKqWnb4im+krWrmmZca9xeUkxK+bX8liXAuh8EFRq39sTSto+IiIiIukzpQDazK4BbgCWT7Kom+q6JbucNqeKOx7fz8ioo3g68/EUuM5gCqs5me2BXjF/PIC+ePm8jLYlX0VOXfXRV57FtRcmPvdzIs5pmsWdTxzAOYeZPo+5IFqgDLB+49axYnNdPSHWb9wKoCBaRETyVr6dPE44yDWzVwM/wUv7PgbsAtRFmadOm1PF0Ihj//H+jE3DlKuCwk8A77tlS0YLP82rKWN2VSlPqRJ3SgRTVwUB0aiDj7Y/TnFRUVK3+TnNddyyuZN9x/o1jVWWCj84mFVZSu/gMEMjXu2Brp4Q77tlC9EqEYSGRnjvLVvYsGl7zh9QiIiIRIo8VsqHk8dT6SX+MN6sKh8FNjjnhlLTJMkGwVzQzx3pUwA9BZFfEgeOD2T0S8LMWDG/VpW4UyTe1FXJ3N6rmmYB8Pje4wqgs1Dk574ndOrP42Rl/PLhgEJERCRSuo6V0mkqRcTOAzqcc59R8Jz/ggC6U5W4pyQZcwEn24r5tTx94KQqcadAsqaumsxZC2spMjQOOktF+9xPR6a/K0RERJItXcdK6TSVAHoI0C97gVg4q4LiItNUVlOUjV8SKxbUcmJgmH3H+jPWhnyViqmroqkqK2FZQw2PqxJ3Vkrm5zuXDyhEREQipetYKZ2mEkA/DJyRqoZIdikpLqK5vlIB9BRl45fEweNe4PziG+/m4hvvpr2jK2NtyTdr17RQElFkLxlTV0VzTvMsHutS2YlslMzPdy4fUIiIiERau6aF8pKJIWeqjpXSZSoB9I3ARWZ2ZaoaI9nFmwtaAfRUZNuXRHtHF9+4f9fY7WCcpYLo5Ghrbaa5voLSYsOA5vpKbrjm3JSM6Tm7qY79x/s5dGIg6euW6Wnv6OLiG++mK0qvcWmRMbuqFCDq/OBveuFpVJYWT7jfDD541YpUNVdERCTt2lqbeeely8Zup/JYKV2mUkRsO/Bp4Bdm9l/A7cBzwGi0hZ1zz828eZJJi/2prCRxba3NPLn/OF+7dxcGGS/Vv2HTdvqHJn5Ec71wQzY51jdEZ3eI6y9bzvuvSu1Jkp6+QQCe/+m7aM6DKSByXWThsHCR2yfW9B2rT58zXrnbnz/8k/+zjff/5JGMf3eIiIgky0VL5gBwy9teyAvOmJvh1szcVALoZ/AKiRrwQf8Si+aBzgOnzaniSO8gJweGqSnX5kzU/LoKAP78kZfRUFue0bZk45jsfPL7HYcZdfCSFQ0pfZ32ji6++fvdY7dVsTnzYhUOa66v5IF1l0+4r621Oep2Cr9/48N7+MCtj3C0z6vRqW0sIiL5Ivi9rCwrnmTJ3DCVqOg5Jp+JQ/JIeCXusxbWZbg1uWPnoZPUVZQwr6Ys002hqb4yanqpxlkmx31PHaK2ooQLFten9HWUSZB9kn1y6rN3PnXKD6y2cW6IlWEgIiKesQC6tMACaOfckhS2Q7LQrkMnAXj5F+5XyugU7Dh4kmWNNZhFjnxMv7VrWk5JM831wg3ZwjnHfU8f4pLl8ygpnko5ialTJkH2CIKlWGeTp3tySts4+0ULlIEJ37HKHBAROVVo0PuOrMiTADq1R32Ss9o7uvjy73aM3VbxqcTtPNTL8oaaTDcD8A7gbrjmXOorvWJG8+vKc75wQ7bYcfAk+471pzx9G7KzunshCsY9R8vqgJmdnNI2zm7h297h/Sa+75YtvPeWLaek8ms+bxGRifqHvSy6fEnhVgAtUcVLGZXYjoWGOHRigGWN2RFAgxdEf/ENrQB84fWtCp6ToL2ji9d87Q8A3HzXUyk/sbR2TcspaU+VpUXKJEizWOOeYeZVRaNvY2WLZIto2z7emDZlDoiIjOvPsx7oKVeGMrN5wD8ClwLBkUIXcA/wLefcoaS1TjJG6YTTs9NPe8+WHuhAs9+Lpe03c5HVlw8cH0h5ymaw3g2bto/1fr7j0mU6GZJmsT4/BqcUDpuqYFve9Jsn2Xesn9ryEj7Zdo62cZaY6nenMgdERMYFx0wVJfnRdzulANrMXg78AJjFxKktVwEvA9aa2Zucc79OXhMlE1R8anp2HvQC6GzqgYbx7dbVrQB6pqL1RKWj2FNQsfnkwDAv+PRd7DmqbZkuqRr3HCnYxn/3tQfpGxpW8JwFJtv20ZQVj2eHqMCYiIh3nFRWXJTymjHpkvB/YWYrgZ8C9cCfgXcAVwJXAW8H/gTMBm7zl5UcpnTC6dl5qJey4iIWz86uEw0VpcXMqymPOXZTEpfp7Iya8hLOWzyLWx/ew9J1t3PxjXerNkEKpXLccywvbWngsa7jHDzen9T1ytRMtu2jKTJY3lhNW2tz1HHTqiUiIoUoNDhCRWl+BM8wtTHQ64AKYK1z7kXOua87537rnLvLOfcN59yL8eaGrgQ+lIrGSvoExadm+cWnFtRVqPhUAnYcPMmSeVVZeYateXb0rAKZmkwXe2rv6OIvz/YA6KA8DVI57jmWy1oaAfjdUxoRlUnxtn3kHAuVpcXc/LoLuP7yM9m27wS7Dp2Mm60i2aG9o4uLb7xbJyNFUmxgeCRvCojB1ALoy4HHnHOfjbWAc+5zwGPAFTNtmGReW2szn3/d+QB8+Y3PU/CcgF2HTrIsy8Y/B5rrK5TCnQRr17RQFHH0nM7sjA2btjMwrAJ/6TLZuOdUfC+etbCW+XXl/G77waSvWxIXb9t//nUX0FxfiTHxRMqbX3g6xQav/uLvY56wVC2K7KAMAZH08XqgCzOAng88msByW4HG6TVHss2i2VUA7Onuy3BLst/g8CjPHu3L4gDa64F2biqj+STSX5/fREVJEVVlxaccPKdDplPIC00mMg7MjKVzq/n11v3qGcugeNu+rbWZB9Zdzu4bXznhRMoDOw4DRu9g9J7reOuV9FKGgEj6hIZGThkamsumEkAfZ7zqdjxNwInpNUeyzSJ/LO8e9VxO6tkjvYyMOpZnWQGxQHN9JQPDoxw+OZjppuS0XYdP0jc0ysdfffYpB8/pkOkU8kLzwatWRE3XTWXGQXtHF395rhuH0vQz6QNXrjjlvsm2/YZN2xmJc5JStUSyh05GiqRPaGi0YHugNwOXmNnFsRYwsxcDfwU8NNOGSXaoKithXk0ZnUfVAz2ZYAqrrO2B9rMJNA56ZjY/0w3AhUtmZ+T1VeAvvVoW1OGA+srStGUcbNi0ncGRiUGYesbS7wz/ZOjsqsS3/WTB1/WXL9dwqCyhk5Ei6dM/mF890FOZxupLwBrg12Z2M/Bd4Fm8E+RLgH8A3os3POhLyW2mZNKi2VV0KoU7rvaOLj7288cAeNv3NvOhq1dm3UFSc9hUVhcsrs9wa3LX5me7mVNdxhnzqjPy+tHmhP6XqzU1TqrcsW0/ZnDXB17KvJrytLymesayw++2H8QMfvuBS5lTXZbQc2JNAblwVgVHegfZd0zbMFusXdPC+o1bJ6Rx62SkSGr0D4+k7Tc0HRLugXbO3Q7cBNQAHwGeAkJAv//3R4Fa4Cbn3K+S31TJlMVzqujUnLMxBYVIjvcPA7DvWH9Wpls2++n4XT06GTITDz/bzfNOm41ZZGJv+gTjL+/54KXAqRWBJXnuePwAq0+fndYffvWMZYd7nzrE+YvqEw6eIXaGyIeuXsl5zXX84I/PaVx7lmhrbebTbeeM3a4qK9ZsIyIpUsjTWOGcWw+8CvgdMAgU+5dB4B7gVc65Dye5jZJhi2dXsrcnxMioik9FkyuFSGZVllJbXqJK3DNw+OQAuw/3sjpD6duRls6rZsX8Gu7YdiDTTclLnUf72LbvOFetWpDW11WafuZ19w7ySGcPL13RMKXnBVNARlboBtjadVzj2rNM+FCcZQ01Cp5FUiQ0lF9VuKeSwg2A37v8KzMrBubidX4cds7FLjkpOW3R7CqGRx37j/ePpQHLuFxKt9Rc0DPz8LPe+OfVp2dHAA1w1aoFfPXenfT0DVJflXhPmUzuTv/ExJWr5qf1dYOD+E/f/gSHTg4wp7qMj71qlQ7u0+j+HYcZdXBpy9QCaPC2X+S2uvjGu2NOP6ftmjk7Dnq1S1afPptHu44xNDJKaXH+9JKJZIv+Aq7CPYFzbsQ5d9A5d0DBc35bPMcLmlVILLpcSrdsrq9URfUZePjZbsqKizineVammzLmylXzGRl13P2k5gxOlvaOLi6+8W7+/X+2UVJkbOnsSXsb2lqbufdfLsUM/uFFpyvISpNg27/nRx0UGew+1JuU9ebSidZCEgTQrz6/icHhUXYlaXuLyET9Q6MKoKWwLParNyuAjm7tmhbKSyZ+lLI13VI90NMTHFR//b5dAPzmsf0ZbtG4c5tnUVdRwod/tlVjK5MgqGkQfE6GR13GUm2rykpYOq+abXuPp/21C1Hkth918JH2x5Ky7XPpRGsh2XnoJPNqynjxsrkAbNt3LMMtEsk/zjlvHuiy/AmgY6Zwm9nH/D+/5Jw7GnY7Ec4598mZNU2yRVN9JWbQqZ7LqNpam+l4rpvvPvgshvd+rV2TnVWRm+srOdE/zPH+IeoqSjPdnJwQHFQH49wHR0ZZv3ErQFZs4188spfewZGxGgXB2ErIjvblmng1DTLxfq5aWJeRHvBClMptr4rP2WnHwZMsa6hh6bxqykuK2Lb3OH/bmulWieSXoRHHyKgrmDHQH8erdfFj4GjY7XgFX4PHHaAAOk+UlRSxsK6CPeqBjmnBLK8XYesn1lBTPuXSAmkzVom7O0TdQgXQici2gCrShk3bTynwl03tyzXZlmq7qqmO/3l0H8dCQ8yq1Gc2lVK57cenn3uSrp5+qsuL+XSbKj5nknOOHQdP8urzmygpLmLlglq27VO2h0iyBcdQhRJA/zteIHw44rYUoEWzqzR2No7O7j5mV5VmdfAME+eCPmthXYZbkxuyLaCKlO3tyzWx5vHNVKrtKv9z+sS+47zwjLkZaUOhSPW2D4qLtX35ASpLixU8p1F7RxcbNm1nb09oLEvsxcvncrx/mOWNNYB3suo3j+3HOZfRaQpF8k2/H0Dn0xjomEf7zrmPx7sthWXRnEoe3Hkk083IWp1H+1g8pyrTzZjU+FzQCq4SlW0BVaRsb1+uybZU21VNXgC9ba8C6FRbu6aFD976CMNhGR2p2PYr5teo6F8aRQ7DCYa5vOWSJQDjAfTCOn705072H+9n4azKqEG3TnqITN1YAF2WP6W38uc/kZRaPLuK/cf7GRhWwfVo9nSHxoqtZbN51eWUlRQpgJ6CbJ+TN9vbl2uCeXyD/qdgHt9MHTg31lYwr6ZcqaVpcPU5CygvKaK8pGjCHM7J3vYr5tdy+OQgR04OJHW9El2sYTg/+ONzABN6oME7WRVeUE7zdovMzFgKd0kB9EBHMrNdwK3OuQ9NstwNwN8555bNtHGSPRbPqcI52NvTz9J51ZluTlYZGXXs6e7jqrPTO1fsdPzikb2MjDq+ft8ubn90n86oJyB4fz5w6yOMjDqas6wnImjHR9sf4+TAME2zKviXq1dmTfty0WUrG3HA+pev5O0vzfxP2aqmOlXiTqGgpzE4sfjuy5axds3KlL1ey4JaAJ46cJIX1ZSn7HXEE2s4y7HQENVlxSyoqwCgZcF4AP3jhzqjBt3vvWULH//F45hBT9+QeqZFEhAa9APoPKrCPZUe6CVAQwLLzfOXlTyyeLbmgo7lwPF+hkZc1vdAB2fUI6s164z65F553kIM78D6gXWXZ93BUltrM5+55lwAvnXd87OufblmT7f3PZctwzJWLazj6YMnGBwezXRT8k7k1FUA3/797pR+L66YHwTQJ1L2GjJuYX1F1PvLS4pY1lgzNt65pryEJXOr2LbveNwaEj2hIbr7htQzLZKgUB6OgU5FCnclMJyC9UoGLfIPJFVI7FTBSYXTsuRgO5Z41aQlvj3dIYZHHUvn1WS6KTGt9Hu1ntyvnsqZ6jzqfc9ly0mxVU11DI14FYMluaJ/L46m9HuxsbacWZWlCqDT5KpVp2aHVZYWU15SxPKGid/psypLuGPbgSlVzNXvqEh8+VhELKkBtJnNAi4G9idzvZJ5f/ILiH34Z1u5+Ma7dbY1TDA/drb0VsWias3Tt/uwF7hk8/CFpfOqKSsu4sn9OiifqfEe6OwoxLbP/4y+4r/u1/dvkmXie9HMaJlfqwA6DZxz/OW5HubVlNEU1hP9watWcLx/mGWN4wF0e0cXj+89ccq0gInQ76hIbP1DXvZUZR6lcMcdA+2Pew73GjO7NM665vvX35p50yRbtHd08ZH2x8ZuBylLgFJF8XqgzZjw45yNVK15+nYf9gKqbA6gS4uLWN5Yw5P7dFA+U51H+6gpL8mKeZfbO7q4+a6nxm7r+ze5MvW9eOb8Gn75yF5NmZQikePa/271Iv7jNefz9IETXPn5+3j4uW5gvIAYeNkIw9MInkG/oyLxjI2BzqMiYpP1QC8JuzigJuK+8Msif5l2IG6hsXjM7A1mdr+ZHTOzk2a22czebWbT6i03s2Ize7uZ3WdmR8ys38w6zeyXZvbq6bazkCj1N77O7j4W1FVQnuVfDKrWPH27D59kVmUps6syH1DFs3JBrVK4k2BPd4hFsyuzIrDxvn8njn3W92/yrF3TQnnJxMOLdHwvtiyo5Xj/MAdPqBJ3skUb1/6LR/bS3tHFmfNrOWNeNb/a6iVK/mv7Y2MZHfF6keOlnup3VCS+sSrceTSN1WRVuJf61wbsAm4D1sZYdhA45Jyb9vhnM/sy8C6gH/gtMARcAXwJuMLMXuucS3geJTObA/wauAg4BjwAnAAW++s9APxyuu0tFEr9jW/P0dyYwirorfqPTU+yt6efmvISPtV2jnqxEvDM4T6WzKvOioAqnpULa9nY0UV37yCzq8sy3Zyc1dndx+lzsyPbQN+/qdXW2syfdx/hh3/uxCBtVZXPbPRqFmzff4L5ddmdvZRrop307w8b197ZPV4M9eCJgbGMjljZCMHMC8Gc0LMqSzGD7r4hSooso9PcyeQ0n3fm5eMY6LgBtHPu2eBvM/sucH/4fclkZtfiBc/7gZc45572758P3AP8LXA98IUE11eEFxxfBHwTeK9zrjfs8aA3XSah1N/4Orv7eNGyuZluRkLaWptpa23mys/dy+lzq/UjkqDdh3u5aOmcTDdjUiv9aVie3H8iZ/bJbOOco/NoiEuWJzLpROrp+zf1HFBXUcKWj11FUVF6TpKtmO+lDj914AQvWZEd+1q+iHfSacOm7QyNTEzTDjI61q5pYf3GrROC76B3OfjtDPeFu57m5t8+xWUrG5P/T0hSBNkIwTbt6gnxvlu28N5btmTdlJT5bCyFO48C6IT70p1zb3HOfTuFbVnvX38oCJ791z0AvNO/uW4Kqdz/CLwYuBd4W3jw7K/3pHPusajPlAmU+hvbwPAI+4/350QPdLjljTXsPKSKvonoHxqhqyeU1eOfA6rEPXNHegcJDY1kTQExff+m3kPPdLN6yZy0Bc8Ac2vKmVdTrkJiKRDr5FJTfWXc4LqttZkbrjmX5vpKDK/nOV7v8uols3EOOvzx1JJ9omUjBKdPNAVZ+vQPj1BabJQW508Kd1b8J2a2CLgQLw381sjHnXP3Al3AAuCFCa72ev/6Jufc9KpCCMDYj0q9X1BnQV25UpZ8e3v6cS77K3BHWt5Yw7NHehkYTnhERMF69oiX7rckBwLohtpy5lSXsV2VuKctmJZuUZacFAs/qAcoMvjM32roRbIc7R1kx8GTrF4yO62v297RxYn+IX6yeY8qqydJe0cXF994d9SMjeCkU7zgGrzP2wPrLmf3ja/kgXWXx/2cXbC4nuIi4+FnFUBnq8mGuqieRHqEBkfzqoAYTD4G+hRm9nzgNcAKoA5vfHQk55y7YgqrbfWvH3fOxdrbHwKa/WX/MEkbFwDn4I2hvsfMzgWuBRYCR4B7nHN3TqF9Ba+ttZmK0iLe8f2/8O3rLmJVU12mm5QVgoPtxbOzo7cqUcsbaxh13tjeFr/XUqILprA6IwcCaDNj5YJanlAAPW17xqaly57PdJA+euvmTtbe9ihnztdnNlmC4Of5S9I3RCNIKx0Y9orDqbL6zEWm6oaLTNWNlaY9VdXlJZy1sJbNzyiAzlYLZ1Ww91h/3GVUTyL1QkMjVOTRFFYwxQDazD4PvIfxoNkxMYAObk+1xzcoVhZvfPVzEcvGc55//Qzwr/hGkboAACAASURBVHjp4eHtXG9m9wHXOucOT6GdBa2+yitK1NM3mOGWZI/nggA6x3qglzV44+92HjqpAHoSuw57oz9yoQcavOq+P/5zJ6OjLq0pqfkiKDCUjcMyLl/ZSJHBHdsOcE7zrEw3Jy9sfuYoZcVFnJvG9zPezBYKoKcn2nsKXvD8wLrLx24H72+yikqtPn0OtzzUydDIaF6lp+aL1Utm84tH9sVdRvUkUq9/aCSvCojBFFK4zezvgX8G9gBvA+7wH1oDvBuvV9iAm4DLo60jjmAivt44ywQDNhM52g9OJS8FPgx8DzgLr8f8cuAJ4CXAT6bYzoI22w+gu/uGMtyS7NHZ3UdpseVcFdUzGrxgcMdBjYOezDOHe2moLaemfMoJOxkRGhwhNDTCsg//Sqmh09B5NMSc6jKqs3B7z60p58LTZ3PXtgOZbkreeOiZo5y3aFZai9uosnryTeU9nUqa9mQuPH02oaERntinuhPZpL2jixfd8Ft+8cg+io2xKSijnVLu6gnptzLFQoMFHEDjFeUaBi53zn0T2AfgnLvTOfdV59wlwMeB9xM/EI4mvEc7GYL/qwT4rXPufznnnnTOnXDO3QNcBYSAy8zspVEbZPY2fw7qzYcOHUpSs3Jb8AV0VD3QY/YcDdFcX0lxjvX0VZWV0FxfqQA6AbsP9+ZEATHwDhp+5h8EOFQkZTr2dPexKIuHZLzsrPls23ecPWFT8cj09A+NsLXrGKvTmL4N8YtcyfRk6j0Nxs4rjTt7BOn8+/zU7RHnTWN28+su4POvu2CsnkQ4/VamVv9w/qVwTyWAPh/4o3NuZ5xlPgl0Ah+ZYjuCAXs1cZYJHktkcF/4Ml+PfNA5twe43b8Zday2c+7rzrnVzrnVDQ2aYgLCUrh7FUAHOrv7ci59O7C8sUYBdAJ2H+5jaZbMCTyZDZu2j42rDKhIytR0Hu3LyvTtQDAV+SU33aNekxlo7+jikpvuZmjEcevmzrS+j9Eqq5eXFKmy+gysXdNCafHEE9npqFa/cFYl9ZWlbNj0JEvX3a7PZBaYbIjEA+sujxpE67cydUKDI1SU5NcQh6n8N9V46duBAQAzG0up9qtdP4Q3fdRUPONfnx5nmcURyyayPoDdMZYJ7l+QwPoEKCsporqsWCncvvaOLh7rOsb9Tx/OyR/N5Y017Dp8ktFRFamP5Xj/EIdPDrC0ITcCaKWGzszoqKOrJ8SiLCogFq69o4vP3zk2y6N6TaYp6KE6fNI7GXykdzCt72PkdEkAV6xs1PjnGWhrbeaMhhqKiyyhKaiSxaumPkxoaFRZP1kikd/BWMt09YR0IiQF+odGqCzgHuiDwNyw20Fe8/KI5WYRvyc5mg7/+mwzi3Xk8vyIZeN5kvE08rkxlpnnX6sLbgrqq8pURAzvR3PdxkcJYs9c/NFc3lhD/9Bo1Ck/xNvGV3z2XgC+ft+unNi2Sg2dmQMn+hkacVnbAx2vZ0USlw3vY/g43BeeMYcn9p9AM25OX7c/Hdk//tUZSRnbnKgNm7YzErHd9JnMrAWzotekCf8djPebqBMhyRcq5CJiwA4mVsB+CG/s8juCO8ysBbgMiJfmfQrnXCfwF6AMeG3k4/445UXAfuDBBNY3BPyPf/OUFG0zK8UrIgaweSptLXT1VaV0K4Bmw6bt9A/ldqpsUIl7xyGdQ4oU9FAdOjEAeHPF5sKPabTU0HSkMeaLzqPBFFbZGUArw2Bm4s0TDJl7H69pXcTuw71s6ezJyOvngzu27Wdk1PGq8xam9XX1mcw+50WpqB/5OxjttzJSrh3TZbP+odGCDqDvBJaZ2Vn+7U1AF/BWM/uzmf0U+CNeEPy9abTlBv/6JjMb69U2s0bgK/7NG51zo2GPXW9mT5rZf8dY3yjwbjO7Iuw5xXiVwpf57f/ZNNpasGZXlSmFm/z40Vze6E9lpXHQp8iGHqrpCFJDF/hV4WdVlqQljTEftHd08fbveedT1976SFaeLFGGwfQFJ8XiZdxk6n18+bkLKDZ40zf/pPTRabp9635Om1PF2U11aX3dWPuMA23HDDjeP8SDu45wXnPd2BCJaOn80YZRRJNLx3TZrNDngf4BXsBdBeCcGzCzv8MLQFf7F4BfAp+fakOcc7eZ2VeBdwJbzewuYAivB7kOaAe+FPG0eUALXs905PoeMbP3Al8A7jCzh/DGcLcCZwDHgNc65/TpmIL6qlJVf8X70Yx2IJZLB7JzqsuYU12mQmJR5PIJkrbWZtpam3nJf9zDWQtrFTwnIAiugpMmB08MsH7jVoCsev/WrmmZ0E6AChWfSkiseYIDmczU+O0TBwGjd9BrX5A+Ctm1/2Wj9o4ubvrNk+w71k9NeQk/37I3re9ZtM9kQNsxfdo7utiwafvYcdmVZy/gny4/M+5zgt9KIGZmSi4d02Wz/sERKkryK4BOuAfaOfecc+7TzrmHw+57EC+t++XAG4ELnXN/45wbnk5jnHPv8tfzF+CleHNM7wCuB651zsX+9Yu+vi/izfv8a7yx2n+Nd9Lg68AFfvtlCtQD7Vm7puWUqatyLVW2vaOLk/3D/PihTp0pj5APPX3PXzKHzc90a1xlAnIl4yBar8masxfo4DwB8U5+pavgVCwaRzs9kdMVnRwYTvtQm/DPZDTajskVDMMIz9SIll3ylXt2Tmk/0PCn1AoNjVBZVrhVuKNyzoWcc5uccz9yziVS4Guy9f3QOXexc67OOVft3P9n783D27que+13YyIBzqMkQhKpkZZk2aJnW7bj2HXo2EnM5jYd75DmXudrm6RJmrCV0wxO0sZKlLZpmuS2vW1vh9s0rtOEtms7cmLFiad4pGaLkixRA0hKnEcQIID9/XFwKAoEQIAEiDPs93nwSAAOwXW4cfbZa6+1fkteK6X89tzU7TnHPiSlFFLKO9J83nNSyvdIKWullB4pZaOU8v+TUnYv1VY7UuVzMzY9Q9Tmys1tLX7W1/pwO5dX8TNX6DeccFS7rJRgxuUUqiVKLrlhXRWDk2He7p9c+GCbY6aMg7niU1etrlAaBhmSavPLX+ldNsGpVJjp+2ckjLLxpV+TqVKB1TjmhrmO8lyhry8+cWTJ34NkGyEfu2ujadZ0RmYmGiMSk7augVYoqPR5kBJGgyoKPRWO8Z6rGpZV8TNXGGXhYVTaWvysrvLiWuaWKLnkuqZqAF7rHiqwJcbHrBkHbTv8HOkZ48SF8UKbYngeuH3dvNeMsilm1u9foTHaxoMax/ySat2SKisy2++BvhGy//N343YIvrXvpNIkyAHT8TErtosDLYRYu5THcp6EYvmoKnED2F6Je3omSs9okMYaY6r1LoTRFh5Go3c0yOmBKT5+1yZTbpAArK8tobbUw2unlQO9EO2tzbhMWJLxnqs1xeFf/s5LaqG3AJGoljVVX1ZkuE2x5OmjqrZ9IYzmsKo04PyS7fpksd+D57r6iQFT4ahqaZUDghZ1oNOJiHWjCQkuBrnAZytMSqXPA2D7XtDnh6eQEppqSgptyqKwgghaPnnyYC8A77m6ocCWLB4hBNc1VvOqikAvSFuLnz97pou+sWkiUUlDpZf21mZDOFfpeOnkIA6h1X6CEi1Kx+MHerjSX85/fuy2QpsyD32s5oogffCWdWoMF6C9tZlPPXrgspKyQjqs+njpomZlxS6+fP+VahxzRKp1S6XXzUQoQiRH34M9e7vmlSnqGXpqLLNnOqyVCtophfvsEh7n8meyopBUxR3o4Ul7p3B3D2hK5GaNQKud8vQ8cbCXK/3lrKs15waJzvXrqjk/HKR3VGUWpOP88BTnhoP8wd3Npso42LO3i0Q5ClWKMZ/TA5McPD/K/Vcbd0z19NGuP7mHCq+Lv3/htMoqWIC2Fj81JR6KXA7DZBW0tfh5+cG7uGJlGVetrjDFPGIWPn335nl15l63k4fet40V5UU506RRGXq5RY9Ae+3SxkpK2bSMdihMQpVPpXADnBnSHWhzOliJEQ+v21nwhYcR6OgM8PDTb3FhLER5sYuOzoCp/yZT8cjkzQ/vw2+SqGoh+NFhrRPiu69cWWBLskMt9NKT2NrG7UrX8dUYPH2oj6lwlJl4yrnKKkhNz0iQi+Mh/vjeLTxw+/pCm3MZN62v4XuvnSUcieFxKbmhXFBfUYxEW4fqdc+fe88WrvRXEBiZ5vPv2cqHbp2vdZAtKkMvt8w60DaKQCsU87iUwm3vCPSZwUnKil2zGwpmRI943LS+mq0N5bZfnOkKnxfGQgCMTS9/S5Rc0tEZ4NvPnZx9ruq4UvP04T62rCqnyWQZB0arATUSyVrbfPXpLsN///fs7Zp1nnVUVkFyfn68H4DbN9cV2JL53LiumumZGIcCo4U2xTL86ytnqPS5efnBu3jq97VSjIlQhMcP9OAQ8J6rVuXk96gMvdxiOxExhSIZ5cUunA5h+wh09+AUTTUlCGH8iMZCrK32cTYeUbczVlMm37O3i+mZy7v/mfl88kFHZ4CbvvIsb5wZ5vzwlOGdq0TUQi81Zr2eVVZB5vz8RD8ry4vZvKK00KbM44Z1WheEV04PFtgS86PP008d6iMSjfGjw31sbShnQ20JX/1RF9989gRup4OX3s7N3zqxpZUAvnT/NtsHGRbLJRExa7mc1jobRd4RQlDpdadsG2AXzgxOmrb+OZHGmhL6x0NMhSOFNqWgWG3harXzyTV6hLJvbBqAcRNmHOgLvVUVxQCUeFQpho5Zv/8qqyAzItEYL5wY4LZNtYbcyK4pLWJTfSmvnFIijkshcZ6eCEV58AeH+GzHIc4NT82KfYUisZzO33qG3ncfuBEJFFkserqcTIetWQOdsQMthIhm8bD3StziVPrctlbhnonGOD8cNK0CdyJrqrWNgHNDxl5Y5hurLVytdj65xqwRykR00aJ7tq2kpMjF+0ysHJ9LzPr9V1kFmXHg/Chj0xFDpm/r3LCumte7h4hEYwsfrEhKqnn63145R3gZSh1uWldDQ0UxP3zzfE4/106oGmgtiyHTh4psW5gqn8fWKdyB4SDRmLRMBHpt3IG2exq3WXsBp0ItxNNj1ghlKu69ahUXx0O8fma40KYYArN+/xPTR0ETSlJZBZfo6Azwwf/7KgBfeeotw2aNOByCyXCUTX/8tFJTXySp5uOoTN5lN9fzt8Mh2NpQzk+7+lm360l2fPEZWr70jFLIzwLbO9BSSkeyB+AE1gMfA4aAL8dfV1iUSp/H1iJi3YOTAKYTHEqFcqA12lr8bGsow+nITSuMQpOY3lte7DL1+eQas0YoU3HXFfUUuRw8dai30KYYgrYWP1+6f9vsczNdz3r66OMf3QmA26mWVDp6Su/4tJbo2Ds6bcjSi47OAI++pnV0lSgRx8WSaj52pkjbz/X83dEZ4PkTA4A2jiPBGYanZtSYZoGuxVJs1xTuVEiNbinlt4E24DNCiF9fumkKo6K1ELBvBPrMoLl7QCdS5XNTVuTibHxjwM70j4e5d/sqU/UCToee3uuv9PLOK+pNfz65pL21GbfTOhkHJUUumleU8s8vd6voSJwrVpYD8J3fusaU1/N2fwX+Su9smzWFeUov9uztYjqiRByXSntrc9Lez79x45plyTDZs7eLUCR1Cr4a04WZVeF2KQc6JVLKF4A3gU/k8nMVxqKqxKPtwKVIobE63YOT+DxO6kqLCm1KThBCsEYpcXNxbJqe0Wl2rKkstCk5Z9OKUo5fmCi0GYaircXPdU1Vs3VHZopQJqOjM8BbfePEpIp46Rzt1VoIbV1VXmBLFocQgndfuZLnTwwwPm3frK+5mKX0wix2Gp1rG6uQQIXXddk8/Sdt22dLHfI5f2cyXmpM0xMMR3E6xLwNa7PjysNnngHenYfPVRiESp+bcCRGcCaKz5OPr5CxOTs4xdpqnyGVPxfL2mofJy6OF9qMgtJ5bgSAHWsqCmxJ7tm8ooyX3h4kGpM4Hdb53i6VqXCMG9dX870P31xoU5ZMuv7BZt0UWCpHe8Yo8Thny1TMSEmRk3A0xvaHnsFf6aW9tdm24wlaim4gicNitNILs9hpdPYduwhAx0duZV1C2Vxbiz/v10KqcUw8RpGa4EwUr9tpqTUz5EfsaxugJActTJXPA2DbVlbdg5OWUeDWWVvj49xwkFjMnlkFAPvPjeByCLY1WM+B3lRfSjgSs32WwVwi0RjHescsM94q4jWfo71jbFlVjsOkm0YdnQH+9uenZp+rrAItpTex/tWIpRdmFbEzGvuOXWRdbck853m5SDaOiUyFI6psJg3BmSjFFhMQgxw60EKIGiHEt4ErgFdy9bkK41HlcwMwPGm/OuhoTHJuKEhjrXkjGslYW+0jHIlxYXy60KYUjP1nR9iyqtySE/2mFWUAHL9g7yyDuZwemCQUiZk2vTcRq4miLZVYTHK0Z4ytDeYdX63eV9XRzqWtxU9tqYdil8PQpRfJ1NT/8B57Zw9ky1Q4wsunBnlnc33BbJg7jgKo9Lqp8rkRgNetbeQoUbH0TM9E8XqsJ4SYcf6tEOJUmrdLgRq0UrIw8NDSzFIYmcp4BNpuStwdnQEefvotwtEYj7x6ji0ryy1zM5xV4h6cYlWF/Rbc0Zjk4PkR3n/N6kKbkhc21ZcCcOLCOK3bVhbYGmNwpGcMgG1+8zpYc2lvbebBHxy6TGDJzhGvs0NTTIajpt4gUVkF85kKR+ifCPHROzfxB3dvLrQ5adFTjM8OTnH7np8yFY4u/EOKWV46OUg4EuPOKwrnQEPqVPFbdj9LcOTyoIPdy2aSMT0TtZyAGGRXA920wPth4Hng81LKlxdtkcLwXErhtk8EWm+doS9OR4IzPPiDQwCWmCjntrK6cX1Nga1Zfk5enGAyHLWkgBhoCs3+Si8nLiohMZ2jvWN4XA421JUW2pScoM9DX/7PowxOhqkt9fDZ+7ZaYn5aDEd7tQ0SM0egVR3tfN7qHSMmNYVys7C2xsf1TVX8sDPA792xwXK1oLmmozPAnr1dBEaCCKBv1JgbRr0jyTP27LzBlYxgOIrXYi2sILsU7nVpHn6gVEp5t3KerY+ewj1iIwfaLK0zFktDpReHsG8v6ANxAbGrLepAg1LiTuRIzyjNK8os1WO3rcXP4x+7FYBP3r3Zts4zaAJiTodgc7x8wYwkq78sdjtsm1UAcDigbYxcabLMkabaEk5enGD9g0+pWtk06MEKfeNIAp977Igh/16pNrIkqDGeg+1roKWUZ9I8eqWUkXwaqjAOlTYUEbN6Kp3H5aCh0mtLB7qjM8BDTxwB4L//wyuWveltXlHG2/0TRG0sFKcjpVYfu83E0clUrCovxut2ctLm2QZHe8fYUFdi6oVbsjra/3nrOltvjBwKjFJb6mFleXGhTcmYjs4ATxzoAVSLuVR0dAbYuXsfn3hkv2mCFekExtQYX2J6JragEJsZsc7Wu2LZ8LgclHictkrhtoNAz1ob9oLWd7v12rSekWnL3vQ2KiXuWXpHpxmemjF1em8qHA7BhvoS3u6fLLQpBeVoz5ip65912lr8vLjrTo5+qZUil8P2dbSHA6Nsa6gwVRr0nr1dTCsxuJQkRp2TYcRgRbINrrmoMdaYjrexshpZO9BCCI8Q4jeEEH8jhHhSCPGfQoi/FUL8phCiKB9GKoxHpc9jKxExO7SkWFvt4+ygvZwrq6fmz2WzUuKe5aguIGZBBxpgQ10pb9s4Aj04EaJvbNpSGyQ+j4vbNtXyzJELSGnPLJLpmSgnLk6Yqv4ZUjt/gZGgan9E8vtwIkYNVugbXKm2c4zo+C83Wgq39eK1WZ2REOIW4Djw/4AHgHcD9wL/C/gX4LgQ4tZcG6kwHlUlbltFoPWdRme8n6hRW2cshbU1PgYnw0yE7FONYfXU/LlsnKPEbXeO9IwhBFyx0joO1lw21JUSGAkyFbbPtazT0RngXX/xcwD+5menLOWYvGvrSgIjwVmBNLtxrG+caEyarv45nfOnUroXvt+aIVhhhyzFxWJ7ETEhxDbgGWAtcBr4UzQn+oH4/98G1gA/ih+rsDBVPo+taqAB7t/RgNspeOC2dby4605LOc8AF0Y1RcntX9hrmx1xO930fnL0Ak4h+Pozx20zvqk40jPKupoSSoqyaURhHvTNklM2S+PWU0EHJ7XN3cHJsKUck7u2aO18fv1vf2HLyOWhwCgAV5osAp2uVlbHqplPmZDufmuWYIUdshQXi+1FxIAvAT7gYWCzlPJzUsq/jz8+B1wBfCV+zBdzb6rCSGgp3PaJQIPW93p6JsZKC/ZJ7ugM8L3XzgH22hFvb23G7bw8+cqKNz3dsYjGUz/tMr7J6OgM8Oyxi5wamLSsA6K35nq7315p3FYvyXj+xAAOAePTEVvN0zpHAqNU+twpa06Nytxa2XSV21bMfMqE9tZmXI759+Fv/NoO0wQr9DFeVaGJ25UVu0zh+C8HISUixjuALinlH0spY4lvSiljUsrPAl3AHTmyT2FAOjoD7HvrAmcGpyy7AE1GbzxCq0+QVmLP3i5CEfuJnLS1+Ll1o9b3WmCe3e5ssbpjkSkdnQF2/eDgrBK5VR2QplofDoHt6qCtXpKxZ28XiSL6driOdYXm7712jmA4ymP7ewptUtbotbKnd9+XcgPAiplPmfDeqxvweRwUuRymvg+3tfh5+cG72NZQzpUNFaazPx9EojHC0ZglI9DZ5K95gTczOO5N4P7FmaMwOnokS1+M6wtQwPKTRd+YtgizogNt9YVnOrweF+vrStj3qTsKbUresPP4ziWdGq6V5q8il5O11T5O2iwC3VDpTarkaxXHxI7XceKaIxSJmX7N0d7afNk5gTUznzLlhZMDjE1H+c5vXcO921cV2pwlc8O6ar77ylnCkRgel/XEs7JhOh6YsXsEugvI5Ju9CjixOHMURsfOkaxLEWhrLMbmYqda4ETODwdNlxKYLXYe37nYyQHRlLjtVQPd3to8T+3VSo6JHa9jK6459HTfSq8bgBXlRaaMuOaK779xngqve7bG3+zcuK6aUCTGocBIoU0pOMF4271iO4uIAX8N3C6E2JnqgPh7twN/s1TDFMbETgvQRHpHpnE6BHVl1uvWZmcBjMBwkNVVvkKbkVfsPL5zsZMDsrG+lNMDk7Pp6nagrcXPJ39p8+xzs6aCpsKO17FV1xxtLX7+7cM3AfDgu7dY5juaDR2dAW5++FmeONBDJBrj6UN9hTYpJ1zfVA3Aq6eHC2xJ4ZmOb37ZOgItpfxb4JtoKttfFUJcJYQoiz+2CyF2A08Dfyml/Ot8GawoLHZagCbSOzpNfVnRbCsrK6HviJcVa1UdqyqKLbXwTMVUOMLgZJjVVdb+/s4VsQFwOoQtxjeR9tZmEi9fqzogG+pKCUdjnBuyV2/3zSu1fueP/s7NphEgyhT9OvbFozn+SuvO03rdc6rtHyusOTavKMPncbL/nP0ilXpqvp7ZNxmOWkaPoqa0iI31pbx6erDQphQc5UADQogo8HE0le1PA53ASPyxH2gHSoBPCCGiCQ/7NaO0KHbcAdfpGwuy0oL1zzr64gzg7//H9ZZclCWiRzGs7kDDJRGbz963hWhMcvOGmkKbtOy0tfip8rnxus0tVpMJG+pLAPspcZ+PbxissWhWSVuLnwfffQUAj/7OLZb87urOVbJ6drDOmsPpEGz3V9BpQwfaiqn5c7lhXTWvdw/bKgMoGfoYJ5bWWIFszkgs4WG9v5xNSZTqL7eRVH/v6DQNFqx/nktTjbbo7h60R+3kuWFtgWb1Gui56Ollr3fbL70sFIkyPDXDA7et5/Tu+ywXoZyL3srqpM2UuM8NB/G4HNRbsNRGZ2tDOQBHe8YKbEl+SOZc6Vht02vHmkre6hkjFEl+vlbFqqn5Ojeuq2Y8FOGt3rHZbAq79W7v6AzwoX98DYA/+o+DljvvbFK4HUt55PMkFMuLLtXv8zj5lWvXWOZGlg4pJX2j05aOQAOsq9Uc6NMD9nCgA8N6BNqa0apkbG0ox+t28lr3UKFNWXbODE4Rk7A+7lxamee6+nEIePjpY7ZatJ0bmmJ1pReHBUttdJpXliMEHO21pgOdyokSYLlNrx1rKglHY5bdDEmF1csBhybDALznr17gk4/sJzAStFXvdj2LZGBC+zsMTIQtd97KsVUsmvqyIi6OTxfajGVhLBhhKhy1ZAuruZQUuagvK7KNA31+OIjbKSwdrUrE7XRw9ZoK3jhjvwj0qXg68/q6kgJbkl/0xYuePWiXRRvAueEp1lRbe0OstMhFU02JZZ0uqztXc9mxthLAdnXQ7a3NuBI2uaySmt/RGeBrP7qUip6YxG2lVPVUWD1FH5QDrVgC9WXFXBwPFdqMZaE33gPa6hFo0KLQdnGgAyNBGiwerUrGdY3VHO0dYzJkL3mKt/u177WeaWFV7LB4ScW5oSBrqq3naCWydVW5ZSPQmtaKdduRzWVVhZcV5UUcsJkD3dbiZ0N9KS6HsJweRboSBB2rpKqnwuop+gCubH9ACOEGfgW4A9C/6QHgOeD7UsqZXBmnMDZ15UWW3QFPxMo9oBNZX1fC3iMXCm3GsnB+eMpW9c861zZVEf2p5MC5EW7ZWFtoc5aNU/2T1JcVUVbsLrQpecUOi5dkjE3PMBqcsayA2Fy2NpTz5KFexqZnKLfY97mtxc/gRIgvP/kWoDlX7a3NlnCukrFjTaXtItCxmKR3JMgHrlvNw++/qtDm5JRM5lkrZlPMpaHSm1QE0ErnnVUEWghxLdAF/D/gAeDe+OOB+GvHhBDX5NpIhTGpLyvi4pg9Urj7Zh1o60egm2pKGJoMMzpl/b0wrQe0dSb0TLlmbRVCwOs2S+M+NTBh+fRtsFcK7Fz0ll1WT+EGLQINcKx3vMCW5Ad/fBOk4yM7LVf3nIjb6aB7cMpWIlOnBiYYm47Qsraq0KbknIXmWatmU8ylvbWZIpe1s0iyaWO1GtgLfU5E0wAAIABJREFUNAHngd1ojvOHgYeBs8A6YK8QwroznWKW+rJiJsNRJmyQBto7EsQhoM4GtbKzQmIWV+KenolycTyEv9L6i+1EKrxuVpQV8e2fnrTNok1Kyan+yVl1aitj13aD54a0iIddItAAR3tGC2xJfnirdwwhYPMKa1+vHZ0BnjmqZXzZSWTqzbNaxP2aeA24lUg2/+pFYi6HsEyqejraWvy0blsBYLkUfZ1sUrh3AdXAN4H2xFRtIcQXgD1ovaJ3AR/LlZEKY6ILL10cm6bU4ovS3tFp6sqKcDutLxugR+i6BybZscZ6NzcdPS3fjhHojs4A/RPh2R6V+qINsNQNbi6Dk2FGgzO2UODWx3D308foG5umwuvmi+/bZtmx1Tk/rEegrX9N15cVUVPisWwd9LG+MdbVlODzZF1paCr27O0iHIld9pquV2Dl67Xz7DDlxS7W11pvPtbHbc/eLnriOivtrc2cGZziG88e5+6tKwps4fIQGJlmW0M5T/7+bYU2JS9k4w3cA5wCPpmszllKGQE+FT/m3tyYpzAy9eVxB9oGQmJ9Y9OstEH9M2jpjw4BpywuJKYvtv02dKD37O2adZ51rC4ydSouIGaHFG7QFnEv7boTj8vBr11vj3aD54amKCtyUeG1Vk1wMoQQbG2wrpDYW73jbImnqVsZu+oVdJ4dYcfaKssKeLa1+Hlx152c3n3fbAnCtoZypNSyK6zOxbFp3jgzTOu2lYU2JW9k40D7gVellImK7LNIKWPAq0DDUg1TGJ/6Mq0e2A4OdO/oNA02qH8GKHI58Vd5La/EfakHtP0caDsu2vQWVhssGPFIhcMh8Fd6Z7/rVufs0BSrq30IYc1FeSJuh+BwYMxyZRjj0zOcHZpiy6qyQpuSd+yoVzARitB1YZwWC2e4JWObX9sQOmID8d298bKEe65UDjRAEC2FeyGq4scqLM7cFG6r0zc6bYsWVjrrakvptrgDfX44iNMhWFlun3HVseOi7dTAJB6Xw3YZB6urvLPZFlbn3HCQNTYZ347OAM+fHACsVzvb1acJo9khAm1HvYID50aQEq5ptJ6AWDpWlhdTXeLhiEV1C0Cbl3bu3sfnOg7jcgiOBKx7rtk40AeBO4QQV6Q6QAjRDLwzfqzC4lT63HicDvotHoEem55hIhSxhQK3zroaH6cHJkmTcGJ6AiNBVpYX47JBXXsidly0neqfoKnGh9OiKYOp8KdoJ2I1pJScH56yhQI3aGUYM1FrlmHoKa52cKDbWvw8/P7tl7VT/Ox9WyxdctF5Vuv+sGO1vSLQQgi2NZRbNgLd0RngwR8cmr3fRGKSz/zwsCU29ZKRzcrx7wEPsE8I8SEhhEd/QwjhFkL8NvAs4Ab+T27NVBgRIQR1ZUWWT+HWW1jZpQYaNCXuiVCEgYlwoU3JG+eHp2wXjdTRF22e+OaBFRUyE7GLAnciq6u8DEyECYajhTYlr/RPhJieidkmAm3lMoy3+sYpL3bZZtNar5d9+uOa2FJwxrrXakdngL/adxKAe7/5vGWdq1Rsa6jg+IXxecJxVmDP3q55312rbOolI2MHWkr5L8C/ASvRHORJIcRZIcQZYAr4O7Ta53+TUv5rPoxVGI/68iIujls7hVtXa7ZLDTRAk97KysJp3IHhIKstnLK8EG0tft5z1Sr8lV7L91kNR2KcGZqyjYDYXPRNIqtHofUWVmtr7BGBtnIZxlu9Y2xZVW6bWnadLavKaarx8fDTxyxX1w56hPIgobjzaKWyg0zZ1lDOTFRy4qL1+rdbeVMvGVnlLkopfwv4KNANOIHVwJr4/08DH5VS/tcc26gwMPVlRVwcs24EuqMzwMf/rROAj3z3TdtM9G9f1ASXfvVvXrbkTfyW3c/SMzrNj49esNS5Zcvqah+9o0FmotbbDdfp6Axw61f3EY1JvvvKWduNt97n3Op10LMtrGzQAxqsW4YRi0m6+uyhwJ1IR2eAwEiQaExapq5dr4ldt+tJPvXvBwjOJG/ZZRe2xfu3HwlYJ41bH+NUBX9W2NRLRtbFf1LK70gpN6A5zjcBNwNrpJQbpZTfybWBCmNTX1Zs2RRuvZ5jJKh1bbswFjL9zSwTOjoDfP2ZSzc0K9zEdfQx7RnRsgrGQxHLnNtiWF3lJSatu0Osj7c+Rw1PzdhuvFfbJgKtOdCrbeJA62UYlfGWXSvKiyxRhnFmaIqpcJStNnSgrVbXPrcmVgLRFJoqVr3/JKOppoQSj9MyQmKJdc+JWGFTLxWLVs+RUgaklK9KKV+RUtpnNaK4jPqyIkaDM0xbsGbHbvUcOtp5W3OX2K5jmgo9Wnfeom2O1HjDivJiXA5h2TEGbRH3nefeBuCX/vxnttkgaWvx8y//80YAvvDebaZ0nudGKHd88Rne81fPA7DnmS7bjKOO1VJgk82/ybBqhDIZDodgyyrrCImlG2Ora6u4FjpACHEn8AGgEQgB+4G/U06zArQaaID+8ZDl1E+tdjPLFCuft5XPbTGsqdYWLnr0zip0dAbYs7cr5a64ncbb6RCsqiy2bC9oPQKiL+L0jBnAsgu3uWxeWYrLITgcGOXe7asKbU5WJI6dnu0F2prCTuMImiOZbM4yq4OZyTxr5QhlKrxuBy+cHGTdridpqPTS3tps2u94qjEWwIu77lxeY5aZtBFoIcQ3gR8DHwbuAe4HPg8cFULckXfrFIanvkwT1rJiGreVRVrSYeXztvK5LYZVFV5cDsE5C9XHLpRSBvYbbyu2stIjl594ZL+tswyKXE42ryjjsAkjWgtFKO00jmC9uvZU86xTCATWj1Amo6MzwC9ODyG51L/9k4/sp8mkonF2XlOldKCFEPejCYYJ4AXgL9BaWZ0HyoDvCiGKlsNIhXGpK9Mj0NZT4rbazSxTrHzeVj63xeB0CBoqvbMKxlZgoUW5Hcd7dZXPUiJimWyS2CnLYFtDOUcCo8gUNaZGJZMxstM46nXtevuusmKXqR3M9tZmit2Xuxlet5M/+9WrOb37Pst3f0hGsjp3/Vk6vZm5pQ5GcrTbW5txJIjl2+Uemy4C/QDauH5MSvkOKeWnpJQPAFuAnwErgPcug40KA6OncFsxAt3W4ucrbVfOPrfLbql+E68p0Vq915Z6LHPe+rm5ndqMb5cxTcfqKq+lItDpFtx2HW9/pZeL4yFCEWtoVWRSW2mHCIjOlf4KBifD9I2ZayM7kzGy0ziCdo96+cG7aKrxcevGWlPPVW0tfh64bf3sc7vOv3NZaEMoOBPlE4/sv8xJThRjK4SwayoH/paNNUgJpUUu22UVpKuBvhY4JqX89twXpZRTQohdwMvxY76fR/sUBqempAiHwLKtrG5vrgPgofdu5YM71xXYmuWjrcVPy9pK3rHnOf7wnissNRnev6OBP/7hIX7rxjU89L5thTan4Kyp8rGv62KhzcgZqeoI9X7XdmR1lRcpoXdkerbHu5lZaBFqlwiIzpX+S61xVlWYx+Fsb23m048eIBJLHjm32zjO5YqV5RzrM3+vYLfTgRCw/3PvosLnLrQ5BSfV/SmRuVoO6cQw87k2m6slIpgfKQe4MDaNBB776E421JXmzRYjki4CXQMcSvHewfi/1bk1R2E2nA5BbWkRF0y2850pAxNhAGrL7Fet0FDpxekQnB20TnQStDGdDEdpqrGW6N1iWVPtpX88ZBkl/VRpg3ZdiAP4LdbKKl1U0k4REJ0tq8oRAg6brDVOW4ufq/wVOB1aTWyl102Vz227SFYyrlhVRvfgJFPhSKFNWRK/ODXI1lXlynmOk6yMLBW6k1wI8dPEMpnELS7NtmM88vo5rmussp3zDOkj0C4g6cpZShkUQgCoK0JBfXmRJVO4AQYmtPOqLbWfA+12Olhd5aV7cLLQpuQU/XwaLRCJywW6ev754Sk21pcV2Jql09biJzASnBUf8ptc5TQXXGpXZo3NsPbWZv7g3/czN3DpdTtt63D5PC421JVyOGA+IbGolNyyoWa2HZdCY8uqcqSErr5xWtZWFdqcRRGKRHnjzDD/9abGQptiGPT5KVlkNxk9I8GCqLNnUiYTGNECZ0O+MB2dAdvNvYvuA61Q6NSXFVvWge4ft68DDbC22sdZi7U46h7QHOh1NcqBBi29F7CUkNgVK7WNgB/+3i22FKpJZGVFMQ6BZVpZ3b+jgSKXA5/HqaKVcbY1lHPEZBFoKSWnByZpVNlA89iyUkvLN3Ma94Fzo4QiMW5aX1NoUwxFW4ufF3fdSffu+/iLX9uBP40j3FDp5YHb55cP5jurKpvo9sjUzLLXZBuBhfpA7xBCfH4x70spv7R4sxRmor6siIPnRwptRl7QI9B1NkzhBmiqKaFjfwApJfGsE9PTPTiJ0yFm01rtjh6dtJSQ2Ki2M243AaJUuJ0OVpYXc94iDvS5oSDBmRhf+eXt/OaNawttjiG4sqGCx/b3MDARMs2G7/DUDGPTEZrUZuY8Vld5KfE4OdZrvqwCnV+cGkQIuKFJVXumoq3FT1uLf15PdACP00F7azMnLmqbKFU+N8NTM1T53HzhvdvyumGYaa22znLUZBuNhRzoq+OPVOxI8r6ekaAcaJtQX17M4GSYSDSGy2mtpIb+iRAep4Py4oUuFWvSWONjfDrCyNQMVXFVbrPTPTjFmiovbot9VxdLXVkRRS6HZZwrgN6RIK64PoNCw1/l5bxFaqAPBrQN26tWVxTYEuMwHNT0Oq77k5+YpmzhtJ4NpMpp5uFwCJpXlvGWiSPQqv45c+amdveMBBEC/JXF3HPlSr60+yh3b13Bd37rGq566Bnu3+HP6bWti4Xp6eLtrc20tzbzR/9xkFAkNntcJunmdiKdV/BPy2aFwtT0jASREjb98dOzF5/Rb9yZMjAeprbUY5noa7Y0xiMDZ4amrONAD0zOnpcChBBaKysLper3jk6zsqIYZ2KDSpvS0RngcGCM4EyUnbv3mX6OPnR+FI/TweYV5q/ZzwUdnQH+4YXTs8/nquQaeZz1chorKMPngy2rynniQM9sBlgyR8eo46vqn7NHj0YD/MsvzvC5jsO0fOnHBGeidJ4d5smDvVy9poI3zgzn7HcmRr71uePh92/njs117D16AQGXfd927t637DXZRiSlAy2l/O3lNERhTjo6Azy+X6t7mNufDox9486U/omQLRW4dXSl6jODk+xYU1lga5aOlJIzg1Ncr1LKLmNNtc9SKdyBkSANJmrnk09SLZDAvHP0wfOjbFlVhselskhAi1pNz8Que80MKZXdg5M4xKUyEsXlXLGqnH995Sy9o9O8enrI0NfxXOe+wusmGpOEIjF+2Blgu7/CEDaaCW98btPHe2AizIM/OMStG2t4rXuYyVCEkqKlZ0ama5G1oryIHWsq6fjIzsveb29tnpdubsdOF+ruo1gSe/Z2EY5entShX3xWYGA8RJ2N00DXVPsQAroHrOFcDUyEmQhFlGhNAloE2jrpV72jQVZVFhfaDEOQboFkRmIxyeHAKFf6Vfq2TiHa3OSC0wOTrK7yqY2QFGyJiyG+1Ttm6Ot4bssjCYwEZxgPae23hibDthSYWip/8ZMT814LzkR58+wI0ZjkwLnc6A6lmzv2nxvh9k21895ra/Hz8Pu346/02lrE0Z6FnYqcYdYbd6YMTITYbuOFWrHbycryYs4MWaOV1ZlBlTKYjDVVPkaDM4xNz1BebO56tVhM0jc6zSoVgQasN0d3D04yHoqo+uc5FKLNTS7oHpxUc3EamuMO9LG+cUNfxwu1PDJDNoTRSDWuQ5NhhIDXzwxzy8b5zm22VJd4GJwMz3u9qsTD0GSYWzfVJf25uenmdkVt+ymWRKobtNFv3JkQi0kGJ8PUllmj9nexNNb4ODNojQi0LlqjVF8vZ7YXtAWi0AMTIWaiEr+KQAPWm6MPBbRWTdv95i8pyRXtrc143c7LXjN6SqWUku6BKdapbKCUPPvWRZwOoUWZU8g5GOE6zsSJN4KjbybSzdvNK8p4PQd10LGYxOMU875aXreTK1aWUuJx0rJWzbOpUA60YkmY8cadKcNTYaIxaXsl36aaktnIrdk5MziF0yFmex8rNN6+OAHAvd98np2795k63U5vYaUi0BrJ52iHaefoQ+dHKXI52LSitNCmGIZLKZXappHX7TR8SuWlchq1mZkMPS06GtNK5GQS+WOjrLUyceKN4OibiXRr62sbq+g8Mzz73ciWjs4AO3fvY/1nnqJ3LMQtG6ov60X92fu2cH54mps31KpuJWlQfxnFktBv3LrarZVqIQYmtLQWu/aA1llb45td7Jid04OTqoVVAh2dAb793MnZ57o4jVmd6N54pEPVQGvMrVfT+eidm0w7Rx8MjLK1oVxdwwm0tfh5cdddvO/qBkqLXdy/o6HQJqWle1C1sEpHqrRoPVrYUFlsmLXW/7ptXdr3jeLom4m0dcZCMh6KsPEzT2W94T23Xl3nzbMjtLc286NP3AbAV556i7NDU7zWPWTadcByoGqgFUumrcXPv/ziDEUuB9994KZCm5MzBiZCACoCrbeyGpxkW4O56w7PDKoWVomYVcE3FXoEWqlwX0KvV7swNs2NX3kWhwnb8nV0Bvja3mP0jExT4nHS0Rkw5fcz39y8oYbHD/Twdv8kG+uNG6VXLazSkyrlWY85fvd/3WSYv91gPNiworyIi2MhKrxuhICRqRnDt9syMsnqjDs6A3z/9cs733zykf184pH9GfV/Ty5GF2PP3i7aW5txCJgMa++PBmcMpfRuNJQDrcgJNSUey9TJ6igHWmNttd7KasrUDrRec3ddo2phNRcji9Mshp6RIF63k0qfucXQ8sGK8mKuWFnGz45f5Hfv2FBoczImsRXXZDiqFnYpuHl9DQAvnxo0tgM9OKnKadKQShiurrSI/okQxy+MG8KBDkWifO+1s/zSlhX83f+4rtDmWJ49e7sIRS7f8NY3VTJpbZbufr9nbxeJWeFm3kzPNyoHSpETako9DE6GCm1GTukf187Hzm2sgNmWT2bfIBmcVC2skmE1kSm9hZUwYZR1ObijuZ7Xu4cZn54ptCkZY+QWPkajscbHqopifvH2YKFNSUv3wJQqp0lDqhrYT71rEwAn4roVhaSjM8BNX3mWgYkwnWeHVbrvMrDQxvZC82K6+73VNtPzTcYzlxBinxDiDzM47tNCiH1LM0thNmpKihiaDBNbpKiBEemfCOFxOij32jtR49m3LuIQ8NUfHTOtwFRHZ4B7vvFzAL6176QpzyFfWE0IsGdkWqVvp+Edm+uIxCQvGdzBmota2GWOEIKb19fwi1ODyGTKUwbh9IBqYZWOVDWwv35DIw0VxZy4MF5Q+/SskOEpbSNuUPV7XhYy2dhONy+2tzbjcly+uazf7622mZ5vstn6uwO4IoPjmoF3LMoahWmpKfUQkzASNE9UYyEGxsPUlnpsHcnSb5L6vogZBab0c9BF4dSN/nISRaYE8OX7t5k2ZatnJEiDEhBLybWNVZR4nDzX1V9oUzJGLeyy46YNNQxOhjl+ofBRykQ0BeBnOdo7pkSKFkAThruT07vv48Vdd87OyZtWlBV8bFVWSGFItuGdSLp58f4dDZR7XRS5HPPEyay2mZ5v8pE7UwSk7qi+AEKI3xRCPC+EGBVCTAghXhdCfEQIsWRbhRAfFkLI+ONbS/08xSVq4mnOgxPWSeMemAhRa3MFbivcJK1wDvlGX6j904duQAJlXnPWD4cjMfonQqqFVRo8Lgfrakv499fOsW7Xk6bIKmlvbabIdfkSQC3sUqOn57d+4+eGGt9LCsCa0N9kKKo2MxfB5hWlvN0/seg2RrlAZYUUhmQb3nMpXqBF4etnhhmanOHh92+ftzGTVvlbMY+c5qbGndxrgYFF/vy3gd8DpoFngRngLuBbwF1CiA9IKRflnAshGoGvo9Xb2zekmCdqSzyA1vpp04oCG5Mj+sdDrKywdyTLCjdJK5zDcrFzQw01JR4e399D67aVhTYnay6MTSMlKgKdho7OAF0XxonG03szEZ4pNG0tfp450sdTh/sQoJR909DRGeDre4/PPjfS+KbbzCy0bWZiU30ZoUiMc0NTBUuDTyVyprJC8s9cde6OzgB79nbRMxJEAu+7uiHpe/qc+crpQbxuZ8r7ezLlb0Vy0jrQSWqZ70lT3+wCNgIrgH/P1hAhxH9Bc577gNullCfir68Afgr8MvBR4C8X8dkC+Hu0iPs/A/8j289QpGc2Am0hIbGBiRDb/eZVnc4FVrhJWuEclguX08GWVWU8eaiXp3Y9aTpHpTfewkpFoFOzZ28XM9HLI1dmcGL64/PxEx+7tdCmGBojO6lqMzM3bFqhqavrStzJHKV8j/Wn797MJx89cNlrKitk+dEdXikl937zBQ6eH0VKyWP7ey7rXBAYCfKJR/YD2jj9+OiFgs8HZmehtOg75jwksDLhtbmPW+Pv7wf+aBG2PBj/94905xlASnkB+N34012LTOX+HbRI9oNA9yJ+XrEANaVaBFrvB2h2YjHJ4GSY2jJPoU0pKFaoiWlvbabYrdI/M6GjM8Cr3cPApR6TZkqx1BfianMkNWZ0YkaDM7x5doR3bK4rtCmGx8jjq2rZc8OmFWWApsR9KS0+uKxz9hUN5QBU+dwq3dcACCH47VuaONY3zvV/+hM+8cj+eRtpOsEZVTqRCxZyRt8Zf9yJlvb8ozmvJT52Ak1SymullGezMUIIsRot9TsMPJr4vpTyZ0AAzUG/KcvPXgd8DXgRLRVckQeqfB6EsE4N9PBUmGhM2r4HtF4Tsyqeyl7hdZnuJtnW4udjd26afa5u9KnZs7eLcEKPSTPVi/eM6g60SuFOhRmdmBdPDhCNSe5oVg70QqQaR4cQBa95V5uZuaG0yDWrxF0ojY9XTmkq/o9/9NZ5tbSKwqDr3Q5kEMgy033dqKRN4Y47rgAIIX4GPDf3tRzSEv/3iJQy1Tbpa4A/fuxLmXxoPHX7H9DO839KKaWdFZXzidMhqPZ5GJi0RgRan4DqbC4iBpoDev+OBq764jPcv8Oc9TGrq7RF5d5P3E7zyrICW2NcjBy9yoTekWkqvG58Hnu3nktHe2vzZal9YHwn5rmui5QVu9ixprLQphieZOMLGKLmva3Fz/EL43znubcBbTPTTCUiRkJX4i7UnP1q9xD+Si9rqn15/T2KzPnGT04sfNAczHJfNyoZp0NLKd8ppfxanuxYF//3TJpj9Kj2ujTHJPJRtPTyh6SUaqslz9SUeiwTgR6In4fdI9A6QgiaakroHpwqtCmLoqtvHJdDsE71HU2LGaOTOh2dAR59/RyjwRlDKQ8bjcSskrIi42aV6C2P/v3188xEY/znwd5Cm2R4EpV0HUliBoWMPsUkuJ2CI19sVVHLJaArca9KkW2TzzlbSsmrp4e4cV113n6HInuydYjNcF83MvloY7UYSuP/TqY5Rm96l1H4SAixAXgYeANNfVuRZ2pKiixTA60c6Pk01vg4M5juEjUuxy+Ms76uBI/LKFOeMTFrzbteBzgdTz83W+32ctPW4uflB+/imrWVbKgvNaQTk9jyaHompsY0Q+b2D5YpOh0VKvr0/Il+rllbRUmRyhJZCroS969et2bee0Wu9K2Mlsrb/RMMTIS5cb1yoI1EOoc4cR/NDPd1o5NyBhNCfD7+329JKYfmPM8EKaX8chbH62Obk6Z2c1K3PcCHFtP6SgjxYeDDAGvXrs2FWZanptTDkZ6xQpuRE/rHNQe6TjnQszTW+PjR4T5mojHcTnM5oscvTHDVansrqmeC7kj96VNv0T8eotrn5vPv3WZIB2suRlYeNjK3bqzlWz89yWhwhgqD9f5WY5objNSFYGAixJGeMbVwzwG63oOetlte7GJ8OoIEIjHJJx/Zz569XXlJkf/FqSEAblxXk9PPVSyNVOU5D79/O8CyK7VbnXRbgA+hObTfA4bmPE9XRKy/L4FsHOjx+L+laY7R3xtPc4zO7wO3A1+SUh7Mwo5ZpJR/C/wtwHXXXVe4bvUmora0aDZya3b6J0J4nA7KvWqXXKexpoRITNIzEqSxxjyp0FPhCGeHpvjAtasLbYopaGvxc9eWerY/9AwP3L7BFDdZs9duF4pbN9XxzX0nefntQe650lh9v9WY5gYj1by/eHIAgNs21S7777YSHZ0B/vpnb1/22kxU8ls3reWR187NtqlbbL37Qm2xXjk9xIryIhprVP2zkdDHKNXYmeFebibSeQdfQnOEBxKe54Pu+L+NaY7R81S60xyj88vxf+8WQrwj4b0m/RghxJXAhJTyPRl8pmIBako8jE9HCEWiFLmcC/+AgRkYD1Nb6kGJzl2iMS4W0j04ZSoH+sQFrfpjsxIPy5iyYjfVJR7ODpmj5n1lRfFsD+i5qBqv9OxYU4nP4+TFkwOGc6CNFDk1M3MX1YGRIE4h+NO2wmSVPH9igCqfm20NKhtoKezZ28X0zPxuCf/2yrlZsbi5r2eTtaGXTsztH/zJR/bziUf2U+l1IwQMT83gdTt5bH+PcsoMht4XWpF/UjrQUsqH0j3PMZ3xf7cJIbwplLivTzg2E25O815D/DGaxecp0lAd7wU9NBlmVYV5FzkdnQH+82APoUiMnbv3qVSXOE1xAa6zg5OAedrJdF3QklaaVygHOhvWVvs4O2Tcmve5URJXEqUkVeO1MB6Xg5vW1/DCyYGFD15m2lub+aP/OEhoTls1NaaLQ19U//joBR7459f58pNv8alHDy5bKqd2rR4jMDKN1+3giQPK8VoKqbIwEp3nhY5PRrLSCf1TR4Izs6/pvYRBRTYV9sQQhYxSynPAm2g1yx9IfD8eRV4N9AEvZ/B5d0gpRbIH8MX4Yd+Ov6b6YuSImhKtXtjMQmL67mtIiRHNo76siGK3w3RK3Mf7xilyOVS7jSzRROOMOdaXBKaCSGAmJhFAlc+NQPWprmi5AAAgAElEQVT6zobyYhenByYL3iM4kbYWP796vZZ4psY0N0wEZxBoEUTJ8tzfEsXggkoMbsmkysJwpsiYyyZrIxtnW/USVtiZRTvQQgiHEKJOCFErhMiFI/5w/N+vCiE2zvk99cB34k93Syljc977qBDimBDin3Pw+xVLpDYegR40cS/odMI1dkcIQWN1iemUuLsujLNpRSnOZP1cFClprPbRMxIkHIktfPAykypK4vO4OL37PtUeJ0M6OgM8fbgPYNkcqmzwOB0UuRwc/9N3qzHNAV//8fF5dXj5vr+pe2ruSdUt4TduXLPkLgoNKdpipUJpEijsStaOrxDiHiHEXjQxrz7gAjAuhNgrhLh3sYZIKb8P/G9gJXBICPGEEOIHwAlgK9ABfCvhx2qBZkDJZBuAmlI9Am1eITElXJMeI0clU3H8wjibVfp21qytKSEmSVqHWmjUdZob9uztuixFGozl3Bw8P8K2hnLTqf4blUJcN+pazT2Jvb717Iw/ads++zqAyyGyztq476pVWdmiNAkUdiUriWEhxDeAj3FJiVu/83qBu4FfEkJ8W0r5+4sxRkr5e0KIF4CPAO8AnMAxtJZU/3tu9FlhPGr0CLSJU7iVcE16mmpLeO54P7GYxGGCiO7o1AwXxkKq/nkR6AqrZwYnWVdrLNE4dZ3mBiM7N5FojMOBMX7t+vl9bhWLoxDXjbpW80MqsSj99T//8XG+te8ErduyEwfcf26UCq+LEo+LntHp2bY6yVCaBAo7k/G2rhDig2jtoSbQFLk3oTnO3vj/v4gWlf6IEOK3F2uQlPK7UsqdUspyKWWJlPJaKeW3kznPUsqH4nXMd2Tx+frPfHSxNiqSU1bkwuN0MDBp3gh0e2szbufljqG6SVxibbWPcCTGhfH5isdG5PhFTUBMKXBnj666bkQl7lQpjOo6zY5UTowRnJsTFycIzkTZsUbJlOSKQlw37a3NFLkuX2qqazX/bF1VTkzCsb6xBY/t6Aywc/c+1u16kldPD/HO5npeevAuunffx1/82o7ZSHel1610JhSKONlEoD8KRIBfklK+lvDe28AXhRBPAS8Cvwf839yYqDALQghqSj2mjkC3tfh5fH+AfV39CFAN5xNoirev6h6YMrzSekdngC88fgSAXf9xkAffvUWNYxbUxUXjjJiy39biJxKN8envHwS0xZy6TrPHSD2CEzl4fgSAq1arlke5Qr8+PvfYYcanIzRUFPOH91yR1+umrcXPL04N8r3Xzql76jKyraEcgCM9Y7SsrUp5XGLbKoAfHemjozMwG81WY6VQzCcbB3oL8LMkzvMsUsrXhBA/A25ZsmUKU6I50OaNQANEJWxZVc7TH7+t0KYYjrlpvTdvqCmwNalJXBRcGAuplhtZIoSIt7IyngMNl7IKvv2b12Rdt6fQ0K+FLz5xhOGpGerLivjMvcbYaDpwfpSyYtfspp0iN7S1+BECPv69/fzTh25g0zKUt8SkpMrn5s3P3Y1IoRStyC2rq7yUF7s42ps+Ap1M5G16JpZV72iFwo5ko8wxBVzM4Lh+oPAFVIqCUFNSZGoVboCuvnGuUCm/SWmo9OJ2Cs4Y1KnSUcqvuWFtdQlnDRiBBs3BAhWhXCptLX7+4YPXA7D7vxgnJfPg+RGuWl1hCq0Fs9GoZxIt07X9+plhrm2sUs7zMiKEYGtDOUd60jvQRtZBUCiMTDYO9IvA9SLNDBh/77r4sQobYvYU7tGpGfrGpmlWDnRSnA7Bmiqf4VtZqUVBbmis0SLQUqaSkSkcB8+NUF3iYXWVsUsJzIA//jc8P2yM62N6Jsqx3nGuXq3qn/PBurgDvRzz+NBkmFP9k1zbWJ3336W4nG0NFRzrHSMSTa2/a2QdBIXCyGTjQH8BWA38mRDCnfimEMIFfD1+zBdyY57CbNSWFjEwETLkgjsTdMEN5UCnZm2Nj+4BY0YlddSiIDc01vgIzkTpHzdeWcaB8yNcvbpCRbVyQF1pEUUuh2Ec6KO9Y0RikquUA50XKnxuKn1uunPsQM8Vo9q5ex8dnQHeODMMwHVNqetwFflh66pyQpEYpwdSj3N7azNOhxJOVSiyJWUNtBDivyd5+R+BjwMfEEI8CpyOv94EfADwA38NXAXsz6WhCnNQU+IhFIkxGY5SWpRVlzRD0HVBU21WKdzJ6egM8Fr3EJOhKDt3P0t7a34FaBZLe2szf/j9g4Tn7LyrRUH2rI0rcZ8ZmqK+vLjA1lxiMhTh5MUJ3n2lqn3OBUII/FVezg8XfmNME/87DMBDjx9meiZqyDnG7DTWlOR0IzRRdyIwEuTBHxzi5g3VeJwOtvtVqcVys82vCYkd7R1LWet+++Y6HIDH7WR6JqpE3hSKDEnn4fwjydu/CTRH+eNJXgf4nfjjn5dqnMJ81JQWATA4ETKlA32sb5wKr5uVBnIWjML8BdK0YYW52lr8/KzrIj/c36OUX5dA42yq5xTXNxknBfNwYJSYhKvXqEV5rlhd5SNQ4Ah04hzTp8T/8kZTjW82OpwLUulOvHBikCv95RQntM9S5J8NdaV4XA6O9Ixx/47Lr5+OzgB79nbN9uj+1Ls28jt3bCyEmQqFKUnn4fwzqfunKxRJqSn1ADAwEZ5dfJuJrr5xmleWqbTQJKQT5jLi4rbI7aSmxMMbn7u70KaYFn+lF4eAswareT84KyCmUnxzhb/Sy5HAaEFtMNscY2Yaa0p44kAPoUiUIpdz1qHqGQkuasMxlb5EOBrjOgNtvtkJt9NB84oyjsaFxOY6zYLLF/h/+exJVlZ41XWmUGRISgdaSvnBZbRDYRFqSy5FoM2GlJKuvnHef426gSTDbMJcXRfG2bwMLVqsjMfloKHSazjV9f3nR/BXeqmNZ7wols7qKi+Dk2GmwhF8nsJkD5ltjjEzTTU+YlITjjt0fjRp+jVkHvlvqPTORjMT+f4b59m6qlw5ZwWgxOPkpbcHaNr15GVOc2J0TG1UKRTZkY2ImEKxIK+fGQLgw//yxqyIiFk4PxxkIhRRAmIpMJMwl5SS4/FsAsXi6egM0D8e4rH9PYa6ng+eH1Hp2zlGVzMvZBq3meYYs9NUe0mJOxdt/9pbm3GmSNwamgzz4A8OGWb+sAsdnQHeODtMLO4tL5RSqjaqFIrMUQ60Imd0dAb46o+OzT7Xd7HNctPs6lMCYulob23Gm1DHZlRhrsBIkMlwlE0rSgttimnR61FDEU2IzQjXc0dngJsffpZzQ0FeODFgmrnFDKyu0gTjzhdwEa05YUoReDloipdYnR6Yyknk//4dDZQUuebdI3SydcgVS2fP3i5moplXYqqNKoUiczLO00qhyp0SKaUSEbMZe/Z2MT1zeb9BM6UF6QrcKu03OfoY6jVUbqfg4fdvN+TYHo+PZbMay0VjtHrURIGpsemIEpjKIasN0Av6fVc38NmOQ0RjKEXgPFPlc1NW7OLM4GTK9OtsHKqe0WnGpiN88X3beOjxI0mjnSrCubxk8/dWG1UKRXZkU+j0j2QmKqaXWSgH2maYvX7tWN84/kovZcXz2pwr4rS1+Glr8fOZHx7i6UO9hl3YHr8wAZCydYdiYYx2PRvNobcadaVFeJyOgrayOtY3zkQoyp5fuYoPXLemYHbYASEETTUldA9OaW3//uMg4cji2/7pit7XNlblxCFXLJ10delwabHuVxtVCkXWZONAp1LldgCNwDVACdABFFbKU1EQzHzT7OgM8PShXiIxyc7d+9TNZAEaq30MT80wGpyhwmu8DYfjfeOsqig2pG1mwWjXs9EceqvhcOi9oAv393z+RD8At22qK5gNdqKxxsehwChtLX4e2x/gp13a39/pyD676M0zw3jdTq5YWUZ7a/Nl2SKgIpyFINk4KKdZocgNGTvQC6lyCyHq0ZzsjcAtSzNLYUbMetPs6Ayw6wcHicSVNhajQGo39BZlZwen2L7aeGJOSoF76SS/nh0Fu56N5tBbEX+ld1ZEbKltjRbDCycH2LyilJUVxXn9PQqNppoSnj7cx0w0xqmBSd6xuY6bN9Sw++lj3LapNunPpPpevHFmmB1rKnE5HZeV+yzn90dxOWocFIr8kbNeFVLKi0KI3wROAA8Bn87VZyvMgT4pP/T4EUaCM6woL+LBd28x/GRt9trtQtBYowkOdQ9OGs6BjsYkJy5OsHNj8gWgIjMSa94BfveODQW7Jtpbm/mj/zg4K2oG5tigMxOrq7z85K2L8+rNc72pmMwJu+fKlbxyeoj/dlPjkj9fkRlNtSVEY5J9xy5yZnCKB25bz8Z6TXjxwPkR7rxixWXHp/pehCNRjvaO8bvv2DB7rF7uoygsahwUivyQUxVuKeUQ8BrwX3L5uQrz0Nbi56//27UAfO1XrjbFxK1SQ7NHd6DPGqw/MGhtWcKRmIpA54C2Fj8v7rqTzs/djUNAJLbwz+TTlt+8QauLFWjRUqOK2JmV1VVeBiZCfO1Hx5bc1igVuhMWGAkiueSEfeMnxwlHYtyaIvKpyD1N8Xn8//z8FAB3b13Bdn8FDgH7z47MOz6VDsHX9nYRjUmubazKv9EKhUJhAPLRxioMrMrD5ypMwvo6Lb33VP9EgS3JDNV7NHt8Hhf1ZUV0D0wW2pR5HJ9VU1ctrHJFVYmHaxurePatCwW1o8jtwu0UHPuTe3hx153Kec4xeiur3tHppO8HRoKs2/XkknqCp3LC/uZnmhP3GRO1PjQ7R3vHAHj9zDBup+DltwcpKXKxeUUZ+89fkrLp6Aywc/e+lIJUAxNhAK5ZqxxohUJhD3LqQAshVgI7gf5cfq7CXNSVFlFW7OJUv/Gcq2S0tzbjcqjeo9nSWOPjzKDxItBdfRMIwWwqoiI33HnFCo70jNE7WrjMjAPnRtiyqpwiV/Jes4ql4Y+3sqou8aQ8Zm7UeDGObqrMHl2htHd0uuD9xu1AR2eAh596a/b5TFTO/t1b1lZy4NwIUsrLMgZSUeRysKm+lAqfEm1UKBT2IGMHWghxe5rHvUKIPwBeBCqBx/JmscLwCCFYX1fKqQFzRKDbWvzcvL4agUoNzYbGmhLODBlrk6SjM8Bf/+wkUsLdf/5ztQjPIb+0pR6AfccuFuT3x2KSw4FRrjJYzb2V0HtB37mlft6mYiKLTenOJLMnV+niitRomQDJtT+uXl3JaHCG0wOTSTMGEglFYgRGgmq+VSgUtiEbEbHnWLgPtAA6gc8u1iCFNdhQW8JLbw8W2oyMKfO6WV9XwrOfuqPQppiGphof338jxFQ4gs+TMz3CRXNJ4EZbFCo19dyysb6U6hI3X3riKJ/94eFlV3Q9NTDJeCjC1asrl+X32ZH6smLcTkFFsRufx8F0RDITiaW88S9GJyKZGFyuPluROem0P3as1a6x/edGMh6HqXBUzbcKhcI2ZJPC/fM0j58A/wT8N+AmKeV89QmFrVhfV0Lf2DSToUihTcmIgfEwdWVFhTbDVKzVW1kZREgsVW2limTlhsf29zAajBCKO1RLSeNdDAfOabeVq9coBzpfPHGgh5iEv3vhNGPTUT60s4nTu+/Dn0OdiLYWP63bNHVnAThF8ki30qDIL+m0PzbVl1HicXLg3AgrypO3FEs2bmq+VSgUdiFjB1pKeYeU8p0pHq1Syg9JKf9VSjmTT4MV5mB9nVZ/etqAIlPJ6J8IUVemeo9mg67gapQ6aKWmnl/2xJV257KcC+aD50fweZxsqFO17flAz+CYO8b/9FI3HZ0B2lub8bovrztfik7ERCjK+roSTu++jz/71atz+tmKzEg3pk6HYGVFMd999Sx9Y/MF5bxuJ1GZPC9BzbcKhcIO5EOFW6GYVeJ+2yRK3P3jIWpLUwvnKObTWK2N8ZlBY2ySKDX1/FLoDYoD50e50l+Bc4HaXMXiSJ7BEWPP3i7aWvw8/P7tNFRqm4xet2PROhGRaIzXTg9x0/oagNnP9ld6lQbFMpLu797RGeDM4BQz0UtOsn7V6cflMitBoVAozEbWhYtCCAFUx392SEWcFcloqilBCEyhxD0VjjARiqgU7iyp8Lmp9LnpNkgEur21mU8/eoDInAiaimTljoZKb1Il3uVYMIcjMY72jPHBnU15/112ZaENkrYWP20tfh56/AjfffUs77yifsHP7OgMsGdvFz0jwdma+fV1JYyHIrMO9NzPViwvqf7ue/Z2XTaPgiaA46/08uKuO2df0zQnLm26qPlWoVDYhYwi0EKIaiHE54QQrwEh4CLQA0wJIQ4JIf5ECKF6PytmKXY7WV3l5ZQJUrgHxrUelnWlyoHOlsaaEs4axIFua/Fzw7oqhFBq6vkg12m8mdLRGWDnV/cRjsZ49PVzSuk3T2SawfH+a/yEIzGeOtSb9vPmtj+aWzP/d89r/Z5vWledE7sVuSeTbBOVOaBQKOzMghFoIcQvA38PVHApi0fHCWwDtgIfF0L8vpTy/875WQHskFJ25s5khVlYX1vKKROkcPdPaDVeKgKdPU01Pt44M1xoM2ZxCAdXra7ksY/sLLQplkNfGO/Z2zUbif7dO9bndcF8SVldi3INT80opd880d7anFFEcbu/gvoyD1947Aif+cGhlGrsqUT99h65wPq6EupTiFMpCk+m2SYqc0ChUNiVtBFoIcQHgEfRejsfBtqBO4AtaE7zHcAfAkeAEuDvhBAPxH/WDTwCvDc/piuMzvq6Ek71TxKLLdT9rLD06xFo5UBnTWO1j56RIOEFWtIsF92Dk7PiZorc09bi58Vdd3LooXdR7BJ857m3WbfrSXbu3peXyLBSVl8+Mo0oPra/h6HJGcLR9GrsqaKYoUjssvRthfEoVLaJQqFQmIWUEWghRB1a5Bng41LKv0py2DG0NlZfF0J8HPgz4C+FEM8Dfw60Aodya7LCLKyvKyU4E6VvbNrQwiL9EyFAOdCLYWAiRExC82efXva+wImEIzF6RoK8/5rVBfn9duLZty4SiUEklt+e24UWLrMbmUQUk9XH6psac392RUUxfaPzFZwBnj7Uyw1N1Sp6aVDmZpvMrV9X46VQKBQa6VK4PwaUArtSOM+XIaX8SyFEMfAw8DrgA04A/5ALQxXmY0NciftU/6SxHejxEEJAtU+pcGdDR2eA77+pRZ3mRqKgMOm154eniElUBHoZyNSJWiqFFC5TJCfTTY3N9aUpHWiVim98VHq2QqFQpCZdCve7gUG0qHKm/BkwhOY8HwFul1IqxRebovdrPTVg7Dro/vEQNSUeXE7V1S0b9uztmpe6Xcj0Wr0fdWNNSUF+v51Yrshwe2szroS2VSqVtLAsJDbW0Rngxq/8hJ+fGMDtFFT53EmPV6n4CoVCoTAr6TyG9cDLUspommMuQ0oZAV5CC0i9Q0p5YYn2KUzMSycHEMDnHzuStxrJXKD1gFbp29litPTa7ng/6kYVgc47y9Vzu63Fz6rKYtxOoZR+DUKy+thil4P21uZZ0bcLY1pZzExUMj2TWh9BpeIrFAqFwoykS+EuAcYX8ZnjQERKObQ4kxRWoKMzwGd+eBg9ybPQ6b3p6J8IqfrnRWC09Nozg1OUFrmoKVGp+PkmmWKz7kTlkr7Rac4NBWlvbeYj79yY089WLI7E+lgJxCR88pH9OAREEzQjgzNRnEIQlfPFJFUqvkKhUCjMSLoI9ADQtIjPbAT6F2WNwjKYST13YFw50IvBaEqt3YOTNNb40LrnKfJJomIzwM6NtTnfHPvxW1oS07u2rsjp5yqWhq7G/he/tgOnQ8wqcic6zzpRKQ01VygUCoVCsRTSOdBvADcIIdZm+mHi/2/vzsPrvOoDj39/kmVbtrzEsZ3EyubYwZDEEENWMpAFOgaatiYQ2gYeoO0MBUJLN0NcCsOUxQZDoS1bmUKBAWZKwKilGeJAtkIaSNIIcOzEWe0ksuN4ieNNtmTpzB/vex1ZuZKvpLtJ+n6e5z6v77seXZ3nWL97zvmdiNOAC/NrNY7V2/DegaSU7IEepkIQdcL07LOb0TyhpsNrN+88wOnOf66aQhD12Kpf59xTZnDLA0+XfUmrm9Y/xfzZU1k4t6Us91N5rV67kZ4SliksDL0/1hJZkiSNBoMN4S6s4fzViHhdSqlrsBtFxESyjNsN+bUax+pteO9A9hw8TNfhXuY4B3pYCplar/j0bZw6a0rN/iA+3NPLE7sO8NpzTqzJ88eztvYO7t+6t+zTNZ7t7ObOR3byB/9lvqMK6lQpX4gWeprN6ixJGisG64H+P8C9wOXA7RHx0oFOjIiXka0HfRnwi/xajWP1Nrx3INv3ugZ0Obxi4Wx+/uguDh0uOedgWW199iCHe5M90DWweu1GDpU5G3tbeweXrb6Vw72J7937ZN0mIBzvBvpCtDFM+iZJGrsG7IFOKaWIWAb8hGxY9t0RsR64Cyhk1z4BuAh4ERDA48BvpVQkW4jGlcIfTB+9YQM79nUxu2Uif/XrZ9XdH1JHAmh7oEfkkoWz+fqdm2l/fDcXnXF81Z9vBu7aKfd0jUIm50IOhR37uuo2AeF4VyyZXHNTo0GzJGlMG3Th25TSk8BLyYZkJ+Ac4PeB6/LX7wFn5ce+A7wsv0Zi2ZJW/u87Lgbgg1fWX/AMWQZusAd6pC5acDyNDcFPH9pRk+dvyteAPn22PdDVVu4lrUZTAsLxrn8yOXucJUnjwWBzoAFIKT0D/G5EfAC4EngZMCc/vIMsYdi/pZQeqVgpNWoVAtNCT2+92eEQ7rKYPrmJl5w8g58+vIO/qMEw/c079jO5qYG5/h6rrngv5PCXtBotCQiVcW6zJGm8OWYAXZBSehT4uwqWRWPQ9MkTmDShoW4D6O37DtHUGMxobqp1UUa9OS2TWLthG/Ovu4F5M5uPJA6qhk07D3DarKkmm6qBvusCFxIHvvdVZw77d3/c1Ins2v/8nJX1loBQkiSNTyUH0NJwRARzpk3i6XoNoPceYk7LJAOvEWpr7+DWB7Pl3xPly8Rcqs079zPf4ds1U+iF3LbnIBd+/OYB1wMeSFt7B6vXbmTL7k4SWUKNvreoxwSEkiRpfBp0DrRUDnOmTarfHui9h5jtsN8RW712I11lzsRcqt7exOZdB5z/XAdOmD6Zc0+ZyU3rnyr5mkLSsI48eAZoCDhuSpPzaiVJUt2xB1oVN6dlEpvzJE/1ZvveQ5w0Y3KtizHq1Wrealt7Byt/eD9dh3v5zt1PcNZJ0w20auy/nn0Cn7xxI1uf7eSkGccedl0saVhPgikTJ9D+of9aqWJKkiQNiwG0Km7OtEncs/mZWhejqB37DvHik2fUuhij3ryZzUfmv/bfXyn9lzva3dntckd1oDGfDnHxyltondnM5S+cw60PbGfL7s6ic+NNGiZJkkYTh3Cr4uZMm8Su/V109/Qe++Qq6ulN7NzfZQbuMli+dBHNTY1H7av0vFWXO6o/be0dfPbHDx1537G7k2/+7PEjw7MLc+Pb2jtoa+/gklW3MNB0aZOGSZKkemQPtCquEKDu3NfFiXU0XPqZA1309CYD6DLon4l50oSGis9bteey/hT7UqO/zu4ePvyv6zl0uHfAc00aJkmS6pU90Kq4OS1ZgPr03oM1LsnRConNCuXTyCxb0sod113B219+OhHwmnNOrOjzBuqhtOeydkr98mJ3Z/eAwbNJwyRJUj0zgFbFzZ2e9TrXUybutvYO3vKPPwfgg/9yH23tHTUu0dhx6aI5HOzu5a7HdlX0OcuXLqKp8ejlx+y5rK2RfnkRwB3XXWHwLEmS6pYBtCquMES6XgLoQvKpnfu7ANixr+vIvEyN3EXzj2fihAZu27i9os9ZtqSVF500jYbA5Y7qRLG58EPh6AFJklTvnAOtipvdMhGonwB6sORTBl8j1zyxkQvnz+L2B58GzqrYcw529/DQtv1cc+GpfHTZ4oo9R6XrOxe+kHW7kIW7WJb2vhw9IEmSRgMDaFXcpAmNzGhuYvu++gigTT5VeZctmstH/m0DT+w6wCmzplTkGf/+4HY6u3t4zdknVeT+Gp5lS1qLfhF1yapbBgyiW4ssbyVJklSPHMKtqpgzbVLd9ECbfKryDudLlr3ik7dyyapbKjI8/sb1TzGjuYkLz5hV9nur/AZa6uyzv32u854lSdKoYQCtqpjTUj8B9PKli5jcdHTVd/ho+WRrAT945H3ftX/Ldf+Xr7qZNfd20HW4lxt+tbUs91VlLVvSysqrFtM6s9k565IkadRyCLeqYs60Sfziid21LgaQ/SH/xDMH+PRNWZDn8NHyyuaY9x61r1xzzAsJ4Apz2Du7e1ixZh2Av79RYKDh3ZIkSaOFAbSqojCEO6VERBz7ggo7YVq2tNatf3EZ82dPrXFpxpZKzjE3AZwkSZJqySHcqoq50ybR2d3D/q6eY59cBeu3PMvUiY2cVqEEV+NZJeeYmwBOkiRJtWQAraqot7WgN2zdw4tOmk5DQ+17w8eagZJFlWOOuQngJEmSVEsG0KqKegqge3sTG7bs4ex502tdlDGpb7IogIaAj7/+nLIMsV6+dBGTJpgATpIkSbVhAK2qqKcAevOuA+zv6uEsA+iKWbaklTuuu4KVVy2mN8G5px5Xtvu+6byTAczkLEmSpKoziZiqYk5LIYA+WOOSwIYtewA4e96MGpdk7Dv/9CxwvnvTrrIla5syaQITGxtY/9dLaWr0O0BJkiRVj399qiqOmzKRxobg6TrogV6/5VkmNARnntBS66KMeQvmtHDclCbu2bSrbPe8f+teFs5tMXiWJElS1fkXqKqioSGY3TKxLoZwb9i6h4VzW5g0ofHYJ2tEIoKXnTaLezY9U7Z7btiyx+H3kiRJqgkDaFXNnGmT2L6v9gH0+i17HL5dReeffhyP7tjPjjL87p/ee5Ad+w7xopMMoCVJklR9BtCqmrnTJte8B/rpvQfZvveQPZhVdN7pswDK0gt9/9a9AJxlAC1JkqQaMIBWVbS1d/CzR6gM44MAACAASURBVHeyfsseLll1C23tHTUpw2s/+xMAvnjbwzUpw3h0Tut0Jk1oKMs86Pu3ZgngDKAlSZJUC2bhVsW1tXewYs06Ort7AOjY3cmKNesAqrb8UP8y7NjXVfUyjFeTJjTSOrOZr9+5ia/89DHmzWxm+dJFw/rcN2zZw7wZk5kxpan8BZUkSZKOwR5oVdzqtRuPBK4Fnd09rF67cVyVYbxqa+/g8V0H6O5JJJ77AmU4IwDu32oCMUmSJNWOAbQqbsvuziHtH6tlGK9Wr93I4d501L7hfHlxsLuHR3fsN4GYJEmSasYAWhU3b2bzkPaP1TKMV+X68uLBbXvp6U0G0JIkSaqZugugI+KaiPhJRDwbEfsi4p6IuDYiSi5rRDRExMsj4qP5vZ6MiK6I2BYR/y8illXyZ9DRli9dRHPT0WsuNzc1snzpoqqWYfKEo6tQtcswXg325UVbeweXrLqF+dfdMGhyubb2Dt76lbsA+J8/WG8COEmSJNVEXQXQEfF54FvAecBPgB8BLwA+B3w3IhoHubyvM4A7gA8AZwHrgTXAZuC1wPcj4p8iIsr7E6iYZUtaWXnVYlrzQGpyUwMrr1pc1eRdy5a08vuvmH/kfevM5qqXYbwa6AuUy184hxVr1tGxu3PQudGFBHC7O7sB2Lbn0LDnUEuSJEkjUTcBdES8AXg38BTw4pTSlSml1wNnAvcDrwfeU+LtEnALWbA8N6W0NKX0OymlC4DLgP3A2/OXqmDZklbuuO4Kfu2sEzj5uCk1CVxPOW4KAD99/+Xccd0VBs9VUvgCZdrkLOn/STMms/Kqxdz6wPaSEruZAE6SJEn1om4CaGBFvn1/Sumhws6U0jbgXfnb60oZyp1SeiSl9KqU0o0ppZ5+x24HVuVv31KGcmsIFs5tYfPO/XT39Fb92Zt27GdiYwMnzXDec7UtW9LKZ950LgCfu2YJy5a0ljw32gRwkiRJqhd1EUBHxMnAy4Au4Pr+x/OgtwM4EbioDI9sz7cnl+FeGoIFc1ro7kk8setA1Z+9aed+Tj1+Co0NjtyvhXNaZwBwX8ceoPTEbiaAkyRJUr2oiwAaWJJv16eUBupWurvfuSNxZr7dWoZ7aQgWzJkKwMNP76v6szftOMDpx0+p+nOVOWH6JGa3TOS+jmeBbG70hH5fZkxuanheYrd3XbbgefcyAZwkSZJqoV4C6EJ2p82DnPN4v3OHJSKmAH+cv/3eSO6loVswtwWAR7bvr+pze3sTm3bu5/Tjp1b1uXpORHD2vBnctyXrgV62pJWFc1uOCqLffMGpz5ubXhiqPXfaJAITwEmSJKl2JtS6ALmWfDtYVFXospw2wmd9gSwI3wB8eYT30hBNn9zE3GmTeGR7dXugt+09yKHDvZw22wC6ls5pnc4/3P4oB7t7aGwIHt91gGsuPJUPXXkWF628hSeeeW4ASlt7B5+48QG2PnuQ5qZG/vJ1LzJoliRJUk3VSwBd6IJKFX1IxAeBtwHPAm9KKR0a5Nx3AO8AOPXUUytZrHFn4dyWqg/hfmxH9t3MfHuga+qceTM43Jt4cNteunt6OdDVw8VnHM+ExgYWt07jpg3bmH/dDcxobmJ/12G6e7ImobO7hxVr1gEYREuSJKlm6mUI99582zLIOYVjewc5Z0AR8WfAX5P1ZL82pbR+sPNTSl9OKZ2XUjpvzpw5w3mkBrBgTguPbN9HShX9vuQom3dmSctOcw50TZ09L0sktn7LHu58ZCcAF55xPG3tHfzHI7uA7Fu03Z3dR4LnApeukiRJUq3VSw/0pnx72iDnnNLv3JJFxB8BnwY6gStTSncO9R4qn4VzW9h78DDb9x1i7rTJVXlmYQkrMzfX1imzmpk2eQL3dTzLpp37eeGJ05g1dSKr127k0OFjL23m0lWSJEmqpXrpgS4sK3V2RAwU4Zzf79ySRMS1wN8BB4HfzJfEUg0tmJMNJqjmMG6XsKoPEcE582Zw7+O7uWfTM1y84Hig9MDYL0AkSZJUS3URQKeUngDuBSYCV/c/HhGXkq3Z/BRQcu9xRLwT+BxwCFiWUvpxWQqsEVkwN5uHXM1M3C5hVT8mNwX3b93DocO9/MsvttDW3lFSYOzSVZIkSaq1ugigcyvz7SciYmFhZ0TMJcucDbAqpdTb59h7IuKBiPhG/5tFxH/PrzsEXJVSWlu5omsoTpw+makTG3mkSj3QLmFVP9raO/jpwzuPvN+1v4sVa9Zx+Qvn0NzUeNS5TQ3BcVOaXLpKkiRJdaNe5kCTUvpuRHwReBewLiJ+DHQDrwKmA21kvcl9zQYWkfVMHxER5wL/QJbd+zHgTRHxpiKP3ZFS+ouy/iA6pohgwdyWqi1l5RJW9WP12o1Fk4Pd+sB2Vl61mNVrN7JldyfzZjazfOkiA2ZJkiTVlboJoAFSSu+OiJ8C1wKXAo3AA8BXgS/27X0+hpk8tzTWC/NXMZsBA+gaWDinhZ89uvPYJ5aBS1jVj4HmOm/Z3cmyJa0GzJIkSaprdRVAA6SUvg18u8RzPwx8uMj+23gugFYdOnS4hy3PHmT+dTdUvLfRJazqx7yZzXQUCaJNDiZJkqTRoJ7mQGucaGvv4EcbtgHZmr8duztZsWYdbe0dFXmeS1jVj+VLFz1vrrPJwSRJkjRaGECr6lav3UhXkXmwq9duLPuz2to7+Pqdm+jq6eWVn7y1YkG6SrNsSSsrr1pM68xmk4NJkiRp1Km7Idwa+wabB1tObe0drFizjoPd2dT5Qk83YMBWQ851liRJ0mhlD7SqbqCh1OUeYr167UY6u3uO2lepnm5JkiRJY58BtKquWvNgq9XTLUmSJGl8MIBW1RXmwR43pQmAudMmVWQebLV6uiVJkiSNDwbQqollS1q5/p0XA/C+17ywInNily9dxISGo1czM+OzJEmSpOEygFbNnDG7hakTG/nVk7srcv9lS1p5cesMGiPM+CxJkiRpxMzCrZppaAjOaZ3Br558tmLPONDdwytfMJt/+r0LKvYMSZIkSeODPdCqqZecMpMNW/fQdbi37Pfu7unlke37WHTi9LLfW5IkSdL4YwCtmlrcOoOuw708uG1v2e+9acd+unsSi05sKfu9JUmSJI0/BtCqqZecPBOgIsO4N+ZB+QtOmFb2e0uSJEkafwygVVOnzGpm5pSmiiQSe/CpvTQELJhjD7QkSZKkkTOAVk1FBIsrlEhs47a9nD57KpObGst+b0mSJEnjjwG0au7FJ89g47a9HOzuKet9H9y2j0UO35YkSZJUJgbQqrnOrh56ehMv+uCNXLLqFtraO0Z8z4PdPWzaud/5z5IkSZLKxgBaNdXW3sG3f/44AAno2N3JijXrRhxEP/z0PlKCRScaQEuSJEkqDwNo1dTqtRs52G8N6M7uHlav3Tii+258ygzckiRJksrLAFo1tWV355D2l+rBbXuZOKGB04+fMqL7SJIkSVKBAbRqat7M5iHtL9XGbXtZOKeFCY1WcUmSJEnlYXShmlq+dBHN/ZaZam5qZPnSRcO6X1t7B5esuoXbNm7nsR37y5KQTJIkSZIAJtS6ABrfli1pBeCjN2xgx74ujp86kQ9eedaR/UPR1t7BijXr6MyXw+rs7mHFmnVHPUeSJEmShsseaNXcsiWt3PSnlwLwrssWDDvYXb1245HguaAcCckkSZIkCQygVSdmTZ3IrKkTefjpfcO+R6USkkmSJEkSGECrjiyc28JDIwigK5WQTJIkSZLAAFp1ZOHcFh5+eh8ppWFdX+6EZJIkSZLUlwG06sbCOS0829nNjn1dw7p+2ZJWPrbs7CPvW2c2s/KqxSYQkyRJklQWZuFW3Vg4twWAh5/ex5xpk4Z1j8UnzwTgb970Eq566cllK5skSZIk2QOtunHmCYUAeu+w77Fh6x4Azpo3vSxlkiRJkqQCA2jVjROnT6Zl0oQRZeLesGUPExsbWDCnpYwlkyRJkiQDaNWRiGDBnKk8vH0EAfTWPbzgxBaaGq3akiRJksrLKEN1ZeHcacPugU4psWHLHs46yeHbkiRJksrPAFp1ZeHcFrbtOcSeg91DvvbpvYfYub/LAFqSJElSRRhAq670zcQ9VBu2FBKIzShrmSRJkiQJDKBVZ0YUQOcZuF940rSylkmSJEmSwABadaZ98y4A3vfdX3HJqltoa+8o+doNW/Zw6qwpTJ/cVKniSZIkSRrHDKBVN9raO/hA2/oj7zt2d7JizbqSg+gNW00gJkmSJKlyDKBVN1av3Uhnd89R+zq7e1i9duOg17W1d3Dxypt5bMd+7nhkx5B6rSVJkiSpVBNqXQCpYMvuziHthyx4XrFm3ZHAe+/Bw6xYsw6AZUtay19ISZIkSeOWPdCqG/NmNg9pPwy/11qSJEmShsoAWnVj+dJFNDc1HrWvuamR5UsXDXjNcHqtJUmSJGk4DKBVN5YtaWXlVYtp7dPj/L7XLBp0KPZweq0lSZIkaTicA626smxJK8uWtPLYjv1c/qnb6E3Fz2tr72D12o10FOlpPlavtSRJkiQNhz3QqkvzZ0/lhSdO48b7tj7vWCFxWN/gOfJt68xmVl612ARikiRJksrOAFp167XnnMQ9m5/h6T0Hj9pfLHFYIgue77juCoNnSZIkSRVhAK26NWlCkBJc8PGbuWTVLUfWdzZxmCRJkqRacA606lJbewd/e/PDR9537O48sr7z3OmT2Lbn0POuMXGYJEmSpEoygFZdGmh95z//zi/oKZJYzMRhkiRJkirNAFp1aaDh2H2D5+C5uc/Llw6+3JUkSZIkjZQBtOrSvJnNRZeo6qtv4jBJkiRJqjSTiKkuLV+6iOamxmOeZ+IwSZIkSdViD7TqUmE49uq1G9myu5OGCHrS8yc/mzhMkiRJUrUYQKtuLVvSeiSQbmvvYMWadUclFjNxmCRJkqRqMoDWqNC/R3qeicMkSZIkVZkBtEaNvj3SkiRJklRtJhGTJEmSJKkEBtCSJEmSJJXAAFqSJEmSpBIYQEuSJEmSVAIDaEmSJEmSSmAALUmSJElSCQygJUmSJEkqgQG0JEmSJEklMICWJEmSJKkEBtCSJEmSJJXAAFqSJEmSpBIYQEuSJEmSVAIDaEmSJEmSSmAALUmSJElSCQygJUmSJEkqQd0F0BFxTUT8JCKejYh9EXFPRFwbEcMqa0S8JiJuiohdEXEgIu6LiA9ExKRyl12SJEmSNHbVVQAdEZ8HvgWcB/wE+BHwAuBzwHcjonGI93sf8EPgCuBe4AZgLvBR4LaImFK+0kuSJEmSxrK6CaAj4g3Au4GngBenlK5MKb0eOBO4H3g98J4h3O88YBVwALgkpfTqlNLVwBnAvwMXAR8r708hSZIkSRqr6iaABlbk2/enlB4q7EwpbQPelb+9bghDua8DAvhESunnfe63D/g9oBd4d0TMHHHJJUmSJEljXl0E0BFxMvAyoAu4vv/xlNLtQAdwIlnP8bHuNxF4bf72W0Xu9yhwJzAReN2wCy5JkiRJGjfqIoAGluTb9SmlzgHOubvfuYNZBEwBdqWUHinD/SRJkiRJ41y9BNDz8+3mQc55vN+5pdzv8UHOGcr9JEmSJEnjXL0E0C35dv8g5+zLt9NqcD9JkiRJ0jg3odYFyEW+TfVyv4h4B/CO/O2+iNg44lJV1mxgR60LIWFdVP2wLqpeWBdVL6yLqhf1WBdPK+Wkegmg9+bblkHOKRzbO8g5ZbtfSunLwJdLeFZdiIh7Ukrn1bocknVR9cK6qHphXVS9sC6qXozmulgvQ7g35dvBov5T+p1byv1OLdP9JEmSJEnjXL0E0O359uyIaB7gnPP7nTuYB4BOYFZELBjgnAuGcD9JkiRJ0jhXFwF0SukJ4F6ydZmv7n88Ii4FTgaeIlu/+Vj36wJ+mL99c5H7nQFcTLbu9A3DLnh9GTXDzTXmWRdVL6yLqhfWRdUL66Lqxaiti5FSufJ2jUxEvBG4nixIfkVK6eF8/1zgVuAs4E9SSn/b55r3AO8B7kopvbXf/c4Hfk7WE315SumufH8L8G/ApcBnU0p/WumfTZIkSZI0+tVFDzRASum7wBeBE4F1EfGDiFgDPEQWPLcBn+t32WxgEUXmOqeU7gauA6YA/xERN0XEd4BHyILnnwMfqNCPI0mSJEkaY+omgAZIKb2bbMj1vWRB7lLgYbJe5jeklHqGeL9PAq8l68E+H/gNsnTpfwVcmlI6UL7SV19EXBMRP4mIZyNiX0TcExHXRkRd/V41+kXE1yIiDfJ6YIDrGvI6eU9eR5/N6+zvVvtn0OgQEYsi4r0R8c2IeCAievM69sYSrh1WmxgRr8m/ZN0VEQci4r6I+EBETCrfT6bRZjh1cbhtZX6t7aWeJyKaIuJVEfHpiPhZRGyNiK6I6IiI70bEZce43nZRZTPc+jjW2sa6GcKtoYmIzwPvBg4CNwPdwKuAacD3gauH+oWDNJCI+BrwNuAOsi+1+tuaUlrR75pGYA3wm8Aesno6iayeTgL+PqX0xxUstkahiPgs8N4ih67ORyoNdN2w2sSIeB/wCaAHuA14huwL3DnAz4BXjfYvWzU8w6mLw2kr8+tsL1VURLwa+FH+9ingP4H9ZKMzz8n3fySl9KEi19ouqqyGWx/HXNuYUvI1yl7AG4AEbAXO7LP/BGBDfuy9tS6nr7HzAr6W16u3D+GaP8+vWQ+c0Gf/mWSNbgJ+q9Y/m6/6egH/Dfgk8CZgAdkfbwl44yDXDKtNBM4Desn+87+wz/4W4Pb8us/U+jPxVZvXMOvikNvK/DrbS18D1Y0rgO+S5Qfqf+y3gcN5/bi83zHbRV9lf42gPo6ptrHmvwhfw/ilwT15hXlrkWOX9mkwG2pdVl9j4zXUhg9oBLbl17yyyPG35cfuqvXP5qu+XyUGLcNqE/M/AhLwoSLXnUHW+3IImFnrz8FX7V+VCqBtL32N5AX8Y14/vtJvv+2ir6q/BqmPY6ptdK7sKBMRJwMvI1uC6/r+x1NKtwMdZMnYLqpu6aQjLgbmAk+mlP69yPHryYaSnR8RrVUtmcaU4baJETGRLEcGwLeKXPco2bKJE4HXlb3g0nNsLzUS7fn25MIO20XV0PPq4wjUbdtoAD36LMm361NKnQOcc3e/c6VyuTwi/iYivhwRH4mIpQMkIinUvbuLHCNlc6fW52/PrURBNW4Mt01cRLZKw66U0iNDuE4qRaltJdheamTOzLdb++yzXVStFKuPfY2JtnFCNR+mspifbzcPcs7j/c6VyuWtRfZtiIjfSSmt67Ov1Hp6LtZTjcxw28T5/Y6Vep1UilLbSrC91DBFxInA2/O33+tzyHZRVTdIfexrTLSN9kCPPi35dv8g5+zLt9MqXBaNH78A/hg4m6wOzgOuBH5Jlnnxx/2Gz1hPVS3DrWvWUVXCUNtKsC5qGCJiAvBNYAZwc0rpB30O2y6qqo5RH2GMtY32QI8+kW9df0xVk1L6bL9d+4EbIuJHZFk5LwJWkK3ZDtZTVc9w65p1VGU3jLYSrIsani+RLeXzBPCWfsdsF1Vtg9XHMdc22gM9+uzNty2DnFM4tneQc6QRSyl1ASvzt30TilhPVS3DrWvWUVXNIG0lWBc1RBHxt8AfkC3j86qU0lP9TrFdVNWUUB8HNFrbRgPo0WdTvj1tkHNO6XeuVEkP5Nu+Q2825VvrqSptU74dal0r/PvUIV4nDVexthJsLzUEEfFpsqGw28mClYeKnLYp39ouqqJKrI/HMuraRgPo0aeQHv7siGge4Jzz+50rVdLx+XZfn3335tvzKSIipgDn5G+tpxqJ4baJDwCdwKyIWDDAdRcUuU4armJtJdheqkQR8Ungz4CdwK+llDYMcKrtoipuCPXxWEZd22gAPcqklJ4gq1ATgav7H4+IS8nWXnuKbK0+qdLelG/7LjNwJ/A0cHJEvLLINVcDTcDdKaWOCpdPY9hw28R82NgP87dvLnLdGWRrUHYBN5S94BqPirWVYHupEkTEKmA58AxZsPLLgc61XVSlDaU+lmDUtY0G0KNTYa7AJyJiYWFnRMwFvpC/XZVS6q16yTTmRMS5EXFlRDT22z8hIv6MbOgOwGcKx1JKPcDq/O0X87pZuO5MYFX+9mOVK7nGkeG2iavIkpO8PyIu6HNdC/BVsv8jv5BS2l2xkmvMGE5bCbaXOraI+AjwfmA3WbBSSm+b7aIqYqj1cSy2jZFS3SU2Uwki4gvAu4CDwI+BbrLsd9OBNuCNecWTRiQilgHfB3YBDwJPki0XsJhsGYJeYEVK6ZP9rmvMr/sNYA9wM9k3ha8GJgN/n1L6Y6Q+IuKlPPfHHWTLW0wDHiKrgwCklC7qd92w2sSIeB/wCaAHuIXsD4JLgbnAz4ErUkoHyvTjaRQZal0cbluZX2t7qaIi4jeBf8nf3gOsH+DUB1JKq/rusF1UuQ2nPo7FttEAehSLiGuAa8kqYCPZ3JWvAl+091nlEhHzgfeSzXs6jWyuSiJrAH8CfD6l9J8DXNsAvBv4PeCFZP8Z/4rs2+tvV770Gm0i4jLg1mOdl1KK/vuG2yZGxGuAPwfOI/sP+VHg28CnUkqHhv5TaCwYal0cSVuZX297qeeJiLcD/1TCqbenlC4rcr3tospmOPVxLLaNBtCSJEmSJJXAOdCSJEmSJJXAAFqSJEmSpBIYQEuSJEmSVAIDaEmSJEmSSmAALUmSJElSCQygJUmSJEkqgQG0JEmSJEklMICWJEmSJKkEBtCSJEmSJJXAAFqSNKZExKaISH1evRGxJyKeiIgfR8TKiHhxBZ97ernvXQ2jvfwFEXFR/jtfVYNnT4mIrRFxd0REtZ8vSao8A2hJ0li1Fvg68A3gRuBh4DzgOuCXEfGvEXFiDctXVWMlQB5MHrT+HbAH+ES1n59SOgB8jKyevbXaz5ckVV6klGpdBkmSyiYiNgGnAZenlG7rd6wB+A3gb4AzgAeBl6eUdpbxufNTSptGer9yO1b5ImIB0AQ8klLqrm7pyiMirgG+BXwkpfShGpVhIrAZ6CX7rLtqUQ5JUmXYAy1JGjdSSr0ppX8h6yF8GHgB8Onalqo+pJQeSSk9MFqD59yfAAn4aq0KkAfM3wTmAVfXqhySpMowgJYkjTsppWfIgi2At/Qfyh0RUyPifflc1j0R0RkR6yPiwxHRMpRnRcSFEbE6Iu6JiG0R0RURWyLiuxFxUZHzT4+InojYFRHNA9yzKZ9rmyLirGM8/+0Rkch6nwEe6zdH/PT8vKJDvAvn9bnXPRGxPyKeioivRMSc/NjkiPifEfFgRByMiMcj4mMR0TRI2cr5OZ8PnA/cPtAIgIg4K/951g9wfEY+f/rpfvsXRcTXI2Jz/vvbm39e34+INxS51dfz7buH8jNIkuqfAbQkabz6f8AuoBG4vLAzIk4G7iKbQ3sacCdwE3Ac8D+AOyLiuCE852PAn5INj74L+FdgJ/AG4KcRcVQvZR78/SB/3u8OcM83ACcCt6WUNhzj+Q+TBXT78/ffy98XXvtK+SEi4hPAP5B9ZjeS9fT+PvDjPNi9GfgjYD1wC3A88JfA5we4X7k/52X59seDnHNevv3PAY6/FAjg3j7lXAzcTTan+QDZ72YtsBVYCvz3/jdJKd0HbAMuLnzBIEkaGybUugCSJNVCSilFRDvwKuBsOJKE6jvAWcDngPfniaHIe4O/DLwF+Azw9hIf9SngzSmlbX13RsRvkAWzX4qIGwrPyf098FtkPZjFhiMXejaLBqd9pZR+ShaoXwZMBf5imHO03wacm1K6Py//cWRB74vz7W6yOb/P5sfPJQs8/1tEfCyltLlwowp9zpfl2zsHOacQQN8zwPGX5dt7++z7U2Aa8JcppZV9T86/OFg8wL3uJAvqLyf7WSVJY4A90JKk8Wx7vj0+374GuBj4GfDevkFtSqkTeCfwNPDmUntHU0o39g+e8/0/AK4HZtGnBzw/djOwAXhZRFzQ91hEnAO8AtgCtJVShjL5UCF4zsv4DPCl/O1ZwDsKwXN+/BdkvfwBXNrvXmX/nIFz8+39g5xzrB7oYgH0Cfn2h/1PTintSykNFLAXRgYsGaQ8kqRRxgBakjSeFf4f7M23r8u330sp9fY/OaW0n6z3cgLZfNuSRMTsfP7wpyLiHyPiaxHxNeCc/JQXFLnsc/m2/zzaa/Ptl1NKh0stQxncWGTfw/l2c9/guo+H8u28fvvL+jlHxFRgSv62aEb1iGgEXgL0AO0D3KoQQPcNsO/Kt1+KiF+LiEnHKk9uV749YdCzJEmjikO4JUnj2ex8Wwh2zsi3qyNi9TGuLWlua0T8IdmyWVMGOW16kX3fAFYCvx0Rf5ZS2hUR08iGNh8mG+ZcTU8W2bdvkGN9j0/ut7/cn/OMfHtokGWjziL7HdzXb7g8ABExHVgIPJNSeqzPodVkPf6vIpujfSgifgHcDnwzpbRugOftybczSyi/JGmUMICWJI1L+TzcwvDaQhDUmG9vBzYd4xabj3GciDgP+CJZwLucLAHVk8CBfA72x4EVZMOcj5JS2h8RXyWbg/v7ZHOp3wa0ANenlLYe6/nlVKynuI/BjhVT1s+ZbP41wKSImJRSOlTknFITiB3VO50H26+OiAvJhp5fQjb8/ELgfRHxP1JKf13kfoUvRZ4pofySpFHCAFqSNF79OlnG58PAbfm+J/Lt9SmlYyboKsEbyYKyv0spfarI8YXHuP7zwHuBd0bE3wDv6rN/NCvr55xSOhAR+8mSpM0iy5DdXyGA/sUAtykMK7+32MGU0s+BnwNExETgGuB/AR+OiH9OKW3sd0lhXv3TSJLGDOdAS5LGnTwx1Wfyt19PKRWCnEKiqKuff9WwzMq3T/Q/kC9v9GuDXZxSeiQv0wLg42TDkNenlG4fRlkKQ5vr4cvzcn/O8FzgO9C62IX5zZ39D0TEDLKAGAbuoT4ipdSVUvoaWRK0IMtE3l+hHEUDcknSAdMfwQAAAy9JREFU6GQALUkaNyKiISJ+k2x5pYXAA2RDqwvayAKoSyPiSxExq8g9zoiIa/vvH8AD+fat+ZJHhXtMI1ueqpT5sX+fb9+fb79Q4rP768i3Lxrm9eVU7s8Z4NZ8e3GRe00gSyAG8Lt9E4FFxEnAPwOt+a6N/a59d0QsKlY+8uXPKD7M/CKytbJvK/1HkCTVu3r4FlqSpEq4LiLenv97MlkyqpfyXNDaBvxhvhwTkM3zjYhlZMsv/SFwTUT8kmze8mzgVLKM2dsobRj1PwF/kj/30Yj4KVmP5SvJeoS/Sja/eTA3kQV1i4C9wP8u4bnFfJ9sreRvRcRNPDdv+P0ppaKZqyulAp8zZL/PDwGvBj7a79g5ZHXgSeACYHNE3Es2hP8lwHqgG2gC/jEi/jal9I382ncAn4+IR4H7yBKjnQj8F2Ai8H9TSnf1fVhELCbLvv0fKaXtSJLGDHugJUlj1VKypFtvJZvv/AKyXs+VwOKU0uv7DN0+IqVUCLLeQ5ZQ6mzgDWRB2F6yZF5XlVKAPDg/jyxj9r68HOcBa8iC6ucN7S5yjwT8OH/7jZTS3lKeXcTngA+S9URfCfxB/po2zPuNSDk/5/x+7WRDql8ZEaf3O1yY/3wz8HqyOdJXkAXqXyELur9ANry7gWyEQsFfAf9AllX75WTz2s8kS4D2JuDNRYrztnw73NECkqQ6Fdn/y5IkqR7lCaseJ+vRPDultKHGRapbEfE7wP8BPpJS+lCf/V8E3gm8p0zJ4QYrw0SyId29wPxBltWSJI1C9kBLklTfriULnm80eD6mfwbuAv4oTxRXUOiBvqcKZXgH2RDvvzR4lqSxxx5oSZLqTJ60ajkwj2woeg9wfkrplzUt2CiQr9d8J/DJlNJ1EdFENiS8AZieUjpYwWdPAR4hn2ud/CNLksYck4hJklR/TiKbn3wI+CXwVwbPpcnXa+47wm4xMAlor2TwnD/7ANnvTpI0RtkDLUmSJElSCZwDLUmSJElSCQygJUmSJEkqgQG0JEmSJEklMICWJEmSJKkEBtCSJEmSJJXAAFqSJEmSpBIYQEuSJEmSVAIDaEmSJEmSSvD/AQVqDga+N1dFAAAAAElFTkSuQmCC\n", - "text/plain": [ - "" - ] - }, - "metadata": {}, - "output_type": "display_data" - } - ], - "source": [ - "expt_cfg={\"start\":soccfg.us2cycles(0.0), \"step\":soccfg.us2cycles(1), \"phase_step\": soccfg.deg2reg(2*360/100, gen_ch=2), \"expts\":250,\n", - " \"reps\": 10, \"rounds\": 200\n", - " }\n", - "config={**hw_cfg,**readout_cfg,**qubit_cfg,**expt_cfg} #combine configs\n", - "t2p=RamseyProgram(soccfg, config)\n", - "x_pts, avgi, avgq= t2p.acquire(soc, threshold=readout_cfg[\"threshold\"], load_pulses=True,progress=True, debug=False)\n", - "\n", - "subplot(111, title=\"Ramsey Fringe Experiment\", xlabel=\"Delay time ($\\mu$s)\", ylabel=\"Qubit Population\")\n", - "plot(soccfg.cycles2us(x_pts),avgi[0][0],'o-')\n", - "ylim(0,1);" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "# Active reset\n", - "\n", - "This experiment demonstrates active reset with the QICK. \n", - "\n", - "The protocol is as follows: there is an overall loop over the qubit drive pulse amplitude (as in the amplitude Rabi measurement above). During each loop iteration, several measurements occur. First, an amplitude rabi measurement is done (labeled \"pre-reset\" in the below plot). If that measurement doesn't exceed a threshold (meaning that the qubit is in its ground state after the qubit drive pulse was applied) nothing is done. But if the measurement exceeds the threshold (meaning that the the qubit is in its excited state after the qubit drive pulse was applied) a $\\pi$ pulse is applied to the qubit (hopefully bringing it back to the gnd state). Finally, a second measurement is done (labeled \"post-reset\" in the below plot). \n", - "\n", - "Note that to run this experiment you must first successfully calibrate the single-shot readout threshold using the Single Shot experiment above. " - ] - }, - { - "cell_type": "code", - "execution_count": 19, - "metadata": { - "ExecuteTime": { - "end_time": "2021-09-30T07:44:01.977293Z", - "start_time": "2021-09-30T07:44:01.666489Z" - } - }, - "outputs": [], - "source": [ - "class ActiveResetProgram(RAveragerProgram): \n", - " def initialize(self):\n", - " cfg=self.cfg\n", - " \n", - " self.q_rp=self.ch_page(self.cfg[\"qubit_ch\"]) # get register page for qubit_ch\n", - " self.r_gain=self.sreg(cfg[\"qubit_ch\"], \"gain\") # get frequency register for qubit_ch \n", - " \n", - " self.r_gain2=4\n", - " self.regwi(self.q_rp, self.r_gain2, cfg[\"start\"]) \n", - "\n", - " self.r_thresh = 6\n", - " self.regwi(0,self.r_thresh,config[\"threshold\"]*cfg[\"readout_length\"])\n", - " \n", - " self.declare_gen(ch=cfg[\"res_ch\"], nqz=1) #Readout\n", - " self.declare_gen(ch=cfg[\"qubit_ch\"], nqz=2) #Qubit\n", - " for ch in [0,1]: #configure the readout lengths and downconversion frequencies\n", - " self.declare_readout(ch=ch, length=cfg[\"readout_length\"],\n", - " freq=cfg[\"f_res\"], gen_ch=cfg[\"res_ch\"])\n", - " \n", - " f_res=self.freq2reg(cfg[\"f_res\"], gen_ch=cfg[\"res_ch\"], ro_ch=0) # conver f_res to dac register value\n", - " f_ge=self.freq2reg(cfg[\"f_ge\"], gen_ch=cfg[\"qubit_ch\"])\n", - "\n", - " # add qubit and readout pulses to respective channels\n", - " self.add_gauss(ch=cfg[\"qubit_ch\"], name=\"qubit\", sigma=cfg[\"sigma\"], length=cfg[\"sigma\"]*4)\n", - " self.set_pulse_registers(ch=cfg[\"qubit_ch\"], style=\"arb\", freq=f_ge, phase=0, gain=cfg[\"start\"], \n", - " waveform=\"qubit\")\n", - " self.set_pulse_registers(ch=cfg[\"res_ch\"], style=\"const\", freq=f_res, phase=cfg[\"res_phase\"], gain=cfg[\"res_gain\"], \n", - " length=cfg[\"readout_length\"]) \n", - " \n", - " self.sync_all(self.us2cycles(500))\n", - " \n", - " def body(self):\n", - " self.mathi(self.q_rp,self.r_gain,self.r_gain2,\"+\",0)\n", - " \n", - " self.pulse(ch=self.cfg[\"qubit_ch\"]) #play probe pulse\n", - " self.sync_all(self.us2cycles(0.05))\n", - " \n", - " self.measure(pulse_ch=self.cfg[\"res_ch\"], \n", - " adcs=[0,1],\n", - " adc_trig_offset=self.cfg[\"adc_trig_offset\"])\n", - " \n", - " self.wait_all(200) # pause until 200 clocks past the end of the readout window\n", - " self.read(0,0,\"lower\",2)\n", - " self.read(0,0,\"upper\",3)\n", - " self.condj(0,2,'<',self.r_thresh,'after_reset')\n", - "\n", - " self.regwi(self.q_rp, self.r_gain, self.cfg[\"pi_gain\"]) #pi pulse qubit\n", - " self.pulse(ch=self.cfg[\"qubit_ch\"], t=0)\n", - "\n", - " self.label('after_reset')\n", - " self.sync_all(self.us2cycles(1)) # align channels and wait 50ns\n", - "\n", - " #trigger measurement, play measurement pulse, wait for qubit to relax\n", - " self.measure(pulse_ch=self.cfg[\"res_ch\"], \n", - " adcs=[0,1],\n", - " adc_trig_offset=self.cfg[\"adc_trig_offset\"],\n", - " wait=True,\n", - " syncdelay=self.us2cycles(self.cfg[\"relax_delay\"]))\n", - "\n", - " def update(self):\n", - " self.mathi(self.q_rp, self.r_gain2, self.r_gain2, '+', self.cfg[\"step\"]) # update frequency list index\n", - " " - ] - }, - { - "cell_type": "code", - "execution_count": 20, - "metadata": { - "ExecuteTime": { - "end_time": "2021-09-30T07:45:04.286343Z", - "start_time": "2021-09-30T07:44:01.984678Z" - } - }, - "outputs": [ - { - "data": { - "application/vnd.jupyter.widget-view+json": { - "model_id": "413c40f8522546cc9ad7e965f6ec9797", - "version_major": 2, - "version_minor": 0 - }, - "text/plain": [ - "HBox(children=(IntProgress(value=0, max=240000), HTML(value='')))" - ] - }, - "metadata": {}, - "output_type": "display_data" - }, - { - "name": "stdout", - "output_type": "stream", - "text": [ - "\n" - ] - }, - { - "data": { - "image/png": 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iN9MXrKG80hka5S4pZ/qCNQAKokVERCRutZoA2lq7lBPrN0d6zBRgSj1tngeeb2y/RESkrtmLNvmCZ6/yympmL9qkAFpERETiVqsJoEVEpO3YVVLeoO0a7i0iIiLxQAG0iIg0WO8sF+4gwXInVzIFsxbXCpSBiId7K9AWERGJf1OmTOGpp57i//7v/5gyZUqsu9MgCqBFRKTBbhk7iNvmf1JrW3KC4WhFFSXllYATKN8ybzU2yPHBhntHOq9aQbaIiIjESptexkpERGKjc0dnPdFsz2NqcgLpqUlUVtcOl4MFz17+w72Lit3c+sLHIedV+7ebvmAN7pJyLCeC7KJid9PekIiIiEgEFECLiEiDLfxkN5mpSbw3/QKuPrsvCcZQUlbZoHP0znIBJ4Liahs83PYPtMMVLwunqNhNwazFDLhjIQWzFivgFhGRWowxvnWDH3/8cfLz80lLSyM7O5uJEyeydu3aeo/761//yllnnUVmZibGGEpKSnztKisrefTRRzn33HPp3LkzqampDBo0iF/+8pfs3bu3wf2dO3cuxhimTJnC/v37+fnPf86AAQNISUmhsLCwVtsdO3bwi1/8gry8PFwuF5mZmRQUFDB37lxskP97S0pKmDFjBkOGDCEtLQ2Xy0WfPn04//zzmTlzZtD+RHqNbdu2YYzhqaeeAuDaa6/1fQ+NMcydO7fB34uWpiHcIiISsaJiN398cyO7So+RlpLI62t2c8HgHjy7YjvZHVPYf7QiovO4khMZPbgbBbMWB51L7a93lss3bDtU21DFy7x91pJbIiItq61Ot7nlllt48MEHOffcc7nkkktYtWoVL7/8MosWLWLRokWMHDky6HE333wzjzzyCAUFBVx88cV8+umnvsD60KFDTJgwgeXLl9OpUyfOOOMMsrKyWLVqFX/605946aWXWLZsGf37929wf/ft28eIESMoLS3l3HPPZfjw4WRnZ/v2L1myhEsvvZTS0lIGDhzIhRdeyJEjR1ixYgXXXnstixcv5umnn/a1Lysro6CggPXr19O9e3fGjh1Lx44d2b17N+vXr2fFihVMnz69Vh8aco309HQmT57M8uXL2bJlCwUFBQwcONB3Lv/nrZUCaBERiUhgIFpWUc30BWsozO8NEHHwnJqcwKQzcnhppbtONjmYcHOpvRKMoajYHfSPMy25JSLSstryjcvHH3+cJUuWcN555wFgrWXGjBnMmjWL73//+3z66aekpqbWOe6ZZ57hvffe48wzz6yz7/rrr2f58uVcdtllPP7443Tu3BmA6upqZsyYwR//+EemTJnC0qVLG9zfhQsXMm7cOObPn09GRkatfbt372bSpEkcOXKEuXPn8oMf/MAX1O/YsYPvfOc7PPPMM4wZM8ZXyGv+/PmsX7+eCRMmUFRURFLSiXCxurqaZcuWNekaXbt2Ze7cuUyZMoUtW7bwox/9SEXEREQkPoUKRP/+wY6g7Q2150C7khM5o18WH247yFsbvoooePYKFzwDVFvLLfNWM3XeanICMh0NXXJLRKS9+e/X1rF+16Gona94ewkV1TW1tpVXVnP7/E/42wfbo3KNr/fO5K5vD4nKufzdcMMNvuAZnCHav//973nhhRfYunUrL730EldddVWd426//fagwfP69euZN28e/fr14+mnn8blcvn2JSYmMnPmTN58802WLVvGmjVrGDp0aIP6m5yczGOPPVYneAZ44IEHOHjwILfffjuTJ0+utS83N5cnnniCESNG8NBDD/mC2C+//BKAsWPH1gqevf0dM2ZMk6/R1mkOtIiIhOWdPxxq+HSw4DYny8WfrjidnCwXxvN65sShnJ6bxfGqGnaXHgt7TdOIfnr7EVhYzDvXOlh7zYcWEYm+wOC5vu2tydVXX11nW2JiIldeeSVAyCzxxIkTg25/4403ALj44otrBc9eCQkJvmHh7733XoP7O2zYsJBDv19//XUALr/88qD7zzjjDNLT01m9ejXHjjn/L3tvAtx33308++yzteZxR+sabZ0y0CIi4hM4Z2304G4RD7X2t6uknML8nDrLT/11+ef1HpsTYo3phiivrGbqvNXMXrSJ8/O68vz7O4IG+m1pWKGISHOJdiY31E3XnCwX837yX1G9VrQNGDAg6HZvkLpz586g+/v16xd0+9atWwF4+OGHefjhh8Ne21tMbOPGjcyaNavO/sLCwjoFwkJd1//aI0aMCHtdgP3795OTk8OoUaO4/fbbmTNnDtdccw3GGAYPHszIkSOZNGkS48ePb/I12joF0CIi7VCw4i5AnTlrz63YHnb4dOAwba9gWV9nCHjo7IMrOZGZE4dSmJ9Tb3GxUNcN5C4p57n3nSHmaSmJlFXUvRHgH2yHKnLTVovhiIjEwrTxebX+PwHnd7z3/5q2zDu/N1Cw7DI484bBycSeeuqpYc89ZIhzI2PPnj2+KtX++vfvXyeADnVd/2tfccUVQedt++vQoYPv+X333cdPf/pTXnnlFZYvX84777zDE088wRNPPMG4ceNYuHChb3h3Y6/RlimAFhFpZ0IVd0lNTqiTaQ4XpOaEyFCH+iMp3JzjwHnLwf748gbNoa5bn5oQy2R5hcpGt+ViOCIiseD93dgWbzxu27aN0047Leh2gN69ezfofLm5uQCMHj2a2bNnR3TM+eefH3R5qYbKzc1l8+bN/OY3v/EF55EaMGAAU6dOZerUqQAsX76cK6+8kn/+8588+eSTXH/99U2+RlulOdAiIu1IUbGbW1/4OGgxsIMNWMc5J8vFO3eM4feFQ5k5cWiduc7B/kgKNRfZey7/Ywrzc+qc909XnM62WRPqXBcimzN9rLKGxBCZA69ga0o3du1pEZH2rDA/h3fuGMPnnt/bbSF4BnjuuefqbKuurmbevHmAE9w2xEUXXQRAUVERVVVVTe5fY6794osvNvlcI0eO9BUB+/jjj5t8jZSUFIAW/55EgwJoEZF2wptJrW7iXe3ADHOkfyRNG5+HKzkx7Ln81Xde7/5tsyb4CpbVp9raOn0I5C4pr1VYTFW8RUTaj0ceeYTly5f7Xltrueuuu9i8eTM5OTlMmjSpQecbNmwYhYWFbN68me9+97tB51Dv3r2bBx54IOrB5LRp08jMzOTee+/l4YcfDnr+FStW1Ap+X375Zd5++21qagKqqJeX8+9//xuoPe+6MdcAfHOhN2zY0Pg3GCMmGsMD4t3w4cPtRx99FOtuiIg0SX3zioNxJSfSNT0Zd8kxrKXJw/Caey5x4HDrQN6h4rMXbQr7vYhkPrY3cy4i0tpt2LCBU045JdbdaNW8c5unTp3Kgw8+yHnnnUevXr1YtWoVmzZtwuVy8cYbbzBq1Kigx4WLqQ4dOsR3vvMdli1bRmpqKqeddhr9+vXj0KFD7Nixgw0bNlBTU0N5eXm984i95s6dy7XXXsvkyZOZO3duyHZLlizhsssu48CBA/Tq1YshQ4aQnZ3Nrl272LJlC7t27eKKK67g73//u+/9//nPf6Zbt27k5+fTrVs3SktLeffddzlw4ACDBw9mxYoVdOrUqdHXAFi9ejVnnHEG4CyZ1adPH4wx/PCHP+Scc86J6HsQiYZ89o0xK621w+trpznQIiLtRGMyprd8cxD3/+tTrjqrH78rDF/8JBKBlbmjzXvuu19dR0l57SHp3my3tw/hgm3/wmKjB3fj7x/soKrG+p0rIWTmXAXHRETarvvvv59Bgwbx2GOP8f7775OamkphYSH33HNPg9do9srMzOStt97i+eef59lnn2XVqlWsXLmSzp0707t3b376059yySWXRBw8N8To0aNZt24dDz30EAsXLmTFihVUVlbSs2dPBg0axM0331xrCaopU6aQmprK8uXLWbt2Lfv27SMrK4uBAwdy5ZVXct1119VZc7qh1wA4/fTTmTdvHnPmzOHdd9/lyJEjgDNUPJoBdHNQBjoCykCLSFvmDegakn3ukdmBLw8dJznRUFlt6Zqewq8nfL1NBYKRBLJFxW6mzlvd4HP/ZsIpXHfuSUGvGazybKh54SIiLUEZ6PpFkkmWtkcZaBERaZD6hjQnJxgwUFntn11N5Jtf78Hz72/3bd93pKLNVZ6OJNtdmJ/ToJsLHZISOF5VQ6YrOej+cAXH2sr3TUREREJTETERkTgWLKDzyslyMfvy05h92Wl1qmgv2biXmoCb8PFaeTpYcbNQjlfVkGDgg88PBN2vgmMiIiLxTRloEZE4FipwM1CrAFZgdvSWEMOa4zEQ9F+vNJJMdI2FD7YFD6B7Z7mCnsPiFHHTfGgREZG2TQG0iEgcCxXQhVqTuanHtVWRFBbz6uRK4ov9ZewpPcaKrftrzbMePbgbL3y4k4rqmjrHuUvK29wweBGR9kJznyVSGsItIhJHiordFMxazIA7FlIwazGjB3cjJan2r/pway97NXTN5nhRmJ/DzIlDfWtKm4D9ruRECk7uCsDZM9/ilnmrcZeUY3EC5JdWuunTObXOcV7xOgxeRESkvVAGWkQkTgRmT70B3Td6Z/LR9hIMka/j7D+sub0tx+RffCywkvfowd2Yv3Knr21gvqK8sprP95Vx6bAcXl7lrrMf4nMYvIiISHuhAFpEpA0KtkRTqArQ63YfpkdmB96fMbZB12juNZvbgsDvQcGsxRyrrDs8258Flm3aS1ZaMgfLKuvsj9dh8CIiIu2BAmgRkTYmWKY53Lzd8spqRg7q2pJdjFuRZo/3H60gOcH41tH2ag/D4EVEROKZ5kCLiLQxoTLNiSbUzFs4rU+n5u5Wu9CQ7HFljaVjShLd0jsA0KVjCjMnDm33WX0REZG2TAG0iEgbEyoLWh2kgmhKovNrfmifrGbtU3sRrLha6NsWUFpeyb9+eR4AN55/soJnERGRNk4BtIhIjAVWzi4qdodtHyoLmpHqzMrpnuFkPDt2SGTckB4AfCNHGeho8K/SbYCcLBd/uuJ0X9XuQL2zXGSlpdDJlcwX+8sivk5DPxMiIiLSMjQHWkQkhkLNZ4bQawVPG5/HbS9+TFVN7Yzz4WNVdEhKYMa3TuEfn+xm3a5SqqotuV1cdO6Y0rxvpB0JVVwtcB66/3zn/tlpbNt/NKLzN+YzISIiIi1DGWgRkRgKNZ853FrB3z6tN2kpCXRIqvsr/HhVDdMXrKGsopLdpcd4c90e9h0+rgxmMwuWmfaf79wvu2PEGejGfCZERESkZSgDLSISQ6HmMwfb7l26yu3Zd21BP/657ivfa6/yymre3XLA73WNMpgtINyyX/2y0/jHJ7uoqKohJciND38N+UyIiIhIy1IGWkQkhkLNZw7c7h3W6x8s/+2DHXWC51CUwYytftkdqbFE9POK9DMhIiIiLU8BtIhIDE0bn0diQt06zmUVVbWGXQcb1nussibs0lWBlMGMnf7ZaQARzYOeNj6PxIAfq9aPFhFpv/r3748xhm3btsW6KzExZcoUjDHMnTs31l0BFECLiMRUYX4OJ3VNIzCGPlhWyfQFa3xBdLilqyJdVkkZzNjpl90RgC/21R9AF+bnkJGa7HsdOJ9aREREYkcBtIhIjB04WklqQBAMtYddhwp+vcGVf/Gqq87uWyeoVgYztrqmp9AxJZFtAYXEgi1X9eWhY5SUV9LJlUxSgmHptPMVPIuIiLQSCqBFRGJo7+Hj7D9aQVlFddD93szztPF5pCbX/pXtDYoL83N4544xfD5rAu/cMYbfFw4NWxFaWp4xxlOJ+6gvaO5/x0Jumbcad0k5lhPLVT26dDMAE77Ri6oaq6H3IiItwBiD8UyLevzxx8nPzyctLY3s7GwmTpzI2rVrQx77xRdfcOONN3LSSSfRoUMHOnfuzOjRo3n++eeDtq+urubRRx/lnHPOoVOnTqSkpNCjRw+GDRvGrbfeyt69ewGYO3cuxhi++OILAAYMGODrZ0OGdHvPM2XKFPbv38/Pf/5zBgwYQEpKCoWFhbXa7tixg1/84hfk5eXhcrnIzMykoKCAuXPnYq2tc+6SkhJmzJjBkCFDSEtLw+Vy0adPH84//3xmzpwZtD+RXmPbtm0YY3jqqacAuPbaa2u9/1gN6VYVbhGRGNq45xDgZCj3Hamos9+beS7Mz2H55n3MX7kT49kTlRrYAAAgAElEQVTuDZ6DCVcRWmKjf9c0Pvz8ACu2HvDNZw/8U6S8spoXV+4kJSmBCUN78fz729m2v8w3BFxEpM345AV46x4o3Qmd+sAFv4VvfDfWvarXLbfcwoMPPsi5557LJZdcwqpVq3j55ZdZtGgRixYtYuTIkbXav//++1x44YWUlJQwYMAALr30Uvbv38+yZctYunQpb775Jk899ZQvOAe47rrreOqpp3C5XIwcOZKuXbuyb98+tmzZwv3338/ll19Ot27dGDhwIJMnT2b+/PkcPXqUSZMmkZ6e7juP//NI7Nu3jxEjRlBaWsq5557L8OHDyc7O9u1fsmQJl156KaWlpQwcOJALL7yQI0eOsGLFCq699loWL17M008/7WtfVlZGQUEB69evp3v37owdO5aOHTuye/du1q9fz4oVK5g+fXqtPjTkGunp6UyePJnly5ezZcsWCgoKGDhwoO9c/s9bkgJoEZEY2rTnMABTxw7iDws31ioUFjjs2n2wnJO6deStX46q9R+xtA39sjvy+po99bY7cryaM/p1ZlB35w+jL/YfBbo1c+9ERKLokxfgtZ9DpWcETekO5zW0+iD68ccfZ8mSJZx33nkAWGuZMWMGs2bN4vvf/z6ffvopqampABw7dozLL7+ckpISpk6dypw5c0hMdKZQrV27lgsuuIBnnnmGgoICfvKTnwBOtvqpp54iNzeXDz/8kB49etS6/urVq+nduzcAI0eOZOTIkSxdupSjR48yZ84c+vfv3+j3tnDhQsaNG8f8+fPJyMiotW/37t1MmjSJI0eOMHfuXH7wgx/4/tbYsWMH3/nOd3jmmWcYM2YMU6ZMAWD+/PmsX7+eCRMmUFRURFLSidCyurqaZcuWNekaXbt2Ze7cuUyZMoUtW7bwox/9yHftWFIALSISQxt2H6Z7RgeuPrs/6R2Sfes8pyYn+IZdFxW7mfXGRvYcOkZGhyReWb1L2eU26MDR4xG3zc/NoltGB1zJiWzbV1b/ASIiTfHGHbBnTfTOt/NDqA74nVdZDq/cBCufis41eg6Fi2ZF51x+brjhBl/wDM7Q7t///ve88MILbN26lZdeeomrrroKgBdffJEdO3bQr18//vjHP/qCZ4BTTz2Vu+++mxtvvJE5c+b4AuivvvoKgGHDhtUJngFOP/30qL8nr+TkZB577LE6wTPAAw88wMGDB7n99tuZPHlyrX25ubk88cQTjBgxgoceesgXxH755ZcAjB07tlbwDJCYmMiYMWOafI3WSHOgRURiaOOeQ+T1dP4j885lvujUnvTq5PIFz9MXrGHPoWMAHD5eVas6t7QNRcVuXi7eFXH7Bat28srqXfTLTvNkoEVE2pDA4Lm+7a3I1VdfXWdbYmIiV155JQBLly71bfdmWK+66iqSk5PrHOeds7t582bcbuf/7cGDB5ORkcHChQu59957ffObW8KwYcNCZrBff/11AC6//PKg+8844wzS09NZvXo1x445f5OceeaZANx33308++yzlJSUhL1+Y67RGikDLSISI1XVNXz21RGmnNO/1vbBPTN5c90eyiqqgq7/7K3OrSx02zF70SYqqmqC7jPUnQt9wLOM2aDuHSNaO1pEpEmincn906nOsO1AnXLh2oXRvVaUDRgwIOh2b+C5c+dO3zZvUBzqmNTUVHr37o3b7cbtdpOTk0NGRgZPPvkkP/zhD7nzzju58847ycnJ4b/+67+YMGEC3/ve93xDxCOxceNGZs2q+/MrLCysUyCsX79+Ic+zdetWAEaMGFHvNffv309OTg6jRo3i9ttvZ86cOVxzzTUYYxg8eDAjR45k0qRJjB8/vsnXaI0UQIuIxMi2/UepqKohr0ftoVR5PTOwFj778kjICsyqzNy2hPt5/emK031D9/2VV1azdV8ZFVU1VNdYEgMXCxcRaa0u+G3tOdAAyS5nexvnX4PEWzE6XF2SYJWrL7vsMsaOHcsrr7zC22+/zTvvvMP8+fOZP38+d999N//5z3/Izc2NqD979uzxVan2179//zoBtMsVfElMcOYsA1xxxRX1BvAdOnTwPb/vvvv46U9/yiuvvMLy5ct55513eOKJJ3jiiScYN24cCxcu9A3vbuw1WhsF0CIiMVBU7Oa/X1sHwKw3N5KYYHwZ5VN6OQH1xj2H6J3lqhNYQeh1oaV1CvVzzMlyhurfMm910OOOHK8CYHdpOX06pzVrH0VEosZbKKwNVuHetm0bp512WtDtgK/AF0CfPn2AE5nVQMeOHWP37t0AdbKpWVlZTJ482TcXeMuWLfz4xz9myZIl/OpXvwq5BFag888/P2iQ3lC5ubls3ryZ3/zmNwwZMqRBxw4YMICpU6cydepUAJYvX86VV17JP//5T5588kmuv/76Jl+jNdEcaBGRFuad13ywrBJw1oL2n9ec2zmNtJRENuw+zLTxeSQG3NgOrM4trd+08Xm4khNrbfP/OYa6IdI1PQWAL/arkJiItDHf+C7cshbuLnEe20DwDPDcc8/V2VZdXc28efMAJ2D1GjVqFAB/+9vfqKqqqnPcU089hbWWgQMH1jsc+eSTT+bOO+8E4OOPP661LyXF+b8g2DWi5aKLLgKcwmhNNXLkSF8RMP/30thrtMT7bwgF0CIiLSzcvGaAhATD13pksGnPYSZ8oxdJiYa0lEQMTsbSW51b2o7C/BxmThxKTpYr6M8xVID9s9HOGpeaBy0i0jIeeeQRli9f7nttreWuu+5i8+bN5OTkMGnSJN++yy+/nNzcXD7//HOmT59OTc2JWhfr16/nrrvuAuC2227zbS8uLmbevHmUl9cdlfTaa68Bdecqe4PvDRs2ROEdBjdt2jQyMzO59957efjhh4MGqytWrKgV/L788su8/fbbtd43QHl5Of/+97+B2u+lMdeAlnn/DaEh3CIiLSySec2De2awaN0ePtx2gONVlkevPp0LT+3ZUl2UZlCYnxPyxod3++xFm9hVUk7vLBfTxufxndN6M/ONjXUy0EXF7jptdVNFRKTpfvzjHzNq1CjOO+88evXqxapVq9i0aRMul4vnnnuu1jzi1NRUXnjhBS666CLmzJnDyy+/zIgRIzhw4ABLly6loqKCa665xjeEGZx1oL/3ve+RlpbGsGHDyM3NpaKiguLiYrZu3UpGRgb33HNPrT5deumlLF26lKuuuopx48aRlZUFOPOPs7Ozo/K+c3NzKSoq4rLLLuOmm27iD3/4A0OGDCE7O5tdu3axZcsWdu3axRVXXOGror1s2TL+/Oc/061bN/Lz8+nWrRulpaW8++67HDhwgMGDB/uW72rsNQAuueQS7rnnHh544AHWrl1Lnz59MMbwwx/+kHPOOScq778hFECLiLSwSOY1D+6Zwd8/3MG8D3eQkpjAyEFdW7KLEgPBAuyiYjc1NZbH397KCx/uwBg4WFZZq3K3u6Sc6QvW+M4hIiKNd//99zNo0CAee+wx3n//fVJTUyksLOSee+5h6NChddqfffbZrF69mlmzZvHmm2+yYMECXC4XZ599Ntdffz3f//73axUZO/vss5k5cybLli1j48aNrFy5kpSUFHJzc7n11lu5+eab62Sgb7rpJg4dOsRzzz3HP/7xD44fd5YD+/Wvfx21ABpg9OjRrFu3joceeoiFCxeyYsUKKisr6dmzJ4MGDeLmm2+uFdhOmTKF1NRUli9fztq1a9m3bx9ZWVkMHDiQK6+8kuuuu67OmtMNvQY4a2PPmzePOXPm8O6773LkyBHAGSoeiwDaRGPSebwbPny4/eijj2LdDRGJE0XFbm578WOqak78/nUlJ9Ya0rti636+9/gKEgwUDOzKM9edFavuSox458oHDvcPJSfLxTt3jGnmXolIW7RhwwZOOeWUWHejVfMGuYqN4ktDPvvGmJXW2uH1tdMcaBGRFlaYn0OvTqkkJ5qQ85q37nXurtZY+GRnia/AmLQfwebKh6OlzURERJqfhnCLiLSwrw4fY8fBcm4b9zVuGjOozv6iYje/+8eJQhml5VUaotsONTQg1tJmIiIizU8ZaBGRZlBU7KZg1mIG3LGQglmLa2WQl27cC8CYwT2CHltflW5pHxoSEGtpMxERkZahAFpEJMq8c1fdJeVYThR58gbRb238kl6dUjmlV0bQ4yOp0i3xL9jSVv68JWkSDNxzyRCNThARaQJrreY/S0QUQIuIRFmoDPLdr67jnJlvsWjdl5SWV/LK6l1Bjw+VedQQ3fYlcO3oLFcyndOSffPm/3TF6fxs9MnUWJg2/5M6Ix1EREQk+jQHWkQkykJlikvKKykprwSgrKI65LzmaePz6lRf1hDd9inc2tFFxW6eXP6577WWsxIREWl+ykCLiERZpJniUPOaAzOPwap0izgjHWpqbdNceRERkealDLSISJTdNu5r3PLCxxG1DZWtDpd5FAHNlReRhrHW+tY6FmkPmmtOuzLQIiJRNqiHUxysk8u5R5mRmkTntOSgbTWvWRpLc+VFJFKJiYlUV0e+rrxIPKipqSEhIfrhrgJoEZEoe2vDVxgDi289nyG9Mxma04m7vj2EpITad/41r1maIliVbldyAtPG54VdRk1E2p+0tDSOHDkS626ItKiysjJcrujfVFYALSISZYs3fkl+bhbZ6R04c0AXVm0/yLeG9qJvlzSSEozmNUtU+M+V97ptnHNDJtwyaiLS/mRmZnLgwAFloaXdsNZSUlJCx44do35uzYEWEWmComI3sxdtYldJOZ1cyVgspeVVZKYmUVTs5qwBXfi/d7bxn8/2sm3/UX42eiC3jlPWWaLDO1d+/a5DfOvB/5Cd3iHkMmqzF23SDRuRdiojI4Py8nK++OILunTpQnp6OomJiZoTLXHHWktFRQX79++nqqqKzp07R/0aCqBFRBqpqNhda7kp7xJVAIeOVTF9wRrunDAYgDn//JQaC2MGd49JXyW+5fXMoGNKIqu2H1RxMRGpwxhD9+7dOXz4MIcOHeKrr75SNlriVlJSEp06daJ79+7NMgdaAbSISCMFy/T5K6+sZs6iT0lKMGzYfYgEA9v2HiW/b/Tvhkr7lphgOC03i1XbD9I7y4U7SLCs4mIi7ZsxhszMTDIzM2PdFZE2TXOgRUQaKZKMXkl5JVU1zjIKNRZmFK3VXFRpFsP6dmbD7sPccP7JdfapYJ2IiEh0KIAWEWmkxmT0vHNRRaJtWL8sqmss63YdAiC7YwoA6R0SVbBOREQkSlpdAG2M+b4x5j/GmFJjzBFjzEfGmJ8ZYxrcV2NMZ2PMvcaYNcaYo8aY48aYL4wxzxhjTm+O/otI+zFtfB4dkhr+a1RzUaU57C45BsDfPthOYoLh1986hWF9s8jrmangWUREJEpaVQBtjHkYeA4YDvwH+BfwNeAvwHxjTGKYwwPP1RdYDUwHegJLgNeASuBq4ENjzKSovgERaVcK83P45td7AGCALFcyndOSfctUdU5LDnqc5qJKtBUVu/n9wg2+19U1lhlFa8lMTWKNu5SKqpoY9k5ERCR+tJoiYp5g9kZgD3CetfYzz/YeOMHvpcBNwJ8jPOUsoC/wOnC5tbbMc74E4LfAXcBjxphXrbWVoU8jIhJaSVkleT0yWHTLeXX2BVbpBs1FleYRaumqT3Y6wfO6XaUqXiciIhIFrSkDPd3z+Ctv8Axgrf0SuMHz8o4GDOUe7Xn8nTd49pyvBvgdUA5kA4Oa1GsRabeOVVbzwbYDFAzsGnR/YX4OMycOJSfL5ctKay6qNIdQ0wIOljn3h1dtL2nJ7oiIiMStVpGBNsb0Ac4AKoAXA/dba5cZY9xADnA28G4Epz0e4eX3RdpPERF/H207SEVVDecOCh5AgxNEK2CW5hZu6SprLau2H+Q6BsSgZyIiIvGltWSg8z2P66y1oarrfBjQtj5veh5/bYxJ8240xhicIdwu4FVr7VcN7ayISFGxm58+uxKAGS+v0dJUElPTxufhSq5dJsQ7XaB7ZgfeXLObAXcspGDWYn1WRUREmqBVZKDBd1v8izBttge0rc+vcYLtCcAXxpgVOFnp04B+wLM4c65FRBokcG7z7tJjTF+wBkDZZokJ7+du9qJN7Copp3eWyzfXft2uQ1Q7S5HjLinXZ1VERKQJWksAne55PBqmzRHPY0YkJ7TW7jPGjAEeBiYDF/vt3gQss9YebmhHRURCFWyavWiTghKJmWDTBQpmLabSGz176LMqIiLSeK1lCLfxPNqwrRpyQmMGA8XAeOAaoBeQBVyAE6g/YYx5Mszx13vWoP5o79690eqWiMSBUAWbtL6ztDb6rIqIiERXawmgvZng9DBtvPvqzRobY5KAl4CBwERr7bPW2j3W2lJr7WLgm8CXwLXGmNHBzmGtfdxaO9xaO7xbt24RvxERiX+h1nHW+s7S2uizKiIiEl2tJYDe5nnsF6ZNbkDbcM4Cvg58bq19L3CntfYA8Ibn5djIuigi4vjlN+uufqf1naU1CldcTERERBqutcyBLvY8DjHGuEJU4h4R0Dacvp7H0jBtvItidongfCLSThUVu+sUZuqd5RT279IxhYNHK3zbNadUWhv/4mLuknKSEgz3XnqqPqsiIiKNZKyN2rTjJjHGrASGAZOttU8H7BsFLAX2ADnW2pp6zuVtXw70ttaWBGnzHs6a0r+y1v4x3PmGDx9uP/roo8jfjIjEhcBq2+Bk784+qTPvbD7Aqt9+k/QOreU+pEh4t8//mBc+2okB3fQREREJYIxZaa0dXl+71jKEG2Cm5/E+Y8xA70ZjTHfgEc/LWf7BszHmJmPMRmNMrYAbeA/YhbPW81+NMZl+xyQYY36NEzxX4cyVFhGpI1S17f98tp+zTuqi4FnajKJiN69+vAtwqnV6l7PSmtAiIiIN02oCaGvtfOB/gJ7AGmPMa8aYBcBnOPOZi4C/BBzWFcjjxJBt77kqgCk4GeiJwFZjzBue820GfgfUAFOttVua7U2JSJsWqlJxVY3lk50lCj6kzZi9aBPHKmsP3vIuZyUiIiKRazUBNIC19kbgKmAVMApnCarNwE3AJGttdZjDA8/1L+A04FFgP3A+zlrQScDfgQJr7cPR7L+IxJdwlYpLy6uUwZM2Q8tZiYiIREerCqABrLXPW2sLrLWZ1tqO1tozrLUPB5v3bK2921prrLXnhzjXZ9baG6y1edZal7U2xVrb11p7pbV2RbO/GRFp06aNzyM50YTcrwyetBVazkpERCQ6Wl0ALSLSWhTm5zC0dycSQsfQyuBJmxBsOavU5AQtZyUiItJACqBFREKoqq5h894jTBzWhxxl8KQNK8zPYebEobU+x1eemasq3CIiIg2kAFpEJISVXxzk0LEqLhjcPWgGz5WcqAyetBmF+Tm8c8cYNv/hIrp0TGHv4YpYd0lERKTN0RosIiIBiordzF60CbdneHZpeQXfO7Mf4FQz3lVSrnV0pc1KSkwgr2c6Cz/ZzcJPFtLJlYwxcLCskkRjqLaWHH2+RUREglIALSLip6jYzfQFa2qt//zfr20gNTmJwvwcBRTS5hUVu1m5rQTreV1SXunbV22drd51ogF95kVERPxoCLeIiJ/ZizbVCp5B1bYlvsxetImK6joLW9Shz72IiEhdCqBFRPxovVyJdw35LOtzLyIiUpuGcItIu+Od4xxsLnPvLJdv7rM/VduWeBHqMx6qrYiIiJygDLSItCveOc7uknIsJ+Z6FhW7AWe93OTE2gs/q9q2xJNgFeWD0edeRESkLmWgRaRdCTXHeeq81dz96jqMgcpq69unasQSb7yfZe8ojGBVuAGmX6TPvYiISCAF0CLSroSb0+lfjRhOZOAUREi8CVdRfvWOEgoffocu6R1auFciIiKtn4Zwi0i70pA5napCLO3RkN6ZpKUk8sHnB+rsKyp2UzBrMQPuWEjBrMW+qQ8iIiLthQJoEWlXnPmfkf/qUxViaW+SExM4o1/nOgF0ffUDRERE2gMF0CLSrhTm53DTmEERt1cVYmmPzuzfhY17DlNSVuHbFqp+wN2vrlNWWkRE2g0F0CLS7nRyJQPwmwmnhK1GrCrE0l4dr3IC5dPv+ZcvKA41GqOkvFJZaRERaTcUQItIu7Nq+0GyO6bww5EDmDlxKDlZLgyQ5Uqmc1oyBqf69syJQ1VATNqdomI3/7v8c99rb1CclZYc0fGqHSAiIvFMVbhFpN0p3l5Cft/OGGPCViMWaY9mL9rEscqaWtvKK6tJSTIhjqhLtQNERCReKYAWkbhWVOz2rXfbO8vFDeefzOf7jnL58D6x7ppIqxQq+C0trwIgLSWRsopqemR2oKKqhoNllXXaqnaAiIjEKw3hFpG4Faxq8D2vrQdgWN/Ose2cSCsVLvhNTjT8bPRAAKZfdAp3fXsIKYm1M9OqHSAiIvFMAbSIxK1gVYMrqp2hqbfMW61CRyJBOEu9BS+uV1lt+cviz0hJNKzafpDC/BxG9O/i2985LVm1A0REJK4pgBaRuBVuHubu0mOqFiwSRGF+jq+4XjDllTUY4wTQ4PxbOndQV5ITDd8dkavgWURE4poCaBGJW/XNw1S1YJHgCvNzeOeOMYQqG3a8qoYNuw+z+asjbN13lPPzunNS13Q2f3mkRfspIiLS0hRAi0jcmjY+j6SE8JWDVS1YJLRQN6GyO6ZQXWN5ZOlmAEYO7MqgHul8+tXhluyeiIhIi1MALSJxqzA/h27pKXRICv2rTtWCRUILNh/alZzImMHdAViwyk2CgfW7Svlajwx2HCinrKIqFl0VERFpEQqgRSRu7TxYxu5Dx5k2Po8Hrjg9aCCgasEiofnPhzZATpaLSWfk8I9Pdvva1FiY8fJaDh49DsCWr47GqLciIiLNT+tAi0jcWrLxKwAuOKUHA7p2BKi1JvS08XkqeCRSj8L8nFr/TgpmLa5T3b68spqFa/YA8OmXhxnap1OL9lFERKSlKIAWkbhTVOxm9qJNuEvKSUowfLyjhAFdO9YJBESk4ULVDdh7+DgpiQmaBy0iInGtUQG0MaYP0BtIDdXGWvt2YzslItJYRcVupi9Y48uQVdVYpi9YA6DgWSQKeme5cAcJontnuchITeIzVeIWEZE41qA50MaYicaYTcAXwHvAkhBfi6PcTxGRiMxetCno8FItVyUSHaEKi00bn8fA7ul8pgy0iIjEsYgz0MaYbwMv4ATdpcBW4FAz9UtEpFFCDS/VclUi0eEdyRGsnsD2A2X845PdlFVUkZaiWWIiIhJ/GvK/2wzAAL8GZltrK5unSyIijRdueKmIREeoegIHy5xK3EN+u0iF+kREJC41ZAj3N4Bia+29Cp5FpLWaNj6vzrrPWq5KpPkVFbt5/v0dAFjAXVLO9AVrKCp2x7ZjIiIiUdSQALoS0CRCEWnVCvNzGJ3XHcC3bu3MiUOVBRNpZrMXbeJ4VU2tbao/ICIi8aYhQ7hXAic1V0dERKJld2k5w/pmseDGglh3RaTdUP0BERFpDxqSgZ4FnGmM+WZzdUZEpKm+OnyMj3eWcsEpPWLdFZF2JVSdAdUfEBGReNKQAHoT8AfgVWPMfcaY84wx/Y0xfYN9NVN/RUTCWrpxLwBjBnePcU9E2pdwy1uJiIjEi4YM4d6GUxfEALd5vkKxDTy3iEiTFBW7mb1oE+6SchINbNx9iFN6Zca6WyLthrfOwN2vrqOkvJIemR2YftEpqj8gIiJxpSFB7nacwFhEpFUpKnYzfcEayiurAai2MOPltRhj9Me7SAsqzM+hV6dUrnh8BbMvO43zvtYt1l0SERGJqogDaGtt/2bsh4hIo81etMkXPHt5q/8qgBZpWSd1Swfg831HFUCLiEjc0TBrEWlzvMO1d5WU0zvLhVvVf0Vaja7pKWR0SOLzfUdj3RUREZGoUwAtIm1K4HBtd0k5huDzS1T9V6TlGWMY0K0jWxVAi4hIHGpwAG2M6Qr8GDgf8I6NdANLgL9aa/dGrXciIgGCDdcOFjyr+q9I7Azo2pFV2w/GuhsiIiJR16AA2hhzEfAc0AmnGrfX14GxwDRjzNXW2jei10URkRPqG5ZtcDLP08bnaf6zSIwM6NqRVz/exfGqajokJdZ/gIiISBsRcQBtjBkMvASkAu8D/wdswfl7dQBwLXA2MN8Yc4a1dmP0uysi7V2oOc8piQkM6pHOwp+fG4NeiYi/AV07Yi1s31/GoB4Zse6OiIhI1DQkA30HTvA8zVr7/4Lsf8IY80tgDvArnIBaRCQigYXBQmWQp43P446XPuFYVY1vW4ekBI5X1XDB4O4t2WURCeGkrk4l7q37jtYKoCP9dy4iItJaJTSg7RhgbYjgGQBr7f3AWuCCpnZMRNoPb2Ewd0k5Fqcw2PQFaygqdtdpW5ifw09GnVxrW2W1E0z/7YMdQY8RkZbVv2saAFv3nigk1pB/5yIiIq1VQwLoHsAnEbRbAygNJCIRC7eOczDeP86nXzSYRGOo8VQR23vkuP4gF2kFMlKT6ZbRgc/3HfFtC/XvfOq81RTMWqx/tyIi0iY0JIA+xImq2+H0Bg43rjsi0h6FKgwWavv2/c72p97dRrWtXYM7XOAtIi1nQNeOtdaCDlcAUNloERFpKxoSQH8EjDTGFIRqYIw5BzgX+LCpHROR9iPUes29s1wUFbspmLWYAXcs9GWpth8oo2dmKrtLjwU9rr5K3SLSvIqK3ax1l/LhtoO+f7e9slLDHqObXyIi0hY0JID+C5AIvGGMuccYc7IxJskYk+h5/t/AGzhVuf/SHJ0Vkfg0bXweqcl1fx25S8q5Zd7qOnMmi7cfpG+XtLCBt4jEhneuc1mFM1zb++94V0nwG17+dPNLRERau4gDaGvtQuA+IB24E/gUKAeOeZ7/GsgA7rPWvh79ropIvCrMz+FHIwcE3WcDXpdXVrNt/1H6ZqcxbXweruTaa8y6khOZNj6vmXoqIvUJNtfZ/9+xCXOsbn6JiLuv7IwAACAASURBVEhr15AMNNba6cDFwFKgAicjneh5vgS42Fo7I8p9FJF2oGt6BwB6ZoYf5glQY6FvlzQK83OYOXEoOVkuDJCT5WLmxKFaFkckhurLIlsgy5Wsm18iItImNWQdaAA82eXXjTGJQDbOzeR91trq8EeKiIS26cvDZKUl8+Wh+od5ghNAg5O9VsAs0nr0znLhrieILi2v5E9XnM6Ml52h3jmeNaEBCmYt1jrRIiLSajUoA+3PWlttrf3KWvulgmcRaaoNuw8zuGdGvUM4UxKdX1u5ngBaRFqXYFMrAvXOclGYn8NPPWu6v3XrKACtEy0iIq1eowNoEZFoqamxfPrlYQb3zAz7x3d2xxQu/kZPAPplK4AWaY38p1ZA3TnP/kO1vSNJdh4sa/B68CIiIrEQcgi3Mea3nqd/sdYe8HsdCWut/V3TuiYi7cWOg2WUVVQzuGeGb7jm7EWbfMM4f3HBIGa8vIbvjsjlWGU1aSmJZHdMiXGvRSQU/6kVRcXuWv+e/Ydle0eSbD9Q1uD14EVERGIh3Bzou3FqffwdOOD3OlwBTe9+CyiAFpGIbNxzGIDBvTKB4POa//7hdj74/ACd05Lp2yUNY8L9KhKR1iJcnQJvBnr7/rKQc6dVmVtEpG0LdyO1LQoXQN+DEwjvC3gtIhJVG3cfxhj4Wo/0kG3OHJDNX5dvpWenVAb3zGzB3olIc+mankJaSiLbD5QzbXwev3rpE45X1fj2qzK3iEjbVlTsZvqCNb4pOt76FkCbDaJDBtDW2rvDvRYRiZaNew7Rr0saaSmh7+mddVIXHl22hR0Hyhn/9Z4t2DsRaS7GGPp2SWP7gTJ+++2v896Wfcz7aCcA3TM6MONbp7TZP7BERISw9S3a6u93FRETkZgpKnZTMGsxb6zdw55Dx8JW291TemJo54srd6oyr0icyO2SxvYDRwFISTpRQPChK/Pb7B9XIiLiiMf6FhEH0MaYrcaY+yJoN9MYs6Vp3RKReOcd0uOd83issibkkjVFxW7ueW2D73VpeaWWtxGJE94MtLWWdbtK6eIpELj3yPEY90xERJoqVB2LtlzfoiEZ6P5AtwjadfW0lf/P3p3Hx3WX9x7/PDMaSaPdlleN4yWbnDhOomykmJLEAQQpi+I0Xei9XWjp7SXQAo0vNtxCoBQbDLeFstxSSntpgdIERyxpMRBnIQkhm5I4Tuws3sebFmsfjZb53T/OjKyRZkYaLdZo9H2/XvMazTlnjn9+JT46z/k9v+cRkbSyaVmj9jYi+WvlwhL6BmKc6ozy0oku3njRIgCauxRAi4jMdZvrayn0Jxd+nev1LWYihTsIDM7AeUUkj2ST0pOP6T8i4klU4n745WYiA0O8/sJFFPiMFs1Ai4jMeQ11Id5xRQ3gtWoKVQXZtmn9nF6ik6kKd9bMrBLYAJyczvOKSP7JpmWN2tuI5K+V1V4A/ZO93q3DZTWVVJcVagZaRCRP1FQF8Rm88je34PfN/TakGWeg4+ueD5jZgfim3xy5bdTrCHAaWAnsmuyAzOzdZvYLM+sws24ze8rM7jCzSc2Wm5nfzP6HmT1sZq1m1mdmR83sR2b2jsmOU0SmZnN9LcGAP2lbupSebI4VkbklVBXEDB55pYWA37hwSRmLy4to6e6f7aGJiMg0aOmOsrC0MC+CZxh/Bnr1iJ8dUBZ/pdMPNAIfmcxgzOwrwPuAPuB+YAC4GfgycLOZ3e6cG8pwitHnWwj8F3Ad0AE8CnQB58XPewr40WTGKiJTk0jdSfQGDFUF2VxfmzKlJ7Ftx679HG+PUJPhWBGZW4oDfpZVFHOio491NRUUFvhYVFakGWgRkTzR3BVlUVnRbA9j2owXQK+JvxtwALgH2Jzm2H6g2Tk3qfXPZnYbXvB8Enijc+6V+PalwAPArcD7gS9O8Hw+vOD4OuAbwAedcz0j9pehYmcis6qhLsQ9Tx+jOzpI4x0bxj1WAbNI/mlsCtMan20+2NJDY1OYxWVF7D/ZldU59IBNRCQ3NXf3s7h8ngTQzrnDiZ/N7P8Bvxi5bZptjb9/JBE8x8dwysz+J/AgsMXM/t45F5vA+d4LvB54CPhT55wbudM51w28MC0jF5FJO93Vx+rq0tkehojMgkQ7u/4h79d6b/8QW3fuYcOF1bR0R4nFHD987njG4DhxjkSl/nB7hK079wAoiBYRyQEtXVEuWJQ/93oTXlfsnPsj59w3Z2IQZrYCuBpvFvvuFH/2Q0AYWAZcP8HTvj/+/tnRwbOI5I7TXVGWVOTPU0kRmbh0LeqePNTGwJDju08cGe4X7zgbHI/sAa82dyIiucs5R3N3NK9moGeijdVk1MXf9zrn0vWleXLUsWmZ2TLgMrw11A+Y2Xozu8vM/sHMPmNmb576kEVkqvoGhmjvHWBpefFsD0VEZkG6VnQdEW812Bfvf2Xc4Fht7kREcldn3yD9g7F5tQZ6DDO7FvhN4GKgAm999GjOOXdzFqdNrLXOlB5+ZNSxmVwefz8E/BVeevjIcW41s4eB25xzLVmMU0SmUaJIkGagReandC3qFpUV0tLdz+k0hcRGBscTaXOnNdIiItNrotfVxL3evJ2BNrO/BR7HKyT2LuDGUa8bRvycjURl754Mx3TH38sncL6F8fc1wEeBfwUuwQv4NwIvAW8E/iPLcYrINErcHC/RDLTIvJSuRd17f/18ABaUBFJ+b2RwvLm+dkxrlJFt7hJrpDOlgYuIyMRlc11t6Z7HAbSZ/S7wF8Ax4E+Bn8Z31QN3AI/hzfJ+Fi9IzUbiN990rVVO/L0KgPudc3/gnNvnnOtyzj0AvAWIADeZ2Q0pB2T2p/Ee1E81NzdP07BEZKTTnX2AZqBF5quGuhDbNq33ekHj9YTetmk9v3PtSgBuuHjxuD3gG+pCrKg6+xAucY6R7e+0RlpEZPpkc11NzEDP1xTu9wKDwEbn3GtmtgHAOfcz4GfA18zs48DHgO9nOY5Er4pMPaYT+ybS12LkMV8fvdM5d8zM7sNLRb8Zr1L36GO+nvjuNddcoyJkIjNAM9AikqpFnXOOQr+PZZVBPnPrZfzl3c8Rc97T9s80XJZ0/FDMcbrLa4NV6Pfx8P+6KWlGWmukRUSmVzbX1Xk9Aw1cATzunHstwzF/DRzFC6KzcSj+virDMeeNOnYi5wM4mOaYxPZlEzifiMyA0119+H1GdWnhbA9FRHKImbG4vIjmrijXX1BNzMHlKypxwPrzKpOOPdjSQ2RgiKtXLaB/KMapeGZLwsh074lsFxGRzLK5rjZ3RfH7jKpg6iU5c1E2AXQpXvp2QhTAzIbXJMfbRT2J1385G03x93Vmlu432rWjjs1kH2fXU1enOWZR/L07zX4RmWGnOqMsLivC50tVi1BE5rNFZYU0d0fZG+4EGE7rfu5oR9Jxe497n992mfc8/HBrb9L+zfW1FPqTb3dGp4GLiMjEba6vpTgwsetqS3eURWWFeXWvl00AfZrkYDSxMPjCUcdVkjkVewzn3FHgGaAQuH30/vg65RXASeCXEzjfAPDj+Mcx1cDNLIBXRAzgqWzGKiLTRz2gRSSdxeVFtHRF2Xu8EzN4+xXLKSn0syecHEC/eLyTQr+Pm9YuAeBoW3IA3VAX4pb1Z5PNRq+RFhGR7DTUhfjLN58NlpdXFqe9rjZ35VcPaMgugH6V5BZST+ItR/qzxAYzqwVuAjKleaezLf7+WTMbDsrNbAnw1fjH7c652Ih97zezfWb2rTTniwF3mNnNI77jxyt0dgEQBu6dxFhFJEuNTWE2bN/Nmi33sWH7bhqbwpzu7GNJnl1URWR6LCorork7yosnOlhdXUpFcYDLQpU8d6w96bi9xzu5eFkZKxeW4PcZR0YF0ABlxV7JlytWVPLolo0KnkVEpui6NQuHf/7nP7o27XW1uTuaVwXEILsA+mfABWZ2SfzzLrwA9E/M7Akz+z5ei6tCvLZRWXHO3QN8DW9N8h4z+5GZ7QReAS4FGoEvj/raIqAWWJnifM8BHwSKgZ+a2eNmdg/wMvAhoAO43TmnKiIiMyxdu4Ojbb0sqVABMREZa3F5EW09/bwQ7uTSmgoALg9V8uLxTgaGvGfpzjn2Hu9g3fJKAn4fNVXFKQPoRFp3Z9/gufsLiIjksa4R19NDLWOvuwktXf0szrMAOpsq3N/GC7hLAJxzUTP7LbwZ3GviL4AfAX87mcE4595nZo/gtcW6AfDjrWf+JvC1kbPPEzzf35vZHuBO4HrgKuAEXnXtbc65Q5MZp4hkJ127A0Az0CKS0qKyIoZijnB7hN+73ntOfvl5VUQfOcjLp7pYV1PJiY4+zvQOsC7kBdirFpamDKAPtXplUbr6Bs7dX0BEJI91jrieHo5fYxubwuzYtZ/j7RFqqoLc+eaLvTXQeXavN+EA2jl3BPibUdt+aWZr8NYTLwT2OecmUuQr05/zHeA7Ezz2LuCucY55EHhwKmMSkanJ1C5GLaxEJJWRa+YuXe4FyKc6vArbv/GlR6gKBhiMec/Vv3T/K1QUBzhvYQm79p5MOk//YIzwmQhmmoEWEZkuiQeSPoNDrb3D2YaJCZJwe4StjXsYjLl5PQOdUjwFetc0jEVE8lRNVZBwmiB6qYqIiUgK+052Dv+85ft7eNOlS/j+02ebgbRHzs5+tHT3s3XnHm6+ZAltPf109Q1QXuy1TDl2ppeYg/MXl3KguYfo4BBFBf5z9xcREclDnRHvgeQFi8s43NrDwy83j8k27BvwHnLO5yJiIiKTsrm+lqKC5MtNod9rZ6AZaBEZrbEpzD88dGD488nOPr79+BEiA+lXckUGhnj01RYAjradfWCXWP+8PuT1j+7SLLSIyJR19Q3gM7i0poLDrb0Zsw3nTRExM1s5lde5/EuISG5rqAvx+7+2avhzwG+880qvWqPaWInIaDt27Sc6mBwsuwl8r73Xm5UeuQ46sf45EUB3RrQOWkRkqjr7BikrKmDNolKOd0RYXpl+QiTfZqAzpXAfYmK/r1Jx45xbROaZBaWFALz319fwjUcOEvD78BlUx7eLiCRkmsnIZFllMSc6+pJ6QR9u7aWsqIDV1aWAZqBFRKZDZ2SAimCA1dWlOAd/8PpV/J+fvZL08LPAZ3m5BjpTCveRKbyOztyQRSTXper5vO9EF6GqIO+6MoRz8OPnjlNdVkSBXytJRCRZTVUw5XbL8J1gwM9H3rqWymBgzAz0quoSKoLemmgF0CIiU9fZN0h5cYBV1SUAXLC4nIYra5KOGYx5c7G3fOlhGpvC53yMMyXtnatzbrVzbs1kX+fyLyEiuSNdz+cnDraydlk562oqqCj20xUdpLkrOhxgi4gkbK6vJRhILvQVDPj5vetXEqoKYkBVMMCCkgAGhKqCbNu0HoDe/kH+9fHDw9eWw629rK4upbzYS4xTKysRkanr7Bugovhsds+h1h56+odYWlHE3/7WFfhGPPEMt/exdeeevLnfU5q1iEyrdD2fIwND3HZ1OT949jg9/WfTexIBNnhrpUVEEteCkf1EN9fXZrxGJB7eDQx5Mx7h9ghbdj5PdCDG2y5bNhxAdyqAFhGZsq6+QUJVQapKAlQUF3CwpYfHXmvlxtrFfP6nLxMbtRA4MjDEjl378+JeTwG0iEyrTGsXa5dV8Nn/2sfQqKtqPl1URWR6NNSFsrompHp4l2ih4s1AK4VbRGS6dEYGuGR5OWbG6kWl/OzFU7T19POGCxdx7zOpZ5onW98i1yiAFpFplann8yXLytNePPPloioisyPTNeRzu/YR8Blm3ro9ERGZmq6+ASriDyb9ZpzuigLwuZ/sp6okwJnesdk+6epbzDUTrt5jZkNZvPTbSWSe2lxfi9+XXOqnwGf4DdYsKk178cyXi6qIzI5M15CW7n4+2vgChT7TGmgRkSmKxRxd0UEqigtobAqzJ9wxvO9kZx/dfYME/Mn3gsGAn831ted6qDMim/K3lsVLZXVF5qmGuhA1VcXDF86SQj8XLCmjdlkFBX5f2uJA+XJRFZHZkeraMlJkYIjBmFMKt4jIFPX0D+IcVAQD7Ni1f7jadsJAzFFaWDBc9DFR6DFflupNOIXbOZcyKDYzA1YBvwF8EviKc+4T0zM8EZlr+gdjnOqI8p4Na2jujvKzvado6YpyQ+1iYHLFgURExjPy2pJuGcmQ89btiYjI5CWWwpQXF6RdPtMRGeDZT7zlXA7rnJnyGmjnnAMOAV8xs+eAB8zsJefcv0/13CIy97x8qov+oRjrV1Ty0olOuqKDEIWfv3iKxqbwcGEgBcwiMt0S15YN23enDKIL/T7NQIuITFFiKUxFcSBt7Zt8Xpo3ranWzrlHgGeAD07neUVk7njuWDsApzr7+OYjB4e3d/YN5lUPQBHJXemWily4pJSuqGagRUSmojOSmIEOzMuleTOxVvkwsG4Gzisic8DzRztYUBLgm48cJDIQS9qXaFclIjKTGupCbNu0fsz6u4uWlmsGWkRkihJLYSqCBWmvt/mcaTgTbazWAbFxjxKRvPR8uIP1K6r4xcvNKferXZWInAuploo8dbhNAbSIyBQlMnnK422s5tvSvGmbgTazajP7CrAW+NV0nVdE5o5I/xAvn+riihWValclIjmnvDhAZ2QAr3yLiIhMRiKFu6J4JuZic9+E/9ZmdiDD7jKgGq+FVT9w19SGJSJz0YsnOhmKOdaHKrlgcRlbd+4hMjA0vD/f18SISG4rLy5gMOboG4gRLEzf8kpERNJLFBFLzEDPN9nMQK/O8FoEDAD3Azc55x6brgGKyNzQ2BTmPf/yBAAf/8FegHm3JkZEcltF/GYvcfMnIiLZ6+wbpDjgo7BgJspp5b5s5t3XZNjXDzQ757SwSGQeamwKJ802n+zsY+vOPWzbtJ5Ht2yc5dGJiHjK4+mGnX2DLKmY5cGIiMxRXX0D83b2GbIIoJ1zh2dyICIyd+3YtT8pVRvOVtzWjLOI5ArNQIuIZKexKcyOXfs53h6hpirI5vpaOiOD83b9M8xMFW4RmWfSVdZWxW0RySUjZ6BFRCSz0RmG4fYIW3fuYeXCIBVBzUBPmJkVArcBNwIrAAccBx4Evu+ci07j+ERkDqipChJOESyr4raI5JJyzUCLiExYugzDAy09/NoFi2ZpVLMvq5XfZvZ64GXg34D3Am8DbgH+BPhX4GUze8N0D1JEctsHNl44ZpsqbotIrqkIevMG6gUtIjK+dJmEA0NOKdwTYWbrgJ8CJcAB4LvAofju1cBvAxcCPzGz1znn9k7rSEUkZ/nMAFhUVkRrd3R4jYzWP4tILtEMtIjIxKXLMPTZ/G1hBdmlcH8KL3jeBvyVcy42cqeZfSJ+zEeBTwK/OV2DFJHclCgsEW6PUOAzPnbLWm69asVsD0tEJKXSQj8+0wy0iMhEbK6v5c67n2Mw5oa3BQN++geHhjN65qNsUrhvAPY75z42OngGcM7FnHP/G9iPtz5aRPJYorBE4snkYMzx0XtfoLEpPMsjExFJzcwoKyqgM6IZaBGR8bzjihrKivwUxfs9+8341LvWMeTOdjWYj7IJoIPAMxM47hmgeHLDEZG5IlPrKhGRXFVeHNAMtIjIOBqbwlz3Nz+nPTJISaGfd1y+nCHnqFtZBaA10BO0H1g+geOWA69MbjgiMleodZWIzEUVwYDaWImIZDC6fdWZ3gF27T0FwC8PtAHzew10NjPQ/xd4o5ltSHdAfN8bgX+Y6sBEJDc1NoXZsH03Ls1+ta4SkVxWXlygImIiIhmkyjLsH/JW8D5+oBVgXq+BnvDf3Dn3dTNbi1dl+6vAt4GD8d2rgd8D3gd80Tn3f6d7oCIy+0Y/kRxNratEJNdVFBdwvL1vuAji8faIOgeIiIyQKZvwV5qBzqqN1cg75jvjr1Q+aGYfHLXNOefm72MKkTyR6olkQkg3oCIyB5QXBzjRcSbpYWC4PcLWnXsAdA0TkXkvXfuq4gIfLd1RQEXEJsqm8MrmzxGRHJXuiaQBj27ZqBtPEcl55cUFtEcGVARRRCSNOzZeMGZbMODnhosXDX8un8dFxCYc2DrnfFN5zeRfQkTOjXTrm7XuWUTmioriAC5NEYdwe4QN23erHZ+IzGuFfj8Ai8uKMLwsw22b1nPrVecNH1MRnL8z0PP30YGIZG1zfS0f+f7zRAfPtoLXumcRmUvGmzVJpHM/dbiNB/Y1a420iMw7/7nnBKGqII985CbMbHj7Pz1yYPjn+r99iM31a+fldVEzwyIyYQ11Id5xRQ1A0hPJ+XjxFJG5p7EpzNcefG3c4yIDQ3z78SOE2yM4zgbVmpkWkXzW2BTm17bdz+59p+mIDPCDZ48n7fv8iGUu4fa+eXtdzHoG2swCwG8CNwKJu+Yw8CBwj3NOvSFE5rDxKtO2dkdZVV3Cg3femPRUUkQkl43XRWC00VneiTXSemAoIvlg9P3eTWsX8/2nw8PXyO7oYFJxRa+QbCzpHPP1uphVAG1mVwN3A6vwJqBG+hPg02Z2u3PumWkan4icQ6NvMEdXpo30D/HYa628+3UrFTyLyJySrouA34yhdIuiR8nU2kVEZK5Idb/37cePZHxwmO76Nx+vi9m0sVoB7AIWAkfx+kC/hhdIrwHeHX/fZWZXOufm33y+yByX6gZzZGXav/7xi0QHY/zw2eNcsaJq3j1xFJG5K91N3pBzBAP+pGufMXYGGlQwUUTyQ6r7vXSPERPXznStrebjdTGbNdBb8ILnLwEXOuc+6pz7J+fcN5xzHwMuAr4IVMePFZE5Jt0NZmImurWnH4DWnv55u+5FROamdDd5iVoOC0u8irKLy4v4vetXEgz4xxyrKt0ikg+ymTVOXDs319eOuS7O10Ky2QTQbwUOAB9Ktc7ZOTcI/GX8mFumZ3giMpMam8Js2L6bNVvuY8P23VSVpG5J4DdTz1QRmdMy3fw11IX4tz+5HoC73rGOTzes5zO3XjZmrRqooJiIzH0TnTUeGSA31IXYtmk9oargvC8km80a6BBwr3PpFwo552Jm9gRw65RHJiIzKtX6l4DP8PuModjZf+ajUxtHmo/rXkRkbkrc5KUrkriqugSAQ609ALzhosU4oDJYQEdkMOlc87Vwjojkh831tdx593MMjrjfKw746BuIUVZUQE90MGUh2Ya6kK57ZBdAR/BSuMezIH6siOSwVOtfBmKOgA9ieGthKooL+NS7LmPHrv1a9yIic16mm7/SogIWlxdxOB5AH2zx3kcHzwl6gCgic1VDXYh/e/wQzxxpJ+aguMDHrXUhvvvEUb79J6/jivOqZnuIOS2bFO7ngRvNbG26A8ysFrgpfqyI5LB0N38DMXj367z1f791zXk01IXYXF9LoT/5cjFf172ISP5aXV3CodZeAA62dAOwtKIo5bF6gCgic1mB38dVKxewce1i+gZjfPeJo/h9xoHm7tkeWs7LJoD+J6AQ2G1m7zGzwsQOMwuY2R8B9wMB4B+nd5giMt0y3fzt2nuS0kIfJzv7gMSsTQ3AvF/3IiL5a1V16fAM9IGWHgJ+4yP1a1U4R0TmrNH1bhL1G0529DEYi/Hoq63Dxw7FHB+99wXVeBjHhFO4nXP/amZvBX4XL0D+BzM7gZfpWYMXjBvwHefct2disCIyfTbX17Jl5/P0DcTG7Gvp7sdn8OLxzuFtyyqK8Rns//TbCPizefYmIjI3rK4u4Z6no/T2D3KwuYdV1aVsunoFPp/xqR/tpa13gMXlRXzslkv0AFFEcl6qejdbd+7BOceJjj5auvuJDibfB6rGw/iyWQONc+73zOxRvGrba4AVI3YfAP6Pc+6r0zg+EZkhDXUhTnRE+OxPUlfSjjk43NY7/PlERx+Ly4sUPItI3lpVXQrAkbZeDrb0sGaR97mhLsTK6hI2ffUxPnfb5dy0dslsDlNEZFhjUzhtccRU9W4iA0N8btd+ooOxMcFzgmo8ZJZVAA0QD5C/amYhvMrcBhxzzmmuX2SOuWJF5iIRQzGHcw4z40RHH8srteZPRPLX6ngAfaC5h8OtvWwcESgvrSgG4FR8aYuIyGxLN8MM3oO/dIHwyQ7vOrawNEBbz5juxKrxMI5JTyU558LOuSecc79S8CwyNzV3RwFYUp66SA5AZ7wC7YmOCMsri8/JuEREZsPKeCurx15roX8oNjwDDbC4zLtOnlQALSI5It0M845dXnZhukB4QalXyuoPXr9aNR4mYdwA2sw2mtnXzOw/zexeM/tEfPZZROa4lu5+AD74povGXEADfgPgVFff8FoZzUCLSD6rDAZYWFrIA/uaAZIC6MICH4vKCjnVGZ2t4YmIJEk3w5zYvrm+luKCsV1UNtYuBuB3r13Jtk3rCVUFVSQ2CxlTuM3sS8AdiY/x93cCHzazdznnHpzBsYnIDGvpjlLgM373upWUFBYkraHZdFWIv9/9Kic7+lhaUUxv/5BmoEUk762qLqHpSDsAaxaXJu1bUl7Mac1Ai0iOqKkKEk4RRCdmnhvqQrx4ooOvP3wQgMpgAZ9852W8fKqLAp9RXVYU77SigDkbaQNoM3sX8P74x18ATwEVwFuA84DvmNka55wexYrkuHQFJlq7o1SXFWJmYy6gh1t7+Pvdr3Kqs294rczyKgXQIpLfVleX0nSknbKiguG07YSlFUWc6lIALSK5YXN9LZvveY6BITe8bXQK9sJS7zpWUujnlvU1NNSF+PD3nmVpRTF+n405p4wvUwr3e/FaVH3AOXeDc+4vnXPvBS4BHgKWAu84B2MUkSlIFJgIt0dwnC0w0dgUpqW7n0Vlqdc/JwrmnO6KcrzDe7qpGWgRyXeRfq/uQ3d0kDd89oGkfqhLK4o52aF5AxHJDQ11Ia5bvXD489KKojEp2PtOdFJTWcxlNZW8eroLgOOqazMlmQLoq4F9zrmvjNzonOsFtuCldF89g2MTkWmQqcBES3c0bQBdHPBTGQxwu7/uBgAAIABJREFUsmPEDLTWQItIHmtsCnP/vtPDn0c+cAQvgG7tiTIwlLr1i4jIudYeGaCsyEsq/vztV4xJx953sovaZeVcuLSMl09145zjZEcfy1Vpe9IyBdDVwJ40+56Pvy9Ms19EckSmAhMtXekDaIinK3b2caI9gs8yV+sWEZnrduzan5QKCckVbZdWFOOcVz9CRGS29fYPsu9kF29ZtxSAY2eS7/n6B2O81tzN2uUVXLykjI7IAKe7ovHCsJqBnqxMAXQB0Jtqh3Mu8V8nMO0jEpFpla6FQU1VMS09/SwqK0z73aUVxZyKX2iXlBdT4J905zsRkZw3XkXbpRXxVlYdWgctIrPvuaMdDMUct1y2nAKfcbQtOXQ70NLNwJBj7bJyLl5aDsCvDrYRHYwpgJ4C3Q2L5LnN9bUpe/y9f+OF9A/GxpmB9irOnujoY5kutCKS59I/cPS2J2pDqJWViOSCZ46cAeDqVQuoqQpydNQM9P6T3prntcsquCgeQD/8stemTwH05GVsYwVcaWYfn8x+59ynJj8sEZkuDXUhnHN8+D+ewwHFBT62bVrP5SsqAVhUnmkGuojTXVGKA37WLis/RyMWEZkdm+tr2bpzT1LdiJEVbc8WV9QMtIjMvqYjZzh/USkLSgtZsSDIsTPJM9Avnegi4DfOX1xKgc+oKgkMB9DLVNdm0sYLoK+Iv9K5MsV+w6verQBaJEdcs3ohDjCDFQtLaKgL8cTBNoBxZ6CHYo5DrT3cVLvkHI1WRGR2JIrvpGr7B1BdWkiBz5TCLSKzymtPuo9wex/BgJ/GpjDnLShJKoIIsP9kJxcsLiMQX4J38ZJynjjk3f/VaAZ60jIF0P/vnI1CRGbU3uOdAFy7eiHPHmlnKOaGi+BUl2YOoAGcU6qPiMwPDXWhMVVsE3w+Y0l5kVK4RWTWJNqTJjJlIgNDbN25h5tqF9PSHaVvYIifvHCSHbv2E26PDAfYDXUhLlpaxhOH2ijwGdUZJlAks7QBtHPuj87lQERk5rx4ohOfQf26ZTxxsI2TnX20xgPozCncZ4Pm5VUKoEVEllQUK4VbRGZNuvakvzzQCsD/e+wgf/fzV8cE2ImfAQZjjjd+7oGkDBuZuPFSuEUkD7x4vIPzF5dxSXwd8+GWHpq7+zGDhSWZ10AnaAZaRMS7Lh5o7pntYYjIPJWuW0B77wAAX3/4YMoA+64f7qW3/+z2RJ97QEF0llSFW2Qe2Hu8k3U1FaxaVArAodZeWrqjLCwpzNia6pevtgz//L5vP0NjU3jGxyoiksuWVhRzqlMz0CIyO9J1C0hkDbb29Kfc3x4ZoH8olrRtZJ97mTgF0CJ5rq2nnxMdfayrqWB5RTGFBT4Ot/bQ0hXNWECssSnMxxr3Dn8+1Rll6849CqJFZF5bWlFMZ98gkf6h8Q8WEZlm6dqTfqS+lsICH2VF2SUYp5vRlvQUQIvkub3HOwBYV1OJz2esXFjCodYeWnv6qS5Ln76dbo2NnlSKyHymVlYiMpsa6kJ85tbLsPjnUFWQbZvWc+vVK1hRFeSCxSUUFSSHeMGAnwUlgZTnSzejLenlXABtZu82s1+YWYeZdZvZU2Z2h5lNeaxm9qdm5uKvL0/HeEVyWWNTmDu+/QwAd979HI1NYVZXl3A4nsKdaQY63RNJPakUkfns1dNdANy440E2bN89JiunsSnMhu27WbPlvpT7RUSm6tcvXowDPvGOS3l0y8bhNcwrFpYQc8bNa73Wo8bZAPsT71iXcuY60edeJi6nioiZ2VeA9wF9wP3AAHAz8GXgZjO73Tk3qZwpM1sFfB6vR7WNc7jInDe6zcGJjj627tzDdWsWcKi1B79ZxgC6pipIOEWwrCeVIjJfNTaF+edHDwHezcToIjyjr7sq0iMiM+Fway8Aq6pLkravWBBkz7F2BoZiXLt6AXf/2evHfDddn3uZuJwJoM3sNrzg+STwRufcK/HtS4EHgFuB9wNfnMS5DfgnvBn3bwF/ME3DFslZ6VKwnz3aQd+AV0QiUwurzfW1STeCoCeVIjK/7di1n+jg2CI8d/1w73DP1dESS190kyoi0+VomxdAr1yYHEB3RgY40+u9KoMFw/2fEzL1uZeJy6UU7q3x948kgmcA59wp4H/GP26ZZCr3n+HNZG8FDk1lkCJzRbpU647IwPDPi0rTz0A31IXYtmk9oapgUgqQLrwiMl+lbR8TGUgZPI/3PRGRyTgSD6BXLDgbQDc2hdm19+Tw547IoIq/zpAJz0Cb2W7gJ865z41z3J3ALc65jVmcewVwNdAP3D16v3PuITMLAyHgeuCxLM69Bvgc8CheKvgnJvpdkbksXQr20ooiTnVGgcwz0KAnlSIiI6W7rk7keyIi0+VIWy9LK4ooHrGmeceu/QwMuaTjlAEzM7KZzb0RWDuB42qBG7IcR138fa9zLt1vpidHHTuueOr2N/EeFPyxc86N8xWRvLG5vpYCX/Jy/2DAz5vihSUAPvJ9PZkUEZmoVO1jxqOlLyIy3Y609Y5J31bx13NnJlK4i4BsC32tib8fznDMkVHHTsT78QL/u5xz6r0j80pDXYhQVTGFft9wCvZtV4fY2XR8+JjmLvV2FhGZqMTSlkQQHaoKpm0NA1Do92npi4hMu6NtvaxcWJq0LV2mizJgpt+0BtDx9clXAy1ZfrUs/t6T4Zju+Hv5BMdyAbANeBqv+nZW4i2vnjKzp5qbm7P9usisi/QPEW7v449/fQ0Ht/8Gj27ZyAP7mtXbWURkChrqQvzxG9bg9xkPbb4xbWuYt65bxkAsxq9dUD1LIxWRfNQ3MMTJzr4xM9CpMmSUATMzMq6Bjq97HumtKbaNPNeFwFLgP7IcRyLPdFpSrEekbhcC75lM6yvn3NeBrwNcc801Sv2WOafpyBkGY47r1iwc3qb0HhGRqVteVcxQzNHcHR2eXf7wfzxLzHmz0pvra7ksVMFP9p7kv/ac4A83ZJM8JyKS3rEzEZyDldXJM8uJa5HaVM288YqI3TjiZwcsi78yaQI+kuU4uuLvZRmOSezrynBMwp8DbwQ+5Zx7PsuxiOSFXx1sw2dw9aoFw9vU21lEZOqWVxYDcKKjj+WVQd6ybikx580A3XHThcPHLaso4jP/uY9P/uhF3cyKyLRI18IKVPz1XBkvgL4p/m7AbuAnwGfTHNsPhJ1zR9Lsz+RQ/H1VhmPOG3VsJrfG399sZqMLmq1OHGNmlwHdzrm3T+CcInPKrw62cmlNBRXFZ9fnqbeziMjULa/0Hjqe7OgDIHzGezC5YsHZh5GNTWFauvsZjHlJbOH2CFt37gHQDa6ITFqihdV5KQJoOTcyBtDOuYcSP5vZQ8CDI7dNo6b4+zozC6apxH3tqGMn4tcy7KuJvzqyOJ/IrGtsCo9Jz4HklJ0Pvekimo6089+uT34mpfQeEZGpS8xAJ5a/HIu/h0Zk8+zYtX84eE5QSxkRmaojbb0EA34WlxXN9lDmrQn3gXbO3TT+UZPjnDtqZs8AVwG3A98auT8+i7wCOAn8cgLnuzHdPjO7C68X9Fecc++f/KhFzr3GpnDSDHK4PcLmu58DY7j3X7g9wp33eCsX7m0Ksz5UmXSzpvQeEZGpqQwGCAb8Y2agQyNmoFVzQkRmQqKFlVfySWbDTLSxmqxt8ffPmtnwAiIzWwJ8Nf5xu3MuNmLf+81sn5klBdwi+WrHrv1jqmgPxNxw8DxaW0+/2lSJiEwzM2N5ZTEnEgF0e4QCn7GkvHj4GLWUEZGZcKS1V+nbsyztDLSZfTz+45edc20jPk+Ec879dTYDcc7dY2ZfA/4nsMfMfg4MADcDFUAj8OVRX1sE1OLNTIvkvcnMXChlUERk+i2vKuZEh3dNDp+JsLyqGL/v7IyQak6IyHS795ljvHyqi/2nutiwfbeW4c2STCncd+FV3v53oG3E50z5Aon9DsgqgAZwzr3PzB4B7gBuAPzAPryWVF8bOfssMh+lq6I9HqUMiohMr2UVQR57rQXwZqBXVCXPCCVuaj9934u0dPdTXVrIX739Ut3sisikJJbxJXIOVZhw9mQKoD+FFwi3jPo8o5xz3wG+M8Fj78IL7LM5f9bfEckVm+tr+V/ff57+weyeJSllUERketVUFXO6K8rgUIzwmQhvuGjRmGMa6kK8Zd1S1t/1U37nuvN0kysik7Zj1376Rt3/KctwdqQNoOOBZtrPInLuNdSF+OWBFr735LEJf0cpgyIi029ZZTFDMceJjj5OdfUlVeAeqaSwgEuWl/PM4fZzPEIRyScqTJg7cqmImIhMwKKyIgp8Rk1Vccr9VcEAoaoghtdSZdum9XoyKSIyzRKtrJ45cgbnkitwj3bVygU8d6ydwaHk2aPGpjAbtu9mzZb72LB9two+ikhaKkyYOybcxmo0M/MB1Xhp3W1anyxybhxpixBaEORDb7o4ZYGau965TgGziMgMW17p3bQ+degMACsy3MRetXIB3/rlYfaf6uKVU93s2LWfcHtkuGgMaD2jiGT2gY0XsiV+jUhQluHsyHoG2szeama7gC686tengC4z22Vmt0z3AEUk2ZHWHlYuLKGhLsS2Tes12ywiMgsSM9BPHmoDxp+BBvjnRw+xdeee4WKQowvLJNYzioiMtri8CIBFZYW675tlWc1Am9nfAR/gbCXuxKxzEHgz8CYz+4pz7s+nb4giMtKRtl7etn454M1S6MIpInLuVQYDBAN+9p/qwuzsjHQqTx9uw2dwz9Pj16/QekYRSeWRV1soDvh45CMbKQ74Z3s489qEZ6DN7A+BPwe68SpyX4QXOAfjP38Sb1b6DjP7o2kfqYjQ2TfAmd4BVi4sGf9gERGZMWbG8spinIMl5UUUFqS+pWpsCvPRe18gNsE+JlrPKCKpPPJKC9euXqjgOQdkk8L9fmAQeJNz7i7n3GvOuYH46zXn3CfxZqGHgPfNxGBF5rujbb0ACqBFRHLA8ngxx3QVuMFrPTOyVkUmWs8oIqmc6uzjldPdvOHCse3y5NzLJoC+BHjIOfdkugPi+x4CLp3qwERkLAXQIiK5Y1mFFziHFqS/Jk80Jbu6tFDrGUVkjMamMG/9u4cB+MYjB1WtPwdkE0D3AqcncFwzoAU8IjPgcGs8gK5WAC0iMpsam8L8dO9JAB7YdzrtTW2mlOxQVZDP3HoZAO95wxoFzyKSpLEpzNadezjTOwBAc1eUrTv3KIieZdkE0I8C15qZpTsgvu+a+LEiMs2OtPVSVRKgojgw20MREZm3Eje1XdFBALqjg2lvajfX1xIctWYxGPDzd799JY9u2ci7X7eKFQuCvHi885yMXUTmjlRLQFStf/ZlE0B/AlgBfMHMxty9m1kB8Pn4MZ+YnuGJyEhH2nqVvi0iMsuyuamdSMvBdTUVvHhCAbSIJEu3BETV+mdX2jZWZvb7KTb/C/AXwO1mdjdwML59NXA7EAL+L3A58Ox0DlREvDXQ60KVsz0MEZF5Ldub2vFaDq6rqWTX3lN0RwcpK8qqw6iI5LGaquBw3/jR22X2ZLpK/wuQqumC4QXKf5FiO8CfxV/fmurgROSsoZjj2JnIcA9oERGZHdN9U7uupgKAl050cu3qhVMam4jkj831tdx593MMjuiDp2r9sy9TAP0tUgfQIjILjrdHGIw5VimFW0RkVm2ur2Xrzj1JadxTualdV+NlFu0NdyiAFplnGpvC7Ni1n+PtEWqqgmyurx3OWGmoC/G1B1/lQEsPg0NuzH6ZHWkDaOfcH57DcYhIBo1NYT5934sAfP6n+ykO+HXxFBGZJYnrb7qb3mwtrShiYWkhe1VITGReSRQkTDyMC7dH2LpzD+BdZ5xznOyM8ptXr2Dbpstnc6gyghbaiOS40RfXlu7+pIuriIice+Ota86GmbG4rJB7m8Lc8/QxzTKJzBOZChI21IU43NpLR2SAy1dUzdIIJZVsqnCLyCxQCwMRkfzW2BTmteYeBmMOx9lZKPV6Fclv6QoPhtsjNDaFeT7cAcB6FZDNKROegU5TlTst55yKiIlMA7UwEBHJbzt27U8qEgTJs1Aikp/SFSQE2LpzD69bs4CiAh+1y8rP8cgkk2xSuP+FiRUVs/hxCqBFpoFaGIiI5Dc9KBWZn+5888V86O7nUu6LDAzx2GttrAtVEPAraTiXZBNAp6vK7QNWAVcBpUAj0DH1oYkIeNVeP/L954kOxoa3qYWBiEj+0INSkfnpwqWZZ5b7h2JcrvTtnDPhAHq8qtxmtgQvyL4QeP3UhiUiCQ11IX7+0kl+/PxJDFRcRkQkz0x3WywRmRvu33cKM1hWUcyJjr6Ux/zwuePUrVyg+74cMm1VuJ1zp83s3cArwF3AndN1bpH5rjs6xEVLyvjZh2+Y7aGIiMg0S9wY/819L9HcHWVBSYBPvGOdbphF5qhMvZ1H2r3vNFetXMB/v37VmIdoCWd6B9R9JcdMa0K9c64NeBK4bTrPKzKfNDaF2bB9N2u23MeG7bvZ+fQxnjp0huvWLJztoYmIyAxpqAvxq4/eTHVpIb9+0WLdKIvMUYn2o+H2SNqq+o1NYa7/zP08f6yDV051AbBt03pCaZZtqPtKbpmJFen9wPIZOK9I3kt50b13D93RQQXQIiJ5zuczblq7hAf3n2ZwKDb+F0Qk54zXfjRxr3ey00vZ7uwbHJ5hfnTLRizNeVVUMHdMawBtZsuADUDzdJ5XZL5IddFNFA9TAC0ikv/Ki/x09g1y0cf+iw3bd6sXtMgck6m384btu/nkj/ZmDLDTFQ9UUcHckU0f6Ddm2F0GrAXuAKqA705xXCJ5K9O6mExPF391oE0pfSIieayxKcx3nzwKkJT6CVr7KDJXZOrtnG47nL0HVFHB3JdNEbEHGb8PtAFNwP+e7IBE8lkibSdxURx9c5TpoqubKBGR/LZj1376BpJTtxMzU7r2i8wNqdqPTkRihjnxb30iRchkdmQTQD9M+gC6HwgD9wP/4ZwbmOrARPJRpnUxDXUhNtfXsvme5xgYGvtPTTdRIiL5LV0WktY+iswdDXUhDrR086X7X53wd0bPMDfUhXS/l8Oy6QN94wyOQ2ReyLQuprEpTENdiJ+8cIKf7D2V1fdFRGTuS5eFpLWPInPLuppKABaXF9HcFc14bEgzzHPOTFThFpE0Mt0EJVocBAsL8FvqGoy6iRIRyV+b62sJBvxjtieKD6mgmMjc0NbTD8AdN12Q8t90guFV3lbwPLdkHUCbp9rMlppZYCYGJZKvNtfXEvCnDo4TKdqHWns4f3HJmAuuCkiIiOS3hrpQ2l6wqXrJikhuSgTQv3PtSrZtWq+JkTwzoQDazBaa2V+Z2ZNAFDgNHAd6zWyPmX3azNT7WWQcDXUh3nVl+qeMx9sjHG7t5ZrVC4dvogwvvWfbpvV6Qikikuca6kI8umVjyiB6ZKsbEcldrd39lBb6KQ74aagL8YXfukITI3lk3DXQZnYr8E9AJYzp7e0H1gGXAn9hZn/unPvnEd814ErnXNP0DVlkblu1sCTtvmWVxZzo6GNVdakKSIiIzGMqKCYyd53p7WdhWeHwZ1XWzi8ZA2gzux2vp7MP2AN8C3gSOIUXTC8BrgN+H7gM+IaZFTjn/jGe3v1t4AW81lYiApzpHaDQb/h9vjE9/t593Uq+8LOXWV2dPsgWEZH8p4JiInNXa08/C0sKk7ZpYiR/pE3hNrPFeDPPAH/hnLvCOfcF59zDzrn9zrl98Z8/75y7HPgQXpurL5rZWuAHwG2M3ztaJG80NoXZsH03a7bcl7bgy5nefpZUFCetcwv4jW2b1rN6USkAq6pLz+m4RUQkt6QqKBYM+JTyKTIHtPVEWVhaOP6BMidlWgP9AaAM+Khz7u/HO5Fz7ovAx4Bi4CngrcCrwDenYZwiOa+xKczWnXsIt0dwpC/4cqa3nwUlhcPr3P7HG8/HMG5Zv5zDrT0ArNIMtIjIvJaqoJjf5+ND33tWFblFctyZngEWlhbN9jBkhmQKoN8GtAJfyOJ8XwDagBJgL/BG55yu8DIv7Ni1PyklG1IXfDnT08+CEU8l16+opH8oxv6TXRxq7WVJeRElhRNu0S4iInkq8aB1x29eDkB3dDDjA1oROTfGyzhs7YlSXaYZ6HyV6S79fOBR59xQhmOSOOcGzewx4DeAG5xzbVMdoMhcMdGCL2d6B4ZTtQGuWFEFwHPH2jnc2sNqpW+LiMgIf/fzV8ZsiwwMcdcP96ookcg5lsg4TEyaJB5ogffQq7d/kL6BGAtKFEDnq0wz0KVA1yTO2QUMKniW+SZdYZfR28/09CddVFcsCLKgJMCeYx0cau1V+raIiCRJ94C2PTIw7rIhEZle42UctnZ7PaCrtQY6b2UKoFuA1ZM45yqgeVKjEZnDUhV8KR5V8GVgKEZXdDApgDYz1q+o4vGDrTR3RZNmp0VERCZaeVt9okVm3ngZh2d6vQBaRcTyV6YA+mngOjNbOdGTmdkq4HXx74rMK4mCLwW+s+3Sb7s6uWXB2YtqIOm7l4cqOdzaC6iAmIiIJEv1gDYd9YkWmVnjZRy29nj3egsUQOetTAH09wA/8E0zG/f/gPgx34yf83vTMzyRueWdV9Tg9xnv2bCGZRXFnOroT9rf3jsAjL2oRvoHh3/+5I9eVAqeiIgMSzygXV5ZDEBZUQELSgIpj62pCk6opaKITM7m+loCfkvaFgz4hzMO25TCnfcyBdDfBZ4BbgIeMrOr0h1oZlcDDwM3As/Gvysy74TbI0QHY1y0tIzapWX8/KVTSTcwbYmnkiNSuBubwnz7V0eGPzd3RbWOTUREkjTUhfjl1pt548WLqS4r5ONvvxRf8j08xQEfN61dPKGWiiIyOQ11Id5y6dLhzwtLC9m2af1wxuFwtqGqcOettAG0c84BDcARvLTsJ83seTP7hpn9Tfz1DTN7AXgCuA44Crwr/l2Reee15m4ATnREePygV0dv5A3Mrr0ngOQAeseu/fQNxpLOo3VsIiKSyvLKIg639vKh/3iOmCMptdtvxr89fmRCLRVFZPKqSgopLy4gGPDzjsuXJy3Xa+3pJ+A3yovUkjRfZfwv65w7Fp95/ipwO3BZ/DUyQDYgBtwN3OGca52hsYrkvNeaewC4+6ljRFMExfc+cxyABSPWQE+0/ZWIiMxvjU1hfvDs8aRtDsfvXXce33niKD396TuP6neKyPQ53h5h5cISFpcX8cirLUn72rq9bitmlubbMteN+2jEOXcG+F0z+xjwduBqYHF8dwtewbAfO+dem7FRiswRr57uZkFJgJMdfSn3t0fia6BHzEDXVAUJp7ixmWjVVRERmR927NpP30Dyw9m+gRj//uQxxkv90+8UkelzoqOP8xaW8Lo1C/n0fS9xoiPC8sqzRcRUgTu/TTi3wDl3APjSDI5FZM57rbmbCxaXcaKjL2VQXFbkZygGxSNS7jbX17J1556klLuRxShEREQg/Szy0Dgr50b/TmlsCrNj136Ot0eoqQqyub42KQVVRDILt0e4/vzq4WzDX9u2m1D839KZ3n6qtf45ryk5X2QaHWju5k2XLOW/Xb8qZVB8ybIKjo+anU7ctOhmRkREMkmXseQ3yxhEj14DPfL3U6JGB6DfOyIT0Nk3QFffIG3dUb735NkisIl/S6VFfq4/v3oWRygzTQG0yDRp7+2npbufCxaXDd+EbP+vlzjZGaUyGOCT71zHD587TtXA2DVqDXUh3biIiEhG6TKWbrs6xPefDidtD/iMmHMMxePqxM19ccCXtsiYfg+JjO9EuzcR8otXW4gMjK130zcwpBZWeS5TGysRyUKigNgFS0oBLyh+bMvN3s3NVStoqAtxplfrYkREZHIS/aBDVUEMCFUF2bZpPZ9uWD9me1lxwXDwnBAZGOJM70DKc6vImMhZmXqpH+/w/q20p/m35ICFpUXnYpgySzQDLTJNEi2sLlhcNrzN5zNWLyrlYIu370xPPysWlMzK+EREZO5Ll7E0evuaLfdldV4VGRPxNDaFMy5zSDxsWlpRxMnOaMpzLBzRbUXyj2agRaZBY1OYT/3oRQB+9x8fT3pSef6iUg62eLPTZ3oHWFiii6qIiMysdAFxVXDs3IkKV4qctWPX/oy91I+3R/D7jP9VvzapDztAUYEXWmkGOr8pgBaZosSTyu7oIADH2/vYunPPcBC9ZlEpR89E6BsYoiMywAKlcIuIyAzbXF875ua+OODjnVd6s9S+eIvaRBq41j+LeNItZ0hsP97ex7KKYjZdvWJ46URC/aVLAbRcL88pgBaZovGeVK5ZVMpQzLEn3AEk94AWERGZCaPXSwO8/fIaDrb0EKoK8r4bL8Rn8MCdNyp4FhkhXfZGYvvx9shw0NxQF+LRLRt59uNvpsBnNB1rBxRA5zsF0CJTNN6TyjWLvaJiTx8+A6AZaBEROScSN/cHtt3CeQuC7HzmGL94pYXOvgHORKLEHBxp653tYYrklM31tcMZGgkjlzkc74iwvKo4aX9VSSEbLlzE0Tbv3k8BdH5TAC0yReM9qTx/kRdAP5MIoLUGWkREzqEfPHuck519xOJVubv6BrnnKW+ZUaJGh4h43nrZMgzwx4PoxeVFw8schmKOkx19Ke/9lleeDarf9ZVHkurhSH5RAC0yRZvrawn4kx9VjnxSWVVSyIKSAM8cSQTQeiopIiLnzo5d+xkY1dMqOuj1r010iRARz/PHOhhysG3T5ZjBu69bObzMoaU7ysCQGxNANzaFaXx2RKurUfVwJL8ogBaZooa6EG+4sBogqS9nUjuRRaW0dPcDSuEWEZFzK1OPZ81AiyR74mArAG9Zt5SrVi5g977Tw/sS/5ZCo1K4d+zaT99ALGnbyHo4kl/UB1pkGgzGYH2okh994A0p969ZVMYzR+KFJTQDLSIi51BNVZBwiiC60O/jQLMCaJGRfnWwjbXLyqkqKWTj2iXs2LWfU514ivZ3AAAgAElEQVR9LK0o5nh7HwDLK5NnoMerhyP5RTPQItNg38kuapeVp91/fryQWFGBj2ChP+1xIiIi0y1VS6tgwM+V51VqBlpkhMGhGE8fPsPr1iwEzrZ7e91n7mfD9t38dO9JYGz9m/Hq4Uh+UQAtMkWt3VGau6KszRBAr4kXElNVRhEROddGt7RKLDW6ce0STndF6Y4OzvYQRXLCC8c76e0f4ro11TQ2hfnS/a8M7wu3R/jBc8cBuOWLDyetb073kCpRD0fyi1K4RaZo/8kuANYuq0h7TOIJ/4mOPjZs383m+lr13RQRkXOmoS405vfOT144AcDB5h7Wr6icjWGJ5IzGpjAf/8ELAPz1j18kOjhEZNS65oRwvEgYJP/b2rFrP8fbI9RUBXWvl8cUQItM0UuJAHp56hnoxqYwf787+QnmyIuuiIjIbFizqAyAAy3dCqBlXmtsCrN15x4iA0MAnOzsG/c7iSJhiXu5VA+pJD8phVtkivaf7GRRWRGLyopS7ldlRhERyUWrqkswUyVukR279g8Hz9lQkbD5KecCaDN7t5n9wsw6zKzbzJ4yszvMbMJjNTOfmb3ezD4dP9cxM+s3s1Nm9p9m1jCTfweZX/ad7Mq4/lmVGUVEJBcVB/zUVAYVQMu81dgUZsP23Smr1E+EioTNTzmVwm1mXwHeB/QB9wMDwM3Al4Gbzex259xEHg+dDzwa/7kNeAp4JL79bcDbzOxfgPc459y0/iUkrzU2hZPWt/zlmy9m/8ku/vv1q9J+J137EF10RURkNjU2hWnpjvKDZ4/z1KEzWrMp88rotO1UqoIBSosKCLdHMGBk0KAiYfNXzsxAm9lteMHzSeBy59zbnXO3AhcBLwG3Au+f4OkcsBsvWF7inKt3zv2Oc+464EagB/jD+EtkQhIX2nB7BEd8LfO9e4gOxjK2sFJlRhERyTWJ32nRQW+JUaI+x8jKwiL5bLy07WDAz13vXMejWzZyaPtv8Le/feWYSvZ64DQ/Wa5MwJrZU8DVwB845741at8NwIN4wXXIOZe6JN7E/6z/Dfw1sNs5d/N4x19zzTXuqaeemsofKXkgU4rP4vIiPnbLJWkvpKNnrvWUX0REZlO632mhqiCPbtk4CyMSObfWbLmPdFFQSPdq85KZPe2cu2a843IihdvMVuAFz/3A3aP3O+ceMrMwEAKuBx6b4h/ZFH9fMcXzyDySac1yc1c0Y2VtVWYUEZFcovocMt+lW2Knh0gynlxJ4a6Lv+91zqW7cj856tipuCj+fmIaziV5JFFMYs2W+9iwfXdSKtt4a5ZVWVtEROaKdL/TVJ9D5ovN9bUE/Ja0TUvsZCJyYgYaWBN/P5zhmCOjjp0UMysB/jz+8ftTOZfkl9HFJEb2awboig6Mew49uRcRkblgc33tmAJKCh4kH0x02VxDXYjvPnGYJw6dAYeW2MmE5UoAXRZ/z9RHoTv+nr5a08R8FS8IfxH4+hTPJXkkVTGJyMAQd/1wL9HB2IT6A+rJvYiIzAWJIGHHrv3Daax/9fb0tTxE5oJMkyGp/t8+1RnlTZcs5R9/f9xlryLDciWFO5E/MaMVzczsr4A/ADqA33LORTMc+6fxHtRPNTc3z+SwJEekmz1ujwykDJ5t1Gc9uRcRkbmkoS7Eo1s28u9/ej0ASyuKgczLmURyWbrJkFRL7E519nGotZfXrVl4roYneSJXZqC74u9lGY5J7OvKcExaZvZh4FN4M9lvc87tzXS8c+7rxGeor7nmmtwoVS4zKl0xiXQcXqEJVdYWEZG57Mrzqij0+3jiYBtdfYNZzeCJ5JJsiuM9cbANgOsUQEuWciWAPhR/X5XhmPNGHTthZvYB4AtABHi7c+6X2Z5D8l+69WDFAR9neseuf1aVRhERyQfFAT9XnFfJrw628ePnT6SdwVMALbmssSmMz2AoxbSXw2vdNnKy44mDbZQW+rl0ecW5HajMebkSQCfaSq0zs2CaStzXjjp2QszsDuBLQB/wTufcQ5MfpuSzhroQsZjjw3c/B3gp2n/TsI4hB5vveT7pWKVri4hIPrluzUL+4aEDDMVSJ92pSKbkssTa51TBc0K4PcKHvvcsH/zes/jNGHKOogIfP37+hB4OSVZyYg20c+4o8AxQCNw+er+Z3YDXs/kkMOHZYzP7M+DLQBRocM79fFoGLHlrw0WLAHj9BdU4YNWiMhaXFwFQXVqI4c08b9u0XhdbERHJG4Mxx2DMpS1GoyKZkstSrX1OJfH/95DzfooOxti6c4/W+UtWciKAjtsWf/+smV2Y2GhmS/AqZwNsd87FRux7v5ntM7NvjT6Zmb03/r0osMk5t2vmhi75IvGE/barVmAGj77awgP7ThMM+Hl0y0YObv8NHt2yUcGziIjkjcam/9/emYfHUZz5/1OSRtLIsiXb+JTNZcCcDiZASEw4E8hJjENINmR3s7/dzUGy5NhAINmAQ3aXKyHZbK5N2NzJgrkMgRBIuIIJEA5jcxmMMT5kfFvyoVuq3x/dLc20unu6RyPNjPT9PE8/M9Nd1V3dVVNdb71HNfOLv7wemaa5pV0BxUTJMhQLibAgY0KEUSom3FhrbzHG/BD4NPCcMeZPQDdwJjABWIqjTc5kP2Aujma6H2PMscD/4FjhrgXON8acH3DZ7dbaLxX0RkRZs7m1A4AjZkzg6JkNLFu9nU2t7Sw4ZD9qU5VFLp0QQghReK6792U6uvtyposKKBZ37V0hhoOkgWD9yEVBJKFkBGgAa+2FxphlwGeAU4FKYBXwU+CHmdrnHDQysMrQ4e4WxDpAAvQoJ8lLfZMrQM9srGXq+BruX7UVgL0dPSxd3qzBgBBCiFFHEuEhKKBY0rV3hSg0Hztpf675Q7YWOVVhwEB3lGO0i1wURBJKSoAGsNb+FvhtzLSLgcUB+x9i8DK9YgyS9KW+ubWd2lQFD67ayiOrt/fvb2nv1mBACCHEqCSp9s4vcEetvat3phgJPAuK6RNq2bK7o19hAk77bG5px0Cgj78Cw4qklJwALUQhSfpS39TawcyGNN+87xW6evti5xNCCCHKlaTLOPq1dUnW3hViOPj9c29w4kGTWPLJtw465o3bPIvE5pb2/ijcTXI3EHkgAVqMaqJe6kGm3ZtbO5jeUMtja3YkOp8QQghRrnjCg/+dCAQK1n5tXZgGW2axYjjIHL81pFP0Wcvujh4a0qlId7uF85skKIuCIAFajGrCXuoN6VSgaXdNleGMI6ZpMCCEEGJMESVcLL7zBVrau5k6voavvOeIQekuPnsuX751JZ09A5ZbMosVw4HfNa+lfcBColXudmKEKKVlrIQoOBefPZe0L3p2OlWJMQSadre09zCzIR2aT4MBIYQQY4mF85u49cK3AfDFdx4WKJgsnN/EGYdP7f89rrqSqxYdIyFGFJxc6z1rSSoxEkiAFqOahfObuGrRMVS4IeXSKeel3hLg0+UxvaG2P19TYxoDNDWmNRgQQggxJjl4v3HsV1/NE2t3hqbZ1NrB/P0bOWLGBE46eLLel2JYiONKJ3c7MdzIhFuMKoL8mt9x5DT63LCLc6aOY+H8pv4gEkHMbKwF5CsjhBBCABhjOPGgSfw1RIDetqeTFRta+NJZh7FiYyvrduwb4RKKsUKciPFytxPDjTTQYtTg+cU0t7RjGfBr/sVfXgdg2oQa1mzdR1+f5eKz51JVkb3SWXWl83v6BHW8QgghRCZvOWgyzS3tbNzVlrV/6fJm3vnthwH45WPr6OruZeOudqzNvfauEEm5+Oy5VFeFiy9ytxMjgTTQYtQQtmTV/y5bC8Dpc6dy45Mb2Ly7g4Xzm7jhkdd4YdNuLNBYl+K0w6aw9NlN/RpoIYQQQjjs7ewB4ORrHqQxncIY2NXWnbW27tY9nexq66K717JzXxeT62uKVl4xOlk4v4k/vbSZu1ZuxuAEhTUGWtq6+y0PZT0ohhsJ0GLUEObzsnNfFwCnuQL0mm17mdmYZldbN++dN4O/rNnBGYdPpTGdojZVQUM6NZLFFkIIIUqapcub+d4Dq/t/Z0Y+9uuZu3udPRt2tUuAFsNCR7fl4P3G8cCXTit2UcQYRSbcYtQQ5vMyrrqSCbVVvPmAiQC8unUvu/Z10dzSztFNDZxw4ET+unYnb7R2MLMhjTEm8DxCCCHEWMSx8OrLnTADv6m3EIXAWsvy9buYv//EYhdFjGEkQItRQ5BfTDpVyexJdew/uY796quZUFvFmm17efGN3QAcNXMCJx40mfU723h2QwvTG2S+LYQQQmSST1TjDTsVCVkUnvU729ixr4vjDmgsdlHEGEYCtBg1LJzfxDnzZvT/bqxLcdWiY+jq6eOASeMwxjBnaj1rtu7jxU2eAN3AWw6aBDhBx2Y0KICYEEIIkUmSqMbpVCV1qQppoMWw8Mz6XQAcJw20KCISoMWoor42xbjqSsZVV3LOm2by/jfNZOOudmZPqgNgzpR61mzbywubWpnRUMukcdW8snkPntH2fS9sZuny5uLdgBBCCFFiXHz2XNKpytDj3ju0qTHNVYuOYc7U8WzYJQ20KDzPrGuhvqaKw6aNL3ZRxBhGQcTEqGLNtr3MmVpPbaqSlRtb2bK7g67ePvZ3BehDptZzy9Mb+evanRw1cwJLlzfz1aXP9wdB2dPZw2W3PQegKI5CCCEEA+/D6+59mU0t7TkjH9/34mZWbd5TrOKKUcjS5c1cd+/LNLe0U1NVwe9WbNI4TRQNCdBiVLFm617ecvBk9quv5hePrWPNtr0A/QL0nCn1AGxq7eC8N88KXfrquntfVscshBBCuCyc3xT7vThrYh1/emkrfX2WigoF5hRDY+nyZi677bn+8VpnT5+UHaKoyIRbjBr2dfawqbWDOVPGMW9WI109ffzpxS3AgAC9dvve/vS/fmI9zSGBUfIJmCKEEEIImD0xTVdPH9v3dha7KGIUEKXsEKIYSIAWo4bXtu0DHDPtebMaALj7uc1UVhhmNtaydHkz1//xlf70O/d1ETYvniRgihBCCCEGmDXRmbTeoEBiogCEKTWk7BDFQibcYtTgmWvPmVLP/pPqaEin2L63k/0n1VFVWcF1975Mh28dS4sT/MRm7EunKrn47LkjVm4hhBBiNDF7kjMJvXFXOxt2Nvf7Tgf5SwuRi5mN6UCLQSk7RLGQAC1GDWu27aWywrD/5DqMMUyfUENrezfrd7ax4OoHQs21LU7kUL3chRBCiKGzfH0LAJ+78dmsSermlnb5ro4hvMBfQx1fXXz23CwfaJCyQxQXCdBi1LBm2172n1RHTVUlS5c3s8Y16Qbnpe3XNHs0NaZ59NIzRqycQgghxGhl6fJmLr/jhf7f/veuAnWODfyBv4YyeeKl//KtK+ns6aNJyg5RZCRAi1HDq1v3MmfKOMAJONHTl/3alrm2EEIIMbwEBXzyI9/V0U/SVU5yaasXzm/iuw+s5ojpE/j+BccNe/mFiEJBxMSooKe3j9e3tzFnqrtMVQ5zbeN+XrXoGM1gCiGEEAUijnAs39XRT5LAX562urmlHcuAtnrp8ub+NNZaNrd2ML2hdriKLERspIEWZc/S5c1cdc9LdPX2cdOTGzhi+oTQgBMy1xZCCCGGj7D3bybNLe0suPoBmeGOYqICf/m1zW1dPYHa6s/f9CzX3fsyF589lzOOmEpbVy/TJ0iAFsVHGmhRkixd3syCqx/goEvvZsHVD2TNQvrTXXbbc2zZ7aw12dLWzWW3Pcfph08hnarMSitzbSGEEGJ4ufjsuYPev0FLRgZpGcXoIagdpFOVnH74lEHa5l1t3aHn8drJbx5fB8A0aaBFCSANtCg5ogJPALFmLR9ctY2rFh2jpTOEEEKIEcR7z/rfv9fdu4rmlo6stAooNnrx6vTSW1fS0dNHdWVF/7gsl4+8n/buXm54ZC2ANNCiJDDWBsUlFpkcf/zx9qmnnip2McYMYUtONaZTdPb0xep4DbD26vcOQ+mEEEIIkZSDLr07cCUMgIl1KVraujXZPQr5wPeWsWJjK+NrqlhxxVnM+crvQ9tBHB655HRmT6orWPmEyMQY87S19vhc6WTCLUqKpcubQ32nWtq7Y89aKkCJEEIIUTpEvZd3tXWHBo8S5c3WPZ1UV1awp7OHDbvaQttBYzpFRZCtv8v4WsdoduqEmuEophCJkAAtSgbPdHuoyNdZCCGEKC2CfGKD8My6RfnT12fZvreTEw+aBMALm3Zz8dlzqfRJyulUJZe/7wiMMbzziKmBvtNHN01g0rhqaqpytyEhhhsJ0KLoeAHDPn/Ts6Ea5nSqkol1qcBj46qdzlRLUwkhhBClycL5TVy16JhYabVO9Oigpb2b7l7LgkP2o7LC8MKmVhbOb2JKfXV/mqbGWq5adAxvPWQ/evssp86dylWLjmHyOCfNfvXVXLXoGOpSVfJ/FiWDBGhRVDLX/oviqkXHcMX7j6IqYNbyrXMmU1VhePHKd/HopWdIeBZCCCFKkIXzm2iK4WIlN6zRwbY9zgopsyamOXRqPS9u2s2W3R1s3t3JNNcU+/cXncLC+U280eoEmJvZWMvC+U3c8dkFAHzhnYf1H9ca0KJUkAAtikrcaIxnHzWdhfObmNFQ2+8jM7EuxVWLjmFvZw9HzJhAulpmPUIIIUQpk8uU2++GFXdZS1F6eAL01PE1HDlzAi9s2s2jr24H4Lw3zwJgY0sbAG+4EdqnT3AmT5oa04yrrmT1lr0AbNndwTRpoEWJIAFaFJVcZlrVlU4Tfa65lb2dPWxq7eDTp81h8rhqTps7lffNm8GKDa0ct3/jSBRXCCGEEEPAM+VuakxjcIJHea5YU8fXZLlhZVqpKchY+bF1jyMUTxlfw1EzG9i6p5PblzczaVw17zhiGgDNu5xx4ButzufMRkdINsZwyNR6Xtmyh86eXnbs62KGNNCiRNA60KKozGxMh5pvNzWm+fRpB/NvS1/gmfW76OjupbfPctLBk1m/s51lr25n1eY9tHf3ctwBE0e45EIIIYTIh4Xzm7LcrVZt3s27vvMI//a+IznnTTP79wdZqWnt6PKhXwM9oZZd+5zvj6zeTjpVwfObWgH6x4BvtHZQm6qgIT0Q7+bQaeN5+JVtbN3t5JUPtCgVpIEWReXis+dSU5XdDNOpSr7z4WN59NIz+NhJB3Lg5DqeWbeLJ9buoLLCcNz+E3n7IfuxbU8nNz25AYDj9pcALYQQQpQjB04ehzGwZuverP1hVmoKMlYebN3TSTpVyR9f2MwNy9b272/v7uM/736JqooBDfTm1g5mNqQxZiDWzWHT6tm2p5NVm/cAME0aaFEiSIAWRcWZhXZmm8OiaB+3/0SeWd/CE6/t5OimBsbVVLHg0P0AuOnJDexXX8OsiQo4IoQQQpQjtalKZk+sY822bAE6LJiYgoyVB9v2dDJ1Qg3fvO8VOrr7so61d/cBJkMD3T4oSNih08YD8MjqbQAy4RYlgwRoUXTqa1LUpipY85/vCYyiPf+AiWzf28nT63fxFnctwSfX7qSywtDV28fejm7ueHZTMYouhBBCiAIwZ8o41mzbl7UvzEotM8iYKF227ulgSn1NqMVAT5/NMuGe0ZA9MXLo1HrAMfsGFERMlAzygRZFZ/XWvRwytZ4K3xJVHq3tXQBYC7c+vZG2rh5ufbqZ3j4LQEdPH5fd9hyAfKKEEEKIMmTOlHr+smYHfX22fzywcH4TKzbu4mePrgOcwKJ+KzVRumzb08nc6eND493UVVfSvKudnt4+tu7pHKRh9iJxr92+j3Sqkgm1EltEaSANtCg6q7fs4dCp4wOPLV3ezPceeLX/9459Xfzm8fWhQUWEEGOAlUvg20fD4kbnc+WSYpdICDFE5kytp7Onb5CglU5VUVVh+OSpB9PT18cph00pUglFUrbt6WRKfU3g0mXpVCWnHTaFHfu6WL+zjd4+y4zGbAHaGMMhrhn3jIbaLP9oIYqJBGhRVHZ3dPNGaweHTqsPPH7dvS8P8puxIedSUBEhxgArl8DvLoLWDYB1Pn93kYRoIcqcQ1xz3Vd9ftArN7Yyd/p43nP0DPosPPzK1qzjWie6NOno7mV3Rw9TxtcMWrrMi3fzzqOcpayeWrcLCPZx9sy4Zb4tSgnZQoii8qobcfOwEA10EqFYQUWEwBEk778SWjdCwyw483KYd36xS1U47r8Sun39Qne7s3803acQY4w5UxxBac3WvZw+dyoA1lpWbmzhvfNmckxTA/vV1/DAqm2cO38WS5c3s/jOF2hp7+4/h7dONMilq9j0L2E13hF8/UuXAfx17U4Ann7dE6AHj+O6ehyLw8de28GCqx/g4rPnqm5F0ZEALYrK6i3O0gRhGugwvxlDtiZaQUWEYEA76wmYnnYWRo9w2box2X4hRFkwaVw1E+tSWYHE1u1oY3dHD/NmNVBRYZgzpY67Vmzidys2DRoHeGid6NJgqytATxlfE5qmyV1B5cl1jiDt10AvXd7MH57f0v9bEySiVJAJtygqr2zZS22qgtkT6wKPh/nNXHDS/oNMgdSZijFPlHZ2tNAQ8j9vmDWy5RBCFJw5U+qzlrJasbEFgHmzGli6vJnl61v6heYwdy6QS1cpsC2GAD1tfA2VFYbXtjlBwhrSqazj1937Ml29/uWvFPNGFB9poEVRyRWB2xOKr7v3ZTa1tDOzMS3zHVG+DLd59VjQzh7xAXj8+9n7UmnnWQohypo5U+q5f9WAxvG5ja3UVFVw2LTxfOKXT9PVGyU2DyCXruKzba9nwh0uQFdVVjB9Qi3NLe2BQcLCJkI0QSKKjQRoMSwsXd4cS+hdvWUPbz14cuS5gvxmhCg7RsK8umGWG1wrYH9mOcrZR7plHVSPByx07XXv4YryuocklHt9CZGAju5etu/t4qBL72ZmY5qaqgqOnDmBVGVFbKEpnaqQS1cJsG13BxUGJteHC9AAsyY6rnr+CNwQ7sanCRJRbGTCLQrO0uXNXHbbczS3tGMZ8FnxR8b0InAfEuL/LMSIMFJLIo2EefWZl4PxdeuZ2tlSjmCdqx5WLoHrj4BVdzlBEI4619n/D/eMXoGylOtLiAKzdHkz9zy/GaB/7PDa9n28uGk3S5c3xxaaLjrzUE26lwDb9nYyaZxjoh2F5wc9fcLg+g1z49MEiSg2EqBFwbnu3pdzrtO8dHkzZ37zYQBueGStlp0QxWEkBZSRMK+edz5UT4BURkwBT0j3NJml6COdqx6847s3Ob879wwc2/Fq4CkLWrZirTldqvUlxDAQ5O8K0NnTx2W3Pcfph08ZJEx5ollTY5rF5xwJRPtGi8IStYTY1t2dkebbHvs6nCjqtz6zcdA5wpa/0gSJKDYy4RYFJ8zMqrmlnQVXP0BzS3tW9Myd+7oUVVEUh0IsiRTXxDaOefVQ2bcdOlvg6PNg1d3Q4zMX99+rR7F9pHPVQ9DxXse/jh1rYM4Zw1OuYkc1Hws+7UK4RJlot3f38uCqbVy16JhI97Bbnt7IAy9t5cLTDhmJIo9pPGtDT2Hij5C9bW9nZAAx7xwPvLyt/3dQlG258YlSRAK0KDhhPitA/37/DLGWnRBFIVRA2eBoG3MJxUkErNO/Aks/nb2vqrawwa/eWOF8rn14QHj2CBOeofgRrHMJilECYz4a6LiTHsVec3okJl3yRb7ZosBEjR3AEbBzCVNNDWnufXFLvw+1go4WDn9sm7aunkhrw+ebW+mzRK7dfN29L9PtCwyn8WAZkeQ9MMreGRKgRcG5+Oy5/OvNK+jtS2ZIpaiKYsTwOvJQYz8zILhECcW5TGzvv9LJbyrBugON6vFO8CssHPbuwr5ANq90Pvdtj59npCNYB71EG5qChWRPUAwTJCtS0QJ00LUg/qRHHA3wcA0KVi5xTNX9lELE8aiJIxhVgyQxclx89twsjaafXD7QS5c389ArjjYzM/4KyLptqARpm8NwnvtKvCFgVD0oynYZk0SBUGxrrmHAWCtvkVwcf/zx9qmnnip2McoGay1v+vq9dPVaOroH+zOF0dSY5tFLh8kUcyxRDrN8+ZSxUPfl78jj0jAbvvB89r7FjYQK4al08DVSaXj/d+Hha2HXWujrLVw93fwPsPEp+v2Ic1FdD+/79tCvG7dugp59Kg37vw3W3D84fXoSvPsa5/ttnyDrWafSMO1o2LcNPrci/rWq0tC+c3D6oPr99tHBzzE9CarHuccyHVIYqN+hPNOoNvq+78Dx/5D8fP7JnIbZ+be5qOfS0z643F49llo/JEqOpcubWXznC7S0d2ftT6cqc/q+ei5ifjS2yB9P6xwlMMclqB5UZ8PIcI8Fw94DSd6lQWmLjDHmaWvt8bnSKYiYiE1UsIhMXti0m90dvXzjA0cTHXtxAEVVLBDlELU3nzIW6r5WLoHbP5VceIYBs+7Ma4aZ0prK8Gt0t8M9X3aWY+rrIet+7vri0AJWbV4JM+Y5L8pUjIi1E2ZGv1DjBNBKUjdhGvs19wMGUuOyj7XvzAgeZqG20UnXMNsRUuecAS3roadrcJmC6rm7PVh4hmBtc1BU84qUY0HQPxjwTaAkDfIV9IyDnpPH+BkJz9vgTD545fUsIYbSN4Rp5tt3Bpfbq8egyOrFCtAmSpKF85t49oqz+M6Hj00cOErazMKSuaJKIQiqB0XZHiaSjpny6YuTxOgYhfE8ZMItYpErWEQmD6zaijFw2typkT5Nnt6mSX5KhWMkfDaH6vOSTxnD8tz2z84xz6Q1qlzeC8UGmwcC2abWQfhNVcNMbHMJ6EFCXHc7PPVT+gWypCZOnXudgFrHnD+Q3tM6BlHbCNtfgdZmx4TaT5jJ1frHYfV9A8+5a1/uuvHKE/mytNDdNnh3dzs88i3AwGeegPHTs8to+2DX6zDlsOxyR9VjEEGTIXPfDdZCzfiBuu7rHpzOT9xBQdgzjmo/6x6Fue/KPkcuM/UwK4l8+4Ywk/IC9hEAACAASURBVPooglwbMrX3Ye0r6H9c6hY2YsjkEzhqpNcM9vsEj7ZxTNCKKn4MkKqqoKsnt7VhUD14z2s0P8eikGScla95dZIYHaUczyNPZMIdA5lwxzOzyTT1SVUarjvvTQCBPk0T61Jc8f6jRqaTHG0Drqj7CTUpNrC4pTDXDjKLDTJZDUsbKhxElDHKVBocraAx0JupiXQH556papQwCbmF50zCTFUBzv5PePyHyQWMMOKaOK1/An56FvzNjY7g5xFWD6dcAvd/HT7wA5h/weDzhZlc+U2Wc5HZPkLPGYPKGvjA97LbWfPT8JMz4CP/52iFc9VxGFVpOCegDb9yL/z2fDj5i/DED5NZLsQxkQ57HqbCmRjwU1kN0+fBP7vm7knN1APJo29YuQRu/2R2GeNeN+cEU4RJfJL+p9CMtvfIKMQ/0Z9JpTH0WktjOoUx0NLWPSRhLehacczMS42oSYCDLr07sqevqaqgs6ePf194NF9b+nxk2nJ8Njkp5T4hyVgwX/PqlUuCXavCxoO3fyp7jDVSfXdCZMItCkou0yi/qU93r+3XUPvX8PvOh49l+eVnjZzwXOomzUnIdT9hs3npiYUxlUyyLm1YWlM5OC1Ez0TmmqXs6/YJzzBIsxUlWKXSyTSWYaaq4PjGnv6V6GulJ8W/VuvGYPOqzH3XHAS/Wuikv+sL2fU773znJdUwmyzz54ZZjqB2x4XZbcI7b+jzSjjpmtk+zrwcKvI0fOrtHPzfnTTH+Xz+1tx1HIUxzkDA/99Y86ATKX3lkuRm/3H6mjBNdZDwnErDIe+AN551rA3yMVMPvljuPsHf1n7/JbeMGU4677ra8XP2m7xnEuXakFmeTPya6yTrYicxS4xKO9reI6OUzDWD/fS6yqKW9m52tXVnBRkLc0eLIkg7mxmBuhzIHLcFPY9cmvseN0rY9x58lca6VGi6Ubl2c1CfcNs/O/1jPv1Cod1ZwsZMQfvzNa8+8GQc16oG53dVbbhAPO98aDzAmQjPHIeUmPCcBGmgYyANdG4NdMkGgiijwAWxiBJsGmbDoWfB8l9lC5OmCioqsvd5M3+QbAY1yaxmlNbYr2HLNRMZpPFKSpiG2VTCuT/KX3vp56hz4U0fhd9+COr2g7btgwM3QfxAZkHa7kCNewZxnueg63uav4Qa5li47aO3B6492BGGezrC00Zd3//fve4Q6GqD7n3Ji5WeBB0t4W3x+yc5JuOvPRRdpqgy9wccC/iP5dTI+6wotjwPj/5X7mvmhXu+pG21ssapzwtugQMWwFWznEkSb51ujziuDVFlW9ySrP8phLXMmz7qmpNH9Lnl+B4ZA4SNSYLw3MiSmBGHaWcNsPbq9+ZX6BEm17ht6fJmvnTzin5BGRxN8qL5M/ntXzdk3X+qwoAha0mqUal19ojsu339dpwAqYW2rFm5BO74bHY/XFUL5/z34HPmGleG3cNTP4O7Pg8XPg7P/Aqe/AlcshZe/v3gceXR58HV+8OxfwPvuS6/exoh4mqg5QMtIomKwJhOVfQHeijZ4B2lGLhgKGY/UeVu3QArfguTDoFtL7k7Ldge8MuNXiCrTMEsjt9LIXxeJjQ5QaE8v9KK1IAwH7T28solcN/XMjReeQoNQcKz/yXlf4nlElQHna8OXnvYESpqGuCLL0FVdXj6OEJ7kDYxlx9uPj7l/c81T0ExEuvMzPd2Q9ceqJsMx17gtNekQot/CamO1tz1E1SPXpA1/6SM99/44xWwZ5OzpSeGa3W9AYbflM2jfedA3kF+vrkmbOyAkLZyCTzx4+xjifAJyEHXgsFBxqpyCL7eAG3do+7EWC98ZIlzz5nt+53fcIT/OBMGfnItZ9Ywa3C/msQ3P0yznRmTIIhCvEdK2Qy0jEky9mhuaecLNz3bX9Nxlr8aaX/rTIbqe50rsrb37BbOb+LaP6xi+94uunv7+q913b0vD/pXdPc55vHjaqrGhi9zrngeEN+XeDhi18w7H1643RFmvX71yIXB5zvzcrjzs9DTOfhY6wbn3XbbPw8WplffB437w5TD4bCz4fHvw4P/AU//bPC4ct82590/9cj87qcEkQAt+vF3yqcfPoVbn24ODSLxyVPn9HeOxXyZRFJqgQuGuhZeruA93e2wc7WjCXrz3w/2OckkLJBVZqedObhLTwzuYCuqnE7VPxA89CxY/mvfDGgajloEj/03nP8r2PIC3PdV2LvF6Xgzn4vXaWcNqm2wMFSRcpL1RgiWtY2OtrF+unM9/2A1K/CWLyBTHEE3lYZZJ8Dah2HljY4w/eLS8Hqd5wb7yuXfnS+Rky15DPwrquDYj8Izv8yRMEQIymxvbTsc4blfWE6gnfX+u95/KZfwnKlJ9dftbZ8IzpNZ1o5Wp31VVgdbccQJ2JZJdzs89b+503l4dXX/lc6EVyJCNCFx21x3iJ9/EOv+4izJVlkNB7zV0brPOx82PAn/+w6on+aUYemnnHT+MkJ4mbwI+IeeBU//PLtPq6xx9vv71ShiT2TkekYWvj4p/2XBCrE2qr+PBmjfNfLLA5YYUQFMg/DXtGeOHSYAXnz2XC6+ZcUgjetwR49OEtA1Tv4gvHHbppZ2NrV28JX3HM4nTpnTf/wLNz0bmK+1vZtnrzgr9r2MGIVs49654r6z4wjCoYqeDc718i1ry3o48O3w8bvgB291fgcx73x45T54/uaQEwUEenzlXti90VkK87mbHeG8staJ/xLkhvPI9c73aUfndy8liATosYqvQ3lyzr9w2ZMHZHXKv3l8fWAXMaOhlu17O9nb0QM4HfLezmzB5ZyKZXw5tYSZHTvg20V8KZ95Odx5UfbAM5UeGFAnZagd8VBnGs+8PLcpc283zD7BOWfSSMQw0Jn7B3eBGrgKZzDsF3Q9bfjkQ2DrCwPH3vQRp0xVtbD/W2HbKif9ff8WcO6QQXVfd/Y6vBUpWPgDeGMFPPY9N5FPiKusgbopzhJAn3k8/N49oTZofxzz+Wd/M7Cvu21okSyHSi6f8iTXTI1zTKQ94blmAnTuJjDgUy4Nskd3u5MuzAT2zMuDzdoyheEo4S7IBM5fD3GF3qw2F/LfDypvEsI0w1495qXtzNBg+89ZyDZXMx6an3EEt9lvcZ6Tx4x5jlC98a9w1r/DvV912k5P58BE27O/8Zn0B0zCtG6AZ3/r9H3V4xyzfazzO8mEhEccDXMc/Bp7CF8DvRArEvjPGdZHxynPPV8OzwMBgvnOwqwjPgJcfPbcnIJiLqK02AvnN3HTk+t5/LWdWKA2VTEi5spRvtdxrh0VWds/bnvtgAuBAzjj8GlZ6TInJ86pWMYlVUuYabaz1UyBlftKq00UYpIq7Fxx8SYAw/4vUf2xp0jw4qbEnRxr2eC4/Jz1787vyYfAS3c6k6dB+bv3waSDYedaIvtE/wRw194BobqvOzxv23bnc+oR4ecuMxREbCwSEPzg6Ge+xjt7H85K5v8bnFOxjGXVF/FoxyKW1VzE9sd+xYGX3s0XbnqW1vaerHTXVN9Ak9mOyXf9uXwDKvjzAbzlk9lpTv5Cfh18YNCITzjrrA553bwNjolrrvs94v3OAKa6Pvo6s04cgnmhG1Toni/HeFH0ESrodrfD9lVwyDvhil3OgGvPG44/6f4nOZ35/V/Pr4jtuxyh4MwrnE77oFOdNZWr0vDVLbDoxwNBs8AZ8O1cDbub8w/OEfo8jVOW1fcN9uuNsyZw3DWbk5BrkijJNStS0OfT8vZ1w6KfZD9nLyjI+653BbYYq8BHtdGw4GdxlsSKG6AkyXPw2tziFufTf+6s8uJo7JMEi7O9g8uSWY/5Ws2ErW9dqDaXSsPstzltYvsr8MbK7P9YVQ3MONbRRLesh31b4R2LB55j0P/GMzX309PuHFvwOaftVVTFW1YslFzuCgkJ+7+HvTviuClEkWsSyTNZDwuKFmaFdM+Xs8ub6YZQiHXERwB/QLFK49RnYzrFxICAV9745rWaj7Ks+iLOqViW04Lu6B338eS4z7O29gIerPwsH6h8tPA34mMo7nJLlzeHauXPqVjG1anscdtxK65gYdWjPLcxO76At3azl2dWxXYqDExnW+m1iaSBB5OeKy5R/5czLye8v3H7qP7/YMjY0x/o8fsnOvke+x7c9UWnn/XO5y9LX59jQXTA2/J7z3S3D7YM8lOVhokHQk2OsWsZIQ30WCSgE0jTySVVS7iz62Qge1Zxk92P+/uO5UOVf6bOOAPpaX3b+M+qG+izcGdfdh6nA/aRZP25pRdmm+gGzopvyB3sxst3yDsBA597Fr47f8B8MKk2OcpvNO4aplEzjX4/SRhcnteXOQPGD93opA/y2e3rdkyJh6JlKpR2qq/X8Y0xxvGTeeUPzv7dzc5AO9+XkdfJH3yaI4Sv/bMjmB/wVkjVDmiSVy6BpZ92hGtwNF/5zj7ncgfI198+yHS8a1+ySMpJZ6cHmR37NX4Zpr9BZfH+z0GCpEec9pfrZR1mERB1/iSBnbxz+zVxYdeLc75558Odn4Nnfp6sDrOWWwvoPwI13DnqKazcOes/An9bO/QsRzPs0dk6+D82+0T4608GBnEHnzaQPjQSecRgbNm3nQFZX094Go9+a4mEBAnncQKheVHzc/ljRwbKizmIjSto+98puQSBuO12qH6aHsNkRh61lnRmAC1PEPTGN7PMdq5O3cCdHWtou+ZC6to305aezrXdH+YXe09kZmOaqw97iS90fK8/zwy203fnRc7YZxg1sDMb07x59x+zxmfX9pzP0xPe2Z8myEca6Df1DuLS6iXUkT1RWme6+FrFL+i44ybsnTswbt0snO/c30l3fHZQnkg3sGK4CAwlDo6/7FHvs4bZufvSsP+LF806ERljT/+YOfP/u2dzsKVNZlm2veS4tx2wwFFG5KNlj+qvU2knJswoMt8GCdDlTz6dU0jHMdNsZ1n1Rcw0jqlFhSsFzzLb+Vvzp/7fHnWmq1/o9r+AYl836EUepFEICnoVJ9iNZyY69Uhn9mvWiY7vxuRDcpv1JOk8vWtldlRB55z/t/DQf0afxztXUEf7yh8c39oDT3YERRgYBFekYNpRjs9m/ZShm5QWike+BVtfcoRcj47W/M+XqZWb8SbHvHDFbx1z8GN96xnff+XgQXa+g75cJsVD8bf3C4qRUbL9588zEnDmNXOuLR5ArgFIrvY3FFeKsPPnc05PoIgSGpKcd+USWHmTb2cOAdU7f9SEQZiPfmYdJnkegfW/IdyU3LuPL6/N3vXtowf7Zvv/Y7NOcDQhj/3AiUEw5fCBtGH/m6hyJPHN7uuG4/9xcMC6MNKTnMkB/3soPclZpiun2b/NDiiXdDLSX2dR/80kk6Td7U654kwWJWGogdQKaWKbgEwT70uqlgwau9SZLs6391LhFquu/Q0usT9gZ0UXd7aczMErrh+Up6JnCBMKMcdyVx3yEsc/ly3sX5O6geePPBA4I9BHOjNAGgxWkHyHjzCdHYHFmmT2Ysxe50dG3Sycfz7csT34XsLcwEaobrPI970cVPbQa2S8gzP70iCC/i+vPeR81k9z4rMkJacVTo7YEgc6SjAOeJszTobkk6tR/fXx/+QEGBtFAcRAy1jFomSXscq59IYvqEimH1MAfZZBQnIu+qzh4M7fsKz6ImZVhHSmHkED/eEKoOTnzR+H9/8XLPkHePG2iIQmI+JuiFYuHzzt0rq/wDO/BhvT7LBh9mAftKo0nOMzT1164YD/barOuVdPAzsUzWYkSZ5H0mcXoRH1Dyx+fDpsesb5Xj/N8fnJGSwpYNmbOEQNcgq9FEXsCZw87yUuQ1kKbqgBjnJRKO1GVD+U1Ncz7HkFLUfm7X/3NYUZUBbqeSSp8zj/sSf+B+65xPme2T95ZQ57j8UVenPh1WFUUEXvulXpEE1+RjT04ZyY9DTm/QPSiL7w0LOcuARDMmP3EfUMgshlOQHR/UCo5USeE4MJ/gOepvaR9nNjj3029u3HyV3f5bWaj4bkGWj3saNlx3h3PHnn/zD7meuYZrdhwsraMJvF+z7Iz/eeGFr+IGVHT2Utu3uqmOQJynGItHpx6y6qHxlKm4lKmyT4p/cfC7LgihsfI+wdH/Ue8MfSePVPsOYBOOs/4K7PFU/pEfSuW7kkXr8Z1F97VkIz5kHz0/ChX8BRC4ev/AUi7jJWEqBjULICdGhQo+SCXj7CM4C1sNPWu7OUEQn9nUyuWbpC84EfQGUK7vyXiPVnhxu3XlJ1ThCtnAOUiHrMfJ4rlwQHSkuy3mmcAVOQ6eagAe4Q16ZNuj71yiVwx4XZ0bcz732k1wEfTnO1Yq1pPhxrVJYahXy2UQLloh+XR8TjJHWe69nFOVfY/yZq8BY2IRFIrnWkGRg8hi1HljkhEFtjn4DaidCxK1meVNoJjri72QmmlmOSPBanXgqT50Q8hwyq0k5k/pzL0eXzXkgwMZg1nggIbJirr7r+SOcZxiCW0qBhNk/O+Rduemo9n+fGLE3vyedeyMLKR+NNbLv/oSfv/B+OfvrfSEdZ+Lm02Wou7f6nfte6TM6pWMb1qR9RZQYHIW1hPBPsXirMwLOzluhxXUUKsNlWXpnPO+r/5neHSNpmUuOc+ApByo7A5ScTtMG4a9ZHTa7GnWhLpZ3yHnoWnPe/0W15SMQ8V9D/JcoiLvMZBPXjT/wPNLvy0/jpznKGpfjOy0ACdAEpVQHaLm50gj0M5RwW2qihjs7ojnIoVFbDB74frXGIc47qcY7wlujaKUe4+uxT8KtzR05gz0XS9YWDiDPLGzT4D5utjaqTJOeKM/DyyBXZOBeFGLyXC8W8l2L7sQ03hXy2xZroKDRx6zzXsxvq84g6PyQSRGKVJZ/yDtWSKqnWNwsDx/0tnPPfA7uSvmMbZsPbvwR3fxFO/jzMfQ/ccOaAOXtQFG5wXGbW/nl43qtx3jne0ord+/I7l8eSv3eWHMwgTKngaaDPrfgz30r9KFTx0EUlWEO1GRAu+1yB1MQUZvqs4e3p27i545+ZSQ4Lv4AyZpLLzc5iMFhabR0TaKOdajqozq2VrqzJXqry1C/D6V9xvketXBFIIQXGoNMXaLLLOVnuCZ4kiqL0RHj3tTG08EHWkTlIsjoGBP9f8hkDrFwCd3wmevnHEiSuAF1yPtDGmI8CnwbmAZXAKuBnwA+tjVq7J/R87wK+CBwP1AKvAf8HfNNaG7Cobfmwhf2cqIdDpJMULbaeJhPsA5M3qTQcfCa88nsnkNRQtM62L7nwDAMBw4ZDeM5cSilxuXzL4uSjOfB8aZIGyYjyswzyj4vrR+kRWscBmoGhmq7muvdcfqPlRDHvJarNjAYK+WwL5ZtdbOLWea5nN5QgPnHOn0tTkvns49RNPvWXNGBj0MRh2JrkObHZQdlg4JnkMr2E7MHyczc7MUJ6Op1J64uWQzogBoK1cP1RTvqhTAKHkUo7GrlvHx0tPMR9X3q+nkEWDvd/3dlvquisqqe6yxGKguTiNlvN/X3Hsqz6IidYqoE9Nk29aR+UvpreQScZELbjCT+b7GSaW9qZXrM9UVD4JrOdcyqWcWffydnBXSPOYVzXtc/XXMk72u7h3MplXN39Ea6uviF6uZ7eTph9EnzsFrh2zkB8k5VLnCWOEjHMCr2CCc8ki20SZyKhfddg//CwPjiXWXVUUNE4ZQnqm/MZA9x/5eD+oVCBB0uAktJAG2O+D1wIdAD3A93AmcB44HbgQ9bG/wcYYy4BrgF6gYeAXcCpwBTgceBMa21brvOUqgb6c1+5jKtyBe7KwW5bwwTTGWiqk9N8JxeLfgITmuDn74GTLoSnf1Yg3w73BZpzNrGAPsxh51/ckscsqy9/JknOla8GOhdD1TbG8c0vlPA3WrR9YnQx2jX2SSg1N4o4dZO0/iKD/sU0Kc77PQJc/BqMmxyzXBn4y3LLP8Lztzjfq2odrXbYAH7phYX1vc5k3oedZQ4L5gsaNhYYbPrbZ/uoyBhX9FknlTHQYauooSdrXNRmq0nTNWQLPq80/b/dYu209TSafVSawWMXf55M2mw1N/eekrV6SihVaWepue0vw8Vr4IFvwLLrB45Xj4euPeH5T70UTr8MfnQqbFnpKDyGW5ucD4XSQCfVoiaxUCmEZU7ivirPMuSi0DFoRoiy00AbYz6IIzxvBk6x1q52908DHgTOBT4L/FfM8x0PXA20AWdYa59w99cDdwOnAP8BfKGwdzJyPDXhnVy6m1izi0F02kpqcTqTgbwGi6W5b/DSVUB8U7OG2c6fuKfL8VV55pe5X4aBPm1BnbDNLTwGdpTBL8xoU+qIl4A3AxmksYhjoh00gxlXK5NUq5KEoWobR1JTOlq0fWJ0Mdo19kkY6f9ormcfp26S1l9UnxdXGI+MWh8i8IHzrltzf/A5/eWKCsa0cgmsumsgb09HeMTk+68cJuHZvb+VSxhe30/r+3Tp6x6kba0wsKNvHBNNG7UZ5tgedaaLHltBFYkNJAeV0hPWYWBMNjnEhLrdVrPpwEU0rbudWgYbU9aZLi6oeiBeuY7+oNOGDj7VmUB54ofZx21PcCT7ympnjHPwaU6dbXvRFZ6h5ITnoQYm9AK65jOeSWKhUijLnFj5QmIGFKpvHsrKJGVAyWigjTFPAW8G/t5a+0vfsVNxNMibgaY4ptzGmFuADwJXWGuv9B07GFgN9ADTrLWRUyGlqoHOXK4gLKBFr4VW6mlkH7vsOIyBRvaxyU6mznQE+re0pWfw5r3fob27N2O5gx101E2n7t3uo0wyq/3DBbAlx2xWmE9brsjDYbNwuWbXAqM1hgwwgu43ThCc/vMmCGwSFRguPTFZFMqxMoAfy/cuRDmg/2g8goKT+YP0hLnZDNWvsCCR16Nw34HpSc6as0HDuKhj+VxrhOgDOmz1kKwBPXpsRWCQr6w0VLD8uKtpnv0+Hr71+1xf+f1ABUpOK8JUGipqHO2y7XXHPyY8joA/OnV/G50FXW2FXR7NuQD9bSanr3uOOl/0E9+EVsZ/rN/kOaT8Q9XIJolJMNLWc8PZN5dpDJqyCiJmjJkFbAC6gEZr7aBWZozZCDQBC6y1f8lxvmocc+064BBr7ZqANMuABcAF1trfRp2vVAVoGFgm4c27/zgoQERUNEYgchmGpR94IXr5hbhLDMQx9YqKZBjnpR7UAYT54RbTrLkQAXmEEEKMXYbLJD6JuWXsFUBClh8cymoQufCWhbMWbv8kIyFIt6VncPm+D/J5bgy1BvQLs2HCbRzXuT4MFYtbWHD1AzS3tMdbRtRP4mXQMtrB078YsE5IRIAiIUqo9IRej1zjzqGO+4Zz/OUfAwatYjIax3plOHlabibc893PF4KEZ5cncQTo+UCkAA3MxRGedwYJzxnnW+CeL1KALmUWzm9i4fwmFlxNvzn3TLODTXYy1/acHyg8N6ZTdPb0scnuxywT0Ok2zOo/byhxTdyiTL3idBZxzP/CylJqZs2FCMgjhBBi7DLUoGxhJDG3DHsvx41zEfaeix1ILUMzCeHBkpIKz0GuV7kE+1Saundfycm9C/jwvWfySPu5gX7JFmju269/fFZnOpjEYAvAXnKbg2/qm8wsYFOL8/yv7Tk/MsK2v7xZEfLjmuJntoM/Xxcvj/+6Qe0jSuj1t50446ihjPuGc/wVVPb9Txr9Y71R7M5UKgL0Qe7nuog0631p45xvfUSaJOcreS4+ey6X3dbFnV3B2maPdKqSxeccBcANd3+MS7p/MNjHuZC+aVEv9TgzbQXx8yizzmkUdzhCCCGGwHD5FSbxVS/E+zXpCg5RLkxBxJ5Q8GnJ+8sRY5lHT9s973wW4ig02q6ZQV37G4OusslmLy0VtKxUnMBfbbaaG6o/xmJgZmOa5pZ2R1HSHSMejt8SIJ+YK0nyhVkg+CmUsmO42uVwobFeWVMqAnS9+xnl4OBN1Y0vwvlKHk9bvPjOF2hpz55R9Ixmmnym2Avnfx1WHjW8Qmboyz5gdjGMfDsZdU5CCCFGE8MVlC2p8DEc79ewe8vHrDVs7BG0hFiQpjOIGM+m7t1X0nPHv1DV29G/r8vU8B0+kpXudxlCr99qcG3t0VySuol0+2Z22XHAQOya7/ARTn6vo6l3FCdOHJw7+07mzq6TebTmIpqC1owOMmPO9xkN5dn6KbSyQ+M+MUKUigDtzZcVMuzikM5njPkE8AmA/fffvxBlGnY8s2vPLzrUfzmT4e5sFCVZCCGEKAwjbWY6khTy3sLGHq7GOK+yxXTDqoKse6g+83JO7l3AYxnjstMPn8KtT5+aZTWYTlXynQ8dw8L57wW+DsCfI8Zz3mfm8U1HXkLTc1fEG3Pl+4yK9WyFKCFKJYjYRTjLUy211p4bkua/gIuAb1lrv5TjfOcAdwDPWmvnh6T5AnA9cKu19ryo85VyELGyoAyDCAghhBCijCnxsUciZUcSktx3vs+oxJ+tEPlSblG4PYF3ubX2uJA0t+GsBf0v1trv5TjfPGAFThCxySFprsdZAzqnQC4BWgghhBBCCCFGL3EFaP+a8cViuft5lDEmHZLmBF/aKFYB7cAkY8yckDQnJjifEEIIIYQQQogxTkkI0NbaDcAzQDXwIf9xY8ypwCxgM/BYjPN1Afe4Py8ION/BwFtx1p2+O++CCyGEEEIIIYQYM5SEAO1ylft5jTHmEG+nMWYq8AP359XW2r6MY581xqwyxvwy4HxX4wQR+7Ix5sSMPPXAT3Hu/QfW2pYC34cQQgghhBBCiFFIyQjQ1tpbgB8C04HnjDG/c/2eVwNHAksBv+/zfsBcYFCYbGvtk8ClQB3wF2PMfcaYJcAa4FTgCeCrw3Q7QgghhBBCCCFGGaWyjBUA1toLjTHLgM/gCLmVOP7MPwV+mKl9jnm+a40xK4F/xfGhrgVeA74LfNNa21nI8gshhBBCCCGEGL2URBTuUkdRuIUQQgghhBBiuyGVpAAAE8xJREFU9FJuUbiFEEIIIYQQQoiSRgK0EEIIIYQQQggRAwnQQgghhBBCCCFEDCRACyGEEEIIIYQQMZAALYQQQgghhBBCxEACtBBCCCGEEEIIEQMJ0EIIIYQQQgghRAwkQAshhBBCCCGEEDGQAC2EEEIIIYQQQsTAWGuLXYaSxxizDVhX7HLkYD9ge7ELIUoWtQ8RhtqGiELtQ0Sh9iGiUPsQYZRq2zjAWjslVyIJ0KMEY8xT1trji10OUZqofYgw1DZEFGofIgq1DxGF2ocIo9zbhky4hRBCCCGEEEKIGEiAFkIIIYQQQgghYiABevTw42IXQJQ0ah8iDLUNEYXah4hC7UNEofYhwijrtiEfaCGEEEIIIYQQIgbSQAshhBBCCCGEEDGQAF3GGGM+aox5xBjTaozZa4x5yhjzGWOM6rVMMMb83BhjI7ZVIfkq3Lp+yq37Vrct/E2Ma+bVbowx7zLG3GeM2WmMaTPGPG+M+aoxpibf+xdgjJlrjPmcMebXxphVxpg+t+7Pi5F3ROvSGPMWY8ztxpitxpgOY8xqY8y1xpiGGPf4a2PMJmNMpzFmnTHmh8aYGbnucayTT/vIt19x86pvKQOMMSljzJnGmG8ZYx43xrxhjOkyxjQbY24xxpyWI7/6jlFMvu1DfcfYwRjzL8aYJcaYl4wxO4wx3caYbcaYPxljPmaMMSH5yqae8+13YmGt1VaGG/B9wALtwF3A7cBud99tQGWxy6gtVj3+3K2zZe53/3ZVQJ5K4A43X6tb33cDHe6+7xa63QCXuGl6gD8BNwNb3X2PAXXFfpblugHfcZ+jfzsvR74RrUvgb9w8Xnu9CVjn/l4NTA3JdyrQ5qZ7GrgReMn9vRU4rNh1UMpbPu0jn37Fzae+pUw24B0ZbeEN95nfBDyXsf/KUqgr9R3l0z7Ud4ydDdgIdAHPAL9z/1+PAX3uM1wKVJRrPefb78R+fsWuQG15VBp8MKNTPDRj/zTgRffY54pdTm2x6tJ7WX08QZ5/dfO8AEzL2H8osNk99oFCtRvgeLdD3Qe8JWN/PfCwm+/bxX6W5boB/wRcC5wPzAEeIreANKJ1CczCGcj2ZrYtoMp96Vrg9oB849wyWuCzvmPfZGBgbIpdD6W65dk+Evcrbj71LWWyAWcAtwBvDzj2YQYGjqcXs67Ud5Rd+1DfMUY24GRgXMD+ozLq7B/KsZ7z7XcSPb9iV6C2PCoNnnIr/+8Cjp2a0UgrRrps2hLXZaKXFc7s3xY3zykBx//ePfbXQrUb9yVsgcsD8h3sdlCdQGOxn+do2IgnII1oXTIwYP1pQL4JODPRFjjSd+yz7v4HA/JVAq+6x99T7OdeLlvM9pGoX8moD/Uto2QDbnCf7f8Ws67Ud5TmFtE+1HdoA/ia+3x/W471nG+/k2STr2yZYYyZBbwZx+ziZv9xa+3DQDMwHThpZEsnRoC3AlOBjdbaPwccvxnoBk4wxjR5O/NtN8aYauDd7s/fBOR7DceEphp4T363JJJQpLpcGJFvN475V2Y6f75fB+TrxZkJDsonRh71LaOL5e7nLG+H+g6RwaD2MQTUd4w+etzPjox95VTP+fY7sZEAXX7Mdz9fsNa2h6R50pdWlD6nG2OuN8b82BjzDWPM2SFBFbw6fTLgGNbaNhzTGoBjA/IlbTdzgTpgp7V2TYJ8YvgY0bo0xkzAMR3OPB7nepm/k+YThSFuvwLqW0Ybh7qfb2TsU98hPILaRybqO8YoxpiDgE+5P3+Xcags6nmI/U5sqvLNKIrGQe7nuog0631pRenzdwH7XjTGfMRa+1zGvrj1fyzZ9Z9vuznIdyxuPjF8jHRdHuh+trgzt7HyuS+xSTnKqrYzvMTtV0B9y6jBGDMd+Lj789aMQ+o7RFT7yER9xxjBGPMPOGbUKRyLhLfhKFivstbenpG0XOr5QPczUb+TFGmgy49693NfRJq97uf4YS6LGDrPAhfhBG2oB2YC7wNWAEcCf8o0hSH/+h/pfGL4KJc2UJ/xPSyv2s7wkLRfgfJpVyICY0wVjtlzA3C/tTZTg1Quday+Y5jI0T5AfcdYZAGO//JHgVPcfV8DrvSlK5d6HpH2IQG6/PDWZbNFLYUoCNba71hr/9ta+6K1dp+19g1r7d3AicDjOP4ml2Vkybf+RzqfGD7KpQ0EriEphp88+hUon3YlovkRcCawAfiY71i51LH6juEjqn2o7xiDWGv/yVprcMylj8JZOnEx8LgxZmZG0nKp5xFpHxKgy4897md9RBrv2J6INKKEsdZ2AVe5PzODI+Rb/yOdTwwf5dIGMr+PS5BPDBMR/QqUT7sSIRhj/gv4R5zlZM601m72JSmXOlbfMQzEaB+hqO8Y/Vhr292Jk4txJkneBHwvI0m51POItA8J0OXH6+7nARFpZvvSivJklfuZaS71uvuZtP6Hmm//hPnE8PG6+zlSdel9b3R9E2Plc32Pdro/w8qqtjPyBPUroL6lrDHGfAvH9HYbjnC0OiDZ6+6n+o4xRsz2kQv1HWOHn7mf7zfGpNzvr7ufpV7P3vdE/U5SJECXH97SA0cZY9IhaU7wpRXlyWT3c2/GvmfczxMIwBhTBxzt/sys/3zbzSqgHZhkjJkzOAvgmHb584nhY0Tr0h3MehEwA9tdUD7f76T5xPAR1K+A+payxRhzLfBFYAfwTmvtiyFJ1XeMQRK0j1yo7xg7tOAsZVXFQEC/sqjnIfY7sZEAXWZYazfgNOJq4EP+48aYU3Gi6G3GWR9NlC/nu5+ZYfgfA7YCs4wxpwzOwodwIik+aa1t9nbm225cs6173J8XBOQ7GGdtwC7g7rg3JvKnSHV5R0S+CcD73Z+3+w5H5asEPhKSTwwfQf0KqG8pS4wxVwMXA7twhKMVYWnVd4w9krSPGKjvGDucgiM8twDb3X3lVM/59jvxsdZqK7MNOA/HOf4N4JCM/VNx1mCzwOeKXU5tOevxWJzolpW+/VU4s8W9bl2e7Tv+JXf/C8DUjP2Hum3CAh8oVLvBmcHrw4loeGLG/nrgITfft4v9PEfLlvFMz4tIM6J1iWPu1Oa2yXN8bfX/3Hy3B+Srz2iTn/Edu87d/wxgiv3cy2XL1T7y7VfcNOpbymgDvuE+o13Am2PmUd8xRrak7UN9x9jZgLfjCJc1AccW4GhwLfDNcqznfPudRM+w2JWoLc+Kgx+4DaAdZ6Hz24BWr1H4O0BtpbcBC9362oEz63Yz8Aeg2d3fC1wSkK8SuNNN0+rW/e/ctmCB7xa63QCXuGl6gPuAJcAWd9/jQF2xn2e5bsBx7jP0tt3uc30lc3+x6xL4GzdPH/Bn4EYc/yELrCbjZerLd6r7IrPAU+7L60X39zZgbrHroJS3pO0j337Fzau+pUw24Bz3GVkcjeDPQ7ZLi11X6jvKo32o7xg7G8464N7kyv3Ab9z684RZC9wFpMu1nvPtd2I/w2JXorYhVJ6zZtujOAOqfcDTwGeAimKXTVus+jsIZ7mAv7gvqA63Y1kN/JSIGWMc94vPunW+z20Dy4CPDle7Ad4F/NHtcNvdjvarBMxgakvUDk7LeGGFbqVQl8BbgKU4g9dO4FXgWqAhR7657gt6s5tvPc5yKjOK/fxLfUvaPobSr7j51beUwcbAADjX9lAp1JX6jtJvH+o7xs7m1vWVwIM4S5q1u/X9OnALsHA01HO+/U6czbgXEEIIIYQQQgghRAQKIiaEEEIIIYQQQsRAArQQQgghhBBCCBEDCdBCCCGEEEIIIUQMJEALIYQQQgghhBAxkAAthBBCCCGEEELEQAK0EEIIIYQQQggRAwnQQgghhBBCCCFEDCRACyGEKFuMMa8bY6xv6zDGrDXG/NIYc2wBr/Vz9/wfL9Q5hwNjzCcynsXni12eJHjlDtj/kHvstCIUK5CwsgohhBjdSIAWQggxGrgX+IW73QfUAn8LPGmM+UgxC1YE/l/I91GHMWaxK8guLnZZhBBCjA2qil0AIYQQogBcba19yPthjEkDPwEuAH5sjLnPWruzWIUbKYwxRwBvAfYBPcAxxpjjrbVPFbdkQ+bvgDpgfbELIoQQYmwjDbQQQohRh7W2Hfg0jiA5Hji7uCUaMf7R/bwZuNH9XvZaaGvtemvtKmttW7HLIoQQYmwjAVoIIcSoxFq7B3jF/XmAtz/Db/rAoHxJ/W2NMZXGmE8ZY/5ijGk1xnQZY7YYY54xxnzLGDMlIM84Y8wlxpgnjTG7jTHtxpgXXJPk+sQ365yzCviY+/NnwE/d739jjKkNydNvAm2MmeX6eb9hjGlzy39eRtoFxpjfG2N2uMcfNMacEHDOA91zvm6MqTLGXGqMecn1Td9ijPmFMWb/hPc2qE5c/+Mr3J9X+PzgF/vLEnHuUF9mY8wxxpjbjTE7jTH73GfyTzHKW/D6FUIIURrIhFsIIcRoZoL72TmM1/hf4O+BdmAZsB3YD5gDfBFHG7zNS2yMmYXjs32ku/8xoAM4AUcgPNcYc5q1dlfCcrwPmAa8BjxirbXGmBfd6ywCfhuR9wDgaWAv8DAwC1gALDHGfBTn+d0EPAv8EXgTcBrwoDHmOGvtK0EndfO8D3gIWOGe8++AdxljTrHWvpzwHjP5BXCsW5YVbtk8ng3MkQBjzKnAPUAaeBlYDswA/scYc2REvuGqXyGEECWABGghhBCjEjcC90HuzyELVCHXOABHeN4AnGCt3RJQhk0Zvw2wBEe4+h7wZc8s2fXb/jGOFvnbwMcTFscz1f65tdbTqP4MuM49FiVAfxz4L+BfrbW9bnk+DfzAzT8OuMBae7N7rMI934eBLzNgOp7JATjC53xr7YtuvmqcCYePAb8CTkx4j/1Yaz/uaprfBCy11i7O91x+3Lr4DU75rwK+6j1TV7D+fUi+4axfIYQQJYBMuIUQQowqjDETjTHnALfhvOeexdGqDgdT3c9n/MIzgLX2WWvt1oxd7wLeCjwOfC7Tp9f12/4UsBW4wBgzMW4hjDHTgHcDFkcz6/ErnGBiZ4SZrLusAy7xhGeXHwM7cLTRf/CEZ7esfcA17s/TI877DU94dvN1AZ8FWoETjDELou+saJwHNAFrgK9lTEhgrX0Y+FFIvmGpXyGEEKWDBGghhBCjgQczfFl3AnfgaJ+fARa6At9wsArYA7zXGPMVVyMdxXvcz1uDymSt3Qc8hWMhNsi/OIK/d/Pcb63tj1TtCvW/BwzRGs8HXOE2syy9wOvuzz8E5Fntfs6MOO+v/Tusta3AXe7P0yLyFpNT3c8bfZMKHr8KyTdc9SuEEKJEkAAthBBiNJC5DvSPgcXAmcDx1tp1w3VRN1DZ/8Pxf/4P4HVjzEZjzM3GmI8HBO862P28zhf0ymZMAHhC2KDgYxF83P38WcAxb9/HXRPjIDaG7N8bdtxa6x2rCcnbYq1tCTn2uvs5K+R4sfHKtTbk+Osh+4erfoUQQpQI8oEWQggxGshaB3qIJJpcttbeYoz5E/AB4BScQFnnudtiY8zbrbUb3OSV7ufDhAthHrEEf2PM24Aj3J9fMMZc6EvivesPwJlU+FPAaXJp6IdLgx8Y/XqkcH258yGs3AWvXyGEEKWFBGghhBBjDc9UOWw5oVxm2INwNa2eBhxjzBzgJzj+wdcAH3WTeoL0zdba7ye9TgiZ6zwfHyNtkAA9HDQaYxpck20/B7qfmwKOFZJ867rZ/Tww5PhBIfuHo36FEEKUEDLhFkIIMdbwhKPD/QeMMUcDs4d6AWvtGhyTbnCiRHvc435+aKjXAGe9YeB89+fbrbUmaAOOctOca4xpLMS1Y3KBf4cxpgFnaStwlrcaCp6AHKYQ2OammWwC1uNmwJzajxd07iPGmMqA44Puy6Wg9SuEEKL0kAAthBBirHG/+3mJMcZbJxpjzGzg5zgBt2JhjJlvjPmwu0SRn/e7n5mmuktx1ls+1RjzI2PMpIBzHmyM+UzMInwIGI/jq/toWCI3EvYzQC0D2vCR4HJjjGdejjEmhbNcVgPwtLV22RDP702GHBF00FrbDTzi/rwy0wfcGHMycGXIeW8B3gAOwTHD9+f7dEi+QtevEEKIEkMCtBBCiLHG93HXbQZeNsbcZox5AHgJ2A38JcG5DgBuBLYbYx4xxvzWGHOLMWYN8DmcCN2Xe4ndyMwLgeeAT+IEHXvEGPN/xpg/GmNexl06Keb1PfPtX2cutRSCFzn6/0WmKhzrcZ7ls8aYe4wxNwKv4kQM3w78XQGucS/QBiwyxvzZGPMzY8wN7jJmHpfjaKE/BbzgBnj7K46W+QdBJ3WXn/oY0AH8G/CiW7cPuvl+HJKv0PUrhBCixJAALYQQYkxhrd2FE+jrNzimv+/Fibp8Hc46vt0JTvc4cBnwZ/ccC4F34Ah13wKOsdY+5bv+RuBEnPWQl+OYV38QOBpH4P4msCjXhV0/67e7PwctFxXA/+GsCf1mY8y8GOmHisUxL/8GTnTqhUAap6wnZK4PnfcFrN2MYw7+EDAPRzj/R+C4jDR/wQmedj+Oeb5ntv131tpQQdZa+wBwEnAnMN0t/0TgM9baL0bkK0j9CiGEKE1M7glrIYQQQoh4GGMOxDEpX2etPbCohRFCCCEKjDTQQgghhBBCCCFEDCRACyGEEEIIIYQQMZAALYQQQgghhBBCxEA+0EIIIYQQQgghRAykgRZCCCGEEEIIIWIgAVoIIYQQQgghhIiBBGghhBBCCCGEECIGEqCFEEIIIYQQQogYSIAWQgghhBBCCCFiIAFaCCGEEEIIIYSIwf8HPqNU4aUw2zcAAAAASUVORK5CYII=\n", - "text/plain": [ - "" - ] - }, - "metadata": {}, - "output_type": "display_data" - } - ], - "source": [ - "expt_cfg={\n", - " \"start\":0, \"step\":100, \"expts\":300, \"reps\": 400\n", - " }\n", - "config={**hw_cfg,**readout_cfg,**qubit_cfg,**expt_cfg} #combine configs\n", - "\n", - "areset=ActiveResetProgram(soccfg, config)\n", - "expt_pts,avgi,avgq = areset.acquire(soc, threshold=readout_cfg[\"threshold\"], readouts_per_experiment=2, save_experiments=[0,1], load_pulses=True, progress=True)\n", - "\n", - "subplot(111,title=\"Active Reset\", xlabel=\"Pulse Amplitude\", ylabel=\"Qubit Population\")\n", - "plot(expt_pts,avgi[0][0],'o-', label=\"pre-reset\")\n", - "plot(expt_pts,avgi[0][1], 'o-', label=\"post-reset\")\n", - "legend();" - ] - } - ], - "metadata": { - "kernelspec": { - "display_name": "Python 3", - "language": "python", - "name": "python3" - }, - "language_info": { - "codemirror_mode": { - "name": "ipython", - "version": 3 - }, - "file_extension": ".py", - "mimetype": "text/x-python", - "name": "python", - "nbconvert_exporter": "python", - "pygments_lexer": "ipython3", - "version": "3.8.2" - }, - "toc": { - "base_numbering": 1, - "nav_menu": {}, - "number_sections": true, - "sideBar": true, - "skip_h1_title": false, - "title_cell": "Table of Contents", - "title_sidebar": "Contents", - "toc_cell": false, - "toc_position": { - "height": "775px", - "left": "66px", - "top": "111.441px", - "width": "324.41px" - }, - "toc_section_display": true, - "toc_window_display": true - } - }, - "nbformat": 4, - "nbformat_minor": 2 -} diff --git a/qick/qick_demos/07_Sweep_ND_variables.ipynb b/qick/qick_demos/07_Sweep_ND_variables.ipynb deleted file mode 100644 index 48c720b..0000000 --- a/qick/qick_demos/07_Sweep_ND_variables.ipynb +++ /dev/null @@ -1,524 +0,0 @@ -{ - "cells": [ - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "#
Sweeping over multiple variables demonstration\n", - "\n", - "###
This notebook demonstrates how to run a ND variable sweep using the NDAveragerProgram.\n", - "\n", - "When running parameter sweep experiments, to cancel the effect of slow drifting of room temperature electronics, we usually prefer to run all the sweeps in the fast FPGA program, and put the repetition as the last iteration axis. \n", - "\n", - "In this notebook, we show how to run a 2D sweep over both \"phase\" and \"gain\" of a generator channel in one qick program. i.e. for each phase value in the \"phi_list\", the gain value will be swept over all the values in \"g_list\", then the whole 2D parameter sweep will be repeated for \"reps\" number of times, all in qick program." - ] - }, - { - "cell_type": "code", - "execution_count": 1, - "metadata": {}, - "outputs": [ - { - "data": { - "application/javascript": [ - "\n", - "try {\n", - "require(['notebook/js/codecell'], function(codecell) {\n", - " codecell.CodeCell.options_default.highlight_modes[\n", - " 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n", - " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", - " Jupyter.notebook.get_cells().map(function(cell){\n", - " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", - " });\n", - "});\n", - "} catch (e) {};\n" - ] - }, - "metadata": {}, - "output_type": "display_data" - }, - { - "data": { - "application/javascript": [ - "\n", - "try {\n", - "require(['notebook/js/codecell'], function(codecell) {\n", - " codecell.CodeCell.options_default.highlight_modes[\n", - " 'magic_text/x-csrc'] = {'reg':[/^%%pybind11/]};\n", - " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", - " Jupyter.notebook.get_cells().map(function(cell){\n", - " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", - " });\n", - "});\n", - "} catch (e) {};\n" - ] - }, - "metadata": {}, - "output_type": "display_data" - } - ], - "source": [ - "# Import the QICK drivers and auxiliary libraries\n", - "from qick import *\n", - "from qick.averager_program import QickSweep\n", - "import matplotlib.pyplot as plt\n", - "import numpy as np" - ] - }, - { - "cell_type": "code", - "execution_count": 3, - "metadata": {}, - "outputs": [], - "source": [ - "# Load bitstream with custom overlay\n", - "soc = QickSoc()\n", - "# Since we're running locally on the QICK, we don't need a separate QickConfig object.\n", - "# If running remotely, you could generate a QickConfig from the QickSoc:\n", - "# soccfg = QickConfig(soc.get_cfg())\n", - "# or save the config to file, and load it later:\n", - "# with open(\"qick_config.json\", \"w\") as f:\n", - "# f.write(soc.dump_cfg())\n", - "# soccfg = QickConfig(\"qick_config.json\")\n", - "soccfg = soc\n", - "# print(soccfg)" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### Hardware Configuration\n", - "\n", - "tProc channel 7 : DAC 229 CH3 <-> Readout channel 0 : ADC 224 CH0" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### Example 1: 2D sweep over gain and phase" - ] - }, - { - "cell_type": "code", - "execution_count": 4, - "metadata": {}, - "outputs": [], - "source": [ - "class NDSweepProgram(NDAveragerProgram):\n", - " def initialize(self):\n", - " cfg = self.cfg\n", - " res_ch = cfg[\"res_ch\"]\n", - "\n", - " self.declare_gen(ch=cfg[\"res_ch\"], nqz=1, ro_ch=cfg[\"ro_chs\"][0])\n", - "\n", - " for ch in cfg[\"ro_chs\"]:\n", - " self.declare_readout(ch=ch, length=self.cfg[\"readout_length\"],\n", - " freq=self.cfg[\"pulse_freq\"], gen_ch=cfg[\"res_ch\"])\n", - "\n", - " # convert frequency to DAC frequency (ensuring it is an available ADC frequency)\n", - " freq = self.freq2reg(cfg[\"pulse_freq\"], gen_ch=res_ch, ro_ch=cfg[\"ro_chs\"][0])\n", - " phase = self.deg2reg(cfg[\"phi_start\"], gen_ch=res_ch)\n", - " gain = cfg[\"g_start\"]\n", - "\n", - " self.set_pulse_registers(ch=res_ch, style=\"const\", freq=freq, phase=phase, gain=gain, length=cfg[\"length\"])\n", - " \n", - " # ---------- sweep defination starts from here -----------------\n", - " # get gain and phase registers of the generator channel (check 04_Reading_Math_Writing for more details about QickRegister object)\n", - " self.res_r_gain = self.get_gen_reg(cfg[\"res_ch\"], \"gain\")\n", - " self.res_r_phase = self.get_gen_reg(cfg[\"res_ch\"], \"phase\")\n", - "\n", - " # add pulse gain and phase sweep, first added will be first swept\n", - " self.add_sweep(QickSweep(self, self.res_r_gain, cfg[\"g_start\"], cfg[\"g_stop\"], cfg[\"g_expts\"]))\n", - " self.add_sweep(QickSweep(self, self.res_r_phase, cfg[\"phi_start\"], cfg[\"phi_stop\"], cfg[\"phi_expts\"]))\n", - "\n", - "\n", - " self.synci(200) # give processor some time to configure pulses\n", - "\n", - " def body(self):\n", - " self.measure(pulse_ch=self.cfg[\"res_ch\"],\n", - " adcs=self.ro_chs,\n", - " pins=[0],\n", - " adc_trig_offset=self.cfg[\"adc_trig_offset\"],\n", - " wait=True,\n", - " syncdelay=self.us2cycles(self.cfg[\"relax_delay\"]))\n", - "\n", - "# unlike the RAveragerProgram, here we only have initialize() and body() part in the program, and the register update \n", - "# parts (which will be run after each body) are programed in QickSweep objects. " - ] - }, - { - "cell_type": "code", - "execution_count": 5, - "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "\n", - "// Program\n", - "\n", - " regwi 3, $22, 936228570; //freq = 936228570\n", - " regwi 3, $23, 0; //phase = 0\n", - " regwi 3, $25, 100; //gain = 100\n", - " regwi 3, $26, 589874; //stdysel | mode | outsel = 0b01001 | length = 50 \n", - " synci 200;\n", - " regwi 0, $13, 0;\n", - " regwi 0, $14, 99;\n", - "LOOP_rep: regwi 3, $23, 0; //'gen6_phase' <= 0 (0 deg)\n", - " regwi 0, $16, 50;\n", - "LOOP_gen6_phase: regwi 3, $25, 100; //'gen6_gain' <= 100 \n", - " regwi 0, $15, 100;\n", - "LOOP_gen6_gain: regwi 0, $31, 16385; //out = 0b0100000000000001\n", - " seti 0, 0, $31, 150; //ch =0 out = $31 @t = 0\n", - " seti 0, 0, $0, 160; //ch =0 out = 0 @t = 0\n", - " regwi 3, $27, 0; //t = 0\n", - " set 7, 3, $22, $23, $0, $25, $26, $27;//ch = 6, pulse @t = $27\n", - " waiti 0, 290;\n", - " synci 720;\n", - " mathi 0, $13, $13 + 1;\n", - " memwi 0, $13, 1;\n", - " mathi 3, $25, $25 + 100; // 'gen6_gain' <= 'gen6_gain' + 100 \n", - " loopnz 0, $15, @LOOP_gen6_gain;\n", - " mathi 3, $23, $23 + 85899345; // 'gen6_phase' <= 'gen6_phase' + 85899345 (7.2 deg)\n", - " loopnz 0, $16, @LOOP_gen6_phase;\n", - " loopnz 0, $14, @LOOP_rep;\n", - " end ;\n" - ] - }, - { - "data": { - "application/vnd.jupyter.widget-view+json": { - "model_id": "2bccf4fdedbe4ecab02e0c055228d5ea", - "version_major": 2, - "version_minor": 0 - }, - "text/plain": [ - " 0%| | 0/515100 [00:00" - ] - }, - "metadata": { - "needs_background": "light" - }, - "output_type": "display_data" - }, - { - "data": { - "image/png": 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sVf3lRCskaWE4h7k51pLUYVPJsX498GrgDYOFSU4A/gXwyYGyU4HzgCcAjwbeneSUqur+Xw5JmrGqfqSC7Jp3BSRpPlYD63G2Ld6x6n3A3UNe+m3gl9qTrjoXeHNV3VtVtwG3Amdu88NI0uJb2T/+NmNL2GPtrCCSYFazgiR5NvDpqvpIHry6x3HABwee723LpA2ZDrC8ln5xoCpqv7OCSFKHjR1YH53kuoHne6pqz0Y7JzkMeBnw9GEvDykzbJKkjZhj3UUOXpQE2+yx3ldVZ4yx/zcDJwGrvdXHAx9OciZND/UJA/seD9wxboUkaSlUk2fddUsYWEsSzCIVpKpuAI5ZfZ7kduCMqtqX5Ergj5L8Fs3gxZOBa6daIUnqrXJJc0nqrqlMt/cm4GyalJG9wMur6rVDz151U5IrgI+1FXmRM4JI0gYKasUc6w5aAb4870pI6oTJxrFV9fwtXj9xzfNLgEsmWgkttKUfwKYlZo+1JHXYbGYFkSRNgD3WktRlBtaS1B8FTrfXRc5jLQkMrCWpP8oea0nqMgNrSeoPF4jpqBWcx1qSgbUk9YzzWEtSlxlYS1IvmAoiSV1mj7Uk9Untt8e6g1Zw8KIkLbZk17yrIGmSqqAHPdZzaXmS/HySm5LcmORNSQ5JclSSq5J8ov155MD+Fye5NcktSZ4xUP6kJDe0r70qcep8SaNa7bEeZ1tOttmSuqD2r4y9zdrMA+skxwE/C5xRVacBu4HzgIuAq6vqZODq9jlJTm1ffwJwDvD7SXa3b/ca4ELg5HY7Z4YfRVKvGViPwjZbUhc00+3V2NuszSsV5ADg0CT3A4cBdwAXA2e3r18OvAd4KXAu8Oaquhe4LcmtwJlJbgeOqKoPACR5A/Ac4J2bn9pZQSSBOdZjmWObvT1V3b9lLI2jBxNiTFn1Isd65j3WVfVp4DeBTwJ3Av9YVe8CHllVd7b73Akc0x5yHPCpgbfY25Yd1z5eWy5JI7LHeiu22ZI6oZ0VZNxt1uaRCnIkTY/GScCjgYck+ZHNDhlSVpuUDzvnhUmuS3Ld5z63nH8cJa1lKsgo5t1m3/35u8etsqRFVdvYZmweqSBPA26rqs8BJHkb8F3AZ5McW1V3JjkWuKvdfy9wwsDxx9PchtzbPl5bvk5V7QH2AJxxxqHlrCCSTAUZ2Vzb7NNPO31bfxqdFUSLZumH+lY/ptubR8vzSeCsJIe1I8KfCtwMXAmc3+5zPvD29vGVwHlJDk5yEs2Al2vbW4/3JDmrfZ8XDBwjSVuwx3pEttmSOqB6kQoy8x7rqromyVuBD9P8pfprmp6Jw4ErklxA05A/t93/piRXAB9r939RVe1v3+6FwOuBQ2kGwIwwCGYF+PLA891D9tk/pKxvFvVzbdeo18PrNlvzvN72WI9i/m22JHDwYsFcZvkY11xmBamqlwMvX1N8L01PyLD9LwEuGVJ+HXDaxCsoaUn4pWkUttmS5q6gZtxkJ3kl8K+A+4C/BX68qr6w2TEmoUlaUqaCSFKfzGEe66uA06rqdOBvaKYZ3dSSLmnuPNaSTAWRFlEte87EoqrZp4K0U4uu+iDwQ1sds4SBtSSBgbUk9UcBK/OdFeQngLdstZOBtaQlZmAtSb2w/Xmpj05y3cDzPe2UngAkeTfwqCHHvayq3t7u8zKaPxhv3OpkSxhYr+A81pLssZYWU5Z+wudFte2c6X1VdcaG71r1tM0OTnI+8CzgqTVCntESBtaSBAbWktQvs56WOsk5wEuBf15VXxnlmCUMrB28KAkMrBdb1ewXhpCmaek74uez8uKrgYOBq9o7IR+sqp/e7IAlDKwlaTqSXEZzy/CuqjqtLdtwHtQkFwMX0Eyo/bNV9ZdzqbgkdVyzQMyMz1n1+HGPcR5rScur9o+3be31wDlryobOg5rkVOA84AntMb+fZNhSlJKkgpWVGnubteXrsS7gPldbk0STGTZBVfW+JCeuKdtoHtRzgTdX1b3AbUluBc4EPjDZWi2nxH4jadH0IcNr+QJrSYLmS/bsv2MPzoN6HE2gvWpvWyZJWqMKVnrQL2pgLWk5bS+w3nQ+1M0MmQd12FAkl4yTpI30YFXN5QusR5kUZF5Zjmv/yJttuZ7XaHqGBZmLfn3Hv6246XyoG9lgHtS9wAkDux0P3DF2jSRpGdTsp9vbDpPQJC2n1R7rcbZtGJgH9dlr5kG9EjgvycFJTgJOBq7d3lkkafHVyvjbrC1fj7UkrZpwo5vkTcDZNCkje4GX08wCsm4e1Kq6KckVwMdoUkReVDXa1COStGyKfvRYL19gXcD9W+yz1euz0pV6dJnXaLoW+fpOYfBiVT1/SPFrN9n/EuCSydZC0iLqQXrxdPUkFWT5AmtJWmX/sCT1htPtdVHhiuaS2vuK866EJGkUZY+1JHWcPdaS1BsG1pLUVfNZIEaStF09yDNfvsB6lMGLkpZDD3o/JI2nln6U32IyFUSSuswea0nqFQNrSeqyHjTSkqSGgXUXjbKkuaTFZ4+1tJDahZi0YEwFkaQuM7CWpF4xsO4iBy9K0sKrPqwkIY1h2Tvi7bGWpK7rQSMtSWoYWEtSV5kKIkm9stKDmRSXL7B28KKkVQbWktQLRZMO0nXLF1hLEjStdA9uK0qSAHOsJanj7LGWpN4wFaSLClNBJmH3kDKDFPWJPdYLLdk17ypImqAC9vegzV6+wFqSVvllUJL6oeyxlqTuclYQSeqNwhzrbnKBmMnwGmoR9KCR1va4QIy0ePbbYy1JHWWPtST1RmEqSDc5j7WkVQbWC8vBi1vzCqlXynmsJam7nBVEknqjMBVEkrrNHmtJ6g1TQbrIwYuSwB7rBefgxa15hdQnRbG/B7kgyxdYS9Iqe6wlqTf60GPt2AVJy2l1VpBxti0kuSzJXUluHCg7KslVST7R/jxy4LWLk9ya5JYkz5jch5OkxVLV5FiPu83a8vVYu6S5pOl5PfBq4A0DZRcBV1fVpUkuap+/NMmpwHnAE4BHA+9OckpV2Y8+Ac4KokXTgyyIqVvpwUWw5ZG0vFbG3LZQVe8D7l5TfC5wefv4cuA5A+Vvrqp7q+o24FbgzO1/GElaXKuzgsyyxzrJryf5aJLrk7wryaO3OsbAWtJymkIqyAYeWVV3ArQ/j2nLjwM+NbDf3rZMkjREbeO/HXplVZ1eVU8E/gz41a0OWL5UkBXgvnlXQtLcbW/lxaOTXDfwfE9V7dlmDbJBrSRJQ8w6Z7qqvjjw9CGM0EbPpcc6ycOTvDXJx5PcnOR/284AnyRPSnJD+9qrkgz7QyVJw42fCrKvqs4Y2EYJqj+b5FiA9uddbfle4ISB/Y4H7tjpR5oW221J89SkgtTYG22HyMB24TjnTXJJkk8BP0yHe6x/B/iLqvqhJAcBhwG/zPgDfF4DXAh8EPhz4BzgnZueuYB7p/OhJPXI9nqst+NK4Hzg0vbn2wfK/yjJb9G0bScD186kRtszv3ZbGkP1YIDbdiz9V9Da9uDFfVV1xkYvJnk38KghL72sqt5eVS8DXpbkYuBngJdvdrKZB9ZJjgCeAvwYQFXdB9yX5Fzg7Ha3y4H3AC9lYIAPcFuSW4Ezk9wOHFFVH2jf9w00g4JsoCWNZsIrZCR5E007dnSSvTQN8KXAFUkuAD4JPBegqm5KcgXwMeAB4EVdnRHEdlvSvBXF/ilky1XV00bc9Y+Ad9C1wBp4HPA54HVJvh34EPAS1gzwSTI4wOeDA8evDvC5v328tnydttv/QoDHHDW5DyKpx6bQY11Vz9/gpadusP8lwCWTrcVUzLTdHmyzj3u04zklfSMVZJaSnFxVn2ifPhv4+FbHzCOwPgD4TuDFVXVNkt+huX24kY0G+Iw88KfNg9wDcMZjUs5jLQlw5cXRzbTdHmyzTz/t9MW8r6+pWdS0/QXNcBnLHOaxvjTJt9Dc3/x74Ke3OmAegfVeYG9VXdM+fytNA/3ZJMe2vR6jDPDZ2z5eWy5JWysmngqywGy3Jc1Vc5NxtoF1Vf3guMfMfFaQqvoM8Kn2GwA0t0g/xjcG+MD6AT7nJTk4yUm0A3za24/3JDmrHVX+goFjJGlrs5nHuvdstyV1QW1jm7V5zQryYuCN7cjyvwN+nCbIH3eAzwtplhA+lGbwy9YDYIomy0/ScrPHelzza7clidnnWG/HXALrqroeGDb1yVgDfKrqOuC0ydZO0tJY4l7ocdluS5qnoljpwRpay7fyYoGDFyXNcB5rSdqxBR2TObJ5zAqyHcsXWEvSKlNBJKk37LGWpK6yx1qSeqPKHutuWgHum3clJM2dgbWW3MynBdOO9CCmnDp7rCVJkqQdq3ksEDM2A2tJy8sca0nqhWaGVAPr7ing3nlXQtLcmQoiLaTqQa+mtsfAWpK6zB5rSeoFe6wlqcvssZakXjHHuotWcIEYbWzYMHl7NReXgbWW2KI2bVnQlVQW9GONYcFWXkxyHPDYwWOq6n3TqJQkTV1zX3Fh2WZLWiQLlQqS5D8A/xr4GN/o4ymgf4104TzWkhoL2mO9UG32NlUt8LcmLaUeZEFMXR8uwag91s8BvqWqnE9D0mJY7Bxr22xJC2dheqyBvwMOxInqJC2Sxe3UtM2WtFCKxeqx/gpwfZKrGWioq+pnp1KraXIea0mw6D3Wi9Nmb1Pigt1aLA5ehOpBaD1qYH1lu0nS4ljcHmvbbEkLp3rw5WKkwLqqLp92RSRppha4x9o2W9Ii6n2PdZIrqup5SW5gSGpLVZ0+tZpNi7OCSFq1YIH1QrbZmhqTZfpl2WcFKWBlAXqsX9L+fNa0KyJJM7WY81jbZktaTFmAVJCqurP9+fezqc4MuPKipFVT6LFO8vPA/0ETut8A/DhwGPAW4ETgduB5VfX5SZ97IdtsTc3ifa+U5m+kO0FJzkryv5J8Kcl9SfYn+eK0KydJU7OaYz3OtoV2tcOfBc6oqtOA3cB5wEXA1VV1MnB1+3xqbLMlLZyC1K6xt1kb9YyvBp4PfAI4lKY35nenVSlJ6rEDgEOTHEDTU30HcC6wOqDwcpoFXKbJNlvS4qmMv83YqNPtUVW3JtldVfuB1yX5/6ZYr+kp4P55V0JSJ0z4XnhVfTrJbwKfBL4KvKuq3pXkkQNpGncmOWayZx5al8Vos6Ux1bKP8ltQAUL3k6xHXiAmyUHAR5L8BnAn8JDpVUuSpmx70+0dneS6ged7qmrP6pMkR9L0Tp8EfAH44yQ/ssOabodttqQFk7mkdoxr1MD6R2nSRl4E/DxwPPCD06qUJE3d9mYF2VdVZ2zy+tOA26rqcwBJ3gZ8F/DZJMe2vdXHAndto8bjsM2WtHDSg0kit5rH+lzg+Kr6vfb5e4FjaP4kfQC4deo1nDRnBZG0avKzgnwSOCvJYTSpIE8FrgO+DJwPXNr+fPvEz8yCttl6ELMcthbX/l5QYVffA2vgl2hGtK86GHgScDjwOuCtU6qXJE3XFFZerKprkrwV+DDwAPDXwB6aNvOKJBfQBN/PneyZv842W9JCanKs+x9YH1RVnxp4/v6quhu4O4n5epL6bQoT+VbVy4GXrym+l6b3etpssyUtrEUIrI8cfFJVPzPw9BGTr84MFKaCSJpKj3UHLF6brQcxy0HLK+xi97wrsaWtQv9rkvzk2sIkPwVcO50qSdKMTHiBmA6wzZa0wLKNbba26rH+eeC/Jfk3NDmD0OTrHcz0FziYDuexlgTbnRWk6xavzZYkmjmsez94saruAr4ryfcBT2iL31FVfzX1mknStPWjF3pkttmSFlnmlAqS5BeBVwKPqKp9m+070jzWbaNswyxpcSxmjzVgmy1pEYVdmX1gneQE4F/QzOi0pZGXNF8YzmMtadWC9VjrG6oW9FuTtKQyv8GLv00zlelI6w8sX2AtSbCos4JI0sKadSpIkmcDn66qj4y68JCBtaTlZaemJPXEtlNBjk5y3cDzPVW15+vvmrwbeNSQ414G/DLw9HFOtnyBtbOCSAJ7rBdc0v3ZAySNLgm7sq2wdV9VnbHRi1X1tA3O90+Ak4DV3urjgQ8nObOqPrPR+y1fYC1JYGAtST2TGc5LXVU3AMd8/dzJ7cAZE5kVZKE4eFGSpIVVVfOuwlS46mbI9nqsZ6r7NZSkadsdJa0AABnmSURBVDHHWpJ6Y55LmlfViaPsZ2AtaTmZCiJJvZE5zWM9ruULrAtTQSQ17LGWFs6o06L1zYJmuIzBVBBJ6i57rCWpPwK7dtljLUndZWAtSb0Qe6w7ynmsJUHTFpgKoiW2qDN9L+qsIArpQY713P6/SrI7yV8n+bP2+VFJrkryifbnkQP7Xpzk1iS3JHnGQPmTktzQvvaqLGpilaTp2D/mtsRssyXNW7Jr7G3W5vmF9SXAzQPPLwKurqqTgavb5yQ5FTgPeAJwDvD7+cZXltcAFwInt9s5s6m6pN5bzbE2sB6Vbbak+UnIrt1jb7M2l1SQJMcD/xK4BPh3bfG5wNnt48uB9wAvbcvfXFX3ArcluRU4s10B54iq+kD7nm8AngO8c9OTu0CMpFWmgoxkrm22JAEBp9vbxH8Cfgl46EDZI6vqToCqujPJ6jKSxwEfHNhvb1t2f/t4bbkkbc1ZQcZhmy1pzjKXHuhxzTywTvIs4K6q+lCSs0c5ZEhZbVI+7JwX0tx+5DHBwYuSGvZYb2nebfZxjzb2lgQEA+sNfDfw7CTPBA4Bjkjyh8Bnkxzb9nwcC9zV7r8XOGHg+OOBO9ry44eUr1NVe4A9AGfsjsOFJdljPbq5ttmnn3a6bbYkmomsux9Yz3zwYlVdXFXHt2uunwf8VVX9CHAlcH672/nA29vHVwLnJTk4yUk0A16ubW9B3pPkrHZk+QsGjpGkrTl4cUu22ZK6wcGL47oUuCLJBcAngecCVNVNSa4APgY8ALyoqlb/xL0QeD1wKM0AmK0HwbikuSRwHuudm02bralZ1F9/Z3FcTDEVZGtV9R6akeRU1T8AT91gv0toRqOvLb8OOG16NZS00KbQC53k4cB/oWmbCvgJ4BbgLcCJwO3A86rq85M/+3TZZkuaqx58aVrUhZckaXPTm8f6d4C/qKpvBb6dZu7noXM+S5JGlJDdu8feZq1LqSCzUbB/YFaQYZd8J51Yk36/ab//tOs7j3OO+r/RqOec9PuN8v7D3mu7120W12OSn32Yqf1OTvheeJIjgKcAPwZQVfcB9yXZaM5nSdKIsqv7/cHLF1hL0vQ8Dvgc8Lok3w58iGbFwo3mfJYkjSRgYN09xYOnsZ70lNbTniK7b/Wdxzn7do1Gff/t1qPL12PeU8pvoyf86CTXDTzf004Nt+oA4DuBF1fVNUl+B9M+JE1AD9KLpyvMJbVjXEsXWEsSbHsa631VdcYmr+8F9lbVNe3zt9IE1hvN+SxJGkk/eqy7X0NJmpKVMbetVNVngE8l+Za26Kk0085tNOezJGkUoQmsx91mbOl6rFdwGmtJU1148cXAG5McBPwd8OM0nRjr5nyWpFHV0q9BGrK7+/3BSxdYS9KqaSyQUVXXA8PSRYbO+SxJGkHoRaK5gbWkpTTFHmtJ0jTsMrDunLWzgkhaTgbWi61qURfs1rLqQWftdCVgKogkdZehlyT1Q3CBGEnqLHusJalHAuzufrf90gXWzgoiaZWBtbR4akGnz1jQjzWGfsxjvXSBtSRB02NtKogk9YQ91t3k4EVJq+yxXlxJ93u2NB1Z+lF+C8wea0nqJnusJalnnG5PkrrLHmtJ6onEwLqLCgcvSnJWEGlRLergRWFgLUldZiqIJPVEIAbWkiRJ0gQ4K0j3OI+1NNywsdaL3KNrKoikZdXLbJnQi1SQ7s9bIklTsBpYj7NJkuYlTY/1uNtOzpi8Ismnk1zfbs/c6pil67F2HmtJqxa5R16SNtLLqb7n12P921X1m6PuvHSBtSSBqSCS1DumgkhSd62MuUmS5ijb2HbuZ5J8NMllSY7cauel67F28KIksMdaknolbDdn+ugk1w0831NVe77+tsm7gUcNOe5lwGuAX6f5k/HrwH8EfmKzky1dYC1JqwysJak/tjmP9b6qOmOjF6vqaSOdO/kD4M+22s/AWtJSKkzvkKTemMOS5kmOrao726c/ANy41TFLF1gXcN+8KyGpE+yxXlxVfm1aVunllBcayewXiPmNJE+kCR9vB35qqwOWLrCWJDDHWpJ6Jcx8yo2q+tFxjzGwlrS07NOUpP7YZo71TC1dYF3AvfOuhKS5s8daknqkJ0uaL11gLUmr7LGWpB7pfly9fIH12sGLk/7DOiz9xz/e2zPJa9nlf5dR6zbtzzDp9x/l/eb57zLNHusku4HrgE9X1bOSHAW8BTiRZgDM86rq81M6vYDE9c+WVVXNuwqakuyedw22ZssjaWntH3Mbw0uAmweeXwRcXVUnA1e3zyVJo1pNBRl3mzEDa0lLaXUe60kvaZ7keOBfAv9loPhc4PL28eXAc3ZYfUlaKgGya/xt1pYuFcQlzSXtwKZL47b+E/BLwEMHyh65ushAVd2Z5Jgp13PpOY/18nIe6wWVOCuIJHXZNnKsN10aN8mzgLuq6kNJzt5+zSRJ6/Qgz8LAWtJSmtLgxe8Gnp3kmcAhwBFJ/hD47OrSuEmOBe6a/KklabHZY91BKziPtaTGpJMFqupi4GKAtsf6F6vqR5K8EjgfuLT9+fYJn1prOCvI8nJWkAWVfswKsnSBtSTBzBeIuRS4IskFwCeB587u1JK0ILrfYW1gLWk5rc4KMrX3r3oP8J728T8AT53i6SRpscVUkE5au0CMpOXlkuaLa1FnBVnULIdMsCtyUWcFWdCPNbLV6fa6bukCa0mCmaeCSJJ2yB7rDiqcx1pSYzH7NNU1C9p5PlHFgnbFa3ICu3rQYz3zKiY5Icl/T3JzkpuSvKQtPyrJVUk+0f48cuCYi5PcmuSWJM8YKH9Skhva116VRb3/I2niVnusp7Sk+UKx3ZbUBX1YeXEesf8DwC9U1bcBZwEvSnIqcBFwdVWdDFzdPqd97TzgCcA5wO8nX59w5TXAhcDJ7XbOLD+IpH4zsB6Z7bakuUo7eHHcbdZmngrSLuu7urTvPUluBo4DzgXObne7nGY0/Uvb8jdX1b3AbUluBc5McjtwRFV9ACDJG4DnAO/c9PzA/ZP9SJJ6aNqzgiySebfbfdeHAVdSH/Th/6W55lgnORH4DuAa4JFt4027Otkx7W7HAR8cOGxvW3Z/+3htuSSNZMl7obfFdlvSvPQhcWxugXWSw4E/AX6uqr64SZrdsBdqk/Jh57qQ5tYjDx+/qpIWkD3W45tVuz3YZh/3aONuSfRm8OJcAuskB9I0zm+sqre1xZ9Ncmzb63EscFdbvhc4YeDw44E72vLjh5SvU1V7gD0AxyXlrCCSwB7rccyy3R5ss08/7fRtTRfhkuZaNIs6h/mownxypsc1j1lBArwWuLmqfmvgpSuB89vH5wNvHyg/L8nBSU6iGexybXv78Z4kZ7Xv+YKBYyRpU84KMjrbbUldsGvX+NuszaPH+ruBHwVuSHJ9W/bLwKXAFUkuAD4JPBegqm5KcgXwMZqR6S+qqtW/cS8EXg8cSjP4ZcsBMCs4j7WkhqkgI5tru70di7ry4qKa5MqLnTHhj9SH/OKpMhVkuKp6Pxv/uj11g2MuAS4ZUn4dcNrkaidJWst2W9K8NUuad//bxdKtvChJ4JLmktQr9lh3k/NYSwID60Xn4MXpcgnyEXiJJs7AWpI6zCxcSeqH0I88cwNrSUvJHmtJ6pHALnOsu6dwVhBJDXusF1eXZgXpUFUmZiFn8Zg0L9HE9SCuXr7AWpLAHmtJ6pNgjrUkdZqBtST1RGB3D7qsly6wdlYQSdC0BQt4h15SV0x4VhCXNLfHWpI6zR5rSeoJBy92k0uaSwJzrKWdmPQ81gs5L/aCLmk+r9g2wO4e9Fj3oIqSNB0rY26SpPlJxt92fs68OMktSW5K8htb7b90PdaSBPZYS1K/hF0z7rZP8r3AucDpVXVvkmO2OmbpAmsHL0paNele6CQnAG8AHtW+/Z6q+p0kRwFvAU4EbgeeV1Wfn/DppU11efBbZ+bF7kq+xQTr0Zlru0PJXFJBXghcWlX3AlTVXVsdYCqIpKW02mM9zjaCB4BfqKpvA84CXpTkVOAi4OqqOhm4un0uSRpRk2OdsbcdOgX4niTXJHlvkidvdcDS9VhL0qpJp4JU1Z3Ane3je5LcDBxHcyvx7Ha3y4H3AC+d8OklaXFl29PtHZ3kuoHne6pqz9ffNnk3zV3GtV5GEycfSdNR8mTgiiSPq9r4/s/SBdYuaS4Jpj+PdZITge8ArgEe2QbdVNWdo+TpSZqDruTLDK3HYqR0bFeA3dtLkdlXVWds9GJVPW3DcyYvBN7WBtLXJlkBjgY+t9ExSxdYS9IObNrzsSrJ4cCfAD9XVV9MV/I2JanH5pBj/d+A7wPek+QU4CBg32YHLF1g7TzWklZtIxVk054PgCQH0gTVb6yqt7XFn01ybNtbfSyw5QAYzc8md3l7bRG/3018YN4CXqRFmSM881nS/DLgsiQ3AvcB52+WBgJLGFhLEkxnur00XdOvBW6uqt8aeOlK4Hzg0vbn2yd8aklaeLP+3lNV9wE/Ms4xBtaSltKUcqy/G/hR4IYk17dlv0wTUF+R5ALgk8BzJ39qSVpcO8ixnqmlC6ydx1rSqinMCvJ+Nh5h9NQJn06bSLafjDk0J34Hf9DXVmUHVetMpsKwFIydpGVsN11h2HE7SuUZcuza9xv5U044A2OSGUo7ea+VuWWWTGT6vKlbusBakmD6s4JIkiZnTjnWYzOwlrS0XNJckvrBVJCOclYQSTCdwYvqjqoJ34/Ywb3ztVXZSdW6PGHJTmafmOTsHpOe3rIr02VOsho7ea95dhrPYbq9sS1dYC1Jq0wFkaR+SOyxlqTOssdakvrFHOsOclYQSasMrBdJh3MkOmKis0p05Hp3eoGYjsSAE79GcxLCLnusJambnBVEkvrFVJAOKhy8KKlhj7WG6cqS5pMef7mIJt5z3pF/+67oUhzrdHuS1GH2WEtSfzjdniR1nD3WktQfBtYd1PfBi8MCgd0zr4W0tVGC1nn+7jorSI9N8m79hNdn7kwaSUcGKk77auxkYN5El67f0TL1k6tHHwb3bVfikuaS1GmmgkhSf+xK91eIMbCWtJTssZak/jDHuqMWcUnzPqe2aLn5u6ttGfq39cGFGbVna8it5Z3cmh927HY72YYdN2pcMcpHGLVaw9ItRi8bzfp0k9GSSIalqYyajlMrQ+5ZDTl27ftl2PsPu/01Yh7M0PoOrcfWV3Nl2HFDr9GodRt2jmH7zSYFqgdx9fIF1pIE9lhLUp/YY91Ri9hjLWl7zLHui9r06bDCGnUS6CHdb6P3II5YNkJVhp5ytA7Vka09dli1hvZGDuvxHFI2vLd0NOt7u4f1fq/vYx/aSz7q3YVdo90SWPd+u4ccN6z7f+S7C6PdIVlbNOywYYMXh1+j0eox/BxbHzuV8Dcxx1qSusoea0nqlz7MemJgLWlp2WMtSf0QDKw7qe/zWEuaDHus+2yEBIMR0zmGGjKorUad73r4yK41z0d7q6HVHfFjjfJRdzKAbdQUj5HnwK61qQSjBlDDUgOGpIwMzWkYcXToKHMnj5rOsaOUke3tM0rqxjh2Mkh1pwysJanDDKwlqR9C2DWzEH77DKwlLaXCVBBJ6pMeLLy4fIF14awgkhr2WC+OUebRHTZv8cizhww/6Yi7jVC3naRljJiqsTZLZdR0jpUR9xx1v2HpIaPESyPP9jEk3yK7dq/fccjvQ4bmTWzxfMOKjFg2bLehxz64cFgmy04M++hDZxkZJSVlaj3L3Y+sly6wliQwx1qS+sZUEEnqMFNBJKkfQh/6q5cwsHZWEElgj3WfrE3XWNm/vhVfeeDBSX777/vK+vcZclzdtz45sO67d7Sy+x9YX4/7hpU9+Ddt/33rv9Kt3L8+PWL/kLIHhvwBe2D9KYeXrTnt/UNmMPnakPSIYQu/3Luy/v+eB4Z8Vd0/bCGZIdHR7pUHhyMHcPD6fThoXdkBu4bst3v9ftl94Pqyg9bvx+4hKSNrynLQkH0OGpJ+MqzswPVluw5af0F2HzikbM1pdw3J3ThwyHEHHrC+7KDdw8rW1+3gIdfjwCFpNQeuyUuZ1jIu00sxmZylC6wlaZU91pLUH90PqyGjDKpYJEnuAW6Zdz2Ao4F9864E1qNrdQDrsdZm9XhsVT1iO2+a5C/a9x7Hvqo6Zzvn0/bYZq9jPR6sC/XoQh2gH/WYdZsNM263lzGwvq6qzrAe1qOLdbAe3a2H5qMr//7Ww3p0uQ7WozumlQYjSZIkLRUDa0mSJGkCljGw3jPvCrSsx4N1oR5dqANYj7W6Ug/NR1f+/a3Hg1mPb+hCHcB6dMLS5VhLkiRJ07CMPdaSJEnSxC1VYJ3knCS3JLk1yUUzPO/tSW5Icn2S69qyo5JcleQT7c8jp3Dey5LcleTGgbINz5vk4vba3JLkGVOuxyuSfLq9JtcneeYM6nFCkv+e5OYkNyV5SVs+s2uySR1mej2SHJLk2iQfaevxa235TH8/NqnHzH8/1D3zarPbcy9tu22bPXI9ZnZNbLN7pKqWYgN2A38LPA44CPgIcOqMzn07cPSast8ALmofXwT8hymc9ynAdwI3bnVe4NT2mhwMnNReq91TrMcrgF8csu8063Es8J3t44cCf9Oeb2bXZJM6zPR60Myzf3j7+EDgGuCsWf9+bFKPmf9+uHVrm2eb3Z5/adtt2+yR6zGza2Kb3Z9tmXqszwRuraq/q6r7gDcD586xPucCl7ePLweeM+kTVNX7gLtHPO+5wJur6t6qug24leaaTaseG5lmPe6sqg+3j+8BbgaOY4bXZJM6bGQq16MaX2qfHthuxYx/Pzapx0am9vuhzulamw1L0m7bZo9cj41M42+HbXZPLFNgfRzwqYHne9n8f4xJKuBdST6U5MK27JFVdSc0/9MCx8yoLhuddx7X52eSfLS97bh6+2om9UhyIvAdNN+253JN1tQBZnw9kuxOcj1wF3BVVc3lWmxQD5jj74c6Yd7/1rbb6y11mz2kHjDDa2Kb3Q/LFFgPW2J+VlOifHdVfSfw/cCLkjxlRucdx6yvz2uAbwaeCNwJ/MdZ1SPJ4cCfAD9XVV/cbNdp1WVIHWZ+Papqf1U9ETgeODPJaZtVecb1mNvvhzpj3v/WttsPttRt9gb1mOk1sc3uh2UKrPcCJww8Px64YxYnrqo72p93AX9Kcxvks0mOBWh/3jWLumxy3plen6r6bPs/5wrwB3zj1tBU65HkQJqG8Y1V9ba2eKbXZFgd5nU92nN/AXgPcA5z/P0YrMc8r4c6Y67/1rbbD7bMbfZG9ZjXNbHN7rZlCqz/F3BykpOSHAScB1w57ZMmeUiSh64+Bp4O3Nie+/x2t/OBt0+7Lq2NznslcF6Sg5OcBJwMXDutSqw2BK0foLkmU61HkgCvBW6uqt8aeGlm12SjOsz6eiR5RJKHt48PBZ4GfJwZ/35sVI95/H6oc+bSZoPt9jDL2mZvVo9ZXhPb7B6pDoygnNUGPJNmNO/fAi+b0TkfRzMi9iPATavnBb4JuBr4RPvzqCmc+000t2Tup/nWeMFm5wVe1l6bW4Dvn3I9/itwA/BRmv/xjp1BPf4ZzS2ojwLXt9szZ3lNNqnDTK8HcDrw1+35bgR+davfyxnXY+a/H27d2+bRZrfnXep22zZ75HrM7JrYZvdnc+VFSZIkaQKWKRVEkiRJmhoDa0mSJGkCDKwlSZKkCTCwliRJkibAwFqSJEmaAANrzUyS/UmuT3Jjkj9OcliSE5PcuPXROzrvsUn+bIPX3pPkjG2+77OS/NrOaidJ3WSbLY3PwFqz9NWqemJVnQbcB/z0jM7772hWgpq0dwDPTnLYFN5bkubNNlsak4G15uV/AI9vH+9O8gdJbkryrnY1J5L8ZJL/leQjSf5ktTFM8ty2B+UjSd7Xlu1O8sp2/48m+amBc/0g8BftfocmeXO7z1uAQ1d3SvL0JB9I8uG2d+bwtvyZST6e5P1JXrXak1LNJPDvAZ41zQslSR1gmy2NwMBaM5fkAOD7aVZpgmaJ09+rqicAX6BpVAHeVlVPrqpvB26mWf0L4FeBZ7Tlz27LLgD+saqeDDwZ+Ml2KeSTgM9X1b3tfi8EvlJVpwOXAE9q63Q08CvA06rqO4HrgH+X5BDgP9OsFvXPgEes+TjXAd+z86siSd1kmy2N7oB5V0BL5dAk17eP/wfwWuDRwG1VtVr+IeDE9vFpSf4v4OHA4cBftuX/E3h9kiuAt7VlTwdOT/JD7fOH0TT+XwI+N1CHpwCvAqiqjyb5aFt+FnAq8D+TABwEfAD4VuDvquq2dr83ARcOvN9d7WeQpEVjmy2NycBas/TVqnriYEHbIN47ULSfb9zqez3wnKr6SJIfA84GqKqfTvJPgX8JXJ/kiUCAF1fVXw68F0m+AzhkTT1qSN0CXFVVzx9y/GYOAb66xT6S1Ee22dKYTAVRlz0UuDPJgcAPrxYm+eaquqaqfhXYB5xA0zPywnZfkpyS5CHA3/CN3hSA962+V5LTgNPb8g8C353k8e1rhyU5Bfg48Lgkq+/xr9fU8RRgqiPkJaknbLO19OyxVpf9e+Aa4O9pcvse2pa/MsnJND0WVwMfAT5K0xh/OE2Xyudoek7+McnfJnl8Vd0KvAZ4XXs78XrgWoCq+lzbw/KmJAe35/mVqvqbJP8W+Isk+1b3H/C9wMVT+OyS1De22Vp6aQbJSosryQ8AT6qqX9nm8YdX1Zfaxv/3gE9U1W8neSTwR1X11EnWV5KWmW22+sxUEC28qvpT4PYdvMVPtgN4bqIZYPOf2/LHAL+ws9pJkgbZZqvP7LGWJEmSJsAea0mSJGkCDKwlSZKkCTCwliRJkibAwFqSJEmaAANrSZIkaQIMrCVJkqQJ+P8BEryllybfL3sAAAAASUVORK5CYII=\n", - "text/plain": [ - "
" - ] - }, - "metadata": { - "needs_background": "light" - }, - "output_type": "display_data" - } - ], - "source": [ - "# plot data\n", - "fig, axes = plt.subplots(1, 2, figsize=(12,5))\n", - "for i, d in enumerate([avg_di, avg_dq]):\n", - " pcm = axes[i].pcolormesh(prog.get_expt_pts()[1], prog.get_expt_pts()[0], d[0,0].T, shading=\"Auto\", cmap=\"RdBu\")\n", - " axes[i].set_xlabel(\"Phase(deg)\")\n", - " axes[i].set_ylabel(\"Gain\")\n", - " axes[i].set_title(\"I data\" if i ==0 else \"Q data\")\n", - " plt.colorbar(pcm, ax=axes[i])\n", - "\n", - "fig, axes = plt.subplots(1, 2, figsize=(12,5))\n", - "for i, d in enumerate([avg_abs, avg_angle]):\n", - " if i==0:\n", - " pcm = axes[i].pcolormesh(prog.get_expt_pts()[1], prog.get_expt_pts()[0], d[0,0].T, shading=\"Auto\", cmap=\"hot\")\n", - " else:\n", - " pcm = axes[i].pcolormesh(prog.get_expt_pts()[1], prog.get_expt_pts()[0], np.unwrap(d[0, 0].T), shading=\"Auto\",cmap=\"twilight\")\n", - " axes[i].set_xlabel(\"Phase(deg)\")\n", - " axes[i].set_ylabel(\"Gain\")\n", - " axes[i].set_title(\"IQ Amp\" if i ==0 else \"IQ phase (rad)\")\n", - " plt.colorbar(pcm, ax=axes[i])" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "### Example 2: when the parameter we sweep over needs to jump between a constant value and a sweep value\n", - "\n", - "A practical example can be transmon ef pulse spec, in which the first qubit pulse of each experiment will be a pi pulse at the ge frequency that prepares the qubit to e state, and the second pulse's frequency needs to sweep around the ef frequency.\n", - "\n", - "Here, for simplicity, we make the gain jump between a constant value and a sweep value to demonstrate the idea." - ] - }, - { - "cell_type": "code", - "execution_count": 7, - "metadata": {}, - "outputs": [], - "source": [ - "class NDSweepProgram_2(NDAveragerProgram):\n", - " def initialize(self):\n", - " cfg = self.cfg\n", - " res_ch = cfg[\"res_ch\"]\n", - "\n", - " self.declare_gen(ch=cfg[\"res_ch\"], nqz=1, ro_ch=cfg[\"ro_chs\"][0])\n", - "\n", - " for ch in cfg[\"ro_chs\"]:\n", - " self.declare_readout(ch=ch, length=self.cfg[\"readout_length\"],\n", - " freq=self.cfg[\"pulse_freq\"], gen_ch=cfg[\"res_ch\"])\n", - "\n", - " # convert frequency to DAC frequency (ensuring it is an available ADC frequency)\n", - " freq = self.freq2reg(cfg[\"pulse_freq\"], gen_ch=res_ch, ro_ch=cfg[\"ro_chs\"][0])\n", - " phase = self.deg2reg(cfg[\"phi_start\"], gen_ch=res_ch)\n", - " gain = cfg[\"g0\"]\n", - "\n", - " self.set_pulse_registers(ch=res_ch, style=\"const\", freq=freq, phase=phase, gain=gain, length=cfg[\"length\"])\n", - " \n", - " # ---------- sweep defination starts from here -----------------\n", - " # get gain and phase registers of the generator channel (check 04_Reading_Math_Writing for more details about QickRegister object)\n", - " self.res_r_gain = self.get_gen_reg(cfg[\"res_ch\"], \"gain\")\n", - " # declare a new register in the res_ch register page that keeps the sweep value\n", - " self.res_r_gain_update = self.new_gen_reg(cfg[\"res_ch\"], init_val=cfg[\"g_start\"], name=\"gain_update\") \n", - " self.res_r_phase = self.get_gen_reg(cfg[\"res_ch\"], \"phase\")\n", - "\n", - " # add pulse gain and phase sweep, first added will be first swept\n", - " self.add_sweep(QickSweep(self, self.res_r_gain_update, cfg[\"g_start\"], cfg[\"g_stop\"], cfg[\"g_expts\"])) # now sweep over \"res_r_gain_update\"\n", - " self.add_sweep(QickSweep(self, self.res_r_phase, cfg[\"phi_start\"], cfg[\"phi_stop\"], cfg[\"phi_expts\"]))\n", - "\n", - "\n", - " self.synci(200) # give processor some time to configure pulses\n", - "\n", - " def body(self):\n", - " # first pulse has fixed gain g0\n", - " self.res_r_gain.set_to(self.cfg[\"g0\"]) # same as: self.safe_regwi(self.res_r_gain.page, self.res_r_gain.addr, self.cfg[\"g0\"])\n", - " self.measure(pulse_ch=self.cfg[\"res_ch\"],\n", - " adcs=self.ro_chs,\n", - " pins=[0],\n", - " adc_trig_offset=self.cfg[\"adc_trig_offset\"],\n", - " wait=True,\n", - " syncdelay=self.us2cycles(self.cfg[\"relax_delay\"]))\n", - "\n", - " # second pulse sweeps gain value\n", - " self.res_r_gain.set_to(self.res_r_gain_update) # same as: self.mathi(self.res_r_gain.page, self.res_r_gain.addr, self.res_r_gain_update.addr, \"+\", 0)\n", - " self.measure(pulse_ch=self.cfg[\"res_ch\"],\n", - " adcs=self.ro_chs,\n", - " pins=[0],\n", - " adc_trig_offset=self.cfg[\"adc_trig_offset\"],\n", - " wait=True,\n", - " syncdelay=self.us2cycles(self.cfg[\"relax_delay\"]))" - ] - }, - { - "cell_type": "code", - "execution_count": 10, - "metadata": {}, - "outputs": [ - { - "data": { - "application/vnd.jupyter.widget-view+json": { - "model_id": "a0ac1f68c5894f54afd2eeb70b06c59c", - "version_major": 2, - "version_minor": 0 - }, - "text/plain": [ - " 0%| | 0/1030200 [00:00" - ] - }, - "metadata": { - "needs_background": "light" - }, - "output_type": "display_data" - } - ], - "source": [ - "# plot data\n", - "fig, axes = plt.subplots(2, 2, figsize=(12,10))\n", - "for j in range(2):\n", - " for i, d in enumerate([avg_di, avg_dq]):\n", - " pcm = axes[j,i].pcolormesh(prog.get_expt_pts()[1], prog.get_expt_pts()[0], d[0,j].T, shading=\"Auto\", cmap=\"RdBu\")\n", - " axes[j, i].set_xlabel(\"Phase(deg)\")\n", - " axes[j, i].set_ylabel(\"Gain\")\n", - " axes[j, i].set_title(f\"I data msmt {j+1} \" if i ==0 else f\"Q data msmt {j+1} \")\n", - " plt.colorbar(pcm, ax=axes[j, i])\n" - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [] - } - ], - "metadata": { - "kernelspec": { - "display_name": "Python 3", - "language": "python", - "name": "python3" - }, - "language_info": { - "codemirror_mode": { - "name": "ipython", - "version": 3 - }, - "file_extension": ".py", - "mimetype": "text/x-python", - "name": "python", - "nbconvert_exporter": "python", - "pygments_lexer": "ipython3", - "version": "3.8.2" - }, - "vscode": { - "interpreter": { - "hash": "618feb7b2b0a35f7e820dec88779cac1ef83ad948f0212540d069fdb92cbb234" - } - } - }, - "nbformat": 4, - "nbformat_minor": 2 -} diff --git a/qick/qick_demos/README.md b/qick/qick_demos/README.md deleted file mode 100644 index 75fc0ac..0000000 --- a/qick/qick_demos/README.md +++ /dev/null @@ -1,50 +0,0 @@ -A high-level overview of the QICK software capabilities -================================================= - -Below is a brief summary of the QICK software capabilities. - -## Sending and receiving pulses -* Basic example given in [Demo 00_Send_receive_pulse](https://github.com/openquantumhardware/qick/blob/main/qick_demos/00_Send_receive_pulse.ipynb) -* Control of 1st and 2nd Nyquist zone pulses, direct synthesis of pulses up to 6 GHz -* Decimated mode and acquire (I/Q) mode (with round-robin style data acquisition) -* Arbitrary pulse envelopes -* DAC modes of operation: CW mode, product mode, envelope-only mode -* ADC modes of operation: demodulation in the ADC -* Relative timing and phase control between pulses - -## Sweeping variables within a QICK program -* Basic example given in [Demo 02_Sweeping_variables](https://github.com/openquantumhardware/qick/blob/main/qick_demos/02_Sweeping_variables.ipynb) -* The update function allows you to easily update parameters such as pulse gain in a fast loop (within a QICK program, rather than a Python slow loop over multiple QICK programs) - -## Conditional logic within a QICK program -* Basic example given in [Demo 03_Conditional_logic](https://github.com/openquantumhardware/qick/blob/main/qick_demos/03_Conditional_logic.ipynb) -* The ability to play conditional pulses based on tProc register values - -## Reading, math and writing within a QICK program -* Basic example given in [Demo 04_Reading_Math_Writing](https://github.com/openquantumhardware/qick/blob/main/qick_demos/04_Reading_Math_Writing.ipynb) -* The ability to write data to and read data from tProc memory addresses (which tProc registers can access) -* Addition, subtraction, multiplication, bit shifting - -## Measurements on quantum devices - -The ZCU111 firmware posted in this repository has been tested on multiple different kinds of quantum devices: - -* Measuring a transmon with high-fidelity readout and active reset enabled [Demo 06_qubit_demos](https://github.com/openquantumhardware/qick/blob/main/qick_demos/06_qubit_demos.ipynb) -* Measuring a storage cavity + qubit + readout cavity system -* Measuring a fluxonium qubit controlled with fast flux pulse gates -* Measuring a Kerr-cat qubit which expands on the standard transmon measurements by adding a squeezing drive and relative phase control - -A modified version of the firmware with 4 DACs and 4 ADCs enabled (instead of 7 DACs and 2 ADCs enabled) has been tested: - -* Measuring independently 4 high-Q resonators at once - -## Features available on the QICK which are not included in this collection of demos -* Control other lab hardware remotely using the QICK (e.g. Yokogawa voltage source, Signalcore LO, digital step attenuators) -* Marker pulses coming out of the RFSoC PMOD pins - -## Other examples of QICK measurement code, shared by QICK collaborators - -* [Connie Miao, Schuster Lab](https://github.com/conniemiao/slab_rfsoc_expts) -* [Chao Zhou, Hatlab](https://github.com/PITT-HATLAB/Hatlab_RFSOC) -* [Sara Sussman, Houck Lab](https://github.com/sarafs1926/qick-amo) - diff --git a/qick/qick_demos/images/Conditional_False_Pulse.pdf b/qick/qick_demos/images/Conditional_False_Pulse.pdf deleted file mode 100644 index e6462c8..0000000 Binary files a/qick/qick_demos/images/Conditional_False_Pulse.pdf and /dev/null differ diff --git a/qick/qick_demos/images/Conditional_True_NoPulse.pdf b/qick/qick_demos/images/Conditional_True_NoPulse.pdf deleted file mode 100644 index 12fcbe1..0000000 Binary files a/qick/qick_demos/images/Conditional_True_NoPulse.pdf and /dev/null differ diff --git a/qick/qick_demos/images/Gain_sweep.pdf b/qick/qick_demos/images/Gain_sweep.pdf deleted file mode 100644 index 47180b7..0000000 Binary files a/qick/qick_demos/images/Gain_sweep.pdf and /dev/null differ diff --git a/qick/qick_demos/images/Gain_sweep_python.pdf b/qick/qick_demos/images/Gain_sweep_python.pdf deleted file mode 100644 index 0f71d09..0000000 Binary files a/qick/qick_demos/images/Gain_sweep_python.pdf and /dev/null differ diff --git a/qick/qick_demos/images/Phase_calibration.pdf b/qick/qick_demos/images/Phase_calibration.pdf deleted file mode 100644 index d353723..0000000 Binary files a/qick/qick_demos/images/Phase_calibration.pdf and /dev/null differ diff --git a/qick/qick_demos/images/Phase_sweep.pdf b/qick/qick_demos/images/Phase_sweep.pdf deleted file mode 100644 index e5a0afc..0000000 Binary files a/qick/qick_demos/images/Phase_sweep.pdf and /dev/null differ diff --git a/qick/qick_demos/images/QICK_wiring_new.png b/qick/qick_demos/images/QICK_wiring_new.png deleted file mode 100644 index 13a2f9d..0000000 Binary files a/qick/qick_demos/images/QICK_wiring_new.png and /dev/null differ diff --git a/qick/qick_demos/images/Send_recieve_pulse_arb.pdf b/qick/qick_demos/images/Send_recieve_pulse_arb.pdf deleted file mode 100644 index 2b34d00..0000000 Binary files a/qick/qick_demos/images/Send_recieve_pulse_arb.pdf and /dev/null differ diff --git a/qick/qick_demos/images/Send_recieve_pulse_const.pdf b/qick/qick_demos/images/Send_recieve_pulse_const.pdf deleted file mode 100644 index d7703a9..0000000 Binary files a/qick/qick_demos/images/Send_recieve_pulse_const.pdf and /dev/null differ diff --git a/qick/qick_demos/images/Send_recieve_pulse_flattop.pdf b/qick/qick_demos/images/Send_recieve_pulse_flattop.pdf deleted file mode 100644 index 03b791c..0000000 Binary files a/qick/qick_demos/images/Send_recieve_pulse_flattop.pdf and /dev/null differ diff --git a/qick/qick_demos/sds_trace_data.dat b/qick/qick_demos/sds_trace_data.dat deleted file mode 100644 index 7adff9b..0000000 Binary files a/qick/qick_demos/sds_trace_data.dat and /dev/null differ diff --git a/qick/qick_lib/qick/VERSION b/qick/qick_lib/qick/VERSION deleted file mode 100644 index 1c1d9be..0000000 --- a/qick/qick_lib/qick/VERSION +++ /dev/null @@ -1 +0,0 @@ -0.2.160 diff --git a/qick/qick_lib/qick/__init__.py b/qick/qick_lib/qick/__init__.py deleted file mode 100644 index 0673440..0000000 --- a/qick/qick_lib/qick/__init__.py +++ /dev/null @@ -1,57 +0,0 @@ -import os -import platform - -def get_version(): - """Read library version from qick_lib/qick/VERSION (a text file containing only the version number). - - Parameters - ---------- - - Returns - ------- - str - version number, in major.minor.PR format - """ - versionpath = os.path.join(os.path.dirname(__file__), 'VERSION') - with open(versionpath) as version_file: - version = version_file.read().strip() - return version - -__version__ = get_version() - -def bitfile_path(): - """Choose the default firmware path for this board. - - Parameters - ---------- - - Returns - ------- - str - absolute path to the firmware bitfile distributed with the QICK library - """ - board2file = {'ZCU216' :'qick_216.bit', - 'ZCU111' :'qick_111.bit', - 'RFSoC4x2' :'qick_4x2.bit'} - filename = board2file[os.environ['BOARD']] - src = os.path.join(os.path.dirname(qick.__file__), filename) - return src - -# tie in to rpyc, if using -try: - from rpyc.utils.classic import obtain -except ModuleNotFoundError: - def obtain(i): - return i - -from .averager_program import AveragerProgram, RAveragerProgram, NDAveragerProgram -from .qick_asm import QickConfig, QickProgram, DummyIp - -# only import the hardware drivers if running on a Zynq -# also import if we're in the ReadTheDocs Sphinx build (the imports won't really work but they will be mocked) -if platform.machine() in ['aarch64', 'armv7l'] or os.getenv('READTHEDOCS', default='False')=='True': - try: - from .ip import SocIp - from .qick import QickSoc - except Exception as e: - print("Could not import QickSoc:", e) diff --git a/qick/qick_lib/qick/averager_program.py b/qick/qick_lib/qick/averager_program.py deleted file mode 100644 index c3efa11..0000000 --- a/qick/qick_lib/qick/averager_program.py +++ /dev/null @@ -1,601 +0,0 @@ -""" -Several helper classes for writing qubit experiments. -""" -from typing import List, Union -import numpy as np -from qick import obtain -from .qick_asm import QickProgram, QickRegister, QickRegisterManagerMixin - -class AveragerProgram(QickProgram): - """ - AveragerProgram class is an abstract base class for programs which do loops over experiments in hardware. - It consists of a template program which takes care of the loop and acquire methods that talk to the processor to stream single shot data in real-time and then reshape and average it appropriately. - - :param soccfg: This can be either a QickSOc object (if the program is running on the QICK) or a QickCOnfig (if running remotely). - :type soccfg: QickConfig - :param cfg: Configuration dictionary - :type cfg: dict - """ - - def __init__(self, soccfg, cfg): - """ - Constructor for the AveragerProgram, calls make program at the end. - For classes that inherit from this, if you want it to do something before the program is made and compiled: - either do it before calling this __init__ or put it in the initialize method. - """ - super().__init__(soccfg) - self.cfg = cfg - self.make_program() - if "soft_avgs" in cfg: - self.rounds = cfg['soft_avgs'] - if "rounds" in cfg: - self.rounds = cfg['rounds'] - self.reps = cfg['reps'] - - def initialize(self): - """ - Abstract method for initializing the program and can include any instructions that are executed once at the beginning of the program. - """ - pass - - def body(self): - """ - Abstract method for the body of the program - """ - pass - - def make_program(self): - """ - A template program which repeats the instructions defined in the body() method the number of times specified in self.cfg["reps"]. - """ - p = self - - rjj = 14 - rcount = 15 - p.initialize() - p.regwi(0, rcount, 0) - p.regwi(0, rjj, self.cfg['reps']-1) - p.label("LOOP_J") - - p.body() - - p.mathi(0, rcount, rcount, "+", 1) - - p.memwi(0, rcount, self.counter_addr) - - p.loopnz(0, rjj, 'LOOP_J') - - p.end() - - - def acquire(self, soc, threshold=None, angle=None, readouts_per_experiment=1, save_experiments=None, load_pulses=True, start_src="internal", progress=False, debug=False): - """ - This method optionally loads pulses on to the SoC, configures the ADC readouts, loads the machine code representation of the AveragerProgram onto the SoC, starts the program and streams the data into the Python, returning it as a set of numpy arrays. - config requirements: - "reps" = number of repetitions; - - :param soc: Qick object - :type soc: Qick object - :param threshold: threshold - :type threshold: int - :param angle: rotation angle - :type angle: list - :param readouts_per_experiment: readouts per experiment - :type readouts_per_experiment: int - :param save_experiments: saved readouts (by default, save all readouts) - :type save_experiments: list - :param load_pulses: If true, loads pulses into the tProc - :type load_pulses: bool - :param start_src: "internal" (tProc starts immediately) or "external" (each round waits for an external trigger) - :type start_src: string - :param progress: If true, displays progress bar - :type progress: bool - :param debug: If true, displays assembly code for tProc program - :type debug: bool - :returns: - - expt_pts (:py:class:`list`) - list of experiment points - - avg_di (:py:class:`list`) - list of lists of averaged accumulated I data for ADCs 0 and 1 - - avg_dq (:py:class:`list`) - list of lists of averaged accumulated Q data for ADCs 0 and 1 - """ - - self.shot_angle = angle - self.shot_threshold = threshold - - if save_experiments is None: - save_experiments = range(readouts_per_experiment) - - d_buf, avg_d, shots = super().acquire(soc, reads_per_rep=readouts_per_experiment, load_pulses=load_pulses, start_src=start_src, progress=progress, debug=debug) - - # reformat the data into separate I and Q arrays - # save results to class in case you want to look at it later or for analysis - self.di_buf = d_buf[:,:,0] - self.dq_buf = d_buf[:,:,1] - - if threshold is not None: - self.shots = shots - - n_ro = len(self.ro_chs) - avg_di = np.zeros((n_ro, len(save_experiments))) - avg_dq = np.zeros((n_ro, len(save_experiments))) - - for nn, ii in enumerate(save_experiments): - for i_ch, (ch, ro) in enumerate(self.ro_chs.items()): - avg_di[i_ch][nn] = avg_d[i_ch, ii, 0] - avg_dq[i_ch][nn] = avg_d[i_ch, ii, 1] - - return avg_di, avg_dq - - - def acquire_decimated(self, soc, load_pulses=True, readouts_per_experiment=1, start_src="internal", progress=True, debug=False): - """ - This method acquires the raw (downconverted and decimated) data sampled by the ADC. This method is slow and mostly useful for lining up pulses or doing loopback tests. - - config requirements: - "reps" = number of tProc loop repetitions; - "soft_avgs" = number of Python loop repetitions; - - The data is returned as a list of ndarrays (one ndarray per readout channel). - There are two possible array formats. - reps = 1: - 2D array with dimensions (2, length), indices (I/Q, sample) - reps > 1: - 3D array with dimensions (reps, 2, length), indices (rep, I/Q, sample) - readouts_per_experiment>1: - 3D array with dimensions (reps, expts, 2, length), indices (rep, expt, I/Q, sample) - - :param soc: Qick object - :type soc: Qick object - :param load_pulses: If true, loads pulses into the tProc - :type load_pulses: bool - :param readouts_per_experiment: readouts per experiment (all will be saved) - :type readouts_per_experiment: int - :param start_src: "internal" (tProc starts immediately) or "external" (each soft_avg waits for an external trigger) - :type start_src: string - :param progress: If true, displays progress bar - :type progress: bool - :param debug: If true, displays assembly code for tProc program - :type debug: bool - :returns: - - iq_list (:py:class:`list`) - list of lists of averaged decimated I and Q data - """ - - buf = super().acquire_decimated(soc, reads_per_rep=readouts_per_experiment, load_pulses=load_pulses, start_src=start_src, progress=progress, debug=debug) - # move the I/Q axis from last to second-last - return np.moveaxis(buf, -1, -2) - -class RAveragerProgram(QickProgram): - """ - RAveragerProgram class, for qubit experiments that sweep over a variable (whose value is stored in expt_pts). - It is an abstract base class similar to the AveragerProgram, except has an outer loop which allows one to sweep a parameter in the real-time program rather than looping over it in software. This can be more efficient for short duty cycles. - Acquire gathers data from both ADCs 0 and 1. - - :param cfg: Configuration dictionary - :type cfg: dict - """ - - def __init__(self, soccfg, cfg): - """ - Constructor for the RAveragerProgram, calls make program at the end so for classes that inherit from this if you want it to do something before the program is made and compiled either do it before calling this __init__ or put it in the initialize method. - """ - super().__init__(soccfg) - self.cfg = cfg - self.make_program() - self.reps = cfg['reps'] - self.expts = cfg['expts'] - if "rounds" in cfg: - self.rounds = cfg['rounds'] - - def initialize(self): - """ - Abstract method for initializing the program and can include any instructions that are executed once at the beginning of the program. - """ - pass - - def body(self): - """ - Abstract method for the body of the program - """ - pass - - def update(self): - """ - Abstract method for updating the program - """ - pass - - def make_program(self): - """ - A template program which repeats the instructions defined in the body() method the number of times specified in self.cfg["reps"]. - """ - p = self - - rcount = 13 - rii = 14 - rjj = 15 - - p.initialize() - - p.regwi(0, rcount, 0) - - p.regwi(0, rii, self.cfg['expts']-1) - p.label("LOOP_I") - - p.regwi(0, rjj, self.cfg['reps']-1) - p.label("LOOP_J") - - p.body() - - p.mathi(0, rcount, rcount, "+", 1) - - p.memwi(0, rcount, self.counter_addr) - - p.loopnz(0, rjj, 'LOOP_J') - - p.update() - - p.loopnz(0, rii, "LOOP_I") - - p.end() - - def get_expt_pts(self): - """ - Method for calculating experiment points (for x-axis of plots) based on the config. - - :return: Numpy array of experiment points - :rtype: array - """ - return self.cfg["start"]+np.arange(self.expts)*self.cfg["step"] - - def acquire(self, soc, threshold=None, angle=None, load_pulses=True, readouts_per_experiment=1, save_experiments=None, start_src="internal", progress=False, debug=False): - """ - This method optionally loads pulses on to the SoC, configures the ADC readouts, loads the machine code representation of the AveragerProgram onto the SoC, starts the program and streams the data into the Python, returning it as a set of numpy arrays. - config requirements: - "reps" = number of repetitions; - - :param soc: Qick object - :type soc: Qick object - :param threshold: threshold - :type threshold: int - :param angle: rotation angle - :type angle: list - :param readouts_per_experiment: readouts per experiment - :type readouts_per_experiment: int - :param save_experiments: saved readouts (by default, save all readouts) - :type save_experiments: list - :param load_pulses: If true, loads pulses into the tProc - :type load_pulses: bool - :param start_src: "internal" (tProc starts immediately) or "external" (each round waits for an external trigger) - :type start_src: string - :param progress: If true, displays progress bar - :type progress: bool - :param debug: If true, displays assembly code for tProc program - :type debug: bool - :returns: - - expt_pts (:py:class:`list`) - list of experiment points - - avg_di (:py:class:`list`) - list of lists of averaged accumulated I data for ADCs 0 and 1 - - avg_dq (:py:class:`list`) - list of lists of averaged accumulated Q data for ADCs 0 and 1 - """ - self.shot_angle = angle - self.shot_threshold = threshold - - if save_experiments is None: - save_experiments = range(readouts_per_experiment) - - d_buf, avg_d, shots = super().acquire(soc, reads_per_rep=readouts_per_experiment, load_pulses=load_pulses, start_src=start_src, progress=progress, debug=debug) - - # reformat the data into separate I and Q arrays - # save results to class in case you want to look at it later or for analysis - self.di_buf = d_buf[:,:,0] - self.dq_buf = d_buf[:,:,1] - - if threshold is not None: - self.shots = shots - - expt_pts = self.get_expt_pts() - - n_ro = len(self.ro_chs) - avg_di = np.zeros((n_ro, len(save_experiments), self.expts)) - avg_dq = np.zeros((n_ro, len(save_experiments), self.expts)) - - for nn, ii in enumerate(save_experiments): - for i_ch, (ch, ro) in enumerate(self.ro_chs.items()): - avg_di[i_ch][nn] = avg_d[i_ch, ii, :, 0] - avg_dq[i_ch][nn] = avg_d[i_ch, ii, :, 1] - - return expt_pts, avg_di, avg_dq - - -class AbsQickSweep: - """ - Abstract QickSweep class. - """ - - def __init__(self, prog: QickProgram, label=None): - """ - :param prog: QickProgram in which the sweep will run. - :param label: label to be used for the loop tag in qick asm program. - """ - self.prog = prog - self.label = label - self.expts: int = None - - def get_sweep_pts(self) -> Union[List, np.array]: - """ - abstract method for getting the sweep values - """ - pass - - def update(self): - """ - abstract method for updating the sweep value - """ - pass - - def reset(self): - """ - abstract method for resetting the sweep value at the beginning of each sweep. - """ - pass - - -class QickSweep(AbsQickSweep): - """ - QickSweep class, describes a sweeps over a qick register. - """ - - def __init__(self, prog: QickProgram, reg: QickRegister, start, stop, expts: int, label=None): - """ - - :param prog: QickProgram in which the sweep happens. - :param reg: QickRegister object associated to the register to sweep. - :param start: start value of the register to sweep, in physical units - :param stop: stop value of the register to sweep, in physical units - :param expts: number of experiment points from start to stop value. - :param label: label to be used for the loop tag in qick asm program. - """ - super().__init__(prog) - self.reg = reg - self.start = start - self.stop = stop - self.expts = expts - step_val = (stop - start) / (expts - 1) - self.step_val = step_val - self.reg.init_val = start - - if label is None: - self.label = self.reg.name - else: - self.label = label - - def get_sweep_pts(self): - return np.linspace(self.start, self.stop, self.expts) - - def update(self): - """ - update the register value. This will be called after finishing last register sweep. - This function should be overwritten if more complicated update is needed. - :return: - """ - self.reg.set_to(self.reg, '+', self.step_val) - - def reset(self): - """ - reset the register to the start value. will be called at the beginning of each sweep. - This function should be overwritten if more complicated reset is needed. - :return: - """ - self.reg.reset() - - -def merge_sweeps(sweeps: List[QickSweep]) -> AbsQickSweep: - """ - create a new QickSweep object that merges the update and reset functions of multiple QickSweeps into one. This is - useful when multiple registers need to be updated at the same time in one sweep. - :param sweeps: list of "QickSweep"s - :return: - """ - label = "-".join([swp.label for swp in sweeps]) - - merged = AbsQickSweep(sweeps[0].prog, label) - merged.get_sweep_pts = sweeps[0].get_sweep_pts - expts_ = set([swp.expts for swp in sweeps]) - if len(expts_) != 1: - raise ValueError(f"all sweeps for merging must have same number of expts, got{expts_}") - merged.expts = sweeps[0].expts - - def _update(): - for swp in sweeps: - swp.update() - - def _reset(): - for swp in sweeps: - swp.reset() - - def _get_sweep_pts(): - sweep_pts = [] - for swp in sweeps: - sweep_pts.append(swp.get_sweep_pts()) - sweep_pts = np.array(sweep_pts).T - return sweep_pts - - merged.update = _update - merged.reset = _reset - merged.get_sweep_pts = _get_sweep_pts - - return merged - - -class NDAveragerProgram(QickRegisterManagerMixin, QickProgram): - """ - NDAveragerProgram class, for experiments that sweep over multiple variables in qick. The order of experiment runs - follow outer->inner: reps, sweep_n,... sweep_0. - - :param cfg: Configuration dictionary - :type cfg: dict - """ - - def __init__(self, soccfg, cfg): - """ - Constructor for the NDAveragerProgram. Make the ND sweep asm commands. - """ - super().__init__(soccfg) - self.cfg = cfg - self.qick_sweeps: List[AbsQickSweep] = [] - self.expts = 1 - self.sweep_axes = [] - self.make_program() - self.reps = cfg['reps'] - if "soft_avgs" in cfg: - self.rounds = cfg['soft_avgs'] - if "rounds" in cfg: - self.rounds = cfg['rounds'] - - def initialize(self): - """ - Abstract method for initializing the program. Should include the instructions that will be executed once at the - beginning of the qick program. - """ - pass - - def body(self): - """ - Abstract method for the body of the program. - """ - pass - - def add_sweep(self, sweep: AbsQickSweep): - """ - Add a layer of register sweep to the qick asm program. The order of sweeping will follow first added first sweep. - :param sweep: - :return: - """ - self.qick_sweeps.append(sweep) - self.expts *= sweep.expts - self.sweep_axes.append(sweep.expts) - - def make_program(self): - """ - Make the N dimensional sweep program. The program will run initialize once at the beginning, then iterate over - all the sweep parameters and run the body. The whole sweep will repeat for cfg["reps"] number of times. - """ - p = self - - p.initialize() # initialize only run once at the very beginning - - rcount = 13 # total run counter - rep_count = 14 # repetition counter - - n_sweeps = len(self.qick_sweeps) - if n_sweeps > 7: # to be safe, only register 15-21 in page 0 can be used as sweep counters - raise OverflowError(f"too many qick inner loops ({n_sweeps}), run out of counter registers") - counter_regs = (np.arange(n_sweeps) + 15).tolist() # not sure why this has to be a list (np.array doesn't work) - - p.regwi(0, rcount, 0) # reset total run count - - # set repetition counter and tag - p.regwi(0, rep_count, self.cfg["reps"] - 1) - p.label("LOOP_rep") - - # add reset and start tags for each sweep - for creg, swp in zip(counter_regs[::-1], self.qick_sweeps[::-1]): - swp.reset() - p.regwi(0, creg, swp.expts - 1) - p.label(f"LOOP_{swp.label if swp.label is not None else creg}") - - # run body and total_run_counter++ - p.body() - p.mathi(0, rcount, rcount, "+", 1) - p.memwi(0, rcount, 1) - - # add update and stop condition for each sweep - for creg, swp in zip(counter_regs, self.qick_sweeps): - swp.update() - p.loopnz(0, creg, f"LOOP_{swp.label if swp.label is not None else creg}") - - # stop condition for repetition - p.loopnz(0, rep_count, 'LOOP_rep') - - p.end() - - def get_expt_pts(self): - """ - :return: - """ - sweep_pts = [] - for swp in self.qick_sweeps: - sweep_pts.append(swp.get_sweep_pts()) - return sweep_pts - - def acquire(self, soc, threshold: int = None, angle: List = None, load_pulses=True, readouts_per_experiment=1, - save_experiments: List = None, start_src: str = "internal", progress=False, debug=False): - """ - This method optionally loads pulses on to the SoC, configures the ADC readouts, loads the machine code - representation of the AveragerProgram onto the SoC, starts the program and streams the data into the Python, - returning it as a set of numpy arrays. - Note here the buf data has "reps" as the outermost axis, and the first swept parameter corresponds to the - innermost axis. - - config requirements: - "reps" = number of repetitions; - - :param soc: Qick object - :param threshold: threshold - :param angle: rotation angle - :param readouts_per_experiment: readouts per experiment - :param save_experiments: saved readouts (by default, save all readouts) - :param load_pulses: If true, loads pulses into the tProc - :param start_src: "internal" (tProc starts immediately) or "external" (each round waits for an external trigger) - :param progress: If true, displays progress bar - :param debug: If true, displays assembly code for tProc program - :returns: - - expt_pts (:py:class:`list`) - list of experiment points - - avg_di (:py:class:`list`) - list of lists of averaged accumulated I data for ADCs 0 and 1 - - avg_dq (:py:class:`list`) - list of lists of averaged accumulated Q data for ADCs 0 and 1 - """ - - self.shot_angle = angle - self.shot_threshold = threshold - - if save_experiments is None: - save_experiments = range(readouts_per_experiment) - - # avg_d calculated in QickProgram.acquire() assumes a different data shape, here we will recalculate based on - # the d_buf returned. - d_buf, avg_d, shots = super().acquire(soc, reads_per_rep=readouts_per_experiment, load_pulses=load_pulses, - start_src=start_src, progress=progress, debug=debug) - - # reformat the data into separate I and Q arrays - # save results to class in case you want to look at it later or for analysis - self.di_buf = d_buf[:, :, 0] - self.dq_buf = d_buf[:, :, 1] - - if threshold is not None: - self.shots = shots - - expt_pts = self.get_expt_pts() - - n_ro = len(self.ro_chs) - avg_di = np.zeros((n_ro, len(save_experiments), *self.sweep_axes[::-1])) - avg_dq = np.zeros((n_ro, len(save_experiments), *self.sweep_axes[::-1])) - - for nn, ii in enumerate(save_experiments): - for i_ch, (ch, ro) in enumerate(self.ro_chs.items()): - avg_di[i_ch][nn] = avg_d[i_ch, ii, ..., 0] - avg_dq[i_ch][nn] = avg_d[i_ch, ii, ..., 1] - - return expt_pts, avg_di, avg_dq - - def _average_buf(self, d_reps, reads_per_rep: int): - """ - overwrites the default _average_buf method in QickProgram. Here "reps" is the outermost axis, and we reshape - avg_d to the shape of the sweep axes. - :param d_reps: - :param reads_per_rep: - :return: - """ - avg_d = np.zeros((len(self.ro_chs), reads_per_rep, *self.sweep_axes[::-1], 2)) - for ii in range(reads_per_rep): - for i_ch, (ch, ro) in enumerate(self.ro_chs.items()): - avg_d[i_ch][ii] = np.sum(d_reps[i_ch][ii::reads_per_rep, :].reshape((self.reps, *self.sweep_axes[::-1], 2)), - axis=0) / (self.reps * ro['length']) - return avg_d diff --git a/qick/qick_lib/qick/drivers/generator.py b/qick/qick_lib/qick/drivers/generator.py deleted file mode 100644 index 06e05c7..0000000 --- a/qick/qick_lib/qick/drivers/generator.py +++ /dev/null @@ -1,524 +0,0 @@ -""" -Drivers for signal generators: FPGA blocks that send data to DACs. -""" -from pynq.buffer import allocate -import numpy as np -from qick import SocIp - -class AbsSignalGen(SocIp): - """ - Abstract class which defines methods that are common to different signal generators. - """ - # The DAC channel has a mixer. - HAS_MIXER = False - # Interpolation factor relating the generator and DAC sampling freqs. - FS_INTERPOLATION = 1 - # Waveform samples per fabric clock. - SAMPS_PER_CLK = 1 - # Maximum waveform amplitude. - MAXV = 2**15-2 - # Scale factor between MAXV and the default maximum amplitude (necessary to avoid overshoot). - MAXV_SCALE = 1.0 - - # Configure this driver with links to the other drivers, and the signal gen channel number. - def configure(self, ch, rf, fs): - # Channel number corresponding to entry in the QickConfig list of gens. - self.ch = ch - - # RF data converter - self.rf = rf - - # DAC sampling frequency. - self.cfg['fs'] = fs - - self.cfg['dac'] = self.dac - - def configure_connections(self, soc): - self.soc = soc - - # what RFDC port does this generator drive? - ((block, port),) = soc.metadata.trace_bus(self.fullpath, 'm_axis') - # might need to jump through an axis_register_slice - while True: - blocktype = soc.metadata.mod2type(block) - if blocktype == "usp_rf_data_converter": # we're done - break - elif blocktype == "axis_register_slice": - ((block, port),) = soc.metadata.trace_bus(block, "M_AXIS") - elif blocktype == "axis_register_slice_nb": - ((block, port),) = soc.metadata.trace_bus(block, "m_axis") - else: - raise RuntimeError("failed to trace RFDC port for %s - ran into unrecognized IP block %s" % (self.fullpath, block)) - # port names are of the form 's00_axis' - self.dac = port[1:3] - - #print("%s: switch %d, tProc ch %d, DAC tile %s block %s"%(self.fullpath, self.switch_ch, self.tproc_ch, *self.dac)) - - def set_nyquist(self, nqz): - self.rf.set_nyquist(self.dac, nqz) - - def set_mixer_freq(self, f, ro_ch=None): - if not self.HAS_MIXER: - raise NotImplementedError("This channel does not have a mixer.") - if ro_ch is None: - rounded_f = f - else: - mixercfg = {} - mixercfg['f_dds'] = self['fs'] - mixercfg['b_dds'] = 48 - fstep = self.soc.calc_fstep(mixercfg, self.soc['readouts'][ro_ch]) - rounded_f = round(f/fstep)*fstep - self.rf.set_mixer_freq(self.dac, rounded_f) - - def get_mixer_freq(self): - if not self.HAS_MIXER: - raise NotImplementedError("This channel does not have a mixer.") - return self.rf.get_mixer_freq(self.dac) - -class AbsArbSignalGen(AbsSignalGen): - """ - A signal generator with a memory for envelope waveforms. - """ - # Name of the input driven by the waveform DMA (if applicable). - WAVEFORM_PORT = 's0_axis' - - def configure(self, ch, rf, fs): - # Define buffer. - self.buff = allocate(shape=self.MAX_LENGTH, dtype=np.int32) - - super().configure(ch, rf, fs) - - def configure_connections(self, soc): - super().configure_connections(soc) - - # what switch port drives this generator? - ((block, port),) = soc.metadata.trace_bus(self.fullpath, self.WAVEFORM_PORT) - # port names are of the form 'M01_AXIS' - self.switch_ch = int(port.split('_')[0][1:]) - - def configure_dma(self, axi_dma, axis_switch): - # dma - self.dma = axi_dma - - # Switch - self.switch = axis_switch - - # Load waveforms. - def load(self, xin, addr=0): - """ - Load waveform into I,Q envelope - - :param xin: array of (I, Q) values for pulse envelope - :type xin: int16 array - :param addr: starting address - :type addr: int - """ - length = xin.shape[0] - assert xin.dtype==np.int16 - - # Check for max length. - if length+addr > self.MAX_LENGTH: - raise RuntimeError("%s: buffer length must be %d samples or less." % - (self.__class__.__name__, self.MAX_LENGTH)) - - # Check for even transfer size. - #if length % 2 != 0: - # raise RuntimeError("Buffer transfer length must be even number.") - - # Route switch to channel. - self.switch.sel(mst=self.switch_ch) - - #print(self.fullpath, xin.shape, addr, self.switch_ch) - - # Pack the data into a single array; columns will be concatenated - # -> lower 16 bits: I value. - # -> higher 16 bits: Q value. - # Format and copy data. - np.copyto(self.buff[:length], - np.frombuffer(xin, dtype=np.int32)) - - ################ - ### Load I/Q ### - ################ - # Enable writes. - self._wr_enable(addr) - - # DMA data. - self.dma.sendchannel.transfer(self.buff, nbytes=int(length*4)) - self.dma.sendchannel.wait() - - # Disable writes. - self._wr_disable() - - def _wr_enable(self, addr=0): - """ - Enable WE reg - """ - self.start_addr_reg = addr - self.we_reg = 1 - - def _wr_disable(self): - """ - Disable WE reg - """ - self.we_reg = 0 - -class AbsPulsedSignalGen(AbsSignalGen): - """ - A signal generator controlled by the TProcessor. - """ - # Name of the input driven by the tProc (if applicable). - TPROC_PORT = 's1_axis' - - def configure(self, ch, rf, fs): - # DDS sampling frequency. - self.cfg['f_dds'] = fs/self.FS_INTERPOLATION - - self.cfg['maxlen'] = self.MAX_LENGTH - self.cfg['b_dds'] = self.B_DDS - self.cfg['switch_ch'] = self.switch_ch - self.cfg['f_fabric'] = self.soc.dacs[self.dac]['f_fabric'] - self.cfg['samps_per_clk'] = self.SAMPS_PER_CLK - self.cfg['maxv'] = self.MAXV - self.cfg['maxv_scale'] = self.MAXV_SCALE - - super().configure(ch, rf, fs) - - def configure_connections(self, soc): - super().configure_connections(soc) - - # what tProc output port drives this generator? - # we will eventually also use this to find out which tProc drives this gen, for multi-tProc firmwares - ((block, port),) = soc.metadata.trace_bus(self.fullpath, self.TPROC_PORT) - while True: - blocktype = soc.metadata.mod2type(block) - if blocktype in ["axis_tproc64x32_x8", "qick_processor"]: # we're done - break - elif blocktype == "axis_clock_converter": - ((block, port),) = soc.metadata.trace_bus(block, 'S_AXIS') - elif blocktype == "axis_cdcsync_v1": - # port name is of the form 'm4_axis' - follow corresponding input 's4_axis' - ((block, port),) = soc.metadata.trace_bus(block, "s"+port[1:]) - elif blocktype == "sg_translator": - ((block, port),) = soc.metadata.trace_bus(block, "s_tproc_axis") - else: - raise RuntimeError("failed to trace tProc port for %s - ran into unrecognized IP block %s" % (self.fullpath, block)) - # ask the tproc to translate this port name to a channel number - self.cfg['tproc_ch'] = getattr(soc, block).port2ch(port) - -class AxisSignalGen(AbsArbSignalGen, AbsPulsedSignalGen): - """ - AxisSignalGen class - Supports AxisSignalGen V4+V5+V6, since they have the same software interface (ignoring registers that are not used) - - AXIS Signal Generator Registers. - START_ADDR_REG - - WE_REG - * 0 : disable writes. - * 1 : enable writes. - """ - bindto = ['user.org:user:axis_signal_gen_v4:1.0', - 'user.org:user:axis_signal_gen_v5:1.0', - 'user.org:user:axis_signal_gen_v6:1.0'] - REGISTERS = {'start_addr_reg': 0, 'we_reg': 1, 'rndq_reg': 2} - SAMPS_PER_CLK = 16 - B_DDS = 32 - - def __init__(self, description): - """ - Constructor method - """ - super().__init__(description) - - # Default registers. - self.start_addr_reg = 0 - self.we_reg = 0 - self.rndq_reg = 10 - - # Generics - self.N = int(description['parameters']['N']) - self.NDDS = int(description['parameters']['N_DDS']) - - # Maximum number of samples - self.MAX_LENGTH = 2**self.N*self.NDDS - - def rndq(self, sel_): - """ - TODO: remove this function. This functionality was removed from IP block. - """ - self.rndq_reg = sel_ - -class AxisSgInt4V1(AbsArbSignalGen, AbsPulsedSignalGen): - """ - AxisSgInt4V1 - - The default max amplitude for this generator is 0.9 times the maximum of int16. - This is necessary to prevent interpolation overshoot: - the output of the interpolation filter may exceed the max value of the input points. - (https://blogs.keysight.com/blogs/tech/rfmw.entry.html/2019/05/07/confronting_measurem-IBRp.html) - The result of overshoot is integer overflow in the filter output and big negative spikes. - If the input to the filter is a square pulse, the rising edge of the output overshoots by 10%. - Therefore, scaling envelopes by 90% seems safe. - - AXIS Signal Generator with envelope x4 interpolation V1 Registers. - START_ADDR_REG - - WE_REG - * 0 : disable writes. - * 1 : enable writes. - """ - bindto = ['user.org:user:axis_sg_int4_v1:1.0'] - REGISTERS = {'start_addr_reg': 0, 'we_reg': 1} - HAS_MIXER = True - FS_INTERPOLATION = 4 - MAXV_SCALE = 0.9 - B_DDS = 16 - - def __init__(self, description): - """ - Constructor method - """ - super().__init__(description) - - # Default registers. - self.start_addr_reg = 0 - self.we_reg = 0 - - # Generics - self.N = int(description['parameters']['N']) - self.NDDS = 4 # Fixed by design, not accesible. - - # Maximum number of samples - # Table is interpolated. Length is given only by parameter N. - self.MAX_LENGTH = 2**self.N - - -class AxisSgMux4V1(AbsPulsedSignalGen): - """ - AxisSgMux4V1 - - AXIS Signal Generator with 4 muxed outputs V1 registers. - - PINC0_REG : frequency of tone 0. - PINC1_REG : frequency of tone 1. - PINC2_REG : frequency of tone 2. - PINC3_REG : frequency of tone 3. - - WE_REG - * 0 : disable writes. - * 1 : enable writes. - """ - bindto = ['user.org:user:axis_sg_mux4_v1:1.0'] - REGISTERS = {'pinc0_reg': 0, - 'pinc1_reg': 1, - 'pinc2_reg': 2, - 'pinc3_reg': 3, - 'we_reg': 4} - - HAS_MIXER = True - FS_INTERPOLATION = 4 - TPROC_PORT = 's_axis' - B_DDS = 16 - - def __init__(self, description): - """ - Constructor method - """ - super().__init__(description) - - # Generics - self.NDDS = int(description['parameters']['N_DDS']) - - # dummy values, since this doesn't have a waveform memory. - self.switch_ch = -1 - self.MAX_LENGTH = 0 - - # Default registers. - self.pinc0_reg = 0 - self.pinc1_reg = 0 - self.pinc2_reg = 0 - self.pinc3_reg = 0 - - self.update() - - def update(self): - """ - Update register values - """ - self.we_reg = 1 - self.we_reg = 0 - - def set_freq(self, f, out=0, ro_ch=0): - """ - Set frequency register - - :param f: frequency in MHz - :type f: float - :param out: muxed channel to configure - :type out: int - :param ro_ch: ADC channel (use None if you don't want to round to a valid ADC frequency) - :type ro_ch: int - """ - # Sanity check. - k_i = np.int64(self.soc.freq2reg(f, gen_ch=self.ch, ro_ch=ro_ch)) - self.set_freq_int(k_i, out) - - def set_freq_int(self, k_i, out=0): - if out not in [0,1,2,3]: - raise IndexError("Invalid output index for mux.") - setattr(self, "pinc%d_reg" % (out), np.uint16(k_i)) - - # Register update. - self.update() - - def get_freq(self, out=0): - return getattr(self, "pinc%d_reg" % (out)) * self['f_dds'] / (2**self.B_DDS) - -class AxisSgMux4V2(AbsPulsedSignalGen): - """ - AxisSgMux4V2 - - AXIS Signal Generator with 4 muxed outputs V2 registers. - - PINC0_REG : frequency of tone 0. - PINC1_REG : frequency of tone 1. - PINC2_REG : frequency of tone 2. - PINC3_REG : frequency of tone 3. - GAIN0_REG : gain of tone 0. - GAIN1_REG : gain of tone 1. - GAIN2_REG : gain of tone 2. - GAIN3_REG : gain of tone 3. - - WE_REG - * 0 : disable writes. - * 1 : enable writes. - """ - bindto = ['user.org:user:axis_sg_mux4_v2:1.0'] - REGISTERS = {'pinc0_reg':0, - 'pinc1_reg':1, - 'pinc2_reg':2, - 'pinc3_reg':3, - 'gain0_reg':4, - 'gain1_reg':5, - 'gain2_reg':6, - 'gain3_reg':7, - 'we_reg':8} - - HAS_MIXER = True - FS_INTERPOLATION = 4 - B_DDS = 32 - TPROC_PORT = 's_axis' - - def __init__(self, description): - """ - Constructor method - """ - super().__init__(description) - - # Generics - self.NDDS = int(description['parameters']['N_DDS']) - - # dummy values, since this doesn't have a waveform memory. - self.switch_ch = -1 - self.MAX_LENGTH = 0 - - # Default registers. - self.pinc0_reg=0 - self.pinc1_reg=0 - self.pinc2_reg=0 - self.pinc3_reg=0 - self.gain0_reg=self.MAXV - self.gain1_reg=self.MAXV - self.gain2_reg=self.MAXV - self.gain3_reg=self.MAXV - - self.update() - - def update(self): - """ - Update register values - """ - self.we_reg = 1 - self.we_reg = 0 - - def set_freq(self, f, out, ro_ch=0): - """ - Set frequency register - - :param f: frequency in MHz - :type f: float - :param out: muxed channel to configure - :type out: int - :param ro_ch: ADC channel (use None if you don't want to round to a valid ADC frequency) - :type ro_ch: int - """ - k_i = np.int64(self.soc.freq2reg(f, gen_ch=self.ch, ro_ch=ro_ch)) - self.set_freq_int(k_i, out) - - def set_freq_int(self, k_i, out): - if out not in range(4): - raise IndexError("Invalid output index for mux.") - setattr(self, "pinc%d_reg" % (out), np.uint32(k_i)) - - # Register update. - self.update() - - def get_freq(self, out): - return getattr(self, "pinc%d_reg" % (out)) * self['f_dds'] / (2**self.B_DDS) - - def set_gain(self, g, out): - """ - Set gain register - - :param g: gain (in range -1 to 1) - :type g: float - :param out: muxed channel to configure - :type out: int - """ - self.set_gain_int(np.round(g*self.MAXV), out) - - def set_gain_int(self, g_i, out): - # Sanity checks. - if out not in range(4): - raise IndexError("Invalid output index for mux.") - if np.abs(g_i)>self.MAXV: - raise RuntimeError("Requested gain exceeds max limit.") - setattr(self, "gain%d_reg" % (out), np.int16(g_i)) - - # Register update. - self.update() - -class AxisConstantIQ(AbsSignalGen): - # AXIS Constant IQ registers: - # REAL_REG : 16-bit. - # IMAG_REG : 16-bit. - # WE_REG : 1-bit. Update registers. - bindto = ['user.org:user:axis_constant_iq:1.0'] - REGISTERS = {'real_reg': 0, 'imag_reg': 1, 'we_reg': 2} - HAS_MIXER = True - - def __init__(self, description): - # Initialize ip - super().__init__(description) - - # Default registers. - self.real_reg = self.MAXV - self.imag_reg = self.MAXV - - # Register update. - self.update() - - def update(self): - self.we_reg = 1 - self.we_reg = 0 - - def set_iq(self, i=1, q=1): - # Set registers. - self.real_reg = np.int16(i*self.MAXV) - self.imag_reg = np.int16(q*self.MAXV) - - # Register update. - self.update() - - diff --git a/qick/qick_lib/qick/drivers/readout.py b/qick/qick_lib/qick/drivers/readout.py deleted file mode 100644 index 38401d2..0000000 --- a/qick/qick_lib/qick/drivers/readout.py +++ /dev/null @@ -1,793 +0,0 @@ -""" -Drivers for readouts (FPGA blocks that receive data from ADCs) and buffers (blocks that receive data from readouts). -""" -from pynq.buffer import allocate -import numpy as np -from qick import DummyIp, SocIp - -class AbsReadout(DummyIp): - # Configure this driver with the sampling frequency. - def configure(self, rf, fs): - self.rf = rf - # Sampling frequency. - self.fs = fs - self.cfg['fs'] = self.fs - self.cfg['adc'] = self.adc - self.cfg['b_dds'] = self.B_DDS - self.cfg['fs'] = self.rf.adccfg[self['adc']]['fs'] - self.cfg['f_dds'] = self.rf.adccfg[self['adc']]['fs'] - self.cfg['f_fabric'] = self.rf.adccfg[self['adc']]['f_fabric'] - - def initialize(self): - """ - Reset the readout configuration. - """ - pass - -class AxisReadoutV2(SocIp, AbsReadout): - """ - AxisReadoutV2 class - - Registers. - FREQ_REG : 32-bit. - - PHASE_REG : 32-bit. - - NSAMP_REG : 16-bit. - - OUTSEL_REG : 2-bit. - * 0 : product. - * 1 : dds. - * 2 : input (bypass). - - MODE_REG : 1-bit. - * 0 : NSAMP. - * 1 : Periodic. - - WE_REG : enable/disable to perform register update. - - :param fs: sampling frequency in MHz - :type fs: float - """ - bindto = ['user.org:user:axis_readout_v2:1.0'] - REGISTERS = {'freq_reg': 0, 'phase_reg': 1, 'nsamp_reg': 2, - 'outsel_reg': 3, 'mode_reg': 4, 'we_reg': 5} - - # Bits of DDS. - B_DDS = 32 - - # this readout is not controlled by the tProc. - tproc_ch = None - - def __init__(self, description): - """ - Constructor method - """ - super().__init__(description) - - # Default registers. - self.freq_reg = 0 - self.phase_reg = 0 - self.nsamp_reg = 10 - self.outsel_reg = 0 - self.mode_reg = 1 - - # Register update. - self.update() - - def configure_connections(self, soc): - self.soc = soc - - # what RFDC port drives this readout? - ((block, port),) = soc.metadata.trace_bus(self.fullpath, 's_axis') - # might need to jump through an axis_register_slice - while soc.metadata.mod2type(block) == "axis_register_slice": - ((block, port),) = soc.metadata.trace_bus(block, 'S_AXIS') - # port names are of the form 'm02_axis' where the block number is always even - iTile, iBlock = [int(x) for x in port[1:3]] - if soc.hs_adc: - iBlock //= 2 - self.adc = "%d%d" % (iTile, iBlock) - - # what buffer does this readout drive? - ((block, port),) = soc.metadata.trace_bus(self.fullpath, 'm1_axis') - blocktype = soc.metadata.mod2type(block) - if blocktype == "axis_broadcaster": - ((block, port),) = soc.metadata.trace_bus(block, 'M00_AXIS') - self.buffer = getattr(soc, block) - - #print("%s: ADC tile %s block %s, buffer %s"%(self.fullpath, *self.adc, self.buffer.fullpath)) - - def update(self): - """ - Update register values - """ - self.we_reg = 1 - self.we_reg = 0 - - def set_out(self, sel="product"): - """ - Select readout signal output - - :param sel: select mux control - :type sel: int - """ - self.outsel_reg = {"product": 0, "dds": 1, "input": 2}[sel] - - # Register update. - self.update() - - def set_freq(self, f, gen_ch=0): - """ - Set frequency register - - :param f: frequency in MHz (before adding any DAC mixer frequency) - :type f: float - :param gen_ch: DAC channel (use None if you don't want to round to a valid DAC frequency) - :type gen_ch: int - """ - thiscfg = {} - thiscfg['f_dds'] = self.fs - thiscfg['b_dds'] = self.B_DDS - # calculate the exact frequency we expect to see - ro_freq = f - if gen_ch is not None: # calculate the frequency that will be applied to the generator - ro_freq = self.soc.roundfreq(f, self.soc['gens'][gen_ch], thiscfg) - if gen_ch is not None and self.soc.gens[gen_ch].HAS_MIXER: - ro_freq += self.soc.gens[gen_ch].get_mixer_freq() - ro_freq = ro_freq % self.fs - # we can calculate the register value without further referencing the gen_ch - f_int = self.soc.freq2int(ro_freq, thiscfg) - self.set_freq_int(f_int) - - def set_freq_int(self, f_int): - """ - Set frequency register (integer version) - - :param f_int: frequency value register - :type f_int: int - """ - self.freq_reg = np.int64(f_int) - - # Register update. - self.update() - - def get_freq(self): - return self.freq_reg * self.fs / (2**self.B_DDS) - -class AxisPFBReadoutV2(SocIp, AbsReadout): - """ - AxisPFBReadoutV2 class. - - This readout block contains a polyphase filter bank with 8 channels. - Channel i mixes the input signal down by a fixed frequency f = i * fs/16, - then by a programmable DDS with a range of +/- fs/16. - - The PFB channels can be freely mapped to the 4 outputs of the readout block. - - Registers. - FREQ[0-7]_REG : 32-bit frequency of each channel. - - OUTSEL_REG : 2-bit. - * 0 : product. - * 1 : input (bypass). - * 2 : dds. - - CH[0-3]SEL_REG : 3-bit ID mapping an output channel to an input. - """ - bindto = ['user.org:user:axis_pfb_readout_v2:1.0'] - REGISTERS = {'freq0_reg': 0, - 'freq1_reg': 1, - 'freq2_reg': 2, - 'freq3_reg': 3, - 'freq4_reg': 4, - 'freq5_reg': 5, - 'freq6_reg': 6, - 'freq7_reg': 7, - 'outsel_reg': 8, - 'ch0sel_reg': 9, - 'ch1sel_reg': 10, - 'ch2sel_reg': 11, - 'ch3sel_reg': 12, - } - - # Bits of DDS. - # The channelizer DDS range is 1/8 of the sampling frequency, which effectively adds 3 bits of resolution. - B_DDS = 35 - - # index of the PFB channel that is centered around DC. - CH_OFFSET = 4 - - # this readout is not controlled by the tProc. - tproc_ch = None - - def __init__(self, description): - """ - Constructor method - """ - super().__init__(description) - self.initialize() - - def configure_connections(self, soc): - self.soc = soc - - # what RFDC port drives this readout? - ((block, port),) = soc.metadata.trace_bus(self.fullpath, 's_axis') - # might need to jump through an axis_register_slice - while soc.metadata.mod2type(block) == "axis_register_slice": - ((block, port),) = soc.metadata.trace_bus(block, 'S_AXIS') - if soc.metadata.mod2type(block) == "axis_combiner": - ((block, port),) = soc.metadata.trace_bus(block, 'S00_AXIS') - - # port names are of the form 'm02_axis' where the block number is always even - iTile, iBlock = [int(x) for x in port[1:3]] - if soc.hs_adc: - iBlock //= 2 - self.adc = "%d%d" % (iTile, iBlock) - - # what buffers does this readout drive? - self.buffers=[] - for iBuf in range(4): - ((block, port),) = soc.metadata.trace_bus(self.fullpath, 'm%d_axis'%(iBuf)) - self.buffers.append(getattr(soc, block)) - - #print("%s: ADC tile %s block %s, buffers[0] %s"%(self.fullpath, *self.adc, self.buffers[0].fullpath)) - - def initialize(self): - """ - Set up local variables to track definitions of frequencies or readout modes. - """ - self.ch_freqs = {} - self.sel = None - self.out_chs = {} - - def set_out(self, sel="product"): - """ - Select readout signal output - - :param sel: select mux control - :type sel: int - """ - if self.sel is not None and sel != self.sel: - raise RuntimeError("trying to set output mode to %s, but mode was previously set to %s"%(sel, self.sel)) - self.sel = sel - self.outsel_reg = {"product": 0, "input": 1, "dds": 2}[sel] - - def set_freq(self, f, out_ch, gen_ch=0): - """ - Select the best PFB channel for reading out the requested frequency. - Set that channel's frequency register, and wire that channel to the specified output of the PFB readout block. - - :param f: frequency in MHz (before adding any DAC mixer frequency) - :type f: float - :param out_ch: output channel - :type out_ch: int - :param gen_ch: DAC channel (use None if you don't want to round to a valid DAC frequency) - :type gen_ch: int - """ - thiscfg = {} - thiscfg['f_dds'] = self.fs - thiscfg['b_dds'] = self.B_DDS - # calculate the exact frequency we expect to see - ro_freq = f - if gen_ch is not None: # calculate the frequency that will be applied to the generator - ro_freq = self.soc.roundfreq(f, self.soc['gens'][gen_ch], thiscfg) - if gen_ch is not None and self.soc.gens[gen_ch].HAS_MIXER: - ro_freq += self.soc.gens[gen_ch].get_mixer_freq() - - nqz = int(ro_freq // (self.fs/2)) + 1 - if nqz % 2 == 0: # even Nyquist zone - ro_freq *= -1 - # the PFB channels are separated by half the DDS range - # round() gives you the single best channel - # floor() and ceil() would give you the 2 best channels - # if you have two RO frequencies close together, you might need to force one of them onto a non-optimal channel - f_steps = int(np.round(ro_freq/(self.fs/16))) - f_dds = ro_freq - f_steps*(self.fs/16) - in_ch = (self.CH_OFFSET + f_steps) % 8 - - # we can calculate the register value without further referencing the gen_ch - freq_int = self.soc.freq2int(f_dds, thiscfg) - self.set_freq_int(freq_int, in_ch, out_ch) - - def set_freq_int(self, f_int, in_ch, out_ch): - if in_ch in self.ch_freqs and f_int != self.ch_freqs[in_ch]: - # we are already using this PFB channel, and it's set to a different frequency - # now do a bunch of math to print an informative message - centerfreq = ((in_ch - self.CH_OFFSET) % 8) * (self.fs/16) - lofreq = centerfreq - self.fs/32 - hifreq = centerfreq + self.fs/32 - thiscfg = {} - thiscfg['f_dds'] = self.fs - thiscfg['b_dds'] = self.B_DDS - oldfreq = centerfreq + self.soc.int2freq(self.ch_freqs[in_ch], thiscfg) - newfreq = centerfreq + self.soc.int2freq(f_int, thiscfg) - raise RuntimeError("frequency collision: tried to set PFB output %d to %f MHz and output %d to %f MHz, but both map to the PFB channel that is optimal for [%f, %f] (all freqs expressed in first Nyquist zone)"%(out_ch, newfreq, self.out_chs[in_ch], oldfreq, lofreq, hifreq)) - self.ch_freqs[in_ch] = f_int - self.out_chs[in_ch] = out_ch - # wire the selected PFB channel to the output - setattr(self, "ch%dsel_reg"%(out_ch), in_ch) - # set the PFB channel's DDS frequency - setattr(self, "freq%d_reg"%(in_ch), f_int) - -class AxisReadoutV3(AbsReadout): - """tProc-controlled readout block. - This isn't a PYNQ driver, since the block has no registers for PYNQ control. - We still need this class to represent the block and its connectivity. - """ - # Bits of DDS. - B_DDS = 32 - - def __init__(self, fullpath): - super().__init__("axis_readout_v3", fullpath) - - def configure(self, rf, fs): - super().configure(rf, fs) - self.cfg['tproc_ctrl'] = self.tproc_ch - # there is a 2x1 resampler between the RFDC and readout, which doubles the effective fabric frequency. - self.cfg['f_fabric'] *= 2 - - def configure_connections(self, soc): - self.soc = soc - - # what tProc output port controls this readout? - ((block, port),) = soc.metadata.trace_bus(self['fullpath'], 's0_axis') - while True: - blocktype = soc.metadata.mod2type(block) - if blocktype == "axis_tproc64x32_x8": # we're done - break - elif blocktype == "axis_clock_converter": - ((block, port),) = soc.metadata.trace_bus(block, 'S_AXIS') - elif blocktype == "axis_cdcsync_v1": - # port name is of the form 'm4_axis' - follow corresponding input 's4_axis' - ((block, port),) = soc.metadata.trace_bus(block, "s"+port[1:]) - else: - raise RuntimeError("failed to trace tProc port for %s - ran into unrecognized IP block %s" % (self.fullpath, block)) - # port names are of the form 'm2_axis_tdata' - # subtract 1 to get the output channel number (m0 goes to the DMA) - self.tproc_ch = int(port.split('_')[0][1:])-1 - - # what RFDC port drives this readout? - ((block, port),) = soc.metadata.trace_bus(self['fullpath'], 's1_axis') - while True: - blocktype = soc.metadata.mod2type(block) - if blocktype == "usp_rf_data_converter": # we're done - break - elif blocktype == "axis_resampler_2x1_v1": - ((block, port),) = soc.metadata.trace_bus(block, 's_axis') - elif blocktype == "axis_register_slice": - ((block, port),) = soc.metadata.trace_bus(block, 'S_AXIS') - elif blocktype == "axis_clock_converter": - ((block, port),) = soc.metadata.trace_bus(block, 'S_AXIS') - else: - raise RuntimeError("failed to trace tProc port for %s - ran into unrecognized IP block %s" % (self.fullpath, block)) - - # port names are of the form 'm02_axis' where the block number is always even - iTile, iBlock = [int(x) for x in port[1:3]] - if soc.hs_adc: - iBlock //= 2 - self.adc = "%d%d" % (iTile, iBlock) - - # what buffer does this readout drive? - ((block, port),) = soc.metadata.trace_bus(self['fullpath'], 'm_axis') - self.buffer = getattr(soc, block) - - #print("%s: ADC tile %s block %s, buffer %s"%(self.fullpath, *self.adc, self.buffer.fullpath)) - -class AxisAvgBuffer(SocIp): - """ - AxisAvgBuffer class - - Registers. - AVG_START_REG - * 0 : Averager Disabled. - * 1 : Averager Enabled (started by external trigger). - - AVG_ADDR_REG : start address to write results. - - AVG_LEN_REG : number of samples to be added. - - AVG_DR_START_REG - * 0 : do not send any data. - * 1 : send data using m0_axis. - - AVG_DR_ADDR_REG : start address to read data. - - AVG_DR_LEN_REG : number of samples to be read. - - BUF_START_REG - * 0 : Buffer Disabled. - * 1 : Buffer Enabled (started by external trigger). - - BUF_ADDR_REG : start address to write results. - - BUF_LEN_REG : number of samples to be buffered. - - BUF_DR_START_REG - * 0 : do not send any data. - * 1 : send data using m1_axis. - - BUF_DR_ADDR_REG : start address to read data. - - BUF_DR_LEN_REG : number of samples to be read. - - :param axi_dma_avg: dma block for average buffers - :type axi_dma_avg: str - :param switch_avg: switch block for average buffers - :type switch_avg: str - :param axi_dma_buf: dma block for raw buffers - :type axi_dma_buf: str - :param switch_buf: switch block for raw buffers - :type switch_buf: str - :param channel: readout channel selection - :type channel: int - """ - bindto = ['user.org:user:axis_avg_buffer:1.0'] - REGISTERS = {'avg_start_reg': 0, - 'avg_addr_reg': 1, - 'avg_len_reg': 2, - 'avg_dr_start_reg': 3, - 'avg_dr_addr_reg': 4, - 'avg_dr_len_reg': 5, - 'buf_start_reg': 6, - 'buf_addr_reg': 7, - 'buf_len_reg': 8, - 'buf_dr_start_reg': 9, - 'buf_dr_addr_reg': 10, - 'buf_dr_len_reg': 11} - - def __init__(self, description): - """ - Constructor method - """ - super().__init__(description) - - # Default registers. - self.avg_start_reg = 0 - self.avg_dr_start_reg = 0 - self.buf_start_reg = 0 - self.buf_dr_start_reg = 0 - - # Generics - self.B = int(description['parameters']['B']) - self.N_AVG = int(description['parameters']['N_AVG']) - self.N_BUF = int(description['parameters']['N_BUF']) - - # Maximum number of samples - self.AVG_MAX_LENGTH = 2**self.N_AVG - self.BUF_MAX_LENGTH = 2**self.N_BUF - - # Preallocate memory buffers for DMA transfers. - self.avg_buff = allocate(shape=self.AVG_MAX_LENGTH, dtype=np.int64) - self.buf_buff = allocate(shape=self.BUF_MAX_LENGTH, dtype=np.int32) - - # Configure this driver with links to the other drivers. - def configure(self, axi_dma_avg, switch_avg, axi_dma_buf, switch_buf): - # DMAs. - self.dma_avg = axi_dma_avg - self.dma_buf = axi_dma_buf - - # Switches. - self.switch_avg = switch_avg - self.switch_buf = switch_buf - - self.cfg['avg_maxlen'] = self.AVG_MAX_LENGTH - self.cfg['buf_maxlen'] = self.BUF_MAX_LENGTH - self.cfg['trigger_bit'] = self.trigger_bit - self.cfg['tproc_ch'] = self.tproc_ch - - def configure_connections(self, soc): - # which readout drives this buffer? - ((block, port),) = soc.metadata.trace_bus(self.fullpath, 's_axis') - blocktype = soc.metadata.mod2type(block) - - if blocktype == "axis_broadcaster": - ((block, port),) = soc.metadata.trace_bus(block, 'S_AXIS') - blocktype = soc.metadata.mod2type(block) - - if blocktype == "axis_readout_v3": - # the V3 readout block has no registers, so it doesn't get a PYNQ driver - # so we initialize it here - self.readout = AxisReadoutV3(block) - self.readout.configure_connections(soc) - else: - self.readout = getattr(soc, block) - if blocktype == "axis_pfb_readout_v2": - # port names are of the form 'm1_axis' - self.readoutport = int(port.split('_')[0][1:], 10) - - # which switch_avg port does this buffer drive? - ((block, port),) = soc.metadata.trace_bus(self.fullpath, 'm0_axis') - # port names are of the form 'S01_AXIS' - switch_avg_ch = int(port.split('_')[0][1:], 10) - - # which switch_buf port does this buffer drive? - ((block, port),) = soc.metadata.trace_bus(self.fullpath, 'm1_axis') - # port names are of the form 'S01_AXIS' - switch_buf_ch = int(port.split('_')[0][1:], 10) - if switch_avg_ch != switch_buf_ch: - raise RuntimeError( - "switch_avg and switch_buf port numbers do not match:", self.fullpath) - self.switch_ch = switch_avg_ch - - # which tProc output bit triggers this buffer? - ((block, port),) = soc.metadata.trace_sig(self.fullpath, 'trigger') - # port names are of the form 'dout14' - self.trigger_bit = int(port[4:]) - - # which tProc input port does this buffer drive? - ((block, port),) = soc.metadata.trace_bus(self.fullpath, 'm2_axis') - # jump through an axis_clk_cnvrt - while soc.metadata.mod2type(block) == "axis_clock_converter": - ((block, port),) = soc.metadata.trace_bus(block, 'M_AXIS') - # port names are of the form 's1_axis' - # subtract 1 to get the channel number (s0 comes from the DMA) - if soc.metadata.mod2type(block) in ["axis_tproc64x32_x8", "qick_processor"]: - # ask the tproc to translate this port name to a channel number - self.tproc_ch = getattr(soc, block).port2ch(port) - else: - # this buffer doesn't feed back into the tProc - self.tproc_ch = -1 - - # print("%s: readout %s, switch %d, trigger %d, tProc port %d"% - # (self.fullpath, self.readout.fullpath, self.switch_ch, self.trigger_bit, self.tproc_ch)) - - def set_freq(self, f, gen_ch=0): - """ - Set the downconversion frequency on the readout that drvies this buffer. - - :param f: frequency in MHz (before adding any DAC mixer frequency) - :type f: float - :param gen_ch: DAC channel (use None if you don't want to round to a valid DAC frequency) - :type gen_ch: int - """ - if isinstance(self.readout, AxisPFBReadoutV2): - self.readout.set_freq(f, self.readoutport, gen_ch=gen_ch) - else: - self.readout.set_freq(f, gen_ch=gen_ch) - - def config(self, address=0, length=100): - """ - Configure both average and raw buffers - - :param addr: Start address of first capture - :type addr: int - :param length: window size - :type length: int - """ - # Configure averaging and buffering to the same address and length. - self.config_avg(address=address, length=length) - self.config_buf(address=address, length=length) - - def enable(self): - """ - Enable both average and raw buffers - """ - # Enable both averager and buffer. - self.enable_avg() - self.enable_buf() - - def config_avg(self, address=0, length=100): - """ - Configure average buffer data from average and buffering readout block - - :param addr: Start address of first capture - :type addr: int - :param length: window size - :type length: int - """ - # Disable averaging. - self.disable_avg() - - # Set registers. - self.avg_addr_reg = address - self.avg_len_reg = length - - def transfer_avg(self, address=0, length=100): - """ - Transfer average buffer data from average and buffering readout block. - - :param addr: starting reading address - :type addr: int - :param length: number of samples - :type length: int - :return: I,Q pairs - :rtype: list - """ - - if length % 2 != 0: - raise RuntimeError("Buffer transfer length must be even number.") - if length >= self.AVG_MAX_LENGTH: - raise RuntimeError("length=%d longer than %d" % - (length, self.AVG_MAX_LENGTH)) - - # Route switch to channel. - self.switch_avg.sel(slv=self.switch_ch) - - # Set averager data reader address and length. - self.avg_dr_addr_reg = address - self.avg_dr_len_reg = length - - # Start send data mode. - self.avg_dr_start_reg = 1 - - # DMA data. - buff = self.avg_buff - # nbytes has to be a Python int (it gets passed to mmio.write, which requires int or bytes) - self.dma_avg.recvchannel.transfer(buff, nbytes=int(length*8)) - self.dma_avg.recvchannel.wait() - - # Stop send data mode. - self.avg_dr_start_reg = 0 - - if self.dma_avg.recvchannel.transferred != length*8: - raise RuntimeError("Requested %d samples but only got %d from DMA" % ( - length, self.dma_avg.recvchannel.transferred//8)) - - # Format: - # -> lower 32 bits: I value. - # -> higher 32 bits: Q value. - data = np.frombuffer(buff[:length], dtype=np.int32).reshape((-1,2)) - - # data is a view into the data buffer, so copy it before returning - - return data.copy() - - def enable_avg(self): - """ - Enable average buffer capture - """ - self.avg_start_reg = 1 - - def disable_avg(self): - """ - Disable average buffer capture - """ - self.avg_start_reg = 0 - - def config_buf(self, address=0, length=100): - """ - Configure raw buffer data from average and buffering readout block - - :param addr: Start address of first capture - :type addr: int - :param length: window size - :type length: int - """ - # Disable buffering. - self.disable_buf() - - # Set registers. - self.buf_addr_reg = address - self.buf_len_reg = length - - def transfer_buf(self, address=0, length=100): - """ - Transfer raw buffer data from average and buffering readout block - - :param addr: starting reading address - :type addr: int - :param length: number of samples - :type length: int - :return: I,Q pairs - :rtype: list - """ - - if length % 2 != 0: - raise RuntimeError("Buffer transfer length must be even number.") - if length >= self.BUF_MAX_LENGTH: - raise RuntimeError("length=%d longer or equal to %d" % - (length, self.BUF_MAX_LENGTH)) - - # Route switch to channel. - self.switch_buf.sel(slv=self.switch_ch) - - # time.sleep(0.050) - - # Set buffer data reader address and length. - self.buf_dr_addr_reg = address - self.buf_dr_len_reg = length - - # Start send data mode. - self.buf_dr_start_reg = 1 - - # DMA data. - buff = self.buf_buff - # nbytes has to be a Python int (it gets passed to mmio.write, which requires int or bytes) - self.dma_buf.recvchannel.transfer(buff, nbytes=int(length*4)) - self.dma_buf.recvchannel.wait() - - if self.dma_buf.recvchannel.transferred != length*4: - raise RuntimeError("Requested %d samples but only got %d from DMA" % ( - length, self.dma_buf.recvchannel.transferred//4)) - - # Stop send data mode. - self.buf_dr_start_reg = 0 - - # Format: - # -> lower 16 bits: I value. - # -> higher 16 bits: Q value. - data = np.frombuffer(buff[:length], dtype=np.int16).reshape((-1,2)) - - # data is a view into the data buffer, so copy it before returning - return data.copy() - - def enable_buf(self): - """ - Enable raw buffer capture - """ - self.buf_start_reg = 1 - - def disable_buf(self): - """ - Disable raw buffer capture - """ - self.buf_start_reg = 0 - - -class MrBufferEt(SocIp): - # Registers. - # DW_CAPTURE_REG - # * 0 : Capture disabled. - # * 1 : Capture enabled (capture started by external trigger). - # - # DR_START_REG - # * 0 : don't send. - # * 1 : start sending data. - # - # DW_CAPTURE_REG needs to be de-asserted and asserted again to allow a new capture. - # DR_START_REG needs to be de-assereted and asserted again to allow a new transfer. - # - bindto = ['user.org:user:mr_buffer_et:1.0'] - REGISTERS = {'dw_capture_reg': 0, 'dr_start_reg': 1} - - def __init__(self, description): - # Init IP. - super().__init__(description) - - # Default registers. - self.dw_capture_reg = 0 - self.dr_start_reg = 0 - - # Generics - self.B = int(description['parameters']['B']) - self.N = int(description['parameters']['N']) - self.NM = int(description['parameters']['NM']) - - # Maximum number of samples - self.MAX_LENGTH = 2**self.N * self.NM - - # Preallocate memory buffers for DMA transfers. - #self.buff = allocate(shape=self.MAX_LENGTH, dtype=np.int32) - self.buff = allocate(shape=self.MAX_LENGTH, dtype=np.int16) - - def config(self, dma, switch): - self.dma = dma - self.switch = switch - - def route(self, ch): - # Route switch to channel. - self.switch.sel(slv=ch) - - def transfer(self, buff=None): - if buff is None: - buff = self.buff - # Start send data mode. - self.dr_start_reg = 1 - - # DMA data. - self.dma.recvchannel.transfer(buff) - self.dma.recvchannel.wait() - - # Stop send data mode. - self.dr_start_reg = 0 - - return buff - - def enable(self): - self.dw_capture_reg = 1 - - def disable(self): - self.dw_capture_reg = 0 - - diff --git a/qick/qick_lib/qick/drivers/tproc.py b/qick/qick_lib/qick/drivers/tproc.py deleted file mode 100644 index d78a56e..0000000 --- a/qick/qick_lib/qick/drivers/tproc.py +++ /dev/null @@ -1,860 +0,0 @@ -""" -Drivers for the QICK timed processor (tProc). -""" -from pynq.buffer import allocate -import numpy as np -from qick import SocIp - -class AxisTProc64x32_x8(SocIp): - """ - AxisTProc64x32_x8 class - - AXIS tProcessor registers: - START_SRC_REG - * 0 : internal start (using START_REG) - * 1 : external start (using "start" input) - - Regardless of the START_SRC, the start logic triggers on a rising edge: - A low level arms the trigger (transitions from "end" to "init" state). - A high level fires the trigger (starts the program). - To stop a running program, see reset(). - - START_REG - * 0 : init - * 1 : start - - MEM_MODE_REG - * 0 : AXIS Read (from memory to m0_axis) - * 1 : AXIS Write (from s0_axis to memory) - - MEM_START_REG - * 0 : Stop. - * 1 : Execute operation (AXIS) - - MEM_ADDR_REG : starting memory address for AXIS read/write mode. - - MEM_LEN_REG : number of samples to be transferred in AXIS read/write mode. - - DMEM: The internal data memory is 2^DMEM_N samples, 32 bits each. - The memory can be accessed either single read/write from AXI interface. The lower 256 Bytes are reserved for registers. - The memory is then accessed in the upper section (beyond 256 bytes). Byte to sample conversion needs to be performed. - The other method is to DMA in and out. Here the access is direct, so no conversion is needed. - There is an arbiter to ensure data coherency and avoid blocking transactions. - - :param mem: memory address - :type mem: int - :param axi_dma: axi_dma address - :type axi_dma: int - """ - bindto = ['user.org:user:axis_tproc64x32_x8:1.0'] - REGISTERS = {'start_src_reg': 0, - 'start_reg': 1, - 'mem_mode_reg': 2, - 'mem_start_reg': 3, - 'mem_addr_reg': 4, - 'mem_len_reg': 5} - - # Number of 32-bit words in the lower address map (reserved for register access) - NREG = 64 - - def __init__(self, description): - """ - Constructor method - """ - super().__init__(description) - - # Default registers. - # start_src_reg = 0 : internal start. - # start_reg = 0 : stopped. - # mem_mode_reg = 0 : axis read. - # mem_start_reg = 0 : axis operation stopped. - # mem_addr_reg = 0 : start address = 0. - # mem_len_reg = 100 : default length. - self.start_src_reg = 0 - self.start_reg = 0 - self.mem_mode_reg = 0 - self.mem_start_reg = 0 - self.mem_addr_reg = 0 - self.mem_len_reg = 100 - - # Generics. - # data memory address size (log2 of the number of 32-bit words) - self.DMEM_N = int(description['parameters']['DMEM_N']) - # program memory address size (log2 of the number of 64-bit words, though the actual memory is usually smaller) - self.PMEM_N = int(description['parameters']['PMEM_N']) - - self.cfg['dmem_size'] = 2**self.DMEM_N - - # Configure this driver with links to its memory and DMA. - def configure(self, mem, axi_dma): - # Program memory. - self.mem = mem - - # dma - self.dma = axi_dma - - self.cfg['pmem_size'] = self.mem.mmio.length//8 - - def configure_connections(self, soc): - self.cfg['output_pins'] = [] - self.cfg['start_pin'] = None - try: - ((port),) = soc.metadata.trace_sig(self.fullpath, 'start') - # check if the start pin is driven by a port of the top-level design - if len(port)==1: - self.cfg['start_pin'] = port[0] - except: - pass - # search for the trigger port - for i in range(8): - # what block does this output drive? - # add 1, because output 0 goes to the DMA - try: - ((block, port),) = soc.metadata.trace_bus(self.fullpath, 'm%d_axis' % (i+1)) - except: # skip disconnected tProc outputs - continue - if soc.metadata.mod2type(block) == "axis_set_reg": - self.cfg['trig_output'] = i - ((block, port),) = soc.metadata.trace_sig(block, 'dout') - for iPin in range(16): - try: - ports = soc.metadata.trace_sig(block, "dout%d"%(iPin)) - if len(ports)==1 and len(ports[0])==1: - # it's an FPGA pin, save it - pinname = ports[0][0] - self.cfg['output_pins'].append((iPin, pinname)) - except KeyError: - pass - - def port2ch(self, portname): - """ - Translate a port name to a channel number. - Used in connection mapping. - """ - # port names are of the form 'm2_axis' (for outputs) and 's2_axis (for inputs) - # subtract 1 to get the output channel number (s0/m0 goes to the DMA) - return int(portname.split('_')[0][1:])-1 - - def start(self): - """ - Start tProc from register. - This has no effect if the tProc is not in init or end state, - or if the start source is set to "external." - """ - self.start_reg = 0 - self.start_reg = 1 - - def reset(self): - """ - Force the tProc to stop by filling the program memory with "end" instructions. - For speed, we hard-code the "end" instruction and write directly to the program memory. - This typically takes about 1 ms. - """ - # we only write the high half of each program word, the low half doesn't matter - np.copyto(self.mem.mmio.array[1::2],np.uint32(0x3F000000)) - - def single_read(self, addr): - """ - Reads one sample of tProc data memory using AXI access - - :param addr: reading address - :type addr: int - :return: requested value - :rtype: int - """ - # Read data. - # Address should be translated to upper map. - return self.mmio.array[addr + self.NREG] - - def single_write(self, addr=0, data=0): - """ - Writes one sample of tProc data memory using AXI access - - :param addr: writing address - :type addr: int - :param data: value to be written - :type data: int - """ - # Write data. - # Address should be translated to upper map. - self.mmio.array[addr + self.NREG] = np.uint32(data) - - def load_dmem(self, buff_in, addr=0): - """ - Writes tProc data memory using DMA - - :param buff_in: Input buffer - :type buff_in: int - :param addr: Starting destination address - :type addr: int - """ - # Length. - length = len(buff_in) - - # Configure dmem arbiter. - self.mem_mode_reg = 1 - self.mem_addr_reg = addr - self.mem_len_reg = length - - # Define buffer. - self.buff = allocate(shape=length, dtype=np.int32) - - # Copy buffer. - np.copyto(self.buff, buff_in) - - # Start operation on block. - self.mem_start_reg = 1 - - # DMA data. - self.dma.sendchannel.transfer(self.buff) - self.dma.sendchannel.wait() - - # Set block back to single mode. - self.mem_start_reg = 0 - - def read_dmem(self, addr=0, length=100): - """ - Reads tProc data memory using DMA - - :param addr: Starting address - :type addr: int - :param length: Number of samples - :type length: int - :return: List of memory data - :rtype: list - """ - # Configure dmem arbiter. - self.mem_mode_reg = 0 - self.mem_addr_reg = addr - self.mem_len_reg = length - - # Define buffer. - buff = allocate(shape=length, dtype=np.int32) - - # Start operation on block. - self.mem_start_reg = 1 - - # DMA data. - self.dma.recvchannel.transfer(buff) - self.dma.recvchannel.wait() - - # Set block back to single mode. - self.mem_start_reg = 0 - - return buff - -class Axis_QICK_Proc(SocIp): - """ - Axis_QICK_Proc class - - #################### - AXIS T_PROC xREG - #################### - TPROC_CTRL Write / Read 32-Bits - TPROC_CFG Write / Read 32-Bits - MEM_ADDR Write / Read 16-Bits - MEM_LEN Write / Read 16-Bits - MEM_DT_I Write / Read 32-Bits - TPROC_W_DT1 Write / Read 32-Bits - TPROC_W_DT2 Write / Read 32-Bits - CORE_CFG Write / Read 32-Bits - READ_SEL Write / Read 32-Bits - MEM_DT_O Read Only 32-Bits - TPROC_R_DT1 Read Only 32-Bits - TPROC_R_DT2 Read Only 32-Bits - TIME_USR Read Only 32-Bits - TPROC_STATUS Read Only 32-Bits - TPROC_DEBUG Read Only 32-Bits - #################### - TPROC_CTRL[0] - Time Reset : Reset absTimer - TPROC_CTRL[1] - Time Update : Update absTimer - TPROC_CTRL[2] - Proc Start : Reset and Starts tProc (Time and cores) - TPROC_CTRL[3] - Proc Stop : Stop the tProc - TPROC_CTRL[4] - Core Start : Reset and Starts the Cores. - TPROC_CTRL[5] - Core Stop : Stop the Cores (Time will continue Running) - TPROC_CTRL[6] - Proc Reset : Reset the TProc - TPROC_CTRL[7] - Proc Run : Reset the TProc - TPROC_CTRL[8] - Proc Pause : Pause the TProc (Time RUN, Core NO) - TPROC_CTRL[9] - Proc Freeze : Freeze absTimer (Core RUN, Time no) - TPROC_CTRL[10] - Proc Step : Debug - Step tProc(Time and CORE ) - TPROC_CTRL[11] - Core Step : Debug - Step Core (Execute ONE instruction) - TPROC_CTRL[12] - Time Step : Debug - Step Timer (Increase absTimer in 1) - TPROC_CTRL[13] - COND_set : Set External Condition Flag from - TPROC_CTRL[14] - COND_clear : Clears External Condition Flag from - #################### - TPROC_CFG[0] - MEM_START - TPROC_CFG[1] - MEM_OPERATION - TPROC_CFG[3:2] - MEM_TYPE (00-NONE, 01-PMEM, 10-DMEM, 11-WMEM) - TPROC_CFG[4] - MEM_SOURCE (0-AXI, 1-SINGLE) - TPROC_CFG[6:5] - MEM_BANK (TPROC, CORE0, CORE1) - TPROC_CFG[10] - Disable INPUT CTRL - TPROC_CFG[11] - WFIFO_Full Pause Core - TPROC_CFG[12] - DFIFO_Full Pause Core - - - :param mem: memory address - :type mem: int - :param axi_dma: axi_dma address - :type axi_dma: int - """ - bindto = ['Fermi:user:qick_processor:2.0'] - - REGISTERS = { - 'tproc_ctrl' :0 , - 'tproc_cfg' :1 , - 'mem_addr' :2 , - 'mem_len' :3 , - 'mem_dt_i' :4 , - 'tproc_w_dt1' :5, - 'tproc_w_dt2' :6, - 'core_cfg' :7, - 'read_sel' :8, - - 'mem_dt_o' :10, - 'tproc_r_dt1' :11 , - 'tproc_r_dt2' :12 , - 'time_usr' :13, - 'tproc_status' :14, - 'tproc_debug' :15 - } - - def __init__(self, description): - """ - Constructor method - """ - super().__init__(description) - - # Parameters - #self.cfg['dual_core'] = = int(description['parameters']['DUAL_CORE']) - #self.cfg['debug'] = = int(description['parameters']['DEBUG']) - # Parameters - self.cfg['pmem_size'] = pow( 2, int(description['parameters']['PMEM_AW']) ) - self.cfg['dmem_size'] = pow( 2, int(description['parameters']['DMEM_AW']) ) - self.cfg['wmem_size'] = pow( 2, int(description['parameters']['WMEM_AW']) ) - self.cfg['dreg_qty'] = pow( 2, int(description['parameters']['REG_AW']) ) - for param in ['in_port_qty', 'out_trig_qty', 'out_dport_qty','out_dport_dw', 'out_wport_qty']: - self.cfg[param] = int(description['parameters'][param.upper()]) - for param in ['lfsr', 'divider', 'arith', 'time_read', 'tnet', 'custom_periph', 'io_ctrl']: - self.cfg['has_'+param] = int(description['parameters'][param.upper()]) - - - # Initial Values - self.tproc_ctrl = 0 - self.tproc_cfg = 0 - self.mem_addr = 0 - self.mem_len = 0 - self.mem_dt_i = 0 - self.tproc_w_dt1 = 0 - self.tproc_w_dt2 = 0 - self.core_cfg = 0 - self.read_sel = 0 - - #Compatible with previous Version - self.DMEM_N = int(description['parameters']['DMEM_AW']) - - - # Configure this driver with links to its memory and DMA. - def configure(self, axi_dma): - # dma - self.dma = axi_dma - - # allocate DMA buffers, using the size of the largest memory - maxlen = max(self['dmem_size'], self['pmem_size'], self['wmem_size']) - self.buff_wr = allocate(shape=(maxlen, 8), dtype=np.int32) - self.buff_rd = allocate(shape=(maxlen, 8), dtype=np.int32) - - - def configure_connections(self, soc): - self.cfg['output_pins'] = [] - self.cfg['start_pin'] = None - self.cfg['trig_output'] = 0 - try: - ((port),) = soc.metadata.trace_sig(self.fullpath, 'start') - self.start_pin = port[0] - except: - pass - # WE have trig_%d_o and port_%d_dt_o as OUT of the QICK_PROCESSOR... - # those can go to vec2bits or to the output... - ## Number of triggers is in ther parameter 'out_trig_qty', the MAX is 8 - ## Number of data ports is in ther parameter 'out_dport_qty', the MAX is 4 - for iPin in range(self['out_trig_qty']): - try: - ports = soc.metadata.trace_sig(self.fullpath, "trig_%d_o"%(iPin)) - print(iPin, ports) - if len(ports)==1 and len(ports[0])==1: - # it's an FPGA pin, save it - pinname = ports[0][0] - self.cfg['output_pins'].append((iPin, pinname)) - except KeyError: - pass - # search for the trigger port - for i in range(self['out_dport_qty']): - # what block does this output drive? - # add 1, because output 0 goes to the DMA - try: - ((block, port),) = soc.metadata.trace_sig(self.fullpath, 'port_%d_dt_o' % (i)) - except: # skip disconnected tProc outputs - continue - if soc.metadata.mod2type(block).startswith("vect2bits"): - self.cfg['trig_output'] = i - for iPin in range(16): - try: - #print(iPin, trace_net(sigparser, block, "dout%d"%(iPin))) - ports = soc.metadata.trace_sig(block, "dout%d"%(iPin)) - if len(ports)==1 and len(ports[0])==1: - # it's an FPGA pin, save it - pinname = ports[0][0] - self.cfg['output_pins'].append((iPin, pinname)) - except KeyError: - pass - - - def port2ch(self, portname): - """ - Translate a port name to a channel number. - Used in connection mapping. - """ - # port names are of the form 'm2_axis' (for outputs) and 's2_axis (for inputs) - return int(portname.split('_')[0][1:]) - - - def time_reset(self): - self.logger.info('TIME_RESET') - self.tproc_ctrl = 1 - def time_update(self): - self.logger.info('TIME_UPDATE') - self.tproc_ctrl = 2 - def proc_start(self): - self.logger.info('PROCESSOR_START') - self.tproc_ctrl = 4 - def proc_stop(self): - self.logger.info('PROCESSOR_STOP') - self.tproc_ctrl = 8 - def core_start(self): - self.logger.info('CORE_START') - self.tproc_ctrl = 16 - def core_stop(self): - self.logger.info('CORE_STOP') - self.tproc_ctrl = 32 - def proc_reset(self): - self.logger.info('PROCESSOR_RESET') - self.tproc_ctrl = 64 - def proc_run(self): - self.logger.info('PROCESSOR_RUN') - self.tproc_ctrl = 128 - def proc_pause(self): - self.logger.info('PROCESSOR_PAUSE') - self.tproc_ctrl = 256 - def proc_freeze(self): - self.logger.info('PROCESSOR_FREEZE') - self.tproc_ctrl = 512 - def proc_step(self): - self.logger.info('PROCESSOR_STEP') - self.tproc_ctrl = 1024 - def core_step(self): - self.logger.info('CORE_STEP') - self.tproc_ctrl = 2048 - def time_step(self): - self.logger.info('TIME_STEP') - self.tproc_ctrl = 4096 - def set_cond(self): - self.logger.info('SET CONDITION') - self.tproc_ctrl = 8192 - def clear_cond(self): - self.logger.info('CLEAR CONDITION') - self.tproc_ctrl = 16384 - - def __str__(self): - lines = [] - lines.append('---------------------------------------------') - lines.append(' TPROC V2 INFO ') - lines.append('---------------------------------------------') - for param in ["pmem_size", "dmem_size", "wmem_size", "dreg_qty"]: - lines.append("%-14s: %d" % (param, self.cfg[param]) ) - for param in ['in_port_qty', 'out_trig_qty', 'out_dport_qty','out_dport_dw', 'out_wport_qty']: - lines.append("%-14s: %d" % (param, self.cfg[param]) ) - lines.append("\nConfiguration:") - #for param in ['dual_core','debug', 'io_ctrl']: - for param in ['has_io_ctrl']: - lines.append("%-14s: %s" % (param, ["NO", "YES"][self.cfg[param]])) - lines.append("\nPeripherals:") - for param in ['has_lfsr', 'has_divider', 'has_arith', 'has_time_read', 'has_tnet', 'has_custom_periph']: - lines.append("%-14s: %s" % (param, ["NO", "YES"][self.cfg[param]])) - return "\n".join(lines) - def info(self): - print(self) - - def single_read(self, mem_sel, addr): - """ - Reads the bottom 32 bits of one sample of tProc memory using AXI access - Do not use! Use the DMA instead. - - :param addr: reading address - :type addr: int - :return: requested value - :rtype: int - """ - # Read data. - self.mem_addr = i - self.tproc_cfg = 0x11 + (mem_sel << 2) - val = self.mem_dt_o - self.tproc_cfg = 0 - return val - - def single_write(self, mem_sel, addr=0, data=0): - """ - Writes the bottom 32 bits of one sample of tProc memory using AXI access - Do not use! This seems to crash the DMA. Use the DMA instead. - - :param addr: writing address - :type addr: int - :param data: value to be written - :type data: int - """ - # Write data. - self.mem_addr = i - self.tproc_cfg = 0x13 + (mem_sel << 2) - self.mem_dt_i = data - self.tproc_cfg = 0 - - def load_mem(self,mem_sel, buff_in, addr=0): - """ - Writes tProc Selected memory using DMA - - Parameters - ---------- - mem_sel : int - PMEM=1, DMEM=2, WMEM=3 - buff_in : array - Data to be loaded - addr : int - Starting write address - """ - # Length. - length = len(buff_in) - # Configure Memory arbiter. (Write MEM) - self.mem_addr = addr - self.mem_len = length - - # Copy buffer. - np.copyto(self.buff_wr[:length], buff_in) - #Start operation - if (mem_sel==1): # WRITE PMEM - self.tproc_cfg |= 7 - elif (mem_sel==2): # WRITE DMEM - self.tproc_cfg |= 11 - elif (mem_sel==3): # WRITE WMEM - self.tproc_cfg |= 15 - else: - raise RuntimeError('Destination Memeory error should be PMEM=1, DMEM=2, WMEM=3 current Value : %d' % (mem_sel)) - - # DMA data. - self.logger.debug('DMA write 1') - self.dma.sendchannel.transfer(self.buff_wr, nbytes=int(length*32)) - self.logger.debug('DMA write 2') - self.dma.sendchannel.wait() - self.logger.debug('DMA write 3') - - # End Operation - self.tproc_cfg &= ~63 - - def read_mem(self,mem_sel, addr=0, length=100): - """ - Read tProc Selected memory using DMA - - Parameters - ---------- - mem_sel : int - PMEM=1, DMEM=2, WMEM=3 - addr : int - Starting read address - length : int - Number of words to read - """ - # Configure Memory arbiter. (Read DMEM) - self.mem_addr = addr - self.mem_len = length - - #Start operation - if (mem_sel==1): # READ PMEM - self.tproc_cfg |= 5 - elif (mem_sel==2): # READ DMEM - self.tproc_cfg |= 9 - elif (mem_sel==3): # READ WMEM - self.tproc_cfg |= 13 - else: - raise RuntimeError('Source Memeory error should be PMEM=1, DMEM=2, WMEM=3 current Value : %d' % (mem_sel)) - - # DMA data. - self.logger.debug('DMA read 1') - self.dma.recvchannel.transfer(self.buff_rd, nbytes=int(length*32)) - self.logger.debug('DMA read 2') - self.dma.recvchannel.wait() - self.logger.debug('DMA read 3') - - # End Operation - self.tproc_cfg &= ~63 - - # truncate and copy - return self.buff_rd[:length].copy() - - def Load_PMEM(self, p_mem, check=True): - length = len(p_mem) - - self.logger.info('Loading Program in PMEM') - self.load_mem(1, p_mem) - - if check: - readback = self.read_mem(1, length=length) - if ( (np.max(readback - p_mem) ) == 0): - self.logger.info('Program Loaded OK') - else: - self.logger.error('Error Loading Program') - - - def get_axi(self): - print('---------------------------------------------') - print('--- AXI Registers') - for xreg in self.REGISTERS.keys(): - print(f'{xreg:>15}', getattr(self, xreg)) - - def get_proc_status(self): - proc_st = ['T_RST','P_RST','RST_WAIT','T_INIT','STOP','PLAY','PAUSE','UPDATE','FREEZE','END_STEP'] - status_num = self.tproc_status - status_bin = '{:032b}'.format(status_num) - print('---------------------------------------------') - print('--- AXI TPROC Register STATUS') - print(status_bin) - p_st = int(status_bin[29:32], 2) - print('--- PROCESSOR -- ') - print( 'PROC_ST : ' + status_bin[29:32] +' - '+ proc_st[p_st]) - print( 'CORE_EN : ' + status_bin[27] ) - print( 'TIME_EN : ' + status_bin[26] ) - print( 'PROC_RST : ' + status_bin[25] ) - print( 'EXT_COND : ' + status_bin[23] ) - print( 'PORT_DT_NEW : ' + status_bin[22] ) - print( 'FLAG_C0 : ' + status_bin[21] ) - print( 'ALL_DFIFO_EMPTY : ' + status_bin[19] ) - print( 'ALL_WFIFO_EMPTY : ' + status_bin[18] ) - print( 'ALL_DFIFO_FULL : ' + status_bin[17] ) - print( 'ALL_WFIFO_FULL : ' + status_bin[16] ) - print( 'DFIFO_FULL : ' + status_bin[15] ) - print( 'WFIFO_FULL : ' + status_bin[14] ) - print( 'FIFO_OK : ' + status_bin[13] ) - print('--- MEMORY -- ') - print( 'AW_EXEC : ' + status_bin[4] ) - print( 'AR_EXEC : ' + status_bin[3] ) - print( 'MEM_WE_SINGLE : ' + status_bin[2] ) - print( 'MEM_OP : ' + status_bin[0] ) - def get_proc_debug(self): - debug_num = self.tproc_debug - debug_bin = '{:032b}'.format(debug_num) - print('---------------------------------------------') - print('--- AXI TPROC Register DEBUG') - print(debug_bin) - print( 'USER_TIME : ' + debug_bin[24:32] + ' - ' +str(int(debug_bin[24:32], 2))) - print( 'REF_TIME : ' + debug_bin[16:24] + ' - ' +str(int(debug_bin[16:24], 2))) - print( 'EXT_MEM_W_DT_O[7:0] : ' + debug_bin[8 :16] + ' - ' +str(int(debug_bin[8:16], 2))) - print( 'EXT_MEM_ADDR[7:0] : ' + debug_bin[0 :8 ] + ' - ' +str(int(debug_bin[0:8], 2))) - def get_core_status(self): - status_num = self.core0_status - status_bin = '{:032b}'.format(status_num) - print('---------------------------------------------') - print('--- AXI CORE Register STATUS') - print(status_bin) - p_st = int(status_bin[29:32], 2) - print('--- PROCESSOR -- ') - print( 'ARITH_DT_NEW : ' + status_bin[31] ) - print( 'DIV_DT_NEW : ' + status_bin[30] ) - print( 'TNET_DT_NEW : ' + status_bin[29] ) - print( 'PERIPH_DT_NEW : ' + status_bin[28] ) - print( 'ARITH_RDY : ' + status_bin[27] ) - print( 'DIV_RDY : ' + status_bin[26] ) - print( 'TNET_RDY : ' + status_bin[25] ) - print( 'PERIPH_RDY : ' + status_bin[24] ) - print( 'DFIFO_FULL : ' + status_bin[23] ) - print( 'DFIFO_EMPTY : ' + status_bin[22] ) - print( 'WFIFO_FULL : ' + status_bin[21] ) - print( 'WFIFO_EMPTY : ' + status_bin[20] ) - def get_core_debug(self): - debug_num = self.core0_debug - debug_bin = '{:032b}'.format(debug_num) - print('---------------------------------------------') - print('--- AXI TPROC Register DEBUG') - print(debug_bin) - print( 'PORT_O.P_TIME[7:0] : ' + debug_bin[24:32] + ' - ' +str(int(debug_bin[24:32], 2))) - print( 'R_X1_ALU_DT[7:0] : ' + debug_bin[16:24] + ' - ' +str(int(debug_bin[16:24], 2))) - print( 'ID_DMEM_WE : ' + debug_bin[8 :16] + ' - ' +str(int(debug_bin[8:16], 2))) - print( 'ID_DREG_WE : ' + debug_bin[0 :8 ] + ' - ' +str(int(debug_bin[0:8], 2))) - print( 'ID_REG_WR : ' + debug_bin[0 :8 ] + ' - ' +str(int(debug_bin[0:8], 2))) - print( 'ID_MEM_WR : ' + debug_bin[0 :8 ] + ' - ' +str(int(debug_bin[0:8], 2))) - print( 'ID_REG_WR : ' + debug_bin[0 :8 ] + ' - ' +str(int(debug_bin[0:8], 2))) - print( 'ID_BRANCH : ' + debug_bin[0 :8 ] + ' - ' +str(int(debug_bin[0:8], 2))) - print( 'ID_DREG_WE : ' + debug_bin[0 :8 ] + ' - ' +str(int(debug_bin[0:8], 2))) - print( 'ID_CFG : ' + debug_bin[0 :8 ] + ' - ' +str(int(debug_bin[0:8], 2))) - print( 'ID_DREG_WE : ' + debug_bin[0 :8 ] + ' - ' +str(int(debug_bin[0:8], 2))) - -class Axis_QICK_Net(SocIp): - """ - Axis_QICK_Proc class - - #################### - AXIS T_CORE xREG - #################### - CORE_CTRL Write / Read 32-Bits - CORE_CFG Write / Read 32-Bits - RAXI_DT1 Write / Read 32-Bits - RAXI_DT2 Write / Read 32-Bits - CORE_R_DT1 Read Only 32-Bits - CORE_R_DT2 Read Only 32-Bits - PORT_LSW Read Only 32-Bits - PORT_MSW Read Only 32-Bits - RAND Read Only 32-Bits - CORE_W_DT1 Read Only 32-Bits - CORE_W_DT2 Read Only 32-Bits - CORE_STATUS Read Only 32-Bits - CORE_DEBUG Read Only 32-Bits - - :param mem: memory address - :type mem: int - :param axi_dma: axi_dma address - :type axi_dma: int - """ - bindto = ['Fermi:user:qick_net:1.0'] - - REGISTERS = { - 'tnet_ctrl' :0 , - 'tnet_cfg' :1 , - 'tnet_addr' :2 , - 'tnet_len' :3 , - 'raxi_dt1' :4 , - 'raxi_dt2' :5 , - 'raxi_dt3' :6 , - 'nn' :7 , - 'id' :8, - 'cd' :9, - 'rtd' :10, - 'version' :11, - 'tnet_w_dt1' :12, - 'tnet_w_dt2' :13, - 'tnet_status' :14, - 'tnet_debug' :15 - } - - def __init__(self, description): - """ - Constructor method - """ - super().__init__(description) - - - # Initial Values - self.tnet_ctrl = 0 - self.tnet_cfg = 0 - self.tnet_addr = 0 - self.mem_len = 100 - self.tnet_len = 0 - self.raxi_dt1 = 0 - self.raxi_dt2 = 0 - self.raxi_dt3 = 0 - - # Configure this driver with links to its memory and DMA. - def configure(self, mem, axi_dma): - # Program memory. - self.mem = mem - # dma - self.dma = axi_dma - - - def clear_cond(self): - self.logger.info('RESET') - self.tproc_ctrl = 2048 - - def get_axi(self): - print('---------------------------------------------') - print('--- AXI Registers') - for xreg in self.REGISTERS.keys(): - print(f'{xreg:>15}', getattr(self, xreg)) - def get_status(self): - status_num = self.tnet_status - status_bin = '{:032b}'.format(status_num) - print('---------------------------------------------') - print('--- AXI TNET Register STATUS') - print(status_bin) - print( ' MMC_LOCKED : ' + status_bin[31] ) - print( ' GT_PLL_LOCK : ' + status_bin[30] ) - print( ' LANE_A_UP : ' + status_bin[29] ) - print( ' CHANNEL_A_UP : ' + status_bin[28] ) - print( ' CHANNEL_B_UP : ' + status_bin[27] ) - print( ' AURORA_RDY : ' + status_bin[26] ) - print( ' AURORA_ST : ' + str(int(status_bin[23:26],2)) ) - print( '--------------------------------') - print( ' CMD_ID : ' + status_bin[19:23] ) - print( ' CMD_DST : ' + status_bin[16:19] ) - print( ' CMD_SRC : ' + status_bin[13:16] ) - print( '--------------------------------') - print( ' GET_NET : ' + status_bin[10] ) - print( ' SET_NET : ' + status_bin[9] ) - print( ' SYNC_NET : ' + status_bin[8] ) - print( ' UPDT_OFF : ' + status_bin[7] ) - print( ' RST_TPROC : ' + status_bin[6] ) - print( ' START_TPROC : ' + status_bin[5] ) - print( ' STOP_TPROC : ' + status_bin[4] ) - print( ' SET_DT : ' + status_bin[3] ) - print( ' GET_DT : ' + status_bin[2] ) - print( ' SET_COND : ' + status_bin[1] ) - print( ' CLEAR_COND : ' + status_bin[0] ) - - def get_debug(self): - cmd_list = ['RST_0','>NET_GNET_P', '>NET_SYNC_P', '>NET_GNET_R', 'LOC_GNET', 'LOC_SNET', 'LOC_SYNC', 'LOC_UPDT_OFF',\ - 'LOC_SET_DT', 'LOC_GET_DT', 'NET_GNET_P', 'NET_SNET_P', 'NET_SYNC_P', 'NET_UPDT_OFF_P', 'NET_SET_DT_P', 'NET_GET_DT_P',\ - 'NET_GNET_R', 'NET_SNET_R', 'NET_SYNC_R', 'NET_UPDT_OFF_R', 'NET_SET_DT_R', 'NET_GET_DT_R', 'RST_1', 'RST_2',\ - 'NET_GET_DT_A', 'NOT_READY', 'TIMEOUR', 'TX_ACK', 'CMD_nACK'] - task_list = ['NOT_READY','IDLE','LOC_CMD','LOC_WSYNC','LOC_SEND','LOC_WnREQ','NET_CMD','NET_WSYNC','NET_SEND','NET_WnREQ'] - debug_num = self.tnet_debug - debug_bin = '{:032b}'.format(debug_num) - task_st = int(debug_bin[19:23], 2) - cmd0_st = int(debug_bin[10:15], 2) - cmd1_st = int(debug_bin[5:10], 2) - cmd2_st = int(debug_bin[0:5], 2) - print('---------------------------------------------') - print('--- AXI TNET Register DEBUG') - print(debug_bin) - print( ' AURORA_CNT : ' + debug_bin[27:32] ) - print( ' AURORA_OP : ' + debug_bin[23:27] ) - print( ' TASK_ST : ' + str(task_st) + ' - ' + task_list[task_st]) - print( ' MAIN_ST : ' + debug_bin[15:19] ) - #print( ' TASK_ST : ' + debug_bin[19:23] ) - print( ' T0 : ' + str(cmd0_st) + ' - ' + cmd_list[cmd0_st]) - print( ' T1 : ' + str(cmd1_st) + ' - ' + cmd_list[cmd1_st]) - print( ' T2 : ' + str(cmd2_st) + ' - ' + cmd_list[cmd2_st]) - - def get_sth(self): - cmd_list = ['RST_0','>NET_GNET_P', '>NET_SYNC_P', '>NET_GNET_R', 'LOC_GNET', 'LOC_SNET', 'LOC_SYNC', 'LOC_UPDT_OFF',\ - 'LOC_SET_DT', 'LOC_GET_DT', 'NET_GNET_P', 'NET_SNET_P', 'NET_SYNC_P', 'NET_UPDT_OFF_P', 'NET_SET_DT_P', 'NET_GET_DT_P',\ - 'NET_GNET_R', 'NET_SNET_R', 'NET_SYNC_R', 'NET_UPDT_OFF_R', 'NET_SET_DT_R', 'NET_GET_DT_R', 'RST_1', 'RST_2',\ - 'NET_GET_DT_A', 'NOT_READY', 'TIMEOUT', 'TX_ACK', 'CMD_nACK >> IDLE', 'ERROR', 'TX_nACK'] - task_list = ['NOT_READY','IDLE','LOC_CMD','LOC_WSYNC','LOC_SEND','LOC_WnREQ','NET_CMD','NET_WSYNC','NET_SEND','NET_WnREQ'] - debug_num = self.tnet_debug - debug_bin = '{:032b}'.format(debug_num) - task_st = int(debug_bin[19:23], 2) - ver_num = self.version - ver_bin = '{:032b}'.format(ver_num) - cmd0_st = int(ver_bin[25:30], 2) - cmd1_st = int(ver_bin[20:25], 2) - cmd2_st = int(ver_bin[15:20], 2) - cmd3_st = int(ver_bin[10:15], 2) - cmd4_st = int(ver_bin[5:10], 2) - cmd5_st = int(ver_bin[0:5], 2) - print('---------------------------------------------') - print( ' AURORA_CNT : ' + debug_bin[27:32] ) - print( ' AURORA_OP : ' + debug_bin[23:27] ) - print( ' TASK_ST : ' + str(task_st) + ' - ' + task_list[task_st]) - print( ' MAIN_ST : ' + debug_bin[15:19] ) - print( ' T0 : ' + str(cmd0_st) + ' - ' + cmd_list[cmd0_st]) - print( ' T1 : ' + str(cmd1_st) + ' - ' + cmd_list[cmd1_st]) - print( ' T2 : ' + str(cmd2_st) + ' - ' + cmd_list[cmd2_st]) - print( ' T3 : ' + str(cmd3_st) + ' - ' + cmd_list[cmd3_st]) - print( ' T4 : ' + str(cmd4_st) + ' - ' + cmd_list[cmd4_st]) - print( ' T5 : ' + str(cmd5_st) + ' - ' + cmd_list[cmd5_st]) - diff --git a/qick/qick_lib/qick/helpers.py b/qick/qick_lib/qick/helpers.py deleted file mode 100644 index baa4e01..0000000 --- a/qick/qick_lib/qick/helpers.py +++ /dev/null @@ -1,137 +0,0 @@ -""" -Support functions. -""" -from typing import Union, List -import numpy as np -import json -import base64 -from collections import OrderedDict - - -def gauss(mu=0, si=25, length=100, maxv=30000): - """ - Create a numpy array containing a Gaussian function - - :param mu: Mu (peak offset) of Gaussian - :type mu: float - :param sigma: Sigma (standard deviation) of Gaussian - :type sigma: float - :param length: Length of array - :type length: int - :param maxv: Maximum amplitude of Gaussian - :type maxv: float - :return: Numpy array containing a Gaussian function - :rtype: array - """ - x = np.arange(0, length) - y = maxv * np.exp(-(x-mu)**2/si**2) - return y - - -def DRAG(mu, si, length, maxv, delta, alpha): - """ - Create I and Q arrays for a DRAG pulse. - Based on QubiC and Qiskit-Pulse implementations. - - :param mu: Mu (peak offset) of Gaussian - :type mu: float - :param si: Sigma (standard deviation) of Gaussian - :type si: float - :param length: Length of array - :type length: int - :param maxv: Maximum amplitude of Gaussian - :type maxv: float - :param delta: anharmonicity of the qubit (units of 1/sample time) - :type delta: float - :param alpha: alpha parameter of DRAG (order-1 scale factor) - :type alpha: float - :return: Numpy array with I and Q components of the DRAG pulse - :rtype: array, array - """ - x = np.arange(0, length) - gaus = maxv * np.exp(-(x-mu)**2/si**2) - # derivative of the gaussian - dgaus = -(x-mu)/(si**2)*gaus - idata = gaus - qdata = -1 * alpha * dgaus / delta - return idata, qdata - - -def triang(length=100, maxv=30000): - """ - Create a numpy array containing a triangle function - - :param length: Length of array - :type length: int - :param maxv: Maximum amplitude of triangle function - :type maxv: float - :return: Numpy array containing a triangle function - :rtype: array - """ - y = np.zeros(length) - - # if length is even, there are length//2 samples in the ramp - # if length is odd, there are length//2 + 1 samples in the ramp - halflength = (length + 1) // 2 - - y1 = np.linspace(0, maxv, halflength) - y[:halflength] = y1 - y[length//2:length] = np.flip(y1) - return y - -class NpEncoder(json.JSONEncoder): - """ - JSON encoder with support for numpy objects. - Taken from https://stackoverflow.com/questions/50916422/python-typeerror-object-of-type-int64-is-not-json-serializable - """ - def default(self, obj): - if isinstance(obj, np.integer): - return int(obj) - if isinstance(obj, np.floating): - return float(obj) - if isinstance(obj, np.ndarray): - # base64 is considerably more compact and faster to pack/unpack - # return obj.tolist() - return (base64.b64encode(obj.tobytes()).decode(), obj.shape, obj.dtype.str) - return super().default(obj) - -def progs2json(proglist): - return json.dumps(proglist, cls=NpEncoder) - -def json2progs(s): - if hasattr(s, 'read'): - # input is file-like, we should use json.load() - # be sure to read dicts back in order (only matters for Python <3.7) - proglist = json.load(s, object_pairs_hook=OrderedDict) - else: - # input is string or bytes - # be sure to read dicts back in order (only matters for Python <3.7) - proglist = json.loads(s, object_pairs_hook=OrderedDict) - - for progdict in proglist: - # tweak data structures that got screwed up by JSON: - # in JSON, dict keys are always strings, so we must cast back to int - progdict['gen_chs'] = OrderedDict([(int(k),v) for k,v in progdict['gen_chs'].items()]) - progdict['ro_chs'] = OrderedDict([(int(k),v) for k,v in progdict['ro_chs'].items()]) - # the envelope arrays need to be restored as numpy arrays with the proper type - for iCh, pulsedict in enumerate(progdict['pulses']): - for name, pulse in pulsedict.items(): - #pulse['data'] = np.array(pulse['data'], dtype=self._gen_mgrs[iCh].env_dtype) - data, shape, dtype = pulse['data'] - pulse['data'] = np.frombuffer(base64.b64decode(data), dtype=np.dtype(dtype)).reshape(shape) - return proglist - -def ch2list(ch: Union[List[int], int]) -> List[int]: - """ - convert a channel number or a list of ch numbers to list of integers - - :param ch: channel number or list of channel numbers - :return: list of channel number(s) - """ - if ch is None: - return [] - try: - ch_list = [int(ch)] - except TypeError: - ch_list = ch - return ch_list diff --git a/qick/qick_lib/qick/ip.py b/qick/qick_lib/qick/ip.py deleted file mode 100644 index ea8de93..0000000 --- a/qick/qick_lib/qick/ip.py +++ /dev/null @@ -1,191 +0,0 @@ -""" -Support classes for dealing with FPGA IP blocks. -""" -from pynq.overlay import DefaultIP -import numpy as np -import logging -from qick import obtain -from .qick_asm import DummyIp - -class SocIp(DefaultIP, DummyIp): - """ - Base class for firmware IP drivers. - Registers are accessed as attributes. - Configuration constants are accessed as dictionary items. - """ - REGISTERS = {} - - def __init__(self, description): - """ - Constructor method - """ - DefaultIP.__init__(self, description) - # this block's unique identifier in the firmware - self.fullpath = description['fullpath'] - # this block's type - self.type = description['type'].split(':')[-2] - DummyIp.__init__(self, self.type, self.fullpath) - # logger for messages associated with this block - self.logger = logging.getLogger(self.type) - - def __setattr__(self, a, v): - """ - Sets the arguments associated with a register - - :param a: Register specified by an offset value - :type a: int - :param v: value to be written - :type v: int - """ - try: - index = self.REGISTERS[a] - self.mmio.array[index] = np.uint32(obtain(v)) - except KeyError: - super().__setattr__(a, v) - - def __getattr__(self, a): - """ - Gets the arguments associated with a register - - :param a: register name - :type a: str - :return: Register arguments - :rtype: *args object - """ - try: - index = self.REGISTERS[a] - return self.mmio.array[index] - except KeyError: - return super().__getattribute__(a) - -class QickMetadata: - """ - Provides information about the connections between IP blocks, extracted from the HWH file. - The HWH parser is very different between PYNQ 2.6/2.7 and 3.0+, so this class serves as a common interface. - """ - def __init__(self, soc): - # We will use the HWH parser to extract information about signal connections between blocks. - self.sigparser = None - self.busparser = None - self.systemgraph = None - self.xml = None - - if hasattr(soc, 'systemgraph'): - # PYNQ 3.0 and higher have a "system graph" - self.systemgraph = soc.systemgraph - # TODO: We shouldn't need to use BusParser, but we think there's a bug in how pynqmetadata handles axis_switch. - self.busparser = BusParser(self.systemgraph._root) - self.xml = soc.systemgraph._element_tree - else: - self.sigparser = soc.parser - # Since the HWH parser doesn't parse buses, we also make our own BusParser. - self.busparser = BusParser(self.sigparser.root) - self.xml = soc.parser.root - - def trace_sig(self, blockname, portname): - if self.systemgraph is not None: - dests = self.systemgraph.blocks[blockname].ports[portname].destinations() - result = [] - for port, block in dests.items(): - blockname = block.parent().name - if blockname==self.systemgraph.name: - result.append([port]) - else: - result.append([blockname, port]) - return result - - return self._trace_net(self.sigparser, blockname, portname) - - def trace_bus(self, blockname, portname): - return self._trace_net(self.busparser, blockname, portname) - - def _trace_net(self, parser, blockname, portname): - """ - Find the block and port that connect to this block and port. - If you expect to only get one block+port as a result, you can assign the result to ((block, port),) - - :param parser: HWH parser object (from Overlay.parser, or BusParser) - :param blockname: the IP block of interest - :type blockname: string - :param portname: the port we want to trace - :type portname: string - - :return: a list of [block, port] pairs, or just [port] for ports of the top-level design - :rtype: list - """ - fullport = blockname+"/"+portname - # the net connected to this port - netname = parser.pins[fullport] - if netname == '__NOC__': - return [] - # get the list of other ports on this net, discard the port we started at and ILA ports - return [x.split('/') for x in parser.nets[netname] if x != fullport and 'system_ila_' not in x] - - def get_fclk(self, blockname, portname): - """ - Find the frequency of a clock port. - - :param parser: HWH parser object (from Overlay.parser, or BusParser) - :param blockname: the IP block of interest - :type blockname: string - :param portname: the port we want to trace - :type portname: string - - :return: frequency in MHz - :rtype: float - """ - xmlpath = "./MODULES/MODULE[@FULLNAME='/{0}']/PORTS/PORT[@NAME='{1}']".format( - blockname, portname) - port = self.xml.find(xmlpath) - return float(port.get('CLKFREQUENCY'))/1e6 - - def get_param(self, blockname, parname): - """ - Find the value of an IP parameter. This works for all IPs, including those that do not show up in ip_dict because they're not addressable. - - :param parser: HWH parser object (from Overlay.parser, or BusParser) - :param blockname: the IP block of interest - :type blockname: string - :param parname: the parameter of interest - :type parname: string - - :return: parameter value - :rtype: string - """ - xmlpath = "./MODULES/MODULE[@FULLNAME='/{0}']/PARAMETERS/PARAMETER[@NAME='{1}']".format( - blockname, parname) - param = self.xml.find(xmlpath) - return param.get('VALUE') - - def mod2type(self, blockname): - if self.systemgraph is not None: - return self.systemgraph.blocks[blockname].vlnv.name - return self.busparser.mod2type[blockname] - -class BusParser: - def __init__(self, root): - """ - Matching all the buses in the modules from the HWH file. - This is essentially a copy of the HWH parser's match_nets() and match_pins(), - but working on buses instead of signals. - - In addition, there's a map from module names to module types. - - :param root: HWH XML tree (from Overlay.parser.root) - """ - self.nets = {} - self.pins = {} - self.mod2type = {} - for module in root.findall('./MODULES/MODULE'): - fullpath = module.get('FULLNAME').lstrip('/') - self.mod2type[fullpath] = module.get('MODTYPE') - for bus in module.findall('./BUSINTERFACES/BUSINTERFACE'): - port = fullpath + '/' + bus.get('NAME') - busname = bus.get('BUSNAME') - self.pins[port] = busname - if busname in self.nets: - self.nets[busname] |= set([port]) - else: - self.nets[busname] = set([port]) - - diff --git a/qick/qick_lib/qick/ipq_pynq_utils/LICENSE b/qick/qick_lib/qick/ipq_pynq_utils/LICENSE deleted file mode 100644 index 57e770d..0000000 --- a/qick/qick_lib/qick/ipq_pynq_utils/LICENSE +++ /dev/null @@ -1,29 +0,0 @@ -BSD 3-Clause License - -Copyright (c) 2022, Karlsruhe Institute of Technology - Institute of Photonics and Quantum Electronics (IPQ) -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - -* Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - -* Neither the name of the copyright holder nor the names of its - contributors may be used to endorse or promote products derived from - this software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/qick/qick_lib/qick/ipq_pynq_utils/README.md b/qick/qick_lib/qick/ipq_pynq_utils/README.md deleted file mode 100644 index d9e0f55..0000000 --- a/qick/qick_lib/qick/ipq_pynq_utils/README.md +++ /dev/null @@ -1,6 +0,0 @@ -# IPQ PYNQ Utilities -This code is a subset of the PYNQ utilities developed by KIT-IPQ, with modifications to suit use in QICK. -While the original project is used mainly to configure the CLK104 daughterboard on the ZCU208/216, we are using the same code to configure the LMX2594 oscillator on the V2 RF board. - -The original project can be found at https://github.com/kit-ipq/ipq-pynq-utils. -The license (which includes attribution) is preserved without modification in this directory. diff --git a/qick/qick_lib/qick/ipq_pynq_utils/clock_models.py b/qick/qick_lib/qick/ipq_pynq_utils/clock_models.py deleted file mode 100644 index 2448d19..0000000 --- a/qick/qick_lib/qick/ipq_pynq_utils/clock_models.py +++ /dev/null @@ -1,1038 +0,0 @@ -""" -Implements different clock / PLL models for easy manipulation without vendor software. -""" - -import json -import re -import numpy as np -#from . import utils -import os -import fractions -from collections import defaultdict - -class EnumVal: - def __init__(self, name, value, description): - self.name = name - self.value = value - self.description = description - self.__doc__ = self.description - - @property - def __pydoc__(self): - return self.description - - def get(self): - return self.value - - def __str__(self): - return self.name - - def __repr__(self): - return self.name - -class ConstantField: - def __init__(self, field): - self.end = field["end"] - self.start = field["start"] - self.value = field["value"] - self.name = "CONST" - self.description = "" - - self.width = self.end - self.start + 1 - self.mask = ((1 << self.width) - 1) << self.start - - def get(self): - return self.value - - def get_raw(self): - return self.mask & (self.value << self.start) - - def parse(self, obj): - pass - - @property - def value_description(self): - return "" - - def __str__(self): - return str(self.value) - - def __repr__(self): - return str(self.value) - -class Field: - def __init__(self, field): - self.end = field["end"] - self.start = field["start"] - self.width = self.end - self.start + 1 - self.mask = ((1 << self.width) - 1) << self.start - - self.name = field["name"] - self.description = field["description"] - self.__doc__ = self.description - self.default = field["default"] if "default" in field else 0 - self.value = self.default - - self.enum_map = {} - - valid = field["valid"] - self.valid_type = valid["type"] - - if self.valid_type == "int": - pass # ?? - elif self.valid_type == "constant": - self.default = valid["value"] - self.value = valid["value"] - elif self.valid_type == "enum": - for value in valid["values"]: - enum_val = EnumVal(**value) - assert getattr(self, value["name"], None) is None, f"Duplicate enum value in field {self.name}: {value['name']}" - setattr(self, value["name"], enum_val) - self.enum_map[enum_val.value] = enum_val - else: - raise RuntimeError("Unknown valid type: " + self.valid_type) - - def get(self): - if self.valid_type == "enum": - if self.value in self.enum_map: - return self.enum_map[self.value] - else: - return "BAD ENUM VALUE" - return self.value - - def set(self, value): - if self.value_type == "enum": - if not isinstance(value, EnumVal): - raise RuntimeError("Expected enum value!") - else: - self.value = value.value - else: - self.value = value - - def get_raw(self): - return self.mask & (self.value << self.start) - - def parse(self, data): - self.value = (data & self.mask) >> self.start - - def set(self, val): - if isinstance(val, int): - self.value = val - elif isinstance(val, EnumVal): - self.value = val.value - else: - raise RuntimeError("Unsupported type!") - - def reset(self): - self.value = self.default - - @property - def value_description(self): - if self.valid_type == "enum": - if self.value in self.enum_map: - return self.enum_map[self.value].description - else: - return "BAD ENUM VALUE" - return "" - - def __str__(self): - return str(self.__dict__) - - def __repr__(self): - return str(self.__dict__) - -class Register: - def __init__(self, obj, dw=8): - self.addr = obj["addr"] - self.fields = [] - self.dw = dw - self.regdef = obj - - for field in self.regdef["fields"]: - fieldtype = field["fieldtype"] - if fieldtype == "constant": - self.fields.append(ConstantField(field)) - elif fieldtype == "normal": - newfield = Field(field) - newfield.index = len(self.fields) - self.fields.append(newfield) - else: - raise RuntimeError("Unsupported field type!") - - def reset(self): - for field in self.fields: - field.reset() - - def parse(self, val): - for field in self.fields: - field.parse(val) - - def __str__(self): - return str({"addr": self.addr, "fields": self.fields}) - - def __repr__(self): - return str({"addr": self.addr, "fields": self.fields}) - - def get_raw(self): - ret = self.addr << self.dw - - for field in self.fields: - ret |= field.get_raw() - - return ret - -class MultiRegister: - def __init__(self, parent, name, fields): - self.parent = parent - self.fields = fields - self.name = name - - @property - def value(self): - return self.parent.get_long_register(*self.fields) - - @value.setter - def value(self, v): - self.parent.set_long_register(v, *self.fields) - -class RegisterDevice: - def __init__(self, aw, dw, definition): - # Address width and data width - self.aw = aw - self.dw = dw - self.registers_by_addr = {} - self.regname_pattern = re.compile(r"[A-Za-z0-9_]+\[(\d+):(\d+)\]") - - defpath = os.path.join(os.path.dirname(__file__), definition) - with open(defpath) as f: - regmap = json.load(f) - - multi_regs = {} - - for register in regmap: - addr = register["addr"] - reg = Register(register, dw=dw) - self.registers_by_addr[addr] = reg - - for field in reg.fields: - field.addr = addr - if isinstance(field, Field) and field.valid_type != "constant": - sanitized_name = field.name.replace("[", "_").replace("]", "").replace(":", "_") - if field.name.endswith("]"): # Multi-field - name = field.name[:field.name.index("[")] - multi_regs[name] = multi_regs.get(name, []) + [field] - setattr(self, sanitized_name, field) - - for k,v in multi_regs.items(): - setattr(self, k, MultiRegister(self, k, v)) - - def init_from_file(self, file): - if hasattr(file, "read"): - lines = file.read().strip().split("\n") - else: - with open(file, "r") as f: - lines = f.read().strip().split("\n") - - for line in lines: - a,b = line.split("\t") - rawdata = int(b, 16) - - addr_mask = (1 << self.aw) - 1 - addr = addr_mask & (rawdata >> self.dw) - data_mask = (1 << self.dw) - 1 - data = rawdata & data_mask - - if not addr in self.registers_by_addr: - print(f"Unhandled register: {hex(addr)}, skipping ...") - print() - continue - - self.registers_by_addr[addr].parse(data) - - self.update() - - def get_long_register(self, *args): - ret = 0 - for field in args: - match = self.regname_pattern.match(field.name) - if match is None: - raise RuntimeError("Cannot read non-long field: " + field.name) - - end = int(match.group(1)) - start = int(match.group(2)) - width = end-start+1 - mask = ((1 << width)-1) - - val = (field.value & mask) - ret |= val << start - - return ret - - def set_long_register(self, value, *args): - for field in args: - match = self.regname_pattern.match(field.name) - if match is None: - raise RuntimeError("Cannot read non-long field: " + field.name) - - end = int(match.group(1)) - start = int(match.group(2)) - width = end-start+1 - mask = ((1 << width)-1) - value_mask = mask << start - - field.value = (value & value_mask) >> start - - def get_register_dump(self, with_addr=False): - ret = [] - for addr in self.register_addresses: - if not with_addr: - ret.append(self.registers_by_addr[addr].get_raw()) - else: - ret.append((addr, self.registers_by_addr[addr].get_raw())) - - return ret - - def print(self): - for addr in self.register_addresses: - register = self.registers_by_addr[addr] - - for field in register.fields: - val = field.get() - if field.name == "CONST": - continue - - print(f" {field.name}") - print(f" Description: {field.description}") - print(f" Value: {val}") - if field.valid_type == "enum": - print(f" ValDesc: {field.value_description}") - print() - -LMX2594_VCOs = [ - (1, 7500, 8600, 164, 12, 299, 240), - (2, 8600, 9800, 165, 16, 356, 247), - (3, 9800, 10800, 158, 19, 324, 224), - (4, 10800, 12000, 140, 0, 383, 244), - (5, 12000, 12900, 183, 36, 205, 146), - (6, 12900, 13900, 155, 6, 242, 163), - (7, 13900, 15000, 175, 19, 323, 244) - ] - -CAL_NO_ASSIST = 0 -CAL_PARTIAL_ASSIST = 1 -CAL_CLOSE_FREQUENCY_ASSIST = 2 -CAL_FULL_ASSIST = 3 - -CHDIV_TABLE = [ - (2, 15000, 3750, 7500), - (4, 15000, 1875, 3750), - (6, 15000, 1250, 2500), - (8, 11500, 937.5, 1437.5), - (12, 11500, 625, 958.333), - (16, 11500, 468.75, 718.75), - (24, 11500, 312.5, 479.167), - (32, 11500, 234.375, 359.375), - (48, 11500, 156.25, 239.583), - (64, 11500, 117.1875, 179.6875), - (72, 11500, 104.167, 159.722), - (96, 11500, 78.125, 119.792), - (128, 11500, 58.594, 89.844), - (192, 11500, 39.0625, 59.896), - (256, 11500, 29.297, 44.922), - (384, 11500, 19.531, 29.948), - (512, 11500, 14.648, 22.461), - (768, 11500, 9.766, 14.974), - (1, 15000, 10, 15000) - ] - -class LMX2594(RegisterDevice): - - def __init__(self, f_osc): - RegisterDevice.__init__(self, 8, 16, "lmx2594_regmap.json") - - self.f_osc = f_osc - - # Note that this isn't the complete range, but skips the readback registers - self.register_addresses = list(range(109, -1, -1)) - - def get_multiplier_freqs(self): - """ - Enumerate all possible multiplier output frequencies. - """ - f2conf = defaultdict(list) - # config tuple order is mult, osc_x, r_pre - we want this to be sortable - # we prefer smaller mult first, then smaller osc_x - # add no-multiplier configs (there are no limits on using r_pre in this mode, but you usually don't need it) - f2conf[self.f_osc].append((1,1,1)) - f2conf[2*self.f_osc].append((1,2,1)) - for osc_x in [1,2]: - if osc_x==2 and self.f_osc>200: # max input freq of doubler - continue - for mult in range(3,8): - # apply limits on the multiplier's input and output freqs - min_r_pre = int(np.ceil(max(1, self.f_osc*osc_x/70.0, self.f_osc*osc_x*mult/250.0))) - max_r_pre = int(np.floor(min(255, self.f_osc*osc_x/30.0, self.f_osc*osc_x*mult/180.0))) - for r_pre in range(min_r_pre, max_r_pre+1): - mult_out = self.f_osc*(osc_x*mult/r_pre) - f2conf[mult_out].append((mult, osc_x, r_pre)) - - f2conf = dict(sorted(f2conf.items())) - for freq in f2conf.keys(): - f2conf[freq].sort() - #for conf in f2conf[freq]: - # print(freq, conf) - f2conf[freq] = f2conf[freq][0] - return f2conf - - def set_output_frequency(self, f_target, pwr=31, solution=None, en_b=False, osc_2x=False, verbose=True): - # We only support integer mode right now - self.MASH_ORDER.value = 0 - self.MASH_RESET_N.set(self.MASH_RESET_N.RESET) - self.PLL_NUM.value = 0 - self.PLL_DEN.value = 0 - - self.OUTA_PWR.value = pwr - self.OUTA_PD.set(self.OUTA_PD.NORMAL_OPERATION) - if en_b: - self.OUTB_PWR.value = pwr - self.OUTB_PD.set(self.OUTB_PD.NORMAL_OPERATION) - else: - self.OUTB_PWR.value = 0 - self.OUTB_PD.set(self.OUTB_PD.POWERDOWN) - - chdivs = [] - f_vco_min = 7500 - - mult = 1 - osc_x = 2 if osc_2x else 1 - for i,(div,f_vco_max,f_out_min,f_out_max) in enumerate(CHDIV_TABLE): - if not (f_out_min <= f_target <= f_out_max): - continue - - f_vco = f_target * div - - if not (f_vco_min <= f_vco <= f_vco_max): - continue - - chdivs.append((i, div, f_vco)) - - if len(chdivs) < 1: - raise RuntimeError("No possible integer solutions found!") - - solutions = [] - if verbose: - print(" i | f_vco | DIV | DLY_SEL | n | osc_2x | R | mult | R_pre | f_pfd | f_out | Delta f | Metric ") - print("----|----------|-----|---------|------|--------|------|------|-------|---------|----------|---------|------------") - - metric_min = np.inf - metric_min_idx = None - for idx,(i,div,f_vco) in enumerate(chdivs): - min_n,dly_sel = LMX2594.get_modulator_constraints(self.MASH_ORDER.value, f_vco) - - ratio = fractions.Fraction(f_vco / (self.f_osc*osc_x)).limit_denominator(255) - n = ratio.numerator - R = ratio.denominator - - R_pre = 1 - - assert n != 0, "N can't be zero!" - - while n < min_n or self.f_osc / (R * R_pre) > 400: - n *= 2 - - if R*2 <= 255: - R *= 2 - elif R_pre * 2 < 128: - R_pre *= 2 - else: - raise RuntimeError("Failed to find solution, N limit can't be met!") - - f_pd = self.f_osc * osc_x / (R * R_pre) - - metric = R_pre * R * n * div - if metric < metric_min: - metric_min_idx = idx - metric_min = metric - - f_out = f_vco / div - delta_f = abs(f_out - f_target) - - metric += delta_f*1e6 - - if verbose: - print(f" {idx:>2d} | {f_vco:8.2f} | {div:3d} | {dly_sel:7d} | {n:4d} | {' True' if osc_x==2 else ' False'} | {R:4d} | {mult:4d} | {R_pre:5d} | {f_pd:7.2f} | {f_out:8.2f} | {delta_f:7.2f} | {metric:6.4e}") - - solutions.append((i, div, f_vco, dly_sel, n, osc_x, R, mult, R_pre)) - - if verbose: print() - if solution is None: - if verbose: print(f"Choosing solution {metric_min_idx} with minimal metric {metric_min}.") - solution = metric_min_idx - - chdiv_i,chdiv,f_vco,dly_sel,n,osc_x,R,mult,R_pre = solutions[solution] - - self.CHDIV.value = chdiv_i % 18 - self.PFD_DLY_SEL.value = dly_sel - self.PLL_N.value = n - self.OSC_2X.value = osc_x - 1 - self.PLL_R_PRE.value = R_pre - self.MULT.value = mult - self.PLL_R.value = R - - if chdiv_i == 18: - self.OUTA_MUX.set(self.OUTA_MUX.VCO) - self.OUTB_MUX.set(self.OUTB_MUX.VCO) - self.CHDIV_DIV2.set(self.CHDIV_DIV2.DISABLED) - else: - self.OUTA_MUX.set(self.OUTA_MUX.CHANNEL_DIVIDER) - self.OUTB_MUX.set(self.OUTB_MUX.CHANNEL_DIVIDER) - - # Enable CHDIV_DIV2 driver for CHDIV > 2 - self.CHDIV_DIV2.set(self.CHDIV_DIV2.DISABLED if chdiv_i == 0 else self.CHDIV_DIV2.ENABLED) - - self.update() - self.configure_calibration() - - return f_vco / chdiv - - def configure_calibration(self, assistance_level=0): - if self.f_pd <= 100: - if self.f_pd >= 10: - self.FCAL_LPFD_ADJ.value = 0 - elif self.f_pd >= 5: - self.FCAL_LPFD_ADJ.value = 1 - elif self.f_pd >= 2.5: - self.FCAL_LPFD_ADJ.value = 2 - else: - self.FCAL_LPFD_ADJ.value = 3 - - self.FCAL_HPFD_ADJ.value = 0 - elif self.f_pd <= 150: - self.FCAL_HPFD_ADJ.value = 1 - elif self.f_pd <= 200: - self.FCAL_HPFD_ADJ.value = 2 - else: - self.FCAL_HPFD_ADJ.value = 3 - - # Optimize for phase noise performance (At the cost of locking time) - self.CAL_CLK_DIV.value = 3 - self.ACAL_CMP_DLY.value = 25 - - # Don't output clock signal during calibration - self.OUT_MUTE.value = 1 - self.OUT_FORCE.value = 0 - - # VCO calibration settings - if 11900 <= self.f_vco <= 12100: - self.VCO_SEL.value = 4 - self.QUICK_RECAL_EN.value = 0 - self.VCO_SEL_FORCE.value = 0 - self.VCO_DACISET_FORCE.value = 0 - self.VCO_CAPCTRL_FORCE.value = 0 - - self.VCO_DACISET_STRT.value = 300 - self.VCO_CAPCTRL_STRT.value = 183 - - elif assistance_level == CAL_NO_ASSIST: - self.QUICK_RECAL_EN.value = 0 - self.VCO_SEL_FORCE.value = 0 - self.VCO_DACISET_FORCE.value = 0 - self.VCO_CAPCTRL_FORCE.value = 0 - self.VCO_SEL.value = 7 - - else: - for vco_id, f_min, f_max, c_min, c_max, a_min, a_max in LMX2594_VCOs: - if f_min <= self.f_vco <= f_max: - self.VCO_SEL.value = vco_id - self.VCO_DACISET_STRT.value = round(c_min - (c_min - c_max) * (f_vco - f_min) / (f_max - f_min)) - self.VCO_CAPCTRL_STRT.value = round(a_min + (a_max - a_min) * (f_vco - f_min) / (f_max - f_min)) - break - - if vco_id == 7: - raise RuntimeError("Failed to find acceptable VCO??") - - if assistance_level == CAL_PARTIAL_ASSIST: - self.QUICK_RECAL_EN.value = 0 - self.VCO_SEL_FORCE.value = 0 - self.VCO_DACISET_FORCE.value = 0 - self.VCO_CAPCTRL_FORCE.value = 0 - - elif assistance_level == CAL_CLOSE_FREQUENCY_ASSIST: - self.QUICK_RECAL_EN.value = 1 - self.VCO_SEL_FORCE.value = 0 - self.VCO_DACISET_FORCE.value = 0 - self.VCO_CAPCTRL_FORCE.value = 0 - - elif assistance_level == CAL_FULL_ASSIST: - self.QUICK_RECAL_EN.value = 0 - self.VCO_SEL_FORCE.value = 1 - self.VCO_DACISET_FORCE.value = 1 - self.VCO_CAPCTRL_FORCE.value = 1 - - def get_modulator_constraints(mash_order, f_vco): - if mash_order == 0: # for now, it's always 0 - if f_vco <= 12500: - min_n = 28 - dly_sel = 1 - else: - min_n = 32 - dly_sel = 2 - elif mash_order == 1: - if f_vco <= 10000: - min_n = 28 - dly_sel = 1 - elif 10000 < f_vco < 12500: - min_n = 32 - dly_sel = 2 - else: - min_n = 36 - dly_sel = 3 - elif mash_order == 2: - if f_vco <= 10000: - min_n = 32 - dly_sel = 2 - else: - min_n = 36 - dly_sel = 3 - elif mash_order == 3: - if f_vco <= 10000: - min_n = 36 - dly_sel = 3 - else: - min_n = 40 - dly_sel = 4 - elif mash_order == 4: - if f_vco <= 10000: - min_n = 44 - dly_sel = 5 - else: - min_n = 48 - dly_sel = 6 - else: - raise RuntimeError(f"Can't handle unknown mash order: {mash_order}") - - return min_n, dly_sel - - def update(self): - """ - Compute the output frequencies from the register values. - """ - if self.OSC_2X.get() == self.OSC_2X.ENABLED: - f_in = 2 * self.f_osc - else: - f_in = self.f_osc - - f_in /= self.PLL_R_PRE.value - f_in *= self.MULT.value - f_in /= self.PLL_R.value - - self.f_pd = f_in - - num = self.PLL_NUM.value - den = self.PLL_DEN.value - pll_n = self.PLL_N.value - - if den != 0 and num != 0: - self.f_vco = self.f_pd * (pll_n + num/den) - else: - self.f_vco = self.f_pd * pll_n - - if not (7500 <= self.f_vco <= 15000): - raise RuntimeError(f"VCO frequency f_vco = {round(self.f_vco, ndigits=2)} out of range: 7500 MHz <= f_vco <= 15000") - - self.f_chdiv = self.f_vco / CHDIV_TABLE[self.CHDIV.value][0] - - if self.OUTA_MUX.get() == self.OUTA_MUX.CHANNEL_DIVIDER: - self.f_outa = self.f_chdiv - else: - self.f_outa = self.f_vco - - sysref_divider_lut = { self.SYSREF_DIV_PRE.DIVIDE_BY_1: 1, - self.SYSREF_DIV_PRE.DIVIDE_BY_2: 2, - self.SYSREF_DIV_PRE.DIVIDE_BY_4: 4 } - - if self.SYSREF_EN.get() == self.SYSREF_EN.ENABLED: - sysref_div = self.SYSREF_DIV.get() - sysref_div *= sysref_divider_lut[self.SYSREF_DIV_PRE.get()] - self.f_sysref = self.f_vco / sysref_div - - outb_mux = self.OUTB_MUX.get() - if outb_mux == self.OUTB_MUX.CHANNEL_DIVIDER: - self.f_outb = self.f_chdiv - elif outb_mux == self.OUTB_MUX.VCO or outb_mux == self.OUTB_MUX.HIGH_IMPEDANCE: - self.f_outb = self.f_vco - elif outb_mux == self.SYSREF: - self.f_outb = self.f_sysref - -class LMK04828BOutputBranch: - def __init__(self, parent, i): - self.parent = parent - self.i = i - - def ga(n): - return getattr(self.parent, n) - - self.DIV = ga(f"DCLKout{self.i}_DIV") - self.CLK_PD = ga(f"CLKout{self.i}_{self.i+1}_PD") - self.SDCLK_PD = ga(f"SDCLKout{self.i+1}_PD") - self.DCLK_FMT = ga(f"DCLKout{self.i}_FMT") - self.SDCLK_FMT = ga(f"SDCLKout{self.i+1}_FMT") - self.DCLK_POL = ga(f"DCLKout{self.i}_POL") - self.SDCLK_POL = ga(f"SDCLKout{self.i+1}_POL") - - self.DCLK_MUX = ga(f"DCLKout{self.i}_MUX") - self.SDCLK_MUX = ga(f"SDCLKout{self.i+1}_MUX") - - def _set_output_status(self, dclk_enable, sdclk_enable): - if not dclk_enable and not sdclk_enable: - self.CLK_PD.set(self.CLK_PD.POWERDOWN) - elif dclk_enable and not sdclk_enable: - self.CLK_PD.set(self.CLK_PD.ENABLED) - self.DCLK_FMT.set(self.DCLK_FMT.LVDS) - self.SDCLK_PD.set(self.SDCLK_PD.POWERDOWN) - elif not dclk_enable and sdclk_enable: - self.CLK_PD.set(self.CLK_PD.ENABLED) - self.DCLK_FMT.set(self.DCLK_FMT.POWERDOWN) - self.SDCLK_FMT.set(self.SDCLK_FMT.LVDS) - self.SDCLK_PD.set(self.SDCLK_PD.ENABLED) - elif dclk_enable and sdclk_enable: - self.CLK_PD.set(self.CLK_PD.ENABLED) - self.DCLK_FMT.set(self.DCLK_FMT.LVDS) - self.SDCLK_FMT.set(self.SDCLK_FMT.LVDS) - self.SDCLK_PD.set(self.SDCLK_PD.ENABLED) - else: - raise RuntimeError("?!") - - @property - def dclk_active(self): - return not (self.dclk_fmt == self.DCLK_FMT.POWERDOWN or self.clk_pd == self.CLK_PD.POWERDOWN) - - @dclk_active.setter - def dclk_active(self, value: bool): - if self.dclk_active == value: - return - - self._set_output_status(value, self.sdclk_active) - self.parent.update() - - @property - def sdclk_active(self): - return not (self.sdclk_pd == self.SDCLK_PD.POWERDOWN or self.sdclk_fmt == self.SDCLK_FMT.POWERDOWN or self.clk_pd == self.CLK_PD.POWERDOWN) - - @sdclk_active.setter - def sdclk_active(self, value: bool): - if self.sdclk_active == value: - return - - self._set_output_status(self.dclk_active, value) - self.parent.update() - - def get_sdclk_freqs(self): - return self.parent.pll2_output_freq / (np.arange(32)+1) - - def request_freq(self, value, ignore_warning=False): - _div = self.parent.pll2_output_freq / value - div = max(1, min(32, round(_div))) - - f_real = self.parent.pll2_output_freq / div - - if abs(div - _div) > 0.01 and not ignore_warning: - print(f"WARNING: Failed to hit requested frequency of {value:.2f} MHz. Using divider {div} where {_div:.3f} would have been required, thus resulting in output frequency {f_real:.2f} MHz or a frequency error of {f_real - value:.2f} MHz!") - - self.DIV.value = 0x1f & div # 32 maps to 0 - self.update() - - return self.parent.pll2_output_freq / div - - def update(self, printDebug=False): - def dbg(*s): - if printDebug: - print(f"Output Branch {self.i:2d}", *s) - - self.div = self.DIV.get() - if self.div == 0: # 0 means 32 - self.div = 32 - - dbg(f"DIV: {self.div}") - - self.clk_pd = self.CLK_PD.get() - dbg("CLK_PD:", self.clk_pd) - - self.sdclk_pd = self.SDCLK_PD.get() - dbg("SDCLK_PD:", self.sdclk_pd) - - self.dclk_fmt = self.DCLK_FMT.get() - dbg("DCLK_FMT:", self.dclk_fmt) - - self.sdclk_fmt = self.SDCLK_FMT.get() - dbg("SDCLK_FMT:", self.sdclk_fmt) - - self.dclk_pol = self.DCLK_POL.get() - dbg("DCLK_POL:", self.dclk_pol) - - self.sdclk_pol = self.SDCLK_POL.get() - dbg("SDCLK_POL:", self.sdclk_pol) - - self.sdclk_mux = self.SDCLK_MUX.get() - dbg("SDCLK_MUX:", self.sdclk_mux) - - self.dclk_mux = self.DCLK_MUX.get() - dbg("DCLK_MUX:", self.dclk_mux) - - pll_freq = self.parent.pll2_output_freq - sysref_freq = self.parent.sysref_freq - - if self.dclk_mux == self.DCLK_MUX.BYPASS: - self.dclk_freq = pll_freq - else: - self.dclk_freq = pll_freq / self.div - - if self.sdclk_mux == self.SDCLK_MUX.DEVICE_CLOCK_OUTPUT: - self.sdclk_freq = self.dclk_freq - else: - self.sdclk_freq = sysref_freq - - dbg("DCLK_FREQ:", round(self.dclk_freq, ndigits=2)) - dbg("SDCLK_FREQ:", round(self.sdclk_freq, ndigits=2)) - - dbg("DCLK_ACTIVE:", self.dclk_active) - dbg("SDCLK_ACTIVE:", self.sdclk_active) - -class LMK04828B(RegisterDevice): - def __init__(self, clkin0_freq, clkin1_freq, clkin2_freq, vcxo_freq): - RegisterDevice.__init__(self, 13, 8, "data/lmk04828b_regmap.json") - - self.clkin0_freq = clkin0_freq - self.clkin1_freq = clkin1_freq - self.clkin2_freq = clkin2_freq - self.vcxo_freq = vcxo_freq - - # Dictionaries are unordered, and because the order of operations is important when writing - # these registers, the correct order of indices is written down in this array: - self.register_addresses = [0, 2, 3, 4, 5, 6, 12, 13, 256, 257, 258, 259, 260, 261, 262, - 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, - 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, 287, 288, - 289, 290, 291, 292, 293, 294, 295, 296, 297, 298, 299, 300, 301, - 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, - 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, - 328, 329, 330, 331, 332, 333, 334, 335, 336, 337, 338, 339, 340, - 341, 342, 343, 344, 345, 346, 347, 348, 349, 350, 351, 352, 353, - 354, 355, 356, 357, 369, 370, 380, 381, 358, 359, 360, 361, 362, - 363, 364, 365, 366, 371, 386, 387, 388, 389, 392, 393, 394, 395, - 8189, 8190, 8191] - - self.clock_branches = [LMK04828BOutputBranch(self, 2*i) for i in range(7)] - - def write_register_dump(self, name): - with open(name, "w") as f: - f.write(f"R0 (INIT)\t0x000090\n") - - for addr,val in self.get_register_dump(with_addr=True): - f.write(f"R{addr}\t0x{val:06X}\n") - - def update(self, printDebug=False): - def dbg(*s): - if printDebug: - print(*s) - - sel_mode = self.CLKin_SEL_MODE.get() - - dbg("SEL_MODE:", self.CLKin_SEL_MODE.get()) - - if sel_mode == self.CLKin_SEL_MODE.CLK_IN_0_MANUAL: - assert self.CLKin0_OUT_MUX.get() == self.CLKin0_OUT_MUX.PLL1 - pll1_src_freq = self.clkin0_freq - - divider = self.CLKin0_R.value - - elif sel_mode == self.CLKin_SEL_MODE.CLK_IN_1_MANUAL: - assert self.CLKin1_OUT_MUX.get() == self.CLKin1_OUT_MUX.PLL1 - pll1_src_freq = self.clkin1_freq - - divider = self.CLKin1_R.value - - elif sel_mode == self.CLKin_SEL_MODE.CLK_IN_2_MANUAL: - assert self.CLKin2_OUT_MUX.get() == self.CLKin2_OUT_MUX.PLL1 - pll1_src_freq = self.clkin2_freq - - divider = self.CLKin2_R.value - else: - raise RuntimeError("sel_mode == " + str(sel_mode) + ", which is not supported!") - - dbg("Input divider:", divider) - - assert self.PLL1_NCLK_MUX.get() == self.PLL1_NCLK_MUX.OSC_IN, "Only configurations using the external VCXO are supported!" - - self.pll1_phase_detector_freq = pll1_src_freq / divider - dbg("PLL1 Phase Detector Frequency:", self.pll1_phase_detector_freq) - - self.pll1_n_divider = self.PLL1_N.value - dbg("PLL1N Divider:", self.pll1_n_divider) - dbg("Expected VCXO Frequency:", self.pll1_n_divider * self.pll1_phase_detector_freq) - - assert self.vcxo_freq == self.pll1_n_divider * self.pll1_phase_detector_freq - - self.pll2_r_divider = self.PLL2_R.value - pll2_input_freq = self.vcxo_freq / self.pll2_r_divider * (2 if self.PLL2_REF_2X_EN.get() == self.PLL2_REF_2X_EN.ENABLED else 1) - dbg("PLL2 Input Frequency:", pll2_input_freq) - - assert self.PLL2_NCLK_MUX.get() == self.PLL2_NCLK_MUX.PLL_PRESCALER, "Only configurations using PLL2 feedback from prescaler are supported!" - - pll2_p_raw = self.PLL2_P.get() - if pll2_p_raw == self.PLL2_P.DIVIDE_2 or pll2_p_raw == self.PLL2_P.DIVIDE_2_2: - pll2_p = 2 - elif pll2_p_raw == self.PLL2_P.DIVIDE_8: - pll2_p = 8 - else: - pll2_p = self.PLL2_P.value - - dbg("PLL2_P:", pll2_p) - - pll2_n = self.PLL2_N.value - dbg("PLL2_N:", pll2_n) - - self.pll2_output_freq = pll2_input_freq * pll2_n * pll2_p - dbg("PLL2 Output Frequency:", round(self.pll2_output_freq, ndigits=2)) - - self.sysref_divider = self.SYSREF_DIV.value - dbg("SYSREF DIVIDER:", self.sysref_divider) - - self.sysref_freq = self.pll2_output_freq / self.sysref_divider - dbg("SYSREF FREQ:", round(self.sysref_freq, ndigits=5)) - - for branch in self.clock_branches: - branch.update(printDebug) - - def set_refclk(self, refclk, precision=1): - f_i = int(self.vcxo_freq * 10**precision) - - if 2370 < refclk < 2630: - vco = 0 # VCO0 - elif 2920 < refclk < 3080: - vco = 1 # VCO1 - else: - raise RuntimeError("Requested VCO frequency is not compatible with either VCO") - - refclk = int(refclk * 10**precision) - - div = np.gcd(f_i, refclk) - - R = f_i // div - N = refclk // div - - if self.vcxo_freq // R > 150: - print("Phase detector frequency too high, introducing factor") - fac = np.ceil((self.vcxo_freq // R) / 150) - R *= fac - N *= fac - - success = False - for P in range(2, 9): # Absorb part of N into the prescaler - if N % P == 0: - success = True - break - - if not success: - raise RuntimeError("Failed to find suitable solution!") - - self.VCO_MUX.value = self.VCO_MUX.VCO_1.value if vco == 1 else self.VCO_MUX.VCO_0.value - - self.PLL2_R.value = R - self.PLL2_N.value = N // P - self.PLL2_P.value = P & 0x7 # 8 is represented as 0 - - self.update() - - return R, N // P, P - - def set_sysref(self, value): - _div = self.pll2_output_freq / value - div = min(8191, max(8, int(round(_div)))) - - f_new = self.pll2_output_freq / div - - if abs(div - _div) / div > 0.01: - print(f"WARNING: SYSREF_CLK target could not be hit accurately! Requested frequency {value} MHz requires divider {_div:.4f} which is not realizable. The closest integer divider {div} results in a frequency of {f_new} MHz!") - - self.SYSREF_DIV.value = div - self.update() - -class CLK104Output: - def __init__(self, branch): - self.branch = branch - - @property - def freq(self): - return self.branch.dclk_freq - - @freq.setter - def freq(self, value): - return self.branch.request_freq(value) - - @property - def sysref_freq(self): - return self.branch.sdclk_freq - - @property - def enable(self): - return self.branch.dclk_active - - @property - def sysref_enable(self): - return self.branch.sdclk_active - - @enable.setter - def enable(self, value): - self.branch.dclk_active = value - - @sysref_enable.setter - def sysref_enable(self, value): - self.branch.sdclk_active = value - -class CLK104: - def __init__(self, src=None): - # 10 MHz reference clock, 10 MHz clock input on external SMA, 160 MHz VCO frequency - self.lmk = LMK04828B(10, 10, 10, 160) - self.lmx_adc = LMX2594(245.76) - self.lmx_dac = LMX2594(245.76) - - if src is None: - with files("ipq_pynq_utils").joinpath("data/lmk04828b_regdump_defaults.txt").open() as f: - self.lmk.init_from_file(f) - else: - self.lmk.init_from_file(src) - - with files("ipq_pynq_utils").joinpath("data/clockFiles/LMX2594_REF-245M76__OUT-9830M40_10172019_I.txt").open() as f: - self.lmx_adc.init_from_file(f) - - with files("ipq_pynq_utils").joinpath("data/clockFiles/LMX2594_REF-245M76__OUT-9830M40_10172019_I.txt").open() as f: - self.lmx_dac.init_from_file(f) - - self.RF_PLL_ADC_REF = CLK104Output(self.lmk.clock_branches[0]) - self.AMS_SYSREF = CLK104Output(self.lmk.clock_branches[1]) - self.RF_PLL_DAC_REF = CLK104Output(self.lmk.clock_branches[2]) - self.DAC_REFCLK = CLK104Output(self.lmk.clock_branches[3]) - self.PL_CLK = CLK104Output(self.lmk.clock_branches[4]) - self.EXT_REF_OUT = CLK104Output(self.lmk.clock_branches[5]) - self.ADC_REFCLK = CLK104Output(self.lmk.clock_branches[6]) - - @property - def PLL2_FREQ(self): - return self.lmk.pll2_output_freq - - @PLL2_FREQ.setter - def PLL2_FREQ(self, value): - self.lmk.set_refclk(value) - - @property - def SYSREF_FREQ(self): - return self.lmk.sysref_freq - - @SYSREF_FREQ.setter - def SYSREF_FREQ(self, value): - self.lmk.set_sysref(value) - - def get_register_dump(self): - return { - "LMK": self.lmk.get_register_dump() - } diff --git a/qick/qick_lib/qick/ipq_pynq_utils/lmx2594_regmap.json b/qick/qick_lib/qick/ipq_pynq_utils/lmx2594_regmap.json deleted file mode 100644 index 0d68b3d..0000000 --- a/qick/qick_lib/qick/ipq_pynq_utils/lmx2594_regmap.json +++ /dev/null @@ -1,3138 +0,0 @@ -[ - { - "addr": 0, - "fields": [ - { - "fieldtype": "normal", - "end": 15, - "start": 15, - "name": "RAMP_EN", - "description": "Control frequency ramping mode.", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "DISABLE", - "description": "Disable frequency ramping mode" - }, - { - "value": 1, - "name": "ENABLE", - "description": "Enable frequency ramping mode" - } - ] - } - }, - { - "fieldtype": "normal", - "end": 14, - "start": 14, - "name": "VCO_PHASE_SYNC", - "description": "Control phase synchronization.", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "DISABLED", - "description": "Disable phase SYNC mode" - }, - { - "value": 1, - "name": "ENABLED", - "description": "Enable phase SYNC mode" - } - ] - } - }, - { - "fieldtype": "normal", - "end": 9, - "start": 9, - "name": "OUT_MUTE", - "description": "Mute the outputs when the VCO is calibrating.", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "DISABLED", - "description": "Disabled. If disabled, also be sure to enable OUT_FORCE" - }, - { - "value": 1, - "name": "ENABLED", - "description": "Enabled. If enabled, also be sure to disable OUT_FORCE" - } - ] - } - }, - { - "fieldtype": "normal", - "end": 8, - "start": 7, - "name": "FCAL_HPFD_ADJ", - "description": "Set this field in accordance to the phase-detector frequency for optimal VCO calibration.", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "F_PD_LTE_100_MHZ", - "description": "f_PD <= 100 MHz" - }, - { - "value": 1, - "name": "F_PD_100_MHZ_TO_150_MHZ", - "description": "100 MHz < f_PD <= 150 MHz" - }, - { - "value": 2, - "name": "F_PD_150_MHZ_TO_200_MHZ", - "description": "150 MHz < f_PD <= 200 MHz" - }, - { - "value": 3, - "name": "F_PD_GT_200_MHZ", - "description": "f_PD > 200 MHz" - } - ] - } - }, - { - "fieldtype": "normal", - "end": 6, - "start": 5, - "name": "FCAL_LPFD_ADJ", - "description": "Set this field in accordance to the phase detector frequency for optimal VCO calibration.", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "F_PD_GTE_10_MHZ", - "description": "f_PD >= 10 MHz" - }, - { - "value": 1, - "name": "F_PD_10_MHZ_TO_5_MHZ", - "description": "10 MHz > f_PD >= 5 MHz" - }, - { - "value": 2, - "name": "F_PD_5_MHZ_TO_2_5_MHZ", - "description": "5 MHz > f_PD >= 2.5 MHz" - }, - { - "value": 3, - "name": "F_PD_LT_2_5_MHZ", - "description": "f_PD < 2.5 MHz" - } - ] - } - }, - { - "fieldtype": "normal", - "end": 3, - "start": 3, - "name": "FCAL_EN", - "description": "Enable the VCO frequency calibration. Also note that the action of programming this bit to a 1 activates the VCO calibration", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": "0", - "name": "DISABLED", - "description": "VCO frequency calibration disabled." - }, - { - "value": "1", - "name": "ENABLED", - "description": "VCO frequency calibration enabled." - } - ] - } - }, - { - "fieldtype": "normal", - "end": 2, - "start": 2, - "name": "MUXOUT_LD_SEL", - "description": "Selects the state of the function of the MUXout pin", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "READBACK", - "description": "Readback" - }, - { - "value": 1, - "name": "LOCK_DETECT", - "description": "Lock detect" - } - ] - } - }, - { - "fieldtype": "normal", - "end": 1, - "start": 1, - "name": "RESET", - "description": "Resets and holds all state machines and registers to default value.", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "NORMAL_OPERATION", - "description": "Normal operation" - }, - { - "value": 1, - "name": "RESET", - "description": "Reset active" - } - ] - } - }, - { - "fieldtype": "normal", - "end": 0, - "start": 0, - "name": "POWERDOWN", - "description": "Powers down entire device", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "NORMAL_OPERATION", - "description": "Normal operation" - }, - { - "value": 1, - "name": "POWERDOWN", - "description": "Powered down" - } - ] - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 9232 - } - ] - }, - { - "addr": 1, - "fields": [ - { - "fieldtype": "normal", - "end": 2, - "start": 0, - "name": "CAL_CLK_DIV", - "description": "Sets divider for VCO calibration state machine clock based on input frequency. If user is not concerned with lock time, it is recommended to set this value to 3. By slowing down the VCO calibration, the best and most repeatable VCO phase noise can be attained.", - "default": 3, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "DIVIDE_BY_1", - "description": "Divide by 1. Use for fOSC ≤ 200 MHz" - }, - { - "value": 1, - "name": "DIVIDE_BY_2", - "description": "Divide by 2. Use for fOSC ≤ 400 MHz" - }, - { - "value": 2, - "name": "DIVIDE_BY_4", - "description": "Divide by 4. Use for fOSC ≤ 800 MHz" - }, - { - "value": 3, - "name": "DIVIDE_BY_8", - "description": "Divide by 8. All fOSC" - } - ] - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 2056 - } - ] - }, - { - "addr": 2, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 1280 - } - ] - }, - { - "addr": 3, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 1602 - } - ] - }, - { - "addr": 4, - "fields": [ - { - "fieldtype": "normal", - "end": 15, - "start": 8, - "name": "ACAL_CMP_DLY", - "description": "VCO amplitude calibration delay. Lowering this value can speed up VCO calibration, but lowering it too much may degrade VCO phase noise. The minimum allowable value for this field is 10 and this allows the VCO to calibrate to the correct frequency for all scenarios. To yield the best and most repeatable VCO phase noise, this relationship should be met: ACAL_CMP_DLY > Fsmclk / 10 MHz, where Fsmclk = Fosc / 2^(CAL_CLK_DIV) and Fosc is the input reference frequency. If calibration time is of concern, then it is recommended to set this register to ≥ 25.", - "default": 10, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 67 - } - ] - }, - { - "addr": 5, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 200 - } - ] - }, - { - "addr": 6, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 51202 - } - ] - }, - { - "addr": 7, - "fields": [ - { - "fieldtype": "normal", - "end": 14, - "start": 14, - "name": "OUT_FORCE", - "description": "Works with OUT_MUTE in disabling outputs when VCO calibrating.", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "OUTPUT_ENABLE_NOT_FORCED", - "description": "Output not forced" - }, - { - "value": 1, - "name": "OUTPUT_ENABLE_FORCED", - "description": "Enabled" - } - ] - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 178 - } - ] - }, - { - "addr": 8, - "fields": [ - { - "fieldtype": "normal", - "end": 14, - "start": 14, - "name": "VCO_DACISET_FORCE", - "description": "This forces the VCO_DACISET value", - "default": 0, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "normal", - "end": 11, - "start": 11, - "name": "VCO_CAPCTRL_FORCE", - "description": "This forces the VCO_CAPCTRL value", - "default": 0, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 8192 - } - ] - }, - { - "addr": 9, - "fields": [ - { - "fieldtype": "normal", - "end": 12, - "start": 12, - "name": "OSC_2X", - "description": "Low noise OSCin frequency doubler.", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "DISABLED", - "description": "Frequency doubler disabled" - }, - { - "value": 1, - "name": "ENABLED", - "description": "Frequency doubler enabled" - } - ] - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 1540 - } - ] - }, - { - "addr": 10, - "fields": [ - { - "fieldtype": "normal", - "end": 11, - "start": 7, - "name": "MULT", - "description": "Programmable input frequency multiplier 0,2,,8-31: Reserved, 1: Byapss, 3: 3X ... 7: 7X", - "default": 1, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 4184 - } - ] - }, - { - "addr": 11, - "fields": [ - { - "fieldtype": "normal", - "end": 11, - "start": 4, - "name": "PLL_R", - "description": "Programmable input path divider after the programmable input frequency multiplier.", - "default": 1, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 8 - } - ] - }, - { - "addr": 12, - "fields": [ - { - "fieldtype": "normal", - "end": 11, - "start": 0, - "name": "PLL_R_PRE", - "description": "Programmable input path divider before the programmable input frequency multiplier.", - "default": 1, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 20480 - } - ] - }, - { - "addr": 13, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 16384 - } - ] - }, - { - "addr": 14, - "fields": [ - { - "fieldtype": "normal", - "end": 6, - "start": 4, - "name": "CPG", - "description": "Effective charge-pump current. This is the sum of up and down currents.", - "default": 7, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "CPC_0_mA", - "description": "0 mA" - }, - { - "value": 1, - "name": "CPC_6_mA", - "description": "6 mA" - }, - { - "value": 3, - "name": "CPC_12_mA", - "description": "12 mA" - }, - { - "value": 4, - "name": "CPC_3_mA", - "description": "3 mA" - }, - { - "value": 5, - "name": "CPC_9_mA", - "description": "9 mA" - }, - { - "value": 7, - "name": "CPC_15_mA", - "description": "15 mA" - } - ] - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 7680 - } - ] - }, - { - "addr": 15, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 1615 - } - ] - }, - { - "addr": 16, - "fields": [ - { - "fieldtype": "normal", - "end": 8, - "start": 0, - "name": "VCO_DACISET", - "description": "This sets the final amplitude for the VCO calibration in the case that amplitude calibration is forced.", - "default": 128, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 17, - "fields": [ - { - "fieldtype": "normal", - "end": 8, - "start": 0, - "name": "VCO_DACISET_STRT", - "description": "This sets the initial starting point for the VCO amplitude calibration.", - "default": 250, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 18, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 100 - } - ] - }, - { - "addr": 19, - "fields": [ - { - "fieldtype": "normal", - "end": 7, - "start": 0, - "name": "VCO_CAPCTRL", - "description": "This sets the final VCO band when VCO_CAPCTRL is forced.", - "default": 183, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 9984 - } - ] - }, - { - "addr": 20, - "fields": [ - { - "fieldtype": "normal", - "end": 13, - "start": 11, - "name": "VCO_SEL", - "description": "This sets VCO start core for calibration and the VCO when it is forced.", - "default": 7, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "NOT_USED", - "description": "Not used." - }, - { - "value": 1, - "name": "VCO1", - "description": "VCO1" - }, - { - "value": 2, - "name": "VCO2", - "description": "VCO2" - }, - { - "value": 3, - "name": "VCO3", - "description": "VCO3" - }, - { - "value": 4, - "name": "VCO4", - "description": "VCO4" - }, - { - "value": 5, - "name": "VCO5", - "description": "VCO5" - }, - { - "value": 6, - "name": "VCO6", - "description": "VCO6" - }, - { - "value": 7, - "name": "VCO7", - "description": "VCO7" - } - ] - } - }, - { - "fieldtype": "normal", - "end": 10, - "start": 10, - "name": "VCO_SEL_FORCE", - "description": "This forces the VCO to use the core specified by VCO_SEL. It is intended mainly for diagnostic purposes.", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "DISABLED", - "description": "Disabled (recommended)" - }, - { - "value": 1, - "name": "ENABLED", - "description": "Enabled" - } - ] - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 49224 - } - ] - }, - { - "addr": 21, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 1025 - } - ] - }, - { - "addr": 22, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 1 - } - ] - }, - { - "addr": 23, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 124 - } - ] - }, - { - "addr": 24, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 1818 - } - ] - }, - { - "addr": 25, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 3115 - } - ] - }, - { - "addr": 26, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 3504 - } - ] - }, - { - "addr": 27, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 2 - } - ] - }, - { - "addr": 28, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 1160 - } - ] - }, - { - "addr": 29, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 12684 - } - ] - }, - { - "addr": 30, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 12684 - } - ] - }, - { - "addr": 31, - "fields": [ - { - "fieldtype": "normal", - "end": 14, - "start": 14, - "name": "CHDIV_DIV2", - "description": "Enable driver buffer for CHDIV > 2", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "DISABLED", - "description": "Disabled (only valid for CHDIV = 2)" - }, - { - "value": 1, - "name": "ENABLED", - "description": "Enabled (use for CHDIV > 2)" - } - ] - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 1004 - } - ] - }, - { - "addr": 32, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 915 - } - ] - }, - { - "addr": 33, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 7713 - } - ] - }, - { - "addr": 34, - "fields": [ - { - "fieldtype": "normal", - "end": 2, - "start": 0, - "name": "PLL_N[18:16]", - "description": "The PLL_N divider value is in the feedback path and divides the VCO frequency.", - "default": 0, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 35, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 4 - } - ] - }, - { - "addr": 36, - "fields": [ - { - "fieldtype": "normal", - "end": 15, - "start": 0, - "name": "PLL_N[15:0]", - "description": "The PLL_N divider value is in the feedback path and divides the VCO frequency.", - "default": 100, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 37, - "fields": [ - { - "fieldtype": "normal", - "end": 15, - "start": 15, - "name": "MASH_SEED_EN", - "description": "Enabling this bit allows the to be applied to shift the phase at the output or optimize spurs.", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "DISABLED", - "description": "Disabled" - }, - { - "value": 1, - "name": "ENABLED", - "description": "Enabled" - } - ] - } - }, - { - "fieldtype": "normal", - "end": 13, - "start": 8, - "name": "PFD_DLY_SEL", - "description": "The PFD_DLY_SEL must be adjusted in accordance to the Ndivider value. This is with the functional description for the Ndivider", - "default": 2, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 4 - } - ] - }, - { - "addr": 38, - "fields": [ - { - "fieldtype": "normal", - "end": 15, - "start": 0, - "name": "PLL_DEN[31:16]", - "description": "The fractional denominator", - "default": 65535, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 39, - "fields": [ - { - "fieldtype": "normal", - "end": 15, - "start": 0, - "name": "PLL_DEN[15:0]", - "description": "The fractional denominator", - "default": 65535, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "NAME", - "description": "Descr" - } - ] - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 40, - "fields": [ - { - "fieldtype": "normal", - "end": 15, - "start": 0, - "name": "MASH_SEED[31:16]", - "description": "The initial state of the MASH engine first accumulator. Can be used to shift phase or optimize fractional spurs. Every time the field is programmed, it ADDS this MASH seed to the existing one. To reset it, use the MASH_RESET_N bit.", - "default": 0, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 41, - "fields": [ - { - "fieldtype": "normal", - "end": 15, - "start": 0, - "name": "MASH_SEED[15:0]", - "description": "The initial state of the MASH engine first accumulator. Can be used to shift phase or optimize fractional spurs. Every time the field is programmed, it ADDS this MASH seed to the existing one. To reset it, use the MASH_RESET_N bit.", - "default": 0, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 42, - "fields": [ - { - "fieldtype": "normal", - "end": 15, - "start": 0, - "name": "PLL_NUM[31:16]", - "description": "The fractional numerator", - "default": 0, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 43, - "fields": [ - { - "fieldtype": "normal", - "end": 15, - "start": 0, - "name": "PLL_NUM[15:0]", - "description": "The fractional numerator", - "default": 0, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 44, - "fields": [ - { - "fieldtype": "normal", - "end": 13, - "start": 8, - "name": "OUTA_PWR", - "description": "Adjusts output power. Higher numbers give more output power to a point, depending on the pullup component used.", - "default": 31, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "normal", - "end": 7, - "start": 7, - "name": "OUTB_PD", - "description": "Powers down output B", - "default": 1, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "NORMAL_OPERATION", - "description": "Normal operation" - }, - { - "value": 1, - "name": "POWERDOWN", - "description": "Powerdown" - } - ] - } - }, - { - "fieldtype": "normal", - "end": 6, - "start": 6, - "name": "OUTA_PD", - "description": "Powers down output A", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "NORMAL_OPERATION", - "description": "Normal operation" - }, - { - "value": 1, - "name": "POWERDOWN", - "description": "Powerdown" - } - ] - } - }, - { - "fieldtype": "normal", - "end": 5, - "start": 5, - "name": "MASH_RESET_N", - "description": "Resets MASH circuitry to an initial state", - "default": 1, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "RESET", - "description": "MASH held in reset. All fractions are ignored" - }, - { - "value": 1, - "name": "ENABLED", - "description": "Fractional mode enabled. MASH is NOT held in reset." - } - ] - } - }, - { - "fieldtype": "normal", - "end": 2, - "start": 0, - "name": "MASH_ORDER", - "description": "Sets the MASH order", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "INTEGER_MODE", - "description": "Integer mode" - }, - { - "value": 1, - "name": "FIRST_ORDER_MODULATOR", - "description": "First order modulator" - }, - { - "value": 2, - "name": "SECOND_ORDER_MODULATOR", - "description": "Second order modulator" - }, - { - "value": 3, - "name": "THIRD_ORDER_MODULATOR", - "description": "Third order modulator" - }, - { - "value": 4, - "name": "FOURTH_ORDER_MODULATOR", - "description": "Fourth order modulator" - } - ] - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 45, - "fields": [ - { - "fieldtype": "normal", - "end": 12, - "start": 11, - "name": "OUTA_MUX", - "description": "Selects what signal goes to RFoutA", - "default": 1, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "CHANNEL_DIVIDER", - "description": "Channel divider" - }, - { - "value": 1, - "name": "VCO", - "description": "VCO" - }, - { - "value": 3, - "name": "HIGH_IMPEDANCE", - "description": "High impedance" - } - ] - } - }, - { - "fieldtype": "normal", - "end": 10, - "start": 9, - "name": "OUT_ISET", - "description": "Setting to a lower value allows slightly higher output power at higher frequencies at the expense of higher current consumption. 0: Maximum power boost, 3: No output power boost.", - "default": 0, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "normal", - "end": 5, - "start": 0, - "name": "OUTB_PWR", - "description": "Output power setting for RFoutB", - "default": 31, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 49344 - } - ] - }, - { - "addr": 46, - "fields": [ - { - "fieldtype": "normal", - "end": 1, - "start": 0, - "name": "OUTB_MUX", - "description": "Selects what signal goes to RFoutB", - "default": 1, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "CHANNEL_DIVIDER", - "description": "Channel divider" - }, - { - "value": 1, - "name": "VCO", - "description": "VCO" - }, - { - "value": 2, - "name": "SYSREF", - "description": "SysRef (also ensure SYSREF_EN=1)" - }, - { - "value": 3, - "name": "HIGH_IMPEDANCE", - "description": "High impedance" - } - ] - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 2044 - } - ] - }, - { - "addr": 47, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 768 - } - ] - }, - { - "addr": 48, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 768 - } - ] - }, - { - "addr": 49, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 16768 - } - ] - }, - { - "addr": 50, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 51, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 128 - } - ] - }, - { - "addr": 52, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 2080 - } - ] - }, - { - "addr": 53, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 54, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 55, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 56, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 57, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 32 - } - ] - }, - { - "addr": 58, - "fields": [ - { - "fieldtype": "normal", - "end": 15, - "start": 15, - "name": "INPIN_IGNORE", - "description": "Ignore SYNC and SysRefReq Pins", - "default": 1, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "NORMAL_OPERATION", - "description": "Pins are used. Only valid for VCO_PHASE_SYNC = 1" - }, - { - "value": 1, - "name": "IGNORED", - "description": "Pin is ignored" - } - ] - } - }, - { - "fieldtype": "normal", - "end": 14, - "start": 14, - "name": "INPIN_HYST", - "description": "High Hysteresis for LVDS mode", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "DISABLED", - "description": "Disabled" - }, - { - "value": 1, - "name": "ENABLED", - "description": "Enabled" - } - ] - } - }, - { - "fieldtype": "normal", - "end": 13, - "start": 12, - "name": "INPIN_LVL", - "description": "Sets bias level for LVDS mode. In LVDS mode, a voltage divider can be inserted to reduce susceptibility to common-mode noise of an LVDS line because the input is single-ended. With a reasonable setup, TI recommends using INPIN_LVL = 1 (Vin) to use the entire signal swing of an LVDS line.", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "VIN_DIV_4", - "description": "Vin/4" - }, - { - "value": 1, - "name": "VIN", - "description": "Vin" - }, - { - "value": 2, - "name": "VIN_DIV_2", - "description": "Vin/2" - } - ] - } - }, - { - "fieldtype": "normal", - "end": 11, - "start": 9, - "name": "INPIN_FMT", - "description": "IO Standard to be used for SYNC and SysRefReq pins.", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "SYNC_CMOS_SYSREFREQ_CMOS", - "description": "Use CMOS for both pins." - }, - { - "value": 1, - "name": "SYNC_LVDS_SYSREFREQ_CMOS", - "description": "Use LVDS for SYNC and CMOS for SysRefReq." - }, - { - "value": 2, - "name": "SYNC_CMOS_SYSREFREQ_LVDS", - "description": "Use CMOS for SYNC and LVDS for SysRefReq." - }, - { - "value": 3, - "name": "SYNC_LVDS_SYSREFREQ_LVDS", - "description": "Use LVDS for both pins." - } - ] - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 1 - } - ] - }, - { - "addr": 59, - "fields": [ - { - "fieldtype": "normal", - "end": 0, - "start": 0, - "name": "LD_TYPE", - "description": "Lock detect type", - "default": 1, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "VCO_CAL_STATUS", - "description": "VCO calibration status" - }, - { - "value": 1, - "name": "VCO_CAL_STATUS_AND_INDIRECT_VTUNE", - "description": "VCO calibration status and Indirect Vtune" - } - ] - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 60, - "fields": [ - { - "fieldtype": "normal", - "end": 15, - "start": 0, - "name": "LD_DLY", - "description": "Lock Detect Delay. This is the delay added to the lock detect after the VCO calibration is successful and before the lock detect is asserted high. The delay added is in phase-detector cycles. If set to 0, the lock detect immediately becomes high after the VCO calibration is successful.", - "default": 1000, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 61, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 168 - } - ] - }, - { - "addr": 62, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 802 - } - ] - }, - { - "addr": 63, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 64, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 5000 - } - ] - }, - { - "addr": 65, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 66, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 500 - } - ] - }, - { - "addr": 67, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 68, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 1000 - } - ] - }, - { - "addr": 69, - "fields": [ - { - "fieldtype": "normal", - "end": 15, - "start": 0, - "name": "MASH_RST_COUNT[31:16]", - "description": "If the designer does not use this device in fractional mode with VCO_PHASE_SYNC = 1, then this field can be set to 0. In phase-sync mode with fractions, this bit is used so that there is a delay for the VCO divider after the MASH is reset. This delay must be set to greater than the lock time of the PLL. It does impact the latency time of the SYNC feature.", - "default": 0, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 70, - "fields": [ - { - "fieldtype": "normal", - "end": 15, - "start": 0, - "name": "MASH_RST_COUNT[15:0]", - "description": "If the designer does not use this device in fractional mode with VCO_PHASE_SYNC = 1, then this field can be set to 0. In phase-sync mode with fractions, this bit is used so that there is a delay for the VCO divider after the MASH is reset. This delay must be set to greater than the lock time of the PLL. It does impact the latency time of the SYNC feature.", - "default": 50000, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 71, - "fields": [ - { - "fieldtype": "normal", - "end": 7, - "start": 5, - "name": "SYSREF_DIV_PRE", - "description": "Pre-divider for SYSREF", - "default": 4, - "valid": { - "type": "enum", - "values": [ - { - "value": 1, - "name": "DIVIDE_BY_1", - "description": "Divide by 1" - }, - { - "value": 2, - "name": "DIVIDE_BY_2", - "description": "Divide by 2" - }, - { - "value": 4, - "name": "DIVIDE_BY_4", - "description": "Divide by 4" - } - ] - } - }, - { - "fieldtype": "normal", - "end": 4, - "start": 4, - "name": "SYSREF_PULSE", - "description": "Enable pulser mode in master mode", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "DISABLED", - "description": "Disabled" - }, - { - "value": 1, - "name": "ENABLED", - "description": "Enabled" - } - ] - } - }, - { - "fieldtype": "normal", - "end": 3, - "start": 3, - "name": "SYSREF_EN", - "description": "Enable SYSREF", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "DISABLED", - "description": "Disabled" - }, - { - "value": 1, - "name": "ENABLED", - "description": "Enabled" - } - ] - } - }, - { - "fieldtype": "normal", - "end": 2, - "start": 2, - "name": "SYSREF_REPEAT", - "description": "Enable repeater mode", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "MASTER", - "description": "Master mode" - }, - { - "value": 1, - "name": "REPEATER", - "description": "Repeater mode" - } - ] - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 1 - } - ] - }, - { - "addr": 72, - "fields": [ - { - "fieldtype": "normal", - "end": 10, - "start": 0, - "name": "SYSREF_DIV", - "description": "Divider for the SYSREF. Actual divider value = regValue * 2 + 4", - "default": 0, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 73, - "fields": [ - { - "fieldtype": "normal", - "end": 11, - "start": 6, - "name": "JESD_DAC2_CTRL", - "description": "These are the adjustments for the delay for the SYSREF. Two of these must be zero and the other two values must sum to 63. ", - "default": 0, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "normal", - "end": 5, - "start": 0, - "name": "JESD_DAC1_CTRL", - "description": "These are the adjustments for the delay for the SYSREF. Two of these must be zero and the other two values must sum to 63. ", - "default": 63, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 74, - "fields": [ - { - "fieldtype": "normal", - "end": 15, - "start": 12, - "name": "SYSREF_PULSE_CNT", - "description": "Number of pulses in pulse mode in master mode", - "default": 0, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "normal", - "end": 11, - "start": 6, - "name": "JESD_DAC4_CTRL", - "description": "These are the adjustments for the delay for the SYSREF. Two of these must be zero and the other two values must sum to 63. ", - "default": 0, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "normal", - "end": 5, - "start": 0, - "name": "JESD_DAC3_CTRL", - "description": "These are the adjustments for the delay for the SYSREF. Two of these must be zero and the other two values must sum to 63. ", - "default": 0, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 75, - "fields": [ - { - "fieldtype": "normal", - "end": 10, - "start": 6, - "name": "CHDIV", - "description": "VCO divider value, 0: 2, 1: 4, 2: 6, 3: 8, 4: 12, 5: 16, 6: 24, 7: 32, 8: 48, 9: 64, 10: 72, 11: 96, 12: 128, 13: 192, 14: 256, 15: 384, 16: 512, 17: 768, 18-31: Reserved", - "default": 0, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 2048 - } - ] - }, - { - "addr": 76, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 12 - } - ] - }, - { - "addr": 77, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 78, - "fields": [ - { - "fieldtype": "normal", - "end": 11, - "start": 11, - "name": "RAMP_THRESH[32:32]", - "description": "This sets how much the ramp can change the VCO frequency before calibrating. If this frequency is chosen to be Δf, then it is calculated as follows: RAMP_THRESH = (Δf / fPD) × 16777216", - "default": 0, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "normal", - "end": 9, - "start": 9, - "name": "QUICK_RECAL_EN", - "description": "Causes the initial VCO_CORE, VCO_CAPCTRL, and VCO_DACISET to be based on the last value. Useful if the frequency change is small, as is often the case for ramping.", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "DISABLED", - "description": "Disabled" - }, - { - "value": 1, - "name": "ENABLED", - "description": "Enabled" - } - ] - } - }, - { - "fieldtype": "normal", - "end": 8, - "start": 1, - "name": "VCO_CAPCTRL_STRT", - "description": "This sets the initial value for VCO_CAPCTRL if not overridden by other settings. Smaller values yield a higher frequency band within a VCO core. Valid number range is 0 to 183.", - "default": 0, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 1 - } - ] - }, - { - "addr": 79, - "fields": [ - { - "fieldtype": "normal", - "end": 15, - "start": 0, - "name": "RAMP_THRESH[31:16]", - "description": "This sets how much the ramp can change the VCO frequency before calibrating. If this frequency is chosen to be Δf, then it is calculated as follows: RAMP_THRESH = (Δf / fPD) × 16777216", - "default": 0, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 80, - "fields": [ - { - "fieldtype": "normal", - "end": 15, - "start": 0, - "name": "RAMP_THRESH[15:0]", - "description": "This sets how much the ramp can change the VCO frequency before calibrating. If this frequency is chosen to be Δf, then it is calculated as follows: RAMP_THRESH = (Δf / fPD) × 16777216", - "default": 0, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 81, - "fields": [ - { - "fieldtype": "normal", - "end": 0, - "start": 0, - "name": "RAMP_LIMIT_HIGH[32:32]", - "description": "This sets a maximum frequency that the ramp can not exceed so that the VCO does not get set beyond a valid frequency range. Suppose fHIGH is this frequency and fVCO is the starting VCO frequency then: For fHIGH ≥ fVCO: RAMP_LIMIT_HIGH = (fHIGH – fVCO)/fPD × 16777216 For fHIGH < fVCO this is not a valid condition to choose", - "default": 0, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 82, - "fields": [ - { - "fieldtype": "normal", - "end": 15, - "start": 0, - "name": "RAMP_LIMIT_HIGH[31:16]", - "description": "This sets a maximum frequency that the ramp can not exceed so that the VCO does not get set beyond a valid frequency range. Suppose fHIGH is this frequency and fVCO is the starting VCO frequency then: For fHIGH ≥ fVCO: RAMP_LIMIT_HIGH = (fHIGH – fVCO)/fPD × 16777216 For fHIGH < fVCO this is not a valid condition to choose", - "default": 0, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 83, - "fields": [ - { - "fieldtype": "normal", - "end": 15, - "start": 0, - "name": "RAMP_LIMIT_HIGH[15:0]", - "description": "This sets a maximum frequency that the ramp can not exceed so that the VCO does not get set beyond a valid frequency range. Suppose fHIGH is this frequency and fVCO is the starting VCO frequency then: For fHIGH ≥ fVCO: RAMP_LIMIT_HIGH = (fHIGH – fVCO)/fPD × 16777216 For fHIGH < fVCO this is not a valid condition to choose", - "default": 0, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 84, - "fields": [ - { - "fieldtype": "normal", - "end": 0, - "start": 0, - "name": "RAMP_LIMIT_LOW[32:32]", - "description": "This sets a minimum frequency that the ramp can not exceed so that the VCO does not get set beyond a valid frequency range. Suppose fLOW is this frequency and fVCO is the starting VCO frequency then: For fLOW ≤ fVCO: RAMP_LIMIT_LOW = 2 33 – 16777216 x (fVCO – fLOW) / fPD For fLOW > fVCO, this is not a valid condition to choose.", - "default": 0, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 85, - "fields": [ - { - "fieldtype": "normal", - "end": 15, - "start": 0, - "name": "RAMP_LIMIT_LOW[31:16]", - "description": "This sets a minimum frequency that the ramp can not exceed so that the VCO does not get set beyond a valid frequency range. Suppose fLOW is this frequency and fVCO is the starting VCO frequency then: For fLOW ≤ fVCO: RAMP_LIMIT_LOW = 2 33 – 16777216 x (fVCO – fLOW) / fPD For fLOW > fVCO, this is not a valid condition to choose.", - "default": 0, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 86, - "fields": [ - { - "fieldtype": "normal", - "end": 15, - "start": 0, - "name": "RAMP_LIMIT_LOW[15:0]", - "description": "This sets a minimum frequency that the ramp can not exceed so that the VCO does not get set beyond a valid frequency range. Suppose fLOW is this frequency and fVCO is the starting VCO frequency then: For fLOW ≤ fVCO: RAMP_LIMIT_LOW = 2 33 – 16777216 x (fVCO – fLOW) / fPD For fLOW > fVCO, this is not a valid condition to choose.", - "default": 0, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 87, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 88, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 89, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 90, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 91, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 92, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 93, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 94, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 95, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 96, - "fields": [ - { - "fieldtype": "normal", - "end": 15, - "start": 15, - "name": "RAMP_BURST_EN", - "description": "Enables burst ramping mode. In this mode, a RAMP_BURST_COUNT ramps are sent out when RAMP_EN is set from 0 to 1.", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "DISABLED", - "description": "Disabled" - }, - { - "value": 1, - "name": "ENABLED", - "description": "Enabled" - } - ] - } - }, - { - "fieldtype": "normal", - "end": 14, - "start": 2, - "name": "RAMP_BURST_COUNT", - "description": "Sets how many ramps are run in burst ramping mode", - "default": 0, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 97, - "fields": [ - { - "fieldtype": "normal", - "end": 15, - "start": 15, - "name": "RAMP0_RST", - "description": "Resets RAMP0 at start of ramp to eliminate round-off errors. Must only be used in automatic ramping mode.", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "DISABLED", - "description": "Disabled" - }, - { - "value": 1, - "name": "ENABLED", - "description": "Enabled" - } - ] - } - }, - { - "fieldtype": "normal", - "end": 10, - "start": 7, - "name": "RAMP_TRIGB", - "description": "Multipurpose trigger B definition", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "DISABLED", - "description": "Disabled" - }, - { - "value": 1, - "name": "RAMP_CLK_RISING_EDGE", - "description": "RampClk pin rising edge" - }, - { - "value": 2, - "name": "RAMP_DIR_RISING_EDGE", - "description": "RampDir pin rising edge" - }, - { - "value": 4, - "name": "ALWAYS", - "description": "Always triggered" - }, - { - "value": 9, - "name": "RAMP_CLK_FALLING_EDGE", - "description": "RampClk pin falling edge" - }, - { - "value": 10, - "name": "RAMP_DIR_FALLING_EDGE", - "description": "RampDir pin falling edge" - } - ] - } - }, - { - "fieldtype": "normal", - "end": 6, - "start": 3, - "name": "RAMP_TRIGA", - "description": "Multipurpose Trigger A definition", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "DISABLED", - "description": "Disabled" - }, - { - "value": 1, - "name": "RAMP_CLK_RISING_EDGE", - "description": "RampClk pin rising edge" - }, - { - "value": 2, - "name": "RAMP_DIR_RISING_EDGE", - "description": "RampDir pin rising edge" - }, - { - "value": 4, - "name": "ALWAYS", - "description": "Always triggered" - }, - { - "value": 9, - "name": "RAMP_CLK_FALLING_EDGE", - "description": "RampClk pin falling edge" - }, - { - "value": 10, - "name": "RAMP_DIR_FALLING_EDGE", - "description": "RampDir pin falling edge" - } - ] - } - }, - { - "fieldtype": "normal", - "end": 1, - "start": 0, - "name": "RAMP_BURST_TRIG", - "description": "Ramp burst trigger definition that triggers the next ramp in the count. Note that RAMP_EN starts the count, not this word.", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "RAMP_TRANSITION", - "description": "Ramp Transition" - }, - { - "value": 1, - "name": "TRIGGER_A", - "description": "Trigger A" - }, - { - "value": 2, - "name": "TRIGGER_B", - "description": "Trigger B" - } - ] - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 2048 - } - ] - }, - { - "addr": 98, - "fields": [ - { - "fieldtype": "normal", - "end": 15, - "start": 2, - "name": "RAMP0_INC[29:16]", - "description": "2's complement of the amount the RAMP0 is incremented in phase detector cycles.", - "default": 0, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "normal", - "end": 0, - "start": 0, - "name": "RAMP0_DLY", - "description": "Enabling this bit uses two clocks instead of one to clock the ramp. Effectively doubling the length.", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "NORMAL_LENGTH", - "description": "Normal ramp length" - }, - { - "value": 1, - "name": "DOUBLE_LENGTH", - "description": "Double ramp length" - } - ] - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 99, - "fields": [ - { - "fieldtype": "normal", - "end": 15, - "start": 0, - "name": "RAMP0_INC[15:0]", - "description": "2's complement of the amount the RAMP0 is incremented in phase detector cycles.", - "default": 0, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 100, - "fields": [ - { - "fieldtype": "normal", - "end": 15, - "start": 0, - "name": "RAMP0_LEN", - "description": "Length of RAMP0 in phase detector cycles", - "default": 0, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 101, - "fields": [ - { - "fieldtype": "normal", - "end": 6, - "start": 6, - "name": "RAMP1_DLY", - "description": "Enabling this bit uses two clocks instead of one to clock the ramp. Effectively doubling the length.", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "NORMAL_LENGTH", - "description": "Normal ramp length" - }, - { - "value": 1, - "name": "DOUBLE_LENGTH", - "description": "Double ramp length" - } - ] - } - }, - { - "fieldtype": "normal", - "end": 5, - "start": 5, - "name": "RAMP1_RST", - "description": "Resets RAMP1 to eliminate rounding errors. Must be used in automatic ramping mode.", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "DISABLED", - "description": "Disabled" - }, - { - "value": 1, - "name": "ENABLED", - "description": "Enabled" - } - ] - } - }, - { - "fieldtype": "normal", - "end": 4, - "start": 4, - "name": "RAMP0_NEXT", - "description": "Defines what ramp comes after RAMP0", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "RAMP0", - "description": "Ramp 0" - }, - { - "value": 1, - "name": "RAMP1", - "description": "Ramp 1" - } - ] - } - }, - { - "fieldtype": "normal", - "end": 1, - "start": 0, - "name": "RAMP0_NEXT_TRIG", - "description": "Defines what triggers the next ramp", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "TIMEOUT_COUNTER", - "description": "RAMP0_LEN timeout counter" - }, - { - "value": 1, - "name": "TRIGGER_A", - "description": "Trigger A" - }, - { - "value": 2, - "name": "TRIGGER_B", - "description": "Trigger B" - } - ] - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 102, - "fields": [ - { - "fieldtype": "normal", - "end": 13, - "start": 0, - "name": "RAMP1_INC[29:16]", - "description": "2's complement of the amount the RAMP1 is incremented in phase detector cycles", - "default": 0, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 103, - "fields": [ - { - "fieldtype": "normal", - "end": 15, - "start": 0, - "name": "RAMP1_INC[15:0]", - "description": "2's complement of the amount the RAMP1 is incremented in phase detector cycles", - "default": 0, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 104, - "fields": [ - { - "fieldtype": "normal", - "end": 15, - "start": 0, - "name": "RAMP1_LEN", - "description": "Length of RAMP1 in phase detector cycles", - "default": 0, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 105, - "fields": [ - { - "fieldtype": "normal", - "end": 15, - "start": 6, - "name": "RAMP_DLY_CNT", - "description": "This is the number of state machine clock cycles for the VCO calibration in automatic mode. If the VCO calibration is less, then it is this time. If it is more, then the time is the VCO calibration time.", - "default": 0, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "normal", - "end": 5, - "start": 5, - "name": "RAMP_MANUAL", - "description": "Enables manual ramping mode, or otherwise automatic mode", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "AUTOMATIC", - "description": "Automatic ramping mode" - }, - { - "value": 1, - "name": "MANUAL", - "description": "Manual ramping mode" - } - ] - } - }, - { - "fieldtype": "normal", - "end": 4, - "start": 4, - "name": "RAMP1_NEXT", - "description": "Determines what ramp comes after RAMP1", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "RAMP0", - "description": "Ramp 0" - }, - { - "value": 1, - "name": "RAMP1", - "description": "Ramp 1" - } - ] - } - }, - { - "fieldtype": "normal", - "end": 1, - "start": 0, - "name": "RAMP1_NEXT_TRIG", - "description": "Defines what triggers the next ramp", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "RAMP1_LEN_TIMEOUT", - "description": "RAMP1_LEN timeout counter" - }, - { - "value": 1, - "name": "TRIGGER_A", - "description": "Trigger A" - }, - { - "value": 2, - "name": "TRIGGER_B", - "description": "Trigger B" - } - ] - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 106, - "fields": [ - { - "fieldtype": "normal", - "end": 4, - "start": 4, - "name": "RAMP_TRIG_CAL", - "description": "Enabling this bit forces the VCO to calibrate after the ramp.", - "default": 0, - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "DISABLED", - "description": "Disabled" - }, - { - "value": 1, - "name": "ENABLED", - "description": "Enabled" - } - ] - } - }, - { - "fieldtype": "normal", - "end": 2, - "start": 0, - "name": "RAMP_SCALE_COUNT", - "description": "Multiplies RAMP_DLY count by 2^RAMP_SCALE_COUNT", - "default": 7, - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 107, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 108, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 109, - "fields": [ - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 110, - "fields": [ - { - "fieldtype": "normal", - "end": 10, - "start": 9, - "name": "rb_LD_VTUNE", - "description": "Readback of Vtune lock detect", - "default": 0, - "access": "R", - "valid": { - "type": "enum", - "values": [ - { - "value": 0, - "name": "UNLOCKED_LOW", - "description": "Unlocked (Vtune low)" - }, - { - "value": 1, - "name": "INVALID_STATE", - "description": "Invalid State" - }, - { - "value": 2, - "name": "LOCKED", - "description": "Locked" - }, - { - "value": 3, - "name": "UNLOCKED_HIGH", - "description": "Unlocked (Vtune High)" - } - ] - } - }, - { - "fieldtype": "normal", - "end": 7, - "start": 5, - "name": "rb_VCO_SEL", - "description": "Reads back the actual VCO that the calibration has selected.", - "default": 0, - "access": "R", - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 111, - "fields": [ - { - "fieldtype": "normal", - "end": 7, - "start": 0, - "name": "rb_VCO_CAPCTRL", - "description": "Reads back the actual CAPCTRL capcode value the VCO calibration has chosen.", - "default": 183, - "access": "R", - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - }, - { - "addr": 112, - "fields": [ - { - "fieldtype": "normal", - "end": 8, - "start": 0, - "name": "rb_VCO_DACISET", - "description": "Reads back the actual amplitude (DACISET) value that the VCO calibration has chosen.", - "default": 170, - "access": "R", - "valid": { - "type": "int" - } - }, - { - "fieldtype": "constant", - "end": 15, - "start": 0, - "value": 0 - } - ] - } -] diff --git a/qick/qick_lib/qick/parser.py b/qick/qick_lib/qick/parser.py deleted file mode 100644 index dce0d3e..0000000 --- a/qick/qick_lib/qick/parser.py +++ /dev/null @@ -1,916 +0,0 @@ -""" -Function to parse tProc assembly language programs. -""" -import re - -# Function to parse program. - - -def parse_prog(file="prog.asm", outfmt="bin"): - """ - Parses the .asm assembly language tProc program into a specified output format (binary or hex) - - :param file: ASM program file name - :type file: str - :param outfmt: Output format ("bin" or "hex") - :type outfmt: str - :return: Program in the new output format - :rtype: bin or hex - """ - # Output structure. - outProg = {} - - # Instructions. - instList = {} - - # I-type. - instList['pushi'] = {'bin': '00010000'} - instList['popi'] = {'bin': '00010001'} - instList['mathi'] = {'bin': '00010010'} - instList['seti'] = {'bin': '00010011'} - instList['synci'] = {'bin': '00010100'} - instList['waiti'] = {'bin': '00010101'} - instList['bitwi'] = {'bin': '00010110'} - instList['memri'] = {'bin': '00010111'} - instList['memwi'] = {'bin': '00011000'} - instList['regwi'] = {'bin': '00011001'} - instList['setbi'] = {'bin': '00011010'} - - # J-type. - instList['loopnz'] = {'bin': '00110000'} - instList['condj'] = {'bin': '00110001'} - instList['end'] = {'bin': '00111111'} - - # R-type. - instList['math'] = {'bin': '01010000'} - instList['set'] = {'bin': '01010001'} - instList['sync'] = {'bin': '01010010'} - instList['read'] = {'bin': '01010011'} - instList['wait'] = {'bin': '01010100'} - instList['bitw'] = {'bin': '01010101'} - instList['memr'] = {'bin': '01010110'} - instList['memw'] = {'bin': '01010111'} - instList['setb'] = {'bin': '01011000'} - - # Structures for symbols and program. - progList = {} - symbList = {} - - ############################## - ### Read program from file ### - ############################## - fd = open(file, "r") - addr = 0 - for line in fd: - # Match comments. - m = re.search("^\s*//", line) - - # If there is a match. - if m: - # print(line) - a = 1 - - else: - # Match instructions. - jump_re = "^((.+):)?" - inst_re_I = "pushi|popi|mathi|seti|synci|waiti|bitwi|memri|memwi|regwi|setbi|" - inst_re_J = "loopnz|condj|end|" - inst_re_R = "math|set|sync|read|wait|bitw|memr|memw|setb" - inst_re = "\s*(" + inst_re_I + inst_re_J + inst_re_R + ")\s+(.+);" - comp_re = jump_re + inst_re - m = re.search(comp_re, line, flags=re.MULTILINE) - - # If there is a match. - if m: - # Tagged instruction for jump. - if m.group(2): - symb = m.group(2) - inst = m.group(3) - args = m.group(4) - - # Add symbol to symbList. - symbList[symb] = addr - - # Add instruction to progList. - progList[addr] = {'inst': inst, 'args': args} - - # Increment address. - addr = addr + 1 - - # Normal instruction. - else: - inst = m.group(3) - args = m.group(4) - - # Add instruction to progList. - progList[addr] = {'inst': inst, 'args': args} - - # Increment address. - addr = addr + 1 - - # Check special case of "end" instruction. - else: - m = re.search("\s*(end)\s*;", line) - - # If there is a match. - if m: - # Add instruction to progList. - progList[addr] = {'inst': 'end', 'args': ''} - - # Increment address. - addr = addr + 1 - - ######################### - ### Support functions ### - ######################### - def unsigned2bin(strin, bits=8): - maxv = 2**bits - 1 - - # Check if hex string. - m = re.search("^0x", strin, flags=re.MULTILINE) - if m: - dec = int(strin, 16) - else: - dec = int(strin, 10) - - # Check max. - if dec > maxv: - print("Error: number %d is bigger than %d" % (dec, maxv)) - return None - - # Convert to binary. - fmt = "{0:0" + str(bits) + "b}" - binv = fmt.format(dec) - - return binv - - def integer2bin(strin, bits=8): - minv = -2**(bits-1) - maxv = 2**(bits-1) - 1 - - # Check if hex string. - m = re.search("^0x", strin, flags=re.MULTILINE) - if m: - # Special case for hex number. - dec = int(strin, 16) - - # Convert to binary. - fmt = "{0:0" + str(bits) + "b}" - binv = fmt.format(dec) - - return binv - else: - dec = int(strin, 10) - - # Check max. - if dec < minv: - print("Error: number %d is smaller than %d" % (dec, minv)) - return None - - # Check max. - if dec > maxv: - print("Error: number %d is bigger than %d" % (dec, maxv)) - return None - - # Check if number is negative. - if dec < 0: - dec = dec + 2**bits - - # Convert to binary. - fmt = "{0:0" + str(bits) + "b}" - binv = fmt.format(dec) - - return binv - - def op2bin(op): - if op == "0": - return "0000" - elif op == ">": - return "0000" - elif op == ">=": - return "0001" - elif op == "<": - return "0010" - elif op == "<=": - return "0011" - elif op == "==": - return "0100" - elif op == "!=": - return "0101" - elif op == "+": - return "1000" - elif op == "-": - return "1001" - elif op == "*": - return "1010" - elif op == "&": - return "0000" - elif op == "|": - return "0001" - elif op == "^": - return "0010" - elif op == "~": - return "0011" - elif op == "<<": - return "0100" - elif op == ">>": - return "0101" - elif op == "upper": - return "1010" - elif op == "lower": - return "0101" - else: - print("Error: operation \"%s\" not recognized" % op) - return "1111" - - ###################################### - ### First pass: parse instructions ### - ###################################### - for e in progList: - inst = progList[e]['inst'] - args = progList[e]['args'] - - # I-type: three registers and an immediate value. - # I-type::page:channel:oper:ra:rb:rc:imm - - # pushi p, $ra, $rb, imm - if inst == 'pushi': - comp_re = "\s*(\d+)\s*,\s*\$(\d+)\s*,\s*\$(\d+)\s*,\s*(\-?\d+)" - m = re.search(comp_re, args) - - # If there is a match. - if m: - page = m.group(1) - ra = m.group(2) - rb = m.group(3) - imm = m.group(4) - - # Add entry into structure. - progList[e]['inst_parse'] = "I-type:pushi:" + \ - page + ":0:0:" + rb + ":" + ra + ":0:" + imm - - # Error: bad instruction format. - else: - print("Error: bad format on instruction @%d: %s" % (e, inst)) - - # popi p, $r - elif inst == 'popi': - comp_re = "\s*(\d+)\s*,\s*\$(\d+)" - m = re.search(comp_re, args) - - # If there is a match. - if m: - page = m.group(1) - r = m.group(2) - - # Add entry into structure. - progList[e]['inst_parse'] = "I-type:popi:" + \ - page + ":0:0:" + r + ":0:0:0" - - # Error: bad instruction format. - else: - print("Error: bad format on instruction @%d: %s" % (e, inst)) - - # mathi p, $ra, $rb oper imm - if inst == 'mathi': - comp_re = "\s*(\d+)\s*,\s*\$(\d+)\s*,\s*\$(\d+)\s*([\+\-\*])\s*(0?x?\-?[0-9a-fA-F]+)" - m = re.search(comp_re, args) - - # If there is a match. - if m: - page = m.group(1) - ra = m.group(2) - rb = m.group(3) - oper = m.group(4) - imm = m.group(5) - - # Add entry into structure. - progList[e]['inst_parse'] = "I-type:mathi:" + page + \ - ":0:" + oper + ":" + ra + ":" + rb + ":0:" + imm - - # Error: bad instruction format. - else: - print("Error: bad format on instruction @%d: %s" % (e, inst)) - - # seti ch, p, $r, t - if inst == 'seti': - comp_re = "\s*(\d+)\s*,\s*(\d+)\s*,\s*\$(\d+)\s*,\s*(\-?\d+)" - m = re.search(comp_re, args) - - # If there is a match. - if m: - ch = m.group(1) - page = m.group(2) - ra = m.group(3) - t = m.group(4) - - # Add entry into structure. - progList[e]['inst_parse'] = "I-type:seti:" + \ - page + ":" + ch + ":0:0:" + ra + ":0:" + t - - # Error: bad instruction format. - else: - print("Error: bad format on instruction @%d: %s" % (e, inst)) - - # synci t - if inst == 'synci': - comp_re = "\s*(\d+)" - m = re.search(comp_re, args) - - # If there is a match. - if m: - t = m.group(1) - - # Add entry into structure. - progList[e]['inst_parse'] = "I-type:synci:0:0:0:0:0:0:" + t - - # Error: bad instruction format. - else: - print("Error: bad format on instruction @%d: %s" % (e, inst)) - - # waiti ch, t - if inst == 'waiti': - comp_re = "\s*(\d+)\s*,\s*(\d+)" - m = re.search(comp_re, args) - - # If there is a match. - if m: - ch = m.group(1) - t = m.group(2) - - # Add entry into structure. - progList[e]['inst_parse'] = "I-type:waiti:0:" + \ - ch + ":0:0:0:0:" + t - - # Error: bad instruction format. - else: - print("Error: bad format on instruction @%d: %s" % (e, inst)) - - # bitwi p, $ra, $rb oper imm - if inst == 'bitwi': - comp_re = "\s*(\d+)\s*,\s*\$(\d+)\s*,\s*\$(\d+)\s*([&|<>^]+)\s*(0?x?\-?[0-9a-fA-F]+)" - m = re.search(comp_re, args) - - # If there is a match. - if m: - page = m.group(1) - ra = m.group(2) - rb = m.group(3) - oper = m.group(4) - imm = m.group(5) - - # Add entry into structure. - progList[e]['inst_parse'] = "I-type:bitwi:" + page + \ - ":0:" + oper + ":" + ra + ":" + rb + ":0:" + imm - - # bitwi p, $ra, ~imm - else: - comp_re = "\s*(\d+)\s*,\s*\$(\d+)\s*,\s*~\s*(0?x?\-?[0-9a-fA-F]+)" - m = re.search(comp_re, args) - - # If there is a match. - if m: - page = m.group(1) - ra = m.group(2) - oper = "~" - imm = m.group(3) - - # Add entry into structure. - progList[e]['inst_parse'] = "I-type:bitwi:" + \ - page + ":0:" + oper + ":" + ra + ":0:0:" + imm - - # Error: bad instruction format. - else: - print("Error: bad format on instruction @%d: %s" % (e, inst)) - - # memri p, $r, imm - if inst == 'memri': - comp_re = "\s*(\d+)\s*,\s*\$(\d+)\s*,\s*(0?x?\-?[0-9a-fA-F]+)" - m = re.search(comp_re, args) - - # If there is a match. - if m: - page = m.group(1) - r = m.group(2) - imm = m.group(3) - - # Add entry into structure. - progList[e]['inst_parse'] = "I-type:memri:" + \ - page + ":0:0:" + r + ":0:0:" + imm - - # Error: bad instruction format. - else: - print("Error: bad format on instruction @%d: %s" % (e, inst)) - - # memwi p, $r, imm - if inst == 'memwi': - comp_re = "\s*(\d+)\s*,\s*\$(\d+)\s*,\s*(0?x?\-?[0-9a-fA-F]+)" - m = re.search(comp_re, args) - - # If there is a match. - if m: - page = m.group(1) - r = m.group(2) - imm = m.group(3) - - # Add entry into structure. - progList[e]['inst_parse'] = "I-type:memwi:" + \ - page + ":0:0:0:0:" + r + ":" + imm - - # Error: bad instruction format. - else: - print("Error: bad format on instruction @%d: %s" % (e, inst)) - - # regwi p, $r, imm - if inst == 'regwi': - comp_re = "\s*(\d+)\s*,\s*\$(\d+)\s*,\s*(0?x?\-?[0-9a-fA-F]+)" - m = re.search(comp_re, args) - - # If there is a match. - if m: - page = m.group(1) - r = m.group(2) - imm = m.group(3) - - # Add entry into structure. - progList[e]['inst_parse'] = "I-type:regwi:" + \ - page + ":0:0:" + r + ":0:0:" + imm - - # Error: bad instruction format. - else: - print("Error: bad format on instruction @%d: %s" % (e, inst)) - - # setbi ch, p, $r, t - if inst == 'setbi': - comp_re = "\s*(\d+)\s*,\s*(\d+)\s*,\s*\$(\d+)\s*,\s*(\-?\d+)" - m = re.search(comp_re, args) - - # If there is a match. - if m: - ch = m.group(1) - page = m.group(2) - ra = m.group(3) - t = m.group(4) - - # Add entry into structure. - progList[e]['inst_parse'] = "I-type:setbi:" + \ - page + ":" + ch + ":0:0:" + ra + ":0:" + t - - # Error: bad instruction format. - else: - print("Error: bad format on instruction @%d: %s" % (e, inst)) - - # J-type: three registers and an address for jump. - # J-type::page:oper:ra:rb:rc:addr - - # loopnz p, $r, @label - if inst == 'loopnz': - comp_re = "\s*(\d+)\s*,\s*\$(\d+)\s*,\s*\@(.+)" - m = re.search(comp_re, args) - - # If there is a match. - if m: - page = m.group(1) - oper = "+" - r = m.group(2) - label = m.group(3) - - # Resolve symbol. - if label in symbList: - label_addr = symbList[label] - else: - print("Error: could not resolve symbol %s on instruction @%d: %s %s" % ( - label, e, inst, args)) - - # Add entry into structure. - regs = r + ":" + r + ":0:" + str(label_addr) - progList[e]['inst_parse'] = "J-type:loopnz:" + \ - page + ":" + oper + ":" + regs - - # Error: bad instruction format. - else: - print("Error: bad format on instruction @%d: %s" % (e, inst)) - - # condj p, $ra op $rb, @label - if inst == 'condj': - comp_re = "\s*(\d+)\s*,\s*\$(\d+)\s*([<>=!]+)\s*\$(\d+)\s*,\s*\@(.+)" - m = re.search(comp_re, args) - - # If there is a match. - if m: - page = m.group(1) - ra = m.group(2) - oper = m.group(3) - rb = m.group(4) - label = m.group(5) - - # Resolve symbol. - if label in symbList: - label_addr = symbList[label] - else: - print("Error: could not resolve symbol %s on instruction @%d: %s %s" % ( - label, e, inst, args)) - - # Add entry into structure. - regs = ra + ":" + rb + ":" + str(label_addr) - progList[e]['inst_parse'] = "J-type:condj:" + \ - page + ":" + oper + ":0:" + regs - - # Error: bad instruction format. - else: - print("Error: bad format on instruction @%d: %s" % (e, inst)) - - # end - if inst == 'end': - # Add entry into structure. - progList[e]['inst_parse'] = "J-type:end:0:0:0:0:0:0" - - # R-type: 8 registers, 7 for reading and 1 for writing. - # R-type::page:channel:oper:ra:rb:rc:rd:re:rf:rg:rh - - # math p, $ra, $rb oper $rc - if inst == 'math': - comp_re = "\s*(\d+)\s*,\s*\$(\d+)\s*,\s*\$(\d+)\s*([\+\-\*])\s*\$(\d+)" - m = re.search(comp_re, args) - - # If there is a match. - if m: - page = m.group(1) - ra = m.group(2) - rb = m.group(3) - oper = m.group(4) - rc = m.group(5) - - # Add entry into structure. - regs = ra + ":" + rb + ":" + rc + ":0:0:0:0:0" - progList[e]['inst_parse'] = "R-type:math:" + \ - page + ":0:" + oper + ":" + regs - - # Error: bad instruction format. - else: - print("Error: bad format on instruction @%d: %s" % (e, inst)) - - # set ch, p, $ra, $rb, $rc, $rd, $re, $rt - if inst == 'set': - regs = "\s*\$(\d+)\s*,\s*\$(\d+)\s*,\s*\$(\d+)\s*,\s*\$(\d+)\s*,\s*\$(\d+)\s*,\s*\$(\d+)" - comp_re = "\s*(\d+)\s*,\s*(\d+)\s*," + regs - m = re.search(comp_re, args) - - # If there is a match. - if m: - ch = m.group(1) - page = m.group(2) - ra = m.group(3) - rb = m.group(4) - rc = m.group(5) - rd = m.group(6) - ree = m.group(7) - rt = m.group(8) - - # Add entry into structure. - regs = ra + ":" + rt + ":" + rb + ":" + rc + ":" + rd + ":" + ree + ":0" - progList[e]['inst_parse'] = "R-type:set:" + \ - page + ":" + ch + ":0:0:" + regs - - # Error: bad instruction format. - else: - print("Error: bad format on instruction @%d: %s" % (e, inst)) - - # sync p, $r - if inst == 'sync': - comp_re = "\s*(\d+)\s*,\s*\$(\d+)" - m = re.search(comp_re, args) - - # If there is a match. - if m: - page = m.group(1) - r = m.group(2) - - # Add entry into structure. - progList[e]['inst_parse'] = "R-type:sync:" + \ - page + ":0:0:0:0:" + r + ":0:0:0:0:0" - - # Error: bad instruction format. - else: - print("Error: bad format on instruction @%d: %s" % (e, inst)) - - # read ch, p, oper $r - if inst == 'read': - comp_re = "\s*(\d+)\s*,\s*(\d+)\s*,\s*(upper|lower)\s+\$(\d+)" - m = re.search(comp_re, args) - - # If there is a match. - if m: - ch = m.group(1) - page = m.group(2) - oper = m.group(3) - r = m.group(4) - - # Add entry into structure. - progList[e]['inst_parse'] = "R-type:read:" + page + \ - ":" + ch + ":" + oper + ":" + r + ":0:0:0:0:0:0:0" - - # Error: bad instruction format. - else: - print("Error: bad format on instruction @%d: %s" % (e, inst)) - - # wait ch, p, $r - if inst == 'wait': - comp_re = "\s*(\d+)\s*,\s*(\d+)\s*,\s*\$(\d+)" - m = re.search(comp_re, args) - - # If there is a match. - if m: - ch = m.group(1) - page = m.group(2) - r = m.group(3) - - # Add entry into structure. - progList[e]['inst_parse'] = "R-type:wait:" + \ - page + ":" + ch + ":0:0:0:" + r + ":0:0:0:0:0" - - # Error: bad instruction format. - else: - print("Error: bad format on instruction @%d: %s" % (e, inst)) - - # bitw p, $ra, $rb oper $rc - if inst == 'bitw': - comp_re = "\s*(\d+)\s*,\s*\$(\d+)\s*,\s*\$(\d+)\s*([&|<>^]+)\s*\$(\d+)" - m = re.search(comp_re, args) - - # If there is a match. - if m: - page = m.group(1) - ra = m.group(2) - rb = m.group(3) - oper = m.group(4) - rc = m.group(5) - - # Add entry into structure. - regs = ra + ":" + rb + ":" + rc + ":0:0:0:0:0" - progList[e]['inst_parse'] = "R-type:bitw:" + \ - page + ":0:" + oper + ":" + regs - - # bitw p, $ra, ~$rb - else: - comp_re = "\s*(\d+)\s*,\s*\$(\d+)\s*,\s*~\s*\$(\d+)" - m = re.search(comp_re, args) - - # If there is a match. - if m: - page = m.group(1) - ra = m.group(2) - rb = m.group(3) - oper = "~" - - # Add entry into structure. - regs = ra + ":0:" + ":" + rb + ":0:0:0:0:0" - progList[e]['inst_parse'] = "R-type:bitw:" + \ - page + ":0:" + oper + ":" + regs - - # Error: bad instruction format. - else: - print("Error: bad format on instruction @%d: %s" % (e, inst)) - - # memr p, $ra, $rb - if inst == 'memr': - comp_re = "\s*(\d+)\s*,\s*\$(\d+)\s*,\s*\$(\d+)" - m = re.search(comp_re, args) - - # If there is a match. - if m: - page = m.group(1) - ra = m.group(2) - rb = m.group(3) - - # Add entry into structure. - regs = ra + ":" + rb + ":0:0:0:0:0:0" - progList[e]['inst_parse'] = "R-type:memr:" + \ - page + ":0:0:" + regs - - # Error: bad instruction format. - else: - print("Error: bad format on instruction @%d: %s" % (e, inst)) - - # memw p, $ra, $rb - if inst == 'memw': - comp_re = "\s*(\d+)\s*,\s*\$(\d+)\s*,\s*\$(\d+)" - m = re.search(comp_re, args) - - # If there is a match. - if m: - page = m.group(1) - ra = m.group(2) - rb = m.group(3) - - # Add entry into structure. - regs = rb + ":" + ra + ":0:0:0:0:0" - progList[e]['inst_parse'] = "R-type:memw:" + \ - page + ":0:0:0:" + regs - - # Error: bad instruction format. - else: - print("Error: bad format on instruction @%d: %s" % (e, inst)) - - # setb ch, p, $ra, $rb, $rc, $rd, $re, $rt - if inst == 'setb': - regs = "\s*\$(\d+)\s*,\s*\$(\d+)\s*,\s*\$(\d+)\s*,\s*\$(\d+)\s*,\s*\$(\d+)\s*,\s*\$(\d+)" - comp_re = "\s*(\d+)\s*,\s*(\d+)\s*," + regs - m = re.search(comp_re, args) - - # If there is a match. - if m: - ch = m.group(1) - page = m.group(2) - ra = m.group(3) - rb = m.group(4) - rc = m.group(5) - rd = m.group(6) - ree = m.group(7) - rt = m.group(8) - - # Add entry into structure. - regs = ra + ":" + rt + ":" + rb + ":" + rc + ":" + rd + ":" + ree + ":0" - progList[e]['inst_parse'] = "R-type:setb:" + \ - page + ":" + ch + ":0:0:" + regs - - # Error: bad instruction format. - else: - print("Error: bad format on instruction @%d: %s" % (e, inst)) - - ###################################### - ### Second pass: convert to binary ### - ###################################### - for e in progList: - inst = progList[e]['inst_parse'] - spl = inst.split(":") - - # I-type - if spl[0] == "I-type": - # Instruction. - if spl[1] in instList: - inst_bin = instList[spl[1]]['bin'] - else: - print( - "Error: instruction %s not found on instraction list" % spl[1]) - - # page. - page = unsigned2bin(spl[2], 3) - - # channel - ch = unsigned2bin(spl[3], 3) - - # oper - oper = op2bin(spl[4]) - - # Registers. - ra = unsigned2bin(spl[5], 5) - rb = unsigned2bin(spl[6], 5) - rc = unsigned2bin(spl[7], 5) - - # Immediate. - imm = integer2bin(spl[8], 31) - - # Machine code (bin/hex). - code = inst_bin + page + ch + oper + ra + rb + rc + imm - code_h = "{:016x}".format(int(code, 2)) - - # Write values back into hash. - progList[e]['inst_bin'] = code - progList[e]['inst_hex'] = code_h - - elif (spl[0] == "J-type"): - # Instruction. - if spl[1] in instList: - inst_bin = instList[spl[1]]['bin'] - else: - print( - "Error: instruction %s not found on instraction list" % spl[1]) - - # Page. - page = unsigned2bin(spl[2], 3) - - # Zeros. - z3 = unsigned2bin("0", 3) - - # oper - oper = op2bin(spl[3]) - - # Registers. - ra = unsigned2bin(spl[4], 5) - rb = unsigned2bin(spl[5], 5) - rc = unsigned2bin(spl[6], 5) - - # Zeros. - z15 = unsigned2bin("0", 15) - - # Address. - jmp_addr = unsigned2bin(spl[7], 16) - - # Machine code (bin/hex). - code = inst_bin + page + z3 + oper + ra + rb + rc + z15 + jmp_addr - code_h = "{:016x}".format(int(code, 2)) - - # Write values back into hash. - progList[e]['inst_bin'] = code - progList[e]['inst_hex'] = code_h - - elif (spl[0] == "R-type"): - # Instruction. - if spl[1] in instList: - inst_bin = instList[spl[1]]['bin'] - else: - print( - "Error: instruction \"%s\" not found on instraction list" % spl[1]) - - # Page. - page = unsigned2bin(spl[2], 3) - - # Channel - ch = unsigned2bin(spl[3], 3) - - # Oper - oper = op2bin(spl[4]) - - # Registers. - ra = unsigned2bin(spl[5], 5) - rb = unsigned2bin(spl[6], 5) - rc = unsigned2bin(spl[7], 5) - rd = unsigned2bin(spl[8], 5) - ree = unsigned2bin(spl[9], 5) - rf = unsigned2bin(spl[10], 5) - rg = unsigned2bin(spl[11], 5) - rh = unsigned2bin(spl[12], 5) - - # Zeros. - z6 = unsigned2bin("0", 6) - - # Machine code (bin/hex). - code = inst_bin + page + ch + oper + ra + \ - rb + rc + rd + ree + rf + rg + rh + z6 - code_h = "{:016x}".format(int(code, 2)) - - # Write values back into hash. - progList[e]['inst_bin'] = code - progList[e]['inst_hex'] = code_h - - else: - print("Error: bad type on instruction @%d: %s" % (e, inst)) - - #################### - ### Write output ### - #################### - # Binary format. - if outfmt == "bin": - for e in progList: - outProg[e] = progList[e]['inst_bin'] - - # Hex format. - elif outfmt == "hex": - for e in progList: - out = progList[e]['inst_hex'] + " -> " + \ - progList[e]['inst'] + " " + progList[e]['args'] - outProg[e] = out - - else: - print("Error: \"%s\" is not a recognized output format" % outfmt) - - # Return program list. - return outProg - - -def parse_to_bin(path): - """ - Parses the .asm assembly language tProc program into a form appropriate for QickSoc.load_bin_program(). - - :param file: ASM program file name - :type file: str - :return: Program as a list of 64-bit ints - :rtype: list - """ - p = parse_prog(path) - return [int(p[i], 2) for i in p] - -def load_program(soc, prog="prog.asm", fmt="asm"): - """ - Loads tProc program. If asm program, it compiles first - - :param soc: Qick to be programmed - :type soc: QickSoc - :param prog: program file name - :type prog: string - :param fmt: file format - :type fmt: string - """ - # Binary file format. - if fmt == "bin": - # Read binary file from disk. - with open(prog, "r") as fd: - progList = [int(line, 2) for line in fd] - - # Asm file. - elif fmt == "asm": - # Compile program. - progList = parse_to_bin(prog) - - soc.load_bin_program(progList) diff --git a/qick/qick_lib/qick/pyro.py b/qick/qick_lib/qick/pyro.py deleted file mode 100644 index 2c6ab01..0000000 --- a/qick/qick_lib/qick/pyro.py +++ /dev/null @@ -1,118 +0,0 @@ -import psutil, socket -import Pyro4 -import Pyro4.naming -from .qick_asm import QickConfig -# QickSoc is needed for the server but not the client -try: - from .qick import QickSoc -except: - pass - -def start_nameserver(ns_host='0.0.0.0', ns_port=8888): - """Starts a Pyro4 nameserver. - - Parameters - ---------- - ns_host : str - the nameserver hostname - ns_port : int - the port number for the nameserver to listen on - - Returns - ------- - """ - Pyro4.config.SERIALIZERS_ACCEPTED = set(['pickle']) - Pyro4.config.PICKLE_PROTOCOL_VERSION=4 - Pyro4.naming.startNSloop(host=ns_host, port=ns_port) - -def start_server(ns_host, ns_port=8888, proxy_name='myqick', **kwargs): - """Initializes the QickSoc and starts a Pyro4 proxy server. - - Parameters - ---------- - ns_host : str - hostname or IP address of the nameserver - if the nameserver is running on the QICK board, "localhost" is fine - ns_port : int - the port number you used when starting the nameserver - proxy_name : str - name for the QickSoc proxy - multiple boards can use the same nameserver, but must have different names - kwargs : optional named arguments - any other options will be passed to the QickSoc constructor; - see QickSoc documentation for details - - Returns - ------- - """ - Pyro4.config.REQUIRE_EXPOSE = False - Pyro4.config.SERIALIZER = "pickle" - Pyro4.config.SERIALIZERS_ACCEPTED=set(['pickle']) - Pyro4.config.PICKLE_PROTOCOL_VERSION=4 - - print("looking for nameserver . . .") - ns = Pyro4.locateNS(host=ns_host, port=ns_port) - print("found nameserver") - - # if we have multiple network interfaces, we want to register the daemon using the IP address that faces the nameserver - host = Pyro4.socketutil.getInterfaceAddress(ns._pyroUri.host) - # if the nameserver is running on the QICK, the above will usually return the loopback address - not useful - if host=="127.0.0.1": - # get the IPv4 address of the eth0 interface - # unless you have an unusual network config (e.g. VPN), this is the interface clients will want to connect to - (myaddr,) = [addr for addr in psutil.net_if_addrs()['eth0'] if addr.family==socket.AddressFamily.AF_INET] - host = myaddr.address - daemon = Pyro4.Daemon(host=host) - - # if you want to use a different firmware image or set some initialization options, you would do that here - soc = QickSoc(**kwargs) - print("initialized QICK") - - # register the QickSoc in the daemon (so the daemon exposes the QickSoc over Pyro4) - # and in the nameserver (so the client can find the QickSoc) - ns.register(proxy_name, daemon.register(soc)) - print("registered QICK") - - # register in the daemon all the objects we expose as properties of the QickSoc - # we don't register them in the nameserver, since they are only meant to be accessed through the QickSoc proxy - # https://pyro4.readthedocs.io/en/stable/servercode.html#autoproxying - # https://github.com/irmen/Pyro4/blob/master/examples/autoproxy/server.py - for obj in soc.autoproxy: - daemon.register(obj) - print("registered member "+str(obj)) - - print("starting daemon") - daemon.requestLoop() # this will run forever until interrupted - -def make_proxy(ns_host, ns_port='8888', proxy_name='myqick'): - """Connects to a QickSoc proxy server. - - Parameters - ---------- - ns_host : str - hostname or IP address of the nameserver - if the nameserver is running on the same PC you are running make_proxy() on, "localhost" is fine - ns_port : int - the port number you used when starting the nameserver - proxy_name : str - name for the QickSoc proxy you used when running start_server() - - Returns - ------- - Proxy - proxy to QickSoc - this is usually called "soc" in demos - QickConfig - config object - this is usually called "soccfg" in demos - """ - Pyro4.config.SERIALIZER = "pickle" - Pyro4.config.PICKLE_PROTOCOL_VERSION=4 - - ns = Pyro4.locateNS(host=ns_host, port=ns_port) - - # print the nameserver entries: you should see the QickSoc proxy - for k,v in ns.list().items(): - print(k,v) - - soc = Pyro4.Proxy(ns.lookup(proxy_name)) - soccfg = QickConfig(soc.get_cfg()) - return(soc, soccfg) diff --git a/qick/qick_lib/qick/pyro_cli.py b/qick/qick_lib/qick/pyro_cli.py deleted file mode 100644 index ab164be..0000000 --- a/qick/qick_lib/qick/pyro_cli.py +++ /dev/null @@ -1,37 +0,0 @@ -#!/usr/bin/env python3 -# Typically (use the IP and port of your Pyro nameserver): -# python -m qick.pyro_cli myqick -n 192.168.133.17 -p 8888 -import sys, getopt -from qick.pyro import start_server - -ns_host = None -ns_port = None -proxy_name = "myqick" - -options, remainder = getopt.gnu_getopt(sys.argv[1:], 'n:p:h') -for opt, arg in options: - if opt == '-n': - ns_host = arg - elif opt == '-p': - ns_port = int(arg) - elif opt == '-h': - print("\nUsage: "+sys.argv[0]+" [server name]") - print("Must be run as root.") - print("Arguments: ") - print("\t-n: nameserver hostname (default localhost)") - print("\t-p: nameserver port (default 9090)") - print("\t-i: network interface (default eth0)") - print("\t-h: this message") - print("\n") - print("On pynq 2.7 you may get an error relating to pynq not loading, or no XRT devices being found.") - print("If this happens, try the following (taken from /usr/local/bin/start_jupyter.sh):") - print("\tsudo -s") - print("\tfor f in /etc/profile.d/*.sh; do source $f; done") - print("\t"+sys.argv[0]+" [options]") - print("\n") - sys.exit(0) - -if remainder: - proxy_name = remainder[0] - -start_server(ns_host, ns_port, proxy_name) diff --git a/qick/qick_lib/qick/qick.py b/qick/qick_lib/qick/qick.py deleted file mode 100644 index 7422c67..0000000 --- a/qick/qick_lib/qick/qick.py +++ /dev/null @@ -1,928 +0,0 @@ -""" -The lower-level driver for the QICK library. Contains classes for interfacing with the SoC. -""" -import os -from pynq.overlay import Overlay -import xrfclk -import xrfdc -import numpy as np -import time -import queue -from . import bitfile_path, obtain -from .ip import SocIp, QickMetadata -from .parser import parse_to_bin -from .streamer import DataStreamer -from .qick_asm import QickConfig, QickProgram -from .drivers.generator import * -from .drivers.readout import * -from .drivers.tproc import * - - -class AxisSwitch(SocIp): - """ - AxisSwitch class to control Xilinx AXI-Stream switch IP - - :param nslave: Number of slave interfaces - :type nslave: int - :param nmaster: Number of master interfaces - :type nmaster: int - """ - bindto = ['xilinx.com:ip:axis_switch:1.1'] - REGISTERS = {'ctrl': 0x0, 'mix_mux': 0x040} - - def __init__(self, description): - """ - Constructor method - """ - super().__init__(description) - - # Number of slave interfaces. - self.NSL = int(description['parameters']['NUM_SI']) - # Number of master interfaces. - self.NMI = int(description['parameters']['NUM_MI']) - - # Init axis_switch. - self.ctrl = 0 - self.disable_ports() - - def disable_ports(self): - """ - Disables ports - """ - for ii in range(self.NMI): - offset = self.REGISTERS['mix_mux'] + 4*ii - self.write(offset, 0x80000000) - - def sel(self, mst=0, slv=0): - """ - Digitally connects a master interface with a slave interface - - :param mst: Master interface - :type mst: int - :param slv: Slave interface - :type slv: int - """ - # Sanity check. - if slv > self.NSL-1: - print("%s: Slave number %d does not exist in block." % - __class__.__name__) - return - if mst > self.NMI-1: - print("%s: Master number %d does not exist in block." % - __class__.__name__) - return - - # Disable register update. - self.ctrl = 0 - - # Disable all MI ports. - self.disable_ports() - - # MI[mst] -> SI[slv] - offset = self.REGISTERS['mix_mux'] + 4*mst - self.write(offset, slv) - - # Enable register update. - self.ctrl = 2 - - -class RFDC(xrfdc.RFdc): - """ - Extends the xrfdc driver. - Since operations on the RFdc tend to be slow (tens of ms), we cache the Nyquist zone and frequency. - """ - bindto = ["xilinx.com:ip:usp_rf_data_converter:2.3", - "xilinx.com:ip:usp_rf_data_converter:2.4", - "xilinx.com:ip:usp_rf_data_converter:2.6"] - - def __init__(self, description): - """ - Constructor method - """ - super().__init__(description) - # Nyquist zone for each channel - self.nqz_dict = {} - # Rounded NCO frequency for each channel - self.mixer_dict = {} - - def configure(self, soc): - self.daccfg = soc.dacs - self.adccfg = soc.adcs - - def set_mixer_freq(self, dacname, f, force=False, reset=False): - """ - Set the NCO frequency that will be mixed with the generator output. - - The RFdc driver does its own math to convert a frequency to a register value. - (see XRFdc_SetMixerSettings in xrfdc_mixer.c, and "NCO Frequency Conversion" in PG269) - This is what it does: - 1. Add/subtract fs to get the frequency in the range of [-fs/2, fs/2]. - 2. If the original frequency was not in [-fs/2, fs/2] and the DAC is configured for 2nd Nyquist zone, multiply by -1. - 3. Convert to a 48-bit register value, rounding using C integer casting (i.e. round towards 0). - - Step 2 is not desirable for us, so we must undo it. - - The rounding gives unexpected results sometimes: it's hard to tell if a freq will get rounded up or down. - This is important if the demanded frequency was rounded to a valid frequency for frequency matching. - The safest way to get consistent behavior is to always round to a valid NCO frequency. - We are trusting that the floating-point math is exact and a number we rounded here is still a round number in the RFdc driver. - - :param dacname: DAC channel (2-digit string) - :type dacname: int - :param f: NCO frequency - :type f: float - :param force: force update, even if the setting is the same - :type force: bool - :param reset: if we change the frequency, also reset the NCO's phase accumulator - :type reset: bool - """ - fs = self.daccfg[dacname]['fs'] - fstep = fs/2**48 - rounded_f = round(f/fstep)*fstep - if not force and rounded_f == self.get_mixer_freq(dacname): - return - fset = rounded_f - if abs(rounded_f) > fs/2 and self.get_nyquist(dacname)==2: - fset *= -1 - - tile, channel = [int(a) for a in dacname] - # Make a copy of mixer settings. - dac_mixer = self.dac_tiles[tile].blocks[channel].MixerSettings - new_mixcfg = dac_mixer.copy() - - # Update the copy - new_mixcfg.update({ - 'EventSource': xrfdc.EVNT_SRC_IMMEDIATE, - 'Freq': fset, - 'MixerType': xrfdc.MIXER_TYPE_FINE, - 'PhaseOffset': 0}) - - # Update settings. - if reset: self.dac_tiles[tile].blocks[channel].ResetNCOPhase() - self.dac_tiles[tile].blocks[channel].MixerSettings = new_mixcfg - self.dac_tiles[tile].blocks[channel].UpdateEvent(xrfdc.EVENT_MIXER) - self.mixer_dict[dacname] = rounded_f - - def get_mixer_freq(self, dacname): - try: - return self.mixer_dict[dacname] - except KeyError: - tile, channel = [int(a) for a in dacname] - self.mixer_dict[dacname] = self.dac_tiles[tile].blocks[channel].MixerSettings['Freq'] - return self.mixer_dict[dacname] - - def set_nyquist(self, dacname, nqz, force=False): - """ - Sets DAC channel to operate in Nyquist zone nqz. - This setting doesn't change the output frequencies: - you will always have some power at both the demanded frequency and its image(s). - Setting the NQZ to 2 increases output power in the 2nd/3rd Nyquist zones. - See "RF-DAC Nyquist Zone Operation" in PG269. - - :param dacname: DAC channel (2-digit string) - :type dacname: int - :param nqz: Nyquist zone (1 or 2) - :type nqz: int - :param force: force update, even if the setting is the same - :type force: bool - """ - if nqz not in [1,2]: - raise RuntimeError("Nyquist zone must be 1 or 2") - tile, channel = [int(a) for a in dacname] - if not force and self.get_nyquist(dacname) == nqz: - return - self.dac_tiles[tile].blocks[channel].NyquistZone = nqz - self.nqz_dict[dacname] = nqz - - def get_nyquist(self, dacname): - try: - return self.nqz_dict[dacname] - except KeyError: - tile, channel = [int(a) for a in dacname] - self.nqz_dict[dacname] = self.dac_tiles[tile].blocks[channel].NyquistZone - return self.nqz_dict[dacname] - - -class QickSoc(Overlay, QickConfig): - """ - QickSoc class. This class will create all object to access system blocks - - :param bitfile: Path to the bitfile. This should end with .bit, and the corresponding .hwh file must be in the same directory. - :type bitfile: str - :param force_init_clks: Re-initialize the board clocks regardless of whether they appear to be locked. Specifying (as True or False) the clk_output or external_clk options will also force clock initialization. - :type force_init_clks: bool - :param clk_output: If true, output a copy of the RF reference. This option is supported for the ZCU111 (get 122.88 MHz from J108) and ZCU216 (get 245.76 MHz from OUTPUT_REF J10). - :type clk_output: bool or None - :param external_clk: If true, lock the board clocks to an external reference. This option is supported for the ZCU111 (put 12.8 MHz on External_REF_CLK J109), ZCU216 (put 10 MHz on INPUT_REF_CLK J11), and RFSoC 4x2 (put 10 MHz on CLK_IN). - :type external_clk: bool or None - :param ignore_version: Whether version discrepancies between PYNQ build and firmware build are ignored - :type ignore_version: bool - """ - - # The following constants are no longer used. Some of the values may not match the bitfile. - # fs_adc = 384*8 # MHz - # fs_dac = 384*16 # MHz - # pulse_mem_len_IQ = 65536 # samples for I, Q - # ADC_decim_buf_len_IQ = 1024 # samples for I, Q - # ADC_accum_buf_len_IQ = 16384 # samples for I, Q - #tProc_instruction_len_bytes = 8 - #tProc_prog_mem_samples = 8000 - #tProc_prog_mem_size_bytes_tot = tProc_instruction_len_bytes*tProc_prog_mem_samples - #tProc_data_len_bytes = 4 - #tProc_data_mem_samples = 4096 - #tProc_data_mem_size_bytes_tot = tProc_data_len_bytes*tProc_data_mem_samples - #tProc_stack_len_bytes = 4 - #tProc_stack_samples = 256 - #tProc_stack_size_bytes_tot = tProc_stack_len_bytes*tProc_stack_samples - #phase_resolution_bits = 32 - #gain_resolution_signed_bits = 16 - - # Constructor. - def __init__(self, bitfile=None, force_init_clks=False, ignore_version=True, no_tproc=False, clk_output=None, external_clk=None, **kwargs): - """ - Constructor method - """ - - self.external_clk = external_clk - self.clk_output = clk_output - # Load bitstream. We read the bitstream configuration from the HWH file, but we don't program the FPGA yet. - # We need to program the clocks first. - if bitfile is None: - Overlay.__init__(self, bitfile_path( - ), ignore_version=ignore_version, download=False, **kwargs) - else: - Overlay.__init__( - self, bitfile, ignore_version=ignore_version, download=False, **kwargs) - - # Initialize the configuration - self._cfg = {} - QickConfig.__init__(self) - - self['board'] = os.environ["BOARD"] - - # Read the config to get a list of enabled ADCs and DACs, and the sampling frequencies. - self.list_rf_blocks( - self.ip_dict['usp_rf_data_converter_0']['parameters']) - - self.config_clocks(force_init_clks) - - # RF data converter (for configuring ADCs and DACs, and setting NCOs) - self.rf = self.usp_rf_data_converter_0 - self.rf.configure(self) - - # Extract the IP connectivity information from the HWH parser and metadata. - self.metadata = QickMetadata(self) - - if not no_tproc: - # tProcessor, 64-bit instruction, 32-bit registers, x8 channels. - if 'axis_tproc64x32_x8_0' in self.ip_dict: - self._tproc = self.axis_tproc64x32_x8_0 - self._tproc.configure(self.axi_bram_ctrl_0, self.axi_dma_tproc) - self['fs_proc'] = self.metadata.get_fclk(self.tproc.fullpath, "aclk") - elif 'qick_processor_0' in self.ip_dict: - self._tproc = self.qick_processor_0 - self._tproc.configure(self.axi_dma_tproc) - self['fs_proc'] = self.metadata.get_fclk(self.tproc.fullpath, "c_clk_i") - else: - raise RuntimeError('No tProcessor found') - - #self.tnet = self.qick_net_0 - - self.map_signal_paths() - - self._streamer = DataStreamer(self) - - # list of objects that need to be registered for autoproxying over Pyro - self.autoproxy = [self.streamer, self.tproc] - - @property - def tproc(self): - return self._tproc - - @property - def streamer(self): - return self._streamer - - def map_signal_paths(self): - """ - Make lists of signal generator, readout, and buffer blocks in the firmware. - Also map the switches connecting the generators and buffers to DMA. - Fill the config dictionary with parameters of the DAC and ADC channels. - """ - # Use the HWH parser to trace connectivity and deduce the channel numbering. - for key, val in self.ip_dict.items(): - if hasattr(val['driver'], 'configure_connections'): - getattr(self, key).configure_connections(self) - - # Signal generators (anything driven by the tProc) - self.gens = [] - - # Constant generators - self.iqs = [] - - # Average + Buffer blocks. - self.avg_bufs = [] - - # Readout blocks. - self.readouts = [] - ro_drivers = set([AxisReadoutV2, AxisPFBReadoutV2]) - - # Populate the lists with the registered IP blocks. - for key, val in self.ip_dict.items(): - if issubclass(val['driver'], AbsPulsedSignalGen): - self.gens.append(getattr(self, key)) - elif val['driver'] == AxisConstantIQ: - self.iqs.append(getattr(self, key)) - elif val['driver'] in ro_drivers: - self.readouts.append(getattr(self, key)) - elif val['driver'] == AxisAvgBuffer: - self.avg_bufs.append(getattr(self, key)) - - # AxisReadoutV3 isn't a PYNQ-registered IP block, so we add it here - for buf in self.avg_bufs: - if buf.readout not in self.readouts: - self.readouts.append(buf.readout) - - # Sort the lists. - # We order gens by the tProc port number and buffers by the switch port number. - # Those orderings are important, since those indices get used in programs. - self.gens.sort(key=lambda x: x['tproc_ch']) - self.avg_bufs.sort(key=lambda x: x.switch_ch) - # The IQ and readout orderings aren't critical for anything. - self.iqs.sort(key=lambda x: x.dac) - self.readouts.sort(key=lambda x: x.adc) - - # which generators have waveform memories? - arb_gens = filter(lambda x: isinstance(x, AbsArbSignalGen), self.gens) - # Configure the DMA connections to upload waveforms to generators. - if arb_gens: - # AXIS Switch to upload samples into Signal Generators. - self.switch_gen = self.axis_switch_gen - - """ - # This sanity check doesn't always pass, we have firmwares that don't use all the switch ports. - if self.switch_gen.NMI != len(arb_gens): - raise RuntimeError("We have %d switch_gen outputs but %d arbitrary-waveform generator blocks." % - (self.switch_gen.NMI, len(arb_gens))) - """ - - for gen in arb_gens: - gen.configure_dma(self.axi_dma_gen, self.switch_gen) - - # Configure the DMA connections to download data from avg+buffer blocks. - if self.avg_bufs: - # AXIS Switch to read samples from averager. - self.switch_avg = self.axis_switch_avg - # AXIS Switch to read samples from buffer. - self.switch_buf = self.axis_switch_buf - # Sanity check: we should have the same number of buffer blocks as switch ports. - if self.switch_avg.NSL != len(self.avg_bufs): - raise RuntimeError("We have %d switch_avg inputs but %d avg/buffer blocks." % - (self.switch_avg.NSL, len(self.avg_bufs))) - if self.switch_buf.NSL != len(self.avg_bufs): - raise RuntimeError("We have %d switch_buf inputs but %d avg/buffer blocks." % - (self.switch_buf.NSL, len(self.avg_bufs))) - - for buf in self.avg_bufs: - buf.configure(self.axi_dma_avg, self.switch_avg, - self.axi_dma_buf, self.switch_buf) - - # Configure the drivers. - for i, gen in enumerate(self.gens): - gen.configure(i, self.rf, self.dacs[gen.dac]['fs']) - - for i, iq in enumerate(self.iqs): - iq.configure(i, self.rf, self.dacs[iq.dac]['fs']) - - for readout in self.readouts: - readout.configure(self.rf, self.adcs[readout.adc]['fs']) - - # Fill the config dictionary with driver parameters. - self['dacs'] = list(self.dacs.keys()) - self['adcs'] = list(self.adcs.keys()) - self['gens'] = [gen.cfg for gen in self.gens] - self['iqs'] = [iq.cfg for iq in self.iqs] - - # In the config, we define a "readout" as the chain of ADC+readout+buffer. - def merge_cfgs(bufcfg, rocfg): - merged = {**bufcfg, **rocfg} - for k in set(bufcfg.keys()) & set(rocfg.keys()): - del merged[k] - merged["avgbuf_"+k] = bufcfg[k] - merged["ro_"+k] = rocfg[k] - return merged - self['readouts'] = [merge_cfgs(buf.cfg, buf.readout.cfg) for buf in self.avg_bufs] - - self['tprocs'] = [self.tproc.cfg] - - def config_clocks(self, force_init_clks): - """ - Configure PLLs if requested, or if any ADC/DAC is not locked. - """ - - # if we're changing the clock config, we must set the clocks to apply the config - if force_init_clks or (self.external_clk is not None) or (self.clk_output is not None): - self.set_all_clks() - self.download() - else: - self.download() - if not self.clocks_locked(): - self.set_all_clks() - self.download() - if not self.clocks_locked(): - print( - "Not all DAC and ADC PLLs are locked. You may want to repeat the initialization of the QickSoc.") - - def clocks_locked(self): - """ - Checks whether the DAC and ADC PLLs are locked. - This can only be run after the bitstream has been downloaded. - - :return: clock status - :rtype: bool - """ - - dac_locked = [self.usp_rf_data_converter_0.dac_tiles[iTile] - .PLLLockStatus == 2 for iTile in self.dac_tiles] - adc_locked = [self.usp_rf_data_converter_0.adc_tiles[iTile] - .PLLLockStatus == 2 for iTile in self.adc_tiles] - return all(dac_locked) and all(adc_locked) - - def list_rf_blocks(self, rf_config): - """ - Lists the enabled ADCs and DACs and get the sampling frequencies. - XRFdc_CheckBlockEnabled in xrfdc_ap.c is not accessible from the Python interface to the XRFdc driver. - This re-implements that functionality. - """ - - self.hs_adc = rf_config['C_High_Speed_ADC'] == '1' - - self.dac_tiles = [] - self.adc_tiles = [] - dac_fabric_freqs = [] - adc_fabric_freqs = [] - refclk_freqs = [] - self.dacs = {} - self.adcs = {} - - for iTile in range(4): - if rf_config['C_DAC%d_Enable' % (iTile)] != '1': - continue - self.dac_tiles.append(iTile) - f_fabric = float(rf_config['C_DAC%d_Fabric_Freq' % (iTile)]) - f_refclk = float(rf_config['C_DAC%d_Refclk_Freq' % (iTile)]) - dac_fabric_freqs.append(f_fabric) - refclk_freqs.append(f_refclk) - fs = float(rf_config['C_DAC%d_Sampling_Rate' % (iTile)])*1000 - for iBlock in range(4): - if rf_config['C_DAC_Slice%d%d_Enable' % (iTile, iBlock)] != 'true': - continue - self.dacs["%d%d" % (iTile, iBlock)] = {'fs': fs, - 'f_fabric': f_fabric} - - for iTile in range(4): - if rf_config['C_ADC%d_Enable' % (iTile)] != '1': - continue - self.adc_tiles.append(iTile) - f_fabric = float(rf_config['C_ADC%d_Fabric_Freq' % (iTile)]) - f_refclk = float(rf_config['C_ADC%d_Refclk_Freq' % (iTile)]) - adc_fabric_freqs.append(f_fabric) - refclk_freqs.append(f_refclk) - fs = float(rf_config['C_ADC%d_Sampling_Rate' % (iTile)])*1000 - for iBlock in range(4): - if self.hs_adc: - if iBlock >= 2 or rf_config['C_ADC_Slice%d%d_Enable' % (iTile, 2*iBlock)] != 'true': - continue - else: - if rf_config['C_ADC_Slice%d%d_Enable' % (iTile, iBlock)] != 'true': - continue - self.adcs["%d%d" % (iTile, iBlock)] = {'fs': fs, - 'f_fabric': f_fabric} - - def get_common_freq(freqs): - """ - Check that all elements of the list are equal, and return the common value. - """ - if not freqs: # input is empty list - return None - if len(set(freqs)) != 1: - raise RuntimeError("Unexpected frequencies:", freqs) - return freqs[0] - - self['refclk_freq'] = get_common_freq(refclk_freqs) - - def set_all_clks(self): - """ - Resets all the board clocks - """ - if self['board'] == 'ZCU111': - # master clock generator is LMK04208, always outputs 122.88 - # DAC/ADC are clocked by LMX2594 - # available: 102.4, 204.8, 409.6, 737.0 - lmk_freq = 122.88 - lmx_freq = self['refclk_freq'] - print("resetting clocks:", lmk_freq, lmx_freq) - - if hasattr(xrfclk, "xrfclk"): # pynq 2.7 - # load the default clock chip configurations from file, so we can then modify them - xrfclk.xrfclk._find_devices() - xrfclk.xrfclk._read_tics_output() - if self.clk_output: - # change the register for the LMK04208 chip's 5th output, which goes to J108 - # we need this for driving the RF board - xrfclk.xrfclk._Config['lmk04208'][lmk_freq][6] = 0x00140325 - if self.external_clk: - # default value is 0x2302886D - xrfclk.xrfclk._Config['lmk04208'][lmk_freq][14] = 0x2302826D - else: # pynq 2.6 - if self.clk_output: - # change the register for the LMK04208 chip's 5th output, which goes to J108 - # we need this for driving the RF board - xrfclk._lmk04208Config[lmk_freq][6] = 0x00140325 - else: # restore the default - xrfclk._lmk04208Config[lmk_freq][6] = 0x80141E05 - if self.external_clk: - xrfclk._lmk04208Config[lmk_freq][14] = 0x2302826D - else: # restore the default - xrfclk._lmk04208Config[lmk_freq][14] = 0x2302886D - xrfclk.set_all_ref_clks(lmx_freq) - elif self['board'] == 'ZCU216': - # master clock generator is LMK04828, which is used for DAC/ADC clocks - # only 245.76 available by default - # LMX2594 is not used - # available: 102.4, 204.8, 409.6, 491.52, 737.0 - lmk_freq = self['refclk_freq'] - lmx_freq = self['refclk_freq']*2 - print("resetting clocks:", lmk_freq, lmx_freq) - - assert hasattr(xrfclk, "xrfclk") # ZCU216 only has a pynq 2.7 image - xrfclk.xrfclk._find_devices() - xrfclk.xrfclk._read_tics_output() - if self.external_clk: - # default value is 0x01471A - xrfclk.xrfclk._Config['lmk04828'][lmk_freq][80] = 0x01470A - if self.clk_output: - # default value is 0x012C22 - xrfclk.xrfclk._Config['lmk04828'][lmk_freq][55] = 0x012C02 - xrfclk.set_ref_clks(lmk_freq=lmk_freq, lmx_freq=lmx_freq) - elif self['board'] == 'RFSoC4x2': - # master clock generator is LMK04828, always outputs 245.76 - # DAC/ADC are clocked by LMX2594 - # available: 102.4, 204.8, 409.6, 491.52, 737.0 - lmk_freq = 245.76 - lmx_freq = self['refclk_freq'] - print("resetting clocks:", lmk_freq, lmx_freq) - - xrfclk.xrfclk._find_devices() - xrfclk.xrfclk._read_tics_output() - if self.external_clk: - # default value is 0x01471A - xrfclk.xrfclk._Config['lmk04828'][lmk_freq][80] = 0x01470A - xrfclk.set_ref_clks(lmk_freq=lmk_freq, lmx_freq=lmx_freq) - - def get_decimated(self, ch, address=0, length=None): - """ - Acquires data from the readout decimated buffer - - :param ch: ADC channel - :type ch: int - :param address: Address of data - :type address: int - :param length: Buffer transfer length - :type length: int - :return: List of I and Q decimated arrays - :rtype: list - """ - if length is None: - # this default will always cause a RuntimeError - # TODO: remove the default, or pick a better fallback value - length = self.avg_bufs[ch].BUF_MAX_LENGTH - - # we must transfer an even number of samples, so we pad the transfer size - transfer_len = length + length % 2 - - # there is a bug which causes the first sample of a transfer to always be the sample at address 0 - # we work around this by requesting an extra 2 samples at the beginning - data = self.avg_bufs[ch].transfer_buf( - (address-2) % self.avg_bufs[ch].BUF_MAX_LENGTH, transfer_len+2) - - # we remove the padding here - return data[2:length+2] - - def get_accumulated(self, ch, address=0, length=None): - """ - Acquires data from the readout accumulated buffer - - :param ch: ADC channel - :type ch: int - :param address: Address of data - :type address: int - :param length: Buffer transfer length - :type length: int - :returns: - - di[:length] (:py:class:`list`) - list of accumulated I data - - dq[:length] (:py:class:`list`) - list of accumulated Q data - """ - if length is None: - # this default will always cause a RuntimeError - # TODO: remove the default, or pick a better fallback value - length = self.avg_bufs[ch].AVG_MAX_LENGTH - - # we must transfer an even number of samples, so we pad the transfer size - transfer_len = length + length % 2 - - # there is a bug which causes the first sample of a transfer to always be the sample at address 0 - # we work around this by requesting an extra 2 samples at the beginning - data = self.avg_bufs[ch].transfer_avg( - (address-2) % self.avg_bufs[ch].AVG_MAX_LENGTH, transfer_len+2) - - # we remove the padding here - return data[2:length+2] - - def init_readouts(self): - """ - Initialize readouts, in preparation for configuring them. - """ - for readout in self.readouts: - # if this is a tProc-controlled readout, we don't initialize it here - if not isinstance(readout, AxisReadoutV3): - readout.initialize() - - def configure_readout(self, ch, output, frequency, gen_ch=0): - """Configure readout channel output style and frequency. - This method is only for use with PYNQ-controlled readouts. - :param ch: Channel to configure - :type ch: int - :param output: output type from 'product', 'dds', 'input' - :type output: str - :param frequency: frequency - :type frequency: float - :param gen_ch: DAC channel (use None if you don't want to round to a valid DAC frequency) - :type gen_ch: int - """ - buf = self.avg_bufs[ch] - buf.readout.set_out(sel=output) - buf.set_freq(frequency, gen_ch=gen_ch) - - def config_avg(self, ch, address=0, length=1, enable=True): - """Configure and optionally enable accumulation buffer - :param ch: Channel to configure - :type ch: int - :param address: Starting address of buffer - :type address: int - :param length: length of buffer (how many samples to take) - :type length: int - :param enable: True to enable buffer - :type enable: bool - """ - avg_buf = self.avg_bufs[ch] - avg_buf.config_avg(address, length) - if enable: - avg_buf.enable_avg() - - def config_buf(self, ch, address=0, length=1, enable=True): - """Configure and optionally enable decimation buffer - :param ch: Channel to configure - :type ch: int - :param address: Starting address of buffer - :type address: int - :param length: length of buffer (how many samples to take) - :type length: int - :param enable: True to enable buffer - :type enable: bool - """ - avg_buf = self.avg_bufs[ch] - avg_buf.config_buf(address, length) - if enable: - avg_buf.enable_buf() - - def get_avg_max_length(self, ch=0): - """Get accumulation buffer length for channel - :param ch: Channel - :type ch: int - :return: Length of accumulation buffer for channel 'ch' - :rtype: int - """ - return self['readouts'][ch]['avg_maxlen'] - - def load_pulse_data(self, ch, data, addr): - """Load pulse data into signal generators - :param ch: Channel - :type ch: int - :param data: array of (I, Q) values for pulse envelope - :type data: int16 array - :param addr: address to start data at - :type addr: int - """ - return self.gens[ch].load(xin=data, addr=addr) - - def set_nyquist(self, ch, nqz, force=False): - """ - Sets DAC channel ch to operate in Nyquist zone nqz mode. - - :param ch: DAC channel (index in 'gens' list) - :type ch: int - :param nqz: Nyquist zone - :type nqz: int - """ - - self.gens[ch].set_nyquist(nqz) - - def set_mixer_freq(self, ch, f, ro_ch=None): - """ - Set mixer frequency for a signal generator. - If the generator does not have a mixer, you will get an error. - - :param ch: DAC channel (index in 'gens' list) - :type ch: int - :param f: frequency (MHz) - :type f: float - :param ro_ch: readout channel (use None if you don't want to round to a valid ADC frequency) - :type ro_ch: int - """ - if self.gens[ch].HAS_MIXER: - self.gens[ch].set_mixer_freq(f, ro_ch) - elif f != 0: - raise RuntimeError("tried to set a mixer frequency, but this channel doesn't have a mixer") - - def set_mux_freqs(self, ch, freqs, gains=None, ro_ch=0): - """ - Set muxed frequencies and gains for a signal generator. - If it's not a muxed signal generator, you will get an error. - - Gains can only be specified for a muxed generator with configurable gains. - The gain list must be the same length as the freqs list. - - :param ch: DAC channel (index in 'gens' list) - :type ch: int - :param freqs: frequencies (MHz) - :type freqs: list - :param gains: gains (in range -1 to 1) - :type gains: list - :param ro_ch: readout channel (use None if you don't want to round to a valid ADC frequency) - :type ro_ch: int - """ - if gains is not None and len(gains) != len(freqs): - raise RuntimeError("lengths of freqs and gains lists do not match") - for ii, f in enumerate(freqs): - self.gens[ch].set_freq(f, out=ii, ro_ch=ro_ch) - if gains is not None: - self.gens[ch].set_gain(gains[ii], out=ii) - - def set_iq(self, ch, f, i, q): - """ - Set frequency, I, and Q for a constant-IQ output. - - :param ch: IQ channel (index in 'iqs' list) - :type ch: int - :param f: frequency (MHz) - :type f: float - :param i: I value (in range -1 to 1) - :type i: float - :param q: Q value (in range -1 to 1) - :type q: float - """ - self.iqs[ch].set_mixer_freq(f) - self.iqs[ch].set_iq(i, q) - - def load_bin_program(self, binprog, reset=False): - """ - Write the program to the tProc program memory. - - :param reset: Reset the tProc before writing the program. - :type reset: bool - """ - if reset: self.tproc.reset() - - # cast the program words to 64-bit uints - self.binprog = np.array(obtain(binprog), dtype=np.uint64) - # reshape to 32 bits to match the program memory - self.binprog = np.frombuffer(self.binprog, np.uint32) - - self.reload_program() - - def reload_program(self): - """ - Write the most recently written program to the tProc program memory. - This is normally useful after a reset (which erases the program memory) - """ - # write the program to memory with a fast copy - #print(self.binprog) - np.copyto(self.tproc.mem.mmio.array[:len(self.binprog)], self.binprog) - - def start_src(self, src): - """ - Sets the start source of tProc - - :param src: start source "internal" or "external" - :type src: string - """ - # set internal-start register to "init" - # otherwise we might start the tProc on a transition from external to internal start - self.tproc.start_reg = 0 - self.tproc.start_src_reg = {"internal": 0, "external": 1}[src] - - def reset_gens(self): - """ - Reset the tProc and run a minimal tProc program that drives all signal generators with 0's. - Useful for stopping any periodic or stdysel="last" outputs that may have been driven by a previous program. - """ - prog = QickProgram(self) - for gen in self.gens: - if isinstance(gen, AbsArbSignalGen): - prog.set_pulse_registers(ch=gen.ch, style="const", mode="oneshot", freq=0, phase=0, gain=0, length=3) - prog.pulse(ch=gen.ch,t=0) - prog.end() - # this should always run with internal trigger - self.start_src("internal") - prog.load_program(self, reset=True) - self.tproc.start() - - def start_readout(self, total_reps, counter_addr=1, ch_list=None, reads_per_rep=1, stride=None): - """ - Start a streaming readout of the accumulated buffers. - - :param total_count: Number of data points expected - :type total_count: int - :param counter_addr: Data memory address for the loop counter - :type counter_addr: int - :param ch_list: List of readout channels - :type ch_list: list - :param reads_per_count: Number of data points to expect per counter increment - :type reads_per_count: int - :param stride: Default number of measurements to transfer at a time. - :type stride: int - """ - ch_list = obtain(ch_list) - if ch_list is None: ch_list = [0, 1] - streamer = self.streamer - - if not streamer.readout_worker.is_alive(): - print("restarting readout worker") - streamer.start_worker() - print("worker restarted") - - # if there's still a readout job running, stop it - if streamer.readout_running(): - print("cleaning up previous readout: stopping tProc and streamer loop") - # stop the tProc - self.tproc.reset() - # tell the readout to stop (this will break the readout loop) - streamer.stop_readout() - streamer.done_flag.wait() - # push a dummy packet into the data queue to halt any running poll_data(), and wait long enough for the packet to be read out - streamer.data_queue.put((0, None)) - time.sleep(0.1) - # reload the program (since the reset will have wiped it out) - self.reload_program() - print("streamer stopped") - streamer.stop_flag.clear() - - if streamer.data_available(): - # flush all the data in the streamer buffer - print("clearing streamer buffer") - # read until the queue times out, discard the data - self.poll_data(totaltime=-1, timeout=0.1) - print("buffer cleared") - - streamer.total_count = total_reps*reads_per_rep - streamer.count = 0 - - streamer.done_flag.clear() - streamer.job_queue.put((total_reps, counter_addr, ch_list, reads_per_rep, stride)) - - def poll_data(self, totaltime=0.1, timeout=None): - """ - Get as much data as possible from the streamer data queue. - Stop when any of the following conditions are met: - * all the data has been transferred (based on the total_count) - * we got data, and it has been totaltime seconds since poll_data was called - * timeout is defined, and the timeout expired without getting new data in the queue - If there are errors in the error queue, raise the first one. - - :param totaltime: How long to acquire data (negative value = ignore total time and total count, just read until timeout) - :type totaltime: float - :param timeout: How long to wait for the next data packet (None = wait forever) - :type timeout: float - :return: list of (data, stats) pairs, oldest first - :rtype: list - """ - streamer = self.streamer - - time_end = time.time() + totaltime - new_data = [] - while (totaltime < 0) or (streamer.count < streamer.total_count and time.time() < time_end): - try: - raise RuntimeError("exception in readout loop") from streamer.error_queue.get(block=False) - except queue.Empty: - pass - try: - length, data = streamer.data_queue.get(block=True, timeout=timeout) - # if we stopped the readout while we were waiting for data, break out and return - if streamer.stop_flag.is_set() or data is None: - break - streamer.count += length - new_data.append(data) - except queue.Empty: - break - return new_data diff --git a/qick/qick_lib/qick/qick_111.bit b/qick/qick_lib/qick/qick_111.bit deleted file mode 100644 index 59d3979..0000000 Binary files a/qick/qick_lib/qick/qick_111.bit and /dev/null differ diff --git a/qick/qick_lib/qick/qick_111.hwh b/qick/qick_lib/qick/qick_111.hwh deleted file mode 100644 index 0028b6c..0000000 --- a/qick/qick_lib/qick/qick_111.hwh +++ /dev/null @@ -1,31261 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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Contains an tProc assembly language wrapper class and auxiliary functions. -""" -import logging -from typing import Union, List -import numpy as np -import json -from collections import namedtuple, OrderedDict -from abc import ABC, abstractmethod -from tqdm.auto import tqdm - -from qick import obtain -from .helpers import gauss, triang, DRAG, NpEncoder, ch2list -from .parser import parse_prog - -RegisterType = ["freq", "time", "phase", "adc_freq"] -DefaultUnits = {"freq": "MHz", "time": "us", "phase": "deg", "adc_freq": "MHz"} -MathOperators = ["+", "-", "*"] -logger = logging.getLogger(__name__) - -class QickConfig(): - """Uses the QICK configuration to convert frequencies and clock delays. - If running on the QICK, you don't need to use this class - the QickSoc class has all of the same methods. - If running remotely, you may want to initialize a QickConfig from a JSON file. - - Parameters - ---------- - cfg : dict or str - config dictionary, or path to JSON file - - Returns - ------ - - """ - - def __init__(self, cfg=None): - if isinstance(cfg, str): - with open(cfg) as f: - self._cfg = json.load(f) - elif cfg is not None: - self._cfg = cfg - - def __str__(self): - return self.description() - - def __getitem__(self, key): - return self._cfg[key] - - def __setitem__(self, key, val): - self._cfg[key] = val - - def description(self): - """Generate a printable description of the QICK configuration. - - Parameters - ---------- - - Returns - ------- - str - description - - """ - lines = [] - lines.append("\n\tBoard: " + self['board']) - lines.append("\n\tGlobal clocks (MHz): tProcessor %.3f, RF reference %.3f" % ( - self['fs_proc'], self['refclk_freq'])) - - lines.append("\n\t%d signal generator channels:" % (len(self['gens']))) - for iGen, gen in enumerate(self['gens']): - lines.append("\t%d:\t%s - tProc output %d, envelope memory %d samples" % - (iGen, gen['type'], gen['tproc_ch'], gen['maxlen'])) - lines.append("\t\tDAC tile %s, blk %s, %d-bit DDS, fabric=%.3f MHz, f_dds=%.3f MHz" % - (*gen['dac'], gen['b_dds'], gen['f_fabric'], gen['f_dds'])) - - if self['iqs']: - lines.append("\n\t%d constant-IQ outputs:" % (len(self['iqs']))) - for iIQ, iq in enumerate(self['iqs']): - lines.append("\t%d:\tDAC tile %s, blk %s, fs=%.3f MHz" % - (iIQ, *iq['dac'], iq['fs'])) - - lines.append("\n\t%d readout channels:" % (len(self['readouts']))) - for iReadout, readout in enumerate(self['readouts']): - if 'tproc_ctrl' in readout: - lines.append("\t%d:\t%s - controlled by tProc output %d" % (iReadout, readout['ro_type'], readout['tproc_ctrl'])) - else: - lines.append("\t%d:\t%s - controlled by PYNQ" % (iReadout, readout['ro_type'])) - lines.append("\t\tADC tile %s, blk %s, %d-bit DDS, fabric=%.3f MHz, fs=%.3f MHz" % - (*readout['adc'], readout['b_dds'], readout['f_fabric'], readout['f_dds'])) - lines.append("\t\tmaxlen %d (avg) %d (decimated), trigger bit %d, tProc input %d" % ( - readout['avg_maxlen'], readout['buf_maxlen'], readout['trigger_bit'], readout['tproc_ch'])) - - lines.append("\n\t%d DACs:" % (len(self['dacs']))) - for dac in self['dacs']: - tile, block = [int(c) for c in dac] - if self['board']=='ZCU111': - label = "DAC%d_T%d_CH%d or RF board output %d" % (tile + 228, tile, block, tile*4 + block) - elif self['board']=='ZCU216': - label = "%d_%d, on JHC%d" % (block, tile + 228, 1 + (block%2) + 2*(tile//2)) - elif self['board']=='RFSoC4x2': - label = {'00': 'DAC_B', '20': 'DAC_A'}[dac] - lines.append("\t\tDAC tile %d, blk %d is %s" % - (tile, block, label)) - - lines.append("\n\t%d ADCs:" % (len(self['adcs']))) - for adc in self['adcs']: - tile, block = [int(c) for c in adc] - if self['board']=='ZCU111': - rfbtype = "DC" if tile > 1 else "AC" - label = "ADC%d_T%d_CH%d or RF board %s input %d" % (tile + 224, tile, block, rfbtype, (tile%2)*2 + block) - elif self['board']=='ZCU216': - label = "%d_%d, on JHC%d" % (block, tile + 224, 5 + (block%2) + 2*(tile//2)) - elif self['board']=='RFSoC4x2': - label = {'00': 'ADC_D', '01': 'ADC_C', '20': 'ADC_B', '21': 'ADC_A'}[adc] - lines.append("\t\tADC tile %d, blk %d is %s" % - (tile, block, label)) - - tproc = self['tprocs'][0] - lines.append("\n\t%d digital output pins (tProc output %d):" % (len(tproc['output_pins']), tproc['trig_output'])) - for pin, name in tproc['output_pins']: - lines.append("\t%d:\t%s" % (pin, name)) - - lines.append("\n\ttProc %s: program memory %d words, data memory %d words" % - (tproc['type'], tproc['pmem_size'], tproc['dmem_size'])) - lines.append("\t\texternal start pin: %s" % (tproc['start_pin'])) - - return "\nQICK configuration:\n"+"\n".join(lines) - - def get_cfg(self): - """Return the QICK configuration dictionary. - This contains everything you need to recreate the QickConfig. - - Parameters - ---------- - - Returns - ------- - dict - configuration dictionary - - """ - return self._cfg - - def dump_cfg(self): - """Generate a JSON description of the QICK configuration. - You can save this string to a file and load it to recreate the QickConfig. - - Parameters - ---------- - - Returns - ------- - str - configuration in JSON format - - """ - return json.dumps(self._cfg, indent=4) - - def calc_fstep(self, dict1, dict2): - """Finds the least common multiple of the frequency steps of two channels (typically a generator and readout) - - Parameters - ---------- - dict1 : dict - config dict for one channel - dict2 : dict - config dict for the other channel - - Returns - ------- - float - frequency step common to the two channels - - """ - refclk = self['refclk_freq'] - # Calculate least common multiple of sampling frequencies. - - # clock multipliers from refclk to DAC/ADC - always integer - fsmult1 = round(dict1['f_dds']/refclk) - fsmult2 = round(dict2['f_dds']/refclk) - - # Calculate a common fstep_lcm, which is divisible by both step sizes of both channels. - # We should only use frequencies that are evenly divisible by fstep_lcm. - b_max = max(dict1['b_dds'], dict2['b_dds']) - mult_lcm = np.lcm(fsmult1 * 2**(b_max - dict1['b_dds']), - fsmult2 * 2**(b_max - dict2['b_dds'])) - return refclk * mult_lcm / 2**b_max - - def roundfreq(self, f, dict1, dict2): - """Round a frequency to the LCM of the frequency steps of two channels (typically a generator and readout). - - Parameters - ---------- - f : float or array - frequency (MHz) - dict1 : dict - config dict for one channel - dict2 : dict - config dict for the other channel - - Returns - ------- - float or array - rounded frequency (MHz) - - """ - fstep = self.calc_fstep(dict1, dict2) - return np.round(f/fstep) * fstep - - def freq2int(self, f, thisch, otherch=None): - """Converts frequency in MHz to integer value suitable for writing to a register. - This method works for both generators and readouts. - If a gen will be connected to an RO, the two channels must have exactly the same frequency, and you must supply the config for the other channel. - - Parameters - ---------- - f : float - frequency (MHz) - thisch : dict - config dict for the channel you're configuring - otherch : dict - config dict for a channel you will set to the same frequency - - Returns - ------- - int - Re-formatted frequency - - """ - if otherch is None: - f_round = f - else: - f_round = self.roundfreq(f, thisch, otherch) - k_i = np.round(f_round*(2**thisch['b_dds'])/thisch['f_dds']) - return np.int64(k_i) - - def int2freq(self, r, thisch): - """Converts register value to MHz. - This method works for both generators and readouts. - - Parameters - ---------- - r : int - register value - thisch : dict - config dict for the channel you're configuring - - Returns - ------- - float - Re-formatted frequency (MHz) - - """ - return r * thisch['f_dds'] / 2**thisch['b_dds'] - - def freq2reg(self, f, gen_ch=0, ro_ch=None): - """Converts frequency in MHz to tProc generator register value. - - Parameters - ---------- - f : float - frequency (MHz) - gen_ch : int - generator channel - ro_ch : int - readout channel (use None if you don't want to frequency-match to a readout) - - Returns - ------- - int - Re-formatted frequency - - """ - if ro_ch is None: - rocfg = None - else: - rocfg = self['readouts'][ro_ch] - gencfg = self['gens'][gen_ch] - if gencfg['type'] in ['axis_sg_int4_v1', 'axis_sg_mux4_v1', 'axis_sg_mux4_v2']: - # because of the interpolation filter, there is no output power in the higher nyquist zones - if abs(f)>gencfg['f_dds']/2: - raise RuntimeError("requested frequency %f is outside of the range [-fs/2, fs/2]"%(f)) - return self.freq2int(f, gencfg, rocfg) % 2**gencfg['b_dds'] - - def freq2reg_adc(self, f, ro_ch=0, gen_ch=None): - """Converts frequency in MHz to readout register value. - - Parameters - ---------- - f : float - frequency (MHz) - ro_ch : int - readout channel - gen_ch : int - generator channel (use None if you don't want to frequency-match to a generator) - - Returns - ------- - int - Re-formatted frequency - - """ - if gen_ch is None: - gencfg = None - else: - gencfg = self['gens'][gen_ch] - rocfg = self['readouts'][ro_ch] - return self.freq2int(f, rocfg, gencfg) % 2**rocfg['b_dds'] - - def reg2freq(self, r, gen_ch=0): - """Converts frequency from format readable by generator to MHz. - - Parameters - ---------- - r : int - frequency in generator format - gen_ch : int - generator channel - - Returns - ------- - float - Re-formatted frequency in MHz - - """ - return (r/2**self['gens'][gen_ch]['b_dds']) * self['gens'][gen_ch]['f_dds'] - - def reg2freq_adc(self, r, ro_ch=0): - """Converts frequency from format readable by readout to MHz. - - Parameters - ---------- - r : int - frequency in readout format - ro_ch : int - readout channel - - Returns - ------- - float - Re-formatted frequency in MHz - - """ - return (r/2**self['readouts'][ro_ch]['b_dds']) * self['readouts'][ro_ch]['f_dds'] - - def adcfreq(self, f, gen_ch=0, ro_ch=0): - """Takes a frequency and trims it to the closest DDS frequency valid for both channels. - - Parameters - ---------- - f : float - frequency (MHz) - gen_ch : int - generator channel - ro_ch : int - readout channel - - Returns - ------- - float - Re-formatted frequency - - """ - return self.roundfreq(f, self['gens'][gen_ch], self['readouts'][ro_ch]) - - def deg2reg(self, deg, gen_ch=0): - """Converts degrees into phase register values; numbers greater than 360 will effectively be wrapped. - - Parameters - ---------- - deg : float - Number of degrees - gen_ch : int - generator channel (index in 'gens' list) - - Returns - ------- - int - Re-formatted number of degrees - - """ - gen_type = self['gens'][gen_ch]['type'] - if gen_type == 'axis_sg_int4_v1': - b_phase = 16 - else: - b_phase = 32 - return int(deg*2**b_phase//360) % 2**b_phase - - def reg2deg(self, reg, gen_ch=0): - """Converts phase register values into degrees. - - Parameters - ---------- - reg : int - Re-formatted number of degrees - gen_ch : int - generator channel (index in 'gens' list) - - Returns - ------- - float - Number of degrees - - """ - gen_type = self['gens'][gen_ch]['type'] - if gen_type == 'axis_sg_int4_v1': - b_phase = 16 - else: - b_phase = 32 - return reg*360/2**b_phase - - def cycles2us(self, cycles, gen_ch=None, ro_ch=None): - """Converts clock cycles to microseconds. - Uses tProc clock frequency by default. - If gen_ch or ro_ch is specified, uses that generator/readout channel's fabric clock. - - Parameters - ---------- - cycles : int - Number of clock cycles - gen_ch : int - generator channel (index in 'gens' list) - ro_ch : int - readout channel (index in 'readouts' list) - - Returns - ------- - float - Number of microseconds - - """ - if gen_ch is not None and ro_ch is not None: - raise RuntimeError("can't specify both gen_ch and ro_ch!") - if gen_ch is not None: - fclk = self['gens'][gen_ch]['f_fabric'] - elif ro_ch is not None: - fclk = self['readouts'][ro_ch]['f_fabric'] - else: - fclk = self['fs_proc'] - return cycles/fclk - - def us2cycles(self, us, gen_ch=None, ro_ch=None): - """Converts microseconds to integer number of clock cycles. - Uses tProc clock frequency by default. - If gen_ch or ro_ch is specified, uses that generator/readout channel's fabric clock. - - Parameters - ---------- - us : float - Number of microseconds - gen_ch : int - generator channel (index in 'gens' list) - ro_ch : int - readout channel (index in 'readouts' list) - - Returns - ------- - int - Number of clock cycles - - """ - if gen_ch is not None and ro_ch is not None: - raise RuntimeError("can't specify both gen_ch and ro_ch!") - if gen_ch is not None: - fclk = self['gens'][gen_ch]['f_fabric'] - elif ro_ch is not None: - fclk = self['readouts'][ro_ch]['f_fabric'] - else: - fclk = self['fs_proc'] - return np.int64(np.round(obtain(us)*fclk)) - -class AbsRegisterManager(ABC): - """Generic class for managing registers that will be written to a tProc-controlled block (signal generator or readout). - """ - def __init__(self, prog, tproc_ch, ch_name): - self.prog = prog - # the tProc output channel controlled by this manager - self.tproc_ch = tproc_ch - # the name of this block (for messages) - self.ch_name = ch_name - # the register page used by this manager - self.rp = prog._ch_page_tproc(tproc_ch) - # default parameters - self.defaults = {} - # registers that are fully defined by the default parameters - self.default_regs = set() - # the registers to be used in the next "set" command - self.next_pulse = None - # registers values used in the last set_registers() call - self.last_set_regs = {} - - def set_reg(self, name, val, comment=None, defaults=False): - """Wrapper around regwi. - Looks up the register name and keeps track of whether the register already has a default value. - - Parameters - ---------- - name : str - Register name - val : int - Register value - comment : str - Comment to be printed in ASM output - defaults : bool - This is a default value, which doesn't need to be rewritten for every pulse - - """ - if defaults: - self.default_regs.add(name) - elif name in self.default_regs: - # this reg was already written, so we skip it this time - return - r = self.prog._sreg_tproc(self.tproc_ch, name) - if comment is None: comment = f'{name} = {val}' - self.prog.safe_regwi(self.rp, r, val, comment) - - def set_defaults(self, kwargs): - """Set default values for parameters. - This is called by QickProgram.set_default_registers(). - - Parameters - ---------- - kwargs : dict - Parameter values - - """ - if self.defaults: - # complain if the default parameter dict is not empty - raise RuntimeError("%s already has a set of default parameters"%(self.ch_name)) - self.defaults = kwargs - self.write_regs(kwargs, defaults=True) - - def set_registers(self, kwargs): - """Set pulse parameters. - This is called by QickProgram.set_pulse_registers(). - - Parameters - ---------- - kwargs : dict - Parameter values - - """ - self.last_set_regs = kwargs - if not self.defaults.keys().isdisjoint(kwargs): - raise RuntimeError("these params were set for {0} both in default_pulse_registers and set_pulse_registers: {1}".format(self.ch_name, self.defaults.keys() & kwargs.keys())) - merged = {**self.defaults, **kwargs} - # check the final param set for validity - self.check_params(merged) - self.write_regs(merged, defaults=False) - - @abstractmethod - def check_params(self, params): - ... - - @abstractmethod - def write_regs(self, params, defaults): - ... - -class DummyIp: - """Stores the configuration constants for a firmware IP block. - """ - def __init__(self, iptype, fullpath): - # config dictionary for QickConfig - self._cfg = {'type': iptype, - 'fullpath': fullpath} - - @property - def cfg(self): - return self._cfg - - def __getitem__(self, key): - return self._cfg[key] - - -class ReadoutManager(AbsRegisterManager): - """Manages the frequency and mode registers for a tProc-controlled readout channel. - """ - PARAMS_REQUIRED = ['freq', 'length'] - PARAMS_OPTIONAL = ['phrst', 'mode', 'outsel'] - - def __init__(self, prog, ro_ch): - self.rocfg = prog.soccfg['readouts'][ro_ch] - tproc_ch = self.rocfg['tproc_ctrl'] - super().__init__(prog, tproc_ch, "readout %d"%(ro_ch)) - - def check_params(self, params): - """Check whether the parameters defined for a pulse are supported and sufficient for this generator and pulse type. - Raise an exception if there is a problem. - - Parameters - ---------- - params : dict - Parameter values - - """ - required = set(self.PARAMS_REQUIRED) - allowed = required | set(self.PARAMS_OPTIONAL) - defined = params.keys() - if required - defined: - raise RuntimeError("missing required pulse parameter(s)", required - defined) - if defined - allowed: - raise RuntimeError("unsupported pulse parameter(s)", defined - allowed) - - def write_regs(self, params, defaults): - if 'freq' in params: - self.set_reg('freq', params['freq'], defaults=defaults) - if not defaults: - self.next_pulse = {} - self.next_pulse['rp'] = self.rp - self.next_pulse['regs'] = [] - - # these mode bits could be defined, or left as None - phrst, mode, outsel = [params.get(x) for x in ['phrst', 'mode', 'outsel']] - mc = self.get_mode_code(phrst=phrst, mode=mode, outsel=outsel, length=params['length']) - self.set_reg('mode', mc, f'mode | outsel = 0b{mc//2**16:>05b} | length = {mc % 2**16} ') - self.next_pulse['regs'].append([self.prog._sreg_tproc(self.tproc_ch,x) for x in ['freq', '0', 'mode', '0', '0']]) - - def get_mode_code(self, length, outsel=None, mode=None, phrst=None): - """Creates mode code for the mode register in the set command, by setting flags and adding the pulse length. - - Parameters - ---------- - length : int - The number of ADC fabric cycles in the pulse - - outsel : str - Selects the output source. The output is complex. Tables define envelopes for I and Q. - The default is "product". - - * If "product", the output is the product of table and DDS. - - * If "dds", the output is the DDS only. - - * If "input", the output is from the table for the real part, and zeros for the imaginary part. - - * If "zero", the output is always zero. - - mode : str - Selects whether the output is "oneshot" or "periodic". The default is "oneshot". - - phrst : int - If 1, it resets the phase coherent accumulator. The default is 0. - - Returns - ------- - int - Compiled mode code in binary - - """ - if length >= 2**16 or length < 3: - raise RuntimeError("Pulse length of %d is out of range (exceeds 16 bits, or less than 3) - use multiple pulses, or zero-pad the waveform" % (length)) - if outsel is None: outsel = "product" - if mode is None: mode = "oneshot" - if phrst is None: phrst = 0 - - outsel_reg = {"product": 0, "dds": 1, "input": 2, "zero": 3}[outsel] - mode_reg = {"oneshot": 0, "periodic": 1}[mode] - mc = phrst*0b01000+mode_reg*0b00100+outsel_reg - return mc << 16 | np.uint16(length) - - -class AbsGenManager(AbsRegisterManager): - """Manages the envelope and pulse information for a signal generator channel. - """ - PARAMS_REQUIRED = {} - PARAMS_OPTIONAL = {} - - def __init__(self, prog, gen_ch): - self.gencfg = prog.soccfg['gens'][gen_ch] - tproc_ch = self.gencfg['tproc_ch'] - super().__init__(prog, tproc_ch, "generator %d"%(gen_ch)) - self.samps_per_clk = self.gencfg['samps_per_clk'] - - # dictionary of defined pulse envelopes - self.pulses = prog.pulses[gen_ch] - # type and max absolute value for envelopes - self.env_dtype = np.int16 - - self.addr = 0 - - def check_params(self, params): - """Check whether the parameters defined for a pulse are supported and sufficient for this generator and pulse type. - Raise an exception if there is a problem. - - Parameters - ---------- - params : dict - Parameter values - - """ - style = params['style'] - required = set(self.PARAMS_REQUIRED[style]) - allowed = required | set(self.PARAMS_OPTIONAL[style]) - defined = params.keys() - if required - defined: - raise RuntimeError("missing required pulse parameter(s)", required - defined) - if defined - allowed: - raise RuntimeError("unsupported pulse parameter(s)", defined - allowed) - - def add_pulse(self, name, idata, qdata): - """Add a waveform to the list of envelope waveforms available for this channel. - The I and Q arrays must be of equal length, and the length must be divisible by the samples-per-clock of this generator. - - Parameters - ---------- - name : str - Name for this waveform - idata : array - I values for this waveform - qdata : array - Q values for this waveform - - """ - length = [len(d) for d in [idata, qdata] if d is not None] - if len(length)==0: - raise RuntimeError("Error: no data argument was supplied") - # if both arrays were defined, they must be the same length - if len(length)>1 and length[0]!=length[1]: - raise RuntimeError("Error: I and Q pulse lengths must be equal") - length = length[0] - - if (length % self.samps_per_clk) != 0: - raise RuntimeError("Error: pulse lengths must be an integer multiple of %d"%(self.samps_per_clk)) - data = np.zeros((length, 2), dtype=self.env_dtype) - - for i, d in enumerate([idata, qdata]): - if d is not None: - # range check - if np.max(np.abs(d)) > self.gencfg['maxv']: - raise ValueError("max abs val of envelope (%d) exceeds limit (%d)" % (np.max(np.abs(d)), self.gencfg['maxv'])) - # copy data - data[:,i] = np.round(d) - - self.pulses[name] = {"data": data, "addr": self.addr} - self.addr += length - - def get_mode_code(self, length, mode=None, outsel=None, stdysel=None, phrst=None): - """Creates mode code for the mode register in the set command, by setting flags and adding the pulse length. - - Parameters - ---------- - length : int - The number of DAC fabric cycles in the pulse - mode : str - Selects whether the output is "oneshot" or "periodic". The default is "oneshot". - outsel : str - Selects the output source. The output is complex. Tables define envelopes for I and Q. - The default is "product". - - * If "product", the output is the product of table and DDS. - - * If "dds", the output is the DDS only. - - * If "input", the output is from the table for the real part, and zeros for the imaginary part. - - * If "zero", the output is always zero. - - stdysel : str - Selects what value is output continuously by the signal generator after the generation of a pulse. - The default is "zero". - - * If "last", it is the last calculated sample of the pulse. - - * If "zero", it is a zero value. - - phrst : int - If 1, it resets the phase coherent accumulator. The default is 0. - - Returns - ------- - int - Compiled mode code in binary - - """ - if mode is None: mode = "oneshot" - if outsel is None: outsel = "product" - if stdysel is None: stdysel = "zero" - if phrst is None: phrst = 0 - if length >= 2**16 or length < 3: - raise RuntimeError("Pulse length of %d is out of range (exceeds 16 bits, or less than 3) - use multiple pulses, or zero-pad the waveform" % (length)) - stdysel_reg = {"last": 0, "zero": 1}[stdysel] - mode_reg = {"oneshot": 0, "periodic": 1}[mode] - outsel_reg = {"product": 0, "dds": 1, "input": 2, "zero": 3}[outsel] - mc = phrst*0b10000+stdysel_reg*0b01000+mode_reg*0b00100+outsel_reg - return mc << 16 | np.uint16(length) - -class FullSpeedGenManager(AbsGenManager): - """Manager for the full-speed (non-interpolated, non-muxed) signal generators. - """ - PARAMS_REQUIRED = {'const': ['style', 'freq', 'phase', 'gain', 'length'], - 'arb': ['style', 'freq', 'phase', 'gain', 'waveform'], - 'flat_top': ['style', 'freq', 'phase', 'gain', 'length', 'waveform']} - PARAMS_OPTIONAL = {'const': ['phrst', 'stdysel', 'mode'], - 'arb': ['phrst', 'stdysel', 'mode', 'outsel'], - 'flat_top': ['phrst', 'stdysel']} - - def write_regs(self, params, defaults): - """Write whichever pulse registers are fully determined by the defined parameters. - - The following pulse styles are supported: - - * const: A constant (rectangular) pulse. - There is no outsel setting for this pulse style; "dds" is always used. - - * arb: An arbitrary-envelope pulse. - - * flat_top: A flattop pulse with arbitrary ramps. - The waveform is played in three segments: ramp up, flat, and ramp down. - To use these pulses one should use add_pulse to add the ramp waveform which should go from 0 to maxamp and back down to zero with the up and down having the same length, the first half will be used as the ramp up and the second half will be used as the ramp down. - - If the waveform is not of even length, the middle sample will be skipped. - It's recommended to use an even-length waveform with flat_top. - - There is no outsel setting for flat_top; the ramps always use "product" and the flat segment always uses "dds". - There is no mode setting; it is always "oneshot". - - Parameters - ---------- - params : dict - Pulse parameters - defaults : - These are default values, which don't need to be rewritten for every pulse - - """ - for parname in ['freq', 'phase', 'gain']: - if parname in params: - self.set_reg(parname, params[parname], defaults=defaults) - if 'waveform' in params: - pinfo = self.pulses[params['waveform']] - wfm_length = pinfo['data'].shape[0] // self.samps_per_clk - addr = pinfo['addr'] // self.samps_per_clk - self.set_reg('addr', addr, defaults=defaults) - if not defaults: - style = params['style'] - # these mode bits could be defined, or left as None - phrst, stdysel, mode, outsel = [params.get(x) for x in ['phrst', 'stdysel', 'mode', 'outsel']] - - self.next_pulse = {} - self.next_pulse['rp'] = self.rp - self.next_pulse['regs'] = [] - if style=='const': - mc = self.get_mode_code(phrst=phrst, stdysel=stdysel, mode=mode, outsel="dds", length=params['length']) - self.set_reg('mode', mc, f'phrst| stdysel | mode | | outsel = 0b{mc//2**16:>05b} | length = {mc % 2**16} ') - self.next_pulse['regs'].append([self.prog._sreg_tproc(self.tproc_ch,x) for x in ['freq', 'phase', '0', 'gain', 'mode']]) - self.next_pulse['length'] = params['length'] - elif style=='arb': - mc = self.get_mode_code(phrst=phrst, stdysel=stdysel, mode=mode, outsel=outsel, length=wfm_length) - self.set_reg('mode', mc, f'phrst| stdysel | mode | | outsel = 0b{mc//2**16:>05b} | length = {mc % 2**16} ') - self.next_pulse['regs'].append([self.prog._sreg_tproc(self.tproc_ch,x) for x in ['freq', 'phase', 'addr', 'gain', 'mode']]) - self.next_pulse['length'] = wfm_length - elif style=='flat_top': - # address for ramp-down - self.set_reg('addr2', addr+(wfm_length+1)//2) - # gain for flat segment - self.set_reg('gain2', params['gain']//2) - # mode for ramp up - mc = self.get_mode_code(phrst=phrst, stdysel=stdysel, mode='oneshot', outsel='product', length=wfm_length//2) - self.set_reg('mode2', mc, f'phrst| stdysel | mode | | outsel = 0b{mc//2**16:>05b} | length = {mc % 2**16} ') - # mode for flat segment - mc = self.get_mode_code(phrst=False, stdysel=stdysel, mode='oneshot', outsel='dds', length=params['length']) - self.set_reg('mode', mc, f'phrst| stdysel | mode | | outsel = 0b{mc//2**16:>05b} | length = {mc % 2**16} ') - # mode for ramp down - mc = self.get_mode_code(phrst=False, stdysel=stdysel, mode='oneshot', outsel='product', length=wfm_length//2) - self.set_reg('mode3', mc, f'phrst| stdysel | mode | | outsel = 0b{mc//2**16:>05b} | length = {mc % 2**16} ') - - self.next_pulse['regs'].append([self.prog._sreg_tproc(self.tproc_ch,x) for x in ['freq', 'phase', 'addr', 'gain', 'mode2']]) - self.next_pulse['regs'].append([self.prog._sreg_tproc(self.tproc_ch,x) for x in ['freq', 'phase', '0', 'gain2', 'mode']]) - self.next_pulse['regs'].append([self.prog._sreg_tproc(self.tproc_ch,x) for x in ['freq', 'phase', 'addr2', 'gain', 'mode3']]) - self.next_pulse['length'] = (wfm_length//2)*2 + params['length'] - - -class InterpolatedGenManager(AbsGenManager): - """Manager for the interpolated signal generators. - """ - PARAMS_REQUIRED = {'const': ['style', 'freq', 'phase', 'gain', 'length'], - 'arb': ['style', 'freq', 'phase', 'gain', 'waveform'], - 'flat_top': ['style', 'freq', 'phase', 'gain', 'length', 'waveform']} - PARAMS_OPTIONAL = {'const': ['phrst', 'stdysel', 'mode'], - 'arb': ['phrst', 'stdysel', 'mode', 'outsel'], - 'flat_top': ['phrst', 'stdysel']} - - def write_regs(self, params, defaults): - """Write whichever pulse registers are fully determined by the defined parameters. - - The following pulse styles are supported: - - * const: A constant (rectangular) pulse. - There is no outsel setting for this pulse style; "dds" is always used. - - * arb: An arbitrary-envelope pulse. - - * flat_top: A flattop pulse with arbitrary ramps. - The waveform is played in three segments: ramp up, flat, and ramp down. - To use these pulses one should use add_pulse to add the ramp waveform which should go from 0 to maxamp and back down to zero with the up and down having the same length, the first half will be used as the ramp up and the second half will be used as the ramp down. - - If the waveform is not of even length, the middle sample will be skipped. - It's recommended to use an even-length waveform with flat_top. - - There is no outsel setting for flat_top; the ramps always use "product" and the flat segment always uses "dds". - There is no mode setting; it is always "oneshot". - - Parameters - ---------- - params : dict - Pulse parameters - defaults : - These are default values, which don't need to be rewritten for every pulse - - """ - addr = 0 - if 'waveform' in params: - pinfo = self.pulses[params['waveform']] - wfm_length = pinfo['data'].shape[0] // self.samps_per_clk - addr = pinfo['addr'] // self.samps_per_clk - if 'phase' in params and 'freq' in params: - phase, freq = [params[x] for x in ['phase', 'freq']] - self.set_reg('freq', (phase << 16) | freq, f'phase = {phase} | freq = {freq}', defaults=defaults) - if 'gain' in params and ('waveform' in params or params.get('style')=='const'): - gain = params['gain'] - self.set_reg('addr', (gain << 16) | addr, f'gain = {gain} | addr = {addr}', defaults=defaults) - if not defaults: - style = params['style'] - # these mode bits could be defined, or left as None - phrst, stdysel, mode, outsel = [params.get(x) for x in ['phrst', 'stdysel', 'mode', 'outsel']] - - self.next_pulse = {} - self.next_pulse['rp'] = self.rp - self.next_pulse['regs'] = [] - if style=='const': - mc = self.get_mode_code(phrst=phrst, stdysel=stdysel, mode=mode, outsel="dds", length=params['length']) - self.set_reg('mode', mc, f'stdysel | mode | outsel = 0b{mc//2**16:>05b} | length = {mc % 2**16} ') - self.next_pulse['regs'].append([self.prog._sreg_tproc(self.tproc_ch,x) for x in ['freq', 'addr', 'mode', '0', '0']]) - self.next_pulse['length'] = params['length'] - elif style=='arb': - mc = self.get_mode_code(phrst=phrst, stdysel=stdysel, mode=mode, outsel=outsel, length=wfm_length) - self.set_reg('mode', mc, f'stdysel | mode | outsel = 0b{mc//2**16:>05b} | length = {mc % 2**16} ') - self.next_pulse['regs'].append([self.prog._sreg_tproc(self.tproc_ch,x) for x in ['freq', 'addr', 'mode', '0', '0']]) - self.next_pulse['length'] = wfm_length - elif style=='flat_top': - maxv_scale = self.gencfg['maxv_scale'] - gain, length = [params[x] for x in ['gain', 'length']] - # mode for flat segment - mc = self.get_mode_code(phrst=phrst, stdysel=stdysel, mode="oneshot", outsel="dds", length=params['length']) - self.set_reg('mode', mc, f'stdysel | mode | outsel = 0b{mc//2**16:>05b} | length = {mc % 2**16} ') - # mode for ramps - mc = self.get_mode_code(phrst=phrst, stdysel=stdysel, mode="oneshot", outsel="product", length=wfm_length//2) - self.set_reg('mode2', mc, f'stdysel | mode | outsel = 0b{mc//2**16:>05b} | length = {mc % 2**16} ') - - # gain+addr for ramp-up - self.set_reg('addr', (gain << 16) | addr, f'gain = {gain} | addr = {addr}') - # gain+addr for flat - self.set_reg('gain', (int(gain*maxv_scale/2) << 16), f'gain = {gain} | addr = {addr}') - # gain+addr for ramp-down - self.set_reg('addr2', (gain << 16) | addr+(wfm_length+1)//2, f'gain = {gain} | addr = {addr}') - - self.next_pulse['regs'].append([self.prog._sreg_tproc(self.tproc_ch,x) for x in ['freq', 'addr', 'mode2', '0', '0']]) - self.next_pulse['regs'].append([self.prog._sreg_tproc(self.tproc_ch,x) for x in ['freq', 'gain', 'mode', '0', '0']]) - self.next_pulse['regs'].append([self.prog._sreg_tproc(self.tproc_ch,x) for x in ['freq', 'addr2', 'mode2', '0', '0']]) - # workaround for FIR bug: we play a zero-gain DDS pulse (length equal to the flat segment) after the ramp-down, which brings the FIR to zero - self.next_pulse['regs'].append((0, 0, 'mode', 0, 0)) - # set the pulse duration (including the extra duration for the FIR workaround) - self.next_pulse['length'] = (wfm_length//2)*2 + 2*params['length'] - -class MultiplexedGenManager(AbsGenManager): - """Manager for the muxed signal generators. - """ - PARAMS_REQUIRED = {'const': ['style', 'mask', 'length']} - PARAMS_OPTIONAL = {'const': []} - - def write_regs(self, params, defaults): - """Write whichever pulse registers are fully determined by the defined parameters. - - Only the "const" pulse style, with the "mask" and "length" parameters, is supported. - The frequency and gain are set at program initialization. - - Parameters - ---------- - params : dict - Pulse parameters - defaults : - These are default values, which don't need to be rewritten for every pulse - - """ - if 'length' in params: - if params['length'] >= 2**32 or params['length'] < 3: - raise RuntimeError("Pulse length of %d is out of range (exceeds 32 bits, or less than 3) - use multiple pulses" % (params['length'])) - self.set_reg('freq', params['length'], defaults=defaults) - if 'mask' in params: - val_mask = 0 - mask = params['mask'] - for maskch in mask: - if maskch not in range(4): - raise RuntimeError("invalid mask specification") - val_mask |= (1 << maskch) - self.set_reg('phase', val_mask, f'mask = {mask}', defaults=defaults) - if not defaults: - style = params['style'] - - self.next_pulse = {} - self.next_pulse['rp'] = self.rp - self.next_pulse['regs'] = [] - self.next_pulse['regs'].append([self.prog._sreg_tproc(self.tproc_ch,x) for x in ['freq', 'phase', '0', '0', '0']]) - self.next_pulse['length'] = params['length'] - -class AbsQickProgram: - def __init__(self, soccfg): - """ - Constructor method - """ - self.soccfg = soccfg - - # Pulse envelopes. - self.pulses = [{} for ch in soccfg['gens']] - # readout channels to configure before running the program - self.ro_chs = OrderedDict() - # signal generator channels to configure before running the program - self.gen_chs = OrderedDict() - - # Timestamps, for keeping track of pulse and readout end times. - self._gen_ts = [0]*len(soccfg['gens']) - self._ro_ts = [0]*len(soccfg['readouts']) - - def config_all(self, soc, load_pulses=True): - """ - Load the waveform memory, gens, ROs, and program memory as specified for this program. - The decimated+accumulated buffers are not configured, since those should be re-configured for each acquisition. - """ - # Load the pulses from the program into the soc - if load_pulses: - self.load_pulses(soc) - - # Configure signal generators - self.config_gens(soc) - - # Configure the readout down converters - self.config_readouts(soc) - - def declare_readout(self, ch, length, freq=None, sel='product', gen_ch=None): - """Add a channel to the program's list of readouts. - - Parameters - ---------- - ch : int - readout channel number (index in 'readouts' list) - freq : float - downconverting frequency (MHz) - length : int - readout length (number of samples) - sel : str - output select ('product', 'dds', 'input') - gen_ch : int - generator channel (use None if you don't want the downconversion frequency to be rounded to a valid DAC frequency or be offset by the DAC mixer frequency) - """ - ro_cfg = self.soccfg['readouts'][ch] - if 'tproc_ctrl' not in ro_cfg: # readout is controlled by PYNQ - if freq is None: - raise RuntimeError("frequency must be declared for a PYNQ-controlled readout") - # this number comes from the fact that the ADC is 12 bit + 3 bits from decimation = 15 bit - # and the sum buffer values are 32 bit signed - if length > 2**(31-15): - logger.warning(f'With the given readout length there is a possibility that the sum buffer will overflow giving invalid results.') - cfg = { - 'freq': freq, - 'length': length, - 'sel': sel, - 'gen_ch': gen_ch - } - else: # readout is controlled by tProc - if (freq is not None) or sel!='product' or (gen_ch is not None): - raise RuntimeError("this is a tProc-controlled readout - freq/sel parameters are set using tProc instructions") - cfg = { - 'length': length - } - self.ro_chs[ch] = cfg - - def config_readouts(self, soc): - """Configure the readout channels specified in this program. - This is usually called as part of an acquire() method. - - Parameters - ---------- - soc : QickSoc - the QickSoc that will execute this program - - """ - soc.init_readouts() - for ch, cfg in self.ro_chs.items(): - if 'tproc_ctrl' not in self.soccfg['readouts'][ch]: - soc.configure_readout(ch, output=cfg['sel'], frequency=cfg['freq'], gen_ch=cfg['gen_ch']) - - def config_bufs(self, soc, enable_avg=True, enable_buf=True): - """Configure the readout buffers specified in this program. - This is usually called as part of an acquire() method. - - Parameters - ---------- - soc : QickSoc - the QickSoc that will execute this program - enable_avg : bool - enable the accumulated (averaging) buffer - enable_buf : bool - enable the decimated (waveform) buffer - - """ - for ch, cfg in self.ro_chs.items(): - if enable_avg: - soc.config_avg(ch, address=0, length=cfg['length'], enable=True) - if enable_buf: - soc.config_buf(ch, address=0, length=cfg['length'], enable=True) - - def declare_gen(self, ch, nqz=1, mixer_freq=0, mux_freqs=None, mux_gains=None, ro_ch=None): - """Add a channel to the program's list of signal generators. - - If this is a generator with a mixer (interpolated or muxed generator), you may define a mixer frequency. - - If this is a muxed generator, the mux_freqs and mux_gains lists must be long enough to define all the tones you will play. - (in other words, if your mask list ever enables tone 2 you must define at least 3 freqs+gains) - - Parameters - ---------- - ch : int - generator channel (index in 'gens' list) - nqz : int, optional - Nyquist zone (must be 1 or 2). - Setting the NQZ to 2 increases output power in the 2nd/3rd Nyquist zones. - mixer_freq : float, optional - Mixer frequency (in MHz) - mux_freqs : list of float, optional - Tone frequencies for the muxed generator (in MHz). - Positive and negative values are allowed. - mux_gains : list of float, optional - Tone amplitudes for the muxed generator (in range -1 to 1). - ro_ch : int, optional - readout channel (use None if you don't want mixer and mux freqs to be rounded to a valid ADC frequency) - """ - cfg = { - 'nqz': nqz, - 'mixer_freq': mixer_freq, - 'mux_freqs': mux_freqs, - 'mux_gains': mux_gains, - 'ro_ch': ro_ch - } - self.gen_chs[ch] = cfg - - def config_gens(self, soc): - """Configure the signal generators specified in this program. - This is usually called as part of an acquire() method. - - Parameters - ---------- - soc : QickSoc - the QickSoc that will execute this program - - """ - for ch, cfg in self.gen_chs.items(): - soc.set_nyquist(ch, cfg['nqz']) - soc.set_mixer_freq(ch, cfg['mixer_freq'], cfg['ro_ch']) - if cfg['mux_freqs'] is not None: - soc.set_mux_freqs(ch, freqs=cfg['mux_freqs'], gains=cfg['mux_gains']) - - def add_pulse(self, ch, name, idata=None, qdata=None): - """Adds a waveform to the waveform library within the program. - - Parameters - ---------- - ch : int - generator channel (index in 'gens' list) - name : str - Name of the pulse - idata : array - I data Numpy array - qdata : array - Q data Numpy array - - """ - self._gen_mgrs[ch].add_pulse(name, idata, qdata) - - def add_gauss(self, ch, name, sigma, length, maxv=None): - """Adds a Gaussian pulse to the waveform library. - The pulse will peak at length/2. - - Parameters - ---------- - ch : int - generator channel (index in 'gens' list) - name : str - Name of the pulse - sigma : float - Standard deviation of the Gaussian (in units of fabric clocks) - length : int - Total pulse length (in units of fabric clocks) - maxv : float - Value at the peak (if None, the max value for this generator will be used) - - """ - gencfg = self.soccfg['gens'][ch] - if maxv is None: maxv = gencfg['maxv']*gencfg['maxv_scale'] - samps_per_clk = gencfg['samps_per_clk'] - - length = np.round(length) * samps_per_clk - sigma *= samps_per_clk - - self.add_pulse(ch, name, idata=gauss(mu=length/2-0.5, si=sigma, length=length, maxv=maxv)) - - - def add_DRAG(self, ch, name, sigma, length, delta, alpha=0.5, maxv=None): - """Adds a DRAG pulse to the waveform library. - The pulse will peak at length/2. - - Parameters - ---------- - ch : int - generator channel (index in 'gens' list) - name : str - Name of the pulse - sigma : float - Standard deviation of the Gaussian (in units of fabric clocks) - length : int - Total pulse length (in units of fabric clocks) - maxv : float - Value at the peak (if None, the max value for this generator will be used) - delta : float - anharmonicity of the qubit (units of MHz) - alpha : float - alpha parameter of DRAG (order-1 scale factor) - - Returns - ------- - - """ - gencfg = self.soccfg['gens'][ch] - if maxv is None: maxv = gencfg['maxv']*gencfg['maxv_scale'] - samps_per_clk = gencfg['samps_per_clk'] - f_fabric = gencfg['f_fabric'] - - delta /= samps_per_clk*f_fabric - - length = np.round(length) * samps_per_clk - sigma *= samps_per_clk - - idata, qdata = DRAG(mu=length/2-0.5, si=sigma, length=length, maxv=maxv, alpha=alpha, delta=delta) - - self.add_pulse(ch, name, idata=idata, qdata=qdata) - - def add_triangle(self, ch, name, length, maxv=None): - """Adds a triangle pulse to the waveform library. - The pulse will peak at length/2. - - Parameters - ---------- - ch : int - generator channel (index in 'gens' list) - name : str - Name of the pulse - length : int - Total pulse length (in units of fabric clocks) - maxv : float - Value at the peak (if None, the max value for this generator will be used) - - """ - gencfg = self.soccfg['gens'][ch] - if maxv is None: maxv = gencfg['maxv']*gencfg['maxv_scale'] - samps_per_clk = gencfg['samps_per_clk'] - - length = np.round(length) * samps_per_clk - - self.add_pulse(ch, name, idata=triang(length=length, maxv=maxv)) - - def load_pulses(self, soc): - """Loads pulses that were added using add_pulse into the SoC's signal generator memories. - - Parameters - ---------- - soc : Qick object - Qick object - - """ - for iCh, pulses in enumerate(self.pulses): - for name, pulse in pulses.items(): - soc.load_pulse_data(iCh, - data=pulse['data'], - addr=pulse['addr']) - - def reset_timestamps(self): - self._gen_ts = [0]*len(self._gen_ts) - self._ro_ts = [0]*len(self._ro_ts) - - def get_timestamp(self, gen_ch=None, ro_ch=None): - if gen_ch is not None and ro_ch is not None: - raise RuntimeError("can't specify both gen_ch and ro_ch!") - if gen_ch is not None: - return self._gen_ts[gen_ch] - elif ro_ch is not None: - return self._ro_ts[ro_ch] - else: - raise RuntimeError("must specify gen_ch or ro_ch!") - - def set_timestamp(self, val, gen_ch=None, ro_ch=None): - if gen_ch is not None and ro_ch is not None: - raise RuntimeError("can't specify both gen_ch and ro_ch!") - if gen_ch is not None: - self._gen_ts[gen_ch] = val - elif ro_ch is not None: - self._ro_ts[ro_ch] = val - else: - raise RuntimeError("must specify gen_ch or ro_ch!") - - def get_max_timestamp(self, gens=True, ros=True): - timestamps = [] - if gens: timestamps += self._gen_ts - if ros: timestamps += self._ro_ts - return max(timestamps) - - -class QickProgram(AbsQickProgram): - """QickProgram is a Python representation of the QickSoc processor assembly program. It can be used to compile simple assembly programs and also contains macros to help make it easy to configure and schedule pulses.""" - # Instruction set for the tproc describing how to automatically generate methods for these instructions - instructions = {'pushi': {'type': "I", 'bin': 0b00010000, 'fmt': ((0, 53), (1, 41), (2, 36), (3, 0)), 'repr': "{0}, ${1}, ${2}, {3}"}, - 'popi': {'type': "I", 'bin': 0b00010001, 'fmt': ((0, 53), (1, 41)), 'repr': "{0}, ${1}"}, - 'mathi': {'type': "I", 'bin': 0b00010010, 'fmt': ((0, 53), (1, 41), (2, 36), (3, 46), (4, 0)), 'repr': "{0}, ${1}, ${2} {3} {4}"}, - 'seti': {'type': "I", 'bin': 0b00010011, 'fmt': ((1, 53), (0, 50), (2, 36), (3, 0)), 'repr': "{0}, {1}, ${2}, {3}"}, - 'synci': {'type': "I", 'bin': 0b00010100, 'fmt': ((0, 0),), 'repr': "{0}"}, - 'waiti': {'type': "I", 'bin': 0b00010101, 'fmt': ((0, 50), (1, 0)), 'repr': "{0}, {1}"}, - 'bitwi': {'type': "I", 'bin': 0b00010110, 'fmt': ((0, 53), (3, 46), (1, 41), (2, 36), (4, 0)), 'repr': "{0}, ${1}, ${2} {3} {4}"}, - 'memri': {'type': "I", 'bin': 0b00010111, 'fmt': ((0, 53), (1, 41), (2, 0)), 'repr': "{0}, ${1}, {2}"}, - 'memwi': {'type': "I", 'bin': 0b00011000, 'fmt': ((0, 53), (1, 31), (2, 0)), 'repr': "{0}, ${1}, {2}"}, - 'regwi': {'type': "I", 'bin': 0b00011001, 'fmt': ((0, 53), (1, 41), (2, 0)), 'repr': "{0}, ${1}, {2}"}, - 'setbi': {'type': "I", 'bin': 0b00011010, 'fmt': ((0, 53), (1, 41), (2, 0)), 'repr': "{0}, ${1}, {2}"}, - - 'loopnz': {'type': "J1", 'bin': 0b00110000, 'fmt': ((0, 53), (1, 41), (1, 36), (2, 0)), 'repr': "{0}, ${1}, @{2}"}, - 'end': {'type': "J1", 'bin': 0b00111111, 'fmt': (), 'repr': ""}, - - 'condj': {'type': "J2", 'bin': 0b00110001, 'fmt': ((0, 53), (2, 46), (1, 36), (3, 31), (4, 0)), 'repr': "{0}, ${1}, {2}, ${3}, @{4}"}, - - 'math': {'type': "R", 'bin': 0b01010000, 'fmt': ((0, 53), (3, 46), (1, 41), (2, 36), (4, 31)), 'repr': "{0}, ${1}, ${2} {3} ${4}"}, - 'set': {'type': "R", 'bin': 0b01010001, 'fmt': ((1, 53), (0, 50), (2, 36), (7, 31), (3, 26), (4, 21), (5, 16), (6, 11)), 'repr': "{0}, {1}, ${2}, ${3}, ${4}, ${5}, ${6}, ${7}"}, - 'sync': {'type': "R", 'bin': 0b01010010, 'fmt': ((0, 53), (1, 31)), 'repr': "{0}, ${1}"}, - 'read': {'type': "R", 'bin': 0b01010011, 'fmt': ((1, 53), (0, 50), (2, 46), (3, 41)), 'repr': "{0}, {1}, {2} ${3}"}, - 'wait': {'type': "R", 'bin': 0b01010100, 'fmt': ((1, 53), (0, 50), (2, 31)), 'repr': "{0}, {1}, ${2}"}, - 'bitw': {'type': "R", 'bin': 0b01010101, 'fmt': ((0, 53), (1, 41), (2, 36), (3, 46), (4, 31)), 'repr': "{0}, ${1}, ${2} {3} ${4}"}, - 'memr': {'type': "R", 'bin': 0b01010110, 'fmt': ((0, 53), (1, 41), (2, 36)), 'repr': "{0}, ${1}, ${2}"}, - 'memw': {'type': "R", 'bin': 0b01010111, 'fmt': ((0, 53), (2, 36), (1, 31)), 'repr': "{0}, ${1}, ${2}"}, - 'setb': {'type': "R", 'bin': 0b01011000, 'fmt': ((0, 53), (2, 36), (1, 31)), 'repr': "{0}, ${1}, ${2}"}, - 'comment': {'fmt': ()} - } - - # op codes for math and bitwise operations - op_codes = {">": 0b0000, ">=": 0b0001, "<": 0b0010, "<=": 0b0011, "==": 0b0100, "!=": 0b0101, - "+": 0b1000, "-": 0b1001, "*": 0b1010, - "&": 0b0000, "|": 0b0001, "^": 0b0010, "~": 0b0011, "<<": 0b0100, ">>": 0b0101, - "upper": 0b1010, "lower": 0b0101 - } - - # To make it easier to configure pulses these special registers are reserved for each channel's pulse configuration. - # In each page, register 0 is hard-wired with the value 0. - # In page 0 we reserve the following additional registers: - # 13, 14 and 15 for loop counters, 31 for the trigger time. - # Pairs of channels share a register page. - # The flat_top pulse uses some extra registers. - pulse_registers = ["freq", "phase", "addr", "gain", "mode", "t", "addr2", "gain2", "mode2", "mode3"] - - soccfg_methods = ['freq2reg', 'freq2reg_adc', - 'reg2freq', 'reg2freq_adc', - 'cycles2us', 'us2cycles', - 'deg2reg', 'reg2deg'] - - # Attributes to dump when saving the program to JSON. - dump_keys = ['prog_list', 'pulses', 'ro_chs', 'gen_chs', 'counter_addr', 'reps', 'expts', 'rounds', 'shot_angle', 'shot_threshold'] - - gentypes = {'axis_signal_gen_v4': FullSpeedGenManager, - 'axis_signal_gen_v5': FullSpeedGenManager, - 'axis_signal_gen_v6': FullSpeedGenManager, - 'axis_sg_int4_v1': InterpolatedGenManager, - 'axis_sg_mux4_v1': MultiplexedGenManager, - 'axis_sg_mux4_v2': MultiplexedGenManager} - - def __init__(self, soccfg): - """ - Constructor method - """ - super().__init__(soccfg) - - # List of commands. This may include comments. - self.prog_list = [] - - # Label to apply to the next instruction. - self._label_next = None - - # Address of the rep counter in the data memory. - self.counter_addr = 1 - # Number of iterations in the innermost loop. - self.reps = None - # Number of times the program repeats the innermost loop. None means there is no outer loop. - self.expts = None - - # Generator managers, for keeping track of register values. - self._gen_mgrs = [self.gentypes[ch['type']](self, iCh) for iCh, ch in enumerate(soccfg['gens'])] - self._ro_mgrs = [ReadoutManager(self, iCh) if 'tproc_ctrl' in ch else None for iCh, ch in enumerate(soccfg['readouts'])] - - # Number of times the whole program is to be run. - self.rounds = 1 - # Rotation angle and thresholds for single-shot readout. - self.shot_angle = None - self.shot_threshold = None - - - def dump_prog(self): - """ - Dump the program to a dictionary. - This output contains all the information necessary to run the program. - Caution: don't modify the sub-dictionaries of this dict! - You will be modifying the original program (this is not a deep copy). - """ - progdict = {} - for key in self.dump_keys: - progdict[key] = getattr(self, key) - return progdict - - def load_prog(self, progdict): - """ - Load the program from a dictionary. - """ - for key in self.dump_keys: - setattr(self, key, progdict[key]) - - def acquire(self, soc, reads_per_rep=1, load_pulses=True, start_src="internal", progress=False, debug=False): - """Acquire data using the accumulated readout. - - Parameters - ---------- - soc : QickSoc - Qick object - reads_per_rep : int - number of readout triggers in the loop body - load_pulses : bool - if True, load pulse envelopes - start_src: str - "internal" (tProc starts immediately) or "external" (each round waits for an external trigger) - progress: bool - if true, displays progress bar - debug: bool - if true, displays assembly code for tProc program - - Returns - ------- - ndarray - raw accumulated IQ values (int32) - if rounds>1, only the last round is kept - dimensions : (n_ch, n_expts*n_reps*n_reads, 2) - - ndarray - averaged IQ values (float) - divided by the length of the RO window, and averaged over reps and rounds - if shot_threshold is defined, the I values will be the fraction of points over threshold - dimensions for a simple averaging program: (n_ch, n_reads, 2) - dimensions for a program with multiple expts/steps: (n_ch, n_reads, n_expts, 2) - """ - self.config_all(soc, load_pulses=load_pulses, start_src=start_src, debug=debug) - - n_ro = len(self.ro_chs) - - expts = self.expts - if expts is None: - expts = 1 - total_reps = expts*self.reps - total_count = total_reps*reads_per_rep - d_buf = np.zeros((n_ro, total_count, 2), dtype=np.int32) - self.stats = [] - - # select which tqdm progress bar to show - hiderounds = True - hidereps = True - if progress: - if self.rounds>1: - hiderounds = False - else: - hidereps = False - - # avg_d doesn't have a specific shape here, so that it's easier for child programs to write custom _average_buf - avg_d = None - shots = None - for ir in tqdm(range(self.rounds), disable=hiderounds): - # Configure and enable buffer capture. - self.config_bufs(soc, enable_avg=True, enable_buf=False) - - count = 0 - with tqdm(total=total_count, disable=hidereps) as pbar: - soc.start_readout(total_reps, counter_addr=self.counter_addr, - ch_list=list(self.ro_chs), reads_per_rep=reads_per_rep) - while count np.ndarray: - """ - calculate averaged data in a data acquire round. This function should be overwritten in the child qick program - if the data is created in a different shape. - - :param d_reps: buffer data acquired in a round - :param reads_per_rep: readouts per experiment - :return: averaged iq data after each round. - """ - expts = self.expts - if expts is None: - expts = 1 - - avg_d = np.zeros((len(self.ro_chs), reads_per_rep, expts, 2)) - for ii in range(reads_per_rep): - for i_ch, (ch, ro) in enumerate(self.ro_chs.items()): - avg_d[i_ch][ii] = np.sum(d_reps[i_ch][ii::reads_per_rep, :].reshape((expts, self.reps, 2)), axis=1) / (self.reps * ro['length']) - - if self.expts is None: # get rid of the expts axis - avg_d = avg_d[:, :, 0, :] - - return avg_d - - def get_single_shots(self, d_buf): - """ - This method converts the raw I/Q data to single shots according to the threshold and rotation angle - - Parameters - ---------- - d_buf : ndarray - Raw IQ data - - Returns - ------- - list of ndarray - Single shot data - - """ - # try to convert threshold to list of floats; if that fails, assume it's already a list - try: - thresholds = [float(self.shot_threshold)]*len(self.ro_chs) - except TypeError: - thresholds = self.shot_threshold - # angle is 0 if not specified - if self.shot_angle is None: - angles = [0.0]*len(self.ro_chs) - else: - try: - angles = [float(self.shot_angle)]*len(self.ro_chs) - except TypeError: - angles = self.shot_angle - - shots = [] - for i, ch in enumerate(self.ro_chs): - rotated = np.inner(d_buf[i], [np.cos(angles[i]), np.sin(angles[i])])/self.ro_chs[ch]['length'] - shots.append(np.heaviside(rotated - thresholds[i], 0)) - return shots - - - def acquire_decimated(self, soc, reads_per_rep=1, load_pulses=True, start_src="internal", progress=True, debug=False): - """Acquire data using the decimating readout. - - Parameters - ---------- - soc : QickSoc - Qick object - reads_per_rep : int - number of readout triggers in the loop body - load_pulses : bool - if True, load pulse envelopes - start_src: str - "internal" (tProc starts immediately) or "external" (each round waits for an external trigger) - progress: bool - if true, displays progress bar - debug: bool - if true, displays assembly code for tProc program - - Returns - ------- - list of ndarray - decimated values, averaged over rounds (float) - dimensions for a single-rep, single-read program : (length, 2) - multi-rep, multi-read: (n_reps, n_reads, length, 2) - """ - self.config_all(soc, load_pulses=load_pulses, start_src=start_src, debug=debug) - - # Initialize data buffers - d_buf = [] - for ch, ro in self.ro_chs.items(): - maxlen = self.soccfg['readouts'][ch]['buf_maxlen'] - if ro['length']*self.reps > maxlen: - raise RuntimeError("Warning: requested readout length (%d x %d reps) exceeds buffer size (%d)"%(ro['length'], self.reps, maxlen)) - d_buf.append(np.zeros((ro['length']*self.reps*reads_per_rep, 2), dtype=float)) - - tproc = soc.tproc - - # for each soft average, run and acquire decimated data - for ii in tqdm(range(self.rounds), disable=not progress): - # Configure and enable buffer capture. - self.config_bufs(soc, enable_avg=True, enable_buf=True) - - # make sure count variable is reset to 0 - tproc.single_write(addr=self.counter_addr, data=0) - - # run the assembly program - # if start_src="external", you must pulse the trigger input once for every round - tproc.start() - - count = 0 - while count < self.reps: - count = tproc.single_read(addr=self.counter_addr) - - for ii, (ch, ro) in enumerate(self.ro_chs.items()): - d_buf[ii] += obtain(soc.get_decimated(ch=ch, - address=0, length=ro['length']*self.reps*reads_per_rep)) - - # average the decimated data - if self.reps == 1 and reads_per_rep == 1: - return [d/self.rounds for d in d_buf] - else: - # split the data into the individual reps: - # we reshape to slice each long buffer into reps, - # then use moveaxis() to transpose the I/Q and rep axes - result = [d.reshape(self.reps*reads_per_rep, -1, 2)/self.rounds for d in d_buf] - if self.reps > 1 and reads_per_rep > 1: - result = [d.reshape(self.reps, reads_per_rep, -1, 2) for d in result] - return result - - def config_all(self, soc, load_pulses=True, start_src="internal", debug=False): - super().config_all(soc, load_pulses) - - # load this program into the soc's tproc - self.load_program(soc, debug=debug) - - # configure tproc for internal/external start - soc.start_src(start_src) - - def _ch_page_tproc(self, ch): - """Gets tProc register page associated with channel. - Page 0 gets one tProc output because it also has some other registers. - Other pages get two outputs each. - - This method is for internal use only. - User code should use ch_page() (for generators) or ch_page_ro() (for readouts). - - Parameters - ---------- - ch : int - tProc output channel - - Returns - ------- - int - tProc page number - - """ - return (ch+1)//2 - - def _sreg_tproc(self, ch, name): - """Gets tProc register number associated with a channel and register name. - - This method is for internal use only. - User code should use sreg() (for generators) or sreg_ro() (for readouts). - - Parameters - ---------- - ch : int - tProc output channel - name : str - Name of special register ("gain", "freq") - - Returns - ------- - int - tProc special register number - - """ - # special case for when we want to use the zero register - if name=='0': return 0 - n_regs = len(self.pulse_registers) - return 31 - (n_regs * 2) + n_regs*((ch+1)%2) + self.pulse_registers.index(name) - - def ch_page(self, gen_ch): - """Gets tProc register page associated with generator channel. - - Parameters - ---------- - gen_ch : int - generator channel (index in 'gens' list) - - Returns - ------- - int - tProc page number - - """ - tproc_ch = self.soccfg['gens'][gen_ch]['tproc_ch'] - return self._ch_page_tproc(tproc_ch) - - def sreg(self, gen_ch, name): - """Gets tProc special register number associated with a generator channel and register name. - - Parameters - ---------- - gen_ch : int - generator channel (index in 'gens' list) - name : str - Name of special register ("gain", "freq") - - Returns - ------- - int - tProc special register number - - """ - tproc_ch = self.soccfg['gens'][gen_ch]['tproc_ch'] - return self._sreg_tproc(tproc_ch, name) - - def ch_page_ro(self, ro_ch): - """Gets tProc register page associated with tProc-controlled readout channel. - - Parameters - ---------- - ro_ch : int - readout channel (index in 'readouts' list) - - Returns - ------- - int - tProc page number - - """ - tproc_ch = self.soccfg['readouts'][ro_ch]['tproc_ctrl'] - return self._ch_page_tproc(tproc_ch) - - def sreg_ro(self, ro_ch, name): - """Gets tProc special register number associated with a readout channel and register name. - - Parameters - ---------- - ro_ch : int - readout channel (index in 'readouts' list) - name : str - Name of special register ("gain", "freq") - - Returns - ------- - int - tProc special register number - - """ - tproc_ch = self.soccfg['readouts'][ro_ch]['tproc_ctrl'] - return self._sreg_tproc(tproc_ch, name) - - def default_pulse_registers(self, ch, **kwargs): - """Set default values for pulse parameters. - If any registers can be written at this point, write them in order to save time later. - - This is optional (you can set all parameters in set_pulse_registers). - You can only call this method once per channel. - There cannot be any overlap between the parameters defined here and the parameters you define in set_pulse_registers. - - Parameters - ---------- - ch : int - generator channel (index in 'gens' list) - **kwargs : dict - Pulse parameters - - """ - self._gen_mgrs[ch].set_defaults(kwargs) - - def set_pulse_registers(self, ch, **kwargs): - """Set the pulse parameters including frequency, phase, address of pulse, gain, stdysel, mode register (compiled from length and other flags), outsel, and length. - The time is scheduled when you call pulse(). - See the write_regs() method of the relevant generator manager for the list of supported pulse styles. - - Parameters - ---------- - ch : int - generator channel (index in 'gens' list) - style : str - Pulse style ("const", "arb", "flat_top") - freq : int - Frequency (register value) - phase : int - Phase (register value) - gain : int - Gain (DAC units) - phrst : int - If 1, it resets the phase coherent accumulator - stdysel : str - Selects what value is output continuously by the signal generator after the generation of a pulse. If "last", it is the last calculated sample of the pulse. If "zero", it is a zero value. - mode : str - Selects whether the output is "oneshot" or "periodic" - outsel : str - Selects the output source. The output is complex. Tables define envelopes for I and Q. If "product", the output is the product of table and DDS. If "dds", the output is the DDS only. If "input", the output is from the table for the real part, and zeros for the imaginary part. If "zero", the output is always zero. - length : int - The number of fabric clock cycles in the flat portion of the pulse, used for "const" and "flat_top" styles - waveform : str - Name of the envelope waveform loaded with add_pulse(), used for "arb" and "flat_top" styles - mask : list of int - for a muxed signal generator, the list of tones to enable for this pulse - """ - self._gen_mgrs[ch].set_registers(kwargs) - - def set_readout_registers(self, ch, **kwargs): - """Set the readout parameters including frequency, mode, outsel, and length. - The time is scheduled when you call readout(). - - Parameters - ---------- - ch : int - readout channel (index in 'readouts' list) - freq : int - Frequency (register value) - phrst : int - If 1, it resets the phase coherent accumulator - mode : str - Selects whether the output is "oneshot" or "periodic" - outsel : str - Selects the output source. The output is complex. The input comes from the ADC and is purely real. If "product", the output is the product of input and DDS. If "dds", the output is the DDS only. If "input", the output is from the input for the real part, and zeros for the imaginary part. If "zero", the output is always zero. - length : int - The number of fabric clock cycles for which these readout parameters are defined. - """ - self._ro_mgrs[ch].set_registers(kwargs) - - def default_readout_registers(self, ch, **kwargs): - """Set default values for readout parameters. - If any registers can be written at this point, write them in order to save time later. - - This is optional (you can set all parameters in set_readout_registers). - You can only call this method once per channel. - There cannot be any overlap between the parameters defined here and the parameters you define in set_readout_registers. - - Parameters - ---------- - ch : int - readout channel (index in 'readouts' list) - **kwargs : dict - Pulse parameters - - """ - self._ro_mgrs[ch].set_defaults(kwargs) - - def readout(self, ch, t): - """Play the pulse currently programmed into the registers for this tProc-controlled readout channel. - You must have already run set_readout_registers for this channel. - - Parameters - ---------- - ch : int - readout channel (index in 'readouts' list) - t : int - The number of tProc cycles at which the pulse starts - """ - # try to convert pulse_ch to int; if that fails, assume it's list of ints - ch_list = ch2list(ch) - for ch in ch_list: - tproc_ch = self.soccfg['readouts'][ch]['tproc_ctrl'] - rp = self._ch_page_tproc(tproc_ch) - next_pulse = self._ro_mgrs[ch].next_pulse - if next_pulse is None: - raise RuntimeError("no pulse has been set up for channel %d"%(ch)) - - r_t = self._sreg_tproc(tproc_ch, 't') - self.safe_regwi(rp, r_t, t, f't = {t}') - - for regs in next_pulse['regs']: - self.set(tproc_ch, rp, *regs, r_t, f"ch = {ch}, pulse @t = ${r_t}") - - - def setup_and_pulse(self, ch, t='auto', **kwargs): - """Set up a pulse on this generator channel, and immediately play it. - This is a wrapper around set_pulse_registers() and pulse(), and takes the arguments from both. - You can only run this on a single generator channel. - - Parameters - ---------- - ch : int - generator channel (index in 'gens' list) - t : int, optional - Pulse time, in tProc cycles - **kwargs : dict - Pulse parameters: refer to set_pulse_registers - """ - self.set_pulse_registers(ch, **kwargs) - self.pulse(ch, t) - - def setup_and_measure(self, adcs, pulse_ch, pins=None, adc_trig_offset=270, t='auto', wait=False, syncdelay=None, **kwargs): - """Set up a pulse on this generator channel, and immediately do a measurement with it. - This is a wrapper around set_pulse_registers() and measure(), and takes the arguments from both. - You can only run this on a single generator channel. - - Parameters - ---------- - adcs : list of int - readout channels (index in 'readouts' list) - pulse_ch : int - generator channel (index in 'gens' list) - pins : list of int, optional - refer to trigger() - adc_trig_offset : int, optional - refer to trigger() - t : int, optional - refer to pulse() - wait : bool, optional - refer to measure() - syncdelay : int, optional - refer to measure() - **kwargs : dict - Pulse parameters: refer to set_pulse_registers() - """ - self.set_pulse_registers(pulse_ch, **kwargs) - self.measure(adcs, pulse_ch, pins=pins, adc_trig_offset=adc_trig_offset, t=t, wait=wait, syncdelay=syncdelay) - - def pulse(self, ch, t='auto'): - """Play the pulse currently programmed into the registers for this generator channel. - You must have already run set_pulse_registers for this channel. - - Parameters - ---------- - ch : int or list of int - generator channel (index in 'gens' list) - t : int, optional - The number of tProc cycles at which the pulse starts (None to use the time register as is, 'auto' to start whenever the last pulse ends) - """ - # try to convert pulse_ch to int; if that fails, assume it's list of ints - ch_list = ch2list(ch) - for ch in ch_list: - tproc_ch = self.soccfg['gens'][ch]['tproc_ch'] - rp = self._ch_page_tproc(tproc_ch) - next_pulse = self._gen_mgrs[ch].next_pulse - if next_pulse is None: - raise RuntimeError("no pulse has been set up for channel %d"%(ch)) - - r_t = self._sreg_tproc(tproc_ch, 't') - - if t is not None: - ts = self.get_timestamp(gen_ch=ch) - if t == 'auto': - t = int(ts) - elif t < ts: - print("warning: pulse time %d appears to conflict with previous pulse ending at %f?"%(t, ts)) - # convert from generator clock to tProc clock - pulse_length = next_pulse['length'] - pulse_length *= self.soccfg['fs_proc']/self.soccfg['gens'][ch]['f_fabric'] - self.set_timestamp(t + pulse_length, gen_ch=ch) - self.safe_regwi(rp, r_t, t, f't = {t}') - - # Play each pulse segment. - # We specify the same time for all segments and rely on the signal generator to concatenate them without gaps. - # We could specify the "correct" times, but it's difficult to get right when the tProc and generator clocks are different. - for regs in next_pulse['regs']: - self.set(tproc_ch, rp, *regs, r_t, f"ch = {ch}, pulse @t = ${r_t}") - - def safe_regwi(self, rp, reg, imm, comment=None): - """Due to the way the instructions are setup immediate values can only be 30bits before not loading properly. - This comes up mostly when trying to regwi values into registers, especially the _frequency_ and _phase_ pulse registers. - safe_regwi can be used wherever one might use regwi and will detect if the value is >2**30 and if so will break it into two steps, putting in the first 30 bits shifting it over and then adding the last two. - - Parameters - ---------- - rp : int - Register page - reg : int - Register number - imm : int - Value of the write - comment : str, optional - Comment associated with the write - """ - if abs(imm) < 2**30: - self.regwi(rp, reg, imm, comment) - else: - self.regwi(rp, reg, imm >> 2, comment) - self.bitwi(rp, reg, reg, "<<", 2) - if imm % 4 != 0: - self.mathi(rp, reg, reg, "+", imm % 4) - - def sync_all(self, t=0): - """Aligns and syncs all channels with additional time t. - Accounts for both generator pulses and readout windows. - This does not pause the tProc. - - Parameters - ---------- - t : int, optional - The time offset in tProc cycles - """ - max_t = self.get_max_timestamp() - if max_t+t > 0: - self.synci(int(max_t+t)) - self.reset_timestamps() - - def wait_all(self, t=0): - """Pause the tProc until all ADC readout windows are complete, plus additional time t. - This does not sync the tProc clock. - - Parameters - ---------- - t : int, optional - The time offset in tProc cycles - """ - self.waiti(0, int(self.get_max_timestamp(gens=False, ros=True) + t)) - - # should change behavior to only change bits that are specified - def trigger(self, adcs=None, pins=None, adc_trig_offset=270, t=0, width=10, rp=0, r_out=31): - """Pulse the readout(s) and marker pin(s) with a specified pulse width at a specified time t+adc_trig_offset. - If no readouts are specified, the adc_trig_offset is not applied. - - Parameters - ---------- - adcs : list of int - List of readout channels to trigger (index in 'readouts' list) - pins : list of int - List of marker pins to pulse. - Use the pin numbers in the QickConfig printout. - adc_trig_offset : int, optional - Offset time at which the ADC is triggered (in tProc cycles) - t : int, optional - The number of tProc cycles at which the ADC trigger starts - width : int, optional - The width of the trigger pulse, in tProc cycles - rp : int, optional - Register page - r_out : int, optional - Register number - """ - if adcs is None: - adcs = [] - if pins is None: - pins = [] - if not adcs and not pins: - raise RuntimeError("must pulse at least one ADC or pin") - - out = 0 - for adc in adcs: - out |= (1 << self.soccfg['readouts'][adc]['trigger_bit']) - for pin in pins: - out |= (1 << pin) - - t_start = t - if adcs: - t_start += adc_trig_offset - # update timestamps with the end of the readout window - for adc in adcs: - ts = self.get_timestamp(ro_ch=adc) - if t_start < ts: - print("Readout time %d appears to conflict with previous readout ending at %f?"%(t, ts)) - # convert from readout clock to tProc clock - ro_length = self.ro_chs[adc]['length'] - ro_length *= self.soccfg['fs_proc']/self.soccfg['readouts'][adc]['f_fabric'] - self.set_timestamp(t_start + ro_length, ro_ch=adc) - t_end = t_start + width - - trig_output = self.soccfg['tprocs'][0]['trig_output'] - - self.regwi(rp, r_out, out, f'out = 0b{out:>016b}') - self.seti(trig_output, rp, r_out, t_start, f'ch =0 out = ${r_out} @t = {t}') - self.seti(trig_output, rp, 0, t_end, f'ch =0 out = 0 @t = {t}') - - def measure(self, adcs, pulse_ch, pins=None, adc_trig_offset=270, t='auto', wait=False, syncdelay=None): - """Wrapper method that combines an ADC trigger, a pulse, and (optionally) the appropriate wait and a sync_all. - You must have already run set_pulse_registers for this channel. - - If you use wait=True, it's recommended to also specify a nonzero syncdelay. - - Parameters - ---------- - adcs : list of int - readout channels (index in 'readouts' list) - pulse_ch : int or list of int - generator channel(s) (index in 'gens' list) - pins : list of int, optional - refer to trigger() - adc_trig_offset : int, optional - refer to trigger() - t : int, optional - refer to pulse() - wait : bool, optional - Pause tProc execution until the end of the ADC readout window - syncdelay : int, optional - The number of additional tProc cycles to delay in the sync_all - """ - self.trigger(adcs, pins=pins, adc_trig_offset=adc_trig_offset) - self.pulse(ch=pulse_ch, t=t) - if wait: - # tProc should wait for the readout to complete. - # This prevents loop counters from getting incremented before the data is available. - self.wait_all() - if syncdelay is not None: - self.sync_all(syncdelay) - - def reset_phase(self, gen_ch: Union[int, List[int]] = None, ro_ch: Union[int, List[int]] = None, t: int = 0): - """ - Reset the phase of generator and tproc-controlled readout channels at tproc time t. - This will play an empty pulse that lasts 3 fabric clock cycles, just to trigger the phase reset. - - This command is designed to be transparent to previous 'set_pulse/readout_registers()' calls. i.e. the register - values set using 'set_pulse/readout_registers()' before this command will remain the same after this command. - However, pulse registers set using other functions will need to be re-set, e.g. if a pulse register value was - set by directly calling 'regwi()', calling this function will overwrite that register value, and user need to - redo the 'regwi()' after this phase reset. - - :param gen_ch: generator channel(s) to reset phase (index in 'gens' list) - :param ro_ch: tProc-controlled readout channel(s) to reset phase (index in 'readouts' list) - :param t: the number of tProc cycles at which the phase reset happens - """ - # todo: not sure if it is possible to perform the phase reset without playing the empty pulses - - # convert gen and readout channels to lists of ints - channels = {"generator": ch2list(gen_ch), "readout": ch2list(ro_ch)} - - # reset phase for each generator and readout channel - for ch_type, ch_list in channels.items(): - for ch in ch_list: - # check time and get generator/readout manager - if ch_type == "generator": - ts = self.get_timestamp(gen_ch=ch) - if t < ts: - print(f"warning: generator {ch} phase reset at t={t} appears to conflict " - f"with previous pulse ending at {ts}") - ch_mgr = self._gen_mgrs[ch] - phrst_params = dict(style="const", phase=0, freq=0, gain=0, length=3, phrst=1) - tproc_ch = self.soccfg["gens"][ch]['tproc_ch'] - else: # for readout channels - ch_mgr = self._ro_mgrs[ch] - # skip PYNQ-controlled readouts, which can't be reset - if ch_mgr is None: continue - ts = self.get_timestamp(ro_ch=ch) - if t < ts: - print(f"warning: readout {ch} phase reset at t={t} appears to conflict " - f"with previous readout ending at {ts}") - phrst_params = dict(freq=0, length=3, phrst=1) - tproc_ch = self.soccfg["readouts"][ch]['tproc_ctrl'] - - # keeps a record of the last set registers and the default registers - last_set_regs_ = ch_mgr.last_set_regs - defaults_regs_ = ch_mgr.defaults - # temporarily ignore the default registers - ch_mgr.defaults = {} - # set registers for phase reset - ch_mgr.set_registers(phrst_params) - - # write phase reset time register - rp = self._ch_page_tproc(tproc_ch) - r_t = self._sreg_tproc(tproc_ch, 't') - self.safe_regwi(rp, r_t, t, f't = {t}') - # schedule phrst at $r_t - for regs in ch_mgr.next_pulse["regs"]: - self.set(tproc_ch, rp, *regs, r_t, f" {ch_type} ch{ch} phase reset @t = ${r_t}") - - # set the default and last set registers back - ch_mgr.set_defaults(defaults_regs_) - ch_mgr.set_registers(last_set_regs_) - - self.sync_all(3) - - def convert_immediate(self, val): - """Convert the register value to ensure that it is positive and not too large. Throws an error if you ever try to use a value greater than 2**31 as an immediate value. - - Parameters - ---------- - val : int - Original register value - - Returns - ------- - int - Converted register value - - """ - if val > 2**31: - raise RuntimeError( - f"Immediate values are only 31 bits {val} > 2**31") - if val < 0: - return 2**31+val - else: - return val - - def compile_instruction(self, inst, labels, debug=False): - """Converts an assembly instruction into a machine bytecode. - - Parameters - ---------- - inst : dict - Assembly instruction - labels : dict - Map from label name to program counter - debug : bool - If True, debug mode is on - - Returns - ------- - int - Compiled instruction in binary - - """ - args = list(inst['args']) - idef = self.__class__.instructions[inst['name']] - fmt = idef['fmt'] - - if debug: - print(inst) - - if idef['type'] == "I": - args[len(fmt)-1] = self.convert_immediate(args[len(fmt)-1]) - - if inst['name'] == 'loopnz': - args[2] = labels[args[2]] # resolve label - - if inst['name'] == 'condj': - args[4] = labels[args[4]] # resolve label - # get binary condtional op code - args[2] = self.__class__.op_codes[inst['args'][2]] - - if inst['name'][:4] == 'math': - args[3] = self.__class__.op_codes[inst['args'][3]] # get math op code - - if inst['name'][:4] == 'bitw': - # get bitwise op code - args[3] = self.__class__.op_codes[inst['args'][3]] - - if inst['name'][:4] == 'read': - args[2] = self.__class__.op_codes[inst['args'][2]] # get read op code - - mcode = (idef['bin'] << 56) - # print(inst) - for field in fmt: - mcode |= (args[field[0]] << field[1]) - - if inst['name'] == 'loopnz': - mcode |= (0b1000 << 46) - - return mcode - - def compile(self, debug=False): - """Compiles program to machine code. - - Parameters - ---------- - debug : bool - If True, debug mode is on - - Returns - ------- - list of int - List of binary instructions - - """ - labels = {} - # Scan the ASM instructions for labels. Skip comment lines. - prog_counter = 0 - for inst in self.prog_list: - if inst['name']=='comment': - continue - if 'label' in inst: - if inst['label'] in labels: - raise RuntimeError("label used twice:", inst['label']) - labels[inst['label']] = prog_counter - prog_counter += 1 - return [self.compile_instruction(inst, labels, debug=debug) for inst in self.prog_list if inst['name']!='comment'] - - def load_program(self, soc, debug=False, reset=False): - """Load the compiled program into the tProcessor. - - Parameters - ---------- - debug : bool - If True, debug mode is on - soc : QickSoc - The QICK to be configured - reset : bool - Reset the tProc before loading - """ - soc.load_bin_program(self.compile(debug=debug), reset=reset) - - def append_instruction(self, name, *args): - """Append instruction to the program list - - Parameters - ---------- - name : str - Instruction name - *args : dict - Instruction arguments - """ - n_args = max([f[0] for f in self.instructions[name]['fmt']]+[-1])+1 - if len(args)==n_args: - inst = {'name': name, 'args': args} - elif len(args)==n_args+1: - inst = {'name': name, 'args': args[:n_args], 'comment': args[n_args]} - else: - raise RuntimeError("wrong number of args:", name, args) - if self._label_next is not None: - # store the label with the instruction, for printing - inst['label'] = self._label_next - self._label_next = None - self.prog_list.append(inst) - - def label(self, name): - """Add line number label to the labels dictionary. This labels the instruction by its position in the program list. The loopz and condj commands use this label information. - - Parameters - ---------- - name : str - Label name - """ - if self._label_next is not None: - raise RuntimeError("label already defined for the next line") - self._label_next = name - - def __getattr__(self, a): - """ - Uses instructions dictionary to automatically generate methods for the standard instruction set. - - Also include all QickConfig methods as methods of the QickProgram. - This allows e.g. this.freq2reg(f) instead of this.soccfg.freq2reg(f). - - :param a: Instruction name - :type a: str - :return: Instruction arguments - :rtype: *args object - """ - if a in self.__class__.instructions: - return lambda *args: self.append_instruction(a, *args) - elif a in self.__class__.soccfg_methods: - return getattr(self.soccfg, a) - else: - return object.__getattribute__(self, a) - - def hex(self): - """Returns hex representation of program as string. - - Returns - ------- - str - Compiled program in hex format - """ - return "\n".join([format(mc, '#018x') for mc in self.compile()]) - - def bin(self): - """Returns binary representation of program as string. - - Returns - ------- - str - Compiled program in binary format - """ - return "\n".join([format(mc, '#066b') for mc in self.compile()]) - - def asm(self): - """Returns assembly representation of program as string, should be compatible with the parse_prog from the parser module. - - Returns - ------- - str - asm file - """ - label_list = [inst['label'] for inst in self.prog_list if 'label' in inst] - if label_list: - max_label_len = max([len(label) for label in label_list]) - else: - max_label_len = 0 - s = "\n// Program\n\n" - lines = [self._inst2asm(inst, max_label_len) for inst in self.prog_list] - return s+"\n".join(lines) - - def _inst2asm(self, inst, max_label_len): - if inst['name']=='comment': - return "// "+inst['comment'] - template = inst['name'] + " " + self.__class__.instructions[inst['name']]['repr'] + ";" - line = " "*(max_label_len+2) + template.format(*inst['args']) - if 'comment' in inst: - line += " "*(48-len(line)) + "//" + (inst['comment'] if inst['comment'] is not None else "") - if 'label' in inst: - label = inst['label'] - line = label + ": " + line[len(label)+2:] - return line - - def compare_program(self, fname): - """For debugging purposes to compare binary compilation of parse_prog with the compile. - - Parameters - ---------- - fname : str - File the comparison program is stored in - - Returns - ------- - bool - True if programs are identical; False otherwise - """ - match = True - pns = [int(n, 2) for n in self.bin().split('\n')] - fns = [int(n, 2) - for ii, n in parse_prog(file=fname, outfmt="bin").items()] - if len(pns) != len(fns): - print("Programs are different lengths") - return False - for ii in range(len(pns)): - if pns[ii] != fns[ii]: - print(f"Mismatch on line ii: p={pns[ii]}, f={fns[ii]}") - match = False - return match - - def __len__(self): - """ - :return: number of instructions in the program - :rtype: int - """ - return len(self.prog_list) - - def __str__(self): - """ - Print as assembly by default. - - :return: The asm file associated with the class - :rtype: str - """ - return self.asm() - - def __enter__(self): - """ - Enter the runtime context related to this object. - - :return: self - :rtype: self - """ - return self - - def __exit__(self, type, value, traceback): - """ - Exit the runtime context related to this object. - - :param type: type of error - :type type: type - :param value: value of error - :type value: int - :param traceback: traceback of error - :type traceback: str - """ - pass - - -class QickRegister: - def __init__(self, prog: QickProgram, page: int, addr: int, reg_type: str = None, - gen_ch: int = None, ro_ch: int = None, init_val=None, name: str = None): - """ - a qick register object that keeps the page, address, generator/readout channel and register type information, - provides functions that make it easier to set register value given input values in physical units. - - :param prog: qick program in which the register is used. - :param page: page of the register - :param addr: address of the register in the register page (referred as "register number" in some other places) - :param reg_type: {"freq", "time", "phase", "adc_freq"} or None, - type of the register, used for automatic converting to physical values. - :param gen_ch: generator channel numer to which the register is associated with, for unit convert. - :param ro_ch: readout channel numer to which the register is associated with, for unit convert. - :param init_val: initial value of the register. If reg_type is not None, the value should be in its physical - unit. i.e. freq in MHz, time in us, phase in deg. - :param name: If None, an auto generated name based on the register page and address will be used - """ - self.prog = prog - self.page = page - self.addr = addr - self.reg_type = reg_type - self.gen_ch = gen_ch - self.ro_ch = ro_ch - self.init_val = init_val - self.unit = DefaultUnits.get(str(self.reg_type)) - if name is None: - self.name = f"reg_p{page}_{addr}" - else: - self.name = name - if init_val is not None: - self.reset() - - def val2reg(self, val): - """ - convert physical value to a qick register value - :param val: - :return: - """ - if self.reg_type == "freq": - return self.prog.freq2reg(val, self.gen_ch, self.ro_ch) - elif self.reg_type == "time": - if self.gen_ch is not None: - return self.prog.us2cycles(val, self.gen_ch) - else: - return self.prog.us2cycles(val, self.gen_ch, self.ro_ch) - elif self.reg_type == "phase": - return self.prog.deg2reg(val, self.gen_ch) - elif self.reg_type == "adc_freq": - return self.prog.freq2reg_adc(val, self.ro_ch, self.gen_ch) - else: - return np.int32(val) - - def reg2val(self, reg): - """ - converts a qick register value to its value in physical units - :param reg: - :return: - """ - if self.reg_type == "freq": - return self.prog.reg2freq(reg, self.gen_ch) - elif self.reg_type == "time": - if self.gen_ch is not None: - return self.prog.cycles2us(reg, self.gen_ch) - else: - return self.prog.cycles2us(reg, self.gen_ch, self.ro_ch) - elif self.reg_type == "phase": - return self.prog.reg2deg(reg, self.gen_ch) - elif self.reg_type == "adc_freq": - return self.prog.reg2freq_adc(reg, self.ro_ch) - else: - return reg - - - def set_to(self, a: Union["QickRegister", float, int], operator: str = "+", - b: Union["QickRegister", float, int] = 0, physical_unit=True): - """ - a shorthand function that sets the register value using different asm commands based on the input type. - - if input "a" is a number, "operator" and "b" will be neglected, "a"(or the register integer that corresponds to - "a") will be assigned to the current register - - if input "a" is a QickRegister and "b" is a number, the register will be set to the "mathi" result between "a" - and "b". (when physical_unit==True, "b" will be auto-converted from physical value to register value based on - the register type) - - if both "a" and "b" are QickRegisters, the register will be set to the "math" result between "a" and "b". - - :param a: first operand register or a constant value - :param operator: {"+", "-", "*"}. math symbol supported by "math" and "mathi" asm commands - :param b: second operand register or a constant value - :param physical_unit: when True, the constant value operands should be in its physical unit and will be - automatically converted to the register integer before assignment. - :return: - """ - if operator not in MathOperators: - raise ValueError(f"operator {operator} is not supported.") - if type(a) != QickRegister: # assign value "a" to register, do unit conversion if physical_unit==True - reg = self.val2reg(a) if physical_unit else a - comment = f"'{self.name}' <= {reg} " + \ - (f"({a} {self.unit})" if physical_unit and (self.unit is not None) else "") - self.prog.safe_regwi(self.page, self.addr, reg, comment) - else: - if type(b) == QickRegister: - # do math operation between register "b" and register "a", assign the result to current register - comment = f" '{self.name}' <= '{a.name}' {operator} '{b.name}'" - if not (self.page == a.page == b.page): - raise RuntimeError(f"the qick registers for mathematical operation must be on the same page. " - f"Got '{self.name}' on page {self.page}, '{a.name}' on page {a.page} " - f"and '{b.name}' on page {b.page}") - self.prog.math(self.page, self.addr, a.addr, operator, b.addr, comment) - else: - # do math operation between value "b" and register "a", assign the result to current register - reg = self.val2reg(b) if physical_unit else b # do unit conversion on "b" if physical_unit==True - comment = f" '{self.name}' <= '{a.name}' {operator} {reg} " \ - + (f"({b} {self.unit})" if physical_unit and (self.unit is not None) else "") - if not (self.page == a.page): - raise RuntimeError(f"the qick registers for mathematical operation must be on the same page. " - f"Got '{self.name}' on page {self.page} and '{a.name}' on page {a.page}") - self.prog.mathi(self.page, self.addr, a.addr, operator, reg, comment) - - def reset(self): - """ - reset register value to its init_val - :return: - """ - self.set_to(self.init_val) - - -class QickRegisterManagerMixin: - """ - A mixin class for QickProgram that provides manager functions for getting and declaring new qick registers. - """ - - def __init__(self, *args, **kwargs): - self.user_reg_dict = {} # look up dict for registers defined in each generator channel - self._user_regs = [] # (page, addr) of all user defined registers - super().__init__(*args, **kwargs) - - def new_reg(self, page: int, addr: int = None, name: str = None, init_val=None, reg_type: str = None, - gen_ch: int = None, ro_ch: int = None): - """ Declare a new register in a specific page. - - :param page: register page - :param addr: address of the new register. If None, the function will automatically try to find the next - available address. - :param name: name of the new register. Optional. - :param init_val: initial value for the register, when reg_type is provided, the reg_val should be in the - physical unit of the corresponding type. i.e. freq in MHz, time in us, phase in deg. - :param reg_type: {"freq", "time", "phase", "adc_freq"} or None, type of the register - :param gen_ch: generator channel numer to which the register is associated with, for unit convert. - :param ro_ch: readout channel numer to which the register is associated with, for unit convert. - :return: QickRegister - """ - if addr is None: - addr = 1 - while (page, addr) in self._user_regs: - addr += 1 - if addr > 12: - raise RuntimeError(f"registers in page {page} is full.") - else: - if addr < 1 or addr > 12: - raise ValueError(f"register address must be greater than 0 and smaller than 13") - if (page, addr) in self._user_regs: - raise ValueError(f"register at address {addr} in page {page} is already occupied.") - self._user_regs.append((page, addr)) - - if name is None: - name = f"reg_page{page}_{addr}" - if name in self.user_reg_dict.keys(): - raise NameError(f"register name '{name}' already exists") - - reg = QickRegister(self, page, addr, reg_type, gen_ch, ro_ch, init_val, name=name) - self.user_reg_dict[name] = reg - - return reg - - def get_gen_reg(self, gen_ch: int, name: str) -> QickRegister: - """ - Gets tProc register page and address associated with gen_ch and register name. Creates a QickRegister object for - return. - - :param gen_ch: generator channel number - :param name: name of the qick register, as in QickProgram.pulse_registers - :return: QickRegister - """ - gen_cgf = self.gen_chs[gen_ch] - page = self.ch_page(gen_ch) - addr = self.sreg(gen_ch, name) - reg_type = name if name in RegisterType else None - reg = QickRegister(self, page, addr, reg_type, gen_ch, gen_cgf.get("ro_ch"), name=f"gen{gen_ch}_{name}") - return reg - - def new_gen_reg(self, gen_ch: int, name: str = None, init_val=None, reg_type: str = None, - tproc_reg=False) -> QickRegister: - """ - Declare a new register in the generator register page. Address automatically adds 1 one when each time a new - register in the same page is declared. - - :param gen_ch: generator channel number - :param name: name of the new register. Optional. - :param init_val: initial value for the register, when reg_type is provided, the reg_val should be in the unit of - the corresponding type. - :param reg_type: {"freq", "time", "phase", "adc_freq"} or None, type of the register. - :param tproc_reg: if True, the new register created will not be associated to a specific generator or readout - channel. It will still be on the same page as the gen_ch for math calculations. This is usually used for a - time register in t_processor, where we want to calculate "us2cycles" with the t_proc fabric clock rate - instead of the generator clock rate. - :return: QickRegister - """ - gen_cgf = self.gen_chs[gen_ch] - page = self.ch_page(gen_ch) - - addr = 1 - while (page, addr) in self._user_regs: - addr += 1 - if name is None: - name = f"gen{gen_ch}_reg{addr}" - - if tproc_reg: - return self.new_reg(page, addr, name, init_val, reg_type, None, None) - else: - return self.new_reg(page, addr, name, init_val, reg_type, gen_ch, gen_cgf.get("ro_ch")) diff --git a/qick/qick_lib/qick/rfboard.py b/qick/qick_lib/qick/rfboard.py deleted file mode 100644 index 1295fa6..0000000 --- a/qick/qick_lib/qick/rfboard.py +++ /dev/null @@ -1,1624 +0,0 @@ -import os -from .qick import SocIp, QickSoc -from .qick_asm import QickConfig -from pynq.overlay import Overlay, DefaultIP -from pynq.buffer import allocate -import xrfclk -import numpy as np -import time -from qick.ipq_pynq_utils import clock_models - - -class AxisSignalGenV3(SocIp): - # AXIS Table Registers. - # START_ADDR_REG - # - # WE_REG - # * 0 : disable writes. - # * 1 : enable writes. - # - bindto = ['user.org:user:axis_signal_gen_v3:1.0'] - REGISTERS = {'start_addr_reg': 0, 'we_reg': 1} - - # Generics - N = 12 - NDDS = 16 - - # Maximum number of samples - MAX_LENGTH = 2**N*NDDS - - def __init__(self, description, **kwargs): - super().__init__(description) - - def config(self, axi_dma, dds_mr_switch, axis_switch, channel, name, **kwargs): - # Default registers. - self.start_addr_reg = 0 - self.we_reg = 0 - - # dma - self.dma = axi_dma - - # Real/imaginary selection switch. - #self.iq_switch = AxisDdsMrSwitch(dds_mr_switch) - self.iq_switch = dds_mr_switch - - # switch - self.switch = axis_switch - - # Channel. - self.ch = channel - - # Name. - self.name = name - - # Load waveforms. - def load(self, buff_in, addr=0): - # Route switch to channel. - self.switch.sel(slv=self.ch) - - time.sleep(0.1) - - # Define buffer. - self.buff = allocate(shape=(len(buff_in)), dtype=np.int16) - - ################### - ### Load I data ### - ################### - np.copyto(self.buff, buff_in) - - # Enable writes. - self.wr_enable(addr) - - # DMA data. - self.dma.sendchannel.transfer(self.buff) - self.dma.sendchannel.wait() - - # Disable writes. - self.wr_disable() - - def wr_enable(self, addr=0): - self.start_addr_reg = addr - self.we_reg = 1 - - def wr_disable(self): - self.we_reg = 0 - - -class AxisSignalGenV3Ctrl(SocIp): - # Signal Generator V3 Control registers. - # ADDR_REG - bindto = ['user.org:user:axis_signal_gen_v3_ctrl:1.0'] - REGISTERS = { - 'freq': 0, - 'phase': 1, - 'addr': 2, - 'gain': 3, - 'nsamp': 4, - 'outsel': 5, - 'mode': 6, - 'stdysel': 7, - 'we': 8} - - # Generics of Signal Generator. - N = 10 - NDDS = 16 - B = 16 - MAX_v = 2**B - 1 - - # Sampling frequency. - fs = 4096 - - def __init__(self, description, **kwargs): - super().__init__(description) - - # Default registers. - self.freq = 0 - self.phase = 0 - self.addr = 0 - self.gain = 30000 - self.nsamp = 16*100 - self.outsel = 1 # dds - self.mode = 1 # periodic - self.stdysel = 1 # zero - self.we = 0 - - def add(self, - freq=0, - phase=0, - addr=0, - gain=30000, - nsamp=16*100, - outsel="dds", - mode="periodic", - stdysel="zero"): - - # Input frequency is in MHz. - w0 = 2*np.pi*freq/self.fs - freq_tmp = w0/(2*np.pi)*self.MAX_v - - self.freq = int(np.round(freq_tmp)) - self.phase = phase - self.addr = addr - self.gain = gain - self.nsamp = int(np.round(nsamp/self.NDDS)) - - self.outsel = {"product": 0, "dds":1, "envelope":2}[outsel] - self.mode = {"nsamp": 0, "periodic":1}[mode] - self.stdysel = {"last": 0, "zero":1}[stdysel] - - # Write fifo.. - self.we = 1 - self.we = 0 - - def set_fs(self, fs): - self.fs = fs - - -class AxisDdsMrSwitch(SocIp): - # AXIS DDS MR SWITCH registers. - # DDS_REAL_IMAG_REG - # * 0 : real part. - # * 1 : imaginary part. - # - bindto = ['user.org:user:axis_dds_mr_switch:1.0'] - REGISTERS = {'dds_real_imag': 0} - - def __init__(self, description, **kwargs): - """ - Constructor method - """ - super().__init__(description) - - # Default registers. - # dds_real_imag = 0 : take real part. - self.dds_real_imag = 0 - - def config(self, reg_): - self.dds_real_imag = reg_ - - def real(self): - self.config(0) - - def imag(self): - self.config(1) - - -class spi(DefaultIP): - - bindto = ['xilinx.com:ip:axi_quad_spi:3.2'] - SPI_REGLIST = ['DGIER', 'IPISR', 'IPIER', 'SRR', 'SPICR', 'SPISR', 'SPI_DTR', 'SPI_DRR', 'SPI_SSR', 'SPI_TXFIFO_OR', 'SPI_RXFIFO_OR'] - - # - # SPI registers - See Xilinx PG153 AXI Quad SPI for discriptions - # - #DGIER = 0x1C # 0x1C - RW - SPI Device Global Interrupt Enable Register - #IPISR = 0x20 # 0x20 - RW - SPI IP Interrupt Status Register - #IPIER = 0x28 # 0x28 - RW - SPI IP Interrupt Enable Register - #SRR = 0x40 # 0x40 - WO - SPI Software Reset Reg - #SPICR = 0x60 # 0x60 - RW - SPI Control Register - #SPISR = 0x64 # 0x64 - RO - SPI Status Register - #SPI_DTR = 0x68 # 0x68 - WO - SPI Data Transmit Register - #SPI_DRR = 0x6C # 0x6C - RO - SPI Data Receive Register - #SPI_SSR = 0x70 # 0x70 - RW - SPI Slave Select Register - #SPI_TXFIFO_OR = 0x74 # 0x74 - RW - SPI Transmit FIFO Occupancy Register - #SPI_RXFIFO_OR = 0x78 # 0x78 - RO - SPI Receive FIFO Occupancy Register - - def __init__(self, description, **kwargs): - super().__init__(description) - - # Soft reset SPI. - self.rst() - - # De-assert slave select - self.SPI_SSR = 0 - - def __setattr__(self, a, v): - if a in self.SPI_REGLIST: - setattr(self.register_map, a, v) - else: - super().__setattr__(a, v) - - def __getattr__(self, a): - #print(self.SPI_REGLIST) - if a in self.SPI_REGLIST: - return getattr(self.register_map, a) - else: - return super().__getattribute__(a) - - def rst(self): - self.SRR = 0xA - - # SPI Control Register: - # Bit 9 : LSB/MSB selection. - # -> 0 : MSB first - # -> 1 : LSB first - # - # Bit 8 : Master Transaction Inhibit. - # -> 0 : Master Transaction Enabled. - # -> 1 : Master Transaction Disabled. - # - # Bit 7 : Manual Slave Select Assertion. - # -> 0 : Slave select asserted by master core logic. - # -> 1 : Slave select follows data in SSR. - # - # Bit 6 : RX FIFO Reset. - # -> 0 : Normal operation. - # -> 1 : Reset RX FIFO. - # - # Bit 5 : TX FIFO Reset. - # -> 0 : Normal operation. - # -> 1 : Reset RX FIFO. - # - # Bit 4 : Clock Phase. - # -> 0 : - # -> 1 : - # - # Bit 3 : Clock Polarity. - # -> 0 : Active-High clock. SCK idles low. - # -> 1 : Active-Low clock. SCK idles high. - # - # Bit 2 : Master mode. - # -> 0 : Slave configuration. - # -> 1 : Master configuration. - # - # Bit 1 : SPI system enable. - # -> 0 : SPI disabled. Outputs 3-state. - # -> 1 : SPI enabled. - # - # Bit 0 : Local loopback mode. - # -> 0 : Normal operation. - # -> 1 : Loopback mode. - def config(self, - lsb="lsb", - msttran="enable", - ssmode="ssr", - rxfifo="rst", - txfifo="rst", - cpha="", - cpol="high", - mst="master", - en="enable", - loopback="no"): - - # LSB/MSB. - self.register_map.SPICR.LSB_First = {"lsb":1, "msb":0}[lsb] - - # Master transaction inhibit. - self.register_map.SPICR.Master_Transaction_Inhibit = {"disable":1, "enable":0}[msttran] - - # Manual slave select. - self.register_map.SPICR.Manual_Slave_Select_Assertion_Enable = {"ssr":1, "auto":0}[ssmode] - - # RX FIFO. - self.register_map.SPICR.RX_FIFO_Reset = {"rst":1, "":0}[rxfifo] - - # TX FIFO. - self.register_map.SPICR.TX_FIFO_Reset = {"rst":1, "":0}[txfifo] - - # CPHA. - self.register_map.SPICR.CPHA = {"invert":1, "":0}[cpha] - - # CPOL - self.register_map.SPICR.CPOL = {"low":1, "high":0}[cpol] - - # Master mode. - self.register_map.SPICR.Master = {"master":1, "slave":0}[mst] - - # SPI enable. - self.register_map.SPICR.SPE = {"enable":1, "disable":0}[en] - - # Loopback - self.register_map.SPICR.LOOP = {"yes":1, "no":0}[loopback] - - # Enable function. - def en_level(self, nch=4, chlist=[0], en_l="high"): - """ - chlist: list of bits to enable - en_l: enable level - "high": ignore nch, enabled bits are set high - "low": nch is total length, enabled bits are set low - """ - ch_en = 0 - if en_l == "high": - for i in range(len(chlist)): - ch_en |= (1 << chlist[i]) - elif en_l == "low": - ch_en = 2**nch - 1 - for i in range(len(chlist)): - ch_en &= ~(1 << chlist[i]) - - return ch_en - - # Send function. - def send_m(self, data, ch_en, cs_t="pulse"): - # Manually assert channels. - ch_en_temp = self.SPI_SSR.Selected_Slave - - # Standard CS at the beginning of transaction. - if cs_t != "pulse": - self.SPI_SSR = ch_en - - # Send data. - for byte in data: - # Send data. - self.SPI_DTR = byte - - # LE pulse at the end. - if cs_t == "pulse": - # Write SSR to enable channels. - self.SPI_SSR = ch_en - - # Write SSR to previous value. - self.SPI_SSR = ch_en_temp - - # Bring CS to default value. - if cs_t != "pulse": - self.SPI_SSR = ch_en_temp - - # Receive function. - def receive(self): - # Fifo is empty - if self.SPISR.RX_Empty==1: - return [] - else: - # Get number of samples on fifo. - nr = self.SPI_RXFIFO_OR.Occupancy_Value + 1 - data_r = bytes([self.SPI_DRR.RX_Data for i in range(nr)]) - return data_r - - # Send/Receive. - def send_receive_m(self, data, ch_en, cs_t="pulse"): - """ - data: list of bytes to send - ch_en: destination address - """ - self.send_m(data, ch_en, cs_t) - data_r = self.receive() - - return data_r - -# Step Attenuator PE43705. -# Range 0-31.75 dB. -# Parts are used in serial mode. -# See schematics for Address/LE correspondance. -class PE43705: - address = 0 - nSteps = 2**7 - dbStep = 0.25 - dbMinAtt = 0 - dbMaxAtt = (nSteps-1)*dbStep - - def __init__(self, address=0): - self.address = address - - def db2step(self, db): - ret = -1 - - # Sanity check. - if db < self.dbMinAtt: - print("%s: attenuation value %f out of range" % - (self.__class__.__name__, db)) - elif db > self.dbMaxAtt: - print("%s: attenuation value %f out of range" % - (self.__class__.__name__, db)) - else: - ret = int(np.round(db/self.dbStep)) - - return ret - - def db2reg(self, db): - reg = 0 - - # Steps. - reg |= self.db2step(db) - - # Address. - reg |= (self.address << 8) - - return reg - -# GPIO chip MCP23S08. -class MCP23S08: - # Commands. - cmd_wr = 0x40 - cmd_rd = 0x41 - - # Registers. - REGS = {'IODIR_REG': 0x00, - 'IPOL_REG': 0x01, - 'GPINTEN_REG': 0x02, - 'DEFVAL_REG': 0x03, - 'INTCON_REG': 0x04, - 'IOCON_REG': 0x05, - 'GPPU_REG': 0x06, - 'INTF_REG': 0x07, - 'INTCAP_REG': 0x08, - 'GPIO_REG': 0x09, - 'OLAT_REG': 0x0A} - - def __init__(self, dev_addr): - self.dev_addr = dev_addr - - # Register/address mapping. - def reg2addr(self, reg="GPIO_REG"): - if reg in self.REGS: - return self.REGS[reg] - else: - print("%s: register %s not recognized." % - (self.__class__.__name__, reg)) - return -1 - - # Data array: 3 bytes. - # byte[0] = opcode. - # byte[1] = register address. - # byte[2] = register value (dummy for read). - def reg_rd(self, reg="GPIO_REG"): - byte = [] - - # Read command. - byte.append(self.cmd_rd + 2*self.dev_addr) - - # Address. - addr = self.reg2addr(reg) - byte.append(addr) - - # Dummy byte for clocking data out. - byte.append(0) - - return byte - - def reg_wr(self, reg="GPIO_REG", val=0): - byte = [] - - # Write command. - byte.append(self.cmd_wr + 2*self.dev_addr) - - # Address. - addr = self.reg2addr(reg) - byte.append(addr) - - # Dummy byte for clocking data out. - byte.append(val) - - return byte - -# LO Chip ADF4372. - - -class ADF4372: - # Reference input. - f_REF_in = 122.88 - - # Fixed 25-bit modulus. - MOD1 = 2**25 - - # Commands. - cmd_wr = 0x00 - cmd_rd = 0x80 - - # Registers. - REGS = {'CONFIG0_REG': 0x00, - 'CONFIG1_REG': 0x01, - 'CHIP_REG': 0x03, - 'PROD_ID0_REG': 0x04, - 'PROD_ID1_REG': 0x05, - 'PROD_REV_REG': 0x06, - 'INT_LOW_REG': 0x10, - 'INT_HIGH_REG': 0x11, - 'CAL_PRE_REG': 0x12, - 'FRAC1_LOW_REG': 0x14, - 'FRAC1_MID_REG': 0x15, - 'FRAC1_HIGH_REG': 0x16, - 'FRAC2_LOW_REG': 0x17, # NOTE: bit zero is the MSB of FRAC1. - 'FRAC2_HIGH_REG': 0x18, - 'MOD2_LOW_REG': 0x19, - 'MOD2_HIGH_REG': 0x1A, # NOTE: bi 6 is PHASE_ADJ. - 'PHASE_LOW_REG': 0x1B, - 'PHASE_MID_REG': 0x1C, - 'PHASE_HIGH_REG': 0x1D, - 'CONFIG2_REG': 0x1E, - 'RCNT_REG': 0x1F, - 'MUXOUT_REG': 0x20, - 'REF_REG': 0x22, - 'CONFIG3_REG': 0x23, - 'RFDIV_REG': 0x24, - 'RFOUT_REG': 0x25, - 'BLEED0_REG': 0x26, - 'BLEED1_REG': 0x27, - 'LOCK_REG': 0x28, - 'CONFIG4_REG': 0x2A, - 'SD_REG': 0x2B, - 'VCO_BIAS0_REG': 0x2C, - 'VCO_BIAS1_REG': 0x2D, - 'VCO_BIAS2_REG': 0x2E, - 'VCO_BIAS3_REG': 0x2F, - 'VCO_BAND_REG': 0x30, - 'TIMEOUT_REG': 0x31, - 'ADC_REG': 0x32, - 'SYNTH_TIMEOUT_REG': 0x33, - 'VCO_TIMEOUT_REG': 0x34, - 'ADC_CLK_REG': 0x35, - 'ICP_OFFSET_REG': 0x36, - 'SI_BAND_REG': 0x37, - 'SI_VCO_REG': 0x38, - 'SI_VTUNE_REG': 0x39, - 'ADC_OFFSET_REG': 0x3A, - 'SD_RESET_REG': 0x3D, - 'CP_TMODE_REG': 0x3E, - 'CLK1_DIV_LOW_REG': 0x3F, - 'CLK1_DIV_HIGH_REG': 0x40, - 'CLK2_DIV_REG': 0x41, - 'TRM_RESD0_REG': 0x47, - 'TRM_RESD1_REG': 0x52, - 'VCO_DATA_LOW_REG': 0x6E, - 'VCO_DATA_HIGH_REG': 0x6F, - 'BIAS_SEL_X2_REG': 0x70, - 'BIAS_SEL_X4_REG': 0x71, - 'AUXOUT_REG': 0x72, - 'LD_PD_ADC_REG': 0x73, - 'LOCK_DETECT_REG': 0x7C} - - def reg2addr(self, reg="CONFIG0_REG"): - if reg in self.REGS: - return self.REGS[reg] - else: - print("%s: register %s not recognized." % - (self.__class__.__name__, reg)) - return -1 - - # Data array: 3 bytes. - # byte[0] = opcode/addr high. - # byte[1] = addr low. - # byte[2] = register value (dummy for read). - def reg_rd(self, reg="CONFIG0_REG"): - byte = [] - - # Read command. - byte.append(self.cmd_rd) - - # Address. - addr = self.reg2addr(reg) - byte.append(addr) - - # Dummy byte for clocking data out. - byte.append(0) - - return byte - - def reg_wr(self, reg="CONFIG0_REG", val=0): - byte = [] - - # Write command. - byte.append(self.cmd_wr) - - # Address. - addr = self.reg2addr(reg) - byte.append(addr) - - # Dummy byte for clocking data out. - byte.append(val) - - return byte - - # Simple frequency setting function. - # FRAC2 = 0 not used. - # INT,FRAC1 sections are used. - # All frequencies are in MHz. - # Frequency must be in the range 4-8 GHz. - def set_freq(self, fin=6000): - # Structures for output. - regs = {} - regs['INT'] = {'FULL': 0, 'LOW': 0, 'HIGH': 0} - regs['FRAC1'] = {'FULL': 0, 'LOW': 0, 'MID': 0, 'HIGH': 0, 'MSB': 0} - - # Sanity check. - if fin < 4000: - print("%s: input frequency %d below the limit" % - (self.__class__.__name__, fin)) - return -1 - elif fin > 8000: - print("%s: input frequency %d above the limit" % - (self.__class__.__name__, fin)) - return -1 - - Ndiv = fin/self.f_REF_in - - # Integer part. - int_ = int(np.floor(Ndiv)) - int_low = int_ & 0xff - int_high = int_ >> 8 - - # Fractional part. - frac_ = Ndiv - int_ - frac_ = int(np.floor(frac_*self.MOD1)) - frac_low = frac_ & 0xff - frac_mid = (frac_ >> 8) & 0xff - frac_high = (frac_ >> 16) & 0xff - frac_msb = frac_ >> 24 - - # Write values into structure. - regs['INT']['FULL'] = int_ - regs['INT']['LOW'] = int_low - regs['INT']['HIGH'] = int_high - regs['FRAC1']['FULL'] = frac_ - regs['FRAC1']['LOW'] = frac_low - regs['FRAC1']['MID'] = frac_mid - regs['FRAC1']['HIGH'] = frac_high - regs['FRAC1']['MSB'] = frac_msb - - return regs - -# BIAS DAC chip AD5781. - - -class AD5781: - # Commands. - cmd_wr = 0x0 - cmd_rd = 0x1 - - # Negative/Positive voltage references. - VREFN = -10 - VREFP = 10 - - # Bits. - B = 18 - - # Registers. - REGS = {'DAC_REG': 0x01, - 'CTRL_REG': 0x02, - 'CLEAR_REG': 0x03, - 'SOFT_REG': 0x04} - - # Register/address mapping. - def reg2addr(self, reg="DAC_REG"): - if reg in self.REGS: - return self.REGS[reg] - else: - print("%s: register %s not recognized." % - (self.__class__.__name__, reg)) - return -1 - - def reg_rd(self, reg="DAC_REG"): - byte = [] - - # Address. - addr = self.reg2addr(reg) - - # R/W bit + address (upper 4 bits). - cmd = (self.cmd_rd << 3) | addr - cmd = (cmd << 4) - byte.append(cmd) - - # Dummy bytes for completing the command. - # NOTE: another full, 24-bit transaction is needed to clock the register out (may be all 0s). - byte.append(0) - byte.append(0) - - return byte - - def reg_wr(self, reg="DAC_REG", val=0): - byte = [] - - # Address. - addr = self.reg2addr(reg) - - # R/W bit + address (upper 4 bits). - cmd = (self.cmd_wr << 3) | addr - cmd = (cmd << 4) - - val_high = val >> 16 - val_mid = (val >> 8) & 0xff - val_low = val & 0xff - - # Append bytes. - byte.append(cmd | val_high) - byte.append(val_mid) - byte.append(val_low) - - return byte - - # Compute register value for voltage setting. - def volt2reg(self, volt=0): - if volt < self.VREFN: - print("%s: %d V out of range." % (self.__class__.__name__, volt)) - return -1 - elif volt > self.VREFP: - print("%s: %d V out of range." % (self.__class__.__name__, volt)) - return -1 - else: - Df = (2**self.B - 1)*(volt - self.VREFN)/(self.VREFP - self.VREFN) - - # Shift by two as 2 lower bits are not used. - Df = int(Df) << 2 - - return int(Df) - -# Attenuator class: This class instantiates spi and PE43705 to simplify access to attenuator. -class attenuator: - - # Constructor. - def __init__(self, spi_ip, ch=0, nch=3, le=[0], en_l="high", cs_t="pulse"): - # PE43705. - self.pe = PE43705(address=ch) - - # SPI. - self.spi = spi_ip - - # Lath-enable. - self.ch_en = self.spi.en_level(nch, le, en_l) - self.cs_t = cs_t - - # Initialize with max attenuation. - self.set_att(31.75) - - # Set attenuation function. - def set_att(self, db): - # Register value. - reg = [self.pe.db2reg(db)] - - # Write value using spi. - self.spi.send_receive_m(reg, self.ch_en, self.cs_t) - -# Power, Switch and Fan. - -class SwitchControl: - # Constructor. - def __init__(self, spi_ip): - self.spi = spi_ip - self.devs = [] - self.net2port = {} - - def add_MCP(self, ch_en, outputs, dev_addr=0): - if len(outputs) != 8: - raise RuntimeError("must define all 8 outputs from the MCP23S08 (use None for NC pins)") - defaults = 0 - for iOutput, output in enumerate(outputs): - defaults <<= 1 - if output is not None: - netname, defaultval = output - self.net2port[netname] = (len(self.devs), iOutput) - defaults += defaultval - self.devs.append(power_sw_fan(self.spi, ch_en=ch_en, dev_addr=dev_addr, defaults=defaults)) - - def __setitem__(self, netname, val): - iDev, iBit = self.net2port[netname] - if val == 1: - self.devs[iDev].bits_set(bits=[iBit]) - elif val == 0: - self.devs[iDev].bits_reset(bits=[iBit]) - else: - raise RuntimeError("invalid value:", val) - -class power_sw_fan: - - # Constructor. - def __init__(self, spi_ip, ch_en, defaults=0xFF, dev_addr=0, cs_t=""): - # MCP23S08. - self.mcp = MCP23S08(dev_addr=dev_addr) - - # SPI. - self.spi = spi_ip - - # CS. - self.ch_en = ch_en - self.cs_t = cs_t - - # All CS to high value. - self.spi.SPI_SSR = 0xff - - # Set all bits as outputs. - byte = self.mcp.reg_wr("IODIR_REG", 0x00) - self.spi.send_receive_m(byte, self.ch_en, self.cs_t) - - # Set default output values. - byte = self.mcp.reg_wr("GPIO_REG", defaults) - self.spi.send_receive_m(byte, self.ch_en, self.cs_t) - - # Write bits. - def bits_set(self, bits=[0]): - val = 0 - - # Read actual value. - byte = self.mcp.reg_rd("GPIO_REG") - vals = self.spi.send_receive_m(byte, self.ch_en, self.cs_t) - val = int(vals[2]) - - # Set bits. - for i in range(len(bits)): - val |= (1 << bits[i]) - - # Set value to hardware. - byte = self.mcp.reg_wr("GPIO_REG", val) - self.spi.send_receive_m(byte, self.ch_en, self.cs_t) - - def bits_reset(self, bits=[0]): - val = 0xff - - # Read actual value. - byte = self.mcp.reg_rd("GPIO_REG") - vals = self.spi.send_receive_m(byte, self.ch_en, self.cs_t) - val = int(vals[2]) - - # Reset bits. - for i in range(len(bits)): - val &= ~(1 << bits[i]) - - # Set value to hardware. - byte = self.mcp.reg_wr("GPIO_REG", val) - self.spi.send_receive_m(byte, self.ch_en, self.cs_t) - -# LO Synthesis. -class lo_synth: - - # Constructor. - def __init__(self, spi_ip, nch=2, le=[0], en_l="low", cs_t=""): - # ADF4372. - self.adf = ADF4372() - - # SPI. - self.spi = spi_ip - - # CS. - self.ch_en = self.spi.en_level(nch, le, en_l) - self.cs_t = cs_t - - # All CS to high value. - self.spi.SPI_SSR = 0xff - - # Write 0x00 to reg 0x73 - self.reg_wr("LD_PD_ADC_REG", 0x00) - # Write 0x3a to reg 0x72 - self.reg_wr("AUXOUT_REG", 0x3A) - # Write 0x60 to reg 0x71 - self.reg_wr("BIAS_SEL_X4_REG", 0x60) - # Write 0xe3 to reg 0x70 - self.reg_wr("BIAS_SEL_X2_REG", 0xE3) - # Write 0xf4 to reg 0x52 - self.reg_wr("TRM_RESD1_REG", 0xF4) - # Write 0xc0 to reg 0x47 - self.reg_wr("TRM_RESD0_REG", 0xC0) - # Write 0x28 to reg 0x41 - self.reg_wr("CLK2_DIV_REG", 0x28) - # Write 0x50 to reg 0x40 - self.reg_wr("CLK1_DIV_HIGH_REG", 0x50) - # Write 0x80 to reg 0x3f - self.reg_wr("CLK1_DIV_LOW_REG", 0x80) - # Write 0x0c to reg 0x3e - self.reg_wr("CP_TMODE_REG", 0x0C) - # Write 0x00 to reg 0x3d - self.reg_wr("SD_RESET_REG", 0x00) - # Write 0x55 to reg 0x3a - self.reg_wr("ADC_OFFSET_REG", 0x55) - # Write 0x07 to reg 0x39 - self.reg_wr("SI_VTUNE_REG", 0x07) - # Write 0x00 to reg 0x38 - self.reg_wr("SI_VCO_REG", 0x00) - # Write 0x00 to reg 0x37 - self.reg_wr("SI_BAND_REG", 0x00) - # Write 0x30 to reg 0x36 - self.reg_wr("ICP_OFFSET_REG", 0x30) - # Write 0xff to reg 0x35 - self.reg_wr("ADC_CLK_REG", 0xFF) - # Write 0x86 to reg 0x34 - self.reg_wr("VCO_TIMEOUT_REG", 0x86) - # Write 0x23 to reg 0x33 - self.reg_wr("SYNTH_TIMEOUT_REG", 0x23) - # Write 0x04 to reg 0x32 - self.reg_wr("ADC_REG", 0x04) - # Write 0x02 to reg 0x31 - self.reg_wr("TIMEOUT_REG", 0x02) - # Write 0x34 to reg 0x30 - self.reg_wr("VCO_BAND_REG", 0x34) - # Write 0x94 to reg 0x2f - self.reg_wr("VCO_BIAS3_REG", 0x94) - # Write 0x12 to reg 0x2e - self.reg_wr("VCO_BIAS2_REG", 0x12) - # Write 0x11 to reg 0x2d - self.reg_wr("VCO_BIAS1_REG", 0x11) - # Write 0x44 to reg 0x2c - self.reg_wr("VCO_BIAS0_REG", 0x44) - # Write 0x10 to reg 0x2b - self.reg_wr("SD_REG", 0x10) - # Write 0x00 to reg 0x2a - self.reg_wr("CONFIG4_REG", 0x00) - # Write 0x83 to reg 0x28 - self.reg_wr("LOCK_REG", 0x83) - # Write 0xcd to reg 0x27 - self.reg_wr("BLEED1_REG", 0xcd) - # Write 0x2f to reg 0x26 - self.reg_wr("BLEED0_REG", 0x2F) - # Write 0x07 to reg 0x25 - self.reg_wr("RFOUT_REG", 0x07) - # Write 0x80 to reg 0x24 - self.reg_wr("RFDIV_REG", 0x80) - # Write 0x00 to reg 0x23 - self.reg_wr("CONFIG3_REG", 0x00) - # Write 0x00 to reg 0x22 - self.reg_wr("REF_REG", 0x00) - # Write 0x14 to reg 0x20 - self.reg_wr("MUXOUT_REG", 0x14) - # Write 0x01 to reg 0x1f - self.reg_wr("RCNT_REG", 0x01) - # Write 0x58 to reg 0x1e - self.reg_wr("CONFIG2_REG", 0x58) - # Write 0x00 to reg 0x1d - self.reg_wr("PHASE_HIGH_REG", 0x00) - # Write 0x00 to reg 0x1c - self.reg_wr("PHASE_MID_REG", 0x00) - # Write 0x00 to reg 0x1b - self.reg_wr("PHASE_LOW_REG", 0x00) - # Write 0x00 to reg 0x1a - self.reg_wr("MOD2_HIGH_REG", 0x00) - # Write 0x03 to reg 0x19 - self.reg_wr("MOD2_LOW_REG", 0x03) - # Write 0x00 to reg 0x18 - self.reg_wr("FRAC2_HIGH_REG", 0x00) - # Write 0x01 to reg 0x17 (holds MSB of FRAC1 on bit[0]). - self.reg_wr("FRAC2_LOW_REG", 0x01) - # Write 0x61 to reg 0x16 - self.reg_wr("FRAC1_HIGH_REG", 0x61) - # Write 0x055 to reg 0x15 - self.reg_wr("FRAC1_MID_REG", 0x55) - # Write 0x55 to reg 0x14 - self.reg_wr("FRAC1_LOW_REG", 0x55) - # Write 0x40 to reg 0x12 - self.reg_wr("CAL_PRE_REG", 0x40) - # Write 0x00 to reg 0x11 - self.reg_wr("INT_HIGH_REG", 0x00) - # Write 0x28 to reg 0x10 - self.reg_wr("INT_LOW_REG", 0x28) - - def reg_rd(self, reg="CONFIG0_REG"): - # Byte array. - byte = self.adf.reg_rd(reg) - - # Execute read. - reg = self.spi.send_receive_m(byte, self.ch_en, self.cs_t) - - return reg - - def reg_wr(self, reg="CONFIG0_REG", val=0): - # Byte array. - byte = self.adf.reg_wr(reg, val) - - # Execute write. - self.spi.send_receive_m(byte, self.ch_en, self.cs_t) - - def set_freq(self, fin=6000): - # Get INT/FRAC register values. - regs = self.adf.set_freq(fin) - - # Check if it was successful. - if regs == -1: - a = 1 - else: - # Write FRAC1 register. - # MSB - self.reg_wr('FRAC2_LOW_REG', regs['FRAC1']['MSB']) - - # HIGH. - self.reg_wr('FRAC1_HIGH_REG', regs['FRAC1']['HIGH']) - - # MID. - self.reg_wr('FRAC1_MID_REG', regs['FRAC1']['MID']) - - # LOW. - self.reg_wr('FRAC1_LOW_REG', regs['FRAC1']['LOW']) - - # Write INT register. - # HIGH. - self.reg_wr('INT_HIGH_REG', regs['INT']['HIGH']) - - # LOW - self.reg_wr('INT_LOW_REG', regs['INT']['LOW']) - -# Bias dac. -class dac_bias: - - # Constructor. - def __init__(self, spi_ip, ch_en, cs_t=""): - # AD5791. - self.ad = AD5781() - - # SPI. - self.spi = spi_ip - - # CS. - self.ch_en = ch_en - self.cs_t = cs_t - - # All CS to high value. - self.spi.SPI_SSR = 0xff - - # Initialize control register. - self.write(reg="CTRL_REG", val=0x312) - - # Initialize to 0 volts. - self.set_volt(0) - - def read(self, reg="DAC_REG"): - # Read command. - byte = self.ad.reg_rd(reg) - reg = self.spi.send_receive_m(byte, self.ch_en, self.cs_t) - - # Another read with dummy data to allow clocking register out. - byte = [0, 0, 0] - reg = self.spi.send_receive_m(byte, self.ch_en, self.cs_t) - - return reg - - def write(self, reg="DAC_REG", val=0): - # Write command. - byte = self.ad.reg_wr(reg, val) - self.spi.send_receive_m(byte, self.ch_en, self.cs_t) - - def set_volt(self, volt=0): - # Convert volts to register value. - val = self.ad.volt2reg(volt) - self.write(reg="DAC_REG", val=val) - -# Variable Gain Amp chip LMH6401. -class LMH6401: - # Commands. - cmd_wr = 0x00 - cmd_rd = 0x80 - - # Registers. - REGS = {'REVID_REG': 0x00, - 'PRODID_REG': 0x01, - 'GAIN_REG': 0x02, - 'TGAIN_REG': 0x04, - 'TFREQ_REG': 0x05} - - # Register/address mapping. - def reg2addr(self, reg="GAIN_REG"): - if reg in self.REGS: - return self.REGS[reg] - else: - print("%s: register %s not recognized." % - (self.__class__.__name__, reg)) - return -1 - - # Data array: 2 bytes. - # byte[0] = rw/address. - # byte[1] = data. - def reg_rd(self, reg="GAIN_REG"): - byte = [] - - # Address. - addr = self.reg2addr(reg) - - # Read command. - cmd = self.cmd_rd | addr - byte.append(cmd) - - # Dummy byte for clocking data out. - byte.append(0) - - return byte - - def reg_wr(self, reg="GAIN_REG", val=0): - byte = [] - - # Address. - addr = self.reg2addr(reg) - - # Read command. - cmd = self.cmd_wr | addr - byte.append(cmd) - - # Data. - byte.append(val) - - return byte - -# Variable step amp class: This class instantiates spi and LMH6401 to simplify access to amplifier. -class gain: - - # Number of bits of gain setting. - B = 6 - - # Minimum/maximum gain. - Gmin = -6 - Gmax = 26 - - # Constructor. - def __init__(self, spi_ip, ch_en, cs_t=""): - # LMH6401. - self.lmh = LMH6401() - - # SPI. - self.spi = spi_ip - - # Lath-enable. - self.ch_en = ch_en - self.cs_t = cs_t - - # Initalize to min gain. - self.set_gain(-6) - - # Set gain. - def set_gain(self, db): - # Sanity check. - if db < self.Gmin: - print("%s: gain %f out of limits." % (self.__class__.__name__, db)) - elif db > self.Gmax: - print("%s: gain %f out of limits." % (self.__class__.__name__, db)) - else: - # Convert gain to attenuation (register value). - db_a = int(np.round(self.Gmax - db)) - - # Write command. - byte = self.lmh.reg_wr(reg="GAIN_REG", val=db_a) - - # Write value using spi. - self.spi.send_receive_m(byte, self.ch_en, self.cs_t) - -# Class to describe the ADC-RF channel chain. -class adc_rf_ch(): - # Constructor. - def __init__(self, ch, switches, attn_spi): - # Channel number. - self.ch = ch - - # Power switches. - self.switches = switches - - # Attenuator. - self.attn = attenuator(attn_spi, ch, le=[0]) - - # Default to 30 dB attenuation. - self.set_attn_db(30) - - # Set attenuator. - def set_attn_db(self, db=0): - self.attn.set_att(db) - self.enable() - - def enable(self): - # Turn on 5V power. - self.switches["RF2IF5V_EN%d"%(self.ch)] = 1 - - def disable(self): - # Turn off 5V power. - self.switches["RF2IF5V_EN%d"%(self.ch)] = 0 - -# Class to describe the ADC-DC channel chain. -class adc_dc_ch(): - # Constructor. - def __init__(self, ch, switches, gain_spi, version=2): - # Channel number. - self.ch = ch - - # RF board version. - self.version = version - - # Power switches. - self.switches = switches - - # Variable Gain Amplifier. - if ch < 4 or ch > 7: - print("%s: channel %d not valid for ADC-DC type" % - (self.__class__.__name__, ch)) - - self.gain = gain(gain_spi, ch_en=ch) - - # Default to 0 dB gain. - self.set_gain_db(0) - - # Set gain. - def set_gain_db(self, db=0): - self.gain.set_gain(db) - if self.version==2: - self.enable() - - def enable(self): - if self.version!=2: - raise RuntimeError("enable/disable not supported for version", self.version) - # Power up. - self.switches["RF2IF_PD%d"%(self.ch)] = 0 - - def disable(self): - if self.version!=2: - raise RuntimeError("enable/disable not supported for version", self.version) - # Power down. - self.switches["RF2IF_PD%d"%(self.ch)] = 1 - -# Class to describe the DAC channel chain. -class dac_ch(): - # Constructor. - def __init__(self, ch, switches, attn_spi, version=2): - # Channel number. - self.ch = ch - - # RF board version. - self.version = version - - # RF input and power switches. - self.switches = switches - - # Attenuators. - self.attn = [] - self.attn.append(attenuator(attn_spi, ch, le=[1])) - self.attn.append(attenuator(attn_spi, ch, le=[2])) - - # Initialize in off state. - self.disable() - - # Switch selection. - def rfsw_sel(self, sel="RF"): - if sel == "RF": - # Set logic one. - # Select RF output from switch. - self.switches["CH%d_PE42020_CTL"%(self.ch)] = 1 - # Turn on 5V power to RF chain. - self.switches["IF2RF5V_EN%d"%(self.ch)] = 1 - if self.version==2: - # Power down DC amplifier. - self.switches["IF2RF_PD%d"%(self.ch)] = 1 - elif sel == "DC": - # Select DC output from switch. - self.switches["CH%d_PE42020_CTL"%(self.ch)] = 0 - # Turn off 5V power to RF chain. - self.switches["IF2RF5V_EN%d"%(self.ch)] = 0 - if self.version==2: - # Power up DC amplifier. - self.switches["IF2RF_PD%d"%(self.ch)] = 0 - elif sel == "OFF": - # Select RF output from switch. - self.switches["CH%d_PE42020_CTL"%(self.ch)] = 1 - # Turn off 5V power to RF chain. - self.switches["IF2RF5V_EN%d"%(self.ch)] = 0 - if self.version==2: - # Power down DC amplifier. - self.switches["IF2RF_PD%d"%(self.ch)] = 1 - else: - print("%s: selection %s not recoginzed." % - (self.__class__.__name__, sel)) - - # Set attenuator. - def set_attn_db(self, attn=0, db=0): - if attn < len(self.attn): - self.attn[attn].set_att(db) - else: - print("%s: attenuator %d not in chain." % - (self.__class__.__name__, attn)) - - def set_rf(self, att1, att2): - self.rfsw_sel("RF") - self.set_attn_db(attn=0, db=att1) - self.set_attn_db(attn=1, db=att2) - - def set_dc(self): - self.rfsw_sel("DC") - - def disable(self): - self.rfsw_sel("OFF") - self.set_attn_db(attn=0, db=31.75) - self.set_attn_db(attn=1, db=31.75) - - - -class RFQickSoc(QickSoc): - """ - Overrides the __init__ method of QickSoc in order to add the drivers for the preproduction (V1) version of the RF board. - Otherwise supports all the QickSoc functionality. - """ - def __init__(self, bitfile, no_tproc=False, **kwargs): - """ - A bitfile must always be provided, since the default bitstream will not work with the RF board. - By default, re-initialize the clocks every time. - This ensures that the LO output to the RF board is enabled. - """ - super().__init__(bitfile=bitfile, clk_output=True, no_tproc=no_tproc, **kwargs) - - self.rfb_config(no_tproc) - - def rfb_config(self, no_tproc): - """ - Configure the SPI interfaces to the RF board. - """ - # SPI used for Attenuators. - self.attn_spi.config(lsb="lsb") - - # SPI used for Power, Switch and Fan. - self.psf_spi.config(lsb="msb") - - # SPI used for the LO. - self.lo_spi.config(lsb="msb") - - # SPI used for DAC BIAS. - self.dac_bias_spi.config(lsb="msb", cpha="invert") - - # GPIO outputs: - # ADC/DAC power enable, DAC RF input switch. - # Initialize everything with power off. - self.switches = SwitchControl(self.psf_spi) - # ADC power - self.switches.add_MCP(ch_en=0, - outputs=[("RF2IF5V_EN"+str(i), 0) for i in range(4)] - + [None]*4) - # DAC power - self.switches.add_MCP(ch_en=1, - outputs=[("IF2RF5V_EN"+str(i), 0) for i in range(8)]) - # DAC RF/DC switch - self.switches.add_MCP(ch_en=2, - outputs=[("CH%d_PE42020_CTL"%(i), 1) for i in range(8)]) - - # LO Synthesizers. - self.lo = [lo_synth(self.lo_spi, le=[i]) for i in range(2)] - - # DAC BIAS. - self.dac_bias = [dac_bias(self.dac_bias_spi, ch_en=ii) for ii in range(8)] - - # ADC channels. - self.adcs = [adc_rf_ch(ii, self.switches, self.attn_spi) for ii in range(4)] + [adc_dc_ch(ii, self.switches, self.psf_spi, version=1) for ii in range(4,8)] - - # DAC channels. - self.dacs = [dac_ch(ii, self.switches, self.attn_spi, version=1) for ii in range(8)] - - if not no_tproc: - # Link gens/readouts to the corresponding RF board channels. - for gen in self.gens: - tile, block = [int(a) for a in gen.dac] - gen.rfb = self.dacs[4*tile + block] - for ro in self.readouts: - tile, block = [int(a) for a in ro.adc] - ro.rfb = self.adcs[2*tile + block] - - def rfb_set_lo(self, f): - """Set both of the RF-board local oscillators to the same frequency. - - Tile 0 DACs and all RF ADCs are connected to LO[0], tile 1 DACs are connected to LO[1]. - - Parameters - ---------- - f : float - Frequency (4000-8000 MHz) - """ - for lo in self.lo: - lo.set_freq(f) - - def rfb_set_gen_rf(self, gen_ch, att1, att2): - """Enable and configure an RF-board output channel for RF output. - - Parameters - ---------- - gen_ch : int - DAC channel (index in 'gens' list) - att1 : float - Attenuation for first stage (0-31.75 dB) - att2 : float - Attenuation for second stage (0-31.75 dB) - """ - self.gens[gen_ch].rfb.set_rf(att1, att2) - - def rfb_set_gen_dc(self, gen_ch): - """Enable and configure an RF-board output channel for DC output. - - Parameters - ---------- - gen_ch : int - DAC channel (index in 'gens' list) - """ - self.gens[gen_ch].rfb.set_dc() - - def rfb_set_ro_rf(self, ro_ch, att): - """Enable and configure an RF-board RF input channel. - Will fail if this is not an RF input. - - Parameters - ---------- - ro_ch : int - ADC channel (index in 'readouts' list) - att : float - Attenuation (0 to 31.75 dB) - """ - self.readouts[ro_ch].rfb.set_attn_db(att) - - def rfb_set_ro_dc(self, ro_ch, gain): - """Enable and configure an RF-board DC input channel. - Will fail if this is not a DC input. - - Parameters - ---------- - ro_ch : int - ADC channel (index in 'readouts' list) - gain : float - Gain (-6 to 26 dB) - """ - self.readouts[ro_ch].rfb.set_gain_db(gain) - - def rfb_set_bias(self, bias_ch, v): - """Set a voltage on an RF-board bias DAC. - - Parameters - ---------- - bias_ch : int - Channel number (0-7) - v : float - Voltage (-10 to 10 V) - """ - self.dac_bias[bias_ch].set_volt(v) - -class lo_synth_v2: - def __init__(self, spi_ip, ch): - # SPI. - self.spi = spi_ip - - # CS. - self.ch_en = self.spi.en_level(3, [ch], "low") - self.cs_t = "" - # All CS to high value. - self.spi.SPI_SSR = 0xff - - self.lmx = clock_models.LMX2594(122.88) - self.reset() - - @property - def freq(self): - return self.lmx.f_outa - - def reset(self): - self.reg_wr(0x000002) - self.reg_wr(0x000000) - - def reg_wr(self, regval): - data = regval.to_bytes(length=3, byteorder='big') - rec = self.spi.send_receive_m(data, self.ch_en, self.cs_t) - - def reg_rd(self, addr): - data = [addr + (1<<7), 0, 0] - return self.spi.send_receive_m(data, self.ch_en, self.cs_t) - - def read_and_parse(self, addr): - regval = int.from_bytes(self.reg_rd(addr), byteorder="big") - reg = clock_models.Register(self.lmx.registers_by_addr[addr].regdef) - reg.parse(regval) - return reg - - def is_locked(self): - status = self.get_param("rb_LD_VTUNE") - #print(status.value_description) - return status.value == self.lmx.rb_LD_VTUNE.LOCKED.value - - def set_freq(self, f, pwr=50, osc_2x=False, reset=True, verbose=False): - self.lmx.set_output_frequency(f, pwr=pwr, en_b=True, osc_2x=osc_2x, verbose=verbose) - if reset: self.reset() - self.program() - time.sleep(0.01) - self.calibrate(verbose=verbose) - - def calibrate(self, timeout=1.0, n_attempts=5, verbose=False): - for i in range(n_attempts): - # you'd think FCAL_EN needs to be toggled, not just set to 1? - # but datasheet doesn't say so, and this seems to work - self.set_param("FCAL_EN", 1) - starttime = time.time() - while time.time()-starttime < timeout: - lock = self.is_locked() - if lock: - if verbose: print("LO locked on attempt %d after %.2f sec"%(i+1, time.time()-starttime)) - return - time.sleep(0.01) - if verbose: print("lock attempt %d failed"%(i+1)) - raise RuntimeError("LO failed to lock after %d attempts"%(n_attempts)) - - def set_param(self, name, val): - param = getattr(self.lmx, name) - param.value = val - if isinstance(param, clock_models.Field): - self.reg_wr(self.lmx.registers_by_addr[param.addr].get_raw()) - else: # MultiRegister - for field in param.fields: - self.reg_wr(self.lmx.registers_by_addr[field.addr].get_raw()) - - def get_param(self, name): - param = getattr(self.lmx, name) - return self.read_and_parse(param.addr).fields[param.index] - - def program(self): - for regval in self.lmx.get_register_dump(): - self.reg_wr(regval) - -class RFQickSocV2(RFQickSoc): - def rfb_config(self, no_tproc): - """ - Configure the SPI interfaces to the RF board. - """ - # SPI used for Attenuators. - self.attn_spi.config(lsb="lsb") - - # SPI used for Power, Switch and Fan. - self.psf_spi.config(lsb="msb") - - # SPI used for the LO. - self.lo_spi.config(lsb="msb") - - # SPI used for DAC BIAS. - self.dac_bias_spi.config(lsb="msb", cpha="invert") - - # GPIO outputs: - # ADC/DAC power enable, DAC RF input switch. - # Initialize everything with power off. - self.switches = SwitchControl(self.psf_spi) - # ADC power/power-down - self.switches.add_MCP(ch_en=0, dev_addr=0, - outputs=[("RF2IF5V_EN"+str(i), 0) for i in range(4)] - + [("RF2IF_PD"+str(i), 1) for i in range(4, 8)]) - # DAC power-down - self.switches.add_MCP(ch_en=1, dev_addr=1, - outputs=[("IF2RF_PD"+str(i), 1) for i in range(8)]) - # DAC power - self.switches.add_MCP(ch_en=1, dev_addr=0, - outputs=[("IF2RF5V_EN"+str(i), 0) for i in range(8)]) - # DAC RF/DC switch - self.switches.add_MCP(ch_en=2, dev_addr=0, - outputs=[("CH%d_PE42020_CTL"%(i), 1) for i in range(8)]) - - # LO Synthesizers. - self.lo = [lo_synth_v2(self.lo_spi, i) for i in range(3)] - - # DAC BIAS. - self.dac_bias = [dac_bias(self.dac_bias_spi, ch_en=ii) for ii in range(8)] - - # ADC channels. - self.adcs = [adc_rf_ch(ii, self.switches, self.attn_spi) for ii in range(4)] + [adc_dc_ch(ii, self.switches, self.psf_spi) for ii in range(4,8)] - - # DAC channels. - self.dacs = [dac_ch(ii, self.switches, self.attn_spi) for ii in range(8)] - - # Link RF channels to LOs. - for adc in self.adcs[:4]: adc.lo = self.lo[0] - for dac in self.dacs[:4]: dac.lo = self.lo[1] - for dac in self.dacs[4:]: dac.lo = self.lo[2] - - if not no_tproc: - # Link gens/readouts to the corresponding RF board channels. - for gen in self.gens: - tile, block = [int(a) for a in gen.dac] - gen.rfb = self.dacs[4*tile + block] - for ro in self.readouts: - tile, block = [int(a) for a in ro.adc] - ro.rfb = self.adcs[2*tile + block] - - def rfb_set_lo(self, f, ch=None, verbose=False): - """Set RF-board local oscillators. - - LO[0]: all RF ADCs - LO[1]: RF DACs 0-3 - LO[2]: RF DACs 4-7 - - Parameters - ---------- - f : float - Frequency (4000-8000 MHz) - ch : int - LO to configure (None=all) - verbose : bool - Print freq and lock info. - """ - if ch is not None: - self.lo[ch].set_freq(f, verbose=verbose) - else: - for lo in self.lo: - lo.set_freq(f, verbose=verbose) - - def rfb_get_lo(self, gen_ch=None, ro_ch=None): - """Get local oscillator frequency for a DAC or ADC channel. - - Parameters - ---------- - gen_ch : int - DAC channel (index in 'gens' list) - ro_ch : int - ADC channel (index in 'readouts' list) - """ - if gen_ch is not None and ro_ch is not None: - raise RuntimeError("can't specify both gen_ch and ro_ch") - if gen_ch is not None: - return self.gens[gen_ch].rfb.lo.freq - if ro_ch is not None: - return self.readouts[ro_ch].rfb.lo.freq - raise RuntimeError("must specify gen_ch or ro_ch") - diff --git a/qick/qick_lib/qick/streamer.py b/qick/qick_lib/qick/streamer.py deleted file mode 100644 index 9b00d2e..0000000 --- a/qick/qick_lib/qick/streamer.py +++ /dev/null @@ -1,169 +0,0 @@ -from threading import Thread, Event -from queue import Queue -import time -import numpy as np -import traceback - -# This code originally used Process not Thread. -# Process is much slower to start (Process.start() is ~100 ms, Thread.start() is a few ms) -# The process-safe versions of Queue and Event are also significantly slower. -# On the other hand, CPU-bound Python threads can't run in parallel ("global interpreter lock"). -# The overall problem is not CPU-bound - we should always be limited by tProc execution. -# In the worst case where the tProc is running fast, we should actually be waiting for IO a lot (due to the DMA). -# So we think it's safe to use threads. -# However, this is a complicated problem and we may ultimately need to mess around with sys.setswitchinterval() or go back to Process. -# To use Process instead of Thread, use the following import and change WORKERTYPE. -#from multiprocessing import Process, Queue, Event - -class DataStreamer(): - """ - Uses a separate thread to read data from the average buffers. - The class methods define the readout loop and initialization of the worker thread. - The QickSoc methods start_readout() and poll_data() are the external interface to the streamer. - - We don't lock the QickSoc or the IPs. The user is responsible for not disrupting a readout in progress. - - :param soc: The QickSoc object. - :type soc: QickSoc - """ - - #WORKERTYPE = Process - WORKERTYPE = Thread - - def __init__(self, soc): - self.soc = soc - - self.start_worker() - - def start_worker(self): - # Initialize flags and queues. - # Passes run commands from the main thread to the worker thread. - self.job_queue = Queue() - # Passes data from the worker thread to the main thread. - self.data_queue = Queue() - # Passes exceptions from the worker thread to the main thread. - self.error_queue = Queue() - # The main thread can use this flag to tell the worker thread to stop. - # The main thread clears the flag when starting readout. - self.stop_flag = Event() - # The worker thread uses this to tell the main thread when it's done. - # The main thread clears the flag when starting readout. - self.done_flag = Event() - self.done_flag.set() - - # Process object for the streaming readout. - # daemon=True means the readout thread will be killed if the parent is killed - self.readout_worker = self.WORKERTYPE(target=self._run_readout, daemon=True) - self.readout_worker.start() - - def stop_readout(self): - """ - Signal the readout loop to break. - """ - self.stop_flag.set() - - def readout_running(self): - """ - Test if the readout loop is running. - - :return: readout thread status - :rtype: bool - """ - return not self.done_flag.is_set() - - def data_available(self): - """ - Test if data is available in the queue. - - :return: data queue status - :rtype: bool - """ - return not self.data_queue.empty() - - def _run_readout(self): - """ - Worker thread for the streaming readout - - :param total_count: Number of data points expected - :type addr: int - :param counter_addr: Data memory address for the loop counter - :type counter_addr: int - :param ch_list: List of readout channels - :type addr: list - :param reads_per_count: Number of data points to expect per counter increment - :type reads_per_count: int - """ - while True: - try: - # wait for a job - total_reps, counter_addr, ch_list, reads_per_count, stride = self.job_queue.get(block=True) - #print("streamer loop: start", total_count) - - reps = 0 - last_reps = 0 - last_count = 0 - - # how many reps worth of data to transfer at a time - if stride is None: - stride = int(0.1 * self.soc.get_avg_max_length(0)/reads_per_count) - # bigger stride is more efficient, but the transfer size must never exceed AVG_MAX_LENGTH, so the stride should be set with some safety margin - - # make sure count variable is reset to 0 before starting processor - self.soc.tproc.single_write(addr=counter_addr, data=0) - stats = [] - - t_start = time.time() - - # if the tproc is configured for internal start, this will start the program - # for external start, the program will not start until a start pulse is received - self.soc.tproc.start() - - # Keep streaming data until you get all of it - while last_reps < total_reps: - if self.stop_flag.is_set(): - print("streamer loop: got stop flag") - break - reps = self.soc.tproc.single_read(addr=counter_addr) - # wait until either you've gotten a full stride of measurements or you've finished (so you don't go crazy trying to download every measurement) - if reps >= min(last_reps+stride, total_reps): - addr = last_count % self.soc.get_avg_max_length(0) - # transfers must be of even length; trim the length (instead of padding it) - # don't trim if this is the last read of the run - if reps < last_reps: - newreps = (reps-last_reps) % 2 - else: - newreps = reps-last_reps - length = newreps * reads_per_count - if length >= self.soc.get_avg_max_length(0): - raise RuntimeError("Overflowed the averages buffer (%d unread samples >= buffer size %d)." - % (length, self.soc.get_avg_max_length(0)) + - "\nYou need to slow down the tProc by increasing relax_delay." + - "\nIf the TQDM progress bar is enabled, disabling it may help.") - - # buffer for each channel - d_buf = np.zeros((len(ch_list), length, 2), dtype=np.int32) - - # for each adc channel get the single shot data and add it to the buffer - for iCh, ch in enumerate(ch_list): - data = self.soc.get_accumulated(ch=ch, address=addr, length=length) - d_buf[iCh] = data - - last_reps += newreps - last_count += length - - stats = (time.time()-t_start, reps, addr, length) - self.data_queue.put((length, (d_buf, stats))) - #if last_count==total_count: print("streamer loop: normal completion") - - except Exception as e: - print("streamer loop: got exception") - traceback.print_exc() - # pass the exception to the main thread - self.error_queue.put(e) - # put dummy data in the data queue, to trigger a poll_data read - self.data_queue.put((0, (None, None))) - finally: - # we should set the done flag regardless of whether we completed readout, used the stop flag, or errored out - self.done_flag.set() - # set tproc for internal start so we don't run the program repeatedly (this also clears the internal-start register) - self.soc.start_src("internal") diff --git a/qick/qick_lib/qick/tprocv2_assembler.py b/qick/qick_lib/qick/tprocv2_assembler.py deleted file mode 100644 index 6cc0443..0000000 --- a/qick/qick_lib/qick/tprocv2_assembler.py +++ /dev/null @@ -1,1707 +0,0 @@ -""" -Assembler for Qick Time Processor QTP - -################################### -### UNDER DEVELOPMENT ### -################################### -""" - - -##### DEFINITIONS -############################################################################### - -# Instructions. -instList = { - 'NOP' : '000 - No Operation', - 'TEST' : '000 - Update ALU Flags with an Operation', - 'REG_WR' : '100 - Register Write', - 'DMEM_WR' : '101 - Data Memory Write', - 'WMEM_WR' : '101 - WaveParam Memory Write', - 'DPORT_WR' : '110 - Data Port Write', - 'TRIG' : '110 - Trigger Set', - 'DPORT_RD' : '110 - Data Port Read', - 'WPORT_WR' : '110 - WaveParam Port Write', - 'JUMP' : '001 - Branch to a Specific Address', - 'CALL' : '001 - Function Call', - 'RET' : '001 - Function Return', - 'FLAG' : '111 - FLAG set / reset', - 'TIME' : '111 - Time Instruction', - 'ARITH' : '111 - Opeates (A+/-B)*C+/-D', - 'DIV' : '111 - Opeates (A/B) Return Quotient and Reminder', - 'NET' : '111 - Net Instruction', - 'CUSTOM' : '111 - Cutsom Peripheral Instruction', - 'WAIT' : '001 - Jump [HERE] Until time value arrives.', - 'COPRO' : '100 -' } - -# ALU OPERATIONS -aluList = { - '+' : '0000', - '-' : '0010', - 'AND' : '0100', - '&' : '0100', - 'MSK' : '0100', - 'ASR' : '0110', - 'ABS' : '1000', - 'MSH' : '1010', - 'LSH' : '1100', - 'SWP' : '1110', - 'NOT' : '0001', - '!' : '0001', - 'OR' : '0011', - '|' : '0011', - 'XOR' : '0101', - '^' : '0101', - 'CAT' : '0111', - '::' : '0111', - 'RFU' : '1001', - 'PAR' : '1011', - 'SL' : '1101', - '<<' : '1101', - 'SR' : '1111', - '>>' : '1111' } - -aluList_s = { - '+' : '00', - '-' : '01', - 'AND' : '10', - 'ASR' : '11' } ## List with Commands for -op() - -aluList_op = ['ABS', 'MSH', 'LSH', 'SWP', 'PAR', 'NOT'] ## List with Commands with one parameter - -arithList = { -'T' : '00000', # A*B -'TP' : '00001', # A*B+C -'TM' : '00010', # A*B-C -'PT' : '00011', # (A+D)*B -'PTP' : '00100', #(A+D)*B+C -'PTM' : '00101', #(A+D)*B-C -} - -# CONDITIONALS -condList = { - '1' : '000', - 'Z' : '001', - 'S' : '010', - 'NZ' : '011', - 'NS' : '100', - 'F' : '101', - 'NF' : '110', - '0' : '111'} - -#### REGULAR EXPRESSIONS -############################################################################### - -# LIT SHOULD BE LAST -Param_List = { - #'COMMENT' : {'RegEx' : r'//(.*)' , 'RL': '//' , 'RR': '' }, - 'TIME' : {'RegEx' : r'(?<=@)[0-9]+' , 'RL': '@' , 'RR': '' }, - 'ADDR' : {'RegEx' : r'\[(.*)\]' , 'RL': '[' , 'RR': ']' }, - 'UF' : {'RegEx' : r'-uf' , 'RL': '' , 'RR': '' }, - 'WW' : {'RegEx' : r'-ww' , 'RL': '' , 'RR': '' }, - 'WP' : {'RegEx' : r'-wp\(([_a-z\s]*)\)' , 'RL': '-wp(' , 'RR': ')' }, - 'OP' : {'RegEx' : r'-op\(([\s#a-zA-Z0-9+\-<>]*)\)', 'RL': '-op(' , 'RR': ')' }, - 'IF' : {'RegEx' : r'-if\(([A-Z\s]*)\)' , 'RL': '-if(' , 'RR': ')' }, - 'WR' : {'RegEx' : r'-wr\(([a-z\s0-9]*)\)' , 'RL': '-wr(' , 'RR': ')' }, - 'PORT' : {'RegEx' : r'p([0-9]+)' , 'RL': 'p' , 'RR': '' }, - #'REG' : {'RegEx' : r'-reg\(([a-z\s0-9]*)\)' , 'RL': '-reg(' , 'RR': ')' }, - 'LIT' : {'RegEx' : r'(?<=#)[b0-9\-]+' , 'RL': '#' , 'RR': '' }, -} - -Alias_List = { - 'W_FREQ' : {'RegEx' : r'w_freq|r_freq' , 'R': 'w0' }, - 'W_PHASE' : {'RegEx' : r'w_phase|r_phase' , 'R': 'w1' }, - 'W_ENV' : {'RegEx' : r'w_env|r_env' , 'R': 'w2' }, - 'W_GAIN' : {'RegEx' : r'w_gain|r_gain' , 'R': 'w3' }, - 'W_LENGHT' : {'RegEx' : r'w_length|r_length' , 'R': 'w4' }, - 'W_CONF' : {'RegEx' : r'w_conf|r_conf' , 'R': 'w5' }, - 'ZERO' : {'RegEx' : r'zero' , 'R': 's0' }, - 'RAND' : {'RegEx' : r'rand' , 'R': 's1' }, - 'CONF' : {'RegEx' : r's_conf|r_conf' , 'R': 's2' }, - 'STATUS' : {'RegEx' : r's_status|r_status' , 'R': 's3' }, - 'DIVQ' : {'RegEx' : r'div_q' , 'R': 's4' }, - 'DIVR' : {'RegEx' : r'div_r' , 'R': 's5' }, - 'ARITHL' : {'RegEx' : r'arith_l' , 'R': 's6' }, - 'CORE_R1' : {'RegEx' : r'core_r1' , 'R': 's7' }, - 'CORE_R2' : {'RegEx' : r'core_r2' , 'R': 's8' }, - 'PORTL' : {'RegEx' : r'port_l' , 'R': 's9' }, - 'PORTH' : {'RegEx' : r'port_h' , 'R': 's10' }, - 'TUSER' : {'RegEx' : r'tuser' , 'R': 's11' }, - 'CORE_W1' : {'RegEx' : r'core_w1' , 'R': 's12' }, - 'CORE_W2' : {'RegEx' : r'core_w2' , 'R': 's13' }, - 'TIME' : {'RegEx' : r's_time|r_time' , 'R': 's14' }, - 'ADDR' : {'RegEx' : r's_addr|r_addr' , 'R': 's15' }, -} - -regex = { - 'LABEL' : r'[A-Za-z0-9_]+(?=\:)', - 'CMD' : r'^[A-Z_]+', - 'DIRECTIVE' : r'(?<=\.)[A-Z]+', - 'LIT' : r'(?<=#)[0-9]+', - 'CDS' : r'\s*([\w&\+\']+)'} - - -import re - -### CUSTOM LOGGER ### -class Logger(): - INFO = 0 - WARNING = 1 - ERROR = 2 - - __STATUS = { INFO: 'INFO', WARNING: 'WARNING', ERROR: 'ERROR', } - - #__STATUS = [Logger.__dict__] - filename = "assembler.log" - f = open(filename, "w") - f.write("-- Assembler LOG-- \n\n") - f.close() - - level = ERROR - - @staticmethod - def setLevel(level : int) -> None: - if level > 2 : - raise ValueError(f"Logger.setLevel: show_level must be samller than 2 (0-INFO, 1-WARNINGS, 2-ERRORS)") - Logger.level = level - - @staticmethod - def setFile(filename : str) -> None: - Logger.filename = filename - open(filename, "w+").close() - with open(filename, 'a') as f: - f.write("-- Assembler LOG-- \n\n") - - @staticmethod - def log(*args, **kwargs) -> None: - print(*args, **kwargs) - - @staticmethod - def info(locator : str, message : str) -> int: - Logger.__show_message__(Logger.INFO, locator, message) - return 0 - - @staticmethod - def warning(locator : str, message : str) -> int: - Logger.__show_message__(Logger.WARNING, locator, message) - return 0 - - @staticmethod - def error(locator : str, message : str) -> int: - Logger.__show_message__(Logger.ERROR, locator, message) - return 1 - - @staticmethod - def __show_message__(severity : int, locator : str, message : str) -> None: - msg = f"{Logger.__STATUS[severity]} : [{locator}] > {message}" - if (Logger.filename): - Logger.save(msg, Logger.filename) - if (severity >= Logger.level): - print(msg) - - @staticmethod - def save(message : str, filename : str) -> None: - msg_log = message + '\n' - with open(filename, 'a') as f: - f.write(msg_log) - - -def find_pattern(regex : str, text : str): - match = re.search(regex, text) - match = match.group() if (match) else None - return match - -class Assembler(): - @staticmethod - def list2asm(program_list : list, label_dict : dict) -> str: - """ - translates a program list to assembly. - - :program_list (list): each element is a dictionary with all the commands and instructions. - :label_dict (dictionary): dictionary with all labels information found. ({'P_ADDR': 0,'LINE': 0, 'ADDR': 0}) - :returns (str): assembly as a string. - """ - - def process_command(assembler : str, command : dict, p_addr : int) -> str: - """ - processes one command from program list and adds adds it to the assembler string as an instruction. - - :assembler (str): assembler instructions as a string - :command (dict): current instruction from program_list to add in assembler - :p_addr (int): program address of the command in memory. // p_addr stands for program address. - :returns (str): returns the assembler with extra information - """ - assembler += "RET\n" if (command['CMD']=='RET') else f" {command['CMD']} " - if (command['CMD'] == 'DPORT_WR') or (command['CMD']=='WPORT_WR') or (command['CMD']=='TRIG') : - assembler += 'p'+command['DST'] + ' ' - elif ('DST' in command): - assembler += command['DST'] + ' ' - - assembler += f"{command['SRC']} " if ('SRC' in command) else '' - assembler += f"{command['DATA']} " if ('DATA' in command) else '' - assembler += f"{command['C_OP']} " if ('C_OP' in command) else '' - assembler += f"{command['R1']} " if ('R1' in command) else '' - assembler += f"{command['R2']} " if ('R2' in command) else '' - assembler += f"{command['R3']} " if ('R3' in command) else '' - assembler += f"{command['R4']} " if ('R4' in command) else '' - - if ('ADDR' in command): - if (not 'LABEL' in command): - if ( f"&{p_addr}" == command['ADDR'] and command['CMD'] == 'JUMP'): - assembler += "HERE " - else: - assembler += f"[{command['ADDR']}] " - assembler += f"{command['LABEL'] } " if ('LABEL' in command) else '' - assembler += f"-if({command['IF']}) " if ('IF' in command) else '' - assembler += f"-wr({command['WR']}) " if ('WR' in command) else '' - assembler += f"#{command['LIT']} " if ('LIT' in command) else '' - assembler += f"-op({command['OP']}) " if ('OP' in command) else '' - assembler += f"-reg({command['REG']}) " if ('REG' in command) else '' - assembler += f"@{command['TIME']} " if ('TIME' in command) else '' - assembler += f"{command['NUM']} " if ('NUM' in command) else '' - if ('DEN' in command): - assembler += '#' if (command['DEN'][0] != 'r') else '' - assembler += f"{command['DEN']} " - assembler += "-uf" if ('UF' in command and command['UF']=='1') else '' - assembler += '\n' - return assembler - - assembler_code = '' - key_list = list(label_dict.keys()) - val_list = list(label_dict.values()) - for address, command in enumerate(program_list, start=1): - address = program_list['P_ADDR'] if ('P_ADDR' in program_list) else address # set correct instruction address in memory. - # LABEL in the Correct Line - PADDR = '&' + str(address) - if (PADDR in val_list): - label = key_list[val_list.index(PADDR)] - if (label[0:2]=='F_'): - label = '\n' + label - assembler_code += label + ':\n' - - assembler_code = process_command(assembler_code, command, address) - - # ADD Address to commands with LABEL - for line_number, command in enumerate(program_list): - if ('LABEL' in command): - if ( command['LABEL'] in label_dict ) : - command['ADDR'] = label_dict[ command['LABEL'] ] - #print('Label <'+command['LABEL'] +'> changed by address '+command['ADDR']) - else: - Logger.error('LABEL: ', 'Label ' + command['LABEL'] + ' not recognized') - command['LINE'] = line_number - return assembler_code - - @staticmethod - def file_asm2list(filename : str) -> tuple: - """ - takes in a filename to open it and remove all comments. - returns it as a list of strings containing each line parsed. - - :filename (str): file to open and parse - :returns (list): list with all lines of the original file stripped except comments (//). - """ - parsed_file = [] - with open(filename, 'r') as f: - for line in f.readlines(): - comment = line.find("//") - if (comment >= 0): - line = line[:comment] - parsed_file.append(line.strip()) - - program_list, label_dict = Assembler.get_list(parsed_file) - return (program_list, label_dict) - - def str_asm2list(asm_str : str) -> tuple: - x = asm_str.splitlines() - parsed_asm = [] - for line in x: - comment = line.find("//") - if (comment >= 0): - line = line[:comment] - parsed_asm.append(line.strip()) - - program_list, label_dict = Assembler.get_list(parsed_asm) - return (program_list, label_dict) - - - def get_list(asm_str : str) -> tuple: - """ - opens file with assembler and returns the program instructions as a list of dictionaries. - :filename (str): file containing ASM. - :returns (tuple): (program_list, label_dict) - :program_list (list): program instructions as a list of dictionaries. - :label_dict (dict): dictionary with all labels found plus their memory address in program memory. ({'LABEL': '&0'}) - """ - - label_line_idxs = [] - - def label_recognition(file_lines : list) -> tuple: - """ - gets and returns all labels from file. - IMPORTANT: This function updates 'Alias_List'. - - :file_lines (list): file as a list of strings, each element represents a new line. (should be stripped) - :returns (tuple): (error, label_dictionary) - :error (int): if function succeeds error is 0, else it is nonzero. - :label_dictionary (dict): dictionary with all labels found plus their memory address in program memory. ({'LABEL': '&0'}) - """ - - # register 15 predefinition. - label_dict = { 's15': 's15' } - error = 0 - mem_addr = 1 # address 0 goes NOP - # Check if LABEL< DIRETIVE OR INSTRUCTION - for line_number, command in enumerate(file_lines, start=1): - label = find_pattern(regex['LABEL'], command) - directive = find_pattern(regex['DIRECTIVE'], command) - instruction = find_pattern(regex['CMD'], command) - if (label): # add label to label_dict if not already registered. - if label in label_dict: - if (label == 'reg'): - error = Logger.error('LABEL_RECOGNITION', 'reg is not a valid label in line > ' + str(line_number) ) - else: - error = Logger.error('LABEL_RECOGNITION', 'Redefinition of LABEL "' + label + '" in line > ' + str(line_number) ) - else: - label_dict[label] = '&' + str(mem_addr) - label_line_idxs.append(line_number) - elif (directive): # identify Aliases and adds them to Alias_List. - if ( directive == 'ALIAS'): - directives = re.findall(regex['CDS'], command) - Name = 'ALIAS_' + directives[1] - RegEx = directives[1] - Register = directives[2] - comp_PARAM = "r(\d+)|s(\d+)|w(\d+)" - alias_reg = re.findall(comp_PARAM, Register) - if (alias_reg): - Alias_List.update({Name : {'RegEx' : RegEx , 'R': Register } } ) - Logger.info("ALIAS_RECOGNITION",' > ' + Register + ' is called ' + RegEx) - else: - error = Logger.error('ALIAS_RECOGNITION', 'Alias Register not recognized.') - if ( directive == 'CONST'): - directives = re.findall(regex['CDS'], command) - Name = 'CONS_' + directives[1] - RegEx = directives[1] - Value = directives[2] - #comp_PARAM = r'(?<=#)[0-9]+' - comp_PARAM = r'[0-9]+' - cons_val = re.findall(comp_PARAM, Value) - - if (cons_val): - Alias_List.update({Name : {'RegEx' : RegEx , 'R': '#'+Value } } ) - Logger.info("CONSTANT_RECOGNITION",' > ' + Value + ' is called ' + RegEx) - else: - error = Logger.error('CONSTANT_RECOGNITION', 'CONST Value not recognized.') - - - elif ( directive == 'END'): - mem_addr += 1 - elif (instruction): # Identify instructions to correctly set addresses. - if ( instruction in instList.keys() ) : - mem_addr += 1 - else: - error = Logger.error('LABEL_RECOGNITION', 'Command Not Recognized in Line >' + str(line_number)) - show_info = ('\n## ALIAS LIST') - show_info += '\n' + ('###############################') - show_info += '\n' + ('REG > ALIAS NAME\n-----|-------------') - for key in Alias_List: - show_info += '\n' + str( (f"{Alias_List[key]['R']:<3}" + ' > '+ Alias_List[key]['RegEx']) ) - show_info += '\n' + ('###############################') - Logger.info("ALIAS_RECOGNITION",show_info) - - show_info = ('\n## LABEL LIST ') - show_info += '\n' + ('###############################') - show_info += '\n' + ('LABEL NAME > PMEM ADDRESS\n-----------------|------------- ') - for key in label_dict: - if key != 's15': - show_info += '\n' + str( (f"{key:<15}" + ' > ' + label_dict[key]) ) - show_info += '\n' + ('###############################') - Logger.info("LABEL_RECOGNITION",show_info) - - return (error, label_dict) - - def command_recognition(file_lines : list, label_dict : dict) -> tuple: - """ - gets and returns all commands from file. - IMPORTANT: Uses 'Alias_List', 'Param_List'. - - :file_lines (list): file as a list of strings, each element represents a new line. (should be stripped) - :label_dict (dict): dictionary with all labels found plus their memory address in program memory. ({'LABEL': '&0'}). see ' label_recognition() ' - :returns (tuple): (error, program_list) - :error (int): if function succeeds error is 0, else it is nonzero. - :program_list (list): program instructions as a list of dictionaries. - - """ - - program_list = [] - error = 0 - mem_addr = 0 - for line_number, command in enumerate(file_lines, start=1): - command_info = {} - instruction = find_pattern(regex['CMD'], command) - directive = find_pattern(regex['DIRECTIVE'], command) - if ((not command) or (line_number in label_line_idxs)): - continue - elif (directive): - if ( directive == 'END'): - mem_addr += 1 - command_info = { 'LINE' : line_number, - 'P_ADDR' : mem_addr, - 'ADDR' : F"&{str(mem_addr)}", - 'UF' : '0', - 'CMD' : 'JUMP' } - program_list.append(command_info) - Logger.info("COMMAND_RECOGNITION",'END OF PROGRAM ') - elif (instruction): - if ( instruction in instList.keys() ) : - mem_addr += 1 - command_info['P_ADDR'] = mem_addr - # CHECK for Literal Values - ############################################################### - LIT = re.findall(regex['LIT'], command) - if (LIT and len(LIT) == 2 and LIT[0] != LIT[1]): - error = Logger.error('COMMAND_RECOGNITION', 'Literals not equals in Line >' + str(line_number)) - - # CHANGE ALIAS - ############################################################### - for key in Alias_List: - CHANGE = find_pattern(Alias_List[key]['RegEx'], command) - command = command.replace(CHANGE, Alias_List[key]['R']) if CHANGE else command - - # Extract PARAMETERS - ############################################################### - if (error == 0): - command_info['LINE'] = line_number # Stores Line Number for ERROR Messages - for key in Param_List: - PARAM = re.findall(Param_List[key]['RegEx'], command) - if PARAM: - if (len(PARAM) >1): - error = Logger.error('COMMAND_RECOGNITION', 'Duplicated Parameter ' + key +' in line > '+str(line_number)) - command_info[key] = PARAM[0].strip() - aux = Param_List[key]['RL'] + PARAM[0] + Param_List[key]['RR'] - command = command.replace(aux, '') - - # COMMANDS PARAMETERS CHECK - ############################################################### - if (error == 0): - CMD_DEST_SOURCE = re.findall(regex['CDS'], command) - ########################################################### - ## LITERAL CHECK - if ('LIT' in command_info) : - if (command_info['LIT'][0] == 'b'): - command_info['LIT'] = str(int(command_info['LIT'][1:],2)) - ########################################################### - if ('UF' in command_info) : - command_info['UF'] = '1' - if not('OP' in command_info): - error = Logger.error("COMMAND_RECOGNITION", "No Operation < -op() > set for Flag Update < -uf > in Line " + str(line_number)) - #else: - # command_info['UF'] = '0' - ########################################################### - #if (CMD_DEST_SOURCE[0] == 'REG_WR'): - # if ( 'WR' in command_info ): - # if (command_info['DST'] != 'r_wave'): - # error = Logger.error("COMMAND_RECOGNITION", "No <-wr()> allowed when Writting Data Register in Line " + str(line_number)) - ########################################################### - elif (CMD_DEST_SOURCE[0] == 'DMEM_WR'): - if ( not('ADDR' in command_info) ): - error = Logger.error("COMMAND_RECOGNITION", "Memory Address < [] > not set in Line " + str(line_number)) - ########################################################### - elif (CMD_DEST_SOURCE[0] == 'WMEM_WR'): - if 'PORT' in command_info: - command_info['DST'] = command_info['PORT'] - else: - error = Logger.error("COMMAND_RECOGNITION", "No Port Address < -p() > in Line " + str(line_number)) - elif (CMD_DEST_SOURCE[0] == 'WMEM_WR'): - if ( ('WP' in command_info) and not('PORT' in command_info) ): - error = Logger.error("COMMAND_RECOGNITION", "No Port Address < -p() > in Line " + str(line_number)) - ########################################################### - elif (CMD_DEST_SOURCE[0] =='DPORT_WR') or (CMD_DEST_SOURCE[0] =='WPORT_WR') \ - or (CMD_DEST_SOURCE[0] =='TRIG') : - if ( not('PORT' in command_info) ): - error = Logger.error("COMMAND_RECOGNITION", "No port in PORT_WR Instruction in line " + str(line_number)) - ########################################################### - elif ( (CMD_DEST_SOURCE[0] == 'OUT_DATA') or (CMD_DEST_SOURCE[0] == 'OUT_WAVE') ): - if ('IF' in command_info): - error = Logger.error("COMMAND_RECOGNITION", "Not allowed Conditional < -if() > with Port Writting cmd in Line " + str(line_number)) - if ('WR' in command_info): - error = Logger.error("COMMAND_RECOGNITION", "Not allowed Write Register < -wr() > with Port Writting cmd in Line " + str(line_number)) - - - # GET COMMAND DESTINATION SOURCE - ############################################################### - if (error == 0): - CMD_DEST_SOURCE = re.findall(regex['CDS'], command) - command_info['CMD'] = CMD_DEST_SOURCE[0] - ## MORE THAN ONE SOURCE - if ( len(CMD_DEST_SOURCE) > 3) : - if (CMD_DEST_SOURCE[0] == 'ARITH') : - command_info['C_OP'] = CMD_DEST_SOURCE[1] - command_info['R1'] = CMD_DEST_SOURCE[2] - command_info['R2'] = CMD_DEST_SOURCE[3] - if ( len(CMD_DEST_SOURCE) > 4) : - command_info['R3'] = CMD_DEST_SOURCE[4] - if ( len(CMD_DEST_SOURCE) > 5) : - command_info['R4'] = CMD_DEST_SOURCE[5] - elif (CMD_DEST_SOURCE[0] =='CUSTOM') : - if (len(CMD_DEST_SOURCE) == 6): - command_info['C_OP'] = CMD_DEST_SOURCE[1] - command_info['R1'] = CMD_DEST_SOURCE[2] - command_info['R2'] = CMD_DEST_SOURCE[3] - command_info['R3'] = CMD_DEST_SOURCE[4] - command_info['R4'] = CMD_DEST_SOURCE[5] - else: - error = Logger.error("COMMAND_RECOGNITION", "CUSTOM Command Should have Op and 4 parameters in line " + str(line_number) + " (possible missing [])") - elif (CMD_DEST_SOURCE[0] == 'REG_WR') and (CMD_DEST_SOURCE[2] == 'label' ) : - command_info['DST'] = CMD_DEST_SOURCE[1] - command_info['SRC'] = CMD_DEST_SOURCE[2] - if (CMD_DEST_SOURCE[3] in label_dict ) : - command_info['ADDR'] = label_dict[CMD_DEST_SOURCE[3]] - error = Logger.info('COMMAND_RECOGNITION', 'REG_WR command source label: '+CMD_DEST_SOURCE[3] +' replaced by value ' + command_info['ADDR'] + ' in line ' + str(line_number)) - else: - error = Logger.error('COMMAND_RECOGNITION', 'Label: '+CMD_DEST_SOURCE[3]+' Not defined in line ' + str(line_number)) - else: - error = Logger.error("COMMAND_RECOGNITION", "Parameter Error (More than 3) in line " + str(line_number) + " (possible missing [])") - ## ONE SOURCE - elif ( len(CMD_DEST_SOURCE) == 3) : - if (CMD_DEST_SOURCE[0] == 'REG_WR'): - if (CMD_DEST_SOURCE[2] == 'label' ) : - error = Logger.error("COMMAND_RECOGNITION", "Missing label in line " + str(line_number)) - else: - command_info['DST'] = CMD_DEST_SOURCE[1] - command_info['SRC'] = CMD_DEST_SOURCE[2] - elif (CMD_DEST_SOURCE[0] =='DPORT_WR') : - if ( int(command_info['PORT']) > 3): - error = Logger.error("COMMAND_RECOGNITION", "Data Port Read max value is 3 in line " + str(line_number)) - else: - command_info['DST'] = command_info['PORT'] - command_info.pop('PORT') - command_info['SRC'] = CMD_DEST_SOURCE[1] - command_info['DATA'] = CMD_DEST_SOURCE[2] - - elif ( (CMD_DEST_SOURCE[0] == 'TIME') \ - or (CMD_DEST_SOURCE[0] == 'OUT_DATA')): - command_info['DST'] = CMD_DEST_SOURCE[1] - command_info['SRC'] = CMD_DEST_SOURCE[2] - elif (CMD_DEST_SOURCE[0] == 'DIV') : - command_info['NUM'] = CMD_DEST_SOURCE[1] - command_info['DEN'] = CMD_DEST_SOURCE[2] - else: - error = Logger.error("COMMAND_RECOGNITION", "Parameter Error in line " + str(line_number) + " Check for .ALIAS") - - ## NO SOURCE OR -- SOURCE IN EXTRACTED PARAMETER - elif ( len(CMD_DEST_SOURCE) == 2) : - if (CMD_DEST_SOURCE[0] =='DMEM_WR' ) : - command_info['SRC'] = CMD_DEST_SOURCE[1] - command_info['DST'] = '[' + command_info['ADDR'] + ']' - #command_info.pop('ADDR') - elif (CMD_DEST_SOURCE[0] =='WPORT_WR') : - command_info['SRC'] = CMD_DEST_SOURCE[1] - command_info['DST'] = command_info['PORT'] - elif (CMD_DEST_SOURCE[0] =='FLAG') : - command_info['SRC'] = CMD_DEST_SOURCE[1] - elif (CMD_DEST_SOURCE[0] =='NET') : - command_info['SRC'] = CMD_DEST_SOURCE[1] - elif (CMD_DEST_SOURCE[0]=='TIME'): # DST is ADDR - command_info['CMD'] = CMD_DEST_SOURCE[0] - command_info['DST'] = CMD_DEST_SOURCE[1] - elif (CMD_DEST_SOURCE[0]=='DIV'): - if ('LIT' in command_info): - command_info['CMD'] = CMD_DEST_SOURCE[0] - command_info['NUM'] = CMD_DEST_SOURCE[1] - else: - error = Logger.error("COMMAND_RECOGNITION", "Parameter Error in line " + str(line_number)) - elif (CMD_DEST_SOURCE[0] =='TRIG'): - command_info['CMD'] = CMD_DEST_SOURCE[0] - command_info['SRC'] = CMD_DEST_SOURCE[1] - if ( int(command_info['PORT']) > 7): - error = Logger.error("COMMAND_RECOGNITION", "Trigger Port max value is 7 in line " + str(line_number)) - else: - command_info['DST'] = command_info['PORT'] - command_info.pop('PORT') - - elif (CMD_DEST_SOURCE[0]=='JUMP' or CMD_DEST_SOURCE[0]=='CALL'): - command_info['CMD'] = CMD_DEST_SOURCE[0] - if CMD_DEST_SOURCE[1] in label_dict: - if (CMD_DEST_SOURCE[1] == 's15'): - Logger.info("COMMAND_RECOGNITION", "BRANCH to r_addr > line " + str(line_number)) - else: - Logger.info("COMMAND_RECOGNITION", "BRANCH to label : " + CMD_DEST_SOURCE[1] + " is done to address " + label_dict[CMD_DEST_SOURCE[1]] + " > line " + str(line_number)) - command_info['ADDR'] = label_dict[CMD_DEST_SOURCE[1]] - command_info['LABEL'] = CMD_DEST_SOURCE[1] - else: - if (CMD_DEST_SOURCE[1] == 'PREV'): - command_info['ADDR'] = '&'+str(mem_addr-1) - elif (CMD_DEST_SOURCE[1] == 'HERE'): - command_info['ADDR'] = '&'+str(mem_addr) - elif (CMD_DEST_SOURCE[1] == 'NEXT'): - command_info['ADDR'] = '&'+str(mem_addr+1) - elif (CMD_DEST_SOURCE[1] == 'SKIP'): - command_info['ADDR'] = '&'+str(mem_addr+2) - else: - error = Logger.error("COMMAND_RECOGNITION", "Branch Address ERROR (Should be a label) in line " + str(line_number)) - else: - error = Logger.error("COMMAND_RECOGNITION", "Parameter Error (2 Parameters) in line " + str(line_number)) - ## NO DESTINATION OR -- DESTINATION / SOURCE IN EXTRACTED PARAMETER - elif ( len(CMD_DEST_SOURCE) == 1): - if (CMD_DEST_SOURCE[0] =='NOP') \ - or (CMD_DEST_SOURCE[0] =='ARITH') \ - or (CMD_DEST_SOURCE[0] =='TEST') \ - or (CMD_DEST_SOURCE[0] =='RET') : - command_info['CMD'] = CMD_DEST_SOURCE[0] - elif (CMD_DEST_SOURCE[0] =='DPORT_RD') : - command_info['CMD'] = CMD_DEST_SOURCE[0] - if ('PORT' in command_info): - if ( int(command_info['PORT']) > 7): - error = Logger.error("COMMAND_RECOGNITION", "Data Port Read max value is 7 in line " + str(line_number)) - else: - command_info['DST'] = command_info['PORT'] - command_info.pop('PORT') - else: - error = Logger.error("COMMAND_RECOGNITION", "No Port for DPORT_RD in line " + str(line_number)) - - elif (CMD_DEST_SOURCE[0]=='WMEM_WR'): - command_info['CMD'] = CMD_DEST_SOURCE[0] - if ('ADDR' in command_info): - command_info['DST'] = command_info['ADDR'] - command_info.pop('ADDR') - else: - error = Logger.error("COMMAND_RECOGNITION", "No Address for WMEM_WR in line " + str(line_number)) - elif ( (CMD_DEST_SOURCE[0]=='JUMP') or (CMD_DEST_SOURCE[0]=='CALL')): - if ('ADDR' in command_info): - command_info['CMD'] = CMD_DEST_SOURCE[0] - command_info['ADDR'] = command_info['ADDR'] - else: - error = Logger.error("COMMAND_RECOGNITION", "Parameter Error in line " + str(line_number)) - elif (CMD_DEST_SOURCE[0]=='WAIT'): - Logger.info("COMMAND_RECOGNITION", "IS WAIT adding Instruction") - mem_addr = mem_addr + 1 - command_info['CMD'] = CMD_DEST_SOURCE[0] - command_info['ADDR'] = '&'+str(mem_addr) - else: - error = Logger.error("COMMAND_RECOGNITION", "Parameter Error (0 Parameter ) in line " + str(line_number)) - else: - error = Logger.error("COMMAND_RECOGNITION", "Error Processing Line " + str(line_number)) + ". Command not recognized." - - - # ADD CMD TO PROGRAM - ########################################################### - if (error == 1): - break - else: - program_list.append(command_info) - else: - break - - - - else: - error = Logger.error("COMMAND_RECOGNITION", f"< {instruction} > is not a Recognized Command in Line " + str(line_number)) - else: - error = Logger.error("COMMAND_RECOGNITION", "Not a Command in Line >" + str(line_number)) - return (error, program_list) - - - ##### START ASSEMBLER TO LIST - Logger.info("ASM2LIST", "##### STEP_1 - LABEL RECOGNITION") - error, label_dict = label_recognition(asm_str) - - if (error): - Logger.warning("LABEL_RECOGNITION", "Errors found!") - return (None, None) - - Logger.info("ASM2LIST", "##### STEP_2 - COMMAND RECOGNITION") - error, program_list = command_recognition(asm_str, label_dict) - - if (error): - Logger.warning("COMMAND_RECOGNITION", "Errors found!") - return (None, None) - - return (program_list, label_dict) - - @staticmethod - def list2bin(program_list : list, label_dict : dict = {}, save_unparsed_filename : str = "") -> list: - """ - translates a program list to binary form. - :program_list (list): each element is a dictionary with all the commands and instructions. see ' asm2list() ' - :label_dict (dict): dictionary with label information only if program_list contains labels. - :save_unparsed_filename (str): if not null, opens this file and saves unparsed binary ('_' not removed). - :returns (tuple): (error, binary_program) - :error (int): if function succeeds error is 0, else it is nonzero. - :binary_program_list (list): each element is a string with 0s and 1s representing the binary program - """ - def parse_lines_and_labels(program_list : list, label_dict : dict) -> None: - for line_number, command in enumerate(program_list, start=1): - if (('LABEL' in command) and (command['LABEL'] in label_dict) and 'ADDR' not in command): - command['ADDR'] = label_dict[ command['LABEL'] ] - if not 'LINE' in command: - command['LINE'] = line_number - - Logger.info("LIST2BIN", "##### LIST 2 BIN") - - parse_lines_and_labels(program_list, label_dict) - - # first line is NOP - binary_program_list = ['000_000__000___00__0_00_00______00000000000_000000_________00000000000000000000000000000000_0000000'] - error = 0 - CODE = 'x' - for command in program_list: - if ('CMD' in command): - if not ('UF' in command): - command['UF'] = '0' - ############################################################################### - if command['CMD'] == 'NOP': - CODE = '000_000__000___00__0_00_00______00000000000_000000_________00000000000000000000000000000000_0000000' - ############################################################################### - elif (command['CMD'] == 'REG_WR'): - error, CODE = Instruction.REG_WR(command) - ############################################################################### - elif command['CMD'] == 'DMEM_WR': - error, CODE = Instruction.DMEM_WR(command) - ############################################################################### - elif command['CMD'] == 'WMEM_WR': - error, CODE = Instruction.WMEM_WR(command) - ############################################################################### - elif command['CMD'] == 'JUMP': - error, CODE = Instruction.BRANCH(command, '00') - ############################################################################### - elif command['CMD'] == 'WAIT': - command['TIME'] = str(int(command['TIME'])-10) - command['UF'] = '1' - command['IF'] = '1' - command['OP'] = 's11-#' + command['TIME'] - error, CODE = Instruction.CFG(command) - if (error==0): - binary_program_list.append(CODE) - command['IF'] = 'S' - error, CODE = Instruction.BRANCH(command, '00') - ############################################################################### - elif command['CMD'] == 'CALL': - error, CODE = Instruction.BRANCH(command, '10') - ############################################################################### - elif command['CMD'] == 'RET': - error, CODE = Instruction.BRANCH(command, '11') - ############################################################################### - elif command['CMD']=='DPORT_WR' or command['CMD'] == 'DPORT_RD' or command['CMD'] == 'WPORT_WR': - error, CODE = Instruction.PORT_WR(command) - ############################################################################### - elif command['CMD']=='TRIG': - error, CODE = Instruction.PORT_WR(command) - ############################################################################### - elif command['CMD'] == 'TIME': - error, CODE = Instruction.CTRL(command) - ############################################################################### - elif command['CMD'] == 'TEST': - command['UF'] = '1' - error, CODE = Instruction.CFG(command) - ############################################################################### - elif command['CMD'] == 'DIV': - error, CODE = Instruction.CTRL(command) - ############################################################################### - elif command['CMD'] == 'FLAG': - error, CODE = Instruction.CTRL(command) - ############################################################################### - elif command['CMD'] == 'NET': - error, CODE = Instruction.CTRL(command) - ############################################################################### - elif command['CMD'] == 'CUSTOM': - error, CODE = Instruction.CTRL(command) - ############################################################################### - elif command['CMD'] == 'ARITH': - error, CODE = Instruction.ARITH(command) - else: - error = Logger.error("COMMAND_TRANSLATION", "Command Listed but not programmed > " + command['CMD']) - else: - error = Logger.error("COMMAND_TRANSLATION", "No Command at line " + str(command['LINE'])) - ################################################################################### - - length = CODE.count('0') + CODE.count('1') - if (length != 72): - error = 72 - Logger.error("COMMAND_TRANSLATION", f"{CODE}\nINSTRUCTION LENGTH > {length} at line {command['LINE']}") - - if (error): - return [] - binary_program_list.append(CODE) - - if (save_unparsed_filename): - with open(save_unparsed_filename, "w+") as f: - for line in binary_program_list: - f.write(f"{line}\n") - - binary_array = [] - for line_bin in binary_program_list: - tmp = line_bin.replace('_', '') - b0 = '0b'+tmp[40:72] - n0 = int(b0,2) - b1 = '0b'+ tmp[8:40] - n1 = int(b1,2) - b2 = '0b'+tmp[:8] - n2 = int(b2,2) - binary_line = [n0, n1, n2, 0, 0, 0, 0, 0] - binary_array.append(binary_line) - return binary_program_list, binary_array - - def file_asm2bin(filename : str, save_unparsed_filename : str = "") -> list: - """ opens file with assembler and returns the binary - - :filename (str): file containing ASM. - :save_unparsed_filename (str): if not null, opens this file and saves unparsed binary ('_' not removed). - - """ - program_list, label_dict = Assembler.file_asm2list(filename) - if program_list: - binary_program_list = Assembler.list2bin(program_list, save_unparsed_filename) - else: - binary_program_list = [[],[]] - Logger.error("ASM2BIN", "Program list with errors.") - return binary_program_list - def str_asm2bin(str_asm : str, save_unparsed_filename : str = "") -> list: - """ get STR with assembler and returns the binary - - :asm_str (str): string ASM. - :save_unparsed_filename (str): if not null, opens this file and saves unparsed binary ('_' not removed). - - """ - program_list, label_dict = Assembler.str_asm2list(str_asm) - if program_list: - binary_program_list = Assembler.list2bin(program_list, save_unparsed_filename) - else: - binary_program_list = [[],[]] - Logger.error("ASM2BIN", "Program list with errors.") - return binary_program_list - -def integer2bin(strin : str, bits : int = 8) -> str: - """ - receives an integer in str format and returns their bits as a string. - - :strin (str): string with an integer - :bits (int): number of bits to return - :returns (str): bits as a string - """ - - minv = -2**(bits-1) - maxv = 2**(bits-1) - 1 - # Check if hex string. - m = re.search("^0x", strin, flags=re.MULTILINE) - if m: - # Special case for hex number. - dec = int(strin, 16) - # Convert to binary. - fmt = "{0:0" + str(bits) + "b}" - binv = fmt.format(dec) - return binv - else: - dec = int(strin, 10) - # Check max. - if dec < minv: - Logger.error("integer2bin", "number %d is smaller than %d" % (dec, minv)) - return None - # Check max. - if dec > maxv: - Logger.error("number %d is bigger than %d" % (dec, maxv)) - return None - # Check if number is negative. - if dec < 0: - dec = dec + 2**bits - # Convert to binary. - fmt = "{0:0" + str(bits) + "b}" - binv = fmt.format(dec) - return binv - -def get_reg_addr (reg : str, Type : str) -> tuple: - """ - :returns (tuple): (error, register_address). - """ - error = 0 - REG = re.findall('r(\d+)|s(\d+)|w(\d+)', reg) - if (REG): - REG = REG[0] - if (Type=='Source'): - if (REG[0]): ## is R_Reg - reg_addr = '0_00'+integer2bin(REG[0], 5) - elif (REG[1]): ## is S_Reg - reg_addr = '0_10'+integer2bin(REG[1], 5) - elif (REG[2]): ## is W_Reg - reg_addr = '0_01'+integer2bin(REG[2], 5) - elif (Type=='Dest'): - if (REG[0]): ## is Data Register - reg_addr = '00'+integer2bin(REG[0], 5) - elif (REG[1]): ## is Special Register - reg_addr = '10'+integer2bin(REG[1], 5) - elif (REG[2]): ## is WaveForm Register - reg_addr = '01'+integer2bin(REG[2], 5) - elif (Type=='Addr'): - if (REG[0]): ## is R_Reg - reg_addr = '0'+integer2bin(REG[0], 5) - elif (REG[1] or REG[2]): ## is S_Reg or W_Reg - error = Logger.error('get_reg_addr', 'Address format error, should be Data Register (Starts with r)' ) - else: - reg_addr = 'X' - error = Logger.error('get_reg_addr', 'Register not Recognized (Registers Starts with r, s or w) ' ) - - return [error, reg_addr] - -############################################################################### -## BASIC COMANDS -############################################################################### -class Instruction(): - #PROCESSING - @staticmethod - def __PROCESS_CONDITION(command : dict) -> tuple: - error = 0 - cond = '' - if ('IF' in command ): - if command['IF'] in condList: - cond = condList[command['IF']] - else: - error = Logger.error('Parameter.IF', 'Posible CONDITIONS are (' + ', '.join(list(condList.keys())) + ') in instruction ' + str(command['LINE']) ) - else: - cond = '000' - return error, cond - - @staticmethod - def __PROCESS_WR(command : dict) -> tuple: #### Get WR - error = 0 - RD = '0000000' - Rdi=Wr = '0' - if ('WR' in command ): - Wr = '1' - regex_inside_parenthesis = r'\s*([\w]+)' - DEST_SOURCE = re.findall(regex_inside_parenthesis, command['WR']) - #### SOURCE - if (len(DEST_SOURCE) == 2): - if (DEST_SOURCE[1] == 'op'): - if ('OP' in command ): - Rdi = '0' - else: - error = Logger.error('Parameter.WR', 'Pperation < -op() > option not found in instruction ' + str(command['LINE']) ) - elif (DEST_SOURCE[1] == 'imm'): - if ('LIT' in command ): - Rdi = '1' - else: - error = Logger.error('Parameter.WR', 'Literal Value not found in instruction ' + str(command['LINE']) ) - else: - error = Logger.error('Parameter.WR', 'Posible Source Dest for <-wr(reg source)> are (op, imm) in instruction ' + str(command['LINE']) ) - else: - error = Logger.error('Parameter.WR', 'Write Register error <-wr(reg source) in instruction ' + str(command['LINE']) ) - #### DESTINATION REGISTER - error, RD = get_reg_addr (DEST_SOURCE [0], 'Dest') - return error, Wr, Rdi, RD - - @staticmethod - def __PROCESS_WP (command : dict) -> tuple: - #### WRITE PORT - error=0 - Wp=Sp='0' - Dp='000000' - if ('WP' in command ): - #### DESTINATION PORT - if ('PORT' in command): - Wp='1' - Dp = integer2bin(command['PORT'], 6) - if (command['WP'] == 'r_wave'): - Sp = '1' - elif (command['WP'] == 'wmem'): - Sp = '0' - else: - error = Logger.error('Parameter.WP', 'Source Wave Port not recognized (wreg, r_wave) ' + str(command['LINE']) ) - else: - error = Logger.error('Parameter.WP', 'Port Address not recognized < pX > ' + str(command['LINE']) ) - return error, Wp, Sp, Dp - - @staticmethod - def __PROCESS_SOURCE (command : dict) -> tuple: - error = 0 - df = alu_op = 'X' - rsD0 = rsD1 = DataImm ='' - FULL = (command['CMD']=='REG_WR') and (command['SRC']=='op') - if ('OP' in command): - error = 0 - comp_OP_PARAM = "r(\d+)|s(\d+)|w(\d+)|#(-?\d+)|#b(\d+)|\s*([A-Z]{3}|[A-Z><]{2}|\+|\-)" - param_op = re.findall(comp_OP_PARAM, command['OP']) - DataImm = rsD1 = '' - if (len(param_op)==1 ) : # COPY REG - df = '01' - rsD1 = '0_1000000' - if ('LIT' in command): - DataImm = '_'+integer2bin(command ['LIT'], 16) - else: - DataImm = '0000000000000000' - if FULL: - alu_op = '0000' - else: - alu_op = '00' - ## CHECK FOR ONLY OPERAND (COPY REG) (ADD S0) - if (param_op[0][0]): ## is R_Reg - rsD0 = '0_00'+integer2bin(param_op[0][0], 5) - elif (param_op[0][1]): ## is S_Reg - rsD0 = '0_10'+integer2bin(param_op[0][1], 5) - elif (param_op[0][2]): ## is W_Reg - rsD0 = '0_01'+integer2bin(param_op[0][2], 5) - elif (param_op[0][3] or param_op[0][4]): ## is Decimal or Binary - error = Logger.error('Parameter.SRC', 'Operand can not be a Literal.') - else: - error = Logger.error('Parameter.SRC', 'Operand not recognized.') - elif (len(param_op)==2 ) : - operation = param_op[0][5] - if (FULL): - if (operation in aluList_op) : #ALU LIST ONE PARAMETER - df = '10' - alu_op = aluList[param_op[0][5]] - DataImm = '000000000000000000000000' - ## CHECK FOR OPERAND (ALU_IN_A > rsD) - if (param_op[1][0]): ## is R_Reg - rsD0 = '0_00'+integer2bin(param_op[1][0], 5) - elif (param_op[1][1]): ## is S_Reg - rsD0 = '0_10'+integer2bin(param_op[1][1], 5) - elif (param_op[1][2]): ## is W_Reg - rsD0 = '0_01'+integer2bin(param_op[1][2], 5) - elif (param_op[1][3] or param_op[0][4] ): ## is Decimal or Binary - error = Logger.error('Parameter.SRC', 'Operand can not be a Literal in instruction ' + str(command['LINE']) ) - else: - error = Logger.error('Parameter.SRC', 'Operantion Not Recognized > ' + str(command['OP']) ) - else: - error = Logger.error('Parameter.SRC', '1-Operantion Not Allowed > ' + str(command['OP']) +' in instruction ' + str(command['LINE']) ) - ## ABS Should be on rsD1 - if (param_op[0][5] == 'ABS') : - df = '01' - rsD1 = rsD0 - rsD0 = '0_0000000' - DataImm = '0000000000000000' - - elif (len(param_op)==3 ) : - ## CHECK FOR FIRST OPERAND (ALU_IN_A > rsD) - if (param_op[0][0]): ## is R_Reg - rsD0 = '0_00'+integer2bin(param_op[0][0], 5) - elif (param_op[0][1]): ## is S_Reg - rsD0 = '0_10'+integer2bin(param_op[0][1], 5) - elif (param_op[0][2]): ## is W_Reg - rsD0 = '0_01'+integer2bin(param_op[0][2], 5) - elif (param_op[1][3] or param_op[0][4] ): ## is Decimal or Binary - error = Logger.error('Parameter.SRC', 'First Operand can not be a Literal.') - else: - error = Logger.error('Parameter.SRC', 'First Operand not recognized.') - ## CHECK FOR SECOND OPERAND (ALU_IN_B > Imm|rsC) - if (error == 0): - if ( (param_op[2][0]) or (param_op[2][1]) or (param_op[2][2]) ): ## REG OP REG - if ('LIT' in command): - Logger.info('Parameter.SRC', 'With < -op() > imm value should be 16 Bits in instruction ' + str(command['LINE']) ) - if ( int(command ['LIT']) >= 65535): - error = Logger.error('Parameter.SRC', ('Literal '+ command ['LIT'] + ' should be 16 Bits.') ) - else: - Logger.info("Parameter.SRC", "[OK] Literal " + command ['LIT'] + " can be represented with 16 Bits.") - df = '01' - DataImm = '_'+integer2bin(command ['LIT'], 16) - else: - DataImm = '0000000000000000' - if (param_op[2][0]): ## is R_Reg - df = '01' - rsD1 = '0_00'+integer2bin(param_op[2][0], 5) - elif (param_op[2][1]): ## is S_Reg - df = '01' - rsD1 = '0_10'+integer2bin(param_op[2][1], 5) - elif (param_op[2][2]): ## is W_Reg - df = '01' - rsD1 = '0_01'+integer2bin(param_op[2][2], 5) - elif (param_op[2][3]): ## is Decimal - df = '10' - DataImm = '_'+ integer2bin(param_op[2][3], 24) - elif (param_op[2][4]): ## is Binary - df = '10' - literal = str(int(param_op[2][4],2)) - DataImm = '_'+ integer2bin(literal, 24) - else: - error = Logger.error('Parameter.SRC', 'Second Operand not recognized in instruction ' + str(command['LINE']) ) - ## CHECK FOR OPERATION - if (error == 0): - operation = param_op[1][5] - if (FULL): - if operation in aluList: - alu_op = aluList[ operation ] - else: - error = Logger.error('Parameter.SRC', 'ALU {Full List} Operation Not Recognized in instruction ' + str(command['LINE']) ) - else: - if operation in aluList_s: - alu_op = aluList_s[ operation ] - else: - error = Logger.error('Parameter.SRC', 'ALU {Reduced List} Operation Not Recognized in instruction ' + str(command['LINE']) ) - ## LITERAL and NO OP - elif ('LIT' in command): - df = '11' - alu_op = '00' - DataImm = '__'+integer2bin(command['LIT'], 32) - else: - df = '11' - alu_op = '00' - DataImm = '__00000000000000000000000000000000' - Data_Source = rsD0 +'_'+ rsD1 +'_'+ DataImm - return error, Data_Source, alu_op, df - - @staticmethod - def __PROCESS_MEM_ADDR (ADDR_CMD : str) -> tuple: - error = 0 - AI = '0' - RsF = RsE = 'x' - comp_ADDR_FMT = "r(\d+)|&(\d+)|\s*([A-Z]{3}|[A-Z]{2}|\+|\-)" - param_op = re.findall(comp_ADDR_FMT, ADDR_CMD) - if (len(param_op)==1 ) : - ## CHECK FOR OPERAND - RsE = '000000' - if (param_op[0][0]): ## is R_Reg - RsF = '00000_' + integer2bin(param_op[0][0], 6) - elif (param_op[0][1]): ## is Literal - RsF = '_'+ integer2bin(param_op[0][1], 11) - AI = '1' - else: - error = Logger.error('Parameter.MEM_ADDR', 'First Operand not recognized.') - elif (len(param_op)==3 ) : - ## CHECK FOR FIRST OPERAND - if (param_op[0][0]): ## is R_Reg - RsE = integer2bin(param_op[0][0], 6) - elif (param_op[0][1]): ## is Literal - error = Logger.error('Parameter.MEM_ADDR', 'First Operand can not be a Literal.') - ## CHECK FOR SECOND OPERAND - if (error == 0): - if (param_op[2][0]): ## is R_Reg - RsF = '00000_' + integer2bin(param_op[2][0], 6) - elif (param_op[2][1]): ## is Literal - RsF = '_'+ integer2bin(param_op[2][1], 11) - AI = '1' - ## CHECK FOR PLUS - if (error == 0): - if (param_op[1][2]) != '+': ## is R_Reg - error = Logger.error('Parameter.MEM_ADDR', 'Address Operand should be < + >.') - else: - error = Logger.error('Parameter.MEM_ADDR', 'Address format error, should be Data Register(r) or Literal(&)') - return error, RsF, RsE, AI - - - - #INSTRUCTIONS - @staticmethod - def REG_WR (current : dict) -> tuple: - AI = '0' - error = 0 - RdP = '000000' - ######### CONDITIONAL - error, COND = Instruction.__PROCESS_CONDITION(current) - ######### SOURCES - if (error==0): - #### SOURCE ALU - if (current ['SRC'] == 'op'): - if ('OP' in current ): - error, DATA, alu_op, DF = Instruction.__PROCESS_SOURCE (current) - CFG = '00__' + current ['UF'] + '__'+ alu_op - ADDR = '_00000000000_000000' # 17 Bits 11 + 6 - else: - error = Logger.error('Instruction.REG_WR', 'No < -op() > for Operation Writting in instruction ' + str(current['LINE'])) - #### SOURCE IMM - elif (current ['SRC'] == 'imm'): - #### Get Data Source - if ('LIT' in current ): - error, DATA, alu_op, DF = Instruction.__PROCESS_SOURCE(current) - CFG = '11__' + current ['UF'] + '_00_' + alu_op - ADDR = '_00000000000_000000' # 17 Bits 11 + 6 - else: - error = Logger.error('Instruction.REG_WR', 'No Literal value for immediate Assignation (#) in instruction ' + str(current['LINE']) ) - #### SOURCE LABEL - elif (current ['SRC'] == 'label'): - #### Get Data Source - if ('ADDR' in current): - comp_addr = "&(\d+)" - address = re.findall(comp_addr, current['ADDR']) - if (address[0]): # LITERAL - ADDR = '_00000000000_000000' # 17 Bits 11 + 6 - DATA = '0000000000000000_' + integer2bin(address[0], 16) - DF = '11' - CFG = '11__' + current ['UF'] + '_00_00' - else: - error = Logger.error('Instruction.REG_WR', 'No Literal value for immediate Assignation (#) in instruction ' + str(current['LINE']) ) - #### SOURCE DATA MEMORY - elif (current ['SRC'] == 'dmem'): - #### Get Data Source - error, DATA, alu_op, DF = Instruction.__PROCESS_SOURCE(current) - CFG = '01__' + current ['UF'] + '_00_' + alu_op - #### Get ADDRESS - if error == 0: - error, RsF, RsE, AI = Instruction.__PROCESS_MEM_ADDR (current ['ADDR']) - ADDR = RsF + '_' + RsE - CFG = '01__' + current ['UF'] + '_00_'+alu_op - #### SOURCE WAVE MEM - elif (current ['SRC'] == 'wmem'): - if (current ['DST'] == 'r_wave'): - if (COND != '000'): - error = Logger.error('Instruction.REG_WR', 'Wave Register Write is not conditional < -if() > in instruction ' + str(current['LINE']) ) - else: - WW = WP = '0' - if ('WW' in current): - WW = '1' - #### WRITE PORT - error, WP, Sp, RdP = Instruction.__PROCESS_WP(current) - COND = WW + Sp + WP - #### WRITE REGISTER - if (error==0): - Wr = Rdi = '0' - error, Wr, Rdi, RD = Instruction.__PROCESS_WR(current) - #### Get Data Source - if (error==0): - error, DATA, alu_op, DF = Instruction.__PROCESS_SOURCE(current) - #### Get ADDRESS - if error == 0: - if ('ADDR' in current): - error, RsF, RsE, AI = Instruction.__PROCESS_MEM_ADDR (current ['ADDR']) - if (RsE != '000000'): - error = Logger.error('Instruction.REG_WR', 'Wave Memory Addres Error Source Should be LIT or Reg in instruction ' + str(current['LINE']) ) - ADDR = RsF + '_' + RdP - else: - error = Logger.error('Instruction.REG_WR', 'No addres for source in instruction ' + str(current['LINE']) ) - else: - error = Logger.error('Instruction.REG_WR', 'Wave Memory Source Should have a Wave Register Destination ' + str(current['LINE']) ) - else: - error = Logger.error('Instruction.REG_WR', 'Posible REG_WR sources are (op, imm, dmem, wmem, label ) in instruction ' + str(current['LINE']) ) - ######### DESTINATION REGISTER - if (error==0): - comp_OP_PARAM = "r(\d+)|s(\d+)|w(\d+)|(r_wave)" - RD = re.findall(comp_OP_PARAM, current ['DST']) - if (RD): - if ( (current ['SRC'] == 'label') and (RD[0][1]!='15') ): - error = Logger.warning('Instruction.REG_WR', 'Register used to BRANCH should be s15 in instruction ' + str(current['LINE']) ) - if (RD[0][0]) : - RD = '00' + integer2bin(RD[0][0], 5) - elif (RD[0][1]) : - RD = '10' + integer2bin(RD[0][1], 5) - elif (RD[0][2]) : - RD = '01' + integer2bin(RD[0][2], 5) - elif (RD[0][3]) : - if (current ['SRC'] == 'wmem'): - Wr = Rdi = '0' - error, Wr, Rdi, RD = Instruction.__PROCESS_WR(current) - CFG = '10__' + current ['UF'] +'_'+ Wr + Rdi +'_'+ alu_op - else: - error = Logger.error('Instruction.REG_WR', 'Wave Register Destination Should have a Wave Memory Source ' + str(current['LINE']) + " (possible missing alias)") - else: - error = Logger.error('Instruction.REG_WR', 'Destination Register '+current ['DST']+' not Recognized in instruction ' + str(current['LINE']) ) - if (error==0): - CODE = '100_' + AI + DF +'__'+ COND +'___'+ CFG +'_____'+ADDR+'_____'+DATA + '_' + RD - else: - CODE = 'X' - return error, CODE - - @staticmethod - def DMEM_WR (current : dict) -> tuple: - error = 0 - #### CONDITIONAL - COND = '000' - error, COND = Instruction.__PROCESS_CONDITION(current) - #### WRITE REGISTER - Wr = Rdi = '0' - if (error==0): - error, Wr, Rdi, RD = Instruction.__PROCESS_WR(current) - #### DATA SOURCE - if (error==0): - error, DATA, alu_op, DF = Instruction.__PROCESS_SOURCE(current) - #### ADDRESS - if (error==0): - error, RsF, RsE, AI = Instruction.__PROCESS_MEM_ADDR (current['DST']) - ADDR = RsF + '_' + RsE - #### SOURCE - if (error==0): - if (current ['SRC'] == 'op'): - if ('OP' in current ): - DI = '0' - else: - error = Logger.error('Instruction.MEM_WR', '> -op() option not found in instruction ' + str(current['LINE']) ) - elif (current ['SRC'] == 'imm'): - if 'LIT' in current: - DI = '1' - else: - error = Logger.error('Instruction.MEM_WR', 'No Literal value found in instruction ' + str(current['LINE']) ) - else: - error = Logger.error('Instruction.MEM_WR', 'Posible MEM_WR sources are (op, imm) in instruction ' + str(current['LINE']) ) - - if (error==0): - CFG = current['UF']+ '_'+Wr+Rdi+'_'+ alu_op - CODE = '101_'+AI+DF+'__'+COND+'_0_'+DI+'__'+CFG+"_____"+ADDR+'_____'+DATA+'_'+RD - else: - CODE = 'X' - return error, CODE - - @staticmethod - def WMEM_WR (current : dict) -> tuple: - error = 0 - AI=Wp=TI='0' - #### WMEM ADDRESS - if 'DST' in current: - error, RsF, RsE, AI = Instruction.__PROCESS_MEM_ADDR (current['DST']) - if (RsE != '000000'): - error = Logger.error('Instruction.REG_WR', 'Wave Memory Addres Error Source Should be LIT or Reg in line ' + str(current['LINE']) ) - else: - error = Logger.error('Instruction.WMEM_WR', 'No address specified in line ' + str(current['LINE']) ) - #### WRITE REGISTER - Wr = Rdi = '0' - if (error==0): - error, Wr, Rdi, RD = Instruction.__PROCESS_WR(current) - #### WRITE PORT - if (error==0): - error, Wp, Sp, Dp = Instruction.__PROCESS_WP(current) - #### DATA SOURCE - if (error==0): - error, DATA, alu_op, DF = Instruction.__PROCESS_SOURCE(current) - if (error==0): - if ('TIME' in current ): - TI='1' - DATA = integer2bin(current['TIME'], 32) - CFG = '1_' + TI+'__' +current['UF'] +'_'+ Wr +Rdi +'_'+ alu_op - CODE = '101_'+AI+DF+'__1'+Sp+Wp+'__'+CFG+"_____"+RsF+'_'+Dp+'____'+DATA+'_'+RD - else: - error = Logger.error('Instruction.WMEM_WR', 'Error in line ' + str(current['LINE']) ) - CODE = 'X' - return error, CODE - - @staticmethod - def CFG (current : dict) -> tuple: - error = 0 - AI=SO=TO= '0' - ADDR = '00000000000_000000' - #### CONDITIONAL - COND = '000' - error, COND = Instruction.__PROCESS_CONDITION(current) - #### WRITE REGISTER - Wr = Rdi = '0' - error, Wr, Rdi, RD = Instruction.__PROCESS_WR(current) - #### DATA SOURCE - if (error==0): - error, DATA, alu_op, DF = Instruction.__PROCESS_SOURCE(current) - if (error==0): - CFG = current['UF'] +'_'+ Wr + Rdi +'_'+ alu_op - CODE = '000_'+AI+DF+'__'+COND+'_'+SO+TO+'__'+CFG+"_____"+ADDR+'_____'+DATA+'_'+RD - else: - CODE = 'X' - return error, CODE - - @staticmethod - def BRANCH (current : dict, cj : str) -> tuple: - error = 0 - #### CONDITIONAL - COND = '000' - error, COND = Instruction.__PROCESS_CONDITION(current) - #### WRITE REGISTER - if error == 0: - Wr = Rdi = '0' - if (error==0): - error, Wr, Rdi, RD = Instruction.__PROCESS_WR(current) - #### DATA SOURCE - if (error==0): - error, DATA, alu_op, DF = Instruction.__PROCESS_SOURCE(current) - #### DESTINATION MEMORY ADDRESS - if error == 0: - if (cj =='11'): # RET Instruction. ADDR came from STACK - current['UF'] = '0' - AI = '0' - ADDR = '_00000000000_000000' - else: - comp_addr = "&(\d+)|s(\d+)" - #addr? - addr = re.findall(comp_addr, current['ADDR']) - - try: - if (addr[0][0]): # LITERAL - ADDR = '_' + integer2bin(addr[0][0], 11) + '_000000' - AI = '1' - elif (addr[0][1] == '15'): #REGISTER - ADDR = '_00000000000_000000' - AI = '0' - else: - error = Logger.error("Instruction.BRANCH", "JUMP Memory Address not recognized (imm or s15)") - except IndexError: - error = Logger.error("COMMAND RECOGNITION", f"for address at line {current['LINE']}. (possible extra [])") - - if (error==0): - CFG = current['UF'] +'_'+ Wr+Rdi +'_'+ alu_op - CODE = '001_'+AI+DF+'__'+COND+'__'+cj+'___'+CFG+"_____"+ADDR+'____'+DATA+"_"+RD - else: - Logger.error("Instruction.BRANCH", "Exit with Error in instruction " + str(current['LINE']) ) - CODE = 'X' - return error, CODE - - @staticmethod - def PORT_WR (current : dict) -> tuple: - error = 0 - if (current['CMD'] == 'DPORT_WR' or current['CMD'] == 'DPORT_RD') \ - or (current['CMD'] == 'TRIG'): - SO=AI=Ww=PS= '0' - RsF = '00000000000' - #### WRITE REGISTER - if error == 0: - Wr = Rdi = '0' - if (error==0): - error, Wr, Rdi, RD = Instruction.__PROCESS_WR(current) - #### DATA SOURCE - if (error==0): - error, DATA, alu_op, DF = Instruction.__PROCESS_SOURCE(current) - if (current['CMD'] == 'TRIG'): - if (current['SRC'] == 'set'): - Wp= '1' - AI=PS = '1' - RsF = '_00000000001' - current['DST'] = str(int(current['DST'])+8) - elif (current['SRC'] == 'clr'): - Wp= '1' - AI=PS = '1' - RsF = '_00000000000' - current['DST'] = str(int(current['DST'])+8) - else: - error = Logger.error('Instruction.CTRL', 'Posible options for TRIG command are (set, clr)' ) - - elif (current['CMD'] == 'DPORT_WR'): - Wp= '1' - if (current ['SRC'] == 'imm'): - if 'DATA' in current: - AI=PS = '1' - RsF = '_'+ integer2bin(current['DATA'], 11) - else: - error = Logger.error('Instruction.PORT_WR', 'No Port Data value found in line ' + str(current['LINE']) ) - elif (current ['SRC'] == 'reg'): - if ('DATA' in current ): - AI=PS = '0' - comp_REG_FMT = "r(\d+)" - param_op = re.findall(comp_REG_FMT, current['DATA']) - if (param_op): - RsF = '00000_' + integer2bin(param_op[0][0], 6) - else: - error = Logger.error('Instruction.PORT_WR', 'Register Selection Error, should be r in line ' + str(current['LINE']) ) - else: - error = Logger.error('Instruction.PORT_WR', 'No Port Register found in line ' + str(current['LINE']) ) - else: - error = Logger.error('Instruction.PORT_WR', 'Posible DPORT_WR sources are (imm, reg) in line ' + str(current['LINE']) ) - else: #DPORT_RD - TO=Wp='0' - else: - AI=Ww=PS= '0' - SO=Wp= '1' - #### SOURCE - if (error==0): - if (current['SRC'] == 'wmem'): - PS = '0' - if 'ADDR' in current: - error, RsF, RsE, AI = Instruction.__PROCESS_MEM_ADDR (current ['ADDR']) - if (RsE != '000000'): - error = Logger.error('Instruction.REG_WR', 'Wave Memory Addres Error Source Should be LIT or Reg in line ' + str(current['LINE']) ) - else: - error = Logger.error('Instruction.PORT_WR', 'No address specified for < wmem > in line ' + str(current['LINE']) ) - elif (current['SRC'] == 'r_wave'): - PS='1' - #### WRITE WAVE MEMORY - if ('WW' in current ): - if 'ADDR' in current: - Ww = '1' - error, RsF, RsE, AI = Instruction.__PROCESS_MEM_ADDR (current ['ADDR']) - if (RsE != '000000'): - error = Logger.error('Instruction.REG_WR', 'Wave Memory Addres Error Source Should be LIT or Reg in line ' + str(current['LINE']) ) - else: - error = Logger.error('Instruction.PORT_WR', 'No address specified for < -ww > in line ' + str(current['LINE']) ) - else: - Ww = '0' - RsF = '_00000000000' - else: - error = Logger.error('Instruction.PORT_WR', 'Posible wave sources are (wmem, r_wave) in line ' + str(current['LINE']) ) - DF = '11' - #### OUT TIME - if (error==0): - if ('TIME' in current): - TO = '1' - DF = '11' - DATA = '____'+ integer2bin(current['TIME'], 32) - CFG = SO+TO+'____00000' - RD = '0000000' - if ('WR' in current): - error = Logger.error('Instruction.PORT_WR', 'If time specified, Not allowed SDI <-wr()> in line ' + str(current['LINE']) ) - else: - TO = '0' - error = Logger.info('Instruction.PORT_WR', 'No time specified for command will use r_time in line ' + str(current['LINE']) ) - #### WRITE REGISTER - Wr = Rdi = '0' - if (error==0): - error, Wr, Rdi, RD = Instruction.__PROCESS_WR(current) - #### DATA SOURCE - if (error==0): - error, DATA, alu_op, DF = Instruction.__PROCESS_SOURCE(current) - CFG = SO+TO+'__'+current['UF'] +'_'+Wr+Rdi +'_'+ alu_op - #### OUT PORT - if (error==0): - if ('DST' in current): - RsE = integer2bin(current['DST'], 6) - else: - error = Logger.error('Instruction.PORT_WR', 'No Destination Port in line ' + str(current['LINE']) ) - if (error == 0): - COND = Ww+PS+Wp - ADDR = RsF+'_'+RsE - CODE = '110'+'_'+AI+DF+'__'+COND+'___'+CFG+ '_____'+ADDR +'__'+ DATA+'_'+RD - else: - Logger.error("Instruction.PORT_WR", "Exit with Error in line " + str(current['LINE']) ) - CODE = 'X' - return error, CODE - - ################################ TO UPDATE CODE HERE. NOT LAST VERSION - @staticmethod - def CTRL (current : dict) -> tuple: - error = 0 - RA0=RA1='000000' - RD0=RD1='0_0000000' - RE='0000000000000000' - DF='10' - ######### TIME - if (current ['CMD'] == 'TIME'): - CTRL = '00001' - if (current['DST'] == 'rst'): - OPERATION = '00001' - elif (current['DST'] == 'updt'): - OPERATION = '00010' - elif (current['DST'] == 'set_ref'): - OPERATION = '00100' - elif (current['DST'] == 'inc_ref'): - OPERATION = '01000' - elif (current['DST'] == 'set_cmp'): - OPERATION = '10000' - else: - error = Logger.error('Instruction.CTRL', 'Posible Operations for TIME command are (rst, set_ref, inc_ref, set_cmp)' ) - if ('LIT' in current ): - DF='11' - RD1 = '_'+integer2bin(current['LIT'], 24) - RE='' - elif ('SRC' in current): - error, RD1 = get_reg_addr (current['SRC'], 'Source') - else: - if (current['DST']!='rst'): - error = Logger.error('Instruction.CTRL', 'No Data' ) - ######### FLAG - elif (current ['CMD'] == 'FLAG'): - CTRL = '00010' - if (current['SRC'] == 'set'): - OPERATION = '00001' - elif (current['SRC'] == 'clr'): - OPERATION = '00010' - else: - error = Logger.error('Instruction.CTRL', 'Posible Operations for FLAG command are (set, clr)' ) - ######### DIVISION - elif (current ['CMD'] == 'DIV'): - CTRL = '01000' - OPERATION = '00001' - if ('NUM' in current ): - error, RD0 = get_reg_addr (current['NUM'], 'Source') - if (error == 0) and ('DEN' in current ): - comp_den = "(\d+)|r(\d+)" - den = re.findall(comp_den, current['DEN']) - if (den[0][0]): # LITERAL - DF='11' - RD1 = '_'+integer2bin(current['DEN'], 24) - RE='' - elif (den[0][1]): #REGISTER - error, RD1 = get_reg_addr (current['DEN'], 'Source') - else: - error = Logger.error("Instruction.CTRL", "JUMP Memory Address not recognized (imm or s15)") - ######### NET - elif (current ['CMD'] == 'NET'): - CTRL = '10001' # QNET ADDRESS - if (current['SRC'] == 'get_net'): - OPERATION = '00001' - elif (current['SRC'] == 'set_net'): - OPERATION = '00010' - elif (current['SRC'] == 'sync_net'): - OPERATION = '01000' - elif (current['SRC'] == 'updt_offset'): - OPERATION = '01001' - elif (current['SRC'] == 'set_dt'): - OPERATION = '01010' - elif (current['SRC'] == 'get_dt'): - OPERATION = '01011' - else: - error = Logger.error('Instruction.CTRL', 'Posible Operations for FLAG command are (set, clr)' ) - ######### CUSTOM - elif (current ['CMD'] == 'CUSTOM'): - CTRL = '10010' # CUSTOM PERIPHERAL - OPERATION = integer2bin(current['C_OP'], 5) - - - if ('LIT' in current): - error = Logger.error('Instruction.CTRL', 'No Immediate value allowed in CUSTOM' ) - else : - if ('R1' in current and 'R2' in current and 'R3' in current and 'R4' in current ): - error, RsA = get_reg_addr (current['R1'], 'Source') - error, RsD = get_reg_addr (current['R2'], 'Addr') - error, RsB = get_reg_addr (current['R3'], 'Source') - error, RsC = get_reg_addr (current['R4'], 'Addr') - else: - error = Logger.error('Instruction.CTRL', 'Few Sources > Need Four Source Register for CUSTOM operation' ) - if (error): - Logger.error("Instruction.CTRL", "Error in instruction " + str(current['LINE']) ) - CODE = 'X' - else: - CODE = '111_0'+DF+'______'+OPERATION+'___'+CTRL+'_____00000___'+RA0+'_'+RA1+'__'+RD0+'__'+RD1+'_'+RE+'_0000000' - return error, CODE - - - @staticmethod - def ARITH (current : dict) -> tuple: - error = 0 - RsC=RsD='000000' - if ('LIT' in current): - error = Logger.error('Instruction.ARITH', 'No Immediate value allowed ' ) - if (not 'C_OP' in current) : - error = Logger.error('Instruction.ARITH', 'No ARITH Operation ' ) - else : - if (current['C_OP'] in arithList ): - ARITH_OP = arithList[current['C_OP']] - - if (current['C_OP'] == 'T'): # A*B - if ('R1' in current and 'R2' in current ): - error, RsA = get_reg_addr (current['R1'], 'Source') - error, RsB = get_reg_addr (current['R2'], 'Source') - else: - error = Logger.error('Instruction.ARITH', 'Few Sources > Need Two Source Register for T operation' ) - elif (current['C_OP'] == 'TP') : # A*B+C - if ('R1' in current and 'R2' in current and 'R3' in current ): - error, RsA = get_reg_addr (current['R1'], 'Source') - error, RsB = get_reg_addr (current['R2'], 'Source') - error, RsC = get_reg_addr (current['R3'], 'Addr') - else: - error = Logger.error('Instruction.ARITH', 'Few Sources > Need three Source Register for TP operation' ) - elif (current['C_OP'] == 'TM') : # A*B-C - if ('R1' in current and 'R2' in current and 'R3' in current ): - error, RsA = get_reg_addr (current['R1'], 'Source') - error, RsB = get_reg_addr (current['R2'], 'Source') - error, RsC = get_reg_addr (current['R3'], 'Addr') - else: - error = Logger.error('Instruction.ARITH', 'Few Sources > Need three Source Register for TM operation' ) - elif (current['C_OP'] == 'PT') : # (A+D)*B - if ('R1' in current and 'R2' in current and 'R3' in current ): - error, RsA = get_reg_addr (current['R1'], 'Source') - error, RsD = get_reg_addr (current['R2'], 'Addr') - error, RsB = get_reg_addr (current['R3'], 'Source') - else: - error = Logger.error('Instruction.ARITH', 'Few Sources > Need three Source Register for PT operation' ) - elif (current['C_OP'] == 'PTP'): #(A+D)*B+C - if ('R1' in current and 'R2' in current and 'R3' in current and 'R4' in current ): - error, RsA = get_reg_addr (current['R1'], 'Source') - error, RsD = get_reg_addr (current['R2'], 'Addr') - error, RsB = get_reg_addr (current['R3'], 'Source') - error, RsC = get_reg_addr (current['R4'], 'Addr') - else: - error = Logger.error('Instruction.ARITH', 'Few Sources > Need Four Source Register for PTP operation' ) - elif (current['C_OP'] == 'PTM'): #(A+D)*B-C - if ('R1' in current and 'R2' in current and 'R3' in current and 'R4' in current ): - error, RsA = get_reg_addr (current['R1'], 'Source') - error, RsD = get_reg_addr (current['R2'], 'Addr') - error, RsB = get_reg_addr (current['R3'], 'Source') - error, RsC = get_reg_addr (current['R4'], 'Addr') - else: - error = Logger.error('Instruction.ARITH', 'Few Sources > Need Four Source Register for PTM operation' ) - else: - error = Logger.error('Instruction.ARITH', 'No Recognized Operation' ) - - if (error==0): - CODE = '111_000______'+ARITH_OP +'___00100_____00000___'+RsC+'__'+RsD+'__'+RsA+'__'+RsB+'___0000000000000000_0000000' - else: - Logger.error("Instruction.ARITH", "Exit with Error in line " + str(current['LINE']) ) - CODE = 'X' - return error, CODE diff --git a/qick/qick_lib/qick/tprocv2_compiler.py b/qick/qick_lib/qick/tprocv2_compiler.py deleted file mode 100644 index c558835..0000000 --- a/qick/qick_lib/qick/tprocv2_compiler.py +++ /dev/null @@ -1,995 +0,0 @@ -# -*- coding: utf-8 -*- -""" -Created on Tue Aug 9 13:40:39 2022 - -@author: mdifeder -""" -import re -import logging - -logger = logging.getLogger('tprocv2_compiler') - - -# ALU OPERATIONS -aluList = {} -aluList['+'] = '0000' -aluList['-'] = '0010' -aluList['AND'] = '0100' -aluList['&'] = '0100' -aluList['MSK'] = '0100' -aluList['ASR'] = '0110' -aluList['ABS'] = '1000' -aluList['MSH'] = '1010' -aluList['LSH'] = '1100' -aluList['SWP'] = '1110' -aluList['NOT'] = '0001' -aluList['!'] = '0001' -aluList['OR'] = '0011' -aluList['|'] = '0011' -aluList['XOR'] = '0101' -aluList['^'] = '0101' -aluList['CAT'] = '0111' -aluList['::'] = '0111' -aluList['RFU'] = '1001' -aluList['PAR'] = '1011' -aluList['SL'] = '1101' -aluList['<<'] = '1101' -aluList['SR'] = '1111' -aluList['>>'] = '1111' -aluList_s = {} ## List with Commands for -op() -aluList_s['+'] = '00' -aluList_s['-'] = '01' -aluList_s['AND'] = '10' -aluList_s['ASR'] = '11' -aluList_op = [] ## List with Commands with one parameter -aluList_op.append('ABS') -aluList_op.append('MSH') -aluList_op.append('LSH') -aluList_op.append('SWP') -aluList_op.append('PAR') -aluList_op.append('NOT') - - -arithList = {} #Arith Comand List -arithList['T'] = '00000' -arithList['TP'] = '00010' -arithList['TM'] = '00011' -arithList['PT'] = '01000' -arithList['MT'] = '11000' -arithList['PTP'] = '01010' -arithList['PTM'] = '01011' -arithList['MTP'] = '11010' -arithList['MTM'] = '11011' - -# CONDITIONALS -condList = {} -condList['0'] = '000' -condList['Z'] = '001' -condList['S'] = '010' -condList['NZ'] = '011' -condList['NS'] = '100' -condList['TC'] = '101' -condList['NTC'] = '110' -condList['EC'] = '111' -condStr = ', '.join(list(condList.keys())) - - -def tprocv2_getasm(prog_list, Dict_Label): - asm = '' - addr = 0 - key_list = list(Dict_Label.keys()) - val_list = list(Dict_Label.values()) - for cmd in prog_list: - addr = addr+1 - # LABEL in the Correct Line - PADDR = '&'+str(addr) - if (PADDR in val_list): - #print('LABEL : ' + key_list[val_list.index(PADDR)] + ' > PADDR ' + PADDR) - label = key_list[val_list.index(PADDR)] - if (label[0:2]=='F_'): - label = '\n' + label - asm = asm + label + ':\n' - # COMMAND - if (cmd['CMD']=='RET'): - asm = asm + 'RET\n' - else: - asm = asm + ' ' +cmd['CMD'] + ' ' - # PARAMETERS - if ('DST' in cmd): - if (cmd['CMD']=='DMEM_WR') or (cmd['CMD']=='WMEM_WR'): - asm = asm + '['+cmd['DST'] + '] ' - elif (cmd['CMD']=='DPORT_WR') or (cmd['CMD']=='WPORT_WR'): - asm = asm + 'p'+cmd['DST'] + ' ' - else: - asm = asm + cmd['DST'] + ' ' - if ('SRC' in cmd): - asm = asm + cmd['SRC'] + ' ' - - if ('LABEL' in cmd): - asm = asm + cmd['LABEL'] + ' ' - - if ('IF' in cmd): - asm = asm + '-if(' + cmd['IF'] + ') ' - - if ('WR' in cmd): - asm = asm + '-wr(' + cmd['WR'] + ') ' - - if ('LIT' in cmd): - asm = asm + '#' + cmd['LIT'] + ' ' - if ('OP' in cmd): - asm = asm + '-op(' + cmd['OP'] + ') ' - elif ('ADDR' in cmd): - asm = asm + '[' + cmd['ADDR'] + '] ' - - if ('NUM' in cmd): - asm = asm + cmd['NUM'] + ' ' - if ('DEN' in cmd): - if (cmd['DEN'][0]=='r'): - asm = asm + cmd['DEN'] + ' ' - else: - asm = asm + '#' + cmd['DEN'] + ' ' - if ('UF' in cmd): - if (cmd['UF']=='1'): - asm = asm + '-uf' - - asm = asm + '\n' - # ADD Address to commands with LABEL - line = 0 - for cmd in prog_list: - if ('LABEL' in cmd): - if ( cmd['LABEL'] in Dict_Label ) : - cmd['ADDR'] = Dict_Label[ cmd['LABEL'] ] - #print('Label <'+cmd['LABEL'] +'> changed by address '+cmd['ADDR']) - else: - error = msg(4, 'LABEL: ', 'Label ' +cmd['LABEL'] + ' not recognized') - cmd['LINE'] = line - line = line + 1 - - return prog_list, asm - - - -def tprocv2_compile(prog_list, Dict_Label): - prog_list, asm = tprocv2_getasm(prog_list, Dict_Label) - error = 0 - PROGRAM = ['000_000__000___00__0_00_00______00000000000_000000_________00000000000000000000000000000000_0000000'] - CODE='x' - for current in prog_list: - if ('CMD' in current): - ############################################################################### - if current['CMD'] == 'NOP': - CODE = '000_000__000___00__0_00_00______00000000000_000000_________00000000000000000000000000000000_0000000' - ############################################################################### - elif (current['CMD'] == 'REG_WR'): - error, CODE = cmd_REG_WR(current) - ############################################################################### - elif current['CMD'] == 'DMEM_WR': - error, CODE = cmd_DMEM_WR(current) - ############################################################################### - elif current['CMD'] == 'WMEM_WR': - error, CODE = cmd_WMEM_WR(current) - ############################################################################### - elif current['CMD'] == 'JUMP': - error, CODE = cmd_BRANCH(current, '00') - ############################################################################### - elif current['CMD'] == 'CALL': - error, CODE = cmd_BRANCH(current, '10') - ############################################################################### - elif current['CMD'] == 'RET': - error, CODE = cmd_BRANCH(current, '11') - ############################################################################### - elif current['CMD']=='DPORT_WR' or current['CMD'] == 'DPORT_RD' or current['CMD'] == 'WPORT_WR': - error, CODE = cmd_PORT_WR(current) - ############################################################################### - elif current['CMD'] == 'TIME': - error, CODE = cmd_CTRL(current) - ############################################################################### - elif current['CMD'] == 'TEST': - current['UF'] = '1' - error, CODE = cmd_CFG(current) - ############################################################################### - elif current['CMD'] == 'DIV': - error, CODE = cmd_CTRL(current) - ############################################################################### - elif current['CMD'] == 'COND': - error, CODE = cmd_CTRL(current) - ############################################################################### - elif current['CMD'] == 'ARITH': - error, CODE = cmd_ARITH(current) - else: - logger.error('[ERROR-S2]- Command not recognized > ' + current['CMD']) - error=1 - long = CODE.count('0') + CODE.count('1') - if (long != 72): - error = 1 - logger.error(CODE+"INSTRUCIONT LONG > " + str(long) +' '+ str(current['LINE'])) - else: - logger.error("[ERROR-S2]-No Command") - error=1 - ################################################################################### - if (error==0): - PROGRAM.append(CODE) - else: - break - if (error!=0): - logger.error("S2-Exit With ERROR") - else: - logger.info('##### STEP_4 - BINARY CREATION') - p_mem = [] - for line_bin in PROGRAM: - tmp = line_bin.replace('_', '') - b0 = '0b'+tmp[40:72] - n0 = int(b0,2) - b1 = '0b'+ tmp[8:40] - n1 = int(b1,2) - b2 = '0b'+tmp[:8] - n2 = int(b2,2) - p_mem_line = [n0, n1, n2, 0, 0, 0, 0, 0] - p_mem.append(p_mem_line) - logger.info("\n#######################\n Finished Successfully\n#######################") - return p_mem, PROGRAM, asm - - -def msg (severity, locator, msg): - if (severity == 4): - logger.error('[%s] > %s' % (locator, msg)) - return 1 - elif (severity == 3 ): - logger.warning('[%s] > %s' % (locator, msg)) - elif (severity == 2 ): - logger.info('[%s] > %s' % (locator, msg)) - elif (severity == 1 ): - logger.debug('[%s] > %s' % (locator, msg)) - else: - logger.debug('[%s] > %s' % (locator, msg)) - return 0 - - -def integer2bin(strin, bits=8): - minv = -2**(bits-1) - maxv = 2**(bits-1) - 1 - # Check if hex string. - m = re.search("^0x", strin, flags=re.MULTILINE) - if m: - # Special case for hex number. - dec = int(strin, 16) - # Convert to binary. - fmt = "{0:0" + str(bits) + "b}" - binv = fmt.format(dec) - return binv - else: - dec = int(strin, 10) - # Check max. - if dec < minv: - logger.error("number %d is smaller than %d" % (dec, minv)) - return None - # Check max. - if dec > maxv: - logger.error("number %d is bigger than %d" % (dec, maxv)) - return None - # Check if number is negative. - if dec < 0: - dec = dec + 2**bits - # Convert to binary. - fmt = "{0:0" + str(bits) + "b}" - binv = fmt.format(dec) - return binv - -def proc_CONDITION (cmd): - error = 0 - cond = '' - if ('IF' in cmd ): - if cmd['IF'] in condList: - cond = condList[cmd['IF']] - else: - error = msg(4, 'proc_CONDITION', 'Posible CONDITIONS are (' + condStr + ') in instruction ' + str(cmd['LINE']) ) - else: - cond = '000' - return [error, cond] - -def get_reg_addr (reg, Type): - error = 0 - REG = re.findall('r(\d+)|s(\d+)|w(\d+)', reg) - if (REG): - REG = REG[0] - if (Type=='Source'): - if (REG[0]): ## is R_Reg - reg_addr = '0_00'+integer2bin(REG[0], 5) - elif (REG[1]): ## is S_Reg - reg_addr = '0_10'+integer2bin(REG[1], 5) - elif (REG[2]): ## is W_Reg - reg_addr = '0_01'+integer2bin(REG[2], 5) - elif (Type=='Dest'): - if (REG[0]): ## is Data Register - reg_addr = '00'+integer2bin(REG[0], 5) - elif (REG[1]): ## is Special Register - reg_addr = '10'+integer2bin(REG[1], 5) - elif (REG[2]): ## is WaveForm Register - reg_addr = '01'+integer2bin(REG[2], 5) - elif (Type=='Addr'): - if (REG[0]): ## is R_Reg - reg_addr = '0'+integer2bin(REG[0], 5) - elif (REG[1] or REG[2]): ## is S_Reg or W_Reg - error = msg(4, 'get_reg_addr', 'Address format error, should be Data Register (Starts with r)' ) - else: - reg_addr = 'X' - error = msg(4, 'get_reg_addr', 'Register not Recognized (Registers Starts with r, s or w) ' ) - return [error, reg_addr] - - -def proc_WR2(cmd): #### Get WR - error = 0 - RD = '0000000' - Rdi=Wr = '0' - if ('WR' in cmd ): - Wr = '1' - regex_DS = r'\s*([\w]+)' - DEST_SOURCE = re.findall(regex_DS, cmd['WR']) - #### SOURCE - if (len(DEST_SOURCE) == 2): - if (DEST_SOURCE[1] == 'op'): - if ('OP' in cmd ): - Rdi = '0' - else: - error = msg(4, 'proc_WR2', 'Pperation < -op() > option not found in instruction ' + str(cmd['LINE']) ) - elif (DEST_SOURCE[1] == 'imm'): - if ('LIT' in cmd ): - Rdi = '1' - else: - error = msg(4, 'proc_WR2', 'Literal Value not found in instruction ' + str(cmd['LINE']) ) - else: - error = msg(4, 'proc_WR2', 'Posible Source Dest for <-wr(reg source)> are (op, imm) in instruction ' + str(cmd['LINE']) ) - else: - error = msg(4, 'proc_WR2', 'Write Register error <-wr(reg source) in instruction ' + str(cmd['LINE']) ) - #### DESTINATION REGISTER - error, RD = get_reg_addr (DEST_SOURCE [0], 'Dest') - return [error, Wr, Rdi, RD] - - - -def proc_SOURCE (cmd): - error = 0 - df = alu_op = 'X' - RsD = RsC = DataImm ='' - FULL = (cmd['CMD']=='REG_WR') and (cmd['SRC']=='op') - if ('OP' in cmd): - error = 0 - comp_OP_PARAM = "r(\d+)|s(\d+)|w(\d+)|#(-?\d+)|\s*([A-Z]{3}|[A-Z><]{2}|\+|\-)" - param_op = re.findall(comp_OP_PARAM, cmd['OP']) - DataImm = RsC = '' - if (len(param_op)==1 ) : - df = '10' - RsC = '0_0000000' - DataImm = '0000000000000000' - if FULL: - alu_op = '0000' - else: - alu_op = '00' - - ## CHECK FOR ONLY OPERAND (COPY REG) - if (param_op[0][0]): ## is R_Reg - RsD = '0_00'+integer2bin(param_op[0][0], 5) - elif (param_op[0][1]): ## is S_Reg - RsD = '0_10'+integer2bin(param_op[0][1], 5) - elif (param_op[0][2]): ## is W_Reg - RsD = '0_01'+integer2bin(param_op[0][2], 5) - elif (param_op[0][3]): ## is Literal - error = msg(4, 'proc_SOURCE', 'Operand can not be a Literal.') - else: - error = msg(4, 'proc_SOURCE', 'Operand not recognized.') - - #error = msg(4, 'proc_SOURCE', 'Few parameters in < -op() >') - elif (len(param_op)==2 ) : - if (param_op[0][4] in aluList_op) : - df = '10' - alu_op = aluList[param_op[0][4]] - DataImm = '000000000000000000000000' - ## CHECK FOR OPERAND (ALU_IN_A > rsD) - if (param_op[1][0]): ## is R_Reg - RsD = '0_00'+integer2bin(param_op[1][0], 5) - elif (param_op[1][1]): ## is S_Reg - RsD = '0_10'+integer2bin(param_op[1][1], 5) - elif (param_op[1][2]): ## is W_Reg - RsD = '0_01'+integer2bin(param_op[1][2], 5) - elif (param_op[1][3]): ## is Literal - error = msg(4, 'proc_SOURCE', 'Operand can not be a Literal in instruction ' + str(cmd['LINE']) ) - else: - error = msg(4, 'proc_SOURCE', 'Operantion Not Recognized in instruction ' + str(cmd['LINE']) ) - ## ABS Should be on RsC - if (param_op[0][4] == 'ABS') : - df = '01' - RsC = RsD - RsD = '0_0000000' - DataImm = '0000000000000000' - elif (len(param_op)==3 ) : - ## CHECK FOR FIRST OPERAND (ALU_IN_A > rsD) - if (param_op[0][0]): ## is R_Reg - RsD = '0_00'+integer2bin(param_op[0][0], 5) - elif (param_op[0][1]): ## is S_Reg - RsD = '0_10'+integer2bin(param_op[0][1], 5) - elif (param_op[0][2]): ## is W_Reg - RsD = '0_01'+integer2bin(param_op[0][2], 5) - elif (param_op[0][3]): ## is Literal - error = msg(4, 'proc_SOURCE', 'First Operand can not be a Literal.') - else: - error = msg(4, 'proc_SOURCE', 'First Operand not recognized.') - ## CHECK FOR SECOND OPERAND (ALU_IN_B > Imm|rsC) - if (error == 0): - if ( (param_op[2][0]) or (param_op[2][1]) or (param_op[2][2]) ): ## REG OP REG - if ('LIT' in cmd): - msg(3, 'proc_SOURCE', 'With < -op() > imm value should be 16 Bits in instruction ' + str(cmd['LINE']) ) - if ( int(cmd ['LIT']) >= 65535): - error = msg(4, 'proc_SOURCE', ('Literal '+ cmd ['LIT'] + ' should be 16 Bits.') ) - else: - logger.info("[OK] Literal " + cmd ['LIT'] + " can be represented with 16 Bits.") - df = '01' - DataImm = '_'+integer2bin(cmd ['LIT'], 16) - else: - DataImm = '0000000000000000' - - if (param_op[2][0]): ## is R_Reg - df = '01' - RsC = '0_00'+integer2bin(param_op[2][0], 5) - elif (param_op[2][1]): ## is S_Reg - df = '01' - RsC = '0_10'+integer2bin(param_op[2][1], 5) - elif (param_op[2][2]): ## is W_Reg - df = '01' - RsC = '0_01'+integer2bin(param_op[2][2], 5) - elif (param_op[2][3]): ## is Literal - df = '10' - DataImm = '_'+ integer2bin(param_op[2][3], 24) - else: - error = msg(4, 'proc_SOURCE', 'Second Operand not recognized in instruction ' + str(cmd['LINE']) ) - ## CHECK FOR OPERATION - if (error == 0): - if (FULL): - if param_op[1][4] in aluList: - alu_op = aluList[ param_op[1][4] ] - else: - error = msg(4, 'proc_SOURCE', 'ALU {Full List} Operation Not Recognized in instruction ' + str(cmd['LINE']) ) - else: - if param_op[1][4] in aluList_s: - alu_op = aluList_s[ param_op[1][4] ] - else: - error = msg(4, 'proc_SOURCE', 'ALU {Reduced List} Operation Not Recognized in instruction ' + str(cmd['LINE']) ) - ## LITERAL and NO OP - elif ('LIT' in cmd): - df = '11' - alu_op = '00' - DataImm = '__'+integer2bin(cmd['LIT'], 32) - else: - df = '11' - alu_op = '00' - DataImm = '__00000000000000000000000000000000' - - Data_Source = RsD +'_'+ RsC +'_'+ DataImm - return [error, Data_Source, alu_op, df] - -def proc_MEM_ADDR (ADDR_CMD): - error = 0 - AI = '0' - RsF = RsE = 'x' - comp_ADDR_FMT = "r(\d+)|&(\d+)|\s*([A-Z]{3}|[A-Z]{2}|\+|\-)" - param_op = re.findall(comp_ADDR_FMT, ADDR_CMD) - if (len(param_op)==1 ) : - ## CHECK FOR OPERAND - RsE = '000000' - if (param_op[0][0]): ## is R_Reg - RsF = '00000_' + integer2bin(param_op[0][0], 6) - elif (param_op[0][1]): ## is Literal - RsF = '_'+ integer2bin(param_op[0][1], 11) - AI = '1' - else: - error = msg(4, 'proc_MEM_ADDR', 'First Operand not recognized.') - elif (len(param_op)==3 ) : - ## CHECK FOR FIRST OPERAND - if (param_op[0][0]): ## is R_Reg - RsE = integer2bin(param_op[0][0], 6) - elif (param_op[0][1]): ## is Literal - error = msg(4, 'proc_MEM_ADDR', 'First Operand can not be a Literal.') - ## CHECK FOR SECOND OPERAND - if (error == 0): - if (param_op[2][0]): ## is R_Reg - RsF = '00000_' + integer2bin(param_op[2][0], 6) - elif (param_op[2][1]): ## is Literal - RsF = '_'+ integer2bin(param_op[2][1], 11) - AI = '1' - ## CHECK FOR PLUS - if (error == 0): - if (param_op[1][2]) != '+': ## is R_Reg - error = msg(4, 'proc_MEM_ADDR', 'Address Operand should be < + >.') - else: - error = msg(4, 'proc_MEM_ADDR', 'Address format error, should be Data Register(r) or Literal(&)') - return [error, RsF, RsE, AI] - - - - -############################################################################### -## BASIC COMANDS -############################################################################### -def cmd_REG_WR (current): - AI = '0' - error = 0 - RdP = '000000' - ######### CONDITIONAL - error, COND = proc_CONDITION(current) - ######### SOURCES - if (error==0): - #### SOURCE ALU - if (current ['SRC'] == 'op'): - if ('OP' in current ): - error, DATA, alu_op, DF = proc_SOURCE (current) - CFG = '00__' + current ['UF'] + '__'+ alu_op - ADDR = '_00000000000_000000' # 17 Bits 11 + 6 - else: - error = msg(4, 'cmd_REG_WR', 'No < -op() > for Operation Writting in instruction ' + str(current['LINE'])) - #### SOURCE IMM - elif (current ['SRC'] == 'imm'): - #### Get Data Source - if ('LIT' in current ): - error, DATA, alu_op, DF = proc_SOURCE(current) - CFG = '11__' + current ['UF'] + '_00_' + alu_op - ADDR = '_00000000000_000000' # 17 Bits 11 + 6 - else: - error = msg(4, 'cmd_REG_WR', 'No Literal value for immediate Assignation (#) in instruction ' + str(current['LINE']) ) - #### SOURCE LABEL - elif (current ['SRC'] == 'label'): - #### Get Data Source - if ('LABEL' in current ): - comp_addr = "&(\d+)" - addr = re.findall(comp_addr, current['ADDR']) - if (addr[0]): # LITERAL - ADDR = '_00000000000_000000' # 17 Bits 11 + 6 - DATA = '0000000000000000_' + integer2bin(addr[0], 16) - DF = '11' - CFG = '11__' + current ['UF'] + '_00_00' - else: - error = msg(4, 'cmd_REG_WR', 'No Literal value for immediate Assignation (#) in instruction ' + str(current['LINE']) ) - #### SOURCE DATA MEMORY - elif (current ['SRC'] == 'dmem'): - #### Get Data Source - error, DATA, alu_op, DF = proc_SOURCE(current) - CFG = '01__' + current ['UF'] + '_00_' + alu_op - #### Get ADDRESS - if error == 0: - error, RsF, RsE, AI = proc_MEM_ADDR (current ['ADDR']) - ADDR = RsF + '_' + RsE - CFG = '01__' + current ['UF'] + '_00_'+alu_op - - #### SOURCE WAVE MEM - elif (current ['SRC'] == 'wmem'): - if (current ['DST'] == 'r_wave'): - if (COND != '000'): - error = msg(4, 'cmd_REG_WR', 'Wave Register Write is not conditional < -if() > in instruction ' + str(current['LINE']) ) - else: - WW = WP = '0' - if ('WW' in current): - WW = '1' - #### WRITE PORT - error, WP, Sp, RdP = proc_WP(current) - COND = WW + Sp + WP - #### WRITE REGISTER - if (error==0): - Wr = Rdi = '0' - error, Wr, Rdi, RD = proc_WR2(current) - #### Get Data Source - if (error==0): - error, DATA, alu_op, DF = proc_SOURCE(current) - #### Get ADDRESS - if error == 0: - if ('ADDR' in current): - error, RsF, RsE, AI = proc_MEM_ADDR (current ['ADDR']) - if (RsE != '000000'): - error = msg(4, 'cmd_REG_WR', 'Wave Memory Addres Error Source Should be LIT or Reg in instruction ' + str(current['LINE']) ) - ADDR = RsF + '_' + RdP - else: - error = msg(4, 'cmd_REG_WR', 'No addres for source in instruction ' + str(current['LINE']) ) - else: - error = msg(4, 'cmd_REG_WR', 'Wave Memory Source Should have a Wave Register Destination ' + str(current['LINE']) ) - - else: - error = msg(4, 'cmd_REG_WR', 'Posible REG_WR sources are (op, imm, dmem, wmem, label ) in instruction ' + str(current['LINE']) ) - ######### DESTINATION REGISTER - if (error==0): - comp_OP_PARAM = "r(\d+)|s(\d+)|w(\d+)|(wave)" - RD = re.findall(comp_OP_PARAM, current ['DST']) - if (RD): - if ( (current ['SRC'] == 'label') and (RD[0][1]!='s15') ): - error = msg(3, 'cmd_REG_WR', 'Register used to Jump is s15 in instruction ' + str(current['LINE']) ) - if (RD[0][0]) : - RD = '00' + integer2bin(RD[0][0], 5) - elif (RD[0][1]) : - RD = '10' + integer2bin(RD[0][1], 5) - elif (RD[0][2]) : - RD = '01' + integer2bin(RD[0][2], 5) - elif (RD[0][3]) : - if (current ['SRC'] == 'wmem'): - Wr = Rdi = '0' - error, Wr, Rdi, RD = proc_WR2(current) - CFG = '10__' + current ['UF'] +'_'+ Wr + Rdi +'_'+ alu_op - else: - error = msg(4, 'cmd_REG_WR', 'Wave Register Destination Should have a Wave Memory Source ' + str(current['LINE']) ) - else: - error = msg(4, 'cmd_REG_WR', 'Destination Register not Recognized (Starts with r, s or w) in instruction ' + str(current['LINE']) ) - - if (error==0): - CODE = '100_' + AI + DF +'__'+ COND +'___'+ CFG +'_____'+ADDR+'_____'+DATA + '_' + RD - else: - CODE = 'X' - return error, CODE - -def cmd_DMEM_WR (current): - error = 0 - #### CONDITIONAL - COND = '000' - error, COND = proc_CONDITION(current) - #### WRITE REGISTER - Wr = Rdi = '0' - if (error==0): - error, Wr, Rdi, RD = proc_WR2(current) - #### DATA SOURCE - if (error==0): - error, DATA, alu_op, DF = proc_SOURCE(current) - #### ADDRESS - if (error==0): - error, RsF, RsE, AI = proc_MEM_ADDR (current ['DST']) - ADDR = RsF + '_' + RsE - #### SOURCE - if (error==0): - if (current ['SRC'] == 'op'): - if ('OP' in current ): - DI = '0' - else: - error = msg(4, 'cmd_MEM_WR', '> -op() option not found in instruction ' + str(current['LINE']) ) - elif (current ['SRC'] == 'imm'): - if 'LIT' in current: - DI = '1' - else: - error = msg(4, 'cmd_MEM_WR', 'No Literal value found in instruction ' + str(current['LINE']) ) - else: - error = msg(4, 'cmd_MEM_WR', 'Posible MEM_WR sources are (op, imm) in instruction ' + str(current['LINE']) ) - - if (error==0): - CFG = current['UF']+ '_'+Wr+Rdi+'_'+ alu_op - CODE = '101_'+AI+DF+'__'+COND+'_0_'+DI+'__'+CFG+"_____"+ADDR+'_____'+DATA+'_'+RD - else: - CODE = 'X' - return error, CODE - - -def proc_WP (cmd): - #### WRITE PORT - error=0 - Wp=Sp='0' - Dp='000000' - if ('WP' in cmd ): - #### DESTINATION PORT - if ('PORT' in cmd): - Wp='1' - Dp = integer2bin(cmd['PORT'], 6) - if (cmd['WP'] == 'r_wave'): - Sp = '1' - elif (cmd['WP'] == 'wmem'): - Sp = '0' - else: - error = msg(4, 'proc_WP', 'Source Wave Port not recognized (wreg, r_wave) ' + str(cmd['LINE']) ) - else: - error = msg(4, 'proc_WP', 'Port Address not recognized < pX > ' + str(cmd['LINE']) ) - return [error, Wp, Sp, Dp] - - -def cmd_WMEM_WR (current): - error = 0 - AI=WP=TI='0' - #### WMEM ADDRESS - if 'DST' in current: - Ww = '1' - error, RsF, RsE, AI = proc_MEM_ADDR (current ['DST']) - if (RsE != '000000'): - error = msg(4, 'cmd_REG_WR', 'Wave Memory Addres Error Source Should be LIT or Reg in instruction ' + str(current['LINE']) ) - - else: - error = msg(4, 'cmd_WMEM_WR', 'No address specified in instruction ' + str(current['LINE']) ) - #### WRITE REGISTER - Wr = Rdi = '0' - if (error==0): - error, Wr, Rdi, RD = proc_WR2(current) - #### WRITE PORT - if (error==0): - error, Wp, Sp, Dp = proc_WP(current) - #### DATA SOURCE - if (error==0): - error, DATA, alu_op, DF = proc_SOURCE(current) - if (error==0): - if ('TIME' in current ): - TI='1' - DATA = integer2bin(current['TIME'], 32) - CFG = '1_' + TI+'__' +current['UF'] +'_'+ Wr +Rdi +'_'+ alu_op - CODE = '101_'+AI+DF+'__1'+Sp+Wp+'__'+CFG+"_____"+RsF+'_'+Dp+'____'+DATA+'_'+RD - else: - CODE = 'X' - return error, CODE - - -def cmd_CFG (current): - error = 0 - AI=SO=TO= '0' - ADDR = '00000000000_000000' - #### CONDITIONAL - COND = '000' - #### WRITE REGISTER - Wr = Rdi = '0' - if (error==0): - error, Wr, Rdi, RD = proc_WR2(current) - #### DATA SOURCE - if (error==0): - error, DATA, alu_op, DF = proc_SOURCE(current) - if (error==0): - CFG = current['UF'] +'_'+ Wr + Rdi +'_'+ alu_op - CODE = '000_'+AI+DF+'__'+COND+'_'+SO+TO+'__'+CFG+"_____"+ADDR+'_____'+DATA+'_'+RD - else: - CODE = 'X' - return error, CODE - - - - -def cmd_BRANCH (current, cj): - #print(current) - error = 0 - #### CONDITIONAL - COND = '000' - error, COND = proc_CONDITION(current) - #### WRITE REGISTER - if error == 0: - Wr = Rdi = '0' - if (error==0): - error, Wr, Rdi, RD = proc_WR2(current) - #### DATA SOURCE - if (error==0): - error, DATA, alu_op, DF = proc_SOURCE(current) - - #### DESTINATION MEMORY ADDRESS - if error == 0: - if (cj =='11'): # RET CMD. ADDR came from STACK - current['UF'] = '0' - AI = '0' - ADDR = '_00000000000_000000' - else: - comp_addr = "&(\d+)|s(\d+)" - addr = re.findall(comp_addr, current['ADDR']) - if (addr[0][0]): # LITERAL - ADDR = '_' + integer2bin(addr[0][0], 11) + '_000000' - AI = '1' - elif (addr[0][1] == '15'): #REGISTER - ADDR = '_00000000000_000000' - AI = '0' - else: - logger.error('[cmd_BRANCH] > JUMP Memory Address not recognized (imm or s15)') - error = 1 - - if (error==0): - CFG = current['UF'] +'_'+ Wr+Rdi +'_'+ alu_op - CODE = '001_'+AI+DF+'__'+COND+'__'+cj+'___'+CFG+"____"+ADDR+'____'+DATA+"_"+RD - else: - logger.error("[cmd_BRANCH] > Exit with Error in instruction " + str(current['LINE']) ) - CODE = 'X' - return error, CODE - - - - -def cmd_PORT_WR (current): - error = 0 - if (current['CMD'] == 'DPORT_WR' or current['CMD'] == 'DPORT_RD'): - SO=AI=Ww=S= '0' - RsF = '00000000000' - #### WRITE REGISTER - if error == 0: - Wr = Rdi = '0' - if (error==0): - error, Wr, Rdi, RD = proc_WR2(current) - #### DATA SOURCE - if (error==0): - error, DATA, alu_op, DF = proc_SOURCE(current) - - if (current['CMD'] == 'DPORT_WR'): - Wp= '0' - if (current ['SRC'] == 'op'): - if ('OP' in current ): - DI = '0' - else: - error = msg(4, 'cmd_PORT_WR', 'No Operation < -op() > found in instruction ' + str(current['LINE']) ) - elif (current ['SRC'] == 'imm'): - if 'LIT' in current: - DI = '1' - else: - error = msg(4, 'cmd_PORT_WR', 'No Literal value < # > found in instruction ' + str(current['LINE']) ) - else: - error = msg(4, 'cmd_PORT_WR', 'Posible DPORT_WR sources are (op, imm) in instruction ' + str(current['LINE']) ) - else: - DI=Wp='1' - - else: - SO=Wp= '1' - #### WRITE WAVE MEMORY - if ('WW' in current ): - if 'ADDR' in current: - Ww = '1' - error, RsF, RsE, AI = proc_MEM_ADDR (current ['ADDR']) - if (RsE != '000000'): - error = msg(4, 'cmd_REG_WR', 'Wave Memory Addres Error Source Should be LIT or Reg in instruction ' + str(current['LINE']) ) - - else: - error = msg(4, 'cmd_PORT_WR', 'No address specified for < -ww > in instruction ' + str(current['LINE']) ) - else: - Ww = '0' - RsF = '00000000000' - if (error==0): - if (current['SRC'] == 'wmem'): - if 'ADDR' in current: - error, RsF, RsE, AI = proc_MEM_ADDR (current ['ADDR']) - if (RsE != '000000'): - error = msg(4, 'cmd_REG_WR', 'Wave Memory Addres Error Source Should be LIT or Reg in instruction ' + str(current['LINE']) ) - S = '0' - else: - error = msg(4, 'cmd_PORT_WR', 'No address specified for < wmem > in instruction ' + str(current['LINE']) ) - elif (current['SRC'] == 'r_wave'): - AI=S='1' - RsF ='00000000000' - else: - error = msg(4, 'cmd_PORT_WR', 'Posible wave sources are (wmem, r_wave) in instruction ' + str(current['LINE']) ) - DF = '11' - - #### OUT TIME - if (error==0): - if ('TIME' in current): - DI = '1' - DF = '11' - DATA = '____'+ integer2bin(current['TIME'], 32) - CFG = SO+DI+'____00000' - RD = '0000000' - if ('WR' in current): - error = msg(4, 'cmd_PORT_WR', 'If time specified, Not allowed SDI <-wr()> in instruction ' + str(current['LINE']) ) - else: - DI = '0' - error = msg(3, 'cmd_PORT_WR', 'No time specified for command will use r_time in instruction ' + str(current['LINE']) ) - #### WRITE REGISTER - Wr = Rdi = '0' - if (error==0): - error, Wr, Rdi, RD = proc_WR2(current) - #### DATA SOURCE - if (error==0): - error, DATA, alu_op, DF = proc_SOURCE(current) - CFG = SO+DI+'__'+current['UF'] +'_'+Wr+Rdi +'_'+ alu_op - #### OUT PORT - if (error==0): - if ('DST' in current): - RsE = integer2bin(current['DST'], 6) - else: - error = msg(4, 'cmd_PORT_WR', 'Port Address not recognized < pX > in instruction ' + str(current['LINE']) ) - if (error == 0): - COND = Ww+S+Wp - ADDR = RsF+'_'+RsE - CODE = '110'+'_'+AI+DF+'__'+COND+'___'+CFG+ '______'+ADDR +'__'+ DATA+'_'+RD - else: - logger.error("[cmd_PORT_WR] > Exit with Error in instruction " + str(current['LINE']) ) - CODE = 'X' - return error, CODE - - - - -def cmd_CTRL (current): - error = 0 - AI = SO ='0' - RA0=RA1='000000' - RD0=RD1='0_0000000' - RE='0000000000000000' - DF='10' -######### TIME - if (current ['CMD'] == 'TIME'): - CTRL = '00001' - if (current['DST'] == 'rst'): - OPERATION = '00001' - elif (current['DST'] == 'set_ref'): - OPERATION = '00010' - elif (current['DST'] == 'inc_ref'): - OPERATION = '00100' - elif (current['DST'] == 'set_cmp'): - OPERATION = '01000' - else: - error = msg(4, 'cmd_TIME', 'Posible Operations for TIME command are (rst, set_ref, inc_ref, set_cmp)' ) - if ('LIT' in current ): - DF='11' - RD1 = '_'+integer2bin(current['LIT'], 24) - RE='' - elif ('SRC' in current): - error, RD1 = get_reg_addr (current['SRC'], 'Source') - else: - if (current['DST']!='rst'): - error = msg(4, 'cmd_TIME', 'No Data' ) - - ######### CONDITION - elif (current ['CMD'] == 'COND'): - CTRL = '00010' - if (current['SRC'] == 'set'): - OPERATION = '00001' - elif (current['SRC'] == 'clear'): - OPERATION = '00010' - else: - error = msg(4, 'cmd_TIME', 'Posible Operations for COND command are (set, clear)' ) - -######### DIVISION - elif (current ['CMD'] == 'DIV'): - CTRL = '01000' - OPERATION = '00001' - if ('NUM' in current ): - error, RD0 = get_reg_addr (current['NUM'], 'Source') - if (error == 0) and ('DEN' in current ): - comp_den = "(\d+)|r(\d+)" - den = re.findall(comp_den, current['DEN']) - if (den[0][0]): # LITERAL - DF='11' - RD1 = '_'+integer2bin(current['DEN'], 24) - RE='' - elif (den[0][1]): #REGISTER - error, RD1 = get_reg_addr (current['DEN'], 'Source') - - else: - logger.error('[cmd_BRANCH] > JUMP Memory Address not recognized (imm or s15)') - error = 1 - - if (error): - logger.error('Error in instruction ' + str(current['LINE']) ) - CODE = 'X' - else: - CODE = '111_'+AI+DF+'______'+OPERATION+'___'+CTRL+'_____00000___'+RA0+'_'+RA1+'__'+RD0+'__'+RD1+'_'+RE+'_0000000' - return error, CODE - -def cmd_ARITH (current): - error = 0 - RsC=RsD='000000' - if ('LIT' in current): - error = msg(4, 'cmd_ARITH', 'No Immediate value allowed ' ) - if ('OP' in current): - if (current['OP'] in arithList ): - ARITH_OP = arithList[current['OP']] - else: - error = msg(4, 'cmd_ARITH', 'No Recognized Operation Posible Operations for ARITH are (P, M, T, PT, MP, PTP, PTM, MTP, MTM)' ) - else: - error = msg(4, 'cmd_ARITH', 'No ARITH Operation ' ) - if (error==0): - if (ARITH_OP[1] == '1'): - if ('R1' in current and 'R2' in current and 'R3' in current): - error, RsD = get_reg_addr (current['R1'], 'Addr') - error, RsA = get_reg_addr (current['R2'], 'Source') - error, RsB = get_reg_addr (current['R3'], 'Source') - else: - error = msg(4, 'cmd_ARITH', 'Few Sources Registers' ) - if (ARITH_OP[3] == '1'): - if ('R4' in current): - error, RsC = get_reg_addr (current['R4'], 'Addr') - else: - if ('R1' in current and 'R2' in current): - RsD = '000000' - error, RsA = get_reg_addr (current['R1'], 'Source') - error, RsB = get_reg_addr (current['R2'], 'Source') - else: - error = msg(4, 'cmd_ARITH', 'Few Sources Registers' ) - if (ARITH_OP[3] == '1'): - if ('R3' in current): - error, RsC = get_reg_addr (current['R3'], 'Addr') - if (error==0): - CODE = '111_000______'+ARITH_OP +'___00100_____00000___'+RsC+'__'+RsD+'__'+RsA+'__'+RsB+'___0000000000000000_0000000' - else: - logger.error("[cmd_ARITH] > Exit with Error in instruction " + str(current['LINE']) ) - CODE = 'X' - return error, CODE - - AI = '0' - - return error, CODE - diff --git a/qick/quick_start/README.md b/qick/quick_start/README.md deleted file mode 100644 index 180fd9a..0000000 --- a/qick/quick_start/README.md +++ /dev/null @@ -1,11 +0,0 @@ -Hello! Welcome to the QICK quick start guide pages! - -Depending on your board, you will follow a different quick start guide. - -If your board is the ZCU111, follow [this guide](https://github.com/openquantumhardware/qick/blob/main/quick_start/README_ZCU111.md). - -If your board is the ZCU216, follow [this guide](https://github.com/openquantumhardware/qick/blob/main/quick_start/README_ZCU216.md). - -If your board is the RFSoC4x2, we don't have a dedicated guide, but you should be able to follow a combination of the 4x2's setup instructions (for basic power and connectivity) and our ZCU111 guide (for flashing an SD card image and installing QICK). - -Enjoy! diff --git a/qick/quick_start/README_ZCU111.md b/qick/quick_start/README_ZCU111.md deleted file mode 100644 index 4f0aba3..0000000 --- a/qick/quick_start/README_ZCU111.md +++ /dev/null @@ -1,169 +0,0 @@ -# QICK quick-start guide - -***Have questions? Contact: ``sarafs AT princeton.edu``*** - -This guide will show you how to set up QICK after configuring your computer and RFSOC ZCU111 board on a local area network (LAN). By the end of this guide you will have run a QICK program in loopback mode (where signals loop back from an RF DAC directly into an RF ADC)! - -### Prerequisites -* A ZCU111 RFSOC evaluation board kit (available for purchase at www.avnet.com). In this guide you will connect the ZCU111 evaluation board to either the XM500 breakout board which comes with the ZCU111 evaluation board kit or the QICK RF board which was custom-designed at Fermilab. The kit includes: - * A ZCU111 evaluation board - * A XM500 breakout board - * An SMA cable that you will use to connect the system in loopback mode - * A power cable (12 volt, 50 watt) for the ZCU111 - * A micro SD card (16 GB) that you will flash the PYNQ 2.6.0 disk image onto - * A screwdriver, hex wrench, and associated screws -* A personal computer with an Ethernet port (this guide assumes a Windows PC with no additional command line tools so as to be accessible to users with little command line programming experience; contact sarafs@princeton.edu if you would like this guide to include support for other operating systems). - * The computer should have git installed. In this guide, Github Desktop is used. - * You can download Github Desktop here: https://desktop.github.com/ - * The computer should have either SSH or PuTTY/PSCP installed. PuTTY is an open-source SSH client for the Windows operating system. This guide uses PuTTY/PSCP for accessibility, as some users are not familiar with the command line. - * You can download PuTTY here: https://www.chiark.greenend.org.uk/~sgtatham/putty/latest.html (for instance `putty-64bit-0.76-installer.msi`). You can also download the PSCP executable from the same link (for instance `pscp.exe`). - * The computer should have the Win32DiskImager utility from the Sourceforge Project page installed. The Win32DiskImager utility is an open-source tool for writing image files to disks. You will use this utility to flash the PYNQ 2.6.0 image onto your micro SD card. - * You can download the Win32DiskImager utility here: https://sourceforge.net/projects/win32diskimager/ -* A router (this guide used a standard Cisco RV160 VPN Router which is available for purchase at www.amazon.com). The router used in this guide has 4 LAN ports. For instance, in a typical qubit control setup you can connect one LAN port to your personal computer, a second LAN port to your ZCU111, and a third point to an Ethernet switch (for example the NETGEAR 24-Port Gigabit Ethernet Unmanaged Switch (JGS524) which is available for purchase at www.amazon.com). That Ethernet switch can place 24 more devices (such as external trigger sources, local oscillators, programmable attenuators or other lab equipment) on the router's subnet, making them accessible to your personal computer. -* Two Ethernet cables that you will use to attach 1) your ZCU111 board and 2) your personal computer to the router. -* A micro SD card reader (such as IOGEAR SuperSpeed USB 3.0 SD/Micro SD Card Reader/Writer (GFR304SD) which is available for purchase at www.amazon.com). -* A torque wrench for tightening SMA cables - -### Flashing the PYNQ image onto your micro SD card -* Your ZCU111 RFSOC evaluation board kit comes with a micro SD card. The QICK requires an up-to-date PYNQ image (as of the writing of this guide, version 2.6.0 and 2.7 are supported), so let's update the micro SD card with this version of the PYNQ image. -* First, download the current PYNQ image from this URL: http://www.pynq.io/board.html under the ZCU111 row. If you downloaded it as a .zip, you need to unzip it to get a .img file. You will see that it's quite a large file. - -

- The PYNQ 2.6.0 image file -

- -* Plug in your micro SD card to your personal computer via your micro SD card reader. If you look in the Windows File Explorer you will see a new disk drive pop up, for example in my case it was the `E:\` drive. This is the drive associated with your micro SD card. -* Now, open the Win32DiskImager utility and configure 1) the image file to be your PYNQ image file and 2) the device to be the `E:\` drive, as in the below picture. Before clicking `Write`, double check that you are not flashing the image file to the wrong drive (e.g. your personal computer hard drive)! - -

- Writing the PYNQ 2.6.0 image onto the micro SD card -

- -* Click `Write`. -* After the write completes, now look in the Windows File Explorer to see what is now contained in the `E:\` drive. You can see several files. `BOOT.BIN` allows the RFSOC to boot and includes the firmware design. `image.ub` stores the Linux kernel. There is also a Python file and an executable. The contents of the `E:\` drive are lightweight and there is plenty more space on the disk (about 6.8 GB!). So we are now ready to load this micro SD card into the ZCU111 board. - -

- The micro SD card drive after a successful write -

- - -### Assembling and powering on your ZCU111 board - -* There are several nice resources on the internet that demonstrate how to assemble the ZCU111 board. For instance, here is a full video guide: https://www.youtube.com/watch?v=4JfKlv8kWhs. The assembly is done using the screwdriver, hex wrench, and associated screws that come with the ZCU111 kit. The recommended screwdriver to install screws is a JIS #1 screwdriver such as a Vessel 220. The 4 mm hex wrench is used to tighten the jackscrew nuts under the screws. -* Use your torque wrench to wire an SMA cable between an RF DAC channel (for this upcoming demo, choose DAC 229 CH3) and an RF ADC channel (choose ADC 224 CH0). In the case of the XM500 breakout board the channel names are written on the board itself. For a more detailed connector mapping, consult pages 95-99 of this Xilinx document: https://www.xilinx.com/support/documentation/boards_and_kits/zcu111/ug1271-zcu111-eval-bd.pdf. -* Slide your micro SD card into its slot on the ZCU111 board. Make sure that switch SW6 of the ZCU111 is in SD card mode according to Table 2-4 of this Xilinx document: https://www.xilinx.com/support/documentation/boards_and_kits/zcu111/ug1271-zcu111-eval-bd.pdf. - -

- Boot mode switch -

- -* Connect your Ethernet cable from a router LAN port to the ZCU111 Ethernet port. -* Power up your router (note that you may have to contact your system administrator to register your router's MAC address to a wall outlet in your building/laboratory). -* Connect the 12 V power cable to the ZCU111. Flip the ZCU111 power switch on (it's next to the power cable). You should hear the fan above the RFSOC chip begin to whir and you should see green LED lights blinking all over the board. You should also see a green LED blinking repeatedly above the ZCU111 Ethernet port to signal that it is connected to the router's network. -* Your board setup should look something like the below cartoon: - -

- An assembled ZCU111 board -

- -### Finding your RFSOC on the router's network -* In the last section, you powered your router on and you connected your ZCU111 board via an Ethernet cable to one of the router's LAN ports. You verified that a green LED was blinking repeatedly above the ZCU111 Ethernet port. -* Now, connect your personal computer via Ethernet to a LAN port of the router. -* Log into your router via a web browser. In the case of the router used in this guide, doing so is straightforward and is explained here: https://www.cisco.com/c/dam/en/us/td/docs/routers/csbr/RV160/Quick_Start_Guide/EN/RV160_qsg_en.pdf -* Look at the list of devices found by your router. You should see two devices; your PC and your ZCU111 (id `pynq`). Take note of the IP address that was assigned to the ZCU111 (in my case it was assigned the address `192.168.1.146`). - -

- Devices found by the router -

- -### Finding your RFSOC via Serial connection -* The IP address of the RFSoC can also be directly obtained via serial connection. -* Connect a PC to the board via the micro USB port. Under the Device Manager under COM ports the RFSoC should show up as a COM connection. Take note of the Port number. -* Using PuTTY, select "Serial" connection type, enter the port number (e.g. `COM12`), and the serial speed, which by default is `115200`. -* This will open a terminal that directly connects to the RFSoC CPU. `ifconfig` should give the assigned IP address. -* If connection problems persist, the default gateway may not be set; this can be checked with `ip route`. There should be an IP address marked as `default`. If this is not present, a default must be set using `sudo ip route add default via xxx.xxx.xxx.1`, replacing the IP address with the local network address. -* Finally, the RFSoC may need to be configured to properly access the internet. Open `/etc/resolv.conf` in a text editor such as `vim` or `nano`, and ensure that it contains `nameserver 8.8.8.8`, `options eth0`. Note that `resolv.conf` may be re-generated when the board is power-cycled. - - -### Connecting to your RFSOC via Jupyter and via SSH - -#### Via Jupyter - -* Now you are prepared to connect to your RFSOC. Before you clone the `qick` repository and copy it onto the RFSOC, let's see what is initially on the RFSOC's operating system (this was determined by the contents of the PYNQ image). To do so, simply enter the IP address assigned to the RFSOC into a web browser on your personal computer: `192.168.1.146`. The username and password for the ZCU111 are by default `xilinx` and `xilinx`, respectively. You can change those by entering `sudo` mode once you've logged into the RFSOC via SSH (you will log in via SSH in the next part of this guide). -* You should see this default Jupyter notebook browser: - -

- PYNQ startup -

- -* You can see that there are a few demo Jupyter notebooks already loaded onto the RFSOC which you can feel free to explore. But now let's connect to the RFSOC via SSH, where you will have more flexibility and control. For instance, only after you have established an SSH connection can you copy the `qick` repo onto the RFSOC and do the upcoming QICK loopback demo. - -#### Via SSH - -* To connect via SSH, open the PuTTY application and input the IP address assigned to the RFSOC (`192.168.1.146`) as below: -

- Using PuTTY (1) -

- -* Click `Open`. You will see the following login screen on a new terminal. The username and password for the ZCU111 are by default `xilinx` and `xilinx`, respectively. - -

- Using PuTTY (2) -

- -* After successfully logging in you will see a Linux terminal. You have now remotely logged on to the RFSOC. - -

- Using PuTTY (3) -

- -### Copy the QICK tools onto your RFSOC - -* Use Github Desktop to clone the `qick` repo onto your personal computer (Google around for resources if you are not sure how to do this). -* Now, copy the `pscp.exe` into the same directory as your cloned `qick` repo, as below: - -

- Folder structure required for PSCP -

- -* Open the Command Prompt application in Windows and, after navigating to the directory containing your cloned `qick` repo, type in the following command (substituting the IP address that was assigned to your RFSOC): - -

- Pushing data to the RFSOC with PSCP -

- -* This copied the `qick` repository into the `jupyter_notebooks` folder in the `/home/xilinx/` directory of the RFSOC. -* Your Jupyter notebook browser has now updated to include the `qick` repository, as shown below: - -

- Jupyter notebook main folder -

- -### Installing the `qick` Python package - - -* Navigate to the `qick_demos` subfolder within the `qick` directory and run the Jupyter notebook `000_Install_qick_package.ipynb`. This will walk you through installing and testing the `qick` package. - -### Running a QICK program in loopback mode - -* Open `00_Send_receive_pulse.ipynb` (also in the `qick_demos` directory) and run the Jupyter notebook cells in order. You should see very similar output to that posted here: https://github.com/openquantumhardware/qick/blob/main/qick_demos/00_Send_receive_pulse.ipynb. You are seeing pulses being sent out of the RFSOC RF DACs and looping back to the RFSOC RF ADCs! In future tutorials you will learn the meaning of all the variables and parameters defined within the Jupyter notebook cells. -* You can also take the opportunity to check that you have flashed the correct PYNQ version: - -

- The correct PYNQ version -

- -### Copy data off of your RFSOC and onto your personal computer - -* Let's say that you have created a `quick_start_demo` directory with your work and you want a local copy of the entire directory (for example, you exported your data to `.png` plots that are within the `quick_start_demo` directory on the RFSOC, and you want to move those plots back to your personal computer). To do this, you do something analogous to when you copied the `qick` repository onto the RFSOC earlier in this guide: -* Open the Command Prompt application in Windows and, after navigating to your local directory containing your `pscp.exe` executable, type in the following command (substituting the IP address that was assigned to your RFSOC): - -

- Pulling data off the RFSOC with PSCP -

- -* Now the `quick_start_demo` directory has been copied to your local directory which contains your `pscp.exe` executable. - -***Hopefully this guide was a helpful introduction to QICK!*** diff --git a/qick/quick_start/README_ZCU216.md b/qick/quick_start/README_ZCU216.md deleted file mode 100644 index 1009dca..0000000 --- a/qick/quick_start/README_ZCU216.md +++ /dev/null @@ -1,180 +0,0 @@ -# QICK quick-start guide for the ZCU216 board - -***Have questions? Contact: ``sarafs AT princeton.edu``*** - -This guide will show you how to set up QICK after configuring your computer and RFSOC ZCU216 board on a local area network (LAN). By the end of this guide you will have run a QICK program in loopback mode (where signals loop back from an RF DAC directly into an RF ADC)! - - - -### Prerequisites -* A ZCU216 RFSOC evaluation board kit (available for purchase at www.avnet.com). In this guide you will connect the ZCU216 eval board with - * A ZCU216 evaluation board (from the kit) - * A CLK-104 clocking board (from the kit) - * A XM655 breakout board (from the kit) - * Two HC2-to-SMA cables (from the kit) - * An SMA cable that you will use to connect the system in loopback mode (from the kit) - * A power cable (12 volt, 50 watt) for the ZCU216 (from the kit) - * A micro SD card (16 GB) that you will flash the PYNQ 2.7.0 disk image onto (from the kit) - * A screwdriver, hex wrench, and associated screws (from the kit) -* A personal computer with an Ethernet port. - * The computer should have git installed. In this guide, Github Desktop is used. - * You can download Github Desktop here: https://desktop.github.com/ - * The computer should have the Win32DiskImager utility from the Sourceforge Project page installed. The Win32DiskImager utility is an open-source tool for writing image files to disks. You will use this utility to flash the PYNQ 2.7.0 image onto your micro SD card. - * You can download the Win32DiskImager utility here: https://sourceforge.net/projects/win32diskimager/ -* A router (this guide used a standard Cisco RV160 VPN Router which is available for purchase at www.amazon.com). The router used in this guide has 4 LAN ports. For instance, in a typical qubit control setup you can connect one LAN port to your personal computer, a second LAN port to your ZCU216, and a third point to an Ethernet switch (for example the NETGEAR 24-Port Gigabit Ethernet Unmanaged Switch (JGS524) which is available for purchase at www.amazon.com). That Ethernet switch can place 24 more devices (such as external trigger sources, local oscillators, programmable attenuators or other lab equipment) on the router's subnet, making them accessible to your personal computer. -* Two Ethernet cables that you will use to attach 1) your ZCU216 board and 2) your personal computer to the router. -* A micro SD card reader (such as IOGEAR SuperSpeed USB 3.0 SD/Micro SD Card Reader/Writer (GFR304SD) which is available for purchase at www.amazon.com). -* A torque wrench for tightening SMA cables - -### Flashing the PYNQ 2.7.0 image onto your micro SD card -* Your ZCU216 RFSOC evaluation board kit comes with a micro SD card that is preloaded with a PYNQ image. The QICK hardware requires PYNQ 2.7.0, so let's update the micro SD card with this version of the PYNQ image. -* First, download the PYNQ 2.7.0 image from the Google Drive link attached to this GitHub issue: https://github.com/sarafs1926/ZCU216-PYNQ/issues/1. You will see that it's quite a large file of approximately 10 GB. - -* Plug in your micro SD card to your personal computer via your micro SD card reader. If you look in the Windows File Explorer you will see a new disk drive pop up, for example in my case it was the `E:\` drive. This is the drive associated with your micro SD card. -* Now, open the Win32DiskImager utility and configure 1) the image file to be your PYNQ 2.7.0 image file and 2) the device to be the `E:\` drive, as in the below picture. Before clicking `Write`, double check that you are not flashing the image file to the wrong drive (e.g. your personal computer hard drive)! - -

- Writing the PYNQ 2.7.0 image onto the micro SD card -

- -* Click `Write`. -* After the write completes, now look in the Windows File Explorer to see what is now contained in the `E:\` drive. You can see several files. `BOOT.BIN` allows the RFSOC to boot and includes the firmware design. `image.ub` stores the Linux kernel. There is also a Python file and an executable. So we are now ready to load this micro SD card into the ZCU216 board. - -

- The micro SD card drive after a successful write -

- - -### Assembling and powering on your ZCU216 board - -* There is a nice resource on the internet that demonstrates how to assemble the ZCU216 board: the basic assembly section of this webpage: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/246153525/RF+DC+Evaluation+Tool+for+ZCU216+board+-+Quick+start. -* After the CLK-104 and XM655 cards are attached to your board, connect the HC2-to-SMA cables to locations JHC3 and JHC7 and tighten with the hex key provided. With the standard QICK ZCU216 firmware, JHC connectors 3,4 and 7 are used to break out the DAC and ADC channels respectively, but the eval board kit only provides two HC2-to-SMA cables (more can be purchased on Digi-Key). -* For detailed connector mapping, consult pages 71-79 of this Xilinx document: https://www.xilinx.com/content/dam/xilinx/support/documents/boards_and_kits/zcu216/ug1390-zcu216-eval-bd.pdf. -* Now, tie the P/N differential SMAs of a DAC (lets say, DAC 6, which is in the below table labeled `2_231` on the XM655 card) to a low frequency balun (10 MHz-1 GHz) on the XM655 card. Also tie the P/N differential SMAs of an ADC (lets say, ADC 0 which is in the below table labeled `0_226` on the XM655 card) to another low frequency balun on the XM655 card. Now connect the balun outputs together to create a loopback from DAC 6 to ADC 0. When you initialize the RFSOC object in your loopback script you will see the mapping between QICK DAC and ADC channels and the tile numbers associated with the various JHC locations on the XM655 card. Here they are listed below, as well. - -* DAC-side - * JHC 3 differential SMAs: - * 2_231 <-> DAC 6 - * 0_231 <-> DAC 4 - * 2_230 <-> DAC 2 - * 0_230 <- DAC 0 - * JHC 4 differential SMAs: - * 1_231 <-> DAC 5 - * 3_230 <-> DAC 3 - * 1_230 <-> DAC 1 - -* ADC-side - * JHC 7 differential SMAs: - * 2_226 <-> ADC 1 - * 0_226 <-> ADC 0 - -* Slide your micro SD card into its slot on the ZCU216 board. Make sure that switch SW2 of the ZCU216 is in SD card mode according to Table 5 of this Xilinx document: https://www.xilinx.com/content/dam/xilinx/support/documents/boards_and_kits/zcu216/ug1390-zcu216-eval-bd.pdf. - -* Connect your Ethernet cable from a router LAN port to the ZCU216 Ethernet port. -* Power up your router (note that you may have to contact your system administrator to register your router's MAC address to a wall outlet in your building/laboratory). -* Connect the 12 V power cable to the ZCU216. Flip the ZCU216 power switch on (it's next to the power cable). You should hear the fan above the RFSOC chip begin to whir and you should see green LED lights blinking all over the board. You should also see a green LED blinking repeatedly above the ZCU216 Ethernet port to signal that it is connected to the router's network. Note that at this point, you should see the 3 LEDs be as follows: - -`PS_LED = flashing green` - -`DONE LED = off` - -`INT_B LED = red` - -It is only after you initialize the QICK firmware that the FPGA has been loaded with its bitstream, so it makes sense that those LEDs are that "unfinished" color since you haven't loaded the firmware onto the FPGA yet. However, the RFSOC processor is running and so you can at this point connect to it via its IP address. So every single time you boot the RFSOC board you will see those same LED patterns that you describe, that is normal. The firmware is loaded later, using the QICK software, every time. The RFSOC processor (which runs Linux and has an IP address like a normal computer) is separate from the RFSOC FPGA. Once you see those LEDs, proceed to the next step. - -### Finding your RFSOC on the router's network -* In the last section, you powered your router on and you connected your ZCU216 board via an Ethernet cable to one of the router's LAN ports. You verified that a green LED was blinking repeatedly above the ZCU216 Ethernet port. -* Now, connect your personal computer via Ethernet to a LAN port of the router. -* Look at the list of devices found by your router. You should see two devices; your PC and your ZCU216 (id `pynq`). One easy way of doing this on a Windows PC is to download the `Advanced IP scanner` tool (https://www.advanced-ip-scanner.com/). Take note of the IP address that was assigned to the ZCU216. - -### Finding your RFSOC via Serial connection -* The IP address of the RFSoC can also be directly obtained via serial connection. -* Connect a PC to the board via the micro USB port. Under the Device Manager under COM ports the RFSoC should show up as a COM connection. Take note of the Port number. -* Using PuTTY, select "Serial" connection type, enter the port number (e.g. `COM12`), and the serial speed, which by default is `115200`. -* This will open a terminal that directly connects to the RFSoC CPU. `ifconfig` should give the assigned IP address. -* If connection problems persist, the default gateway may not be set; this can be checked with `ip route`. There should be an IP address marked as `default`. If this is not present, a default must be set using `sudo ip route add default via xxx.xxx.xxx.1`, replacing the IP address with the local network address. -* Finally, the RFSoC may need to be configured to properly access the internet. Open `/etc/resolv.conf` in a text editor such as `vim` or `nano`, and ensure that it contains `nameserver 8.8.8.8`, `options eth0`. Note that `resolv.conf` may be re-generated when the board is power-cycled. - -### Connecting to your RFSOC via Jupyter and via SSH - -#### Via Jupyter - -* Now you are prepared to connect to your RFSOC. Before you clone the `qick` repository and copy it onto the RFSOC, let's see what is initially on the RFSOC's operating system (this was determined by the contents of the PYNQ image). To do so, simply enter the IP address assigned to the RFSOC into a web browser on your personal computer, for instance it could be: `192.168.1.146`. The username and password for the ZCU216 are by default `xilinx` and `xilinx`, respectively. -* You should see this default Jupyter notebook browser: - -

- PYNQ startup -

- -* You can see that there are a few demo Jupyter notebooks already loaded onto the RFSOC which you can feel free to explore. But now let's connect to the RFSOC via SSH, where you will have more flexibility and control. For instance, only after you have established an SSH connection can you copy the `qick` repo onto the RFSOC and do the upcoming QICK loopback demo. - -#### Via SSH - -* To connect via SSH, open the PuTTY application and input the IP address assigned to the RFSOC (`192.168.1.146`) as below: -

- Using PuTTY (1) -

- -* Click `Open`. You will see the following login screen on a new terminal. The username and password for the ZCU111 are by default `xilinx` and `xilinx`, respectively. - -

- Using PuTTY (2) -

- -* After successfully logging in you will see a Linux terminal. You have now remotely logged on to the RFSOC. - -

- Using PuTTY (3) -

- - -### Copy the QICK tools onto your RFSOC - -* Use Github Desktop to clone the `qick` repo onto your personal computer (Google around for resources if you are not sure how to do this). -* Now, copy the `pscp.exe` into the same directory as your cloned `qick` repo, as below: - -

- Folder structure required for PSCP -

- -* Open the Command Prompt application in Windows and, after navigating to the directory containing your cloned `qick` repo, type in the following command (substituting the IP address that was assigned to your RFSOC): - -

- Pushing data to the RFSOC with PSCP -

- -* This copied the `qick` repository into the `jupyter_notebooks` folder in the `/home/xilinx/` directory of the RFSOC. -* Your Jupyter notebook browser has now updated to include the `qick` repository, as shown below: - -

- Jupyter notebook main folder -

- -### Installing the `qick` Python package - - -* Navigate to the `qick_demos` subfolder within the `qick` directory and run the Jupyter notebook `000_Install_qick_package.ipynb`. This will walk you through installing and testing the `qick` package. - -### Running a QICK program in loopback mode - -* Open `00_Send_receive_pulse.ipynb` (also in the `qick_demos` directory). Run the Jupyter notebook cells in order. You should see very similar output to that posted here: https://github.com/openquantumhardware/qick/blob/main/qick_demos/00_Send_receive_pulse.ipynb. You are seeing pulses being sent out of the RFSOC RF DACs and looping back to the RFSOC RF ADCs! In future tutorials you will learn the meaning of all the variables and parameters defined within the Jupyter notebook cells. -* You can also take the opportunity to check that you have flashed the correct PYNQ version (2.7.0): - -

- The correct PYNQ version -

- -### Copy data off of your RFSOC and onto your personal computer - -* Let's say that you have created a `quick_start_demo` directory with your work and you want a local copy of the entire directory (for example, you exported your data to `.png` plots that are within the `quick_start_demo` directory on the RFSOC, and you want to move those plots back to your personal computer). To do this, you can either store the data in a separate GitHub repo which you can then push back to GitHub so it is available for your download onto your local PC via your browser, or you can use the standard Linux `scp` command to securely copy data from the RFSOC back to the local PC. -* Open the Command Prompt application in Windows and, after navigating to your local directory containing your `pscp.exe` executable, type in the following command (substituting the IP address that was assigned to your RFSOC): - -

- Pulling data off the RFSOC with PSCP -

- -* Now the `quick_start_demo` directory has been copied to your local directory which contains your `pscp.exe` executable. - -***Hopefully this guide was a helpful introduction to QICK!*** diff --git a/qick/quick_start/quick-start-guide-pics/Bootmodeswitch.png b/qick/quick_start/quick-start-guide-pics/Bootmodeswitch.png deleted file mode 100644 index 7e98afc..0000000 Binary files a/qick/quick_start/quick-start-guide-pics/Bootmodeswitch.png and /dev/null differ diff --git a/qick/quick_start/quick-start-guide-pics/Eafterwrite.PNG b/qick/quick_start/quick-start-guide-pics/Eafterwrite.PNG deleted file mode 100644 index e05b76f..0000000 Binary files a/qick/quick_start/quick-start-guide-pics/Eafterwrite.PNG and /dev/null differ diff --git a/qick/quick_start/quick-start-guide-pics/boardpic_cartoon.PNG b/qick/quick_start/quick-start-guide-pics/boardpic_cartoon.PNG deleted file mode 100644 index 93cd227..0000000 Binary files a/qick/quick_start/quick-start-guide-pics/boardpic_cartoon.PNG and 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/dev/null @@ -1,217 +0,0 @@ -"""A setuptools based setup module. -See: -https://packaging.python.org/guides/distributing-packages-using-setuptools/ -https://github.com/pypa/sampleproject -""" - -# Always prefer setuptools over distutils -from setuptools import setup, find_packages -import pathlib - -here = pathlib.Path(__file__).parent.resolve() - -def get_version(rel_path): - """ - qick_lib/qick/VERSION is a text file containing only the version number. - """ - return (here / rel_path).read_text().strip() - -# Get the long description from the README file -long_description = (here / 'README.md').read_text(encoding='utf-8') - -# Arguments marked as "Required" below must be included for upload to PyPI. -# Fields marked as "Optional" may be commented out. - -setup( - # This is the name of your project. The first time you publish this - # package, this name will be registered for you. It will determine how - # users can install this project, e.g.: - # - # $ pip install sampleproject - # - # And where it will live on PyPI: https://pypi.org/project/sampleproject/ - # - # There are some restrictions on what makes a valid project name - # specification here: - # https://packaging.python.org/specifications/core-metadata/#name - name='qick', # Required - - # Versions should comply with PEP 440: - # https://www.python.org/dev/peps/pep-0440/ - # - # For a discussion on single-sourcing the version across setup.py and the - # project code, see - # https://packaging.python.org/en/latest/single_source_version.html - version=get_version("qick_lib/qick/VERSION"), # Required - - # This is a one-line description or tagline of what your project does. This - # corresponds to the "Summary" metadata field: - # https://packaging.python.org/specifications/core-metadata/#summary - description='Quantum Instrumentation Controller Kit software library', # Optional - - # This is an optional longer description of your project that represents - # the body of text which users will see when they visit PyPI. - # - # Often, this is the same as your README, so you can just read it in from - # that file directly (as we have already done above) - # - # This field corresponds to the "Description" metadata field: - # https://packaging.python.org/specifications/core-metadata/#description-optional - long_description=long_description, # Optional - - # Denotes that our long_description is in Markdown; valid values are - # text/plain, text/x-rst, and text/markdown - # - # Optional if long_description is written in reStructuredText (rst) but - # required for plain-text or Markdown; if unspecified, "applications should - # attempt to render [the long_description] as text/x-rst; charset=UTF-8 and - # fall back to text/plain if it is not valid rst" (see link below) - # - # This field corresponds to the "Description-Content-Type" metadata field: - # https://packaging.python.org/specifications/core-metadata/#description-content-type-optional - long_description_content_type='text/markdown', # Optional (see note above) - - # This should be a valid link to your project's main homepage. - # - # This field corresponds to the "Home-Page" metadata field: - # https://packaging.python.org/specifications/core-metadata/#home-page-optional - url='https://github.com/openquantumhardware/qick', # Optional - - # This should be your name or the name of the organization which owns the - # project. - author='Open Quantum Hardware', # Optional - - # This should be a valid email address corresponding to the author listed - # above. - author_email='openquantumhardware@gmail.com', # Optional - - # Classifiers help users find your project by categorizing it. - # - # For a list of valid classifiers, see https://pypi.org/classifiers/ - classifiers=[ # Optional - # How mature is this project? Common values are - # 3 - Alpha - # 4 - Beta - # 5 - Production/Stable - 'Development Status :: 3 - Alpha', - - # Indicate who your project is intended for - 'Intended Audience :: Developers', - 'Topic :: Software Development :: Build Tools', - - # Pick your license as you wish - 'License :: OSI Approved :: MIT License', - - # Specify the Python versions you support here. In particular, ensure - # that you indicate you support Python 3. These classifiers are *not* - # checked by 'pip install'. See instead 'python_requires' below. - 'Programming Language :: Python :: 3', - 'Programming Language :: Python :: 3.6', - 'Programming Language :: Python :: 3.7', - 'Programming Language :: Python :: 3.8', - 'Programming Language :: Python :: 3.9', - 'Programming Language :: Python :: 3 :: Only', - ], - - # This field adds keywords for your project which will appear on the - # project page. What does your project relate to? - # - # Note that this is a list of additional keywords, separated - # by commas, to be used to assist searching for the distribution in a - # larger catalog. - # keywords='sample, setuptools, development', # Optional - - # When your source code is in a subdirectory under the project root, e.g. - # `src/`, it is necessary to specify the `package_dir` argument. - package_dir={'': 'qick_lib'}, # Optional - - # You can just specify package directories manually here if your project is - # simple. Or you can use find_packages(). - # - # Alternatively, if you just want to distribute a single Python file, use - # the `py_modules` argument instead as follows, which will expect a file - # called `my_module.py` to exist: - # - # py_modules=["my_module"], - # - packages=find_packages(where='qick_lib'), # Required - - # Specify which Python versions you support. In contrast to the - # 'Programming Language' classifiers above, 'pip install' will check this - # and refuse to install the project if the version does not match. See - # https://packaging.python.org/guides/distributing-packages-using-setuptools/#python-requires - python_requires='>=3.6, <4', - - # This field lists other packages that your project depends on to run. - # Any package you put here will be installed by pip when your project is - # installed, so they must be valid existing projects. - # - # For an analysis of "install_requires" vs pip's requirements files see: - # https://packaging.python.org/en/latest/requirements.html - # setup_requires=["numpy","cffi"], - - # Only install pynq on the supported architectures. - # If you're not installing this on a Zynq, you won't be able to use qick.py (hardware interface) - # but qick_asm.py, averager_program.py, and the notebooks should still work. - install_requires=[ - "numpy", - "pynq>=2.6;platform_machine=='aarch64' or platform_machine=='armv7l'", - "tqdm", # Optional - ], - - # List additional groups of dependencies here (e.g. development - # dependencies). Users will be able to install these using the "extras" - # syntax, for example: - # - # $ pip install sampleproject[dev] - # - # Similar to `install_requires` above, these must be valid existing - # projects. - extras_require={ - # install all extra optional dependencies - 'full': ['pyro4'], - }, - - # If there are data files included in your packages that need to be - # installed, specify them here. - package_data={ # Optional - 'qick': ['*.bit', '*.hwh', 'VERSION'] - }, - include_package_data=True, - - # Although 'package_data' is the preferred approach, in some case you may - # need to place data files outside of your packages. See: - # http://docs.python.org/distutils/setupscript.html#installing-additional-files - # - # In this case, 'data_file' will be installed into '/my_data' - # data_files=[('my_data', ['data/data_file'])], # Optional - - # To provide executable scripts, use entry points in preference to the - # "scripts" keyword. Entry points provide cross-platform support and allow - # `pip` to create the appropriate form of executable for the target - # platform. - # - # For example, the following would provide a command called `sample` which - # executes the function `main` from this package when invoked: - # entry_points={ # Optional - # 'console_scripts': [ - # 'sample=sample:main', - # ], - # }, - - # List additional URLs that are relevant to your project as a dict. - # - # This field corresponds to the "Project-URL" metadata fields: - # https://packaging.python.org/specifications/core-metadata/#project-url-multiple-use - # - # Examples listed include a pattern for specifying where the package tracks - # issues, where the source is hosted, where to say thanks to the package - # maintainers, and where to support the project financially. The key is - # what's used to render the link text on PyPI. - project_urls={ # Optional - 'Source': 'https://github.com/openquantumhardware/qick', - 'Documentation': 'https://qick-docs.readthedocs.io/en/latest/', - 'Tracker': 'https://github.com/openquantumhardware/qick/issues', - }, -) - diff --git a/qickdawg/__init__.py b/qickdawg/__init__.py deleted file mode 100644 index 9c44fab..0000000 --- a/qickdawg/__init__.py +++ /dev/null @@ -1,5 +0,0 @@ -from qickdawg.util import * -from qickdawg.nvpulsing import * -from qickdawg.fitfunctions import * - -# Now using QICK 0.2.160 as of 7/03/2023 diff --git a/qickdawg/__pycache__/__init__.cpython-311.pyc b/qickdawg/__pycache__/__init__.cpython-311.pyc deleted file mode 100644 index 9d5af1b..0000000 Binary files a/qickdawg/__pycache__/__init__.cpython-311.pyc and /dev/null differ diff --git a/qickdawg/fitfunctions/__init__.py b/qickdawg/fitfunctions/__init__.py deleted file mode 100644 index edd1dbb..0000000 --- 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file mode 100644 index 0000000..8c87223 --- /dev/null +++ b/setup.py @@ -0,0 +1,10 @@ +import setuptools +import json + + +with open("./src/qickdawg/version.json") as file: + __version__ = json.load(file)['version'] + +setuptools.setup( + name='qickdawg', + version=__version__) diff --git a/src/qickdawg/__init__.py b/src/qickdawg/__init__.py new file mode 100644 index 0000000..3fc4907 --- /dev/null +++ b/src/qickdawg/__init__.py @@ -0,0 +1,3 @@ +from .util import * +from .nvpulsing import * +from .fitfunctions import * diff --git a/src/qickdawg/fitfunctions/__init__.py b/src/qickdawg/fitfunctions/__init__.py new file mode 100644 index 0000000..d52b6c4 --- /dev/null +++ b/src/qickdawg/fitfunctions/__init__.py @@ -0,0 +1 @@ +from .exponentialdecay import exponential_decay diff --git a/qickdawg/fitfunctions/exponentialdecay.py b/src/qickdawg/fitfunctions/exponentialdecay.py similarity index 94% rename from qickdawg/fitfunctions/exponentialdecay.py rename to src/qickdawg/fitfunctions/exponentialdecay.py index 8ec6ee1..c165eb1 100644 --- a/qickdawg/fitfunctions/exponentialdecay.py +++ b/src/qickdawg/fitfunctions/exponentialdecay.py @@ -2,5 +2,5 @@ def exponential_decay(x, a, t, y0): - + return a * np.exp(-x / t) + y0 diff --git a/qickdawg/nvpulsing/__init__.py b/src/qickdawg/nvpulsing/__init__.py similarity index 100% rename from qickdawg/nvpulsing/__init__.py rename to src/qickdawg/nvpulsing/__init__.py diff --git a/qickdawg/nvpulsing/development/cpmgxy8ndelaysweep.py b/src/qickdawg/nvpulsing/development/cpmgxy8ndelaysweep.py similarity index 73% rename from qickdawg/nvpulsing/development/cpmgxy8ndelaysweep.py rename to src/qickdawg/nvpulsing/development/cpmgxy8ndelaysweep.py index 6ece116..162038a 100644 --- a/qickdawg/nvpulsing/development/cpmgxy8ndelaysweep.py +++ b/src/qickdawg/nvpulsing/development/cpmgxy8ndelaysweep.py @@ -4,6 +4,7 @@ import numpy as np + class CPMGXY8nDelaySweep(NVAveragerProgram): def initialize(self): """ @@ -18,60 +19,57 @@ def initialize(self): # Get registers for mw self.declare_gen(ch=self.cfg.mw_channel, - nqz=self.cfg.mw_nqz) - + nqz=self.cfg.mw_nqz) + # Setup pulse defaults microwave self.default_pulse_registers(ch=self.cfg.mw_channel, - style='const', - freq=self.cfg.mw_freg, - length=self.cfg.mw_pi2_treg, - gain=self.cfg.mw_gain) - + style='const', + freq=self.cfg.mw_freg, + length=self.cfg.mw_pi2_treg, + gain=self.cfg.mw_gain) + self.set_pulse_registers(ch=self.cfg.mw_channel, phase=0) - - + # Delcare laser controls if self.cfg.laser_control == 'aom': self.declare_gen(ch=self.cfg.aom_channel, nqz=1) self.set_pulse_registers(ch=self.cfg.aom_channel, - style='const', - freq=self.cfg.aom_freg, - gain=self.cfg.aom_gain, - length=self.cfg.laser_on_treg, - phase=0) + style='const', + freq=self.cfg.aom_freg, + gain=self.cfg.aom_gain, + length=self.cfg.laser_on_treg, + phase=0) elif self.cfg.laser_control == 'ttl': pass else: assert 0, "cfg.laser_control must be assigned to 'aom' or 'ttl'" - # Addd loops self.delay_register = self.new_gen_reg(self.cfg.mw_channel, name='delay', init_val=self.cfg.delay_start_treg) self.time_register = self.new_gen_reg(self.cfg.mw_channel, - name='time', - init_val=0) + name='time', + init_val=0) - - if self.cfg.scaling_mode=='exponential': + if self.cfg.scaling_mode == 'exponential': self.add_sweep(NVQickSweep(self, - self.delay_register, - self.cfg.delay_start_treg, - self.cfg.delay_end_treg, - expts=self.cfg.nsweep_points, - scaling_mode= self.cfg.scaling_mode, - scaling_factor=self.cfg.scaling_factor)) + self.delay_register, + self.cfg.delay_start_treg, + self.cfg.delay_end_treg, + expts=self.cfg.nsweep_points, + scaling_mode=self.cfg.scaling_mode, + scaling_factor=self.cfg.scaling_factor)) else: self.add_sweep(NVQickSweep(self, - self.delay_register, - self.cfg.delay_start_treg, - self.cfg.delay_end_treg, - self.cfg.nsweep_points)) + self.delay_register, + self.cfg.delay_start_treg, + self.cfg.delay_end_treg, + self.cfg.nsweep_points)) self.synci(400) # give processor some time to self.cfgure pulses @@ -80,7 +78,6 @@ def initialize(self): self.wait_all() self.sync_all(self.cfg.relax_delay_treg) - ## NEWEST ADD self.mw_length_register = self.get_gen_reg(self.mw_channel, name='time') @@ -114,12 +111,11 @@ def body(self): self.math(0, 26, 26, '+', self.delay_register.addr) - - #pi/2 phase x + # pi/2 phase x self.set_pulse_registers(ch=self.cfg.mw_channel, phase=self.deg2reg(0)) self.pulse(ch=self.cfg.mw_channel) self.mathi(0, 26, 26, '+', self.cfg.mw_pi2_treg) - + self.sync(0, 26) # readout if self.cfg.laser_control == 'aom': @@ -128,17 +124,17 @@ def body(self): self.trigger( pins=[self.cfg.laser_gate_pmod], width=self.cfg.readout_integration_treg - ) + ) t = self.cfg.laser_readout_offset_treg self.trigger(adcs=[0], - pins=[0, 1], - adc_trig_offset=0, - t = t) - t += self.cfg.readout_reference_treg + pins=[0, 1], + adc_trig_offset=0, + t=t) + t += self.cfg.readout_reference_treg self.trigger(adcs=[0], - pins=[0, 1], - adc_trig_offset=0, - t = t) + pins=[0, 1], + adc_trig_offset=0, + t=t) # Pause between pulse sequences, let aom turn off self.wait_all() self.sync_all(self.cfg.relax_delay_treg) @@ -171,9 +167,8 @@ def body(self): # tau delay self.math(0, 26, 26, '+', self.delay_register.addr) - - #pi/2 phase -x + # pi/2 phase -x self.set_pulse_registers(ch=self.cfg.mw_channel, phase=self.deg2reg(180)) self.pulse(ch=self.cfg.mw_channel) self.mathi(0, 26, 26, '+', self.cfg.mw_pi2_treg) @@ -187,17 +182,17 @@ def body(self): self.trigger( pins=[self.cfg.laser_gate_pmod], width=self.cfg.readout_integration_treg - ) + ) t = self.cfg.laser_readout_offset_treg self.trigger(adcs=[0], - pins=[0, 1], - adc_trig_offset=0, - t = t) - t += self.cfg.readout_reference_treg + pins=[0, 1], + adc_trig_offset=0, + t=t) + t += self.cfg.readout_reference_treg self.trigger(adcs=[0], - pins=[0, 1], - adc_trig_offset=0, - t = t) + pins=[0, 1], + adc_trig_offset=0, + t=t) # Pause between pulse sequences, let aom turn off self.wait_all() self.sync_all(self.cfg.relax_delay_treg) @@ -207,7 +202,7 @@ def acquire_decimated(self, soc, *arg, **kwarg): data = super().acquire_decimated(soc, *arg, **kwarg) return data[0][:, 0] - + def analyze_results(self, data): data = np.reshape(data, self.data_shape) @@ -229,18 +224,18 @@ def analyze_results(self, data): d.signal1 = data[:, :, :, 0] d.reference1 = data[:, :, :, 1] if self.data_shape[-1] == 4: - d.signal2 = data[:, :, :, 2] + d.signal2 = data[:, :, :, 2] d.reference2 = data[:, :, :, 3] - if self.data_shape[-1]==2: - d.contrast = ((d.signal1 - d.reference1)/d.reference1 *100) + if self.data_shape[-1] == 2: + d.contrast = ((d.signal1 - d.reference1) / d.reference1 * 100) for _ in range(len(d.contrast.shape) - 1): d.contrast = np.mean(d.contrast, axis=0) d.signal1 = np.mean(d.signal1, axis=0) d.reference1 = np.mean(d.reference1, axis=0) - elif self.data_shape[-1]==4: - d.contrast1 = ((d.signal1 - d.reference1)/d.reference1 *100) - d.contrast2 = ((d.signal2 - d.reference2)/d.reference2 *100) + elif self.data_shape[-1] == 4: + d.contrast1 = ((d.signal1 - d.reference1) / d.reference1 * 100) + d.contrast2 = ((d.signal2 - d.reference2) / d.reference2 * 100) d.contrast = d.contrast1 - d.contrast2 for _ in range(len(d.contrast1.shape) - 1): d.contrast1 = np.mean(d.contrast1, axis=0) @@ -252,6 +247,6 @@ def analyze_results(self, data): d.contrast = np.mean(d.contrast, axis=0) d.x_treg = self.qick_sweeps[0].get_sweep_pts() - d.x_tus = self.qick_sweeps[0].get_sweep_pts()*self.cycles2us(1) + d.x_tus = self.qick_sweeps[0].get_sweep_pts() * self.cycles2us(1) - return d \ No newline at end of file + return d diff --git a/qickdawg/nvpulsing/development/lockinodmrtwosources.py b/src/qickdawg/nvpulsing/development/lockinodmrtwosources.py similarity index 60% rename from qickdawg/nvpulsing/development/lockinodmrtwosources.py rename to src/qickdawg/nvpulsing/development/lockinodmrtwosources.py index 760b901..49f0814 100644 --- a/qickdawg/nvpulsing/development/lockinodmrtwosources.py +++ b/src/qickdawg/nvpulsing/development/lockinodmrtwosources.py @@ -4,6 +4,7 @@ import numpy as np + class LockinODMRTwoSources(NVAveragerProgram): def initialize(self): @@ -17,34 +18,40 @@ def initialize(self): # Get registers for mw1 self.declare_gen(ch=self.cfg.mw1_channel, nqz=self.cfg.mw1_nqz) - + # Setup pulse defaults microwave self.set_pulse_registers(ch=self.cfg.mw1_channel, - style='const', - freq=self.cfg.mw1_start_freg, - gain= self.cfg.mw1_gain, - length=self.cfg.readout_treg, - phase=0) - + style='const', + freq=self.cfg.mw1_start_freg, + gain=self.cfg.mw1_gain, + length=self.cfg.readout_treg, + phase=0) + # Get registers for mw1 self.declare_gen(ch=self.cfg.mw2_channel, nqz=self.cfg.mw1_nqz) - + # Setup pulse defaults microwave self.set_pulse_registers(ch=self.cfg.mw2_channel, - style='const', - freq=self.cfg.mw2_start_freg, - gain= self.cfg.mw2_gain, - length=self.cfg.readout_treg, - phase=self.cfg.mw2_phase_preg) - + style='const', + freq=self.cfg.mw2_start_freg, + gain=self.cfg.mw2_gain, + length=self.cfg.readout_treg, + phase=self.cfg.mw2_phase_preg) ## Get frequency register and convert frequency values to integers - self.mw1_frequency_register=self.get_gen_reg(self.cfg.mw1_channel, "freq") - self.mw2_frequency_register=self.get_gen_reg(self.cfg.mw2_channel, "freq") + self.mw1_frequency_register = self.get_gen_reg(self.cfg.mw1_channel, "freq") + self.mw2_frequency_register = self.get_gen_reg(self.cfg.mw2_channel, "freq") + + df_points = (self.cfg.mw1_end_freg - self.cfg.mw1_start_freg) // self.cfg.mw1_delta_freg + 1 - df_points = (self.cfg.mw1_end_freg - self.cfg.mw1_start_freg)//self.cfg.mw1_delta_freg +1 - - self.add_sweep(NVQickSweep(self, self.mw1_frequency_register, self.cfg.mw1_start_freqMHz, self.cfg.mw1_end_freqMHz, df_points, source2=self.mw2_frequency_register)) + self.add_sweep( + NVQickSweep( + self, + self.mw1_frequency_register, + self.cfg.mw1_start_freqMHz, + self.cfg.mw1_end_freqMHz, + df_points, + source2=self.mw2_frequency_register)) if self.cfg.pre_init: self.pulse(ch=self.cfg.mw1_channel) @@ -54,23 +61,23 @@ def initialize(self): self.synci(400) # give processor some time to configure pulses def body(self): - t0 = 0 + t0 = 0 + + self.pulse(ch=self.cfg.mw1_channel, t=t0) + self.pulse(ch=self.cfg.mw2_channel, t=t0) - self.pulse(ch=self.cfg.mw1_channel, t=t0) - self.pulse(ch=self.cfg.mw2_channel, t=t0) + self.trigger(adcs=[0], + adc_trig_offset=0) - self.trigger(adcs=[0], - adc_trig_offset=0) + self.wait_all() + self.sync_all(self.cfg.relax_delay_treg) - self.wait_all() - self.sync_all(self.cfg.relax_delay_treg) - - self.trigger(adcs=[0], - adc_trig_offset=0) + self.trigger(adcs=[0], + adc_trig_offset=0) + + self.wait_all() + self.sync_all(self.cfg.relax_delay_treg) - self.wait_all() - self.sync_all(self.cfg.relax_delay_treg) - def analyze_results(self, data): data = np.reshape(data, self.data_shape) @@ -85,24 +92,24 @@ def analyze_results(self, data): reference = data[:, :, :, 1] odmr = (signal - reference) - odmr_contrast = (signal - reference)/reference *100 - + odmr_contrast = (signal - reference) / reference * 100 + for _ in range(len(odmr.shape) - 1): odmr = np.mean(odmr, axis=0) signal = np.mean(signal, axis=0) reference = np.mean(reference, axis=0) odmr_contrast = np.mean(odmr_contrast, axis=0) - + d = ItemAttribute() d.odmr = odmr d.signal = signal d.reference = reference d.odmr_contrast = odmr_contrast - + d.frequencies = self.qick_sweeps[0].get_sweep_pts() - + return d - + def acquire(self, soc, *arg, **kwarg): data = super().new_acquire(soc, *arg, **kwarg) @@ -110,4 +117,3 @@ def acquire(self, soc, *arg, **kwarg): data = self.analyze_results(data) return data - diff --git a/qickdawg/nvpulsing/development/lockinodmrtwosources2.py b/src/qickdawg/nvpulsing/development/lockinodmrtwosources2.py similarity index 70% rename from qickdawg/nvpulsing/development/lockinodmrtwosources2.py rename to src/qickdawg/nvpulsing/development/lockinodmrtwosources2.py index 2b1eb36..150817d 100644 --- a/qickdawg/nvpulsing/development/lockinodmrtwosources2.py +++ b/src/qickdawg/nvpulsing/development/lockinodmrtwosources2.py @@ -6,6 +6,7 @@ import matplotlib.pyplot as plt import matplotlib.image as mpimg + class LockinODMRTwoSources2(NVAveragerProgram): def initialize(self): @@ -22,11 +23,11 @@ def initialize(self): self.declare_gen(ch=self.cfg.aom_channel, nqz=1) self.set_pulse_registers(ch=self.cfg.aom_channel, - style='const', - freq=self.cfg.aom_freg, - gain=self.cfg.aom_gain, - length=self.cfg.readout_integration_treg, - phase=0) + style='const', + freq=self.cfg.aom_freg, + gain=self.cfg.aom_gain, + length=self.cfg.readout_integration_treg, + phase=0) elif self.cfg.laser_control == 'ttl': pass else: @@ -34,35 +35,34 @@ def initialize(self): # Get registers for mw 1 self.declare_gen(ch=self.cfg.mw_channel, nqz=self.cfg.mw_nqz) - + # Setup pulse defaults microwave self.default_pulse_registers(ch=self.cfg.mw_channel, style='const', - gain= self.cfg.mw_gain, + gain=self.cfg.mw_gain, length=self.cfg.readout_integration_treg, phase=0) - + self.set_pulse_registers(ch=self.cfg.mw_channel, freq=self.cfg.mw_start_freg - ) - + ) # Get registers for mw2 self.declare_gen(ch=self.cfg.mw2_channel, nqz=self.cfg.mw2_nqz) - + # Setup pulse defaults microwave self.default_pulse_registers(ch=self.cfg.mw2_channel, style='const', - gain= self.cfg.mw2_gain, + gain=self.cfg.mw2_gain, length=self.cfg.readout_integration_treg, phase=self.cfg.mw2_phase_preg) self.set_pulse_registers(ch=self.cfg.mw2_channel, freq=self.cfg.mw_start_freg - ) + ) - self.mw1_frequency_register=self.get_gen_reg(self.cfg.mw_channel, "freq") - self.mw2_frequency_register=self.get_gen_reg(self.cfg.mw2_channel, "freq") + self.mw1_frequency_register = self.get_gen_reg(self.cfg.mw_channel, "freq") + self.mw2_frequency_register = self.get_gen_reg(self.cfg.mw2_channel, "freq") self.add_sweep(NVQickSweep(self, self.mw1_frequency_register, @@ -71,7 +71,6 @@ def initialize(self): self.cfg.nsweep_points, source2_reg=self.mw2_frequency_register)) - self.synci(400) # give processor some time to self.cfgure pulses if self.cfg.pre_init: @@ -80,22 +79,22 @@ def initialize(self): if self.cfg.laser_control == 'aom': self.pulse(ch=self.cfg.aom_channel) self.sync_all(self.cfg.relax_delay_treg) - + elif self.cfg.laser_control == 'ttl': self.trigger( pins=[self.cfg.laser_gate_pmod], width=self.cfg.readout_integration_treg, adc_trig_offset=0 - ) - self.sync_all(self.cfg.readout_integration_treg+self.cfg.relax_delay_treg) + ) + self.sync_all(self.cfg.readout_integration_treg + self.cfg.relax_delay_treg) def body(self): - if self.cfg.laser_control=='aom': - t0=0 + if self.cfg.laser_control == 'aom': + t0 = 0 self.pulse(ch=self.cfg.mw_channel, t=t0) self.pulse(ch=self.cfg.mw2_channel, t=t0) - + self.pulse(ch=self.cfg.aom_channel) self.trigger(adcs=[0], adc_trig_offset=0) @@ -106,38 +105,36 @@ def body(self): self.pulse(ch=self.cfg.aom_channel) self.trigger(adcs=[0], adc_trig_offset=0) - - + self.wait_all() self.sync_all(self.cfg.relax_delay) - - if self.cfg.laser_control=='ttl': + if self.cfg.laser_control == 'ttl': t0 = 0 self.pulse(ch=self.cfg.mw_channel, t=t0) self.pulse(ch=self.cfg.mw2_channel, t=t0) self.trigger(adcs=[0], - pins=[self.cfg.laser_gate_pmod], - width=self.cfg.readout_integration_treg, - adc_trig_offset=0, - t=t0) + pins=[self.cfg.laser_gate_pmod], + width=self.cfg.readout_integration_treg, + adc_trig_offset=0, + t=t0) t0 += self.cfg.readout_integration_treg t0 += self.cfg.relax_delay_treg - + self.trigger(adcs=[0], - pins=[self.cfg.laser_gate_pmod], - width=self.cfg.readout_integration_treg, - adc_trig_offset=0, - t=t0 - ) + pins=[self.cfg.laser_gate_pmod], + width=self.cfg.readout_integration_treg, + adc_trig_offset=0, + t=t0 + ) self.sync_all(self.cfg.relax_delay_treg) self.wait_all() - + def analyze_results(self, data): data = np.reshape(data, self.data_shape) - data = data/self.cfg.readout_integration_treg + data = data / self.cfg.readout_integration_treg if len(self.data_shape) == 2: signal = data[:, 0] @@ -150,43 +147,43 @@ def analyze_results(self, data): reference = data[:, :, :, 1] odmr = (signal - reference) - odmr_contrast = (signal - reference)/reference *100 - + odmr_contrast = (signal - reference) / reference * 100 + for _ in range(len(odmr.shape) - 1): odmr = np.mean(odmr, axis=0) signal = np.mean(signal, axis=0) reference = np.mean(reference, axis=0) odmr_contrast = np.mean(odmr_contrast, axis=0) - + d = ItemAttribute() d.odmr = odmr d.signal = signal d.reference = reference d.odmr_contrast = odmr_contrast - + d.frequencies = self.qick_sweeps[0].get_sweep_pts() - + return d - + def plot_sequence(self): - plt.figure(figsize=(10,10)) + plt.figure(figsize=(10, 10)) plt.axis('off') plt.imshow(mpimg.imread('../graphics/ODMR.jpg')) - plt.text(240,710,"Repeat {} times".format(self.cfg.reps),fontsize=16) - plt.text(170,465,"readout_integration = {} us".format(int(self.cfg.readout_integration_tus)),fontsize=14) - plt.text(485,490,"relax_delay \n = {} us".format(str(self.cfg.relax_delay_tus)[:4]),fontsize=14) - plt.text(90,520,"Sweep linearly from {} MHz to {} MHz in steps of {} MHz".format(int(self.cfg.mw_start_fMHz),int(self.cfg.mw_end_fMHz),str(self.cfg.mw_delta_fMHz)[:4]), fontsize=14) + plt.text(240, 710, "Repeat {} times".format(self.cfg.reps), fontsize=16) + plt.text(170, 465, "readout_integration = {} us".format(int(self.cfg.readout_integration_tus)), fontsize=14) + plt.text(485, 490, "relax_delay \n = {} us".format(str(self.cfg.relax_delay_tus)[:4]), fontsize=14) + plt.text(90, 520, "Sweep linearly from {} MHz to {} MHz in steps of {} MHz".format( + int(self.cfg.mw_start_fMHz), int(self.cfg.mw_end_fMHz), str(self.cfg.mw_delta_fMHz)[:4]), fontsize=14) plt.title(" ODMR Pulse Sequence", fontsize=20) - def time_per_rep(self): - t = self.cfg.readout_integration_tus*2 - t += self.cfg.relax_delay_tus *2 - t *= self.cfg.nsweep_points /1e6 + t = self.cfg.readout_integration_tus * 2 + t += self.cfg.relax_delay_tus * 2 + t *= self.cfg.nsweep_points / 1e6 return t def total_time(self): - return self.time_per_rep() * self.cfg.reps \ No newline at end of file + return self.time_per_rep() * self.cfg.reps diff --git a/qickdawg/nvpulsing/development/nvqicksweep.py b/src/qickdawg/nvpulsing/development/nvqicksweep.py similarity index 91% rename from qickdawg/nvpulsing/development/nvqicksweep.py rename to src/qickdawg/nvpulsing/development/nvqicksweep.py index 38806c3..c8be278 100644 --- a/qickdawg/nvpulsing/development/nvqicksweep.py +++ b/src/qickdawg/nvpulsing/development/nvqicksweep.py @@ -18,7 +18,7 @@ class NVQickSweep(AbsQickSweep): Class that generates the assembly language code to change parameters between measurements. Modified from the original QickSweep class to handle pulse length sweep and implement exponential scaling - + Attributes ---------- prog @@ -50,7 +50,7 @@ class NVQickSweep(AbsQickSweep): update generates the assembly code to update the sweep parameter after each iteration of the loop - + reset generates the assembly code to rset the swept parameter(s) to the initial value(s) @@ -65,7 +65,7 @@ def __init__(self, prog, reg, start, stop, expts, label=None, super().__init__(prog) self.reg = reg - + self.start = start self.stop = stop self.expts = expts @@ -95,7 +95,8 @@ def __init__(self, prog, reg, start, stop, expts, label=None, self.scaling_factor = scaling_factor if self.scaling_mode == 'exponential': - assert self.scaling_factor in ['17/16', '9/8', '5/4', '3/2'], 'Currently accepting only scaling values 17/16, 9/8, /5/4, 3/2' + assert self.scaling_factor in ['17/16', '9/8', '5/4', + '3/2'], 'Currently accepting only scaling values 17/16, 9/8, /5/4, 3/2' self.numerator, self.denominator = self.scaling_factor.split('/') self.numerator = int(self.numerator) self.denominator = int(self.denominator) @@ -103,7 +104,6 @@ def __init__(self, prog, reg, start, stop, expts, label=None, self.temp_reg = self.prog.new_gen_reg(self.reg.page) self.source2_reg = source2_reg - def get_sweep_pts(self): ''' Method that returns a 1D array of points for which the main sweep parameter is swept over @@ -112,33 +112,29 @@ def get_sweep_pts(self): with setps determined by self.scaling_factor. see qickdawg.int_exp_scale for details ''' - - - - - if self.scaling_mode=='linear': + if self.scaling_mode == 'linear': return np.linspace(self.start, self.stop, self.expts) - elif self.scaling_mode=='exponential': + elif self.scaling_mode == 'exponential': return int_exp_scale(self.start, self.stop, self.scaling_factor) def update(self): """ Method that generates the assembly code to update the swept register value for each iteration of the appropriate loop - + """ - if self.scaling_mode=='linear': + if self.scaling_mode == 'linear': self.reg.set_to(self.reg, '+', self.step_val) - if self.label=='length': + if self.label == 'length': self.mw_mode_register.set_to(self.mw_mode_register, '+', self.step_val) if self.source2_reg is not None: self.source2_reg.set_to(self.source2_reg, '+', self.step_val) - - elif self.scaling_mode=='exponential': + + elif self.scaling_mode == 'exponential': self.prog.bitwi(self.reg.page, self.temp_reg.addr, self.reg.addr, '>>', self.nshift) - self.prog.math(self.reg.page, self.reg.addr, self.reg.addr, '+', self.temp_reg.addr ) + self.prog.math(self.reg.page, self.reg.addr, self.reg.addr, '+', self.temp_reg.addr) def reset(self): """ @@ -148,13 +144,12 @@ def reset(self): """ self.reg.reset() - + if self.source2_reg is not None: # self.source2_reg.reset() self.prog.set_pulse_registers(ch=self.prog.cfg.mw2_channel, - freq = self.prog.cfg.mw_start_freg) + freq=self.prog.cfg.mw_start_freg) - if self.label=='length': + if self.label == 'length': self.prog.set_pulse_registers(ch=self.mw_channel, length=self.start) - \ No newline at end of file diff --git a/qickdawg/nvpulsing/getreadoutwindow.py b/src/qickdawg/nvpulsing/getreadoutwindow.py similarity index 91% rename from qickdawg/nvpulsing/getreadoutwindow.py rename to src/qickdawg/nvpulsing/getreadoutwindow.py index 3d7ac5a..4605ff1 100644 --- a/qickdawg/nvpulsing/getreadoutwindow.py +++ b/src/qickdawg/nvpulsing/getreadoutwindow.py @@ -46,13 +46,13 @@ def get_readout_window(config, n_time_bins): laser_readout_offset_treg = config.laser_readout_offset_treg prog = ReadoutWindow(config) data_off = prog.acquire_decimated(progress=False) - print(i, config.laser_readout_offset_treg) + # print(i, config.laser_readout_offset_treg) else: config.laser_readout_offset_treg += 1020 prog = ReadoutWindow(config) data = prog.acquire_decimated(progress=False) data_off = np.append(data_off, data) - print(i, config.laser_readout_offset_treg) + # print(i, config.laser_readout_offset_treg) config.laser_readout_offset_treg = laser_readout_offset_treg config.mw_pi2_tus = pi2 @@ -63,12 +63,12 @@ def get_readout_window(config, n_time_bins): laser_readout_offset_treg = config.laser_readout_offset_treg prog = ReadoutWindow(config) data_on = prog.acquire_decimated(progress=False) - print(i, config.laser_readout_offset_treg) + # print(i, config.laser_readout_offset_treg) else: config.laser_readout_offset_treg += 1020 prog = ReadoutWindow(config) data = prog.acquire_decimated(progress=False) data_on = np.append(data_on, data) - print(i, config.laser_readout_offset_treg) + # print(i, config.laser_readout_offset_treg) return data_on, data_off, prog diff --git a/qickdawg/nvpulsing/hahnechodelaysweep.py b/src/qickdawg/nvpulsing/hahnechodelaysweep.py similarity index 95% rename from qickdawg/nvpulsing/hahnechodelaysweep.py rename to src/qickdawg/nvpulsing/hahnechodelaysweep.py index 8fde135..5d2327b 100644 --- a/qickdawg/nvpulsing/hahnechodelaysweep.py +++ b/src/qickdawg/nvpulsing/hahnechodelaysweep.py @@ -14,6 +14,7 @@ import matplotlib.image as mpimg import os + class HahnEchoDelaySweep(NVAveragerProgram): ''' An NVAveragerProgram class that generates and executes a sequence used @@ -219,7 +220,7 @@ def body(self): def acquire(self, raw_data=False, *arg, **kwarg): - data = super().acquire(reads_per_rep=4, *arg, **kwarg) + data = super().acquire(readouts_per_experiment=4, *arg, **kwarg) if raw_data is False: data = self.analyze_pulse_sequence_results(data) @@ -239,7 +240,6 @@ def plot_sequence(cfg=None): graphics_folder = os.path.join(os.path.dirname(__file__), '../../graphics') image_path = os.path.join(graphics_folder, 'HAHN_ECHO.png') - if cfg is None: plt.figure(figsize=(12, 12)) plt.axis('off') @@ -274,12 +274,16 @@ def plot_sequence(cfg=None): plt.text(310, 395, " pi/2", fontsize=12) plt.text(240, 465, "laser_readout_offset = {} treg".format(cfg.laser_readout_offset_treg), fontsize=10) plt.text(390, 337, "readout_integration = {} us".format(str(cfg.readout_integration_tus)[:4]), fontsize=10) - plt.text(650, 357, "readout_integration \n = {} us".format(str(cfg.readout_integration_tus)[:4]), fontsize=10) + plt.text(650, 357, "readout_integration \n = {} us".format( + str(cfg.readout_integration_tus)[:4]), fontsize=10) plt.text(850, 357, "relax_delay \n = {} us".format(str(cfg.relax_delay_tus)[:4]), fontsize=10) plt.text(400, 430, "laser_on = {} us".format(cfg.laser_on_tus), fontsize=12) - plt.text(375, 605, " Sweep delay from {} us to {} us \n\ - in {} {} steps".format(int(cfg.delay_start_tns), int(cfg.delay_end_tns), cfg.nsweep_points, cfg.scaling_mode), fontsize=12) - plt.title(" Hahn Echo Pulse Sequence", fontsize=20) + plt.text( + 375, 605, " Sweep delay from {} us to {} us \n\ + in {} {} steps".format( + int(cfg.delay_start_tns), int(cfg.delay_end_tns), + cfg.nsweep_points, cfg.scaling_mode), fontsize=12) + plt.title(" Hahn Echo Pulse Sequence", fontsize=20) def time_per_rep(self): diff --git a/qickdawg/nvpulsing/laseroff.py b/src/qickdawg/nvpulsing/laseroff.py similarity index 99% rename from qickdawg/nvpulsing/laseroff.py rename to src/qickdawg/nvpulsing/laseroff.py index 938fe61..eae040d 100644 --- a/qickdawg/nvpulsing/laseroff.py +++ b/src/qickdawg/nvpulsing/laseroff.py @@ -31,7 +31,7 @@ def laser_off(config, reps=1, readout_integration_treg=65535): data = np.mean(data) data /= readout_integration_treg - return data + return float(data) class LaserOff(NVAveragerProgram): diff --git a/qickdawg/nvpulsing/laseron.py b/src/qickdawg/nvpulsing/laseron.py similarity index 99% rename from qickdawg/nvpulsing/laseron.py rename to src/qickdawg/nvpulsing/laseron.py index 8422eb1..4f2242e 100644 --- a/qickdawg/nvpulsing/laseron.py +++ b/src/qickdawg/nvpulsing/laseron.py @@ -32,7 +32,7 @@ def laser_on(config, reps=1, readout_integration_treg=1020): data = np.mean(data) data /= readout_integration_treg - return data + return float(data) class LaserOn(NVAveragerProgram): diff --git a/qickdawg/nvpulsing/lockinodmr.py b/src/qickdawg/nvpulsing/lockinodmr.py similarity index 94% rename from qickdawg/nvpulsing/lockinodmr.py rename to src/qickdawg/nvpulsing/lockinodmr.py index 691f45b..146a88b 100644 --- a/qickdawg/nvpulsing/lockinodmr.py +++ b/src/qickdawg/nvpulsing/lockinodmr.py @@ -16,6 +16,7 @@ import matplotlib.image as mpimg import os + class LockinODMR(NVAveragerProgram): ''' An NVAveragerProgram class that generates and executes ODMR measurements by @@ -175,7 +176,7 @@ def body(self): def acquire(self, raw_data=False, *arg, **kwarg): - data = super().acquire(reads_per_rep=2, *arg, **kwarg) + data = super().acquire(readouts_per_experiment=2, *arg, **kwarg) if raw_data is False: data = self.analyze_results(data) @@ -256,7 +257,6 @@ def total_time(self): return self.time_per_rep() * self.cfg.reps def plot_sequence(cfg=None): - ''' Function that plots the pulse sequence generated by this program @@ -268,7 +268,7 @@ def plot_sequence(cfg=None): ''' graphics_folder = os.path.join(os.path.dirname(__file__), '../../graphics') image_path = os.path.join(graphics_folder, 'ODMR.png') - + if cfg is None: plt.figure(figsize=(10, 10)) plt.axis('off') @@ -276,7 +276,13 @@ def plot_sequence(cfg=None): plt.text(295, 340, " config.reps", fontsize=16) plt.text(200, 275, "config.readout_integration_t#", fontsize=14) plt.text(520, 275, "config.relax_delay_t#", fontsize=14) - plt.text(145, 430, "Sweep linearly from config.mw_start_f# to config.mw_end_f# \n in steps of config.mw_delta_f#", fontsize=14) + string = "Sweep linearly from config.mw_start_f# to config.mw_end_f# \n" + string += " in steps of config.mw_delta_f#" + plt.text( + 145, + 430, + string, + fontsize=14) plt.title(" ODMR Pulse Sequence", fontsize=20) else: plt.figure(figsize=(10, 10)) @@ -285,5 +291,8 @@ def plot_sequence(cfg=None): plt.text(295, 340, "Repeat {} times".format(cfg.reps), fontsize=16) plt.text(200, 275, "readout_integration = {} us".format(int(cfg.readout_integration_tus)), fontsize=14) plt.text(520, 290, "relax_delay \n = {} us".format(str(cfg.relax_delay_tus)[:4]), fontsize=14) - plt.text(130, 400, "Sweep linearly from {} MHz to {} MHz in steps of {} MHz".format(int(cfg.mw_start_fMHz), int(cfg.mw_end_fMHz), str(cfg.mw_delta_fMHz)[:4]), fontsize=14) + plt.text( + 130, 400, "Sweep linearly from {} MHz to {} MHz in steps of {} MHz".format( + int(cfg.mw_start_fMHz), int(cfg.mw_end_fMHz), + str(cfg.mw_delta_fMHz)[:4]), fontsize=14) plt.title(" ODMR Pulse Sequence", fontsize=20) diff --git a/qickdawg/nvpulsing/nvaverageprogram.py b/src/qickdawg/nvpulsing/nvaverageprogram.py similarity index 66% rename from qickdawg/nvpulsing/nvaverageprogram.py rename to src/qickdawg/nvpulsing/nvaverageprogram.py index 0b8b432..6d13c2f 100644 --- a/qickdawg/nvpulsing/nvaverageprogram.py +++ b/src/qickdawg/nvpulsing/nvaverageprogram.py @@ -5,24 +5,30 @@ qick.NDAverageProgram """ -from qick import QickProgram -from qick.qick_asm import QickRegisterManagerMixin +from qick.asm_v1 import QickRegisterManagerMixin, AcquireProgram from qick.averager_program import AbsQickSweep from tqdm.auto import tqdm import qickdawg as qd + try: from rpyc.utils.classic import obtain except ModuleNotFoundError: def obtain(i): return i +import operator +import functools import numpy as np from typing import List +from collections import defaultdict from ..util.itemattribute import ItemAttribute +import logging +logger = logging.getLogger(__name__) + -class NVAveragerProgram(QickRegisterManagerMixin, QickProgram): +class NVAveragerProgram(QickRegisterManagerMixin, AcquireProgram): """ NVAveragerProgram class, for experiments that sweep over multiple variables in qick-dawg ordered in reps, sweep_n,... sweep_0. @@ -31,8 +37,6 @@ class NVAveragerProgram(QickRegisterManagerMixin, QickProgram): Parameters -------------------------------------------------------------------------- - soccfg - an instance of QickConfig cfg an instance of NVConfiguration @@ -50,6 +54,8 @@ class NVAveragerProgram(QickRegisterManagerMixin, QickProgram): """ + COUNTER_ADDR = 1 + def __init__(self, cfg): """ Constructor for the NVAveragerProgram. Make the ND sweep asm commands. @@ -65,17 +71,21 @@ def __init__(self, cfg): self.rounds = cfg['soft_avgs'] if "rounds" in cfg: self.rounds = cfg['rounds'] + # reps loop is the outer loop, first-added sweep is innermost loop + loop_dims = [cfg['reps'], *self.sweep_axes[::-1]] + # average over the reps axis + self.setup_acquire(counter_addr=self.COUNTER_ADDR, loop_dims=loop_dims, avg_level=0) def initialize(self): """ - Abstract method for initializing the program. Should include the instructions that will be executed once at the - beginning of the qick program. This is filled in by child classes to make a pulse program. + Abstract method for initializing the program and can include any instructions + that are executed once at the beginning of the program. """ pass def body(self): """ - Abstract method for the body of the program. This is filled in by child classes to make a pulse program. + Abstract method for the body of the program """ pass @@ -94,7 +104,7 @@ def make_program(self): """ Method that makes the assmebly code for an N dimensional sweep pogram. The steps are as follows: 1. run the overloaded self.initialize() method to initialize the mw and adc channels etc. - 2. asserts N <7 + 2. asserts N < 5 3. sets the run count to 0 4. sets and labels repitition counter 5. Adds reset and start for each sweep, with label @@ -111,12 +121,10 @@ def make_program(self): rep_count = 14 # repetition counter n_sweeps = len(self.qick_sweeps) - if n_sweeps > 7: # to be safe, only register 15-21 in page 0 can be used as sweep counters + if n_sweeps > 5: # to be safe, only register 15-21 in page 0 can be used as sweep counters raise OverflowError(f"too many qick inner loops ({n_sweeps}), run out of counter registers") - counter_regs = (np.arange(n_sweeps) + 15).tolist() # not sure why this has to be a list (np.array doesn't work) - + counter_regs = (np.arange(n_sweeps) + 17).tolist() # not sure why this has to be a list (np.array doesn't work) self.regwi(0, rcount, 0) # reset total run count - # set repetition counter and tag self.regwi(0, rep_count, self.cfg["reps"] - 1) self.label("LOOP_rep") @@ -130,12 +138,11 @@ def make_program(self): # run body and total_run_counter++ self.body() self.mathi(0, rcount, rcount, "+", 1) - self.memwi(0, rcount, 1) + self.memwi(0, rcount, self.COUNTER_ADDR) # add update and stop condition for each sweep for creg, swp in zip(counter_regs, self.qick_sweeps): swp.update() - # pass self.loopnz(0, creg, f"LOOP_{swp.label if swp.label is not None else creg}") # stop condition for repetition @@ -145,32 +152,35 @@ def make_program(self): def get_expt_pts(self): """ - Method that returns the swept values for each sweep as a 2D array. + :return: """ sweep_pts = [] for swp in self.qick_sweeps: sweep_pts.append(swp.get_sweep_pts()) return sweep_pts - def acquire(self, reads_per_rep=1, load_pulses=True, start_src="internal", progress=False, debug=False): + def acquire(self, load_pulses=True, readouts_per_experiment: int = 1, + save_experiments: List = None, start_src: str = "internal", + progress=False, remove_offset=True): """ Method that exectues the qick program and accumulates data from the data buffer until the proram is complete For NV measurements, the results are DC values and thus only have I values (rather than I and Q) Parameters ---------- - soc : QickSoc - qick.QickSoc instance - reads_per_rep + readouts_per_experiment : int int number of readout triggers in the loop body load_pulses bool: if True, load pulse envelopes - start_src - str: "internal" (tProc starts immediately) or "external" (each round waits for an external trigger) - progress + start_src: str + "internal" (tProc starts immediately) or + "external" (each round waits for an external trigger) + progress: bool bool: if true, displays progress bar - debug - bool: if true, displays assembly code for tProc program + remove_offset : bool + Some readouts (muxed and tProc-configured) introduce a small fixed offset to the I and Q + values of every decimated sample. This subtracts that offset, if any, before returning the + averaged IQ values or rotating to apply software thresholding. Returns ------- @@ -186,73 +196,102 @@ def acquire(self, reads_per_rep=1, load_pulses=True, start_src="internal", progr dimensions for a simple averaging program: (n_ch, n_reads, 2) dimensions for a program with multiple expts/steps: (n_ch, n_reads, n_expts, 2) """ - self.config_all(qd.soc, load_pulses=load_pulses, start_src=start_src, debug=debug) - n_ro = len(self.ro_chs) + if readouts_per_experiment is not None: + self.set_reads_per_shot(readouts_per_experiment) - expts = self.expts - if expts is None: - expts = 1 - total_reps = expts * self.reps - total_count = total_reps * reads_per_rep - d_buf = np.zeros((n_ro, total_count, 2), dtype=np.int32) - self.stats = [] + self.config_all(qd.soc, load_pulses=load_pulses, load_mem=False) + + if any([x is None for x in [self.counter_addr, self.loop_dims, self.avg_level]]): + raise RuntimeError("data dimensions need to be defined with setup_acquire() before calling acquire()") - if 'rounds' not in self.cfg: - self.cfg.rounds = 1 + # configure tproc for internal/external start + qd.soc.start_src(start_src) + + # n_ro = len(self.ro_chs) + + total_count = functools.reduce(operator.mul, self.loop_dims) + self.d_buf = [np.zeros((*self.loop_dims, nreads, 2), dtype=np.int64) for nreads in self.reads_per_shot] + self.stats = [] # select which tqdm progress bar to show hiderounds = True hidereps = True if progress: - if self.rounds > 1: + if self.cfg.rounds > 1: hiderounds = False else: hidereps = False - # avg_d doesn't have a specific shape here, so that it's easier for child programs to write custom _average_buf - self.dbuf_shape = [] + # avg_d doesn't have a specific shape here, so that it's easier for child programs + # to write custom _average_buf + self.get_data_shape(readouts_per_experiment) - if reads_per_rep > 1: - self.dbuf_shape.append(reads_per_rep) + # Actual data acquisition - for swp in self.qick_sweeps: - self.dbuf_shape = [swp.expts] + self.dbuf_shape - - if self.cfg.reps > 1: - self.dbuf_shape = [self.cfg.reps] + self.dbuf_shape - - if self.cfg.rounds > 1: - self.data_shape = [self.cfg.rounds] + self.dbuf_shape - else: - self.data_shape = self.dbuf_shape - - for i, ir in enumerate(tqdm(range(self.rounds), disable=hiderounds)): + # avg_d = None + for ir in tqdm(range(self.cfg.rounds), disable=hiderounds): # Configure and enable buffer capture. self.config_bufs(qd.soc, enable_avg=True, enable_buf=False) + # Reload data memory. + qd.soc.reload_mem() + count = 0 with tqdm(total=total_count, disable=hidereps) as pbar: - qd.soc.start_readout( - total_reps, - counter_addr=self.counter_addr, - ch_list=list(self.ro_chs), - reads_per_rep=reads_per_rep) + qd.soc.start_readout(total_count, counter_addr=self.counter_addr, + ch_list=list(self.ro_chs), reads_per_shot=self.reads_per_shot) while count < total_count: new_data = obtain(qd.soc.poll_data()) - for d, s in new_data: - # print(len(new_data), count, total_count) - new_points = d.shape[1] - d_buf[:, count:count + new_points] = d + for new_points, (d, s) in new_data: + # print(new_points, (d, s)) + for ii, nreads in enumerate(self.reads_per_shot): + # print(count, new_points, nreads, d[ii].shape, total_count) + if new_points * nreads != d[ii].shape[0]: + logger.error( + "data size mismatch: new_points=%d, nreads=%d, data shape %s" % + (new_points, nreads, d[ii].shape)) + if count + new_points > total_count: + logger.error( + "got too much data: count=%d, new_points=%d, total_count=%d" % + (count, new_points, total_count)) + # use reshape to view the d_buf array in a shape that matches the raw data + self.d_buf[ii].reshape((-1, 2))[count * nreads:(count + new_points) * nreads] = d[ii] count += new_points self.stats.append(s) pbar.update(new_points) - if i == 0: - data = np.array(d_buf[0][:, 0]) - else: - data = np.append(data, [np.array(d_buf[0][:, 0])]) - return data + return self.d_buf[0][..., 0] + + def get_data_shape(self, readouts_per_experiment): + ''' + Determines the shape of the data to be returned and stores as an attribute + + Parameters + ---------- + readouts_per_experiment : int + The number of readouts per experimental cycle + + Returns + ------- + None + ''' + + self.dbuf_shape = [] + + if readouts_per_experiment > 1: + self.dbuf_shape.append(readouts_per_experiment) + + for swp in self.qick_sweeps: + self.dbuf_shape = [swp.expts] + self.dbuf_shape + + if self.cfg.reps > 1: + self.dbuf_shape = [self.cfg.reps] + self.dbuf_shape + + if self.cfg.rounds > 1: + self.data_shape = [self.cfg.rounds] + self.dbuf_shape + else: + self.data_shape = self.dbuf_shape def acquire_decimated(self, *arg, **kwarg): ''' @@ -269,26 +308,41 @@ def acquire_decimated(self, *arg, **kwarg): ''' - data = super().acquire_decimated(qd.soc, *arg, **kwarg) + data = super().acquire_decimated(qd.soc, soft_avgs=self.cfg['soft_avgs'], *arg, **kwarg) return data[0][:, 0] - def trigger_no_off(self, adcs=None, pins=None, adc_trig_offset=0, t=0, rp=0, r_out=31): - """ - Method that is a slight modificaiton of qick.QickProgram.trigger(). - This method does not turn off the PMOD pins, thus also does not require a width parameter + def trigger_no_off( + self, + adcs=None, + pins=None, + ddr4=False, + mr=False, + adc_trig_offset=270, + t=0, + width=10, + rp=0, + r_out=16): + """Pulse the readout(s) and marker pin(s) with a specified pulse width at a specified time t+adc_trig_offset. + If no readouts are specified, the adc_trig_offset is not applied. Parameters ---------- adcs : list of int - List of readout channels to trigger (index in 'readouts' list) [0], [1], or [0, 1] + List of readout channels to trigger (index in 'readouts' list) pins : list of int - List of marker pins to pulsem, i.e. PMOD channels. + List of marker pins to pulse. Use the pin numbers in the QickConfig printout. + ddr4 : bool + If True, trigger the DDR4 buffer. + mr : bool + If True, trigger the MR buffer. adc_trig_offset : int, optional Offset time at which the ADC is triggered (in tProc cycles) t : int, optional The number of tProc cycles at which the ADC trigger starts + width : int, optional + The width of the trigger pulse, in tProc cycles rp : int, optional Register page r_out : int, optional @@ -298,33 +352,43 @@ def trigger_no_off(self, adcs=None, pins=None, adc_trig_offset=0, t=0, rp=0, r_o adcs = [] if pins is None: pins = [] - if not adcs and not pins: - raise RuntimeError("must pulse at least one ADC or pin") - - out = 0 - for adc in adcs: - out |= (1 << self.soccfg['readouts'][adc]['trigger_bit']) + # if not any([adcs, pins, ddr4]): + # raise RuntimeError("must pulse at least one readout or pin") + + outdict = defaultdict(int) + for ro in adcs: + rocfg = self.soccfg['readouts'][ro] + outdict[rocfg['trigger_port']] |= (1 << rocfg['trigger_bit']) + # update trigger count for this readout + self.ro_chs[ro]['trigs'] += 1 for pin in pins: - out |= (1 << pin) + pincfg = self.soccfg['tprocs'][0]['output_pins'][pin] + outdict[pincfg[1]] |= (1 << pincfg[2]) + if ddr4: + rocfg = self.soccfg['ddr4_buf'] + outdict[rocfg['trigger_port']] |= (1 << rocfg['trigger_bit']) + if mr: + rocfg = self.soccfg['mr_buf'] + outdict[rocfg['trigger_port']] |= (1 << rocfg['trigger_bit']) t_start = t - if adcs: + if any([adcs, ddr4, mr]): t_start += adc_trig_offset # update timestamps with the end of the readout window - for adc in adcs: - ts = self.get_timestamp(ro_ch=adc) + for ro in adcs: + ts = self.get_timestamp(ro_ch=ro) if t_start < ts: - print("Readout time %d appears to conflict with previous readout ending at %f?" % (t, ts)) + logger.warning("Readout time %d appears to conflict with previous readout ending at %f?" % (t, ts)) # convert from readout clock to tProc clock - ro_length = self.ro_chs[adc]['length'] - ro_length *= self.soccfg['fs_proc'] / self.soccfg['readouts'][adc]['f_fabric'] - self.set_timestamp(t_start + ro_length, ro_ch=adc) - - trig_output = self.soccfg['tprocs'][0]['trig_output'] - - self.regwi(rp, r_out, out, f'out = 0b{out:>016b}') - self.seti(trig_output, rp, r_out, t_start, f'ch =0 out = ${r_out} @t = {t}') - # self.seti(trig_output, rp, 0, t_end, f'ch =0 out = 0 @t = {t}') + ro_length = self.ro_chs[ro]['length'] + ro_length *= self.tproccfg['f_time'] / self.soccfg['readouts'][ro]['f_output'] + self.set_timestamp(t_start + ro_length, ro_ch=ro) + # t_end = t_start + width + + for outport, out in outdict.items(): + self.regwi(rp, r_out, out, f'out = 0b{out:>016b}') + self.seti(outport, rp, r_out, t_start, f'ch =0 out = ${r_out} @t = {t}') + # self.seti(outport, rp, 0, t_end, f'ch =0 out = 0 @t = {t}') def ttl_readout(self): ''' diff --git a/qickdawg/nvpulsing/nvconfiguration.py b/src/qickdawg/nvpulsing/nvconfiguration.py similarity index 100% rename from qickdawg/nvpulsing/nvconfiguration.py rename to src/qickdawg/nvpulsing/nvconfiguration.py diff --git a/qickdawg/nvpulsing/nvqicksweep.py b/src/qickdawg/nvpulsing/nvqicksweep.py similarity index 100% rename from qickdawg/nvpulsing/nvqicksweep.py rename to src/qickdawg/nvpulsing/nvqicksweep.py diff --git a/qickdawg/nvpulsing/plintensity.py b/src/qickdawg/nvpulsing/plintensity.py similarity index 99% rename from qickdawg/nvpulsing/plintensity.py rename to src/qickdawg/nvpulsing/plintensity.py index 06edbd8..e132670 100644 --- a/qickdawg/nvpulsing/plintensity.py +++ b/src/qickdawg/nvpulsing/plintensity.py @@ -12,6 +12,7 @@ import matplotlib.image as mpimg import os + class PLIntensity(NVAveragerProgram): """ NVAveragerProgram which simply turns on an AOM and collects PL intensity from an @@ -80,10 +81,9 @@ def acquire(self, *arg, **kwarg): data = np.mean(data) / self.cfg.readout_integration_treg - return data + return float(data) def plot_sequence(cfg=None): - ''' Method that plots the pulse sequence generated by this program diff --git a/qickdawg/nvpulsing/rabisweep.py b/src/qickdawg/nvpulsing/rabisweep.py similarity index 89% rename from qickdawg/nvpulsing/rabisweep.py rename to src/qickdawg/nvpulsing/rabisweep.py index 178b808..6581d1d 100644 --- a/qickdawg/nvpulsing/rabisweep.py +++ b/src/qickdawg/nvpulsing/rabisweep.py @@ -14,6 +14,7 @@ import matplotlib.image as mpimg import os + class RabiSweep(NVAveragerProgram): ''' An NVAveragerProgram class that generates and executes a sequence used @@ -102,6 +103,7 @@ def initialize(self): initiailzes the spin state with a laser pulse ''' self.check_cfg() + self.declare_readout(ch=self.cfg.adc_channel, freq=0, length=self.cfg.readout_integration_treg, @@ -124,7 +126,7 @@ def initialize(self): # configure the sweep self.mw_length_register = self.new_gen_reg(self.cfg.mw_channel, - name='length', + name='mw_length', init_val=self.cfg.mw_start_treg) self.add_sweep(NVQickSweep(self, @@ -132,7 +134,7 @@ def initialize(self): start=self.cfg.mw_start_treg, stop=self.cfg.mw_end_treg, expts=self.cfg.nsweep_points, - label='length', + label='mw_length', mw_channel=self.cfg.mw_channel)) self.synci(400) # give processor some time to configure pulses @@ -167,7 +169,7 @@ def body(self): def acquire(self, raw_data=False, *arg, **kwarg): - data = super().acquire(reads_per_rep=4, *arg, **kwarg) + data = super().acquire(readouts_per_experiment=4, *arg, **kwarg) if raw_data is False: data = self.analyze_pulse_sequence_results(data) @@ -175,7 +177,6 @@ def acquire(self, raw_data=False, *arg, **kwarg): return data def plot_sequence(cfg=None): - ''' Function that plots the pulse sequence generated by this program @@ -188,14 +189,17 @@ def plot_sequence(cfg=None): graphics_folder = os.path.join(os.path.dirname(__file__), '../../graphics') image_path = os.path.join(graphics_folder, 'RABI.png') - if cfg is None: plt.figure(figsize=(15, 15)) plt.axis('off') plt.imshow(mpimg.imread(image_path)) plt.text(455, 510, "config.reps", fontsize=14) plt.text(350, 440, "config.laser_on", fontsize=14) - plt.text(195, 580, " Sweep pi/2 pulse time linearly from config.mw_start to config.mw_end in config.mw_delta sized steps", fontsize=12) + plt.text( + 195, + 580, + " Sweep pi/2 pulse time linearly from config.mw_start to config.mw_end in config.mw_delta sized steps", + fontsize=12) plt.text(265, 355, "config.readout_integration", fontsize=14) plt.text(527, 355, " config.readout_integration", fontsize=14) plt.text(190, 368, " pi/2\npulse", fontsize=14) @@ -210,11 +214,19 @@ def plot_sequence(cfg=None): plt.imshow(mpimg.imread(image_path)) plt.text(420, 510, "Repeat {} times".format(cfg.reps), fontsize=14) plt.text(350, 440, "laser_on_tus = {} us".format(str(cfg.laser_on_tus)[:4]), fontsize=14) - plt.text(195, 580, " Sweep pi/2 pulse time linearly from {} time register to {} time register in steps of {} time register".format(int(cfg.mw_start_treg), int(cfg.mw_end_treg), str(cfg.mw_delta_treg)[:4]), fontsize=12) - plt.text(265, 370, "readout_integration \n = {} ns".format(int(cfg.readout_integration_tns)), fontsize=14) - plt.text(527, 370, "readout_integration \n = {} ns".format(int(cfg.readout_integration_tns)), fontsize=14) + + string = f"Sweep pi/2 pulse time linearly from {int(cfg.mw_start_treg)} time register" + string += f" to {int(cfg.mw_end_treg)} time register in steps of " + string += f"{str(cfg.mw_delta_treg)[:4]} time register" + plt.text(195, 580, string, fontsize=12) + + plt.text(265, 370, "readout_integration \n = {} ns".format( + int(cfg.readout_integration_tns)), fontsize=14) + plt.text(527, 370, "readout_integration \n = {} ns".format( + int(cfg.readout_integration_tns)), fontsize=14) plt.text(190, 368, " pi/2\npulse", fontsize=14) plt.text(735, 370, "relax_delay \n = {} ns".format(int(cfg.relax_delay_tns)), fontsize=14) plt.text(235, 407, "laser_offset = {} ns".format(int(cfg.laser_readout_offset_tns)), fontsize=14) - plt.text(430, 407, "readout_reference_start = {} us".format(int(cfg.readout_reference_start_tus)), fontsize=14) + plt.text(430, 407, "readout_reference_start = {} us".format( + int(cfg.readout_reference_start_tus)), fontsize=14) plt.title(" Rabi Oscillation Pulse Sequence", fontsize=20) diff --git a/qickdawg/nvpulsing/ramsey.py b/src/qickdawg/nvpulsing/ramsey.py similarity index 93% rename from qickdawg/nvpulsing/ramsey.py rename to src/qickdawg/nvpulsing/ramsey.py index 03cefe4..717b966 100644 --- a/qickdawg/nvpulsing/ramsey.py +++ b/src/qickdawg/nvpulsing/ramsey.py @@ -14,6 +14,7 @@ import matplotlib.image as mpimg import os + class Ramsey(NVAveragerProgram): ''' An NVAveragerProgram class that generates and executes a sequence used @@ -191,7 +192,7 @@ def body(self): def acquire(self, raw_data=False, *arg, **kwarg): - data = super().acquire(reads_per_rep=4, *arg, **kwarg) + data = super().acquire(readouts_per_experiment=4, *arg, **kwarg) if raw_data is False: data = self.analyze_pulse_sequence_results(data) @@ -203,7 +204,6 @@ def time_per_rep(self): pass def plot_sequence(cfg=None): - ''' Function that plots the pulse sequence generated by this program @@ -216,7 +216,6 @@ def plot_sequence(cfg=None): graphics_folder = os.path.join(os.path.dirname(__file__), '../../graphics') image_path = os.path.join(graphics_folder, 'Ramsey.png') - if cfg is None: plt.figure(figsize=(12, 12)) plt.axis('off') @@ -232,7 +231,11 @@ def plot_sequence(cfg=None): plt.text(650, 340, "config.readout_integration", fontsize=10) plt.text(850, 340, "config.relax_delay", fontsize=10) plt.text(400, 430, "config.laser_on", fontsize=10) - plt.text(220, 605, "Sweep delay linearly from config.delay_start to config.delay_end in config.nsweep_points \n with scaling given by config.scaling_mode", fontsize=12) + + string = "Sweep delay linearly from config.delay_start to config.delay_end in config.nsweep_points \n" + string += " with scaling given by config.scaling_mode" + plt.text(220, 605, string, fontsize=12) + plt.title(" Ramsey Pulse Sequence", fontsize=20) else: plt.figure(figsize=(12, 12)) @@ -245,8 +248,13 @@ def plot_sequence(cfg=None): plt.text(310, 340, " pi/2", fontsize=12) plt.text(240, 465, "laser_readout_offset = {} treg".format(cfg.laser_readout_offset_treg), fontsize=10) plt.text(390, 337, "readout_integration = {} us".format(str(cfg.readout_integration_tus)[:4]), fontsize=10) - plt.text(650, 357, "readout_integration \n = {} us".format(str(cfg.readout_integration_tus)[:4]), fontsize=10) + plt.text(650, 357, "readout_integration \n = {} us".format( + str(cfg.readout_integration_tus)[:4]), fontsize=10) plt.text(850, 357, "relax_delay \n = {} us".format(str(cfg.relax_delay_tus)[:4]), fontsize=10) plt.text(400, 430, "laser_on = {} us".format(cfg.laser_on_tus), fontsize=12) - plt.text(375, 605, " Sweep delay linearly from {} to {} \n in {} steps".format(int(cfg.delay_start_tns), int(cfg.delay_end_tns), cfg.nsweep_points), fontsize=12) + + string = f" Sweep delay linearly from {int(cfg.delay_start_tns)} " + string += "to { int(cfg.delay_end_tns)} \n" + string += " in {cfg.nsweep_points} steps" + plt.text(375, 605, string, fontsize=12) plt.title(" Ramsey Pulse Sequence", fontsize=20) diff --git a/qickdawg/nvpulsing/readoutwindow.py b/src/qickdawg/nvpulsing/readoutwindow.py similarity index 96% rename from qickdawg/nvpulsing/readoutwindow.py rename to src/qickdawg/nvpulsing/readoutwindow.py index 96f733f..5d2fb94 100644 --- a/qickdawg/nvpulsing/readoutwindow.py +++ b/src/qickdawg/nvpulsing/readoutwindow.py @@ -10,6 +10,7 @@ import matplotlib.pyplot as plt import matplotlib.image as mpimg +import os class ReadoutWindow(NVAveragerProgram): @@ -165,18 +166,20 @@ def body(self): def plot_sequence(cfg=None): ''' Function that plots the pulse sequence generated by this program - + Parameters ---------- cfg: `.NVConfiguration` or None(default None) If None, this plots the squence with configuration labels If a `.NVConfiguration` object is supplied, the configuraiton value are added to the plot ''' + graphics_folder = os.path.join(os.path.dirname(__file__), '../../graphics') + image_path = os.path.join(graphics_folder, 'READOUT.png') if cfg is None: plt.figure(figsize=(10, 10)) plt.axis('off') - plt.imshow(mpimg.imread('../graphics/READOUT.png')) + plt.imshow(mpimg.imread(image_path)) plt.text(265, 440, "config.soft_avgs", fontsize=14) plt.text(205, 305, "config.readout_length_t#", fontsize=12) plt.text(445, 305, "config.relax_delay_t#", fontsize=14) @@ -186,7 +189,7 @@ def plot_sequence(cfg=None): else: plt.figure(figsize=(10, 10)) plt.axis('off') - plt.imshow(mpimg.imread('../graphics/READOUT.png')) + plt.imshow(mpimg.imread(image_path)) plt.text(265, 440, "Repeat {} times".format(cfg.soft_avgs), fontsize=14) plt.text(205, 305, "readout_length = {} treg".format(int(cfg.readout_length_treg)), fontsize=12) plt.text(445, 305, "relax_delay = {} us".format(str(cfg.relax_delay_tus)[:4]), fontsize=14) diff --git a/qickdawg/nvpulsing/t1delaysweep.py b/src/qickdawg/nvpulsing/t1delaysweep.py similarity index 93% rename from qickdawg/nvpulsing/t1delaysweep.py rename to src/qickdawg/nvpulsing/t1delaysweep.py index f778b58..92a83d4 100644 --- a/qickdawg/nvpulsing/t1delaysweep.py +++ b/src/qickdawg/nvpulsing/t1delaysweep.py @@ -14,6 +14,7 @@ import matplotlib.image as mpimg import os + class T1DelaySweep(NVAveragerProgram): ''' An NVAveragerProgram class that generates and executes a sequence used @@ -27,7 +28,7 @@ class T1DelaySweep(NVAveragerProgram): instance of qickdawg.NVConfiguration class with attributes: .adc_channel (required) int channel which is reading data 0 or 1 - + .mw_channel (required) qick channel that provides microwave excitation 0 or 1 for RFSoC4x2 @@ -36,7 +37,7 @@ class T1DelaySweep(NVAveragerProgram): nyquist zone for microwave generator (1 or 2) .mw_gain (required) gain of micrwave channel, in register values, from 0 to 2**15-1 - + .pre_init (required) boolian value that indicates whether to pre-pulse the laser to initialize the spin state @@ -107,7 +108,7 @@ def initialize(self): ## Setup Microwave Channel self.declare_gen(ch=self.cfg.mw_channel, nqz=self.cfg.mw_nqz) - + self.default_pulse_registers( ch=self.cfg.mw_channel, style='const', @@ -175,7 +176,7 @@ def body(self): # readout self.sync_all(self.cfg.mw_readout_delay_treg) self.ttl_readout() - + ## Second pulse sequence ## pi(x) off - delay - readout ## Second pulse sequence @@ -187,10 +188,10 @@ def body(self): # readout self.sync_all(self.cfg.mw_readout_delay_treg) self.ttl_readout() - + def acquire(self, raw_data=False, *arg, **kwarg): - data = super().acquire(reads_per_rep=4, *arg, **kwarg) + data = super().acquire(readouts_per_experiment=4, *arg, **kwarg) if raw_data is False: data = self.analyze_pulse_sequence_results(data) @@ -201,7 +202,7 @@ def acquire(self, raw_data=False, *arg, **kwarg): def plot_sequence(cfg=None): ''' Function that plots the pulse sequence generated by this program - + Parameters ---------- cfg: `.NVConfiguration` or None(default None) @@ -211,13 +212,12 @@ def plot_sequence(cfg=None): graphics_folder = os.path.join(os.path.dirname(__file__), '../../graphics') image_path = os.path.join(graphics_folder, 'T1.png') - if cfg is None: plt.figure(figsize=(12, 12)) plt.axis('off') plt.imshow(mpimg.imread(image_path)) plt.text(500, 700, "config.reps", fontsize=14) - + plt.text(305, 335, "delay", fontsize=10) plt.text(400, 385, " config.readout_reference_start", fontsize=10) plt.text(250, 335, "pi", fontsize=10) @@ -227,7 +227,12 @@ def plot_sequence(cfg=None): plt.text(650, 340, "config.readout_integration", fontsize=10) plt.text(850, 340, "config.relax_delay", fontsize=10) plt.text(400, 430, "config.laser_on", fontsize=10) - plt.text(220, 605, "Sweep delay from config.delay_start to config.delay_end in config.nsweep_points \n with scaling given by config.scaling_mode", fontsize=12) + + string = "Sweep delay from config.delay_start to config.delay_end in " + string += "config.nsweep_points \n" + string += " with scaling given by config.scaling_mode" + + plt.text(220, 605, string, fontsize=12) plt.title(" T1 Pulse Sequence", fontsize=20) else: plt.figure(figsize=(12, 12)) @@ -239,8 +244,10 @@ def plot_sequence(cfg=None): plt.text(250, 335, "pi", fontsize=10) plt.text(240, 465, "laser_readout_offset = {} treg".format(cfg.laser_readout_offset_treg), fontsize=10) plt.text(390, 337, "readout_integration = {} us".format(str(cfg.readout_integration_tus)[:4]), fontsize=10) - plt.text(650, 357, "readout_integration \n = {} us".format(str(cfg.readout_integration_tus)[:4]), fontsize=10) + plt.text(650, 357, "readout_integration \n = {} us".format( + str(cfg.readout_integration_tus)[:4]), fontsize=10) plt.text(850, 357, "relax_delay \n = {} us".format(str(cfg.relax_delay_tus)[:4]), fontsize=10) plt.text(400, 430, "laser_on = {} us".format(cfg.laser_on_tus), fontsize=12) - plt.text(325, 605, " Sweep delay from {} us to {} us \n in {} {} steps".format(int(cfg.delay_start_tns), int(cfg.delay_end_tns), cfg.nsweep_points, cfg.scaling_mode), fontsize=12) + plt.text(325, 605, " Sweep delay from {} us to {} us \n in {} {} steps".format( + int(cfg.delay_start_tns), int(cfg.delay_end_tns), cfg.nsweep_points, cfg.scaling_mode), fontsize=12) plt.title(" T1 Pulse Sequence", fontsize=20) diff --git a/qickdawg/util/__init__.py b/src/qickdawg/util/__init__.py similarity index 100% rename from qickdawg/util/__init__.py rename to src/qickdawg/util/__init__.py diff --git a/qickdawg/util/absolute.py b/src/qickdawg/util/absolute.py similarity index 100% rename from qickdawg/util/absolute.py rename to src/qickdawg/util/absolute.py diff --git a/qickdawg/util/compresseddifference.py b/src/qickdawg/util/compresseddifference.py similarity index 100% rename from qickdawg/util/compresseddifference.py rename to src/qickdawg/util/compresseddifference.py diff --git a/qickdawg/util/cpmgxy8arb.py b/src/qickdawg/util/cpmgxy8arb.py similarity index 100% rename from qickdawg/util/cpmgxy8arb.py rename to src/qickdawg/util/cpmgxy8arb.py diff --git a/qickdawg/util/intexpscale.py b/src/qickdawg/util/intexpscale.py similarity index 100% rename from qickdawg/util/intexpscale.py rename to src/qickdawg/util/intexpscale.py diff --git a/qickdawg/util/itemattribute.py b/src/qickdawg/util/itemattribute.py similarity index 100% rename from qickdawg/util/itemattribute.py rename to src/qickdawg/util/itemattribute.py diff --git a/qickdawg/util/liveplot.py b/src/qickdawg/util/liveplot.py similarity index 100% rename from qickdawg/util/liveplot.py rename to src/qickdawg/util/liveplot.py diff --git a/qickdawg/util/startclient.py b/src/qickdawg/util/startclient.py similarity index 100% rename from qickdawg/util/startclient.py rename to src/qickdawg/util/startclient.py diff --git a/src/qickdawg/version.json b/src/qickdawg/version.json new file mode 100644 index 0000000..af1d575 --- /dev/null +++ b/src/qickdawg/version.json @@ -0,0 +1,3 @@ +{ + "version": "0.0.5" +} \ No newline at end of file