diff --git a/src/rcc/backup.rs b/src/rcc/backup.rs index 221569c0..2b6c4ec1 100644 --- a/src/rcc/backup.rs +++ b/src/rcc/backup.rs @@ -96,7 +96,7 @@ mod rtc { fn reset(self) -> Self { // unsafe: Owned exclusive access to this bitfield interrupt::free(|_| { - let bdcr = unsafe { &(*RCC::ptr()).bdcr() }; + let bdcr = unsafe { (*RCC::ptr()).bdcr() }; #[cfg(not(feature = "rm0455"))] bdcr.modify(|_, w| w.bdrst().set_bit()); @@ -104,9 +104,9 @@ mod rtc { bdcr.modify(|_, w| w.bdrst().clear_bit()); #[cfg(feature = "rm0455")] - bdcr().modify(|_, w| w.vswrst().set_bit()); + bdcr.modify(|_, w| w.vswrst().set_bit()); #[cfg(feature = "rm0455")] - bdcr().modify(|_, w| w.vswrst().set_bit()); + bdcr.modify(|_, w| w.vswrst().set_bit()); }); self } diff --git a/src/rcc/mod.rs b/src/rcc/mod.rs index 38fc9a16..a4b8d542 100644 --- a/src/rcc/mod.rs +++ b/src/rcc/mod.rs @@ -1016,16 +1016,16 @@ impl Rcc { let cdcfgr1 = rcc.cdcfgr1().read(); debug!( "CDCFGR1 register: CDCPRE={:?} HPRE={:?} CDPPRE={:?}", - cdcfgr1.cdcpre().variant().unwrap(), - cdcfgr1.hpre().variant().unwrap(), - cdcfgr1.cdppre().variant().unwrap(), + cdcfgr1.cdcpre().variant(), + cdcfgr1.hpre().variant(), + cdcfgr1.cdppre().variant(), ); let cdcfgr2 = rcc.cdcfgr2().read(); debug!( "CDCFGR2 register: CDPPRE1={:?} CDPPRE1={:?}", - cdcfgr2.cdppre1().variant().unwrap(), - cdcfgr2.cdppre2().variant().unwrap(), + cdcfgr2.cdppre1().variant(), + cdcfgr2.cdppre2().variant(), ); let srdcfgr = rcc.srdcfgr().read(); diff --git a/src/rcc/rec.rs b/src/rcc/rec.rs index 2ff49ba2..db5ff099 100644 --- a/src/rcc/rec.rs +++ b/src/rcc/rec.rs @@ -507,7 +507,7 @@ peripheral_reset_and_enable_control! { AHB1, "" => [ Crc, Usb1Otg [group clk: Usb USB cdccip2 "USB"], - Adc12 [group clk: Adc(Variant) ADC12 srdccip "ADC"] + Adc12 [group clk: Adc(Variant) ADC srdccip "ADC"] ]; @@ -649,8 +649,7 @@ peripheral_reset_and_enable_control! { #[cfg(all())] APB2, "Advanced Peripheral Bus 2 (APB2) peripherals" => [ - Tim1, Tim8, Tim15, Tim16, Tim17, - Hrtim [kernel clk: Hrtim HRTIM cfg "HRTIM"] + Tim1, Tim8, Tim15, Tim16, Tim17 ]; #[cfg(not(feature = "rm0455"))] APB2, "" => [ @@ -660,7 +659,8 @@ peripheral_reset_and_enable_control! { Spi1 [group clk: Spi123(Variant) SAI1 d2ccip1 "SPI1/2/3"], Spi4 [group clk: Spi45(Variant) SPI45 d2ccip1 "SPI4/5"], - Spi5 [group clk: Spi45] + Spi5 [group clk: Spi45], + Hrtim [kernel clk: Hrtim HRTIM cfg "HRTIM"] ]; #[cfg(any(feature = "rm0433", feature = "rm0399"))] APB2, "" => [ @@ -675,16 +675,16 @@ peripheral_reset_and_enable_control! { Dfsdm1 [kernel clk: Dfsdm1 DFSDM1 cdccip1 "DFSDM1"], Sai1 [kernel clk: Sai1(Variant) SAI1 cdccip1 "SAI1"], - Sai2 [kernel clk_a: Sai2A(Variant) SAI1 cdccip1 + Sai2 [kernel clk_a: Sai2A(Variant) SAI2A cdccip1 "Sub-Block A of SAI2"] - [kernel clk_b: Sai2B(Variant) SAI1 cdccip1 + [kernel clk_b: Sai2B(Variant) SAI2A cdccip1 "Sub-Block B of SAI2"], Spi1 [group clk: Spi123(Variant) SAI1 cdccip1 "SPI1/2/3"], Spi4 [group clk: Spi45(Variant) SPI45 cdccip1 "SPI4/5"], Spi5 [group clk: Spi45], - Usart1 [group clk: Usart16910(Variant) USART16 cdccip2 "USART1/6/9/10"], + Usart1 [group clk: Usart16910(Variant) USART16910 cdccip2 "USART1/6/9/10"], Usart6 [group clk: Usart16910], Uart9 [group clk: Usart16910], Usart10 [group clk: Usart16910] @@ -697,14 +697,12 @@ peripheral_reset_and_enable_control! { Usart10 [group clk: Usart16910] ]; - #[cfg(all())] APB3, "Advanced Peripheral Bus 3 (APB3) peripherals" => [ Ltdc [fixed clk: "pll3_r_ck"], #[cfg(any(feature = "rm0399"))] Dsi ]; - #[cfg(all())] APB4, "Advanced Peripheral Bus 4 (APB4) peripherals" => [ (Auto) Vref, diff --git a/src/rcc/reset_reason.rs b/src/rcc/reset_reason.rs index aa4c7b3d..3556e1e0 100644 --- a/src/rcc/reset_reason.rs +++ b/src/rcc/reset_reason.rs @@ -65,14 +65,14 @@ pub fn get_reset_reason(rcc: &mut crate::stm32::RCC) -> ResetReason { #[cfg(feature = "rm0455")] // See RM0455 Rev 6 Section 8.4.4 Reset source identification match ( - reset_reason.lpwrrstf().is_reset_occourred(), - reset_reason.wwdgrstf().is_reset_occourred(), - reset_reason.iwdgrstf().is_reset_occourred(), - reset_reason.sftrstf().is_reset_occourred(), - reset_reason.porrstf().is_reset_occourred(), - reset_reason.pinrstf().is_reset_occourred(), - reset_reason.borrstf().is_reset_occourred(), - reset_reason.cdrstf().is_reset_occourred(), + reset_reason.lpwrrstf().is_reset_occurred(), + reset_reason.wwdgrstf().is_reset_occurred(), + reset_reason.iwdgrstf().is_reset_occurred(), + reset_reason.sftrstf().is_reset_occurred(), + reset_reason.porrstf().is_reset_occurred(), + reset_reason.pinrstf().is_reset_occurred(), + reset_reason.borrstf().is_reset_occurred(), + reset_reason.cdrstf().is_reset_occurred(), ) { (false, false, false, false, true, true, true, true) => { ResetReason::PowerOnReset diff --git a/src/xspi/octospi.rs b/src/xspi/octospi.rs index 57ab50c4..b5d2c0e3 100644 --- a/src/xspi/octospi.rs +++ b/src/xspi/octospi.rs @@ -475,7 +475,7 @@ macro_rules! octospi_impl { divisor @ 1..=256 => divisor - 1, _ => panic!("Invalid OCTOSPI frequency requested"), }; - regs.dcr2 + regs.dcr2() .write(|w| unsafe { w.prescaler().bits(divisor as u8) }); // Note that we default to setting SSHIFT (sampling on the falling @@ -564,7 +564,7 @@ macro_rules! octospi_impl { }); // Prescaler - regs.dcr2 + regs.dcr2() .write(|w| unsafe { w.prescaler().bits(divisor - 1) }); // CS boundary. We actually use this feature to ensure the // transcation is re-started when crossing between each half of @@ -580,7 +580,7 @@ macro_rules! octospi_impl { (1000 * hyperbus.refresh_interval.ticks() as u32); (interval_ns + period_ns - 1) / period_ns }; - regs.dcr4 + regs.dcr4() .write(|w| unsafe { w.refresh().bits(refresh_cycles) }); // 8-wide, DDR