From 55f97fd424baec0a5e416f1a8086fef03dc41073 Mon Sep 17 00:00:00 2001
From: Stafford Horne <shorne@gmail.com>
Date: Thu, 4 Oct 2018 18:20:51 +0900
Subject: [PATCH] litex: sim: Get sim working in litex-buildenv

Changes needed to get PLATFORM=sim to work again.

The platforms/sim was basically copied from
litex.boards.platforms.sim but then updated to properly handle
sending the SimConfig details to the toolchain needed during building
and running of the verilog backend.
---
 platforms/sim.py    | 66 ++++++++++++++++++++++++++++++++++++++++++---
 targets/sim/base.py | 12 ++++-----
 targets/sim/net.py  |  2 +-
 3 files changed, 70 insertions(+), 10 deletions(-)

diff --git a/platforms/sim.py b/platforms/sim.py
index 713fb6a7b..8ba7322ad 100644
--- a/platforms/sim.py
+++ b/platforms/sim.py
@@ -1,3 +1,63 @@
-from litex.boards.platforms import sim
-from litex.boards.platforms.sim import *
-__all__ = ['SimPins', 'Platform']
+from litex.build.generic_platform import *
+from litex.build.sim import SimPlatform
+
+from litex.build.sim.config import SimConfig
+
+from targets.sim.net import NetSoC
+
+class SimPins(Pins):
+    def __init__(self, n):
+        Pins.__init__(self, "s "*n)
+
+_io = [
+    ("sys_clk", 0, SimPins(1)),
+    ("sys_rst", 0, SimPins(1)),
+    ("serial", 0,
+        Subsignal("source_valid", SimPins(1)),
+        Subsignal("source_ready", SimPins(1)),
+        Subsignal("source_data", SimPins(8)),
+
+        Subsignal("sink_valid", SimPins(1)),
+        Subsignal("sink_ready", SimPins(1)),
+        Subsignal("sink_data", SimPins(8)),
+    ),
+    ("eth_clocks", 0,
+        Subsignal("none", SimPins(1)),
+    ),
+    ("eth", 0,
+        Subsignal("source_valid", SimPins(1)),
+        Subsignal("source_ready", SimPins(1)),
+        Subsignal("source_data", SimPins(8)),
+
+        Subsignal("sink_valid", SimPins(1)),
+        Subsignal("sink_ready", SimPins(1)),
+        Subsignal("sink_data", SimPins(8)),
+    ),
+    ("vga", 0,
+        Subsignal("de", SimPins(1)),
+        Subsignal("hsync", SimPins(1)),
+        Subsignal("vsync", SimPins(1)),
+        Subsignal("r", SimPins(8)),
+        Subsignal("g", SimPins(8)),
+        Subsignal("b", SimPins(8)),
+    ),
+]
+
+
+class Platform(SimPlatform):
+    default_clk_name = "sys_clk"
+    default_clk_period = 1000  # on modern computers simulate at ~ 1MHz
+
+    def __init__(self):
+        SimPlatform.__init__(self, "SIM", _io)
+
+    def do_finalize(self, fragment):
+        pass
+
+    def build(self, fragment, **kwargs):
+        scfg = SimConfig(default_clk="sys_clk")
+        scfg.add_module("serial2console", "serial")
+        if isinstance(fragment, NetSoC):
+            scfg.add_module('ethernet', "eth", args={"interface": "tap1", "ip": "192.168.1.100"})
+        kwargs['sim_config'] = scfg
+        return SimPlatform.build(self, fragment, **kwargs)
diff --git a/targets/sim/base.py b/targets/sim/base.py
index 7723ea59f..b373d175d 100644
--- a/targets/sim/base.py
+++ b/targets/sim/base.py
@@ -6,6 +6,8 @@
 from litex.soc.integration.builder import *
 from litex.soc.cores import uart
 
+from litex.build.sim.config import SimConfig
+
 from litedram.common import PhySettings
 from litedram.modules import IS42S16160
 from litedram.phy.model import SDRAMPHYModel
@@ -18,7 +20,7 @@
 
 class BaseSoC(SoCSDRAM):
     csr_peripherals = (
-        ,
+        "firmware_ram",
     )
     csr_map_update(SoCSDRAM.csr_map, csr_peripherals)
 
@@ -32,10 +34,9 @@ def __init__(self, platform, **kwargs):
             kwargs['integrated_rom_size']=0x8000
         if 'integrated_sram_size' not in kwargs:
             kwargs['integrated_sram_size']=0x8000
-        if 'firmware_ram_size' not in kwargs:
-            kwargs['firmware_ram_size']=0x10000
-        if 'firmware_filename' not in kwargs:
-            kwargs['firmware_filename'] = "build/sim_{}_{}/software/firmware/firmware.fbi".format(
+
+        firmware_ram_size=0x20000
+        firmware_filename="build/sim_{}_{}/software/firmware/firmware.fbi".format(
                 self.__class__.__name__.lower()[:-3], kwargs.get('cpu_type', 'lm32'))
 
         clk_freq = int((1/(platform.default_clk_period))*1000000000)
@@ -76,5 +77,4 @@ def __init__(self, platform, **kwargs):
         self.add_constant("MEMTEST_ADDR_SIZE", 1024)
         self.add_constant("SIMULATION", 1)
 
-
 SoC = BaseSoC
diff --git a/targets/sim/net.py b/targets/sim/net.py
index 530919364..9ea28fe3b 100644
--- a/targets/sim/net.py
+++ b/targets/sim/net.py
@@ -22,7 +22,7 @@ class NetSoC(BaseSoC):
     csr_map.update(BaseSoC.csr_map)
 
     interrupt_map = {
-        "ethmac": 2,
+        "ethmac": 3,
     }
     interrupt_map.update(BaseSoC.interrupt_map)