analtsis_tele.v

module analtsis_tele(
	sys_clk,
	tele_sign_in1,
	tele_out11,
	tele_out12,
	tele_sign_in2,
	tele_sign_in3,
	tele_out21,
	tele_out22,
	tele_out31,
	tele_out32);

	//---Ports declearation: generated by Robei---
	input sys_clk;
	input [1:0] tele_sign_in1;
	output tele_out11;
	output tele_out12;
	input [1:0] tele_sign_in2;
	input [1:0] tele_sign_in3;
	output tele_out21;
	output tele_out22;
	output tele_out31;
	output tele_out32;

	wire sys_clk;
	wire [1:0] tele_sign_in1;
	reg tele_out11;
	reg tele_out12;
	wire [1:0] tele_sign_in2;
	wire [1:0] tele_sign_in3;
	reg tele_out21;
	reg tele_out22;
	reg tele_out31;
	reg tele_out32;

	//----Code starts here: integrated by Robei-----
	//tele1˝âÎöżé
	always@(posedge sys_clk) begin
	         if(tele_sign_in1 == 0) begin
	                tele_out11 <= 0;
	                tele_out12 <= 0;
	         end     
	         else if(tele_sign_in1 == 1) begin
	                tele_out11 <= 1;
	                tele_out12 <= 0;
	         end
	         else begin
	                tele_out11 <= 0;
	                tele_out12 <= 1;
	         end
	
	end
	
	//tele1˝âÎöżé
	always@(posedge sys_clk) begin
	         if(tele_sign_in2 == 0) begin
	                tele_out21 <= 0;
	                tele_out22 <= 0;
	         end     
	         else if(tele_sign_in2 == 1) begin
	                tele_out21 <= 1;
	                tele_out22 <= 0;
	         end
	         else begin
	                tele_out21 <= 0;
	                tele_out22 <= 1;
	         end
	
	end
	
	//tele1˝âÎöżé
	always@(posedge sys_clk) begin
	         if(tele_sign_in3 == 0) begin
	                tele_out31 <= 0;
	                tele_out32 <= 0;
	         end     
	         else if(tele_sign_in3 == 1) begin
	                tele_out31 <= 1;
	                tele_out32 <= 0;
	         end
	         else begin
	                tele_out31 <= 0;
	                tele_out32 <= 1;
	         end
	
	end
	
	
	
endmodule    //analtsis_tele