4 flash devices in FLEXSPI2 peripheral on our custom board based on RT1062 SOC #49736

ofirshe · 2022-08-31T12:22:26Z

ofirshe
Aug 31, 2022

Hey,

I would like to get your help with zephyr.
On our board, we have 4 flash devices in FLEXSPI2 peripheral - 2 NOR devices (Winbond w25q512nwbiq) with chip select on port A and 2 NAND devices (Micron mt29f8g01adbfd12-it) on port B with chip select.
In my pinctrl.dtsi file I created 2 pinmuxes - one for FLEXSPI2_A and one for FLEXSPI2_B:

pinmux_flexspi2_a: pinmux_flexspi2 {
group0 {
pinmux = <&iomuxc_gpio_emc_23_flexspi2_a_dqs>;
drive-strength = "r0-6";
input-schmitt-enable;
bias-pull-down;
bias-pull-down-value = "100k";
slew-rate = "fast";
nxp,speed = "200-mhz";
input-enable;
};
group1 {
pinmux = <&iomuxc_gpio_emc_22_flexspi2_a_ss1_b>,
<&iomuxc_gpio_emc_24_flexspi2_a_ss0_b>,
<&iomuxc_gpio_emc_25_flexspi2_a_sclk>,
<&iomuxc_gpio_emc_25_flexspi2_a_sclk>,
<&iomuxc_gpio_emc_26_flexspi2_a_data0>,
<&iomuxc_gpio_emc_27_flexspi2_a_data1>,
<&iomuxc_gpio_emc_28_flexspi2_a_data2>,
<&iomuxc_gpio_emc_29_flexspi2_a_data3>;
drive-strength = "r0-6";
slew-rate = "fast";
nxp,speed = "200-mhz";
input-enable;
};
};

pinmux_flexspi2_b: pinmux_flexspi2_b {
group0 {
pinmux = <&iomuxc_gpio_emc_11_flexspi2_b_dqs>;
drive-strength = "r0-6";
input-schmitt-enable;
bias-pull-down;
bias-pull-down-value = "100k";
slew-rate = "fast";
nxp,speed = "200-mhz";
input-enable;
};
group1 {
pinmux = <&iomuxc_gpio_emc_09_flexspi2_b_ss1_b>,
<&iomuxc_gpio_emc_10_flexspi2_b_ss0_b>,
<&iomuxc_gpio_emc_12_flexspi2_b_sclk>,
<&iomuxc_gpio_emc_13_flexspi2_b_data0>,
<&iomuxc_gpio_emc_14_flexspi2_b_data1>,
<&iomuxc_gpio_emc_15_flexspi2_b_data2>,
<&iomuxc_gpio_emc_16_flexspi2_b_data3>;
drive-strength = "r0-6";
slew-rate = "fast";
nxp,speed = "200-mhz";
input-enable;
};
};

flexspi2 declaration in my dts file:
&flexspi2 {
reg = < 0x402a4000 0x4000 >, < 0x70000000 DT_SIZE_M(4) >;
status = "okay";
/* Nor Devices */
flexspi2_a: flexspi2_a {
pinctrl-0 = <&pinmux_flexspi2_a>;
#address-cells = <1>;
#size-cells = <0>;
w25q512nwbiq@0 {
compatible = "winbond,w25q512nwbiq";
size = < 67108864 >;
reg = < 0 >;
spi-max-frequency = < 133000000 >;
status = "okay";
jedec-id = [ef 60 20];
};
w25q512nwbiq@1 {
compatible = "winbond,w25q512nwbiq";
size = < 67108864 >;
reg = < 1 >;
spi-max-frequency = < 133000000 >;
status = "okay";
jedec-id = [ef 60 20];
};
};

/* Nand Devices */
flexspi2_b: flexspi2_b {
pinctrl-0 = <&pinmux_flexspi2_b>;
#address-cells = <1>;
#size-cells = <0>;
mt29f8g01adbfd12-it@0 {
compatible = "micron,mt29f8g01adbfd12-it";
status = "okay";
reg = < 0 >;
size = < 1073741824 >;
};
mt29f8g01adbfd12-it@1 {
compatible = "micron,mt29f8g01adbfd12-it";
status = "okay";
reg = < 1 >;
size = < 1073741824 >;
};
};
};

Can you please tell me how can I declared it correctly in the dts file because I have many compilation errors and if you can also send me a code sample which does this chip select and write to the chosen device I will be very grateful.

Answered by DerekSnell

Sep 8, 2022

Hi @ofirshe ,
The FlexSPI hardware will assert the chip select to the 3rd flash device based on the address requested, and the memory map you created with the flash sizes in the devicetree.

It seems to me that you do not have hardware available to confirm this yet. But you could test this with an EVK board. The EVK does not have multiple memory devices connected to the other chip selects. But you can still test the code to access the other chip select, and monitor the chip select pin to confirm the FlexSPI drives it. Best regards

View full answer

DerekSnell · 2022-09-01T22:26:17Z

DerekSnell
Sep 1, 2022
Collaborator

Hi @ofirshe ,

I was able to tweak your devicetree and get it to build. I added your additions for FlexSPI2 to the mimxrt1060_evk DTS, then made my changes, and I could build it. Below are the FlexSPI2 configuration I used. Unfortunately without hardware to match, I can't test that any of this works. So please let me know what you find. I also have some additional notes for you:

Be aware that the memory map available for FlexSPI2 is limited to 240MB. I point this out because based on the sizes of your flash devices, I see 2 devices with 128MB each plus 2 devices of 8MB each. But if you are wanting to use the AHB memory-mapped access, the address range on the RT1060 is 0x7000_0000 to 0x7EFF_FFFF, or 240MB. Reading the FlexSPI chapter, I see the FLSHSZ parameter enables up to 512MB for the combined flashes. Maybe that means you could access all your flash memory using FlexSPI IP commands. But I want to make sure you are aware of the memory-map limit.

You need the reg property of each flash to range from 0-3. Meaning the two devices on portB should use 2 and 3 for the reg property. The reg property determines the index of the FLSHCR registers in the FlexSPI, and the MCUXpresso SDK driver uses this flexspi_port_t enumeration for the 4 options.

And note that your DTS used a binding for micron,mt29f8g01adbfd12-it, which I did not find in the Zephyr tree. So I changed this to nxp,imx-flexspi-nor just to be able to build the DTS.

Also, you asked for a code sample which does this chip select and write to the chosen device. Once the FlexSPI is configured, the chosen device and chip select are just determined by the address requested. The FlexSPI will use the FLSHSZ bits in the FLSHxxCR0 registers (which are configured from your DTS) to translate the address to the flash device and chip select. For more details, see the FlexSPI chapter of the RT1060 Reference Manual, and search for FLSHSZ. If you have the FlexSPI configured for AHB memory-map, you just read from an address offset with base 0x7000_0000. Or you can use the Zephyr flash driver APIs with the desired address. For examples, you can refer to the flash_shell sample, or the flash test.

Best regards

FlexSPI2 in DTS

&flexspi2 {
	reg = < 0x402a4000 0x4000 >, < 0x70000000 DT_SIZE_M(240) >;
	status = "okay";
	pinctrl-0 = <&pinmux_flexspi2>;
	pinctrl-names = "default";

	/* Port A: Nor Devices */
	w25q512nwbiq@0 {
		compatible = "nxp,imx-flexspi-nor";
		size = < 67108864 >;
		reg = < 0 >;
		spi-max-frequency = < 133000000 >;
		status = "okay";
		jedec-id = [ef 60 20];
	};
	w25q512nwbiq@1 {
		compatible = "nxp,imx-flexspi-nor";
		size = < 67108864 >;
		reg = < 1 >;
		spi-max-frequency = < 133000000 >;
		status = "okay";
		jedec-id = [ef 60 20];
	};

	/* Port B: Nand Devices */
	mt29f8g01adbfd12-it@2 {
		compatible = "nxp,imx-flexspi-nor";
		status = "okay";
		reg = < 2 >;
		/* too large? */
		size = < 1073741824 >;
		spi-max-frequency = <133000000>;
	};
	mt29f8g01adbfd12-it@3 {
		compatible = "nxp,imx-flexspi-nor";
		status = "okay";
		reg = < 3 >;
		size = < 1073741824 >;
		spi-max-frequency = <133000000>;
	};
};

pinctrl for FlexSPI2:

pinmux_flexspi2: pinmux_flexspi2 {
	group0 {
		pinmux = <&iomuxc_gpio_emc_23_flexspi2_a_dqs>,
			<&iomuxc_gpio_emc_11_flexspi2_b_dqs>;
		drive-strength = "r0-6";
		input-schmitt-enable;
		bias-pull-down;
		bias-pull-down-value = "100k";
		slew-rate = "fast";
		nxp,speed = "200-mhz";
		input-enable;
	};
	group1 {
		pinmux = <&iomuxc_gpio_emc_22_flexspi2_a_ss1_b>,
			<&iomuxc_gpio_emc_24_flexspi2_a_ss0_b>,
			<&iomuxc_gpio_emc_25_flexspi2_a_sclk>,
			<&iomuxc_gpio_emc_26_flexspi2_a_data0>,
			<&iomuxc_gpio_emc_27_flexspi2_a_data1>,
			<&iomuxc_gpio_emc_28_flexspi2_a_data2>,
			<&iomuxc_gpio_emc_29_flexspi2_a_data3>,
			<&iomuxc_gpio_emc_09_flexspi2_b_ss1_b>,
			<&iomuxc_gpio_emc_10_flexspi2_b_ss0_b>,
			<&iomuxc_gpio_emc_12_flexspi2_b_sclk>,
			<&iomuxc_gpio_emc_13_flexspi2_b_data0>,
			<&iomuxc_gpio_emc_14_flexspi2_b_data1>,
			<&iomuxc_gpio_emc_15_flexspi2_b_data2>,
			<&iomuxc_gpio_emc_16_flexspi2_b_data3>;
		drive-strength = "r0-6";
		slew-rate = "fast";
		nxp,speed = "200-mhz";
		input-enable;
	};
};

1 reply

ofirshe Sep 5, 2022
Author

Hey @DerekSnell, regarding to the limitation of the memory space to 240MB, I divided equally the space by four so each device will own 60MB (62914560 bytes) and that's my final dts hierarchy:

&flexspi2 {
reg = < 0x402a4000 0x4000 >, < 0x70000000 DT_SIZE_M(240) >;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinmux_flexspi2>;

/* Port A: Nor Devices */
w25q512nwbiq@0 {
	compatible = "nxp,imx-flexspi-nor";
	size = < 62914560 >;
	reg = < 0 >;
	spi-max-frequency = < 133000000 >;
	status = "okay";
	jedec-id = [ef 60 20];
};
w25q512nwbiq@1 {
	compatible = "nxp,imx-flexspi-nor";
	size = < 62914560 >;
	reg = < 1 >;
	spi-max-frequency = < 133000000 >;
	status = "okay";
	jedec-id = [ef 60 20];
};

/* Port B: Nand Devices */
mt29f8g01adbfd12-it@2 {
	compatible = "nxp,imx-flexspi-nor";
	status = "okay";
	reg = < 2 >;
	size = < 62914560 >;
	spi-max-frequency = <133000000>;
};
mt29f8g01adbfd12-it@3 {
	compatible = "nxp,imx-flexspi-nor";
	status = "okay";
	reg = < 3 >;
	size = < 62914560 >;
	spi-max-frequency = <133000000>;
};

};

I have many questions regarding this:

In case I would like to access the second nor flash, can I use it's path or it has to be different? for example:

#define TEST_SPI_FLASH_DEV DT_PATH(soc, spi_402a4000, w25q512nwbiq_1)
const struct device *flash_dev = DEVICE_DT_GET(TEST_SPI_FLASH_DEV);
flash_write(flash_dev, TEST_SPI_FLASH_REGION_OFFSET, buffer_to_write, buffer_len);
flash_read(flash_dev, TEST_SPI_FLASH_REGION_OFFSET, read_buffer, buffer_len);
.
.
.
2. For the NAND devices (mt29f8g01adbfd12-it@2 and mt29f8g01adbfd12-it@3), how should I configured
micron,mt29f8g01adbfd12-it.yaml file ? Will I be able to use the spi_flash driver to communicate with those
NAND flash devices ?

Best regards,
Ofir.

DerekSnell · 2022-09-07T21:27:28Z

DerekSnell
Sep 7, 2022
Collaborator

Hi @ofirshe ,
You can use DT_PATH to access a node from the devicetree. Another option you may prefer is to use chosen nodes or aliases for these flash devices in your board's devicetree. Zephyr has this doc page on Devicetree access from C/C++ for the options.

For your NAND .YAML file, you can copy nxp,imx-flexspi-nor.yaml and rename for your flash. The key include you need is to nxp,imx-flexspi-device.yaml, as that file has all the bindings for the FlexSPI driver.

The more challenging task is to create the flash driver files. You can refer to existing drivers in the tree as examples, like flash_mcux_flexspi_nor.c or flash_mcux_flexspi_mx25um51345g.c. Then you can tweak for the FlexSPI configuration and initialization required for your flash device. I don't know if this NAND device is similar to a driver that NXP already has for the FlexSPI. But if you need help from NXP to configure the FlexSPI for a specific memory, you can request support on NXP's Community forum at https://community.nxp.com/t5/i-MX-RT/bd-p/imxrt.

Best regards

1 reply

ofirshe Sep 8, 2022
Author

Hey @DerekSnell,

I would like to make sure the if I access for example the third flash device, will the chip select be occurred automatically with my dts and pintctrl code ?

DerekSnell · 2022-09-08T13:11:51Z

DerekSnell
Sep 8, 2022
Collaborator

Hi @ofirshe ,
The FlexSPI hardware will assert the chip select to the 3rd flash device based on the address requested, and the memory map you created with the flash sizes in the devicetree.

It seems to me that you do not have hardware available to confirm this yet. But you could test this with an EVK board. The EVK does not have multiple memory devices connected to the other chip selects. But you can still test the code to access the other chip select, and monitor the chip select pin to confirm the FlexSPI drives it. Best regards

0 replies

DerekSnell · 2024-05-23T14:16:33Z

DerekSnell
May 23, 2024
Collaborator

Following up on this topic to make others aware, this pull request #72528 was merged, which adds multiple memory support on a single FlexSPI. Best regards

0 replies

ofirshe · 2025-01-22T20:33:02Z

ofirshe
Jan 22, 2025
Author

Hi @DerekSnell,

In the final plan, we will have three w25q512nw flash devices in flexspi2: two connected to Port A and one to Port B. All of these devices will be used for storage, while the NOR flash connected to flexspi1 will store the RT1061 image binary. Below is the final configuration for the flexspi2 peripheral:

&flexspi2 {
    reg = <0x402a4000 0x4000>, <0x70000000 DT_SIZE_M(192)>;
    status = "okay";
    pinctrl-0 = <&pinmux_flexspi2>;
    pinctrl-names = "default";

    /* Port A: 2 NOR Devices */
    w25q512nw1: w25q512nw@0 {
        compatible = "nxp,imx-flexspi-nor";
        size = <DT_SIZE_M(64 * 8)>;
        reg = <0>;
        spi-max-frequency = <DT_FREQ_M(133)>;
        status = "okay";
        jedec-id = [ef 60 20];
        erase-block-size = <4096>;
        write-block-size = <1>;

        partitions {
            compatible = "fixed-partitions";
            #address-cells = <1>;
            #size-cells = <1>;

            w25q512nw1_partition: partition@0 {
                label = "NOR1";
                reg = <0x00000000 DT_SIZE_M(64)>;
            };
        };
    };

    w25q512nw2: w25q512nw@1 {
        compatible = "nxp,imx-flexspi-nor";
        size = <DT_SIZE_M(64 * 8)>;
        reg = <1>;
        spi-max-frequency = <DT_FREQ_M(133)>;
        status = "okay";
        jedec-id = [ef 60 20];
        erase-block-size = <4096>;
        write-block-size = <1>;

        partitions {
            compatible = "fixed-partitions";
            #address-cells = <1>;
            #size-cells = <1>;

            w25q512nw2_partition: partition@0 {
                label = "NOR2";
                reg = <0x00000000 DT_SIZE_M(64)>;
            };
        };
    };

    /* Port B: 1 NOR Device */
    w25q512nw3: w25q512nw@2 {
        compatible = "nxp,imx-flexspi-nor";
        size = <DT_SIZE_M(64 * 8)>;
        reg = <2>;
        spi-max-frequency = <DT_FREQ_M(133)>;
        status = "okay";
        jedec-id = [ef 60 20];
        erase-block-size = <4096>;
        write-block-size = <1>;

        partitions {
            compatible = "fixed-partitions";
            #address-cells = <1>;
            #size-cells = <1>;

            w25q512nw3_partition: partition@0 {
                label = "NOR3";
                reg = <0x00000000 DT_SIZE_M(64)>;
            };
        };
    };
};

My question is:
Do I need to create a additional flexspi_nor_config.c file for flexspi2, similar to what I have for flexspi1, or is this configuration sufficient for regular operation?

Thanks!

2 replies

DerekSnell Jan 24, 2025
Collaborator

Hi @ofirshe ,
The flexspi_nor_config structure like in evkbmimxrt1170_flexspi_nor_config.c is for the ROM bootloader. The bootloader uses this Flash Configuration Block (FCB) to configure the FlexSPI peripheral to interface to the external boot flash. You only need 1 FCB in the boot memory. After the bootloader configures the FlexSPI, it will read from the boot flash, and your application can XIP from that boot flash. Then the app can configure other FlexSPIs and other external memories to access them.

Best regards

ofirshe Jan 24, 2025
Author

@DerekSnell thanks for that clarification.

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

4 flash devices in FLEXSPI2 peripheral on our custom board based on RT1062 SOC #49736

{{title}}

Replies: 5 comments 4 replies

{{title}}

{{title}}

{{title}}

{{title}}

{{editor}}'s edit

{{editor}}'s edit

{{title}}

{{title}}

{{title}}

{{title}}

{{title}}

Select a reply

4 flash devices in FLEXSPI2 peripheral on our custom board based on RT1062 SOC #49736

ofirshe Aug 31, 2022

Replies: 5 comments · 4 replies

DerekSnell Sep 1, 2022 Collaborator

ofirshe Sep 5, 2022 Author

DerekSnell Sep 7, 2022 Collaborator

ofirshe Sep 8, 2022 Author

DerekSnell Sep 8, 2022 Collaborator

DerekSnell May 23, 2024 Collaborator

ofirshe Jan 22, 2025 Author

DerekSnell Jan 24, 2025 Collaborator

ofirshe Jan 24, 2025 Author

ofirshe
Aug 31, 2022

Replies: 5 comments 4 replies

DerekSnell
Sep 1, 2022
Collaborator

ofirshe Sep 5, 2022
Author

DerekSnell
Sep 7, 2022
Collaborator

ofirshe Sep 8, 2022
Author

DerekSnell
Sep 8, 2022
Collaborator

DerekSnell
May 23, 2024
Collaborator

ofirshe
Jan 22, 2025
Author

DerekSnell Jan 24, 2025
Collaborator

ofirshe Jan 24, 2025
Author