Enable some test designs

.github/workflows/main.yml

@@ -75,18 +75,18 @@ jobs:
       matrix:
         include:
           - { count: "32", width: "8", variant: "DEFAULT" }
-          # - { count: "32", width: "8", variant: "1RW1R" }
+          - { count: "32", width: "8", variant: "1RW1R" }
           - { count: "32", width: "16", variant: "DEFAULT" }
-          # - { count: "32", width: "16", variant: "1RW1R" }
+          - { count: "32", width: "16", variant: "1RW1R" }
           - { count: "32", width: "32", variant: "DEFAULT" }
           # - { count: "32", width: "32", variant: "1RW1R" } # Timeout
           - { count: "32", width: "32", variant: "2R1W" }
           - { count: "256", width: "8", variant: "DEFAULT" }
-          # - { count: "256", width: "8", variant: "1RW1R" }
+          - { count: "256", width: "8", variant: "1RW1R" }
           - { count: "256", width: "16", variant: "DEFAULT" }
           # - { count: "256", width: "16", variant: "1RW1R" } # Timeout
           - { count: "256", width: "32", variant: "DEFAULT" }
-          #- { count: "256", width: "32", variant: "1RW1R" } # Timeout
+          # - { count: "256", width: "32", variant: "1RW1R" } # Timeout
     steps:
       - name: Checkout code
         uses: actions/checkout@v3

.gitignore

@@ -28,4 +28,5 @@ support/
 *.log
 *.cvcrc
 *.xz
-venv/
+venv/
+products_path

dffram.py

@@ -194,7 +194,7 @@ def cl():
 def synthesis(
     design,
     building_blocks,
-    block_deinitions,
+    block_definitions,
     sta_info,
     widths_supported,
     word_width_bytes,
@@ -215,7 +215,7 @@ def synthesis(
             yosys -import
             set SCL {pdk_liberty_dir}/{sta_info["libs"]["typical"]}
             read_liberty -lib -ignore_miss_dir -setattr blackbox $SCL
-            read_verilog {block_deinitions}
+            read_verilog {block_definitions}
             read_verilog {building_blocks}
             {chparam}
             hierarchy -check -top {design}