Fix visibiliy of clock on remove or connecting wires

FPGAwars · Jan 10, 2025 · 187e0b8 · 187e0b8
1 parent e78762a
commit 187e0b8
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Showing 2 changed files with 3 additions and 3 deletions.
diff --git a/app/scripts/graphics/joint.shapes.js b/app/scripts/graphics/joint.shapes.js
@@ -2246,7 +2246,7 @@ joint.shapes.ice.CodeView = joint.shapes.ice.ModelView.extend({
         });
       }
     }
-
+    
     // Render rules
     if (data && data.ports && data.ports.in) {
       tokId = "port-default-" + modelId + "-";
@@ -2894,7 +2894,6 @@ joint.shapes.ice.WireView = joint.dia.LinkView.extend({
       function (label, idx) {
         if(typeof idx === 'undefined' || idx === null || idx===false){
 
-            console.log('IDX NULL');
         }
         var labelNode = labelNodeInstance.clone().node;
         V(labelNode).attr("label-idx", idx);

diff --git a/app/scripts/services/graph.js b/app/scripts/services/graph.js
@@ -904,7 +904,7 @@ function isElementInViewport(elementBBox, viewport) {
                     break;
                   }
                 }
-                paper.findViewByModel(block.id).updateBox();
+                paper.findViewByModel(block.id).updateBox(true);
               }
             }
           }
@@ -1387,6 +1387,7 @@ function isElementInViewport(elementBBox, viewport) {
       };
 
       this.removeSelected = function () {
+        console.log('RemoveSelected');
         if (hasSelection()) {
           graph.removeCells(selection.models);
           selectionView.cancelSelection();