Handle undefined inouts in automatic code block generation from Verilog

FPGAwars · Jan 16, 2025 · 6176281 · 6176281
1 parent ade48cc
commit 6176281
Showing 1 changed file with 4 additions and 2 deletions.
diff --git a/app/scripts/services/forms.js b/app/scripts/services/forms.js
@@ -1749,12 +1749,14 @@ angular.module('icestudio')
                     const result = utils.parseVerilog(content);
                     portsIn = result.inputs;
                     portsOut = result.outputs;
-                    portsInOutLeft = result.inouts;
                     paramsIn = result.parameters;
                     field0.write(result.inputs);
                     field1.write(result.outputs);
                     field2.write(result.parameters);
-                    field3.write(result.inouts);
+                    if (portsInOutLeft !== undefined) {
+                      portsInOutLeft = result.inouts;
+                      field3.write(result.inouts);
+                    }
                     self.code = result.moduleBody;
                   }
                 });