RUN_BUILD --> Verilog importer improvements

FPGAwars · Jan 18, 2025 · 6d0fb9f · 6d0fb9f
1 parent 1a63cd7
commit 6d0fb9f
Showing 1 changed file with 3 additions and 1 deletion.
diff --git a/build.info b/build.info
@@ -1,7 +1,9 @@
-2025-01-16 01:14 (GMT+1)
+2025-01-18 22:38 (GMT+1)
 ========================
 Type: WIP
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 App Changes: 
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   - Header comments and multiple module per file support for verilog importer by @cavearr
   - Add inouts and parameters automatic loading verilog code and improve code by @cavearr
   - Automatic code block from verilog file by @lmcapacho