RUN_BUILD --> refactor node modules and enhance import verilog UI

FPGAwars · Jan 20, 2025 · 916f562 · 916f562
1 parent 63386ed
commit 916f562
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/build.info b/build.info
@@ -1,4 +1,4 @@
-2025-01-18 22:38 (GMT+1)
+2025-01-21 00:06 (GMT+1)
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 Type: WIP