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Handle undefined inouts in automatic code block generation from Verilog #802

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cavearr merged 1 commit into FPGAwars:develop from lmcapacho:develop

Jan 17, 2025

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lmcapacho commented Jan 16, 2025

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          Handle undefined inouts in automatic code block generation from Verilog

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cavearr commented Jan 17, 2025

Thanks! i don't view your PR until reply in the mail list, thanks again!

cavearr merged commit d9e3302 into FPGAwars:develop

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