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reading and sending values working
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some mapping seems to be wrong
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@LeoDJ
LeoDJ committed Jun 14, 2021
1 parent 7574c90 commit eedcb01
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Showing 6 changed files with 424 additions and 101 deletions.
3 changes: 3 additions & 0 deletions README.md
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@@ -0,0 +1,3 @@
# Janitza Power Meter

Code for reading the Janitza UMG 96S via Modbus and pushing the values into a InfluxDB.
Binary file added janitza-bhb-umg96s-24v-en.pdf
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4 changes: 2 additions & 2 deletions software/platformio.ini
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Expand Up @@ -17,5 +17,5 @@ lib_deps =
[email protected]
[email protected]
build_flags =
-D ENABLE_HWSERIAL2
; -Wl,-u,vfprintf -lprintf_flt -lm ; enable float printf
-D ENABLE_HWSERIAL3
-Wl,-u_printf_float ; enable float printf
4 changes: 3 additions & 1 deletion software/src/globals.h
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Expand Up @@ -8,10 +8,12 @@
#define UPDATE_INTERVAL 5000 // ms

#define CT_RATIO (40/5) // calculated current transformer ratio (e.g. 40:5 -> 8)
#define MODUBS_SERIAL Serial2
#define MODUBS_SERIAL Serial3
#define MODBUS_BAUD 38400
#define MODBUS_ADDR 1



#define SPI2_MOSI PB15
#define SPI2_MISO PB14
#define SPI2_SCK PB13
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340 changes: 309 additions & 31 deletions software/src/janitza.h
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Expand Up @@ -5,6 +5,7 @@ typedef struct {
uint8_t multiplier;
uint8_t applyCtRatio : 1;
uint8_t type : 2;
uint8_t phaseTag : 3;
const char *influxStr;
} registerDefinition_t;

Expand All @@ -14,40 +15,317 @@ enum registerDataTypes {
LONG,
};

enum phaseTag {
P_ALL,
P_L1,
P_L2,
P_L3,
P_L1L2,
P_L2L3,
P_L3L1,
P_TAG_NUM // length of enum
};

const char *phaseTagStr[] = {
"All",
"L1",
"L2",
"L3",
"L1-L2",
"L2-L3",
"L3-L1"
};























































#define EMPTY {0, 1, false, INT, P_ALL, NULL}
#define LONG_SPACER EMPTY


// TODO: fix addresses (currently not needed)
registerDefinition_t registerDefinition[] = {
//addr multipl CTratio type name
{ 200, 10, false, INT, "ULN1" },
{ 201, 10, false, INT, "ULN2" },
{ 202, 10, false, INT, "ULN3" },
{ 203, 10, false, INT, "ULL12" }, // L1-L2
{ 204, 10, false, INT, "ULL23" },
{ 205, 10, false, INT, "ULL31" },
{ 206, 1, true, INT, "IL1" },
{ 207, 1, true, INT, "IL2" },
{ 208, 1, true, INT, "IL3" },
{ 209, 10, true, INT, "PL1" }, // real power
{ 210, 10, true, INT, "PL2" },
{ 211, 10, true, INT, "PL3" },
{ 212, 10, true, INT, "QL1" }, // reactive power
{ 213, 10, true, INT, "QL2" },
{ 214, 10, true, INT, "QL3" },
{ 215, 10, true, INT, "SL1" }, // apparent power
{ 216, 10, true, INT, "SL2" },
{ 217, 10, true, INT, "SL3" },
{ 218, 100, false, INT, "CosPhiL1" },
{ 219, 100, false, INT, "CosPhiL2" },
{ 220, 100, false, INT, "CosPhiL3" },
{ 221, 10, false, INT, "ULN1H1" },
{ 221, 10, false, INT, "ULN1H3" },
{ 221, 10, false, INT, "ULN1H5" },
{ 221, 10, false, INT, "ULN1H7" },
{ 221, 10, false, INT, "ULN1H9" },
{ 221, 10, false, INT, "ULN1H11" },
{ 221, 10, false, INT, "ULN1H13" },
{ 221, 10, false, INT, "ULN1H15" },
// ...
//addr multipl CTratio type phase name
{ 200, 10, false, INT, P_L1, "U_LN" },
{ 201, 10, false, INT, P_L2, "U_LN" },
{ 202, 10, false, INT, P_L3, "U_LN" },
{ 203, 10, false, INT, P_L1L2, "U_LL" }, // L1-L2
{ 204, 10, false, INT, P_L2L3, "U_LL" },
{ 205, 10, false, INT, P_L3L1, "U_LL" },
{ 206, 1, true, INT, P_L1, "I" },
{ 207, 1, true, INT, P_L2, "I" },
{ 208, 1, true, INT, P_L3, "I" },
{ 209, 10, true, INT, P_L1, "P" }, // real power
{ 210, 10, true, INT, P_L2, "P" },
{ 211, 10, true, INT, P_L3, "P" },
{ 212, 10, true, INT, P_L1, "Q" }, // reactive power
{ 213, 10, true, INT, P_L2, "Q" },
{ 214, 10, true, INT, P_L3, "Q" },
{ 215, 10, true, INT, P_L1, "S" }, // apparent power
{ 216, 10, true, INT, P_L2, "S" },
{ 217, 10, true, INT, P_L3, "S" },
{ 218, 100, false, INT, P_L1, "CosPhi" },
{ 219, 100, false, INT, P_L2, "CosPhi" },
{ 220, 100, false, INT, P_L3, "CosPhi" },
{ 1, 10, false, INT, P_L1, "U_LN_Harm1" },
{ 1, 10, false, INT, P_L1, "U_LN_Harm3" },
{ 1, 10, false, INT, P_L1, "U_LN_Harm5" },
{ 1, 10, false, INT, P_L1, "U_LN_Harm7" },
{ 1, 10, false, INT, P_L1, "U_LN_Harm9" },
{ 1, 10, false, INT, P_L1, "U_LN_Harm11" },
{ 1, 10, false, INT, P_L1, "U_LN_Harm13" },
{ 1, 10, false, INT, P_L1, "U_LN_Harm15" },
{ 1, 10, false, INT, P_L2, "U_LN_Harm1" },
{ 1, 10, false, INT, P_L2, "U_LN_Harm3" },
{ 1, 10, false, INT, P_L2, "U_LN_Harm5" },
{ 1, 10, false, INT, P_L2, "U_LN_Harm7" },
{ 1, 10, false, INT, P_L2, "U_LN_Harm9" },
{ 1, 10, false, INT, P_L2, "U_LN_Harm11" },
{ 1, 10, false, INT, P_L2, "U_LN_Harm13" },
{ 1, 10, false, INT, P_L2, "U_LN_Harm15" },
{ 1, 10, false, INT, P_L3, "U_LN_Harm1" },
{ 1, 10, false, INT, P_L3, "U_LN_Harm3" },
{ 1, 10, false, INT, P_L3, "U_LN_Harm5" },
{ 1, 10, false, INT, P_L3, "U_LN_Harm7" },
{ 1, 10, false, INT, P_L3, "U_LN_Harm9" },
{ 1, 10, false, INT, P_L3, "U_LN_Harm11" },
{ 1, 10, false, INT, P_L3, "U_LN_Harm13" },
{ 1, 10, false, INT, P_L3, "U_LN_Harm15" },
{ 1, 1, false, INT, P_L1, "I_Harm1" },
{ 1, 1, false, INT, P_L1, "I_Harm3" },
{ 1, 1, false, INT, P_L1, "I_Harm5" },
{ 1, 1, false, INT, P_L1, "I_Harm7" },
{ 1, 1, false, INT, P_L1, "I_Harm9" },
{ 1, 1, false, INT, P_L1, "I_Harm11" },
{ 1, 1, false, INT, P_L1, "I_Harm13" },
{ 1, 1, false, INT, P_L1, "I_Harm15" },
{ 1, 1, false, INT, P_L2, "I_Harm1" },
{ 1, 1, false, INT, P_L2, "I_Harm3" },
{ 1, 1, false, INT, P_L2, "I_Harm5" },
{ 1, 1, false, INT, P_L2, "I_Harm7" },
{ 1, 1, false, INT, P_L2, "I_Harm9" },
{ 1, 1, false, INT, P_L2, "I_Harm11" },
{ 1, 1, false, INT, P_L2, "I_Harm13" },
{ 1, 1, false, INT, P_L2, "I_Harm15" },
{ 1, 1, false, INT, P_L3, "I_Harm1" },
{ 1, 1, false, INT, P_L3, "I_Harm3" },
{ 1, 1, false, INT, P_L3, "I_Harm5" },
{ 1, 1, false, INT, P_L3, "I_Harm7" },
{ 1, 1, false, INT, P_L3, "I_Harm9" },
{ 1, 1, false, INT, P_L3, "I_Harm11" },
{ 1, 1, false, INT, P_L3, "I_Harm13" },
{ 1, 1, false, INT, P_L3, "I_Harm15" },
{ 1, 10, false, INT, P_L1, "THD_U" },
{ 1, 10, false, INT, P_L2, "THD_U" },
{ 1, 10, false, INT, P_L3, "THD_U" },
{ 1, 10, false, INT, P_L1, "THD_I" },
{ 1, 10, false, INT, P_L2, "THD_I" },
{ 1, 10, false, INT, P_L3, "THD_I" },
{ 1, 100, false, INT, P_L1, "F" },
{ 1, 100, false, INT, P_ALL, "CosPhi" },
{ 1, 1, false, INT, P_ALL, "Rotation" },
{ 1, 1, false, INT, P_ALL, "I_N" },
{ 1, 1, false, INT, P_ALL, "P" },
{ 1, 1, false, INT, P_ALL, "Q" },
{ 1, 1, false, INT, P_ALL, "S" },
EMPTY, // { 0, 1, true, INT, P_L1, "I_Mean" },
EMPTY, // { 0, 1, true, INT, P_L2, "I_Mean" },
EMPTY, // { 0, 1, true, INT, P_L3, "I_Mean" },
EMPTY, // { 0, 10, true, INT, P_L1, "P_Mean" }, // real power
EMPTY, // { 0, 10, true, INT, P_L2, "P_Mean" },
EMPTY, // { 0, 10, true, INT, P_L3, "P_Mean" },
EMPTY, // { 0, 10, true, INT, P_L1, "Q_Mean" }, // reactive power
EMPTY, // { 0, 10, true, INT, P_L2, "Q_Mean" },
EMPTY, // { 0, 10, true, INT, P_L3, "Q_Mean" },
EMPTY, // { 0, 10, true, INT, P_L1, "S_Mean" }, // apparent power
EMPTY, // { 0, 10, true, INT, P_L2, "S_Mean" },
EMPTY, // { 0, 10, true, INT, P_L3, "S_Mean" },
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
{ 1, 60, false, LONG, P_ALL, "OperatingTime" },
LONG_SPACER,
EMPTY,
LONG_SPACER,
EMPTY,
LONG_SPACER,
EMPTY,
LONG_SPACER,
EMPTY,
LONG_SPACER,
EMPTY,
LONG_SPACER,
EMPTY,
LONG_SPACER,
{ 1, 1, false, INT, P_ALL, "Temperature" },
{ 1, 100, false, INT, P_ALL, "U_Operating" },
EMPTY,
LONG_SPACER,
EMPTY,
EMPTY,
EMPTY,
EMPTY,
{ 1, 1, false, LONG, P_ALL, "Wp" }, // Wh
LONG_SPACER,
{ 1, 1, false, LONG, P_ALL, "Wq" },
LONG_SPACER,
EMPTY,
EMPTY,
{ 1, 1, false, LONG, P_ALL, "Wp_Import" }, // Wh
LONG_SPACER,
{ 1, 1, false, LONG, P_ALL, "Wp_Supply" }, // Wh
LONG_SPACER,
};
#define REG_DEF_NUM (sizeof(registerDefinition) / sizeof(registerDefinition[0]))
#define REG_DEF_START_ADDR 200


#define REG_SERIAL 911
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