More ram, stock video and jpeg

arch/arm/configs/venturi_eur_defconfig

@@ -395,7 +395,7 @@ CONFIG_PAGE_OFFSET=0xC0000000
 # CONFIG_PREEMPT_NONE is not set
 # CONFIG_PREEMPT_VOLUNTARY is not set
 CONFIG_PREEMPT=y
-CONFIG_HZ=256
+CONFIG_HZ=300
 # CONFIG_THUMB2_KERNEL is not set
 CONFIG_AEABI=y
 CONFIG_OABI_COMPAT=y

arch/arm/mach-s5pv210/cpu-freq.c

@@ -54,8 +54,8 @@ extern int exp_UV_mV[6];
 
 /* frequency */
 static struct cpufreq_frequency_table freq_table[] = {
-	{L0, 1200*1000},
-	{L1, 1000*1000},
+	{L0, 1320*1000},
+	{L1, 1096*1000},
 	{L2, 800*1000},
 	{L3, 400*1000},
 	{L4, 200*1000},
@@ -75,20 +75,20 @@ static unsigned int g_dvfslockval[DVFS_LOCK_TOKEN_NUM];
 //static DEFINE_MUTEX(dvfs_high_lock);
 #endif
 
-const unsigned long arm_volt_max = 1350000;
-const unsigned long int_volt_max = 1250000;
+const unsigned long arm_volt_max = 1400000;
+const unsigned long int_volt_max = 1200000;
 
 static struct s5pv210_dvs_conf dvs_conf[] = {
 	[L0] = {
-		.arm_volt   = 1300000,
-		.int_volt   = 1125000,
+		.arm_volt   = 1310000,
+		.int_volt   = 1130000,
 	},
 	[L1] = {
-		.arm_volt   = 1275000,
-		.int_volt   = 1100000,
+		.arm_volt   = 1285000,
+		.int_volt   = 1120000,
 	},
 	[L2] = {
-		.arm_volt   = 1200000,
+		.arm_volt   = 1100000,
 		.int_volt   = 1100000,
 	},
 	[L3] = {
@@ -110,9 +110,9 @@ static u32 clkdiv_val[6][11] = {
 	 * HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS, ONEDRAM,
 	 * MFC, G3D }
 	 */
-	/* L0 : [1200/200/200/100][166/83][133/66][200/200] */
+	/* L0 : [1320/200/200/100][166/83][133/66][220/220] */
 	{0, 5, 5, 1, 3, 1, 4, 1, 3, 0, 0},
-	/* L1 : [1000/200/200/100][166/83][133/66][200/200] */
+	/* L1 : [1096/200/200/100][166/83][133/66][219,2/219,2] */
 	{0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0},
 	/* L2 : [800/200/200/100][166/83][133/66][200/200] */
 	{0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0},
@@ -125,9 +125,9 @@ static u32 clkdiv_val[6][11] = {
 };
 
 static struct s3c_freq clk_info[] = {
-	[L0] = {	/* L0: 1.2GHz */
-		.fclk       = 1200000,
-		.armclk     = 1200000,
+	[L0] = {	/* L0: 1.32GHz */
+		.fclk       = 1320000,
+		.armclk     = 1320000,
 		.hclk_tns   = 0,
 		.hclk       = 133000,
 		.pclk       = 66000,
@@ -136,9 +136,9 @@ static struct s3c_freq clk_info[] = {
 		.hclk_dsys  = 166750,
 		.pclk_dsys  = 83375,
 	},
-	[L1] = {	/* L0: 1GHz */
-		.fclk       = 1000000,
-		.armclk     = 1000000,
+	[L1] = {	/* L0: 1,096GHz */
+		.fclk       = 1096000,
+		.armclk     = 1096000,
 		.hclk_tns   = 0,
 		.hclk       = 133000,
 		.pclk       = 66000,
@@ -296,19 +296,19 @@ static void s5pv210_cpufreq_clksrcs_MPLL2APLL(unsigned int index,
 	 * 2-1. Set PMS values
 	 */
 	//	if (index == L0)
-		/* APLL FOUT becomes 1000 Mhz */
-	//		__raw_writel(PLL45XX_APLL_VAL_1000, S5P_APLL_CON);
+		/* APLL FOUT becomes 1096 Mhz */
+	//		__raw_writel(PLL45XX_APLL_VAL_1096, S5P_APLL_CON);
 	//else
 		/* APLL FOUT becomes 800 Mhz */
 	//	__raw_writel(PLL45XX_APLL_VAL_800, S5P_APLL_CON);
         switch ( index ) {
                 case L0:
-                        /* APLL FOUT becomes 1200 Mhz */
-                        __raw_writel(PLL45XX_APLL_VAL_1200, S5P_APLL_CON);
+                        /* APLL FOUT becomes 1320 Mhz */
+                        __raw_writel(PLL45XX_APLL_VAL_1320, S5P_APLL_CON);
                         break;
                 case L1:
-                        /* APLL FOUT becomes 1000 Mhz */
-                        __raw_writel(PLL45XX_APLL_VAL_1000, S5P_APLL_CON);
+                        /* APLL FOUT becomes 1096 Mhz */
+                        __raw_writel(PLL45XX_APLL_VAL_1096, S5P_APLL_CON);
                         break;
                 default:
                         /* APLL FOUT becomes 800 Mhz */
@@ -804,7 +804,7 @@ static int __init s5pv210_cpufreq_driver_init(struct cpufreq_policy *policy)
 
 	ret = cpufreq_frequency_table_cpuinfo(policy, freq_table);
 	/* define safe default min and max speeds */
-	policy->max = 1200000;
+	policy->max = 1096000;
 	policy->min = 100000;
 	return ret;
 }

arch/arm/mach-s5pv210/include/mach/cpu-freq-v210.h

@@ -18,22 +18,24 @@
  * APLL M,P,S value for target frequency
  **/
 #define APLL_VAL_1664	((1<<31)|(417<<16)|(3<<8)|(0))
+#define APLL_VAL_1320	((1<<31)|(165<<16)|(3<<8)|(1))
 #define APLL_VAL_1332	((1<<31)|(444<<16)|(4<<8)|(0))
-#define APLL_VAL_1200	((1<<31)|(150<<16)|(3<<8)|(1))
-#define APLL_VAL_1000	((1<<31)|(125<<16)|(3<<8)|(1))
+#define APLL_VAL_1200	((1<<31)|(150<<16)|(3<<8)|(0))
+#define APLL_VAL_1096	((1<<31)|(137<<16)|(3<<8)|(1))
+#define APLL_VAL_1000	((1<<31)|(125<<16)|(3<<8)|(0))
 #define APLL_VAL_800	((1<<31)|(100<<16)|(3<<8)|(1))
 
 enum perf_level {
-	L0 = 0,	// 1.2GHz
-	L1,     // 1GHz
+	L0 = 0,	// 1.32GHz
+	L1,     // 1.096GHz
 	L2,	// 800MHz
 	L3,	// 400MHz
 	L4,	// 200MHz
 	L5,	// 100MHz
 	MAX_PERF_LEVEL = L5,
 };
 #ifdef CONFIG_MACH_VENTURI
-#define SLEEP_FREQ      (1000 * 1000) /* Use 1GHz when entering sleep */
+#define SLEEP_FREQ      (1096 * 1000) /* Use 1GHz when entering sleep */
 #else
 #define SLEEP_FREQ      (800 * 1000) /* Use 800MHz when entering sleep */
 #endif

arch/arm/mach-s5pv210/mach-venturi.c

@@ -339,12 +339,12 @@ static struct s3cfb_lcd hx8369 = {
 #define  S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMC1 (5000 * SZ_1K)
 #define  S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMC2 (5000 * SZ_1K)
 #define  S5PV210_VIDEO_SAMSUNG_MEMSIZE_MFC0 (32768 * SZ_1K)
-#define  S5PV210_VIDEO_SAMSUNG_MEMSIZE_MFC1 (32768 * SZ_1K)
-#define  S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMD (4800 * SZ_1K)
+#define  S5PV210_VIDEO_SAMSUNG_MEMSIZE_MFC1 (32768* SZ_1K)
+#define  S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMD (3000 * SZ_1K)
 #define  S5PV210_VIDEO_SAMSUNG_MEMSIZE_JPEG (8192 * SZ_1K)
-#define  S5PV210_VIDEO_SAMSUNG_MEMSIZE_PMEM (8192 * SZ_1K)
-#define  S5PV210_VIDEO_SAMSUNG_MEMSIZE_GPU1 (3300 * SZ_1K)
-#define  S5PV210_VIDEO_SAMSUNG_MEMSIZE_ADSP (6144 * SZ_1K)
+#define  S5PV210_VIDEO_SAMSUNG_MEMSIZE_PMEM (2048 * SZ_1K)
+#define  S5PV210_VIDEO_SAMSUNG_MEMSIZE_GPU1 (3000 * SZ_1K)
+#define  S5PV210_VIDEO_SAMSUNG_MEMSIZE_ADSP (1500* SZ_1K)
 #define  S5PV210_VIDEO_SAMSUNG_MEMSIZE_TEXTSTREAM (3000 * SZ_1K)
 #else	// optimized settings, 19th Jan.2011
 #define  S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMC0 (5000 * SZ_1K)
@@ -356,7 +356,7 @@ static struct s3cfb_lcd hx8369 = {
 #define  S5PV210_VIDEO_SAMSUNG_MEMSIZE_MFC1 (32768 * SZ_1K)
 #else    /* NTT - support playing 1080p */
 #define  S5PV210_VIDEO_SAMSUNG_MEMSIZE_MFC0 (32768 * SZ_1K)
-#define  S5PV210_VIDEO_SAMSUNG_MEMSIZE_MFC1 (32768 * SZ_1K)
+#define  S5PV210_VIDEO_SAMSUNG_MEMSIZE_MFC1 (32768* SZ_1K)
 #endif
 #else    /* NTT - support playing 1080p */
 #define  S5PV210_VIDEO_SAMSUNG_MEMSIZE_MFC0 (32768 * SZ_1K)
@@ -369,8 +369,8 @@ static struct s3cfb_lcd hx8369 = {
                                                  (CONFIG_FB_S3C_NUM_OVLY_WIN * \
                                                   CONFIG_FB_S3C_NUM_BUF_OVLY_WIN)))
 #define  S5PV210_VIDEO_SAMSUNG_MEMSIZE_JPEG (8192 * SZ_1K)
-#define  S5PV210_VIDEO_SAMSUNG_MEMSIZE_PMEM (5550 * SZ_1K)
-#define  S5PV210_VIDEO_SAMSUNG_MEMSIZE_GPU1 (3300 * SZ_1K)
+#define  S5PV210_VIDEO_SAMSUNG_MEMSIZE_PMEM (2048 * SZ_1K)
+#define  S5PV210_VIDEO_SAMSUNG_MEMSIZE_GPU1 (3000 * SZ_1K)
 #define  S5PV210_VIDEO_SAMSUNG_MEMSIZE_ADSP (1500 * SZ_1K)
 #define  S5PV210_VIDEO_SAMSUNG_MEMSIZE_TEXTSTREAM (3000 * SZ_1K)
 #endif
@@ -3504,7 +3504,7 @@ static u8 t7_config[] = {GEN_POWERCONFIG_T7,
 static u8 t8_config[] = {GEN_ACQUISITIONCONFIG_T8,
 				7, 0, 5, 0, 0, 0, 9, 35};
 static u8 t9_config[] = {TOUCH_MULTITOUCHSCREEN_T9,
-				139, 0, 0, 19, 11, 0, 33, 30, 0, 1, 0, 0, 1,
+				139, 0, 0, 19, 11, 0, 33, 25, 0, 1, 0, 0, 1,
 				46, MXT224_MAX_MT_FINGERS, 5, 14, 10, 255, 3,
 				255, 3, 18, 18, 10, 10, 141, 65, 143, 110, 18};
 static u8 t18_config[] = {SPT_COMCONFIG_T18,

arch/arm/plat-s5p/include/plat/pll.h

@@ -21,8 +21,8 @@
 
 #include <asm/div64.h>
 
-#define PLL45XX_APLL_VAL_1200	((1 << 31) | (150 << 16) | (3 << 8) | (1))
-#define PLL45XX_APLL_VAL_1000	((1 << 31) | (125 << 16) | (3 << 8) | (1))
+#define PLL45XX_APLL_VAL_1320	((1 << 31) | (165 << 16) | (3 << 8) | (1))
+#define PLL45XX_APLL_VAL_1096	((1 << 31) | (137 << 16) | (3 << 8) | (1))
 #define PLL45XX_APLL_VAL_800	((1 << 31) | (100 << 16) | (3 << 8) | (1))
 
 enum pll45xx_type_t {

block/cfq-iosched.c

@@ -1388,16 +1388,11 @@ static void cfq_add_rq_rb(struct request *rq)
 {
 	struct cfq_queue *cfqq = RQ_CFQQ(rq);
 	struct cfq_data *cfqd = cfqq->cfqd;
-	struct request *__alias, *prev;
+	struct request *prev;
 
 	cfqq->queued[rq_is_sync(rq)]++;
 
-	/*
-	 * looks a little odd, but the first insert might return an alias.
-	 * if that happens, put the alias on the dispatch list
-	 */
-	while ((__alias = elv_rb_add(&cfqq->sort_list, rq)) != NULL)
-		cfq_dispatch_insert(cfqd->queue, __alias);
+	elv_rb_add(&cfqq->sort_list, rq);
 
 	if (!cfq_cfqq_on_rr(cfqq))
 		cfq_add_cfqq_rr(cfqd, cfqq);

block/deadline-iosched.c

@@ -77,10 +77,7 @@ static void
 deadline_add_rq_rb(struct deadline_data *dd, struct request *rq)
 {
 	struct rb_root *root = deadline_rb_root(dd, rq);
-	struct request *__alias;
-
-	while (unlikely(__alias = elv_rb_add(root, rq)))
-		deadline_move_request(dd, __alias);
+	 elv_rb_add(root, rq);
 }
 
 static inline void

block/elevator.c

@@ -353,7 +353,7 @@ static struct request *elv_rqhash_find(struct request_queue *q, sector_t offset)
  * RB-tree support functions for inserting/lookup/removal of requests
  * in a sorted RB tree.
  */
-struct request *elv_rb_add(struct rb_root *root, struct request *rq)
+void elv_rb_add(struct rb_root *root, struct request *rq)
 {
 	struct rb_node **p = &root->rb_node;
 	struct rb_node *parent = NULL;
@@ -365,15 +365,12 @@ struct request *elv_rb_add(struct rb_root *root, struct request *rq)
 
 		if (blk_rq_pos(rq) < blk_rq_pos(__rq))
 			p = &(*p)->rb_left;
-		else if (blk_rq_pos(rq) > blk_rq_pos(__rq))
+		else if (blk_rq_pos(rq) >= blk_rq_pos(__rq))
 			p = &(*p)->rb_right;
-		else
-			return __rq;
 	}
 
 	rb_link_node(&rq->rb_node, parent, p);
 	rb_insert_color(&rq->rb_node, root);
-	return NULL;
 }
 EXPORT_SYMBOL(elv_rb_add);
 

drivers/cpufreq/cpufreq.c

@@ -33,7 +33,7 @@
 						"cpufreq-core", msg)
 
 /* UV */
-int exp_UV_mV[6] = {1300000, 1275000, 1200000, 1050000, 950000, 950000 };
+int exp_UV_mV[6] = {1310000, 1285000, 1100000, 1050000, 950000, 950000 };
 
 /**
  * The "cpufreq driver" - the arch- or hardware-dependent low
@@ -653,7 +653,7 @@ static ssize_t show_scaling_setspeed(struct cpufreq_policy *policy, char *buf)
 /* sysfs interface for UV control */
 static ssize_t show_UV_mV_table(struct cpufreq_policy *policy, char *buf) {
 
-  return sprintf(buf, "1200mhz: %d mV\n1000mhz: %d mV\n800mhz: %d mV\n400mhz: %d mV\n200mhz: %d mV\n100mhz: %d mV\n", exp_UV_mV[0]/1000, exp_UV_mV[1]/1000, exp_UV_mV[2]/1000, exp_UV_mV[3]/1000, exp_UV_mV[4]/1000, exp_UV_mV[5]/1000);
+  return sprintf(buf, "1320mhz: %d mV\n1096mhz: %d mV\n800mhz: %d mV\n400mhz: %d mV\n200mhz: %d mV\n100mhz: %d mV\n", exp_UV_mV[0]/1000, exp_UV_mV[1]/1000, exp_UV_mV[2]/1000, exp_UV_mV[3]/1000, exp_UV_mV[4]/1000, exp_UV_mV[5]/1000);
 
 }