Update dvl2013.md (#328)

src/design_notebooks/2024fall/dvl2013.md

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 ## Work for Week Ending 9-13
 * Completed Lab 1 and built dependencies on local system (cmake, verilator, git, cURL)
-* Completed Lab 2 and began on Lab 3 for verification: https://github.com/DmitriLyalikov/onboarding-lab-2/
+* Completed Lab 2 https://github.com/DmitriLyalikov/onboarding-lab-2/
+
+### Work for Week end September 23
+Started on lab 3, had trouble with Cmake and running verilator tests on my virtual machine (Debian)
+
+- **30 September 2024:**  
+  Went to meeting. Started studying SystemVerilog and verification more deeply. Got a book (SystemVerilog For Verification: A Guide to Learning the Testbench Language Features by Chris Spear & Greg Tumbush (3rd Edition))
+
+- **7 October 2024:**  
+  Was away this week for a conference event. Continued reading about system verilog and UVM verification. 
+
+- **14 October 2024:**  
+  Finished Lab 3. 
+
+- **21 October 2024:**  
+  Started lab 4, finsihed same week.
+
+- **28 October 2024:**  
+  Started reading through lab 5, also got access to Cadence University program and started online Cadence course for systemverilog (https://www.cadence.com/en_US/home/training/all-courses/82143.html)
+
+- **4 November 2024:**  
+  Finished and understood lab 5, continuing on SV course outside of direct work. 
+
+- **11 November 2024:**  
+  Started group work on presentation. Selected project for open source ASIC design flow. Made initial template for presentation based on each design flow step.
+
+- **18 November 2024:**  
+  Finished Lab 6, and read about openroad and Chipyard for synthesis and open hardware for reuse. 
+
+- **25 November 2024:**  
+  Finalized presentation and contributed topics on synthesis (YoSys, OpenRoad), Open IP (Chipyard, EFabless) and open PDKs for physical design. Consulted with an expert at Microchip Technology on FPGA flows and tools as well. Got good feedback and understanding of the PolarFire FPGAs.
+
+- **28 November 2024:**  
+  Finished presentation. Presented on Thursday meeting, started on lab 7, despite no direct work on it. 
+
+- **12 December 2024:**
+- Finished reading through labs 7 and 8. Pushed final update for semester. Good luck on finals everyone and have a good break!
+
+
+
+**Project Work:**  
+
+- **Onboarding Lab 1:**  
+
+- **Onboarding Lab 2:**  
+  - **Repository Link:** [Lab 2 Repository](https://github.com/DmitriLyalikov/onboarding-lab-2)  
+
+
+- **Onboarding Lab 3:**  
+  - **Repository Link:** [Lab 3 Repository](https://github.com/DmitriLyalikov/onboarding-lab-3)  
+
+
+- **Onboarding Lab 4:**  
+  - **Repository Link:** [Lab 4 Repository](https://github.com/DmitriLyalikov/onboarding-lab-4)
+
+  - ** VIP Presentation on Open Sourse ASIC Design Flow **
+
+---
+
+