Improvements to the HDL build

HDL/.gitignore

@@ -3,4 +3,5 @@ uImage
 devicetree.dtb
 *~
 tmp/
-vivado*
+vivado*
+.Xil/

HDL/Makefile

@@ -23,7 +23,7 @@ RM = rm -rf
 
 VIVADO_VER = $(shell vivado -version | grep "v20" | sed -r 's/.*v(20[0-9]{2}.[0-9]).*/\1/g')
 
-DTREE_TAG = xlnx_rel_v2022.2
+DTREE_TAG = xlnx_rel_v2024.1
 
 DTREE_DIR = tmp/device-tree-xlnx-$(DTREE_TAG)
 DTREE_URL = https://github.com/Xilinx/device-tree-xlnx/
@@ -34,7 +34,7 @@ DTREE_URL = https://github.com/Xilinx/device-tree-xlnx/
 .PHONY: clean all xpr bit dtbo setup
 
 .ONESHELL:
-all: setup tmp/%.bin tmp/%.dtbo
+all: setup tmp/%.bin
 
 
 .ONESHELL:

HDL/README.md

@@ -2,11 +2,11 @@
 
 This directory contains all the HDL code of the ocra project. The code is organized in projects, which can be found in subdirectories of the projects folders.
 
-In order to build the HDL code you need to have Xilinx Vitis 2022.2 full edition. We highly recommend that you use Linux, because the build system and other tooling relies on Linux. We are working on and recommend [Ubuntu 22.04 LTS](https://ubuntu.com/download/desktop).
+In order to build the HDL code you need to have at least Xilinx Vitis 2022.2 full edition. This build has been tested up to Vitis 2024.1. We highly recommend that you use Linux, because the build system and other tooling relies on Linux. We are working on and recommend [Ubuntu 22.04 LTS or Ubuntu 24.04 LTS](https://ubuntu.com/download/desktop).
 
 **Basic working knowledge of Linux and bash is more or less required to follow these instructions.**
 
-In order to install Vitis you will need about 110 GB of free disk space, and you will need to register an account with Xilinx website (remember the password, because the installer will also require the same login credentials that you created on the Xilinx website. It is best to download the [Vitis web installer](https://www.xilinx.com/member/forms/download/xef.html?filename=Xilinx_Unified_2022.2_1014_8888_Lin64.bin).
+In order to install Vitis you will need about 110 GB of free disk space, and you will need to register an account with Xilinx website (remember the password, because the installer will also require the same login credentials that you created on the Xilinx website. It is best to download the [Vitis web installer](https://account.amd.com/en/forms/downloads/xef.html?filename=FPGAs_AdaptiveSoCs_Unified_2024.1_0522_2023_Lin64.bin).
 
 Vivado (the main tool in the Vitis package) is a bit of a beast and requires a reasonably powerful workstation.
 
@@ -15,15 +15,18 @@ All building of the HDL is done by a [GNU Makefile](https://www.gnu.org/software
 This makes it straightforward to build multiple projects etc. from the command line without having to wrestle the Vivado GUI. This entire setup is based on the [red-pitaya-notes](https://github.com/pavel-demin/red-pitaya-notes) by Pavel Demin, and some of his architecture and cores can also be found in this repository.
 
 This repository makes use of Vivado board files, which requires additional configuration of your Vivado/Vitis setup. In order to make everything work the following configuration steps need to be taken:
-1. Add `source /tools/Xilinx/Vitis/2022.2/settings64.sh` to your `.bash_profile`
+1. Add `source /tools/Xilinx/Vitis/2024.1/settings64.sh` to your `.bash_profile`
 1. Define the environment variable OCRA_DIR in your `.bash_profile` to point to the ocra directory
-2. Include the following in your local Vivado config (i.e. $HOME/.Xilinx/Vivado/2022.2/Vivado_init.tcl):
+2. Include the following in your local Vivado config (i.e. $HOME/.Xilinx/Vivado/2024.1/Vivado_init.tcl):
 ```
 # set up the OCRA project
 set ocra_dir $::env(OCRA_DIR)
 source $ocra_dir/HDL/scripts/Vivado_ocra_init.tcl
 ```
 
+You may need to adjust the path of your Vitis installation as appropriate for this to be correct on your installation.
+
+
 To get a quick start, assuming you have Vitis/Vivado configured in your path, you should be able to build the base_pl project for the snickerdoodle_black
 ```
 cd $OCRA_DIR/HDL
@@ -35,4 +38,12 @@ Similarily, you can build the ocra_mri project for the stemlab_125_14 by calling
 make NAME=ocra_mri BOARD=stemlab_125_14
 ```
 
+This will build bitfiles that can be used with on a Linux installation on your Zynq so long it supports the fpga_manager. If you want to build a device tree and the associated files to create your own bootloader etc. you need to run
+
+```
+make dtbo NAME=ocra_mri BOARD=stemlab_125_14
+```
+
+Note that this requires the HSI tool xsct and the device tree compiler dtc.
+
 This is pretty easy, isn't it?