Task 5 (Hazard Detection & Forwarding) added

05_pipelined_RISC-V_core_hazardDetection/build.sbt

@@ -0,0 +1,19 @@
+scalaVersion := "2.12.13"
+
+scalacOptions ++= Seq(
+  "-deprecation",
+  "-feature",
+  "-unchecked",
+  "-Xfatal-warnings",
+  "-language:reflectiveCalls",
+)
+
+resolvers ++= Seq(
+  Resolver.sonatypeRepo("snapshots"),
+  Resolver.sonatypeRepo("releases")
+)
+
+// Chisel 3.5
+addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.5.0" cross CrossVersion.full)
+libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.5.0"
+libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "0.5.0"

05_pipelined_RISC-V_core_hazardDetection/src/main/scala/HazardDetectionRISCV32I.scala

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+// ADS I Class Project
+// Pipelined RISC-V Core with Hazard Detetcion and Resolution
+//
+// Chair of Electronic Design Automation, RPTU in Kaiserslautern
+// File created on 05/21/2024 by Andro Mazmishvili (@Andrew8846)
+
+package HazardDetectionRV32I
+
+import chisel3._
+import chisel3.util._
+
+import core_tile._
+
+class HazardDetectionRV32I (BinaryFile: String) extends Module {
+
+  val io     = IO(new Bundle {
+    val result = Output(UInt(32.W)) 
+  })
+
+  val core   = Module(new HazardDetectionRV32Icore(BinaryFile))
+
+  io.result  := core.io.check_res
+
+}
+

05_pipelined_RISC-V_core_hazardDetection/src/main/scala/MakeVerilog.scala

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+// ADS I Class Project
+// Pipelined RISC-V Core with Hazard Detetcion and Resolution
+//
+// Chair of Electronic Design Automation, RPTU in Kaiserslautern
+// File created on 05/21/2024 by Andro Mazmishvili (@Andrew8846)
+
+package makeverilog
+
+import chisel3._
+import chiseltest._
+import org.scalatest.flatspec.AnyFlatSpec
+
+import HazardDetectionRV32I._
+
+
+object Verilog_Gen extends App {
+  emitVerilog(new HazardDetectionRV32I("src/test/programs/BinaryFile"), Array("--target-dir", "generated-src")
+)}