Update to svd2rust 0.33.1 #155

Rahix · 2024-05-04T20:47:01Z

This improves the generated API in various ways.

The most major change seems to be from 0.31.0 where registers are now accessed using methods instead of fields. This will require rather large downstream changes.

Upstream svd2rust also switched to a different case style for identifiers in 0.32.0. For now, this is disabled using --ident-formats legacy but we should consider following their suggestion at some point in the future.

This improves the generated API in various minor ways. We cannot guarantee full backwards compatibility for downstream users but the changes should not be too disrupting. Most importantly, upstream svd2rust switched to a different case style for identifiers in 0.32.0. For now, this is disabled using `--ident-formats legacy` but we should consider following their suggestion at some point in the future.

This is needed to ensure the changed versions are actually used.

Rahix · 2024-05-04T21:11:22Z

Full diff (very large!): svd2rust-0.33.1-changes.diff.txt.zip

"Manageable" diff of just ATmega328P: svd2rust-0.33.1-changes-atmega328p.diff.txt

Rahix · 2024-05-04T22:33:43Z

The most major change seems to be from 0.31.0 where registers are now accessed using methods instead of fields. This will require rather large downstream changes.

This can be fixed rather easily for avr-hal: Rustc already makes some good suggestions for where the parentheses are missing to convert field accesses into method calls. So with a bit of jq and sed magic, we can apply those fixes automatically. Simply run the following command from inside examples/arduino-uno:

cargo build --message-format json 2>/dev/null | jq '.message.children[].spans[] | {file: .file_name, line: .line_start, col: (.text[0].highlight_start - 1), insert: .suggested_replacement}' 2>/dev/null | jq -r '"sed -ri '"'"'" + (.line | tostring) + "s/^(.{" + (.col | tostring) + "})/\\1" + .insert + "/'"'"' $(cd ../..; realpath " + .file + ")"' | sort | uniq | bash

(Definitely not cursed......)

For reference, the diff it produces is here:

avr-hal diff

diff --git a/avr-hal-generic/src/adc.rs b/avr-hal-generic/src/adc.rs
index 0d6904c2d4..acf5ec4c62 100644
--- a/avr-hal-generic/src/adc.rs
+++ b/avr-hal-generic/src/adc.rs
@@ -250,17 +250,17 @@ macro_rules! impl_adc {
 
             #[inline]
             fn raw_read_adc(&self) -> u16 {
-                self.adc.read().bits()
+                self.adc().read().bits()
             }
 
             #[inline]
             fn raw_is_converting(&self) -> bool {
-                self.adcsra.read().adsc().bit_is_set()
+                self.adcsra().read().adsc().bit_is_set()
             }
 
             #[inline]
             fn raw_start_conversion(&mut self) {
-                self.adcsra.modify(|_, w| w.adsc().set_bit());
+                self.adcsra().modify(|_, w| w.adsc().set_bit());
             }
 
             #[inline]
@@ -276,7 +276,7 @@ macro_rules! impl_adc {
                 match channel {
                     $(
                         x if x == $pin_channel => {
-                            $(self.$didr.modify(|_, w| w.$didr_method().set_bit());)?
+                            $(self.$didr().modify(|_, w| w.$didr_method().set_bit());)?
                         }
                     )+
                     _ => unreachable!(),
@@ -288,7 +288,7 @@ macro_rules! impl_adc {
                 match channel {
                     $(
                         x if x == $pin_channel => {
-                            $(self.$didr.modify(|_, w| w.$didr_method().clear_bit());)?
+                            $(self.$didr().modify(|_, w| w.$didr_method().clear_bit());)?
                         }
                     )+
                     _ => unreachable!(),
diff --git a/avr-hal-generic/src/eeprom.rs b/avr-hal-generic/src/eeprom.rs
index ce9094519b..d8706e7e39 100644
--- a/avr-hal-generic/src/eeprom.rs
+++ b/avr-hal-generic/src/eeprom.rs
@@ -159,8 +159,8 @@ macro_rules! impl_eeprom_common {
                         $set_address
                     }
 
-                    self.eecr.write(|w| w.eere().set_bit());
-                    self.eedr.read().bits()
+                    self.eecr().write(|w| w.eere().set_bit());
+                    self.eedr().read().bits()
                 }
             }
 
@@ -173,8 +173,8 @@ macro_rules! impl_eeprom_common {
                     }
 
                     //Start EEPROM read operation
-                    self.eecr.write(|w| w.eere().set_bit());
-                    let old_value = self.eedr.read().bits();
+                    self.eecr().write(|w| w.eere().set_bit());
+                    let old_value = self.eedr().read().bits();
                     let diff_mask = old_value ^ data;
 
                     // Check if any bits are changed to '1' in the new value.
@@ -184,20 +184,20 @@ macro_rules! impl_eeprom_common {
                         // Check if any bits in the new value are '0'.
                         if data != 0xff {
                             // Now we know that some bits need to be programmed to '0' also.
-                            self.eedr.write(|w| w.bits(data)); // Set EEPROM data register.
+                            self.eedr().write(|w| w.bits(data)); // Set EEPROM data register.
 
                             {
                                 let $periph_ewmode_var = &self;
                                 $set_erasewrite_mode
                             }
-                            self.eecr.modify(|_, w| w.eepe().set_bit()); // Start Erase+Write operation.
+                            self.eecr().modify(|_, w| w.eepe().set_bit()); // Start Erase+Write operation.
                         } else {
                             // Now we know that all bits should be erased.
                             {
                                 let $periph_emode_var = &self;
                                 $set_erase_mode
                             }
-                            self.eecr.modify(|_, w| w.eepe().set_bit()); // Start Erase-only operation.
+                            self.eecr().modify(|_, w| w.eepe().set_bit()); // Start Erase-only operation.
                         }
                     }
                     //Now we know that _no_ bits need to be erased to '1'.
@@ -205,12 +205,12 @@ macro_rules! impl_eeprom_common {
                         // Check if any bits are changed from '1' in the old value.
                         if diff_mask != 0 {
                             // Now we know that _some_ bits need to the programmed to '0'.
-                            self.eedr.write(|w| w.bits(data)); // Set EEPROM data register.
+                            self.eedr().write(|w| w.bits(data)); // Set EEPROM data register.
                             {
                                 let $periph_wmode_var = &self;
                                 $set_write_mode
                             }
-                            self.eecr.modify(|_, w| w.eepe().set_bit()); // Start Write-only operation.
+                            self.eecr().modify(|_, w| w.eepe().set_bit()); // Start Write-only operation.
                         }
                     }
                 }
@@ -229,7 +229,7 @@ macro_rules! impl_eeprom_common {
                         $set_erase_mode
                     }
                     // Start Erase-only operation.
-                    self.eecr.modify(|_, w| w.eepe().set_bit());
+                    self.eecr().modify(|_, w| w.eepe().set_bit());
                 }
             }
         }
@@ -305,7 +305,7 @@ macro_rules! impl_eeprom_atmega {
             #[inline]
             pub unsafe fn wait_read(regs: &$EEPROM) {
                 //Wait for completion of previous write.
-                while regs.eecr.read().eepe().bit_is_set() {}
+                while regs.eecr().read().eepe().bit_is_set() {}
             }
             #[inline]
             pub unsafe fn set_address(regs: &$EEPROM, address: $addrwidth) {
@@ -316,21 +316,21 @@ macro_rules! impl_eeprom_atmega {
             }
             #[inline]
             pub unsafe fn set_erasewrite_mode(regs: &$EEPROM) {
-                regs.eecr.write(|w| {
+                regs.eecr().write(|w| {
                     // Set Master Write Enable bit, and and Erase+Write mode mode..
                     w.eempe().set_bit().eepm().val_0x00()
                 })
             }
             #[inline]
             pub unsafe fn set_erase_mode(regs: &$EEPROM) {
-                regs.eecr.write(|w| {
+                regs.eecr().write(|w| {
                     // Set Master Write Enable bit, and Erase-only mode..
                     w.eempe().set_bit().eepm().val_0x01()
                 });
             }
             #[inline]
             pub unsafe fn set_write_mode(regs: &$EEPROM) {
-                regs.eecr.write(|w| {
+                regs.eecr().write(|w| {
                     // Set Master Write Enable bit, and Write-only mode..
                     w.eempe().set_bit().eepm().val_0x02()
                 });
diff --git a/avr-hal-generic/src/i2c.rs b/avr-hal-generic/src/i2c.rs
index 1159ce2cf6..839e0a4a6a 100644
--- a/avr-hal-generic/src/i2c.rs
+++ b/avr-hal-generic/src/i2c.rs
@@ -466,22 +466,22 @@ macro_rules! impl_i2c_twi {
             fn raw_setup<CLOCK: $crate::clock::Clock>(&mut self, speed: u32) {
                 // Calculate TWBR register value
                 let twbr = ((CLOCK::FREQ / speed) - 16) / 2;
-                self.twbr.write(|w| unsafe { w.bits(twbr as u8) });
+                self.twbr().write(|w| unsafe { w.bits(twbr as u8) });
 
                 // Disable prescaler
-                self.twsr.write(|w| w.twps().prescaler_1());
+                self.twsr().write(|w| w.twps().prescaler_1());
             }
 
             #[inline]
             fn raw_start(&mut self, address: u8, direction: Direction) -> Result<(), Error> {
                 // Write start condition
-                self.twcr
+                self.twcr()
                     .write(|w| w.twen().set_bit().twint().set_bit().twsta().set_bit());
                 // wait()
-                while self.twcr.read().twint().bit_is_clear() {}
+                while self.twcr().read().twint().bit_is_clear() {}
 
                 // Validate status
-                match self.twsr.read().tws().bits() {
+                match self.twsr().read().tws().bits() {
                     $crate::i2c::twi_status::TW_START | $crate::i2c::twi_status::TW_REP_START => (),
                     $crate::i2c::twi_status::TW_MT_ARB_LOST
                     | $crate::i2c::twi_status::TW_MR_ARB_LOST => {
@@ -502,13 +502,13 @@ macro_rules! impl_i2c_twi {
                     0
                 };
                 let rawaddr = (address << 1) | dirbit;
-                self.twdr.write(|w| unsafe { w.bits(rawaddr) });
+                self.twdr().write(|w| unsafe { w.bits(rawaddr) });
                 // transact()
-                self.twcr.write(|w| w.twen().set_bit().twint().set_bit());
-                while self.twcr.read().twint().bit_is_clear() {}
+                self.twcr().write(|w| w.twen().set_bit().twint().set_bit());
+                while self.twcr().read().twint().bit_is_clear() {}
 
                 // Check if the slave responded
-                match self.twsr.read().tws().bits() {
+                match self.twsr().read().tws().bits() {
                     $crate::i2c::twi_status::TW_MT_SLA_ACK
                     | $crate::i2c::twi_status::TW_MR_SLA_ACK => (),
                     $crate::i2c::twi_status::TW_MT_SLA_NACK
@@ -535,12 +535,12 @@ macro_rules! impl_i2c_twi {
             #[inline]
             fn raw_write(&mut self, bytes: &[u8]) -> Result<(), Error> {
                 for byte in bytes {
-                    self.twdr.write(|w| unsafe { w.bits(*byte) });
+                    self.twdr().write(|w| unsafe { w.bits(*byte) });
                     // transact()
-                    self.twcr.write(|w| w.twen().set_bit().twint().set_bit());
-                    while self.twcr.read().twint().bit_is_clear() {}
+                    self.twcr().write(|w| w.twen().set_bit().twint().set_bit());
+                    while self.twcr().read().twint().bit_is_clear() {}
 
-                    match self.twsr.read().tws().bits() {
+                    match self.twsr().read().tws().bits() {
                         $crate::i2c::twi_status::TW_MT_DATA_ACK => (),
                         $crate::i2c::twi_status::TW_MT_DATA_NACK => {
                             self.raw_stop()?;
@@ -565,17 +565,17 @@ macro_rules! impl_i2c_twi {
                 let last = buffer.len() - 1;
                 for (i, byte) in buffer.iter_mut().enumerate() {
                     if i != last {
-                        self.twcr
+                        self.twcr()
                             .write(|w| w.twint().set_bit().twen().set_bit().twea().set_bit());
                         // wait()
-                        while self.twcr.read().twint().bit_is_clear() {}
+                        while self.twcr().read().twint().bit_is_clear() {}
                     } else {
-                        self.twcr.write(|w| w.twint().set_bit().twen().set_bit());
+                        self.twcr().write(|w| w.twint().set_bit().twen().set_bit());
                         // wait()
-                        while self.twcr.read().twint().bit_is_clear() {}
+                        while self.twcr().read().twint().bit_is_clear() {}
                     }
 
-                    match self.twsr.read().tws().bits() {
+                    match self.twsr().read().tws().bits() {
                         $crate::i2c::twi_status::TW_MR_DATA_ACK
                         | $crate::i2c::twi_status::TW_MR_DATA_NACK => (),
                         $crate::i2c::twi_status::TW_MR_ARB_LOST => {
@@ -589,14 +589,14 @@ macro_rules! impl_i2c_twi {
                         }
                     }
 
-                    *byte = self.twdr.read().bits();
+                    *byte = self.twdr().read().bits();
                 }
                 Ok(())
             }
 
             #[inline]
             fn raw_stop(&mut self) -> Result<(), Error> {
-                self.twcr
+                self.twcr()
                     .write(|w| w.twen().set_bit().twint().set_bit().twsto().set_bit());
                 Ok(())
             }
diff --git a/avr-hal-generic/src/port.rs b/avr-hal-generic/src/port.rs
index fb7f1cf767..cd1ecb55f3 100644
--- a/avr-hal-generic/src/port.rs
+++ b/avr-hal-generic/src/port.rs
@@ -632,7 +632,7 @@ macro_rules! impl_port_traditional {
                 #[inline]
                 unsafe fn out_set(&mut self) {
                     match self.port {
-                        $(DynamicPort::[<PORT $name>] => (*<$port>::ptr()).[<port $name:lower>].modify(|r, w| {
+                        $(DynamicPort::[<PORT $name>] => (*<$port>::ptr()).[<port $name:lower>]().modify(|r, w| {
                             w.bits(r.bits() | self.mask)
                         }),)+
                     }
@@ -641,7 +641,7 @@ macro_rules! impl_port_traditional {
                 #[inline]
                 unsafe fn out_clear(&mut self) {
                     match self.port {
-                        $(DynamicPort::[<PORT $name>] => (*<$port>::ptr()).[<port $name:lower>].modify(|r, w| {
+                        $(DynamicPort::[<PORT $name>] => (*<$port>::ptr()).[<port $name:lower>]().modify(|r, w| {
                             w.bits(r.bits() & !self.mask)
                         }),)+
                     }
@@ -650,7 +650,7 @@ macro_rules! impl_port_traditional {
                 #[inline]
                 unsafe fn out_toggle(&mut self) {
                     match self.port {
-                        $(DynamicPort::[<PORT $name>] => (*<$port>::ptr()).[<pin $name:lower>].write(|w| {
+                        $(DynamicPort::[<PORT $name>] => (*<$port>::ptr()).[<pin $name:lower>]().write(|w| {
                             w.bits(self.mask)
                         }),)+
                     }
@@ -660,7 +660,7 @@ macro_rules! impl_port_traditional {
                 unsafe fn out_get(&self) -> bool {
                     match self.port {
                         $(DynamicPort::[<PORT $name>] => {
-                            (*<$port>::ptr()).[<port $name:lower>].read().bits() & self.mask != 0
+                            (*<$port>::ptr()).[<port $name:lower>]().read().bits() & self.mask != 0
                         })+
                     }
                 }
@@ -669,7 +669,7 @@ macro_rules! impl_port_traditional {
                 unsafe fn in_get(&self) -> bool {
                     match self.port {
                         $(DynamicPort::[<PORT $name>] => {
-                            (*<$port>::ptr()).[<pin $name:lower>].read().bits() & self.mask != 0
+                            (*<$port>::ptr()).[<pin $name:lower>]().read().bits() & self.mask != 0
                         })+
                     }
                 }
@@ -677,7 +677,7 @@ macro_rules! impl_port_traditional {
                 #[inline]
                 unsafe fn make_output(&mut self) {
                     match self.port {
-                        $(DynamicPort::[<PORT $name>] => (*<$port>::ptr()).[<ddr $name:lower>].modify(|r, w| {
+                        $(DynamicPort::[<PORT $name>] => (*<$port>::ptr()).[<ddr $name:lower>]().modify(|r, w| {
                             w.bits(r.bits() | self.mask)
                         }),)+
                     }
@@ -686,7 +686,7 @@ macro_rules! impl_port_traditional {
                 #[inline]
                 unsafe fn make_input(&mut self, pull_up: bool) {
                     match self.port {
-                        $(DynamicPort::[<PORT $name>] => (*<$port>::ptr()).[<ddr $name:lower>].modify(|r, w| {
+                        $(DynamicPort::[<PORT $name>] => (*<$port>::ptr()).[<ddr $name:lower>]().modify(|r, w| {
                             w.bits(r.bits() & !self.mask)
                         }),)+
                     }
@@ -715,45 +715,45 @@ macro_rules! impl_port_traditional {
 
                     #[inline]
                     unsafe fn out_set(&mut self) {
-                        (*<$port>::ptr()).[<port $name:lower>].modify(|_, w| {
+                        (*<$port>::ptr()).[<port $name:lower>]().modify(|_, w| {
                             w.[<p $name:lower $pin>]().set_bit()
                         })
                     }
 
                     #[inline]
                     unsafe fn out_clear(&mut self) {
-                        (*<$port>::ptr()).[<port $name:lower>].modify(|_, w| {
+                        (*<$port>::ptr()).[<port $name:lower>]().modify(|_, w| {
                             w.[<p $name:lower $pin>]().clear_bit()
                         })
                     }
 
                     #[inline]
                     unsafe fn out_toggle(&mut self) {
-                        (*<$port>::ptr()).[<pin $name:lower>].write(|w| {
+                        (*<$port>::ptr()).[<pin $name:lower>]().write(|w| {
                             w.[<p $name:lower $pin>]().set_bit()
                         })
                     }
 
                     #[inline]
                     unsafe fn out_get(&self) -> bool {
-                        (*<$port>::ptr()).[<port $name:lower>].read().[<p $name:lower $pin>]().bit()
+                        (*<$port>::ptr()).[<port $name:lower>]().read().[<p $name:lower $pin>]().bit()
                     }
 
                     #[inline]
                     unsafe fn in_get(&self) -> bool {
-                        (*<$port>::ptr()).[<pin $name:lower>].read().[<p $name:lower $pin>]().bit()
+                        (*<$port>::ptr()).[<pin $name:lower>]().read().[<p $name:lower $pin>]().bit()
                     }
 
                     #[inline]
                     unsafe fn make_output(&mut self) {
-                        (*<$port>::ptr()).[<ddr $name:lower>].modify(|_, w| {
+                        (*<$port>::ptr()).[<ddr $name:lower>]().modify(|_, w| {
                             w.[<p $name:lower $pin>]().set_bit()
                         })
                     }
 
                     #[inline]
                     unsafe fn make_input(&mut self, pull_up: bool) {
-                        (*<$port>::ptr()).[<ddr $name:lower>].modify(|_, w| {
+                        (*<$port>::ptr()).[<ddr $name:lower>]().modify(|_, w| {
                             w.[<p $name:lower $pin>]().clear_bit()
                         });
                         if pull_up {
diff --git a/avr-hal-generic/src/simple_pwm.rs b/avr-hal-generic/src/simple_pwm.rs
index 93b4081bf5..b0330927c6 100644
--- a/avr-hal-generic/src/simple_pwm.rs
+++ b/avr-hal-generic/src/simple_pwm.rs
@@ -175,7 +175,7 @@ macro_rules! impl_simple_pwm {
                 }
 
                 fn get_duty(&self) -> Self::Duty {
-                    unsafe { (&*<$TIMER>::ptr()) }.$ocr.read().bits() as Self::Duty
+                    unsafe { (&*<$TIMER>::ptr()) }.$ocr().read().bits() as Self::Duty
                 }
 
                 fn get_max_duty(&self) -> Self::Duty {
@@ -185,7 +185,7 @@ macro_rules! impl_simple_pwm {
                 fn set_duty(&mut self, duty: Self::Duty) {
                     // SAFETY: This register is exclusively used here so there are no concurrency
                     // issues.
-                    unsafe { (&*<$TIMER>::ptr()).$ocr.write(|w| w.bits(duty.into())); };
+                    unsafe { (&*<$TIMER>::ptr()).$ocr().write(|w| w.bits(duty.into())); };
                 }
             }
         )+
diff --git a/avr-hal-generic/src/spi.rs b/avr-hal-generic/src/spi.rs
index d12563235c..73d2d2a30e 100644
--- a/avr-hal-generic/src/spi.rs
+++ b/avr-hal-generic/src/spi.rs
@@ -454,7 +454,7 @@ macro_rules! impl_spi {
                 use $crate::hal::spi;
 
                 // set up control register
-                self.spcr.write(|w| {
+                self.spcr().write(|w| {
                     // enable SPI
                     w.spe().set_bit();
                     // Set to primary mode
@@ -486,7 +486,7 @@ macro_rules! impl_spi {
                     }
                 });
                 // set up 2x clock rate status bit
-                self.spsr.write(|w| match settings.clock {
+                self.spsr().write(|w| match settings.clock {
                     SerialClockRate::OscfOver2 => w.spi2x().set_bit(),
                     SerialClockRate::OscfOver4 => w.spi2x().clear_bit(),
                     SerialClockRate::OscfOver8 => w.spi2x().set_bit(),
@@ -498,19 +498,19 @@ macro_rules! impl_spi {
             }
 
             fn raw_release(&mut self) {
-                self.spcr.write(|w| w.spe().clear_bit());
+                self.spcr().write(|w| w.spe().clear_bit());
             }
 
             fn raw_check_iflag(&self) -> bool {
-                self.spsr.read().spif().bit_is_set()
+                self.spsr().read().spif().bit_is_set()
             }
 
             fn raw_read(&self) -> u8 {
-                self.spdr.read().bits()
+                self.spdr().read().bits()
             }
 
             fn raw_write(&mut self, byte: u8) {
-                self.spdr.write(|w| unsafe { w.bits(byte) });
+                self.spdr().write(|w| unsafe { w.bits(byte) });
             }
 
             fn raw_transaction(&mut self, byte: u8) -> u8 {
diff --git a/avr-hal-generic/src/usart.rs b/avr-hal-generic/src/usart.rs
index d929cf553b..ed670014c5 100644
--- a/avr-hal-generic/src/usart.rs
+++ b/avr-hal-generic/src/usart.rs
@@ -484,18 +484,18 @@ macro_rules! impl_usart_traditional {
                 $crate::port::Pin<$crate::port::mode::Output, $txpin>,
             > for $USART {
                 fn raw_init<CLOCK>(&mut self, baudrate: $crate::usart::Baudrate<CLOCK>) {
-                    self.[<ubrr $n>].write(|w| unsafe { w.bits(baudrate.ubrr) });
-                    self.[<ucsr $n a>].write(|w| w.[<u2x $n>]().bit(baudrate.u2x));
+                    self.[<ubrr $n>]().write(|w| unsafe { w.bits(baudrate.ubrr) });
+                    self.[<ucsr $n a>]().write(|w| w.[<u2x $n>]().bit(baudrate.u2x));
 
                     // Enable receiver and transmitter but leave interrupts disabled.
-                    self.[<ucsr $n b>].write(|w| w
+                    self.[<ucsr $n b>]().write(|w| w
                         .[<txen $n>]().set_bit()
                         .[<rxen $n>]().set_bit()
                     );
 
                     // Set frame format to 8n1 for now.  At some point, this should be made
                     // configurable, similar to what is done in other HALs.
-                    self.[<ucsr $n c>].write(|w| w
+                    self.[<ucsr $n c>]().write(|w| w
                         .[<umsel $n>]().usart_async()
                         .[<ucsz $n>]().chr8()
                         .[<usbs $n>]().stop1()
@@ -506,11 +506,11 @@ macro_rules! impl_usart_traditional {
                 fn raw_deinit(&mut self) {
                     // Wait for any ongoing transfer to finish.
                     $crate::nb::block!(self.raw_flush()).ok();
-                    self.[<ucsr $n b>].reset();
+                    self.[<ucsr $n b>]().reset();
                 }
 
                 fn raw_flush(&mut self) -> $crate::nb::Result<(), core::convert::Infallible> {
-                    if self.[<ucsr $n a>].read().[<udre $n>]().bit_is_clear() {
+                    if self.[<ucsr $n a>]().read().[<udre $n>]().bit_is_clear() {
                         Err($crate::nb::Error::WouldBlock)
                     } else {
                         Ok(())
@@ -521,26 +521,26 @@ macro_rules! impl_usart_traditional {
                     // Call flush to make sure the data-register is empty
                     self.raw_flush()?;
 
-                    self.[<udr $n>].write(|w| unsafe { w.bits(byte) });
+                    self.[<udr $n>]().write(|w| unsafe { w.bits(byte) });
                     Ok(())
                 }
 
                 fn raw_read(&mut self) -> $crate::nb::Result<u8, core::convert::Infallible> {
-                    if self.[<ucsr $n a>].read().[<rxc $n>]().bit_is_clear() {
+                    if self.[<ucsr $n a>]().read().[<rxc $n>]().bit_is_clear() {
                         return Err($crate::nb::Error::WouldBlock);
                     }
 
-                    Ok(self.[<udr $n>].read().bits())
+                    Ok(self.[<udr $n>]().read().bits())
                 }
 
                 fn raw_interrupt(&mut self, event: $crate::usart::Event, state: bool) {
                     match event {
                         $crate::usart::Event::RxComplete =>
-                            self.[<ucsr $n b>].modify(|_, w| w.[<rxcie $n>]().bit(state)),
+                            self.[<ucsr $n b>]().modify(|_, w| w.[<rxcie $n>]().bit(state)),
                         $crate::usart::Event::TxComplete =>
-                            self.[<ucsr $n b>].modify(|_, w| w.[<txcie $n>]().bit(state)),
+                            self.[<ucsr $n b>]().modify(|_, w| w.[<txcie $n>]().bit(state)),
                         $crate::usart::Event::DataRegisterEmpty =>
-                            self.[<ucsr $n b>].modify(|_, w| w.[<udrie $n>]().bit(state)),
+                            self.[<ucsr $n b>]().modify(|_, w| w.[<udrie $n>]().bit(state)),
                     }
                 }
             }
diff --git a/avr-hal-generic/src/wdt.rs b/avr-hal-generic/src/wdt.rs
index 94d0a2d7ed..bb0da54fda 100644
--- a/avr-hal-generic/src/wdt.rs
+++ b/avr-hal-generic/src/wdt.rs
@@ -112,10 +112,10 @@ macro_rules! impl_wdt {
                     // Reset the watchdog timer.
                     self.raw_feed();
                     // Enable watchdog configuration mode.
-                    self.$wdtcsr
+                    self.$wdtcsr()
                         .modify(|_, w| w.wdce().set_bit().wde().set_bit());
                     // Enable watchdog and set interval.
-                    self.$wdtcsr.write(|w| {
+                    self.$wdtcsr().write(|w| {
                         let $to = timeout;
                         let $w = w;
                         ($to_match).wde().set_bit().wdce().clear_bit()
@@ -143,10 +143,10 @@ macro_rules! impl_wdt {
                     // Reset the watchdog timer.
                     self.raw_feed();
                     // Enable watchdog configuration mode.
-                    self.$wdtcsr
+                    self.$wdtcsr()
                         .modify(|_, w| w.wdce().set_bit().wde().set_bit());
                     // Disable watchdog.
-                    self.$wdtcsr.reset();
+                    self.$wdtcsr().reset();
                 })
             }
         }
diff --git a/mcu/atmega-hal/src/adc.rs b/mcu/atmega-hal/src/adc.rs
index d79f5866ec..817bef7ffe 100644
--- a/mcu/atmega-hal/src/adc.rs
+++ b/mcu/atmega-hal/src/adc.rs
@@ -32,7 +32,7 @@ pub struct AdcSettings {
 }
 
 fn apply_settings(peripheral: &crate::pac::ADC, settings: AdcSettings) {
-    peripheral.adcsra.write(|w| {
+    peripheral.adcsra().write(|w| {
         w.aden().set_bit();
         match settings.clock_divider {
             ClockDivider::Factor2 => w.adps().prescaler_2(),
@@ -44,7 +44,7 @@ fn apply_settings(peripheral: &crate::pac::ADC, settings: AdcSettings) {
             ClockDivider::Factor128 => w.adps().prescaler_128(),
         }
     });
-    peripheral.admux.write(|w| match settings.ref_voltage {
+    peripheral.admux().write(|w| match settings.ref_voltage {
         ReferenceVoltage::Aref => w.refs().aref(),
         ReferenceVoltage::AVcc => w.refs().avcc(),
         ReferenceVoltage::Internal => w.refs().internal(),
@@ -150,7 +150,7 @@ avr_hal_generic::impl_adc! {
     apply_settings: |peripheral, settings| { apply_settings(peripheral, settings) },
     channel_id: crate::pac::adc::admux::MUX_A,
     set_channel: |peripheral, id| {
-        peripheral.admux.modify(|_, w| w.mux().variant(id));
+        peripheral.admux().modify(|_, w| w.mux().variant(id));
     },
     pins: {
         port::PC0: (crate::pac::adc::admux::MUX_A::ADC0, didr0::adc0d),
diff --git a/mcu/atmega-hal/src/eeprom.rs b/mcu/atmega-hal/src/eeprom.rs
index 52f92eb689..a5bd4ff9c2 100644
--- a/mcu/atmega-hal/src/eeprom.rs
+++ b/mcu/atmega-hal/src/eeprom.rs
@@ -36,7 +36,7 @@ avr_hal_generic::impl_eeprom_atmega! {
     capacity: 1024,
     addr_width: u16,
     set_address: |peripheral, address| {
-        peripheral.eear.write(|w| w.bits(address));
+        peripheral.eear().write(|w| w.bits(address));
     },
 }
 
diff --git a/mcu/atmega-hal/src/simple_pwm.rs b/mcu/atmega-hal/src/simple_pwm.rs
index d0bda71be0..8a70ed0f02 100644
--- a/mcu/atmega-hal/src/simple_pwm.rs
+++ b/mcu/atmega-hal/src/simple_pwm.rs
@@ -25,8 +25,8 @@ avr_hal_generic::impl_simple_pwm! {
     pub struct Timer0Pwm {
         timer: crate::pac::TC0,
         init: |tim, prescaler| {
-            tim.tccr0a.modify(|_r, w| w.wgm0().pwm_fast());
-            tim.tccr0b.modify(|_r, w| match prescaler {
+            tim.tccr0a().modify(|_r, w| w.wgm0().pwm_fast());
+            tim.tccr0b().modify(|_r, w| match prescaler {
                 Prescaler::Direct => w.cs0().direct(),
                 Prescaler::Prescale8 => w.cs0().prescale_8(),
                 Prescaler::Prescale64 => w.cs0().prescale_64(),
@@ -38,18 +38,18 @@ avr_hal_generic::impl_simple_pwm! {
             PD6: {
                 ocr: ocr0a,
                 into_pwm: |tim| if enable {
-                    tim.tccr0a.modify(|_r, w| w.com0a().match_clear());
+                    tim.tccr0a().modify(|_r, w| w.com0a().match_clear());
                 } else {
-                    tim.tccr0a.modify(|_r, w| w.com0a().disconnected());
+                    tim.tccr0a().modify(|_r, w| w.com0a().disconnected());
                 },
             },
 
             PD5: {
                 ocr: ocr0b,
                 into_pwm: |tim| if enable {
-                    tim.tccr0a.modify(|_r, w| w.com0b().match_clear());
+                    tim.tccr0a().modify(|_r, w| w.com0b().match_clear());
                 } else {
-                    tim.tccr0a.modify(|_r, w| w.com0b().disconnected());
+                    tim.tccr0a().modify(|_r, w| w.com0b().disconnected());
                 },
             },
         },
@@ -78,8 +78,8 @@ avr_hal_generic::impl_simple_pwm! {
     pub struct Timer1Pwm {
         timer: crate::pac::TC1,
         init: |tim, prescaler| {
-            tim.tccr1a.modify(|_r, w| w.wgm1().bits(0b01));
-            tim.tccr1b.modify(|_r, w| {
+            tim.tccr1a().modify(|_r, w| w.wgm1().bits(0b01));
+            tim.tccr1b().modify(|_r, w| {
                 w.wgm1().bits(0b01);
 
                 match prescaler {
@@ -95,18 +95,18 @@ avr_hal_generic::impl_simple_pwm! {
             PB1: {
                 ocr: ocr1a,
                 into_pwm: |tim| if enable {
-                    tim.tccr1a.modify(|_r, w| w.com1a().match_clear());
+                    tim.tccr1a().modify(|_r, w| w.com1a().match_clear());
                 } else {
-                    tim.tccr1a.modify(|_r, w| w.com1a().disconnected());
+                    tim.tccr1a().modify(|_r, w| w.com1a().disconnected());
                 },
             },
 
             PB2: {
                 ocr: ocr1b,
                 into_pwm: |tim| if enable {
-                    tim.tccr1a.modify(|_r, w| w.com1b().match_clear());
+                    tim.tccr1a().modify(|_r, w| w.com1b().match_clear());
                 } else {
-                    tim.tccr1a.modify(|_r, w| w.com1b().disconnected());
+                    tim.tccr1a().modify(|_r, w| w.com1b().disconnected());
                 },
             },
         },
@@ -135,8 +135,8 @@ avr_hal_generic::impl_simple_pwm! {
     pub struct Timer2Pwm {
         timer: crate::pac::TC2,
         init: |tim, prescaler| {
-            tim.tccr2a.modify(|_r, w| w.wgm2().pwm_fast());
-            tim.tccr2b.modify(|_r, w| match prescaler {
+            tim.tccr2a().modify(|_r, w| w.wgm2().pwm_fast());
+            tim.tccr2b().modify(|_r, w| match prescaler {
                     Prescaler::Direct => w.cs2().direct(),
                     Prescaler::Prescale8 => w.cs2().prescale_8(),
                     Prescaler::Prescale64 => w.cs2().prescale_64(),
@@ -148,18 +148,18 @@ avr_hal_generic::impl_simple_pwm! {
             PB3: {
                 ocr: ocr2a,
                 into_pwm: |tim| if enable {
-                    tim.tccr2a.modify(|_r, w| w.com2a().match_clear());
+                    tim.tccr2a().modify(|_r, w| w.com2a().match_clear());
                 } else {
-                    tim.tccr2a.modify(|_r, w| w.com2a().disconnected());
+                    tim.tccr2a().modify(|_r, w| w.com2a().disconnected());
                 },
             },
 
             PD3: {
                 ocr: ocr2b,
                 into_pwm: |tim| if enable {
-                    tim.tccr2a.modify(|_r, w| w.com2b().match_clear());
+                    tim.tccr2a().modify(|_r, w| w.com2b().match_clear());
                 } else {
-                    tim.tccr2a.modify(|_r, w| w.com2b().disconnected());
+                    tim.tccr2a().modify(|_r, w| w.com2b().disconnected());
                 },
             },
         },

Rahix added 2 commits May 4, 2024 22:41

ci: Bump tools cache

0ee041b

This is needed to ensure the changed versions are actually used.

Rahix force-pushed the new-svd2rust branch from 716ce6a to 0ee041b Compare May 4, 2024 21:08

This was referenced May 4, 2024

treewide: Apply changes for new svd2rust API Rahix/avr-hal#545

Draft

Restructure ADC macros Rahix/avr-hal#457

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LuigiPiucco mentioned this pull request May 10, 2024

Investigate crate-size optimizations #59

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Rahix mentioned this pull request Jan 9, 2025

Move PAM generation to build time, optimizing download size #157

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tones111 mentioned this pull request Jan 11, 2025

svd2rust: update to v0.35.0 #176

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