Kernel+LibC: Clean up assembly code

Some assembly files were previously inconsistently formatted. - Use 4 spaces for indentation - Use `.L` as the local label prefix - Remove trailing whitespace
RatcheT2497 · Jan 10, 2025 · 524f699 · 524f699
1 parent 1e0e569
commit 524f699
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Showing 4 changed files with 100 additions and 100 deletions.
diff --git a/Kernel/Arch/aarch64/boot.S b/Kernel/Arch/aarch64/boot.S
@@ -13,32 +13,32 @@
 .global start
 .type start, @function
 start:
-  // Let only core 0 continue, put other cores to sleep.
-  mrs x13, MPIDR_EL1
-  and x13, x13, 0xff
-  cbnz x13, halt
+    // Let only core 0 continue, put other cores to sleep.
+    mrs x13, MPIDR_EL1
+    and x13, x13, 0xff
+    cbnz x13, halt
 
-  // Set the stack pointer register to the location defined in the linker script.
-  adrp x14, end_of_initial_stack
-  add x14, x14, :lo12:end_of_initial_stack
-  mov sp, x14
+    // Set the stack pointer register to the location defined in the linker script.
+    adrp x14, end_of_initial_stack
+    add x14, x14, :lo12:end_of_initial_stack
+    mov sp, x14
 
-  // Clear BSS.
-  adrp x14, start_of_bss
-  add x14, x14, :lo12:start_of_bss
-  adrp x15, end_of_bss
-  add x15, x15, :lo12:end_of_bss
-  cmp x14, x15
-  b.ge Lbss_clear_done
-Lbss_clear_loop:
-  str xzr, [x14], #8
-  cmp x14, x15
-  b.lt Lbss_clear_loop
-Lbss_clear_done:
+    // Clear BSS.
+    adrp x14, start_of_bss
+    add x14, x14, :lo12:start_of_bss
+    adrp x15, end_of_bss
+    add x15, x15, :lo12:end_of_bss
+    cmp x14, x15
+    b.ge .Lbss_clear_done
+.Lbss_clear_loop:
+    str xzr, [x14], #8
+    cmp x14, x15
+    b.lt .Lbss_clear_loop
+.Lbss_clear_done:
 
-  b pre_init
+    b pre_init
 
 halt:
-  msr daifset, #2
-  wfi
-  b halt
+    msr daifset, #2
+    wfi
+    b halt
diff --git a/Kernel/Arch/riscv64/boot.S b/Kernel/Arch/riscv64/boot.S
@@ -12,89 +12,89 @@
 linux_header:
 .option push
 .option arch, -c
-  j start                                   // u32 code0
-  j start                                   // u32 code1
+    j start                                   // u32 code0
+    j start                                   // u32 code1
 .option pop
 
-  // This offset is needed, as otherwise U-Boot will try to load us at the same address where OpenSBI is loaded.
-  // The value is the same that Linux uses.
-  .dword 0x400000                           // u64 text_offset
+    // This offset is needed, as otherwise U-Boot will try to load us at the same address where OpenSBI is loaded.
+    // The value is the same that Linux uses.
+    .dword 0x400000                           // u64 text_offset
 
-  .dword end_of_kernel_image - linux_header // u64 image_size
-  .dword 0                                  // u64 flags
-  .word 2                                   // u32 version
-  .word 0                                   // u32 res1
-  .dword 0                                  // u64 res2
-  .ascii "RISCV\0\0\0"                      // u64 magic (deprecated)
-  .ascii "RSC\x5"                           // u32 magic2
-  .word 0                                   // u32 res3
+    .dword end_of_kernel_image - linux_header // u64 image_size
+    .dword 0                                  // u64 flags
+    .word 2                                   // u32 version
+    .word 0                                   // u32 res1
+    .dword 0                                  // u64 res2
+    .ascii "RISCV\0\0\0"                      // u64 magic (deprecated)
+    .ascii "RSC\x5"                           // u32 magic2
+    .word 0                                   // u32 res3
 
 .global start
 .type start, @function
 start:
-  // We expect that only one hart jumps here and that we are running in supervisor mode.
-  // We also expect that an implementation of the RISC-V Supervisor Binary Interface is available.
+    // We expect that only one hart jumps here and that we are running in supervisor mode.
+    // We also expect that an implementation of the RISC-V Supervisor Binary Interface is available.
 
-  // Don't touch a0/a1 as we expect those registers to contain the hart ID
-  // and a pointer to the Flattened Devicetree.
+    // Don't touch a0/a1 as we expect those registers to contain the hart ID
+    // and a pointer to the Flattened Devicetree.
 
-  // Clear sstatus.SIE, which disables all interrupts in supervisor mode.
-  csrci sstatus, 1 << 1
+    // Clear sstatus.SIE, which disables all interrupts in supervisor mode.
+    csrci sstatus, 1 << 1
 
-  // Also, disable all interrupts sources and mark them as non-pending.
-  csrw sie, zero
-  csrw sip, zero
+    // Also, disable all interrupts sources and mark them as non-pending.
+    csrw sie, zero
+    csrw sip, zero
 
-  // TODO: maybe load the gp register here?
+    // TODO: maybe load the gp register here?
 
-  // Clear the BSS.
-  lla t0, start_of_bss
-  lla t1, end_of_bss
-  bgeu t0, t1, Lclear_bss_done
-Lclear_bss_loop:
-  sd zero, (t0)
-  addi t0, t0, 8
-  bltu t0, t1, Lclear_bss_loop
-Lclear_bss_done:
+    // Clear the BSS.
+    lla t0, start_of_bss
+    lla t1, end_of_bss
+    bgeu t0, t1, .Lclear_bss_done
+.Lclear_bss_loop:
+    sd zero, (t0)
+    addi t0, t0, 8
+    bltu t0, t1, .Lclear_bss_loop
+.Lclear_bss_done:
 
-  // Set the stack pointer register to the location defined in the linker script.
-  lla sp, end_of_initial_stack
+    // Set the stack pointer register to the location defined in the linker script.
+    lla sp, end_of_initial_stack
 
-  // Zero all registers except sp, a0 and a1.
-  li ra, 0
-  // sp
-  li gp, 0
-  li tp, 0
-  li t0, 0
-  li t1, 0
-  li t2, 0
-  li fp, 0
-  li s1, 0
-  // a0
-  // a1
-  li a2, 0
-  li a3, 0
-  li a4, 0
-  li a5, 0
-  li a6, 0
-  li a7, 0
-  li s2, 0
-  li s3, 0
-  li s4, 0
-  li s5, 0
-  li s6, 0
-  li s7, 0
-  li s8, 0
-  li s9, 0
-  li s10, 0
-  li s11, 0
-  li t3, 0
-  li t4, 0
-  li t5, 0
-  li t6, 0
+    // Zero all registers except sp, a0 and a1.
+    li ra, 0
+    // sp
+    li gp, 0
+    li tp, 0
+    li t0, 0
+    li t1, 0
+    li t2, 0
+    li fp, 0
+    li s1, 0
+    // a0
+    // a1
+    li a2, 0
+    li a3, 0
+    li a4, 0
+    li a5, 0
+    li a6, 0
+    li a7, 0
+    li s2, 0
+    li s3, 0
+    li s4, 0
+    li s5, 0
+    li s6, 0
+    li s7, 0
+    li s8, 0
+    li s9, 0
+    li s10, 0
+    li s11, 0
+    li t3, 0
+    li t4, 0
+    li t5, 0
+    li t6, 0
 
-  // The trap handler expects sscratch to be zero if we are in supervisor mode.
-  // sscratch contains the kernel stack pointer if we are in user mode.
-  csrw sscratch, zero
+    // The trap handler expects sscratch to be zero if we are in supervisor mode.
+    // sscratch contains the kernel stack pointer if we are in user mode.
+    csrw sscratch, zero
 
-  tail pre_init
+    tail pre_init
diff --git a/Kernel/Prekernel/boot.S b/Kernel/Prekernel/boot.S
@@ -136,7 +136,7 @@ print_no_halt:
 
 
 
-/* 
+/*
     this function assumes that paging is disabled (or everything is mapped 1:1)
     param 1: pointer to string ended with null terminator (C string)
 */
@@ -222,15 +222,15 @@ print_and_halt:
 gdt_table_real_mode:
     .quad 0             /* Empty entry */
 
-	.short 0xffff
-	.short 0
+    .short 0xffff
+    .short 0
     .byte 0
     .byte 0b10011010
     .byte 0b00001111
     .byte 0x0
 
     .short 0xffff
-	.short 0
+    .short 0
     .byte 0
     .byte 0b10010010
     .byte 0b00001111
@@ -328,7 +328,7 @@ real_start:
     mov $end_of_prekernel_image, %esi
     cmp $MAX_KERNEL_SIZE, %esi
     jbe kernel_not_too_large
-    
+
     movl $kernel_image_too_big_string, %esi
     pushl %esi
     call print_and_halt

diff --git a/Userland/Libraries/LibC/arch/x86_64/setjmp.S b/Userland/Libraries/LibC/arch/x86_64/setjmp.S
@@ -42,7 +42,7 @@ sigsetjmp:
     mov %rbp, (5 * 8)(%rdi)
     mov %rsp, (6 * 8)(%rdi)
     mov (%rsp), %rax        // Grab return address
-    mov %rax, (7 * 8)(%rdi)    
+    mov %rax, (7 * 8)(%rdi)
     xor %eax, %eax
     ret