fix indent

SpinalHDL · Nov 13, 2024 · bd39421 · bd39421
1 parent 110b2a1
commit bd39421
Showing 1 changed file with 4 additions and 4 deletions.
diff --git a/src/main/scala/vexriscv/demo/Murax.scala b/src/main/scala/vexriscv/demo/Murax.scala
@@ -175,10 +175,10 @@ case class Murax(config : MuraxConfig) extends Component{
     val xip = ifGen(genXip)(master(SpiXdrMaster(xipConfig.ctrl.spi)))
   }
 
-    val jtagNative = withNativeJtag generate new ClockingArea(debugClockDomain){
-          val jtagCtrl = JtagTapInstructionCtrl()
-          val tap = jtagCtrl.fromXilinxBscane2(userId = 2)
-    }
+  val jtagNative = withNativeJtag generate new ClockingArea(debugClockDomain){
+    val jtagCtrl = JtagTapInstructionCtrl()
+    val tap = jtagCtrl.fromXilinxBscane2(userId = 2)
+  }
 
   val resetCtrlClockDomain = ClockDomain(
     clock = io.mainClk,