renamed utime to time & doc

README.md

@@ -49,6 +49,7 @@
     - [YamlPlugin](#yamlplugin)
     - [FpuPlugin](#fpuplugin)
     - [AesPlugin](#aesplugin)
+    - [CounterPlugin](#counterplugin)
 
 
 
@@ -1319,3 +1320,14 @@ It was also ported on libressl via the following patch :
 <https://github.com/SpinalHDL/buildroot-spinal-saxon/blob/main/patches/libressl/0000-vexriscv-aes.patch>
 
 Speed up of 4 was observed in libressl running in linux. <https://github.com/SpinalHDL/SaxonSoc/pull/53#issuecomment-730133020>
+
+#### CounterPlugin
+
+Provides performance-counter and time CSRs.
+
+Here is how to provide a custom event condition (which can then be configured by code):
+```scala
+val ctrSrv = pipeline.service(classOf[CounterService])
+ctrSrv.getCondition(eventId) := boolCond
+```
+eventId is BigInt, but only events between 0 and 2 ** XLEN (excluding boundaries) can be selected by cpu.

src/main/scala/vexriscv/plugin/CounterPlugin.scala

@@ -106,7 +106,7 @@ class CounterPlugin(config : CounterPluginConfig) extends Plugin[VexRiscv] with
     import pipeline._
     import pipeline.config._
 
-    if (utimeAccess != CsrAccess.NONE) time = in UInt(64 bits) setName("utime")
+    if (utimeAccess != CsrAccess.NONE) time = in UInt(64 bits) setName("time")
   }
 
   override def build(pipeline : VexRiscv) : Unit = {