Fix RISC-V compilation extensions, update binaries of MNIST, COREMARK…

… and performance results
ThalesGroup · Jan 8, 2025 · 0b5eebd · 0b5eebd
1 parent 455f034
commit 0b5eebd
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Showing 7 changed files with 18,163 additions and 13,159 deletions.
diff --git a/Annonce RISC-V contest 2024-2025.pdf b/Annonce RISC-V contest 2024-2025.pdf
diff --git a/Reporting_results_2024-2025.pdf b/Reporting_results_2024-2025.pdf
diff --git a/sw/app/Makefile b/sw/app/Makefile
@@ -88,7 +88,7 @@ INCS += -I$(src_dir)/../bsp/config \
 FLAGS_STR:="$(RISCV_CFLAGS)  $(RISCV_LDFLAGS) "
 
 
-CFLAGS  ?=	-march=rv32imac_zba_zbb_zbs_zbc_zicsr_zifencei \
+CFLAGS  ?=	-march=rv32im_zicsr \
 		-mabi=ilp32 \
 		-DPREALLOCATE=1 \
 		-fvisibility=hidden \
@@ -106,7 +106,7 @@ CFLAGS  ?=	-march=rv32imac_zba_zbb_zbs_zbc_zicsr_zifencei \
 RISCV_CFLAGS :=-DPERFORMANCE_RUN=1 \
 		-DITERATIONS=3 \
 		-DFLAGS_STR=\"$(FLAGS_STR)\" \
-		-march=rv32imac_zba_zbb_zbs_zbc_zicsr_zifencei \
+		-march=rv32im_zicsr \
 		-mabi=ilp32 \
 		-DPREALLOCATE=1 \
 		-fvisibility=hidden \