Updated suite/cstest/arm64_detail to work with SVCR and SME_INDEX ope…

…rand types.
UoB-HPC · Oct 24, 2022 · 6225717 · 6225717
1 parent a4d7b7f
commit 6225717
Showing 1 changed file with 16 additions and 0 deletions.
diff --git a/suite/cstest/src/arm64_detail.c b/suite/cstest/src/arm64_detail.c
@@ -74,6 +74,22 @@ char *get_detail_arm64(csh *handle, cs_mode mode, cs_insn *ins)
 			case ARM64_OP_BARRIER:
 				add_str(&result, " ; operands[%u].type: BARRIER = 0x%x", i, op->barrier);
 				break;
+			case ARM64_OP_SME_INDEX:
+				add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->sme_index.reg));
+				if(op->sme_index.base != ARM64_REG_INVALID)
+					add_str(&result, " ; operands[%u].index.base: REG = %s", i, cs_reg_name(*handle, op->sme_index.base));
+				if(op->sme_index.disp != 0)
+					add_str(&result, " ; operands[%u].index.disp: 0x%x", i, op->sme_index.disp);
+				break;
+			case ARM64_OP_SVCR:
+				add_str(&result, " ; operands[%u].type: SYS = 0x%x", i, op->sys);
+				if(op->svcr == ARM64_SVCR_SVCRSM)
+					add_str(&result, " ; operands[%u].svcr: BIT = SM", i);
+				if(op->svcr == ARM64_SVCR_SVCRZA)
+					add_str(&result, " ; operands[%u].svcr: BIT = ZA", i);
+				if(op->svcr == ARM64_SVCR_SVCRSMZA)
+					add_str(&result, " ; operands[%u].svcr: BIT = SM & ZA", i);
+				break;
 		}
 
 		access = op->access;