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nv_small FPGA Mapping Workflow - Max's Blog #3
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$ petalinux-build会报错: Summary: 1 task failed: |
@JiawenYang |
用的zcu102,BD里uart选的both,SDK环境下生成bsp,hello world工程正确输出 |
@open2mind |
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哦,那了解了,这个错误是在第一次build时就存在? |
@@VVViy是第一次Build出现的,您说这个错误和什么有关,版本都用的和你的一样的?不知道为啥? |
看错误信息,都是报的SDK 驱动文件那边错误,我以为你们是用SDK做的bsp。一个师弟也走过上面流程是没出现过这种错误的,你看看这个链接里面设置有没有帮助https://forums.xilinx.com/t5/Embedded-Linux/Petalinux-2018-2-build-crash-xparameters-h-cut-off/td-p/881843 |
谢谢,这个链接我找到过,仍然没解决?您可不可以将您的工程共享出来或者hdf共享出来,我排除一下问题。我的qq:1565519979@VVViy |
共享工程这个事情,确实是没办法,如果是我个人项目,我写blog时就share了,NVDLA本来就是开源项目。但是这活是公司项目的一块,里边还有其他东西,我要是share出去,那就违规了,所以见谅了。 |
好吧,ok,可以理解。我在查查怎么解决吧,thanks ! |
我在前一篇vivado project博客里刚更新了一幅BD的结构图,你可以参考一下。 |
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部分错误log如下: |
这个无所谓的,我也是Windows+Linux联合开发。 |
您这问题太诡异了,怎么还有python和Java,装的petalinux 2018? |
why? |
按照blog里的流程,环境安装正确性你验证通过了吗? |
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Apparently,u need to check opendla.bb recipe(intutionly,i think u write wrong SRC_URI). |
@VVViy 我的opendla.bb是这样写的 : The inherit of module.bbclass will automatically name module packages with@VVViy 仔细检查了,还是这个错误。 |
@VVViy 我的opendla.bb是这样写的 : The inherit of module.bbclass will automatically name module packages with@VVViy 仔细检查了,还是这个错误。 |
SUMMARY = "Recipe for build an external opendla Linux kernel module" |
@peterzh2018 SRC_URI = "file://Makefile |
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哦,忘了转义字符这茬了,下面是我的完整opendla.bb内容,你可以核实一下,UG1144我看时好像没加过命令类的处理脚本,可能2018版有变化吧。
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when you completed build libjpeg, the output file is libjpeg.a you should replace new file in "external" folder, remove the previous one, it can works |
Thank you, I try it. Sould I need to re-build it with aarch-linux-gnu-gcc? |
ah no need, this is independent, you just build inside umd is okay |
How to build inside umd? |
ah, you can place source "libjpeg" inside "external" folder and build inside as normal, then follow the steps I said before~~ |
The source "libjpeg" is libjpeg.a? |
ah no, you should download opensource of "libjpeg" and compile it,https://www.ijg.org/files/jpegsrc.v9d.tar.gz |
Thank you, I will try. |
I an so sorry to bother you again, can you explain the difference or operations of the re-build and complie for the libjpeg. |
well, 1st step, you should remove "libjpeg.a" inside "external" folder. 2nd step, build libjpeg from source I sent you before. 3rd take output file "libjpeg.a" place into "external" folder. |
Why I should put the source libjpeg that downloaded from website in the umd/external and build it in external? |
well, you don't need to put inside "umd/external" folder, I just recommend to you that place to keep source, you can place wherever you like~ |
OK, thank you. |
hello, I rebuilt libjpeg.a using jpegsrc.v9d, thus I can make "umd" successfully. But when I run ./nvdla_runtime, it reports something wrong about jpeg: |
I also meet this problem. |
well, send me the log error |
Usage: ./nvdla_runtime [-options] --loadable <loadable_file> |
well, try to re-compile with another version of libjpeg, the lower version could be better |
Thank you. |
Thanks, I used jpeg v6b and fixed this problem. But I got a new problem while running "pdp_L0_0_small_fbuf", here is a part of the error log: [ 222.072241] Enter: dla_program_operation it seems that "mem_type" should be 0 (defined as DLA_MEM_MC in dla_interface.h) |
May I have your e-mail? I want to communicate with you something. |
sure,[email protected] |
well, my email: [email protected] Next week, I'll take a look on your issue ^^ |
题主您好,我在ZC706板子移植nvdla,芯片是ZYNQ7000,在移植KMD后 insmod后 出现了 |
是DMA的问题的话,是你petalinux版本的问题吧2019和2018按照那个应该可以吧
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主题: Re: [VVViy/VVViy.github.io] nv_small FPGA Mapping Workflow - Max's Blog (#3)
题主您好,我在ZC706板子移植nvdla,芯片是ZYNQ7000,在移植KMD后 insmod后 出现了
vmap allocation for size 268439552 failed : use vmalloc= to increase size的错误,请问DMA预留的空间与vmalloc有必然的联系嘛。
在增加了vmalloc重新insmod后又出现了failed to register drm deviece的错误。请问应该从什么角度修改呢。
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@sunny-yellow |
感谢博主的分享,我想问您一个问题!就是如何在vivado BD中查看DDR的有效地址呢?谢谢! |
我记得在BD里双击“zynq” IP,在弹出界面中是能看到和设置DDR地址的。 |
嗯嗯,晓得了!还有个问题,您使用的ZCU102的内存是多大的呢?预留内存必须是0x40000000地址开始吗?我的是4GB内存,换成其他大点的起始地址的话在跑runtime就报SERROR的错误。请问您知道是为什么吗?谢谢! |
zcu102好像也是4G,预留地址是指DMA的那个?要查一下那个DMA内存声明函数的定义,然后根据DDR有效地址计算一下,细节时间太久不记得了。 |
https://vvviy.github.io/2018/09/17/nv_small-FPGA-Mapping-Workflow-II/
Keep self busy.
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