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12 Open 1 Closed
12 Open 1 Closed
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Issues list

Design Space Exploration Methods - Max's Blog Gitalk /2022/12/31/DSE/
#13 opened Mar 2, 2023 by VVViy
All-In-One Platform for Chip Design - Max's Blog Gitalk /2022/07/26/IC-platform/
#12 opened Jul 29, 2022 by VVViy
致歉 - Max's Blog Gitalk /2022/07/22/Apology/
#11 opened Jul 28, 2022 by VVViy
博客复更 - Max's Blog Gitalk /2020/04/06/recover/
#10 opened Apr 6, 2020 by VVViy
6
create the NVDLA IP for the nv_small with Vivado and manage the connections with the Zynq UltraScale
#9 opened Jan 15, 2019 by ghost
5
NVDLA HW Source Code Analysis - Max's Blog Gitalk /2019/01/11/NVDLA-Source-Code-Analysis/
#8 opened Jan 14, 2019 by VVViy
8
Learning Chisel and Scala - Max's Blog Gitalk /2018/12/12/Learning-Chisel-and-Scala-Part-II/
#7 opened Dec 13, 2018 by VVViy
Learning Chisel and Scala - Max's Blog Gitalk /2018/12/01/Learning-Chisel-and-Scala-Part-I/
#6 opened Dec 1, 2018 by VVViy
Git - Max's Blog Gitalk /2017/02/15/Git-CMD/
#5 opened Oct 18, 2018 by VVViy
nv_small FPGA Mapping Workflow - Max's Blog Gitalk /2018/09/12/nv_small-FPGA-Mapping-Workflow-I/
#4 opened Oct 18, 2018 by VVViy
50
nv_small FPGA Mapping Workflow - Max's Blog Gitalk /2018/09/17/nv_small-FPGA-Mapping-Workflow-II/
#3 opened Oct 18, 2018 by VVViy
162
Device Tree Survey and Summary - Max's Blog Gitalk /2018/10/02/Device-Tree-Survey-and-Summary/
#2 opened Oct 18, 2018 by VVViy
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