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Pull requests: Xilinx/llvm-aie
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[AIE2P] Legalization and instruction selection support for G_FADD/G_FSUB
#274
opened Jan 16, 2025 by
katerynamuts
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[AIE2P] Support end to end bfp16 conversion C intrinsics
#273
opened Jan 16, 2025 by
khallouh
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Model accumulators as integers + support missing broadcast intrinsics.
#270
opened Jan 15, 2025 by
SagarMaheshwari99
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[AIE2P] Support exponent register classes in RegisterBankSelect
#268
opened Jan 15, 2025 by
khallouh
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[AIE2P] Support spilling Load/Store FIFO registers and PLFR super registers
#265
opened Jan 15, 2025 by
khallouh
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[AIE2P] Fix Accumulator Register Bank assignment for G_STORE
#264
opened Jan 15, 2025 by
khallouh
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Prune all Python versions from hosted tool cache prior to building
#263
opened Jan 15, 2025 by
philippjh
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[AIE] Add missing addressing intrinsics using dims_2d_t/dims_3d_t
#256
opened Jan 10, 2025 by
khallouh
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[AIE] Solve it. Work In Progress adding a solver-based postpipeliner
#255
opened Jan 10, 2025 by
martien-de-jong
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Draft
[AIE NFC] Postpipeliner cleanups and refactorings
#253
opened Jan 8, 2025 by
martien-de-jong
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[AIEX] Schedule SWP epilogue with "free" instructions
#247
opened Dec 10, 2024 by
andcarminati
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Add support for bfloat in VInsert PreLegalizerCombiner
#243
opened Nov 21, 2024 by
abhinay-anubola
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Support for allowing direct VEXTRACT to 20-bit registers
#233
opened Nov 8, 2024 by
abhinay-anubola
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[AIEX] Ignore bank conflict if in the next cycle we cannot schedule the instruction.
#229
opened Nov 1, 2024 by
krishnamtibrewala
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Draft
[GlobalISel] Match G_SHUFFLE_VECTORs representing sub-vector extracts
#224
opened Oct 25, 2024 by
konstantinschwarz
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Draft
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