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Pepijn de Vos edited this page Nov 17, 2024 · 3 revisions

OTP

Ports

Port Size Direction
CLK 1 input
DOUT 1 output
READ 1 input
SHIFT 1 input

Parameters

Parameter Default Value
MODE 1 (0b01)

Verilog Instantiation

OTP #(
    .MODE(MODE)
) otp_inst (
    .CLK(CLK),
    .DOUT(DOUT),
    .READ(READ),
    .SHIFT(SHIFT)
);
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