OVIDEO

The OVIDEO primitive is a serializer that realizes 7:1 parallel to serial conversion, converting 7 bits of parallel input data into 1 bit of serial output data. The primary clock input (PCLK) is usually obtained by frequency division of the high-speed clock input (FCLK), with a typical ratio of 3.5 PCLK per FCLK.

This device is supported in Apicula.

Ports

Port	Size	Direction
D0	1	input
D1	1	input
D2	1	input
D3	1	input
D4	1	input
D5	1	input
D6	1	input
FCLK	1	input
PCLK	1	input
Q	1	output
RESET	1	input

Parameters

Parameter	Default Value
GSREN	false
LSREN	true

Verilog Instantiation

OVIDEO #(
    .GSREN(GSREN),
    .LSREN(LSREN)
) ovideo_inst (
    .D0(D0),
    .D1(D1),
    .D2(D2),
    .D3(D3),
    .D4(D4),
    .D5(D5),
    .D6(D6),
    .FCLK(FCLK),
    .PCLK(PCLK),
    .Q(Q),
    .RESET(RESET)
);