Remove references to ilang

examples/bitcnt/test_eq.sby

@@ -8,7 +8,7 @@ smtbmc yices
 
 [script]
 read_verilog -sv test_eq.sv
-read_ilang mutated.il
+read_rtlil mutated.il
 prep -top miter
 fmcombine miter ref uut
 flatten

examples/bitcnt/test_fm.sby

@@ -8,7 +8,7 @@ smtbmc boolector
 
 [script]
 read_verilog -sv test_fm.sv
-read_ilang mutated.il
+read_rtlil mutated.il
 prep -top testbench
 flatten
 opt -fast

examples/picorv32_primes/eq_bmc.sby

@@ -16,7 +16,7 @@ smtbmc yices
 output("verilog_defines -Dmutidx=%s" % task)
 --pycode-end--
 read_verilog -sv miter.sv
-read_ilang mutated.il
+read_rtlil mutated.il
 prep -top miter
 fmcombine miter ref uut
 flatten

examples/picorv32_primes/eq_bmc.sh

@@ -4,11 +4,11 @@ exec 2>&1
 set -ex
 
 {
-	echo "read_ilang ../../database/design.il"
+	echo "read_rtlil ../../database/design.il"
 	while read -r idx mut; do
 		echo "mutate -ctrl mutsel 8 ${idx} ${mut#* }"
 	done < input.txt
-	echo "write_ilang mutated.il"
+	echo "write_rtlil mutated.il"
 } > mutate.ys
 
 yosys -ql mutate.log mutate.ys

examples/picorv32_primes/eq_sim3.sby

@@ -16,7 +16,7 @@ abc sim3
 output("verilog_defines -Dmutidx=%s" % task)
 --pycode-end--
 read_verilog -sv miter.sv
-read_ilang mutated.il
+read_rtlil mutated.il
 prep -top miter
 fmcombine miter ref uut
 

examples/picorv32_primes/eq_sim3.sh

@@ -4,11 +4,11 @@ exec 2>&1
 set -ex
 
 {
-	echo "read_ilang ../../database/design.il"
+	echo "read_rtlil ../../database/design.il"
 	while read -r idx mut; do
 		echo "mutate -ctrl mutsel 8 ${idx} ${mut#* }"
 	done < input.txt
-	echo "write_ilang mutated.il"
+	echo "write_rtlil mutated.il"
 } > mutate.ys
 
 yosys -ql mutate.log mutate.ys

examples/picorv32_primes/sim_simple.sh

@@ -6,7 +6,7 @@ exec 2>&1
 set -ex
 
 {
-	echo "read_ilang ../../database/design.il"
+	echo "read_rtlil ../../database/design.il"
 	while read -r idx mut; do
 		echo "mutate -ctrl mutsel 8 ${idx} ${mut#* }"
 	done < input.txt

mcy.py

@@ -283,7 +283,7 @@ def reset_status(db, cfg, do_reset=False):
 
             log_step("Creating additional mutations script file.")
             with open("database/mutations2.ys", "w") as f:
-                print("read_ilang database/design.il", file=f)
+                print("read_rtlil database/design.il", file=f)
                 print(f"mutate -list {cfg.opt_size} -seed {cfg.opt_seed} -none{''.join(' -cfg %s %d' % (k, v) for k, v, in sorted(cfg.mutopts.items()))}{' -mode ' + cfg.opt_mode if cfg.opt_mode else ''} -o database/mutations2.txt -s database/sources.txt{' ' + ' '.join(cfg.select) if len(cfg.select) else ''}", file=f)
 
             log_step("Creating additional mutations.")
@@ -473,15 +473,15 @@ def init_command(force, nosetup, trace):
     with open("database/design.ys", "w") as f:
         for line in cfg.script:
             print(line, file=f)
-        print("write_ilang database/design.il", file=f)
+        print("write_rtlil database/design.il", file=f)
 
     log_step("Creating design RTL.")
     task = Task("yosys -ql database/design.log database/design.ys")
     task.wait()
 
     log_step("Creating mutations script file.")
     with open("database/mutations.ys", "w") as f:
-        print("read_ilang database/design.il", file=f)
+        print("read_rtlil database/design.il", file=f)
         print(f"mutate -list {cfg.opt_size} -seed {cfg.opt_seed} -none{''.join(' -cfg %s %d' % (k, v) for k, v, in sorted(cfg.mutopts.items()))}{' -mode ' + cfg.opt_mode if cfg.opt_mode else ''} -o database/mutations.txt -s database/sources.txt{' ' + ' '.join(cfg.select) if len(cfg.select) else ''}", file=f)
 
     log_step("Creating mutations.")

scripts/create_mutated.sh

@@ -68,15 +68,15 @@ if [[ ( "$output_file" == *.v ) ]]; then
 elif [[ ( "$output_file" == *.sv ) ]]; then
 	write_cmd="write_verilog -norename -sv $output_file"
 elif [[ ( "$output_file" == *.il ) ]]; then
-	write_cmd="write_ilang $output_file"
+	write_cmd="write_rtlil $output_file"
 else
 	echo "Unrecognized file extension: '$output_file' (this script can write .v, .sv and .il files)" 1>&2
 	# usage 1>&2
 	exit 1
 fi
 
 {
-	echo "read_ilang $design_file"
+	echo "read_rtlil $design_file"
 	while read -r idx mut; do
 		if [[ "$use_ctrl" -eq 1 ]]; then
 			echo "mutate -ctrl mutsel ${ctrl_width} ${idx} ${mut#* }"