vexriscv: correct isa to rv32ic #31
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The VexRiscv config included in this repo has support for compressed instructions (see the config), but was configured as
rv32i. This caused the instruction failures in #10, asrv32irequires branches to 2-byte aligned addresses to trap butrv32icdoes not (as compressed instructions are 2-byte aligned).I have only tested the instruction checks to a bound of 15 as I am just running on a laptop, but it would be good for someone to test them to 20 (maybe @jix if you feel like running them for a bit at somepoint). None of the instruction checks (including the new c extension instructions) fail within this bound, although the liveness case mentioned in #10 does still fail.