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Add waveform with iverilog simulator #35

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Add waveform with iverilog simulator #35

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4 changes: 3 additions & 1 deletion .gitignore
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Original file line number Diff line number Diff line change
Expand Up @@ -5,4 +5,6 @@ test/logs/*
gds/**/*.gltf

.DS_Store
results.xml
results.xml

sim_build/**
9 changes: 7 additions & 2 deletions Makefile
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Expand Up @@ -5,7 +5,7 @@ export LIBPYTHON_LOC=$(shell cocotb-config --libpython)
test_%:
make compile
iverilog -o build/sim.vvp -s gpu -g2012 build/gpu.v
MODULE=test.test_$* vvp -M $$(cocotb-config --prefix)/cocotb/libs -m libcocotbvpi_icarus build/sim.vvp
MODULE=test.test_$* vvp -M $$(cocotb-config --prefix)/cocotb/libs -m libcocotbvpi_icarus build/sim.vvp -fst

compile:
make compile_alu
Expand All @@ -19,7 +19,12 @@ compile:
compile_%:
sv2v -w build/$*.v src/$*.sv

# TODO: Get gtkwave visualizaiton
# The gtkwave FST file -> sim_build/gpu.fst
test.test_%: compile
make -f Makefile.cocotb.mk MODULE=$@

show_%: %.vcd %.gtkw
gtkwave $^

clean:
rm -rf build/* sim_build
19 changes: 19 additions & 0 deletions Makefile.cocotb.mk
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@@ -0,0 +1,19 @@
# Makefile

# defaults
SIM ?= icarus
TOPLEVEL_LANG ?= verilog

# Enable wakeform
WAVES=1

VERILOG_SOURCES += build/gpu.v

# TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
TOPLEVEL = gpu

# MODULE is the basename of the Python test file
MODULE := test.test_matadd

# include cocotb's make rules to take care of the simulator setup
include $(shell cocotb-config --makefiles)/Makefile.sim